diff --git a/.gitignore b/.gitignore index 5bb02714..34fa012d 100644 --- a/.gitignore +++ b/.gitignore @@ -15,4 +15,6 @@ mux* rfs_server* doc/dist doc/cache - +*~ +*.*~ +luac.cross* diff --git a/CHANGELOG b/CHANGELOG index a8a25517..6ce25e1f 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,3 +1,10 @@ +xx.yy.zzzz Bogdan Marinescu + Dado Sutter + James Snyder + + * Official release 0.9 + * New feature: system timer ([TODO] add link) + 02.02.2011 Bogdan Marinescu Dado Sutter James Snyder diff --git a/SConstruct b/SConstruct index 50bf5daa..7ec681eb 100644 --- a/SConstruct +++ b/SConstruct @@ -1,5 +1,6 @@ import os, sys, shutil, string -import platform as syspl +import platform as syspl +import glob # Helper: "normalize" a name to make it a suitable C macro name def cnorm( name ): @@ -79,14 +80,14 @@ toolchain_list['devkitarm'] = toolchain_list['arm-eabi-gcc'] # (the one that will be used if none is specified) platform_list = { 'at91sam7x' : { 'cpus' : [ 'AT91SAM7X256', 'AT91SAM7X512' ], 'toolchains' : [ 'arm-gcc', 'codesourcery', 'devkitarm', 'arm-eabi-gcc' ] }, - 'lm3s' : { 'cpus' : [ 'LM3S1968', 'LM3S8962', 'LM3S6965', 'LM3S6918', 'LM3S9B92' ], 'toolchains' : [ 'arm-gcc', 'codesourcery', 'devkitarm', 'arm-eabi-gcc' ] }, + 'lm3s' : { 'cpus' : [ 'LM3S1968', 'LM3S8962', 'LM3S6965', 'LM3S6918', 'LM3S9B92', 'LM3S9D92' ], 'toolchains' : [ 'arm-gcc', 'codesourcery', 'devkitarm', 'arm-eabi-gcc' ] }, 'str9' : { 'cpus' : [ 'STR912FAW44' ], 'toolchains' : [ 'arm-gcc', 'codesourcery', 'devkitarm', 'arm-eabi-gcc' ] }, 'i386' : { 'cpus' : [ 'I386' ], 'toolchains' : [ 'i686-gcc' ] }, 'sim' : { 'cpus' : [ 'LINUX' ], 'toolchains' : [ 'i686-gcc' ] }, 'lpc288x' : { 'cpus' : [ 'LPC2888' ], 'toolchains' : [ 'arm-gcc', 'codesourcery', 'devkitarm', 'arm-eabi-gcc' ] }, 'str7' : { 'cpus' : [ 'STR711FR2' ], 'toolchains' : [ 'arm-gcc', 'codesourcery', 'devkitarm', 'arm-eabi-gcc' ] }, 'stm32' : { 'cpus' : [ 'STM32F103ZE', 'STM32F103RE' ], 'toolchains' : [ 'arm-gcc', 'codesourcery', 'devkitarm', 'arm-eabi-gcc' ] }, - 'avr32' : { 'cpus' : [ 'AT32UC3A0512', 'AT32UC3A0128', 'AT32UC3B0256' ], 'toolchains' : [ 'avr32-gcc', 'avr32-unknown-none-gcc' ] }, + 'avr32' : { 'cpus' : [ 'AT32UC3A0512', 'AT32UC3A0256', 'AT32UC3A0128', 'AT32UC3B0256' ], 'toolchains' : [ 'avr32-gcc', 'avr32-unknown-none-gcc' ] }, 'lpc24xx' : { 'cpus' : [ 'LPC2468' ], 'toolchains' : [ 'arm-gcc', 'codesourcery', 'devkitarm', 'arm-eabi-gcc' ] }, 'lpc17xx' : { 'cpus' : [ 'LPC1768' ], 'toolchains' : [ 'arm-gcc', 'codesourcery', 'devkitarm', 'arm-eabi-gcc' ] } } @@ -97,6 +98,7 @@ board_list = { 'SAM7-EX256' : [ 'AT91SAM7X256', 'AT91SAM7X512' ], 'EK-LM3S8962' : [ 'LM3S8962' ], 'EK-LM3S6965' : [ 'LM3S6965' ], 'EK-LM3S9B92' : [ 'LM3S9B92' ], + 'SOLDERCORE' : [ 'LM3S9D92' ], 'STR9-COMSTICK' : [ 'STR912FAW44' ], 'STR-E912' : [ 'STR912FAW44' ], 'PC' : [ 'I386' ], @@ -110,95 +112,12 @@ board_list = { 'SAM7-EX256' : [ 'AT91SAM7X256', 'AT91SAM7X512' ], 'EAGLE-100' : [ 'LM3S6918' ], 'ELUA-PUC' : ['LPC2468' ], 'MBED' : ['LPC1768'], - 'MIZAR32' : [ 'AT32UC3A0128' ], + 'MIZAR32' : [ 'AT32UC3A0128', 'AT32UC3A0256', 'AT32UC3A0512', ], 'NETDUINO' : [ 'AT91SAM7X512' ], } cpu_list = sum([board_list[i] for i in board_list],[]) - -# ROMFS file list "groups" -# To include a file in a ROMFS build, include it in a group here (or create one -# if you need) and make sure the group is included on your platform's file_list -# definition (right after this). - -# The following table will be left here just as an example -# eLua examples were removed from the distro since v0.8 -#romfs = { 'bisect' : [ 'bisect.lua' ], -# 'hangman' : [ 'hangman.lua' ], -# 'lhttpd' : [ 'index.pht', 'lhttpd.lua', 'test.lua' ], -# 'led' : [ 'led.lua' ], -# 'piano' : [ 'piano.lua' ], -# 'pwmled' : [ 'pwmled.lua' ], -# 'tvbgone' : [ 'tvbgone.lua', 'codes.bin' ], -# 'hello' : [ 'hello.lua' ], -# 'info' : [ 'info.lua' ], -# 'morse' : [ 'morse.lua' ], -# 'dualpwm' : [ 'dualpwm.lua' ], -# 'adcscope' : [ 'adcscope.lua' ], -# 'adcpoll' : [ 'adcpoll.lua' ], -# 'life' : [ 'life.lua' ], -# 'logo' : ['logo.lua', 'logo.bin' ], -# 'pong' : [ 'pong.lua' ], -# 'spaceship' : [ 'spaceship.lua' ], -# 'tetrives' : [ 'tetrives.lua' ], -# 'snake' : [ 'snake.lua' ], -# 'dataflash' : [ 'dataflash.lua' ], -# 'pachube' : [ 'pachube_demo.lua' ], -# 'inttest' : [ 'inttest.lua' ] -# } - -romfs = { - } - -# List of board/romfs data combinations -# The following table will be left here just as an example -# eLua examples were removed from the distro since v0.8 -#file_list = { 'SAM7-EX256' : [ 'bisect', 'hangman' , 'led', 'piano', 'hello', 'info', 'morse' ], -# 'EK-LM3S1968' : [ 'bisect', 'hangman', 'pong', 'led', 'piano', 'pwmled', 'hello', 'info', 'morse', 'adcscope', 'adcpoll', 'logo', 'spaceship', 'tetrives', 'snake' ], -# 'EK-LM3S8962' : [ 'lhttpd','bisect', 'led', 'pachube' ], -# 'EK-LM3S6965' : [ 'bisect', 'hangman', 'pong', 'led', 'piano', 'pwmled', 'hello', 'info', 'morse', 'adcscope', 'adcpoll', 'logo', 'tetrives' ], -# 'EK-LM3S9B92' : [ 'bisect', 'hangman', 'led', 'pwmled', 'hello', 'info', 'adcscope','adcpoll', 'life' ], -# 'STR9-COMSTICK' : [ 'bisect', 'hangman', 'led', 'hello', 'info' ], -# 'STR-E912' : [ 'bisect', 'hangman', 'led', 'hello', 'info', 'piano', 'adcscope' ], -# 'PC' : [ 'bisect', 'hello', 'info', 'life', 'hangman' ], -# 'SIM' : [ 'bisect', 'hello', 'info', 'life', 'hangman' ], -# 'LPC-H2888' : [ 'bisect', 'hangman', 'led', 'hello', 'info' ], -# 'MOD711' : [ 'bisect', 'hangman', 'led', 'hello', 'info', 'dualpwm' ], -# 'STM3210E-EVAL' : [ 'bisect', 'hello', 'info' ], -# 'ATEVK1100' : [ 'bisect', 'hangman', 'led', 'hello', 'info', 'dataflash' ], -# 'ATEVK1101' : [ 'bisect', 'led', 'hello', 'info', 'dataflash' ], -# 'ET-STM32' : [ 't' ], -# 'EAGLE-100' : [ 'bisect', 'hangman', 'lhttpd', 'led', 'hello', 'info' ], -# 'ELUA-PUC' : [ 'bisect', 'hangman', 'led', 'hello', 'info', 'pwmled', 'adcscope', 'adcpoll', 'inttest' ], -# 'MBED' : [ 'bisect', 'hangman', 'hello', 'info', 'led', 'pwmled', 'dualpwm', 'life', 'adcscope', 'adcpoll' ], -# 'MIZAR32' : [ ], -# 'NETDUINO': [ ], -#} - -file_list = { 'SAM7-EX256' : [ ], - 'EK-LM3S1968' : [ ], - 'EK-LM3S8962' : [ ], - 'EK-LM3S6965' : [ ], - 'EK-LM3S9B92' : [ ], - 'STR9-COMSTICK' : [ ], - 'STR-E912' : [ ], - 'PC' : [ ], - 'SIM' : [ ], - 'LPC-H2888' : [ ], - 'MOD711' : [ ], - 'STM3210E-EVAL' : [ ], - 'ATEVK1100' : [ ], - 'ATEVK1101' : [ ], - 'ET-STM32' : [ ], - 'EAGLE-100' : [ ], - 'ELUA-PUC' : [ ], - 'MBED' : [ ], - 'MIZAR32' : [ ], - 'NETDUINO': [ ], -} - - comp = Environment( tools = [], OBJSUFFIX = ".o", PROGSUFFIX = ".elf", @@ -243,9 +162,9 @@ vars.AddVariables( 'none', allowed_values = [ 'none', 'emblod' ] ), MatchEnumVariable('target', - 'build "regular" float lua or integer-only "lualong"', + 'build "regular" float lua, 32 bit integer-only "lualong" or 64-bit integer-only "lualonglong"', 'lua', - allowed_values = [ 'lua', 'lualong' ] ), + allowed_values = [ 'lua', 'lualong', 'lualonglong' ] ), MatchEnumVariable('cpu', 'build for the specified CPU (board will be inferred, if possible)', 'auto', @@ -358,6 +277,9 @@ if not GetOption( 'help' ): # Build the compilation command now compcmd = '' if comp['romfs'] == 'compile': + if comp['target'] == 'lualonglong': + print "Cross-compilation is not yet supported in 64-bit mode" + Exit( -1 ) if syspl.system() == 'Windows': suffix = '.exe' else: @@ -417,8 +339,10 @@ if not GetOption( 'help' ): lua_full_files = " " + " ".join( [ "src/lua/%s" % name for name in lua_files.split() ] ) comp.Append(CPPPATH = ['inc', 'inc/newlib', 'inc/remotefs', 'src/platform', 'src/lua']) - if comp['target'] == 'lualong': + if comp['target'] == 'lualong' or comp['target'] == 'lualonglong': conf.env.Append(CPPDEFINES = ['LUA_NUMBER_INTEGRAL']) + if comp['target'] == 'lualonglong': + conf.env.Append(CPPDEFINES = ['LUA_INTEGRAL_LONGLONG']) conf.env.Append(CPPPATH = ['src/modules', 'src/platform/%s' % platform]) conf.env.Append(CPPDEFINES = {"LUA_OPTIMIZE_MEMORY" : ( comp['optram'] != 0 and 2 or 0 ) } ) @@ -466,15 +390,19 @@ if not GetOption( 'help' ): comp = conf.Finish() + romfs_exclude = [ '.DS_Store' ] + # Make ROM File System first if not GetOption( 'clean' ): print "Building ROM File System..." - romdir = "romfs" flist = [] - for sample in file_list[ comp['board'] ]: - flist += romfs[ sample ] + os.chdir( "romfs" ); + for sample in glob.glob("*"): + if sample not in romfs_exclude: + flist += [ sample ] + os.chdir( ".." ) import mkfs - mkfs.mkfs( romdir, "romfiles", flist, comp['romfs'], compcmd ) + mkfs.mkfs( "romfs", "romfiles", flist, comp['romfs'], compcmd ) print if os.path.exists( "inc/romfiles.h" ): os.remove( "inc/romfiles.h" ) diff --git a/build_elua.lua b/build_elua.lua index 2caa3584..4f48e821 100755 --- a/build_elua.lua +++ b/build_elua.lua @@ -157,14 +157,14 @@ toolchain_list[ 'devkitarm' ] = toolchain_list[ 'arm-eabi-gcc' ] local platform_list = { at91sam7x = { cpus = { 'AT91SAM7X256', 'AT91SAM7X512' }, toolchains = { 'arm-gcc', 'codesourcery', 'devkitarm', 'arm-eabi-gcc' } }, - lm3s = { cpus = { 'LM3S1968', 'LM3S8962', 'LM3S6965', 'LM3S6918', 'LM3S9B92' }, toolchains = { 'arm-gcc', 'codesourcery', 'devkitarm', 'arm-eabi-gcc' } }, + lm3s = { cpus = { 'LM3S1968', 'LM3S8962', 'LM3S6965', 'LM3S6918', 'LM3S9B92', 'LM3S9D92' }, toolchains = { 'arm-gcc', 'codesourcery', 'devkitarm', 'arm-eabi-gcc' } }, str9 = { cpus = { 'STR912FAW44' }, toolchains = { 'arm-gcc', 'codesourcery', 'devkitarm', 'arm-eabi-gcc' } }, i386 = { cpus = { 'I386' }, toolchains = { 'i686-gcc' } }, sim = { cpus = { 'LINUX' }, toolchains = { 'i686-gcc' } }, lpc288x = { cpus = { 'LPC2888' }, toolchains = { 'arm-gcc', 'codesourcery', 'devkitarm', 'arm-eabi-gcc' } }, str7 = { cpus = { 'STR711FR2' }, toolchains = { 'arm-gcc', 'codesourcery', 'devkitarm', 'arm-eabi-gcc' } }, stm32 = { cpus = { 'STM32F103ZE', 'STM32F103RE' }, toolchains = { 'arm-gcc', 'codesourcery', 'devkitarm', 'arm-eabi-gcc' } }, - avr32 = { cpus = { 'AT32UC3A0512', 'AT32UC3A0128', 'AT32UC3B0256' }, toolchains = { 'avr32-gcc', 'avr32-unknown-none-gcc' } }, + avr32 = { cpus = { 'AT32UC3A0128', 'AT32UC3A0256', 'AT32UC3A0512', 'AT32UC3B0256' }, toolchains = { 'avr32-gcc', 'avr32-unknown-none-gcc' } }, lpc24xx = { cpus = { 'LPC2468' }, toolchains = { 'arm-gcc', 'codesourcery', 'devkitarm', 'arm-eabi-gcc' } }, lpc17xx = { cpus = { 'LPC1768' }, toolchains = { 'arm-gcc', 'codesourcery', 'devkitarm', 'arm-eabi-gcc' } } } @@ -177,6 +177,7 @@ local board_list = [ 'EK-LM3S8962' ] = { 'LM3S8962' }, [ 'EK-LM3S6965' ] = { 'LM3S6965' }, [ 'EK-LM3S9B92' ] = { 'LM3S9B92' }, + [ 'SOLDERCORE' ] = { 'LM3S9D92' }, [ 'STR9-COMSTICK' ] = { 'STR912FAW44' }, [ 'STR-E912' ] = { 'STR912FAW44' }, [ 'PC' ] = { 'I386' }, @@ -190,7 +191,7 @@ local board_list = [ 'EAGLE-100' ] = { 'LM3S6918' }, [ 'ELUA-PUC' ] = { 'LPC2468' }, [ 'MBED' ] = { 'LPC1768' }, - [ 'MIZAR32' ] = { 'AT32UC3A0128' }, + [ 'MIZAR32' ] = { 'AT32UC3A0128', 'AT32UC3A0256', 'AT32UC3A0512' }, [ 'NETDUINO' ] = { 'AT91SAM7X512' }, } @@ -205,97 +206,7 @@ for k, v in pairs( board_list ) do end end --- ROMFS file list "groups" --- To include a file in a ROMFS build, include it in a group here (or create one --- if you need) and make sure the group is included on your platform's file_list --- definition (right after this). - --- The following table will be left here just as an example --- eLua examples were removed from the distro since v0.8 ---[[ -local romfs = -{ - bisect = { 'bisect.lua' }, - hangman = { 'hangman.lua' }, - lhttpd = { 'index.pht', 'lhttpd.lua', 'test.lua' }, - led = { 'led.lua' }, - piano = { 'piano.lua' }, - pwmled = { 'pwmled.lua' }, - tvbgone = { 'tvbgone.lua', 'codes.bin' }, - hello = { 'hello.lua' }, - info = { 'info.lua' }, - morse = { 'morse.lua' }, - dualpwm = { 'dualpwm.lua' }, - adcscope = { 'adcscope.lua' }, - adcpoll = { 'adcpoll.lua' }, - life = { 'life.lua' }, - logo = {'logo.lua', 'logo.bin' }, - pong = { 'pong.lua' }, - spaceship = { 'spaceship.lua' }, - tetrives = { 'tetrives.lua' }, - snake = { 'snake.lua' }, - dataflash = { 'dataflash.lua' }, - pachube = { 'pachube_demo.lua' }, - inttest = { 'inttest.lua' } -} ---]] - -local romfs = {} - --- List of board/romfs data combinations --- The following table will be left here just as an example --- eLua examples were removed from the distro since v0.8 ---[[ -local file_list = -{ - [ 'SAM7-EX256' ] = { 'bisect', 'hangman' , 'led', 'piano', 'hello', 'info', 'morse' }, - [ 'EK-LM3S1968' ] = { 'bisect', 'hangman', 'pong', 'led', 'piano', 'pwmled', 'hello', 'info', 'morse', 'adcscope', 'adcpoll', 'logo', 'spaceship', 'tetrives', 'snake' }, - [ 'EK-LM3S8962' ] = { 'lhttpd','bisect', 'led', 'pachube' }, - [ 'EK-LM3S6965' ] = { 'bisect', 'hangman', 'pong', 'led', 'piano', 'pwmled', 'hello', 'info', 'morse', 'adcscope', 'adcpoll', 'logo', 'tetrives' }, - [ 'EK-LM3S9B92' ] = { 'bisect', 'hangman', 'led', 'pwmled', 'hello', 'info', 'adcscope','adcpoll', 'life' }, - [ 'STR9-COMSTICK' ] = { 'bisect', 'hangman', 'led', 'hello', 'info' }, - [ 'STR-E912' ] = { 'bisect', 'hangman', 'led', 'hello', 'info', 'piano', 'adcscope' }, - [ 'PC' ] = { 'bisect', 'hello', 'info', 'life', 'hangman' }, - [ 'SIM' ] = { 'bisect', 'hello', 'info', 'life', 'hangman' }, - [ 'LPC-H2888' ] = { 'bisect', 'hangman', 'led', 'hello', 'info' }, - [ 'MOD711' ] = { 'bisect', 'hangman', 'led', 'hello', 'info', 'dualpwm' }, - [ 'STM3210E-EVAL' ] = { 'bisect', 'hello', 'info' }, - [ 'ATEVK1100' ] = { 'bisect', 'hangman', 'led', 'hello', 'info', 'dataflash' }, - [ 'ATEVK1101' ] = { 'bisect', 'led', 'hello', 'info', 'dataflash' }, - [ 'ET-STM32' ] = { 't' }, - [ 'EAGLE-100' ] = { 'bisect', 'hangman', 'lhttpd', 'led', 'hello', 'info' }, - [ 'ELUA-PUC' ] = { 'bisect', 'hangman', 'led', 'hello', 'info', 'pwmled', 'adcscope', 'adcpoll', 'inttest' }, - [ 'MBED' ] = { 'bisect', 'hangman', 'hello', 'info', 'led', 'pwmled', 'dualpwm', 'life', 'adcscope', 'adcpoll' }, - [ 'MIZAR32' ] = { }, - [ 'NETDUINO' ] = { }, -} ---]] - -local file_list = -{ - [ 'SAM7-EX256' ] = {}, - [ 'EK-LM3S1968' ] = {}, - [ 'EK-LM3S8962' ] = {}, - [ 'EK-LM3S6965' ] = {}, - [ 'EK-LM3S9B92' ] = {}, - [ 'STR9-COMSTICK' ] = {}, - [ 'STR-E912' ] = {}, - [ 'PC' ] = {}, - [ 'SIM' ] = {}, - [ 'LPC-H2888' ] = {}, - [ 'MOD711' ] = {}, - [ 'STM3210E-EVAL' ] = {}, - [ 'ATEVK1100' ] = {}, - [ 'ATEVK1101' ] = {}, - [ 'ET-STM32' ] = {}, - [ 'EAGLE-100' ] = {}, - [ 'ELUA-PUC' ] = {}, - [ 'MBED' ] = {}, - [ 'MIZAR32' ] = {}, - [ 'NETDUINO'] = {}, -} - -builder:add_option( 'target', 'build "regular" float lua or integer-only "lualong"', 'lua', { 'lua', 'lualong' } ) +builder:add_option( 'target', 'build "regular" float lua, 32 bit integer-only "lualong" or 64-bit integer only lua "lualonglong"', 'lua', { 'lua', 'lualong', 'lualonglong' } ) builder:add_option( 'cpu', 'build for the specified CPU (board will be inferred, if possible)', 'auto', { cpu_list, 'auto' } ) builder:add_option( 'allocator', 'select memory allocator', 'auto', { 'newlib', 'multiple', 'simple', 'auto' } ) builder:add_option( 'board', 'selects board for target (cpu will be inferred)', 'auto', { utils.table_keys( board_list ), 'auto' } ) @@ -399,6 +310,10 @@ end -- Build the compilation command now local fscompcmd = '' if comp.romfs == 'compile' then + if comp.target == 'lualonglong' then + print "Cross-compilation is not yet supported for 64-bit integer only Lua (lualonglong)." + os.exit( -1 ) + end local suffix = '' if utils.is_windows() then suffix = '.exe' @@ -451,13 +366,14 @@ elseif comp.allocator == 'simple' then addm( "USE_SIMPLE_ALLOCATOR" ) end if comp.boot == 'luarpc' then addm( "ELUA_BOOT_RPC" ) end -if comp.target == 'lualong' then addm( "LUA_NUMBER_INTEGRAL" ) end +if comp.target == 'lualong' or comp.target == 'lualonglong' then addm( "LUA_NUMBER_INTEGRAL" ) end +if comp.target == 'lualonglong' then addm( "LUA_INTEGRAL_LONGLONG" ) end -- Special macro definitions for the SYM target if platform == 'sim' then addm( { "ELUA_SIMULATOR", "ELUA_SIM_" .. cnorm( comp.cpu ) } ) end -- Lua source files and include path -exclude_patterns = { "^src/platform", "^src/uip", "^src/serial", "^src/luarpc_desktop_serial.c", "^src/lua/print.c", "^src/lua/luac.c" } +exclude_patterns = { "^src/platform", "^src/uip", "^src/serial", "^src/luarpc_desktop_serial.c", "^src/linenoise_posix.c", "^src/lua/print.c", "^src/lua/luac.c" } local source_files = utils.get_files( "src", function( fname ) fname = fname:gsub( "\\", "/" ) local include = fname:find( ".*%.c$" ) @@ -487,15 +403,25 @@ source_files = source_files .. uip_files .. specific_files -- Create compiler/linker/assembler command lines and build -- ROM file system builder + +romfs_exclude_patterns = { '%.DS_Store', '%.gitignore' } + +function match_pattern_list( item, list ) + for k, v in pairs( list ) do + if item:find(v) then return true end + end +end + local function make_romfs() print "Building ROM file system ..." - local romdir = "romfs" local flist = {} - for _, sample in pairs( file_list[ comp.board:upper() ] ) do - table.insert( flist, romfs[ sample ] ) - end + flist = utils.string_to_table( utils.get_files( 'romfs', function( fname ) return not match_pattern_list( fname, romfs_exclude_patterns ) end ) ) flist = utils.linearize_array( flist ) - if not mkfs.mkfs( romdir, "romfiles", flist, comp.romfs, fscompcmd ) then return -1 end + for k, v in pairs( flist ) do + flist[ k ] = v:gsub( "romfs" .. utils.dir_sep, "" ) + end + + if not mkfs.mkfs( "romfs", "romfiles", flist, comp.romfs, fscompcmd ) then return -1 end if utils.is_file( "inc/romfiles.h" ) then -- Read both the old and the new file local oldfile = io.open( "inc/romfiles.h", "rb" ) @@ -546,7 +472,6 @@ builder:set_exe_extension( ".elf" ) -- Create the ROM file system make_romfs() -- Creaate executable targets -builder:make_depends( source_files ) odeps = builder:create_compile_targets( source_files ) exetarget = builder:link_target( output, odeps ) -- This is also the default target diff --git a/doc/docdata.lua b/doc/docdata.lua index a8c899f6..4dc5ae54 100644 --- a/doc/docdata.lua +++ b/doc/docdata.lua @@ -72,6 +72,7 @@ local menu = { "Status", "status.html", { { { "Supported platforms", "Plataformas Suportadas" }, "status.html" }, + { "System timer support", "status.html#systmr" }, { { "Modules per platform table", "Módulos por plataforma" }, "status.html#plat_modules" }, { { "Modules overview status", "Visão geral dos módulos" }, "status.html#gen_modules" }, { { "Roadmap", "Planejamento Futuro" }, "status.html#roadmap" } @@ -225,14 +226,15 @@ local menu = -- "Platform modules" (automatically generated) { { "Platform modules", "Módulos Específicos" }, "refman_dep.html", { - { "lm3s", "modules_lm3s.html", "refman_ps_lm3s" }, - { "str9", "modules_str9.html", "refman_ps_str9" }, - { "mbed", "modules_mbed.html", "refman_ps_mbed" } + { "lm3s", "modules_lm3s.html", "refman_ps_lm3s" }, + { "str9", "modules_str9.html", "refman_ps_str9" }, + { "mbed", "modules_mbed.html", "refman_ps_mbed" }, + { "mizar32", "modules_mizar32.html", "refman_ps_mizar32" }, } } } } - + } -- Translations for different strings needed by the generator -- The order of languages is the same as the one defines in the languages array diff --git a/doc/eluadoc.lua b/doc/eluadoc.lua index 2ed9b6b2..d946cf12 100644 --- a/doc/eluadoc.lua +++ b/doc/eluadoc.lua @@ -9,7 +9,7 @@ local sf = string.format -- Data structure declarations -- List here all the sections for which we're generating the documentation -local doc_sections = { "arch_platform", "refman_gen", "refman_ps_lm3s", "refman_ps_str9", "refman_ps_mbed" } +local doc_sections = { "arch_platform", "refman_gen", "refman_ps_lm3s", "refman_ps_str9", "refman_ps_mbed", "refman_ps_mizar32" } -- List here all the components of each section local components = @@ -17,8 +17,9 @@ local components = arch_platform = { "ll", "pio", "spi", "uart", "timers", "pwm", "cpu", "eth", "adc", "i2c", "can" }, refman_gen = { "bit", "pd", "cpu", "pack", "adc", "term", "pio", "uart", "spi", "tmr", "pwm", "net", "can", "rpc", "elua", "i2c" }, refman_ps_lm3s = { "disp" }, - refman_ps_str9 = { "pio", "rtc" }, - refman_ps_mbed = { "pio" } + refman_ps_str9 = { "pio" }, + refman_ps_mbed = { "pio" }, + refman_ps_mizar32 = { "lcd" }, } ------------------------------------------------------------------------------- diff --git a/doc/eluadoc/arch_platform_adc.lua b/doc/eluadoc/arch_platform_adc.lua index 410d2f93..86a0b1cb 100644 --- a/doc/eluadoc/arch_platform_adc.lua +++ b/doc/eluadoc/arch_platform_adc.lua @@ -23,34 +23,56 @@ data_en = ret = "1 if the ADC interface exists, 0 otherwise" }, - { sig = "u32 #platform_adc_op#( unsigned id, int op, u32 data );", - desc = "Executes an operation on an ADC channel", - args = + { sig = "u32 #platform_adc_get_maxval#( unsigned id );", + desc = "Gets the maximum conversion value the channel may supply (based on channel resolution)", + args = "$id$ - ADC channel ID", + ret = "the maximum possible conversion value" + }, + + { sig = "u32 #platform_adc_set_smoothing#( unsigned id, u32 length );", + desc = "Sets the length of the moving average smoothing filter", + args = { "$id$ - ADC channel ID", - [[$op$ - the operation that must be executed. It can take any value from @#adc_operations@this enum@, as follows: -
    -
  • $PLATFORM_ADC_GET_MAXVAL$: get the maximum conversion value the channel may supply (based on channel resolution)
    • -
  • $PLATFORM_ADC_SET_SMOOTHING$: sets the length of the moving average smoothing filter to $data$
    • -
  • $PLATFORM_ADC_SET_BLOCKING$: sets whether or not sample requests should block, waiting for additional samples
    • -
  • $PLATFORM_ADC_IS_DONE$: checks whether sampling has completed
    • -
  • $PLATFORM_ADC_OP_SET_TIMER$: selects a timer to control sampling frequency
    • -
  • $PLATFORM_ADC_OP_SET_CLOCK$: set the frequency of sample acquisition
    • -
]], - "$data$ - when used with $op$ == $PLATFORM_ADC_SET_SMOOTHING$, specifies the length of the moving average filter (must be a power of 2). If it is 1, filter is disabled.", - "$data$ - when used with $op$ == $PLATFORM_ADC_SET_BLOCKING$, specifies whether or not sample requests block. If 1, requests will block until enough samples are available or sampling has ended. If 0, requests will return immediately with up to the number of samples requested.", - "$data$ - when used with $op$ == $PLATFORM_ADC_OP_SET_TIMER$, specifies the timer to use to control sampling frequency.", - "$data$ - when used with $op$ == $PLATFORM_ADC_OP_SET_CLOCK$, specifies the frequency of sample collection in Hz (number of samples per second). If 0, timer is not used and samples are acquired as quickly as possible." + "$length$ - the length of the moving average filter (must be a power of 2). If it is 1, the filter is disabled.", }, - ret = - { - "the maximum possible conversion value when $op$ == $PLATFORM_ADC_GET_MAXVAL$", - "whether or not sampling has completed (1: yes, 0: no) when $op$ == $PLATFORM_ADC_IS_DONE$. This will return 1 (yes), if no samples have been requested.", - "the actual frequency of acquisition that will be used when $op$ == $PLATFORM_ADC_OP_SET_CLOCK$", - "irellevant for other operations" - } + ret = "$PLATFORM_OK$ if the operation succeeded, $PLATFORM_ERR$ otherwise." }, - + + { sig = "void #platform_adc_set_blocking#( unsigned id, u32 mode );", + desc = "Sets whether or not sample requests should block, waiting for additional samples", + args = + { + "$id$ - ADC channel ID", + "$mode$ - specifies whether or not sample requests block. If 1, requests will block until enough samples are available or sampling has ended. If 0, requests will return immediately with up to the number of samples requested.", + }, + }, + + { sig = "u32 #platform_adc_is_done#( unsigned id );", + desc = "Checks whether sampling has completed", + args = "$id$ - ADC channel ID", + ret = "1 if sampling has completed, 0 if not", + }, + + { sig = "void #platform_adc_set_timer#( unsigned id, u32 timer );", + desc = "Selects a timer to control the sampling frequency", + args = + { + "$id$ - ADC channel ID", + "$timer$ - the ID of the timer to use to control the sampling frequency.", + }, + }, + + { sig = "u32 #platform_adc_set_clock#( unsigned id, u32 freq );", + desc = "Set the frequency of sample acquisition", + args = + { + "$id$ - ADC channel ID", + "$freq$ - the frequency of sample collection in Hz (number of samples per second). If 0, the timer is not used and samples are acquired as quickly as possible.", + }, + ret = "the actual sampling frequency that will be used, which might be different from the requested frequency, depending on the hardware" + }, + { sig = "int #platform_adc_check_timer_id#( unsigned id, unsigned timer_id );", desc = "Checks whether a timer may be used with a particular ADC channel", args = @@ -63,64 +85,4 @@ data_en = } } -data_pt = -{ - -- Menu name - menu_name = "ADC", - - -- Title - title = "eLua API - ADC", - - -- Overview - overview = "Interfaceamento com as funcões do ADC da MCU.", - - -- Functions - funcs = - { - { sig = "int #platform_adc_exists#( unsigned id );", - desc = [[Checa se a plataforma possui hardware para o Conversor AD especificado no argumento. Implementado em %src/common.c%, utiliza a macro $NUM_ADC$ que deve estar definida no arquivo $platform_conf.h$ da plataforma em questão. (veja @arch_overview.html#platforms@here@ para detalhes). Por exemplo:

- ~#define NUM_ADC 1 $// A Plataforma possui uma interface para ADC$~

]], - args = "$id$ - ADC ID", - ret = "1 se a interface do ADC existir, 0 em caso contrário" - }, - - { sig = "u32 #platform_adc_op#( unsigned id, int op, u32 data );", - desc = "Executes an operation on an ADC channel", - args = - { - "$id$ - ID do canal ADC", - [[$op$ - A operação que deve ser executada. Valores possíveis em @#adc_operations@this enum@, conforme: -

    -
  • $PLATFORM_ADC_GET_MAXVAL$: Pega o maior valor de conversão que o canal pode fornecer, dependendo de sua resolução.
    • -
  • $PLATFORM_ADC_SET_SMOOTHING$: Seta o tamanho do filtro atenuador de média móvel em $data$
    • -
  • $PLATFORM_ADC_SET_BLOCKING$: Seta se a amostragem deve aguardar novos valores (blocking)
    • -
  • $PLATFORM_ADC_IS_DONE$: Checa se a amostragem foi completada
    • -
  • $PLATFORM_ADC_OP_SET_TIMER$: Seleciona um Timer para o controle da amostragem
    • -
  • $PLATFORM_ADC_OP_SET_CLOCK$: Seta a frequência de amostragem
    • -
]], - "$data$ - quando usada com $op$ == $PLATFORM_ADC_SET_SMOOTHING$, especifica o tamanho do filtro de média móvel (deve ser potência de 2). O valor 1 desabilita o filtro.", - "$data$ - quando usada com $op$ == $PLATFORM_ADC_SET_BLOCKING$, especifica se a amostragem é blocking ou não. Se 1, os pedidos só retornam quando as amostras tiverem sido obtidas ou a amostragem encerrada. Se 0, os pedidos retornam imediatamente, com o número de amostras já obtidas.", - "$data$ - quando usada com $op$ == $PLATFORM_ADC_OP_SET_TIMER$, especifica o Timer a ser usado para o controle da frequência de amostragem.", - "$data$ - quando usada com $op$ == $PLATFORM_ADC_OP_SET_CLOCK$, especifica a frequência de amostragem em Hz (número de amostras por segundo). Se 0, nenhum Timer é usado e a amostragem é feita o mais rapidamente possível." - }, - ret = - { - "O maior valor possível de ser obtido do conversor, quando $op$ == $PLATFORM_ADC_GET_MAXVAL$", - "Flag informando se a conversão foi completada (1: sim, 0: não), quando $op$ == $PLATFORM_ADC_IS_DONE$. Também retorna 1 se nenhuma conversão foi solicitada.", - "A frequência real de conversão que sera usada, quando $op$ == $PLATFORM_ADC_OP_SET_CLOCK$", - "Indefinido para outras operações." - } - }, - - { sig = "int #platform_adc_check_timer_id#( unsigned id, unsigned timer_id );", - desc = "Checa see um Timer pode ser usado com um ADC específico", - args = - { - "$id$ - ADC ID", - "$timer_id$ - Timer ID", - }, - ret = "1 se o Timer pode ser usado para trigar um ADC. 0 em caso contrário", - } - } -} - +data_pt = data_en diff --git a/doc/eluadoc/arch_platform_eth.lua b/doc/eluadoc/arch_platform_eth.lua index 8cbe107c..6fb8fea0 100644 --- a/doc/eluadoc/arch_platform_eth.lua +++ b/doc/eluadoc/arch_platform_eth.lua @@ -87,103 +87,11 @@ data_en = ret = { "0 if the uIP loop was called because of Ethernet activity, not because a timer expired", - "the Ethernet timer perios in ms (which indicates timer activity)" + "the Ethernet timer period in ms (which indicates timer activity)" }, } } } -data_pt = -{ - -- Title - title = "eLua platform interface - Ethernet support", - - -- Menu name - menu_name = "Ethernet", - - -- Overview - overview = [[$NOTE$: TCP/IP support is experimental in eLua. Although functional, it's quite incomplete at the moment.

-

This part of the platform interface groups functions related to accessing the Ethernet interface (internal or external) of the CPU. Note that unlike the - other parts of the platform interface this one is dedicated for TCP/IP support and thus it does not correspond directly to an eLua module, although - the @refman_gen_net.html@net module@ is implemented with functions that rely on this part of the platform interface. Currently only - the ^http://www.sics.se/~~adam/uip/index.php/Main_Page^uIP^ TCP/IP stack is supported by eLua.

-

uIP is implemented in eLua using two hardware interrupts (that should be available on your platform): the Ethernet receive interrupt (to handle - incoming packets) and a timer interrupt (timers are used internally by uIP). However, the uIP main loop is only called from the Ethernet interrupt handler - in eLua, so in order to acknowledge the timer interrupt (as well as to provide some optimizations) a function that "forces" an Ethernet interrupt - must also be provided by the platform interface (see @#platform_eth_force_interrupt@here@ for details).

-

To put everything together, part of the Ethernet platform interface for the $lm3s$ platform is given below:

- ~u32 platform_eth_get_elapsed_time() - { - if( eth_timer_fired ) - { - eth_timer_fired = 0; - return SYSTICKMS; - } - else - return 0; - } - - void SysTickIntHandler() - { - // Handle virtual timers - cmn_virtual_timer_cb(); - - // Indicate that a SysTick interrupt has occurred. - eth_timer_fired = 1; - - // Generate a fake Ethernet interrupt. This will perform the actual work - // of incrementing the timers and taking the appropriate actions. - platform_eth_force_interrupt(); - } - - void EthernetIntHandler() - { - u32 temp; - - // Read and Clear the interrupt. - temp = EthernetIntStatus( ETH_BASE, false ); - EthernetIntClear( ETH_BASE, temp ); - - // Call the UIP main loop - elua_uip_mainloop(); - }~

]], - - -- Functions - funcs = - { - { sig = "void #platform_eth_send_packet#( const void* src, u32 size )", - desc = "Sends an Ethernet packet to the network", - args = - { - "$src$ - start address of the Ethernet packet", - "$size$ - size of the Ethernet packet" - }, - }, - - { sig = "u32 #platform_eth_get_packet_nb#( void* buf, u32 maxlen );", - desc = "Non-blocking read of an Ethernet packet from the network", - args = - { - "$buf$ - start address of the receive buffer", - "$maxlen$ - maximum length of the Ethernet packet", - }, - ret = "the size of the read packet or 0 if no packet is available" - }, - - { sig = "void #platform_eth_force_interrupt#();", - desc = "Force the Ethernet interrupt on the platform (see @#overview@overview@ above for details)", - }, - - { sig = "u32 #platform_eth_get_elapsed_time#();", - desc = [[Get the elapsed time (in ms) since the last invocation of the uIP main loop ($elua_uip_mainloop$, from which this function is called). See @#overview@overview@ for a possible - implementation of this function).]], - ret = - { - "0 if the uIP loop was called because of Ethernet activity, not because a timer expired", - "the Ethernet timer perios in ms (which indicates timer activity)" - }, - } - } -} - +data_pt = data_en diff --git a/doc/eluadoc/arch_platform_ll.lua b/doc/eluadoc/arch_platform_ll.lua index f335adff..73ae026f 100644 --- a/doc/eluadoc/arch_platform_ll.lua +++ b/doc/eluadoc/arch_platform_ll.lua @@ -32,90 +32,6 @@ enum }, }, - -- Functions - funcs = - { - { sig = "int #platform_init#();", - desc = [[This is the platform-specific initialization code. It is the first function called from %main()% ($src/main.c$) and it should handle - all the platform initialization sequence, included (but not limited to) setting up the proper clocks, initializing the interrupt subsystem, - setting up various peripherals and so on. Although platform specific, this function has a common part named %cmn_platform_init% (implemented - in $src/common.c$) that initializes terminal support over serial connections, as well as the XMODEM and TERM components - (see @building.html@here@ for details). If you need any of these, you need to call %cmn_platform_init% at the end of your - %platform_init% function, $after$ initializing all the peripherals (in particular the UART used for the serial connection).
- An implementation skeleton for this function is given below:

- ~int platform_init() - { - ............. // perform all your initializations here - cmn_platform_init(); // call the common initialiation code - return PLATFORM_OK; - }~

]], - ret = - { - "$PLATFORM_OK$ for success", - [[$PLATFORM_ERR$ if an error occured. If $PLATFORM_ERR$ is returned, %main% will block in an infinite loop right - after calling this function, so you should return $PLATFORM_ERR$ only for serious errors]], - }, - }, - - { sig = "void* #platform_get_last_free_ram#( unsigned id );", - desc = [[Returns the start address of a free RAM area in the system (this is the RAM that will be used by any part of the code that uses malloc(), - a good example being the Lua interpreter itself). There can be multiple free RAM areas in the system (for example the internal MCU RAM and external - RAM chips). Implemented in $src/common.c$, it uses the the $MEM_START_ADDRESS$ macro that must be defined in the platform's $platform_conf.h$ - file (see @arch_overview.html#platforms@here@ for details). This macro must be defined as an array that contains all the start addresses of - free RAM in the system. For internal RAM, this is generally handled by a linker exported symbol (named $end$ in many eLua ports) which - points to the first RAM address after all the constant and non-constant program data. An example is given below:

- ~#define MEM_START_ADDRESS { ( void* )end }~

]], - args = "$id$ - the identifier of the RAM area", - ret = "the start address of the given memory area", - }, - - { sig = "void* #platform_get_last_free_ram#( unsigned id );", - desc = [[Returns the last address of a free RAM area in the system (this is the RAM that will be used by any part of the code that uses malloc(), - a good example being the Lua interpreter itself). There can be multiple free RAM areas in the system (for example the internal MCU RAM and external - RAM chips). Implemented in $src/common.c$, it uses the the $MEM_END_ADDRESS$ macro that must be defined in the platform's $platform_conf.h$ - file (see @arch_overview.html#platforms@here@ for details). This macro must be defined as an array that contains all the end addresses of - free RAM in the system. For internal RAM, this is generally set as the last RAM memory address minus the size of the system stack(s). An example is - given below:

- ~#define MEM_END_ADDRESS { ( void* )( SRAM_BASE + 0x10000 - STACK_SIZE_TOTAL - 1 ) }~

]], - args = "$id$ - the identifier of the RAM area", - ret = "the end address of the given memory area", - }, - - } -} - -data_pt = -{ - -- Title - title = "eLua platform interface - low level functions", - - -- Menu title - menu_name = "Low-level", - - -- Overview - overview = [[ - This part of the platform interface deals contains a small set of "low level functions" that are used to "couple" the eLua port with the - target system. No eLua module exposes these functions, as they are strictly used for porting and do not provide any other functionality. - ]], - - -- Data structures, constants and types - structures = - { - { text = [[// Error / status codes -enum -{ - PLATFORM_ERR, - PLATFORM_OK, - PLATFORM_UNDERFLOW = -1 -};]], - name = "Status codes", - desc = [[ - This enum defines the possible return values of the @#platform_init@platform_init@ function (although only $PLATFORM_ERR$ and $PLATFORM_OK$ should be - returned from $platform_init$). - ]] - }, - }, - -- Functions funcs = { @@ -147,7 +63,7 @@ enum RAM chips). Implemented in $src/common.c$, it uses the the $MEM_START_ADDRESS$ macro that must be defined in the platform's $platform_conf.h$ file (see @arch_overview.html#platforms@here@ for details). This macro must be defined as an array that contains all the start addresses of free RAM in the system. For internal RAM, this is generally handled by a linker exported symbol (named $end$ in many eLua ports) which - points to the firs RAM address after all the constant and non-constant program data. An example is given below:

+ points to the first RAM address after all the constant and non-constant program data. An example is given below:

~#define MEM_START_ADDRESS { ( void* )end }~

]], args = "$id$ - the identifier of the RAM area", ret = "the start address of the given memory area", @@ -168,3 +84,4 @@ enum } } +data_pt = data_en diff --git a/doc/eluadoc/arch_platform_pio.lua b/doc/eluadoc/arch_platform_pio.lua index 7e30d463..2902a7f3 100644 --- a/doc/eluadoc/arch_platform_pio.lua +++ b/doc/eluadoc/arch_platform_pio.lua @@ -99,115 +99,11 @@ data_en = { "an actual value for $PLATFORM_IO_PIN_GET$ (0 or 1) and $PLATFORM_IO_PORT_GET$ (the value of the port).", [[an error flag for all the other operations: 1 if the operation succeeded, 0 otherwise. For example, a platform that doesn't have pulldowns on its ports will always return a 0 - when caled with the $PLATFORM_IO_PIN_PULLDOWN$ operation.]] + when called with the $PLATFORM_IO_PIN_PULLDOWN$ operation.]] } }, } } -data_pt = -{ - -- Title - title = "eLua platform interface - PIO", - - -- Menu name - menu_name = "PIO", - - -- OverviewA - overview = "This part of the platform interface deals with PIO (Programmable Input Output) operations, thus letting the user access the low level input/output facilities of the host MCU.", - - -- Data structures, constants and types - structures = - { - { text = [[enum -{ - // Pin operations - PLATFORM_IO_PIN_SET, $// Set the pin to 1$ - PLATFORM_IO_PIN_CLEAR, $// Clear the pin (set it to 0)$ - PLATFORM_IO_PIN_GET, $// Get the value of the pin$ - PLATFORM_IO_PIN_DIR_INPUT, $// Make the pin an input$ - PLATFORM_IO_PIN_DIR_OUTPUT, $// Make the pin an output$ - PLATFORM_IO_PIN_PULLUP, $// Activate the pullup on the pin$ - PLATFORM_IO_PIN_PULLDOWN, $// Activate the pulldown on the pin$ - PLATFORM_IO_PIN_NOPULL, $// Disable all pullups/pulldowns on the pin$ - // Port operations - PLATFORM_IO_PORT_SET_VALUE, $// Set port value$ - PLATFORM_IO_PORT_GET_VALUE, $// Get port value$ - PLATFORM_IO_PORT_DIR_INPUT, $// Set port as input$ - PLATFORM_IO_PORT_DIR_OUTPUT $// Set port as output$ -}; ]], - name = "PIO operations", - desc = [[These are the operations that can be executed by the PIO subsystem on both ports and pins. They are given as arguments to the @#platform_pio_op@platform_pio_op@ function - shown below.]] - }, - - { text = "typedef u32 pio_type;", - name = "PIO data type", - desc = [[This is the type used for the actual I/O operations. Currently defined as an unsigned 32-bit type, thus no port can have more than 32 pins. If this happens, it is possible to split - it in two or more parts and adding the new parts as "virtual ports" (logical ports that don't have a direct hardware equivalent). The "virtual port" technique is used in the AVR32 backend.]] - } - }, - - -- Functions - funcs = - { - { sig = "int #platform_pio_has_port#( unsigned port );", - desc = [[Checks if the platform has the hardware port specified as argument. Implemented in %src/common.c%, it uses the $NUM_PIO$ macro that must be defined in the - platform's $platform_conf.h$ file (see @arch_overview.html#platforms@here@ for details). For example:

- ~#define NUM_PIO 4 $// The platform has 4 hardware PIO ports$~

]], - args = "$port$ - the port ID", - ret = "1 if the port exists, 0 otherwise", - }, - - { sig = "int #platform_pio_has_pin#( unsigned port, unsigned pin );", - desc = [[Checks if the platform has the hardware port and pin specified as arguments. Implemented in %src/common.c%, it uses the $NUM_PIO$ macro to check the validity - of the port and the $PIO_PINS_PER_PORT$ or $PIO_PIN_ARRAY$ macros to check the validity of the pin. The macros must be defined in the platform's $platform_conf.h$ file - (see @arch_overview.html#platforms@here@ for details).

-
    -
  • use $PIO_PINS_PER_PORT$ when all the ports of the MCU have the same number of pins. For example: - ~#define PIO_PINS_PER_PORT 8 $// Each port has 8 pins$~
    • -
  • use $PIO_PIN_ARRAY$ when different ports of the MCU have different number of pins. For example: - ~#define PIO_PIN_ARRAY { 4, 4, 2, 6 } $// Port 0 has 4 pins, port 1 has 4 pins, port 2 has 2 pins, port 3 has 6 pins$~
    • -

]], - args = - { - "$port$ - the port ID", - "$pin$ - the pin number" - }, - ret = "1 if the pin exists, 0 otherwise", - }, - - { sig = "const char* #platform_pio_get_prefix#( unsigned port );", - desc = [[Get the port prefix. Used to establish if the port notation uses numbers (P0, P1, P2...) or letters (PA, PB, PC...). Implemented in %src/common.c%, it uses the - $PIO_PREFIX$ macro that must be defined in the platform's $platform_conf.h$ file (see @arch_overview.html#platforms@here@ for details). The value of this macro can be either '0' (for - numeric notation) or 'A' (for letter notation). For example:

- ~#define PIO_PREFIX 'A' $// Use PA, PB, PC ... for port notation$~

]], - args = "$port$ - the port ID", - ret = "the port prefix (either '0' or 'A')", - }, - - { sig = "pio_type #platform_pio_op#( unsigned port, pio_type pinmask, int op );", - link = "platform_pio_op", - desc = "This is the function that does the actual I/O work. It is implemented in the platform's own porting layer (%platform.c%, see @arch_overview.html#ports@here@ for more details).", - args = - { - "$port$ - the port number", - [[$pinmask$ - has different meanings: -

    -
  • for $pin operations$ it is the mask of pins in the operation. Each pin on which the function action is executed is encoded with an 1 in the corresponding bit position - of the pinmask.
    • -
  • for $port operations$ it is only meaningful for $PLATFORM_IO_PORT_SET_VALUE$ and in this case it specifies the new value of the port.
    • -
]], - "$op$ - specifies the I/O operations, as specified @#pio_operations@here@." - }, - ret = - { - "an actual value for $PLATFORM_IO_PIN_GET$ (0 or 1) and $PLATFORM_IO_PORT_GET$ (the value of the port).", - [[an error flag for all the other operations: 1 if the operation succeeded, 0 otherwise. For example, a platform that doesn't have pulldowns on its ports will always return a 0 - when caled with the $PLATFORM_IO_PIN_PULLDOWN$ operation.]] - } - }, - } -} - +data_pt = data_en diff --git a/doc/eluadoc/arch_platform_pwm.lua b/doc/eluadoc/arch_platform_pwm.lua index 972ab0d4..21783064 100644 --- a/doc/eluadoc/arch_platform_pwm.lua +++ b/doc/eluadoc/arch_platform_pwm.lua @@ -49,102 +49,45 @@ enum ret = "The actual frequency set on the PWM channel, which might differ from the $frequency$ parameter, depeding on the hardware", }, - { sig = "u32 #platform_pwm_op#( unsigned id, int op, u32 data );", - desc = "Executes an operation on a PWM channel", + { sig = "u32 #platform_pwm_start#( unsigned id );", + desc = "Starts PWM generation on the specified channel", args = { "$id$ - PWM channel ID", - [[$op$ - the operation that must be executed. It can take any value from @#pwm_operations@this enum@, as follows: -
    -
  • $PLATFORM_PWM_OP_START$: starts PWM generation on the specified channel.
    • -
  • $PLATFORM_PWM_OP_STOP$: stops PWM generation on the specified channel.
    • -
  • $PLATFORM_PWM_OP_SET_CLOCK$: sets the $base$ clock of the specified PWM channel (which will be used to generate the frequencies requested by - @#platform_pwm_setup@platform_pwm_setup@) to $data$ hertz.
    • -
  • $PLATFORM_PWM_OP_GET_CLOCK$: get the $base$ clock of the specified PWM channel.
    • -
]], - "$data$ - when used with $op$ == $PLATFORM_PWM_OP_SET_CLOCK$ it is used to specify the value of the base clock. Not used with other operations." - }, - ret = + } + }, + + { sig = "u32 #platform_pwm_stop#( unsigned id );", + desc = "Stops PWM generation on the specified channel", + args = { - "the actual value of the base clock when $op$ == $PLATFORM_PWM_OP_SET_CLOCK$, which might be different than $data$ depending on the hardware", - "the value of the base clock when $op$ == $PLATFORM_PWM_OP_GET_CLOCK$", - "irellevant for other operations" - } - } - } -} - -data_pt = -{ - -- Title - title = "eLua platform interface - PWM", - - -- Menu name - menu_name = "PWM", - - -- Overview - overview = "This part of the platform interface groups functions related to the PWM channel(s) of the MCU.", - - -- Data structures, constants and types - structures = - { - { text = [[// PWM operations -enum -{ - PLATFORM_PWM_OP_START, - PLATFORM_PWM_OP_STOP, - PLATFORM_PWM_OP_SET_CLOCK, - PLATFORM_PWM_OP_GET_CLOCK -} ]], - name = "PWM operations", - desc = "This enum lists all the operations that can be executed on a given PWM channel." - }, - }, - - -- Functions - funcs = - { - { sig = "int #platform_pwm_exists#( unsigned id );", - desc = [[Checks if the platform has the PWM channel specified as argument. Implemented in %src/common.c%, it uses the $NUM_PWM$ macro that must be defined in the - platform's $platform_conf.h$ file (see @arch_overview.html#platforms@here@ for details). For example:

- ~#define NUM_PWM 4 $// The platform has 4 PWM channels$~

]], - args = "$id$ - PWM channel ID", - ret = "1 if the specified PWM channel exists, 0 otherwise" - }, - - { sig = "u32 #platform_pwm_setup#( unsigned id, u32 frequency, unsigned duty );", - desc = "Sets up a PWM channel", - args = - { - "$id$ - PWM channel ID", - "$frequency$ - PWM channel frequency (in hertz)", - "$duty$ - PWM channel duty cycle, specified as percent (from 0 to 100). Note that some platform don't allow the full 0%-100% duty cycle" - }, - ret = "The actual frequency set on the PWM channel, which might differ from the $frequency$ parameter, depeding on the hardware", - }, - - { sig = "u32 #platform_pwm_op#( unsigned id, int op, u32 data );", - desc = "Executes an operation on a PWM channel", - args = - { - "$id$ - PWM channel ID", - [[$op$ - the operation that must be executed. It can take any value from @#pwm_operations@this enum@, as follows: -

    -
  • $PLATFORM_PWM_OP_START$: starts PWM generation on the specified channel.
    • -
  • $PLATFORM_PWM_OP_STOP$: stops PWM generation on the specified channel.
    • -
  • $PLATFORM_PWM_OP_SET_CLOCK$: sets the $base$ clock of the specified PWM channel (which will be used to generate the frequencies requested by - @#platform_pwm_setup@platform_pwm_setup@) to $data$ hertz.
    • -
  • $PLATFORM_PWM_OP_GET_CLOCK$: get the $base$ clock of the specified PWM channel.
    • -
]], - "$data$ - when used with $op$ == $PLATFORM_PWM_OP_SET_CLOCK$ it is used to specify the value of the base clock. Not used with other operations." - }, - ret = - { - "the actual value of the base clock when $op$ == $PLATFORM_PWM_OP_SET_CLOCK$, which might be different than $data$ depending on the hardware", - "the value of the base clock when $op$ == $PLATFORM_PWM_OP_GET_CLOCK$", - "irellevant for other operations" - } - } + "$id$ - PWM channel ID", + } + }, + + { sig = "u32 #platform_pwm_set_clock#( unsigned id, u32 clock );", + desc = [[Sets the $base$ clock of the specified PWM channel + (which will be used to generate the frequencies requested by + @#platform_pwm_setup@platform_pwm_setup@) to $data$ hertz.]], + args = + { + "$id$ - PWM channel ID", + "$clock$ - the desired frequency of the base clock." + }, + ret = [[The actual value of the base clock, which might be different + from $data$ depending on the hardware]], + }, + + { sig = "u32 #platform_pwm_get_clock#( unsigned id );", + desc = "Gets the $base$ clock of the specified PWM channel", + args = + { + "$id$ - PWM channel ID", + "$clock$ - the desired frequency of the base clock." + }, + ret = "the value of the base clock" + }, } } +data_pt = data_en diff --git a/doc/eluadoc/arch_platform_spi.lua b/doc/eluadoc/arch_platform_spi.lua index 81355809..102de98a 100644 --- a/doc/eluadoc/arch_platform_spi.lua +++ b/doc/eluadoc/arch_platform_spi.lua @@ -82,84 +82,4 @@ data_en = } } -data_pt = -{ - -- Menu name - menu_name = "SPI", - - -- Title - title = "eLua platform interface - SPI", - - -- Overview - overview = "This part of the platform interface groups functions related to the SPI interface(s) of the MCU.", - - -- Data structures, constants and types - structures = - { - { text = [[// SPI mode -#define PLATFORM_SPI_MASTER 1 -#define PLATFORM_SPI_SLAVE 0 ]], - name = "Chip select", - desc = "Constants used to select/deselect the SPI SS pin (if applicable)." - }, - - { text = [[// SS values -#define PLATFORM_SPI_SELECT_ON 1 -#define PLATFORM_SPI_SELECT_OFF 0]], - name = "SPI mode", - desc = "Constants used to select/deselect the SPI SS pin (if applicable)." - }, - - { text = "typedef u32 spi_data_type;", - name = "SPI data type", - desc = "This is the type of a SPI data word, thus limiting the maximum size of a SPI data work to 32 bits (which should be enough for all practical purposes)." - } - }, - - -- Functions - funcs = - { - { sig = "int #platform_spi_exists#( unsigned id );", - desc = [[Checks if the platform has the hardware SPI specified as argument. Implemented in %src/common.c%, it uses the $NUM_SPI$ macro that must be defined in the - platform's $platform_conf.h$ file (see @arch_overview.html#platforms@here@ for details). For example:

- ~#define NUM_SPI 1 $// The platform has 1 SPI interface$~

]], - args = "$id$ - SPI interface ID", - ret = "1 if the SPI interface exists, 0 otherwise" - }, - - { sig = "u32 #platform_spi_setup#( unsigned id, int mode, u32 clock, unsigned cpol, unsigned cpha, unsigned databits );", - desc = [[This function is used to initialize the parameters of the SPI interface. NOTE: currently, only master SPI mode is implemented in eLua.]], - args = - { - "$id$ - SPI interface ID", - "$mode$ - SPI port mode ($PLATFORM_SPI_MASTER$ or $PLATFORM_SPI_SLAVE$, see @#spi_mode@here@.", - "$clock$ - clock speed for the SPI interface in master mode.", - "$cpol$ - SPI clock polarity", - "$cpha$ - SPI clock phase", - "$databits$ - length of the SPI data word in bits (usually 8, but configurable on some platforms)." - }, - ret = "the actual clock set for the SPI interface. Depending on the hardware, this may have a different value than the $clock$ argument." - }, - - { sig = "spi_data_type #platform_spi_send_recv#( unsigned id, spi_data_type data );", - desc = "Executes a SPI read/write cycle", - args = - { - "$id$ - SPI interface ID", - "$data$ - data to be sent to the SPI interface", - }, - ret = "data read from the SPI interface" - }, - - { sig = "void #platform_spi_select#( unsigned id, int is_select );", - desc = [[For platforms that have a dedicates SS (Slave Select) pin in master SPI mode that can be controlled manually, this function should enable/disable this pin. If this functionality - does not exist in hardware this function does nothing.]], - args = - { - "$id$ - SPI interface ID.", - "$is_select$ - $PLATFORM_SPI_SELECT_ON$ to select, $PLATFORM_SPI_SELECT_OFF$ to deselect , see @#chip_select@here@." - }, - } - } -} - +data_pt = data_en diff --git a/doc/eluadoc/arch_platform_timers.lua b/doc/eluadoc/arch_platform_timers.lua index b5fab827..4b11e79f 100644 --- a/doc/eluadoc/arch_platform_timers.lua +++ b/doc/eluadoc/arch_platform_timers.lua @@ -1,5 +1,13 @@ -- eLua platform interface - timers +--[[ +// The next 3 functions need to be implemented only if the generic system timer mechanism +// (src/common.c:cmn_systimer*) is used by the backend +u64 platform_timer_sys_raw_read(); +void platform_timer_sys_enable_int(); +void platform_timer_sys_disable_int(); +--]] + data_en = { -- Title @@ -10,14 +18,15 @@ data_en = -- Overview overview = [[This part of the platform interface groups functions related to the timers of the MCU. It also makes provisions for using $virtual timers$ on any platform, see @#virtual@this section@ - for details. Keep in mind that in the following paragraphs a $timer id$ can reffer to both a hardware timer or a virtual timer.]], + for details. Keep in mind that in the following paragraphs a $timer id$ can refer to both a hardware timer or a virtual timer.]], -- Data structures, constants and types structures = { - { text = "typedef u32 timer_data_type;", + { text = "typedef u64/u32 timer_data_type;", name = "Timer data type", - desc = "This defines the data type used to specify delays and time intervals (which are always specifide in $microseconds$)." + desc = [[This defines the data type used to specify delays and time intervals (which are always specified in $microseconds$). The choice between u64 and u32 for the timer data type depends +on the build type, check ^#the_system_timer^here^ for mode details.]] }, { text = [[// Timer operations @@ -28,7 +37,8 @@ enum PLATFORM_TIMER_OP_SET_CLOCK, PLATFORM_TIMER_OP_GET_CLOCK, PLATFORM_TIMER_OP_GET_MAX_DELAY, - PLATFORM_TIMER_OP_GET_MIN_DELAY + PLATFORM_TIMER_OP_GET_MIN_DELAY, + PLATFORM_TIMER_OP_GET_MAX_CNT };]], name = "Timer operations", desc = "This enum lists all the operations that can be executed on a given timer." @@ -46,9 +56,9 @@ enum ret = "1 if the timer exists, 0 otherwise" }, - { sig = "void #platform_timer_delay#( unsigned id, u32 delay_us );", - desc = [[Waits on a timer, then returns. This function is "split" in two parts: a platform-independent part implemented in %src/common.c% (that - handles virtual timers) and a platform-dependent part that must be implemented by each platform in a function named @#platform_s_timer_delay@platform_s_timer_delay@. This function handles both + { sig = "void #platform_timer_delay#( unsigned id, timer_data_type delay_us );", + desc = [[Waits on a timer, then returns. This function is "split" in two parts: a platform-independent part implemented in %src/common_tmr.c% (that + handles virtual timers and the system timer) and a platform-dependent part that must be implemented by each platform in a function named @#platform_s_timer_delay@platform_s_timer_delay@. This function handles both hardware timer IDs and virtual timer IDs.
IMPORTANT NOTE: the real delay after executing this functions depends on a number of variables, most notably the base clock of the timer and the size of the timer counter register (32 bits on some platforms, 16 bits on most platforms, other values are less common). To ensure that the delay you're requesting is achievable, use @@ -62,9 +72,9 @@ enum } }, - { sig = "void #platform_s_timer_delay#( unsigned id, u32 delay_us );", - desc = [[This function is identical in functionality to @#platform_timer_delay@platform_timer_delay@, but this is the function that must actually be implemented by a platform port, - and it must never handle virtual timer IDs, only hardware timer IDs. It has the same @#limitations@limitations@ as @#platform_timer_delay@platform_timer_delay@.]], + { sig = "void #platform_s_timer_delay#( unsigned id, timer_data_type delay_us );", + desc = [[This function is identical in functionality to @#platform_timer_delay@platform_timer_delay@, but this is the function that must actually be implemented by a platform port + and it must never handle virtual timer IDs or the system timer ID, only hardware timer IDs. It has the same @#limitations@limitations@ as @#platform_timer_delay@platform_timer_delay@.]], args = { "$id$ - the timer ID", @@ -72,8 +82,8 @@ enum } }, - { sig = "u32 #platform_timer_op#( unsigned id, int op, u32 data );", - desc = [[Executes an operation on a timer. This function is "split" in two parts: a platform-independent part implemented in %src/common.c% (that handles virtual timers) and a + { sig = "timer_data_type #platform_timer_op#( unsigned id, int op, timer_data_type data );", + desc = [[Executes an operation on a timer. This function is "split" in two parts: a platform-independent part implemented in %src/common_tmr.c% (that handles virtual timers and the system timer) and a platform-dependent part that must be implemented by each platform in a function named @#platform_s_timer_op@platform_s_timer_op@. This function handles both hardware timer IDs and virtual timer IDs.]], args = @@ -87,6 +97,7 @@ enum

  • $PLATFORM_TIMER_GET_CLOCK$: get the clock of the specified timer.
  • $PLATFORM_TIMER_OP_GET_MAX_DELAY$: get the maximum achievable timeout on the specified timer (in us).
  • $PLATFORM_TIMER_OP_GET_MIN_DELAY$: get the minimum achievable timeout on the specified timer (in us).
    • +
  • $PLATFORM_TIMER_OP_GET_MAX_CNT$: get the maximum value of the timer's counter register.
    • ]], "$data$ - used to specify the timer clock value when $op = PLATFORM_TIMER_SET_CLOCK$, ignored otherwise", }, @@ -97,13 +108,14 @@ enum "the actual clock set on the timer, which might be different than the request clock depending on the hardware if $op = PLATFORM_TIMER_SET_CLOCK$", "the timer clock if $op = PLATFORM_TIMER_GET_CLOCK$", "the maximum achievable delay (in microseconds) if $op = PLATFORM_TIMER_OP_GET_MAX_DELAY$", - "the minimum achievable delay (in microseconds) if $op = PLATFORM_TIMER_OP_GET_MIN_DELAY$" + "the minimum achievable delay (in microseconds) if $op = PLATFORM_TIMER_OP_GET_MIN_DELAY$", + "the maximum value of the timer's coutner register if $op == PLATFORM_TIMER_OP_GET_MAX_CNT$", } }, - { sig = "u32 #platform_s_timer_op#( unsigned id, int op, u32 data );", - desc = [[This function is identical in functionality to @#platform_timer_op@platform_timer_op@, but this is the function that must actually be implemented by a platform port, and it must - never handle virtual timer IDs, only hardware timer IDs.]], + { sig = "timer_data_type #platform_s_timer_op#( unsigned id, int op, timer_data_type data );", + desc = [[This function is identical in functionality to @#platform_timer_op@platform_timer_op@, but this is the function that must actually be implemented by a platform port and it must + never handle virtual timer IDs or the system timer, only hardware timer IDs.]], args = { "$id$ - the timer ID", @@ -115,6 +127,7 @@ enum
  • $PLATFORM_TIMER_GET_CLOCK$: get the clock of the specified timer.
  • $PLATFORM_TIMER_OP_GET_MAX_DELAY$: get the maximum achievable timeout on the specified timer (in us).
  • $PLATFORM_TIMER_OP_GET_MIN_DELAY$: get the minimum achievable timeout on the specified timer (in us).
    • +
  • $PLATFORM_TIMER_OP_GET_MAX_CNT$: get the maximum value of the timer's counter register.
    • ]], "$data$ - used to specify the timer clock value when $op = PLATFORM_TIMER_SET_CLOCK$, ignored otherwise", }, @@ -125,23 +138,29 @@ enum "the actual clock set on the timer, which might be different than the request clock depending on the hardware if $op = PLATFORM_TIMER_SET_CLOCK$", "the timer clock if $op = PLATFORM_TIMER_GET_CLOCK$", "the maximum achievable delay (in microseconds) if $op = PLATFORM_TIMER_OP_GET_MAX_DELAY$", - "the minimum achievable delay (in microseconds) if $op = PLATFORM_TIMER_OP_GET_MIN_DELAY$" + "the minimum achievable delay (in microseconds) if $op = PLATFORM_TIMER_OP_GET_MIN_DELAY$", + "the maximum value of the timer's coutner register if $op == PLATFORM_TIMER_OP_GET_MAX_CNT$", } }, - { sig = "u32 #platform_timer_get_diff_us#( unsigned id, timer_data_type end, timer_data_type start );", - desc = [[Return the time difference (in us) betweeen two timer values. This function is generic for all platforms, thus it is implemented in %src/common.c%.]], + { sig = "timer_data_type #platform_timer_get_diff_us#( unsigned id, timer_data_type end, timer_data_type start );", + desc = [[Return the time difference (in us) between two timer values (as returned by calling @refman_gen_tmr.html#platform_timer_op@platform_timer_op@ with $PLATFORM_TIMER_OP_READ$ or $PLATFORM_TIMER_OP_START$. This function +is generic, thus it is implemented in %src/common.c%. NOTE: the order of $end$ and $start$ is important. $end$ must correspond to a moment in time which came after $start$. The function knows how to deal +with $a single$ timer overflow condition ($end$ is less than $start$); if the timer overflowed 2 or more times between $start$ and $end$ the result of this function will be incorrect.]], args = { "$id$ - the timer ID", - "$end$ - the first timer value", - "$start$ - the second timer value", + "$end$ - the final counter value.", + "$start$ - the initial counter value.", }, ret = "the time difference (in microseconds)" }, - { sig = "int #platform_timer_set_match_int#( unsigned id, u32 period_us, int type );", - desc = "Setup the timer match interrupt. Only available if interrupt support is enabed, check @inthandlers.html@here@ for details.", + { sig = "int #platform_timer_set_match_int#( unsigned id, timer_data_type period_us, int type );", + desc = [[Setup the timer match interrupt. Only available if interrupt support is enabled, check @inthandlers.html@here@ for details.This function is "split" in two parts: a platform-independent part +implemented in %src/common_tmr.c% (that handles virtual timers and the system timer) and a platform-dependent part that must be implemented by each platform in a function named +@#platform_s_timer_set_math_int@platform_s_timer_set_match_int@. This function handles both hardware timer IDs and virtual timer IDs. NOTE: the @#the_system_timer@system timer@ can't +generate interrupts.]], args = { "$id$ - the timer ID", @@ -153,11 +172,62 @@ $period_us$ microseconds]] { "$PLATFORM_TIMER_INT_OK$ if the operation was successful.", "$PLATFORM_TIMER_INT_TOO_SHORT$ if the specified period is too short.", + "$PLATFORM_TIMER_INT_TOO_LONG$ if the specified period is too long.", "$PLATFORM_TIMER_INT_INVALID_ID$ if the specified timer cannot handle this operation." } - } + }, + + { sig = "int #platform_s_timer_set_match_int#( unsigned id, timer_data_type period_us, int type );", + desc = [[This function is identical in functionality to @#platform_timer_set_match_int@platform_timer_set_match_int@, but this is the function that must actually be implemented by a platform port and it must + never handle virtual timer IDs or the system timer, only hardware timer IDs.]], + args = + { + "$id$ - the timer ID", + "$period_us$ - the period (in microseconds) of the timer interrupt. Setting this to 0 disables the timer match interrupt.", + [[$type$ - $PLATFORM_TIMER_INT_ONESHOT$ for an interrupt that occurs only once after $period_us$ microseconds, or $PLATFORM_TIMER_INT_CYCLIC$ for an interrupt that occurs every +$period_us$ microseconds]] + }, + ret = + { + "$PLATFORM_TIMER_INT_OK$ if the operation was successful.", + "$PLATFORM_TIMER_INT_TOO_SHORT$ if the specified period is too short.", + "$PLATFORM_TIMER_INT_TOO_LONG$ if the specified period is too long.", + "$PLATFORM_TIMER_INT_INVALID_ID$ if the specified timer cannot handle this operation." + } + }, + + { + sig = "timer_data_type #platform_timer_read_sys#();", + desc = "Returns the current value of the system timer, see @#the_system_timer@here@ for more details.", + ret = "The current value of the system timer." + }, + + { + sig = "int #platform_timer_sys_available#();", + desc = [[Used to check the availability of the system timer. This function is platform independent and is implemented in %src/common_tmr.c%. It returns the value of the $PLATFORM_HAS_SYSTIMER$ macro, check +@#the_system_timer@here@ for more details.]], + ret = "1 if the system timer is implemented, 0 otherwise." + }, + + { + sig = "u64 #platform_timer_sys_raw_read#();", + desc = [[Return the counter of the timer used to implement the system timer. Needs to be implemented only if eLua's generic system timer mechanism is used, check @#the_system_timer@here@ for details.]], + ret = "The counter of the timer used to implement the system timer." + }, + + { + sig = "void #platform_timer_sys_enable_int#();", + desc = [[Enable the overflow/match interrupt of the timer used to implement the system timer. Needs to be implemented only if eLua's generic system timer mechanism is used, check @#the_system_timer@here@ for details.]], + }, + + { + sig = "void #platform_timer_sys_disable_int#();", + desc = [[Disable the overflow/match interrupt of the timer used to implement the system timer. Needs to be implemented only if eLua's generic system timer mechanism is used, check @#the_system_timer@here@ for details.]], + }, + }, + auxdata = { { title = "Virtual timers", @@ -199,8 +269,88 @@ $period_us$ microseconds]] $VTMR_FIRST_ID$) is the ID of the first virtual timer in the system, and $VTMR_FIRST_ID+2$ is the ID of the third virtual timer in the system.

    Virtual timers are capable of generating timer match interrupts just like regular timers, check @#platform_timer_set_match_int@here@ for details. ]] - } + }, + { title = "The system timer", + desc = + [[The system timer was introduced in eLua 0.9 as a simpler alternative to the traditional eLua timers. Working with regular timers in eLua might be challenging for a number of reasons:

    +
      +
    • depending on the hardware, the timers might have a limited range. Because of this, they might not be able to timeout in the interval requested by the user.
      • +
    • the timers might have different ranges even on the same platform (they might have a different base clock, for example). The problem is further aggravated when switching platforms.
      • +
    • the timers might be shared with other hardware resources (for example PWMs or ADC triggers) so using them might have unexpected side effects.
      • +
    • manual timer management is error prone. The user needs to keep into account the timers he's using, their base frequencies and wether they are shared or not with the C code.
      • +
    +

    The ^#virtual_timers^virtual timers^ can fix some of the above problems, but their resolution is fairly low and they still require manual management.

    +

    The $system timer$ attemps to fix (at least partially) these issues. It is a timer with fixed resolution (1us) %on all platforms% and large counters:

    +
      +
    • if eLua is compiled in floating point mode (default) the counter is 52 bits wide. It will overflow after more than 142 %years%.
      • +
    • if eLua is compiled in 32 bit integer-only mode (lualong) the counter is 32 bits wide. It will overflow after about one hour.
      • +
    • if eLua is compiled in 64 bit integer-only mode (lualonglong, new in 0.9) the counter is again 52 bits wide and it will also overflow after more than 142 years.
      • +
    +

    The eLua API was partially modified to take full advantage of this new timer:

    +
      +
    • all the functions that can operate with a timeout (for example @refman_gen_uart.html#uart.read@uart.read@ or @refman_gen_net.html#net.accept@net.accept@) +will default to the system timer is a timer ID is not specified explicitly.
      • +
    • all the function in the @refman_gen_tmr.html@timer module@ will default to the system timer if a timer ID is not specified explicitly.
      • +
    • timeouts are specified in a more unified manner across the eLua modules as a $[timeout], [timer_id]$ pair: + + + + + + + + + + + + + + + + + + + + + + + + + + + +
      timeouttimer_idResult
      not specifiedany valueinfinite timeout (the function blocks until it completes).
      0any valueno timeout (the function returns immediately). +
      a positive valuenot specifiedthe system timer will be used to measure the function's timeout.
      a positive valuea timer IDthe specified timer will be used to measure the function's timeout.
      +
      • +
    +

    Using the system timer as much as possible is also encouraged with C code that uses the eLua C api, not only with Lua programs. The C code can use the system timer by specifying +$PLATFORM_TIMER_SYS_ID$ as the timer ID.

    +

    From an implementation stand point, the system timer is built around a hardware timer with a base clock of at least 1MHz that can generate an interrupt when the timer counter overflows +or when it reaches a certain value. The interrupt handler updates the upper part of the system timer counter (basically an overflow counter). eLua has a generic mechanism that can be used +to implement a system timer on any platform using this method. To take advantage of this mechanism follow the steps below:

    +
      +
    1. define the $PLATFORM_HAS_SYSTIMER$ macro in your %platform_conf.h% file.
      2. +
    2. implement @#platform_timer_sys_raw_read@platform_timer_sys_raw_read@, @#platform_timer_sys_enable_int@platform_timer_sys_enable_int@ and @#platform_timer_sys_disable_int@platform_timer_sys_disable_int@.
      3. +
    3. include the %common.h% header.
      4. +
    4. setup your hardware timer and its associated interrupt. This should happen an initialization time (for example in %platform_init%).
      5. +
    5. call %cmn_systimer_set_base_freq% with the base frequency of your timer in Hz.
      6. +
    6. call %cmn_systimer_set_interrupt_freq% with the frequency of the timer's overflow/match interrupt in Hz. Alternatively you can call %cmn_systimer_set_interrupt_period_us% to set the timer's overflow/match +interrupt %period% (in microseconds) instead of its frequency. Use the latter form if the frequency is not an integer.
      7. +
    7. call %cmn_systimer_periodic% from your timer's overflow interrupt handler.
      8. +
    8. use this implementation for @#platform_timer_read_sys@platform_timer_read_sys@: + ~timer_data_type platform_timer_read_sys() +{ + return cmn_systimer_get(); +}~
    +

    Note that the above mechanism is optional. A platform might have a different method to implement the system timer; this is OK as long as the system timer requirements are respected.

    +

    IMPORTANT NOTE: although system timer support in eLua is optional, implementing the system timer is highly recommended. As already specified, all the timer IDs +in various eLua modules default to the system timer. This means that any code that was written under the assumption that a system timer is present (which is a fair assumption) will fail on +platforms that don't actually have a system timer. Check @status.html#systmr@here@ for a list of platforms that implement the system timer. If your platform doesn't implement the +system timer, you'll get this warning at compile time:

    + ~#warning This platform does not have a system timer. Your eLua image might not work as expected.~ +]] } + } } diff --git a/doc/eluadoc/arch_platform_uart.lua b/doc/eluadoc/arch_platform_uart.lua index 51896b72..4acf4727 100644 --- a/doc/eluadoc/arch_platform_uart.lua +++ b/doc/eluadoc/arch_platform_uart.lua @@ -36,12 +36,6 @@ enum desc = "Constants used to specify the number of UART stop bits.", }, - { text = [[// "Infinite timeout" constant for recv -#define PLATFORM_UART_INFINITE_TIMEOUT (-1)]], - name = "UART timeout", - desc = "This constant is used as a special timeout value (infinite timeout) in the UART functions that expect a timeout as argument.", - }, - { text = [[// Virtual UART IDs #define SERMUX_SERVICE_ID_FIRST 0xD0 #define SERMUX_SERVICE_ID_LAST 0xD7 @@ -108,7 +102,7 @@ enum }, }, - { sig = "int #platform_uart_recv#( unsigned id, unsigned timer_id, s32 timeout );", + { sig = "int #platform_uart_recv#( unsigned id, unsigned timer_id, timer_data_type timeout );", link = "platform_uart_recv", desc = [[Receive data from the UART interface (blocking/non blocking with timeout/immediate).
    This function is "split" in two parts: a platform-independent part that is implemented in %src/common.c% and a platform-dependent part that must be implemented by each @@ -121,7 +115,7 @@ enum
    • $timeout > 0$: the timer with the specified $timer_id$ will be used to timeout the receive operation after $timeout$ microseconds.
    • $timeout = 0$: the function returns immediately regardless of data being available or not. $timer_id$ is ignored.
      • -
    • $timeout$ = @#uart_timeout@PLATFORM_UART_INFINITE_TIMEOUT@: the function waits indefinitely for UART data to be available and returns it. In this mode the function doesn't +
    • $timeout = PLATFORM_TIMER_INF_TIMEOUT$: the function waits indefinitely for UART data to be available and returns it. In this mode the function doesn't time out, so $timer_id$ is ignored.
    ]], }, @@ -129,11 +123,11 @@ enum { "if $timeout > 0$ and data from the UART is available in $timeout$ microseconds of less it is returned, otherwise -1 is returned", "if $timeout = 0$ and data from the UART is available when the function is called it is returned, otherwise -1 is returned", - "if $timeout$ = @#uart_timeout@PLATFORM_UART_INIFINITE_TIMEOUT@ it returns the data read from the UART after it becomes available" + "if $timeout = PLATFORM_TIMER_INF_TIMEOUT$ it returns the data read from the UART after it becomes available" } }, - { sig = "int #platform_s_uart_recv#( unsigned id, s32 timeout );", + { sig = "int #platform_s_uart_recv#( unsigned id, timer_data_type timeout );", link = "platform_s_uart_recv", desc = [[This is the platform-dependent part of the UART receive function @#platform_uart_recv@platform_uart_recv@ and is in fact a "subset" of the full function (thus being easier to implement by each platform in part). In particular, it never needs to deal with the $timeout > 0$ case, which is handled by @#platform_uart_recv@platform_uart_recv@.]], @@ -143,13 +137,13 @@ enum [[$timeout$ - specifies a timeout for the receive operation as follows:
    • $timeout = 0$: the function returns immediately regardless of data being available or not.
      • -
    • $timeout$ = @#uart_timeout@PLATFORM_UART_INFINITE_TIMEOUT@: the function waits indefinitely for UART data to be available and returns it.
      • +
    • $timeout = PLATFORM_TIMER_INF_TIMEOUT$: the function waits indefinitely for UART data to be available and returns it.
    ]], }, ret = { "if $timeout = 0$ and data from the UART is available when the function is called it is returned, otherwise -1 is returned", - "if $timeout$ = @#uart_timeout@PLATFORM_UART_INIFINITE_TIMEOUT@ it returns the data read from the UART after it becomes available" + "if $timeout = PLATFORM_TIMER_INF_TIMEOUT$ it returns the data read from the UART after it becomes available" } }, diff --git a/doc/eluadoc/refman_gen_adc.lua b/doc/eluadoc/refman_gen_adc.lua index f4833055..ccbb6949 100644 --- a/doc/eluadoc/refman_gen_adc.lua +++ b/doc/eluadoc/refman_gen_adc.lua @@ -70,7 +70,7 @@ data_en = "$clock$ - frequency to acquire samples at in Hz (number of samples per second), 0 to acquire as fast as possible.", "$timer_id$ - Timer channel ID to use to control ADC conversion. Note: At this time, a timer selection will apply to all channels on a given ADC peripheral." }, - ret = "$clock$ - actual acquisition frequency to be used" + ret = "$clock$ - actual acquisition frequency that was set" }, { sig = "status = #adc.isdone#( id )", desc = "Check whether samples are still being acquired on a channel.", @@ -81,7 +81,7 @@ data_en = ret = "$status$ - 1 if no samples are being acquired, 0 if samples are pending acquisition." }, { sig = "#adc.setblocking#( id, mode )", - desc = "Set whether or not functions that request converted samples should wait for requested samples or return immediately with what is available.", + desc = "Set whether or not functions that request converted samples should wait for requested samples or return immediately with what is available. If this function is not called, each channel starts in blocking mode.", args = { "$id$ - ADC channel ID.", diff --git a/doc/eluadoc/refman_gen_cpu.lua b/doc/eluadoc/refman_gen_cpu.lua index 6271915c..f1ab87bb 100644 --- a/doc/eluadoc/refman_gen_cpu.lua +++ b/doc/eluadoc/refman_gen_cpu.lua @@ -31,7 +31,7 @@ $_C$. For example, to get the constants listed above declare your $PLATFORM_CPU_ _C( INT_GPIOB ),\ ................. _C( INT_UDMA )~ -

    It's worth to note that adding more constants does not increas RAM usage, only Flash usage, so you can expose as much constants as you need without worrying about RAM consumption.
    +

    It's worth to note that adding more constants does not increase RAM usage, only Flash usage, so you can expose as many constants as you need without worrying about RAM consumption.
    This mechanism is also used to expose interrupt IDs to the CPU module, check @inthandlers.html@here@ for an overview of eLua interrupt support.]] }, }, diff --git a/doc/eluadoc/refman_gen_i2c.lua b/doc/eluadoc/refman_gen_i2c.lua index b7c7da42..0735898d 100644 --- a/doc/eluadoc/refman_gen_i2c.lua +++ b/doc/eluadoc/refman_gen_i2c.lua @@ -21,7 +21,7 @@ data_en = args = { "$id$ - the ID of the I2C interface.", - "$speed$ - the speed of the I2C interface. It can be either $i2c.FAST$ (400KHz) or $i2c.SLOW$ (100KHz).", + "$speed$ - the clock frequency of the I2C interface. It can be $i2c.FAST$ (400KHz), $i2c.SLOW$ (100KHz) or a number giving the required I2C bus clock speed in Hz.", }, ret = "the actual speed of the I2C interface." }, @@ -48,22 +48,22 @@ data_en = }, { sig = "wrote = #i2c.write#( id, data1, [data2], ..., [datan] )", - desc = "Writes data to a slave that already acknowledged an @#i2c.address@i2c.address@ call.", + desc = "Writes data to a slave that has already acknowledged an @#i2c.address@i2c.address@ call.", args = { "$id$ - the ID of the I2C interface.", - "$data1$ - the data to send. It can be either a number between 0 and 255, a string or a table (array).", + "$data1$ - the data to send. It can be either a number between 0 and 255, a string or a table (array) of numbers.", "$data2 (optional)$ - the second data to send.", "$datan (optional)$ - the %n%-th data to send." }, - ret = "the number of bytes actually wrote." + ret = "the number of bytes actually written." }, { sig = "data = #i2c.read#( id, numbytes )", - desc = "Reads a number of bytes from a slave that already acknowledged an @#i2c.address@i2c.address@ call. It acknowledges all the bytes received, except for the last one.", + desc = "Reads a number of bytes from a slave that has already acknowledged an @#i2c.address@i2c.address@ call. It acknowledges all the bytes received except for the last one.", args = { - "$id$ - the ID os the SPI interface.", + "$id$ - the ID of the I2C interface.", "$numbytes$ - the number of bytes to read." }, ret = "a string with all the data read from the I2C interface." diff --git a/doc/eluadoc/refman_gen_net.lua b/doc/eluadoc/refman_gen_net.lua index 1d37e46d..2d7859d9 100644 --- a/doc/eluadoc/refman_gen_net.lua +++ b/doc/eluadoc/refman_gen_net.lua @@ -104,15 +104,15 @@ argument. The IP is given as a string.]], ret = "$err$ - the error code, as defined @#error_codes@here@." }, - { sig = "socket, remoteip, err = #net.accept#( port, [timer_id, timeout] )", + { sig = "socket, remoteip, err = #net.accept#( port, [timeout], [timer_id] )", desc = "Accept a connection from a remote system with an optional timeout.", args = { "$port$ - the port to wait for connections from the remote system.", - [[$timer_id (optional)$ - the timer ID of the timer used to timeout the accept function after a specified time. If this is specified, $timeout$ must also -be specified.]], - [[$timeout (optional)$ - the timeout after which the accept function returns if no connection was requested. If this is specified, $timer_id$ must also -be specified.]] + [[$timeout (optional)$ - timeout of the operation, can be either $net.NO_TIMEOUT$ or 0 for non-blocking operation, $net.INF_TIMEOUT$ for +blocking operation, or a positive number that specifies the timeout in microseconds. The default value of this argument is $unet.INF_TIMEOUT$.]], + [[$timer_id (optional)$ - the ID of the timer used for measuring the timeout. If not specified it defaults to the @arch_platform_timers.html#the_system_timer@system timer@.]], + }, ret = { @@ -136,7 +136,7 @@ be specified.]] } }, - { sig = "res, err = #net.recv#( sock, format, [timer_id, timeout] )", + { sig = "res, err = #net.recv#( sock, format, [timeout], [timer_id] )", desc = "Read data from a socket.", args = { @@ -146,10 +146,9 @@ be specified.]]

  • $"*l"$: read a line (until the next '\n' character).
  • $an integer$: read up to that many bytes.
    • ]], - [[$timer_id (optional)$ - the timer ID of the timer used to timeout the recv function after a specified time. If this is specified, $timeout$ must also -be specified.]], - [[$timeout (optional)$ - the timeout after which the recv function returns if no connection was requested. If this is specified, $timer_id$ must also -be specified.]] + [[$timeout (optional)$ - timeout of the operation, can be either $net.NO_TIMEOUT$ or 0 for non-blocking operation, $net.INF_TIMEOUT$ for +blocking operation, or a positive number that specifies the timeout in microseconds. The default value of this argument is $unet.INF_TIMEOUT$.]], + [[$timer_id (optional)$ - the ID of the timer used for measuring the timeout. If not specified it defaults to the @arch_platform_timers.html#the_system_timer@system timer@.]], }, ret = { @@ -160,4 +159,3 @@ be specified.]] }, } -data_pt = data_en diff --git a/doc/eluadoc/refman_gen_tmr.lua b/doc/eluadoc/refman_gen_tmr.lua index bee583e1..1405bb1a 100644 --- a/doc/eluadoc/refman_gen_tmr.lua +++ b/doc/eluadoc/refman_gen_tmr.lua @@ -14,86 +14,100 @@ data_en = (see @arch_platform_timers.html#virtual_timers@here@ and @building.html@here@ for details), they can be used just like the "regular" (hardware) timers with a single exception: you can't set the clock of a virtual timer (using @#tmr.setclock@tmr.setclock@). To use virtual timers with this module, specify $tmr.VIRTx$ as the timer ID instead of a number. For example, if the eLua image was configured to support 4 virtual timers, they will - be available by using $tmr.VIRT0$ to $tmr.VIRT3$ as timer IDs.

    + be available by using $tmr.VIRT0$ to $tmr.VIRT3$ as timer IDs. The @arch_platform_timers.html#the_system_timer@system timer@ can also be used with + any of these functions by ommiting the timer ID or specifying it as $tmr.SYS_TIMER$.

    All "time units" (delays, differences in time) in this module, as well as in other parts of eLua (timeouts) are expressed in microseconds. However, please keep in mind that the actual timer resolution depends on many factors. For example, it's very likely that the @#tmr.delay@tmr.delay@ function won't - be able to delay for the exact amount you specify (in us), as the real delay depends ona number of variables, most notably the base clock of the timer + be able to delay for the exact amount you specify (in us), as the real delay depends on a number of variables, most notably the base clock of the timer and the size of the timer counter register (32 bits on some platforms, 16 bits on most platforms, other values are less common). To ensure that the delay you're requesting is achievable, use @#tmr.getmindelay@tmr.getmindelay@ and @#tmr.getmaxdelay@tmr.getmaxdelay@ to obtain the maximum and the minimum achievable wait times on your timer, respectively. Even if your delay is within these limits, the $precision$ of this function still varies a lot, - mainly as a function of the timer base clock.]], + mainly as a function of the timer base clock. Using the @arch_platform_timers.html#the_system_timer@system timer@ is highly encouraged if it is + available on the platform as it can eliminate the forementioned problems.]], -- Functions funcs = { - { sig = "#tmr.delay#( id, period )", + { sig = "#tmr.delay#( period, [id] )", desc = "Waits for the specified period, then returns.", args = { - "$period$ - the timer ID.", - "$period$ - how long to wait (in us)." + "$period$ - how long to wait (in us).", + "$id (optional)$ - the timer ID. If not specified it defaults to the @arch_platform_timers.html#the_system_timer@system timer@.", } }, - { sig = "counter = #tmr.read#( id )", + { sig = "counter = #tmr.read#( [id] )", desc= "Reads the timer counter register.", - args = "$id$ - the timer ID.", + args = "$id (optional)$ - the timer ID. If not specified it defaults to the @arch_platform_timers.html#the_system_timer@system timer@.", ret = "The value of the timer counter register." }, - { sig = "counter = #tmr.start#( id )", + { sig = "counter = #tmr.start#( [id] )", desc = "Starts the specified timer.", - args = "$id$ - the timer ID.", + args = "$id (optional)$ - the timer ID. If not specified it defaults to the @arch_platform_timers.html#the_system_timer@system timer@.", ret = "The value of the timer counter register when the timer started.", }, - { sig = "delta = #tmr.gettimediff#( id, counter1, counter2 )", - desc = "Computes the time difference between two timer counter values (you can get counter values by calling @#tmr.read@tmr.read@ or @#tmr.start@tmr.start@).", + { sig = "delta = #tmr.gettimediff#( end, start, [id] )", + desc = [[Computes the time difference between two timer counter values (obtained by calling @#tmr.read@tmr.read@ or @#tmr.start@tmr.start@). NOTE: the order +of $end$ and $start$ is important. $end$ must correspond to a moment in time which came after $start$. The function knows how to deal with $a single$ timer overflow condition ($end$ is less than $start$); if the timer overflowed 2 or more times between $start$ and $end$ the result of this function will be incorrect.]], args = { - "$id$ - the timer ID.", - "$counter1$ - the first counter value.", - "$counter2$ - the second counter value.", + "$end$ - the final counter value.", + "$start$ - the initial counter value.", + "$id (optional)$ - the timer ID. If not specified it defaults to the @arch_platform_timers.html#the_system_timer@system timer@.", + }, + ret = "The time difference (in us)." + }, + + { sig = "delta = #tmr.getdiffnow#( start, [id] )", + desc = [[Computes the time difference between a counter value from the past (obtained by calling @#tmr.read@tmr.read@ or @#tmr.start@tmr.start@) and the counter value corresponding to the current time.]], + args = + { + "$start$ - the initial counter value.", + "$id (optional)$ - the timer ID. If not specified it defaults to the @arch_platform_timers.html#the_system_timer@system timer@.", }, ret = "The time difference (in us)." }, - { sig = "mindelay = #tmr.getmindelay#( id )", - desc = "Get the minimum achieavable delay on the specified timer.", - args = "$id$ - the timer ID.", + + { sig = "mindelay = #tmr.getmindelay#( [id] )", + desc = "Get the minimum achievable delay on the specified timer.", + args = "$id (optional)$ - the timer ID. If not specified it defaults to the @arch_platform_timers.html#the_system_timer@system timer@.", ret = "The minimum achievable delay on the specified timer (in us)." }, - { sig = "maxdelay = #tmr.getmaxdelay#( id )", - desc = "Get the maximum achieavable delay on the specified timer.", - args = "$id$ - the timer ID.", + { sig = "maxdelay = #tmr.getmaxdelay#( [id] )", + desc = "Get the maximum achievable delay on the specified timer.", + args = "$id (optional)$ - the timer ID. If not specified it defaults to the @arch_platform_timers.html#the_system_timer@system timer@.", ret = "The maximum achievable delay on the specified timer (in us)." }, - { sig = "clock = #tmr.setclock#( id, clock )", + { sig = "clock = #tmr.setclock#( clock, [id] )", desc = "Set the timer clock (the clock used to increment the timer counter register).", args = { - "$id$ - the timer ID.", - "$clock$ - the timer clock (in Hz)." + "$clock$ - the timer clock (in Hz). ", + "$id (optional)$ - the timer ID. If not specified it defaults to the @arch_platform_timers.html#the_system_timer@system timer@.", }, ret = [[The actual clock set on the timer (in Hz). Depending on the hardware, this might have a different value than the $clock$ argument. -$NOTE:$ this function does not work with virtual timers.]] +$NOTE:$ this function does not work with virtual timers or with the system timer.]] }, - { sig = "clock = #tmr.getclock#( id )", + { sig = "clock = #tmr.getclock#( [id] )", desc = "Get the timer clock (the clock used to increment the timer counter register).", - args = "$id$ - the timer ID.", + args = "$id (optional)$ - the timer ID. If not specified it defaults to the @arch_platform_timers.html#the_system_timer@system timer@.", ret = "The timer clock (in Hz)." }, - { sig = "#tmr.set_match_int#( id, period, type )", + { sig = "#tmr.set_match_int#( period, type, [id] )", desc = "Setup the timer match interrupt. Only available if interrupt support is enabled, check @inthandlers.html@here@ for details.", args = { - "$id$ - the timer ID.", "$period$ - the interrupt period in microseconds. Setting this to 0 disabled the timer match interrupt.", - "$type$ - $tmr.INT_ONESHOT$ to generate a single interrupt after *period* microseconds, or $tmr.INT_CYCLIC$ to generate interrupts every $period$ microseconds." + "$type$ - $tmr.INT_ONESHOT$ to generate a single interrupt after *period* microseconds, or $tmr.INT_CYCLIC$ to generate interrupts every $period$ microseconds.", + [[$id (optional)$ - the timer ID. If not specified it defaults to the @arch_platform_timers.html#the_system_timer@system timer@ (but note that this happens only for consistency, as the system timer can't generate interrupts).]], } } diff --git a/doc/eluadoc/refman_gen_uart.lua b/doc/eluadoc/refman_gen_uart.lua index 1d0eaf33..297d4067 100644 --- a/doc/eluadoc/refman_gen_uart.lua +++ b/doc/eluadoc/refman_gen_uart.lua @@ -57,12 +57,10 @@ to the IDs of the virtual UARTs in the system.]] desc = "Read a single character from the serial port", args = { - "$id$ - the ID of the serial port", - [[$timeout (optional)$ - timeout of the receive operation, can be either $uart.NO_TIMEOUT$ or 0 for non-blocking operation, $uart.INF_TIMEOUT$ for -blocking operation, or a positive number that specifies the timeout in microseconds (in this case, the $timer_id$ parameter is also required). The default -value of this argument is $uart.INF_TIMEOUT$]], - [[$timer_id (optional)$ - the ID of the timer for the receive operation, needed if the $timeout$ parameter specifies an actual timeout (that is, -$timeout$ is neither $uart.NO_TIMEOUT$, nor $uart.INF_TIMEOUT$).]] + "$id$ - the ID of the serial port", + [[$timeout (optional)$ - timeout of the operation, can be either $uart.NO_TIMEOUT$ or 0 for non-blocking operation, $uart.INF_TIMEOUT$ for +blocking operation, or a positive number that specifies the timeout in microseconds. The default value of this argument is $uart.INF_TIMEOUT$.]], + [[$timer_id (optional)$ - the ID of the timer used for measuring the timeout. If not specified it defaults to the @arch_platform_timers.html#the_system_timer@system timer@.]], }, ret = "The character read from the serial port as a string, or the empty string it timeout occured while waiting for the character." }, @@ -79,10 +77,9 @@ $timeout$ is neither $uart.NO_TIMEOUT$, nor $uart.INF_TIMEOUT$).]]

  • $'*s'$ - read until a spacing character (like a space or a TAB) is found (the spacing character is not returned) or a timeout occurs.
  • $a positive number$ - read at most this many characters before returning (reading can stop earlier if a timeout occurs).
    • ]], - [[$timeout (optional)$ - timeout of the receive operation, can be either $uart.NO_TIMEOUT$ or 0 for non-blocking operation, $uart.INF_TIMEOUT$ for -blocking operation, or a positive number that specifies the inter-char timeout in microseconds (in this case, the $timer_id$ parameter is also required). The default value of this argument is $uart.INF_TIMEOUT$]], - [[$timer_id (optional)$ - the ID of the timer for the receive operation, needed if the $timeout$ parameter specifies an actual timeout (that is, -$timeout$ is neither $uart.NO_TIMEOUT$, nor $uart.INF_TIMEOUT$).]] + [[$timeout (optional)$ - timeout of the operation, can be either $uart.NO_TIMEOUT$ or 0 for non-blocking operation, $uart.INF_TIMEOUT$ for +blocking operation, or a positive number that specifies the timeout in microseconds. The default value of this argument is $uart.INF_TIMEOUT$.]], + [[$timer_id (optional)$ - the ID of the timer used for measuring the timeout. If not specified it defaults to the @arch_platform_timers.html#the_system_timer@system timer@.]], }, ret = [[The data read from the serial port as a string (or as a number if $format$ is $'*n'$). If a timeout occures, only the data read before the timeout is returned. If the function times out while trying to read the first character, the empty string is returned]] }, diff --git a/doc/eluadoc/refman_ps_mizar32_lcd.lua b/doc/eluadoc/refman_ps_mizar32_lcd.lua new file mode 100644 index 00000000..b9fcee8b --- /dev/null +++ b/doc/eluadoc/refman_ps_mizar32_lcd.lua @@ -0,0 +1,88 @@ +-- eLaa reference manual - platform data + +data_en = +{ + + -- Title + title = "eLua reference manual - Mizar32 LCD module", + + -- Menu name + menu_name = "lcd", + + -- Overview + overview = [[This module contains functions to drive the two-line character LCD panel of the Mizar32 display module.

    +

    Physically, the display has 16 characters per line but internally it has a 40 characters by two line memory. It displays 16 of those 40 columns at a time, with various ways to determine which of the 40 columns appear in the 16-column display. If you just want to display 16x2 characters, the $reset$, $goto$ and $print$ functions are enough to do this.]], + + -- Functions + funcs = + { + { sig = "#mizar32.lcd.reset#()", + desc = "Initialises the display, resetting everything to as initial state: clear screen, no cursor, displaying columns 1-16 of the 40-column memory, ready to print at (1,1), writing text from left to right and moving the cursor one place right after each character. You don't %have% to call $reset$ at the start of your program, but doing so does will ensure that your program still works if the display has been left in a funny state by some previous run." + }, + + { sig = "#mizar32.lcd.setup#( display_shift, right_to_left )", + desc = "This can be used to set some of the stranger operating modes of the LCD display. Both parameters are optional and if you omit them, they default to $false$, which sets sensible mode.", + args = + { + [[$display_shift$ - If $true$, then with each character you subsequently print, the cursor will move by one place in the character memory as usual but the display's contents will also move by one position horizontally so that the cursor remains in the same column of the physical display. This can be used to achieve "scrolling text" effects. Note, however, that when the cursor passes from column 40 to column 1 or vice versa, it flips over to the other row.]], + "$right_to_left$ - If $true$, text will be printed right-to-left: the cursor will move one position to the left in the character memory and, if display shifting is also enabled, the display will shift so as to keep the cursor in the same column on the screen." + } + }, + + { sig = "#mizar32.lcd.clear#()", + desc = "Clears the display, move the cursor to the top left (position 1,1) and reset the display shift to show columns 1-16." + }, + + { sig = "#mizar32.lcd.home#()", + desc = "Moves the cursor to the top left (position 1,1) and reset the display shift." + }, + + { sig = "#mizar32.lcd.goto#( row, column )", + desc = "Move the cursor to the specified row and column.", + args = + { + "$row$ - A number (1 or 2) giving the row you want to move to.", + "$column$ - A number (1 to 40) giving the position within that row in the character memory." + } + }, + + { sig = "#mizar32.lcd.print#( [data1] [, data2] ... [datan] )", + desc = "Writes into the LCD character memory starting at the current cursor position. The cursor will advance by one position for each character printed. When it goes past column 40, it moves to column 1 of the other line, (and vice versa when printing right-to-left).", + args = + { + "$data$ - Each item of data can be a string or an integer. Strings are the normal way to display messages of ASCII text. An integer parameter should have a value from 0 to 255 to display a single character, which can be one of the user-defined characters 0-7, the regular ASCII characters 32-125 plus 126 and 127 for right- and left-pointing arrows and the chinese, greek and mathematical symbols with codes 160-255." + } + }, + + { sig = "#mizar32.lcd.cursor#( what )", + desc = "Sets the type of cursor that is displayed at the cursor position or move the cursor left or right.", + args = + { + [[$what$ - A string to say what should be done: +

    $"none"$, $"line"$ or $"block"$ will display, respectively, no visible cursor, a constant underline or a blinking solid block at the cursor position. +

    $"left"$ or $"right"$ move the cursor one position left or right in the character memory and on the display without changing the underlying characters. The display never shifts in this case and, as usual, the cursor wraps between column 40 of one row and column 1 of the other.]] + } + }, + + { sig = "#mizar32.lcd.display#( what )", + desc = "Turns the physical display on or off, or shifts the displayed characters left or right.", + args = + { + [[$what$ - A string to say what should be done: +

    $"off"$ and $"on"$ turn the physical display off or back on again. While the display is off it appears blank but the contents of the character memory, the position and type of cursor, user-defined characters and setup mode are all remembered and you can write to the character memory and perform all other operations while the display is off. This allows you to update the display without the viewer seeing too much flickering. +

    $"left"$ or $"right"$ shift the displayed characters one place left or right. For example, if it was displaying the usual columns 1-16 and you say %mizar32.lcd.display("left")%, it will then display columns 2-17: the visible characters move left but the window onto the character memory moves right. ]], + } + }, + + { sig = "#mizar32.lcd.definechar#( code, glyph )", + desc = "Programs one of the eight user-definable characters whose codes are 0 to 7. When it has been defined, a character can be displayed using $mizar32.lcd.print(n)$, where $n$ is a number from 0 to 7. If the character in question is already being displayed, its visible form will change immediately on the display. At power-on, the 8 characters are defined as random garbage.", + args = + { + "$code$ - A number (0 to 7) saying which of the characters you wish to redefine.", + "$glyph$ - A table of up to eight numbers giving the bit-patterns for the eight rows of the character, in order from top to bottom. Each of these number is a value from 0 to 31, to define which of the 5 bits in the row should be black. The pixels' values from left to right are 16, 8, 4, 2 and 1. For example, { 1, 3, 7, 15, 31, 15, 7, 3, 1, 0 } would define a left-pointing solid triangle in the top 7 rows. Extra rows are ignored, and missing rows are blanked." + } + }, + }, +} + +data_pt = data_en diff --git a/doc/eluadoc/refman_ps_str9_pio.lua b/doc/eluadoc/refman_ps_str9_pio.lua index 73a2d936..38a4ddf8 100644 --- a/doc/eluadoc/refman_ps_str9_pio.lua +++ b/doc/eluadoc/refman_ps_str9_pio.lua @@ -10,7 +10,7 @@ data_en = menu_name = "pio", -- Overview - overview = [[This module contains functions for accesing the particular features of the PIO subsystem of the STR9 family of CPUs. This subsystem is very flexible, allowing things like + overview = [[This module contains functions for accessing the particular features of the PIO subsystem of the STR9 family of CPUs. This subsystem is very flexible, allowing things like configurable output types (push-pull or open collector), multiple alternate functions for the PIO pins, and others. For a full description of the STR9 PIO module check the STR9 CPU Reference manual, available from ST at @http://www.st.com/mcu/devicedocs-STR912FAW44-101.html@this address@. Note that this module is a supplement of the platform independent @refman_gen_pio.html@pio@ module, not a replacement. Use this module only for setting up the STR9 PIO pins, and the @refman_gen_pio.html@pio@ module for all the other PIO related operations.]], diff --git a/doc/eluadoc/refman_ps_str9_rtc.lua b/doc/eluadoc/refman_ps_str9_rtc.lua deleted file mode 100644 index 1513cdea..00000000 --- a/doc/eluadoc/refman_ps_str9_rtc.lua +++ /dev/null @@ -1,60 +0,0 @@ --- eLua reference manual - str9 platform specific rtc - Real Time Clock - data - -data_en = -{ - - -- Title - title = "eLua reference manual - STR9 rtc module", - - -- Menu name - menu_name = "rtc", - - -- Overview - overview = [[This module contains functions for accesing the particular features of the RTC - Real Time Clock - subsystem of the STR9 family of CPUs. - This internal subsystem offers functions to keep track of a real time clock calendar, as well as some other features like alarms and auxiliar functions. - Reference manual, available from ST at @http://www.st.com/mcu/devicedocs-STR912FAW44-101.html@this address@.]], - - -- Functions - funcs = - { - { sig = "#str9.rtc.settime#( time )", - desc = "Sets the Real Time Clock time to a specific time of the day.", - args = - { - "$time$ - a string in the format 'hh:mm:ss' or a Lua table with 'hour', 'min' and 'sec' string fields.", - }, - ret = "nothing.", - ex = 'str9.settime("14:25:00") - Sets the RTC time to 14 hour 25 minutes, 2:25 PM', - }, - { sig = "#str9.rtc.gettime#( format )", - desc = "Gets the time kept by the Real Time Clock.", - args = - { - "$format$ - the string '*s' to return the time as a string 'hh:mm:ss' or '*t' to return as a Lua table with string fields 'hour', 'min' and 'sec'.", - }, - ret = "a string or a Lua table, according to the format argument.", - ex = 'now = str9.rtc.gettime( "*s" ) - now receives a sting like "14:25:05", now = str9.rtc.gettime( "*t" ) - now receives the Lua table { hour = 14, min = 25, sec = 05 }', - }, - { sig = "#str9.rtc.setdate#( date )", - desc = "Sets the Real Time Clock date to a specific date.", - args = - { - "$date$ - a string in the format 'dd/mm/yyyy' or a Lua table with 'day', 'month' and 'year' string fields.", - }, - ret = "nothing.", - ex = 'str9.rtc.setdate( "31/08/1960" ) - set the RTC date to August 31st 1960', - }, - { sig = "#str9.rtc.getdate#( format )", - desc = "Gets the date kept by the Real Time Clock.", - args = - { - "$format$ - the string '*s' to return the date as a string 'dd/mm/yyyy' or '*t' to return as a Lua table with string fields 'day', 'month' and 'year'.", - }, - ret = "a string or a Lua table, according to the format argument.", - ex = 'today = str9.rtc.getdate( "*s" ) - today receives a string like "14/12/2010", meaning December 14th of 2010, today = str9.rtc.getdate( "*t" ) - today receives the Lua table { day = 14, month = 12, year = 2010 }', - }, - - }, -} - -data_pt = data_en diff --git a/doc/en/arch_con_term.html b/doc/en/arch_con_term.html index c058cd08..8ad9e55b 100644 --- a/doc/en/arch_con_term.html +++ b/doc/en/arch_con_term.html @@ -15,7 +15,7 @@ typedef void ( *p_std_send_char )( int fd, char c ); typedef int ( *p_std_get_char )( s32 to );

    (the send function gets an additional fd parameter that you can use to differentiate between the standard C stdout and stderr output streams).

    -

    To set them, use std_set_send_func and std_set_get_func, both are defined in inc/newlib/getstd.h. Usually they are called from src/common.c and configured to work +

    To set them, use std_set_send_func and std_set_get_func, both are defined in inc/newlib/genstd.h. Usually they are called from src/common.c and configured to work over the UART by default:

    // *****************************************************************************
 // std functions and platform initialization
diff --git a/doc/en/arch_platform.html b/doc/en/arch_platform.html
index 2ebf02fd..6b727e67 100644
--- a/doc/en/arch_platform.html
+++ b/doc/en/arch_platform.html
@@ -9,7 +9,7 @@ $$HEADER$$
   0, PORTB will have 1 and so on. Similarly, the second SPI interface (SPI1) of the MCU will probably have an id equal to 1. However, this is not a strict
   rule. The implementation of the platform interface might choose to expose only some of the peripherals (components) of the MCU, thus this rule might be 
   broken. For example, if a board has 3 UARTs, but for some reason the second UART (UART1) is dedicated and can't be touched by eLua, then UART0 will have the id 0 and UART2 will
-  have the id 1, so UART1 won't ever be accesible to the code. 
    
+  have the id 1, so UART1 won't ever be accessible to the code. 
    
   
    With some exceptions (most notably the low-level support functions), the different modules supported by the platform interface are 
   mirrored more or less accurately in separate Lua modules that can be used directly from eLua. Check the reference manual for a 
   complete description of these modules.
    
diff --git a/doc/en/arch_rfs.txt b/doc/en/arch_rfs.txt
index 583dba5c..adbb1479 100644
--- a/doc/en/arch_rfs.txt
+++ b/doc/en/arch_rfs.txt
@@ -22,7 +22,7 @@ You need to define the following macros for RFS:
 | RFS_BUFFER_SIZE     | Size of the RFS buffer. Needs to be one of the *BUF_SIZE_xxx* constants defined in _inc/buf.h_
 | RFS_UART_ID         | The ID of the UART that will be used by RFS. This is the physical connection over which the PC directory will be shared.
 | RFS_UART_SPEED      | Communication speed of the RFS UART interface. 
-| RFS_TIMER_ID        | The ID of a timer that will be used by RFS for internal operations
+| RFS_TIMER_ID        | The ID of a timer that will be used by RFS for internal operations. If not specified it defaults to the link:arch_platform_timers.html#the_system_timer[system timer].
 | RFS_FLOW_TYPE       | Flow control type on the serial RFS interface, see link:arch_platform_uart.html#flow_control_type[here] for details. 
 If not specified it defaults to \'no flow control'.
 | RFS_TIMEOUT         | RFS operations timeout (in microseconds). If during a RFS operation no data is received from the PC side for the
diff --git a/doc/en/arch_romfs.html b/doc/en/arch_romfs.html
index e0400ca5..c32489e0 100644
--- a/doc/en/arch_romfs.html
+++ b/doc/en/arch_romfs.html
@@ -68,8 +68,8 @@ $$HEADER$$
   (see     here for details on cross compilation and its benefits) and the result is written in the eLua binary image. This option
   might decrease or increase the physical size of the ROMFS image, but its real benefits are increased speed (because eLua doesn't need to compile the Lua
   code to bytecode first) and decreased RAM consumption (the Lua parser might get quite memory-hungry at times, which in turn might lead to stack overflows and very
-  hard to find bugs). 
+  hard to find bugs). NOTE: this option is not available if eLua is compiled in 64-bit integer only mode (lualonglong).
 
 
    See here for instructions on how to specify the ROMFS compilation mode.
    
 $$FOOTER$$
- 
\ No newline at end of file
+ 
diff --git a/doc/en/arch_tcpip.html b/doc/en/arch_tcpip.html
index ce975d0a..ec3e1f05 100644
--- a/doc/en/arch_tcpip.html
+++ b/doc/en/arch_tcpip.html
@@ -31,7 +31,7 @@ stack. These are the services provided by the TCP/IP stack:
    
   be used instead. To use only the static configuration (and make the eLua image
   size a bit smaller) don't define the BUILD_DHCPC client.
    
 
-
  • #define BUILD_DNSM if you want support for the DNS server.
    • 
+
  • #define BUILD_DNS if you want support for the DNS server.
    • 
 
  • #define BUILD_CON_TCP if you want support for shell over telnet instead of
    serial. Note that you must NOT define BUILD_CON_GENERIC in this case (see
    here for details).
    • 
@@ -48,8 +48,8 @@ you have a list of parameters that you might want to change:
    
     but doing so when you have to transfer large amounts of data will slow the transfer speed. 1k seems to be a good compromise.
   
  • UIP_CONF_UDP: turn off UDP support. While eLua doesn't have support for UDP via its net module at this time, UDP can still
     be used (for example by DNS/DHCP), so be careful if you disable this.
    • 
-  
  • ELUA_DHCP_TIMER_ID: the timer ID used for the TCP/IP subsystem. Note that this should be a dedicated timer, not available to the rest 
-    of the system (or available in "read-only" mode).
    • 
+  
  • ELUA_DHCP_TIMER_ID: the timer ID used for the TCP/IP subsystem. If not specified it defaults to the link:arch_platform_timers.html#the_system_timer[system timer].
+    If the system timer is not used, please note that this should be a dedicated timer, not available to the rest of the system (or available in "read-only" mode). 
    • 
 
 
    
 
diff --git a/doc/en/asciidoc.conf b/doc/en/asciidoc.conf
index ca100c16..ca597de5 100644
--- a/doc/en/asciidoc.conf
+++ b/doc/en/asciidoc.conf
@@ -101,3 +101,5 @@ _mmbedpio=link:refman_ps_mbed_pio.html[mbed.pio]
 
 # Miscellaneous
 _br=
    
+_systmr=link:arch_platform_timers.html#the_system_timer[system timer]
+_virttmr=link:arch_platform_timers.html#virtual_timers[virtual timers]
diff --git a/doc/en/building.txt b/doc/en/building.txt
index 10c10cbc..39178df3 100644
--- a/doc/en/building.txt
+++ b/doc/en/building.txt
@@ -76,7 +76,7 @@ o|BUILD_MMCFS       |Enable the eLua SD/MMC FAT filesystem support. To enable:
 
   #define BUILD_MMCFS
 
-xref:static[Static configuration data dependencies]: *MMCFS_TICK_HZ, MMCFS_TICK_MS, MMCFS_CS_PORT, MMCFS_CS_PIN, MMCFS_SPI_NUM*
+xref:static[Static configuration data dependencies]: *MMCFS_CS_PORT, MMCFS_CS_PIN, MMCFS_SPI_NUM*
 
 o|BUILD_TERM        |Enable ANSI terminal support. It allows eLua to interact with terminals that support ANSI escape sequences 
 (more details link:arch_con_term.html[here]). Currently it works only over RS-232 connections, although this is not a strict requirement. 
@@ -210,7 +210,8 @@ o|CON_UART_ID +
 CON_UART_SPEED +
 CON_TIMER_ID +
 CON_FLOW_TYPE       |Used to configure console input/output over UART. The specified UART id will be used for console input/output, at the
-specified speed. The data format is always 8N1 (8 data bits, no parity, 1 stop bits)t. The specified timer ID will be used for the console subsystem. These
+specified speed. The data format is always 8N1 (8 data bits, no parity, 1 stop bits)t. The specified timer ID will be used for the console subsystem (if
+not specified it defaults to the link:arch_platform_timers.html#the_system_timer[system timer]). These
 variables are also used by the XMODEM and TERM implementations. If CON_FLOW_TYPE is defined the specified flow control is applied to the console UART
 interface (see link:arch_platform_uart.html#platform_uart_set_flow_control[this link] to find out how to specify the flow control). If not defined it
 defaults to no flow control.
@@ -229,10 +230,6 @@ o|VTMR_NUM_TIMERS +
 VTMR_FREQ_HZ       |Specify the virtual timers configuration for the platform (refer to link:refman_gen_tmr.html[the timer module documentation] for details). Define VTMR_NUM_TIMERS to 0 
 if this feature is not used.
 
-o|MMCFS_TICK_HZ +
-MMCFS_TICK_MS      |Specify the rate at which SD/MMC timer function _disk_timerproc()_ are being called by the platform. On most platforms MMCFS_TICK_HZ will match VTMR_FREQ_HZ.  
-Only needed if MMCFS support is enabled.
-
 o|MMCFS_CS_PORT +
 MMCFS_CS_PIN       |Specify the port and pin to be used as chip select for MMCFS control of an SD/MMC card over SPI. Only needed if MMCFS support is enabled.
 
@@ -265,6 +262,7 @@ value that can be returned by the ADC.
 o|RPC_UART_ID       |If the link:refman_gen_rpc.html[rpc module] is enabled and boot mode is set to luarpc, this selects which uart luarpc will listen on for incoming client connections.
 
 o|RPC_TIMER_ID      |If the link:refman_gen_rpc.html[rpc module] is enabled and boot mode is set to luarpc, this selects which timer will be used with the uart selected with RPC_UART_ID.
+If not specified it defaults to the link:arch_platform_timers.html#the_system_timer[system timer].
 
 o|EGC_INITIAL_MODE +
 EGC_INITIAL_MEMLIMIT |**(version 0.7 or above)**Configure the default (compile time) operation mode and memory limit of the emergency garbage collector link:elua_egc.html[here] for details
@@ -284,7 +282,7 @@ by this macro. Check link:linenoise.html[here] for details. This macro is option
 o|RFS_BUFFER_SIZE     |Size of the RFS buffer. Needs to be one of the *BUF_SIZE_xxx* constants defined in _inc/buf.h_
 o|RFS_UART_ID         |The ID of the UART that will be used by RFS. This is the physical connection over which the PC directory will be shared.
 o|RFS_UART_SPEED      |Communication speed of the RFS UART interface. 
-o|RFS_TIMER_ID        |The ID of a timer that will be used by RFS for internal operations
+o|RFS_TIMER_ID        |The ID of a timer that will be used by RFS for internal operations. If not specified it defaults to the link:arch_platform_timers.html#the_system_timer[system timer].
 o|RFS_FLOW_TYPE       |Flow control type on the serial RFS interface, see link:arch_platform_uart.html#flow_control_type[here] for details. 
 If not specified it defaults to \'no flow control'.
 o|RFS_TIMEOUT         |RFS operations timeout (in microseconds). If during a RFS operation no data is received from the PC side for the
@@ -315,7 +313,7 @@ to modify them, so don't worry about the apparent complexity. The examples at th
 
 ------------------------------------
 $ scons
-  [target=lua | lualong]
+  [target=lua | lualong | lualonglong]
   [cpu=]
   [board=]
   [cpumode=arm | thumb]
@@ -336,8 +334,9 @@ one CPU. This allows the build system to be very flexible. You can use these two
 For board/CPU assignment, look at the beginning of the SConstruct file (the _platform_list_), it's self-explanatory. +
 The other options are as follows:
 
-* **target=lua | lualong**: specify if you want to build "regular" Lua (with floating point support) or integer only Lua (lualong). The default is "lua". "lualong" runs faster on
-  targets that don't have a floating point co-processor, but it completely lacks support for floating point operations, it can only handle integers.
+* **target=lua | lualong | lualonglong**: specify if you want to build "regular" Lua (with floating point support). 32 bit integer only Lua (lualong) or 64 bit integer only Lua (lualonglong,
+  starting with version 0.9).  The default is "lua". "lualong" and "lualonglong" run faster on targets that don't have a floating point co-processor, but they completely lack support for floating 
+  point operations, they can only handle integers. Also, "lualonglong" doesn't support cross-compilation of Lua source files to bytecode (check link:arch_romfs.html#mode[here] for details).
 
 * **cpumode=arm | thumb**: for ARM targets (not Cortex) this specifies the compilation mode. Its default value is 'thumb' for AT91SAM7X targets and 'arm' for STR9, LPC2888 and LPC2468 targets.
 
diff --git a/doc/en/filesystems.html b/doc/en/filesystems.html
index b50fa829..43367d89 100644
--- a/doc/en/filesystems.html
+++ b/doc/en/filesystems.html
@@ -5,7 +5,7 @@ $$HEADER$$
   
  • the ROM file system: a very simple, very low footprint read-only file system that can be included in the eLua binary image. Check here for details.
    • 
   
  • the FAT file system: a read-write FAT file system implementation (platform independent) that can currently be used with SD/MMC memory cards. Check here for 
   details. (new in 0.7)
    • 
-  
  • the remote file system (RFS): a read-write file system that allows eLua to 'share' a directory on a PC, effectively accesing
+  
  • the remote file system (RFS): a read-write file system that allows eLua to 'share' a directory on a PC, effectively accessing
   its contents as if it was a local file system. Check here for details. (new in 0.8)
    •   
 
 $$FOOTER$$
diff --git a/doc/en/modules_mizar32.txt b/doc/en/modules_mizar32.txt
new file mode 100644
index 00000000..526f4b90
--- /dev/null
+++ b/doc/en/modules_mizar32.txt
@@ -0,0 +1,5 @@
+$$HEADER$$
+
    Reference manual - Mizar32 platform dependent modules
    
+
    This paragraph presents all the modules specific to the Mizar32 platform.
    
+$$FOOTER$$
+
diff --git a/doc/en/sermux.txt b/doc/en/sermux.txt
index 3f5f8a79..56062a71 100644
--- a/doc/en/sermux.txt
+++ b/doc/en/sermux.txt
@@ -59,7 +59,7 @@ install it, then open the com0com serial port manager to create your virtual
 serial port pairs. Then give it a little spin to get used to how it works. Supposing
 that you created COM10 and COM11 as a virtual serial port pair, try this:
 
-- start your terminal emulator program. My preffered terminal emulator program in 
+- start your terminal emulator program. My preferred terminal emulator program in 
   Windows is http://www.ayera.com/teraterm/[TeraTerm], but you can use any emulator 
   you want. Open COM10 at baud 115200.
 - start another instance of the terminal emulator, but this time open COM11 at baud 115200.
diff --git a/doc/en/status.txt b/doc/en/status.txt
index 56ff447b..d9a39c38 100644
--- a/doc/en/status.txt
+++ b/doc/en/status.txt
@@ -43,6 +43,27 @@ The list of CPUs and boards currently supported by eLua is given below:
 | _I386          |  x86          o|    i386               |  PCs/emulators    | _sok
 |=====================================================================================
 
+[[systmr]]
+System timer support
+--------------------
+The table below shows the status of _systmr implementation on all eLua platforms.
+
+[width="70%", cols="<1, ^4", options="header"]
+|============================================
+^| Platform          ^| System timer support 
+| AT91SAM7x          o| yes
+| AVR32              o| yes
+| i386               o| no
+| LM3S               o| yes
+| LPC17xx            o| yes
+| LPC24xx            o| yes
+| LPC288x            o| no
+| SIM                o| yes
+| STM32              o| yes
+| STR7               o| no
+| STR9               o| yes
+|============================================
+
 [[plat_modules]]
 eLua modules x MCUs
 -------------------
diff --git a/inc/common.h b/inc/common.h
index e6479535..9aebffe7 100644
--- a/inc/common.h
+++ b/inc/common.h
@@ -4,9 +4,12 @@
 #define __COMMON_H__
 
 #include "elua_int.h"
+#include "lua.h"
+#include "platform.h"
 
 // Virtual timers data
-#define VTMR_FIRST_ID           ( 32 )
+// VTMR_FIRST_ID must be LARGER than PLATFORM_TIMER_SYS_ID (as declared in platform.h)
+#define VTMR_FIRST_ID           ( 0x200 )
 #define VTMR_GET_ID( x )        ( ( x ) - VTMR_FIRST_ID )
 #define TIMER_IS_VIRTUAL( x )   ( ( VTMR_NUM_TIMERS > 0 ) && ( ( x ) >= VTMR_FIRST_ID ) && ( ( x ) < VTMR_NUM_TIMERS + VTMR_FIRST_ID ) )
 
@@ -18,9 +21,18 @@ void cmn_int_handler( elua_int_id id, elua_int_resnum resnum );
 int cmn_tmr_int_set_status( elua_int_resnum resnum, int status );
 int cmn_tmr_int_get_status( elua_int_resnum resnum );
 int cmn_tmr_int_get_flag( elua_int_resnum resnum, int clear );
+// System timer generic implemenation
+void cmn_systimer_set_base_freq( u32 freq_hz );
+void cmn_systimer_set_interrupt_freq( u32 freq_hz );
+void cmn_systimer_set_interrupt_period_us( u32 period );
+void cmn_systimer_periodic();
+timer_data_type cmn_systimer_get();
+
 void cmn_uart_setup_sermux();
 
 unsigned int intlog2( unsigned int v );
+const char* cmn_str64( u64 x );
+void cmn_get_timeout_data( lua_State *L, int pidx, timer_data_type *ptimeout, unsigned *pid );
 
 #endif // #ifndef __COMMON_H__
 
diff --git a/inc/desktop/platform_conf.h b/inc/desktop/platform_conf.h
index fd2b631f..0a379aab 100644
--- a/inc/desktop/platform_conf.h
+++ b/inc/desktop/platform_conf.h
@@ -9,6 +9,9 @@
 #define BUILD_RPC
 #define LUARPC_ENABLE_SERIAL
 
+#define LUA_PLATFORM_LIBS_REG \
+  {LUA_OSLIBNAME, luaopen_os}
+
 #define LUA_PLATFORM_LIBS_ROM \
   _ROM( AUXLIB_RPC, luaopen_rpc, rpc_map )\
   _ROM( AUXLIB_BITARRAY, luaopen_bitarray, bitarray_map )\
diff --git a/inc/elua_net.h b/inc/elua_net.h
index 28b5fb12..96db308b 100644
--- a/inc/elua_net.h
+++ b/inc/elua_net.h
@@ -5,6 +5,7 @@
 
 #include "type.h"
 #include "lauxlib.h"
+#include "platform.h"
 
 // eLua network typedefs
 typedef s16 elua_net_size;
@@ -40,10 +41,10 @@ typedef union
 // eLua TCP/IP functions
 int elua_net_socket( int type );
 int elua_net_close( int s );
-elua_net_size elua_net_recvbuf( int s, luaL_Buffer *buf, elua_net_size maxsize, s16 readto, unsigned timer_id, u32 to_us );
-elua_net_size elua_net_recv( int s, void *buf, elua_net_size maxsize, s16 readto, unsigned timer_id, u32 to_us );
+elua_net_size elua_net_recvbuf( int s, luaL_Buffer *buf, elua_net_size maxsize, s16 readto, unsigned timer_id, timer_data_type to_us );
+elua_net_size elua_net_recv( int s, void *buf, elua_net_size maxsize, s16 readto, unsigned timer_id, timer_data_type to_us );
 elua_net_size elua_net_send( int s, const void* buf, elua_net_size len );
-int elua_accept( u16 port, unsigned timer_id, u32 to_us, elua_net_ip* pfrom );
+int elua_accept( u16 port, unsigned timer_id, timer_data_type to_us, elua_net_ip* pfrom );
 int elua_net_connect( int s, elua_net_ip addr, u16 port );
 elua_net_ip elua_net_lookup( const char* hostname );
 
diff --git a/inc/eluarpc.h b/inc/eluarpc.h
index 83aa0a20..8c4fc0da 100644
--- a/inc/eluarpc.h
+++ b/inc/eluarpc.h
@@ -1,65 +1,65 @@
-// Lightweight remote procedure call layer
-
-#ifndef __ELUARPC_H__
-#define __ELUARPC_H__
-
-#include "type.h"
-
-#define   PACKET_SIG          0x18AFC284UL
-
-// Error codes
-#define   ELUARPC_OK          0
-#define   ELUARPC_ERR         1
-
-#define   ELUARPC_OP_RES_MOD  0x80
-
-// Protocol constants
-#define   ELUARPC_START_OFFSET    4
-#define   ELUARPC_START_SIZE      6
-#define   ELUARPC_END_SIZE        6
-#define   ELUARPC_RESPONSE_SIZE   1
-#define   ELUARPC_PTR_HEADER_SIZE 6
-#define   ELUARPC_SMALL_PTR_HEADER_SIZE 4
-#define   ELUARPC_U32_SIZE        5
-#define   ELUARPC_U16_SIZE        3
-#define   ELUARPC_U8_SIZE         2
-#define   ELUARPC_OP_ID_SIZE      2
-#define   ELUARPC_READ_BUF_OFFSET ( ELUARPC_START_OFFSET + ELUARPC_START_SIZE + ELUARPC_RESPONSE_SIZE + ELUARPC_PTR_HEADER_SIZE )
-#define   ELUARPC_SMALL_READ_BUF_OFFSET ( ELUARPC_START_OFFSET + ELUARPC_START_SIZE + ELUARPC_RESPONSE_SIZE + ELUARPC_SMALL_PTR_HEADER_SIZE )
-#define   ELUARPC_WRITE_REQUEST_EXTRA ( ELUARPC_START_OFFSET + ELUARPC_START_SIZE + ELUARPC_OP_ID_SIZE + ELUARPC_U32_SIZE + ELUARPC_PTR_HEADER_SIZE + ELUARPC_END_SIZE )
-
-// Public interface
-// Get request ID
-int eluarpc_get_request_id( const u8 *p, u8 *pid );
-
-// Replace a flag with another flag
-u32 eluarpc_replace_flag( u32 val, u32 origflag, u32 newflag );
-
-// Get packet size
-int eluarpc_get_packet_size( const u8 *p, u16 *psize );
-
-// Generic write function
-// Specifiers: o - operation
-//             r - response
-//             c - u8
-//             h - u16
-//             l - u32
-//             i - int
-//             L - s32
-//             p - ptr (given as ptr, len, len is an u32)
-//             P - ptr (given as ptr, len, len is an u16)
-void eluarpc_gen_write( u8 *p, const char *fmt, ... );
-
-// Generic read function
-// Specifiers: o - operation
-//             r - response
-//             c - u8
-//             h - u16
-//             l - u32
-//             L - s32
-//             i - int
-//             p - ptr (returned as ptr, len, len is an u32)
-//             P - ptr (returned as ptr, len, len is an u16)
-int eluarpc_gen_read( const u8 *p, const char *fmt, ... );
-
-#endif
+// Lightweight remote procedure call layer
+
+#ifndef __ELUARPC_H__
+#define __ELUARPC_H__
+
+#include "type.h"
+
+#define   PACKET_SIG          0x18AFC284UL
+
+// Error codes
+#define   ELUARPC_OK          0
+#define   ELUARPC_ERR         1
+
+#define   ELUARPC_OP_RES_MOD  0x80
+
+// Protocol constants
+#define   ELUARPC_START_OFFSET    4
+#define   ELUARPC_START_SIZE      6
+#define   ELUARPC_END_SIZE        6
+#define   ELUARPC_RESPONSE_SIZE   1
+#define   ELUARPC_PTR_HEADER_SIZE 6
+#define   ELUARPC_SMALL_PTR_HEADER_SIZE 4
+#define   ELUARPC_U32_SIZE        5
+#define   ELUARPC_U16_SIZE        3
+#define   ELUARPC_U8_SIZE         2
+#define   ELUARPC_OP_ID_SIZE      2
+#define   ELUARPC_READ_BUF_OFFSET ( ELUARPC_START_OFFSET + ELUARPC_START_SIZE + ELUARPC_RESPONSE_SIZE + ELUARPC_PTR_HEADER_SIZE )
+#define   ELUARPC_SMALL_READ_BUF_OFFSET ( ELUARPC_START_OFFSET + ELUARPC_START_SIZE + ELUARPC_RESPONSE_SIZE + ELUARPC_SMALL_PTR_HEADER_SIZE )
+#define   ELUARPC_WRITE_REQUEST_EXTRA ( ELUARPC_START_OFFSET + ELUARPC_START_SIZE + ELUARPC_OP_ID_SIZE + ELUARPC_U32_SIZE + ELUARPC_PTR_HEADER_SIZE + ELUARPC_END_SIZE )
+
+// Public interface
+// Get request ID
+int eluarpc_get_request_id( const u8 *p, u8 *pid );
+
+// Replace a flag with another flag
+u32 eluarpc_replace_flag( u32 val, u32 origflag, u32 newflag );
+
+// Get packet size
+int eluarpc_get_packet_size( const u8 *p, u16 *psize );
+
+// Generic write function
+// Specifiers: o - operation
+//             r - response
+//             c - u8
+//             h - u16
+//             l - u32
+//             i - int
+//             L - s32
+//             p - ptr (given as ptr, len, len is an u32)
+//             P - ptr (given as ptr, len, len is an u16)
+void eluarpc_gen_write( u8 *p, const char *fmt, ... );
+
+// Generic read function
+// Specifiers: o - operation
+//             r - response
+//             c - u8
+//             h - u16
+//             l - u32
+//             L - s32
+//             i - int
+//             p - ptr (returned as ptr, len, len is an u32)
+//             P - ptr (returned as ptr, len, len is an u16)
+int eluarpc_gen_read( const u8 *p, const char *fmt, ... );
+
+#endif
diff --git a/inc/linenoise_posix.h b/inc/linenoise_posix.h
new file mode 100644
index 00000000..15f2a31e
--- /dev/null
+++ b/inc/linenoise_posix.h
@@ -0,0 +1,56 @@
+/* linenoise.h -- guerrilla line editing library against the idea that a
+ * line editing lib needs to be 20,000 lines of C code.
+ *
+ * See linenoise.c for more information.
+ *
+ * ------------------------------------------------------------------------
+ *
+ * Copyright (c) 2010, Salvatore Sanfilippo 
+ * Copyright (c) 2010, Pieter Noordhuis 
+ *
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * 
+ *  *  Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *  *  Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in the
+ *     documentation and/or other materials provided with the distribution.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __LINENOISE_H
+#define __LINENOISE_H
+
+typedef struct linenoiseCompletions {
+  size_t len;
+  char **cvec;
+} linenoiseCompletions;
+
+typedef void(linenoiseCompletionCallback)(const char *, linenoiseCompletions *);
+void linenoiseSetCompletionCallback(linenoiseCompletionCallback *);
+void linenoiseAddCompletion(linenoiseCompletions *, char *);
+
+char *linenoise(const char *prompt);
+int linenoiseHistoryAdd(const char *line);
+int linenoiseHistorySetMaxLen(int len);
+int linenoiseHistorySave(char *filename);
+int linenoiseHistoryLoad(char *filename);
+void linenoiseClearScreen(void);
+
+#endif /* __LINENOISE_H */
diff --git a/inc/luarpc_rpc.h b/inc/luarpc_rpc.h
index c84ab3af..c38c4c28 100644
--- a/inc/luarpc_rpc.h
+++ b/inc/luarpc_rpc.h
@@ -67,7 +67,7 @@ enum exception_type { done, nonfatal, fatal };
 
 struct exception {
   enum exception_type type;
-	int errnum;
+  int errnum;
 };
 
 define_exception_type(struct exception);
@@ -113,7 +113,7 @@ typedef struct _ServerHandle ServerHandle;
 struct _ServerHandle {
   Transport ltpt;   // listening transport, always valid if no error
   Transport atpt;   // accepting transport, valid if connection established
-	int link_errs;
+  int link_errs;
 };
 
 
@@ -125,12 +125,12 @@ struct _ServerHandle {
 #endif
 
 #define TRANSPORT_VERIFY_OPEN \
-	if (tpt->fd == INVALID_TRANSPORT) \
-	{ \
-		e.errnum = ERR_CLOSED; \
-		e.type = fatal; \
-		Throw( e ); \
-	}
+  if (tpt->fd == INVALID_TRANSPORT) \
+  { \
+    e.errnum = ERR_CLOSED; \
+    e.type = fatal; \
+    Throw( e ); \
+  }
 
 // Arg & Error Checking Provided to Transport Mechanisms 
 int check_num_args (lua_State *L, int desired_n);
@@ -156,11 +156,11 @@ void transport_read_buffer (Transport *tpt, u8 *buffer, int length);
 void transport_write_buffer (Transport *tpt, const u8 *buffer, int length);
 
 // Check if data is available on connection without reading:
-// 		- 1 = data available, 0 = no data available
+//     - 1 = data available, 0 = no data available
 int transport_readable (Transport *tpt);
 
 // Check if transport is open:
-//		- 1 = connection open, 0 = connection closed
+//    - 1 = connection open, 0 = connection closed
 int transport_is_open (Transport *tpt);
 
 // Shut down connection
diff --git a/inc/newlib/genstd.h b/inc/newlib/genstd.h
index 0c0d2816..5adfade7 100644
--- a/inc/newlib/genstd.h
+++ b/inc/newlib/genstd.h
@@ -10,12 +10,12 @@
 // STD device name (for devman)
 #define STD_DEV_NAME         "/std"
 
-#define STD_INFINITE_TIMEOUT    PLATFORM_UART_INFINITE_TIMEOUT
+#define STD_INFINITE_TIMEOUT    PLATFORM_TIMER_INF_TIMEOUT
 #define STD_INTER_CHAR_TIMEOUT  10000
 
 // Send/receive function types
 typedef void ( *p_std_send_char )( int fd, char c );
-typedef int ( *p_std_get_char )( s32 to );
+typedef int ( *p_std_get_char )( timer_data_type to );
 
 // STD functions
 void std_set_send_func( p_std_send_char pfunc );
diff --git a/inc/platform.h b/inc/platform.h
index 86727db8..b2217987 100644
--- a/inc/platform.h
+++ b/inc/platform.h
@@ -68,6 +68,77 @@ const char* platform_pio_get_prefix( unsigned port );
 int platform_pio_has_pin( unsigned port, unsigned pin );
 pio_type platform_pio_op( unsigned port, pio_type pinmask, int op );
 
+// *****************************************************************************
+// Timer subsection
+
+// The ID of the system timer
+#define PLATFORM_TIMER_SYS_ID                 0x100
+
+#if defined( LUA_NUMBER_INTEGRAL ) && !defined( LUA_INTEGRAL_LONGLONG )
+// Maximum values of the system timer
+#define PLATFORM_TIMER_SYS_MAX                ( ( 1LL << 32 ) - 2 )
+// Timer data type
+typedef u32 timer_data_type;
+#else
+// Maximum values of the system timer
+#define PLATFORM_TIMER_SYS_MAX                ( ( 1LL << 52 ) - 2 )
+// Timer data type
+typedef u64 timer_data_type;
+#endif // #if defined( LUA_NUMBER_INTEGRAL ) && !defined( LUA_INTEGRAL_LONGLONG )
+
+// This constant means 'infinite timeout'
+#define PLATFORM_TIMER_INF_TIMEOUT            ( PLATFORM_TIMER_SYS_MAX + 1 )
+
+// System timer frequency
+#define PLATFORM_TIMER_SYS_FREQ               1000000
+
+// Interrupt types
+#define PLATFORM_TIMER_INT_ONESHOT            1
+#define PLATFORM_TIMER_INT_CYCLIC             2
+
+// Match interrupt error codes
+#define PLATFORM_TIMER_INT_OK                 0
+#define PLATFORM_TIMER_INT_TOO_SHORT          1
+#define PLATFORM_TIMER_INT_TOO_LONG           2
+#define PLATFORM_TIMER_INT_INVALID_ID         3
+
+// Timer operations
+enum
+{
+  PLATFORM_TIMER_OP_START,
+  PLATFORM_TIMER_OP_READ,
+  PLATFORM_TIMER_OP_SET_CLOCK,
+  PLATFORM_TIMER_OP_GET_CLOCK,
+  PLATFORM_TIMER_OP_GET_MAX_DELAY,
+  PLATFORM_TIMER_OP_GET_MIN_DELAY,
+  PLATFORM_TIMER_OP_GET_MAX_CNT
+};
+
+// The platform timer functions
+int platform_timer_exists( unsigned id );
+void platform_timer_delay( unsigned id, timer_data_type delay_us );
+void platform_s_timer_delay( unsigned id, timer_data_type delay_us );
+timer_data_type platform_timer_op( unsigned id, int op, timer_data_type data );
+timer_data_type platform_s_timer_op( unsigned id, int op, timer_data_type data );
+int platform_timer_set_match_int( unsigned id, timer_data_type period_us, int type );
+int platform_s_timer_set_match_int( unsigned id, timer_data_type period_us, int type );
+timer_data_type platform_timer_get_diff_us( unsigned id, timer_data_type end, timer_data_type start );
+// System timer functions
+timer_data_type platform_timer_read_sys();
+int platform_timer_sys_available();
+// The next 3 functions need to be implemented only if the generic system timer mechanism
+// (src/common.c:cmn_systimer*) is used by the backend
+u64 platform_timer_sys_raw_read();
+void platform_timer_sys_enable_int();
+void platform_timer_sys_disable_int();
+
+// Convenience macros
+#define platform_timer_read( id )             platform_timer_op( id, PLATFORM_TIMER_OP_READ, 0 )
+#define platform_timer_start( id )            platform_timer_op( id, PLATFORM_TIMER_OP_START, 0 )
+#define platform_timer_get_diff_crt( id, v )  platform_timer_get_diff_us( id, platform_timer_read( id ), v )
+#define platform_timer_sys_delay( us )        platform_timer_delay( PLATFORM_TIMER_SYS_ID, us )
+#define platform_timer_get_max_cnt( id )      platform_timer_op( id, PLATFORM_TIMER_OP_GET_MAX_CNT, 0 )
+
 // *****************************************************************************
 // CAN subsection
 
@@ -133,9 +204,6 @@ enum
   PLATFORM_UART_STOPBITS_2
 };
 
-// "Infinite timeout" constant for recv
-#define PLATFORM_UART_INFINITE_TIMEOUT        (-1)
-
 // Flow control types (this is a bit mask, one can specify PLATFORM_UART_FLOW_RTS | PLATFORM_UART_FLOW_CTS )
 #define PLATFORM_UART_FLOW_NONE               0
 #define PLATFORM_UART_FLOW_RTS                1
@@ -147,70 +215,24 @@ u32 platform_uart_setup( unsigned id, u32 baud, int databits, int parity, int st
 int platform_uart_set_buffer( unsigned id, unsigned size );
 void platform_uart_send( unsigned id, u8 data );
 void platform_s_uart_send( unsigned id, u8 data );
-int platform_uart_recv( unsigned id, unsigned timer_id, s32 timeout );
-int platform_s_uart_recv( unsigned id, s32 timeout );
+int platform_uart_recv( unsigned id, unsigned timer_id, timer_data_type timeout );
+int platform_s_uart_recv( unsigned id, timer_data_type timeout );
 int platform_uart_set_flow_control( unsigned id, int type );
 int platform_s_uart_set_flow_control( unsigned id, int type );
 
-// *****************************************************************************
-// Timer subsection
-
-// There are 16 "virtual" timers (TMR0...TMR15)
-#define PLATFORM_TIMER_TOTAL                  16
-
-// Data types
-typedef u32 timer_data_type;
-
-// Interrupt types
-#define PLATFORM_TIMER_INT_ONESHOT            1
-#define PLATFORM_TIMER_INT_CYCLIC             2
-
-// Match interrupt error codes
-#define PLATFORM_TIMER_INT_OK                 0
-#define PLATFORM_TIMER_INT_TOO_SHORT          1
-#define PLATFORM_TIMER_INT_TOO_LONG           2
-#define PLATFORM_TIMER_INT_INVALID_ID         3  
-
-// Timer operations
-enum
-{
-  PLATFORM_TIMER_OP_START,
-  PLATFORM_TIMER_OP_READ,
-  PLATFORM_TIMER_OP_SET_CLOCK,
-  PLATFORM_TIMER_OP_GET_CLOCK,
-  PLATFORM_TIMER_OP_GET_MAX_DELAY,
-  PLATFORM_TIMER_OP_GET_MIN_DELAY
-};
-
-// The platform timer functions
-int platform_timer_exists( unsigned id );
-void platform_timer_delay( unsigned id, u32 delay_us );
-void platform_s_timer_delay( unsigned id, u32 delay_us );
-u32 platform_timer_op( unsigned id, int op, u32 data );
-u32 platform_s_timer_op( unsigned id, int op, u32 data );
-int platform_timer_set_match_int( unsigned id, u32 period_us, int type );
-int platform_s_timer_set_match_int( unsigned id, u32 period_us, int type );
-u32 platform_timer_get_diff_us( unsigned id, timer_data_type end, timer_data_type start );
-
 // *****************************************************************************
 // PWM subsection
 
 // There are 16 "virtual" PWM channels (PWM0...PWM15)
 #define PLATFORM_PWM_TOTAL                    16
 
-// PWM operations
-enum
-{
-  PLATFORM_PWM_OP_START,
-  PLATFORM_PWM_OP_STOP,
-  PLATFORM_PWM_OP_SET_CLOCK,
-  PLATFORM_PWM_OP_GET_CLOCK
-};
-
 // The platform PWM functions
 int platform_pwm_exists( unsigned id );
 u32 platform_pwm_setup( unsigned id, u32 frequency, unsigned duty );
-u32 platform_pwm_op( unsigned id, int op, u32 data );
+void platform_pwm_start( unsigned id );
+void platform_pwm_stop( unsigned id );
+u32 platform_pwm_set_clock( unsigned id, u32 data );
+u32 platform_pwm_get_clock( unsigned id );
 
 // *****************************************************************************
 // CPU specific functions
@@ -235,27 +257,21 @@ u32 platform_cpu_get_frequency();
 // *****************************************************************************
 // The platform ADC functions
 
-enum
-{
-  PLATFORM_ADC_GET_MAXVAL,
-  PLATFORM_ADC_SET_SMOOTHING,
-  PLATFORM_ADC_SET_BLOCKING,
-  PLATFORM_ADC_SET_FREERUNNING,
-  PLATFORM_ADC_IS_DONE,
-  PLATFORM_ADC_OP_SET_TIMER,
-  PLATFORM_ADC_OP_SET_CLOCK,
-};
-
 // Functions requiring platform-specific implementation
-int platform_adc_update_sequence();
-int platform_adc_start_sequence();
+int  platform_adc_update_sequence();
+int  platform_adc_start_sequence();
 void platform_adc_stop( unsigned id );
-u32 platform_adc_setclock( unsigned id, u32 frequency);
+u32  platform_adc_set_clock( unsigned id, u32 frequency);
+int  platform_adc_check_timer_id( unsigned id, unsigned timer_id );
 
 // ADC Common Functions
-int platform_adc_exists( unsigned id );
-int platform_adc_check_timer_id( unsigned id, unsigned timer_id );
-u32 platform_adc_op( unsigned id, int op, u32 data );
+int  platform_adc_exists( unsigned id );
+u32  platform_adc_get_maxval( unsigned id );
+u32  platform_adc_set_smoothing( unsigned id, u32 length );
+void platform_adc_set_blocking( unsigned id, u32 mode );
+void platform_adc_set_freerunning( unsigned id, u32 mode );
+u32  platform_adc_is_done( unsigned id );
+void platform_adc_set_timer( unsigned id, u32 timer );
 
 // *****************************************************************************
 // I2C platform interface
@@ -290,10 +306,22 @@ u32 platform_eth_get_packet_nb( void* buf, u32 maxlen );
 void platform_eth_force_interrupt();
 u32 platform_eth_get_elapsed_time();
 
+// *****************************************************************************
+// USB platform interface
+// NOTE: for now this just supports CDC functionality
+
+#define CDC_UART_ID     0xB0
+
+void platform_usb_cdc_send( u8 data );
+int platform_usb_cdc_recv( s32 timeout );
+
+
+
 // *****************************************************************************
 // Allocator support
 
 void* platform_get_first_free_ram( unsigned id );
 void* platform_get_last_free_ram( unsigned id );
 
+
 #endif
diff --git a/inc/remotefs/client.h b/inc/remotefs/client.h
index 7bd67f59..f647e31f 100644
--- a/inc/remotefs/client.h
+++ b/inc/remotefs/client.h
@@ -4,6 +4,7 @@
 #define __CLIENT_H__
 
 #include "type.h"
+#include "platform.h"
 
 // Error codes
 #define CLIENT_OK   0
@@ -11,11 +12,11 @@
 
 // RFS client send/receive functions
 typedef u32 ( *p_rfsc_send )( const u8 *p, u32 size );
-typedef u32 ( *p_rfsc_recv )( u8 *p, u32 size, s32 timeout );
+typedef u32 ( *p_rfsc_recv )( u8 *p, u32 size, timer_data_type timeout );
 
 // Public interface
-void rfsc_setup( u8 *pbuf, p_rfsc_send rfsc_send_func, p_rfsc_recv rfsc_recv_func, u32 timeout );
-void rfsc_set_timeout( u32 timeout );
+void rfsc_setup( u8 *pbuf, p_rfsc_send rfsc_send_func, p_rfsc_recv rfsc_recv_func, timer_data_type timeout );
+void rfsc_set_timeout( timer_data_type timeout );
 int rfsc_open( const char* pathname, int flags, int mode );
 s32 rfsc_write( int fd, const void *buf, u32 count );
 s32 rfsc_read( int fd, void *buf, u32 count );
diff --git a/inc/swi.h b/inc/swi.h
index f5c91031..cb78549c 100644
--- a/inc/swi.h
+++ b/inc/swi.h
@@ -27,42 +27,42 @@
 
 
 /* Now the SWI numbers and reason codes for RDI (Angel) monitors.  */
-#define AngelSWI_ARM 			0x123456
+#define AngelSWI_ARM                    0x123456
 #ifdef __thumb__
-#define AngelSWI 			0xAB
+#define AngelSWI                        0xAB
 #else
-#define AngelSWI 			AngelSWI_ARM
+#define AngelSWI                        AngelSWI_ARM
 #endif
 /* For Thumb-2 code use the BKPT instruction instead of SWI.  */
 #ifdef __thumb2__
-#define AngelSWIInsn			"bkpt"
-#define AngelSWIAsm			bkpt
+#define AngelSWIInsn                    "bkpt"
+#define AngelSWIAsm                     bkpt
 #else
-#define AngelSWIInsn			"swi"
-#define AngelSWIAsm			swi
+#define AngelSWIInsn                    "swi"
+#define AngelSWIAsm                     swi
 #endif
 
 /* The reason codes:  */
-#define AngelSWI_Reason_Open		0x01
-#define AngelSWI_Reason_Close		0x02
-#define AngelSWI_Reason_WriteC		0x03
-#define AngelSWI_Reason_Write0		0x04
-#define AngelSWI_Reason_Write		0x05
-#define AngelSWI_Reason_Read		0x06
-#define AngelSWI_Reason_ReadC		0x07
-#define AngelSWI_Reason_IsTTY		0x09
-#define AngelSWI_Reason_Seek		0x0A
-#define AngelSWI_Reason_FLen		0x0C
-#define AngelSWI_Reason_TmpNam		0x0D
-#define AngelSWI_Reason_Remove		0x0E
-#define AngelSWI_Reason_Rename		0x0F
-#define AngelSWI_Reason_Clock		0x10
-#define AngelSWI_Reason_Time		0x11
-#define AngelSWI_Reason_System		0x12
-#define AngelSWI_Reason_Errno		0x13
-#define AngelSWI_Reason_GetCmdLine 	0x15
-#define AngelSWI_Reason_HeapInfo 	0x16
-#define AngelSWI_Reason_EnterSVC 	0x17
+#define AngelSWI_Reason_Open            0x01
+#define AngelSWI_Reason_Close           0x02
+#define AngelSWI_Reason_WriteC          0x03
+#define AngelSWI_Reason_Write0          0x04
+#define AngelSWI_Reason_Write           0x05
+#define AngelSWI_Reason_Read            0x06
+#define AngelSWI_Reason_ReadC           0x07
+#define AngelSWI_Reason_IsTTY           0x09
+#define AngelSWI_Reason_Seek            0x0A
+#define AngelSWI_Reason_FLen            0x0C
+#define AngelSWI_Reason_TmpNam          0x0D
+#define AngelSWI_Reason_Remove          0x0E
+#define AngelSWI_Reason_Rename          0x0F
+#define AngelSWI_Reason_Clock           0x10
+#define AngelSWI_Reason_Time            0x11
+#define AngelSWI_Reason_System          0x12
+#define AngelSWI_Reason_Errno           0x13
+#define AngelSWI_Reason_GetCmdLine      0x15
+#define AngelSWI_Reason_HeapInfo        0x16
+#define AngelSWI_Reason_EnterSVC        0x17
 #define AngelSWI_Reason_ReportException 0x18
-#define ADP_Stopped_ApplicationExit 	((2 << 16) + 38)
-#define ADP_Stopped_RunTimeError 	((2 << 16) + 35)
+#define ADP_Stopped_ApplicationExit     ((2 << 16) + 38)
+#define ADP_Stopped_RunTimeError        ((2 << 16) + 35)
diff --git a/inc/validate.h b/inc/validate.h
index 0e7d3889..e94b0347 100644
--- a/inc/validate.h
+++ b/inc/validate.h
@@ -74,6 +74,10 @@
   #endif
 #endif
 
+#if defined( BUILD_MMCFS ) && !defined( PLATFORM_HAS_SYSTIMER )
+  #error "BUILD_MMCFS needs system timer support. Ensure your platform has this implemented and PLATFORM_HAS_SYSTIMER is defined"
+#endif
+
 // CON_BUF_SIZE needs BUF_ENABLE_UART and CON_UART_ID
 #if defined( CON_BUF_SIZE )
   #if !defined( BUF_ENABLE_UART )
diff --git a/inc/xmodem.h b/inc/xmodem.h
index 53fe14e1..e31ca9f9 100644
--- a/inc/xmodem.h
+++ b/inc/xmodem.h
@@ -4,6 +4,7 @@
 #define __XMODEM_H__
 
 #include "type.h"
+#include "platform.h"
 
 // XMODEM constants
 #define XMODEM_INITIAL_BUFFER_SIZE    1024
@@ -20,7 +21,7 @@
 #define XMODEM_ERROR_OUTOFMEM         (-4)
 
 typedef void ( *p_xm_send_func )( u8 );
-typedef int ( *p_xm_recv_func )( u32 );
+typedef int ( *p_xm_recv_func )( timer_data_type );
 long xmodem_receive( char** dest );
 void xmodem_init( p_xm_send_func send_func, p_xm_recv_func recv_func );
 
diff --git a/romfs/.gitignore b/romfs/.gitignore
new file mode 100644
index 00000000..a5baada1
--- /dev/null
+++ b/romfs/.gitignore
@@ -0,0 +1,3 @@
+*
+!.gitignore
+
diff --git a/rpc-lua.py b/rpc-lua.py
index d028504a..37dd7070 100644
--- a/rpc-lua.py
+++ b/rpc-lua.py
@@ -1,7 +1,7 @@
 import os, sys, platform
 
 output = 'luarpc'
-cdefs = ['-DLUA_CROSS_COMPILER','-DLUA_RPC']
+cdefs = "-DLUA_CROSS_COMPILER -DLUA_RPC"
 
 # Lua source files and include path
 lua_files = """lapi.c lcode.c ldebug.c ldo.c ldump.c lfunc.c lgc.c llex.c lmem.c lobject.c lopcodes.c
@@ -10,24 +10,25 @@ lua_files = """lapi.c lcode.c ldebug.c ldo.c ldump.c lfunc.c lgc.c llex.c lmem.c
 lua_full_files = " " + " ".join( [ "src/lua/%s" % name for name in lua_files.split() ] )
 lua_full_files += " src/modules/luarpc.c src/modules/lpack.c src/modules/bitarray.c src/modules/bit.c src/luarpc_desktop_serial.c "
 
-external_libs = ['m']
+external_libs = '-lm'
 
 if platform.system() == "Windows":
   lua_full_files += " src/serial/serial_win32.c"
-  cdefs.append("-DWIN32_BUILD")
+  cdefs += " -DWIN32_BUILD"
 else:
-  lua_full_files += " src/serial/serial_posix.c"
-  external_libs += ['readline']
-  cdefs.append("-DLUA_USE_READLINE")
+  lua_full_files += " src/serial/serial_posix.c src/linenoise_posix.c"
+  cdefs += " -DLUA_USE_LINENOISE "
 
-local_include = ['src/lua', 'inc', 'src/modules', 'inc/desktop'];
+local_include = "-Isrc/lua -Iinc -Isrc/modules -Iinc/desktop"
+
+# Compiler/linker options
+cccom = "gcc -O2 -g %s -Wall %s -c $SOURCE -o $TARGET" % ( local_include, cdefs )
+linkcom = "gcc -o $TARGET $SOURCES %s" % external_libs
 
 # Env for building the program
-comp = Environment( CPPPATH = local_include,
-                    CCFLAGS = cdefs,
+comp = Environment( CCCOM = cccom,
+                    LINKCOM = linkcom,
                     ENV = os.environ )
 # Debug
-comp.PrependUnique(CCFLAGS=['-g'])
-
 Decider( 'MD5-timestamp' )                  
-Default( comp.Program( output, Split( lua_full_files ), LIBS=external_libs ) )
+Default( comp.Program( output, Split( lua_full_files ) ) )
diff --git a/run_elua_sim.sh b/run_elua_sim.sh
index a9cc6c86..0bd80940 100755
--- a/run_elua_sim.sh
+++ b/run_elua_sim.sh
@@ -4,7 +4,7 @@
 stty -echo raw -igncr
 
 # Run simulator
-./elua_lua_linux.elf
+./elua_lua$1_linux.elf
 
 # Restore terminal to default settings
 stty echo cooked
diff --git a/src/common.c b/src/common.c
index 4902a05d..f600ba91 100644
--- a/src/common.c
+++ b/src/common.c
@@ -8,6 +8,7 @@
 #include "buf.h"
 #include 
 #include 
+#include 
 #include 
 #include "math.h"
 #include "elua_adc.h"
@@ -15,6 +16,9 @@
 #include "xmodem.h"
 #include "elua_int.h"
 #include "sermux.h"
+#include "lua.h"
+#include "lapi.h"
+#include "lauxlib.h"
 
 // [TODO] the new builder should automatically do this
 #if defined( BUILD_LUA_INT_HANDLERS ) || defined( BUILD_C_INT_HANDLERS )
@@ -45,7 +49,12 @@ extern const elua_int_descriptor elua_int_table[ INT_ELUA_LAST ];
 
 // [TODO] the new builder should automatically do this
 #ifndef CON_FLOW_TYPE
-#define CON_FLOW_TYPE        PLATFORM_UART_FLOW_NONE
+#define CON_FLOW_TYPE         PLATFORM_UART_FLOW_NONE
+#endif
+
+// [TODO] the new builder should automatically do this
+#ifndef CON_TIMER_ID
+#define CON_TIMER_ID          PLATFORM_TIMER_SYS_ID
 #endif
 
 // ****************************************************************************
@@ -58,7 +67,7 @@ static void xmodem_send( u8 data )
   platform_uart_send( CON_UART_ID, data );
 }
 
-static int xmodem_recv( u32 timeout )
+static int xmodem_recv( timer_data_type timeout )
 {
   return platform_uart_recv( CON_UART_ID, CON_TIMER_ID, timeout );
 }
@@ -82,7 +91,7 @@ static int term_in( int mode )
   if( mode == TERM_INPUT_DONT_WAIT )
     return platform_uart_recv( CON_UART_ID, CON_TIMER_ID, 0 );
   else
-    return platform_uart_recv( CON_UART_ID, CON_TIMER_ID, PLATFORM_UART_INFINITE_TIMEOUT );
+    return platform_uart_recv( CON_UART_ID, CON_TIMER_ID, PLATFORM_TIMER_INF_TIMEOUT );
 }
 
 static int term_translate( int data )
@@ -176,7 +185,7 @@ static void uart_send( int fd, char c )
   platform_uart_send( CON_UART_ID, c );
 }
 
-static int uart_recv( s32 to )
+static int uart_recv( timer_data_type to )
 {
   return platform_uart_recv( CON_UART_ID, CON_TIMER_ID, to );
 }
@@ -201,7 +210,7 @@ void cmn_platform_init()
     platform_uart_set_buffer( i + SERMUX_SERVICE_ID_FIRST, bufsizes[ i ] );
 #endif // #ifdef BUILD_SERMUX
 
-#if defined( CON_UART_ID ) && CON_UART_ID < SERMUX_SERVICE_ID_FIRST
+#if defined( CON_UART_ID ) && CON_UART_ID < SERMUX_SERVICE_ID_FIRST && ( CON_UART_ID != CDC_UART_ID )
   // Setup console UART
   platform_uart_setup( CON_UART_ID, CON_UART_SPEED, 8, PLATFORM_UART_PARITY_NONE, PLATFORM_UART_STOPBITS_1 );  
   platform_uart_set_flow_control( CON_UART_ID, CON_FLOW_TYPE );
@@ -294,47 +303,41 @@ int platform_adc_exists( unsigned id )
 
 #ifdef BUILD_ADC
 
-u32 platform_adc_op( unsigned id, int op, u32 data )
-{  
-  elua_adc_ch_state *s = adc_get_ch_state( id );
-  elua_adc_dev_state *d = adc_get_dev_state( 0 );
-  u32 res = 0;
-
-  switch( op )
-  {
-    case PLATFORM_ADC_GET_MAXVAL:
-      res = pow( 2, ADC_BIT_RESOLUTION ) - 1;
-      break;
-
-    case PLATFORM_ADC_SET_SMOOTHING:
-      res = adc_update_smoothing( id, ( u8 )intlog2( ( unsigned ) data ) );
-      break;
-      
-    case PLATFORM_ADC_SET_BLOCKING:
-      s->blocking = data;
-      break;
-      
-    case PLATFORM_ADC_IS_DONE:
-      res = ( s->op_pending == 0 );
-      break;
-    
-    case PLATFORM_ADC_OP_SET_TIMER:
-      if ( d->timer_id != data )
-        d->running = 0;
-      platform_adc_stop( id );
-      d->timer_id = data;
-      break;
-    
-    case PLATFORM_ADC_OP_SET_CLOCK:
-      res = platform_adc_setclock( id, data );
-      break;
-      
-    case PLATFORM_ADC_SET_FREERUNNING:
-      s->freerunning = data;
-      break;
-  }
-  return res;
+u32 platform_adc_get_maxval( unsigned id )
+{
+  return pow( 2, ADC_BIT_RESOLUTION ) - 1;
 }
+
+u32 platform_adc_set_smoothing( unsigned id, u32 length )
+{
+  return adc_update_smoothing( id, ( u8 )intlog2( ( unsigned ) length ) );
+}
+
+void platform_adc_set_blocking( unsigned id, u32 mode )
+{
+  adc_get_ch_state( id )->blocking = mode;
+}
+
+void platform_adc_set_freerunning( unsigned id, u32 mode )
+{
+  adc_get_ch_state( id )->freerunning = mode;
+}
+
+u32 platform_adc_is_done( unsigned id )
+{
+  return adc_get_ch_state( id )->op_pending == 0;
+}
+
+void platform_adc_set_timer( unsigned id, u32 timer )
+{
+  elua_adc_dev_state *d = adc_get_dev_state( 0 );
+
+  if ( d->timer_id != timer )
+    d->running = 0;
+  platform_adc_stop( id );
+  d->timer_id = timer;
+}
+
 #endif // #ifdef BUILD_ADC
 
 // ****************************************************************************
@@ -451,3 +454,44 @@ unsigned int intlog2( unsigned int v )
   return r;
 }
 
+// 64-bits integer printf support seems to be broken in some versions of Newlib...
+const char* cmn_str64( u64 x )
+{
+  static char nr[ 32 ];
+  u64 q, r;
+  unsigned l = 30;
+
+  memset( nr, 0, 32 );
+  do
+  {
+    q = x / 10;
+    r = x % 10;
+    nr[ l -- ] = r + '0';
+    x = q;
+  } while( x != 0 );
+  return nr + l + 1;
+}
+
+// Read a timeout spec from the user and return it
+// The timeout spec has the format [timeout], [timer_id]. Both arguments are optional.
+// If none is specified -> defaults to infinite timeout
+// If timeout is PLATFORM_TIMER_INF_TIMEOUT -> also infinite timeout (see above)
+// If a timeout is specified -> timer_id might also be specified. If not, it defaults to
+// PLATFORM_TIMER_SYS_ID
+void cmn_get_timeout_data( lua_State *L, int pidx, timer_data_type *ptimeout, unsigned *pid )
+{
+  lua_Number tempn;
+
+  *ptimeout = PLATFORM_TIMER_INF_TIMEOUT;
+  *pid = ( unsigned )luaL_optinteger( L, pidx + 1, PLATFORM_TIMER_SYS_ID );
+  if( lua_type( L, pidx ) == LUA_TNUMBER )
+  {
+    tempn = lua_tonumber( L, pidx );
+    if( tempn < 0 || tempn > PLATFORM_TIMER_INF_TIMEOUT )
+      luaL_error( L, "invalid timeout value" );
+    *ptimeout = ( timer_data_type )tempn;
+  }
+  if( *pid == PLATFORM_TIMER_SYS_ID && !platform_timer_sys_available() )
+    luaL_error( L, "the system timer is not implemented on this platform" );
+}
+
diff --git a/src/common_tmr.c b/src/common_tmr.c
index 64dee30a..97aa0828 100644
--- a/src/common_tmr.c
+++ b/src/common_tmr.c
@@ -6,6 +6,7 @@
 #include "type.h"
 #include "common.h"
 #include "elua_int.h"
+#include "utils.h"
 #include 
 
 // [TODO] when the new build system is ready, automatically add the
@@ -25,11 +26,20 @@ extern const elua_int_descriptor elua_int_table[ INT_ELUA_LAST ];
 #define VTMR_NUM_TIMERS       0
 #endif // #ifndef VTMR_NUM_TIMERS
 
+#ifndef PLATFORM_HAS_SYSTIMER
+#warning This platform does not have a system timer. Your eLua image might not work as expected.
+#define SYSTIMER_SUPPORT 0
+#else // #ifndef PLATFORM_HAS_SYSTIMER
+#define SYSTIMER_SUPPORT 1
+#endif // #ifndef PLATFORM_HAS_SYSTIMER
+
 // ****************************************************************************
 // Timers (and vtimers) functions
 
 #if VTMR_NUM_TIMERS > 0
 
+#define VTMR_MAX_PERIOD       ( ( 1LL << 32 ) - 1 )
+
 // ============================================================================
 // VTMR functions
 
@@ -87,23 +97,28 @@ static void vtmr_reset_timer( unsigned vid )
   while( vtmr_reset_idx != -1 );  
 }
 
-static void vtmr_delay( unsigned vid, u32 delay_us )
+static void vtmr_delay( unsigned vid, timer_data_type delay_us )
 {
   timer_data_type final;
   unsigned id = VTMR_GET_ID( vid );
   
+  if( delay_us > VTMR_MAX_PERIOD )
+    return;
   final = ( ( u64 )delay_us * VTMR_FREQ_HZ ) / 1000000;
   vtmr_reset_timer( vid );
   while( vtmr_counters[ id ] < final );  
 }
 
 #ifdef CMN_TIMER_INT_SUPPORT
-static int vtmr_set_match_int( unsigned vid, u32 period_us, int type )
+
+static int vtmr_set_match_int( unsigned vid, timer_data_type period_us, int type )
 {
   timer_data_type final;
   unsigned id = VTMR_GET_ID( vid );
   u8 msk = 1 << ( id & 0x07 );
 
+  if( period_us > VTMR_MAX_PERIOD )
+    return PLATFORM_TIMER_INT_TOO_LONG;
   if( period_us == 0 )
   {
     vtmr_int_enabled[ id >> 3 ] &= ( u8 )~msk;
@@ -166,6 +181,18 @@ void cmn_virtual_timer_cb()
 // ============================================================================
 // Actual timer functions
 
+int platform_timer_sys_available()
+{
+  return SYSTIMER_SUPPORT;
+}
+
+#ifndef PLATFORM_HAS_SYSTIMER
+timer_data_type platform_timer_read_sys()
+{
+  return 0;
+}
+#endif
+
 int platform_timer_exists( unsigned id )
 {
 #if VTMR_NUM_TIMERS > 0
@@ -173,25 +200,81 @@ int platform_timer_exists( unsigned id )
     return TIMER_IS_VIRTUAL( id );
   else
 #endif
-    return id < NUM_TIMER;
+    return id < NUM_TIMER || ( id == PLATFORM_TIMER_SYS_ID && SYSTIMER_SUPPORT );
 }
 
-void platform_timer_delay( unsigned id, u32 delay_us )
+void platform_timer_delay( unsigned id, timer_data_type delay_us )
 {
 #if VTMR_NUM_TIMERS > 0
   if( TIMER_IS_VIRTUAL( id ) )
     vtmr_delay( id, delay_us );
   else
 #endif
+  if( id == PLATFORM_TIMER_SYS_ID )
+  {
+    if( !SYSTIMER_SUPPORT )
+      return;
+    if( delay_us > 0 )
+    {
+      u64 tstart = platform_timer_read_sys(), tend;
+      while( 1 )
+      {
+        if( ( tend = platform_timer_read_sys() ) < tstart ) // overflow
+          tend += ( u64 )PLATFORM_TIMER_SYS_MAX + 1;
+        if( tend - tstart >= delay_us )
+          return;
+      }
+    }
+  }
+  else
     platform_s_timer_delay( id, delay_us );
 }
       
-u32 platform_timer_op( unsigned id, int op, u32 data )
+timer_data_type platform_timer_op( unsigned id, int op, timer_data_type data )
 {
-  u32 res = 0;
+  timer_data_type res = 0;
 
+  if( id == PLATFORM_TIMER_SYS_ID ) // the system timer gets special treatment
+  {
+    if( !SYSTIMER_SUPPORT )
+      return 0;
+    switch( op )
+    {
+      case PLATFORM_TIMER_OP_START:
+      case PLATFORM_TIMER_OP_READ:
+        res = platform_timer_read_sys();
+        break;
+
+      case PLATFORM_TIMER_OP_SET_CLOCK:
+      case PLATFORM_TIMER_OP_GET_CLOCK:
+        res = PLATFORM_TIMER_SYS_FREQ;
+        break;
+
+      case PLATFORM_TIMER_OP_GET_MAX_DELAY:
+        res = PLATFORM_TIMER_SYS_MAX + 1;
+        break;
+
+      case PLATFORM_TIMER_OP_GET_MAX_CNT:
+        res = PLATFORM_TIMER_SYS_MAX;
+        break;
+
+      case PLATFORM_TIMER_OP_GET_MIN_DELAY:
+        res = 1;
+        break;
+    }
+
+    return res;
+  }
   if( ( VTMR_NUM_TIMERS == 0 ) || ( !TIMER_IS_VIRTUAL( id ) ) )
-    return platform_s_timer_op( id, op, data );
+  {
+    // 'get min delay' and 'get max delay' are very common cases, handle them here
+    if( op == PLATFORM_TIMER_OP_GET_MAX_DELAY )
+      return platform_timer_get_diff_us( id, platform_timer_get_max_cnt( id ), 0 );
+    else if( op == PLATFORM_TIMER_OP_GET_MIN_DELAY )
+      return platform_timer_get_diff_us( id, 1, 0 );
+    else
+      return platform_s_timer_op( id, op, data );
+  }
 #if VTMR_NUM_TIMERS > 0
   switch( op )
   {
@@ -205,11 +288,15 @@ u32 platform_timer_op( unsigned id, int op, u32 data )
       break;
       
     case PLATFORM_TIMER_OP_GET_MAX_DELAY:
-      res = platform_timer_get_diff_us( id, 0, 0xFFFFFFFF );
+      res = platform_timer_get_diff_us( id, 0xFFFFFFFF, 0 );
       break;
       
     case PLATFORM_TIMER_OP_GET_MIN_DELAY:
-      res = platform_timer_get_diff_us( id, 0, 1 );
+      res = platform_timer_get_diff_us( id, 1, 0 );
+      break;
+
+    case PLATFORM_TIMER_OP_GET_MAX_CNT:
+      res = VTMR_MAX_PERIOD;
       break;
       
     case PLATFORM_TIMER_OP_SET_CLOCK:
@@ -221,39 +308,41 @@ u32 platform_timer_op( unsigned id, int op, u32 data )
   return res;
 }
 
-u32 platform_timer_get_diff_us( unsigned id, timer_data_type end, timer_data_type start )
+timer_data_type platform_timer_get_diff_us( unsigned id, timer_data_type end, timer_data_type start )
 {
-  timer_data_type temp;
   u32 freq;
+  u64 tstart = ( u64 )start, tend = ( u64 )end;
     
   freq = platform_timer_op( id, PLATFORM_TIMER_OP_GET_CLOCK, 0 );
-  if( start < end )
-  {
-    temp = end;
-    end = start;
-    start = temp;
-  }
-  return ( ( u64 )( start - end ) * 1000000 ) / freq;
+  if( tstart > tend )
+    tend += platform_timer_op( id, PLATFORM_TIMER_OP_GET_MAX_CNT, 0 ) + 1;
+  tstart = ( ( tend - tstart ) * 1000000 ) / freq;
+  return UMIN( tstart, PLATFORM_TIMER_SYS_MAX );
 }
 
 #ifdef BUILD_INT_HANDLERS
-int platform_timer_set_match_int( unsigned id, u32 period_us, int type )
+int platform_timer_set_match_int( unsigned id, timer_data_type period_us, int type )
 {
 #if VTMR_NUM_TIMERS > 0 && defined( CMN_TIMER_INT_SUPPORT )
   if( TIMER_IS_VIRTUAL( id ) )
     return vtmr_set_match_int( id, period_us, type );
   else
 #endif
+  if( id == PLATFORM_TIMER_SYS_ID )
+    return PLATFORM_TIMER_INT_INVALID_ID;
+  else
     return platform_s_timer_set_match_int( id, period_us, type );
 }
 
 int cmn_tmr_int_set_status( elua_int_resnum resnum, int status )
 {
+  elua_int_p_set_status ps;
 #if VTMR_NUM_TIMERS > 00 && defined( CMN_TIMER_INT_SUPPORT )
   if( TIMER_IS_VIRTUAL( resnum ) )
     return vtmr_int_set_status( resnum, status );
 #endif
-  elua_int_p_set_status ps;
+  if( resnum == PLATFORM_TIMER_SYS_ID )
+    return PLATFORM_INT_BAD_RESNUM;
   if( ( ps = elua_int_table[ INT_TMR_MATCH - ELUA_INT_FIRST_ID ].int_set_status ) == NULL )
     return PLATFORM_INT_NOT_HANDLED;
   return ps( resnum, status );
@@ -261,11 +350,13 @@ int cmn_tmr_int_set_status( elua_int_resnum resnum, int status )
 
 int cmn_tmr_int_get_status( elua_int_resnum resnum )
 {
+  elua_int_p_get_status pg;
 #if VTMR_NUM_TIMERS > 00 && defined( CMN_TIMER_INT_SUPPORT )
   if( TIMER_IS_VIRTUAL( resnum ) )
     return vtmr_int_get_status( resnum );
 #endif
-  elua_int_p_get_status pg;
+  if( resnum == PLATFORM_TIMER_SYS_ID )
+    return PLATFORM_INT_BAD_RESNUM;
   if( ( pg = elua_int_table[ INT_TMR_MATCH - ELUA_INT_FIRST_ID ].int_get_status ) == NULL )
     return PLATFORM_INT_NOT_HANDLED;
   return pg( resnum );
@@ -273,11 +364,13 @@ int cmn_tmr_int_get_status( elua_int_resnum resnum )
 
 int cmn_tmr_int_get_flag( elua_int_resnum resnum, int clear )
 {
+  elua_int_p_get_flag pf;
 #if VTMR_NUM_TIMERS > 00 && defined( CMN_TIMER_INT_SUPPORT )
   if( TIMER_IS_VIRTUAL( resnum ) )
     return vtmr_int_get_flag( resnum, clear );
 #endif
-  elua_int_p_get_flag pf;
+  if( resnum == PLATFORM_TIMER_SYS_ID )
+    return PLATFORM_INT_BAD_RESNUM;
   if( ( pf = elua_int_table[ INT_TMR_MATCH - ELUA_INT_FIRST_ID ].int_get_flag ) == NULL )
     return PLATFORM_INT_NOT_HANDLED;
   return pf( resnum, clear );
@@ -285,7 +378,7 @@ int cmn_tmr_int_get_flag( elua_int_resnum resnum, int clear )
 
 #else // #ifdef BUILD_INT_HANDLERS
 
-int platform_timer_set_match_int( unsigned id, u32 period_us, int type )
+int platform_timer_set_match_int( unsigned id, timer_data_type period_us, int type )
 {
   fprintf( stderr, "Timer match interrupt not available when eLua interrupt support is not enabled.\n" );
   return 0;
@@ -293,3 +386,52 @@ int platform_timer_set_match_int( unsigned id, u32 period_us, int type )
 
 #endif // #ifdef BUILD_INT_HANDLERS
 
+// ****************************************************************************
+// Generic system timer support
+
+static u32 cmn_systimer_ticks_for_us;
+static volatile u64 cmn_systimer_counter;
+static u32 cmn_systimer_us_per_interrupt;
+
+void cmn_systimer_set_base_freq( u32 freq_hz )
+{
+  cmn_systimer_ticks_for_us = freq_hz / 1000000;
+}
+
+void cmn_systimer_set_interrupt_freq( u32 freq_hz )
+{
+  cmn_systimer_us_per_interrupt = 1000000 / freq_hz;
+}
+
+void cmn_systimer_set_interrupt_period_us( u32 period )
+{
+  cmn_systimer_us_per_interrupt = period;
+}
+
+void cmn_systimer_periodic()
+{
+  cmn_systimer_counter += cmn_systimer_us_per_interrupt;
+}
+
+timer_data_type cmn_systimer_get()
+{
+  u64 tempsys, tempcnt, crtsys;
+
+  tempcnt = platform_timer_sys_raw_read();
+  tempsys = cmn_systimer_counter;
+  while( ( crtsys = cmn_systimer_counter ) != tempsys )
+  {
+    tempcnt = platform_timer_sys_raw_read();
+    tempsys = crtsys;
+  }
+  crtsys += tempcnt / cmn_systimer_ticks_for_us;
+  if( crtsys > PLATFORM_TIMER_SYS_MAX ) // timer overflow
+  {
+    crtsys %= PLATFORM_TIMER_SYS_MAX;
+    platform_timer_sys_disable_int();
+    cmn_systimer_counter = 0;
+    platform_timer_sys_enable_int();
+  }
+  return ( timer_data_type )crtsys;
+}
+
diff --git a/src/common_uart.c b/src/common_uart.c
index 5ea7ee40..e457835b 100644
--- a/src/common_uart.c
+++ b/src/common_uart.c
@@ -24,18 +24,34 @@ int uart_last_sent = -1;
 int platform_uart_exists( unsigned id )
 {
 #ifdef BUILD_SERMUX
-  return id < NUM_UART || ( id >= SERMUX_SERVICE_ID_FIRST && id < SERMUX_SERVICE_ID_FIRST + SERMUX_NUM_VUART );
-#else // #ifdef BUILD_SERMUX
-  return id < NUM_UART;
-#endif // #ifdef BUILD_SERMUX
+  if( id >= SERMUX_SERVICE_ID_FIRST && id < SERMUX_SERVICE_ID_FIRST + SERMUX_NUM_VUART )
+    return 1;
+#endif
+
+#ifdef BUILD_USB_CDC
+  if( id == CDC_UART_ID )
+    return 1;
+#endif
+
+  if( id < NUM_UART )
+    return 1;
+
+  return 0;
 }
 
 // Helper function for buffers
-static int cmn_recv_helper( unsigned id, s32 timeout )
+static int cmn_recv_helper( unsigned id, timer_data_type timeout )
 {
 #ifdef BUF_ENABLE_UART
   t_buf_data data;
-  
+#endif
+
+#ifdef BUILD_USB_CDC
+  if( id == CDC_UART_ID )
+    return platform_usb_cdc_recv( timeout );
+#endif
+
+#ifdef BUF_ENABLE_UART
   if( buf_is_enabled( BUF_ID_UART, id ) )
   {
     if( timeout == 0 )
@@ -51,28 +67,30 @@ static int cmn_recv_helper( unsigned id, s32 timeout )
   }
   else
 #endif // #ifdef BUF_ENABLE_UART
-  return platform_s_uart_recv( id, timeout );
+  if( id < NUM_UART )
+    return platform_s_uart_recv( id, timeout );
+
+  return -1;
 }
 
-int platform_uart_recv( unsigned id, unsigned timer_id, s32 timeout )
+int platform_uart_recv( unsigned id, unsigned timer_id, timer_data_type timeout )
 {
-  timer_data_type tmr_start, tmr_crt;
+  timer_data_type tmr_start;
   int res;
   
   if( timeout == 0 )
     return cmn_recv_helper( id, timeout );
-  else if( timeout == PLATFORM_UART_INFINITE_TIMEOUT )
+  else if( timeout ==  PLATFORM_TIMER_INF_TIMEOUT )
     return cmn_recv_helper( id, timeout );
   else
   {
     // Receive char with the specified timeout
-    tmr_start = platform_timer_op( timer_id, PLATFORM_TIMER_OP_START, 0 );
+    tmr_start = platform_timer_start( timer_id );
     while( 1 )
     {
       if( ( res = cmn_recv_helper( id, 0 ) ) >= 0 )
         break;
-      tmr_crt = platform_timer_op( timer_id, PLATFORM_TIMER_OP_READ, 0 );
-      if( platform_timer_get_diff_us( timer_id, tmr_crt, tmr_start ) >= timeout )
+      if( platform_timer_get_diff_crt( timer_id, tmr_start ) >= timeout )
         break;
     }
     return res;
@@ -122,6 +140,10 @@ static void cmn_rx_handler( int usart_id, u8 data )
 // Send: version with and without mux
 void platform_uart_send( unsigned id, u8 data ) 
 {
+#ifdef BUILD_USB_CDC
+  if( id == CDC_UART_ID )
+    platform_usb_cdc_send( data );
+#endif
 #ifdef BUILD_SERMUX
   if( id >= SERMUX_SERVICE_ID_FIRST && id < SERMUX_SERVICE_ID_FIRST + SERMUX_NUM_VUART )
   {
@@ -138,19 +160,24 @@ void platform_uart_send( unsigned id, u8 data )
       platform_s_uart_send( SERMUX_PHYS_ID, data );
     uart_service_id_out = id;
   }
-  else
 #endif // #ifdef BUILD_SERMUX
-  platform_s_uart_send( id, data );
+  if( id < NUM_UART )
+    platform_s_uart_send( id, data );
 }
 
 #ifdef BUF_ENABLE_UART
 static elua_int_c_handler prev_uart_rx_handler;
 
 static void cmn_uart_rx_inthandler( elua_int_resnum resnum )
-{   
+{
+  int data;
+
   if( buf_is_enabled( BUF_ID_UART, resnum ) || resnum == SERMUX_PHYS_ID )
-    cmn_rx_handler( resnum, platform_s_uart_recv( resnum, 0 ) );
-  
+  {
+    while( -1 != ( data = platform_s_uart_recv( resnum, 0 ) ) )
+      cmn_rx_handler( resnum, ( u8 )data );
+  }
+
   // Chain to previous handler
   if( prev_uart_rx_handler != NULL )
     prev_uart_rx_handler( resnum );  
diff --git a/src/elua_adc.c b/src/elua_adc.c
index ee3f47d3..e9a38374 100644
--- a/src/elua_adc.c
+++ b/src/elua_adc.c
@@ -24,7 +24,7 @@ elua_adc_dev_state *adc_get_dev_state( unsigned dev_id )
   return &adc_dev_state;
 }
 
-// Rewrite revice sequence
+// Rewrite device sequence
 void adc_update_dev_sequence( unsigned dev_id  )
 {
   elua_adc_dev_state *d = adc_get_dev_state( dev_id );
@@ -126,7 +126,7 @@ void adc_init_ch_state( unsigned id )
 #endif
 
   // Set to run as fast as possible
-  platform_adc_setclock( id, 0 );
+  platform_adc_set_clock( id, 0 );
 }
 
 void adc_init_dev_state( unsigned dev_id )
diff --git a/src/elua_mmc.c b/src/elua_mmc.c
index b6582ab6..fe6838da 100644
--- a/src/elua_mmc.c
+++ b/src/elua_mmc.c
@@ -55,8 +55,8 @@ void DESELECT (void)
 static volatile
 DSTATUS Stat = STA_NOINIT;    /* Disk status */
 
-static volatile UINT Timer1 = 0;
-static volatile UINT Timer2 = 0;    /* decrement timer */
+static volatile timer_data_type Timer1 = 0;
+static volatile timer_data_type Timer2 = 0;
 
 static
 BYTE TriesLeft = 2;
@@ -67,6 +67,7 @@ BYTE CardType;            /* b0:MMC, b1:SDC, b2:Block addressing */
 static
 BYTE PowerFlag = 0;     /* indicates if "power" is on */
 
+
 /*-----------------------------------------------------------------------*/
 /* Transmit a byte to MMC via SPI  (Platform dependent)                  */
 /*-----------------------------------------------------------------------*/
@@ -109,11 +110,11 @@ BYTE wait_ready (void)
 {
     BYTE res;
 
-    Timer2 = 500/MMCFS_TICK_MS;    /* Wait for ready in timeout of 500ms */
+    Timer2 = platform_timer_read( PLATFORM_TIMER_SYS_ID );
     rcvr_spi();
-    do
-        res = rcvr_spi();
-    while ((res != 0xFF) && Timer2);
+    do  
+        res = rcvr_spi(); /* Wait for ready in timeout of 500ms. */
+    while ( ( res != 0xFF ) && ( platform_timer_get_diff_crt( PLATFORM_TIMER_SYS_ID, Timer2 ) < 500000 ) );
 
     return res;
 }
@@ -205,11 +206,11 @@ BOOL rcvr_datablock (
 {
     BYTE token;
 
-
-    Timer1 = 100/MMCFS_TICK_MS ? 100/MMCFS_TICK_MS : 1;
+    Timer1 = platform_timer_read( PLATFORM_TIMER_SYS_ID );
     do {                            /* Wait for data packet in timeout of 100ms */
         token = rcvr_spi();
-    } while ((token == 0xFF) && Timer1);
+    } while ( ( token == 0xFF ) && 
+              platform_timer_get_diff_crt( PLATFORM_TIMER_SYS_ID, Timer1 ) < 100000 );
     if(token != 0xFE) return FALSE;    /* If not valid data token, retutn with error */
 
     do {                            /* Receive the data block into buffer */
@@ -326,29 +327,31 @@ DSTATUS disk_initialize (
       SELECT();                /* CS = L */
       ty = 0;
       if (send_cmd(CMD0, 0) == 1) {            /* Enter Idle state */
-        Timer1 = 1000/MMCFS_TICK_MS;     /* Initialization timeout of 1000 msec */
+        Timer1 = platform_timer_read( PLATFORM_TIMER_SYS_ID );
         if (send_cmd(CMD8, 0x1AA) == 1) {    /* SDC Ver2+ */
-	  for (n = 0; n < 4; n++) ocr[n] = rcvr_spi();
-	  if (ocr[2] == 0x01 && ocr[3] == 0xAA) {    /* The card can work at vdd range of 2.7-3.6V */
-	    do {
-	      if (send_cmd(CMD55, 0) <= 1 && send_cmd(CMD41, 1UL << 30) == 0)    break;    /* ACMD41 with HCS bit */
-	    } while (Timer1);
-	    if (Timer1 && send_cmd(CMD58, 0) == 0) {    /* Check CCS bit */
-	      for (n = 0; n < 4; n++) ocr[n] = rcvr_spi();
-	      ty = (ocr[0] & 0x40) ? 6 : 2;
-	    }
-	  }
+          for (n = 0; n < 4; n++) ocr[n] = rcvr_spi();
+          if (ocr[2] == 0x01 && ocr[3] == 0xAA) {    /* The card can work at vdd range of 2.7-3.6V */
+            do {
+              if (send_cmd(CMD55, 0) <= 1 && send_cmd(CMD41, 1UL << 30) == 0)    break;    /* ACMD41 with HCS bit */
+            } while ( platform_timer_get_diff_crt( PLATFORM_TIMER_SYS_ID, Timer1 ) < 1000000 );
+            if ( ( platform_timer_get_diff_crt( PLATFORM_TIMER_SYS_ID, Timer1 ) < 1000000 ) 
+                 && send_cmd(CMD58, 0) == 0) {    /* Check CCS bit (it seems pointless to check the timer here*/
+              for (n = 0; n < 4; n++) ocr[n] = rcvr_spi();
+              ty = (ocr[0] & 0x40) ? 6 : 2;
+            }
+          }
         } else {                            /* SDC Ver1 or MMC */
-	  ty = (send_cmd(CMD55, 0) <= 1 && send_cmd(CMD41, 0) <= 1) ? 2 : 1;    /* SDC : MMC */
-	  do {
-	    if (ty == 2) {
-	      if (send_cmd(CMD55, 0) <= 1 && send_cmd(CMD41, 0) == 0) break;    /* ACMD41 */
-	    } else {
-	      if (send_cmd(CMD1, 0) == 0) break;                                /* CMD1 */
-	    }
-	  } while (Timer1);
-	  if (!Timer1 || send_cmd(CMD16, 512) != 0)    /* Select R/W block length */
-	    ty = 0;
+          ty = (send_cmd(CMD55, 0) <= 1 && send_cmd(CMD41, 0) <= 1) ? 2 : 1;    /* SDC : MMC */
+          do {
+            if (ty == 2) {
+              if (send_cmd(CMD55, 0) <= 1 && send_cmd(CMD41, 0) == 0) break;    /* ACMD41 */
+            } else {
+              if (send_cmd(CMD1, 0) == 0) break;                                /* CMD1 */
+            }
+          } while ( platform_timer_get_diff_crt( PLATFORM_TIMER_SYS_ID, Timer1 ) < 1000000 );
+          if ( (  platform_timer_get_diff_crt( PLATFORM_TIMER_SYS_ID, Timer1 ) >= 1000000 ) 
+               || send_cmd(CMD16, 512) != 0 )    /* Select R/W block length */
+            ty = 0;
         }
       }
       CardType = ty;
@@ -356,13 +359,13 @@ DSTATUS disk_initialize (
       rcvr_spi();            /* Idle (Release DO) */
 
       if (TriesLeft)
-	TriesLeft--;
+        TriesLeft--;
 
       if (ty) {            /* Initialization succeded */
-	Stat &= ~STA_NOINIT;        /* Clear STA_NOINIT */
-	set_max_speed();
+        Stat &= ~STA_NOINIT;        /* Clear STA_NOINIT */
+        set_max_speed();
       } else {            /* Initialization failed */
-	power_off();
+        power_off();
       }
 
     } while( TriesLeft > 0 && ty == 0 );
@@ -580,22 +583,6 @@ DRESULT disk_ioctl (
 
 
 
-/*-----------------------------------------------------------------------*/
-/* Device Timer Interrupt Procedure  (Platform dependent)                */
-/*-----------------------------------------------------------------------*/
-/* This function must be called in period of 10ms                        */
-
-void disk_timerproc( void )
-{
-    UINT n;
-
-    n = Timer1;
-    if (n) Timer1 = --n;
-    n = Timer2;
-    if (n) Timer2 = --n;
-
-}
-
 /*---------------------------------------------------------*/
 /* User Provided Timer Function for FatFs module           */
 /*---------------------------------------------------------*/
diff --git a/src/elua_uip.c b/src/elua_uip.c
index ace6604c..c5e42d46 100644
--- a/src/elua_uip.c
+++ b/src/elua_uip.c
@@ -545,10 +545,10 @@ elua_net_size elua_net_send( int s, const void* buf, elua_net_size len )
 }
 
 // Internal "read" function
-static elua_net_size elua_net_recv_internal( int s, void* buf, elua_net_size maxsize, s16 readto, unsigned timer_id, u32 to_us, int with_buffer )
+static elua_net_size elua_net_recv_internal( int s, void* buf, elua_net_size maxsize, s16 readto, unsigned timer_id, timer_data_type to_us, int with_buffer )
 {
   volatile struct elua_uip_state *pstate = ( volatile struct elua_uip_state* )&( uip_conns[ s ].appstate );
-  u32 tmrstart = 0;
+  timer_data_type tmrstart = 0;
   int old_status;
   
   if( !ELUA_UIP_IS_SOCK_OK( s ) || !uip_conn_active( s ) )
@@ -557,12 +557,12 @@ static elua_net_size elua_net_recv_internal( int s, void* buf, elua_net_size max
     return 0;
   elua_prep_socket_state( pstate, buf, maxsize, readto, with_buffer, ELUA_UIP_STATE_RECV );
   if( to_us > 0 )
-    tmrstart = platform_timer_op( timer_id, PLATFORM_TIMER_OP_START, 0 );
+    tmrstart = platform_timer_start( timer_id );
   while( 1 )
   {
     if( pstate->state == ELUA_UIP_STATE_IDLE )
       break;
-    if( to_us > 0 && platform_timer_get_diff_us( timer_id, tmrstart, platform_timer_op( timer_id, PLATFORM_TIMER_OP_READ, 0 ) ) >= to_us )
+    if( to_us > 0 && platform_timer_get_diff_crt( timer_id, tmrstart ) >= to_us )
     {
       old_status = platform_cpu_set_global_interrupts( PLATFORM_CPU_DISABLE );
       if( pstate->state != ELUA_UIP_STATE_IDLE )
@@ -578,13 +578,13 @@ static elua_net_size elua_net_recv_internal( int s, void* buf, elua_net_size max
 }
 
 // Receive data in buf, upto "maxsize" bytes, or upto the 'readto' character if it's not -1
-elua_net_size elua_net_recv( int s, void* buf, elua_net_size maxsize, s16 readto, unsigned timer_id, u32 to_us )
+elua_net_size elua_net_recv( int s, void* buf, elua_net_size maxsize, s16 readto, unsigned timer_id, timer_data_type to_us )
 {
   return elua_net_recv_internal( s, buf, maxsize, readto, timer_id, to_us, 0 );
 }
 
 // Same thing, but with a Lua buffer as argument
-elua_net_size elua_net_recvbuf( int s, luaL_Buffer* buf, elua_net_size maxsize, s16 readto, unsigned timer_id, u32 to_us )
+elua_net_size elua_net_recvbuf( int s, luaL_Buffer* buf, elua_net_size maxsize, s16 readto, unsigned timer_id, timer_data_type to_us )
 {
   return elua_net_recv_internal( s, buf, maxsize, readto, timer_id, to_us, 1 );
 }
@@ -627,9 +627,9 @@ int elua_net_get_last_err( int s )
 }
 
 // Accept a connection on the given port, return its socket id (and the IP of the remote host by side effect)
-int elua_accept( u16 port, unsigned timer_id, u32 to_us, elua_net_ip* pfrom )
+int elua_accept( u16 port, unsigned timer_id, timer_data_type to_us, elua_net_ip* pfrom )
 {
-  u32 tmrstart = 0;
+  timer_data_type tmrstart = 0;
   int old_status;
   
   if( !elua_uip_configured )
@@ -645,12 +645,12 @@ int elua_accept( u16 port, unsigned timer_id, u32 to_us, elua_net_ip* pfrom )
   elua_uip_accept_sock = -1;
   elua_uip_accept_request = 1;
   if( to_us > 0 )
-    tmrstart = platform_timer_op( timer_id, PLATFORM_TIMER_OP_START, 0 );
+    tmrstart = platform_timer_start( timer_id );
   while( 1 )
   {
     if( elua_uip_accept_request == 0 )
       break;
-    if( to_us > 0 && platform_timer_get_diff_us( timer_id, tmrstart, platform_timer_op( timer_id, PLATFORM_TIMER_OP_READ, 0 ) ) >= to_us )
+    if( to_us > 0 && platform_timer_get_diff_crt( timer_id, tmrstart ) >= to_us )
     {
       elua_uip_accept_request = 0;
       break;
diff --git a/src/eluarpc.c b/src/eluarpc.c
index b72ed920..3c0811bc 100644
--- a/src/eluarpc.c
+++ b/src/eluarpc.c
@@ -1,359 +1,359 @@
-// eLua RPC mechanism
-
-#include 
-#include 
-#include 
-#include "type.h"
-#include "eluarpc.h"
-#include "rtype.h"
-
-static u8 eluarpc_err_flag;
-
-// *****************************************************************************
-// Internal functions: fdata serialization
-
-static u8 *eluarpc_write_u8( u8 *p, u8 fdata )
-{
-  *p ++ = TYPE_INT_8;
-  *p ++ = fdata;
-  return p;  
-}
-
-static u8* eluarpc_write_op_id( u8 *p, u8 fdata )
-{
-  *p ++ = TYPE_OP_ID;
-  *p ++ = fdata;
-  return p;    
-}
-
-static u8 *eluarpc_write_u16( u8 *p, u16 fdata )
-{
-  *p ++ = TYPE_INT_16;
-  *p ++ = fdata & 0xFF;
-  *p ++ = ( fdata >> 8 ) & 0xFF;
-  return p;    
-}
-
-static u8 *eluarpc_write_u32( u8 *p, u32 fdata )
-{
-  *p ++ = TYPE_INT_32;
-  *p ++ = fdata & 0xFF;
-  *p ++ = ( fdata >> 8 ) & 0xFF;
-  *p ++ = ( fdata >> 16 ) & 0xFF;
-  *p ++ = ( fdata >> 24 ) & 0xFF;
-  return p;        
-}
-
-static u8 *eluarpc_write_ptr( u8 *p, const void* src, u32 srclen )
-{
-  *p ++ = TYPE_PTR;
-  p = eluarpc_write_u32( p, srclen );
-  if( src )
-    memcpy( p, src, srclen );
-  return p + srclen;    
-}
-
-static u8 *eluarpc_write_small_ptr( u8 *p, const void* src, u16 srclen )
-{
-  *p ++ = TYPE_SMALL_PTR;
-  p = eluarpc_write_u16( p, srclen );
-  if( src )
-    memcpy( p, src, srclen );
-  return p + srclen;    
-}
-
-// *****************************************************************************
-// Internal functions: fdata deserialization
-
-static const u8* eluarpc_read_expect( const u8 *p, u8 fdata )
-{
-  if( *p ++ != fdata )
-    eluarpc_err_flag = ELUARPC_ERR;
-  return p;
-}
-
-static const u8 *eluarpc_read_u8( const u8 *p, u8 *pfdata )
-{
-  p = eluarpc_read_expect( p, TYPE_INT_8 );
-  *pfdata = *p ++;
-  return p;  
-}
-
-static const u8 *eluarpc_read_op_id( const u8 *p, u8 *pfdata )
-{
-  p = eluarpc_read_expect( p, TYPE_OP_ID );
-  *pfdata = *p ++;
-  return p;  
-}
-
-static const u8* eluarpc_expect_op_id( const u8 *p, u8 id )
-{
-  u8 temp;
-  
-  p = eluarpc_read_expect( p, TYPE_OP_ID );
-  temp = *p ++;
-  if( temp != id )
-    eluarpc_err_flag = ELUARPC_ERR;
-  return p;
-}
-
-static const u8 *eluarpc_read_u16( const u8 *p, u16 *pfdata )
-{
-  p = eluarpc_read_expect( p, TYPE_INT_16 );
-  *pfdata = *p ++;
-  *pfdata |= ( u32 )( *p ++ ) << 8;  
-  return p;    
-}
-
-static const u8 *eluarpc_read_u32( const u8 *p, u32 *pfdata )
-{
-  p = eluarpc_read_expect( p, TYPE_INT_32 );
-  *pfdata = *p ++;                         
-  *pfdata |= ( u32 )( *p ++ ) << 8;
-  *pfdata |= ( u32 )( *p ++ ) << 16;
-  *pfdata |= ( u32 )( *p ++ ) << 24;      
-  return p;        
-}
-
-static const u8 *eluarpc_read_ptr( const u8 *p, void* src, u32 *psrclen )
-{                                         
-  p = eluarpc_read_expect( p, TYPE_PTR );
-  p = eluarpc_read_u32( p, psrclen );
-  if( src && p )
-    memcpy( src, p, *psrclen );
-  return p + *psrclen;    
-}
-
-static const u8 *eluarpc_read_small_ptr( const u8 *p, void* src, u16 *psrclen )
-{                                         
-  p = eluarpc_read_expect( p, TYPE_SMALL_PTR );
-  p = eluarpc_read_u16( p, psrclen );
-  if( src && p )
-    memcpy( src, p, *psrclen );
-  return p + *psrclen;    
-}
-
-
-// *****************************************************************************
-// Internal functions: packet handling (read and write)
-
-static u8* eluarpc_packet_ptr;
-
-static u8* eluarpc_start_packet( u8 *p )
-{
-  eluarpc_packet_ptr = p;
-  p += ELUARPC_START_OFFSET;
-  *p ++ = TYPE_START;
-  p = eluarpc_write_u32( p, PACKET_SIG );
-  return p;
-}
-
-static u8* eluarpc_end_packet( u8 *p )
-{
-  u16 len;
-  
-  *p ++ = TYPE_END;
-  p = eluarpc_write_u32( p, ~PACKET_SIG );
-  len = p - eluarpc_packet_ptr;
-  p = eluarpc_packet_ptr;
-  *p ++ = TYPE_PKT_SIZE;
-  eluarpc_write_u16( p, len );  
-  return p;  
-}
-
-static const u8* eluarpc_match_packet_start( const u8 *p )
-{
-  u32 fdata;
-  
-  p += ELUARPC_START_OFFSET;
-  p = eluarpc_read_expect( p, TYPE_START );
-  p = eluarpc_read_u32( p, &fdata );
-  if( fdata != PACKET_SIG )
-    eluarpc_err_flag = ELUARPC_ERR;
-  return p;
-}
-
-static const u8* eluarpc_match_packet_end( const u8 *p )
-{
-  u32 fdata;
-  
-  p = eluarpc_read_expect( p, TYPE_END );
-  p = eluarpc_read_u32( p, &fdata );
-  if( fdata != ~PACKET_SIG )
-    eluarpc_err_flag = ELUARPC_ERR;
-  return p;
-}
-
-// *****************************************************************************
-// Function serialization and deserialization
-
-int eluarpc_get_request_id( const u8 *p, u8 *pid )
-{ 
-  eluarpc_err_flag = ELUARPC_OK;
-  p = eluarpc_match_packet_start( p );
-  p = eluarpc_read_op_id( p, pid );
-  return eluarpc_err_flag;
-}
-
-u32 eluarpc_replace_flag( u32 val, u32 origflag, u32 newflag )
-{
-  return ( val & origflag ) ? newflag : 0; 
-}
-
-int eluarpc_get_packet_size( const u8 *p, u16 *psize )
-{
-  eluarpc_err_flag = ELUARPC_OK;
-  p = eluarpc_read_expect( p, TYPE_PKT_SIZE );
-  p = eluarpc_read_u16( p, psize );
-  return eluarpc_err_flag;
-}
-
-// Generic write function
-// Specifiers: o - operation
-//             r - response
-//             c - u8
-//             h - u16
-//             l - u32
-//             i - int
-//             L - s32
-//             p - ptr (given as ptr, len, len is an u32)
-//             P - ptr (given as ptr, len, len is an u16)
-void eluarpc_gen_write( u8 *p, const char *fmt, ... )
-{
-  va_list ap;
-  const void *ptr;
-  u32 ptrlen;
-  
-  va_start( ap, fmt );
-  p = eluarpc_start_packet( p );
-  while( *fmt )
-    switch( *fmt ++ )
-    {
-      case 'o':
-        p = eluarpc_write_op_id( p, va_arg( ap, int ) );
-        break;
-        
-      case 'r':
-        *p++ = ELUARPC_OP_RES_MOD | ( u8 )va_arg( ap, int );
-        break;
-        
-      case 'c':
-        p = eluarpc_write_u8( p, ( u8 )va_arg( ap, int ) );
-        break;
-        
-      case 'h':
-        p = eluarpc_write_u16( p, ( u16 )va_arg( ap, int ) );
-        break;
-
-      case 'i':
-        p = eluarpc_write_u32( p, ( u32 )va_arg( ap, int ) );
-        break;
-        
-      case 'l':
-        p = eluarpc_write_u32( p, ( u32 )va_arg( ap, u32 ) );
-        break;
-
-      case 'L':
-        p = eluarpc_write_u32( p, ( u32 )va_arg( ap, s32 ) );
-        break;         
-      
-      case 'p':
-        ptr = va_arg( ap, void* );
-        ptrlen = ( u32 )va_arg( ap, u32 );
-        p = eluarpc_write_ptr( p, ptr, ptrlen );
-        break;
-        
-      case 'P':
-        ptr = va_arg( ap, void * );
-        ptrlen = ( u16 )va_arg( ap, int );
-        p = eluarpc_write_small_ptr( p, ptr, ptrlen );
-        break;        
-    }
-  eluarpc_end_packet( p );
-}
-
-// Generic read function
-// Specifiers: o - operation
-//             r - response
-//             c - u8
-//             h - u16
-//             l - u32
-//             L - s32
-//             i - int
-//             p - ptr (returned as ptr, len, len is an u32)
-//             P - ptr (returned as ptr, len, len is an u16)
-int eluarpc_gen_read( const u8 *p, const char *fmt, ... )
-{
-  va_list ap;
-  const void *pptr;
-  u32 *ptrlen;
-  const u8 *tempptr;
-  u32 temp32;
-  u16 temp16;
-  u16 *sptrlen;
-  
-  va_start( ap, fmt );
-  eluarpc_err_flag = ELUARPC_OK;
-  p = eluarpc_match_packet_start( p );
-  while( *fmt )
-    switch( *fmt ++ )
-    {
-      case 'o':
-        p = eluarpc_expect_op_id( p, va_arg( ap, int ) );
-        break;
-        
-      case 'r':
-        p = eluarpc_read_expect( p, ELUARPC_OP_RES_MOD | ( u8 )va_arg( ap, int ) );
-        break;
-        
-      case 'c':
-        p = eluarpc_read_u8( p, ( u8* )va_arg( ap, void * ) );
-        break;
-        
-      case 'h':
-        p = eluarpc_read_u16( p, ( u16* )va_arg( ap, void * ) );
-        break;
-        
-      case 'l':
-        p = eluarpc_read_u32( p, ( u32* )va_arg( ap, void * ) );
-        break;     
-
-      case 'L':
-        p = eluarpc_read_u32( p, &temp32 );        
-        *( s32 *)va_arg( ap, void * ) = ( s32 )temp32;
-        break;     
-        
-      case 'i':
-        p = eluarpc_read_u32( p, &temp32 );
-        *( int* )va_arg( ap, void * ) = ( int )temp32;        
-        break;     
-      
-      case 'p':
-        pptr = va_arg( ap, void** );
-        ptrlen = ( u32* )va_arg( ap, void* );
-        tempptr = p;
-        p = eluarpc_read_ptr( p, NULL, &temp32 );
-        if( p == tempptr + ELUARPC_PTR_HEADER_SIZE )
-          *( const u8** )pptr = NULL;
-        else
-          *( const u8** )pptr = tempptr + ELUARPC_PTR_HEADER_SIZE;
-        if( ptrlen )
-          *ptrlen = temp32;        
-        break;
-        
-      case 'P':
-        pptr = va_arg( ap, void** );
-        sptrlen = ( u16* )va_arg( ap, void* );
-        tempptr = p;
-        p = eluarpc_read_small_ptr( p, NULL, &temp16 );
-        if( p == tempptr + ELUARPC_SMALL_PTR_HEADER_SIZE )
-          *( const u8** )pptr = NULL;
-        else
-          *( const u8** )pptr = tempptr + ELUARPC_SMALL_PTR_HEADER_SIZE;
-        if( sptrlen )
-          *sptrlen = temp16;        
-        break;        
-    }
-  eluarpc_match_packet_end( p );  
-  return eluarpc_err_flag;
-}
+// eLua RPC mechanism
+
+#include 
+#include 
+#include 
+#include "type.h"
+#include "eluarpc.h"
+#include "rtype.h"
+
+static u8 eluarpc_err_flag;
+
+// *****************************************************************************
+// Internal functions: fdata serialization
+
+static u8 *eluarpc_write_u8( u8 *p, u8 fdata )
+{
+  *p ++ = TYPE_INT_8;
+  *p ++ = fdata;
+  return p;  
+}
+
+static u8* eluarpc_write_op_id( u8 *p, u8 fdata )
+{
+  *p ++ = TYPE_OP_ID;
+  *p ++ = fdata;
+  return p;    
+}
+
+static u8 *eluarpc_write_u16( u8 *p, u16 fdata )
+{
+  *p ++ = TYPE_INT_16;
+  *p ++ = fdata & 0xFF;
+  *p ++ = ( fdata >> 8 ) & 0xFF;
+  return p;    
+}
+
+static u8 *eluarpc_write_u32( u8 *p, u32 fdata )
+{
+  *p ++ = TYPE_INT_32;
+  *p ++ = fdata & 0xFF;
+  *p ++ = ( fdata >> 8 ) & 0xFF;
+  *p ++ = ( fdata >> 16 ) & 0xFF;
+  *p ++ = ( fdata >> 24 ) & 0xFF;
+  return p;        
+}
+
+static u8 *eluarpc_write_ptr( u8 *p, const void* src, u32 srclen )
+{
+  *p ++ = TYPE_PTR;
+  p = eluarpc_write_u32( p, srclen );
+  if( src )
+    memcpy( p, src, srclen );
+  return p + srclen;    
+}
+
+static u8 *eluarpc_write_small_ptr( u8 *p, const void* src, u16 srclen )
+{
+  *p ++ = TYPE_SMALL_PTR;
+  p = eluarpc_write_u16( p, srclen );
+  if( src )
+    memcpy( p, src, srclen );
+  return p + srclen;    
+}
+
+// *****************************************************************************
+// Internal functions: fdata deserialization
+
+static const u8* eluarpc_read_expect( const u8 *p, u8 fdata )
+{
+  if( *p ++ != fdata )
+    eluarpc_err_flag = ELUARPC_ERR;
+  return p;
+}
+
+static const u8 *eluarpc_read_u8( const u8 *p, u8 *pfdata )
+{
+  p = eluarpc_read_expect( p, TYPE_INT_8 );
+  *pfdata = *p ++;
+  return p;  
+}
+
+static const u8 *eluarpc_read_op_id( const u8 *p, u8 *pfdata )
+{
+  p = eluarpc_read_expect( p, TYPE_OP_ID );
+  *pfdata = *p ++;
+  return p;  
+}
+
+static const u8* eluarpc_expect_op_id( const u8 *p, u8 id )
+{
+  u8 temp;
+  
+  p = eluarpc_read_expect( p, TYPE_OP_ID );
+  temp = *p ++;
+  if( temp != id )
+    eluarpc_err_flag = ELUARPC_ERR;
+  return p;
+}
+
+static const u8 *eluarpc_read_u16( const u8 *p, u16 *pfdata )
+{
+  p = eluarpc_read_expect( p, TYPE_INT_16 );
+  *pfdata = *p ++;
+  *pfdata |= ( u32 )( *p ++ ) << 8;  
+  return p;    
+}
+
+static const u8 *eluarpc_read_u32( const u8 *p, u32 *pfdata )
+{
+  p = eluarpc_read_expect( p, TYPE_INT_32 );
+  *pfdata = *p ++;                         
+  *pfdata |= ( u32 )( *p ++ ) << 8;
+  *pfdata |= ( u32 )( *p ++ ) << 16;
+  *pfdata |= ( u32 )( *p ++ ) << 24;      
+  return p;        
+}
+
+static const u8 *eluarpc_read_ptr( const u8 *p, void* src, u32 *psrclen )
+{                                         
+  p = eluarpc_read_expect( p, TYPE_PTR );
+  p = eluarpc_read_u32( p, psrclen );
+  if( src && p )
+    memcpy( src, p, *psrclen );
+  return p + *psrclen;    
+}
+
+static const u8 *eluarpc_read_small_ptr( const u8 *p, void* src, u16 *psrclen )
+{                                         
+  p = eluarpc_read_expect( p, TYPE_SMALL_PTR );
+  p = eluarpc_read_u16( p, psrclen );
+  if( src && p )
+    memcpy( src, p, *psrclen );
+  return p + *psrclen;    
+}
+
+
+// *****************************************************************************
+// Internal functions: packet handling (read and write)
+
+static u8* eluarpc_packet_ptr;
+
+static u8* eluarpc_start_packet( u8 *p )
+{
+  eluarpc_packet_ptr = p;
+  p += ELUARPC_START_OFFSET;
+  *p ++ = TYPE_START;
+  p = eluarpc_write_u32( p, PACKET_SIG );
+  return p;
+}
+
+static u8* eluarpc_end_packet( u8 *p )
+{
+  u16 len;
+  
+  *p ++ = TYPE_END;
+  p = eluarpc_write_u32( p, ~PACKET_SIG );
+  len = p - eluarpc_packet_ptr;
+  p = eluarpc_packet_ptr;
+  *p ++ = TYPE_PKT_SIZE;
+  eluarpc_write_u16( p, len );  
+  return p;  
+}
+
+static const u8* eluarpc_match_packet_start( const u8 *p )
+{
+  u32 fdata;
+  
+  p += ELUARPC_START_OFFSET;
+  p = eluarpc_read_expect( p, TYPE_START );
+  p = eluarpc_read_u32( p, &fdata );
+  if( fdata != PACKET_SIG )
+    eluarpc_err_flag = ELUARPC_ERR;
+  return p;
+}
+
+static const u8* eluarpc_match_packet_end( const u8 *p )
+{
+  u32 fdata;
+  
+  p = eluarpc_read_expect( p, TYPE_END );
+  p = eluarpc_read_u32( p, &fdata );
+  if( fdata != ~PACKET_SIG )
+    eluarpc_err_flag = ELUARPC_ERR;
+  return p;
+}
+
+// *****************************************************************************
+// Function serialization and deserialization
+
+int eluarpc_get_request_id( const u8 *p, u8 *pid )
+{ 
+  eluarpc_err_flag = ELUARPC_OK;
+  p = eluarpc_match_packet_start( p );
+  p = eluarpc_read_op_id( p, pid );
+  return eluarpc_err_flag;
+}
+
+u32 eluarpc_replace_flag( u32 val, u32 origflag, u32 newflag )
+{
+  return ( val & origflag ) ? newflag : 0; 
+}
+
+int eluarpc_get_packet_size( const u8 *p, u16 *psize )
+{
+  eluarpc_err_flag = ELUARPC_OK;
+  p = eluarpc_read_expect( p, TYPE_PKT_SIZE );
+  p = eluarpc_read_u16( p, psize );
+  return eluarpc_err_flag;
+}
+
+// Generic write function
+// Specifiers: o - operation
+//             r - response
+//             c - u8
+//             h - u16
+//             l - u32
+//             i - int
+//             L - s32
+//             p - ptr (given as ptr, len, len is an u32)
+//             P - ptr (given as ptr, len, len is an u16)
+void eluarpc_gen_write( u8 *p, const char *fmt, ... )
+{
+  va_list ap;
+  const void *ptr;
+  u32 ptrlen;
+  
+  va_start( ap, fmt );
+  p = eluarpc_start_packet( p );
+  while( *fmt )
+    switch( *fmt ++ )
+    {
+      case 'o':
+        p = eluarpc_write_op_id( p, va_arg( ap, int ) );
+        break;
+        
+      case 'r':
+        *p++ = ELUARPC_OP_RES_MOD | ( u8 )va_arg( ap, int );
+        break;
+        
+      case 'c':
+        p = eluarpc_write_u8( p, ( u8 )va_arg( ap, int ) );
+        break;
+        
+      case 'h':
+        p = eluarpc_write_u16( p, ( u16 )va_arg( ap, int ) );
+        break;
+
+      case 'i':
+        p = eluarpc_write_u32( p, ( u32 )va_arg( ap, int ) );
+        break;
+        
+      case 'l':
+        p = eluarpc_write_u32( p, ( u32 )va_arg( ap, u32 ) );
+        break;
+
+      case 'L':
+        p = eluarpc_write_u32( p, ( u32 )va_arg( ap, s32 ) );
+        break;         
+      
+      case 'p':
+        ptr = va_arg( ap, void* );
+        ptrlen = ( u32 )va_arg( ap, u32 );
+        p = eluarpc_write_ptr( p, ptr, ptrlen );
+        break;
+        
+      case 'P':
+        ptr = va_arg( ap, void * );
+        ptrlen = ( u16 )va_arg( ap, int );
+        p = eluarpc_write_small_ptr( p, ptr, ptrlen );
+        break;        
+    }
+  eluarpc_end_packet( p );
+}
+
+// Generic read function
+// Specifiers: o - operation
+//             r - response
+//             c - u8
+//             h - u16
+//             l - u32
+//             L - s32
+//             i - int
+//             p - ptr (returned as ptr, len, len is an u32)
+//             P - ptr (returned as ptr, len, len is an u16)
+int eluarpc_gen_read( const u8 *p, const char *fmt, ... )
+{
+  va_list ap;
+  const void *pptr;
+  u32 *ptrlen;
+  const u8 *tempptr;
+  u32 temp32;
+  u16 temp16;
+  u16 *sptrlen;
+  
+  va_start( ap, fmt );
+  eluarpc_err_flag = ELUARPC_OK;
+  p = eluarpc_match_packet_start( p );
+  while( *fmt )
+    switch( *fmt ++ )
+    {
+      case 'o':
+        p = eluarpc_expect_op_id( p, va_arg( ap, int ) );
+        break;
+        
+      case 'r':
+        p = eluarpc_read_expect( p, ELUARPC_OP_RES_MOD | ( u8 )va_arg( ap, int ) );
+        break;
+        
+      case 'c':
+        p = eluarpc_read_u8( p, ( u8* )va_arg( ap, void * ) );
+        break;
+        
+      case 'h':
+        p = eluarpc_read_u16( p, ( u16* )va_arg( ap, void * ) );
+        break;
+        
+      case 'l':
+        p = eluarpc_read_u32( p, ( u32* )va_arg( ap, void * ) );
+        break;     
+
+      case 'L':
+        p = eluarpc_read_u32( p, &temp32 );        
+        *( s32 *)va_arg( ap, void * ) = ( s32 )temp32;
+        break;     
+        
+      case 'i':
+        p = eluarpc_read_u32( p, &temp32 );
+        *( int* )va_arg( ap, void * ) = ( int )temp32;        
+        break;     
+      
+      case 'p':
+        pptr = va_arg( ap, void** );
+        ptrlen = ( u32* )va_arg( ap, void* );
+        tempptr = p;
+        p = eluarpc_read_ptr( p, NULL, &temp32 );
+        if( p == tempptr + ELUARPC_PTR_HEADER_SIZE )
+          *( const u8** )pptr = NULL;
+        else
+          *( const u8** )pptr = tempptr + ELUARPC_PTR_HEADER_SIZE;
+        if( ptrlen )
+          *ptrlen = temp32;        
+        break;
+        
+      case 'P':
+        pptr = va_arg( ap, void** );
+        sptrlen = ( u16* )va_arg( ap, void* );
+        tempptr = p;
+        p = eluarpc_read_small_ptr( p, NULL, &temp16 );
+        if( p == tempptr + ELUARPC_SMALL_PTR_HEADER_SIZE )
+          *( const u8** )pptr = NULL;
+        else
+          *( const u8** )pptr = tempptr + ELUARPC_SMALL_PTR_HEADER_SIZE;
+        if( sptrlen )
+          *sptrlen = temp16;        
+        break;        
+    }
+  eluarpc_match_packet_end( p );  
+  return eluarpc_err_flag;
+}
diff --git a/src/fatfs/diskio.h b/src/fatfs/diskio.h
index 4e21e529..6fde2dde 100644
--- a/src/fatfs/diskio.h
+++ b/src/fatfs/diskio.h
@@ -34,7 +34,6 @@ DRESULT disk_read (BYTE, BYTE*, DWORD, BYTE);
 DRESULT disk_write (BYTE, const BYTE*, DWORD, BYTE);
 #endif
 DRESULT disk_ioctl (BYTE, BYTE, void*);
-void	disk_timerproc (void);
 
 
 
diff --git a/src/linenoise.c b/src/linenoise.c
index 843e707a..fb415830 100644
--- a/src/linenoise.c
+++ b/src/linenoise.c
@@ -414,9 +414,9 @@ int linenoise_savehistory( int id, const char *filename )
 int linenoise_getline( int id, char* buffer, int maxinput, const char* prompt )
 {
   ( void )id;
-	fputs( prompt, stdout );
+  fputs( prompt, stdout );
   fflush( stdout );
-	return fgets( buffer, maxinput, stdin ) == NULL ? -1 : 0;
+  return fgets( buffer, maxinput, stdin ) == NULL ? -1 : 0;
 }
 
 int linenoise_addhistory( int id, const char *line )
diff --git a/src/linenoise_posix.c b/src/linenoise_posix.c
new file mode 100644
index 00000000..2ddce3ff
--- /dev/null
+++ b/src/linenoise_posix.c
@@ -0,0 +1,612 @@
+/* linenoise.c -- guerrilla line editing library against the idea that a
+ * line editing lib needs to be 20,000 lines of C code.
+ *
+ * You can find the latest source code at:
+ * 
+ *   http://github.com/antirez/linenoise
+ *
+ * Does a number of crazy assumptions that happen to be true in 99.9999% of
+ * the 2010 UNIX computers around.
+ *
+ * ------------------------------------------------------------------------
+ *
+ * Copyright (c) 2010, Salvatore Sanfilippo 
+ * Copyright (c) 2010, Pieter Noordhuis 
+ *
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * 
+ *  *  Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *  *  Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in the
+ *     documentation and/or other materials provided with the distribution.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ------------------------------------------------------------------------
+ *
+ * References:
+ * - http://invisible-island.net/xterm/ctlseqs/ctlseqs.html
+ * - http://www.3waylabs.com/nw/WWW/products/wizcon/vt220.html
+ *
+ * Todo list:
+ * - Switch to gets() if $TERM is something we can't support.
+ * - Filter bogus Ctrl+ combinations.
+ * - Win32 support
+ *
+ * Bloat:
+ * - Completion?
+ * - History search like Ctrl+r in readline?
+ *
+ * List of escape sequences used by this program, we do everything just
+ * with three sequences. In order to be so cheap we may have some
+ * flickering effect with some slow terminal, but the lesser sequences
+ * the more compatible.
+ *
+ * CHA (Cursor Horizontal Absolute)
+ *    Sequence: ESC [ n G
+ *    Effect: moves cursor to column n
+ *
+ * EL (Erase Line)
+ *    Sequence: ESC [ n K
+ *    Effect: if n is 0 or missing, clear from cursor to end of line
+ *    Effect: if n is 1, clear from beginning of line to cursor
+ *    Effect: if n is 2, clear entire line
+ *
+ * CUF (CUrsor Forward)
+ *    Sequence: ESC [ n C
+ *    Effect: moves cursor forward of n chars
+ *
+ * The following are used to clear the screen: ESC [ H ESC [ 2 J
+ * This is actually composed of two sequences:
+ *
+ * cursorhome
+ *    Sequence: ESC [ H
+ *    Effect: moves the cursor to upper left corner
+ *
+ * ED2 (Clear entire screen)
+ *    Sequence: ESC [ 2 J
+ *    Effect: clear the whole screen
+ * 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "linenoise_posix.h"
+
+#define LINENOISE_DEFAULT_HISTORY_MAX_LEN 100
+#define LINENOISE_MAX_LINE 4096
+static char *unsupported_term[] = {"dumb","cons25",NULL};
+static linenoiseCompletionCallback *completionCallback = NULL;
+
+static struct termios orig_termios; /* in order to restore at exit */
+static int rawmode = 0; /* for atexit() function to check if restore is needed*/
+static int atexit_registered = 0; /* register atexit just 1 time */
+static int history_max_len = LINENOISE_DEFAULT_HISTORY_MAX_LEN;
+static int history_len = 0;
+char **history = NULL;
+
+static void linenoiseAtExit(void);
+int linenoiseHistoryAdd(const char *line);
+
+static int isUnsupportedTerm(void) {
+    char *term = getenv("TERM");
+    int j;
+
+    if (term == NULL) return 0;
+    for (j = 0; unsupported_term[j]; j++)
+        if (!strcasecmp(term,unsupported_term[j])) return 1;
+    return 0;
+}
+
+static void freeHistory(void) {
+    if (history) {
+        int j;
+
+        for (j = 0; j < history_len; j++)
+            free(history[j]);
+        free(history);
+    }
+}
+
+static int enableRawMode(int fd) {
+    struct termios raw;
+
+    if (!isatty(STDIN_FILENO)) goto fatal;
+    if (!atexit_registered) {
+        atexit(linenoiseAtExit);
+        atexit_registered = 1;
+    }
+    if (tcgetattr(fd,&orig_termios) == -1) goto fatal;
+
+    raw = orig_termios;  /* modify the original mode */
+    /* input modes: no break, no CR to NL, no parity check, no strip char,
+     * no start/stop output control. */
+    raw.c_iflag &= ~(BRKINT | ICRNL | INPCK | ISTRIP | IXON);
+    /* output modes - disable post processing */
+    raw.c_oflag &= ~(OPOST);
+    /* control modes - set 8 bit chars */
+    raw.c_cflag |= (CS8);
+    /* local modes - choing off, canonical off, no extended functions,
+     * no signal chars (^Z,^C) */
+    raw.c_lflag &= ~(ECHO | ICANON | IEXTEN | ISIG);
+    /* control chars - set return condition: min number of bytes and timer.
+     * We want read to return every single byte, without timeout. */
+    raw.c_cc[VMIN] = 1; raw.c_cc[VTIME] = 0; /* 1 byte, no timer */
+
+    /* put terminal in raw mode after flushing */
+    if (tcsetattr(fd,TCSAFLUSH,&raw) < 0) goto fatal;
+    rawmode = 1;
+    return 0;
+
+fatal:
+    errno = ENOTTY;
+    return -1;
+}
+
+static void disableRawMode(int fd) {
+    /* Don't even check the return value as it's too late. */
+    if (rawmode && tcsetattr(fd,TCSAFLUSH,&orig_termios) != -1)
+        rawmode = 0;
+}
+
+/* At exit we'll try to fix the terminal to the initial conditions. */
+static void linenoiseAtExit(void) {
+    disableRawMode(STDIN_FILENO);
+    freeHistory();
+}
+
+static int getColumns(void) {
+    struct winsize ws;
+
+    if (ioctl(1, TIOCGWINSZ, &ws) == -1) return 80;
+    return ws.ws_col;
+}
+
+static void refreshLine(int fd, const char *prompt, char *buf, size_t len, size_t pos, size_t cols) {
+    char seq[64];
+    size_t plen = strlen(prompt);
+    
+    while((plen+pos) >= cols) {
+        buf++;
+        len--;
+        pos--;
+    }
+    while (plen+len > cols) {
+        len--;
+    }
+
+    /* Cursor to left edge */
+    snprintf(seq,64,"\x1b[0G");
+    if (write(fd,seq,strlen(seq)) == -1) return;
+    /* Write the prompt and the current buffer content */
+    if (write(fd,prompt,strlen(prompt)) == -1) return;
+    if (write(fd,buf,len) == -1) return;
+    /* Erase to right */
+    snprintf(seq,64,"\x1b[0K");
+    if (write(fd,seq,strlen(seq)) == -1) return;
+    /* Move cursor to original position. */
+    snprintf(seq,64,"\x1b[0G\x1b[%dC", (int)(pos+plen));
+    if (write(fd,seq,strlen(seq)) == -1) return;
+}
+
+static void beep() {
+    fprintf(stderr, "\x7");
+    fflush(stderr);
+}
+
+static void freeCompletions(linenoiseCompletions *lc) {
+    size_t i;
+    for (i = 0; i < lc->len; i++)
+        free(lc->cvec[i]);
+    if (lc->cvec != NULL)
+        free(lc->cvec);
+}
+
+static int completeLine(int fd, const char *prompt, char *buf, size_t buflen, size_t *len, size_t *pos, size_t cols) {
+    linenoiseCompletions lc = { 0, NULL };
+    int nread, nwritten;
+    char c = 0;
+
+    completionCallback(buf,&lc);
+    if (lc.len == 0) {
+        beep();
+    } else {
+        size_t stop = 0, i = 0;
+        size_t clen;
+
+        while(!stop) {
+            /* Show completion or original buffer */
+            if (i < lc.len) {
+                clen = strlen(lc.cvec[i]);
+                refreshLine(fd,prompt,lc.cvec[i],clen,clen,cols);
+            } else {
+                refreshLine(fd,prompt,buf,*len,*pos,cols);
+            }
+
+            nread = read(fd,&c,1);
+            if (nread <= 0) {
+                freeCompletions(&lc);
+                return -1;
+            }
+
+            switch(c) {
+                case 9: /* tab */
+                    i = (i+1) % (lc.len+1);
+                    if (i == lc.len) beep();
+                    break;
+                case 27: /* escape */
+                    /* Re-show original buffer */
+                    if (i < lc.len) {
+                        refreshLine(fd,prompt,buf,*len,*pos,cols);
+                    }
+                    stop = 1;
+                    break;
+                default:
+                    /* Update buffer and return */
+                    if (i < lc.len) {
+                        nwritten = snprintf(buf,buflen,"%s",lc.cvec[i]);
+                        *len = *pos = nwritten;
+                    }
+                    stop = 1;
+                    break;
+            }
+        }
+    }
+
+    freeCompletions(&lc);
+    return c; /* Return last read character */
+}
+
+void linenoiseClearScreen(void) {
+    if (write(STDIN_FILENO,"\x1b[H\x1b[2J",7) <= 0) {
+        /* nothing to do, just to avoid warning. */
+    }
+}
+
+static int linenoisePrompt(int fd, char *buf, size_t buflen, const char *prompt) {
+    size_t plen = strlen(prompt);
+    size_t pos = 0;
+    size_t len = 0;
+    size_t cols = getColumns();
+    int history_index = 0;
+
+    buf[0] = '\0';
+    buflen--; /* Make sure there is always space for the nulterm */
+
+    /* The latest history entry is always our current buffer, that
+     * initially is just an empty string. */
+    linenoiseHistoryAdd("");
+    
+    if (write(fd,prompt,plen) == -1) return -1;
+    while(1) {
+        char c;
+        int nread;
+        char seq[2], seq2[2];
+
+        nread = read(fd,&c,1);
+        if (nread <= 0) return len;
+
+        /* Only autocomplete when the callback is set. It returns < 0 when
+         * there was an error reading from fd. Otherwise it will return the
+         * character that should be handled next. */
+        if (c == 9 && completionCallback != NULL) {
+            c = completeLine(fd,prompt,buf,buflen,&len,&pos,cols);
+            /* Return on errors */
+            if (c < 0) return len;
+            /* Read next character when 0 */
+            if (c == 0) continue;
+        }
+
+        switch(c) {
+        case 13:    /* enter */
+            history_len--;
+            free(history[history_len]);
+            return (int)len;
+        case 3:     /* ctrl-c */
+            errno = EAGAIN;
+            return -1;
+        case 127:   /* backspace */
+        case 8:     /* ctrl-h */
+            if (pos > 0 && len > 0) {
+                memmove(buf+pos-1,buf+pos,len-pos);
+                pos--;
+                len--;
+                buf[len] = '\0';
+                refreshLine(fd,prompt,buf,len,pos,cols);
+            }
+            break;
+        case 4:     /* ctrl-d, remove char at right of cursor */
+            if (len > 1 && pos < (len-1)) {
+                memmove(buf+pos,buf+pos+1,len-pos);
+                len--;
+                buf[len] = '\0';
+                refreshLine(fd,prompt,buf,len,pos,cols);
+            } else if (len == 0) {
+                history_len--;
+                free(history[history_len]);
+                return -1;
+            }
+            break;
+        case 20:    /* ctrl-t */
+            if (pos > 0 && pos < len) {
+                int aux = buf[pos-1];
+                buf[pos-1] = buf[pos];
+                buf[pos] = aux;
+                if (pos != len-1) pos++;
+                refreshLine(fd,prompt,buf,len,pos,cols);
+            }
+            break;
+        case 2:     /* ctrl-b */
+            goto left_arrow;
+        case 6:     /* ctrl-f */
+            goto right_arrow;
+        case 16:    /* ctrl-p */
+            seq[1] = 65;
+            goto up_down_arrow;
+        case 14:    /* ctrl-n */
+            seq[1] = 66;
+            goto up_down_arrow;
+            break;
+        case 27:    /* escape sequence */
+            if (read(fd,seq,2) == -1) break;
+            if (seq[0] == 91 && seq[1] == 68) {
+left_arrow:
+                /* left arrow */
+                if (pos > 0) {
+                    pos--;
+                    refreshLine(fd,prompt,buf,len,pos,cols);
+                }
+            } else if (seq[0] == 91 && seq[1] == 67) {
+right_arrow:
+                /* right arrow */
+                if (pos != len) {
+                    pos++;
+                    refreshLine(fd,prompt,buf,len,pos,cols);
+                }
+            } else if (seq[0] == 91 && (seq[1] == 65 || seq[1] == 66)) {
+up_down_arrow:
+                /* up and down arrow: history */
+                if (history_len > 1) {
+                    /* Update the current history entry before to
+                     * overwrite it with tne next one. */
+                    free(history[history_len-1-history_index]);
+                    history[history_len-1-history_index] = strdup(buf);
+                    /* Show the new entry */
+                    history_index += (seq[1] == 65) ? 1 : -1;
+                    if (history_index < 0) {
+                        history_index = 0;
+                        break;
+                    } else if (history_index >= history_len) {
+                        history_index = history_len-1;
+                        break;
+                    }
+                    strncpy(buf,history[history_len-1-history_index],buflen);
+                    buf[buflen] = '\0';
+                    len = pos = strlen(buf);
+                    refreshLine(fd,prompt,buf,len,pos,cols);
+                }
+            } else if (seq[0] == 91 && seq[1] > 48 && seq[1] < 55) {
+                /* extended escape */
+                if (read(fd,seq2,2) == -1) break;
+                if (seq[1] == 51 && seq2[0] == 126) {
+                    /* delete */
+                    if (len > 0 && pos < len) {
+                        memmove(buf+pos,buf+pos+1,len-pos-1);
+                        len--;
+                        buf[len] = '\0';
+                        refreshLine(fd,prompt,buf,len,pos,cols);
+                    }
+                }
+            }
+            break;
+        default:
+            if (len < buflen) {
+                if (len == pos) {
+                    buf[pos] = c;
+                    pos++;
+                    len++;
+                    buf[len] = '\0';
+                    if (plen+len < cols) {
+                        /* Avoid a full update of the line in the
+                         * trivial case. */
+                        if (write(fd,&c,1) == -1) return -1;
+                    } else {
+                        refreshLine(fd,prompt,buf,len,pos,cols);
+                    }
+                } else {
+                    memmove(buf+pos+1,buf+pos,len-pos);
+                    buf[pos] = c;
+                    len++;
+                    pos++;
+                    buf[len] = '\0';
+                    refreshLine(fd,prompt,buf,len,pos,cols);
+                }
+            }
+            break;
+        case 21: /* Ctrl+u, delete the whole line. */
+            buf[0] = '\0';
+            pos = len = 0;
+            refreshLine(fd,prompt,buf,len,pos,cols);
+            break;
+        case 11: /* Ctrl+k, delete from current to end of line. */
+            buf[pos] = '\0';
+            len = pos;
+            refreshLine(fd,prompt,buf,len,pos,cols);
+            break;
+        case 1: /* Ctrl+a, go to the start of the line */
+            pos = 0;
+            refreshLine(fd,prompt,buf,len,pos,cols);
+            break;
+        case 5: /* ctrl+e, go to the end of the line */
+            pos = len;
+            refreshLine(fd,prompt,buf,len,pos,cols);
+            break;
+        case 12: /* ctrl+l, clear screen */
+            linenoiseClearScreen();
+            refreshLine(fd,prompt,buf,len,pos,cols);
+        }
+    }
+    return len;
+}
+
+static int linenoiseRaw(char *buf, size_t buflen, const char *prompt) {
+    int fd = STDIN_FILENO;
+    int count;
+
+    if (buflen == 0) {
+        errno = EINVAL;
+        return -1;
+    }
+    if (!isatty(STDIN_FILENO)) {
+        if (fgets(buf, buflen, stdin) == NULL) return -1;
+        count = strlen(buf);
+        if (count && buf[count-1] == '\n') {
+            count--;
+            buf[count] = '\0';
+        }
+    } else {
+        if (enableRawMode(fd) == -1) return -1;
+        count = linenoisePrompt(fd, buf, buflen, prompt);
+        disableRawMode(fd);
+        printf("\n");
+    }
+    return count;
+}
+
+char *linenoise(const char *prompt) {
+    char buf[LINENOISE_MAX_LINE];
+    int count;
+
+    if (isUnsupportedTerm()) {
+        size_t len;
+
+        printf("%s",prompt);
+        fflush(stdout);
+        if (fgets(buf,LINENOISE_MAX_LINE,stdin) == NULL) return NULL;
+        len = strlen(buf);
+        while(len && (buf[len-1] == '\n' || buf[len-1] == '\r')) {
+            len--;
+            buf[len] = '\0';
+        }
+        return strdup(buf);
+    } else {
+        count = linenoiseRaw(buf,LINENOISE_MAX_LINE,prompt);
+        if (count == -1) return NULL;
+        return strdup(buf);
+    }
+}
+
+/* Register a callback function to be called for tab-completion. */
+void linenoiseSetCompletionCallback(linenoiseCompletionCallback *fn) {
+    completionCallback = fn;
+}
+
+void linenoiseAddCompletion(linenoiseCompletions *lc, char *str) {
+    size_t len = strlen(str);
+    char *copy = malloc(len+1);
+    memcpy(copy,str,len+1);
+    lc->cvec = realloc(lc->cvec,sizeof(char*)*(lc->len+1));
+    lc->cvec[lc->len++] = copy;
+}
+
+/* Using a circular buffer is smarter, but a bit more complex to handle. */
+int linenoiseHistoryAdd(const char *line) {
+    char *linecopy;
+
+    if (history_max_len == 0) return 0;
+    if (history == NULL) {
+        history = malloc(sizeof(char*)*history_max_len);
+        if (history == NULL) return 0;
+        memset(history,0,(sizeof(char*)*history_max_len));
+    }
+    linecopy = strdup(line);
+    if (!linecopy) return 0;
+    if (history_len == history_max_len) {
+        free(history[0]);
+        memmove(history,history+1,sizeof(char*)*(history_max_len-1));
+        history_len--;
+    }
+    history[history_len] = linecopy;
+    history_len++;
+    return 1;
+}
+
+int linenoiseHistorySetMaxLen(int len) {
+    char **new;
+
+    if (len < 1) return 0;
+    if (history) {
+        int tocopy = history_len;
+
+        new = malloc(sizeof(char*)*len);
+        if (new == NULL) return 0;
+        if (len < tocopy) tocopy = len;
+        memcpy(new,history+(history_max_len-tocopy), sizeof(char*)*tocopy);
+        free(history);
+        history = new;
+    }
+    history_max_len = len;
+    if (history_len > history_max_len)
+        history_len = history_max_len;
+    return 1;
+}
+
+/* Save the history in the specified file. On success 0 is returned
+ * otherwise -1 is returned. */
+int linenoiseHistorySave(char *filename) {
+    FILE *fp = fopen(filename,"w");
+    int j;
+    
+    if (fp == NULL) return -1;
+    for (j = 0; j < history_len; j++)
+        fprintf(fp,"%s\n",history[j]);
+    fclose(fp);
+    return 0;
+}
+
+/* Load the history from the specified file. If the file does not exist
+ * zero is returned and no operation is performed.
+ *
+ * If the file exists and the operation succeeded 0 is returned, otherwise
+ * on error -1 is returned. */
+int linenoiseHistoryLoad(char *filename) {
+    FILE *fp = fopen(filename,"r");
+    char buf[LINENOISE_MAX_LINE];
+    
+    if (fp == NULL) return -1;
+
+    while (fgets(buf,LINENOISE_MAX_LINE,fp) != NULL) {
+        char *p;
+        
+        p = strchr(buf,'\r');
+        if (!p) p = strchr(buf,'\n');
+        if (p) *p = '\0';
+        linenoiseHistoryAdd(buf);
+    }
+    fclose(fp);
+    return 0;
+}
diff --git a/src/lua/ldump.c b/src/lua/ldump.c
index 6076d85b..283aa12c 100644
--- a/src/lua/ldump.c
+++ b/src/lua/ldump.c
@@ -51,7 +51,7 @@ static void MaybeByteSwap(char *number, size_t numbersize, DumpState *D)
  int platform_little_endian = *(char*)&x;
  if (platform_little_endian != D->target.little_endian)
  {
-  int i;
+  unsigned long i;
   for (i=0; itarget.sizeof_int,D);
 }
 
-static void DumpSize(int32_t x, DumpState* D)
+static void DumpSize(uint32_t x, DumpState* D)
 {
  /* dump unsigned integer */
  switch(D->target.sizeof_strsize_t) {
@@ -179,7 +179,7 @@ static void DumpString(const TString* s, DumpState* D)
  }
  else
  {
-  strsize_t size=s->tsv.len+1;		/* include trailing '\0' */
+  strsize_t size=( strsize_t )s->tsv.len+1;		/* include trailing '\0' */
   DumpSize(size,D);
   DumpBlock(getstr(s),size,D);
  }
diff --git a/src/lua/lmathlib.c b/src/lua/lmathlib.c
index b8731e4e..b6a12867 100644
--- a/src/lua/lmathlib.c
+++ b/src/lua/lmathlib.c
@@ -34,6 +34,8 @@ static int math_abs (lua_State *L) {
   return 1;
 }
 
+#ifndef LUA_NUMBER_INTEGRAL
+
 static int math_sin (lua_State *L) {
   lua_pushnumber(L, sin(luaL_checknumber(L, 1)));
   return 1;
@@ -107,6 +109,20 @@ static int math_modf (lua_State *L) {
   return 2;
 }
 
+#else  // #ifndef LUA_NUMBER_INTEGRAL
+
+// In integer math, floor() and ceil() give the same value;
+// having them in the integer library allows you to write code that
+// works in both integer and floating point versions of Lua.
+// This identity function is used for them.
+
+static int math_identity (lua_State *L) {
+  lua_pushnumber(L, luaL_checknumber(L, 1));
+  return 1;
+}
+
+#endif // #ifndef LUA_NUMBER_INTEGRAL
+
 #ifdef LUA_NUMBER_INTEGRAL
 // Integer square root for integer version
 static lua_Number isqrt(lua_Number x)
@@ -142,6 +158,8 @@ static int math_sqrt (lua_State *L) {
   return 1;
 }
 
+#ifndef LUA_NUMBER_INTEGRAL
+
 static int math_pow (lua_State *L) {
   lua_pushnumber(L, pow(luaL_checknumber(L, 1), luaL_checknumber(L, 2)));
   return 1;
@@ -184,7 +202,7 @@ static int math_ldexp (lua_State *L) {
   return 1;
 }
 
-
+#endif // #ifdef LUA_NUMBER_INTEGRAL
 
 static int math_min (lua_State *L) {
   int n = lua_gettop(L);  /* number of arguments */
@@ -284,6 +302,8 @@ static int math_randomseed (lua_State *L) {
 const LUA_REG_TYPE math_map[] = {
 #ifdef LUA_NUMBER_INTEGRAL
   {LSTRKEY("abs"),   LFUNCVAL(math_abs)},
+  {LSTRKEY("ceil"),  LFUNCVAL(math_identity)},
+  {LSTRKEY("floor"), LFUNCVAL(math_identity)},
   {LSTRKEY("max"),   LFUNCVAL(math_max)},
   {LSTRKEY("min"),   LFUNCVAL(math_min)},
   {LSTRKEY("random"),     LFUNCVAL(math_random)},
diff --git a/src/lua/luaconf.h b/src/lua/luaconf.h
index 98a33ca5..5e9dca21 100644
--- a/src/lua/luaconf.h
+++ b/src/lua/luaconf.h
@@ -160,8 +160,12 @@
 #if !defined LUA_NUMBER_INTEGRAL
 #define LUA_INTEGER ptrdiff_t
 #else
-#define LUA_INTEGER	long
-#endif
+  #if !defined LUA_INTEGRAL_LONGLONG
+  #define LUA_INTEGER	long
+  #else
+  #define LUA_INTEGER long long
+  #endif // #if !defined LUA_INTEGRAL_LONGLONG
+#endif // #if !defined LUA_NUMBER_INTEGRAL
 
 /*
 @@ LUA_API is a mark for all core API functions.
@@ -300,6 +304,13 @@
 	if (lua_strlen(L,idx) > 0)  /* non-empty line? */ \
 	  add_history(lua_tostring(L, idx));  /* add it to history */
 #define lua_freeline(L,b)	((void)L, free(b))
+#elif defined(LUA_USE_LINENOISE) // #if defined(LUA_USE_READLINE)
+#include "linenoise_posix.h"
+#define lua_readline(L,b,p)     ((void)L, ((b)=linenoise(p)) != NULL)
+#define lua_saveline(L,idx) \
+  if (lua_strlen(L,idx) > 0)  /* non-empty line? */ \
+    linenoiseHistoryAdd(lua_tostring(L, idx));  /* add it to history */
+#define lua_freeline(L,b)       ((void)L, free(b))
 #else // #if defined(LUA_USE_READLINE)
 #define lua_readline(L,b,p)	\
 	((void)L, fputs(p, stdout), fflush(stdout),  /* show prompt */ \
@@ -511,7 +522,7 @@
 @@ LUAI_MAXUPVALUES is the maximum number of upvalues per function
 @* (must be smaller than 250).
 */
-#define LUAI_MAXUPVALUES	10
+#define LUAI_MAXUPVALUES	60
 
 
 /*
@@ -546,7 +557,7 @@
    %G. */
 
 #if defined LUA_NUMBER_INTEGRAL
-#define LUA_NUMBER	long
+#define LUA_NUMBER	LUA_INTEGER
 #else
 #define LUA_NUMBER_DOUBLE
 #define LUA_NUMBER	double
@@ -567,20 +578,28 @@
 @@ lua_str2number converts a string to a number.
 */
 #if defined LUA_NUMBER_INTEGRAL
-#define LUA_NUMBER_SCAN		"%ld"
-#define LUA_NUMBER_FMT		"%ld"
+  #if !defined LUA_INTEGRAL_LONGLONG
+  #define LUA_NUMBER_SCAN		"%ld"
+  #define LUA_NUMBER_FMT		"%ld"
+  #else
+  #define LUA_NUMBER_SCAN   "%lld"
+  #define LUA_NUMBER_FMT    "%lld"
+  #endif // #if !defined LUA_INTEGRAL_LONGLONG
 #else
 #define LUA_NUMBER_SCAN		"%lf"
 #define LUA_NUMBER_FMT		"%.14g"
-#endif
+#endif // #if defined LUA_NUMBER_INTEGRAL
 #define lua_number2str(s,n)	sprintf((s), LUA_NUMBER_FMT, (n))
 #define LUAI_MAXNUMBER2STR	32 /* 16 digits, sign, point, and \0 */
 #if defined LUA_NUMBER_INTEGRAL
-#define lua_str2number(s,p)	strtol((s), (p), 10)
+  #if !defined LUA_INTEGRAL_LONGLONG
+  #define lua_str2number(s,p)	strtol((s), (p), 10)
+  #else
+  #define lua_str2number(s,p) strtoll((s), (p), 10)
+  #endif // #if !defined LUA_INTEGRAL_LONGLONG
 #else
 #define lua_str2number(s,p)	strtod((s), (p))
-#endif
-
+#endif // #if defined LUA_NUMBER_INTEGRAL
 
 /*
 @@ The luai_num* macros define the primitive operations over numbers.
@@ -820,7 +839,7 @@ union luai_Cast { double l_d; long l_l; };
 ** CHANGE them if your system supports long long or does not support long.
 */
 
-#if defined(LUA_USELONGLONG)
+#if defined(LUA_USELONGLONG) || defined(LUA_INTEGRAL_LONGLONG)
 
 #define LUA_INTFRMLEN		"ll"
 #define LUA_INTFRM_T		long long
diff --git a/src/luarpc_desktop_serial.c b/src/luarpc_desktop_serial.c
index b3f2960a..3d8de2fd 100644
--- a/src/luarpc_desktop_serial.c
+++ b/src/luarpc_desktop_serial.c
@@ -82,7 +82,7 @@ void transport_accept (Transport *tpt, Transport *atpt)
 // Read & Write to Transport
 void transport_read_buffer (Transport *tpt, u8 *buffer, int length)
 {
-  u32 n;
+  int n;
   struct exception e;
   TRANSPORT_VERIFY_OPEN;
   
diff --git a/src/luarpc_elua_uart.c b/src/luarpc_elua_uart.c
index 824afb09..fab41de3 100644
--- a/src/luarpc_elua_uart.c
+++ b/src/luarpc_elua_uart.c
@@ -7,18 +7,32 @@
 
 #if defined( BUILD_RPC )
 
-// Setup Transport
-void transport_init (Transport *tpt)
+// Buffer for async dispatch
+int adispatch_buff = -1;
+
+void set_adispatch_buff( int i )
 {
-	tpt->fd = INVALID_TRANSPORT;
+  adispatch_buff = i;
+}
+
+// Setup Transport
+void transport_init( Transport *tpt )
+{
+  tpt->fd = INVALID_TRANSPORT;
   tpt->tmr_id = 0;
 }
 
-// Open Listener / Server
-void transport_open_listener(lua_State *L, ServerHandle *handle)
+// Read a char from serial buffer
+int transport_get_char(Transport *t)
 {
-	// Get args & Set up connection
-	unsigned uart_id, tmr_id;
+  return platform_uart_recv( t->fd, t->tmr_id, 0 );
+}
+
+// Open Listener / Server
+void transport_open_listener( lua_State *L, ServerHandle *handle )
+{
+  // Get args & Set up connection
+  unsigned uart_id, tmr_id;
   
   check_num_args( L,3 ); // 1st arg is uart num, 2nd arg is tmr_id, 3nd is handle
   if ( !lua_isnumber( L, 1 ) ) 
@@ -36,15 +50,18 @@ void transport_open_listener(lua_State *L, ServerHandle *handle)
   if( !platform_timer_exists( tmr_id ) )
     luaL_error( L, "invalid timer id" );
   
-	handle->ltpt.fd = ( int )uart_id;
-	handle->ltpt.tmr_id = tmr_id;
+  handle->ltpt.fd = ( int )uart_id;
+  handle->ltpt.tmr_id = tmr_id;
+
+  // Setup uart
+  platform_uart_setup( (unsigned int) uart_id, 115200, 8, PLATFORM_UART_PARITY_NONE, PLATFORM_UART_STOPBITS_1 );
 }
 
 // Open Connection / Client
 int transport_open_connection(lua_State *L, Handle *handle)
 {
-	// Get args & Set up connection
-	unsigned uart_id, tmr_id;
+  // Get args & Set up connection
+  unsigned uart_id, tmr_id;
   
   check_num_args( L,3 ); // 1st arg is uart num, 2nd arg is tmr_id, 3nd is handle
   if ( !lua_isnumber( L, 1 ) ) 
@@ -59,80 +76,104 @@ int transport_open_connection(lua_State *L, Handle *handle)
   tmr_id = lua_tonumber( L, 1 );
   MOD_CHECK_ID( timer, tmr_id );
   
-	handle->tpt.fd = ( int )uart_id;
-	handle->tpt.tmr_id = tmr_id;
-	return 1;
+  adispatch_buff = -1;
+
+  handle->tpt.fd = ( int )uart_id;
+  handle->tpt.tmr_id = tmr_id;
+
+  // Setup uart
+  platform_uart_setup( (unsigned int) uart_id, 115200, 8, PLATFORM_UART_PARITY_NONE, PLATFORM_UART_STOPBITS_1 );
+
+  return 1;
 }
 
 // Accept Connection 
-void transport_accept (Transport *tpt, Transport *atpt)
+void transport_accept( Transport *tpt, Transport *atpt )
 {
-	struct exception e;
-	TRANSPORT_VERIFY_OPEN;
-	atpt->fd = tpt->fd;
+  struct exception e;
+  TRANSPORT_VERIFY_OPEN;
+  atpt->fd = tpt->fd;
 }
 
-
-
-void transport_read_buffer (Transport *tpt, u8 *buffer, int length)
+void transport_read_buffer( Transport *tpt, u8 *buffer, int length )
 {
-	int n = 0;
-	int c;
-	struct exception e;
-	int uart_timeout = PLATFORM_UART_INFINITE_TIMEOUT; // not sure whether we should always follow this
+  int n = 0;
+  int c;
+  struct exception e;
+  timer_data_type uart_timeout = PLATFORM_TIMER_INF_TIMEOUT; // not sure whether we should always follow this
+  // int uart_timeout = 100000;
 	
-	while( n < length )
-	{
-		TRANSPORT_VERIFY_OPEN;
-		c = platform_uart_recv( tpt->fd, tpt->tmr_id, uart_timeout );
-				
+  while( n < length )
+  {
+    TRANSPORT_VERIFY_OPEN;
+
+    if ( adispatch_buff < 0 )
+      c = platform_uart_recv( tpt->fd, tpt->tmr_id, uart_timeout );
+    else
+    {
+      c = adispatch_buff;
+      adispatch_buff = -1;
+    }
+
     if( c < 0 )
-		{
-		  // uart_timeout = 1000000;  // Reset and use timeout of 1s
-			e.errnum = ERR_NODATA;
-			e.type = nonfatal;
-			Throw( e );
-		}
-		else
-		{
-			buffer[ n ] = ( u8 )c;
-			n++;
-		}
-		// After getting one char of a read remainder
-		//  should follow within a timeout of 0.1 sec
-		uart_timeout = 100000;
+    {
+      // uart_timeout = 1000000;  // Reset and use timeout of 1s
+      e.errnum = ERR_NODATA;
+      e.type = nonfatal;
+      Throw( e );
+    }
+    else
+    {
+      buffer[ n ] = ( u8 )c;
+      n++;
+    }
+    // After getting one char of a read remainder
+    //  should follow within a timeout of 0.1 sec
+    uart_timeout = 100000;
   }
-	
 }
 
 void transport_write_buffer( Transport *tpt, const u8 *buffer, int length )
 {
-	int i;
-	struct exception e;
-	TRANSPORT_VERIFY_OPEN;
+  int i;
+  struct exception e;
+  TRANSPORT_VERIFY_OPEN;
 	
-	for( i = 0; i < length; i ++ )
-    platform_uart_send( CON_UART_ID, buffer[ i ] );
+  for( i = 0; i < length; i ++ )
+    platform_uart_send( tpt->fd, buffer[ i ] );
 }
 
 // Check if data is available on connection without reading:
-// 		- 1 = data available, 0 = no data available
-int transport_readable (Transport *tpt)
+//     - 1 = data available, 0 = no data available
+int transport_readable( Transport *tpt )
 {
-	return 1; // no really easy way to check this unless platform support is added
+  int c;
+
+  if ( adispatch_buff >= 0 ) // if we have a char already
+    return 1;
+  else // check if a char is ready to be read
+  {
+    c = transport_get_char( tpt );
+    if( c > 0)
+    {
+      adispatch_buff = c;
+      return 1;
+    }
+  }
+  return 0;
 }
 
 // Check if transport is open:
-//		- 1 = connection open, 0 = connection closed
-int transport_is_open (Transport *tpt)
+//    - 1 = connection open, 0 = connection closed
+int transport_is_open( Transport *tpt )
 {
-	return ( tpt->fd != INVALID_TRANSPORT );
+  return ( tpt->fd != INVALID_TRANSPORT );
 }
 
 // Shut down connection
-void transport_close (Transport *tpt)
+void transport_close( Transport *tpt )
 {
-	tpt->fd = INVALID_TRANSPORT;
+  tpt->fd = INVALID_TRANSPORT;
 }
 
 #endif
diff --git a/src/main.c b/src/main.c
index cc72966c..4ef1c1cb 100644
--- a/src/main.c
+++ b/src/main.c
@@ -48,7 +48,7 @@ extern char etext[];
 #endif
 
 #ifndef RPC_TIMER_ID
-  #define RPC_TIMER_ID    CON_TIMER_ID
+  #define RPC_TIMER_ID    PLATFORM_TIMER_SYS_ID
 #endif
 
 #ifndef RPC_UART_SPEED
diff --git a/src/modules/adc.c b/src/modules/adc.c
index 2120f921..1c96c9ca 100644
--- a/src/modules/adc.c
+++ b/src/modules/adc.c
@@ -20,30 +20,30 @@ static int adc_maxval( lua_State* L )
   
   id = luaL_checkinteger( L, 1 );
   MOD_CHECK_ID( adc, id );
-  res = platform_adc_op( id, PLATFORM_ADC_GET_MAXVAL, 0 );
+  res = platform_adc_get_maxval( id );
   lua_pushinteger( L, res );
   return 1;
 }
 
-// Lua: realclock = setclock( id, clock, [timer_id] )
+// Lua: realclock = setclock( id, freq, [timer_id] )
 static int adc_setclock( lua_State* L )
 {
-  u32 clock;
+  u32 freq;
   unsigned id, timer_id = 0;
   
   id = luaL_checkinteger( L, 1 );
   MOD_CHECK_ID( adc, id );
-  clock = luaL_checkinteger( L, 2 );
-  if ( clock > 0 )
+  freq = luaL_checkinteger( L, 2 );
+  if ( freq > 0 )
   {
     timer_id = luaL_checkinteger( L, 3 );
     MOD_CHECK_ID( timer, timer_id );
     MOD_CHECK_RES_ID( adc, id, timer, timer_id );
   }
 
-  platform_adc_op( id, PLATFORM_ADC_OP_SET_TIMER, timer_id );
-  clock = platform_adc_op( id, PLATFORM_ADC_OP_SET_CLOCK, clock );
-  lua_pushinteger( L, clock );
+  platform_adc_set_timer( id, timer_id );
+  freq = platform_adc_set_clock( id, freq );
+  lua_pushinteger( L, freq );
   return 1;
 }
 
@@ -54,7 +54,7 @@ static int adc_isdone( lua_State* L )
     
   id = luaL_checkinteger( L, 1 );
   MOD_CHECK_ID( adc, id );
-  lua_pushinteger( L, platform_adc_op( id, PLATFORM_ADC_IS_DONE, 0 ) );
+  lua_pushinteger( L, platform_adc_is_done( id ) );
   return 1;
 }
 
@@ -66,7 +66,7 @@ static int adc_setblocking( lua_State* L )
   id = luaL_checkinteger( L, 1 );
   MOD_CHECK_ID( adc, id );
   mode = luaL_checkinteger( L, 2 );
-  platform_adc_op( id, PLATFORM_ADC_SET_BLOCKING, mode );
+  platform_adc_set_blocking( id, mode );
   return 0;
 }
 
@@ -81,7 +81,7 @@ static int adc_setsmoothing( lua_State* L )
   length = luaL_checkinteger( L, 2 );
   if ( !( length & ( length - 1 ) ) )
   {
-    res = platform_adc_op( id, PLATFORM_ADC_SET_SMOOTHING, length );
+    res = platform_adc_set_smoothing( id, length );
     if ( res == PLATFORM_ERR )
       return luaL_error( L, "Buffer allocation failed." );
     else
@@ -185,7 +185,7 @@ static int adc_getsamples( lua_State* L )
     lua_pushinteger( L, adc_get_processed_sample( id ) );
     lua_rawseti( L, -2, i );
   }
-  return 0;
+  return 1;
 }
 
 
@@ -201,22 +201,22 @@ static int adc_insertsamples( lua_State* L )
   luaL_checktype(L, 2, LUA_TTABLE);
   
   startidx = luaL_checkinteger( L, 3 );
-	if  ( startidx <= 0 )
+  if  ( startidx <= 0 )
     return luaL_error( L, "idx must be > 0" );
 
   count = luaL_checkinteger(L, 4 );
-	if  ( count == 0 )
+  if  ( count == 0 )
     return luaL_error( L, "count must be > 0" );
   
   bcnt = adc_wait_samples( id, count );
   
   for( i = startidx; i < ( count + startidx ); i ++ )
   {
-		if ( i < bcnt + startidx )
-    	lua_pushinteger( L, adc_get_processed_sample( id ) );
-		else
-			lua_pushnil( L ); // nil-out values where we don't have enough samples
-		
+    if ( i < bcnt + startidx )
+      lua_pushinteger( L, adc_get_processed_sample( id ) );
+    else
+      lua_pushnil( L ); // nil-out values where we don't have enough samples
+
     lua_rawseti( L, 2, i );
   }
   
diff --git a/src/modules/auxmods.h b/src/modules/auxmods.h
index d59fb6a4..0db5560d 100644
--- a/src/modules/auxmods.h
+++ b/src/modules/auxmods.h
@@ -62,6 +62,12 @@ LUALIB_API int ( luaopen_i2c )( lua_State *L );
   if( !platform_ ## mod ## _exists( id ) )\
     return luaL_error( L, #mod" %d does not exist", ( unsigned )id )
 
+#define MOD_CHECK_TIMER( id )\
+  if( id == PLATFORM_TIMER_SYS_ID && !platform_timer_sys_available() )\
+    return luaL_error( L, "the system timer is not available on this platform" );\
+  if( !platform_timer_exists( id ) )\
+    return luaL_error( L, "timer %d does not exist", ( unsigned )id )\
+
 #define MOD_CHECK_RES_ID( mod, id, resmod, resid )\
   if( !platform_ ## mod ## _check_ ## resmod ## _id( id, resid ) )\
     return luaL_error( L, #resmod" %d not valid with " #mod " %d", ( unsigned )resid, ( unsigned )id )
diff --git a/src/modules/bit.c b/src/modules/bit.c
index f1b529ca..8e9d75e2 100644
--- a/src/modules/bit.c
+++ b/src/modules/bit.c
@@ -4,9 +4,11 @@
 
 // Modified by BogdanM for eLua
 
-#include 
-#include 
+
 #include 
+
+#include "lua.h"
+#include "lauxlib.h"
 #include "auxmods.h"
 #include "type.h"
 #include "lrotable.h"
diff --git a/src/modules/bitarray.c b/src/modules/bitarray.c
index 1df3283c..321debb1 100644
--- a/src/modules/bitarray.c
+++ b/src/modules/bitarray.c
@@ -45,7 +45,7 @@ static int bitarray_new( lua_State *L )
   if( lua_isnumber( L, 1 ) )
   {
     // capacity, [element_size_bits], [fill]
-    capacity = luaL_checkinteger( L, 1 );
+    capacity = ( u32 )luaL_checkinteger( L, 1 );
     if( lua_isnumber( L, 2 ) )
       elsize = luaL_checkinteger( L, 2 );
     else
@@ -69,7 +69,7 @@ static int bitarray_new( lua_State *L )
       elsize = 8;
     if( ( temp << 3 ) % elsize )
       return luaL_error( L, "length is not a multiple of element size." );
-    capacity = ( temp << 3 ) / elsize;  
+    capacity = ( u32 )( temp << 3 ) / elsize;  
   }
   else 
     return luaL_error( L, "invalid arguments." );
@@ -141,7 +141,7 @@ static int bitarray_get( lua_State *L )
   u32 idx;
    
   pa = bitarray_check( L );
-  idx = luaL_checkinteger( L, 2 );
+  idx = ( u32 )luaL_checkinteger( L, 2 );
   if( ( idx <= 0 ) || ( idx > pa->capacity ) )
     return luaL_error( L, "invalid index." );
   lua_pushinteger( L, bitarray_getval( pa, idx ) );    
@@ -156,8 +156,8 @@ static int bitarray_set( lua_State *L )
   u8 rest, mask;
    
   pa = bitarray_check( L );
-  idx = luaL_checkinteger( L, 2 );
-  newval = luaL_checkinteger( L, 3 );
+  idx = ( u32 )luaL_checkinteger( L, 2 );
+  newval = ( u32 )luaL_checkinteger( L, 3 );
   if( ( idx <= 0 ) || ( idx > pa->capacity ) )
     return luaL_error( L, "invalid index." );
   idx --;
@@ -206,7 +206,7 @@ static int bitarray_iter( lua_State *L )
   u32 idx;
   
   pa = bitarray_check( L );
-  idx = luaL_checkinteger( L, 2 ) + 1;
+  idx = ( u32 )luaL_checkinteger( L, 2 ) + 1;
   if( idx <= pa->capacity )
   {
     lua_pushinteger( L, idx );
diff --git a/src/modules/i2c.c b/src/modules/i2c.c
index bb2c477d..5ea44a6e 100644
--- a/src/modules/i2c.c
+++ b/src/modules/i2c.c
@@ -13,10 +13,12 @@
 static int i2c_setup( lua_State *L )
 {
   unsigned id = luaL_checkinteger( L, 1 );
-  u32 speed = ( u32 )luaL_checkinteger( L, 2 );
+  s32 speed = ( s32 )luaL_checkinteger( L, 2 );
 
   MOD_CHECK_ID( i2c, id );
-  lua_pushinteger( L, platform_i2c_setup( id, speed ) );
+  if (speed <= 0)
+    return luaL_error( L, "frequency must be > 0" );
+  lua_pushinteger( L, platform_i2c_setup( id, (u32)speed ) );
   return 1;
 }
 
@@ -44,11 +46,13 @@ static int i2c_stop( lua_State *L )
 static int i2c_address( lua_State *L )
 {
   unsigned id = luaL_checkinteger( L, 1 );
-  u16 address = ( u16 )luaL_checkinteger( L, 2 );
+  int address = luaL_checkinteger( L, 2 );
   int direction = luaL_checkinteger( L, 3 );
 
   MOD_CHECK_ID( i2c, id );
-  lua_pushboolean( L, platform_i2c_send_address( id, address, direction ) );
+  if ( address < 0 || address > 127 )
+    return luaL_error( L, "slave address must be from 0 to 127" );
+  lua_pushboolean( L, platform_i2c_send_address( id, (u16)address, direction ) );
   return 1;
 }
 
@@ -68,11 +72,13 @@ static int i2c_write( lua_State *L )
     return luaL_error( L, "invalid number of arguments" );
   for( argn = 2; argn <= lua_gettop( L ); argn ++ )
   {
-    if( lua_isnumber( L, argn ) )
+    // lua_isnumber() would silently convert a string of digits to an integer
+    // whereas here strings are handled separately.
+    if( lua_type( L, argn ) == LUA_TNUMBER )
     {
       numdata = ( int )luaL_checkinteger( L, argn );
       if( numdata < 0 || numdata > 255 )
-        return luaL_error( L, "numeric data can be between 0 and 255" );
+        return luaL_error( L, "numeric data must be from 0 to 255" );
       if( platform_i2c_send_byte( id, numdata ) != 1 )
         break;
       wrote ++;
@@ -83,10 +89,10 @@ static int i2c_write( lua_State *L )
       for( i = 0; i < datalen; i ++ )
       {
         lua_rawgeti( L, argn, i + 1 );
-        numdata = luaL_checkinteger( L, -1 );
+        numdata = ( int )luaL_checkinteger( L, -1 );
         lua_pop( L, 1 );
         if( numdata < 0 || numdata > 255 )
-          return luaL_error( L, "numeric data can be between 0 and 255" );
+          return luaL_error( L, "numeric data must be from 0 to 255" );
         if( platform_i2c_send_byte( id, numdata ) == 0 )
           break;
       }
diff --git a/src/modules/lpack.c b/src/modules/lpack.c
index a9621371..607ff2b5 100644
--- a/src/modules/lpack.c
+++ b/src/modules/lpack.c
@@ -10,25 +10,25 @@
 * Modified by BogdanM for eLua
 */
 
-#define	OP_ZSTRING	'z'		/* zero-terminated string */
-#define	OP_BSTRING	'p'		/* string preceded by length byte */
-#define	OP_WSTRING	'P'		/* string preceded by length word */
-#define	OP_SSTRING	'a'		/* string preceded by length size_t */
-#define	OP_STRING	'A'		/* string */
-#define	OP_FLOAT	'f'		/* float */
-#define	OP_DOUBLE	'd'		/* double */
-#define	OP_NUMBER	'n'		/* Lua number */
-#define	OP_CHAR		'c'		/* char */
-#define	OP_BYTE		'b'		/* byte = unsigned char */
-#define	OP_SHORT	'h'		/* short */
-#define	OP_USHORT	'H'		/* unsigned short */
-#define	OP_INT		'i'		/* int */
-#define	OP_UINT		'I'		/* unsigned int */
-#define	OP_LONG		'l'		/* long */
-#define	OP_ULONG	'L'		/* unsigned long */
-#define	OP_LITTLEENDIAN	'<'		/* little endian */
-#define	OP_BIGENDIAN	'>'		/* big endian */
-#define	OP_NATIVE	'='		/* native endian */
+#define OP_ZSTRING      'z'             /* zero-terminated string */
+#define OP_BSTRING      'p'             /* string preceded by length byte */
+#define OP_WSTRING      'P'             /* string preceded by length word */
+#define OP_SSTRING      'a'             /* string preceded by length size_t */
+#define OP_STRING       'A'             /* string */
+#define OP_FLOAT        'f'             /* float */
+#define OP_DOUBLE       'd'             /* double */
+#define OP_NUMBER       'n'             /* Lua number */
+#define OP_CHAR         'c'             /* char */
+#define OP_BYTE         'b'             /* byte = unsigned char */
+#define OP_SHORT        'h'             /* short */
+#define OP_USHORT       'H'             /* unsigned short */
+#define OP_INT          'i'             /* int */
+#define OP_UINT         'I'             /* unsigned int */
+#define OP_LONG         'l'             /* long */
+#define OP_ULONG        'L'             /* unsigned long */
+#define OP_LITTLEENDIAN '<'             /* little endian */
+#define OP_BIGENDIAN    '>'             /* big endian */
+#define OP_NATIVE       '='             /* native endian */
 
 #include 
 #include 
@@ -62,44 +62,44 @@ static void doswap(int swap, void *p, size_t n)
  {
   char *a=p;
   int i,j;
-  for (i=0, j=n-1, n=n/2; n--; i++, j--)
+  for (i=0, j=( int )n-1, n=n/2; n--; i++, j--)
   {
    char t=a[i]; a[i]=a[j]; a[j]=t;
   }
  }
 }
 
-#define UNPACKNUMBER(OP,T)		\
-   case OP:				\
-   {					\
-    T a;				\
-    int m=sizeof(a);			\
-    if (i+m>len) goto done;		\
-    memcpy(&a,s+i,m);			\
-    i+=m;				\
-    doswap(swap,&a,m);			\
-    lua_pushnumber(L,(lua_Number)a);	\
-    ++n;				\
-    break;				\
+#define UNPACKNUMBER(OP,T)                      \
+   case OP:                                     \
+   {                                            \
+    T a;                                        \
+    int m=sizeof(a);                            \
+    if (((unsigned long)i+m)>len) goto done;    \
+    memcpy(&a,s+i,m);                           \
+    i+=m;                                       \
+    doswap(swap,&a,m);                          \
+    lua_pushnumber(L,(lua_Number)a);            \
+    ++n;                                        \
+    break;                                      \
    }
 
-#define UNPACKSTRING(OP,T)		\
-   case OP:				\
-   {					\
-    T l;				\
-    int m=sizeof(l);			\
-    if (i+m>len) goto done;		\
-    memcpy(&l,s+i,m);			\
-    doswap(swap,&l,m);			\
-    if (i+m+l>len) goto done;		\
-    i+=m;				\
-    lua_pushlstring(L,s+i,l);		\
-    i+=l;				\
-    ++n;				\
-    break;				\
+#define UNPACKSTRING(OP,T)                      \
+   case OP:                                     \
+   {                                            \
+    T l;                                        \
+    int m=sizeof(l);                            \
+    if (((unsigned long)i+m)>len) goto done;    \
+    memcpy(&l,s+i,m);                           \
+    doswap(swap,&l,m);                          \
+    if (((unsigned long)i+m+l)>len) goto done;  \
+    i+=m;                                       \
+    lua_pushlstring(L,s+i,l);                   \
+    i+=l;                                       \
+    ++n;                                        \
+    break;                                      \
    }
 
-static int l_unpack(lua_State *L) 		/** unpack(s,f,[init]) */
+static int l_unpack(lua_State *L)               /** unpack(s,f,[init]) */
 {
  size_t len;
  const char *s=luaL_checklstring(L,1,&len);
@@ -112,7 +112,7 @@ static int l_unpack(lua_State *L) 		/** unpack(s,f,[init]) */
  {
   int c=*f++;
   int N=1;
-  if (isdigit(*f)) 
+  if (isdigit(*f))
   {
    N=0;
    while (isdigit(*f)) N=10*N+(*f++)-'0';
@@ -131,7 +131,7 @@ static int l_unpack(lua_State *L) 		/** unpack(s,f,[init]) */
    case OP_STRING:
    {
     ++N;
-    if (i+N>len) goto done;
+    if (((unsigned long)i+N)>len) goto done;
     lua_pushlstring(L,s+i,N);
     i+=N;
     ++n;
@@ -141,7 +141,7 @@ static int l_unpack(lua_State *L) 		/** unpack(s,f,[init]) */
    case OP_ZSTRING:
    {
     size_t l;
-    if (i>=len) goto done;
+    if (((unsigned long)i)>=len) goto done;
     l=strlen(s+i);
     lua_pushlstring(L,s+i,l);
     i+=l+1;
@@ -152,10 +152,10 @@ static int l_unpack(lua_State *L) 		/** unpack(s,f,[init]) */
    UNPACKSTRING(OP_WSTRING, unsigned short)
    UNPACKSTRING(OP_SSTRING, size_t)
    UNPACKNUMBER(OP_NUMBER, lua_Number)
-#ifndef LUA_NUMBER_INTEGRAL   
+#ifndef LUA_NUMBER_INTEGRAL
    UNPACKNUMBER(OP_DOUBLE, double)
    UNPACKNUMBER(OP_FLOAT, float)
-#endif   
+#endif
    UNPACKNUMBER(OP_CHAR, char)
    UNPACKNUMBER(OP_BYTE, unsigned char)
    UNPACKNUMBER(OP_SHORT, short)
@@ -177,28 +177,28 @@ done:
  return n+1;
 }
 
-#define PACKNUMBER(OP,T)			\
-   case OP:					\
-   {						\
-    T a=(T)luaL_checknumber(L,i++);		\
-    doswap(swap,&a,sizeof(a));			\
-    luaL_addlstring(&b,(void*)&a,sizeof(a));	\
-    break;					\
+#define PACKNUMBER(OP,T)                        \
+   case OP:                                     \
+   {                                            \
+    T a=(T)luaL_checknumber(L,i++);             \
+    doswap(swap,&a,sizeof(a));                  \
+    luaL_addlstring(&b,(void*)&a,sizeof(a));    \
+    break;                                      \
    }
 
-#define PACKSTRING(OP,T)			\
-   case OP:					\
-   {						\
-    size_t l;					\
-    const char *a=luaL_checklstring(L,i++,&l);	\
-    T ll=(T)l;					\
-    doswap(swap,&ll,sizeof(ll));		\
-    luaL_addlstring(&b,(void*)&ll,sizeof(ll));	\
-    luaL_addlstring(&b,a,l);			\
-    break;					\
+#define PACKSTRING(OP,T)                        \
+   case OP:                                     \
+   {                                            \
+    size_t l;                                   \
+    const char *a=luaL_checklstring(L,i++,&l);  \
+    T ll=(T)l;                                  \
+    doswap(swap,&ll,sizeof(ll));                \
+    luaL_addlstring(&b,(void*)&ll,sizeof(ll));  \
+    luaL_addlstring(&b,a,l);                    \
+    break;                                      \
    }
 
-static int l_pack(lua_State *L) 		/** pack(f,...) */
+static int l_pack(lua_State *L)                 /** pack(f,...) */
 {
  int i=2;
  const char *f=luaL_checkstring(L,1);
@@ -209,7 +209,7 @@ static int l_pack(lua_State *L) 		/** pack(f,...) */
  {
   int c=*f++;
   int N=1;
-  if (isdigit(*f)) 
+  if (isdigit(*f))
   {
    N=0;
    while (isdigit(*f)) N=10*N+(*f++)-'0';
@@ -236,7 +236,7 @@ static int l_pack(lua_State *L) 		/** pack(f,...) */
    PACKSTRING(OP_WSTRING, unsigned short)
    PACKSTRING(OP_SSTRING, size_t)
    PACKNUMBER(OP_NUMBER, lua_Number)
-#ifndef LUA_NUMBER_INTEGRAL   
+#ifndef LUA_NUMBER_INTEGRAL
    PACKNUMBER(OP_DOUBLE, double)
    PACKNUMBER(OP_FLOAT, float)
 #endif
@@ -263,9 +263,9 @@ static int l_pack(lua_State *L) 		/** pack(f,...) */
 #include "lrodefs.h"
 const LUA_REG_TYPE pack_map[] =
 {
-	{ LSTRKEY( "pack" ),  LFUNCVAL( l_pack ) },
-	{ LSTRKEY( "unpack" ), LFUNCVAL( l_unpack ) },
-	{ LNILKEY, LNILVAL }
+  { LSTRKEY( "pack" ),  LFUNCVAL( l_pack ) },
+  { LSTRKEY( "unpack" ), LFUNCVAL( l_unpack ) },
+  { LNILKEY, LNILVAL }
 };
 
 int luaopen_pack( lua_State *L )
diff --git a/src/modules/luarpc.c b/src/modules/luarpc.c
index 40e4d0cf..5ddd571b 100644
--- a/src/modules/luarpc.c
+++ b/src/modules/luarpc.c
@@ -52,7 +52,8 @@ void *alloca(size_t);
 // Prototypes for Local Functions  
 LUALIB_API int luaopen_rpc( lua_State *L );
 Handle *handle_create( lua_State *L );
-
+static void rpc_dispatch_helper( lua_State *L, ServerHandle *handle );
+static int rpc_adispatch_helper( lua_State *L, ServerHandle * handle );
 
 struct exception_context the_exception_context[ 1 ];
 
@@ -175,7 +176,7 @@ static void transport_write_u8( Transport *tpt, u8 x )
 
 static void swap_bytes( uint8_t *number, size_t numbersize )
 {
-  int i;
+  u32 i;
   for ( i = 0 ; i < numbersize / 2 ; i ++ )
   {
     uint8_t temp = number[ i ];
@@ -217,7 +218,7 @@ static void transport_write_u32( Transport *tpt, u32 x )
 // read a lua number from the transport 
 static lua_Number transport_read_number( Transport *tpt )
 {
-  lua_Number x;
+  lua_Number x = 0;
   u8 b[ tpt->lnum_bytes ];
   struct exception e;
   TRANSPORT_VERIFY_OPEN;
@@ -448,7 +449,7 @@ static void write_variable( Transport *tpt, lua_State *L, int var_index )
       u32 len;
       transport_write_u8( tpt, RPC_STRING );
       s = lua_tostring( L, var_index );
-      len = lua_strlen( L, var_index );
+      len = ( u32 )lua_strlen( L, var_index );
       transport_write_u32( tpt, len );
       transport_write_string( tpt, s, len );
       break;
@@ -492,7 +493,7 @@ static void write_variable( Transport *tpt, lua_State *L, int var_index )
       luaL_error( L, "light userdata transmission unsupported" );
       break;
   }
-  MYASSERT( lua_gettop( L ) == stack_at_start );
+  lua_assert( lua_gettop( L ) == stack_at_start );
 }
 
 
@@ -632,7 +633,7 @@ static void client_negotiate( Transport *tpt )
   header[1] = 'R';
   header[2] = 'P';
   header[3] = 'C';
-  header[4] = RPC_PROTOCOL_VERSION;
+  header[4] = ( char )RPC_PROTOCOL_VERSION;
   header[5] = tpt->loc_little;
   header[6] = tpt->lnum_bytes;
   header[7] = tpt->loc_intnum;
@@ -779,7 +780,7 @@ static int handle_index (lua_State *L)
   const char *s;
 
   check_num_args( L, 2 );
-  MYASSERT( lua_isuserdata( L, 1 ) && ismetatable_type( L, 1, "rpc.handle" ) );
+  lua_assert( lua_isuserdata( L, 1 ) && ismetatable_type( L, 1, "rpc.handle" ) );
 
   if( lua_type( L, 2 ) != LUA_TSTRING )
     return luaL_error( L, "can't index a handle with a non-string" );
@@ -801,7 +802,7 @@ static int handle_newindex( lua_State *L )
   const char *s;
 
   check_num_args( L, 3 );
-  MYASSERT( lua_isuserdata( L, 1 ) && ismetatable_type( L, 1, "rpc.handle" ) );
+  lua_assert( lua_isuserdata( L, 1 ) && ismetatable_type( L, 1, "rpc.handle" ) );
 
   if( lua_type( L, 2 ) != LUA_TSTRING )
     return luaL_error( L, "can't index handle with a non-string" );
@@ -820,12 +821,13 @@ static int handle_newindex( lua_State *L )
 // replays series of indexes to remote side as a string
 static void helper_remote_index( Helper *helper )
 {
-  int i, len;
+  int i;
+  u32 len;
   Helper **hstack;
   Transport *tpt = &helper->handle->tpt;
   
   // get length of name & make stack of helpers
-  len = strlen( helper->funcname );
+  len = ( u32 )strlen( helper->funcname );
   if( helper->nparents > 0 ) // If helper has parents, build string to remote index
   {
     hstack = ( Helper ** )alloca( sizeof( Helper * ) * helper->nparents );
@@ -837,20 +839,20 @@ static void helper_remote_index( Helper *helper )
       hstack[ i - 1 ] = hstack[ i ]->parent;
       len += strlen( hstack[ i ]->funcname ) + 1;
     }
-	
-	  transport_write_u32( tpt, len );
+
+    transport_write_u32( tpt, len );
 
     // replay helper key names      
     for( i = 0 ; i < helper->nparents ; i ++ )
     {
-     transport_write_string( tpt, hstack[ i ]->funcname, strlen( hstack[ i ]->funcname ) );
+     transport_write_string( tpt, hstack[ i ]->funcname, ( int )strlen( hstack[ i ]->funcname ) );
      transport_write_string( tpt, ".", 1 ); 
     }
   }
   else // If helper has no parents, just use length of global
-	  transport_write_u32( tpt, len );
+    transport_write_u32( tpt, len );
 
-  transport_write_string( tpt, helper->funcname, strlen( helper->funcname ) );
+  transport_write_string( tpt, helper->funcname, ( int )strlen( helper->funcname ) );
 }
 
 static void helper_wait_ready( Transport *tpt, u8 cmd )
@@ -1072,7 +1074,7 @@ static int helper_index( lua_State *L )
   const char *s;
 
   check_num_args( L, 2 );
-  MYASSERT( lua_isuserdata( L, 1 ) && ismetatable_type( L, 1, "rpc.helper" ) );
+  lua_assert( lua_isuserdata( L, 1 ) && ismetatable_type( L, 1, "rpc.helper" ) );
 
   if( lua_type( L, 2 ) != LUA_TSTRING )
     return luaL_error( L, "can't index handle with non-string" );
@@ -1257,13 +1259,13 @@ static void read_cmd_call( Transport *tpt, lua_State *L )
     // handle errors
     if ( error_code )
     {
-      size_t len;
+      size_t elen;
       const char *errmsg;
-      errmsg = lua_tolstring (L, -1, &len);
+      errmsg = lua_tolstring( L, -1, &elen );
       transport_write_u8( tpt, 1 );
       transport_write_u32( tpt, error_code );
-      transport_write_u32( tpt, len );
-      transport_write_string( tpt, errmsg, len );
+      transport_write_u32( tpt, ( u32 )elen );
+      transport_write_string( tpt, errmsg, ( int )elen );
     }
     else
     {
@@ -1279,11 +1281,11 @@ static void read_cmd_call( Transport *tpt, lua_State *L )
   {
     // bad function
     const char *msg = "undefined function: ";
-    int errlen = strlen( msg ) + len;
+    int errlen = ( int )strlen( msg ) + len;
     transport_write_u8( tpt, 1 );
     transport_write_u32( tpt, LUA_ERRRUN );
     transport_write_u32( tpt, errlen );
-    transport_write_string( tpt, msg, strlen( msg ) );
+    transport_write_string( tpt, msg, ( int )strlen( msg ) );
     transport_write_string( tpt, funcname, len );
   }
   // empty the stack
@@ -1567,6 +1569,29 @@ static int rpc_dispatch( lua_State *L )
   return 0;
 }
 
+static int rpc_adispatch_helper( lua_State *L, ServerHandle * handle )
+{
+  // Check if we have waiting data that we can dispatch on,
+  // don't block if we don't have any data
+  if( transport_readable( &handle->atpt ) || transport_readable( &handle->ltpt ) )
+      rpc_dispatch_helper( L, handle );
+
+  return 0;
+}
+
+static int rpc_adispatch( lua_State *L )
+{
+
+  ServerHandle *handle = 0;
+
+  handle = ( ServerHandle * )luaL_checkudata(L, 1, "rpc.server_handle");
+  luaL_argcheck(L, handle, 1, "server handle expected");
+
+  handle = ( ServerHandle * )lua_touserdata( L, 1 );
+  rpc_adispatch_helper( L, handle );
+
+  return 0;
+}  
 
 // rpc_server( transport_identifier )
 static int rpc_server( lua_State *L )
@@ -1658,6 +1683,7 @@ const LUA_REG_TYPE rpc_map[] =
   {  LSTRKEY( "listen" ), LFUNCVAL( rpc_listen ) },
   {  LSTRKEY( "peek" ), LFUNCVAL( rpc_peek ) },
   {  LSTRKEY( "dispatch" ), LFUNCVAL( rpc_dispatch ) },
+  {  LSTRKEY( "adispatch" ), LFUNCVAL( rpc_adispatch ) },
 //  {  LSTRKEY( "rpc_async" ), LFUNCVAL( rpc_async ) },
 #if LUA_OPTIMIZE_MEMORY > 0
 // {  LSTRKEY("mode"), LSTRVAL( LUARPC_MODE ) }, 
@@ -1720,6 +1746,7 @@ static const luaL_reg rpc_map[] =
   { "listen", rpc_listen },
   { "peek", rpc_peek },
   { "dispatch", rpc_dispatch },
+  { "adispatch", rpc_adispatch },
 //  { "rpc_async", rpc_async },
   { NULL, NULL }
 };
diff --git a/src/modules/net.c b/src/modules/net.c
index c72c4609..b158d553 100644
--- a/src/modules/net.c
+++ b/src/modules/net.c
@@ -6,6 +6,7 @@
 #include "platform.h"
 #include "auxmods.h"
 #include "elua_net.h"
+#include "common.h"
 #include 
 #include 
 #include 
@@ -14,20 +15,16 @@
 #include "platform_conf.h"
 #ifdef BUILD_UIP
 
-// Lua: sock, remoteip, err = accept( port, [ timer_id, timeout ] )
+// Lua: sock, remoteip, err = accept( port, [timeout], [timer_id] )
 static int net_accept( lua_State *L )
 {
   u16 port = ( u16 )luaL_checkinteger( L, 1 );
-  unsigned timer_id = 0;
-  u32 timeout = 0;
+  unsigned timer_id = PLATFORM_TIMER_SYS_ID;
+  timer_data_type timeout = PLATFORM_TIMER_INF_TIMEOUT;
   elua_net_ip remip;
   int sock;
 
-  if( lua_gettop( L ) >= 2 ) // check for timeout arguments
-  {
-    timer_id = ( unsigned )luaL_checkinteger( L, 2 );
-    timeout = ( u32 )luaL_checkinteger( L, 3 );
-  }  
+  cmn_get_timeout_data( L, 2, &timeout, &timer_id );
   lua_pushinteger( L, sock = elua_accept( port, timer_id, timeout, &remip ) );
   lua_pushinteger( L, remip.ipaddr );
   lua_pushinteger( L, elua_net_get_last_err( sock ) );
@@ -140,15 +137,15 @@ static int net_unpackip( lua_State *L )
     return luaL_error( L, "invalid format" );                                      
 }
 
-// Lua: res, err = recv( sock, maxsize, [ timer_id, timeout ] ) or
-//      res, err = recv( sock, "*l", [ timer_id, timeout ] )
+// Lua: res, err = recv( sock, maxsize, [timeout], [timer_id] ) or
+//      res, err = recv( sock, "*l", [timeout], [timer_id] )
 static int net_recv( lua_State *L )
 {
   int sock = ( int )luaL_checkinteger( L, 1 );
   elua_net_size maxsize;
   s16 lastchar = ELUA_NET_NO_LASTCHAR;
-  unsigned timer_id = 0;
-  u32 timeout = 0;
+  unsigned timer_id = PLATFORM_TIMER_SYS_ID;
+  timer_data_type timeout = PLATFORM_TIMER_INF_TIMEOUT;
   luaL_Buffer net_recv_buff;
 
   if( lua_isnumber( L, 2 ) ) // invocation with maxsize
@@ -160,11 +157,7 @@ static int net_recv( lua_State *L )
     lastchar = '\n';
     maxsize = BUFSIZ;
   }
-  if( lua_gettop( L ) >= 3 ) // check for timeout arguments
-  {
-    timer_id = ( unsigned )luaL_checkinteger( L, 3 );
-    timeout = ( u32 )luaL_checkinteger( L, 4 );
-  }
+  cmn_get_timeout_data( L, 3, &timeout, &timer_id );
   // Initialize buffer
   luaL_buffinit( L, &net_recv_buff );
   elua_net_recvbuf( sock, &net_recv_buff, maxsize, lastchar, timer_id, timeout );
@@ -206,6 +199,9 @@ const LUA_REG_TYPE net_map[] =
   { LSTRKEY( "ERR_CLOSED" ), LNUMVAL( ELUA_NET_ERR_CLOSED ) },
   { LSTRKEY( "ERR_ABORTED" ), LNUMVAL( ELUA_NET_ERR_ABORTED ) },
   { LSTRKEY( "ERR_OVERFLOW" ), LNUMVAL( ELUA_NET_ERR_OVERFLOW ) },
+  { LSTRKEY( "SYS_TIMER" ), LNUMVAL( PLATFORM_TIMER_SYS_ID ) },
+  { LSTRKEY( "NO_TIMEOUT" ), LNUMVAL( 0 ) },
+  { LSTRKEY( "INF_TIMEOUT" ), LNUMVAL( PLATFORM_TIMER_INF_TIMEOUT ) },
 #endif
   { LNILKEY, LNILVAL }
 };
@@ -225,6 +221,9 @@ LUALIB_API int luaopen_net( lua_State *L )
   MOD_REG_NUMBER( L, "ERR_CLOSED", ELUA_NET_ERR_CLOSED );
   MOD_REG_NUMBER( L, "ERR_ABORTED", ELUA_NET_ERR_ABORTED );
   MOD_REG_NUMBER( L, "ERR_OVERFLOW", ELUA_NET_ERR_OVERFLOW );
+  MOD_REG_NUMBER( L, "SYS_TIMER", PLATFORM_TIMER_SYS_ID );
+  MOD_REG_NUMBER( L, "NO_TIMEOUT", 0 );
+  MOD_REG_NUMBER( L, "INF_TIMEOUT", PLATFORM_TIMER_INF_TIMEOUT );
   
   return 1;
 #endif // #if LUA_OPTIMIZE_MEMORY > 0  
diff --git a/src/modules/pio.c b/src/modules/pio.c
index d1d45a35..d495dadb 100644
--- a/src/modules/pio.c
+++ b/src/modules/pio.c
@@ -274,10 +274,10 @@ static int pio_mt_index( lua_State* L )
 #ifdef ELUA_PLATFORM_AVR32
       /* AVR32UC3A0 has a bizarre "port" called "PX" with 40 pins which map to
        * random areas of hardware ports 2 and 3:
-       * PX00-PX10 = GPIO100-GPIO90	//Port 3 pins 04-00; port 2 pins 31-26
-       * PX11-PX14 = GPIO109-GPIO106	//Port 3 pins 13-10
-       * PX15-PX34 = GPIO89-GPIO70	//Port 2 pins 25-06
-       * PX35-PX39 = GPIO105-GPIO101	//Port 3 pins 09-05
+       * PX00-PX10 = GPIO100-GPIO90     //Port 3 pins 04-00; port 2 pins 31-26
+       * PX11-PX14 = GPIO109-GPIO106    //Port 3 pins 13-10
+       * PX15-PX34 = GPIO89-GPIO70      //Port 2 pins 25-06
+       * PX35-PX39 = GPIO105-GPIO101    //Port 3 pins 09-05
        * Then port = trunc(GPIO/32) and pin = GPIO % 32
        *
        * This "Port X" exists in EVK1100 and MIZAR32 but not on EVK1101, which
@@ -287,32 +287,32 @@ static int pio_mt_index( lua_State* L )
 
       // Disallow "PC_06-PC_31" as aliases for PX pins
       if (key[1] == 'C' && pin > 5)
-	return 0;
+        return 0;
 
       // Disallow "PD_nn" as aliases for PX pins
       if (key[1] == 'D')
-	return 0;
+        return 0;
 
       // Map PX pins 00-39 to their ports/pins in the hardware register layout.
       if (key[1] == 'X')
       {
-	unsigned gpio;
+        unsigned gpio;
 
-	// You cannot perform port operations on port X because it
-	// doesn't exist in hardware.
-	if (pin == 0xFFFF)
-	  return 0;
+        // You cannot perform port operations on port X because it
+        // doesn't exist in hardware.
+        if (pin == 0xFFFF)
+          return 0;
 
-	// Map PX pin numbers to GPIO pin numbers
-	if( pin < 0 ) return 0;
-	if( pin <= 10 ) gpio = 100 - pin;
-	else if( pin <= 14 ) gpio = 109 - (pin - 11);
-	else if( pin <= 34 ) gpio = 89 - (pin - 15);
-	else if( pin <= 39 ) gpio = 105 - (pin - 35);
-	else return 0;
+        // Map PX pin numbers to GPIO pin numbers
+        if( pin < 0 ) return 0;
+        if( pin <= 10 ) gpio = 100 - pin;
+        else if( pin <= 14 ) gpio = 109 - (pin - 11);
+        else if( pin <= 34 ) gpio = 89 - (pin - 15);
+        else if( pin <= 39 ) gpio = 105 - (pin - 35);
+        else return 0;
 
-	port = gpio >> 5;
-	pin = gpio & 0x1F;
+        port = gpio >> 5;
+        pin = gpio & 0x1F;
       }
 #endif
     }
@@ -392,10 +392,10 @@ static const LUA_REG_TYPE pio_port_map[] =
 
 const LUA_REG_TYPE pio_map[] =
 {
+  { LSTRKEY( "decode" ), LFUNCVAL( pio_decode ) },  
 #if LUA_OPTIMIZE_MEMORY > 0
   { LSTRKEY( "pin" ), LROVAL( pio_pin_map ) },
   { LSTRKEY( "port" ), LROVAL( pio_port_map ) },
-  { LSTRKEY( "decode" ), LFUNCVAL( pio_decode ) },  
   { LSTRKEY( "INPUT" ), LNUMVAL( PIO_DIR_INPUT ) },
   { LSTRKEY( "OUTPUT" ), LNUMVAL( PIO_DIR_OUTPUT ) },
   { LSTRKEY( "PULLUP" ), LNUMVAL( PLATFORM_IO_PIN_PULLUP ) },
diff --git a/src/modules/pwm.c b/src/modules/pwm.c
index 27287dc5..fc065270 100644
--- a/src/modules/pwm.c
+++ b/src/modules/pwm.c
@@ -10,16 +10,20 @@
 // Lua: realfrequency = setup( id, frequency, duty )
 static int pwm_setup( lua_State* L )
 {
-  u32 freq;
-  unsigned duty, id;
+  s32 freq;	  // signed, to error check for negative values
+  unsigned duty;
+  unsigned id;
   
   id = luaL_checkinteger( L, 1 );
   MOD_CHECK_ID( pwm, id );
   freq = luaL_checkinteger( L, 2 );
+  if ( freq <= 0 )
+    return luaL_error( L, "frequency must be > 0" );
   duty = luaL_checkinteger( L, 3 );
-  if( duty > 100 )
-    duty = 100;
-  freq = platform_pwm_setup( id, freq, duty );
+  if ( duty > 100 )
+    // Negative values will turn out > 100, so will also fail.
+    return luaL_error( L, "duty cycle must be from 0 to 100" );
+  freq = platform_pwm_setup( id, (u32)freq, duty );
   lua_pushinteger( L, freq );
   return 1;  
 }
@@ -31,7 +35,7 @@ static int pwm_start( lua_State* L )
   
   id = luaL_checkinteger( L, 1 );
   MOD_CHECK_ID( pwm, id );
-  platform_pwm_op( id, PLATFORM_PWM_OP_START, 0 );
+  platform_pwm_start( id );
   return 0;  
 }
 
@@ -42,7 +46,7 @@ static int pwm_stop( lua_State* L )
   
   id = luaL_checkinteger( L, 1 );
   MOD_CHECK_ID( pwm, id );
-  platform_pwm_op( id, PLATFORM_PWM_OP_STOP, 0 );
+  platform_pwm_stop( id );
   return 0;  
 }
 
@@ -50,12 +54,14 @@ static int pwm_stop( lua_State* L )
 static int pwm_setclock( lua_State* L )
 {
   unsigned id;
-  u32 clk;
+  s32 clk;	// signed to error-check for negative values
   
   id = luaL_checkinteger( L, 1 );
   MOD_CHECK_ID( pwm, id );
   clk = luaL_checkinteger( L, 2 );
-  clk = platform_pwm_op( id, PLATFORM_PWM_OP_SET_CLOCK, clk );
+  if ( clk <= 0 )
+    return luaL_error( L, "frequency must be > 0" );
+  clk = platform_pwm_set_clock( id, (u32)clk );
   lua_pushinteger( L, clk );
   return 1;
 }
@@ -68,7 +74,7 @@ static int pwm_getclock( lua_State* L )
   
   id = luaL_checkinteger( L, 1 );
   MOD_CHECK_ID( pwm, id );
-  clk = platform_pwm_op( id, PLATFORM_PWM_OP_GET_CLOCK, 0 );
+  clk = platform_pwm_get_clock( id );
   lua_pushinteger( L, clk );
   return 1;
 }
diff --git a/src/modules/tmr.c b/src/modules/tmr.c
index df89dedb..a4e1bd76 100644
--- a/src/modules/tmr.c
+++ b/src/modules/tmr.c
@@ -21,120 +21,136 @@ static int tmrh_timer_op( lua_State* L, int op )
   unsigned id;
   timer_data_type res;
     
-  id = luaL_checkinteger( L, 1 );
-  MOD_CHECK_ID( timer, id );
+  id = ( unsigned )luaL_optinteger( L, 1, PLATFORM_TIMER_SYS_ID );
+  MOD_CHECK_TIMER( id );
   res = platform_timer_op( id, op, 0 );
-  lua_pushinteger( L, res );
+  lua_pushnumber( L, ( lua_Number )res );
   return 1;  
 }
 
-// Lua: delay( id, period )
+// Lua: delay( period, [id] )
 static int tmr_delay( lua_State* L )
 {
-  unsigned id, period;
+  timer_data_type period;
+  unsigned id;
   
-  id = luaL_checkinteger( L, 1 );
-  MOD_CHECK_ID( timer, id );
-  period = luaL_checkinteger( L, 2 );
+  period = ( timer_data_type )luaL_checknumber( L, 1 );
+  id = ( unsigned )luaL_optinteger( L, 2, PLATFORM_TIMER_SYS_ID );
+  MOD_CHECK_TIMER( id );
   platform_timer_delay( id, period );
   return 0;
 }
 
-// Lua: timervalue = read( id )
+// Lua: timervalue = read( [id] )
 static int tmr_read( lua_State* L )
 {
   return tmrh_timer_op( L, PLATFORM_TIMER_OP_READ );
 }
 
-// Lua: timervalue = start( id )
+// Lua: timervalue = start( [id] )
 static int tmr_start( lua_State* L )
 {
   return tmrh_timer_op( L, PLATFORM_TIMER_OP_START );
 }
 
-// Lua: time_us = gettimediff( id, end, start )
+// Lua: time_us = gettimediff( end, start, [id] )
 static int tmr_gettimediff( lua_State* L )
 {
-  timer_data_type end, start;
-  u32 res;
+  timer_data_type end, start, res;
   unsigned id;
     
-  id = luaL_checkinteger( L, 1 ); 
-  MOD_CHECK_ID( timer, id );
-  end = ( timer_data_type )luaL_checkinteger( L, 2 );
-  start = ( timer_data_type )luaL_checkinteger( L, 3 );  
+  id = ( unsigned )luaL_optinteger( L, 3, PLATFORM_TIMER_SYS_ID ); 
+  MOD_CHECK_TIMER( id );
+  end = ( timer_data_type )luaL_checknumber( L, 1 );
+  start = ( timer_data_type )luaL_checknumber( L, 2 );  
   res = platform_timer_get_diff_us( id, end, start );
-  lua_pushinteger( L, res );
+  lua_pushnumber( L, ( lua_Number )res );
   return 1;    
 }
 
-// Lua: res = getmindelay( id )
+// Lua: time_us = getdiffnow( start, [id] )
+static int tmr_getdiffnow( lua_State *L )
+{
+  timer_data_type start, res;
+  unsigned id;
+
+  id = ( unsigned )luaL_optinteger( L, 2, PLATFORM_TIMER_SYS_ID );
+  MOD_CHECK_TIMER( id );
+  start = ( timer_data_type )luaL_checknumber( L, 1 );
+  res = platform_timer_get_diff_crt( id, start );
+  lua_pushnumber( L, ( lua_Number )res );
+  return 1;
+}
+
+// Lua: res = getmindelay( [id] )
 static int tmr_getmindelay( lua_State* L )
 {
-  u32 res;
+  timer_data_type res;
   unsigned id;
   
-  id = luaL_checkinteger( L, 1 );
-  MOD_CHECK_ID( timer, id );
+  id = ( unsigned )luaL_optinteger( L, 1, PLATFORM_TIMER_SYS_ID );
+  MOD_CHECK_TIMER( id );
   res = platform_timer_op( id, PLATFORM_TIMER_OP_GET_MIN_DELAY, 0 );
-  lua_pushinteger( L, res );
+  lua_pushnumber( L, ( lua_Number )res );
   return 1;
 }
 
-// Lua: res = getmaxdelay( id )
+// Lua: res = getmaxdelay( [id] )
 static int tmr_getmaxdelay( lua_State* L )
 {
-  u32 res;
+  timer_data_type res;
   unsigned id;
   
-  id = luaL_checkinteger( L, 1 );
-  MOD_CHECK_ID( timer, id );
+  id = ( unsigned )luaL_optinteger( L, 1, PLATFORM_TIMER_SYS_ID );
+  MOD_CHECK_TIMER( id );
   res = platform_timer_op( id, PLATFORM_TIMER_OP_GET_MAX_DELAY, 0 );
-  lua_pushinteger( L, res );
+  lua_pushnumber( L, ( lua_Number )res );
   return 1;
 }
 
-// Lua: realclock = setclock( id, clock )
+// Lua: realclock = setclock( clock, [id] )
 static int tmr_setclock( lua_State* L )
 {
   u32 clock;
   unsigned id;
   
-  id = luaL_checkinteger( L, 1 );
-  MOD_CHECK_ID( timer, id );
-  clock = ( u32 )luaL_checkinteger( L, 2 );
+  id = ( unsigned )luaL_optinteger( L, 2, PLATFORM_TIMER_SYS_ID );
+  MOD_CHECK_TIMER( id );
+  clock = ( u32 )luaL_checkinteger( L, 1 );
   clock = platform_timer_op( id, PLATFORM_TIMER_OP_SET_CLOCK, clock );
   lua_pushinteger( L, clock );
   return 1;
 }
 
-// Lua: clock = getclock( id )
+// Lua: clock = getclock( [id] )
 static int tmr_getclock( lua_State* L )
 {
   u32 res;
   unsigned id;
   
-  id = luaL_checkinteger( L, 1 );
-  MOD_CHECK_ID( timer, id );
+  id = ( unsigned )luaL_optinteger( L, 1, PLATFORM_TIMER_SYS_ID );
+  MOD_CHECK_TIMER( id );
   res = platform_timer_op( id, PLATFORM_TIMER_OP_GET_CLOCK, 0 );
   lua_pushinteger( L, res );
   return 1;
 }
 
 #ifdef BUILD_LUA_INT_HANDLERS
-// Lua: set_match_int( id, timeout, type )
+// Lua: set_match_int( timeout, type, [id] )
 static int tmr_set_match_int( lua_State *L )
 {
   unsigned id;
   u32 res;
   
-  id = luaL_checkinteger( L, 1 );
-  MOD_CHECK_ID( timer, id );
-  res = platform_timer_set_match_int( id, ( u32 )luaL_checknumber( L, 2 ), ( int )luaL_checkinteger( L, 3 ) );
+  id = ( unsigned )luaL_optinteger( L, 3, PLATFORM_TIMER_SYS_ID );
+  MOD_CHECK_TIMER( id );
+  res = platform_timer_set_match_int( id, ( timer_data_type )luaL_checknumber( L, 1 ), ( int )luaL_checkinteger( L, 2 ) );
   if( res == PLATFORM_TIMER_INT_TOO_SHORT )
     return luaL_error( L, "timer interval too small" );
+  else if( res == PLATFORM_TIMER_INT_TOO_LONG )
+    return luaL_error( L, "timer interval too long" );
   else if( res == PLATFORM_TIMER_INT_INVALID_ID )
-    return luaL_error( L, "mach interrupt cannot be set on this timer" );
+    return luaL_error( L, "match interrupt cannot be set on this timer" );
   return 0;
 }
 #endif // #ifdef BUILD_LUA_INT_HANDLERS
@@ -170,7 +186,8 @@ const LUA_REG_TYPE tmr_map[] =
   { LSTRKEY( "delay" ), LFUNCVAL( tmr_delay ) },
   { LSTRKEY( "read" ), LFUNCVAL( tmr_read ) },
   { LSTRKEY( "start" ), LFUNCVAL( tmr_start ) },
-  { LSTRKEY( "gettimediff" ), LFUNCVAL( tmr_gettimediff ) },  
+  { LSTRKEY( "gettimediff" ), LFUNCVAL( tmr_gettimediff ) },
+  { LSTRKEY( "getdiffnow" ), LFUNCVAL( tmr_getdiffnow ) },
   { LSTRKEY( "getmindelay" ), LFUNCVAL( tmr_getmindelay ) },
   { LSTRKEY( "getmaxdelay" ), LFUNCVAL( tmr_getmaxdelay ) },
   { LSTRKEY( "setclock" ), LFUNCVAL( tmr_setclock ) },
@@ -183,6 +200,7 @@ const LUA_REG_TYPE tmr_map[] =
 #endif
 #if VTMR_NUM_TIMERS > 0  
   { LSTRKEY( "__index" ), LFUNCVAL( tmr_mt_index ) },
+  { LSTRKEY( "SYS_TIMER" ), LNUMVAL( PLATFORM_TIMER_SYS_ID ) },
 #endif  
 #if LUA_OPTIMIZE_MEMORY > 0 && defined( BUILD_LUA_INT_HANDLERS )
   { LSTRKEY( "INT_ONESHOT" ), LNUMVAL( PLATFORM_TIMER_INT_ONESHOT ) },
@@ -202,6 +220,11 @@ LUALIB_API int luaopen_tmr( lua_State *L )
   lua_pushvalue( L, -1 );
   lua_setmetatable( L, -2 );  
 #endif // #if VTMR_NUM_TIMERS > 0
+  MOD_REG_NUMBER( L, "SYS_TIMER", PLATFORM_TIMER_SYS_ID );
+#ifdef BUILD_LUA_INT_HANDLERS
+  MOD_REG_NUMBER( L, "INT_ONESHOT", PLATFORM_TIMER_INT_ONESHOT );
+  MOD_REG_NUMBER( L, "INT_CYCLIC", PLATFORM_TIMER_INT_CYCLIC );
+#endif //#ifdef BUILD_LUA_INT_HANDLERS
   return 1;
 #endif // #if LUA_OPTIMIZE_MEMORY > 0
 }
diff --git a/src/modules/uart.c b/src/modules/uart.c
index b9138a11..febea5a9 100644
--- a/src/modules/uart.c
+++ b/src/modules/uart.c
@@ -22,6 +22,8 @@ enum
   UART_READ_MODE_MAXSIZE
 };
 
+#define UART_INFINITE_TIMEOUT PLATFORM_TIMER_INF_TIMEOUT
+
 // Lua: actualbaud = setup( id, baud, databits, parity, stopbits )
 static int uart_setup( lua_State* L )
 {
@@ -71,14 +73,16 @@ static int uart_write( lua_State* L )
   return 0;
 }
 
+// Lua: uart.read( id, format, [timeout], [timer_id] )
 static int uart_read( lua_State* L )
 {
   int id, res, mode, issign;
-  unsigned timer_id = 0;
-  s32 timeout = PLATFORM_UART_INFINITE_TIMEOUT, maxsize = 0, count = 0;
+  unsigned timer_id = PLATFORM_TIMER_SYS_ID;
+  s32 maxsize = 0, count = 0;
   const char *fmt;
   luaL_Buffer b;
   char cres;
+  timer_data_type timeout = PLATFORM_TIMER_INF_TIMEOUT;
   
   id = luaL_checkinteger( L, 1 );
   MOD_CHECK_ID( uart, id );
@@ -104,14 +108,7 @@ static int uart_read( lua_State* L )
   }
 
   // Check timeout and timer id
-  if( lua_gettop( L ) >= 3 )
-  {
-    timeout = luaL_checkinteger( L, 3 );
-    if( ( timeout < 0 ) && ( timeout != PLATFORM_UART_INFINITE_TIMEOUT ) )
-      return luaL_error( L, "invalid timeout value" );      
-    if( ( timeout != PLATFORM_UART_INFINITE_TIMEOUT ) && ( timeout != 0 ) )
-      timer_id = luaL_checkinteger( L, 4 );    
-  }
+  cmn_get_timeout_data( L, 3, &timeout, &timer_id );
 
   // Read data
   luaL_buffinit( L, &b );
@@ -151,21 +148,13 @@ static int uart_getchar( lua_State* L )
 {
   int id, res;
   char cres;
-  unsigned timer_id = 0;
-  s32 timeout = PLATFORM_UART_INFINITE_TIMEOUT;
+  unsigned timer_id = PLATFORM_TIMER_SYS_ID;
+  timer_data_type timeout = PLATFORM_TIMER_INF_TIMEOUT;
   
   id = luaL_checkinteger( L, 1 );
   MOD_CHECK_ID( uart, id );
-
   // Check timeout and timer id
-  if( lua_gettop( L ) >= 2 )
-  {
-    timeout = luaL_checkinteger( L, 2 );
-    if( ( timeout < 0 ) && ( timeout != PLATFORM_UART_INFINITE_TIMEOUT ) )
-      return luaL_error( L, "invalid timeout value" );      
-    if( ( timeout != PLATFORM_UART_INFINITE_TIMEOUT ) && ( timeout != 0 ) )
-      timer_id = luaL_checkinteger( L, 3 );    
-  }
+  cmn_get_timeout_data( L, 2, &timeout, &timer_id );
   res = platform_uart_recv( id, timer_id, timeout );
   if( res == -1 )
     lua_pushstring( L, "" );
@@ -252,10 +241,11 @@ const LUA_REG_TYPE uart_map[] =
   { LSTRKEY( "STOP_1_5" ), LNUMVAL( PLATFORM_UART_STOPBITS_1_5 ) },
   { LSTRKEY( "STOP_2" ), LNUMVAL( PLATFORM_UART_STOPBITS_2 ) },
   { LSTRKEY( "NO_TIMEOUT" ), LNUMVAL( 0 ) },
-  { LSTRKEY( "INF_TIMEOUT" ), LNUMVAL( PLATFORM_UART_INFINITE_TIMEOUT ) },
+  { LSTRKEY( "INF_TIMEOUT" ), LNUMVAL( UART_INFINITE_TIMEOUT ) },
   { LSTRKEY( "FLOW_NONE" ), LNUMVAL( PLATFORM_UART_FLOW_NONE ) },
   { LSTRKEY( "FLOW_RTS" ), LNUMVAL( PLATFORM_UART_FLOW_RTS ) },
   { LSTRKEY( "FLOW_CTS" ), LNUMVAL( PLATFORM_UART_FLOW_CTS ) },
+  { LSTRKEY( "SYS_TIMER" ), LNUMVAL( PLATFORM_TIMER_SYS_ID ) },
 #endif
 #if LUA_OPTIMIZE_MEMORY > 0 && defined( BUILD_SERMUX )
   { LSTRKEY( "__metatable" ), LROVAL( uart_map ) },
@@ -281,7 +271,9 @@ LUALIB_API int luaopen_uart( lua_State *L )
   
   // Add the "none" and "infinite" constant used in recv()
   MOD_REG_NUMBER( L, "NO_TIMEOUT", 0 );
-  MOD_REG_NUMBER( L, "INF_TIMEOUT", PLATFORM_UART_INFINITE_TIMEOUT );
+  MOD_REG_NUMBER( L, "INF_TIMEOUT", UART_INFINITE_TIMEOUT );
+  // Also add the system timer ID
+  MOD_REG_NUMBER( L, "SYS_TIMER", PLATFORM_TIMER_SYS_ID );
 
   // Add the UART flow constants
   MOD_REG_NUMBER( L, "FLOW_RTS", PLATFORM_UART_FLOW_RTS );
diff --git a/src/platform/at91sam7x/conf.lua b/src/platform/at91sam7x/conf.lua
index f03ddb43..53834b12 100644
--- a/src/platform/at91sam7x/conf.lua
+++ b/src/platform/at91sam7x/conf.lua
@@ -2,7 +2,7 @@
 
 local cpumode = ( builder:get_option( 'cpumode' ) or 'thumb' ):lower()
 
-specific_files = "board_cstartup.s board_lowlevel.c board_memories.c usart.c pmc.c pio.c platform.c tc.c pwmc.c aic.c platform_int.c"
+specific_files = "board_cstartup.s board_lowlevel.c board_memories.c usart.c pmc.c pio.c platform.c tc.c pwmc.c aic.c platform_int.c pit.c"
 local ldscript
 if comp.cpu:upper() == 'AT91SAM7X256' then
   ldscript = "flash256.lds"
diff --git a/src/platform/at91sam7x/conf.py b/src/platform/at91sam7x/conf.py
index 26607164..eaaec673 100644
--- a/src/platform/at91sam7x/conf.py
+++ b/src/platform/at91sam7x/conf.py
@@ -2,7 +2,7 @@
 
 cpumode = ARGUMENTS.get( 'cpumode', 'thumb' ).lower()
 
-specific_files = "board_cstartup.s board_lowlevel.c board_memories.c usart.c pmc.c pio.c platform.c tc.c pwmc.c aic.c platform_int.c"
+specific_files = "board_cstartup.s board_lowlevel.c board_memories.c usart.c pmc.c pio.c platform.c tc.c pwmc.c aic.c platform_int.c pit.c"
 if comp[ 'cpu' ] == 'AT91SAM7X256':
   ldscript = "flash256.lds"
   comp.Append(CPPDEFINES = 'at91sam7x256')
diff --git a/src/platform/at91sam7x/pit.c b/src/platform/at91sam7x/pit.c
new file mode 100644
index 00000000..7d45324d
--- /dev/null
+++ b/src/platform/at91sam7x/pit.c
@@ -0,0 +1,129 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+//------------------------------------------------------------------------------
+//         Headers
+//------------------------------------------------------------------------------
+
+#include "pit.h"
+#include 
+
+//------------------------------------------------------------------------------
+//         Global functions
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+/// Initialize the Periodic Interval Timer to generate a tick at the specified
+/// period, given the current master clock frequency.
+/// \param period  Period in µsecond.
+/// \param pit_frequency  Master clock frequency in MHz.
+//------------------------------------------------------------------------------
+void PIT_Init(unsigned int period, unsigned int pit_frequency)
+{
+    AT91C_BASE_PITC->PITC_PIMR = period? (period * pit_frequency + 8) >> 4 : 0;
+    AT91C_BASE_PITC->PITC_PIMR |= AT91C_PITC_PITEN;
+}
+
+//------------------------------------------------------------------------------
+/// Set the Periodic Interval Value of the PIT.
+/// \param piv  PIV value to set.
+//------------------------------------------------------------------------------
+void PIT_SetPIV(unsigned int piv)
+{
+    AT91C_BASE_PITC->PITC_PIMR = (AT91C_BASE_PITC->PITC_PIMR & AT91C_PITC_PIV)
+                                 | piv;
+}
+
+//------------------------------------------------------------------------------
+/// Enables the PIT if this is not already the case.
+//------------------------------------------------------------------------------
+void PIT_Enable(void)
+{
+    AT91C_BASE_PITC->PITC_PIMR |= AT91C_PITC_PITEN;
+}
+//------------------------------------------------------------------------------
+/// Disables the PIT
+//------------------------------------------------------------------------------
+void PIT_Disable(void)
+{
+    AT91C_BASE_PITC->PITC_PIMR &= ~AT91C_PITC_PITEN;
+}
+
+//----------------------------------------------------------------------------
+/// Enable the PIT periodic interrupt.
+//----------------------------------------------------------------------------
+void PIT_EnableIT(void)
+{
+    AT91C_BASE_PITC->PITC_PIMR |= AT91C_PITC_PITIEN;
+}
+
+//------------------------------------------------------------------------------
+/// Disables the PIT periodic interrupt.
+//------------------------------------------------------------------------------
+void PIT_DisableIT(void)
+{
+    AT91C_BASE_PITC->PITC_PIMR &= ~AT91C_PITC_PITIEN;
+}
+
+//------------------------------------------------------------------------------
+/// Returns the value of the PIT mode register.
+/// \return PIT_MR value.
+//------------------------------------------------------------------------------
+unsigned int PIT_GetMode(void)
+{
+    return AT91C_BASE_PITC->PITC_PIMR;
+}
+
+//------------------------------------------------------------------------------
+/// Returns the value of the PIT status register, clearing it as a side effect.
+/// \return PIT_SR value.
+//------------------------------------------------------------------------------
+unsigned int PIT_GetStatus(void)
+{
+    return AT91C_BASE_PITC->PITC_PISR;
+}
+
+//------------------------------------------------------------------------------
+/// Returns the value of the PIT Image Register, to read PICNT and CPIV without
+/// clearing the current values.
+/// \return PIT_PIIR value.
+//------------------------------------------------------------------------------
+unsigned int PIT_GetPIIR(void)
+{
+    return AT91C_BASE_PITC->PITC_PIIR;
+}
+
+//------------------------------------------------------------------------------
+/// Returns the value of the PIT Value Register, clearing it as a side effect.
+/// \return PIT_PIVR value.
+//------------------------------------------------------------------------------
+unsigned int PIT_GetPIVR(void)
+{
+    return AT91C_BASE_PITC->PITC_PIVR;
+}
diff --git a/src/platform/at91sam7x/pit.h b/src/platform/at91sam7x/pit.h
new file mode 100644
index 00000000..13cf0eea
--- /dev/null
+++ b/src/platform/at91sam7x/pit.h
@@ -0,0 +1,79 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+//------------------------------------------------------------------------------
+/// \unit
+///
+/// !Purpose
+///
+/// Interface for configuration the Periodic Interval Timer (PIT) peripheral.
+///
+/// !Usage
+///
+/// -# Initialize the PIT with the desired period using PIT_Init().
+///    Alternatively, the Periodic Interval Value (PIV) can be configured
+///    manually using PIT_SetPIV().
+/// -# Start the PIT counting using PIT_Enable().
+/// -# Enable & disable the PIT interrupt using PIT_EnableIT() and
+///    PIT_DisableIT().
+/// -# Retrieve the current status of the PIT using PIT_GetStatus().
+/// -# To get the current value of the internal counter and the number of ticks
+///    that have occurred, use either PIT_GetPIVR() or PIT_GetPIIR() depending
+///    on whether you want the values to be cleared or not.
+//------------------------------------------------------------------------------
+
+#ifndef PIT_H
+#define PIT_H
+
+//------------------------------------------------------------------------------
+//         Global Functions
+//------------------------------------------------------------------------------
+
+extern void PIT_Init(unsigned int period, unsigned int pit_frequency);
+
+extern void PIT_SetPIV(unsigned int piv);
+
+extern void PIT_Enable(void);
+
+extern void PIT_Disable(void);
+
+extern void PIT_EnableIT(void);
+
+extern void PIT_DisableIT(void);
+
+extern unsigned int PIT_GetMode(void);
+
+extern unsigned int PIT_GetStatus(void);
+
+extern unsigned int PIT_GetPIIR(void);
+
+extern unsigned int PIT_GetPIVR(void);
+
+#endif //#ifndef PIT_H
+
diff --git a/src/platform/at91sam7x/platform.c b/src/platform/at91sam7x/platform.c
index 2f25e893..5369cc42 100644
--- a/src/platform/at91sam7x/platform.c
+++ b/src/platform/at91sam7x/platform.c
@@ -1,4 +1,4 @@
-// Platform-dependent functions
+// platform-dependent functions
 
 #include "platform.h"
 #include "type.h"
@@ -21,6 +21,7 @@
 #include "aic.h"
 #include "platform_conf.h"
 #include "buf.h"
+#include "pit.h"
 
 // "Stubs" used for our interrupt handlers
 // Just a trick to avoid interworking and some other complications
@@ -33,6 +34,41 @@
   "bx   r0\n\t"\
  )\
 
+// ****************************************************************************
+// AT91SAM7X system timer
+// We implement this using the PIT, as it has a 20-bit counter (the timers only
+// have 16-bit counters) and is not used by eLua in any other way. It is clocked
+// at 3MHz (MCLK/16) which means we have 3 ticks per microsecond. To keep things
+// as precise as possible, we choose the counter limit to be a multiple of 3.
+// This translates to limit = 1048575 (kept as high as possible to minimize system
+// impact), which means PIV = 1048574 (since the period is PIV + 1) which in turn
+// means 349525us/interrupt
+
+#define SYSTIMER_US_PER_INTERRUPT 349525
+#define SYSTIMER_LIMIT            1048574
+#define SYSTIMER_MASK             ( ( 1 << 20 ) - 1 )
+
+void __isr_pit_helper()
+{
+  PIT_GetPIVR();
+  cmn_systimer_periodic();
+  AT91C_BASE_AIC->AIC_ICCR = 1 << AT91C_ID_SYS;
+}
+
+static void __attribute__((naked)) ISR_Pit()
+{
+  INT_STUB( __isr_pit_helper );
+}
+
+static void platform_systimer_init()
+{
+  PIT_SetPIV( SYSTIMER_LIMIT );
+  AIC_ConfigureIT( AT91C_ID_SYS, 0, ISR_Pit );
+  PIT_EnableIT();
+  AIC_EnableIT( AT91C_ID_SYS );
+  PIT_Enable();
+}
+
 // ****************************************************************************
 // Platform initialization
 
@@ -98,7 +134,12 @@ int platform_init()
   AT91C_BASE_TC2->TC_IER = AT91C_TC_CPCS;
   AIC_EnableIT( AT91C_ID_TC2 );  
   TC_Start( AT91C_BASE_TC2 );
-#endif
+#endif  
+
+  // Initialize the system timer
+  cmn_systimer_set_base_freq( BOARD_MCK / 16 );
+  cmn_systimer_set_interrupt_period_us( SYSTIMER_US_PER_INTERRUPT );
+  platform_systimer_init();
     
   return PLATFORM_OK;
 } 
@@ -228,7 +269,7 @@ void platform_s_uart_send( unsigned id, u8 data )
   USART_Write( base, data, 0 );
 }
 
-int platform_s_uart_recv( unsigned id, s32 timeout )
+int platform_s_uart_recv( unsigned id, timer_data_type timeout )
 {
   AT91S_USART* base = id == 0 ? AT91C_BASE_US0 : AT91C_BASE_US1;  
     
@@ -276,7 +317,7 @@ static u32 platform_timer_set_clock( unsigned id, u32 clock )
   return BOARD_MCK / clkdivs[ mini ];
 }
 
-void platform_s_timer_delay( unsigned id, u32 delay_us )
+void platform_s_timer_delay( unsigned id, timer_data_type delay_us )
 {
   AT91S_TC* base = ( AT91S_TC* )timer_base[ id ];  
   u32 freq;
@@ -292,7 +333,7 @@ void platform_s_timer_delay( unsigned id, u32 delay_us )
   while( base->TC_CV < final );  
 }
 
-u32 platform_s_timer_op( unsigned id, int op, u32 data )
+timer_data_type platform_s_timer_op( unsigned id, int op, timer_data_type data )
 {
   u32 res = 0;
   AT91S_TC* base = ( AT91S_TC* )timer_base[ id ];
@@ -310,14 +351,6 @@ u32 platform_s_timer_op( unsigned id, int op, u32 data )
       res = base->TC_CV;
       break;
       
-    case PLATFORM_TIMER_OP_GET_MAX_DELAY:
-      res = platform_timer_get_diff_us( id, 0, 0xFFFF );
-      break;
-      
-    case PLATFORM_TIMER_OP_GET_MIN_DELAY:
-      res = platform_timer_get_diff_us( id, 0, 1 );
-      break;      
-      
     case PLATFORM_TIMER_OP_SET_CLOCK:
       res = platform_timer_set_clock( id, data );
       break;
@@ -325,10 +358,34 @@ u32 platform_s_timer_op( unsigned id, int op, u32 data )
     case PLATFORM_TIMER_OP_GET_CLOCK:
       res = platform_timer_get_clock( id );
       break;
+
+    case PLATFORM_TIMER_OP_GET_MAX_CNT:
+      res = 0xFFFF;
+      break;
   }
   return res;
 }
 
+u64 platform_timer_sys_raw_read()
+{
+  return PIT_GetPIIR() & SYSTIMER_MASK;
+}
+
+void platform_timer_sys_disable_int()
+{
+  PIT_DisableIT();
+}
+
+void platform_timer_sys_enable_int()
+{
+  PIT_EnableIT();
+}
+
+timer_data_type platform_timer_read_sys()
+{
+  return cmn_systimer_get();
+}
+
 // ****************************************************************************
 // PWMs
 
@@ -338,8 +395,8 @@ u32 platform_s_timer_op( unsigned id, int op, u32 data )
 // PWM pins
 static const Pin pwm_pins[] = { PIN_PWMC_PWM0, PIN_PWMC_PWM1, PIN_PWMC_PWM2, PIN_PWMC_PWM3 };
 
-// Helper function: return the PWM clock
-static u32 platform_pwm_get_clock( unsigned id )
+// Return the PWM clock
+u32 platform_pwm_get_clock( unsigned id )
 {
   u32 cfg = AT91C_BASE_PWMC->PWMC_CH[ id ].PWMC_CMR;
   u16 clkdata;
@@ -358,8 +415,8 @@ static u32 platform_pwm_get_clock( unsigned id )
   }
 }
 
-// Helper function: set the PWM clock
-static u32 platform_pwm_set_clock( unsigned id, u32 clock )
+// Set the PWM clock
+u32 platform_pwm_set_clock( unsigned id, u32 clock )
 {
   if( id < 2 )
     PWMC_ConfigureClocks( clock, 0, BOARD_MCK );
@@ -386,30 +443,14 @@ u32 platform_pwm_setup( unsigned id, u32 frequency, unsigned duty )
   return pwmclk / period;
 }
 
-u32 platform_pwm_op( unsigned id, int op, u32 data )
+void platform_pwm_start( unsigned id )
 {
-  u32 res = 0;
-    
-  switch( op )
-  {
-    case PLATFORM_PWM_OP_SET_CLOCK:
-      res = platform_pwm_set_clock( id, data );
-      break;
-      
-    case PLATFORM_PWM_OP_GET_CLOCK:
-      res = platform_pwm_get_clock( id );
-      break;
-      
-    case PLATFORM_PWM_OP_START:
-      PIO_Configure( pwm_pins + id, 1 );    
-      res = AT91C_BASE_PWMC->PWMC_ISR;
-      break;
-      
-    case PLATFORM_PWM_OP_STOP:
-      platform_pio_op( 1, 1 << ( 19 + id ), PLATFORM_IO_PIN_DIR_INPUT );
-      break;
-  }
-  
-  return res;
+  volatile u32 dummy;
+  PIO_Configure( pwm_pins + id, 1 );    
+  dummy = AT91C_BASE_PWMC->PWMC_ISR;
 }
 
+void platform_pwm_stop( unsigned id )
+{
+  platform_pio_op( 1, 1 << ( 19 + id ), PLATFORM_IO_PIN_DIR_INPUT );
+}
diff --git a/src/platform/at91sam7x/platform_conf.h b/src/platform/at91sam7x/platform_conf.h
index ae8c9441..699203b8 100644
--- a/src/platform/at91sam7x/platform_conf.h
+++ b/src/platform/at91sam7x/platform_conf.h
@@ -19,17 +19,18 @@
 #define BUILD_TERM
 #define BUILD_CON_GENERIC
 //#define BUILD_RPC
-#define BUILD_RFS
-#define BUILD_SERMUX
+//#define BUILD_RFS
+//#define BUILD_SERMUX
 #define BUILD_C_INT_HANDLERS
 
+#define PLATFORM_HAS_SYSTIMER
+
 // *****************************************************************************
 // UART/Timer IDs configuration data (used in main.c)
 
-#define CON_UART_ID         ( SERMUX_SERVICE_ID_FIRST + 1 )
-//#define CON_UART_ID         0
+//#define CON_UART_ID         ( SERMUX_SERVICE_ID_FIRST + 1 )
+#define CON_UART_ID           0
 #define CON_UART_SPEED        115200
-#define CON_TIMER_ID          0
 #define TERM_LINES            25
 #define TERM_COLS             80
 
@@ -82,14 +83,13 @@
 
 // RPC boot options
 #define RPC_UART_ID           CON_UART_ID
-#define RPC_TIMER_ID          CON_TIMER_ID
 #define RPC_UART_SPEED        CON_UART_SPEED
 
 // Enable RX buffering on UART
 #define BUF_ENABLE_UART
 #define CON_BUF_SIZE          BUF_SIZE_128
 
-// CPU frequency (needed by the CPU module, 0 if not used)
+// CPU frequency (needed by the CPU module and MMCFS code, 0 if not used)
 #define CPU_FREQUENCY         BOARD_MCK
 
 // PIO prefix ('0' for P0, P1, ... or 'A' for PA, PB, ...)
@@ -111,9 +111,9 @@
 #define MEM_START_ADDRESS     { ( void* )end }
 #define MEM_END_ADDRESS       { ( void* )( SRAM_ORIGIN + SRAM_SIZE - STACK_SIZE_TOTAL - 1 ) }
 
+/*
 #define RFS_BUFFER_SIZE       BUF_SIZE_512
 #define RFS_UART_ID           ( SERMUX_SERVICE_ID_FIRST )
-#define RFS_TIMER_ID          0
 #define RFS_TIMEOUT           100000
 #define RFS_UART_SPEED        115200
 
@@ -121,6 +121,7 @@
 #define SERMUX_PHYS_SPEED     115200
 #define SERMUX_NUM_VUART      2
 #define SERMUX_BUFFER_SIZES   { RFS_BUFFER_SIZE, CON_BUF_SIZE }
+*/
 
 // Interrupt list
 #define INT_UART_RX           ELUA_INT_FIRST_ID
diff --git a/src/platform/avr32/EVK1100/evk1100_conf.h b/src/platform/avr32/EVK1100/evk1100_conf.h
index 11999228..46d8ef2a 100644
--- a/src/platform/avr32/EVK1100/evk1100_conf.h
+++ b/src/platform/avr32/EVK1100/evk1100_conf.h
@@ -33,7 +33,6 @@
 //#define CON_UART_ID         ( SERMUX_SERVICE_ID_FIRST + 1 )
 #define CON_UART_ID         0
 #define CON_UART_SPEED      115200
-#define CON_TIMER_ID        0
 #define TERM_LINES          25
 #define TERM_COLS           80
 
@@ -87,6 +86,7 @@
   _ROM( AUXLIB_UART, luaopen_uart, uart_map )\
   _ROM( AUXLIB_PIO, luaopen_pio, pio_map )\
   _ROM( AUXLIB_PWM, luaopen_pwm, pwm_map )\
+  _ROM( AUXLIB_I2C, luaopen_i2c, i2c_map )\
   _ROM( AUXLIB_SPI, luaopen_spi, spi_map )\
   _ROM( AUXLIB_TMR, luaopen_tmr, tmr_map )\
   _ROM( AUXLIB_TERM, luaopen_term, term_map )\
@@ -104,7 +104,7 @@
 
 // Virtual timers (0 if not used)
 #define VTMR_NUM_TIMERS       4
-#define VTMR_FREQ_HZ          4
+#define VTMR_FREQ_HZ          10
 
 // Number of resources (0 if not available/not implemented)
 #define NUM_PIO               4
@@ -115,13 +115,13 @@
 #else
 #define NUM_TIMER             3
 #endif
-#define NUM_PWM               7
+#define NUM_PWM               6
+#define NUM_I2C               1
 #define NUM_ADC               8
 #define NUM_CAN               0
 
 // RPC boot options
 #define RPC_UART_ID           CON_UART_ID
-#define RPC_TIMER_ID          CON_TIMER_ID
 #define RPC_UART_SPEED        CON_UART_SPEED
 
 // Enable RX buffering on UART
@@ -138,13 +138,11 @@
 #define ADC_NUM_TIMERS        0
 
 // SD/MMC Filesystem Setup
-#define MMCFS_TICK_HZ     10
-#define MMCFS_TICK_MS     ( 1000 / MMCFS_TICK_HZ )
 #define MMCFS_SPI_NUM     5
 #define MMCFS_CS_PORT     0
 #define MMCFS_CS_PIN      SD_MMC_SPI_NPCS_PIN
 
-// CPU frequency (needed by the CPU module, 0 if not used)
+// CPU frequency (needed by the CPU module and MMCFS code, 0 if not used)
 #define CPU_FREQUENCY         REQ_CPU_FREQ
 
 // PIO prefix ('0' for P0, P1, ... or 'A' for PA, PB, ...)
@@ -154,6 +152,7 @@
 // #define PIO_PIN_ARRAY { n1, n2, ... } to define pins per port in an array
 // Use #define PIO_PINS_PER_PORT 0 if this isn't needed
 #define PIO_PIN_ARRAY         { 31, 32, 32, 14 }
+#define AVR32_NUM_GPIO        110 // actually 109, but consider also PA31
 
 // Allocator data: define your free memory zones here in two arrays
 // (start address and end address)
@@ -162,7 +161,6 @@
 
 #define RFS_BUFFER_SIZE       BUF_SIZE_512
 #define RFS_UART_ID           ( SERMUX_SERVICE_ID_FIRST )
-#define RFS_TIMER_ID          0
 #define RFS_TIMEOUT           100000
 #define RFS_UART_SPEED        115200
 
@@ -171,16 +169,6 @@
 //#define SERMUX_NUM_VUART      2
 //#define SERMUX_BUFFER_SIZES   { RFS_BUFFER_SIZE, CON_BUF_SIZE }
 
-// Interrupt queue size
-#define PLATFORM_INT_QUEUE_LOG_SIZE 5
-
-// Interrupt list
-#define INT_UART_RX           ELUA_INT_FIRST_ID
-#define INT_ELUA_LAST         INT_UART_RX
-
-#define PLATFORM_CPU_CONSTANTS\
- _C( INT_UART_RX )
-
 // *****************************************************************************
 // CPU constants that should be exposed to the eLua "cpu" module
 
diff --git a/src/platform/avr32/EVK1101/evk1101_conf.h b/src/platform/avr32/EVK1101/evk1101_conf.h
index f659fd47..53d628ee 100644
--- a/src/platform/avr32/EVK1101/evk1101_conf.h
+++ b/src/platform/avr32/EVK1101/evk1101_conf.h
@@ -14,13 +14,13 @@
 #define BUILD_CON_GENERIC
 //#define BUILD_RPC
 #define BUILD_C_INT_HANDLERS
+#define BUILD_ADC
 
 // *****************************************************************************
 // UART/Timer IDs configuration data (used in main.c)
 
 #define CON_UART_ID         1
 #define CON_UART_SPEED      115200
-#define CON_TIMER_ID        0
 #define TERM_LINES          25
 #define TERM_COLS           80
 
@@ -43,6 +43,12 @@
 #define BUILD_RPC
 #endif
 
+#ifdef BUILD_ADC
+#define ADCLINE _ROM( AUXLIB_ADC, luaopen_adc, adc_map )
+#else
+#define ADCLINE
+#endif
+
 #if defined( BUILD_RPC ) 
 #define RPCLINE _ROM( AUXLIB_RPC, luaopen_rpc, rpc_map )
 #else
@@ -57,6 +63,7 @@
   _ROM( AUXLIB_TMR, luaopen_tmr, tmr_map )\
   _ROM( AUXLIB_TERM, luaopen_term, term_map )\
   _ROM( AUXLIB_CPU, luaopen_cpu, cpu_map )\
+  ADCLINE\
   RPCLINE\
   _ROM( AUXLIB_BIT, luaopen_bit, bit_map )\
   _ROM( AUXLIB_PACK, luaopen_pack, pack_map )\
@@ -67,7 +74,7 @@
 
 // Virtual timers (0 if not used)
 #define VTMR_NUM_TIMERS       4
-#define VTMR_FREQ_HZ          4
+#define VTMR_FREQ_HZ          10
 
 // Number of resources (0 if not available/not implemented)
 #define NUM_PIO               2
@@ -78,27 +85,29 @@
 #else
 #define NUM_TIMER             3
 #endif
-#define NUM_PWM               0
-#define NUM_ADC               0
+#define NUM_PWM               6
+#define NUM_ADC               8
 #define NUM_CAN               0
 
 // RPC boot options
 #define RPC_UART_ID           CON_UART_ID
-#define RPC_TIMER_ID          CON_TIMER_ID
 #define RPC_UART_SPEED        CON_UART_SPEED
 
 // Enable RX buffering on UART
 #define BUF_ENABLE_UART
 #define CON_BUF_SIZE          BUF_SIZE_128
 
+// ADC Configuration Params
+#define ADC_BIT_RESOLUTION    10
+#define BUF_ENABLE_ADC
+#define ADC_BUF_SIZE          BUF_SIZE_2
+
 // SD/MMC Filesystem Setup
-#define MMCFS_TICK_HZ     10
-#define MMCFS_TICK_MS     ( 1000 / MMCFS_TICK_HZ )
 #define MMCFS_SPI_NUM     1
 #define MMCFS_CS_PORT     0  //PA17
 #define MMCFS_CS_PIN      SD_MMC_SPI_NPCS_PIN
 
-// CPU frequency (needed by the CPU module, 0 if not used)
+// CPU frequency (needed by the CPU module and MMCFS code, 0 if not used)
 #define CPU_FREQUENCY         REQ_CPU_FREQ
 
 // PIO prefix ('0' for P0, P1, ... or 'A' for PA, PB, ...)
@@ -108,22 +117,13 @@
 // #define PIO_PIN_ARRAY { n1, n2, ... } to define pins per port in an array
 // Use #define PIO_PINS_PER_PORT 0 if this isn't needed
 #define PIO_PIN_ARRAY         { 32, 12 }
+#define AVR32_NUM_GPIO        44
 
 // Allocator data: define your free memory zones here in two arrays
 // (start address and end address)
 #define MEM_START_ADDRESS     { ( void* )end }
 #define MEM_END_ADDRESS       { ( void* )( AVR32_SRAM_SIZE - STACK_SIZE_TOTAL - 1 ) }    
 
-// Interrupt queue size
-#define PLATFORM_INT_QUEUE_LOG_SIZE 5
-
-// Interrupt list
-#define INT_UART_RX           ELUA_INT_FIRST_ID
-#define INT_ELUA_LAST         INT_UART_RX
-
-#define PLATFORM_CPU_CONSTANTS\
- _C( INT_UART_RX )
- 
 // *****************************************************************************
 // CPU constants that should be exposed to the eLua "cpu" module
 
diff --git a/src/platform/avr32/MIZAR32/mizar32_conf.h b/src/platform/avr32/MIZAR32/mizar32_conf.h
index cab9aa32..61af4d68 100644
--- a/src/platform/avr32/MIZAR32/mizar32_conf.h
+++ b/src/platform/avr32/MIZAR32/mizar32_conf.h
@@ -16,30 +16,51 @@
 
 #define BUILD_MMCFS
 //#define BUILD_XMODEM
-#define BUILD_SHELL
-#define BUILD_ROMFS
-//#define BUILD_TERM
-//#define BUILD_CON_GENERIC
+//#define BUILD_SHELL
+//#define BUILD_ROMFS
+#define BUILD_CON_GENERIC
 //#define BUILD_RPC
 #define BUF_ENABLE_UART
 #define BUILD_C_INT_HANDLERS
-//#define BUILD_ADC
-#define BUILA_LUA_INT_HANDLERS
+#define BUILD_LUA_INT_HANDLERS
 //#define BUILD_RFS
 //#define BUILD_SERMUX
 
-#define BUILD_UIP
+#if defined( ELUA_CPU_AT32UC3A0128 )
+  // Build options for 120KB image
+# define RAM_SIZE 0x8000
+#else
+  // Build options for 256KB and 512KB flash
+# define RAM_SIZE 0x10000
+# define BUILD_ADC
+# define BUILD_LCD
+# define BUILD_TERM
+# define BUILD_UIP
+#endif
+
+#ifdef BUILD_UIP
 //#define BUILD_DHCPC
 #define BUILD_DNS
-#define BUILD_CON_TCP
+//#define BUILD_CON_TCP
+#endif
+
+// ****************************************************************************
+// Auxiliary libraries that will be compiled for this platform
+
+// The name of the platform specific libs table
+#ifdef BUILD_LCD
+#define PS_LIB_TABLE_NAME   "mizar32"
+#endif
 
 // *****************************************************************************
 // UART/Timer IDs configuration data (used in main.c)
 
-//#define CON_UART_ID         ( SERMUX_SERVICE_ID_FIRST + 1 )
-#define CON_UART_ID         0
+#ifdef BUILD_SERMUX
+# define CON_UART_ID         ( SERMUX_SERVICE_ID_FIRST + 1 )
+#else
+# define CON_UART_ID         0
+#endif
 #define CON_UART_SPEED      115200
-#define CON_TIMER_ID        0
 #define TERM_LINES          25
 #define TERM_COLS           80
 
@@ -75,23 +96,41 @@
 #else
 #define ADCLINE
 #endif
+
 #ifdef BUILD_UIP
 #define NETLINE  _ROM( AUXLIB_NET, luaopen_net, net_map )
 #else
 #define NETLINE
 #endif
 
-#if defined( BUILD_RPC ) 
+#if defined( BUILD_RPC )
 #define RPCLINE _ROM( AUXLIB_RPC, luaopen_rpc, rpc_map )
 #else
 #define RPCLINE
 #endif
 
+#if defined( PS_LIB_TABLE_NAME )
+#define PLATLINE _ROM( PS_LIB_TABLE_NAME, luaopen_platform, platform_map )
+#else
+#define PLATLINE
+#endif
+
+#if defined( ELUA_CPU_AT32UC3A0128 )
+
+// Minimal ROM modules, to fit in 120KB
+#define LUA_PLATFORM_LIBS_ROM\
+  _ROM( AUXLIB_PD, luaopen_pd, pd_map )\
+  _ROM( AUXLIB_PIO, luaopen_pio, pio_map )\
+  _ROM( AUXLIB_TMR, luaopen_tmr, tmr_map )\
+
+#else
+
 #define LUA_PLATFORM_LIBS_ROM\
   _ROM( AUXLIB_PD, luaopen_pd, pd_map )\
   _ROM( AUXLIB_UART, luaopen_uart, uart_map )\
   _ROM( AUXLIB_PIO, luaopen_pio, pio_map )\
   _ROM( AUXLIB_PWM, luaopen_pwm, pwm_map )\
+  _ROM( AUXLIB_I2C, luaopen_i2c, i2c_map )\
   _ROM( AUXLIB_SPI, luaopen_spi, spi_map )\
   _ROM( AUXLIB_TMR, luaopen_tmr, tmr_map )\
   NETLINE\
@@ -101,15 +140,10 @@
   RPCLINE\
   _ROM( AUXLIB_BIT, luaopen_bit, bit_map )\
   _ROM( AUXLIB_PACK, luaopen_pack, pack_map )\
-  _ROM( LUA_MATHLIBNAME, luaopen_math, math_map )
+  _ROM( AUXLIB_TERM, luaopen_term, term_map )\
+  _ROM( LUA_MATHLIBNAME, luaopen_math, math_map )\
+  PLATLINE\
 
-#if MINIMAL_ROM_MODULES_TO_FIT_IN_120KB
-/* Minimal ROM modules, to fit in 120KB */
-#undef  LUA_PLATFORM_LIBS_ROM
-#define LUA_PLATFORM_LIBS_ROM\
-  _ROM( AUXLIB_PIO, luaopen_pio, pio_map )\
-  _ROM( AUXLIB_TMR, luaopen_tmr, tmr_map )\
-  NETLINE
 #endif
 
 // *****************************************************************************
@@ -117,7 +151,7 @@
 
 // Virtual timers (0 if not used)
 #define VTMR_NUM_TIMERS       4
-#define VTMR_FREQ_HZ          4
+#define VTMR_FREQ_HZ          10
 
 // Number of resources (0 if not available/not implemented)
 #define NUM_PIO               4
@@ -128,8 +162,9 @@
 #else
 #define NUM_TIMER             3
 #endif
-#define NUM_PWM               7		// PWM7 is on GPIO50
-#define NUM_ADC               8		// Though ADC3 pin is the Ethernet IRQ
+#define NUM_PWM               6         // PWM7 is on GPIO50
+#define NUM_I2C               1
+#define NUM_ADC               8         // Though ADC3 pin is the Ethernet IRQ
 #define NUM_CAN               0
 
 // As flow control seems not to work, we use a large buffer so that people
@@ -140,7 +175,6 @@
 
 // RPC boot options
 #define RPC_UART_ID           CON_UART_ID
-#define RPC_TIMER_ID          CON_TIMER_ID
 #define RPC_UART_SPEED        CON_UART_SPEED
 
 // ADC Configuration Params
@@ -153,13 +187,11 @@
 #define ADC_NUM_TIMERS        0
 
 // SD/MMC Filesystem Setup
-#define MMCFS_TICK_HZ          10
-#define MMCFS_TICK_MS          ( 1000 / MMCFS_TICK_HZ )
 #define MMCFS_SPI_NUM          4
 #define MMCFS_CS_PORT          0
 #define MMCFS_CS_PIN           SD_MMC_SPI_NPCS_PIN
 
-// CPU frequency (needed by the CPU module, 0 if not used)
+// CPU frequency (needed by the CPU module and MMCFS code, 0 if not used)
 #define CPU_FREQUENCY         REQ_CPU_FREQ
 
 // PIO prefix ('0' for P0, P1, ... or 'A' for PA, PB, ...)
@@ -169,6 +201,7 @@
 // #define PIO_PIN_ARRAY { n1, n2, ... } to define pins per port in an array
 // Use #define PIO_PINS_PER_PORT 0 if this isn't needed
 #define PIO_PIN_ARRAY         { 31, 32, 32, 14 }
+#define AVR32_NUM_GPIO        110 // actually 109, but consider also PA31
 
 #ifdef BOOTLOADER_EMBLOD
 # define ELUA_FIRMWARE_SIZE 0x80000
@@ -179,14 +212,10 @@
 // Allocator data: define your free memory zones here in two arrays
 // (start address and end address)
 #define MEM_START_ADDRESS     { ( void* )end, ( void* )( SDRAM + ELUA_FIRMWARE_SIZE ) }
-#define MEM_END_ADDRESS       { ( void* )( 0x8000 - STACK_SIZE_TOTAL - 1 ), ( void* )( SDRAM + SDRAM_SIZE - 1 ) }
-
-// Interrupt queue size
-#define PLATFORM_INT_QUEUE_LOG_SIZE 5
+#define MEM_END_ADDRESS       { ( void* )( RAM_SIZE - STACK_SIZE_TOTAL - 1 ), ( void* )( SDRAM + SDRAM_SIZE - 1 ) }
 
 #define RFS_BUFFER_SIZE       BUF_SIZE_512
 #define RFS_UART_ID           ( SERMUX_SERVICE_ID_FIRST )
-#define RFS_TIMER_ID          0
 #define RFS_TIMEOUT           100000
 #define RFS_UART_SPEED        115200
 
@@ -195,13 +224,6 @@
 //#define SERMUX_NUM_VUART      2
 //#define SERMUX_BUFFER_SIZES   { RFS_BUFFER_SIZE, CON_BUF_SIZE }
 
-// Interrupt list
-#define INT_UART_RX           ELUA_INT_FIRST_ID
-#define INT_ELUA_LAST         INT_UART_RX
-
-#define PLATFORM_CPU_CONSTANTS\
- _C( INT_UART_RX )
-
 // *****************************************************************************
 // CPU constants that should be exposed to the eLua "cpu" module
 
diff --git a/src/platform/avr32/adc.c b/src/platform/avr32/adc.c
index e3d0e296..fc1b2e4e 100644
--- a/src/platform/avr32/adc.c
+++ b/src/platform/avr32/adc.c
@@ -87,11 +87,7 @@ void adc_disable(volatile avr32_adc_t * adc, unsigned short channel)
   Assert( adc!=NULL );
   Assert( channel <= AVR32_ADC_CHANNELS_MSB ); // check if channel exist
 
-  if (adc_get_status(adc, channel) == ENABLED)
-  {
-    // disable channel
-    adc->chdr |= (1 << channel);
-  }
+  adc->chdr = (1 << channel);
 }
 
 Bool adc_get_status(volatile avr32_adc_t * adc, unsigned short channel)
diff --git a/src/platform/avr32/at32uc3a0256.ld b/src/platform/avr32/at32uc3a0256.ld
new file mode 100644
index 00000000..9a412986
--- /dev/null
+++ b/src/platform/avr32/at32uc3a0256.ld
@@ -0,0 +1,50 @@
+MEMORY
+{
+    sram (W!RX) : ORIGIN = 0x00000004, LENGTH = 0x0000FFFC
+    flash (RX) : ORIGIN = 0x80002000, LENGTH = 0x00040000 - 0x2000
+}
+
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _stext = .;
+        PROVIDE(stext = .);
+        KEEP(*(.start))
+        *(.text .text.*)
+        *(.rodata .rodata.*)
+        *(.gnu.linkonce.t.*)
+        *(.glue_7)
+        *(.glue_7t)
+        *(.gcc_except_table)
+        *(.gnu.linkonce.r.*)
+        *(.exception .exception.*)
+        . = ALIGN(4);
+        _etext = .;
+        PROVIDE(etext = .);
+    } >flash
+
+    .data : AT (_etext)
+    {
+        . = ALIGN(4);
+        _data = .;
+        *(.ramfunc .ramfunc.* .fastrun .fastrun.*)
+        *(.data .data.*)
+        *(.gnu.linkonce.d.*)
+        . = ALIGN(4);
+        _edata = .;
+    } >sram
+
+    .bss (NOLOAD) : {
+        _bss = .;
+        *(.bss .bss.*)
+        *(.gnu.linkonce.b.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = .;
+    } >sram
+
+    end = .;
+    _sstack = 0x00010000;
+}
diff --git a/src/platform/avr32/board.h b/src/platform/avr32/board.h
index b45a4c35..55bf0daa 100644
--- a/src/platform/avr32/board.h
+++ b/src/platform/avr32/board.h
@@ -120,7 +120,16 @@
   #define FRCOSC    AVR32_PM_RCOSC_FREQUENCY  //!< Default RCOsc frequency.
 #endif
 
+#if BOARD == MIZAR32
+// All Mizar32 peripherals seem to work OK at max freq:
+// All derived frequencies (sdram, USB, tmr, VTMT, SPI, UARTs, PWM, MMC)
+// compensate correctly for the different PBA freq and
+// tmr.getmaxdelay() is still just over 0.5 sec (by a hair!).
+#define REQ_CPU_FREQ      66000000
+#define REQ_PBA_FREQ      16500000
+#else
 #define REQ_CPU_FREQ      60000000
 #define REQ_PBA_FREQ      15000000
+#endif
 
 #endif  // _BOARD_H_
diff --git a/src/platform/avr32/conf.lua b/src/platform/avr32/conf.lua
index 126cf2a8..03a5c7cd 100644
--- a/src/platform/avr32/conf.lua
+++ b/src/platform/avr32/conf.lua
@@ -1,6 +1,6 @@
 -- Configuration file for the AVR32 microcontrollers
 
-specific_files = "crt0.s trampoline.s platform.c exception.s intc.c pm.c flashc.c pm_conf_clocks.c usart.c gpio.c tc.c spi.c platform_int.c adc.c pwm.c ethernet.c"
+specific_files = "crt0.s trampoline.s platform.c exception.s intc.c pm.c flashc.c pm_conf_clocks.c usart.c gpio.c tc.c spi.c platform_int.c adc.c pwm.c i2c.c ethernet.c lcd.c"
 addm( "FORAVR32" )
 
 -- See board.h for possible BOARD values.
diff --git a/src/platform/avr32/conf.py b/src/platform/avr32/conf.py
index 13f5f79d..8ccfe805 100644
--- a/src/platform/avr32/conf.py
+++ b/src/platform/avr32/conf.py
@@ -1,6 +1,6 @@
 # Configuration file for the AVR32 microcontrollers
 
-specific_files = "crt0.s trampoline.s platform.c exception.s intc.c pm.c flashc.c pm_conf_clocks.c usart.c gpio.c tc.c spi.c platform_int.c adc.c pwm.c ethernet.c"
+specific_files = "crt0.s trampoline.s platform.c exception.s intc.c pm.c flashc.c pm_conf_clocks.c usart.c gpio.c tc.c spi.c platform_int.c adc.c pwm.c i2c.c ethernet.c lcd.c"
 comp.Append(CPPDEFINES = 'FORAVR32')
 
 # See board.h for possible BOARD values.
diff --git a/src/platform/avr32/ethernet.c b/src/platform/avr32/ethernet.c
index d0a8eb33..a0d6fc44 100644
--- a/src/platform/avr32/ethernet.c
+++ b/src/platform/avr32/ethernet.c
@@ -62,588 +62,588 @@
 
 #include "ethernet.h"
 
-/* Size of each receive buffer - DO NOT CHANGE. */
-#define RX_BUFFER_SIZE    128
-
-
-/* The buffer addresses written into the descriptors must be aligned so the
-last two bits are zero.  These bits have special meaning for the MACB
-peripheral and cannot be used as part of the address. */
-#define ADDRESS_MASK      ( ( unsigned long ) 0xFFFFFFFC )
-
-/* Bit used within the address stored in the descriptor to mark the last
-descriptor in the array. */
-#define RX_WRAP_BIT       ( ( unsigned long ) 0x02 )
-
-/* A short delay is used to wait for a buffer to become available, should
-one not be immediately available when trying to transmit a frame. */
+/* Size of each receive buffer - DO NOT CHANGE. */
+#define RX_BUFFER_SIZE    128
+
+
+/* The buffer addresses written into the descriptors must be aligned so the
+last two bits are zero.  These bits have special meaning for the MACB
+peripheral and cannot be used as part of the address. */
+#define ADDRESS_MASK      ( ( unsigned long ) 0xFFFFFFFC )
+
+/* Bit used within the address stored in the descriptor to mark the last
+descriptor in the array. */
+#define RX_WRAP_BIT       ( ( unsigned long ) 0x02 )
+
+/* A short delay is used to wait for a buffer to become available, should
+one not be immediately available when trying to transmit a frame. */
 #define BUFFER_WAIT_DELAY   ( 2 )
 
 #include "ethernet.h"
 #include "intc.h"
 #include "elua_uip.h"
 
-#ifndef FREERTOS_USED
-#define portENTER_CRITICAL           Disable_global_interrupt
-#define portEXIT_CRITICAL            Enable_global_interrupt
-#define portENTER_SWITCHING_ISR()
-#define portEXIT_SWITCHING_ISR()
+#ifndef FREERTOS_USED
+#define portENTER_CRITICAL           Disable_global_interrupt
+#define portEXIT_CRITICAL            Enable_global_interrupt
+#define portENTER_SWITCHING_ISR()
+#define portEXIT_SWITCHING_ISR()
 #endif
-
+
 #define TIMEOUT 500
 
 
-/* Buffer written to by the MACB DMA.  Must be aligned as described by the
+/* Buffer written to by the MACB DMA.  Must be aligned as described by the
 comment above the ADDRESS_MASK definition. */
 
 static volatile char pcRxBuffer[ ETHERNET_CONF_NB_RX_BUFFERS * RX_BUFFER_SIZE ] __attribute__ ((aligned (4)));
-/* Buffer read by the MACB DMA.  Must be aligned as described by the comment
+/* Buffer read by the MACB DMA.  Must be aligned as described by the comment
 above the ADDRESS_MASK definition. */
-
-static volatile char pcTxBuffer[ ETHERNET_CONF_NB_TX_BUFFERS * ETHERNET_CONF_TX_BUFFER_SIZE ] __attribute__ ((aligned (4)));
 
-/* Descriptors used to communicate between the program and the MACB peripheral.
-These descriptors hold the locations and state of the Rx and Tx buffers.
-Alignment value chosen from RBQP and TBQP registers description in datasheet. */
-
-static volatile AVR32_TxTdDescriptor xTxDescriptors[ ETHERNET_CONF_NB_TX_BUFFERS ] __attribute__ ((aligned (8)));
-static volatile AVR32_RxTdDescriptor xRxDescriptors[ ETHERNET_CONF_NB_RX_BUFFERS ] __attribute__ ((aligned (8)));
-
-/* The IP and Ethernet addresses are read from the header files. */
-unsigned char cMACAddress[ 6 ] = { ETHERNET_CONF_ETHADDR0,ETHERNET_CONF_ETHADDR1,ETHERNET_CONF_ETHADDR2,ETHERNET_CONF_ETHADDR3,ETHERNET_CONF_ETHADDR4,ETHERNET_CONF_ETHADDR5 };
-
-/*-----------------------------------------------------------*/
-
-/* See the header file for descriptions of public functions. */
-
-/*
- * Prototype for the MACB interrupt function - called by the asm wrapper.
+static volatile char pcTxBuffer[ ETHERNET_CONF_NB_TX_BUFFERS * ETHERNET_CONF_TX_BUFFER_SIZE ] __attribute__ ((aligned (4)));
+
+/* Descriptors used to communicate between the program and the MACB peripheral.
+These descriptors hold the locations and state of the Rx and Tx buffers.
+Alignment value chosen from RBQP and TBQP registers description in datasheet. */
+
+static volatile AVR32_TxTdDescriptor xTxDescriptors[ ETHERNET_CONF_NB_TX_BUFFERS ] __attribute__ ((aligned (8)));
+static volatile AVR32_RxTdDescriptor xRxDescriptors[ ETHERNET_CONF_NB_RX_BUFFERS ] __attribute__ ((aligned (8)));
+
+/* The IP and Ethernet addresses are read from the header files. */
+unsigned char cMACAddress[ 6 ] = { ETHERNET_CONF_ETHADDR0,ETHERNET_CONF_ETHADDR1,ETHERNET_CONF_ETHADDR2,ETHERNET_CONF_ETHADDR3,ETHERNET_CONF_ETHADDR4,ETHERNET_CONF_ETHADDR5 };
+
+/*-----------------------------------------------------------*/
+
+/* See the header file for descriptions of public functions. */
+
+/*
+ * Prototype for the MACB interrupt function - called by the asm wrapper.
  */
 
-__attribute__((__interrupt__)) void vMACB_ISR(void);
+__attribute__((__interrupt__)) void vMACB_ISR(void);
 
 
 /*
  * Initialise both the Tx and Rx descriptors used by the MACB.
  */
-static void prvSetupDescriptors(volatile avr32_macb_t *macb);
+static void prvSetupDescriptors(volatile avr32_macb_t *macb);
 
 //
 // Restore ownership of all Rx buffers to the MACB.
 //
-static void vResetMacbRxFrames( void );
+static void vResetMacbRxFrames( void );
 
 /*
  * Write our MAC address into the MACB.
  */
-static void prvSetupMACAddress(volatile avr32_macb_t *macb);
+static void prvSetupMACAddress(volatile avr32_macb_t *macb);
 
 /*
  * Configure the MACB for interrupts.
  */
-static void prvSetupMACBInterrupt(volatile avr32_macb_t *macb);
+static void prvSetupMACBInterrupt(volatile avr32_macb_t *macb);
 
 /*
  * Some initialisation functions.
  */
-static Bool prvProbePHY(volatile avr32_macb_t *macb);
-static unsigned long ulReadMDIO(volatile avr32_macb_t *macb, unsigned short usAddress);
-static void vWriteMDIO(volatile avr32_macb_t *macb, unsigned short usAddress, unsigned short usValue);
+static Bool prvProbePHY(volatile avr32_macb_t *macb);
+static unsigned long ulReadMDIO(volatile avr32_macb_t *macb, unsigned short usAddress);
+static void vWriteMDIO(volatile avr32_macb_t *macb, unsigned short usAddress, unsigned short usValue);
+
 
-
 /* Holds the index to the next buffer from which data will be read. */
 volatile unsigned long ulNextRxBuffer = 0;
 
-
-long lMACBSend(volatile avr32_macb_t *macb, const void *pvFrom, unsigned long ulLength, long lEndOfFrame)
-{
-  const unsigned char *pcFrom = pvFrom;
-  static unsigned long uxTxBufferIndex = 0;
-  void *pcBuffer;
-  unsigned long ulLastBuffer, ulDataBuffered = 0, ulDataRemainingToSend, ulLengthToSend;
-
-  /* If the length of data to be transmitted is greater than each individual
-  transmit buffer then the data will be split into more than one buffer.
-  Loop until the entire length has been buffered. */
-  while( ulDataBuffered < ulLength )
-  {
-    // Is a buffer available ?
-    while( !( xTxDescriptors[ uxTxBufferIndex ].U_Status.status & AVR32_TRANSMIT_OK ) )
-    {
-      // There is no room to write the Tx data to the Tx buffer.
-      // Wait a short while, then try again.
-      __asm__ __volatile__ ("nop");
-    }
-
-    portENTER_CRITICAL();
-    {
-      // Get the address of the buffer from the descriptor,
-      // then copy the data into the buffer.
-      pcBuffer = ( void * ) xTxDescriptors[ uxTxBufferIndex ].addr;
-
-      // How much can we write to the buffer ?
-      ulDataRemainingToSend = ulLength - ulDataBuffered;
-      if( ulDataRemainingToSend <= ETHERNET_CONF_TX_BUFFER_SIZE )
-      {
-        // We can write all the remaining bytes.
-        ulLengthToSend = ulDataRemainingToSend;
-      }
-      else
-      {
-        // We can't write more than ETH_TX_BUFFER_SIZE in one go.
-        ulLengthToSend = ETHERNET_CONF_TX_BUFFER_SIZE;
-      }
-      // Copy the data into the buffer.
-      memcpy( pcBuffer, &( pcFrom[ ulDataBuffered ] ), ulLengthToSend );
-      ulDataBuffered += ulLengthToSend;
-      // Is this the last data for the frame ?
-      if( lEndOfFrame && ( ulDataBuffered >= ulLength ) )
-      {
-        // No more data remains for this frame so we can start the transmission.
-        ulLastBuffer = AVR32_LAST_BUFFER;
-      }
-      else
-      {
-        // More data to come for this frame.
-        ulLastBuffer = 0;
-      }
-      // Fill out the necessary in the descriptor to get the data sent,
-      // then move to the next descriptor, wrapping if necessary.
-      if( uxTxBufferIndex >= ( ETHERNET_CONF_NB_TX_BUFFERS - 1 ) )
-      {
-        xTxDescriptors[ uxTxBufferIndex ].U_Status.status =   ( ulLengthToSend & ( unsigned long ) AVR32_LENGTH_FRAME )
-                                    | ulLastBuffer
-                                    | AVR32_TRANSMIT_WRAP;
-        uxTxBufferIndex = 0;
-      } else
-      {
-        xTxDescriptors[ uxTxBufferIndex ].U_Status.status =   ( ulLengthToSend & ( unsigned long ) AVR32_LENGTH_FRAME )
-                                    | ulLastBuffer;
-        uxTxBufferIndex++;
-      }
-      /* If this is the last buffer to be sent for this frame we can
-         start the transmission. */
-      if( ulLastBuffer )
-        macb->ncr |=  AVR32_MACB_TSTART_MASK;
-
-    }
-    portEXIT_CRITICAL();
-  }
-
-  return PASS;
-}
-
-
-unsigned long ulMACBInputLength(void)
-{
-  register unsigned long ulIndex , ulLength = 0;
-  unsigned int uiTemp;
-  volatile unsigned long ulEventStatus;
-
-  // Check if the MACB encountered a problem.
-  ulEventStatus = AVR32_MACB.rsr;
-  if( ulEventStatus & AVR32_MACB_RSR_BNA_MASK )
-  {     // MACB couldn't get ownership of a buffer. This could typically
-        // happen if the total numbers of Rx buffers is tailored too small
-        // for a noisy network with big frames.
-        // We might as well restore ownership of all buffers to the MACB to
-        // restart from a clean state.
-    vResetMacbRxFrames();
-    return( ulLength );
-  }
-
-  // Skip any fragments.  We are looking for the first buffer that contains
-  // data and has the SOF (start of frame) bit set.
-  while( ( xRxDescriptors[ ulNextRxBuffer ].addr & AVR32_OWNERSHIP_BIT )
-        && !( xRxDescriptors[ ulNextRxBuffer ].U_Status.status & AVR32_SOF ) )
-  {
-    // Ignoring this buffer.  Mark it as free again.
-    uiTemp = xRxDescriptors[ ulNextRxBuffer ].addr;
-    xRxDescriptors[ ulNextRxBuffer ].addr = uiTemp & ~( AVR32_OWNERSHIP_BIT );
-    ulNextRxBuffer++;
-    if( ulNextRxBuffer >= ETHERNET_CONF_NB_RX_BUFFERS )
-    {
-      ulNextRxBuffer = 0;
-    }
-  }
-
-  // We are going to walk through the descriptors that make up this frame,
-  // but don't want to alter ulNextRxBuffer as this would prevent vMACBRead()
-  // from finding the data.  Therefore use a copy of ulNextRxBuffer instead.
-  ulIndex = ulNextRxBuffer;
-
-  // Walk through the descriptors until we find the last buffer for this frame.
-  // The last buffer will give us the length of the entire frame.
-  while ( xRxDescriptors[ ulIndex ].addr & AVR32_OWNERSHIP_BIT )
-  {
-    ulLength = xRxDescriptors[ ulIndex ].U_Status.status & AVR32_LENGTH_FRAME;
-    if (ulLength) break; //return ulLength
-
-    // Increment to the next buffer, wrapping if necessary.
-    if( ++ulIndex >= ETHERNET_CONF_NB_RX_BUFFERS ) ulIndex = 0;
-
-    // Is the descriptor valid?
-    if (!(xRxDescriptors[ ulIndex ].addr & AVR32_OWNERSHIP_BIT)) break; //return 0
-
-    // Is it a SOF? If so, the head packet is bad and should be discarded
-    if (xRxDescriptors[ ulIndex ].U_Status.status & AVR32_SOF)
-    {
-      // Mark the buffers of the CURRENT, FAULTY packet available.
-      unsigned int i = ulNextRxBuffer;
-      do{
-        // Ignore the faulty frame. Mark its buffers as owned by the MACB.
-        uiTemp = xRxDescriptors[ i ].addr;
-        xRxDescriptors[ i ].addr = uiTemp & ~(AVR32_OWNERSHIP_BIT);
-        if (++i>=ETHERNET_CONF_NB_RX_BUFFERS) i=0;
-      }while (i!=ulIndex);
-      ulNextRxBuffer=ulIndex;
-      // We have the start of a new packet, look at that one instead.
-    }
-  }
-  return ulLength;
-}
-/*-----------------------------------------------------------*/
-
-void vMACBRead(void *pvTo, unsigned long ulSectionLength, unsigned long ulTotalFrameLength)
-{
-  unsigned char *pcTo = pvTo;
-  static unsigned long ulSectionBytesReadSoFar = 0, ulBufferPosition = 0, ulFrameBytesReadSoFar = 0;
-  static const unsigned char *pcSource;
-  register unsigned long ulBytesRemainingInBuffer, ulRemainingSectionBytes;
-  unsigned int uiTemp;
-
-  // Read ulSectionLength bytes from the Rx buffers.
-  // This is not necessarily any correspondence between the length of our Rx buffers,
-  // and the length of the data we are returning or the length of the data being requested.
-  // Therefore, between calls  we have to remember not only which buffer we are currently
-  // processing, but our position within that buffer.
-  // This would be greatly simplified if PBUF_POOL_BUFSIZE could be guaranteed to be greater
-  // than the size of each Rx buffer, and that memory fragmentation did not occur.
-
-  // This function should only be called after a call to ulMACBInputLength().
-  // This will ensure ulNextRxBuffer is set to the correct buffer. */
-
-  // vMACBRead is called with pcTo set to NULL to indicate that we are about
-  // to read a new frame.  Any fragments remaining in the frame we were
-  // processing during the last call should be dropped.
-  if( pcTo == NULL )
-  {
-    // How many bytes are indicated as being in this buffer?
-    // If none then the buffer is completely full and the frame is contained within more
-    // than one buffer.
-    // Reset our state variables ready for the next read from this buffer.
-    pcSource = ( unsigned char * )( xRxDescriptors[ ulNextRxBuffer ].addr & ADDRESS_MASK );
-    ulFrameBytesReadSoFar = ( unsigned long ) 0;
-    ulBufferPosition = ( unsigned long ) 0;
-  }
-  else
-  {
-    // Loop until we have obtained the required amount of data.
-    ulSectionBytesReadSoFar = 0;
-    while( ulSectionBytesReadSoFar < ulSectionLength )
-    {
-      // We may have already read some data from this buffer.
-      // How much data remains in the buffer?
-      ulBytesRemainingInBuffer = ( RX_BUFFER_SIZE - ulBufferPosition );
-
-      // How many more bytes do we need to read before we have the
-      // required amount of data?
-      ulRemainingSectionBytes = ulSectionLength - ulSectionBytesReadSoFar;
-
-      // Do we want more data than remains in the buffer?
-      if( ulRemainingSectionBytes > ulBytesRemainingInBuffer )
-      {
-        // We want more data than remains in the buffer so we can
-        // write the remains of the buffer to the destination, then move
-        // onto the next buffer to get the rest.
-        memcpy( &( pcTo[ ulSectionBytesReadSoFar ] ), &( pcSource[ ulBufferPosition ] ), ulBytesRemainingInBuffer );
-        ulSectionBytesReadSoFar += ulBytesRemainingInBuffer;
-        ulFrameBytesReadSoFar += ulBytesRemainingInBuffer;
-
-        // Mark the buffer as free again.
-        uiTemp = xRxDescriptors[ ulNextRxBuffer ].addr;
-        xRxDescriptors[ ulNextRxBuffer ].addr = uiTemp & ~( AVR32_OWNERSHIP_BIT );
-        // Move onto the next buffer.
-        ulNextRxBuffer++;
-
-        if( ulNextRxBuffer >= ETHERNET_CONF_NB_RX_BUFFERS )
-        {
-          ulNextRxBuffer = ( unsigned long ) 0;
-        }
-
-        // Reset the variables for the new buffer.
-        pcSource = ( unsigned char * )( xRxDescriptors[ ulNextRxBuffer ].addr & ADDRESS_MASK );
-        ulBufferPosition = ( unsigned long ) 0;
-      }
-      else
-      {
-        // We have enough data in this buffer to send back.
-        // Read out enough data and remember how far we read up to.
-        memcpy( &( pcTo[ ulSectionBytesReadSoFar ] ), &( pcSource[ ulBufferPosition ] ), ulRemainingSectionBytes );
-
-        // There may be more data in this buffer yet.
-        // Increment our position in this buffer past the data we have just read.
-        ulBufferPosition += ulRemainingSectionBytes;
-        ulSectionBytesReadSoFar += ulRemainingSectionBytes;
-        ulFrameBytesReadSoFar += ulRemainingSectionBytes;
-
-        // Have we now finished with this buffer?
-        if( ( ulBufferPosition >= RX_BUFFER_SIZE ) || ( ulFrameBytesReadSoFar >= ulTotalFrameLength ) )
-        {
-          // Mark the buffer as free again.
-          uiTemp = xRxDescriptors[ ulNextRxBuffer ].addr;
-          xRxDescriptors[ ulNextRxBuffer ].addr = uiTemp & ~( AVR32_OWNERSHIP_BIT );
-          // Move onto the next buffer.
-          ulNextRxBuffer++;
-
-          if( ulNextRxBuffer >= ETHERNET_CONF_NB_RX_BUFFERS )
-          {
-            ulNextRxBuffer = 0;
-          }
-
-          pcSource = ( unsigned char * )( xRxDescriptors[ ulNextRxBuffer ].addr & ADDRESS_MASK );
-          ulBufferPosition = 0;
-        }
-      }
-    }
-  }
-}
-
-/*-----------------------------------------------------------*/
-void vMACBFlushCurrentPacket(unsigned long ulTotalFrameLength)
-{
-   unsigned int   uiTemp;
-   long int lTotalFrameLen = (long int)ulTotalFrameLength;
-
-   while( lTotalFrameLen > 0 )
-   {
-      // Ignoring this buffer.  Mark it as free again.
-      uiTemp = xRxDescriptors[ ulNextRxBuffer ].addr;
-      xRxDescriptors[ ulNextRxBuffer ].addr = uiTemp & ~( AVR32_OWNERSHIP_BIT );
-
-      // Move on to the next buffer.
-      ulNextRxBuffer++;
-      ulNextRxBuffer = ulNextRxBuffer%ETHERNET_CONF_NB_RX_BUFFERS;
-
-      lTotalFrameLen -= RX_BUFFER_SIZE;
-   }
-}
-
-
-/*-----------------------------------------------------------*/
-void vMACBSetMACAddress(const unsigned char *MACAddress)
-{
-  memcpy(cMACAddress, MACAddress, sizeof(cMACAddress));
-}
-
-Bool xMACBInit(volatile avr32_macb_t *macb)
-{
-  Bool global_interrupt_enabled = Is_global_interrupt_enabled();
-  volatile unsigned long status;
+
+long lMACBSend(volatile avr32_macb_t *macb, const void *pvFrom, unsigned long ulLength, long lEndOfFrame)
+{
+  const unsigned char *pcFrom = pvFrom;
+  static unsigned long uxTxBufferIndex = 0;
+  void *pcBuffer;
+  unsigned long ulLastBuffer, ulDataBuffered = 0, ulDataRemainingToSend, ulLengthToSend;
+
+  /* If the length of data to be transmitted is greater than each individual
+  transmit buffer then the data will be split into more than one buffer.
+  Loop until the entire length has been buffered. */
+  while( ulDataBuffered < ulLength )
+  {
+    // Is a buffer available ?
+    while( !( xTxDescriptors[ uxTxBufferIndex ].U_Status.status & AVR32_TRANSMIT_OK ) )
+    {
+      // There is no room to write the Tx data to the Tx buffer.
+      // Wait a short while, then try again.
+      __asm__ __volatile__ ("nop");
+    }
+
+    portENTER_CRITICAL();
+    {
+      // Get the address of the buffer from the descriptor,
+      // then copy the data into the buffer.
+      pcBuffer = ( void * ) xTxDescriptors[ uxTxBufferIndex ].addr;
+
+      // How much can we write to the buffer ?
+      ulDataRemainingToSend = ulLength - ulDataBuffered;
+      if( ulDataRemainingToSend <= ETHERNET_CONF_TX_BUFFER_SIZE )
+      {
+        // We can write all the remaining bytes.
+        ulLengthToSend = ulDataRemainingToSend;
+      }
+      else
+      {
+        // We can't write more than ETH_TX_BUFFER_SIZE in one go.
+        ulLengthToSend = ETHERNET_CONF_TX_BUFFER_SIZE;
+      }
+      // Copy the data into the buffer.
+      memcpy( pcBuffer, &( pcFrom[ ulDataBuffered ] ), ulLengthToSend );
+      ulDataBuffered += ulLengthToSend;
+      // Is this the last data for the frame ?
+      if( lEndOfFrame && ( ulDataBuffered >= ulLength ) )
+      {
+        // No more data remains for this frame so we can start the transmission.
+        ulLastBuffer = AVR32_LAST_BUFFER;
+      }
+      else
+      {
+        // More data to come for this frame.
+        ulLastBuffer = 0;
+      }
+      // Fill out the necessary in the descriptor to get the data sent,
+      // then move to the next descriptor, wrapping if necessary.
+      if( uxTxBufferIndex >= ( ETHERNET_CONF_NB_TX_BUFFERS - 1 ) )
+      {
+        xTxDescriptors[ uxTxBufferIndex ].U_Status.status =   ( ulLengthToSend & ( unsigned long ) AVR32_LENGTH_FRAME )
+                                    | ulLastBuffer
+                                    | AVR32_TRANSMIT_WRAP;
+        uxTxBufferIndex = 0;
+      } else
+      {
+        xTxDescriptors[ uxTxBufferIndex ].U_Status.status =   ( ulLengthToSend & ( unsigned long ) AVR32_LENGTH_FRAME )
+                                    | ulLastBuffer;
+        uxTxBufferIndex++;
+      }
+      /* If this is the last buffer to be sent for this frame we can
+         start the transmission. */
+      if( ulLastBuffer )
+        macb->ncr |=  AVR32_MACB_TSTART_MASK;
+
+    }
+    portEXIT_CRITICAL();
+  }
+
+  return PASS;
+}
+
+
+unsigned long ulMACBInputLength(void)
+{
+  register unsigned long ulIndex , ulLength = 0;
+  unsigned int uiTemp;
+  volatile unsigned long ulEventStatus;
+
+  // Check if the MACB encountered a problem.
+  ulEventStatus = AVR32_MACB.rsr;
+  if( ulEventStatus & AVR32_MACB_RSR_BNA_MASK )
+  {     // MACB couldn't get ownership of a buffer. This could typically
+        // happen if the total numbers of Rx buffers is tailored too small
+        // for a noisy network with big frames.
+        // We might as well restore ownership of all buffers to the MACB to
+        // restart from a clean state.
+    vResetMacbRxFrames();
+    return( ulLength );
+  }
+
+  // Skip any fragments.  We are looking for the first buffer that contains
+  // data and has the SOF (start of frame) bit set.
+  while( ( xRxDescriptors[ ulNextRxBuffer ].addr & AVR32_OWNERSHIP_BIT )
+        && !( xRxDescriptors[ ulNextRxBuffer ].U_Status.status & AVR32_SOF ) )
+  {
+    // Ignoring this buffer.  Mark it as free again.
+    uiTemp = xRxDescriptors[ ulNextRxBuffer ].addr;
+    xRxDescriptors[ ulNextRxBuffer ].addr = uiTemp & ~( AVR32_OWNERSHIP_BIT );
+    ulNextRxBuffer++;
+    if( ulNextRxBuffer >= ETHERNET_CONF_NB_RX_BUFFERS )
+    {
+      ulNextRxBuffer = 0;
+    }
+  }
+
+  // We are going to walk through the descriptors that make up this frame,
+  // but don't want to alter ulNextRxBuffer as this would prevent vMACBRead()
+  // from finding the data.  Therefore use a copy of ulNextRxBuffer instead.
+  ulIndex = ulNextRxBuffer;
+
+  // Walk through the descriptors until we find the last buffer for this frame.
+  // The last buffer will give us the length of the entire frame.
+  while ( xRxDescriptors[ ulIndex ].addr & AVR32_OWNERSHIP_BIT )
+  {
+    ulLength = xRxDescriptors[ ulIndex ].U_Status.status & AVR32_LENGTH_FRAME;
+    if (ulLength) break; //return ulLength
+
+    // Increment to the next buffer, wrapping if necessary.
+    if( ++ulIndex >= ETHERNET_CONF_NB_RX_BUFFERS ) ulIndex = 0;
+
+    // Is the descriptor valid?
+    if (!(xRxDescriptors[ ulIndex ].addr & AVR32_OWNERSHIP_BIT)) break; //return 0
+
+    // Is it a SOF? If so, the head packet is bad and should be discarded
+    if (xRxDescriptors[ ulIndex ].U_Status.status & AVR32_SOF)
+    {
+      // Mark the buffers of the CURRENT, FAULTY packet available.
+      unsigned int i = ulNextRxBuffer;
+      do{
+        // Ignore the faulty frame. Mark its buffers as owned by the MACB.
+        uiTemp = xRxDescriptors[ i ].addr;
+        xRxDescriptors[ i ].addr = uiTemp & ~(AVR32_OWNERSHIP_BIT);
+        if (++i>=ETHERNET_CONF_NB_RX_BUFFERS) i=0;
+      }while (i!=ulIndex);
+      ulNextRxBuffer=ulIndex;
+      // We have the start of a new packet, look at that one instead.
+    }
+  }
+  return ulLength;
+}
+/*-----------------------------------------------------------*/
+
+void vMACBRead(void *pvTo, unsigned long ulSectionLength, unsigned long ulTotalFrameLength)
+{
+  unsigned char *pcTo = pvTo;
+  static unsigned long ulSectionBytesReadSoFar = 0, ulBufferPosition = 0, ulFrameBytesReadSoFar = 0;
+  static const unsigned char *pcSource;
+  register unsigned long ulBytesRemainingInBuffer, ulRemainingSectionBytes;
+  unsigned int uiTemp;
+
+  // Read ulSectionLength bytes from the Rx buffers.
+  // This is not necessarily any correspondence between the length of our Rx buffers,
+  // and the length of the data we are returning or the length of the data being requested.
+  // Therefore, between calls  we have to remember not only which buffer we are currently
+  // processing, but our position within that buffer.
+  // This would be greatly simplified if PBUF_POOL_BUFSIZE could be guaranteed to be greater
+  // than the size of each Rx buffer, and that memory fragmentation did not occur.
+
+  // This function should only be called after a call to ulMACBInputLength().
+  // This will ensure ulNextRxBuffer is set to the correct buffer. */
+
+  // vMACBRead is called with pcTo set to NULL to indicate that we are about
+  // to read a new frame.  Any fragments remaining in the frame we were
+  // processing during the last call should be dropped.
+  if( pcTo == NULL )
+  {
+    // How many bytes are indicated as being in this buffer?
+    // If none then the buffer is completely full and the frame is contained within more
+    // than one buffer.
+    // Reset our state variables ready for the next read from this buffer.
+    pcSource = ( unsigned char * )( xRxDescriptors[ ulNextRxBuffer ].addr & ADDRESS_MASK );
+    ulFrameBytesReadSoFar = ( unsigned long ) 0;
+    ulBufferPosition = ( unsigned long ) 0;
+  }
+  else
+  {
+    // Loop until we have obtained the required amount of data.
+    ulSectionBytesReadSoFar = 0;
+    while( ulSectionBytesReadSoFar < ulSectionLength )
+    {
+      // We may have already read some data from this buffer.
+      // How much data remains in the buffer?
+      ulBytesRemainingInBuffer = ( RX_BUFFER_SIZE - ulBufferPosition );
+
+      // How many more bytes do we need to read before we have the
+      // required amount of data?
+      ulRemainingSectionBytes = ulSectionLength - ulSectionBytesReadSoFar;
+
+      // Do we want more data than remains in the buffer?
+      if( ulRemainingSectionBytes > ulBytesRemainingInBuffer )
+      {
+        // We want more data than remains in the buffer so we can
+        // write the remains of the buffer to the destination, then move
+        // onto the next buffer to get the rest.
+        memcpy( &( pcTo[ ulSectionBytesReadSoFar ] ), &( pcSource[ ulBufferPosition ] ), ulBytesRemainingInBuffer );
+        ulSectionBytesReadSoFar += ulBytesRemainingInBuffer;
+        ulFrameBytesReadSoFar += ulBytesRemainingInBuffer;
+
+        // Mark the buffer as free again.
+        uiTemp = xRxDescriptors[ ulNextRxBuffer ].addr;
+        xRxDescriptors[ ulNextRxBuffer ].addr = uiTemp & ~( AVR32_OWNERSHIP_BIT );
+        // Move onto the next buffer.
+        ulNextRxBuffer++;
+
+        if( ulNextRxBuffer >= ETHERNET_CONF_NB_RX_BUFFERS )
+        {
+          ulNextRxBuffer = ( unsigned long ) 0;
+        }
+
+        // Reset the variables for the new buffer.
+        pcSource = ( unsigned char * )( xRxDescriptors[ ulNextRxBuffer ].addr & ADDRESS_MASK );
+        ulBufferPosition = ( unsigned long ) 0;
+      }
+      else
+      {
+        // We have enough data in this buffer to send back.
+        // Read out enough data and remember how far we read up to.
+        memcpy( &( pcTo[ ulSectionBytesReadSoFar ] ), &( pcSource[ ulBufferPosition ] ), ulRemainingSectionBytes );
+
+        // There may be more data in this buffer yet.
+        // Increment our position in this buffer past the data we have just read.
+        ulBufferPosition += ulRemainingSectionBytes;
+        ulSectionBytesReadSoFar += ulRemainingSectionBytes;
+        ulFrameBytesReadSoFar += ulRemainingSectionBytes;
+
+        // Have we now finished with this buffer?
+        if( ( ulBufferPosition >= RX_BUFFER_SIZE ) || ( ulFrameBytesReadSoFar >= ulTotalFrameLength ) )
+        {
+          // Mark the buffer as free again.
+          uiTemp = xRxDescriptors[ ulNextRxBuffer ].addr;
+          xRxDescriptors[ ulNextRxBuffer ].addr = uiTemp & ~( AVR32_OWNERSHIP_BIT );
+          // Move onto the next buffer.
+          ulNextRxBuffer++;
+
+          if( ulNextRxBuffer >= ETHERNET_CONF_NB_RX_BUFFERS )
+          {
+            ulNextRxBuffer = 0;
+          }
+
+          pcSource = ( unsigned char * )( xRxDescriptors[ ulNextRxBuffer ].addr & ADDRESS_MASK );
+          ulBufferPosition = 0;
+        }
+      }
+    }
+  }
+}
+
+/*-----------------------------------------------------------*/
+void vMACBFlushCurrentPacket(unsigned long ulTotalFrameLength)
+{
+   unsigned int   uiTemp;
+   long int lTotalFrameLen = (long int)ulTotalFrameLength;
+
+   while( lTotalFrameLen > 0 )
+   {
+      // Ignoring this buffer.  Mark it as free again.
+      uiTemp = xRxDescriptors[ ulNextRxBuffer ].addr;
+      xRxDescriptors[ ulNextRxBuffer ].addr = uiTemp & ~( AVR32_OWNERSHIP_BIT );
+
+      // Move on to the next buffer.
+      ulNextRxBuffer++;
+      ulNextRxBuffer = ulNextRxBuffer%ETHERNET_CONF_NB_RX_BUFFERS;
+
+      lTotalFrameLen -= RX_BUFFER_SIZE;
+   }
+}
+
+
+/*-----------------------------------------------------------*/
+void vMACBSetMACAddress(const unsigned char *MACAddress)
+{
+  memcpy(cMACAddress, MACAddress, sizeof(cMACAddress));
+}
+
+Bool xMACBInit(volatile avr32_macb_t *macb)
+{
+  Bool global_interrupt_enabled = Is_global_interrupt_enabled();
+  volatile unsigned long status;
 
   //vDisableMACBOperations(macb);
-
-  // set up registers
-  macb->ncr = 0;
-  macb->tsr = ~0UL;
-  macb->rsr = ~0UL;
-
-  if (global_interrupt_enabled) Disable_global_interrupt();
-  macb->idr = ~0UL;
-  status = macb->isr;
-  if (global_interrupt_enabled) Enable_global_interrupt();
-
-  // RMII used, set 0 to the USRIO Register
-  macb->usrio &= ~AVR32_MACB_RMII_MASK;
-
-  // Load our MAC address into the MACB.
-  prvSetupMACAddress(macb);
-
-  // Setup the buffers and descriptors.
-  prvSetupDescriptors(macb);
-
-#if ETHERNET_CONF_SYSTEM_CLOCK <= 20000000
-  macb->ncfgr |= (AVR32_MACB_NCFGR_CLK_DIV8 << AVR32_MACB_NCFGR_CLK_OFFSET);
-#elif ETHERNET_CONF_SYSTEM_CLOCK <= 40000000
-  macb->ncfgr |= (AVR32_MACB_NCFGR_CLK_DIV16 << AVR32_MACB_NCFGR_CLK_OFFSET);
-#elif ETHERNET_CONF_SYSTEM_CLOCK <= 80000000
-  macb->ncfgr |= AVR32_MACB_NCFGR_CLK_DIV32 << AVR32_MACB_NCFGR_CLK_OFFSET;
-#elif ETHERNET_CONF_SYSTEM_CLOCK <= 160000000
-  macb->ncfgr |= AVR32_MACB_NCFGR_CLK_DIV64 << AVR32_MACB_NCFGR_CLK_OFFSET;
-#else
-# error System clock too fast
-#endif
-
-  // Are we connected?
-  if( prvProbePHY(macb) == TRUE )
-  {
-    // Enable the interrupt!
-    portENTER_CRITICAL();
-    {
-      prvSetupMACBInterrupt(macb);
-    }
-    portEXIT_CRITICAL();
-    // Enable Rx and Tx, plus the stats register.
-    macb->ncr = AVR32_MACB_NCR_TE_MASK | AVR32_MACB_NCR_RE_MASK;
-    return (TRUE);
-  }
-  return (FALSE);
-}
-
-void vDisableMACBOperations (volatile avr32_macb_t *macb)
-{
-  Bool global_interrupt_enabled = Is_global_interrupt_enabled();
-
-  // write the MACB control register : disable Tx & Rx
-  macb->ncr &= ~((1 << AVR32_MACB_RE_OFFSET) | (1 << AVR32_MACB_TE_OFFSET));
-
-  // We no more want to interrupt on Rx and Tx events.
-  if (global_interrupt_enabled) Disable_global_interrupt();
-  macb->idr = AVR32_MACB_IER_RCOMP_MASK | AVR32_MACB_IER_TCOMP_MASK;
-  macb->isr;
-  if (global_interrupt_enabled) Enable_global_interrupt();
-}
-
-
-void vClearMACBTxBuffer(void)
-{
-  static unsigned long uxNextBufferToClear = 0;
-
-  // Called on Tx interrupt events to set the AVR32_TRANSMIT_OK bit in each
-  // Tx buffer within the frame just transmitted.  This marks all the buffers
-  // as available again.
-
-  // The first buffer in the frame should have the bit set automatically. */
-  if( xTxDescriptors[ uxNextBufferToClear ].U_Status.status & AVR32_TRANSMIT_OK )
-  {
-    // Loop through the other buffers in the frame.
-    while( !( xTxDescriptors[ uxNextBufferToClear ].U_Status.status & AVR32_LAST_BUFFER ) )
-    {
-      uxNextBufferToClear++;
-
-      if( uxNextBufferToClear >= ETHERNET_CONF_NB_TX_BUFFERS )
-      {
-        uxNextBufferToClear = 0;
-      }
-
-      xTxDescriptors[ uxNextBufferToClear ].U_Status.status |= AVR32_TRANSMIT_OK;
-    }
-
-    // Start with the next buffer the next time a Tx interrupt is called.
-    uxNextBufferToClear++;
-
-    // Do we need to wrap back to the first buffer?
-    if( uxNextBufferToClear >= ETHERNET_CONF_NB_TX_BUFFERS )
-    {
-      uxNextBufferToClear = 0;
-    }
-  }
-}
-
-static void prvSetupDescriptors(volatile avr32_macb_t *macb)
-{
-  unsigned long xIndex;
-  unsigned long ulAddress;
-
-  // Initialise xRxDescriptors descriptor.
-  for( xIndex = 0; xIndex < ETHERNET_CONF_NB_RX_BUFFERS; ++xIndex )
-  {
-    // Calculate the address of the nth buffer within the array.
-    ulAddress = ( unsigned long )( pcRxBuffer + ( xIndex * RX_BUFFER_SIZE ) );
-
-    // Write the buffer address into the descriptor.
-    // The DMA will place the data at this address when this descriptor is being used.
-    // No need to mask off the bottom bits of the address (these have special meaning
-    // for the MACB) because pcRxBuffer is 4Bytes-aligned.
-    xRxDescriptors[ xIndex ].addr = ulAddress;
-  }
-
-  // The last buffer has the wrap bit set so the MACB knows to wrap back
-  // to the first buffer.
-  xRxDescriptors[ ETHERNET_CONF_NB_RX_BUFFERS - 1 ].addr |= RX_WRAP_BIT;
-
-  // Initialise xTxDescriptors.
-  for( xIndex = 0; xIndex < ETHERNET_CONF_NB_TX_BUFFERS; ++xIndex )
-  {
-    // Calculate the address of the nth buffer within the array.
-    ulAddress = ( unsigned long )( pcTxBuffer + ( xIndex * ETHERNET_CONF_TX_BUFFER_SIZE ) );
-
-    // Write the buffer address into the descriptor.
-    // The DMA will read data from here when the descriptor is being used.
-    xTxDescriptors[ xIndex ].addr = ulAddress;
-    xTxDescriptors[ xIndex ].U_Status.status = AVR32_TRANSMIT_OK;
-  }
-
-  // The last buffer has the wrap bit set so the MACB knows to wrap back
-  // to the first buffer.
-  xTxDescriptors[ ETHERNET_CONF_NB_TX_BUFFERS - 1 ].U_Status.status = AVR32_TRANSMIT_WRAP | AVR32_TRANSMIT_OK;
-
-  // Tell the MACB where to find the descriptors.
-  macb->rbqp =   ( unsigned long )xRxDescriptors;
-  macb->tbqp =   ( unsigned long )xTxDescriptors;
-
-  // Do not copy the FCS field of received frames to memory.
-  macb->ncfgr |= ( AVR32_MACB_NCFGR_DRFCS_MASK );
-
-}
-
-//!
-//! \brief Restore ownership of all Rx buffers to the MACB.
-//!
-static void vResetMacbRxFrames( void )
-{
-   register unsigned long  ulIndex;
-   unsigned int            uiTemp;
-
-
-   // Disable MACB frame reception.
-   AVR32_MACB.ncr &= ~(AVR32_MACB_NCR_RE_MASK);
-
-   // Restore ownership of all Rx buffers to the MACB.
-   for( ulIndex = 0; ulIndex < ETHERNET_CONF_NB_RX_BUFFERS; ++ulIndex )
-   {
-      // Mark the buffer as owned by the MACB.
-      uiTemp = xRxDescriptors[ ulIndex ].addr;
-      xRxDescriptors[ ulIndex ].addr = uiTemp & ~( AVR32_OWNERSHIP_BIT );
-   }
-
-   // Reset the Buffer-not-available bit and the overrun bit.
-   AVR32_MACB.rsr = AVR32_MACB_RSR_BNA_MASK | AVR32_MACB_RSR_OVR_MASK;  // Clear
-   AVR32_MACB.rsr; // We read to force the previous operation.
-
-   // Reset the MACB starting point.
-   AVR32_MACB.rbqp = ( unsigned long )xRxDescriptors;
-
-   // Reset the index to the next buffer from which data will be read.
-   ulNextRxBuffer = 0;
-
-   // Enable MACB frame reception.
-   AVR32_MACB.ncr |= AVR32_MACB_NCR_RE_MASK;
-}
-
-
-static void prvSetupMACAddress(volatile avr32_macb_t *macb)
-{
-  // Must be written SA1L then SA1H.
-  macb->sa1b =  ( ( unsigned long ) cMACAddress[ 3 ] << 24 ) |
-                ( ( unsigned long ) cMACAddress[ 2 ] << 16 ) |
-                ( ( unsigned long ) cMACAddress[ 1 ] << 8  ) |
-                                    cMACAddress[ 0 ];
-
-  macb->sa1t =  ( ( unsigned long ) cMACAddress[ 5 ] << 8 ) |
-                                    cMACAddress[ 4 ];
-}
-
-static void prvSetupMACBInterrupt(volatile avr32_macb_t *macb)
-{
-
-    // Setup the interrupt for MACB.
-    // Register the interrupt handler to the interrupt controller at interrupt level 2
-    INTC_register_interrupt((__int_handler)&vMACB_ISR, AVR32_MACB_IRQ, AVR32_INTC_INT2);
-
-    // We want to interrupt on Rx and Tx events
-    macb->ier = AVR32_MACB_IER_RCOMP_MASK | AVR32_MACB_IER_TCOMP_MASK ;
-}
+
+  // set up registers
+  macb->ncr = 0;
+  macb->tsr = ~0UL;
+  macb->rsr = ~0UL;
+
+  if (global_interrupt_enabled) Disable_global_interrupt();
+  macb->idr = ~0UL;
+  status = macb->isr;
+  if (global_interrupt_enabled) Enable_global_interrupt();
+
+  // RMII used, set 0 to the USRIO Register
+  macb->usrio &= ~AVR32_MACB_RMII_MASK;
+
+  // Load our MAC address into the MACB.
+  prvSetupMACAddress(macb);
+
+  // Setup the buffers and descriptors.
+  prvSetupDescriptors(macb);
+
+#if ETHERNET_CONF_SYSTEM_CLOCK <= 20000000
+  macb->ncfgr |= (AVR32_MACB_NCFGR_CLK_DIV8 << AVR32_MACB_NCFGR_CLK_OFFSET);
+#elif ETHERNET_CONF_SYSTEM_CLOCK <= 40000000
+  macb->ncfgr |= (AVR32_MACB_NCFGR_CLK_DIV16 << AVR32_MACB_NCFGR_CLK_OFFSET);
+#elif ETHERNET_CONF_SYSTEM_CLOCK <= 80000000
+  macb->ncfgr |= AVR32_MACB_NCFGR_CLK_DIV32 << AVR32_MACB_NCFGR_CLK_OFFSET;
+#elif ETHERNET_CONF_SYSTEM_CLOCK <= 160000000
+  macb->ncfgr |= AVR32_MACB_NCFGR_CLK_DIV64 << AVR32_MACB_NCFGR_CLK_OFFSET;
+#else
+# error System clock too fast
+#endif
+
+  // Are we connected?
+  if( prvProbePHY(macb) == TRUE )
+  {
+    // Enable the interrupt!
+    portENTER_CRITICAL();
+    {
+      prvSetupMACBInterrupt(macb);
+    }
+    portEXIT_CRITICAL();
+    // Enable Rx and Tx, plus the stats register.
+    macb->ncr = AVR32_MACB_NCR_TE_MASK | AVR32_MACB_NCR_RE_MASK;
+    return (TRUE);
+  }
+  return (FALSE);
+}
+
+void vDisableMACBOperations (volatile avr32_macb_t *macb)
+{
+  Bool global_interrupt_enabled = Is_global_interrupt_enabled();
+
+  // write the MACB control register : disable Tx & Rx
+  macb->ncr &= ~((1 << AVR32_MACB_RE_OFFSET) | (1 << AVR32_MACB_TE_OFFSET));
+
+  // We no more want to interrupt on Rx and Tx events.
+  if (global_interrupt_enabled) Disable_global_interrupt();
+  macb->idr = AVR32_MACB_IER_RCOMP_MASK | AVR32_MACB_IER_TCOMP_MASK;
+  macb->isr;
+  if (global_interrupt_enabled) Enable_global_interrupt();
+}
+
+
+void vClearMACBTxBuffer(void)
+{
+  static unsigned long uxNextBufferToClear = 0;
+
+  // Called on Tx interrupt events to set the AVR32_TRANSMIT_OK bit in each
+  // Tx buffer within the frame just transmitted.  This marks all the buffers
+  // as available again.
+
+  // The first buffer in the frame should have the bit set automatically. */
+  if( xTxDescriptors[ uxNextBufferToClear ].U_Status.status & AVR32_TRANSMIT_OK )
+  {
+    // Loop through the other buffers in the frame.
+    while( !( xTxDescriptors[ uxNextBufferToClear ].U_Status.status & AVR32_LAST_BUFFER ) )
+    {
+      uxNextBufferToClear++;
+
+      if( uxNextBufferToClear >= ETHERNET_CONF_NB_TX_BUFFERS )
+      {
+        uxNextBufferToClear = 0;
+      }
+
+      xTxDescriptors[ uxNextBufferToClear ].U_Status.status |= AVR32_TRANSMIT_OK;
+    }
+
+    // Start with the next buffer the next time a Tx interrupt is called.
+    uxNextBufferToClear++;
+
+    // Do we need to wrap back to the first buffer?
+    if( uxNextBufferToClear >= ETHERNET_CONF_NB_TX_BUFFERS )
+    {
+      uxNextBufferToClear = 0;
+    }
+  }
+}
+
+static void prvSetupDescriptors(volatile avr32_macb_t *macb)
+{
+  unsigned long xIndex;
+  unsigned long ulAddress;
+
+  // Initialise xRxDescriptors descriptor.
+  for( xIndex = 0; xIndex < ETHERNET_CONF_NB_RX_BUFFERS; ++xIndex )
+  {
+    // Calculate the address of the nth buffer within the array.
+    ulAddress = ( unsigned long )( pcRxBuffer + ( xIndex * RX_BUFFER_SIZE ) );
+
+    // Write the buffer address into the descriptor.
+    // The DMA will place the data at this address when this descriptor is being used.
+    // No need to mask off the bottom bits of the address (these have special meaning
+    // for the MACB) because pcRxBuffer is 4Bytes-aligned.
+    xRxDescriptors[ xIndex ].addr = ulAddress;
+  }
+
+  // The last buffer has the wrap bit set so the MACB knows to wrap back
+  // to the first buffer.
+  xRxDescriptors[ ETHERNET_CONF_NB_RX_BUFFERS - 1 ].addr |= RX_WRAP_BIT;
+
+  // Initialise xTxDescriptors.
+  for( xIndex = 0; xIndex < ETHERNET_CONF_NB_TX_BUFFERS; ++xIndex )
+  {
+    // Calculate the address of the nth buffer within the array.
+    ulAddress = ( unsigned long )( pcTxBuffer + ( xIndex * ETHERNET_CONF_TX_BUFFER_SIZE ) );
+
+    // Write the buffer address into the descriptor.
+    // The DMA will read data from here when the descriptor is being used.
+    xTxDescriptors[ xIndex ].addr = ulAddress;
+    xTxDescriptors[ xIndex ].U_Status.status = AVR32_TRANSMIT_OK;
+  }
+
+  // The last buffer has the wrap bit set so the MACB knows to wrap back
+  // to the first buffer.
+  xTxDescriptors[ ETHERNET_CONF_NB_TX_BUFFERS - 1 ].U_Status.status = AVR32_TRANSMIT_WRAP | AVR32_TRANSMIT_OK;
+
+  // Tell the MACB where to find the descriptors.
+  macb->rbqp =   ( unsigned long )xRxDescriptors;
+  macb->tbqp =   ( unsigned long )xTxDescriptors;
+
+  // Do not copy the FCS field of received frames to memory.
+  macb->ncfgr |= ( AVR32_MACB_NCFGR_DRFCS_MASK );
+
+}
+
+//!
+//! \brief Restore ownership of all Rx buffers to the MACB.
+//!
+static void vResetMacbRxFrames( void )
+{
+   register unsigned long  ulIndex;
+   unsigned int            uiTemp;
+
+
+   // Disable MACB frame reception.
+   AVR32_MACB.ncr &= ~(AVR32_MACB_NCR_RE_MASK);
+
+   // Restore ownership of all Rx buffers to the MACB.
+   for( ulIndex = 0; ulIndex < ETHERNET_CONF_NB_RX_BUFFERS; ++ulIndex )
+   {
+      // Mark the buffer as owned by the MACB.
+      uiTemp = xRxDescriptors[ ulIndex ].addr;
+      xRxDescriptors[ ulIndex ].addr = uiTemp & ~( AVR32_OWNERSHIP_BIT );
+   }
+
+   // Reset the Buffer-not-available bit and the overrun bit.
+   AVR32_MACB.rsr = AVR32_MACB_RSR_BNA_MASK | AVR32_MACB_RSR_OVR_MASK;  // Clear
+   AVR32_MACB.rsr; // We read to force the previous operation.
+
+   // Reset the MACB starting point.
+   AVR32_MACB.rbqp = ( unsigned long )xRxDescriptors;
+
+   // Reset the index to the next buffer from which data will be read.
+   ulNextRxBuffer = 0;
+
+   // Enable MACB frame reception.
+   AVR32_MACB.ncr |= AVR32_MACB_NCR_RE_MASK;
+}
+
+
+static void prvSetupMACAddress(volatile avr32_macb_t *macb)
+{
+  // Must be written SA1L then SA1H.
+  macb->sa1b =  ( ( unsigned long ) cMACAddress[ 3 ] << 24 ) |
+                ( ( unsigned long ) cMACAddress[ 2 ] << 16 ) |
+                ( ( unsigned long ) cMACAddress[ 1 ] << 8  ) |
+                                    cMACAddress[ 0 ];
+
+  macb->sa1t =  ( ( unsigned long ) cMACAddress[ 5 ] << 8 ) |
+                                    cMACAddress[ 4 ];
+}
+
+static void prvSetupMACBInterrupt(volatile avr32_macb_t *macb)
+{
+
+    // Setup the interrupt for MACB.
+    // Register the interrupt handler to the interrupt controller at interrupt level 2
+    INTC_register_interrupt((__int_handler)&vMACB_ISR, AVR32_MACB_IRQ, AVR32_INTC_INT2);
+
+    // We want to interrupt on Rx and Tx events
+    macb->ier = AVR32_MACB_IER_RCOMP_MASK | AVR32_MACB_IER_TCOMP_MASK ;
+}
 
 /*! Read a register on MDIO bus (access to the PHY)
  *         This function is looping until PHY gets ready
@@ -653,7 +653,7 @@ static void prvSetupMACBInterrupt(volatile avr32_macb_t *macb)
  *
  * \return unsigned long data that has been read
  */
-static unsigned long ulReadMDIO(volatile avr32_macb_t *macb, unsigned short usAddress)
+static unsigned long ulReadMDIO(volatile avr32_macb_t *macb, unsigned short usAddress)
 {
   unsigned long value, status;
   u16 timeout = 0;
@@ -686,7 +686,7 @@ static unsigned long ulReadMDIO(volatile avr32_macb_t *macb, unsigned short usAd
  * \param usValue      Input. value to write.
  *
  */
-static void vWriteMDIO(volatile avr32_macb_t *macb, unsigned short usAddress, unsigned short usValue)
+static void vWriteMDIO(volatile avr32_macb_t *macb, unsigned short usAddress, unsigned short usValue)
 {
   unsigned long status;
   u16 timeout = 0;
@@ -708,7 +708,7 @@ static void vWriteMDIO(volatile avr32_macb_t *macb, unsigned short usAddress, un
   macb->ncr &= ~AVR32_MACB_NCR_MPE_MASK;
 }
 
-static Bool prvProbePHY(volatile avr32_macb_t *macb)
+static Bool prvProbePHY(volatile avr32_macb_t *macb)
 {
   volatile unsigned long mii_status, phy_ctrl;
   volatile unsigned long config;
@@ -716,28 +716,28 @@ static Bool prvProbePHY(volatile avr32_macb_t *macb)
   volatile unsigned long physID;
 
   // Read Phy Identifier register 1 & 2
-  lower = ulReadMDIO(macb, PHY_PHYSID2);
-  upper = ulReadMDIO(macb, PHY_PHYSID1);
+  lower = ulReadMDIO(macb, PHY_PHYSID2);
+  upper = ulReadMDIO(macb, PHY_PHYSID1);
   // get Phy ID, ignore Revision
   physID = ((upper << 16) & 0xFFFF0000) | (lower & 0xFFF0);
   // check if it match config
   if (physID == ETHERNET_CONF_PHY_ID)
   {
     // read RBR
-    mode = ulReadMDIO(macb, PHY_RBR);
+    mode = ulReadMDIO(macb, PHY_RBR);
     // set RMII mode if not done
     if ((mode & RBR_RMII) != RBR_RMII)
     {
       // force RMII flag if strap options are wrong
       mode |= RBR_RMII;
-      vWriteMDIO(macb, PHY_RBR, mode);
+      vWriteMDIO(macb, PHY_RBR, mode);
     }
 
     advertise = ADVERTISE_CSMA | ADVERTISE_ALL;
     // write advertise register
-    vWriteMDIO(macb, PHY_ADVERTISE, advertise);
+    vWriteMDIO(macb, PHY_ADVERTISE, advertise);
     // read Control register
-    config = ulReadMDIO(macb, PHY_BMCR);
+    config = ulReadMDIO(macb, PHY_BMCR);
     // read Phy Control register
     phy_ctrl = ulReadMDIO(macb, PHY_PHYCR);
     // enable Auto MDIX
@@ -745,18 +745,18 @@ static Bool prvProbePHY(volatile avr32_macb_t *macb)
     // reset auto-negociation capability
     config |= (BMCR_ANRESTART | BMCR_ANENABLE);
     // update Phy ctrl register
-    vWriteMDIO(macb, PHY_PHYCR, phy_ctrl);
+    vWriteMDIO(macb, PHY_PHYCR, phy_ctrl);
 
     // update ctrl register
-    vWriteMDIO(macb, PHY_BMCR, config);
+    vWriteMDIO(macb, PHY_BMCR, config);
 
     // loop while link status isn't OK
     do {
-      mii_status = ulReadMDIO(macb, PHY_BMSR);
+      mii_status = ulReadMDIO(macb, PHY_BMSR);
     } while (!(mii_status & BMSR_LSTATUS));
 
     // read the LPA configuration of the PHY
-    lpa = ulReadMDIO(macb, PHY_LPA);
+    lpa = ulReadMDIO(macb, PHY_LPA);
 
     // read the MACB config register
     config = AVR32_MACB.ncfgr;
@@ -779,17 +779,17 @@ static Bool prvProbePHY(volatile avr32_macb_t *macb)
     return TRUE;
   }
   return FALSE;
-}
-
-/*
- * The MACB ISR.  Handles both Tx and Rx complete interrupts.
+}
+
+/*
+ * The MACB ISR.  Handles both Tx and Rx complete interrupts.
  */
-__attribute__((__interrupt__)) void vMACB_ISR(void)
-{
+__attribute__((__interrupt__)) void vMACB_ISR(void)
+{
   // Variable definitions can be made now.
   volatile unsigned long ulIntStatus, ulEventStatus;
 
-	  // Find the cause of the interrupt.
+  // Find the cause of the interrupt.
   ulIntStatus = AVR32_MACB.isr;
   ulEventStatus = AVR32_MACB.rsr;
 
@@ -810,5 +810,5 @@ __attribute__((__interrupt__)) void vMACB_ISR(void)
     AVR32_MACB.tsr =  AVR32_MACB_TSR_COMP_MASK; // Clear
     AVR32_MACB.tsr; // Read to force the previous write
   }
-}
-#endif
+}
+#endif
diff --git a/src/platform/avr32/ethernet.h b/src/platform/avr32/ethernet.h
index 7eeab831..b51afa08 100644
--- a/src/platform/avr32/ethernet.h
+++ b/src/platform/avr32/ethernet.h
@@ -275,7 +275,7 @@ to use an MII interface. */
 #define ETHERNET_CONF_TX_BUFFER_SIZE       512
 
 /*! Clock definition */
-#define ETHERNET_CONF_SYSTEM_CLOCK         60000000
+#define ETHERNET_CONF_SYSTEM_CLOCK         REQ_CPU_FREQ
 
 /*! Allow Auto Negociation */
 #define ETHERNET_CONF_AN_ENABLE            1
@@ -413,7 +413,7 @@ typedef struct _AVR32_TxTdDescriptor {
  *
  * \return TRUE if success, FALSE otherwise.
  */
-extern Bool xMACBInit(volatile avr32_macb_t *macb);
+extern Bool xMACBInit(volatile avr32_macb_t *macb);
 
 /**
  * \brief Send ulLength bytes from pcFrom. This copies the buffer to one of the
@@ -428,7 +428,7 @@ extern Bool xMACBInit(volatile avr32_macb_t *macb);
  *
  * \return length sent.
  */
-extern long lMACBSend(volatile avr32_macb_t *macb, const void *pvFrom, unsigned long ulLength, long lEndOfFrame);
+extern long lMACBSend(volatile avr32_macb_t *macb, const void *pvFrom, unsigned long ulLength, long lEndOfFrame);
 
 /**
  * \brief Frames can be read from the MACB in multiple sections.
@@ -441,21 +441,21 @@ extern long lMACBSend(volatile avr32_macb_t *macb, const void *pvFrom, unsigned
  * \param ulSectionLength     Length of the buffer
  * \param ulTotalFrameLength  Length of the frame
  */
-extern void vMACBRead(void *pvTo, unsigned long ulSectionLength, unsigned long ulTotalFrameLength);
+extern void vMACBRead(void *pvTo, unsigned long ulSectionLength, unsigned long ulTotalFrameLength);
 
 /**
  * \brief Flush the current received packet.
  *
  * \param ulTotalFrameLength  Length of the packet to flush
  */
-extern void vMACBFlushCurrentPacket(unsigned long ulTotalFrameLength);
+extern void vMACBFlushCurrentPacket(unsigned long ulTotalFrameLength);
 
 /**
  * \brief Called by the Tx interrupt, this function traverses the buffers used to
  * hold the frame that has just completed transmission and marks each as
  * free again.
  */
-extern void vClearMACBTxBuffer(void);
+extern void vClearMACBTxBuffer(void);
 
 /**
  * \brief Suspend on a semaphore waiting either for the semaphore to be obtained
@@ -465,28 +465,28 @@ extern void vClearMACBTxBuffer(void);
  * \param ulTimeOut    time to wait for an input
  *
  */
-extern void vMACBWaitForInput(unsigned long ulTimeOut);
+extern void vMACBWaitForInput(unsigned long ulTimeOut);
 
 /**
  * \brief Function to get length of the next frame in the receive buffers
  *
  * \return the length of the next frame in the receive buffers.
  */
-extern unsigned long ulMACBInputLength(void);
+extern unsigned long ulMACBInputLength(void);
 
 /**
  * \brief Set the MACB Physical address (SA1B & SA1T registers).
  *
  * \param *MACAddress the MAC address to set.
  */
-extern void vMACBSetMACAddress(const unsigned char *MACAddress);
+extern void vMACBSetMACAddress(const unsigned char *MACAddress);
 
 /**
  * \brief Disable MACB operations (Tx and Rx).
  *
  * \param *macb        Base address of the MACB
  */
-extern void vDisableMACBOperations(volatile avr32_macb_t *macb);
-
+extern void vDisableMACBOperations(volatile avr32_macb_t *macb);
+
 
 #endif
diff --git a/src/platform/avr32/i2c.c b/src/platform/avr32/i2c.c
new file mode 100644
index 00000000..62df700c
--- /dev/null
+++ b/src/platform/avr32/i2c.c
@@ -0,0 +1,352 @@
+// This file implements I2C protocol on AVR32 devices in eLua.
+//
+// For reasons outlined below, it does not use the Atmel TWI hardware
+// but implements it by bit-banging two GPIO lines.
+//
+//      Martin Guy , June 2011
+
+// AVR32 has two families of "two wire" interfaces, both of them inadequate:
+//
+// AT32UC3A[01]* and AT32UC3B* have a single "TWI" "I2C-compatibile" interface
+//   that can be switched between master and slave modes;
+// AT32UC3A[34]* and AT32UC3C* devices have separate "TWIM" and "TWIS"
+//   interfaces, three of each in the C series.
+// Their registers and functionality are completely different,
+//
+// All currently supported eLua AVR32 targets
+// (EVK1100 Mizar32 == AT32UC3A0* and EVK1101 == AT32UC3B*)
+// have one "TWI" interface.
+//
+// 1) "TWI" hardware limitations
+// 
+// The only repeated start sequence that TWI can generate as master is
+// START/ADDRESS(W)/WRITE 1, 2 or 3 bytes/START/ADDRESS(R)/READ n BYTES/STOP.
+//
+// It cannot emit START/ADDRESS(R/W)/STOP, which is necessary to probe
+// for the presence of a device on the bus. Their SDK writes a single 0 bytes
+// to do this, which has different effects on different hardware.
+// This makes I2C unimplementable using this variant of the hardware.
+//
+// Worse, you have to have all the data in hand before you start any transfer
+// because if you fail to rewrite the "Transmit Holding Register" with the next
+// byte while the current byte is being sent, the hardware automatically
+// generates a STOP without asking you.
+// This makes eLua's current Lua and C I2C interfaces unimplementable.
+//
+// 2) "TWIM" and "TWIS" hardware limitations
+//
+// This seems to be able to generate a wider range of repeated start signals
+// but the amount of data you can send or receive in one packet is limited to
+// 255 bytes.
+//
+// 3) Bit-banging them as GPIO pins
+//
+// Given the two sets of incompatible hardware and the fact that neither is
+// capable either of speaking I2C or of implementing the current eLua I2C
+// interface, we just bit-bang the IO pins.
+//
+// Some of the chips (e.g. AVR32UC3[01]*) have a GPIO open-collector mode,
+// which sounds promising, but others (AVR32UC3A[34], AVR32UC3[BC]) do not
+// so we obtain a pseudo-open-collector mode by switching the GPIO pins
+// between output (always low) and input (of high impedance).
+//
+// The disadvantage of bit-banging GPIO pins instead of using the TWI hardware
+// is that in TWI mode, the pins "are open-drain outputs with slew-rate
+// limitation and inputs with spike-filtering" (AT32UC3A Datasheet, para 8.3).
+// In GPIO mode, a "glitch filter" is available to reject pulses of 1 CPU cycle
+// but this only affects the interrupt function, not the value read from the
+// PVR register. (para 22.4.8)
+
+// This first hack only support a single I2C channel and is only tested on the
+// currently supported hardware (AVR32UC3A0*), all of which has a single TWI
+// interface.
+// To extend it to have multiple I2C channels you need to turn the variables
+//   started, delay, sda_regs, scl_regs
+// and the constants
+//   {SDA,SCL}_{PIN,PORT,PINMASK}
+// into arrays[NUM_I2C] and index them with id.
+
+#include "platform_conf.h"
+#include "compiler.h"
+#include "gpio.h"
+#include "i2c.h"
+
+// Which port/pins are used for I2C?
+
+#if   defined(ELUA_CPU_AT32UC3A0128) || \
+      defined(ELUA_CPU_AT32UC3A0256) || \
+      defined(ELUA_CPU_AT32UC3A0512) || \
+      defined(ELUA_CPU_AT32UC3A1128) || \
+      defined(ELUA_CPU_AT32UC3A1256) || \
+      defined(ELUA_CPU_AT32UC3A1512)
+
+// One master-slave TWI interface
+# define SDA_PIN     AVR32_PIN_PA29
+# define SCL_PIN     AVR32_PIN_PA30
+
+#elif defined(ELUA_CPU_AT32UC3A364)  || defined(ELUA_CPU_AT32UC3A364S)  || \
+      defined(ELUA_CPU_AT32UC3A3128) || defined(ELUA_CPU_AT32UC3A3128S) || \
+      defined(ELUA_CPU_AT32UC3A3256) || defined(ELUA_CPU_AT32UC3A3256S) || \
+      defined(ELUA_CPU_AT32UC3A464)  || defined(ELUA_CPU_AT32UC3A464S)  || \
+      defined(ELUA_CPU_AT32UC3A4128) || defined(ELUA_CPU_AT32UC3A4128S) || \
+      defined(ELUA_CPU_AT32UC3A4256) || defined(ELUA_CPU_AT32UC3A4256S)
+
+// The first of the two TWIM/TWIS interfaces, in pin configuration A
+# define SDA_PIN     AVR32_PIN_PA25
+# define SCL_PIN     AVR32_PIN_PA26
+
+#elif defined(ELUA_CPU_AT32UC3B064)  || \
+      defined(ELUA_CPU_AT32UC3B0128) || \
+      defined(ELUA_CPU_AT32UC3B0256) || \
+      defined(ELUA_CPU_AT32UC3B0512) || \
+      defined(ELUA_CPU_AT32UC3B164)  || \
+      defined(ELUA_CPU_AT32UC3B1128) || \
+      defined(ELUA_CPU_AT32UC3B1256) || \
+      defined(ELUA_CPU_AT32UC3B1512)
+
+// One master-slave TWI interface
+# define SDA_PIN     AVR32_PIN_PA10
+# define SCL_PIN     AVR32_PIN_PA09
+
+#elif defined(ELUA_CPU_AT32UC3C064C)  || \
+      defined(ELUA_CPU_AT32UC3C0128C) || \
+      defined(ELUA_CPU_AT32UC3C0256C) || \
+      defined(ELUA_CPU_AT32UC3C0512C) || \
+      defined(ELUA_CPU_AT32UC3C164C)  || \
+      defined(ELUA_CPU_AT32UC3C1128C) || \
+      defined(ELUA_CPU_AT32UC3C1256C) || \
+      defined(ELUA_CPU_AT32UC3C1512C) || \
+      defined(ELUA_CPU_AT32UC3C264C)  || \
+      defined(ELUA_CPU_AT32UC3C2128C) || \
+      defined(ELUA_CPU_AT32UC3C2256C) || \
+      defined(ELUA_CPU_AT32UC3C2512C)
+
+// One master-slave TWI interface
+# define SDA_PIN     AVR32_PIN_PC02
+# define SCL_PIN     AVR32_PIN_PC03
+
+#else
+# error "I2C pin assignment is unknown for this CPU"
+#endif
+
+// Split these into port and pinmask
+#define SDA_PORT    ( SDA_PIN >> 5 )
+#define SCL_PORT    ( SCL_PIN >> 5 )
+#define SDA_PINMASK ( 1 << ( SDA_PIN & 31 ) )
+#define SCL_PINMASK ( 1 << ( SCL_PIN & 31 ) )
+
+// The set of GPIO registers we will be using for each bus line.
+// In practice, these two will always have the same value. Ho hum.
+static volatile avr32_gpio_port_t *sda_regs =
+        &AVR32_GPIO.port[ SDA_PORT ];
+static volatile avr32_gpio_port_t *scl_regs =
+        &AVR32_GPIO.port[ SCL_PORT ];
+
+// Half an I2C bus clock cycle, as a number of HSB(==CPU) clock cycles;
+// Be default, use the slow mode setting.
+// This is exported to the LCD display driver ("disp") so that it can
+// change the bus speed as required by the LCD, then restore it.
+u32 i2c_delay = REQ_CPU_FREQ / 100000 / 2;
+
+// Local functions used by the bit-banger
+static void I2CDELAY(void); // Pause for half an I2C bus clock cycle
+static int READSCL(void);   // Set SCL as input and return current level of line
+static int READSDA(void);   // Set SDA as input and return current level of line
+static void CLRSCL(void);   // Actively drive SCL signal low
+static void CLRSDA(void);   // Actively drive SDA signal low
+static void ARBITRATION_LOST(void); // Bus control was lost
+
+// ************************
+// The bitbanger itself, taken from http://en.wikipedia.org/wiki/I2C
+
+// We don't use GPIO open-drain mode, which is not available on all hardware
+// models. Instead, we use two modes to simulate open-drain:
+// output of 0 and input.
+u32 i2c_setup( u32 speed )
+{
+  // First, set both pins as high-impedance inputs to avoid startup glitches
+  sda_regs->oderc = SDA_PINMASK;
+  scl_regs->oderc = SCL_PINMASK;
+
+  // When they are outputs, they will always output 0.
+  sda_regs->ovrc = SDA_PINMASK;
+  scl_regs->ovrc = SCL_PINMASK;
+
+  // Let the GPIO hardware control these pins
+  sda_regs->gpers = SDA_PINMASK;
+  scl_regs->gpers = SCL_PINMASK;
+
+  // Limit range to possible values, to avoid divisions by zero below.
+  if (speed == 0) speed = 1;
+  if (speed > REQ_CPU_FREQ / 2) speed = REQ_CPU_FREQ / 2;
+
+  // Figure out how many clock cycles correspond to half a clock waveform.
+  // "+(speed-1)" ensures we never set a faster speed than what they asked for.
+  i2c_delay = ( REQ_CPU_FREQ / 2 + (speed - 1) ) / speed;
+
+  // Return the closest integer to the actual speed we set
+  return ( REQ_CPU_FREQ / 2 + i2c_delay / 2 ) / i2c_delay;
+}
+
+// Are we between a start bit and a stop bit?
+static int started = 0;
+
+void i2c_start_cond(void)
+{
+  if (started) {
+    // if started, do a restart cond
+    // set SDA to 1
+    READSDA();
+    I2CDELAY();
+    // Clock stretching
+    while (READSCL() == 0)
+      ;  // You can add a timeout to this loop to
+         // recover from SCL being stuck low.
+    // Repeated start setup time, minimum 4.7us
+    I2CDELAY();
+  }
+  if (READSDA() == 0)
+    ARBITRATION_LOST();
+  // SCL is high, set SDA from 1 to 0
+  CLRSDA();
+  I2CDELAY();
+  CLRSCL();
+  started = true;
+}
+ 
+void i2c_stop_cond(void)
+{
+  /* set SDA to 0 */
+  CLRSDA();
+  I2CDELAY();
+  /* Clock stretching */
+  while (READSCL() == 0)
+    ;  /* You should add timeout to this loop */
+  /* SCL is high. Respect I2C spec's minimum stop setup time of 4ms. */
+  I2CDELAY();
+  /* set SDA from 0 to 1 */
+  if (READSDA() == 0)
+    ARBITRATION_LOST();
+  I2CDELAY();
+  started = false;
+}
+ 
+/* Write a bit to I2C bus */
+static void i2c_write_bit(int bit)
+{
+  if (bit) 
+    READSDA();
+  else 
+    CLRSDA();
+  I2CDELAY();
+  /* Clock stretching */
+  while (READSCL() == 0)
+    ;  /* You should add timeout to this loop */
+  /* SCL is high, now data is valid */
+  /* If SDA is high, check that nobody else is driving SDA */
+  if (bit && READSDA() == 0) 
+    ARBITRATION_LOST();
+  I2CDELAY();
+  CLRSCL();
+}
+ 
+/* Read a bit from I2C bus */
+static int i2c_read_bit(void)
+{
+  int bit;
+
+  /* Let the slave drive data */
+  READSDA();
+  I2CDELAY();
+  /* Clock stretching */
+  while (READSCL() == 0)
+    ;  /* You should add timeout to this loop */
+  /* SCL is high, now data is valid */
+  bit = READSDA();
+  I2CDELAY();
+  CLRSCL();
+  return bit;
+}
+ 
+/* Write a byte to I2C bus. Return 0 if ack by the slave */
+int i2c_write_byte(unsigned char byte)
+{
+  unsigned bit;
+  int nack;
+
+  for (bit = 0; bit < 8; bit++) {
+    i2c_write_bit((byte & 0x80) != 0);
+    byte <<= 1;
+  }
+  nack = i2c_read_bit();
+
+  return nack;
+}
+ 
+/* Read a byte from I2C bus */
+unsigned char i2c_read_byte(int nack)
+{
+  unsigned char byte = 0;
+  unsigned bit;
+
+  for (bit = 0; bit < 8; bit++)
+    byte = (byte << 1) | i2c_read_bit();             
+  i2c_write_bit(nack);
+
+  return byte;
+}
+
+//*******************
+// Low-level functions used by the bit-banger
+
+// Pause for half an I2C bus clock cycle
+static void I2CDELAY()
+{
+  // Code stolen from sdramc.c::sdramc_ck_delay()
+
+  // Use the CPU cycle counter (CPU and HSB clocks are the same).
+  u32 delay_start_cycle = Get_system_register(AVR32_COUNT);
+  u32 delay_end_cycle = delay_start_cycle + i2c_delay;
+ 
+  // To be safer, the end of wait is based on an inequality test, so CPU cycle
+  // counter wrap around is checked.
+  if (delay_start_cycle > delay_end_cycle)
+  { 
+    while ((unsigned long)Get_system_register(AVR32_COUNT) > delay_end_cycle);
+  }
+  while ((unsigned long)Get_system_register(AVR32_COUNT) < delay_end_cycle);
+}
+
+// Set SCL as input and return current level of line
+static int READSCL()
+{
+  scl_regs->oderc = SCL_PINMASK;
+  return ( scl_regs->pvr & SCL_PINMASK ) ? 1 : 0;
+}
+
+// Set SDA as input and return current level of line
+static int READSDA()
+{
+  sda_regs->oderc = SDA_PINMASK;
+  return ( sda_regs->pvr & SDA_PINMASK ) ? 1 : 0;
+}
+
+// Actively drive SCL signal low
+static void CLRSCL(void)
+{
+  scl_regs->oders = SCL_PINMASK;
+}
+
+// Actively drive SDA signal low
+static void CLRSDA(void)
+{
+  sda_regs->oders = SDA_PINMASK;
+}
+
+// Bus control was lost.
+// Not currently used. With a higher-level I2C interface, this can do a
+// longjmp back to the eLua C interface routine which can retry the transfer
+// when the bus is free.
+static void ARBITRATION_LOST(void)
+{
+}
diff --git a/src/platform/avr32/i2c.h b/src/platform/avr32/i2c.h
new file mode 100644
index 00000000..6646f3cf
--- /dev/null
+++ b/src/platform/avr32/i2c.h
@@ -0,0 +1,9 @@
+// Declarations for the low-level AVR32 I2C driver for eLua
+
+#include "type.h"	// for u32
+
+u32 i2c_setup( u32 speed );                // speed is in Hz
+void i2c_start_cond( void );
+void i2c_stop_cond( void );
+int i2c_write_byte( unsigned char byte );  // returns 0 if acked by slave
+unsigned char i2c_read_byte( int nack );
diff --git a/src/platform/avr32/lcd.c b/src/platform/avr32/lcd.c
new file mode 100644
index 00000000..613e3da3
--- /dev/null
+++ b/src/platform/avr32/lcd.c
@@ -0,0 +1,392 @@
+// eLua module for Mizar32 LCD character display
+
+#include "lua.h"
+#include "lualib.h"
+#include "lauxlib.h"
+#include "platform.h"
+#include "lrotable.h"
+#include "platform_conf.h"
+
+#include "lcd.h"       
+#include "i2c.h"
+
+
+// Since the LCD firmware currently only runs at up to 20kHz on the I2C bus,
+// we bracket all I2C packets to the LCD module with two functions
+// to be able to save, change and restore the I2C clock rate to what it was
+// before.
+
+// Declarations to save/restore the I2C clock rate
+extern u32 i2c_delay;
+static u32 old_i2c_delay;
+
+static void lcd_start()
+{
+  old_i2c_delay = i2c_delay;
+  i2c_delay = REQ_CPU_FREQ / LCD_BUS_FREQ / 2;
+}
+
+static void lcd_stop()
+{
+  i2c_delay = old_i2c_delay;
+}
+
+
+// Low-level functions to send LCD commands or data.
+// The command and data packets differ only in the slave address used,
+// so we coalesce them into a single function, generating smaller code.
+//
+// All three are designed to be used in a tail call:
+//   return send_generic( data, len );
+
+// Send a command or data packet.
+// "address" is LCD_CMD for LCD commands, LCD_DATA for LCD data.
+static int send_generic(char address, const char *data, int len)
+{
+  while (len > 0) {
+    int nbytes;    // number of bytes sent in this I2C packet
+
+    lcd_start();
+    i2c_start_cond();
+    i2c_write_byte( address );
+    // Mizar32 LCD module has a maximum of 31 bytes per data packet
+    nbytes = 0;
+    while ( len > 0 && nbytes < 31 ) {
+      i2c_write_byte( *data++ );
+      nbytes++; len--;
+    }
+    i2c_stop_cond();
+    lcd_stop();
+  }
+  return 0;
+}
+
+// Send a single command byte
+static int send_command(const char command)
+{
+  return send_generic(LCD_CMD, &command, 1);
+}
+
+// Send multiple command bytes as one message
+static int send_commands(const char *commands, int len)
+{
+  return send_generic(LCD_CMD, commands, len);
+}
+
+// Send data bytes
+// This is used for printing data and for programming the user-defining chars
+static int send_data(const char *data, int len)
+{
+  return send_generic(LCD_DATA, data, len);
+}
+
+
+// *** Lua module functions begin... ***
+
+
+// Turning the display on can only be achieved by simultaneously specifying the
+// cursor type, so we have to remember what type of cursor they last set.
+// Similarly, if they have turned the display off then set the cursor, this
+// shouldn-t turn the display on.
+
+// Power-on setting is no cursor
+#define DEFAULT_CURSOR_TYPE   LCD_CMD_CURSOR_NONE
+
+static char cursor_type = DEFAULT_CURSOR_TYPE;
+static char display_is_off = 0;     // Have they called display("off")?
+
+
+// Should we try to maintain the current cursor position across a definechar()?
+// Unfortunately we can't read the current cursor position, and definechar()
+// destroys it. The LCD controller does have a read-cursor-position primitive
+// but the current PIC firmware doesn't pass this on as an I2C read.2
+// So we have to track the cursor position. Yuk.
+// The only relief is that we don't have to track the display scrolling.
+// Adds 284 bytes of code to the executable.
+//
+// If, one day, we can read the LCD cursor position through the PIC firmware
+// we can remove all this stuff.
+#define KEEP_CURSOR_POSITION 1
+
+#ifdef KEEP_CURSOR_POSITION
+// Where is the cursor in the character memory?  Required ONLY to be able to
+// restore the cursor position when they define a character :-/
+static int current_row = 0;        // 0 or 1
+static int current_column = 0;     // 0-39 (though it over- and underflows)
+static int current_direction = 1;  // left-to-right. -1 is right-to-left
+#endif
+
+
+// Lua: mizar32.disp.reset()
+// Ensure the display is in a known initial state
+static int lcd_reset( lua_State *L )
+{
+  // Initialise the display to a known state
+  static const char reset[] = {
+    0	/* reset */
+  };
+
+  // Set the static variables
+  cursor_type = DEFAULT_CURSOR_TYPE;
+  display_is_off = 0;
+#ifdef KEEP_CURSOR_POSITION
+  current_row = current_column = 0;
+  current_direction = 1;
+#endif
+
+  return send_commands( reset, sizeof( reset ) );
+}
+
+// "Entry mode" function.
+
+// Lua: mizar32.disp.setup( shift_display, right-to-left )
+// Set right-to-left mode,
+static int lcd_setup( lua_State *L )
+{
+  // lua_toboolean returns 0 or 1, and returns 0 if the parameter is absent
+  unsigned shift_display = lua_toboolean( L, 1 );  // Default: move cursor
+  unsigned right_to_left = lua_toboolean( L, 2 );  // Default: print left-to-right
+
+#ifdef KEEP_CURSOR_POSITION
+  current_direction = right_to_left ? -1 : 1;
+#endif
+
+  return send_command( LCD_CMD_ENTRYMODE + shift_display +
+                       (!right_to_left) * 2 );
+}
+
+// Lua: mizar32.disp.clear()
+// Clear the display, reset its shiftedness and put the cursor at 1,1
+static int lcd_clear( lua_State *L )
+{
+#ifdef KEEP_CURSOR_POSITION
+  current_row = current_column = 0;
+#endif
+  return send_command( LCD_CMD_CLEAR );
+}
+
+// Lua: mizar32.disp.home()
+// Reset the display's shiftedness and put the cursor at 1,1
+static int lcd_home(lua_State *L)
+{
+#ifdef KEEP_CURSOR_POSITION
+  current_row = current_column = 0;
+#endif
+  return send_command( LCD_CMD_HOME );
+}
+
+// Lua: mizar32.disp.goto( row, col )
+// Move the cursor to the specified row (1 or 2) and column (1-40)
+// in the character memory.
+static int lcd_goto(lua_State *L)
+{
+  unsigned row = luaL_checkinteger( L, 1 );
+  unsigned col = luaL_checkinteger( L, 2 );
+  unsigned address;
+
+  if ( row < 1 || row > 2 || col < 1 || col > 40 )
+    return luaL_error( L, "row/column must be 1-2 and 1-40" );
+
+#ifdef KEEP_CURSOR_POSITION
+  current_row = row - 1;
+  current_column = col - 1;
+#endif
+  address = ( row - 1 ) * 0x40 + ( col - 1 ) ;
+  return send_command( LCD_CMD_DDADDR + address );
+}
+
+// Lua: mizar32.disp.print( string )
+// Send data bytes to the LCD module.
+// Usually this will be a string of text or a list of character codes.
+// If they pass us integer values <0 or >255, we just use the bottom 8 bits.
+
+#ifdef KEEP_CURSOR_POSITION
+// Adjust current cursor position by N printed characters.
+// Written for shortest code.
+static void current_print(int n)
+{
+  current_column += current_direction * n;
+  if (current_column < 0 || current_column >= 40) {
+    current_row = ! current_row;
+    current_column -= 40 * current_direction;
+  }
+}
+#endif
+
+static int lcd_print(lua_State *L)
+{
+  unsigned argc = lua_gettop( L );  // Number of parameters supplied
+  int argn;
+  
+  for ( argn = 1; argn <= argc; argn ++ )
+  {
+    switch (lua_type( L, argn ) )
+    {
+      case LUA_TNUMBER:
+      {
+        char byte = luaL_checkint( L, argn );
+
+#ifdef KEEP_CURSOR_POSITION
+        current_print(1);
+#endif
+        send_data(&byte, (size_t) 1);
+      }
+      break;
+
+      case LUA_TSTRING:
+      {
+        size_t len;  // Number of chars in string
+        const char *str = luaL_checklstring( L, argn, &len );
+
+#ifdef KEEP_CURSOR_POSITION
+        current_print(len);
+#endif
+        send_data(str, len);
+      }
+      break;
+
+      default:
+        return luaL_typerror( L, argn, "integer or string" );
+    }
+  }
+  return 0;
+}
+
+
+// "Display on/off control" functions
+
+// Helper function to set a cursor type if the display is on,
+// or to remember which cursor they asked for, to be able to set it
+// when they turn the display on.
+static int set_cursor( char command_byte )
+{
+  cursor_type = command_byte;
+
+  // Setting cursor type always turns the display on
+  if (display_is_off)
+    return 0;
+  else
+    return send_command( cursor_type );
+}
+
+// Perform cursor operations, selected by a string parameter,
+// as recommended in the Lua Reference Manual, p.58: "luaL_checkoption()"
+static int lcd_cursor( lua_State *L )
+{
+  static const char const *args[] =
+    { "none", "block", "line", "left", "right", NULL };
+
+  switch ( luaL_checkoption( L, 1, NULL, args ) )
+  {
+  case 0:
+    return set_cursor( LCD_CMD_CURSOR_NONE );
+  case 1:
+    return set_cursor( LCD_CMD_CURSOR_BLOCK );
+  case 2:
+    return set_cursor( LCD_CMD_CURSOR_LINE );
+
+  case 3: 
+#ifdef KEEP_CURSOR_POSITION
+    if (--current_column < 0) {
+      current_row = !current_row;
+      current_column = 39;
+    }
+#endif
+    return send_command( LCD_CMD_SHIFT_CURSOR_LEFT );
+
+  case 4:
+#ifdef KEEP_CURSOR_POSITION
+    if (++current_column >= 40) {
+      current_row = !current_row;
+      current_column = 0;
+    }
+#endif
+    return send_command( LCD_CMD_SHIFT_CURSOR_RIGHT );
+
+  default: return luaL_argerror( L, 1, NULL );
+  }
+}
+
+// Perform display operations, selected by a string parameter.
+static int lcd_display( lua_State *L )
+{
+  static const char const *args[] =
+    { "off", "on", "left", "right", NULL };
+
+  switch ( luaL_checkoption( L, 1, NULL, args ) )
+  {
+  case 0: display_is_off = 1;
+	  return send_command( LCD_CMD_DISPLAY_OFF );
+  case 1: display_is_off = 0;
+          return send_command( cursor_type );	// Turns display on
+  case 2: return send_command( LCD_CMD_SHIFT_DISPLAY_LEFT );
+  case 3: return send_command( LCD_CMD_SHIFT_DISPLAY_RIGHT );
+  default: return luaL_argerror( L, 1, NULL );
+  }
+}
+
+// Lua: mizar32.disp.definechar( code, glyph )
+// code: 0-7
+// glyph: a table of up to 8 numbers with values 0-31.
+//        If less than 8 are supplied, the bottom rows are blanked.
+//        If more than 8 are supplied, the extra are ignored.
+
+static int lcd_definechar( lua_State *L ) {
+  int code;        // The character code we are defining, 0-7
+  size_t datalen;  // The number of elements in the glyph table
+  size_t line;     // Which line of the char are we defining?
+  char data[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
+#ifdef KEEP_CURSOR_POSITION
+  int old_column = current_column, old_row = current_row;
+#endif
+
+  // First parameter: glyph code to define
+  code = luaL_checkint( L, 1 );
+  if( code < 0 || code > 7 )
+    return luaL_error( L, "user-defined characters have codes 0-7");
+
+  // Second parameter: table of integer values to define the glyph
+  luaL_checktype( L, 2, LUA_TTABLE );
+  datalen = lua_objlen( L, 2 );
+  // Check all parameters before starting the I2C command.
+  if( datalen >= 8) datalen = 8;            // Ignore extra parameters
+  for( line = 0; line < datalen; line ++ )
+  {
+    int value;
+    lua_rawgeti( L, 2, line + 1 );
+    value = luaL_checkint( L, -1 );
+    lua_pop( L, 1 );
+    data[line] = value;
+  }
+
+  send_command( LCD_CMD_CGADDR + code * 8 );
+  send_data( data, sizeof(data) );
+
+#ifdef KEEP_CURSOR_POSITION
+  // Move back to where we were
+  current_row = old_row; current_column = old_column;
+  return send_command( LCD_CMD_DDADDR + current_row * 0x40 + current_column );
+#else
+  // Sadly, we cannot save and restore the current cursor position
+  // so return to the home position.
+  return send_command( LCD_CMD_DDADDR );
+#endif
+}
+
+#define MIN_OPT_LEVEL 2
+#include "lrodefs.h"
+
+// mizar32.disp.*() module function map
+const LUA_REG_TYPE lcd_map[] =
+{
+  { LSTRKEY( "reset" ),      LFUNCVAL( lcd_reset ) },
+  { LSTRKEY( "setup" ),      LFUNCVAL( lcd_setup ) },
+  { LSTRKEY( "clear" ),      LFUNCVAL( lcd_clear ) },
+  { LSTRKEY( "home" ),       LFUNCVAL( lcd_home ) },
+  { LSTRKEY( "goto" ),       LFUNCVAL( lcd_goto ) },
+  { LSTRKEY( "print" ),      LFUNCVAL( lcd_print ) },
+  { LSTRKEY( "definechar" ), LFUNCVAL( lcd_definechar ) },
+  { LSTRKEY( "cursor" ),     LFUNCVAL( lcd_cursor ) },
+  { LSTRKEY( "display" ),    LFUNCVAL( lcd_display ) },
+  { LNILKEY, LNILVAL }
+};
diff --git a/src/platform/avr32/lcd.h b/src/platform/avr32/lcd.h
new file mode 100644
index 00000000..32ec7df2
--- /dev/null
+++ b/src/platform/avr32/lcd.h
@@ -0,0 +1,102 @@
+// Mizar32 LCD character display
+
+#ifndef __LCD_H__
+#define __LCD_H__
+
+// See the Ampire datasheet http://home.comet.bg/datasheets/LCD/AC-162B.pdf
+// and http://embeddedtutorial.com/2010/01/interfacing-lcd-with-8051/
+
+// I2C bus frequency that the LCD display runs at.
+// It works up to 54kHz, with another window at 67 to 68kHz.
+// For reliable operation, we set it to 10% less than the highest "normal" speed.
+#define LCD_BUS_FREQ 50000
+
+// I2C slave addresses for command bytes and data strings
+// Command address is followed by a dingle byte giving the command to perform
+// Data address is followed by multiple bytes of ASCII data to display
+// on the character display at the current cursor location.
+#define LCD_CMD  0x7C
+#define LCD_DATA 0x7E
+
+// Command bytes
+
+// "Clear display: Write "20H" to DDRAM and set DDRAM address to "00H" from AC"
+#define LCD_CMD_CLEAR              1
+
+// "Return Home: Sets DDRAM address to "00H" from AC and return cursor to its
+// original position if shifted."
+#define LCD_CMD_HOME               2      // Bit 0: don't care
+
+// "Assign cursor moving direction and enable the shift of entire display"
+#define LCD_CMD_ENTRYMODE          4
+#define LCD_CMD_ENTRYMODE_SHIFT      1    // 0: move cursor / 1: shift display
+#define LCD_CMD_ENTRYMODE_DIRECTION  2    // 0: move/shift left / 1: right
+// or, if you prefer...
+#define LCD_CMD_ENTRYMODE_MOVE_LEFT   4   // move cursor left when printing
+#define LCD_CMD_ENTRYMODE_SHIFT_LEFT  5   // shift display left when printing
+#define LCD_CMD_ENTRYMODE_MOVE_RIGHT  6   // move cursor right when printing
+#define LCD_CMD_ENTRYMODE_SHIFT_RIGHT 7   // shift display right when printing
+
+// Command 8 uses bits 4,2,1 to set display on/off, underline cursor on/off
+// and blinking block on/off.
+#define LCD_CMD_DISPLAY_OFF        8
+#define LCD_CMD_CURSOR_NONE        12
+#define LCD_CMD_CURSOR_BLOCK       13
+#define LCD_CMD_CURSOR_LINE        14
+#define LCD_CMD_CURSOR_BOTH        15
+
+// "Set cursor moving and display shift control bit, and the direction,
+// without changing of DDRAM data".
+//
+// Actually, this sets no bits at all. It just moves the cursor one place
+// left or right or shift the display contents one place left or right.
+//
+// Command 16 uses bits 8 and 4 to move the cursor one place left or right in
+// the character memory and on the display,
+// or to shift the displayed characters one place left or right.
+// Bit 8 is 0 to move the cursor, 1 to shift the display
+// Bit 4 is 0 to move the cursor or to shift the displayed characters left,
+//          1 to move the cursor or to shift the displayed characters right
+// When shifting the display left, the cursor also moves one place left in the
+// physical display, so remains over the same character as before.
+#define LCD_CMD_SHIFT              16
+#define LCD_CMD_SHIFT_LEFT           0
+#define LCD_CMD_SHIFT_RIGHT          4
+#define LCD_CMD_SHIFT_CURSOR         0
+#define LCD_CMD_SHIFT_DISPLAY        8
+// or, if you prefer...
+#define LCD_CMD_SHIFT_CURSOR_LEFT   16
+#define LCD_CMD_SHIFT_CURSOR_RIGHT  20
+#define LCD_CMD_SHIFT_DISPLAY_LEFT  24
+#define LCD_CMD_SHIFT_DISPLAY_RIGHT 28
+
+// Command 32 uses bits 16, 8 and 4 to set 
+// - interface data length (0 = 4-bit, 16 = 8-bit).  Mizar32 uses 4-bit
+// - number of displayed lines (0 = one, 8 = two)
+// - display font type (0 = 5x8, 4 = 5x11).
+#define LCD_CMD_FUNCTION          32
+#define LCD_CMD_FUNCTION_DATABITS_4 0
+#define LCD_CMD_FUNCTION_DATABITS_8 16
+#define LCD_CMD_FUNCTION_LINES_1    0
+#define LCD_CMD_FUNCTION_LINES_2    8
+#define LCD_CMD_FUNCTION_FONT_5x8   0
+#define LCD_CMD_FUNCTION_FONT_5x11  4
+
+// "Sets CG RAM address in address counter"
+// Sets an address in the user-defined character generator RAM.
+// The bottom 6 bits define which character to define as code(0-7) * 8.
+// Data is then sent to write values 0-31 into the CG RAM, which define a
+// character with one byte per row from top to bottom, and bits
+// 16, 8, 4, 2, 1 defining the row's pixels left to right.
+#define LCD_CMD_CGADDR           64
+
+// "Sets DD RAM address in address counter"
+// Bits 0-7 are the address:
+//   00-0F are the first line
+//   40-4F are the second line
+// The location automatically wraps from the end of the first row to the
+// start of the second, the end of the second to the start of the first and,
+// when printing from right to left, vice versa.
+#define LCD_CMD_DDADDR           128
+
+#endif
diff --git a/src/platform/avr32/platform.c b/src/platform/avr32/platform.c
index 8832d72b..e1121538 100644
--- a/src/platform/avr32/platform.c
+++ b/src/platform/avr32/platform.c
@@ -15,7 +15,6 @@
 #include "platform_conf.h"
 #include "common.h"
 #include "buf.h"
-#include "spi.h"
 #ifdef BUILD_MMCFS
 #include "diskio.h"
 #endif
@@ -40,21 +39,76 @@
 #include "spi.h"
 #include "adc.h"
 #include "pwm.h"
+#include "i2c.h"
+
+#ifdef BUILD_UIP
 
 // UIP sys tick data
 // NOTE: when using virtual timers, SYSTICKHZ and VTMR_FREQ_HZ should have the
 // same value, as they're served by the same timer (the systick)
-#define SYSTICKHZ               4
-#define SYSTICKMS               (1000 / SYSTICKHZ)
-
-#ifdef BUILD_UIP
-static int eth_timer_fired;
+#if !defined( VTMR_NUM_TIMERS ) || VTMR_NUM_TIMERS == 0
+# error "On AVR32, UIP needs virtual timer support. Define VTMR_NUM_TIMERS > 0."
 #endif
 
+#define SYSTICKHZ VTMR_FREQ_HZ
+#define SYSTICKMS (1000 / SYSTICKHZ)
+
+static int eth_timer_fired;
+
+#endif // BUILD_UIP
+
+// ****************************************************************************
+// AVR32 system timer implementation
+
+// Since the timer hardware (TC) on the AVR32 is pretty basic (16-bit timers,
+// limited prescaling options) we'll be using the PWM subsystem for the system
+// timer. The PWM hardware has much better prescaling options and it uses 20-bit
+// timers which are perfect for our needs. As a bonus, each PWM channel can be
+// clocked from two independent linear prescalers (CLKA and CLKB). The AVR32
+// PWM driver (pwm.c) uses only CLKA and disables CLKB, so by using CLKB we
+// won't change the regular PWM behaviour. The only downside is that we'll steal
+// a PWM channel for the system timer.
+
+#define SYSTIMER_PWM_CH       6
+
+__attribute__((__interrupt__)) static void systimer_int_handler()
+{
+  volatile u32 dummy = AVR32_PWM.isr; // clear interrupt
+
+  ( void )dummy;
+  cmn_systimer_periodic();
+}
+
+static void platform_systimer_init()
+{
+  avr32_pwm_mr_t mr = AVR32_PWM.MR;
+
+  // Set CLKB prescaler for 1MHz clock (which is exactly our system clock frequency)
+  mr.preb = 0; // main source clock is MCK (PBA)
+  mr.divb = REQ_PBA_FREQ / 1000000; // set CLKB to 1MHz
+  AVR32_PWM.MR = mr;
+
+  // Now setup our PWM channel
+  // Clock from CLKB, left aligned (the other parameters are not important)
+  AVR32_PWM.channel[ SYSTIMER_PWM_CH ].cmr = AVR32_PWM_CMR_CPRE_CLKB;
+  // The period register is 20-bit wide (1048576). We set it so we get interrupts
+  // every second (which results in a very reasonable system load)
+  AVR32_PWM.channel[ SYSTIMER_PWM_CH ].cprd = 1000000;
+  // The duty cycle is arbitrary set to 50%
+  AVR32_PWM.channel[ SYSTIMER_PWM_CH ].cdty = 500000;
+
+  // Setup PWM interrupt
+  INTC_register_interrupt( &systimer_int_handler, AVR32_PWM_IRQ, AVR32_INTC_INT0 );
+  AVR32_PWM.ier = 1 << SYSTIMER_PWM_CH;
+
+  // Enable the channel
+  AVR32_PWM.ena = 1 << SYSTIMER_PWM_CH;
+}
+
 // ****************************************************************************
 // Platform initialization
 #ifdef BUILD_UIP
-u32  platform_ethernet_setup(void);
+u32 platform_ethernet_setup( void );
 #endif
 
 extern int pm_configure_clocks( pm_freq_param_t *param );
@@ -65,32 +119,6 @@ static u32 platform_timer_set_clock( unsigned id, u32 clock );
 __attribute__((__interrupt__)) static void adc_int_handler();
 #endif
 
-// Virtual timers support
-#if VTMR_NUM_TIMERS > 0
-#define VTMR_CH     (2)
-
-__attribute__((__interrupt__)) static void tmr_int_handler()
-{
-  volatile avr32_tc_t *tc = &AVR32_TC;
-
-  tc_read_sr( tc, VTMR_CH );
-  cmn_virtual_timer_cb();
-
-#ifdef BUILD_MMCFS
-  disk_timerproc();
-#endif
-
-#ifdef BUILD_UIP
-  // Indicate that a SysTick interrupt has occurred.
-  eth_timer_fired = 1;
-
-  // Generate a fake Ethernet interrupt.  This will perform the actual work
-  // of incrementing the timers and taking the appropriate actions.
-  platform_eth_force_interrupt();
-#endif
-}                                
-#endif
-
 const u32 uart_base_addr[ ] = {
   AVR32_USART0_ADDRESS,
   AVR32_USART1_ADDRESS,
@@ -145,10 +173,12 @@ int platform_init()
   // Setup clocks
   if( PM_FREQ_STATUS_FAIL == pm_configure_clocks( &pm_freq_param ) )
     return PLATFORM_ERR;
+#ifdef FOSC32
   // Select the 32-kHz oscillator crystal
   pm_enable_osc32_crystal (&AVR32_PM );
   // Enable the 32-kHz clock
   pm_enable_clk32_no_wait( &AVR32_PM, AVR32_PM_OSCCTRL32_STARTUP_0_RCOSC );
+#endif
 
   // Initialize external memory if any.
 #ifdef AVR32_SDRAMC
@@ -168,47 +198,16 @@ int platform_init()
 #endif
   }
 
-  // Setup timer interrupt for the virtual timers if needed
-#if VTMR_NUM_TIMERS > 0
-  INTC_register_interrupt( &tmr_int_handler, AVR32_TC_IRQ2, AVR32_INTC_INT0 );
-  tmropt.waveform.wavsel = TC_WAVEFORM_SEL_UP_MODE_RC_TRIGGER;
-  tc_init_waveform( tc, VTMR_CH, &tmropt );
-  tc_interrupt_t tmrint =
-  {
-    0,              // External trigger interrupt.
-    0,              // RB load interrupt.
-    0,              // RA load interrupt.
-    1,              // RC compare interrupt.
-    0,              // RB compare interrupt.
-    0,              // RA compare interrupt.
-    0,              // Load overrun interrupt.
-    0               // Counter overflow interrupt.
-  };
-# ifdef FOSC32
-  tc_write_rc( tc, VTMR_CH, FOSC32 / VTMR_FREQ_HZ );
-# else
-  // Run VTMR from the slowest available PBA clock divisor
-  { u32 vt_clock_freq = platform_timer_set_clock( VTMR_CH, REQ_PBA_FREQ / 128 );
-    u32 div = vt_clock_freq / VTMR_FREQ_HZ;
-    if (div > 0xffff) div = 0xffff;
-    tc_write_rc( tc, VTMR_CH, div );
-  }
-# endif
-  tc_configure_interrupts( tc, VTMR_CH, &tmrint );
-  Enable_global_interrupt();
-  tc_start( tc, VTMR_CH );
-#endif
-
   // Setup spi controller(s) : up to 4 slave by controller.
 #if NUM_SPI > 0
   spi_master_options_t spiopt;
   spiopt.modfdis = TRUE;
   spiopt.pcs_decode = FALSE;
   spiopt.delay = 0;
-  spi_initMaster(&AVR32_SPI0, &spiopt, REQ_CPU_FREQ);
+  spi_initMaster(&AVR32_SPI0, &spiopt, REQ_PBA_FREQ);
 
 #if NUM_SPI > 4
-  spi_initMaster(&AVR32_SPI1, &spiopt, REQ_CPU_FREQ);
+  spi_initMaster(&AVR32_SPI1, &spiopt, REQ_PBA_FREQ);
 #endif
 
 #endif
@@ -225,7 +224,6 @@ int platform_init()
   pwm_init();
 #endif
 
-
 #ifdef BUILD_UIP
     platform_ethernet_setup();
 #endif
@@ -240,6 +238,19 @@ int platform_init()
   platform_pio_op( 0, ( pio_type )1 << 0 , PLATFORM_IO_PIN_PULLUP );
 #endif
 
+  // Setup system timer
+  // NOTE: this MUST come AFTER pwm_init!
+  cmn_systimer_set_base_freq( 1000000 );
+  cmn_systimer_set_interrupt_freq( 1 );
+  platform_systimer_init();
+
+  // Setup virtual timers if needed
+#if VTMR_NUM_TIMERS > 0
+#define VTMR_CH               2
+  platform_cpu_set_interrupt( INT_TMR_MATCH, VTMR_CH, PLATFORM_CPU_ENABLE );
+  platform_timer_set_match_int( VTMR_CH, 1000000 / VTMR_FREQ_HZ, PLATFORM_TIMER_INT_CYCLIC );
+#endif // #if VTMR_NUM_TIMERS > 0
+
   cmn_platform_init();
 
   // All done
@@ -249,104 +260,59 @@ int platform_init()
 // ****************************************************************************
 // PIO functions
 
-// Reg types for our helper function
-#define PIO_REG_PVR   0
-#define PIO_REG_OVR   1
-#define PIO_REG_GPER  2
-#define PIO_REG_ODER  3
-#define PIO_REG_PUER  4
-
-#define GPIO          AVR32_GPIO
-
-// Helper function: for a given port, return the address of a specific register (value, direction, pullup ...)
-static volatile unsigned long* platform_pio_get_port_reg_addr( unsigned port, int regtype )
-{
-  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[ port ];
-
-  switch( regtype )
-  {
-    case PIO_REG_PVR:
-      return ( unsigned long * )&gpio_port->pvr;
-    case PIO_REG_OVR:
-      return &gpio_port->ovr;
-    case PIO_REG_GPER:
-      return &gpio_port->gper;
-    case PIO_REG_ODER:
-      return &gpio_port->oder;
-    case PIO_REG_PUER:
-      return &gpio_port->puer;
-  }
-  // Should never get here
-  return ( unsigned long* )&gpio_port->pvr;
-}
-
-// Helper function: get port value, get direction, get pullup, ...
-static pio_type platform_pio_get_port_reg( unsigned port, int reg )
-{
-  volatile unsigned long *pv = platform_pio_get_port_reg_addr( port, reg );
-
-  return *pv;
-}
-
-// Helper function: set port value, set direction, set pullup ...
-static void platform_pio_set_port_reg( unsigned port, pio_type val, int reg )
-{
-  volatile unsigned long *pv = platform_pio_get_port_reg_addr( port, reg );
-
-  *pv = val;
-}
-
 pio_type platform_pio_op( unsigned port, pio_type pinmask, int op )
 {
   pio_type retval = 1;
 
+  // Pointer to the register set for this GPIO port
+  volatile avr32_gpio_port_t *gpio_regs = &AVR32_GPIO.port[ port ];
+
   switch( op )
   {
     case PLATFORM_IO_PORT_SET_VALUE:
-      platform_pio_set_port_reg( port, pinmask, PIO_REG_OVR );
+      gpio_regs->ovr = pinmask;
       break;
 
     case PLATFORM_IO_PIN_SET:
-      platform_pio_set_port_reg( port, platform_pio_get_port_reg( port, PIO_REG_OVR ) | pinmask, PIO_REG_OVR );
+      gpio_regs->ovrs = pinmask;
       break;
 
     case PLATFORM_IO_PIN_CLEAR:
-      platform_pio_set_port_reg( port, platform_pio_get_port_reg( port, PIO_REG_OVR ) & ~pinmask, PIO_REG_OVR );
+      gpio_regs->ovrc = pinmask;
       break;
 
     case PLATFORM_IO_PORT_DIR_INPUT:
       pinmask = 0xFFFFFFFF;
     case PLATFORM_IO_PIN_DIR_INPUT:
-      platform_pio_set_port_reg( port, platform_pio_get_port_reg( port, PIO_REG_ODER ) & ~pinmask, PIO_REG_ODER );
-      platform_pio_set_port_reg( port, platform_pio_get_port_reg( port, PIO_REG_GPER ) | pinmask, PIO_REG_GPER );
+      gpio_regs->oderc = pinmask;  // Disable output drivers
+      gpio_regs->gpers = pinmask;  // Make GPIO control this pin
       break;
 
     case PLATFORM_IO_PORT_DIR_OUTPUT:
       pinmask = 0xFFFFFFFF;
     case PLATFORM_IO_PIN_DIR_OUTPUT:
-      platform_pio_set_port_reg( port, platform_pio_get_port_reg( port, PIO_REG_ODER ) | pinmask, PIO_REG_ODER );
-      platform_pio_set_port_reg( port, platform_pio_get_port_reg( port, PIO_REG_GPER ) | pinmask, PIO_REG_GPER );
+      gpio_regs->oders = pinmask;  // Enable output drivers
+      gpio_regs->gpers = pinmask;  // Make GPIO control this pin
       break;
 
     case PLATFORM_IO_PORT_GET_VALUE:
-      retval = platform_pio_get_port_reg( port, PIO_REG_PVR );
+      retval = gpio_regs->pvr;
       break;
 
     case PLATFORM_IO_PIN_GET:
-      retval = platform_pio_get_port_reg( port, PIO_REG_PVR ) & pinmask ? 1 : 0;
+      retval = gpio_regs->pvr & pinmask ? 1 : 0;
       break;
 
     case PLATFORM_IO_PIN_PULLUP:
-      platform_pio_set_port_reg( port, platform_pio_get_port_reg( port, PIO_REG_PUER ) | pinmask, PIO_REG_PUER );
+      gpio_regs->puers = pinmask;
       break;
 
     case PLATFORM_IO_PIN_NOPULL:
-      platform_pio_set_port_reg( port, platform_pio_get_port_reg( port, PIO_REG_PUER ) & ~pinmask, PIO_REG_PUER );
+      gpio_regs->puerc = pinmask;
       break;
 
     default:
       retval = 0;
-      break;
   }
   return retval;
 }
@@ -436,7 +402,7 @@ void platform_s_uart_send( unsigned id, u8 data )
   pusart->thr = ( data << AVR32_USART_THR_TXCHR_OFFSET ) & AVR32_USART_THR_TXCHR_MASK;
 }
 
-int platform_s_uart_recv( unsigned id, s32 timeout )
+int platform_s_uart_recv( unsigned id, timer_data_type timeout )
 {
   volatile avr32_usart_t *pusart = ( volatile avr32_usart_t* )uart_base_addr[ id ];
   int temp;
@@ -517,7 +483,7 @@ int platform_s_uart_set_flow_control( unsigned id, int type )
       gpio_enable_module_pin( ppindata->pin, ppindata->function );
     else // release pin to GPIO module
     {
-      gpio_port = &GPIO.port[ ppindata->pin >> 5 ];
+      gpio_port = &AVR32_GPIO.port[ ppindata->pin >> 5 ];
       gpio_port->gpers = 1 << ( ppindata->pin & 0x1F );
     }
   return PLATFORM_OK;
@@ -527,6 +493,7 @@ int platform_s_uart_set_flow_control( unsigned id, int type )
 // Timer functions
 
 static const u16 clkdivs[] = { 0xFFFF, 2, 8, 32, 128 };
+u8 avr32_timer_int_periodic_flag[ 3 ];
 
 // Helper: get timer clock
 static u32 platform_timer_get_clock( unsigned id )
@@ -566,7 +533,7 @@ static u32 platform_timer_set_clock( unsigned id, u32 clock )
 #endif
 }
 
-void platform_s_timer_delay( unsigned id, u32 delay_us )
+void platform_s_timer_delay( unsigned id, timer_data_type delay_us )
 {
   volatile avr32_tc_t *tc = &AVR32_TC;
   u32 freq;
@@ -584,7 +551,7 @@ void platform_s_timer_delay( unsigned id, u32 delay_us )
   while( ( tc_read_tc( tc, id ) < final ) && !sr->covfs );
 }
 
-u32 platform_s_timer_op( unsigned id, int op, u32 data )
+timer_data_type platform_s_timer_op( unsigned id, int op, timer_data_type data )
 {
   u32 res = 0;
   volatile int i;
@@ -602,14 +569,6 @@ u32 platform_s_timer_op( unsigned id, int op, u32 data )
       res = tc_read_tc( tc, id );
       break;
 
-    case PLATFORM_TIMER_OP_GET_MAX_DELAY:
-      res = platform_timer_get_diff_us( id, 0, 0xFFFF );
-      break;
-
-    case PLATFORM_TIMER_OP_GET_MIN_DELAY:
-      res = platform_timer_get_diff_us( id, 0, 1 );
-      break;
-
     case PLATFORM_TIMER_OP_SET_CLOCK:
       res = platform_timer_set_clock( id, data );
       break;
@@ -617,13 +576,55 @@ u32 platform_s_timer_op( unsigned id, int op, u32 data )
     case PLATFORM_TIMER_OP_GET_CLOCK:
       res = platform_timer_get_clock( id );
       break;
+
+    case PLATFORM_TIMER_OP_GET_MAX_CNT:
+      res = 0xFFFF;
+      break;
   }
   return res;
 }
 
-int platform_s_timer_set_match_int( unsigned id, u32 period_us, int type )
+int platform_s_timer_set_match_int( unsigned id, timer_data_type period_us, int type )
 {
-  return PLATFORM_TIMER_INT_INVALID_ID;
+  volatile avr32_tc_t *tc = &AVR32_TC;
+  u32 final;
+
+  if( period_us == 0 )
+  {
+    tc->channel[ id ].CMR.waveform.wavsel = TC_WAVEFORM_SEL_UP_MODE;
+    return PLATFORM_TIMER_INT_OK;
+  }
+  final = ( u32 )( ( u64 )( platform_timer_get_clock( id ) * period_us ) / 1000000 );
+  if( final == 0 )
+    return PLATFORM_TIMER_INT_TOO_SHORT;
+  if( final > 0xFFFF )
+    return PLATFORM_TIMER_INT_TOO_LONG;
+  tc_stop( tc, id );
+  tc->channel[ id ].CMR.waveform.wavsel = TC_WAVEFORM_SEL_UP_MODE_RC_TRIGGER;
+  tc->channel[ id ].rc = final;
+  avr32_timer_int_periodic_flag[ id ] = type;
+  tc_start( tc, id );
+  return PLATFORM_TIMER_INT_OK;
+}
+
+u64 platform_timer_sys_raw_read()
+{
+  return AVR32_PWM.channel[ SYSTIMER_PWM_CH ].ccnt;
+}
+
+void platform_timer_sys_disable_int()
+{
+  AVR32_PWM.idr = 1 << SYSTIMER_PWM_CH;
+}
+
+void platform_timer_sys_enable_int()
+{
+  AVR32_PWM.ier = 1 << SYSTIMER_PWM_CH;
+}
+
+timer_data_type platform_timer_read_sys()
+{
+  return cmn_systimer_get();
 }
 
 // ****************************************************************************
@@ -670,14 +671,12 @@ u32 platform_spi_setup( unsigned id, int mode, u32 clock, unsigned cpol, unsigne
   opt.bits = min(databits, 16);
   opt.spck_delay = 0;
   opt.trans_delay = 0;
-  opt.mode = ((cpol & 1) << 1) | (cpha & 1);
+  opt.mode = (cpol << 1) | cpha;
 
   // Set actual interface
   gpio_enable_module(spi_pins + (id >> 2) * 4, 4);
-  spi_setupChipReg((volatile avr32_spi_t *) spireg[id >> 2], id % 4, &opt, REQ_CPU_FREQ);
-
-  // TODO: return the actual baudrate.
-  return clock;
+  return spi_setupChipReg((volatile avr32_spi_t *) spireg[id >> 2], id % 4,
+                          &opt, REQ_PBA_FREQ);
 }
 
 spi_data_type platform_spi_send_recv( unsigned id, spi_data_type data )
@@ -753,6 +752,8 @@ void platform_adc_stop( unsigned id )
   s->op_pending = 0;
   INACTIVATE_CHANNEL( d, id );
 
+  adc_disable( adc, s->id );
+
   // If there are no more active channels, stop the sequencer
   if( d->ch_active == 0 )
     d->running = 0;
@@ -781,7 +782,6 @@ int platform_adc_update_sequence( )
 
 __attribute__((__interrupt__)) static void adc_int_handler()
 {
-  int i;
   elua_adc_dev_state *d = adc_get_dev_state( 0 );
   elua_adc_ch_state *s;
 
@@ -795,9 +795,6 @@ __attribute__((__interrupt__)) static void adc_int_handler()
       d->sample_buf[ d->seq_ctr ] = ( u16 )adc_get_value(adc, s->id );
       s->value_fresh = 1;
 
-      // Read LCDR to signal that conversion has been captured
-      i = adc->lcdr;
-
       if ( s->logsmoothlen > 0 && s->smooth_ready == 0)
         adc_smooth_data( s->id );
 #if defined( BUF_ENABLE_ADC )
@@ -817,18 +814,14 @@ __attribute__((__interrupt__)) static void adc_int_handler()
   }
   d->seq_ctr = 0;
 
-  // Only attempt to refresh sequence order if still running
-  // This allows us to "cache" an old sequence if all channels
-  // finish at the same time
-  if ( d->running == 1 )
-    adc_update_dev_sequence( 0 );
+  adc_update_dev_sequence( 0 );
 
   if ( d->clocked == 0 && d->running == 1 )
     adc_start( adc );
 }
 
 
-u32 platform_adc_setclock( unsigned id, u32 frequency )
+u32 platform_adc_set_clock( unsigned id, u32 frequency )
 {
   return 0;
 }
@@ -864,15 +857,32 @@ int platform_adc_start_sequence( )
 # error "NUM_PWM > AVR32_PWM_CHANNEL_LENGTH"
 #endif
 
+#if NUM_PWM > 0
+
+// One PWM channel is used by the AVR32 system timer (look at the start of this
+// file for more information). Currently this channel is hardcoded in platform.c
+// (SYSTIMER_PWM_CH) to 6. If this is not convenient feel free to move the
+// definition of SYSTIMER_PWM_CH in platform_conf.h and select another PWM channel,
+// BUT remember to modify the below PWM pin mapping accordingly!
 static const gpio_map_t pwm_pins =
 {
-  { AVR32_PWM_0_PIN, AVR32_PWM_0_FUNCTION },
-  { AVR32_PWM_1_PIN, AVR32_PWM_1_FUNCTION },
-  { AVR32_PWM_2_PIN, AVR32_PWM_2_FUNCTION },
-  { AVR32_PWM_3_PIN, AVR32_PWM_3_FUNCTION },
-  { AVR32_PWM_4_1_PIN, AVR32_PWM_4_1_FUNCTION },	// PB27
-  { AVR32_PWM_5_1_PIN, AVR32_PWM_5_1_FUNCTION },	// PB28
-  { AVR32_PWM_6_PIN, AVR32_PWM_6_FUNCTION },
+#if ( BOARD == ATEVK1100 ) || ( BOARD == MIZAR32 )
+  { AVR32_PWM_0_PIN, AVR32_PWM_0_FUNCTION },      // PB19 - LED4
+  { AVR32_PWM_1_PIN, AVR32_PWM_1_FUNCTION },      // PB20 - LED5
+  { AVR32_PWM_2_PIN, AVR32_PWM_2_FUNCTION },	  // PB21 - LED6
+  { AVR32_PWM_3_PIN, AVR32_PWM_3_FUNCTION },      // PB22 - LED7
+  { AVR32_PWM_4_1_PIN, AVR32_PWM_4_1_FUNCTION },  // PB27 - LED0
+  { AVR32_PWM_5_1_PIN, AVR32_PWM_5_1_FUNCTION },  // PB28 - LED1
+//  { AVR32_PWM_6_PIN, AVR32_PWM_6_FUNCTION },      // PB18 - LCD_C / GPIO50
+#elif BOARD == ATEVK1101
+  { AVR32_PWM_0_0_PIN, AVR32_PWM_0_0_FUNCTION },  // PA7  LED0
+  { AVR32_PWM_1_0_PIN, AVR32_PWM_1_0_FUNCTION },  // PA8  LED1
+  { AVR32_PWM_2_0_PIN, AVR32_PWM_2_0_FUNCTION },  // PA21 LED2
+  { AVR32_PWM_3_0_PIN, AVR32_PWM_3_0_FUNCTION },  // PA14 ? or _1 PA25
+  { AVR32_PWM_4_1_PIN, AVR32_PWM_4_1_FUNCTION },  // PA28 - audio out
+  { AVR32_PWM_5_1_PIN, AVR32_PWM_5_1_FUNCTION },  // PB5: UART1-RTS & Nexus i/f EVTIn / _0 PA18=Xin0
+//  { AVR32_PWM_6_0_PIN, AVR32_PWM_6_0_FUNCTION },  // PA22 - LED3 and audio out
+#endif
 };
 
 
@@ -899,27 +909,22 @@ u32 platform_pwm_setup( unsigned id, u32 frequency, unsigned duty )
   //
   // PWM output wave frequency is requested in Hz but programmed as a
   // number of cycles of the master PWM clock frequency.
-  // The obvious but simple formulae to convert between these values:
-  // channel_period = pwmclk / frequency; return pwmclk / channel_period;
-  // return the same values as requested from 1 to just over sqrt(pwmclk)
-  // (up to 1031 for 1000000 Hz).
-  // In reality, they always set a frequency <= the one requested.
-  // A better formula would program the geometrically closest available
-  // actual frequency and return the geometrically closest integer frequency
-  // to that.
-  // Unfortunately we mustn't use floating point because that would pull
-  // the whole FP subsystem into the integer-only executable.
+  //
+  // Here, we use rounding to select the numerically closest available
+  // frequency and return the closest integer in Hz to that.
 
-  period = pwmclk / frequency;
-  duty_cycle = (period * duty) / 100;
+  period = (pwmclk + frequency/2) / frequency;
+  if (period == 0) period = 1;
+  if (period >= 1<<20) period = (1<<20) - 1;
+  duty_cycle = (period * duty + 50) / 100;
 
   // The AVR32 PWM duty cycle is upside down:
   // duty_period==0 gives an all-active output, while
   // duty_period==period gives an all-inactive output.
+  // So we invert the cuty cycle here.
   pwm_channel_set_period_and_duty_cycle( id, period, period - duty_cycle );
 
-  return pwmclk / period;    // Inaccurate. We Should return the nearest int.
-                             // TODO: Try (pwmclk + period/2) / period
+  return (pwmclk + period/2) / period;
 }
 
 /*
@@ -930,18 +935,18 @@ u32 platform_pwm_setup( unsigned id, u32 frequency, unsigned duty )
  * If the configuration cannot be met (because freq is too high), set the
  * maximum frequency possible.
  *
- * The algorithm is too simple: the actual frequency is always <= the one
- * requested, not the closest possible.
+ * The algorithm is too simple: the actual clock frequency is always >=
+ * the one requested, not the closest possible.
  */
-static void find_clock_configuration( u32 frequency,
-                                      unsigned *pre, unsigned *div )
+static void pwm_find_clock_configuration( u32 frequency,
+                                          unsigned *pre, unsigned *div )
 {
   // prescalers[11] = { 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024 };
 #define prescalers( n ) ( 1 << n )
   const unsigned nprescalers = 11;
 
-  unsigned prescaler;       // Select a prescaler
-  unsigned divisor = 0;
+  unsigned prescaler;	// Which of the prescalers are we considering?
+  unsigned divisor;
 
   if ( frequency > REQ_PBA_FREQ )
   {
@@ -951,6 +956,7 @@ static void find_clock_configuration( u32 frequency,
   }
 
   // Find prescaler and divisor values
+  prescaler = 0;
   do
     divisor = REQ_PBA_FREQ / ( prescalers( prescaler ) * frequency );
   while ( ( divisor > 255 ) && ( ++prescaler < nprescalers ) );
@@ -970,122 +976,212 @@ static void find_clock_configuration( u32 frequency,
 }
 #undef prescalers
 
-
-static u32 pwm_set_clock_freq( u32 freq )
+u32 platform_pwm_set_clock( unsigned id, u32 freq )
 {
   unsigned pre, div;
 
-  find_clock_configuration( freq, &pre, &div );
+  pwm_find_clock_configuration( freq, &pre, &div );
   pwm_set_linear_divider( pre, div );
 
   return pwm_get_clock_freq();
 }
 
-u32 platform_pwm_op( unsigned id, int op, u32 data)
+u32 platform_pwm_get_clock( unsigned id )
 {
-  // Sanity check
-  if (id < 0 || id >= NUM_PWM)
-    return 0;
-
-  switch( op )
-  {
-    case PLATFORM_PWM_OP_SET_CLOCK:
-      return pwm_set_clock_freq( data );
-
-    case PLATFORM_PWM_OP_GET_CLOCK:
-      return pwm_get_clock_freq();
-
-    case PLATFORM_PWM_OP_START:
-      pwm_channel_start( id );
-      break;
-
-    case PLATFORM_PWM_OP_STOP:
-      pwm_channel_stop( id );
-      break;
-  }
-  return 0;
+  return pwm_get_clock_freq();
 }
 
+void platform_pwm_start( unsigned id )
+{
+  pwm_channel_start( id );
+}
+
+void platform_pwm_stop( unsigned id )
+{
+  pwm_channel_stop( id );
+}
+
+#endif // #if NUM_PWM > 0
+
+// ****************************************************************************
+// I2C support
+
+u32 platform_i2c_setup( unsigned id, u32 speed )
+{
+  return i2c_setup(speed);
+}
+
+void platform_i2c_send_start( unsigned id )
+{
+  i2c_start_cond();
+}
+
+void platform_i2c_send_stop( unsigned id )
+{
+  i2c_stop_cond();
+}
+
+int platform_i2c_send_address( unsigned id, u16 address, int direction )
+{
+  // Convert enum codes to R/w bit value.
+  // If TX == 0 and RX == 1, this test will be removed by the compiler
+  if ( ! ( PLATFORM_I2C_DIRECTION_TRANSMITTER == 0 &&
+           PLATFORM_I2C_DIRECTION_RECEIVER == 1 ) ) {
+    direction = ( direction == PLATFORM_I2C_DIRECTION_TRANSMITTER ) ? 0 : 1;
+  }
+
+  // Low-level returns nack (0=acked); we return ack (1=acked).
+  return ! i2c_write_byte( (address << 1) | direction );
+}
+
+int platform_i2c_send_byte( unsigned id, u8 data )
+{
+  // Low-level returns nack (0=acked); we return ack (1=acked).
+  return ! i2c_write_byte( data );
+}
+
+int platform_i2c_recv_byte( unsigned id, int ack )
+{
+  return i2c_read_byte( !ack );
+}
+
+
 // ****************************************************************************
 // Network support
 
 #ifdef BUILD_UIP
 static const gpio_map_t MACB_GPIO_MAP =
 {
-  {AVR32_MACB_MDC_0_PIN,    AVR32_MACB_MDC_0_FUNCTION   },
-  {AVR32_MACB_MDIO_0_PIN,   AVR32_MACB_MDIO_0_FUNCTION  },
-  {AVR32_MACB_RXD_0_PIN,    AVR32_MACB_RXD_0_FUNCTION   },
-  {AVR32_MACB_TXD_0_PIN,    AVR32_MACB_TXD_0_FUNCTION   },
-  {AVR32_MACB_RXD_1_PIN,    AVR32_MACB_RXD_1_FUNCTION   },
-  {AVR32_MACB_TXD_1_PIN,    AVR32_MACB_TXD_1_FUNCTION   },
-  {AVR32_MACB_TX_EN_0_PIN,  AVR32_MACB_TX_EN_0_FUNCTION },
-  {AVR32_MACB_RX_ER_0_PIN,  AVR32_MACB_RX_ER_0_FUNCTION },
-  {AVR32_MACB_RX_DV_0_PIN,  AVR32_MACB_RX_DV_0_FUNCTION },
-  {AVR32_MACB_TX_CLK_0_PIN, AVR32_MACB_TX_CLK_0_FUNCTION}
+  { AVR32_MACB_MDC_0_PIN,    AVR32_MACB_MDC_0_FUNCTION    },
+  { AVR32_MACB_MDIO_0_PIN,   AVR32_MACB_MDIO_0_FUNCTION   },
+  { AVR32_MACB_RXD_0_PIN,    AVR32_MACB_RXD_0_FUNCTION    },
+  { AVR32_MACB_TXD_0_PIN,    AVR32_MACB_TXD_0_FUNCTION    },
+  { AVR32_MACB_RXD_1_PIN,    AVR32_MACB_RXD_1_FUNCTION    },
+  { AVR32_MACB_TXD_1_PIN,    AVR32_MACB_TXD_1_FUNCTION    },
+  { AVR32_MACB_TX_EN_0_PIN,  AVR32_MACB_TX_EN_0_FUNCTION  },
+  { AVR32_MACB_RX_ER_0_PIN,  AVR32_MACB_RX_ER_0_FUNCTION  },
+  { AVR32_MACB_RX_DV_0_PIN,  AVR32_MACB_RX_DV_0_FUNCTION  },
+  { AVR32_MACB_TX_CLK_0_PIN, AVR32_MACB_TX_CLK_0_FUNCTION },
 };
 
-u32  platform_ethernet_setup()
+u32 platform_ethernet_setup()
 {
-	  static struct uip_eth_addr sTempAddr;
-	  // Assign GPIO to MACB
-	  gpio_enable_module(MACB_GPIO_MAP, sizeof(MACB_GPIO_MAP) / sizeof(MACB_GPIO_MAP[0]));
+  static struct uip_eth_addr sTempAddr = {
+    .addr[0] = ETHERNET_CONF_ETHADDR0,
+    .addr[1] = ETHERNET_CONF_ETHADDR1,
+    .addr[2] = ETHERNET_CONF_ETHADDR2,
+    .addr[3] = ETHERNET_CONF_ETHADDR3,
+    .addr[4] = ETHERNET_CONF_ETHADDR4,
+    .addr[5] = ETHERNET_CONF_ETHADDR5,
+  };
 
-	  // initialize MACB & Phy Layers
-	  if (xMACBInit(&AVR32_MACB) == FALSE ) {
-		  return PLATFORM_ERR;
-	  }
+  // Assign GPIO to MACB
+  gpio_enable_module( MACB_GPIO_MAP, sizeof(MACB_GPIO_MAP ) / sizeof( MACB_GPIO_MAP[0] ) );
 
-	  sTempAddr.addr[0] = ETHERNET_CONF_ETHADDR0;
-	  sTempAddr.addr[1] = ETHERNET_CONF_ETHADDR1;
-	  sTempAddr.addr[2] = ETHERNET_CONF_ETHADDR2;
-	  sTempAddr.addr[3] = ETHERNET_CONF_ETHADDR3;
-	  sTempAddr.addr[4] = ETHERNET_CONF_ETHADDR4;
-	  sTempAddr.addr[5] = ETHERNET_CONF_ETHADDR5;
+  // initialize MACB & Phy Layers
+  if ( xMACBInit( &AVR32_MACB ) == FALSE ) {
+    return PLATFORM_ERR;
+  }
 
-	  // Initialize the eLua uIP layer
-   elua_uip_init( &sTempAddr );
-   return PLATFORM_OK;
-}  
+  // Initialize the eLua uIP layer
+  elua_uip_init( &sTempAddr );
+  return PLATFORM_OK;
+}
 
 void platform_eth_send_packet( const void* src, u32 size )
 {
-   lMACBSend(&AVR32_MACB,src, size, TRUE);
+  lMACBSend( &AVR32_MACB,src, size, TRUE );
 }
 
 u32 platform_eth_get_packet_nb( void* buf, u32 maxlen )
 {
-	u32    len;
+  u32 len;
 
-    /* Obtain the size of the packet. */
-    len = ulMACBInputLength();
+  /* Obtain the size of the packet. */
+  len = ulMACBInputLength();
 
-    if (len > maxlen) {
-    	return 0;
-    }
+  if( len > maxlen ) {
+    return 0;
+  }
 
-    if( len ) {
-        /* Let the driver know we are going to read a new packet. */
-    	vMACBRead( NULL, 0, len );
-    	vMACBRead( buf, len, len );
-    }
+  if( len ) {
+    /* Let the driver know we are going to read a new packet. */
+    vMACBRead( NULL, 0, len );
+    vMACBRead( buf, len, len );
+  }
 
- return len;
+  return len;
 }
 
 void platform_eth_force_interrupt()
 {
-    elua_uip_mainloop();
+  elua_uip_mainloop();
 }
 
 u32 platform_eth_get_elapsed_time()
 {
-    if( eth_timer_fired )
-    {
-      eth_timer_fired = 0;
-      return SYSTICKMS;
-    }
-    else
-      return 0;
+  if( eth_timer_fired )
+  {
+    eth_timer_fired = 0;
+    return SYSTICKMS;
+  }
+  else
+    return 0;
 }
 
+void platform_eth_timer_handler()
+{
+  // Indicate that a SysTick interrupt has occurred.
+  eth_timer_fired = 1;
+
+  // Generate a fake Ethernet interrupt.  This will perform the actual work
+  // of incrementing the timers and taking the appropriate actions.
+  platform_eth_force_interrupt();
+}
+
+#else // #ifdef BUILD_UIP
+
+void platform_eth_timer_handler()
+{
+}
+
+#endif // #ifdef BUILD_UIP
+
+// ****************************************************************************
+// Platform specific modules go here
+
+#ifdef PS_LIB_TABLE_NAME
+
+#define MIN_OPT_LEVEL 2
+#include "lua.h"
+#include "lauxlib.h"
+#include "lrotable.h"
+#include "lrodefs.h"
+
+extern const LUA_REG_TYPE lcd_map[];
+
+const LUA_REG_TYPE platform_map[] =
+{
+#if LUA_OPTIMIZE_MEMORY > 0
+  { LSTRKEY( "lcd" ), LROVAL( lcd_map ) },
 #endif
+  { LNILKEY, LNILVAL }
+};
+
+LUALIB_API int luaopen_platform( lua_State *L )
+{
+#if LUA_OPTIMIZE_MEMORY > 0
+  return 0;
+#else // #if LUA_OPTIMIZE_MEMORY > 0
+  luaL_register( L, PS_LIB_TABLE_NAME, platform_map );
+
+  // Setup the new tables inside platform table
+  lua_newtable( L );
+  luaL_register( L, NULL, lcd_map );
+  lua_setfield( L, -2, "lcd" );
+
+  return 1;
+#endif // #if LUA_OPTIMIZE_MEMORY > 0
+}
+
+#endif // #ifdef PS_LIB_TABLE_NAME
diff --git a/src/platform/avr32/platform_conf.h b/src/platform/avr32/platform_conf.h
index 3583a0b4..8eb4e962 100644
--- a/src/platform/avr32/platform_conf.h
+++ b/src/platform/avr32/platform_conf.h
@@ -6,6 +6,9 @@
 #include "auxmods.h"
 #include "board.h"
 #include "stacks.h"
+#include "elua_int.h"
+
+#define PLATFORM_HAS_SYSTIMER
 
 #if BOARD == EVK1100
     #include "EVK1100/evk1100_conf.h"
@@ -17,4 +20,22 @@
     #error No known AVR32 board defined    
 #endif
 
+// Common parts
+
+// Interrupt queue size
+#define PLATFORM_INT_QUEUE_LOG_SIZE 5
+
+// Interrupt list
+#define INT_UART_RX           ELUA_INT_FIRST_ID
+#define INT_TMR_MATCH         ( ELUA_INT_FIRST_ID + 1 )
+#define INT_GPIO_POSEDGE      ( ELUA_INT_FIRST_ID + 2 )
+#define INT_GPIO_NEGEDGE      ( ELUA_INT_FIRST_ID + 3 )
+#define INT_ELUA_LAST         INT_GPIO_NEGEDGE
+
+#define PLATFORM_CPU_CONSTANTS\
+ _C( INT_UART_RX ),\
+ _C( INT_TMR_MATCH ),\
+ _C( INT_GPIO_POSEDGE ),\
+ _C( INT_GPIO_NEGEDGE )
+
 #endif // #ifndef __PLATFORM_CONF_H__
diff --git a/src/platform/avr32/platform_int.c b/src/platform/avr32/platform_int.c
index 7bb06016..3da928e5 100644
--- a/src/platform/avr32/platform_int.c
+++ b/src/platform/avr32/platform_int.c
@@ -12,6 +12,8 @@
 #include 
 #include "usart.h"
 #include "intc.h"
+#include "tc.h"
+#include "gpio.h"
 
 // ****************************************************************************
 // Interrupt handlers
@@ -56,6 +58,130 @@ __attribute__((__interrupt__)) static void uart3_rx_handler()
   uart_common_rx_handler( 3 );
 }
 
+// ----------------------------------------------------------------------------
+// TMR_MATCH interrupts
+
+#ifndef VTMR_CH
+  #if VTMR_NUM_TIMERS > 0 
+  #define VTMR_CH     (2)
+  #else // #if VTMR_NUM_TIMERS > 0 
+  #define VTMR_CH     0xFFFF
+  #endif // #if VTMR_NUM_TIMERS > 0 
+#endif // #ifndef VTMR_CH
+
+extern void platform_eth_timer_handler();
+static const int tmr_irqs[] = { AVR32_TC_IRQ0, AVR32_TC_IRQ1, AVR32_TC_IRQ2 };
+extern u8 avr32_timer_int_periodic_flag[ 3 ];
+
+static void tmr_match_common_handler( int id )
+{
+  volatile avr32_tc_t *tc = &AVR32_TC;
+
+  tc_read_sr( tc, id ); // clear interrupt
+  if( id == VTMR_CH )
+  {
+    cmn_virtual_timer_cb();
+    platform_eth_timer_handler();
+  }
+  else
+    cmn_int_handler( INT_TMR_MATCH, id );
+  if( avr32_timer_int_periodic_flag[ id ] != PLATFORM_TIMER_INT_CYCLIC )
+  {
+    tc->channel[ id ].IDR.cpcs = 1;
+    tc->channel[ id ].CMR.waveform.wavsel = TC_WAVEFORM_SEL_UP_MODE;
+  }
+}
+
+__attribute__((__interrupt__)) static void tmr0_int_handler()
+{
+  tmr_match_common_handler( 0 );
+}
+
+__attribute__((__interrupt__)) static void tmr1_int_handler()
+{
+  tmr_match_common_handler( 1 );
+}
+
+__attribute__((__interrupt__)) static void tmr2_int_handler()
+{
+  tmr_match_common_handler( 2 );
+}
+
+// ----------------------------------------------------------------------------
+// GPIO interrupts and helpers
+
+// AVR32 has a special "pin change" interrupt mode. eLua doesn't have this 
+// interrupt, so we'll enable it when both POSEDGE and NEGEDGE for a pin are
+// enabled. To do this, we must keep the individual per-pin status of POSEDGE
+// and NEGEDGE in the arrays below.
+
+#define AVR32_NUM_PORTS       ( ( AVR32_NUM_GPIO + 31 ) >> 5 )
+static u32 gpio_posedge_status[ AVR32_NUM_PORTS ];
+static u32 gpio_negedge_status[ AVR32_NUM_PORTS ];
+
+static void gpioh_set_interrupt( elua_int_resnum resnum )
+{
+  u8 port = resnum >> 5, pin = resnum & 0x1F;
+  u32 posedge_mask = gpio_posedge_status[ port ] & ( 1 << pin );
+  u32 negedge_mask = gpio_negedge_status[ port ] & ( 1 << pin );
+
+  if( posedge_mask && negedge_mask )
+    gpio_enable_pin_interrupt( resnum, GPIO_PIN_CHANGE );
+  else if( posedge_mask )
+    gpio_enable_pin_interrupt( resnum, GPIO_RISING_EDGE );
+  else if( negedge_mask )
+    gpio_enable_pin_interrupt( resnum, GPIO_FALLING_EDGE );
+  else
+    gpio_disable_pin_interrupt( resnum );
+}
+
+/* Now for the interrupt handlers ... a bit weird, but easy to follow. The manual
+has this to say: "In every port there are four interrupt lines connected to the 
+interrupt controller. Every eigth interrupts in the port are ORed together to form 
+an interrupt line.". So we have an IRQ for each group of 8 consecutive GPIO pins.
+We could use a single interrupt handler and scan through all pins to see which one
+generated the interrupt, but it would take a lot of time for 109 pins. Instead,
+we use all the interrupts that the system can provide and we point them to a single
+handler; with the proper arguments, it needs to scan only 8 GPIO pins. */
+
+static void gpio_int_common_handler( int resnum )
+{
+  int i;
+
+  for( i = 0; i < 8; i ++, resnum ++ )
+    if( gpio_get_pin_interrupt_flag( resnum ) )
+    {
+      if( gpio_get_pin_value( resnum ) )
+        cmn_int_handler( INT_GPIO_POSEDGE, resnum );
+      else
+        cmn_int_handler( INT_GPIO_NEGEDGE, resnum );
+      gpio_clear_pin_interrupt_flag( resnum );
+    }
+}
+
+#define DEFINE_GPIO_HANDLER( num )\
+  __attribute__((__interrupt__)) static void gpio_irq##num##_handler ()\
+  {\
+    gpio_int_common_handler( num << 3 );\
+  }
+
+DEFINE_GPIO_HANDLER( 0 )
+DEFINE_GPIO_HANDLER( 1 )
+DEFINE_GPIO_HANDLER( 2 )
+DEFINE_GPIO_HANDLER( 3 )
+DEFINE_GPIO_HANDLER( 4 )
+DEFINE_GPIO_HANDLER( 5 )
+#if AVR32_NUM_GPIO > 44 // not an UC3B, asume 109 pins, thus 14 IRQs
+DEFINE_GPIO_HANDLER( 6 )
+DEFINE_GPIO_HANDLER( 7 )
+DEFINE_GPIO_HANDLER( 8 )
+DEFINE_GPIO_HANDLER( 9 )
+DEFINE_GPIO_HANDLER( 10 )
+DEFINE_GPIO_HANDLER( 11 )
+DEFINE_GPIO_HANDLER( 12 )
+DEFINE_GPIO_HANDLER( 13 )
+#endif // #if AVR32_NUM_GPIO > 44
+
 // ****************************************************************************
 // Interrupt: INT_UART_RX
 
@@ -86,11 +212,116 @@ static int int_uart_rx_get_flag( elua_int_resnum resnum, int clear )
   return ( pusart->csr & AVR32_USART_CSR_RXRDY_MASK ) ? 1 : 0;
 }
 
+// ****************************************************************************
+// Interrupt: INT_TMR_MATCH
+
+static int int_tmr_match_get_status( elua_int_resnum resnum )
+{
+  volatile avr32_tc_channel_t *pch = AVR32_TC.channel + resnum;
+
+  return pch->IMR.cpcs;
+}
+
+static int int_tmr_match_set_status( elua_int_resnum resnum, int status )
+{
+  volatile avr32_tc_channel_t *pch = AVR32_TC.channel + resnum;
+  int previous = pch->IMR.cpcs;
+
+  if( status == PLATFORM_CPU_ENABLE )
+    pch->IER.cpcs = 1;
+  else
+    pch->IDR.cpcs = 1;
+  return previous;
+}
+
+static int int_tmr_match_get_flag( elua_int_resnum resnum, int clear )
+{
+  volatile avr32_tc_channel_t *pch = AVR32_TC.channel + resnum;
+
+  ( void )clear; // reading the status register will automatically clear the interrupt flag
+  return pch->SR.cpcs;
+}
+
+// ****************************************************************************
+// Interrupt: INT_GPIO_POSEDGE
+
+static int int_gpio_posedge_get_status( elua_int_resnum resnum )
+{
+  u8 port = resnum >> 5, pin = resnum & 0x1F;
+
+  return ( gpio_posedge_status[ port ] & ( 1 << pin ) ) != 0;
+}
+
+static int int_gpio_posedge_set_status( elua_int_resnum resnum, int status )
+{
+  u8 port = resnum >> 5, pin = resnum & 0x1F;
+  int prev = int_gpio_posedge_get_status( resnum );
+
+  if( status == PLATFORM_CPU_ENABLE )
+    gpio_posedge_status[ port ] |= 1 << pin;
+  else
+    gpio_posedge_status[ port ] &= ~( 1 << pin );
+  gpioh_set_interrupt( resnum );
+  return prev;
+}
+
+static int int_gpio_posedge_get_flag( elua_int_resnum resnum, int clear )
+{
+  if( !int_gpio_posedge_get_status( resnum ) )
+    return 0;
+  int status = gpio_get_pin_interrupt_flag( resnum );
+
+  if( clear )
+    gpio_clear_pin_interrupt_flag( resnum );
+  return status;
+}
+
+// ****************************************************************************
+// Interrupt: INT_GPIO_NEGEDGE
+
+static int int_gpio_negedge_get_status( elua_int_resnum resnum )
+{
+  u8 port = resnum >> 5, pin = resnum & 0x1F;
+
+  return ( gpio_negedge_status[ port ] & ( 1 << pin ) ) != 0;
+}
+
+static int int_gpio_negedge_set_status( elua_int_resnum resnum, int status )
+{
+  u8 port = resnum >> 5, pin = resnum & 0x1F;
+  int prev = int_gpio_negedge_get_status( resnum );
+
+  if( status == PLATFORM_CPU_ENABLE )
+    gpio_negedge_status[ port ] |= 1 << pin;
+  else
+    gpio_negedge_status[ port ] &= ~( 1 << pin );
+  gpioh_set_interrupt( resnum );
+  return prev;
+}
+
+static int int_gpio_negedge_get_flag( elua_int_resnum resnum, int clear )
+{
+  if( !int_gpio_negedge_get_status( resnum ) )
+    return 0;
+  int status = gpio_get_pin_interrupt_flag( resnum );
+
+  if( clear )
+    gpio_clear_pin_interrupt_flag( resnum );
+  return status;
+}
+
 // ****************************************************************************
 // Interrupt initialization
 
 typedef void ( *phandler )();
-static const phandler phandlers[] = { uart0_rx_handler, uart1_rx_handler, uart2_rx_handler, uart3_rx_handler };
+static const phandler phandlers_usart[] = { uart0_rx_handler, uart1_rx_handler, uart2_rx_handler, uart3_rx_handler };
+static const phandler phandlers_tmr[] = { tmr0_int_handler, tmr1_int_handler, tmr2_int_handler };
+#if AVR32_NUM_GPIO == 44 // UC3B - 44 pins
+static const phandler phandlers_gpio[] = { gpio_irq0_handler, gpio_irq1_handler, gpio_irq2_handler, gpio_irq3_handler, gpio_irq4_handler, gpio_irq5_handler };
+#else // UC3A - 109 pins
+static const phandler phandlers_gpio[] = { gpio_irq0_handler, gpio_irq1_handler, gpio_irq2_handler, gpio_irq3_handler, gpio_irq4_handler, gpio_irq5_handler,
+  gpio_irq6_handler, gpio_irq7_handler, gpio_irq8_handler, gpio_irq9_handler, gpio_irq10_handler, gpio_irq11_handler, gpio_irq12_handler, gpio_irq13_handler };
+#endif
 
 void platform_int_init()
 {
@@ -98,7 +329,11 @@ void platform_int_init()
   
   for( i = 0; i < NUM_UART; i ++ )
     if( usart_irqs[ i ] != -1 )
-      INTC_register_interrupt( phandlers[ i ], usart_irqs[ i ], AVR32_INTC_INT0 );   
+      INTC_register_interrupt( phandlers_usart[ i ], usart_irqs[ i ], AVR32_INTC_INT0 );   
+  for( i = 0; i < sizeof( phandlers_tmr ) / sizeof( phandler ); i ++ )
+    INTC_register_interrupt( phandlers_tmr[ i ], tmr_irqs[ i ], AVR32_INTC_INT0 );
+  for( i = 0; i < sizeof( phandlers_gpio ) / sizeof( phandler ); i ++ )
+    INTC_register_interrupt( phandlers_gpio[ i ], AVR32_GPIO_IRQ_0 + i, AVR32_INTC_INT0 );
   Enable_global_interrupt();   
 }
 
@@ -108,7 +343,11 @@ void platform_int_init()
 
 const elua_int_descriptor elua_int_table[ INT_ELUA_LAST ] = 
 {
-  { int_uart_rx_set_status, int_uart_rx_get_status, int_uart_rx_get_flag }
+  { int_uart_rx_set_status, int_uart_rx_get_status, int_uart_rx_get_flag },
+  { int_tmr_match_set_status, int_tmr_match_get_status, int_tmr_match_get_flag },
+  { int_gpio_posedge_set_status, int_gpio_posedge_get_status, int_gpio_posedge_get_flag },
+  { int_gpio_negedge_set_status, int_gpio_negedge_get_status, int_gpio_negedge_get_flag }
 };
 
 #endif // #if defined( BUILD_C_INT_HANDLERS ) || defined( BUILD_LUA_INT_HANDLERS )
+
diff --git a/src/platform/avr32/pm_conf_clocks.c b/src/platform/avr32/pm_conf_clocks.c
index ed350d28..e98e122b 100644
--- a/src/platform/avr32/pm_conf_clocks.c
+++ b/src/platform/avr32/pm_conf_clocks.c
@@ -259,16 +259,18 @@ void pm_configure_usb_clock(void)
   pm_gc_enable(&AVR32_PM, AVR32_PM_GCLK_USBB);
 #else
   // Use 12MHz from OSC0 and generate 96 MHz
-  pm_pll_setup(&AVR32_PM, 1,  // pll.
-	  7,   // mul.
-	  1,   // div.
-	  0,   // osc.
-	  16); // lockcount.
+  pm_pll_setup(&AVR32_PM,
+               1,  // pll.
+               7,   // mul.
+               1,   // div.
+               0,   // osc.
+               16); // lockcount.
 
-  pm_pll_set_option(&AVR32_PM, 1, // pll.
-	  1,  // pll_freq: choose the range 80-180MHz.
-	  1,  // pll_div2.
-	  0); // pll_wbwdisable.
+  pm_pll_set_option(&AVR32_PM,
+                    1, // pll.
+                    1,  // pll_freq: choose the range 80-180MHz.
+                    1,  // pll_div2.
+                    0); // pll_wbwdisable.
 
   // start PLL1 and wait forl lock
   pm_pll_enable(&AVR32_PM, 1);
diff --git a/src/platform/avr32/pwm.c b/src/platform/avr32/pwm.c
index cea18e1c..000ccd1a 100644
--- a/src/platform/avr32/pwm.c
+++ b/src/platform/avr32/pwm.c
@@ -5,7 +5,7 @@
  */
 
 #include "pwm.h"
-#include "platform_conf.h"	// for REQ_PBA_FREQ
+#include "platform_conf.h"    // for REQ_PBA_FREQ
 
 /*
  * The AVR32 has 7 PWM channels, each of which chooses its clock from
@@ -91,7 +91,7 @@ void pwm_set_linear_divider( unsigned prea, unsigned diva )
 
   mr.prea = prea;
   mr.diva = diva;
-  mr.preb = 0;		// Turn clock B off
+  mr.preb = 0;             // Turn clock B off
   mr.divb = 0;
   AVR32_PWM.MR = mr;
 }
@@ -107,9 +107,9 @@ u32 pwm_get_clock_freq( void )
   if (divisor == 0)
   {
     // This clock is turned off. A frequency of 0 should surprise them.
-    return 0;   
+    return 0;
   }
-  
+
   return REQ_PBA_FREQ / ( ( 1< cycle_period is not allowed by the hardware.
- * 
+ *
  * - To know when one value has been flushed to its register, you have to
  *   enable the per-channel PWM interrupt, clear its status flag and wait until
  *   that interrupt status flag goes high, which happens at the end of each
@@ -208,16 +208,14 @@ void pwm_channel_set_period_and_duty_cycle( unsigned id, u32 period, u32 duty )
     }
   }
 #else
-  // No nasty interrupts: just disable, configure and re-enable.
-  // In practice, it seems you don't even need to disable the channel
-  // like the User's Guide tells you to, so we don't bother.
+  // No nasty asynchronous stuff. just disable, configure and re-enable.
   {
-    //int was_enabled = AVR32_PWM.sr & (1 << id);
+    int was_enabled = AVR32_PWM.sr & (1 << id);
 
-    //if (was_enabled) AVR32_PWM.dis = 1 << id;
+    if (was_enabled) AVR32_PWM.dis = 1 << id;
     AVR32_PWM.channel[id].cprd = period;
     AVR32_PWM.channel[id].cdty = duty;
-    //if (was_enabled) AVR32_PWM.ena = 1 << id;
+    if (was_enabled) AVR32_PWM.ena = 1 << id;
   }
 #endif
 }
@@ -236,8 +234,8 @@ static void pwm_channel_set_period( unsigned id, u32 period )
 
   // Select updating of the period and write into the update register
   AVR32_PWM.channel[id].CMR.cpd = AVR32_PWM_CMR_CPD_UPDATE_CPRD;
-  update_has_flushed &= ~(1 << id);	// The update hasn't happened yet...
-  AVR32_PWM.channel[id].cupd = period;	// Schedule the update to be performed
+  update_has_flushed &= ~(1 << id);     // The update hasn't happened yet...
+  AVR32_PWM.channel[id].cupd = period;  // Schedule the update to be performed
 }
 
 static void pwm_channel_set_duty_cycle( unsigned id, u32 duty )
diff --git a/src/platform/avr32/pwm.h b/src/platform/avr32/pwm.h
index aa515b76..fb5aaf4c 100644
--- a/src/platform/avr32/pwm.h
+++ b/src/platform/avr32/pwm.h
@@ -4,7 +4,7 @@
  *      Martin Guy , March 2011
  */
 
-#include "platform.h"	// for u32
+#include "platform.h"   // for u32
 
 // Initialize the PWM system, called at startup
 void pwm_init( void );
diff --git a/src/platform/avr32/spi.c b/src/platform/avr32/spi.c
index 5fa559cf..329d1954 100644
--- a/src/platform/avr32/spi.c
+++ b/src/platform/avr32/spi.c
@@ -72,18 +72,6 @@ typedef union
   avr32_spi_csr0_t              CSR;
 } u_avr32_spi_csr_t;
 //! @}
-
-/*-----------------------------------------------------------*/
-static int getBaudDiv(const spi_options_t *options, U32 pba_hz)
-{
-  int baudDiv = (pba_hz + options->baudrate / 2) / options->baudrate;
-
-  if (baudDiv <= 0 || baudDiv > 255) {
-    return -1;
-  }
-
-  return baudDiv;
-}
 /*-----------------------------------------------------------*/
 void spi_reset(volatile avr32_spi_t *spi)
 {
@@ -98,14 +86,15 @@ int spi_initMaster(volatile avr32_spi_t *spi, const spi_master_options_t *opt, U
   spi->cr = AVR32_SPI_CR_SWRST_MASK;
 
   // Master Mode.
+  // The mode register's reset state is all 0s, so omit 0 values.
   u_avr32_spi_mr.mr = spi->mr;
   u_avr32_spi_mr.MR.dlybcs = opt->delay*(pba_hz/1000000UL);
   u_avr32_spi_mr.MR.pcs = (1 << AVR32_SPI_MR_PCS_SIZE) - 1;
-  u_avr32_spi_mr.MR.llb = 0;
+  //u_avr32_spi_mr.MR.llb = 0;
   u_avr32_spi_mr.MR.modfdis = opt->modfdis;
   //u_avr32_spi_mr.MR.fdiv = 0;
   u_avr32_spi_mr.MR.pcsdec = opt->pcs_decode;
-  u_avr32_spi_mr.MR.ps = 0;
+  //u_avr32_spi_mr.MR.ps = 0;
   u_avr32_spi_mr.MR.mstr = 1;
   spi->mr = u_avr32_spi_mr.mr;
 
@@ -116,20 +105,29 @@ int spi_initMaster(volatile avr32_spi_t *spi, const spi_master_options_t *opt, U
   return 0;
 }
 /*-----------------------------------------------------------*/
-int spi_setupChipReg(volatile avr32_spi_t *spi,
-		unsigned char reg, const spi_options_t *options, U32 pba_hz)
+// Changed for eLua not to set clock frequencies higher than requested
+// and to return the actual baud rate that was set.
+U32 spi_setupChipReg(volatile avr32_spi_t *spi,
+                     unsigned char reg, const spi_options_t *options, U32 pba_hz)
 {
   u_avr32_spi_csr_t u_avr32_spi_csr;
+  U32 baudDiv;
 
   if (options->mode > 3 ||
       options->bits < 8 || options->bits > 16) {
-    return -1;
+    return 0;
   }
 
-  int baudDiv = getBaudDiv(options, pba_hz);
-
-  if (baudDiv < 0)
-    return -1;
+  // Use a frequency less than or equal to that requested, not the nearest
+  // available one, to avoid driving devices over their maximum speeds.
+  // A frequency less than or equal needs a divisor greater than or equal,
+  // and this formula cannot give a result of 0, so no need to check for it.
+  // Well, unless pba_hz is passed as 0...
+  if (options->baudrate == 0) baudDiv = 255;
+  else {
+    baudDiv = (pba_hz + options->baudrate - 1) / options->baudrate;
+    if (baudDiv > 255) baudDiv = 255;
+  }
 
   // Will use CSR0 offsets; these are the same for CSR0 to CSR3.
   u_avr32_spi_csr.csr = 0;
@@ -155,10 +153,11 @@ int spi_setupChipReg(volatile avr32_spi_t *spi,
       spi->csr3 = u_avr32_spi_csr.csr;
       break;
     default:
-      return -1;
+      return 0;  // Cannot happen in eLua
   }
 
-  return 0;
+  // Return the nearest integer to the actual baud rate
+  return (pba_hz + baudDiv/2) / baudDiv;
 }
 /*-----------------------------------------------------------*/
 int spi_selectChip(volatile avr32_spi_t *spi, unsigned char chip)
@@ -167,11 +166,11 @@ int spi_selectChip(volatile avr32_spi_t *spi, unsigned char chip)
   spi->mr |= AVR32_SPI_MR_PCS_MASK;
 
   if (spi->mr & AVR32_SPI_MR_PCSDEC_MASK) {
-	// The signal is decoded; allow up to 15 chips.
+    // The signal is decoded; allow up to 15 chips.
     if (chip > 14) goto err;
     spi->mr &= ~AVR32_SPI_MR_PCS_MASK | (chip << AVR32_SPI_MR_PCS_OFFSET);
-  }else {
-	  if (chip > 3) goto err;
+  } else {
+    if (chip > 3) goto err;
     spi->mr &= ~(1 << (AVR32_SPI_MR_PCS_OFFSET + chip));
   }
 
@@ -183,7 +182,7 @@ err:
 int spi_unselectChip(volatile avr32_spi_t *spi, unsigned char chip)
 {
   while (!(spi->sr & AVR32_SPI_SR_TXEMPTY_MASK))
-	  continue;
+    continue;
 
   // Assert all lines; no peripheral is selected.
   spi->mr |= AVR32_SPI_MR_PCS_MASK;
diff --git a/src/platform/avr32/spi.h b/src/platform/avr32/spi.h
index ca87b4bb..e872c640 100644
--- a/src/platform/avr32/spi.h
+++ b/src/platform/avr32/spi.h
@@ -4,15 +4,15 @@
 #include 
 
 #ifndef AVR32_SPI0
-    #define AVR32_SPI0          AVR32_SPI      
-    #define AVR32_SPI0_ADDRESS  AVR32_SPI_ADDRESS      
+    #define AVR32_SPI0          AVR32_SPI
+    #define AVR32_SPI0_ADDRESS  AVR32_SPI_ADDRESS
 #endif
-    
+
 typedef enum {
-	SPI_MODE_0 = 0,
-	SPI_MODE_1,
-	SPI_MODE_2,
-	SPI_MODE_3
+  SPI_MODE_0 = 0,
+  SPI_MODE_1,
+  SPI_MODE_2,
+  SPI_MODE_3
 } spi_mode_t;
 
 //! Option structure for SPI channels.
@@ -37,19 +37,19 @@ typedef struct
 
 typedef struct
 {
-	//! Mode fault detection disable
-	Bool modfdis;
-	//! Chip select decoding
-	Bool pcs_decode;
-	//! delay before chip select (in microseconds)
-	unsigned int delay;
+  //! Mode fault detection disable
+  Bool modfdis;
+  //! Chip select decoding
+  Bool pcs_decode;
+  //! delay before chip select (in microseconds)
+  unsigned int delay;
 } spi_master_options_t;
 
 
 extern void spi_reset(volatile avr32_spi_t *spi);
 
 extern int spi_initMaster(volatile avr32_spi_t *spi, const spi_master_options_t *, U32 pba_hz);
-extern int spi_setupChipReg(volatile avr32_spi_t *spi, unsigned char chip, const spi_options_t *, U32 pba_hz);
+extern U32 spi_setupChipReg(volatile avr32_spi_t *spi, unsigned char chip, const spi_options_t *, U32 pba_hz);
 
 extern int spi_selectChip(volatile avr32_spi_t *spi, unsigned char chip);
 extern int spi_unselectChip(volatile avr32_spi_t *spi, unsigned char chip);
diff --git a/src/platform/avr32/uip-conf.h b/src/platform/avr32/uip-conf.h
index f453d044..87251af5 100644
--- a/src/platform/avr32/uip-conf.h
+++ b/src/platform/avr32/uip-conf.h
@@ -34,7 +34,7 @@ typedef unsigned short uip_stats_t;
 //
 #define UIP_CONF_PINGADDRCONF       0
 
-// 
+//
 // TCP support on or off
 //
 #define UIP_CONF_TCP                1
@@ -130,8 +130,6 @@ typedef struct dhcpc_state uip_udp_appstate_t;
 #define UIP_UDP_APPCALL             elua_uip_udp_appcall
 #endif
 
-// Added for eLua: DHCP TIMER ID
-#define ELUA_DHCP_TIMER_ID          1
 #define CLOCK_SECOND                1000000UL
 
 #endif // __UIP_CONF_H_
diff --git a/src/platform/avr32/usart.c b/src/platform/avr32/usart.c
index b0c35242..a6eddedf 100644
--- a/src/platform/avr32/usart.c
+++ b/src/platform/avr32/usart.c
@@ -124,14 +124,14 @@ static int usart_set_async_baudrate(volatile avr32_usart_t *usart, unsigned int
  */
 unsigned int usart_get_async_baudrate(volatile avr32_usart_t *usart, unsigned long pba_hz)
 {
-  unsigned int clock;	// Master clock frequency
+  unsigned int clock;   // Master clock frequency
   unsigned int over;    // divisor of 8 or 16
   unsigned int cd;      // clock divider (0-65535)
   unsigned int fp;      // fractional part of clock divider (0-7)
   unsigned int divisor; // What the master clock is divided by to get
                         // the final baud rate
 
-  // Find 
+  // Find
   switch ((usart->mr & AVR32_USART_MR_USCLKS_MASK) >> AVR32_USART_MR_USCLKS_OFFSET)
   {
     case AVR32_USART_MR_USCLKS_MCK:
@@ -145,7 +145,7 @@ unsigned int usart_get_async_baudrate(volatile avr32_usart_t *usart, unsigned lo
     case AVR32_USART_MR_USCLKS_SCK:
       // If we have an external clock, we don't know its frequency here.
     default:
-      return 0;	
+      return 0;
   }
 
   over = usart->mr & AVR32_USART_MR_OVER_MASK;
@@ -154,7 +154,7 @@ unsigned int usart_get_async_baudrate(volatile avr32_usart_t *usart, unsigned lo
 
   // if CD==0, no baud rate is generated.
   // if CD==1, the clock divider and fractional part are bypassed.
-  if (cd == 0) return 0;   
+  if (cd == 0) return 0;
   if (cd == 1) fp = 0;
 
   // Rewriting "divisor = 8 * (2 - over) * (cd + fp/8)" for integer math:
diff --git a/src/platform/i386/platform.c b/src/platform/i386/platform.c
index fce2c3f8..b43b2ab1 100644
--- a/src/platform/i386/platform.c
+++ b/src/platform/i386/platform.c
@@ -67,7 +67,7 @@ static void scr_write( int fd, char c )
   monitor_put( c );
 }
 
-static int kb_read( s32 to )
+static int kb_read( timer_data_type to )
 {
   int res;
 
@@ -150,7 +150,7 @@ void platform_s_uart_send( unsigned id, u8 data )
 {
 }
 
-int platform_s_uart_recv( unsigned id, s32 timeout )
+int platform_s_uart_recv( unsigned id, timer_data_type timeout )
 {
   return -1;
 }
@@ -163,11 +163,11 @@ int platform_s_uart_set_flow_control( unsigned id, int type )
 // ****************************************************************************
 // "Dummy" timer functions
 
-void platform_s_timer_delay( unsigned id, u32 delay_us )
+void platform_s_timer_delay( unsigned id, timer_data_type delay_us )
 {
 }
 
-u32 platform_s_timer_op( unsigned id, int op, u32 data )
+timer_data_type platform_s_timer_op( unsigned id, int op, timer_data_type data )
 {
  return 0;
 }
diff --git a/src/platform/i386/platform_conf.h b/src/platform/i386/platform_conf.h
index 2098a4cf..aa7c1373 100644
--- a/src/platform/i386/platform_conf.h
+++ b/src/platform/i386/platform_conf.h
@@ -46,7 +46,7 @@
 #define NUM_ADC               0
 #define NUM_CAN               0
 
-// CPU frequency (needed by the CPU module, 0 if not used)
+// CPU frequency (needed by the CPU module and MMCFS code, 0 if not used)
 #define CPU_FREQUENCY         0
 
 // PIO prefix ('0' for P0, P1, ... or 'A' for PA, PB, ...)
diff --git a/src/platform/lm3s/conf.lua b/src/platform/lm3s/conf.lua
index 3ddcd6ff..55f67c95 100644
--- a/src/platform/lm3s/conf.lua
+++ b/src/platform/lm3s/conf.lua
@@ -1,6 +1,18 @@
 -- Configuration file for the LM3S microcontroller
 
-specific_files = "startup_gcc.c platform.c uart.c sysctl.c gpio.c ssi.c timer.c pwm.c ethernet.c systick.c flash.c interrupt.c cpu.c adc.c can.c platform_int.c"
+addi( sf( 'src/platform/%s/inc', platform ) )
+addi( sf( 'src/platform/%s/driverlib', platform ) )
+local cpu = comp.board:upper()
+
+-- Only include USB headers/paths for boards which support it
+if cpu == 'LM3S9B92' or board == 'LM3S9D92' then
+  addi( sf( 'src/platform/%s/usblib', platform ) )
+  addi( sf( 'src/platform/%s/usblib/device', platform ) )
+end
+
+specific_files = "startup_gcc.c platform.c platform_int.c"
+local fwlib_files = utils.get_files( "src/platform/" .. platform .. "/driverlib", ".*%.c$" )
+
 
 local board = comp.board:upper()
 if board == 'EK-LM3S1968' or board == 'EK-LM3S6965' or board == 'EK-LM3S8962' then
@@ -14,10 +26,22 @@ if board == 'EAGLE-100' then
   addlf '-Wl,-Ttext,0x2000'
 end
 
-local ldscript = board == 'EK-LM3S9B92' and "lm3s-9b92.ld" or "lm3s.ld"
+if cpu == 'LM3S9B92' or cpu == 'LM3S9D92' then
+   fwlib_files = fwlib_files .. " " .. utils.get_files( "src/platform/" .. platform .. "/usblib", ".*%.c$" ) 
+   fwlib_files = fwlib_files .. " " .. utils.get_files( "src/platform/" .. platform .. "/usblib/device", ".*%.c$" )
+   specific_files = specific_files .. "  usb_serial_structs.c"
+end
+
+if board == 'EK-LM3S9B92'  then
+   ldscript = "lm3s-9b92.ld"
+elseif board == 'SOLDERCORE' then
+   ldscript = "lm3s-9d92.ld"
+else
+   ldscript = "lm3s.ld"
+end
 
 -- Prepend with path
-specific_files = utils.prepend_path( specific_files, sf( "src/platform/%s", platform) )
+specific_files = fwlib_files .. " " .. utils.prepend_path( specific_files, "src/platform/" .. platform )
 specific_files = specific_files .. " src/platform/cortex_utils.s src/platform/arm_cortex_interrupts.c"
 ldscript = sf( "src/platform/%s/%s", platform, ldscript )
 
diff --git a/src/platform/lm3s/conf.py b/src/platform/lm3s/conf.py
index 854e8881..5aeec575 100644
--- a/src/platform/lm3s/conf.py
+++ b/src/platform/lm3s/conf.py
@@ -1,5 +1,19 @@
 # Configuration file for the LM3S microcontroller
-specific_files = "startup_gcc.c platform.c uart.c sysctl.c gpio.c ssi.c timer.c pwm.c ethernet.c systick.c flash.c interrupt.c cpu.c adc.c can.c platform_int.c"
+import fnmatch
+import glob
+import os
+
+comp.Append(CPPPATH = ['src/platform/%s/inc' % platform])
+comp.Append(CPPPATH = ['src/platform/%s/driverlib' % platform])
+
+# Only include USB headers/paths for boards which support it
+if comp[ 'cpu' ] == 'LM3S9B92' or comp[ 'cpu' ] == 'LM3S9D92':
+  comp.Append(CPPPATH = ['src/platform/%s/usblib' % platform])
+  comp.Append(CPPPATH = ['src/platform/%s/usblib/device' % platform])
+
+fwlib_files = " ".join(glob.glob("src/platform/%s/driverlib/*.c" % platform))
+
+specific_files = "startup_gcc.c platform.c platform_int.c"
 
 if comp[ 'board' ] == 'EK-LM3S1968' or comp[ 'board' ] == 'EK-LM3S6965' or comp[ 'board' ] == 'EK-LM3S8962':
   specific_files = specific_files + " rit128x96x4.c disp.c"
@@ -11,13 +25,21 @@ if comp[ 'board' ] == 'EK-LM3S1968' or comp[ 'board' ] == 'EK-LM3S6965' or comp[
 if comp[ 'board' ] == 'EAGLE-100':
   comp.Append(LINKFLAGS = ['-Wl,-Ttext,0x2000'])
 
+if comp[ 'cpu' ] == 'LM3S9B92' or comp[ 'cpu' ] == 'LM3S9D92':
+  fwlib_files = fwlib_files + " " + " ".join(glob.glob("src/platform/%s/usblib/*.c" % platform))
+  fwlib_files = fwlib_files + " " + " ".join(glob.glob("src/platform/%s/usblib/device/*.c" % platform))
+  specific_files = specific_files + " usb_serial_structs.c"
+
+
 if comp[ 'board' ] == 'EK-LM3S9B92':
   ldscript = "lm3s-9b92.ld"
+elif comp[ 'board' ] == 'SOLDERCORE':
+  ldscript = "lm3s-9d92.ld"
 else:
   ldscript = "lm3s.ld"
 
 # Prepend with path
-specific_files = " ".join( [ "src/platform/%s/%s" % ( platform, f ) for f in specific_files.split() ] )
+specific_files = fwlib_files + " " + " ".join( [ "src/platform/%s/%s" % ( platform, f ) for f in specific_files.split() ] )
 specific_files += " src/platform/cortex_utils.s src/platform/arm_cortex_interrupts.c"
 ldscript = "src/platform/%s/%s" % ( platform, ldscript )
 
diff --git a/src/platform/lm3s/cpu.c b/src/platform/lm3s/cpu.c
deleted file mode 100755
index 5b32cfd5..00000000
--- a/src/platform/lm3s/cpu.c
+++ /dev/null
@@ -1,189 +0,0 @@
-//*****************************************************************************
-//
-// cpu.c - Instruction wrappers for special CPU instructions needed by the
-//         drivers.
-//
-// Copyright (c) 2006-2009 Luminary Micro, Inc.  All rights reserved.
-// Software License Agreement
-// 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
-// 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
-// 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
-//
-//*****************************************************************************
-
-#include "cpu.h"
-
-//*****************************************************************************
-//
-// Wrapper function for the CPSID instruction.  Returns the state of PRIMASK
-// on entry.
-//
-//*****************************************************************************
-#if defined(codered) || defined(gcc) || defined(sourcerygxx)
-unsigned long __attribute__((naked))
-CPUcpsid(void)
-{
-    unsigned long ulRet;
-
-    //
-    // Read PRIMASK and disable interrupts.
-    //
-    __asm("    mrs     %0, PRIMASK\n"
-          "    cpsid   i\n"
-          "    bx      lr\n"
-          : "=r" (ulRet));
-
-    //
-    // The return is handled in the inline assembly, but the compiler will
-    // still complain if there is not an explicit return here (despite the fact
-    // that this does not result in any code being produced because of the
-    // naked attribute).
-    //
-    return(ulRet);
-}
-#endif
-#if defined(ewarm)
-unsigned long
-CPUcpsid(void)
-{
-    //
-    // Read PRIMASK and disable interrupts.
-    //
-    __asm("    mrs     r0, PRIMASK\n"
-          "    cpsid   i\n");
-
-    //
-    // "Warning[Pe940]: missing return statement at end of non-void function"
-    // is suppressed here to avoid putting a "bx lr" in the inline assembly
-    // above and a superfluous return statement here.
-    //
-#pragma diag_suppress=Pe940
-}
-#pragma diag_default=Pe940
-#endif
-#if defined(rvmdk) || defined(__ARMCC_VERSION)
-__asm unsigned long
-CPUcpsid(void)
-{
-    //
-    // Read PRIMASK and disable interrupts.
-    //
-    mrs     r0, PRIMASK;
-    cpsid   i;
-    bx      lr
-}
-#endif
-
-//*****************************************************************************
-//
-// Wrapper function for the CPSIE instruction.  Returns the state of PRIMASK
-// on entry.
-//
-//*****************************************************************************
-#if defined(codered) || defined(gcc) || defined(sourcerygxx)
-unsigned long __attribute__((naked))
-CPUcpsie(void)
-{
-    unsigned long ulRet;
-
-    //
-    // Read PRIMASK and enable interrupts.
-    //
-    __asm("    mrs     %0, PRIMASK\n"
-          "    cpsie   i\n"
-          "    bx      lr\n"
-          : "=r" (ulRet));
-
-    //
-    // The return is handled in the inline assembly, but the compiler will
-    // still complain if there is not an explicit return here (despite the fact
-    // that this does not result in any code being produced because of the
-    // naked attribute).
-    //
-    return(ulRet);
-}
-#endif
-#if defined(ewarm)
-unsigned long
-CPUcpsie(void)
-{
-    //
-    // Read PRIMASK and enable interrupts.
-    //
-    __asm("    mrs     r0, PRIMASK\n"
-          "    cpsie   i\n");
-
-    //
-    // "Warning[Pe940]: missing return statement at end of non-void function"
-    // is suppressed here to avoid putting a "bx lr" in the inline assembly
-    // above and a superfluous return statement here.
-    //
-#pragma diag_suppress=Pe940
-}
-#pragma diag_default=Pe940
-#endif
-#if defined(rvmdk) || defined(__ARMCC_VERSION)
-__asm unsigned long
-CPUcpsie(void)
-{
-    //
-    // Read PRIMASK and enable interrupts.
-    //
-    mrs     r0, PRIMASK;
-    cpsie   i;
-    bx      lr
-}
-#endif
-
-//*****************************************************************************
-//
-// Wrapper function for the WFI instruction.
-//
-//*****************************************************************************
-#if defined(codered) || defined(gcc) || defined(sourcerygxx)
-void __attribute__((naked))
-CPUwfi(void)
-{
-    //
-    // Wait for the next interrupt.
-    //
-    __asm("    wfi\n"
-          "    bx      lr\n");
-}
-#endif
-#if defined(ewarm)
-void
-CPUwfi(void)
-{
-    //
-    // Wait for the next interrupt.
-    //
-    __asm("    wfi\n");
-}
-#endif
-#if defined(rvmdk) || defined(__ARMCC_VERSION)
-__asm void
-CPUwfi(void)
-{
-    //
-    // Wait for the next interrupt.
-    //
-    wfi;
-    bx      lr
-}
-#endif
diff --git a/src/platform/lm3s/disp.c b/src/platform/lm3s/disp.c
index e4fa4537..161baf0b 100644
--- a/src/platform/lm3s/disp.c
+++ b/src/platform/lm3s/disp.c
@@ -103,9 +103,3 @@ const LUA_REG_TYPE disp_map[] =
   { LSTRKEY( "draw" ), LFUNCVAL( disp_imageDraw ) },  
   { LNILKEY, LNILVAL }
 };
-
-LUALIB_API int luaopen_disp( lua_State *L )
-{
-  LREGISTER( L, AUXLIB_DISP, disp_map );
-}  
-
diff --git a/src/platform/lm3s/adc.c b/src/platform/lm3s/driverlib/adc.c
similarity index 79%
rename from src/platform/lm3s/adc.c
rename to src/platform/lm3s/driverlib/adc.c
index d8f7f0e3..568edfac 100755
--- a/src/platform/lm3s/adc.c
+++ b/src/platform/lm3s/driverlib/adc.c
@@ -2,26 +2,23 @@
 //
 // adc.c - Driver for the ADC.
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2011 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
+// This is part of revision 7611 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -32,13 +29,14 @@
 //
 //*****************************************************************************
 
-#include "hw_adc.h"
-#include "hw_ints.h"
-#include "hw_memmap.h"
-#include "hw_types.h"
-#include "adc.h"
-#include "debug.h"
-#include "interrupt.h"
+#include "inc/hw_adc.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_types.h"
+#include "inc/hw_sysctl.h"
+#include "driverlib/adc.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
 
 //*****************************************************************************
 //
@@ -99,7 +97,8 @@ ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum,
     //
     // Determine the interrupt to register based on the sequence number.
     //
-    ulInt = INT_ADC0 + ulSequenceNum;
+    ulInt = ((ulBase == ADC0_BASE) ? (INT_ADC0SS0 + ulSequenceNum) :
+             (INT_ADC1SS0 + ulSequenceNum));
 
     //
     // Register the interrupt handler.
@@ -143,7 +142,8 @@ ADCIntUnregister(unsigned long ulBase, unsigned long ulSequenceNum)
     //
     // Determine the interrupt to unregister based on the sequence number.
     //
-    ulInt = INT_ADC0 + ulSequenceNum;
+    ulInt = ((ulBase == ADC0_BASE) ? (INT_ADC0SS0 + ulSequenceNum) :
+             (INT_ADC1SS0 + ulSequenceNum));
 
     //
     // Disable the interrupt.
@@ -258,7 +258,7 @@ ADCIntStatus(unsigned long ulBase, unsigned long ulSequenceNum,
         ulTemp = HWREG(ulBase + ADC_O_RIS) & (0x10000 | (1 << ulSequenceNum));
 
         //
-        // If the Digital Comparator status bit is set, reflect it to the 
+        // If the digital comparator status bit is set, reflect it to the
         // appropriate sequence bit.
         //
         if(ulTemp & 0x10000)
@@ -285,14 +285,14 @@ ADCIntStatus(unsigned long ulBase, unsigned long ulSequenceNum,
 //! asserts.  This must be done in the interrupt handler to keep it from being
 //! called again immediately upon exit.
 //!
-//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
-//! several clock cycles before the interrupt source is actually cleared.
+//! \note Because there is a write buffer in the Cortex-M3 processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
 //! Therefore, it is recommended that the interrupt source be cleared early in
 //! the interrupt handler (as opposed to the very last action) to avoid
 //! returning from the interrupt handler before the interrupt source is
 //! actually cleared.  Failure to do so may result in the interrupt handler
-//! being immediately reentered (since NVIC still sees the interrupt source
-//! asserted).
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
 //!
 //! \return None.
 //
@@ -405,6 +405,8 @@ ADCSequenceDisable(unsigned long ulBase, unsigned long ulSequenceNum)
 //!                         configured with PWMGenIntTrigEnable().
 //! - \b ADC_TRIGGER_PWM2 - A trigger generated by the third PWM generator;
 //!                         configured with PWMGenIntTrigEnable().
+//! - \b ADC_TRIGGER_PWM3 - A trigger generated by the fourth PWM generator;
+//!                         configured with PWMGenIntTrigEnable().
 //! - \b ADC_TRIGGER_ALWAYS - A trigger that is always asserted, causing the
 //!                           sample sequence to capture repeatedly (so long as
 //!                           there is not a higher priority source active).
@@ -439,6 +441,7 @@ ADCSequenceConfigure(unsigned long ulBase, unsigned long ulSequenceNum,
            (ulTrigger == ADC_TRIGGER_PWM0) ||
            (ulTrigger == ADC_TRIGGER_PWM1) ||
            (ulTrigger == ADC_TRIGGER_PWM2) ||
+           (ulTrigger == ADC_TRIGGER_PWM3) ||
            (ulTrigger == ADC_TRIGGER_ALWAYS));
     ASSERT(ulPriority < 4);
 
@@ -470,12 +473,9 @@ ADCSequenceConfigure(unsigned long ulBase, unsigned long ulSequenceNum,
 //! \param ulSequenceNum is the sample sequence number.
 //! \param ulStep is the step to be configured.
 //! \param ulConfig is the configuration of this step; must be a logical OR of
-//! \b ADC_CTL_TS, \b ADC_CTL_IE, \b ADC_CTL_END, \b ADC_CTL_D, and one of the
-//! input channel selects (\b ADC_CTL_CH0 through \b ADC_CTL_CH15).  For parts
-//! with the Digital Comparator feature, the follow values may also be OR'd
-//! into the \e ulConfig value to enable the Digital Comparater feature:
-//! \b ADC_CTL_CE and one of the comparater selects (\b ADC_CTL_CMP0 through
-//! \b ADC_CTL_CMP7).
+//! \b ADC_CTL_TS, \b ADC_CTL_IE, \b ADC_CTL_END, \b ADC_CTL_D, one of the
+//! input channel selects (\b ADC_CTL_CH0 through \b ADC_CTL_CH15), and one of
+//! the digital comparator selects (\b ADC_CTL_CMP0 through \b ADC_CTL_CMP7).
 //!
 //! This function will set the configuration of the ADC for one step of a
 //! sample sequence.  The ADC can be configured for single-ended or
@@ -485,15 +485,15 @@ ADCSequenceConfigure(unsigned long ulBase, unsigned long ulSequenceNum,
 //! temperature sensor can be selected (the \b ADC_CTL_TS bit).  Additionally,
 //! this step can be defined as the last in the sequence (the \b ADC_CTL_END
 //! bit) and it can be configured to cause an interrupt when the step is
-//! complete (the \b ADC_CTL_IE bit).  If the Digital Comparators are present
-//! on the device, this step may also be configured send the ADC sample to
-//! the selected comparator (the \b ADC_CTL_CMP0 through \b ADC_CTL_CMP7
-//! values) by using the \b ADC_CTL_CE bit.  The configuration is used by the
-//! ADC at the appropriate time when the trigger for this sequence occurs.
+//! complete (the \b ADC_CTL_IE bit).  If the digital comparators are present
+//! on the device, this step may also be configured to send the ADC sample to
+//! the selected comparator using \b ADC_CTL_CMP0 through \b ADC_CTL_CMP7.
+//! The configuration is used by the ADC at the appropriate time when the
+//! trigger for this sequence occurs.
 //!
 //! \note If the Digitial Comparator is present and enabled using the
-//! \b ADC_CTL_CE bit, the ADC sample will NOT be written into the ADC
-//! sequence data FIFO.
+//! \b ADC_CTL_CMP0 through \b ADC_CTL_CMP7 selects, the ADC sample will NOT be
+//! written into the ADC sequence data FIFO.
 //!
 //! The \e ulStep parameter determines the order in which the samples are
 //! captured by the ADC when the trigger occurs.  It can range from zero to
@@ -555,7 +555,7 @@ ADCSequenceStepConfigure(unsigned long ulBase, unsigned long ulSequenceNum,
                                  (((ulConfig & 0xf0) >> 4) << ulStep));
 
     //
-    // Enable Digital Comparator if specified in the ulConfig bit-fields.
+    // Enable digital comparator if specified in the ulConfig bit-fields.
     //
     if(ulConfig & 0x000F0000)
     {
@@ -576,7 +576,7 @@ ADCSequenceStepConfigure(unsigned long ulBase, unsigned long ulSequenceNum,
     }
 
     //
-    // Disable Digital Comparator if not specified.
+    // Disable digital comparator if not specified.
     //
     else
     {
@@ -766,10 +766,16 @@ ADCSequenceDataGet(unsigned long ulBase, unsigned long ulSequenceNum,
 //! Causes a processor trigger for a sample sequence.
 //!
 //! \param ulBase is the base address of the ADC module.
-//! \param ulSequenceNum is the sample sequence number.
+//! \param ulSequenceNum is the sample sequence number, with
+//! \b ADC_TRIGGER_WAIT or \b ADC_TRIGGER_SIGNAL optionally ORed into it.
 //!
 //! This function triggers a processor-initiated sample sequence if the sample
-//! sequence trigger is configured to \b ADC_TRIGGER_PROCESSOR.
+//! sequence trigger is configured to \b ADC_TRIGGER_PROCESSOR.  If
+//! \b ADC_TRIGGER_WAIT is ORed into the sequence number, the
+//! processor-initiated trigger is delayed until a later processor-initiated
+//! trigger to a different ADC module that specifies \b ADC_TRIGGER_SIGNAL,
+//! allowing multiple ADCs to start from a processor-initiated trigger in a
+//! synchronous manner.
 //!
 //! \return None.
 //
@@ -781,12 +787,13 @@ ADCProcessorTrigger(unsigned long ulBase, unsigned long ulSequenceNum)
     // Check the arguments.
     //
     ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
-    ASSERT(ulSequenceNum < 4);
+    ASSERT((ulSequenceNum & 0xf) < 4);
 
     //
     // Generate a processor trigger for this sample sequence.
     //
-    HWREG(ulBase + ADC_O_PSSI) = 1 << ulSequenceNum;
+    HWREG(ulBase + ADC_O_PSSI) |= ((ulSequenceNum & 0xffff0000) |
+                                   (1 << (ulSequenceNum & 0xf)));
 }
 
 //*****************************************************************************
@@ -1036,7 +1043,7 @@ ADCHardwareOversampleConfigure(unsigned long ulBase, unsigned long ulFactor)
 
 //*****************************************************************************
 //
-//! Configures an ADC Digital Comparator.
+//! Configures an ADC digital comparator.
 //!
 //! \param ulBase is the base address of the ADC module.
 //! \param ulComp is the index of the comparator to configure.
@@ -1123,14 +1130,14 @@ ADCComparatorConfigure(unsigned long ulBase, unsigned long ulComp,
 
 //*****************************************************************************
 //
-//! Define the ADC Digital Comparator Regions.
+//! Defines the ADC digital comparator regions.
 //!
 //! \param ulBase is the base address of the ADC module.
 //! \param ulComp is the index of the comparator to configure.
 //! \param ulLowRef is the reference point for the low/mid band threshold.
 //! \param ulHighRef is the reference point for the mid/high band threshold.
 //!
-//! The ADC Digital Comparator operation is based on three ADC value regions:
+//! The ADC digital comparator operation is based on three ADC value regions:
 //! - \b low-band is defined as any ADC value less than or equal to the
 //! \e ulLowRef value.
 //! - \b mid-band is defined as any ADC value greater than the \e ulLowRef
@@ -1161,14 +1168,14 @@ ADCComparatorRegionSet(unsigned long ulBase, unsigned long ulComp,
 
 //*****************************************************************************
 //
-//! Resets the current ADC Digital Comparator conditions.
+//! Resets the current ADC digital comparator conditions.
 //!
 //! \param ulBase is the base address of the ADC module.
 //! \param ulComp is the index of the comparator.
 //! \param bTrigger is the flag to indicate reset of Trigger conditions.
 //! \param bInterrupt is the flag to indicate reset of Interrupt conditions.
 //!
-//! Because the Digital Comparator uses current and previous ADC values, this
+//! Because the digital comparator uses current and previous ADC values, this
 //! function is provide to allow the comparator to be reset to its initial
 //! value to prevent stale data from being used when a sequence is enabled.
 //!
@@ -1263,7 +1270,7 @@ ADCComparatorIntEnable(unsigned long ulBase, unsigned long ulSequenceNum)
 //!
 //! \param ulBase is the base address of the ADC module.
 //!
-//! This returns the Digitial Comparator interrupt status bits.  This status
+//! This returns the digitial comparator interrupt status bits.  This status
 //! is sequence agnostic.
 //!
 //! \return The current comparator interrupt status.
@@ -1299,7 +1306,7 @@ void
 ADCComparatorIntClear(unsigned long ulBase, unsigned long ulStatus)
 {
     //
-    // Check the arugments.
+    // Check the arguments.
     //
     ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
 
@@ -1309,6 +1316,217 @@ ADCComparatorIntClear(unsigned long ulBase, unsigned long ulStatus)
     HWREG(ulBase + ADC_O_DCISC) = ulStatus;
 }
 
+//*****************************************************************************
+//
+//! Selects the ADC reference.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulRef is the reference to use.
+//!
+//! The ADC reference is set as specified by \e ulRef.  It must be one of
+//! \b ADC_REF_INT, \b ADC_REF_EXT_3V, or \b ADC_REF_EXT_1V for internal or
+//! external reference.  If \b ADC_REF_INT is chosen, then an internal 3V
+//! reference is used and no external reference is needed.  If
+//! \b ADC_REF_EXT_3V is chosen, then a 3V reference must be supplied to the
+//! AVREF pin.  If \b ADC_REF_EXT_1V is chosen, then a 1V external referece
+//! must be supplied to the AVREF pin.
+//!
+//! \note The ADC reference can only be selected on parts that have an external
+//! reference.  Consult the data sheet for your part to determine if there is
+//! an external reference.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCReferenceSet(unsigned long ulBase, unsigned long ulRef)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+    ASSERT((ulRef == ADC_REF_INT) || (ulRef == ADC_REF_EXT_3V) ||
+           (ulRef == ADC_REF_EXT_1V));
+
+    //
+    // Set the reference.
+    //
+    HWREG(ulBase + ADC_O_CTL) = (HWREG(ulBase + ADC_O_CTL) & ~ADC_CTL_VREF) |
+                                ulRef;
+}
+
+//*****************************************************************************
+//
+//! Returns the current setting of the ADC reference.
+//!
+//! \param ulBase is the base address of the ADC module.
+//!
+//! Returns the value of the ADC reference setting.  The returned value will be
+//! one of \b ADC_REF_INT, \b ADC_REF_EXT_3V, or \b ADC_REF_EXT_1V.
+//!
+//! \note The value returned by this function is only meaningful if used on a
+//! part that is capable of using an external reference.  Consult the data
+//! sheet for your part to determine if it has an external reference input.
+//!
+//! \return The current setting of the ADC reference.
+//
+//*****************************************************************************
+unsigned long
+ADCReferenceGet(unsigned long ulBase)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+
+    //
+    // Return the value of the reference.
+    //
+    return(HWREG(ulBase + ADC_O_CTL) & ADC_CTL_VREF);
+}
+
+//*****************************************************************************
+//
+//! Selects the ADC resolution.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulResolution is the ADC bit resolution.
+//!
+//! The ADC resolution is set as specified by \e ulResolution.  It must be one
+//! of \b ADC_RES_12BIT or \b ADC_RES_10BIT.
+//!
+//! \note The ADC resolution can only be set on parts that are capable of
+//! greater than 10-bit conversions.  Consult the data sheet for your part to
+//! determine if it is capable of 12-bit conversions.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCResolutionSet(unsigned long ulBase, unsigned long ulResolution)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+    ASSERT((ulResolution == ADC_RES_10BIT) || (ulResolution == ADC_RES_12BIT));
+
+    //
+    // Set the resolution.
+    //
+    HWREG(ulBase + ADC_O_CTL) = (HWREG(ulBase + ADC_O_CTL) & ~ADC_CTL_RES) |
+                                ulResolution;
+}
+
+//*****************************************************************************
+//
+//! Gets the setting of ADC resolution.
+//!
+//! \param ulBase is the base address of the ADC module.
+//!
+//! The ADC resolution is returned as one of \b ADC_RES_12BIT or
+//! \b ADC_RES_10BIT.
+//!
+//! \note The value returned by this function is only meaningful if used on a
+//! part that is capable of higher than 10-bit ADC resolution.  Consult the
+//! data sheet for your part to determine if it is capable of 12-bit
+//! conversions.
+//!
+//! \return The current setting of the ADC resolution.
+//
+//*****************************************************************************
+unsigned long
+ADCResolutionGet(unsigned long ulBase)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+
+    //
+    // Get the resolution and return it to the caller.
+    //
+    return(HWREG(ulBase + ADC_O_CTL) & ADC_CTL_RES);
+}
+
+//*****************************************************************************
+//
+//! Sets the phase delay between a trigger and the start of a sequence.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulPhase is the phase delay, specified as one of \b ADC_PHASE_0,
+//! \b ADC_PHASE_22_5, \b ADC_PHASE_45, \b ADC_PHASE_67_5, \b ADC_PHASE_90,
+//! \b ADC_PHASE_112_5, \b ADC_PHASE_135, \b ADC_PHASE_157_5, \b ADC_PHASE_180,
+//! \b ADC_PHASE_202_5, \b ADC_PHASE_225, \b ADC_PHASE_247_5, \b ADC_PHASE_270,
+//! \b ADC_PHASE_292_5, \b ADC_PHASE_315, or \b ADC_PHASE_337_5.
+//!
+//! This function sets the phase delay between the detection of an ADC trigger
+//! event and the start of the sample sequence.  By selecting a different phase
+//! delay for a pair of ADC modules (such as \b ADC_PHASE_0 and
+//! \b ADC_PHASE_180) and having each ADC module sample the same analog input,
+//! it is possible to increase the sampling rate of the analog input (with
+//! samples N, N+2, N+4, and so on, coming from the first ADC and samples N+1,
+//! N+3, N+5, and so on, coming from the second ADC).  The ADC module has a
+//! single phase delay that is applied to all sample sequences within that
+//! module.
+//!
+//! \note This capability is not available on all parts.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCPhaseDelaySet(unsigned long ulBase, unsigned long ulPhase)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+    ASSERT((ulPhase == ADC_PHASE_0) || (ulPhase == ADC_PHASE_22_5) ||
+           (ulPhase == ADC_PHASE_45) || (ulPhase == ADC_PHASE_67_5) ||
+           (ulPhase == ADC_PHASE_90) || (ulPhase == ADC_PHASE_112_5) ||
+           (ulPhase == ADC_PHASE_135) || (ulPhase == ADC_PHASE_157_5) ||
+           (ulPhase == ADC_PHASE_180) || (ulPhase == ADC_PHASE_202_5) ||
+           (ulPhase == ADC_PHASE_225) || (ulPhase == ADC_PHASE_247_5) ||
+           (ulPhase == ADC_PHASE_270) || (ulPhase == ADC_PHASE_292_5) ||
+           (ulPhase == ADC_PHASE_315) || (ulPhase == ADC_PHASE_337_5));
+
+    //
+    // Set the phase delay.
+    //
+    HWREG(ulBase + ADC_O_SPC) = ulPhase;
+}
+
+//*****************************************************************************
+//
+//! Gets the phase delay between a trigger and the start of a sequence.
+//!
+//! \param ulBase is the base address of the ADC module.
+//!
+//! This function gets the current phase delay between the detection of an ADC
+//! trigger event and the start of the sample sequence.
+//!
+//! \return Returns the phase delay, specified as one of \b ADC_PHASE_0,
+//! \b ADC_PHASE_22_5, \b ADC_PHASE_45, \b ADC_PHASE_67_5, \b ADC_PHASE_90,
+//! \b ADC_PHASE_112_5, \b ADC_PHASE_135, \b ADC_PHASE_157_5, \b ADC_PHASE_180,
+//! \b ADC_PHASE_202_5, \b ADC_PHASE_225, \b ADC_PHASE_247_5, \b ADC_PHASE_270,
+//! \b ADC_PHASE_292_5, \b ADC_PHASE_315, or \b ADC_PHASE_337_5.
+//
+//*****************************************************************************
+unsigned long
+ADCPhaseDelayGet(unsigned long ulBase)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+
+    //
+    // Return the phase delay.
+    //
+    return(HWREG(ulBase + ADC_O_SPC));
+}
+
 //*****************************************************************************
 //
 // Close the Doxygen group.
diff --git a/src/platform/lm3s/adc.h b/src/platform/lm3s/driverlib/adc.h
similarity index 72%
rename from src/platform/lm3s/adc.h
rename to src/platform/lm3s/driverlib/adc.h
index 274ca7cb..b7ebc9bb 100755
--- a/src/platform/lm3s/adc.h
+++ b/src/platform/lm3s/driverlib/adc.h
@@ -2,26 +2,23 @@
 //
 // adc.h - ADC headers for using the ADC driver functions.
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2011 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
+// This is part of revision 7611 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -54,6 +51,7 @@ extern "C"
 #define ADC_TRIGGER_PWM0        0x00000006  // PWM0 event
 #define ADC_TRIGGER_PWM1        0x00000007  // PWM1 event
 #define ADC_TRIGGER_PWM2        0x00000008  // PWM2 event
+#define ADC_TRIGGER_PWM3        0x00000009  // PWM3 event
 #define ADC_TRIGGER_ALWAYS      0x0000000F  // Always event
 
 //*****************************************************************************
@@ -135,6 +133,56 @@ extern "C"
 #define ADC_COMP_INT_HIGH_HONCE \
                                 0x0000001F  // Interrupt High Once (Hysteresis)
 
+//*****************************************************************************
+//
+// Values that can be used to modify the sequence number passed to
+// ADCProcessorTrigger in order to get cross-module synchronous processor
+// triggers.
+//
+//*****************************************************************************
+#define ADC_TRIGGER_WAIT        0x08000000  // Wait for the synchronous trigger
+#define ADC_TRIGGER_SIGNAL      0x80000000  // Signal the synchronous trigger
+
+//*****************************************************************************
+//
+// Values that can be passed to ADCPhaseDelaySet as the ulPhase parameter and
+// returned from ADCPhaseDelayGet.
+//
+//*****************************************************************************
+#define ADC_PHASE_0             0x00000000  // 0 degrees
+#define ADC_PHASE_22_5          0x00000001  // 22.5 degrees
+#define ADC_PHASE_45            0x00000002  // 45 degrees
+#define ADC_PHASE_67_5          0x00000003  // 67.5 degrees
+#define ADC_PHASE_90            0x00000004  // 90 degrees
+#define ADC_PHASE_112_5         0x00000005  // 112.5 degrees
+#define ADC_PHASE_135           0x00000006  // 135 degrees
+#define ADC_PHASE_157_5         0x00000007  // 157.5 degrees
+#define ADC_PHASE_180           0x00000008  // 180 degrees
+#define ADC_PHASE_202_5         0x00000009  // 202.5 degrees
+#define ADC_PHASE_225           0x0000000A  // 225 degrees
+#define ADC_PHASE_247_5         0x0000000B  // 247.5 degrees
+#define ADC_PHASE_270           0x0000000C  // 270 degrees
+#define ADC_PHASE_292_5         0x0000000D  // 292.5 degrees
+#define ADC_PHASE_315           0x0000000E  // 315 degrees
+#define ADC_PHASE_337_5         0x0000000F  // 337.5 degrees
+
+//*****************************************************************************
+//
+// Values that can be passed to ADCReferenceSet as the ulRef parameter.
+//
+//*****************************************************************************
+#define ADC_REF_INT             0x00000000  // Internal reference
+#define ADC_REF_EXT_3V          0x00000001  // External 3V reference
+#define ADC_REF_EXT_1V          0x00000003  // External 1V reference
+
+//*****************************************************************************
+//
+// Values that can be passed to ADCResolutionSet as the ulResolution parameter.
+//
+//*****************************************************************************
+#define ADC_RES_10BIT           0x00000000  // 10-bit resolution
+#define ADC_RES_12BIT           0x00000010  // 12-bit resolution
+
 //*****************************************************************************
 //
 // Prototypes for the APIs.
@@ -202,7 +250,12 @@ extern void ADCComparatorIntEnable(unsigned long ulBase,
 extern unsigned long ADCComparatorIntStatus(unsigned long ulBase);
 extern void ADCComparatorIntClear(unsigned long ulBase,
                                   unsigned long ulStatus);
-
+extern void ADCReferenceSet(unsigned long ulBase, unsigned long ulRef);
+extern unsigned long ADCReferenceGet(unsigned long ulBase);
+extern void ADCResolutionSet(unsigned long ulBase, unsigned long ulResolution);
+extern unsigned long ADCResolutionGet(unsigned long ulBase);
+extern void ADCPhaseDelaySet(unsigned long ulBase, unsigned long ulPhase);
+extern unsigned long ADCPhaseDelayGet(unsigned long ulBase);
 
 //*****************************************************************************
 //
diff --git a/src/platform/lm3s/can.c b/src/platform/lm3s/driverlib/can.c
similarity index 84%
rename from src/platform/lm3s/can.c
rename to src/platform/lm3s/driverlib/can.c
index d5895ad5..e71dbde9 100755
--- a/src/platform/lm3s/can.c
+++ b/src/platform/lm3s/driverlib/can.c
@@ -2,26 +2,23 @@
 //
 // can.c - Driver for the CAN module.
 //
-// Copyright (c) 2006-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2006-2011 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
+// This is part of revision 7611 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -32,14 +29,14 @@
 //
 //*****************************************************************************
 
-#include "hw_can.h"
-#include "hw_ints.h"
-#include "hw_nvic.h"
-#include "hw_memmap.h"
-#include "hw_types.h"
-#include "can.h"
-#include "debug.h"
-#include "interrupt.h"
+#include "inc/hw_can.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_nvic.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_types.h"
+#include "driverlib/can.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
 
 //*****************************************************************************
 //
@@ -47,34 +44,56 @@
 // identifier.
 //
 //*****************************************************************************
-#define CAN_MAX_11BIT_MSG_ID    (0x7ff)
+#define CAN_MAX_11BIT_MSG_ID    0x7ff
 
 //*****************************************************************************
 //
 // This is used as the loop delay for accessing the CAN controller registers.
 //
 //*****************************************************************************
-#define CAN_RW_DELAY            (5)
+#define CAN_RW_DELAY            5
 
+//*****************************************************************************
 //
-// The maximum CAN bit timing divisor is 13.
+// The maximum CAN bit timing divisor is 19.
 //
-#define CAN_MAX_BIT_DIVISOR     (13)
+//*****************************************************************************
+#define CAN_MAX_BIT_DIVISOR     19
 
+//*****************************************************************************
 //
-// The minimum CAN bit timing divisor is 5.
+// The minimum CAN bit timing divisor is 4.
 //
-#define CAN_MIN_BIT_DIVISOR     (5)
+//*****************************************************************************
+#define CAN_MIN_BIT_DIVISOR     4
 
+//*****************************************************************************
 //
 // The maximum CAN pre-divisor is 1024.
 //
-#define CAN_MAX_PRE_DIVISOR     (1024)
+//*****************************************************************************
+#define CAN_MAX_PRE_DIVISOR     1024
 
+//*****************************************************************************
 //
-// The minimum CAN pre-divisor is 1024.
+// The minimum CAN pre-divisor is 1.
 //
-#define CAN_MIN_PRE_DIVISOR     (1024)
+//*****************************************************************************
+#define CAN_MIN_PRE_DIVISOR     1
+
+//*****************************************************************************
+//
+// Converts a set of CAN bit timing values into the value that needs to be
+// programmed into the CAN_BIT register to achieve those timings.
+//
+//*****************************************************************************
+#define CAN_BIT_VALUE(seg1, seg2, sjw)                                        \
+                                ((((seg1 - 1) << CAN_BIT_TSEG1_S) &           \
+                                  CAN_BIT_TSEG1_M) |                          \
+                                 (((seg2 - 1) << CAN_BIT_TSEG2_S) &           \
+                                  CAN_BIT_TSEG2_M) |                          \
+                                 (((sjw - 1) << CAN_BIT_SJW_S) &              \
+                                  CAN_BIT_SJW_M))
 
 //*****************************************************************************
 //
@@ -84,15 +103,22 @@
 //*****************************************************************************
 static const unsigned short g_usCANBitValues[] =
 {
-    0x1100, // TSEG2 2, TSEG1 2, SJW 1, Divide 5
-    0x1200, // TSEG2 2, TSEG1 3, SJW 1, Divide 6
-    0x2240, // TSEG2 3, TSEG1 3, SJW 2, Divide 7
-    0x2340, // TSEG2 3, TSEG1 4, SJW 2, Divide 8
-    0x3340, // TSEG2 4, TSEG1 4, SJW 2, Divide 9
-    0x3440, // TSEG2 4, TSEG1 5, SJW 2, Divide 10
-    0x3540, // TSEG2 4, TSEG1 6, SJW 2, Divide 11
-    0x3640, // TSEG2 4, TSEG1 7, SJW 2, Divide 12
-    0x3740  // TSEG2 4, TSEG1 8, SJW 2, Divide 13
+    CAN_BIT_VALUE(2, 1, 1),     // 4 clocks/bit
+    CAN_BIT_VALUE(3, 1, 1),     // 5 clocks/bit
+    CAN_BIT_VALUE(3, 2, 2),     // 6 clocks/bit
+    CAN_BIT_VALUE(4, 2, 2),     // 7 clocks/bit
+    CAN_BIT_VALUE(4, 3, 3),     // 8 clocks/bit
+    CAN_BIT_VALUE(5, 3, 3),     // 9 clocks/bit
+    CAN_BIT_VALUE(5, 4, 4),     // 10 clocks/bit
+    CAN_BIT_VALUE(6, 4, 4),     // 11 clocks/bit
+    CAN_BIT_VALUE(6, 5, 4),     // 12 clocks/bit
+    CAN_BIT_VALUE(7, 5, 4),     // 13 clocks/bit
+    CAN_BIT_VALUE(7, 6, 4),     // 14 clocks/bit
+    CAN_BIT_VALUE(8, 6, 4),     // 15 clocks/bit
+    CAN_BIT_VALUE(8, 7, 4),     // 16 clocks/bit
+    CAN_BIT_VALUE(9, 7, 4),     // 17 clocks/bit
+    CAN_BIT_VALUE(9, 8, 4),     // 18 clocks/bit
+    CAN_BIT_VALUE(10, 8, 4)     // 19 clocks/bit
 };
 
 //*****************************************************************************
@@ -207,7 +233,7 @@ CANIntNumberGet(unsigned long ulBase)
 static unsigned long
 CANRegRead(unsigned long ulRegAddress)
 {
-    volatile int iDelay;
+    volatile unsigned long ulDelay;
     unsigned long ulRetVal;
     unsigned long ulIntNumber;
     unsigned long ulReenableInts;
@@ -237,7 +263,7 @@ CANRegRead(unsigned long ulRegAddress)
     }
 
     //
-    // Trigger the inital read to the CAN controller.  The value returned at
+    // Trigger the initial read to the CAN controller.  The value returned at
     // this point is not valid.
     //
     HWREG(ulRegAddress);
@@ -245,7 +271,7 @@ CANRegRead(unsigned long ulRegAddress)
     //
     // This delay is necessary for the CAN have the correct data on the bus.
     //
-    for(iDelay = 0; iDelay < CAN_RW_DELAY; iDelay++)
+    for(ulDelay = 0; ulDelay < CAN_RW_DELAY; ulDelay++)
     {
     }
 
@@ -255,7 +281,7 @@ CANRegRead(unsigned long ulRegAddress)
     ulRetVal = HWREG(ulRegAddress);
 
     //
-    // Reenable CAN interrupts if they were enabled before this call.
+    // Enable CAN interrupts if they were enabled before this call.
     //
     if(ulReenableInts)
     {
@@ -291,10 +317,10 @@ CANRegRead(unsigned long ulRegAddress)
 static void
 CANRegWrite(unsigned long ulRegAddress, unsigned long ulRegValue)
 {
-    volatile int iDelay;
+    volatile unsigned long ulDelay;
 
     //
-    // Trigger the inital write to the CAN controller.  The value will not make
+    // Trigger the initial write to the CAN controller.  The value will not make
     // it out to the CAN controller for CAN_RW_DELAY cycles.
     //
     HWREG(ulRegAddress) = ulRegValue;
@@ -302,7 +328,7 @@ CANRegWrite(unsigned long ulRegAddress, unsigned long ulRegValue)
     //
     // Delay to allow the CAN controller to receive the new data.
     //
-    for(iDelay = 0; iDelay < CAN_RW_DELAY; iDelay++)
+    for(ulDelay = 0; ulDelay < CAN_RW_DELAY; ulDelay++)
     {
     }
 }
@@ -334,29 +360,29 @@ CANRegWrite(unsigned long ulRegAddress, unsigned long ulRegValue)
 //
 //*****************************************************************************
 static void
-CANDataRegWrite(unsigned char *pucData, unsigned long *pulRegister, int iSize)
+CANDataRegWrite(unsigned char *pucData, unsigned long *pulRegister,
+                unsigned long ulSize)
 {
-    int iIdx;
-    unsigned long ulValue;
+    unsigned long ulIdx, ulValue;
 
     //
     // Loop always copies 1 or 2 bytes per iteration.
     //
-    for(iIdx = 0; iIdx < iSize; )
+    for(ulIdx = 0; ulIdx < ulSize; )
     {
 
         //
         // Write out the data 16 bits at a time since this is how the registers
         // are aligned in memory.
         //
-        ulValue = pucData[iIdx++];
+        ulValue = pucData[ulIdx++];
 
         //
         // Only write the second byte if needed otherwise it will be zero.
         //
-        if(iIdx < iSize)
+        if(ulIdx < ulSize)
         {
-            ulValue |= (pucData[iIdx++] << 8);
+            ulValue |= (pucData[ulIdx++] << 8);
         }
         CANRegWrite((unsigned long)(pulRegister++), ulValue);
     }
@@ -389,15 +415,15 @@ CANDataRegWrite(unsigned char *pucData, unsigned long *pulRegister, int iSize)
 //
 //*****************************************************************************
 static void
-CANDataRegRead(unsigned char *pucData, unsigned long *pulRegister, int iSize)
+CANDataRegRead(unsigned char *pucData, unsigned long *pulRegister,
+               unsigned long ulSize)
 {
-    int iIdx;
-    unsigned long ulValue;
+    unsigned long ulIdx, ulValue;
 
     //
     // Loop always copies 1 or 2 bytes per iteration.
     //
-    for(iIdx = 0; iIdx < iSize; )
+    for(ulIdx = 0; ulIdx < ulSize; )
     {
         //
         // Read out the data 16 bits at a time since this is how the registers
@@ -408,14 +434,14 @@ CANDataRegRead(unsigned char *pucData, unsigned long *pulRegister, int iSize)
         //
         // Store the first byte.
         //
-        pucData[iIdx++] = (unsigned char)ulValue;
+        pucData[ulIdx++] = (unsigned char)ulValue;
 
         //
         // Only read the second byte if needed.
         //
-        if(iIdx < iSize)
+        if(ulIdx < ulSize)
         {
-            pucData[iIdx++] = (unsigned char)(ulValue >> 8);
+            pucData[ulIdx++] = (unsigned char)(ulValue >> 8);
         }
     }
 }
@@ -439,7 +465,7 @@ CANDataRegRead(unsigned char *pucData, unsigned long *pulRegister, int iSize)
 void
 CANInit(unsigned long ulBase)
 {
-    int iMsg;
+    unsigned long ulMsg;
 
     //
     // Check the arguments.
@@ -473,7 +499,7 @@ CANInit(unsigned long ulBase)
     //
     // Loop through to program all 32 message objects
     //
-    for(iMsg = 1; iMsg <= 32; iMsg++)
+    for(ulMsg = 1; ulMsg <= 32; ulMsg++)
     {
         //
         // Wait for busy bit to clear
@@ -485,7 +511,7 @@ CANInit(unsigned long ulBase)
         //
         // Initiate programming the message object
         //
-        CANRegWrite(ulBase + CAN_O_IF1CRQ, iMsg);
+        CANRegWrite(ulBase + CAN_O_IF1CRQ, ulMsg);
     }
 
     //
@@ -498,7 +524,7 @@ CANInit(unsigned long ulBase)
     //
     // Loop through to program all 32 message objects
     //
-    for(iMsg = 1; iMsg <= 32; iMsg++)
+    for(ulMsg = 1; ulMsg <= 32; ulMsg++)
     {
         //
         // Wait for busy bit to clear.
@@ -510,7 +536,7 @@ CANInit(unsigned long ulBase)
         //
         // Initiate programming the message object
         //
-        CANRegWrite(ulBase + CAN_O_IF1CRQ, iMsg);
+        CANRegWrite(ulBase + CAN_O_IF1CRQ, ulMsg);
     }
 
     //
@@ -602,7 +628,7 @@ CANDisable(unsigned long ulBase)
 void
 CANBitTimingGet(unsigned long ulBase, tCANBitClkParms *pClkParms)
 {
-    unsigned int uBitReg;
+    unsigned long ulBitReg;
 
     //
     // Check the arguments.
@@ -613,28 +639,30 @@ CANBitTimingGet(unsigned long ulBase, tCANBitClkParms *pClkParms)
     //
     // Read out all the bit timing values from the CAN controller registers.
     //
-    uBitReg = CANRegRead(ulBase + CAN_O_BIT);
+    ulBitReg = CANRegRead(ulBase + CAN_O_BIT);
 
     //
     // Set the phase 2 segment.
     //
-    pClkParms->uPhase2Seg = ((uBitReg & CAN_BIT_TSEG2_M) >> 12) + 1;
+    pClkParms->ulPhase2Seg =
+        ((ulBitReg & CAN_BIT_TSEG2_M) >> CAN_BIT_TSEG2_S) + 1;
 
     //
     // Set the phase 1 segment.
     //
-    pClkParms->uSyncPropPhase1Seg = ((uBitReg & CAN_BIT_TSEG1_M) >> 8) + 1;
+    pClkParms->ulSyncPropPhase1Seg =
+        ((ulBitReg & CAN_BIT_TSEG1_M) >> CAN_BIT_TSEG1_S) + 1;
 
     //
-    // Set the sychronous jump width.
+    // Set the synchronous jump width.
     //
-    pClkParms->uSJW = ((uBitReg & CAN_BIT_SJW_M) >> 6) + 1;
+    pClkParms->ulSJW = ((ulBitReg & CAN_BIT_SJW_M) >> CAN_BIT_SJW_S) + 1;
 
     //
     // Set the pre-divider for the CAN bus bit clock.
     //
-    pClkParms->uQuantumPrescaler =
-        ((uBitReg & CAN_BIT_BRP_M) |
+    pClkParms->ulQuantumPrescaler =
+        ((ulBitReg & CAN_BIT_BRP_M) |
          ((CANRegRead(ulBase + CAN_O_BRPE) & CAN_BRPE_BRPE_M) << 6)) + 1;
 }
 
@@ -651,12 +679,14 @@ CANBitTimingGet(unsigned long ulBase, tCANBitClkParms *pClkParms)
 //! \e ulBitRate parameter based on the \e ulSourceClock parameter.  Since the
 //! CAN clock is based off of the system clock the calling function should pass
 //! in the source clock rate either by retrieving it from SysCtlClockGet() or
-//! using a specific value in Hz.  The CAN bit clock is calculated to be an
-//! average timing value that should work for most systems.  If tighter timing
-//! requirements are needed, then the CANBitTimingSet() function is available
-//! for full customization of all of the CAN bit timing values.  Since not all
-//! bit rates can be matched exactly, the bit rate is set to the value closest
-//! to the desired bit rate without being higher than the \e ulBitRate value.
+//! using a specific value in Hz.  The CAN bit timing is calculated assuming a
+//! minimal amount of propagation delay, which will work for most cases where
+//! the network length is short.  If tighter timing requirements or longer
+//! network lengths are needed, then the CANBitTimingSet() function is
+//! available for full customization of all of the CAN bit timing values.
+//! Since not all bit rates can be matched exactly, the bit rate is set to the
+//! value closest to the desired bit rate without being higher than the
+//! \e ulBitRate value.
 //!
 //! \note On some devices the source clock is fixed at 8MHz so the
 //! \e ulSourceClock should be set to 8000000.
@@ -676,22 +706,24 @@ CANBitRateSet(unsigned long ulBase, unsigned long ulSourceClock,
     unsigned long ulRegValue;
     unsigned short usCANCTL;
 
+    //
+    // Check the arguments.
+    //
+    ASSERT(CANBaseValid(ulBase));
+    ASSERT(ulSourceClock != 0);
     ASSERT(ulBitRate != 0);
 
     //
-    // Caclulate the desired clock rate.
+    // Calculate the desired clock rate.
     //
     ulDesiredRatio = ulSourceClock / ulBitRate;
 
     //
-    // If the ratio of CAN bit rate to processor clock is too small or too
-    // large then return 0 indicating that no bit rate was set.
+    // Make sure that the ratio of CAN bit rate to processor clock is not too
+    // small or too large.
     //
-    if((ulDesiredRatio > (CAN_MIN_PRE_DIVISOR * CAN_MIN_BIT_DIVISOR)) ||
-       (ulDesiredRatio < CAN_MIN_BIT_DIVISOR))
-    {
-        return(0);
-    }
+    ASSERT(ulDesiredRatio <= (CAN_MAX_PRE_DIVISOR * CAN_MAX_BIT_DIVISOR));
+    ASSERT(ulDesiredRatio >= (CAN_MIN_PRE_DIVISOR * CAN_MIN_BIT_DIVISOR));
 
     //
     // Make sure that the Desired Ratio is not too large.  This enforces the
@@ -705,7 +737,7 @@ CANBitRateSet(unsigned long ulBase, unsigned long ulSourceClock,
     //
     // Check all possible values to find a matching value.
     //
-    while(ulDesiredRatio <= CAN_MAX_PRE_DIVISOR * CAN_MAX_BIT_DIVISOR)
+    while(ulDesiredRatio <= (CAN_MAX_PRE_DIVISOR * CAN_MAX_BIT_DIVISOR))
     {
         //
         // Loop through all possible CAN bit divisors.
@@ -719,7 +751,7 @@ CANBitRateSet(unsigned long ulBase, unsigned long ulSourceClock,
             ulPreDivide = ulDesiredRatio / ulCANBits;
 
             //
-            // If the caculated divisors match the desired clock ratio then
+            // If the calculated divisors match the desired clock ratio then
             // return these bit rate and set the CAN bit timing.
             //
             if((ulPreDivide * ulCANBits) == ulDesiredRatio)
@@ -733,17 +765,17 @@ CANBitRateSet(unsigned long ulBase, unsigned long ulSourceClock,
                 //
                 // To set the bit timing register, the controller must be placed
                 // in init mode (if not already), and also configuration change
-                // bit enabled.  The stat of the register should be saved
+                // bit enabled.  The state of the register should be saved
                 // so it can be restored.
                 //
                 usCANCTL = CANRegRead(ulBase + CAN_O_CTL);
-                CANRegWrite(ulBase + CAN_O_CTL, usCANCTL | CAN_CTL_INIT |
-                                                CAN_CTL_CCE);
+                CANRegWrite(ulBase + CAN_O_CTL,
+                            usCANCTL | CAN_CTL_INIT | CAN_CTL_CCE);
 
                 //
                 // Now add in the pre-scalar on the bit rate.
                 //
-                ulRegValue |= ((ulPreDivide - 1)& CAN_BIT_BRP_M);
+                ulRegValue |= ((ulPreDivide - 1) & CAN_BIT_BRP_M);
 
                 //
                 // Set the clock bits in the and the lower bits of the
@@ -775,6 +807,11 @@ CANBitRateSet(unsigned long ulBase, unsigned long ulSourceClock,
         //
         ulDesiredRatio++;
     }
+
+    //
+    // A valid combination could not be found, so return 0 to indicate that the
+    // bit rate was not changed.
+    //
     return(0);
 }
 
@@ -789,16 +826,16 @@ CANBitRateSet(unsigned long ulBase, unsigned long ulSourceClock,
 //! Propagation segment, Phase Buffer 1 segment, Phase Buffer 2 segment, and
 //! the Synchronization Jump Width.  The values for Propagation and Phase
 //! Buffer 1 segments are derived from the combination
-//! \e pClkParms->uSyncPropPhase1Seg parameter.  Phase Buffer 2 is determined
-//! from the \e pClkParms->uPhase2Seg parameter.  These two parameters, along
-//! with \e pClkParms->uSJW are based in units of bit time quanta.  The actual
-//! quantum time is determined by the \e pClkParms->uQuantumPrescaler value,
+//! \e pClkParms->ulSyncPropPhase1Seg parameter.  Phase Buffer 2 is determined
+//! from the \e pClkParms->ulPhase2Seg parameter.  These two parameters, along
+//! with \e pClkParms->ulSJW are based in units of bit time quanta.  The actual
+//! quantum time is determined by the \e pClkParms->ulQuantumPrescaler value,
 //! which specifies the divisor for the CAN module clock.
 //!
 //! The total bit time, in quanta, will be the sum of the two Seg parameters,
 //! as follows:
 //!
-//! bit_time_q = uSyncPropPhase1Seg + uPhase2Seg + 1
+//! bit_time_q = ulSyncPropPhase1Seg + ulPhase2Seg + 1
 //!
 //! Note that the Sync_Seg is always one quantum in duration, and will be added
 //! to derive the correct duration of Prop_Seg and Phase1_Seg.
@@ -806,10 +843,10 @@ CANBitRateSet(unsigned long ulBase, unsigned long ulSourceClock,
 //! The equation to determine the actual bit rate is as follows:
 //!
 //! CAN Clock /
-//! ((\e uSyncPropPhase1Seg + \e uPhase2Seg + 1) * (\e uQuantumPrescaler))
+//! ((\e ulSyncPropPhase1Seg + \e ulPhase2Seg + 1) * (\e ulQuantumPrescaler))
 //!
-//! This means that with \e uSyncPropPhase1Seg = 4, \e uPhase2Seg = 1,
-//! \e uQuantumPrescaler = 2 and an 8 MHz CAN clock, that the bit rate will be
+//! This means that with \e ulSyncPropPhase1Seg = 4, \e ulPhase2Seg = 1,
+//! \e ulQuantumPrescaler = 2 and an 8 MHz CAN clock, that the bit rate will be
 //! (8 MHz) / ((5 + 2 + 1) * 2) or 500 Kbit/sec.
 //!
 //! This function replaces the original CANSetBitTiming() API and performs the
@@ -822,8 +859,7 @@ CANBitRateSet(unsigned long ulBase, unsigned long ulSourceClock,
 void
 CANBitTimingSet(unsigned long ulBase, tCANBitClkParms *pClkParms)
 {
-    unsigned int uBitReg;
-    unsigned int uSavedInit;
+    unsigned long ulBitReg, ulSavedInit;
 
     //
     // Check the arguments.
@@ -834,60 +870,63 @@ CANBitTimingSet(unsigned long ulBase, tCANBitClkParms *pClkParms)
     //
     // The phase 1 segment must be in the range from 2 to 16.
     //
-    ASSERT((pClkParms->uSyncPropPhase1Seg >= 2) &&
-           (pClkParms->uSyncPropPhase1Seg <= 16));
+    ASSERT((pClkParms->ulSyncPropPhase1Seg >= 2) &&
+           (pClkParms->ulSyncPropPhase1Seg <= 16));
 
     //
     // The phase 2 segment must be in the range from 1 to 8.
     //
-    ASSERT((pClkParms->uPhase2Seg >= 1) && (pClkParms->uPhase2Seg <= 8));
+    ASSERT((pClkParms->ulPhase2Seg >= 1) && (pClkParms->ulPhase2Seg <= 8));
 
     //
     // The synchronous jump windows must be in the range from 1 to 4.
     //
-    ASSERT((pClkParms->uSJW >= 1) && (pClkParms->uSJW <= 4));
+    ASSERT((pClkParms->ulSJW >= 1) && (pClkParms->ulSJW <= 4));
 
     //
     // The CAN clock pre-divider must be in the range from 1 to 1024.
     //
-    ASSERT((pClkParms->uQuantumPrescaler <= 1024) &&
-           (pClkParms->uQuantumPrescaler >= 1));
+    ASSERT((pClkParms->ulQuantumPrescaler <= 1024) &&
+           (pClkParms->ulQuantumPrescaler >= 1));
 
     //
     // To set the bit timing register, the controller must be placed in init
     // mode (if not already), and also configuration change bit enabled.  State
     // of the init bit should be saved so it can be restored at the end.
     //
-    uSavedInit = CANRegRead(ulBase + CAN_O_CTL);
-    CANRegWrite(ulBase + CAN_O_CTL, uSavedInit | CAN_CTL_INIT | CAN_CTL_CCE);
+    ulSavedInit = CANRegRead(ulBase + CAN_O_CTL);
+    CANRegWrite(ulBase + CAN_O_CTL, ulSavedInit | CAN_CTL_INIT | CAN_CTL_CCE);
 
     //
     // Set the bit fields of the bit timing register according to the parms.
     //
-    uBitReg = ((pClkParms->uPhase2Seg - 1) << 12) & CAN_BIT_TSEG2_M;
-    uBitReg |= ((pClkParms->uSyncPropPhase1Seg - 1) << 8) & CAN_BIT_TSEG1_M;
-    uBitReg |= ((pClkParms->uSJW - 1) << 6) & CAN_BIT_SJW_M;
-    uBitReg |= (pClkParms->uQuantumPrescaler - 1) & CAN_BIT_BRP_M;
-    CANRegWrite(ulBase + CAN_O_BIT, uBitReg);
+    ulBitReg = (((pClkParms->ulPhase2Seg - 1) << CAN_BIT_TSEG2_S) &
+                CAN_BIT_TSEG2_M);
+    ulBitReg |= (((pClkParms->ulSyncPropPhase1Seg - 1) << CAN_BIT_TSEG1_S) &
+                 CAN_BIT_TSEG1_M);
+    ulBitReg |= ((pClkParms->ulSJW - 1) << CAN_BIT_SJW_S) & CAN_BIT_SJW_M;
+    ulBitReg |= (pClkParms->ulQuantumPrescaler - 1) & CAN_BIT_BRP_M;
+    CANRegWrite(ulBase + CAN_O_BIT, ulBitReg);
 
     //
     // Set the divider upper bits in the extension register.
     //
     CANRegWrite(ulBase + CAN_O_BRPE,
-                ((pClkParms->uQuantumPrescaler - 1) >> 6) & CAN_BRPE_BRPE_M);
+                ((pClkParms->ulQuantumPrescaler - 1) >> 6) & CAN_BRPE_BRPE_M);
+
     //
     // Clear the config change bit, and restore the init bit.
     //
-    uSavedInit &= ~CAN_CTL_CCE;
+    ulSavedInit &= ~CAN_CTL_CCE;
 
     //
     // If Init was not set before, then clear it.
     //
-    if(uSavedInit & CAN_CTL_INIT)
+    if(ulSavedInit & CAN_CTL_INIT)
     {
-        uSavedInit &= ~CAN_CTL_INIT;
+        ulSavedInit &= ~CAN_CTL_INIT;
     }
-    CANRegWrite(ulBase + CAN_O_CTL, uSavedInit);
+    CANRegWrite(ulBase + CAN_O_CTL, ulSavedInit);
 }
 
 //*****************************************************************************
@@ -971,15 +1010,15 @@ CANIntUnregister(unsigned long ulBase)
     //
     ulIntNumber = CANIntNumberGet(ulBase);
 
-    //
-    // Register the interrupt handler.
-    //
-    IntUnregister(ulIntNumber);
-
     //
     // Disable the CAN interrupt.
     //
     IntDisable(ulIntNumber);
+
+    //
+    // Register the interrupt handler.
+    //
+    IntUnregister(ulIntNumber);
 }
 
 //*****************************************************************************
@@ -1145,6 +1184,7 @@ CANIntStatus(unsigned long ulBase, tCANIntStsReg eIntStsReg)
             break;
         }
     }
+
     //
     // Return the interrupt status value
     //
@@ -1172,14 +1212,14 @@ CANIntStatus(unsigned long ulBase, tCANIntStsReg eIntStsReg)
 //! using CANStatusGet().  A specific message object interrupt is normally
 //! cleared by reading the message object using CANMessageGet().
 //!
-//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
-//! several clock cycles before the interrupt source is actually cleared.
+//! \note Because there is a write buffer in the Cortex-M3 processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
 //! Therefore, it is recommended that the interrupt source be cleared early in
 //! the interrupt handler (as opposed to the very last action) to avoid
 //! returning from the interrupt handler before the interrupt source is
 //! actually cleared.  Failure to do so may result in the interrupt handler
-//! being immediately reentered (since NVIC still sees the interrupt source
-//! asserted).
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
 //!
 //! \return None.
 //
@@ -1556,14 +1596,13 @@ CANErrCntrGet(unsigned long ulBase, unsigned long *pulRxCount,
 //! -# Set \e pMsgObject->ulMsgIDMask bits that should be used for masking
 //! during comparison.
 //! -# Set \e pMsgObject->ulFlags as follows:
-//!   - Set \b MSG_OBJ_TX_INT_ENABLE flag to be interrupted when the data frame
+//!   - Set \b MSG_OBJ_RX_INT_ENABLE flag to be interrupted when the data frame
 //!   is received.
 //!   - Set \b MSG_OBJ_USE_ID_FILTER flag to enable identifier based filtering.
 //! -# Set \e pMsgObject->ulMsgLen to the number of bytes in the expected data
 //! frame.
-//! -# The buffer pointed to by \e pMsgObject->pucMsgData  and
-//! \e pMsgObject->ulMsgLen are not used by this call as no data is present at
-//! the time of the call.
+//! -# The buffer pointed to by \e pMsgObject->pucMsgData is not used by this
+//! call as no data is present at the time of the call.
 //! -# Call this function with \e ulObjID set to one of the 32 object buffers.
 //!
 //! If you specify a message object buffer that already contains a message
@@ -1577,8 +1616,8 @@ CANMessageSet(unsigned long ulBase, unsigned long ulObjID,
               tCANMsgObject *pMsgObject, tMsgObjType eMsgType)
 {
     unsigned short usCmdMaskReg;
-    unsigned short usMaskReg[2];
-    unsigned short usArbReg[2];
+    unsigned short usMaskReg0, usMaskReg1;
+    unsigned short usArbReg0, usArbReg1;
     unsigned short usMsgCtrl;
     tBoolean bTransferData;
     tBoolean bUseExtendedID;
@@ -1630,10 +1669,11 @@ CANMessageSet(unsigned long ulBase, unsigned long ulObjID,
     // Initialize the values to a known state before filling them in based on
     // the type of message object that is being configured.
     //
-    usArbReg[0] = 0;
+    usArbReg0 = 0;
+    usArbReg1 = 0;
     usMsgCtrl = 0;
-    usMaskReg[0] = 0;
-    usMaskReg[1] = 0;
+    usMaskReg0 = 0;
+    usMaskReg1 = 0;
 
     switch(eMsgType)
     {
@@ -1646,7 +1686,7 @@ CANMessageSet(unsigned long ulBase, unsigned long ulObjID,
             // Set the TXRQST bit and the reset the rest of the register.
             //
             usMsgCtrl |= CAN_IF1MCTL_TXRQST;
-            usArbReg[1] = CAN_IF1ARB2_DIR;
+            usArbReg1 = CAN_IF1ARB2_DIR;
             bTransferData = 1;
             break;
         }
@@ -1660,7 +1700,7 @@ CANMessageSet(unsigned long ulBase, unsigned long ulObjID,
             // Set the TXRQST bit and the reset the rest of the register.
             //
             usMsgCtrl |= CAN_IF1MCTL_TXRQST;
-            usArbReg[1] = 0;
+            usArbReg1 = 0;
             break;
         }
 
@@ -1670,10 +1710,10 @@ CANMessageSet(unsigned long ulBase, unsigned long ulObjID,
         case MSG_OBJ_TYPE_RX:
         {
             //
-            // This clears the DIR bit along with everthing else.  The TXRQST
-            // bit was cleard by defaulting usMsgCtrl to 0.
+            // This clears the DIR bit along with everything else.  The TXRQST
+            // bit was cleared by defaulting usMsgCtrl to 0.
             //
-            usArbReg[1] = 0;
+            usArbReg1 = 0;
             break;
         }
 
@@ -1684,9 +1724,9 @@ CANMessageSet(unsigned long ulBase, unsigned long ulObjID,
         {
             //
             // The DIR bit is set to one for remote receivers.  The TXRQST bit
-            // was cleard by defaulting usMsgCtrl to 0.
+            // was cleared by defaulting usMsgCtrl to 0.
             //
-            usArbReg[1] = CAN_IF1ARB2_DIR;
+            usArbReg1 = CAN_IF1ARB2_DIR;
 
             //
             // Set this object so that it only indicates that a remote frame
@@ -1698,8 +1738,8 @@ CANMessageSet(unsigned long ulBase, unsigned long ulObjID,
             //
             // Use the full Identifier by default.
             //
-            usMaskReg[0] = 0xffff;
-            usMaskReg[1] = 0x1fff;
+            usMaskReg0 = 0xffff;
+            usMaskReg1 = 0x1fff;
 
             //
             // Make sure to send the mask to the message object.
@@ -1716,7 +1756,7 @@ CANMessageSet(unsigned long ulBase, unsigned long ulObjID,
             //
             // Oddly the DIR bit is set to one for remote receivers.
             //
-            usArbReg[1] = CAN_IF1ARB2_DIR;
+            usArbReg1 = CAN_IF1ARB2_DIR;
 
             //
             // Set this object to auto answer if a matching identifier is seen.
@@ -1750,8 +1790,8 @@ CANMessageSet(unsigned long ulBase, unsigned long ulObjID,
             //
             // Set the 29 bits of Identifier mask that were requested.
             //
-            usMaskReg[0] = pMsgObject->ulMsgIDMask & CAN_IF1MSK1_IDMSK_M;
-            usMaskReg[1] = ((pMsgObject->ulMsgIDMask >> 16) &
+            usMaskReg0 = pMsgObject->ulMsgIDMask & CAN_IF1MSK1_IDMSK_M;
+            usMaskReg1 = ((pMsgObject->ulMsgIDMask >> 16) &
                             CAN_IF1MSK2_IDMSK_M);
         }
         else
@@ -1759,13 +1799,13 @@ CANMessageSet(unsigned long ulBase, unsigned long ulObjID,
             //
             // Lower 16 bit are unused so set them to zero.
             //
-            usMaskReg[0] = 0;
+            usMaskReg0 = 0;
 
             //
             // Put the 11 bit Mask Identifier into the upper bits of the field
             // in the register.
             //
-            usMaskReg[1] = ((pMsgObject->ulMsgIDMask << 2) &
+            usMaskReg1 = ((pMsgObject->ulMsgIDMask << 2) &
                             CAN_IF1MSK2_IDMSK_M);
         }
     }
@@ -1776,7 +1816,7 @@ CANMessageSet(unsigned long ulBase, unsigned long ulObjID,
     if((pMsgObject->ulFlags & MSG_OBJ_USE_EXT_FILTER) ==
        MSG_OBJ_USE_EXT_FILTER)
     {
-        usMaskReg[1] |= CAN_IF1MSK2_MXTD;
+        usMaskReg1 |= CAN_IF1MSK2_MXTD;
     }
 
     //
@@ -1785,7 +1825,7 @@ CANMessageSet(unsigned long ulBase, unsigned long ulObjID,
     if((pMsgObject->ulFlags & MSG_OBJ_USE_DIR_FILTER) ==
        MSG_OBJ_USE_DIR_FILTER)
     {
-        usMaskReg[1] |= CAN_IF1MSK2_MDIR;
+        usMaskReg1 |= CAN_IF1MSK2_MDIR;
     }
 
     if(pMsgObject->ulFlags & (MSG_OBJ_USE_ID_FILTER | MSG_OBJ_USE_DIR_FILTER |
@@ -1797,7 +1837,7 @@ CANMessageSet(unsigned long ulBase, unsigned long ulObjID,
         usMsgCtrl |= CAN_IF1MCTL_UMASK;
 
         //
-        // Set the MASK bit so that this gets trasferred to the Message Object.
+        // Set the MASK bit so that this gets transferred to the Message Object.
         //
         usCmdMaskReg |= CAN_IF1CMSK_MASK;
     }
@@ -1815,13 +1855,13 @@ CANMessageSet(unsigned long ulBase, unsigned long ulObjID,
         //
         // Set the 29 bit version of the Identifier for this message object.
         //
-        usArbReg[0] |= pMsgObject->ulMsgID & CAN_IF1ARB1_ID_M;
-        usArbReg[1] |= (pMsgObject->ulMsgID >> 16) & CAN_IF1ARB2_ID_M;
+        usArbReg0 |= pMsgObject->ulMsgID & CAN_IF1ARB1_ID_M;
+        usArbReg1 |= (pMsgObject->ulMsgID >> 16) & CAN_IF1ARB2_ID_M;
 
         //
         // Mark the message as valid and set the extended ID bit.
         //
-        usArbReg[1] |= CAN_IF1ARB2_MSGVAL | CAN_IF1ARB2_XTD;
+        usArbReg1 |= CAN_IF1ARB2_MSGVAL | CAN_IF1ARB2_XTD;
     }
     else
     {
@@ -1829,19 +1869,27 @@ CANMessageSet(unsigned long ulBase, unsigned long ulObjID,
         // Set the 11 bit version of the Identifier for this message object.
         // The lower 18 bits are set to zero.
         //
-        usArbReg[1] |= (pMsgObject->ulMsgID << 2) & CAN_IF1ARB2_ID_M;
+        usArbReg1 |= (pMsgObject->ulMsgID << 2) & CAN_IF1ARB2_ID_M;
 
         //
         // Mark the message as valid.
         //
-        usArbReg[1] |= CAN_IF1ARB2_MSGVAL;
+        usArbReg1 |= CAN_IF1ARB2_MSGVAL;
     }
 
     //
     // Set the data length since this is set for all transfers.  This is also a
     // single transfer and not a FIFO transfer so set EOB bit.
     //
-    usMsgCtrl |= (pMsgObject->ulMsgLen & CAN_IF1MCTL_DLC_M) | CAN_IF1MCTL_EOB;
+    usMsgCtrl |= (pMsgObject->ulMsgLen & CAN_IF1MCTL_DLC_M);
+
+    //
+    // Mark this as the last entry if this is not the last entry in a FIFO.
+    //
+    if((pMsgObject->ulFlags & MSG_OBJ_FIFO) == 0)
+    {
+        usMsgCtrl |= CAN_IF1MCTL_EOB;
+    }
 
     //
     // Enable transmit interrupts if they should be enabled.
@@ -1873,18 +1921,16 @@ CANMessageSet(unsigned long ulBase, unsigned long ulObjID,
     // Write out the registers to program the message object.
     //
     CANRegWrite(ulBase + CAN_O_IF1CMSK, usCmdMaskReg);
-    CANRegWrite(ulBase + CAN_O_IF1MSK1, usMaskReg[0]);
-    CANRegWrite(ulBase + CAN_O_IF1MSK2, usMaskReg[1]);
-    CANRegWrite(ulBase + CAN_O_IF1ARB1, usArbReg[0]);
-    CANRegWrite(ulBase + CAN_O_IF1ARB2, usArbReg[1]);
+    CANRegWrite(ulBase + CAN_O_IF1MSK1, usMaskReg0);
+    CANRegWrite(ulBase + CAN_O_IF1MSK2, usMaskReg1);
+    CANRegWrite(ulBase + CAN_O_IF1ARB1, usArbReg0);
+    CANRegWrite(ulBase + CAN_O_IF1ARB2, usArbReg1);
     CANRegWrite(ulBase + CAN_O_IF1MCTL, usMsgCtrl);
 
     //
-    // Transfer the message object to the message object specifiec by ulObjID.
+    // Transfer the message object to the message object specified by ulObjID.
     //
     CANRegWrite(ulBase + CAN_O_IF1CRQ, ulObjID & CAN_IF1CRQ_MNUM_M);
-
-    return;
 }
 
 //*****************************************************************************
@@ -1928,8 +1974,8 @@ CANMessageGet(unsigned long ulBase, unsigned long ulObjID,
               tCANMsgObject *pMsgObject, tBoolean bClrPendingInt)
 {
     unsigned short usCmdMaskReg;
-    unsigned short usMaskReg[2];
-    unsigned short usArbReg[2];
+    unsigned short usMaskReg0, usMaskReg1;
+    unsigned short usArbReg0, usArbReg1;
     unsigned short usMsgCtrl;
 
     //
@@ -1959,7 +2005,7 @@ CANMessageGet(unsigned long ulBase, unsigned long ulObjID,
     CANRegWrite(ulBase + CAN_O_IF2CMSK, usCmdMaskReg);
 
     //
-    // Transfer the message object to the message object specifiec by ulObjID.
+    // Transfer the message object to the message object specified by ulObjID.
     //
     CANRegWrite(ulBase + CAN_O_IF2CRQ, ulObjID & CAN_IF1CRQ_MNUM_M);
 
@@ -1973,10 +2019,10 @@ CANMessageGet(unsigned long ulBase, unsigned long ulObjID,
     //
     // Read out the IF Registers.
     //
-    usMaskReg[0] = CANRegRead(ulBase + CAN_O_IF2MSK1);
-    usMaskReg[1] = CANRegRead(ulBase + CAN_O_IF2MSK2);
-    usArbReg[0] = CANRegRead(ulBase + CAN_O_IF2ARB1);
-    usArbReg[1] = CANRegRead(ulBase + CAN_O_IF2ARB2);
+    usMaskReg0 = CANRegRead(ulBase + CAN_O_IF2MSK1);
+    usMaskReg1 = CANRegRead(ulBase + CAN_O_IF2MSK2);
+    usArbReg0 = CANRegRead(ulBase + CAN_O_IF2ARB1);
+    usArbReg1 = CANRegRead(ulBase + CAN_O_IF2ARB2);
     usMsgCtrl = CANRegRead(ulBase + CAN_O_IF2MCTL);
 
     pMsgObject->ulFlags = MSG_OBJ_NO_FLAGS;
@@ -1984,10 +2030,8 @@ CANMessageGet(unsigned long ulBase, unsigned long ulObjID,
     //
     // Determine if this is a remote frame by checking the TXRQST and DIR bits.
     //
-    if((!(usMsgCtrl & CAN_IF1MCTL_TXRQST) &&
-        (usArbReg[1] & CAN_IF1ARB2_DIR)) ||
-       ((usMsgCtrl & CAN_IF1MCTL_TXRQST) &&
-        (!(usArbReg[1] & CAN_IF1ARB2_DIR))))
+    if((!(usMsgCtrl & CAN_IF1MCTL_TXRQST) && (usArbReg1 & CAN_IF1ARB2_DIR)) ||
+       ((usMsgCtrl & CAN_IF1MCTL_TXRQST) && (!(usArbReg1 & CAN_IF1ARB2_DIR))))
     {
         pMsgObject->ulFlags |= MSG_OBJ_REMOTE_FRAME;
     }
@@ -1996,13 +2040,13 @@ CANMessageGet(unsigned long ulBase, unsigned long ulObjID,
     // Get the identifier out of the register, the format depends on size of
     // the mask.
     //
-    if(usArbReg[1] & CAN_IF1ARB2_XTD)
+    if(usArbReg1 & CAN_IF1ARB2_XTD)
     {
         //
         // Set the 29 bit version of the Identifier for this message object.
         //
-        pMsgObject->ulMsgID = ((usArbReg[1] & CAN_IF1ARB2_ID_M) << 16) |
-            usArbReg[0];
+        pMsgObject->ulMsgID = ((usArbReg1 & CAN_IF1ARB2_ID_M) << 16) |
+            usArbReg0;
 
         pMsgObject->ulFlags |= MSG_OBJ_EXTENDED_ID;
     }
@@ -2011,7 +2055,7 @@ CANMessageGet(unsigned long ulBase, unsigned long ulObjID,
         //
         // The Identifier is an 11 bit value.
         //
-        pMsgObject->ulMsgID = (usArbReg[1] & CAN_IF1ARB2_ID_M) >> 2;
+        pMsgObject->ulMsgID = (usArbReg1 & CAN_IF1ARB2_ID_M) >> 2;
     }
 
     //
@@ -2027,13 +2071,14 @@ CANMessageGet(unsigned long ulBase, unsigned long ulObjID,
     //
     if(usMsgCtrl & CAN_IF1MCTL_UMASK)
     {
-        if(usArbReg[1] & CAN_IF1ARB2_XTD)
+        if(usArbReg1 & CAN_IF1ARB2_XTD)
         {
             //
             // The Identifier Mask is assumed to also be a 29 bit value.
             //
             pMsgObject->ulMsgIDMask =
-                ((usMaskReg[1] & CAN_IF1MSK2_IDMSK_M) << 16) | usMaskReg[0];
+                ((usMaskReg1 & CAN_IF1MSK2_IDMSK_M) << 16) | usMaskReg0;
+
             //
             // If this is a fully specified Mask and a remote frame then don't
             // set the MSG_OBJ_USE_ID_FILTER because the ID was not really
@@ -2050,7 +2095,7 @@ CANMessageGet(unsigned long ulBase, unsigned long ulObjID,
             //
             // The Identifier Mask is assumed to also be an 11 bit value.
             //
-            pMsgObject->ulMsgIDMask = ((usMaskReg[1] & CAN_IF1MSK2_IDMSK_M) >>
+            pMsgObject->ulMsgIDMask = ((usMaskReg1 & CAN_IF1MSK2_IDMSK_M) >>
                                        2);
 
             //
@@ -2068,7 +2113,7 @@ CANMessageGet(unsigned long ulBase, unsigned long ulObjID,
         //
         // Indicate if the extended bit was used in filtering.
         //
-        if(usMaskReg[1] & CAN_IF1MSK2_MXTD)
+        if(usMaskReg1 & CAN_IF1MSK2_MXTD)
         {
             pMsgObject->ulFlags |= MSG_OBJ_USE_EXT_FILTER;
         }
@@ -2076,14 +2121,14 @@ CANMessageGet(unsigned long ulBase, unsigned long ulObjID,
         //
         // Indicate if direction filtering was enabled.
         //
-        if(usMaskReg[1] & CAN_IF1MSK2_MDIR)
+        if(usMaskReg1 & CAN_IF1MSK2_MDIR)
         {
             pMsgObject->ulFlags |= MSG_OBJ_USE_DIR_FILTER;
         }
     }
 
     //
-    // Set the interupt flags.
+    // Set the interrupt flags.
     //
     if(usMsgCtrl & CAN_IF1MCTL_TXIE)
     {
@@ -2124,7 +2169,7 @@ CANMessageGet(unsigned long ulBase, unsigned long ulObjID,
         CANRegWrite(ulBase + CAN_O_IF2CMSK, CAN_IF1CMSK_NEWDAT);
 
         //
-        // Transfer the message object to the message object specifiec by
+        // Transfer the message object to the message object specified by
         // ulObjID.
         //
         CANRegWrite(ulBase + CAN_O_IF2CRQ, ulObjID & CAN_IF1CRQ_MNUM_M);
diff --git a/src/platform/lm3s/can.h b/src/platform/lm3s/driverlib/can.h
similarity index 59%
rename from src/platform/lm3s/can.h
rename to src/platform/lm3s/driverlib/can.h
index c81edff9..b0c6c60a 100755
--- a/src/platform/lm3s/can.h
+++ b/src/platform/lm3s/driverlib/can.h
@@ -2,26 +2,23 @@
 //
 // can.h - Defines and Macros for the CAN controller.
 //
-// Copyright (c) 2006-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2006-2011 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
+// This is part of revision 7611 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -54,77 +51,80 @@ extern "C"
 
 //*****************************************************************************
 //
-//! These are the flags used by the tCANMsgObject variable when calling the
-//! CANMessageSet() and CANMessageGet() functions.
+// These are the flags used by the tCANMsgObject.ulFlags value when calling the
+// CANMessageSet() and CANMessageGet() functions.
 //
 //*****************************************************************************
-typedef enum
-{
-    //
-    //! This indicates that transmit interrupts should be enabled, or are
-    //! enabled.
-    //
-    MSG_OBJ_TX_INT_ENABLE =     0x00000001,
 
-    //
-    //! This indicates that receive interrupts should be enabled, or are
-    //! enabled.
-    //
-    MSG_OBJ_RX_INT_ENABLE =     0x00000002,
+//
+//! This definition is used with the tCANMsgObject ulFlags value and indicates
+//! that transmit interrupts should be enabled, or are enabled.
+//
+#define MSG_OBJ_TX_INT_ENABLE   0x00000001
 
-    //
-    //! This indicates that a message object will use or is using an extended
-    //! identifier.
-    //
-    MSG_OBJ_EXTENDED_ID =       0x00000004,
+//
+//! This indicates that receive interrupts should be enabled, or are
+//! enabled.
+//
+#define MSG_OBJ_RX_INT_ENABLE   0x00000002
 
-    //
-    //! This indicates that a message object will use or is using filtering
-    //! based on the object's message identifier.
-    //
-    MSG_OBJ_USE_ID_FILTER =     0x00000008,
+//
+//! This indicates that a message object will use or is using an extended
+//! identifier.
+//
+#define MSG_OBJ_EXTENDED_ID     0x00000004
 
-    //
-    //! This indicates that new data was available in the message object.
-    //
-    MSG_OBJ_NEW_DATA =          0x00000080,
+//
+//! This indicates that a message object will use or is using filtering
+//! based on the object's message identifier.
+//
+#define MSG_OBJ_USE_ID_FILTER   0x00000008
 
-    //
-    //! This indicates that data was lost since this message object was last
-    //! read.
-    //
-    MSG_OBJ_DATA_LOST =         0x00000100,
+//
+//! This indicates that new data was available in the message object.
+//
+#define MSG_OBJ_NEW_DATA        0x00000080
 
-    //
-    //! This indicates that a message object will use or is using filtering
-    //! based on the direction of the transfer.  If the direction filtering is
-    //! used, then ID filtering must also be enabled.
-    //
-    MSG_OBJ_USE_DIR_FILTER =    (0x00000010 | MSG_OBJ_USE_ID_FILTER),
+//
+//! This indicates that data was lost since this message object was last
+//! read.
+//
+#define MSG_OBJ_DATA_LOST       0x00000100
 
-    //
-    //! This indicates that a message object will use or is using message
-    //! identifier filtering based on the extended identifier.  If the extended
-    //! identifier filtering is used, then ID filtering must also be enabled.
-    //
-    MSG_OBJ_USE_EXT_FILTER =    (0x00000020 | MSG_OBJ_USE_ID_FILTER),
+//
+//! This indicates that a message object will use or is using filtering
+//! based on the direction of the transfer.  If the direction filtering is
+//! used, then ID filtering must also be enabled.
+//
+#define MSG_OBJ_USE_DIR_FILTER  (0x00000010 | MSG_OBJ_USE_ID_FILTER)
 
-    //
-    //! This indicates that a message object is a remote frame.
-    //
-    MSG_OBJ_REMOTE_FRAME =      0x00000040,
+//
+//! This indicates that a message object will use or is using message
+//! identifier filtering based on the extended identifier.  If the extended
+//! identifier filtering is used, then ID filtering must also be enabled.
+//
+#define MSG_OBJ_USE_EXT_FILTER  (0x00000020 | MSG_OBJ_USE_ID_FILTER)
 
-    //
-    //! This indicates that a message object has no flags set.
-    //
-    MSG_OBJ_NO_FLAGS =          0x00000000
-}
-tCANObjFlags;
+//
+//! This indicates that a message object is a remote frame.
+//
+#define MSG_OBJ_REMOTE_FRAME    0x00000040
+
+//
+//! This indicates that this message object is part of a FIFO structure and
+//! not the final message object in a FIFO.
+//
+#define MSG_OBJ_FIFO            0x00000200
+
+//
+//! This indicates that a message object has no flags set.
+//
+#define MSG_OBJ_NO_FLAGS        0x00000000
 
 //*****************************************************************************
 //
-//! This define is used with the #tCANObjFlags enumerated values to allow
-//! checking only status flags and not configuration flags.
+//! This define is used with the flag values to allow checking only status
+//! flags and not configuration flags.
 //
 //*****************************************************************************
 #define MSG_OBJ_STATUS_MASK     (MSG_OBJ_NEW_DATA | MSG_OBJ_DATA_LOST)
@@ -179,25 +179,25 @@ typedef struct
     //! Buffer 1 segments, measured in time quanta.  The valid values for this
     //! setting range from 2 to 16.
     //
-    unsigned int uSyncPropPhase1Seg;
+    unsigned long ulSyncPropPhase1Seg;
 
     //
     //! This value holds the Phase Buffer 2 segment in time quanta.  The valid
     //! values for this setting range from 1 to 8.
     //
-    unsigned int uPhase2Seg;
+    unsigned long ulPhase2Seg;
 
     //
     //! This value holds the Resynchronization Jump Width in time quanta.  The
     //! valid values for this setting range from 1 to 4.
     //
-    unsigned int uSJW;
+    unsigned long ulSJW;
 
     //
     //! This value holds the CAN_CLK divider used to determine time quanta.
     //! The valid values for this setting range from 1 to 1023.
     //
-    unsigned int uQuantumPrescaler;
+    unsigned long ulQuantumPrescaler;
 }
 tCANBitClkParms;
 
@@ -254,32 +254,28 @@ tCANStsReg;
 
 //*****************************************************************************
 //
-//! These definitions are used to specify interrupt sources to CANIntEnable()
-//! and CANIntDisable().
+// These definitions are used to specify interrupt sources to CANIntEnable()
+// and CANIntDisable().
 //
 //*****************************************************************************
-typedef enum
-{
-    //
-    //! This flag is used to allow a CAN controller to generate error
-    //! interrupts.
-    //
-    CAN_INT_ERROR =             0x00000008,
+//
+//! This flag is used to allow a CAN controller to generate error
+//! interrupts.
+//
+#define CAN_INT_ERROR           0x00000008
 
-    //
-    //! This flag is used to allow a CAN controller to generate status
-    //! interrupts.
-    //
-    CAN_INT_STATUS =            0x00000004,
+//
+//! This flag is used to allow a CAN controller to generate status
+//! interrupts.
+//
+#define CAN_INT_STATUS          0x00000004
 
-    //
-    //! This flag is used to allow a CAN controller to generate any CAN
-    //! interrupts.  If this is not set, then no interrupts will be generated
-    //! by the CAN controller.
-    //
-    CAN_INT_MASTER =            0x00000002
-}
-tCANIntFlags;
+//
+//! This flag is used to allow a CAN controller to generate any CAN
+//! interrupts.  If this is not set, then no interrupts will be generated
+//! by the CAN controller.
+//
+#define CAN_INT_MASTER          0x00000002
 
 //*****************************************************************************
 //
@@ -318,84 +314,80 @@ tMsgObjType;
 
 //*****************************************************************************
 //
-//! The following enumeration contains all error or status indicators that can
-//! be returned when calling the CANStatusGet() function.
+// The following enumeration contains all error or status indicators that can
+// be returned when calling the CANStatusGet() function.
 //
 //*****************************************************************************
-typedef enum
-{
-    //
-    //! CAN controller has entered a Bus Off state.
-    //
-    CAN_STATUS_BUS_OFF =        0x00000080,
+//
+//! CAN controller has entered a Bus Off state.
+//
+#define CAN_STATUS_BUS_OFF      0x00000080
 
-    //
-    //! CAN controller error level has reached warning level.
-    //
-    CAN_STATUS_EWARN =          0x00000040,
+//
+//! CAN controller error level has reached warning level.
+//
+#define CAN_STATUS_EWARN        0x00000040
 
-    //
-    //! CAN controller error level has reached error passive level.
-    //
-    CAN_STATUS_EPASS =          0x00000020,
+//
+//! CAN controller error level has reached error passive level.
+//
+#define CAN_STATUS_EPASS        0x00000020
 
-    //
-    //! A message was received successfully since the last read of this status.
-    //
-    CAN_STATUS_RXOK =           0x00000010,
+//
+//! A message was received successfully since the last read of this status.
+//
+#define CAN_STATUS_RXOK         0x00000010
 
-    //
-    //! A message was transmitted successfully since the last read of this
-    //! status.
-    //
-    CAN_STATUS_TXOK =           0x00000008,
+//
+//! A message was transmitted successfully since the last read of this
+//! status.
+//
+#define CAN_STATUS_TXOK         0x00000008
 
-    //
-    //! This is the mask for the last error code field.
-    //
-    CAN_STATUS_LEC_MSK =        0x00000007,
+//
+//! This is the mask for the last error code field.
+//
+#define CAN_STATUS_LEC_MSK      0x00000007
 
-    //
-    //! There was no error.
-    //
-    CAN_STATUS_LEC_NONE =       0x00000000,
+//
+//! There was no error.
+//
+#define CAN_STATUS_LEC_NONE     0x00000000
 
-    //
-    //! A bit stuffing error has occurred.
-    //
-    CAN_STATUS_LEC_STUFF =      0x00000001,
+//
+//! A bit stuffing error has occurred.
+//
+#define CAN_STATUS_LEC_STUFF    0x00000001
 
-    //
-    //! A formatting error has occurred.
-    //
-    CAN_STATUS_LEC_FORM =       0x00000002,
+//
+//! A formatting error has occurred.
+//
+#define CAN_STATUS_LEC_FORM     0x00000002
 
-    //
-    //! An acknowledge error has occurred.
-    //
-    CAN_STATUS_LEC_ACK =        0x00000003,
+//
+//! An acknowledge error has occurred.
+//
+#define CAN_STATUS_LEC_ACK      0x00000003
 
-    //
-    //! The bus remained a bit level of 1 for longer than is allowed.
-    //
-    CAN_STATUS_LEC_BIT1 =       0x00000004,
+//
+//! The bus remained a bit level of 1 for longer than is allowed.
+//
+#define CAN_STATUS_LEC_BIT1     0x00000004
 
-    //
-    //! The bus remained a bit level of 0 for longer than is allowed.
-    //
-    CAN_STATUS_LEC_BIT0 =       0x00000005,
+//
+//! The bus remained a bit level of 0 for longer than is allowed.
+//
+#define CAN_STATUS_LEC_BIT0     0x00000005
 
-    //
-    //! A CRC error has occurred.
-    //
-    CAN_STATUS_LEC_CRC =        0x00000006,
+//
+//! A CRC error has occurred.
+//
+#define CAN_STATUS_LEC_CRC      0x00000006
 
-    //
-    //! This is the mask for the CAN Last Error Code (LEC).
-    //
-    CAN_STATUS_LEC_MASK =       0x00000007
-}
-tCANStatusCtrl;
+//
+//! This is the mask for the CAN Last Error Code (LEC).
+//
+#define CAN_STATUS_LEC_MASK     0x00000007
 
 //*****************************************************************************
 //
diff --git a/src/platform/lm3s/driverlib/cpu.c b/src/platform/lm3s/driverlib/cpu.c
new file mode 100755
index 00000000..17569a47
--- /dev/null
+++ b/src/platform/lm3s/driverlib/cpu.c
@@ -0,0 +1,442 @@
+//*****************************************************************************
+//
+// cpu.c - Instruction wrappers for special CPU instructions needed by the
+//         drivers.
+//
+// Copyright (c) 2006-2011 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 7611 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#include "driverlib/cpu.h"
+
+//*****************************************************************************
+//
+// Wrapper function for the CPSID instruction.  Returns the state of PRIMASK
+// on entry.
+//
+//*****************************************************************************
+#if defined(codered) || defined(gcc) || defined(sourcerygxx)
+unsigned long __attribute__((naked))
+CPUcpsid(void)
+{
+    unsigned long ulRet;
+
+    //
+    // Read PRIMASK and disable interrupts.
+    //
+    __asm("    mrs     r0, PRIMASK\n"
+          "    cpsid   i\n"
+          "    bx      lr\n"
+          : "=r" (ulRet));
+
+    //
+    // The return is handled in the inline assembly, but the compiler will
+    // still complain if there is not an explicit return here (despite the fact
+    // that this does not result in any code being produced because of the
+    // naked attribute).
+    //
+    return(ulRet);
+}
+#endif
+#if defined(ewarm)
+unsigned long
+CPUcpsid(void)
+{
+    //
+    // Read PRIMASK and disable interrupts.
+    //
+    __asm("    mrs     r0, PRIMASK\n"
+          "    cpsid   i\n");
+
+    //
+    // "Warning[Pe940]: missing return statement at end of non-void function"
+    // is suppressed here to avoid putting a "bx lr" in the inline assembly
+    // above and a superfluous return statement here.
+    //
+#pragma diag_suppress=Pe940
+}
+#pragma diag_default=Pe940
+#endif
+#if defined(rvmdk) || defined(__ARMCC_VERSION)
+__asm unsigned long
+CPUcpsid(void)
+{
+    //
+    // Read PRIMASK and disable interrupts.
+    //
+    mrs     r0, PRIMASK;
+    cpsid   i;
+    bx      lr
+}
+#endif
+#if defined(ccs)
+unsigned long
+CPUcpsid(void)
+{
+    //
+    // Read PRIMASK and disable interrupts.
+    //
+    __asm("    mrs     r0, PRIMASK\n"
+          "    cpsid   i\n"
+          "    bx      lr\n");
+
+    //
+    // The following keeps the compiler happy, because it wants to see a
+    // return value from this function.  It will generate code to return
+    // a zero.  However, the real return is the "bx lr" above, so the
+    // return(0) is never executed and the function returns with the value
+    // you expect in R0.
+    //
+    return(0);
+}
+#endif
+
+//*****************************************************************************
+//
+// Wrapper function returning the state of PRIMASK (indicating whether
+// interrupts are enabled or disabled).
+//
+//*****************************************************************************
+#if defined(codered) || defined(gcc) || defined(sourcerygxx)
+unsigned long __attribute__((naked))
+CPUprimask(void)
+{
+    unsigned long ulRet;
+
+    //
+    // Read PRIMASK and disable interrupts.
+    //
+    __asm("    mrs     r0, PRIMASK\n"
+          "    bx      lr\n"
+          : "=r" (ulRet));
+
+    //
+    // The return is handled in the inline assembly, but the compiler will
+    // still complain if there is not an explicit return here (despite the fact
+    // that this does not result in any code being produced because of the
+    // naked attribute).
+    //
+    return(ulRet);
+}
+#endif
+#if defined(ewarm)
+unsigned long
+CPUprimask(void)
+{
+    //
+    // Read PRIMASK and disable interrupts.
+    //
+    __asm("    mrs     r0, PRIMASK\n");
+
+    //
+    // "Warning[Pe940]: missing return statement at end of non-void function"
+    // is suppressed here to avoid putting a "bx lr" in the inline assembly
+    // above and a superfluous return statement here.
+    //
+#pragma diag_suppress=Pe940
+}
+#pragma diag_default=Pe940
+#endif
+#if defined(rvmdk) || defined(__ARMCC_VERSION)
+__asm unsigned long
+CPUprimask(void)
+{
+    //
+    // Read PRIMASK and disable interrupts.
+    //
+    mrs     r0, PRIMASK;
+    bx      lr
+}
+#endif
+#if defined(ccs)
+unsigned long
+CPUprimask(void)
+{
+    //
+    // Read PRIMASK and disable interrupts.
+    //
+    __asm("    mrs     r0, PRIMASK\n"
+          "    bx      lr\n");
+
+    //
+    // The following keeps the compiler happy, because it wants to see a
+    // return value from this function.  It will generate code to return
+    // a zero.  However, the real return is the "bx lr" above, so the
+    // return(0) is never executed and the function returns with the value
+    // you expect in R0.
+    //
+    return(0);
+}
+#endif
+
+//*****************************************************************************
+//
+// Wrapper function for the CPSIE instruction.  Returns the state of PRIMASK
+// on entry.
+//
+//*****************************************************************************
+#if defined(codered) || defined(gcc) || defined(sourcerygxx)
+unsigned long __attribute__((naked))
+CPUcpsie(void)
+{
+    unsigned long ulRet;
+
+    //
+    // Read PRIMASK and enable interrupts.
+    //
+    __asm("    mrs     r0, PRIMASK\n"
+          "    cpsie   i\n"
+          "    bx      lr\n"
+          : "=r" (ulRet));
+
+    //
+    // The return is handled in the inline assembly, but the compiler will
+    // still complain if there is not an explicit return here (despite the fact
+    // that this does not result in any code being produced because of the
+    // naked attribute).
+    //
+    return(ulRet);
+}
+#endif
+#if defined(ewarm)
+unsigned long
+CPUcpsie(void)
+{
+    //
+    // Read PRIMASK and enable interrupts.
+    //
+    __asm("    mrs     r0, PRIMASK\n"
+          "    cpsie   i\n");
+
+    //
+    // "Warning[Pe940]: missing return statement at end of non-void function"
+    // is suppressed here to avoid putting a "bx lr" in the inline assembly
+    // above and a superfluous return statement here.
+    //
+#pragma diag_suppress=Pe940
+}
+#pragma diag_default=Pe940
+#endif
+#if defined(rvmdk) || defined(__ARMCC_VERSION)
+__asm unsigned long
+CPUcpsie(void)
+{
+    //
+    // Read PRIMASK and enable interrupts.
+    //
+    mrs     r0, PRIMASK;
+    cpsie   i;
+    bx      lr
+}
+#endif
+#if defined(ccs)
+unsigned long
+CPUcpsie(void)
+{
+    //
+    // Read PRIMASK and enable interrupts.
+    //
+    __asm("    mrs     r0, PRIMASK\n"
+          "    cpsie   i\n"
+          "    bx      lr\n");
+
+    //
+    // The following keeps the compiler happy, because it wants to see a
+    // return value from this function.  It will generate code to return
+    // a zero.  However, the real return is the "bx lr" above, so the
+    // return(0) is never executed and the function returns with the value
+    // you expect in R0.
+    //
+    return(0);
+}
+#endif
+
+//*****************************************************************************
+//
+// Wrapper function for the WFI instruction.
+//
+//*****************************************************************************
+#if defined(codered) || defined(gcc) || defined(sourcerygxx)
+void __attribute__((naked))
+CPUwfi(void)
+{
+    //
+    // Wait for the next interrupt.
+    //
+    __asm("    wfi\n"
+          "    bx      lr\n");
+}
+#endif
+#if defined(ewarm)
+void
+CPUwfi(void)
+{
+    //
+    // Wait for the next interrupt.
+    //
+    __asm("    wfi\n");
+}
+#endif
+#if defined(rvmdk) || defined(__ARMCC_VERSION)
+__asm void
+CPUwfi(void)
+{
+    //
+    // Wait for the next interrupt.
+    //
+    wfi;
+    bx      lr
+}
+#endif
+#if defined(ccs)
+void
+CPUwfi(void)
+{
+    //
+    // Wait for the next interrupt.
+    //
+    __asm("    wfi\n");
+}
+#endif
+
+//*****************************************************************************
+//
+// Wrapper function for writing the BASEPRI register.
+//
+//*****************************************************************************
+#if defined(codered) || defined(gcc) || defined(sourcerygxx)
+void __attribute__((naked))
+CPUbasepriSet(unsigned long ulNewBasepri)
+{
+
+    //
+    // Set the BASEPRI register
+    //
+    __asm("    msr     BASEPRI, r0\n"
+          "    bx      lr\n");
+}
+#endif
+#if defined(ewarm)
+void
+CPUbasepriSet(unsigned long ulNewBasepri)
+{
+    //
+    // Set the BASEPRI register
+    //
+    __asm("    msr     BASEPRI, r0\n");
+}
+#endif
+#if defined(rvmdk) || defined(__ARMCC_VERSION)
+__asm void
+CPUbasepriSet(unsigned long ulNewBasepri)
+{
+    //
+    // Set the BASEPRI register
+    //
+    msr     BASEPRI, r0;
+    bx      lr
+}
+#endif
+#if defined(ccs)
+void
+CPUbasepriSet(unsigned long ulNewBasepri)
+{
+    //
+    // Set the BASEPRI register
+    //
+    __asm("    msr     BASEPRI, r0\n");
+}
+#endif
+
+//*****************************************************************************
+//
+// Wrapper function for reading the BASEPRI register.
+//
+//*****************************************************************************
+#if defined(codered) || defined(gcc) || defined(sourcerygxx)
+unsigned long __attribute__((naked))
+CPUbasepriGet(void)
+{
+    unsigned long ulRet;
+
+    //
+    // Read BASEPRI
+    //
+    __asm("    mrs     r0, BASEPRI\n"
+          "    bx      lr\n"
+          : "=r" (ulRet));
+
+    //
+    // The return is handled in the inline assembly, but the compiler will
+    // still complain if there is not an explicit return here (despite the fact
+    // that this does not result in any code being produced because of the
+    // naked attribute).
+    //
+    return(ulRet);
+}
+#endif
+#if defined(ewarm)
+unsigned long
+CPUbasepriGet(void)
+{
+    //
+    // Read BASEPRI
+    //
+    __asm("    mrs     r0, BASEPRI\n");
+
+    //
+    // "Warning[Pe940]: missing return statement at end of non-void function"
+    // is suppressed here to avoid putting a "bx lr" in the inline assembly
+    // above and a superfluous return statement here.
+    //
+#pragma diag_suppress=Pe940
+}
+#pragma diag_default=Pe940
+#endif
+#if defined(rvmdk) || defined(__ARMCC_VERSION)
+__asm unsigned long
+CPUbasepriGet(void)
+{
+    //
+    // Read BASEPRI
+    //
+    mrs     r0, BASEPRI;
+    bx      lr
+}
+#endif
+#if defined(ccs)
+unsigned long
+CPUbasepriGet(void)
+{
+    //
+    // Read BASEPRI
+    //
+    __asm("    mrs     r0, BASEPRI\n"
+          "    bx      lr\n");
+
+    //
+    // The following keeps the compiler happy, because it wants to see a
+    // return value from this function.  It will generate code to return
+    // a zero.  However, the real return is the "bx lr" above, so the
+    // return(0) is never executed and the function returns with the value
+    // you expect in R0.
+    //
+    return(0);
+}
+#endif
diff --git a/src/platform/lm3s/cpu.h b/src/platform/lm3s/driverlib/cpu.h
similarity index 52%
rename from src/platform/lm3s/cpu.h
rename to src/platform/lm3s/driverlib/cpu.h
index bf478031..6ff26c93 100755
--- a/src/platform/lm3s/cpu.h
+++ b/src/platform/lm3s/driverlib/cpu.h
@@ -2,26 +2,23 @@
 //
 // cpu.h - Prototypes for the CPU instruction wrapper functions.
 //
-// Copyright (c) 2006-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2006-2011 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
+// This is part of revision 7611 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -46,7 +43,10 @@ extern "C"
 //*****************************************************************************
 extern unsigned long CPUcpsid(void);
 extern unsigned long CPUcpsie(void);
+extern unsigned long CPUprimask(void);
 extern void CPUwfi(void);
+extern unsigned long CPUbasepriGet(void);
+extern void CPUbasepriSet(unsigned long ulNewBasepri);
 
 //*****************************************************************************
 //
diff --git a/src/platform/lm3s/driverlib/debug.h b/src/platform/lm3s/driverlib/debug.h
new file mode 100755
index 00000000..1f45f410
--- /dev/null
+++ b/src/platform/lm3s/driverlib/debug.h
@@ -0,0 +1,53 @@
+//*****************************************************************************
+//
+// debug.h - Macros for assisting debug of the driver library.
+//
+// Copyright (c) 2006-2011 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 7611 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __DEBUG_H__
+#define __DEBUG_H__
+
+//*****************************************************************************
+//
+// Prototype for the function that is called when an invalid argument is passed
+// to an API.  This is only used when doing a DEBUG build.
+//
+//*****************************************************************************
+extern void __error__(char *pcFilename, unsigned long ulLine);
+
+//*****************************************************************************
+//
+// The ASSERT macro, which does the actual assertion checking.  Typically, this
+// will be for procedure arguments.
+//
+//*****************************************************************************
+#ifdef DEBUG
+#define ASSERT(expr) {                                      \
+                         if(!(expr))                        \
+                         {                                  \
+                             __error__(__FILE__, __LINE__); \
+                         }                                  \
+                     }
+#else
+#define ASSERT(expr)
+#endif
+
+#endif // __DEBUG_H__
diff --git a/src/platform/lm3s/ethernet.c b/src/platform/lm3s/driverlib/ethernet.c
similarity index 91%
rename from src/platform/lm3s/ethernet.c
rename to src/platform/lm3s/driverlib/ethernet.c
index d2c9ca96..7880bf4e 100755
--- a/src/platform/lm3s/ethernet.c
+++ b/src/platform/lm3s/driverlib/ethernet.c
@@ -2,26 +2,23 @@
 //
 // ethernet.c - Driver for the Integrated Ethernet Controller
 //
-// Copyright (c) 2006-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2006-2011 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
+// This is part of revision 7611 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -32,13 +29,13 @@
 //
 //*****************************************************************************
 
-#include "hw_ethernet.h"
-#include "hw_ints.h"
-#include "hw_memmap.h"
-#include "hw_types.h"
-#include "debug.h"
-#include "ethernet.h"
-#include "interrupt.h"
+#include "inc/hw_ethernet.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_types.h"
+#include "driverlib/debug.h"
+#include "driverlib/ethernet.h"
+#include "driverlib/interrupt.h"
 
 //*****************************************************************************
 //
@@ -1147,14 +1144,14 @@ EthernetIntStatus(unsigned long ulBase, tBoolean bMasked)
 //! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
 //! parameter to EthernetIntEnable().
 //!
-//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
-//! several clock cycles before the interrupt source is actually cleared.
+//! \note Because there is a write buffer in the Cortex-M3 processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
 //! Therefore, it is recommended that the interrupt source be cleared early in
 //! the interrupt handler (as opposed to the very last action) to avoid
 //! returning from the interrupt handler before the interrupt source is
 //! actually cleared.  Failure to do so may result in the interrupt handler
-//! being immediately reentered (since NVIC still sees the interrupt source
-//! asserted).
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
 //!
 //! \return None.
 //
@@ -1176,6 +1173,42 @@ EthernetIntClear(unsigned long ulBase, unsigned long ulIntFlags)
     HWREG(ulBase + MAC_O_IACK) = ulIntFlags;
 }
 
+//*****************************************************************************
+//
+//! Sets the PHY address.
+//!
+//! \param ulBase is the base address of the controller.
+//! \param ucAddr is the address of the PHY.
+//!
+//! This function sets the address of the PHY that is accessed via
+//! EthernetPHYRead() and EthernePHYWrite().  This is only needed when
+//! connecting to an external PHY via MII, and should not be used on devices
+//! that have integrated PHYs.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EthernetPHYAddrSet(unsigned long ulBase, unsigned char ucAddr)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulBase == ETH_BASE);
+
+    //
+    // Wait for any pending transaction to complete.
+    //
+    while(HWREG(ulBase + MAC_O_MCTL) & MAC_MCTL_START)
+    {
+    }
+
+    //
+    // Set the PHY address.
+    //
+    HWREG(ulBase + MAC_O_MADD) = ucAddr;
+}
+
 //*****************************************************************************
 //
 //! Writes to the PHY register.
@@ -1272,6 +1305,56 @@ EthernetPHYRead(unsigned long ulBase, unsigned char ucRegAddr)
     return(HWREG(ulBase + MAC_O_MRXD) & MAC_MRXD_MDRX_M);
 }
 
+//*****************************************************************************
+//
+//! Powers off the Ethernet PHY.
+//!
+//! \param ulBase is the base address of the controller.
+//!
+//! This function will power off the Ethernet PHY, reducing the current
+//! consuption of the device.  While in the powered off state, the Ethernet
+//! controller will be unable to connect to the Ethernet.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EthernetPHYPowerOff(unsigned long ulBase)
+{
+    //
+    // Set the PWRDN bit and clear the ANEGEN bit in the PHY, putting it into
+    // its low power mode.
+    //
+    EthernetPHYWrite(ulBase, PHY_MR0,
+                     (EthernetPHYRead(ulBase, PHY_MR0) & ~PHY_MR0_ANEGEN) |
+                     PHY_MR0_PWRDN);
+}
+
+//*****************************************************************************
+//
+//! Powers on the Ethernet PHY.
+//!
+//! \param ulBase is the base address of the controller.
+//!
+//! This function will power on the Ethernet PHY, enabling it return to normal
+//! operation.  By default, the PHY is powered on, so this function only needs
+//! to be called if EthernetPHYPowerOff() has previously been called.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EthernetPHYPowerOn(unsigned long ulBase)
+{
+    //
+    // Clear the PWRDN bit and set the ANEGEN bit in the PHY, putting it into
+    // normal operating mode.
+    //
+    EthernetPHYWrite(ulBase, PHY_MR0,
+                     (EthernetPHYRead(ulBase, PHY_MR0) & ~PHY_MR0_PWRDN) |
+                     PHY_MR0_ANEGEN);
+}
+
 //*****************************************************************************
 //
 // Close the Doxygen group.
diff --git a/src/platform/lm3s/ethernet.h b/src/platform/lm3s/driverlib/ethernet.h
similarity index 85%
rename from src/platform/lm3s/ethernet.h
rename to src/platform/lm3s/driverlib/ethernet.h
index 45ddd970..6cea603d 100755
--- a/src/platform/lm3s/ethernet.h
+++ b/src/platform/lm3s/driverlib/ethernet.h
@@ -2,26 +2,23 @@
 //
 // ethernet.h - Defines and Macros for the ethernet module.
 //
-// Copyright (c) 2006-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2006-2011 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
+// This is part of revision 7611 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -139,10 +136,13 @@ extern void EthernetIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
 extern void EthernetIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
 extern unsigned long EthernetIntStatus(unsigned long ulBase, tBoolean bMasked);
 extern void EthernetIntClear(unsigned long ulBase, unsigned long ulIntFlags);
+extern void EthernetPHYAddrSet(unsigned long ulBase, unsigned char ucAddr);
 extern void EthernetPHYWrite(unsigned long ulBase, unsigned char ucRegAddr,
                              unsigned long ulData);
 extern unsigned long EthernetPHYRead(unsigned long ulBase,
                                      unsigned char ucRegAddr);
+extern void EthernetPHYPowerOff(unsigned long ulBase);
+extern void EthernetPHYPowerOn(unsigned long ulBase);
 
 //*****************************************************************************
 //
@@ -151,7 +151,7 @@ extern unsigned long EthernetPHYRead(unsigned long ulBase,
 //
 //*****************************************************************************
 #ifndef DEPRECATED
-#include "sysctl.h"
+#include "driverlib/sysctl.h"
 #define EthernetInit(a)                         \
         EthernetInitExpClk(a, SysCtlClockGet())
 #define EthernetPacketNonBlockingGet(a, b, c) \
diff --git a/src/platform/lm3s/flash.c b/src/platform/lm3s/driverlib/flash.c
similarity index 91%
rename from src/platform/lm3s/flash.c
rename to src/platform/lm3s/driverlib/flash.c
index 1adcded6..6e7fa4ee 100755
--- a/src/platform/lm3s/flash.c
+++ b/src/platform/lm3s/driverlib/flash.c
@@ -2,26 +2,23 @@
 //
 // flash.c - Driver for programming the on-chip flash.
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2011 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
+// This is part of revision 7611 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -32,13 +29,13 @@
 //
 //*****************************************************************************
 
-#include "hw_flash.h"
-#include "hw_ints.h"
-#include "hw_sysctl.h"
-#include "hw_types.h"
-#include "debug.h"
-#include "flash.h"
-#include "interrupt.h"
+#include "inc/hw_flash.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_sysctl.h"
+#include "inc/hw_types.h"
+#include "driverlib/debug.h"
+#include "driverlib/flash.h"
+#include "driverlib/interrupt.h"
 
 //*****************************************************************************
 //
@@ -177,12 +174,9 @@ FlashErase(unsigned long ulAddress)
 //! of four.
 //!
 //! This function will program a sequence of words into the on-chip flash.
-//! Programming each location consists of the result of an AND operation
-//! of the new data and the existing data; in other words bits that contain
-//! 1 can remain 1 or be changed to 0, but bits that are 0 cannot be changed
-//! to 1.  Therefore, a word can be programmed multiple times as long as these
-//! rules are followed; if a program operation attempts to change a 0 bit to
-//! a 1 bit, that bit will not have its value changed.
+//! Each word in a page of flash can only be programmed one time between an
+//! erase of that page; programming a word multiple times will result in an
+//! unpredictable value in that word of flash.
 //!
 //! Since the flash is programmed one word at a time, the starting address and
 //! byte count must both be multiples of four.  It is up to the caller to
@@ -539,7 +533,7 @@ FlashProtectSet(unsigned long ulAddress, tFlashProtection eProtect)
     {
         ulProtectRE &= ~(FLASH_FMP_BLOCK_31 | FLASH_FMP_BLOCK_30);
         ulProtectRE |= (HWREG(g_pulFMPRERegs[ulBank]) &
-                (FLASH_FMP_BLOCK_31 | FLASH_FMP_BLOCK_30));
+                        (FLASH_FMP_BLOCK_31 | FLASH_FMP_BLOCK_30));
     }
 
     //
@@ -570,7 +564,7 @@ FlashProtectSet(unsigned long ulAddress, tFlashProtection eProtect)
 long
 FlashProtectSave(void)
 {
-    int ulTemp, ulLimit;
+    unsigned long ulTemp, ulLimit;
 
     //
     // If running on a Sandstorm-class device, only trigger a save of the first
@@ -802,7 +796,7 @@ FlashIntUnregister(void)
 //! Enables individual flash controller interrupt sources.
 //!
 //! \param ulIntFlags is a bit mask of the interrupt sources to be enabled.
-//! Can be any of the \b FLASH_FCIM_PROGRAM or \b FLASH_FCIM_ACCESS values.
+//! Can be any of the \b FLASH_INT_PROGRAM or \b FLASH_INT_ACCESS values.
 //!
 //! Enables the indicated flash controller interrupt sources.  Only the sources
 //! that are enabled can be reflected to the processor interrupt; disabled
@@ -825,7 +819,7 @@ FlashIntEnable(unsigned long ulIntFlags)
 //! Disables individual flash controller interrupt sources.
 //!
 //! \param ulIntFlags is a bit mask of the interrupt sources to be disabled.
-//! Can be any of the \b FLASH_FCIM_PROGRAM or \b FLASH_FCIM_ACCESS values.
+//! Can be any of the \b FLASH_INT_PROGRAM or \b FLASH_INT_ACCESS values.
 //!
 //! Disables the indicated flash controller interrupt sources.  Only the
 //! sources that are enabled can be reflected to the processor interrupt;
@@ -855,11 +849,11 @@ FlashIntDisable(unsigned long ulIntFlags)
 //! the processor can be returned.
 //!
 //! \return The current interrupt status, enumerated as a bit field of
-//! \b FLASH_FCMISC_PROGRAM and \b FLASH_FCMISC_AMISC.
+//! \b FLASH_INT_PROGRAM and \b FLASH_INT_ACCESS.
 //
 //*****************************************************************************
 unsigned long
-FlashIntGetStatus(tBoolean bMasked)
+FlashIntStatus(tBoolean bMasked)
 {
     //
     // Return either the interrupt status or the raw interrupt status as
@@ -880,20 +874,20 @@ FlashIntGetStatus(tBoolean bMasked)
 //! Clears flash controller interrupt sources.
 //!
 //! \param ulIntFlags is the bit mask of the interrupt sources to be cleared.
-//! Can be any of the \b FLASH_FCMISC_PROGRAM or \b FLASH_FCMISC_AMISC values.
+//! Can be any of the \b FLASH_INT_PROGRAM or \b FLASH_INT_AMISC values.
 //!
 //! The specified flash controller interrupt sources are cleared, so that they
 //! no longer assert.  This must be done in the interrupt handler to keep it
 //! from being called again immediately upon exit.
 //!
-//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
-//! several clock cycles before the interrupt source is actually cleared.
+//! \note Because there is a write buffer in the Cortex-M3 processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
 //! Therefore, it is recommended that the interrupt source be cleared early in
 //! the interrupt handler (as opposed to the very last action) to avoid
 //! returning from the interrupt handler before the interrupt source is
 //! actually cleared.  Failure to do so may result in the interrupt handler
-//! being immediately reentered (since NVIC still sees the interrupt source
-//! asserted).
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
 //!
 //! \return None.
 //
diff --git a/src/platform/lm3s/flash.h b/src/platform/lm3s/driverlib/flash.h
similarity index 58%
rename from src/platform/lm3s/flash.h
rename to src/platform/lm3s/driverlib/flash.h
index 995a164a..6bc85776 100755
--- a/src/platform/lm3s/flash.h
+++ b/src/platform/lm3s/driverlib/flash.h
@@ -2,26 +2,23 @@
 //
 // flash.h - Prototypes for the flash driver.
 //
-// Copyright (c) 2005-2007 Luminary Micro, Inc.  All rights reserved
+// Copyright (c) 2005-2011 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
+// This is part of revision 7611 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -53,6 +50,15 @@ typedef enum
 }
 tFlashProtection;
 
+//*****************************************************************************
+//
+// Values passed to FlashIntEnable(), FlashIntDisable() and FlashIntClear() and
+// returned from FlashIntStatus().
+//
+//*****************************************************************************
+#define FLASH_INT_PROGRAM     0x00000002 // Programming Interrupt Mask
+#define FLASH_INT_ACCESS      0x00000001 // Access Interrupt Mask
+
 //*****************************************************************************
 //
 // Prototypes for the APIs.
@@ -74,9 +80,20 @@ extern void FlashIntRegister(void (*pfnHandler)(void));
 extern void FlashIntUnregister(void);
 extern void FlashIntEnable(unsigned long ulIntFlags);
 extern void FlashIntDisable(unsigned long ulIntFlags);
-extern unsigned long FlashIntGetStatus(tBoolean bMasked);
+extern unsigned long FlashIntStatus(tBoolean bMasked);
 extern void FlashIntClear(unsigned long ulIntFlags);
 
+//*****************************************************************************
+//
+// Deprecated function names.  These definitions ensure backwards compatibility
+// but new code should avoid using deprecated function names since these will
+// be removed at some point in the future.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+#define FlashIntGetStatus       FlashIntStatus
+#endif
+
 //*****************************************************************************
 //
 // Mark the end of the C bindings section for C++ compilers.
diff --git a/src/platform/lm3s/gpio.c b/src/platform/lm3s/driverlib/gpio.c
similarity index 88%
rename from src/platform/lm3s/gpio.c
rename to src/platform/lm3s/driverlib/gpio.c
index c465d0e4..504426aa 100755
--- a/src/platform/lm3s/gpio.c
+++ b/src/platform/lm3s/driverlib/gpio.c
@@ -2,26 +2,23 @@
 //
 // gpio.c - API for GPIO ports
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2011 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
+// This is part of revision 7611 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -32,14 +29,14 @@
 //
 //*****************************************************************************
 
-#include "hw_gpio.h"
-#include "hw_ints.h"
-#include "hw_memmap.h"
-#include "hw_sysctl.h"
-#include "hw_types.h"
-#include "debug.h"
-#include "gpio.h"
-#include "interrupt.h"
+#include "inc/hw_gpio.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_sysctl.h"
+#include "inc/hw_types.h"
+#include "driverlib/debug.h"
+#include "driverlib/gpio.h"
+#include "driverlib/interrupt.h"
 
 //*****************************************************************************
 //
@@ -104,7 +101,7 @@ GPIOBaseValid(unsigned long ulPort)
 static long
 GPIOGetIntNumber(unsigned long ulPort)
 {
-    unsigned int ulInt;
+    long lInt;
 
     //
     // Determine the GPIO interrupt number for the given module.
@@ -114,63 +111,63 @@ GPIOGetIntNumber(unsigned long ulPort)
         case GPIO_PORTA_BASE:
         case GPIO_PORTA_AHB_BASE:
         {
-            ulInt = INT_GPIOA;
+            lInt = INT_GPIOA;
             break;
         }
 
         case GPIO_PORTB_BASE:
         case GPIO_PORTB_AHB_BASE:
         {
-            ulInt = INT_GPIOB;
+            lInt = INT_GPIOB;
             break;
         }
 
         case GPIO_PORTC_BASE:
         case GPIO_PORTC_AHB_BASE:
         {
-            ulInt = INT_GPIOC;
+            lInt = INT_GPIOC;
             break;
         }
 
         case GPIO_PORTD_BASE:
         case GPIO_PORTD_AHB_BASE:
         {
-            ulInt = INT_GPIOD;
+            lInt = INT_GPIOD;
             break;
         }
 
         case GPIO_PORTE_BASE:
         case GPIO_PORTE_AHB_BASE:
         {
-            ulInt = INT_GPIOE;
+            lInt = INT_GPIOE;
             break;
         }
 
         case GPIO_PORTF_BASE:
         case GPIO_PORTF_AHB_BASE:
         {
-            ulInt = INT_GPIOF;
+            lInt = INT_GPIOF;
             break;
         }
 
         case GPIO_PORTG_BASE:
         case GPIO_PORTG_AHB_BASE:
         {
-            ulInt = INT_GPIOG;
+            lInt = INT_GPIOG;
             break;
         }
 
         case GPIO_PORTH_BASE:
         case GPIO_PORTH_AHB_BASE:
         {
-            ulInt = INT_GPIOH;
+            lInt = INT_GPIOH;
             break;
         }
 
         case GPIO_PORTJ_BASE:
         case GPIO_PORTJ_AHB_BASE:
         {
-            ulInt = INT_GPIOJ;
+            lInt = INT_GPIOJ;
             break;
         }
 
@@ -183,7 +180,7 @@ GPIOGetIntNumber(unsigned long ulPort)
     //
     // Return GPIO interrupt number.
     //
-    return(ulInt);
+    return(lInt);
 }
 
 //*****************************************************************************
@@ -215,6 +212,9 @@ GPIOGetIntNumber(unsigned long ulPort)
 //! set identifies the pin to be accessed, and where bit 0 of the byte
 //! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
 //!
+//! \note GPIOPadConfigSet() must also be used to configure the corresponding
+//! pad(s) in order for them to propagate the signal to/from the GPIO.
+//!
 //! \return None.
 //
 //*****************************************************************************
@@ -423,7 +423,7 @@ GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin)
 //! where \b GPIO_PIN_TYPE_STD* specifies a push-pull pin, \b GPIO_PIN_TYPE_OD*
 //! specifies an open-drain pin, \b *_WPU specifies a weak pull-up, \b *_WPD
 //! specifies a weak pull-down, and \b GPIO_PIN_TYPE_ANALOG specifies an
-//! analog input (for the comparators).
+//! analog input.
 //!
 //! The pin(s) are specified using a bit-packed byte, where each bit that is
 //! set identifies the pin to be accessed, and where bit 0 of the byte
@@ -663,14 +663,14 @@ GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked)
 //! set identifies the pin to be accessed, and where bit 0 of the byte
 //! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
 //!
-//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
-//! several clock cycles before the interrupt source is actually cleared.
+//! \note Because there is a write buffer in the Cortex-M3 processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
 //! Therefore, it is recommended that the interrupt source be cleared early in
 //! the interrupt handler (as opposed to the very last action) to avoid
 //! returning from the interrupt handler before the interrupt source is
 //! actually cleared.  Failure to do so may result in the interrupt handler
-//! being immediately reentered (since NVIC still sees the interrupt source
-//! asserted).
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
 //!
 //! \return None.
 //
@@ -962,6 +962,129 @@ GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins)
     GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_ANALOG);
 }
 
+//*****************************************************************************
+//
+//! Configures pin(s) for use by the external peripheral interface.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//!
+//! The external peripheral interface pins must be properly configured for the
+//! external peripheral interface to function correctly.  This function
+//! provides a typical configuration for those pin(s); other configurations may
+//! work as well depending upon the board setup (for example, using the on-chip
+//! pull-ups).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This cannot be used to turn any pin into an external peripheral
+//! interface pin; it only configures an external peripheral interface pin for
+//! proper operation.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeEPI(unsigned long ulPort, unsigned char ucPins)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(GPIOBaseValid(ulPort));
+
+    //
+    // Make the pin(s) be peripheral controlled.
+    //
+    GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW);
+
+    //
+    // Set the pad(s) for standard push-pull operation.
+    //
+    GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use by the Ethernet peripheral as LED signals.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//!
+//! The Ethernet peripheral provides two signals that can be used to drive
+//! an LED (e.g. for link status/activity).  This function provides a typical
+//! configuration for the pins.
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This cannot be used to turn any pin into an Ethernet LED pin; it only
+//! configures an Ethernet LED pin for proper operation.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeEthernetLED(unsigned long ulPort, unsigned char ucPins)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(GPIOBaseValid(ulPort));
+
+    //
+    // Make the pin(s) be peripheral controlled.
+    //
+    GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW);
+
+    //
+    // Set the pad(s) for standard push-pull operation.
+    //
+    GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use by the Ethernet peripheral as MII signals.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//!
+//! The Ethernet peripheral on some parts provides a set of MII signals that
+//! are used to connect to an external PHY.  This function provides a typical
+//! configuration for the pins.
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This cannot be used to turn any pin into an Ethernet MII pin; it only
+//! configures an Ethernet MII pin for proper operation.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeEthernetMII(unsigned long ulPort, unsigned char ucPins)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(GPIOBaseValid(ulPort));
+
+    //
+    // Make the pin(s) be peripheral controlled.
+    //
+    GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW);
+
+    //
+    // Set the pad(s) for standard push-pull operation.
+    //
+    GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD);
+}
+
 //*****************************************************************************
 //
 //! Configures pin(s) for use as GPIO inputs.
@@ -1027,15 +1150,15 @@ GPIOPinTypeGPIOOutput(unsigned long ulPort, unsigned char ucPins)
     //
     ASSERT(GPIOBaseValid(ulPort));
 
-    //
-    // Make the pin(s) be outputs.
-    //
-    GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_OUT);
-
     //
     // Set the pad(s) for standard push-pull operation.
     //
     GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
+
+    //
+    // Make the pin(s) be outputs.
+    //
+    GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_OUT);
 }
 
 //*****************************************************************************
@@ -1065,15 +1188,15 @@ GPIOPinTypeGPIOOutputOD(unsigned long ulPort, unsigned char ucPins)
     //
     ASSERT(GPIOBaseValid(ulPort));
 
-    //
-    // Make the pin(s) be outputs.
-    //
-    GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_OUT);
-
     //
     // Set the pad(s) for standard push-pull operation.
     //
     GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_OD);
+
+    //
+    // Make the pin(s) be outputs.
+    //
+    GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_OUT);
 }
 
 //*****************************************************************************
@@ -1116,6 +1239,47 @@ GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins)
     GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_OD_WPU);
 }
 
+//*****************************************************************************
+//
+//! Configures pin(s) for use by the I2S peripheral.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//!
+//! Some I2S pins must be properly configured for the I2S peripheral to
+//! function correctly.  This function provides a typical configuration for
+//! the digital I2S pin(s); other configurations may work as well depending
+//! upon the board setup (for example, using the on-chip pull-ups).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This cannot be used to turn any pin into a I2S pin; it only
+//! configures a I2S pin for proper operation.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeI2S(unsigned long ulPort, unsigned char ucPins)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(GPIOBaseValid(ulPort));
+
+    //
+    // Make the pin(s) be peripheral controlled.
+    //
+    GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW);
+
+    //
+    // Set the pad(s) for standard push-pull operation.
+    //
+    GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
+}
+
 //*****************************************************************************
 //
 //! Configures pin(s) for use by the PWM peripheral.
@@ -1321,6 +1485,47 @@ GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins)
     GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
 }
 
+//*****************************************************************************
+//
+//! Configures pin(s) for use by the USB peripheral.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//!
+//! Some USB analog pins must be properly configured for the USB peripheral to
+//! function correctly.  This function provides the proper configuration for
+//! any USB pin(s).  This can also be used to configure the EPEN and PFAULT pins
+//! so that they are no longer used by the USB controller.
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This cannot be used to turn any pin into a USB pin; it only
+//! configures a USB pin for proper operation.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeUSBAnalog(unsigned long ulPort, unsigned char ucPins)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(GPIOBaseValid(ulPort));
+
+    //
+    // Make the pin(s) be inputs.
+    //
+    GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_IN);
+
+    //
+    // Set the pad(s) for analog operation.
+    //
+    GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_ANALOG);
+}
+
 //*****************************************************************************
 //
 //! Configures pin(s) for use by the USB peripheral.
@@ -1366,94 +1571,12 @@ GPIOPinTypeUSBDigital(unsigned long ulPort, unsigned char ucPins)
     GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
 }
 
-//*****************************************************************************
-//
-//! Configures pin(s) for use by the USB peripheral.
-//!
-//! \param ulPort is the base address of the GPIO port.
-//! \param ucPins is the bit-packed representation of the pin(s).
-//!
-//! Some USB analog pins must be properly configured for the USB peripheral to
-//! function correctly.  This function provides the proper configuration for
-//! any USB pin(s).  This can also be used to configure the EPEN and PFAULT pins
-//! so that they are no longer used by the USB controller.
-//!
-//! The pin(s) are specified using a bit-packed byte, where each bit that is
-//! set identifies the pin to be accessed, and where bit 0 of the byte
-//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
-//!
-//! \note This cannot be used to turn any pin into a USB pin; it only
-//! configures a USB pin for proper operation.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-GPIOPinTypeUSBAnalog(unsigned long ulPort, unsigned char ucPins)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(GPIOBaseValid(ulPort));
-
-    //
-    // Make the pin(s) be inputs.
-    //
-    GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_IN);
-
-    //
-    // Set the pad(s) for analog operation.
-    //
-    GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_ANALOG);
-}
-
-//*****************************************************************************
-//
-//! Configures pin(s) for use by the I2S peripheral.
-//!
-//! \param ulPort is the base address of the GPIO port.
-//! \param ucPins is the bit-packed representation of the pin(s).
-//!
-//! Some I2S pins must be properly configured for the I2S peripheral to
-//! function correctly.  This function provides a typical configuration for
-//! the digital I2S pin(s); other configurations may work as well depending
-//! upon the board setup (for example, using the on-chip pull-ups).
-//!
-//! The pin(s) are specified using a bit-packed byte, where each bit that is
-//! set identifies the pin to be accessed, and where bit 0 of the byte
-//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
-//!
-//! \note This cannot be used to turn any pin into a I2S pin; it only
-//! configures a I2S pin for proper operation.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-GPIOPinTypeI2S(unsigned long ulPort, unsigned char ucPins)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(GPIOBaseValid(ulPort));
-
-    //
-    // Make the pin(s) be peripheral controlled.
-    //
-    GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW);
-
-    //
-    // Set the pad(s) for standard push-pull operation.
-    //
-    GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
-}
-
 //*****************************************************************************
 //
 //! Configures the alternate function of a GPIO pin.
 //!
-//! \param ulPinConfig is the pin configuration value, specified as one of the
-//! \b GPIO_P??_??? values.
+//! \param ulPinConfig is the pin configuration value, specified as only one of
+//! the \b GPIO_P??_??? values.
 //!
 //! This function configures the pin mux that selects the peripheral function
 //! associated with a particular GPIO pin.  Only one peripheral function at a
@@ -1486,7 +1609,7 @@ GPIOPinConfigure(unsigned long ulPinConfig)
     // Get the base address of the GPIO module, selecting either the APB or the
     // AHB aperture as appropriate.
     //
-    if(HWREG(SYSCTL_GPIOHSCTL) & (1 << ulBase))
+    if(HWREG(SYSCTL_GPIOHBCTL) & (1 << ulBase))
     {
         ulBase = g_pulGPIOBaseAddrs[(ulBase << 1) + 1];
     }
diff --git a/src/platform/lm3s/gpio.h b/src/platform/lm3s/driverlib/gpio.h
similarity index 89%
rename from src/platform/lm3s/gpio.h
rename to src/platform/lm3s/driverlib/gpio.h
index bd17047e..56a5357e 100755
--- a/src/platform/lm3s/gpio.h
+++ b/src/platform/lm3s/driverlib/gpio.h
@@ -2,26 +2,23 @@
 //
 // gpio.h - Defines and Macros for GPIO API.
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2011 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
+// This is part of revision 7611 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -124,6 +121,7 @@ extern "C"
 // GPIO pin A2
 //
 #define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_TXD2           0x00000803
 #define GPIO_PA2_PWM4           0x00000804
 #define GPIO_PA2_I2S0RXSD       0x00000809
 
@@ -131,6 +129,7 @@ extern "C"
 // GPIO pin A3
 //
 #define GPIO_PA3_SSI0FSS        0x00000c01
+#define GPIO_PA3_TXD1           0x00000c03
 #define GPIO_PA3_PWM5           0x00000c04
 #define GPIO_PA3_I2S0RXMCLK     0x00000c09
 
@@ -138,6 +137,7 @@ extern "C"
 // GPIO pin A4
 //
 #define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_TXD0           0x00001003
 #define GPIO_PA4_PWM6           0x00001004
 #define GPIO_PA4_CAN0RX         0x00001005
 #define GPIO_PA4_I2S0TXSCK      0x00001009
@@ -146,6 +146,7 @@ extern "C"
 // GPIO pin A5
 //
 #define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_RXDV           0x00001403
 #define GPIO_PA5_PWM7           0x00001404
 #define GPIO_PA5_CAN0TX         0x00001405
 #define GPIO_PA5_I2S0TXWS       0x00001409
@@ -155,6 +156,7 @@ extern "C"
 //
 #define GPIO_PA6_I2C1SCL        0x00001801
 #define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_RXCK           0x00001803
 #define GPIO_PA6_PWM0           0x00001804
 #define GPIO_PA6_PWM4           0x00001805
 #define GPIO_PA6_CAN0RX         0x00001806
@@ -166,6 +168,7 @@ extern "C"
 //
 #define GPIO_PA7_I2C1SDA        0x00001c01
 #define GPIO_PA7_CCP4           0x00001c02
+#define GPIO_PA7_RXER           0x00001c03
 #define GPIO_PA7_PWM1           0x00001c04
 #define GPIO_PA7_PWM5           0x00001c05
 #define GPIO_PA7_CAN0TX         0x00001c06
@@ -241,6 +244,7 @@ extern "C"
 // GPIO pin B7
 //
 #define GPIO_PB7_NMI            0x00011c04
+#define GPIO_PB7_RXD1           0x00011c07
 
 //
 // GPIO pin C0
@@ -267,6 +271,7 @@ extern "C"
 //
 #define GPIO_PC4_CCP5           0x00021001
 #define GPIO_PC4_PHA0           0x00021002
+#define GPIO_PC4_TXD3           0x00021003
 #define GPIO_PC4_PWM6           0x00021004
 #define GPIO_PC4_CCP2           0x00021005
 #define GPIO_PC4_CCP4           0x00021006
@@ -316,6 +321,7 @@ extern "C"
 #define GPIO_PD0_U2RX           0x00030004
 #define GPIO_PD0_U1RX           0x00030005
 #define GPIO_PD0_CCP6           0x00030006
+#define GPIO_PD0_RXDV           0x00030007
 #define GPIO_PD0_I2S0RXSCK      0x00030008
 #define GPIO_PD0_U1CTS          0x00030009
 
@@ -328,6 +334,7 @@ extern "C"
 #define GPIO_PD1_U2TX           0x00030404
 #define GPIO_PD1_U1TX           0x00030405
 #define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_TXER           0x00030407
 #define GPIO_PD1_I2S0RXWS       0x00030408
 #define GPIO_PD1_U1DCD          0x00030409
 #define GPIO_PD1_CCP2           0x0003040a
@@ -356,6 +363,7 @@ extern "C"
 //
 #define GPIO_PD4_CCP0           0x00031001
 #define GPIO_PD4_CCP3           0x00031002
+#define GPIO_PD4_TXD3           0x00031004
 #define GPIO_PD4_I2S0RXSD       0x00031008
 #define GPIO_PD4_U1RI           0x00031009
 #define GPIO_PD4_EPI0S19        0x0003100a
@@ -365,6 +373,7 @@ extern "C"
 //
 #define GPIO_PD5_CCP2           0x00031401
 #define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_TXD2           0x00031404
 #define GPIO_PD5_I2S0RXMCLK     0x00031408
 #define GPIO_PD5_U2RX           0x00031409
 #define GPIO_PD5_EPI0S28        0x0003140a
@@ -373,6 +382,7 @@ extern "C"
 // GPIO pin D6
 //
 #define GPIO_PD6_FAULT0         0x00031801
+#define GPIO_PD6_TXD1           0x00031804
 #define GPIO_PD6_I2S0TXSCK      0x00031808
 #define GPIO_PD6_U2TX           0x00031809
 #define GPIO_PD6_EPI0S29        0x0003180a
@@ -383,6 +393,7 @@ extern "C"
 #define GPIO_PD7_IDX0           0x00031c01
 #define GPIO_PD7_C0O            0x00031c02
 #define GPIO_PD7_CCP1           0x00031c03
+#define GPIO_PD7_TXD0           0x00031c04
 #define GPIO_PD7_I2S0TXWS       0x00031c08
 #define GPIO_PD7_U1DTR          0x00031c09
 #define GPIO_PD7_EPI0S30        0x00031c0a
@@ -430,15 +441,18 @@ extern "C"
 // GPIO pin E4
 //
 #define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_CAN2RX         0x00041002
 #define GPIO_PE4_FAULT0         0x00041004
 #define GPIO_PE4_U2TX           0x00041005
 #define GPIO_PE4_CCP2           0x00041006
+#define GPIO_PE4_RXD0           0x00041007
 #define GPIO_PE4_I2S0TXWS       0x00041009
 
 //
 // GPIO pin E5
 //
 #define GPIO_PE5_CCP5           0x00041401
+#define GPIO_PE5_CAN2TX         0x00041402
 #define GPIO_PE5_I2S0TXSD       0x00041409
 
 //
@@ -461,6 +475,7 @@ extern "C"
 #define GPIO_PF0_CAN1RX         0x00050001
 #define GPIO_PF0_PHB0           0x00050002
 #define GPIO_PF0_PWM0           0x00050003
+#define GPIO_PF0_RXCK           0x00050004
 #define GPIO_PF0_I2S0TXSD       0x00050008
 #define GPIO_PF0_U1DSR          0x00050009
 
@@ -470,6 +485,7 @@ extern "C"
 #define GPIO_PF1_CAN1TX         0x00050401
 #define GPIO_PF1_IDX1           0x00050402
 #define GPIO_PF1_PWM1           0x00050403
+#define GPIO_PF1_RXER           0x00050404
 #define GPIO_PF1_I2S0TXMCLK     0x00050408
 #define GPIO_PF1_U1RTS          0x00050409
 #define GPIO_PF1_CCP3           0x0005040a
@@ -479,6 +495,7 @@ extern "C"
 //
 #define GPIO_PF2_LED1           0x00050801
 #define GPIO_PF2_PWM4           0x00050802
+#define GPIO_PF2_PHYINT         0x00050803
 #define GPIO_PF2_PWM2           0x00050804
 #define GPIO_PF2_SSI1CLK        0x00050809
 
@@ -487,6 +504,7 @@ extern "C"
 //
 #define GPIO_PF3_LED0           0x00050c01
 #define GPIO_PF3_PWM5           0x00050c02
+#define GPIO_PF3_MDC            0x00050c03
 #define GPIO_PF3_PWM3           0x00050c04
 #define GPIO_PF3_SSI1FSS        0x00050c09
 
@@ -495,6 +513,7 @@ extern "C"
 //
 #define GPIO_PF4_CCP0           0x00051001
 #define GPIO_PF4_C0O            0x00051002
+#define GPIO_PF4_MDIO           0x00051003
 #define GPIO_PF4_FAULT0         0x00051004
 #define GPIO_PF4_EPI0S12        0x00051008
 #define GPIO_PF4_SSI1RX         0x00051009
@@ -504,6 +523,7 @@ extern "C"
 //
 #define GPIO_PF5_CCP2           0x00051401
 #define GPIO_PF5_C1O            0x00051402
+#define GPIO_PF5_RXD3           0x00051403
 #define GPIO_PF5_EPI0S15        0x00051408
 #define GPIO_PF5_SSI1TX         0x00051409
 
@@ -512,6 +532,7 @@ extern "C"
 //
 #define GPIO_PF6_CCP1           0x00051801
 #define GPIO_PF6_C2O            0x00051802
+#define GPIO_PF6_RXD2           0x00051803
 #define GPIO_PF6_PHA0           0x00051804
 #define GPIO_PF6_I2S0TXMCLK     0x00051809
 #define GPIO_PF6_U1RTS          0x0005180a
@@ -520,6 +541,7 @@ extern "C"
 // GPIO pin F7
 //
 #define GPIO_PF7_CCP4           0x00051c01
+#define GPIO_PF7_RXD1           0x00051c03
 #define GPIO_PF7_PHB0           0x00051c04
 #define GPIO_PF7_EPI0S12        0x00051c08
 #define GPIO_PF7_FAULT1         0x00051c09
@@ -547,6 +569,7 @@ extern "C"
 // GPIO pin G2
 //
 #define GPIO_PG2_PWM0           0x00060801
+#define GPIO_PG2_COL            0x00060803
 #define GPIO_PG2_FAULT0         0x00060804
 #define GPIO_PG2_IDX1           0x00060808
 #define GPIO_PG2_I2S0RXSD       0x00060809
@@ -555,6 +578,7 @@ extern "C"
 // GPIO pin G3
 //
 #define GPIO_PG3_PWM1           0x00060c01
+#define GPIO_PG3_CRS            0x00060c03
 #define GPIO_PG3_FAULT2         0x00060c04
 #define GPIO_PG3_FAULT0         0x00060c08
 #define GPIO_PG3_I2S0RXMCLK     0x00060c09
@@ -563,6 +587,7 @@ extern "C"
 // GPIO pin G4
 //
 #define GPIO_PG4_CCP3           0x00061001
+#define GPIO_PG4_RXD0           0x00061003
 #define GPIO_PG4_FAULT1         0x00061004
 #define GPIO_PG4_EPI0S15        0x00061008
 #define GPIO_PG4_PWM6           0x00061009
@@ -572,6 +597,7 @@ extern "C"
 // GPIO pin G5
 //
 #define GPIO_PG5_CCP5           0x00061401
+#define GPIO_PG5_TXEN           0x00061403
 #define GPIO_PG5_IDX0           0x00061404
 #define GPIO_PG5_FAULT1         0x00061405
 #define GPIO_PG5_PWM7           0x00061408
@@ -582,6 +608,7 @@ extern "C"
 // GPIO pin G6
 //
 #define GPIO_PG6_PHA1           0x00061801
+#define GPIO_PG6_TXCK           0x00061803
 #define GPIO_PG6_PWM6           0x00061804
 #define GPIO_PG6_FAULT1         0x00061808
 #define GPIO_PG6_I2S0RXWS       0x00061809
@@ -591,6 +618,7 @@ extern "C"
 // GPIO pin G7
 //
 #define GPIO_PG7_PHB1           0x00061c01
+#define GPIO_PG7_TXER           0x00061c03
 #define GPIO_PG7_PWM7           0x00061c04
 #define GPIO_PG7_CCP5           0x00061c08
 #define GPIO_PG7_EPI0S31        0x00061c09
@@ -618,6 +646,7 @@ extern "C"
 #define GPIO_PH2_C1O            0x00070802
 #define GPIO_PH2_FAULT3         0x00070804
 #define GPIO_PH2_EPI0S1         0x00070808
+#define GPIO_PH2_TXD3           0x00070809
 
 //
 // GPIO pin H3
@@ -626,18 +655,21 @@ extern "C"
 #define GPIO_PH3_FAULT0         0x00070c02
 #define GPIO_PH3_USB0EPEN       0x00070c04
 #define GPIO_PH3_EPI0S0         0x00070c08
+#define GPIO_PH3_TXD2           0x00070c09
 
 //
 // GPIO pin H4
 //
 #define GPIO_PH4_USB0PFLT       0x00071004
 #define GPIO_PH4_EPI0S10        0x00071008
+#define GPIO_PH4_TXD1           0x00071009
 #define GPIO_PH4_SSI1CLK        0x0007100b
 
 //
 // GPIO pin H5
 //
 #define GPIO_PH5_EPI0S11        0x00071408
+#define GPIO_PH5_TXD0           0x00071409
 #define GPIO_PH5_FAULT2         0x0007140a
 #define GPIO_PH5_SSI1FSS        0x0007140b
 
@@ -645,12 +677,14 @@ extern "C"
 // GPIO pin H6
 //
 #define GPIO_PH6_EPI0S26        0x00071808
+#define GPIO_PH6_RXDV           0x00071809
 #define GPIO_PH6_PWM4           0x0007180a
 #define GPIO_PH6_SSI1RX         0x0007180b
 
 //
 // GPIO pin H7
 //
+#define GPIO_PH7_RXCK           0x00071c03
 #define GPIO_PH7_EPI0S27        0x00071c08
 #define GPIO_PH7_PWM5           0x00071c0a
 #define GPIO_PH7_SSI1TX         0x00071c0b
@@ -658,6 +692,7 @@ extern "C"
 //
 // GPIO pin J0
 //
+#define GPIO_PJ0_RXER           0x00080003
 #define GPIO_PJ0_EPI0S16        0x00080008
 #define GPIO_PJ0_PWM0           0x0008000a
 #define GPIO_PJ0_I2C1SCL        0x0008000b
@@ -742,6 +777,9 @@ extern void GPIOPinConfigure(unsigned long ulPinConfig);
 extern void GPIOPinTypeADC(unsigned long ulPort, unsigned char ucPins);
 extern void GPIOPinTypeCAN(unsigned long ulPort, unsigned char ucPins);
 extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPinTypeEPI(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPinTypeEthernetLED(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPinTypeEthernetMII(unsigned long ulPort, unsigned char ucPins);
 extern void GPIOPinTypeGPIOInput(unsigned long ulPort, unsigned char ucPins);
 extern void GPIOPinTypeGPIOOutput(unsigned long ulPort, unsigned char ucPins);
 extern void GPIOPinTypeGPIOOutputOD(unsigned long ulPort,
diff --git a/src/platform/lm3s/interrupt.c b/src/platform/lm3s/driverlib/interrupt.c
similarity index 70%
rename from src/platform/lm3s/interrupt.c
rename to src/platform/lm3s/driverlib/interrupt.c
index 11421a81..d24a8a27 100755
--- a/src/platform/lm3s/interrupt.c
+++ b/src/platform/lm3s/driverlib/interrupt.c
@@ -2,26 +2,23 @@
 //
 // interrupt.c - Driver for the NVIC Interrupt Controller.
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2011 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
+// This is part of revision 7611 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -32,12 +29,12 @@
 //
 //*****************************************************************************
 
-#include "hw_ints.h"
-#include "hw_nvic.h"
-#include "hw_types.h"
-#include "cpu.h"
-#include "debug.h"
-#include "interrupt.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_nvic.h"
+#include "inc/hw_types.h"
+#include "driverlib/cpu.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
 
 //*****************************************************************************
 //
@@ -100,13 +97,18 @@ IntDefaultHandler(void)
 //
 //*****************************************************************************
 #if defined(ewarm)
+#pragma data_alignment=1024
 static __no_init void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) @ "VTABLE";
 #elif defined(sourcerygxx)
 static __attribute__((section(".cs3.region-head.ram")))
+void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) __attribute__ ((aligned(1024)));
+#elif defined(ccs) || defined(DOXYGEN)
+#pragma DATA_ALIGN(g_pfnRAMVectors, 1024)
+#pragma DATA_SECTION(g_pfnRAMVectors, ".vtable")
 void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void);
 #else
 static __attribute__((section("vtable")))
-void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void);
+void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) __attribute__ ((aligned(1024)));
 #endif
 
 //*****************************************************************************
@@ -183,11 +185,9 @@ IntMasterDisable(void)
 //! to ensure that the SRAM vector table is located at the beginning of SRAM;
 //! otherwise NVIC will not look in the correct portion of memory for the
 //! vector table (it requires the vector table be on a 1 kB memory alignment).
-//! Normally, the SRAM vector table is so placed via the use of linker scripts;
-//! some tool chains, such as the evaluation version of RV-MDK, do not support
-//! linker scripts and therefore will not produce a valid executable.  See the
-//! discussion of compile-time versus run-time interrupt handler registration
-//! in the introduction to this chapter.
+//! Normally, the SRAM vector table is so placed via the use of linker scripts.
+//! See the discussion of compile-time versus run-time interrupt handler
+//! registration in the introduction to this chapter.
 //!
 //! \return None.
 //
@@ -542,6 +542,181 @@ IntDisable(unsigned long ulInterrupt)
     }
 }
 
+//*****************************************************************************
+//
+//! Pends an interrupt.
+//!
+//! \param ulInterrupt specifies the interrupt to be pended.
+//!
+//! The specified interrupt is pended in the interrupt controller.  This will
+//! cause the interrupt controller to execute the corresponding interrupt
+//! handler at the next available time, based on the current interrupt state
+//! priorities.  For example, if called by a higher priority interrupt handler,
+//! the specified interrupt handler will not be called until after the current
+//! interrupt handler has completed execution.  The interrupt must have been
+//! enabled for it to be called.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+IntPendSet(unsigned long ulInterrupt)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulInterrupt < NUM_INTERRUPTS);
+
+    //
+    // Determine the interrupt to pend.
+    //
+    if(ulInterrupt == FAULT_NMI)
+    {
+        //
+        // Pend the NMI interrupt.
+        //
+        HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_NMI_SET;
+    }
+    else if(ulInterrupt == FAULT_PENDSV)
+    {
+        //
+        // Pend the PendSV interrupt.
+        //
+        HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PEND_SV;
+    }
+    else if(ulInterrupt == FAULT_SYSTICK)
+    {
+        //
+        // Pend the SysTick interrupt.
+        //
+        HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTSET;
+    }
+    else if((ulInterrupt >= 16) && (ulInterrupt <= 47))
+    {
+        //
+        // Pend the general interrupt.
+        //
+        HWREG(NVIC_PEND0) = 1 << (ulInterrupt - 16);
+    }
+    else if(ulInterrupt >= 48)
+    {
+        //
+        // Pend the general interrupt.
+        //
+        HWREG(NVIC_PEND1) = 1 << (ulInterrupt - 48);
+    }
+}
+
+//*****************************************************************************
+//
+//! Unpends an interrupt.
+//!
+//! \param ulInterrupt specifies the interrupt to be unpended.
+//!
+//! The specified interrupt is unpended in the interrupt controller.  This will
+//! cause any previously generated interrupts that have not been handled yet
+//! (due to higher priority interrupts or the interrupt no having been enabled
+//! yet) to be discarded.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+IntPendClear(unsigned long ulInterrupt)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulInterrupt < NUM_INTERRUPTS);
+
+    //
+    // Determine the interrupt to unpend.
+    //
+    if(ulInterrupt == FAULT_PENDSV)
+    {
+        //
+        // Unpend the PendSV interrupt.
+        //
+        HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_UNPEND_SV;
+    }
+    else if(ulInterrupt == FAULT_SYSTICK)
+    {
+        //
+        // Unpend the SysTick interrupt.
+        //
+        HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTCLR;
+    }
+    else if((ulInterrupt >= 16) && (ulInterrupt <= 47))
+    {
+        //
+        // Unpend the general interrupt.
+        //
+        HWREG(NVIC_UNPEND0) = 1 << (ulInterrupt - 16);
+    }
+    else if(ulInterrupt >= 48)
+    {
+        //
+        // Unpend the general interrupt.
+        //
+        HWREG(NVIC_UNPEND1) = 1 << (ulInterrupt - 48);
+    }
+}
+
+//*****************************************************************************
+//
+//! Sets the priority masking level
+//!
+//! \param ulPriorityMask is the priority level that will be masked.
+//!
+//! This function sets the interrupt priority masking level so that all
+//! interrupts at the specified or lesser priority level is masked.  This
+//! can be used to globally disable a set of interrupts with priority below
+//! a predetermined threshold.  A value of 0 disables priority
+//! masking.
+//!
+//! Smaller numbers correspond to higher interrupt priorities.  So for example
+//! a priority level mask of 4 will allow interrupts of priority level 0-3,
+//! and interrupts with a numerical priority of 4 and greater will be blocked.
+//!
+//! The hardware priority mechanism will only look at the upper N bits of the
+//! priority level (where N is 3 for the Stellaris family), so any
+//! prioritization must be performed in those bits.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+IntPriorityMaskSet(unsigned long ulPriorityMask)
+{
+    CPUbasepriSet(ulPriorityMask);
+}
+
+//*****************************************************************************
+//
+//! Gets the priority masking level
+//!
+//! This function gets the current setting of the interrupt priority masking
+//! level.  The value returned is the priority level such that all interrupts
+//! of that and lesser priority are masked.  A value of 0 means that priority
+//! masking is disabled.
+//!
+//! Smaller numbers correspond to higher interrupt priorities.  So for example
+//! a priority level mask of 4 will allow interrupts of priority level 0-3,
+//! and interrupts with a numerical priority of 4 and greater will be blocked.
+//!
+//! The hardware priority mechanism will only look at the upper N bits of the
+//! priority level (where N is 3 for the Stellaris family), so any
+//! prioritization must be performed in those bits.
+//!
+//! \return Returns the value of the interrupt priority level mask.
+//
+//*****************************************************************************
+unsigned long
+IntPriorityMaskGet(void)
+{
+    return(CPUbasepriGet());
+}
+
 //*****************************************************************************
 //
 // Close the Doxygen group.
diff --git a/src/platform/lm3s/interrupt.h b/src/platform/lm3s/driverlib/interrupt.h
similarity index 65%
rename from src/platform/lm3s/interrupt.h
rename to src/platform/lm3s/driverlib/interrupt.h
index ca91271c..1a52eca4 100755
--- a/src/platform/lm3s/interrupt.h
+++ b/src/platform/lm3s/driverlib/interrupt.h
@@ -2,26 +2,23 @@
 //
 // interrupt.h - Prototypes for the NVIC Interrupt Controller Driver.
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2011 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
+// This is part of revision 7611 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -63,6 +60,10 @@ extern void IntPrioritySet(unsigned long ulInterrupt,
 extern long IntPriorityGet(unsigned long ulInterrupt);
 extern void IntEnable(unsigned long ulInterrupt);
 extern void IntDisable(unsigned long ulInterrupt);
+extern void IntPendSet(unsigned long ulInterrupt);
+extern void IntPendClear(unsigned long ulInterrupt);
+extern void IntPriorityMaskSet(unsigned long ulPriorityMask);
+extern unsigned long IntPriorityMaskGet(void);
 
 //*****************************************************************************
 //
diff --git a/src/platform/lm3s/driverlib/pin_map.h b/src/platform/lm3s/driverlib/pin_map.h
new file mode 100755
index 00000000..f17b4ad9
--- /dev/null
+++ b/src/platform/lm3s/driverlib/pin_map.h
@@ -0,0 +1,47314 @@
+//*****************************************************************************
+//
+// pin_map.h - Mapping of peripherals to pins for all parts.
+//
+// Copyright (c) 2007-2011 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 7611 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __PIN_MAP_H__
+#define __PIN_MAP_H__
+
+//*****************************************************************************
+//
+// LM3S101 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S101
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOB
+#define C0O_PORT                GPIO_PORTB_BASE
+#define C0O_PIN                 GPIO_PIN_5
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define SSICLK_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSICLK_PORT             GPIO_PORTA_BASE
+#define SSICLK_PIN              GPIO_PIN_2
+
+#define SSIFSS_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSIFSS_PORT             GPIO_PORTA_BASE
+#define SSIFSS_PIN              GPIO_PIN_3
+
+#define SSIRX_PERIPH            SYSCTL_PERIPH_GPIOA
+#define SSIRX_PORT              GPIO_PORTA_BASE
+#define SSIRX_PIN               GPIO_PIN_4
+
+#define SSITX_PERIPH            SYSCTL_PERIPH_GPIOA
+#define SSITX_PORT              GPIO_PORTA_BASE
+#define SSITX_PIN               GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define 32KHZ_PERIPH            SYSCTL_PERIPH_GPIOB
+#define 32KHZ_PORT              GPIO_PORTB_BASE
+#define 32KHZ_PIN               GPIO_PIN_1
+
+#endif // PART_LM3S101
+
+//*****************************************************************************
+//
+// LM3S102 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S102
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOB
+#define C0O_PORT                GPIO_PORTB_BASE
+#define C0O_PIN                 GPIO_PIN_5
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP1_PORT               GPIO_PORTB_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define I2CSCL_PERIPH           SYSCTL_PERIPH_GPIOB
+#define I2CSCL_PORT             GPIO_PORTB_BASE
+#define I2CSCL_PIN              GPIO_PIN_2
+
+#define I2CSDA_PERIPH           SYSCTL_PERIPH_GPIOB
+#define I2CSDA_PORT             GPIO_PORTB_BASE
+#define I2CSDA_PIN              GPIO_PIN_3
+
+#define SSICLK_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSICLK_PORT             GPIO_PORTA_BASE
+#define SSICLK_PIN              GPIO_PIN_2
+
+#define SSIFSS_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSIFSS_PORT             GPIO_PORTA_BASE
+#define SSIFSS_PIN              GPIO_PIN_3
+
+#define SSIRX_PERIPH            SYSCTL_PERIPH_GPIOA
+#define SSIRX_PORT              GPIO_PORTA_BASE
+#define SSIRX_PIN               GPIO_PIN_4
+
+#define SSITX_PERIPH            SYSCTL_PERIPH_GPIOA
+#define SSITX_PORT              GPIO_PORTA_BASE
+#define SSITX_PIN               GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define 32KHZ_PERIPH            SYSCTL_PERIPH_GPIOB
+#define 32KHZ_PORT              GPIO_PORTB_BASE
+#define 32KHZ_PIN               GPIO_PIN_1
+
+#endif // PART_LM3S102
+
+//*****************************************************************************
+//
+// LM3S300 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S300
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOD
+#define C0O_PORT                GPIO_PORTD_BASE
+#define C0O_PIN                 GPIO_PIN_7
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1O_PERIPH              SYSCTL_PERIPH_GPIOC
+#define C1O_PORT                GPIO_PORTC_BASE
+#define C1O_PIN                 GPIO_PIN_5
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_5
+
+#define C2O_PERIPH              SYSCTL_PERIPH_GPIOC
+#define C2O_PORT                GPIO_PORTC_BASE
+#define C2O_PIN                 GPIO_PIN_6
+
+#define C2_MINUS_PERIPH         SYSCTL_PERIPH_GPIOC
+#define C2_MINUS_PORT           GPIO_PORTC_BASE
+#define C2_MINUS_PIN            GPIO_PIN_7
+
+#define C2_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C2_PLUS_PORT            GPIO_PORTC_BASE
+#define C2_PLUS_PIN             GPIO_PIN_6
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP0_PORT               GPIO_PORTD_BASE
+#define CCP0_PIN                GPIO_PIN_4
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOE
+#define CCP1_PORT               GPIO_PORTE_BASE
+#define CCP1_PIN                GPIO_PIN_3
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP2_PORT               GPIO_PORTD_BASE
+#define CCP2_PIN                GPIO_PIN_5
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOE
+#define CCP3_PORT               GPIO_PORTE_BASE
+#define CCP3_PIN                GPIO_PIN_4
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOE
+#define CCP4_PORT               GPIO_PORTE_BASE
+#define CCP4_PIN                GPIO_PIN_2
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOE
+#define CCP5_PORT               GPIO_PORTE_BASE
+#define CCP5_PIN                GPIO_PIN_5
+
+#define I2CSCL_PERIPH           SYSCTL_PERIPH_GPIOB
+#define I2CSCL_PORT             GPIO_PORTB_BASE
+#define I2CSCL_PIN              GPIO_PIN_2
+
+#define I2CSDA_PERIPH           SYSCTL_PERIPH_GPIOB
+#define I2CSDA_PORT             GPIO_PORTB_BASE
+#define I2CSDA_PIN              GPIO_PIN_3
+
+#define SSICLK_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSICLK_PORT             GPIO_PORTA_BASE
+#define SSICLK_PIN              GPIO_PIN_2
+
+#define SSIFSS_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSIFSS_PORT             GPIO_PORTA_BASE
+#define SSIFSS_PIN              GPIO_PIN_3
+
+#define SSIRX_PERIPH            SYSCTL_PERIPH_GPIOA
+#define SSIRX_PORT              GPIO_PORTA_BASE
+#define SSIRX_PIN               GPIO_PIN_4
+
+#define SSITX_PERIPH            SYSCTL_PERIPH_GPIOA
+#define SSITX_PORT              GPIO_PORTA_BASE
+#define SSITX_PIN               GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#endif // PART_LM3S300
+
+//*****************************************************************************
+//
+// LM3S301 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S301
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOD
+#define C0O_PORT                GPIO_PORTD_BASE
+#define C0O_PIN                 GPIO_PIN_7
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1O_PERIPH              SYSCTL_PERIPH_GPIOC
+#define C1O_PORT                GPIO_PORTC_BASE
+#define C1O_PIN                 GPIO_PIN_5
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_5
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP2_PORT               GPIO_PORTD_BASE
+#define CCP2_PIN                GPIO_PIN_5
+
+#define FAULT_PERIPH            SYSCTL_PERIPH_GPIOD
+#define FAULT_PORT              GPIO_PORTD_BASE
+#define FAULT_PIN               GPIO_PIN_6
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM0_PORT               GPIO_PORTD_BASE
+#define PWM0_PIN                GPIO_PIN_0
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM1_PORT               GPIO_PORTD_BASE
+#define PWM1_PIN                GPIO_PIN_1
+
+#define SSICLK_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSICLK_PORT             GPIO_PORTA_BASE
+#define SSICLK_PIN              GPIO_PIN_2
+
+#define SSIFSS_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSIFSS_PORT             GPIO_PORTA_BASE
+#define SSIFSS_PIN              GPIO_PIN_3
+
+#define SSIRX_PERIPH            SYSCTL_PERIPH_GPIOA
+#define SSIRX_PORT              GPIO_PORTA_BASE
+#define SSIRX_PIN               GPIO_PIN_4
+
+#define SSITX_PERIPH            SYSCTL_PERIPH_GPIOA
+#define SSITX_PORT              GPIO_PORTA_BASE
+#define SSITX_PIN               GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#endif // PART_LM3S301
+
+//*****************************************************************************
+//
+// LM3S308 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S308
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP1_PORT               GPIO_PORTC_BASE
+#define CCP1_PIN                GPIO_PIN_5
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_1
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP3_PORT               GPIO_PORTC_BASE
+#define CCP3_PIN                GPIO_PIN_6
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP4_PORT               GPIO_PORTC_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP5_PORT               GPIO_PORTB_BASE
+#define CCP5_PIN                GPIO_PIN_5
+
+#define I2CSCL_PERIPH           SYSCTL_PERIPH_GPIOB
+#define I2CSCL_PORT             GPIO_PORTB_BASE
+#define I2CSCL_PIN              GPIO_PIN_2
+
+#define I2CSDA_PERIPH           SYSCTL_PERIPH_GPIOB
+#define I2CSDA_PORT             GPIO_PORTB_BASE
+#define I2CSDA_PIN              GPIO_PIN_3
+
+#define SSICLK_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSICLK_PORT             GPIO_PORTA_BASE
+#define SSICLK_PIN              GPIO_PIN_2
+
+#define SSIFSS_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSIFSS_PORT             GPIO_PORTA_BASE
+#define SSIFSS_PIN              GPIO_PIN_3
+
+#define SSIRX_PERIPH            SYSCTL_PERIPH_GPIOA
+#define SSIRX_PORT              GPIO_PORTA_BASE
+#define SSIRX_PIN               GPIO_PIN_4
+
+#define SSITX_PERIPH            SYSCTL_PERIPH_GPIOA
+#define SSITX_PORT              GPIO_PORTA_BASE
+#define SSITX_PIN               GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#endif // PART_LM3S308
+
+//*****************************************************************************
+//
+// LM3S310 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S310
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOD
+#define C0O_PORT                GPIO_PORTD_BASE
+#define C0O_PIN                 GPIO_PIN_7
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1O_PERIPH              SYSCTL_PERIPH_GPIOC
+#define C1O_PORT                GPIO_PORTC_BASE
+#define C1O_PIN                 GPIO_PIN_5
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_5
+
+#define C2O_PERIPH              SYSCTL_PERIPH_GPIOC
+#define C2O_PORT                GPIO_PORTC_BASE
+#define C2O_PIN                 GPIO_PIN_6
+
+#define C2_MINUS_PERIPH         SYSCTL_PERIPH_GPIOC
+#define C2_MINUS_PORT           GPIO_PORTC_BASE
+#define C2_MINUS_PIN            GPIO_PIN_7
+
+#define C2_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C2_PLUS_PORT            GPIO_PORTC_BASE
+#define C2_PLUS_PIN             GPIO_PIN_6
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP0_PORT               GPIO_PORTD_BASE
+#define CCP0_PIN                GPIO_PIN_4
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOE
+#define CCP1_PORT               GPIO_PORTE_BASE
+#define CCP1_PIN                GPIO_PIN_3
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP2_PORT               GPIO_PORTD_BASE
+#define CCP2_PIN                GPIO_PIN_5
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOE
+#define CCP3_PORT               GPIO_PORTE_BASE
+#define CCP3_PIN                GPIO_PIN_4
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOE
+#define CCP4_PORT               GPIO_PORTE_BASE
+#define CCP4_PIN                GPIO_PIN_2
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOE
+#define CCP5_PORT               GPIO_PORTE_BASE
+#define CCP5_PIN                GPIO_PIN_5
+
+#define FAULT_PERIPH            SYSCTL_PERIPH_GPIOD
+#define FAULT_PORT              GPIO_PORTD_BASE
+#define FAULT_PIN               GPIO_PIN_6
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM0_PORT               GPIO_PORTD_BASE
+#define PWM0_PIN                GPIO_PIN_0
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM1_PORT               GPIO_PORTD_BASE
+#define PWM1_PIN                GPIO_PIN_1
+
+#define PWM2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define PWM2_PORT               GPIO_PORTB_BASE
+#define PWM2_PIN                GPIO_PIN_0
+
+#define PWM3_PERIPH             SYSCTL_PERIPH_GPIOB
+#define PWM3_PORT               GPIO_PORTB_BASE
+#define PWM3_PIN                GPIO_PIN_1
+
+#define PWM4_PERIPH             SYSCTL_PERIPH_GPIOE
+#define PWM4_PORT               GPIO_PORTE_BASE
+#define PWM4_PIN                GPIO_PIN_0
+
+#define PWM5_PERIPH             SYSCTL_PERIPH_GPIOE
+#define PWM5_PORT               GPIO_PORTE_BASE
+#define PWM5_PIN                GPIO_PIN_1
+
+#define SSICLK_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSICLK_PORT             GPIO_PORTA_BASE
+#define SSICLK_PIN              GPIO_PIN_2
+
+#define SSIFSS_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSIFSS_PORT             GPIO_PORTA_BASE
+#define SSIFSS_PIN              GPIO_PIN_3
+
+#define SSIRX_PERIPH            SYSCTL_PERIPH_GPIOA
+#define SSIRX_PORT              GPIO_PORTA_BASE
+#define SSIRX_PIN               GPIO_PIN_4
+
+#define SSITX_PERIPH            SYSCTL_PERIPH_GPIOA
+#define SSITX_PORT              GPIO_PORTA_BASE
+#define SSITX_PIN               GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#endif // PART_LM3S310
+
+//*****************************************************************************
+//
+// LM3S315 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S315
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOD
+#define C0O_PORT                GPIO_PORTD_BASE
+#define C0O_PIN                 GPIO_PIN_7
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP1_PORT               GPIO_PORTC_BASE
+#define CCP1_PIN                GPIO_PIN_5
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP2_PORT               GPIO_PORTD_BASE
+#define CCP2_PIN                GPIO_PIN_5
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP3_PORT               GPIO_PORTC_BASE
+#define CCP3_PIN                GPIO_PIN_6
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP4_PORT               GPIO_PORTC_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP5_PORT               GPIO_PORTB_BASE
+#define CCP5_PIN                GPIO_PIN_5
+
+#define FAULT_PERIPH            SYSCTL_PERIPH_GPIOD
+#define FAULT_PORT              GPIO_PORTD_BASE
+#define FAULT_PIN               GPIO_PIN_6
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM0_PORT               GPIO_PORTD_BASE
+#define PWM0_PIN                GPIO_PIN_0
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM1_PORT               GPIO_PORTD_BASE
+#define PWM1_PIN                GPIO_PIN_1
+
+#define SSICLK_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSICLK_PORT             GPIO_PORTA_BASE
+#define SSICLK_PIN              GPIO_PIN_2
+
+#define SSIFSS_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSIFSS_PORT             GPIO_PORTA_BASE
+#define SSIFSS_PIN              GPIO_PIN_3
+
+#define SSIRX_PERIPH            SYSCTL_PERIPH_GPIOA
+#define SSIRX_PORT              GPIO_PORTA_BASE
+#define SSIRX_PIN               GPIO_PIN_4
+
+#define SSITX_PERIPH            SYSCTL_PERIPH_GPIOA
+#define SSITX_PORT              GPIO_PORTA_BASE
+#define SSITX_PIN               GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#endif // PART_LM3S315
+
+//*****************************************************************************
+//
+// LM3S316 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S316
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOD
+#define C0O_PORT                GPIO_PORTD_BASE
+#define C0O_PIN                 GPIO_PIN_7
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP0_PORT               GPIO_PORTD_BASE
+#define CCP0_PIN                GPIO_PIN_4
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP1_PORT               GPIO_PORTC_BASE
+#define CCP1_PIN                GPIO_PIN_5
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP2_PORT               GPIO_PORTD_BASE
+#define CCP2_PIN                GPIO_PIN_5
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP3_PORT               GPIO_PORTC_BASE
+#define CCP3_PIN                GPIO_PIN_6
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP4_PORT               GPIO_PORTC_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP5_PORT               GPIO_PORTB_BASE
+#define CCP5_PIN                GPIO_PIN_5
+
+#define FAULT_PERIPH            SYSCTL_PERIPH_GPIOD
+#define FAULT_PORT              GPIO_PORTD_BASE
+#define FAULT_PIN               GPIO_PIN_6
+
+#define I2CSCL_PERIPH           SYSCTL_PERIPH_GPIOB
+#define I2CSCL_PORT             GPIO_PORTB_BASE
+#define I2CSCL_PIN              GPIO_PIN_2
+
+#define I2CSDA_PERIPH           SYSCTL_PERIPH_GPIOB
+#define I2CSDA_PORT             GPIO_PORTB_BASE
+#define I2CSDA_PIN              GPIO_PIN_3
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM0_PORT               GPIO_PORTD_BASE
+#define PWM0_PIN                GPIO_PIN_0
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM1_PORT               GPIO_PORTD_BASE
+#define PWM1_PIN                GPIO_PIN_1
+
+#define PWM2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define PWM2_PORT               GPIO_PORTB_BASE
+#define PWM2_PIN                GPIO_PIN_0
+
+#define PWM3_PERIPH             SYSCTL_PERIPH_GPIOB
+#define PWM3_PORT               GPIO_PORTB_BASE
+#define PWM3_PIN                GPIO_PIN_1
+
+#define SSICLK_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSICLK_PORT             GPIO_PORTA_BASE
+#define SSICLK_PIN              GPIO_PIN_2
+
+#define SSIFSS_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSIFSS_PORT             GPIO_PORTA_BASE
+#define SSIFSS_PIN              GPIO_PIN_3
+
+#define SSIRX_PERIPH            SYSCTL_PERIPH_GPIOA
+#define SSIRX_PORT              GPIO_PORTA_BASE
+#define SSIRX_PIN               GPIO_PIN_4
+
+#define SSITX_PERIPH            SYSCTL_PERIPH_GPIOA
+#define SSITX_PORT              GPIO_PORTA_BASE
+#define SSITX_PIN               GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#endif // PART_LM3S316
+
+//*****************************************************************************
+//
+// LM3S317 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S317
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOB
+#define C0O_PORT                GPIO_PORTB_BASE
+#define C0O_PIN                 GPIO_PIN_5
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP0_PORT               GPIO_PORTD_BASE
+#define CCP0_PIN                GPIO_PIN_4
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP1_PORT               GPIO_PORTC_BASE
+#define CCP1_PIN                GPIO_PIN_5
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP2_PORT               GPIO_PORTD_BASE
+#define CCP2_PIN                GPIO_PIN_5
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP3_PORT               GPIO_PORTC_BASE
+#define CCP3_PIN                GPIO_PIN_6
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP4_PORT               GPIO_PORTC_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP5_PORT               GPIO_PORTC_BASE
+#define CCP5_PIN                GPIO_PIN_4
+
+#define FAULT_PERIPH            SYSCTL_PERIPH_GPIOB
+#define FAULT_PORT              GPIO_PORTB_BASE
+#define FAULT_PIN               GPIO_PIN_3
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM0_PORT               GPIO_PORTD_BASE
+#define PWM0_PIN                GPIO_PIN_0
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM1_PORT               GPIO_PORTD_BASE
+#define PWM1_PIN                GPIO_PIN_1
+
+#define PWM2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define PWM2_PORT               GPIO_PORTB_BASE
+#define PWM2_PIN                GPIO_PIN_0
+
+#define PWM3_PERIPH             SYSCTL_PERIPH_GPIOB
+#define PWM3_PORT               GPIO_PORTB_BASE
+#define PWM3_PIN                GPIO_PIN_1
+
+#define PWM4_PERIPH             SYSCTL_PERIPH_GPIOE
+#define PWM4_PORT               GPIO_PORTE_BASE
+#define PWM4_PIN                GPIO_PIN_0
+
+#define PWM5_PERIPH             SYSCTL_PERIPH_GPIOE
+#define PWM5_PORT               GPIO_PORTE_BASE
+#define PWM5_PIN                GPIO_PIN_1
+
+#define SSICLK_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSICLK_PORT             GPIO_PORTA_BASE
+#define SSICLK_PIN              GPIO_PIN_2
+
+#define SSIFSS_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSIFSS_PORT             GPIO_PORTA_BASE
+#define SSIFSS_PIN              GPIO_PIN_3
+
+#define SSIRX_PERIPH            SYSCTL_PERIPH_GPIOA
+#define SSIRX_PORT              GPIO_PORTA_BASE
+#define SSIRX_PIN               GPIO_PIN_4
+
+#define SSITX_PERIPH            SYSCTL_PERIPH_GPIOA
+#define SSITX_PORT              GPIO_PORTA_BASE
+#define SSITX_PIN               GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#endif // PART_LM3S317
+
+//*****************************************************************************
+//
+// LM3S328 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S328
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP1_PORT               GPIO_PORTC_BASE
+#define CCP1_PIN                GPIO_PIN_5
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_1
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP3_PORT               GPIO_PORTC_BASE
+#define CCP3_PIN                GPIO_PIN_6
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP4_PORT               GPIO_PORTC_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP5_PORT               GPIO_PORTB_BASE
+#define CCP5_PIN                GPIO_PIN_5
+
+#define I2CSCL_PERIPH           SYSCTL_PERIPH_GPIOB
+#define I2CSCL_PORT             GPIO_PORTB_BASE
+#define I2CSCL_PIN              GPIO_PIN_2
+
+#define I2CSDA_PERIPH           SYSCTL_PERIPH_GPIOB
+#define I2CSDA_PORT             GPIO_PORTB_BASE
+#define I2CSDA_PIN              GPIO_PIN_3
+
+#define SSICLK_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSICLK_PORT             GPIO_PORTA_BASE
+#define SSICLK_PIN              GPIO_PIN_2
+
+#define SSIFSS_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSIFSS_PORT             GPIO_PORTA_BASE
+#define SSIFSS_PIN              GPIO_PIN_3
+
+#define SSIRX_PERIPH            SYSCTL_PERIPH_GPIOA
+#define SSIRX_PORT              GPIO_PORTA_BASE
+#define SSIRX_PIN               GPIO_PIN_4
+
+#define SSITX_PERIPH            SYSCTL_PERIPH_GPIOA
+#define SSITX_PORT              GPIO_PORTA_BASE
+#define SSITX_PIN               GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#endif // PART_LM3S328
+
+//*****************************************************************************
+//
+// LM3S600 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S600
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOD
+#define C0O_PORT                GPIO_PORTD_BASE
+#define C0O_PIN                 GPIO_PIN_7
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1O_PERIPH              SYSCTL_PERIPH_GPIOC
+#define C1O_PORT                GPIO_PORTC_BASE
+#define C1O_PIN                 GPIO_PIN_5
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_5
+
+#define C2O_PERIPH              SYSCTL_PERIPH_GPIOC
+#define C2O_PORT                GPIO_PORTC_BASE
+#define C2O_PIN                 GPIO_PIN_6
+
+#define C2_MINUS_PERIPH         SYSCTL_PERIPH_GPIOC
+#define C2_MINUS_PORT           GPIO_PORTC_BASE
+#define C2_MINUS_PIN            GPIO_PIN_7
+
+#define C2_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C2_PLUS_PORT            GPIO_PORTC_BASE
+#define C2_PLUS_PIN             GPIO_PIN_6
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP0_PORT               GPIO_PORTD_BASE
+#define CCP0_PIN                GPIO_PIN_4
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOE
+#define CCP1_PORT               GPIO_PORTE_BASE
+#define CCP1_PIN                GPIO_PIN_3
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP2_PORT               GPIO_PORTD_BASE
+#define CCP2_PIN                GPIO_PIN_5
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOE
+#define CCP3_PORT               GPIO_PORTE_BASE
+#define CCP3_PIN                GPIO_PIN_4
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOE
+#define CCP4_PORT               GPIO_PORTE_BASE
+#define CCP4_PIN                GPIO_PIN_2
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOE
+#define CCP5_PORT               GPIO_PORTE_BASE
+#define CCP5_PIN                GPIO_PIN_5
+
+#define I2CSCL_PERIPH           SYSCTL_PERIPH_GPIOB
+#define I2CSCL_PORT             GPIO_PORTB_BASE
+#define I2CSCL_PIN              GPIO_PIN_2
+
+#define I2CSDA_PERIPH           SYSCTL_PERIPH_GPIOB
+#define I2CSDA_PORT             GPIO_PORTB_BASE
+#define I2CSDA_PIN              GPIO_PIN_3
+
+#define SSICLK_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSICLK_PORT             GPIO_PORTA_BASE
+#define SSICLK_PIN              GPIO_PIN_2
+
+#define SSIFSS_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSIFSS_PORT             GPIO_PORTA_BASE
+#define SSIFSS_PIN              GPIO_PIN_3
+
+#define SSIRX_PERIPH            SYSCTL_PERIPH_GPIOA
+#define SSIRX_PORT              GPIO_PORTA_BASE
+#define SSIRX_PIN               GPIO_PIN_4
+
+#define SSITX_PERIPH            SYSCTL_PERIPH_GPIOA
+#define SSITX_PORT              GPIO_PORTA_BASE
+#define SSITX_PIN               GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#endif // PART_LM3S600
+
+//*****************************************************************************
+//
+// LM3S601 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S601
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOC
+#define C0O_PORT                GPIO_PORTC_BASE
+#define C0O_PIN                 GPIO_PIN_5
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_5
+
+#define C2_MINUS_PERIPH         SYSCTL_PERIPH_GPIOC
+#define C2_MINUS_PORT           GPIO_PORTC_BASE
+#define C2_MINUS_PIN            GPIO_PIN_7
+
+#define C2_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C2_PLUS_PORT            GPIO_PORTC_BASE
+#define C2_PLUS_PIN             GPIO_PIN_6
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP0_PORT               GPIO_PORTD_BASE
+#define CCP0_PIN                GPIO_PIN_4
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOE
+#define CCP1_PORT               GPIO_PORTE_BASE
+#define CCP1_PIN                GPIO_PIN_3
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP2_PORT               GPIO_PORTD_BASE
+#define CCP2_PIN                GPIO_PIN_5
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOE
+#define CCP3_PORT               GPIO_PORTE_BASE
+#define CCP3_PIN                GPIO_PIN_4
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOE
+#define CCP4_PORT               GPIO_PORTE_BASE
+#define CCP4_PIN                GPIO_PIN_2
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOE
+#define CCP5_PORT               GPIO_PORTE_BASE
+#define CCP5_PIN                GPIO_PIN_5
+
+#define FAULT_PERIPH            SYSCTL_PERIPH_GPIOD
+#define FAULT_PORT              GPIO_PORTD_BASE
+#define FAULT_PIN               GPIO_PIN_6
+
+#define I2CSCL_PERIPH           SYSCTL_PERIPH_GPIOB
+#define I2CSCL_PORT             GPIO_PORTB_BASE
+#define I2CSCL_PIN              GPIO_PIN_2
+
+#define I2CSDA_PERIPH           SYSCTL_PERIPH_GPIOB
+#define I2CSDA_PORT             GPIO_PORTB_BASE
+#define I2CSDA_PIN              GPIO_PIN_3
+
+#define IDX_PERIPH              SYSCTL_PERIPH_GPIOD
+#define IDX_PORT                GPIO_PORTD_BASE
+#define IDX_PIN                 GPIO_PIN_7
+
+#define PHA_PERIPH              SYSCTL_PERIPH_GPIOC
+#define PHA_PORT                GPIO_PORTC_BASE
+#define PHA_PIN                 GPIO_PIN_4
+
+#define PHB_PERIPH              SYSCTL_PERIPH_GPIOC
+#define PHB_PORT                GPIO_PORTC_BASE
+#define PHB_PIN                 GPIO_PIN_6
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM0_PORT               GPIO_PORTD_BASE
+#define PWM0_PIN                GPIO_PIN_0
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM1_PORT               GPIO_PORTD_BASE
+#define PWM1_PIN                GPIO_PIN_1
+
+#define PWM2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define PWM2_PORT               GPIO_PORTB_BASE
+#define PWM2_PIN                GPIO_PIN_0
+
+#define PWM3_PERIPH             SYSCTL_PERIPH_GPIOB
+#define PWM3_PORT               GPIO_PORTB_BASE
+#define PWM3_PIN                GPIO_PIN_1
+
+#define PWM4_PERIPH             SYSCTL_PERIPH_GPIOE
+#define PWM4_PORT               GPIO_PORTE_BASE
+#define PWM4_PIN                GPIO_PIN_0
+
+#define PWM5_PERIPH             SYSCTL_PERIPH_GPIOE
+#define PWM5_PORT               GPIO_PORTE_BASE
+#define PWM5_PIN                GPIO_PIN_1
+
+#define SSICLK_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSICLK_PORT             GPIO_PORTA_BASE
+#define SSICLK_PIN              GPIO_PIN_2
+
+#define SSIFSS_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSIFSS_PORT             GPIO_PORTA_BASE
+#define SSIFSS_PIN              GPIO_PIN_3
+
+#define SSIRX_PERIPH            SYSCTL_PERIPH_GPIOA
+#define SSIRX_PORT              GPIO_PORTA_BASE
+#define SSIRX_PIN               GPIO_PIN_4
+
+#define SSITX_PERIPH            SYSCTL_PERIPH_GPIOA
+#define SSITX_PORT              GPIO_PORTA_BASE
+#define SSITX_PIN               GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#endif // PART_LM3S601
+
+//*****************************************************************************
+//
+// LM3S608 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S608
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP1_PORT               GPIO_PORTC_BASE
+#define CCP1_PIN                GPIO_PIN_5
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_1
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP3_PORT               GPIO_PORTC_BASE
+#define CCP3_PIN                GPIO_PIN_6
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP4_PORT               GPIO_PORTC_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP5_PORT               GPIO_PORTB_BASE
+#define CCP5_PIN                GPIO_PIN_5
+
+#define I2CSCL_PERIPH           SYSCTL_PERIPH_GPIOB
+#define I2CSCL_PORT             GPIO_PORTB_BASE
+#define I2CSCL_PIN              GPIO_PIN_2
+
+#define I2CSDA_PERIPH           SYSCTL_PERIPH_GPIOB
+#define I2CSDA_PORT             GPIO_PORTB_BASE
+#define I2CSDA_PIN              GPIO_PIN_3
+
+#define SSICLK_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSICLK_PORT             GPIO_PORTA_BASE
+#define SSICLK_PIN              GPIO_PIN_2
+
+#define SSIFSS_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSIFSS_PORT             GPIO_PORTA_BASE
+#define SSIFSS_PIN              GPIO_PIN_3
+
+#define SSIRX_PERIPH            SYSCTL_PERIPH_GPIOA
+#define SSIRX_PORT              GPIO_PORTA_BASE
+#define SSIRX_PIN               GPIO_PIN_4
+
+#define SSITX_PERIPH            SYSCTL_PERIPH_GPIOA
+#define SSITX_PORT              GPIO_PORTA_BASE
+#define SSITX_PIN               GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#endif // PART_LM3S608
+
+//*****************************************************************************
+//
+// LM3S610 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S610
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP0_PORT               GPIO_PORTD_BASE
+#define CCP0_PIN                GPIO_PIN_4
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOE
+#define CCP1_PORT               GPIO_PORTE_BASE
+#define CCP1_PIN                GPIO_PIN_3
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP2_PORT               GPIO_PORTD_BASE
+#define CCP2_PIN                GPIO_PIN_5
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP3_PORT               GPIO_PORTC_BASE
+#define CCP3_PIN                GPIO_PIN_6
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP4_PORT               GPIO_PORTC_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP5_PORT               GPIO_PORTB_BASE
+#define CCP5_PIN                GPIO_PIN_5
+
+#define FAULT_PERIPH            SYSCTL_PERIPH_GPIOD
+#define FAULT_PORT              GPIO_PORTD_BASE
+#define FAULT_PIN               GPIO_PIN_6
+
+#define I2CSCL_PERIPH           SYSCTL_PERIPH_GPIOB
+#define I2CSCL_PORT             GPIO_PORTB_BASE
+#define I2CSCL_PIN              GPIO_PIN_2
+
+#define I2CSDA_PERIPH           SYSCTL_PERIPH_GPIOB
+#define I2CSDA_PORT             GPIO_PORTB_BASE
+#define I2CSDA_PIN              GPIO_PIN_3
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM0_PORT               GPIO_PORTD_BASE
+#define PWM0_PIN                GPIO_PIN_0
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM1_PORT               GPIO_PORTD_BASE
+#define PWM1_PIN                GPIO_PIN_1
+
+#define PWM2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define PWM2_PORT               GPIO_PORTB_BASE
+#define PWM2_PIN                GPIO_PIN_0
+
+#define PWM3_PERIPH             SYSCTL_PERIPH_GPIOB
+#define PWM3_PORT               GPIO_PORTB_BASE
+#define PWM3_PIN                GPIO_PIN_1
+
+#define PWM4_PERIPH             SYSCTL_PERIPH_GPIOE
+#define PWM4_PORT               GPIO_PORTE_BASE
+#define PWM4_PIN                GPIO_PIN_0
+
+#define PWM5_PERIPH             SYSCTL_PERIPH_GPIOE
+#define PWM5_PORT               GPIO_PORTE_BASE
+#define PWM5_PIN                GPIO_PIN_1
+
+#define SSICLK_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSICLK_PORT             GPIO_PORTA_BASE
+#define SSICLK_PIN              GPIO_PIN_2
+
+#define SSIFSS_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSIFSS_PORT             GPIO_PORTA_BASE
+#define SSIFSS_PIN              GPIO_PIN_3
+
+#define SSIRX_PERIPH            SYSCTL_PERIPH_GPIOA
+#define SSIRX_PORT              GPIO_PORTA_BASE
+#define SSIRX_PIN               GPIO_PIN_4
+
+#define SSITX_PERIPH            SYSCTL_PERIPH_GPIOA
+#define SSITX_PORT              GPIO_PORTA_BASE
+#define SSITX_PIN               GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#endif // PART_LM3S610
+
+//*****************************************************************************
+//
+// LM3S611 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S611
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP0_PORT               GPIO_PORTD_BASE
+#define CCP0_PIN                GPIO_PIN_4
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP1_PORT               GPIO_PORTC_BASE
+#define CCP1_PIN                GPIO_PIN_5
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP2_PORT               GPIO_PORTD_BASE
+#define CCP2_PIN                GPIO_PIN_5
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP3_PORT               GPIO_PORTC_BASE
+#define CCP3_PIN                GPIO_PIN_6
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP4_PORT               GPIO_PORTC_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP5_PORT               GPIO_PORTB_BASE
+#define CCP5_PIN                GPIO_PIN_5
+
+#define FAULT_PERIPH            SYSCTL_PERIPH_GPIOD
+#define FAULT_PORT              GPIO_PORTD_BASE
+#define FAULT_PIN               GPIO_PIN_6
+
+#define I2CSCL_PERIPH           SYSCTL_PERIPH_GPIOB
+#define I2CSCL_PORT             GPIO_PORTB_BASE
+#define I2CSCL_PIN              GPIO_PIN_2
+
+#define I2CSDA_PERIPH           SYSCTL_PERIPH_GPIOB
+#define I2CSDA_PORT             GPIO_PORTB_BASE
+#define I2CSDA_PIN              GPIO_PIN_3
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM0_PORT               GPIO_PORTD_BASE
+#define PWM0_PIN                GPIO_PIN_0
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM1_PORT               GPIO_PORTD_BASE
+#define PWM1_PIN                GPIO_PIN_1
+
+#define PWM2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define PWM2_PORT               GPIO_PORTB_BASE
+#define PWM2_PIN                GPIO_PIN_0
+
+#define PWM3_PERIPH             SYSCTL_PERIPH_GPIOB
+#define PWM3_PORT               GPIO_PORTB_BASE
+#define PWM3_PIN                GPIO_PIN_1
+
+#define PWM4_PERIPH             SYSCTL_PERIPH_GPIOE
+#define PWM4_PORT               GPIO_PORTE_BASE
+#define PWM4_PIN                GPIO_PIN_0
+
+#define PWM5_PERIPH             SYSCTL_PERIPH_GPIOE
+#define PWM5_PORT               GPIO_PORTE_BASE
+#define PWM5_PIN                GPIO_PIN_1
+
+#define SSICLK_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSICLK_PORT             GPIO_PORTA_BASE
+#define SSICLK_PIN              GPIO_PIN_2
+
+#define SSIFSS_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSIFSS_PORT             GPIO_PORTA_BASE
+#define SSIFSS_PIN              GPIO_PIN_3
+
+#define SSIRX_PERIPH            SYSCTL_PERIPH_GPIOA
+#define SSIRX_PORT              GPIO_PORTA_BASE
+#define SSIRX_PIN               GPIO_PIN_4
+
+#define SSITX_PERIPH            SYSCTL_PERIPH_GPIOA
+#define SSITX_PORT              GPIO_PORTA_BASE
+#define SSITX_PIN               GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#endif // PART_LM3S611
+
+//*****************************************************************************
+//
+// LM3S612 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S612
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOD
+#define C0O_PORT                GPIO_PORTD_BASE
+#define C0O_PIN                 GPIO_PIN_7
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOE
+#define CCP1_PORT               GPIO_PORTE_BASE
+#define CCP1_PIN                GPIO_PIN_3
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP2_PORT               GPIO_PORTD_BASE
+#define CCP2_PIN                GPIO_PIN_5
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP3_PORT               GPIO_PORTC_BASE
+#define CCP3_PIN                GPIO_PIN_6
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP4_PORT               GPIO_PORTC_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP5_PORT               GPIO_PORTB_BASE
+#define CCP5_PIN                GPIO_PIN_5
+
+#define FAULT_PERIPH            SYSCTL_PERIPH_GPIOD
+#define FAULT_PORT              GPIO_PORTD_BASE
+#define FAULT_PIN               GPIO_PIN_6
+
+#define I2CSCL_PERIPH           SYSCTL_PERIPH_GPIOB
+#define I2CSCL_PORT             GPIO_PORTB_BASE
+#define I2CSCL_PIN              GPIO_PIN_2
+
+#define I2CSDA_PERIPH           SYSCTL_PERIPH_GPIOB
+#define I2CSDA_PORT             GPIO_PORTB_BASE
+#define I2CSDA_PIN              GPIO_PIN_3
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM0_PORT               GPIO_PORTD_BASE
+#define PWM0_PIN                GPIO_PIN_0
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM1_PORT               GPIO_PORTD_BASE
+#define PWM1_PIN                GPIO_PIN_1
+
+#define SSICLK_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSICLK_PORT             GPIO_PORTA_BASE
+#define SSICLK_PIN              GPIO_PIN_2
+
+#define SSIFSS_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSIFSS_PORT             GPIO_PORTA_BASE
+#define SSIFSS_PIN              GPIO_PIN_3
+
+#define SSIRX_PERIPH            SYSCTL_PERIPH_GPIOA
+#define SSIRX_PORT              GPIO_PORTA_BASE
+#define SSIRX_PIN               GPIO_PIN_4
+
+#define SSITX_PERIPH            SYSCTL_PERIPH_GPIOA
+#define SSITX_PORT              GPIO_PORTA_BASE
+#define SSITX_PIN               GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#endif // PART_LM3S612
+
+//*****************************************************************************
+//
+// LM3S613 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S613
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOD
+#define C0O_PORT                GPIO_PORTD_BASE
+#define C0O_PIN                 GPIO_PIN_7
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP0_PORT               GPIO_PORTD_BASE
+#define CCP0_PIN                GPIO_PIN_4
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP1_PORT               GPIO_PORTC_BASE
+#define CCP1_PIN                GPIO_PIN_5
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP2_PORT               GPIO_PORTD_BASE
+#define CCP2_PIN                GPIO_PIN_5
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP3_PORT               GPIO_PORTC_BASE
+#define CCP3_PIN                GPIO_PIN_6
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP4_PORT               GPIO_PORTC_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP5_PORT               GPIO_PORTB_BASE
+#define CCP5_PIN                GPIO_PIN_5
+
+#define FAULT_PERIPH            SYSCTL_PERIPH_GPIOD
+#define FAULT_PORT              GPIO_PORTD_BASE
+#define FAULT_PIN               GPIO_PIN_6
+
+#define I2CSCL_PERIPH           SYSCTL_PERIPH_GPIOB
+#define I2CSCL_PORT             GPIO_PORTB_BASE
+#define I2CSCL_PIN              GPIO_PIN_2
+
+#define I2CSDA_PERIPH           SYSCTL_PERIPH_GPIOB
+#define I2CSDA_PORT             GPIO_PORTB_BASE
+#define I2CSDA_PIN              GPIO_PIN_3
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM0_PORT               GPIO_PORTD_BASE
+#define PWM0_PIN                GPIO_PIN_0
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM1_PORT               GPIO_PORTD_BASE
+#define PWM1_PIN                GPIO_PIN_1
+
+#define PWM2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define PWM2_PORT               GPIO_PORTB_BASE
+#define PWM2_PIN                GPIO_PIN_0
+
+#define PWM3_PERIPH             SYSCTL_PERIPH_GPIOB
+#define PWM3_PORT               GPIO_PORTB_BASE
+#define PWM3_PIN                GPIO_PIN_1
+
+#define SSICLK_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSICLK_PORT             GPIO_PORTA_BASE
+#define SSICLK_PIN              GPIO_PIN_2
+
+#define SSIFSS_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSIFSS_PORT             GPIO_PORTA_BASE
+#define SSIFSS_PIN              GPIO_PIN_3
+
+#define SSIRX_PERIPH            SYSCTL_PERIPH_GPIOA
+#define SSIRX_PORT              GPIO_PORTA_BASE
+#define SSIRX_PIN               GPIO_PIN_4
+
+#define SSITX_PERIPH            SYSCTL_PERIPH_GPIOA
+#define SSITX_PORT              GPIO_PORTA_BASE
+#define SSITX_PIN               GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#endif // PART_LM3S613
+
+//*****************************************************************************
+//
+// LM3S615 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S615
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOD
+#define C0O_PORT                GPIO_PORTD_BASE
+#define C0O_PIN                 GPIO_PIN_7
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1O_PERIPH              SYSCTL_PERIPH_GPIOC
+#define C1O_PORT                GPIO_PORTC_BASE
+#define C1O_PIN                 GPIO_PIN_5
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_5
+
+#define C2_MINUS_PERIPH         SYSCTL_PERIPH_GPIOC
+#define C2_MINUS_PORT           GPIO_PORTC_BASE
+#define C2_MINUS_PIN            GPIO_PIN_7
+
+#define C2_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C2_PLUS_PORT            GPIO_PORTC_BASE
+#define C2_PLUS_PIN             GPIO_PIN_6
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP0_PORT               GPIO_PORTD_BASE
+#define CCP0_PIN                GPIO_PIN_4
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOE
+#define CCP1_PORT               GPIO_PORTE_BASE
+#define CCP1_PIN                GPIO_PIN_3
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP2_PORT               GPIO_PORTD_BASE
+#define CCP2_PIN                GPIO_PIN_5
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP3_PORT               GPIO_PORTC_BASE
+#define CCP3_PIN                GPIO_PIN_6
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOE
+#define CCP4_PORT               GPIO_PORTE_BASE
+#define CCP4_PIN                GPIO_PIN_2
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP5_PORT               GPIO_PORTC_BASE
+#define CCP5_PIN                GPIO_PIN_4
+
+#define FAULT_PERIPH            SYSCTL_PERIPH_GPIOD
+#define FAULT_PORT              GPIO_PORTD_BASE
+#define FAULT_PIN               GPIO_PIN_6
+
+#define I2CSCL_PERIPH           SYSCTL_PERIPH_GPIOB
+#define I2CSCL_PORT             GPIO_PORTB_BASE
+#define I2CSCL_PIN              GPIO_PIN_2
+
+#define I2CSDA_PERIPH           SYSCTL_PERIPH_GPIOB
+#define I2CSDA_PORT             GPIO_PORTB_BASE
+#define I2CSDA_PIN              GPIO_PIN_3
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM0_PORT               GPIO_PORTD_BASE
+#define PWM0_PIN                GPIO_PIN_0
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM1_PORT               GPIO_PORTD_BASE
+#define PWM1_PIN                GPIO_PIN_1
+
+#define PWM2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define PWM2_PORT               GPIO_PORTB_BASE
+#define PWM2_PIN                GPIO_PIN_0
+
+#define PWM3_PERIPH             SYSCTL_PERIPH_GPIOB
+#define PWM3_PORT               GPIO_PORTB_BASE
+#define PWM3_PIN                GPIO_PIN_1
+
+#define PWM4_PERIPH             SYSCTL_PERIPH_GPIOE
+#define PWM4_PORT               GPIO_PORTE_BASE
+#define PWM4_PIN                GPIO_PIN_0
+
+#define PWM5_PERIPH             SYSCTL_PERIPH_GPIOE
+#define PWM5_PORT               GPIO_PORTE_BASE
+#define PWM5_PIN                GPIO_PIN_1
+
+#define SSICLK_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSICLK_PORT             GPIO_PORTA_BASE
+#define SSICLK_PIN              GPIO_PIN_2
+
+#define SSIFSS_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSIFSS_PORT             GPIO_PORTA_BASE
+#define SSIFSS_PIN              GPIO_PIN_3
+
+#define SSIRX_PERIPH            SYSCTL_PERIPH_GPIOA
+#define SSIRX_PORT              GPIO_PORTA_BASE
+#define SSIRX_PIN               GPIO_PIN_4
+
+#define SSITX_PERIPH            SYSCTL_PERIPH_GPIOA
+#define SSITX_PORT              GPIO_PORTA_BASE
+#define SSITX_PIN               GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#endif // PART_LM3S615
+
+//*****************************************************************************
+//
+// LM3S617 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S617
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOB
+#define C0O_PORT                GPIO_PORTB_BASE
+#define C0O_PIN                 GPIO_PIN_5
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP0_PORT               GPIO_PORTD_BASE
+#define CCP0_PIN                GPIO_PIN_4
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP1_PORT               GPIO_PORTC_BASE
+#define CCP1_PIN                GPIO_PIN_5
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP2_PORT               GPIO_PORTD_BASE
+#define CCP2_PIN                GPIO_PIN_5
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP3_PORT               GPIO_PORTC_BASE
+#define CCP3_PIN                GPIO_PIN_6
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP4_PORT               GPIO_PORTC_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP5_PORT               GPIO_PORTC_BASE
+#define CCP5_PIN                GPIO_PIN_4
+
+#define FAULT_PERIPH            SYSCTL_PERIPH_GPIOB
+#define FAULT_PORT              GPIO_PORTB_BASE
+#define FAULT_PIN               GPIO_PIN_3
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM0_PORT               GPIO_PORTD_BASE
+#define PWM0_PIN                GPIO_PIN_0
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM1_PORT               GPIO_PORTD_BASE
+#define PWM1_PIN                GPIO_PIN_1
+
+#define PWM2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define PWM2_PORT               GPIO_PORTB_BASE
+#define PWM2_PIN                GPIO_PIN_0
+
+#define PWM3_PERIPH             SYSCTL_PERIPH_GPIOB
+#define PWM3_PORT               GPIO_PORTB_BASE
+#define PWM3_PIN                GPIO_PIN_1
+
+#define PWM4_PERIPH             SYSCTL_PERIPH_GPIOE
+#define PWM4_PORT               GPIO_PORTE_BASE
+#define PWM4_PIN                GPIO_PIN_0
+
+#define PWM5_PERIPH             SYSCTL_PERIPH_GPIOE
+#define PWM5_PORT               GPIO_PORTE_BASE
+#define PWM5_PIN                GPIO_PIN_1
+
+#define SSICLK_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSICLK_PORT             GPIO_PORTA_BASE
+#define SSICLK_PIN              GPIO_PIN_2
+
+#define SSIFSS_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSIFSS_PORT             GPIO_PORTA_BASE
+#define SSIFSS_PIN              GPIO_PIN_3
+
+#define SSIRX_PERIPH            SYSCTL_PERIPH_GPIOA
+#define SSIRX_PORT              GPIO_PORTA_BASE
+#define SSIRX_PIN               GPIO_PIN_4
+
+#define SSITX_PERIPH            SYSCTL_PERIPH_GPIOA
+#define SSITX_PORT              GPIO_PORTA_BASE
+#define SSITX_PIN               GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#endif // PART_LM3S617
+
+//*****************************************************************************
+//
+// LM3S618 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S618
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOB
+#define C0O_PORT                GPIO_PORTB_BASE
+#define C0O_PIN                 GPIO_PIN_5
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP0_PORT               GPIO_PORTD_BASE
+#define CCP0_PIN                GPIO_PIN_4
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP1_PORT               GPIO_PORTC_BASE
+#define CCP1_PIN                GPIO_PIN_5
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP2_PORT               GPIO_PORTD_BASE
+#define CCP2_PIN                GPIO_PIN_5
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP4_PORT               GPIO_PORTC_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define FAULT_PERIPH            SYSCTL_PERIPH_GPIOB
+#define FAULT_PORT              GPIO_PORTB_BASE
+#define FAULT_PIN               GPIO_PIN_3
+
+#define IDX_PERIPH              SYSCTL_PERIPH_GPIOB
+#define IDX_PORT                GPIO_PORTB_BASE
+#define IDX_PIN                 GPIO_PIN_2
+
+#define PHA_PERIPH              SYSCTL_PERIPH_GPIOC
+#define PHA_PORT                GPIO_PORTC_BASE
+#define PHA_PIN                 GPIO_PIN_4
+
+#define PHB_PERIPH              SYSCTL_PERIPH_GPIOC
+#define PHB_PORT                GPIO_PORTC_BASE
+#define PHB_PIN                 GPIO_PIN_6
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM0_PORT               GPIO_PORTD_BASE
+#define PWM0_PIN                GPIO_PIN_0
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM1_PORT               GPIO_PORTD_BASE
+#define PWM1_PIN                GPIO_PIN_1
+
+#define PWM2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define PWM2_PORT               GPIO_PORTB_BASE
+#define PWM2_PIN                GPIO_PIN_0
+
+#define PWM3_PERIPH             SYSCTL_PERIPH_GPIOB
+#define PWM3_PORT               GPIO_PORTB_BASE
+#define PWM3_PIN                GPIO_PIN_1
+
+#define PWM4_PERIPH             SYSCTL_PERIPH_GPIOE
+#define PWM4_PORT               GPIO_PORTE_BASE
+#define PWM4_PIN                GPIO_PIN_0
+
+#define PWM5_PERIPH             SYSCTL_PERIPH_GPIOE
+#define PWM5_PORT               GPIO_PORTE_BASE
+#define PWM5_PIN                GPIO_PIN_1
+
+#define SSICLK_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSICLK_PORT             GPIO_PORTA_BASE
+#define SSICLK_PIN              GPIO_PIN_2
+
+#define SSIFSS_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSIFSS_PORT             GPIO_PORTA_BASE
+#define SSIFSS_PIN              GPIO_PIN_3
+
+#define SSIRX_PERIPH            SYSCTL_PERIPH_GPIOA
+#define SSIRX_PORT              GPIO_PORTA_BASE
+#define SSIRX_PIN               GPIO_PIN_4
+
+#define SSITX_PERIPH            SYSCTL_PERIPH_GPIOA
+#define SSITX_PORT              GPIO_PORTA_BASE
+#define SSITX_PIN               GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#endif // PART_LM3S618
+
+//*****************************************************************************
+//
+// LM3S628 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S628
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP1_PORT               GPIO_PORTC_BASE
+#define CCP1_PIN                GPIO_PIN_5
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_1
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP3_PORT               GPIO_PORTC_BASE
+#define CCP3_PIN                GPIO_PIN_6
+
+#define I2CSCL_PERIPH           SYSCTL_PERIPH_GPIOB
+#define I2CSCL_PORT             GPIO_PORTB_BASE
+#define I2CSCL_PIN              GPIO_PIN_2
+
+#define I2CSDA_PERIPH           SYSCTL_PERIPH_GPIOB
+#define I2CSDA_PORT             GPIO_PORTB_BASE
+#define I2CSDA_PIN              GPIO_PIN_3
+
+#define SSICLK_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSICLK_PORT             GPIO_PORTA_BASE
+#define SSICLK_PIN              GPIO_PIN_2
+
+#define SSIFSS_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSIFSS_PORT             GPIO_PORTA_BASE
+#define SSIFSS_PIN              GPIO_PIN_3
+
+#define SSIRX_PERIPH            SYSCTL_PERIPH_GPIOA
+#define SSIRX_PORT              GPIO_PORTA_BASE
+#define SSIRX_PIN               GPIO_PIN_4
+
+#define SSITX_PERIPH            SYSCTL_PERIPH_GPIOA
+#define SSITX_PORT              GPIO_PORTA_BASE
+#define SSITX_PIN               GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#endif // PART_LM3S628
+
+//*****************************************************************************
+//
+// LM3S800 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S800
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOD
+#define C0O_PORT                GPIO_PORTD_BASE
+#define C0O_PIN                 GPIO_PIN_7
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1O_PERIPH              SYSCTL_PERIPH_GPIOC
+#define C1O_PORT                GPIO_PORTC_BASE
+#define C1O_PIN                 GPIO_PIN_5
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_5
+
+#define C2O_PERIPH              SYSCTL_PERIPH_GPIOC
+#define C2O_PORT                GPIO_PORTC_BASE
+#define C2O_PIN                 GPIO_PIN_6
+
+#define C2_MINUS_PERIPH         SYSCTL_PERIPH_GPIOC
+#define C2_MINUS_PORT           GPIO_PORTC_BASE
+#define C2_MINUS_PIN            GPIO_PIN_7
+
+#define C2_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C2_PLUS_PORT            GPIO_PORTC_BASE
+#define C2_PLUS_PIN             GPIO_PIN_6
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP0_PORT               GPIO_PORTD_BASE
+#define CCP0_PIN                GPIO_PIN_4
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOE
+#define CCP1_PORT               GPIO_PORTE_BASE
+#define CCP1_PIN                GPIO_PIN_3
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP2_PORT               GPIO_PORTD_BASE
+#define CCP2_PIN                GPIO_PIN_5
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOE
+#define CCP3_PORT               GPIO_PORTE_BASE
+#define CCP3_PIN                GPIO_PIN_4
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOE
+#define CCP4_PORT               GPIO_PORTE_BASE
+#define CCP4_PIN                GPIO_PIN_2
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOE
+#define CCP5_PORT               GPIO_PORTE_BASE
+#define CCP5_PIN                GPIO_PIN_5
+
+#define I2CSCL_PERIPH           SYSCTL_PERIPH_GPIOB
+#define I2CSCL_PORT             GPIO_PORTB_BASE
+#define I2CSCL_PIN              GPIO_PIN_2
+
+#define I2CSDA_PERIPH           SYSCTL_PERIPH_GPIOB
+#define I2CSDA_PORT             GPIO_PORTB_BASE
+#define I2CSDA_PIN              GPIO_PIN_3
+
+#define SSICLK_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSICLK_PORT             GPIO_PORTA_BASE
+#define SSICLK_PIN              GPIO_PIN_2
+
+#define SSIFSS_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSIFSS_PORT             GPIO_PORTA_BASE
+#define SSIFSS_PIN              GPIO_PIN_3
+
+#define SSIRX_PERIPH            SYSCTL_PERIPH_GPIOA
+#define SSIRX_PORT              GPIO_PORTA_BASE
+#define SSIRX_PIN               GPIO_PIN_4
+
+#define SSITX_PERIPH            SYSCTL_PERIPH_GPIOA
+#define SSITX_PORT              GPIO_PORTA_BASE
+#define SSITX_PIN               GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#endif // PART_LM3S800
+
+//*****************************************************************************
+//
+// LM3S801 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S801
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOC
+#define C0O_PORT                GPIO_PORTC_BASE
+#define C0O_PIN                 GPIO_PIN_5
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_5
+
+#define C2_MINUS_PERIPH         SYSCTL_PERIPH_GPIOC
+#define C2_MINUS_PORT           GPIO_PORTC_BASE
+#define C2_MINUS_PIN            GPIO_PIN_7
+
+#define C2_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C2_PLUS_PORT            GPIO_PORTC_BASE
+#define C2_PLUS_PIN             GPIO_PIN_6
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP0_PORT               GPIO_PORTD_BASE
+#define CCP0_PIN                GPIO_PIN_4
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOE
+#define CCP1_PORT               GPIO_PORTE_BASE
+#define CCP1_PIN                GPIO_PIN_3
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP2_PORT               GPIO_PORTD_BASE
+#define CCP2_PIN                GPIO_PIN_5
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOE
+#define CCP3_PORT               GPIO_PORTE_BASE
+#define CCP3_PIN                GPIO_PIN_4
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOE
+#define CCP4_PORT               GPIO_PORTE_BASE
+#define CCP4_PIN                GPIO_PIN_2
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOE
+#define CCP5_PORT               GPIO_PORTE_BASE
+#define CCP5_PIN                GPIO_PIN_5
+
+#define FAULT_PERIPH            SYSCTL_PERIPH_GPIOD
+#define FAULT_PORT              GPIO_PORTD_BASE
+#define FAULT_PIN               GPIO_PIN_6
+
+#define I2CSCL_PERIPH           SYSCTL_PERIPH_GPIOB
+#define I2CSCL_PORT             GPIO_PORTB_BASE
+#define I2CSCL_PIN              GPIO_PIN_2
+
+#define I2CSDA_PERIPH           SYSCTL_PERIPH_GPIOB
+#define I2CSDA_PORT             GPIO_PORTB_BASE
+#define I2CSDA_PIN              GPIO_PIN_3
+
+#define IDX_PERIPH              SYSCTL_PERIPH_GPIOD
+#define IDX_PORT                GPIO_PORTD_BASE
+#define IDX_PIN                 GPIO_PIN_7
+
+#define PHA_PERIPH              SYSCTL_PERIPH_GPIOC
+#define PHA_PORT                GPIO_PORTC_BASE
+#define PHA_PIN                 GPIO_PIN_4
+
+#define PHB_PERIPH              SYSCTL_PERIPH_GPIOC
+#define PHB_PORT                GPIO_PORTC_BASE
+#define PHB_PIN                 GPIO_PIN_6
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM0_PORT               GPIO_PORTD_BASE
+#define PWM0_PIN                GPIO_PIN_0
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM1_PORT               GPIO_PORTD_BASE
+#define PWM1_PIN                GPIO_PIN_1
+
+#define PWM2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define PWM2_PORT               GPIO_PORTB_BASE
+#define PWM2_PIN                GPIO_PIN_0
+
+#define PWM3_PERIPH             SYSCTL_PERIPH_GPIOB
+#define PWM3_PORT               GPIO_PORTB_BASE
+#define PWM3_PIN                GPIO_PIN_1
+
+#define PWM4_PERIPH             SYSCTL_PERIPH_GPIOE
+#define PWM4_PORT               GPIO_PORTE_BASE
+#define PWM4_PIN                GPIO_PIN_0
+
+#define PWM5_PERIPH             SYSCTL_PERIPH_GPIOE
+#define PWM5_PORT               GPIO_PORTE_BASE
+#define PWM5_PIN                GPIO_PIN_1
+
+#define SSICLK_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSICLK_PORT             GPIO_PORTA_BASE
+#define SSICLK_PIN              GPIO_PIN_2
+
+#define SSIFSS_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSIFSS_PORT             GPIO_PORTA_BASE
+#define SSIFSS_PIN              GPIO_PIN_3
+
+#define SSIRX_PERIPH            SYSCTL_PERIPH_GPIOA
+#define SSIRX_PORT              GPIO_PORTA_BASE
+#define SSIRX_PIN               GPIO_PIN_4
+
+#define SSITX_PERIPH            SYSCTL_PERIPH_GPIOA
+#define SSITX_PORT              GPIO_PORTA_BASE
+#define SSITX_PIN               GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#endif // PART_LM3S801
+
+//*****************************************************************************
+//
+// LM3S808 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S808
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP1_PORT               GPIO_PORTC_BASE
+#define CCP1_PIN                GPIO_PIN_5
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_1
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP3_PORT               GPIO_PORTC_BASE
+#define CCP3_PIN                GPIO_PIN_6
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP4_PORT               GPIO_PORTC_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP5_PORT               GPIO_PORTB_BASE
+#define CCP5_PIN                GPIO_PIN_5
+
+#define I2CSCL_PERIPH           SYSCTL_PERIPH_GPIOB
+#define I2CSCL_PORT             GPIO_PORTB_BASE
+#define I2CSCL_PIN              GPIO_PIN_2
+
+#define I2CSDA_PERIPH           SYSCTL_PERIPH_GPIOB
+#define I2CSDA_PORT             GPIO_PORTB_BASE
+#define I2CSDA_PIN              GPIO_PIN_3
+
+#define SSICLK_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSICLK_PORT             GPIO_PORTA_BASE
+#define SSICLK_PIN              GPIO_PIN_2
+
+#define SSIFSS_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSIFSS_PORT             GPIO_PORTA_BASE
+#define SSIFSS_PIN              GPIO_PIN_3
+
+#define SSIRX_PERIPH            SYSCTL_PERIPH_GPIOA
+#define SSIRX_PORT              GPIO_PORTA_BASE
+#define SSIRX_PIN               GPIO_PIN_4
+
+#define SSITX_PERIPH            SYSCTL_PERIPH_GPIOA
+#define SSITX_PORT              GPIO_PORTA_BASE
+#define SSITX_PIN               GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#endif // PART_LM3S808
+
+//*****************************************************************************
+//
+// LM3S811 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S811
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOD
+#define C0O_PORT                GPIO_PORTD_BASE
+#define C0O_PIN                 GPIO_PIN_7
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP0_PORT               GPIO_PORTD_BASE
+#define CCP0_PIN                GPIO_PIN_4
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP1_PORT               GPIO_PORTC_BASE
+#define CCP1_PIN                GPIO_PIN_5
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP2_PORT               GPIO_PORTD_BASE
+#define CCP2_PIN                GPIO_PIN_5
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP3_PORT               GPIO_PORTC_BASE
+#define CCP3_PIN                GPIO_PIN_6
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP4_PORT               GPIO_PORTC_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP5_PORT               GPIO_PORTB_BASE
+#define CCP5_PIN                GPIO_PIN_5
+
+#define FAULT_PERIPH            SYSCTL_PERIPH_GPIOD
+#define FAULT_PORT              GPIO_PORTD_BASE
+#define FAULT_PIN               GPIO_PIN_6
+
+#define I2CSCL_PERIPH           SYSCTL_PERIPH_GPIOB
+#define I2CSCL_PORT             GPIO_PORTB_BASE
+#define I2CSCL_PIN              GPIO_PIN_2
+
+#define I2CSDA_PERIPH           SYSCTL_PERIPH_GPIOB
+#define I2CSDA_PORT             GPIO_PORTB_BASE
+#define I2CSDA_PIN              GPIO_PIN_3
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM0_PORT               GPIO_PORTD_BASE
+#define PWM0_PIN                GPIO_PIN_0
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM1_PORT               GPIO_PORTD_BASE
+#define PWM1_PIN                GPIO_PIN_1
+
+#define PWM2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define PWM2_PORT               GPIO_PORTB_BASE
+#define PWM2_PIN                GPIO_PIN_0
+
+#define PWM3_PERIPH             SYSCTL_PERIPH_GPIOB
+#define PWM3_PORT               GPIO_PORTB_BASE
+#define PWM3_PIN                GPIO_PIN_1
+
+#define PWM4_PERIPH             SYSCTL_PERIPH_GPIOE
+#define PWM4_PORT               GPIO_PORTE_BASE
+#define PWM4_PIN                GPIO_PIN_0
+
+#define PWM5_PERIPH             SYSCTL_PERIPH_GPIOE
+#define PWM5_PORT               GPIO_PORTE_BASE
+#define PWM5_PIN                GPIO_PIN_1
+
+#define SSICLK_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSICLK_PORT             GPIO_PORTA_BASE
+#define SSICLK_PIN              GPIO_PIN_2
+
+#define SSIFSS_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSIFSS_PORT             GPIO_PORTA_BASE
+#define SSIFSS_PIN              GPIO_PIN_3
+
+#define SSIRX_PERIPH            SYSCTL_PERIPH_GPIOA
+#define SSIRX_PORT              GPIO_PORTA_BASE
+#define SSIRX_PIN               GPIO_PIN_4
+
+#define SSITX_PERIPH            SYSCTL_PERIPH_GPIOA
+#define SSITX_PORT              GPIO_PORTA_BASE
+#define SSITX_PIN               GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#endif // PART_LM3S811
+
+//*****************************************************************************
+//
+// LM3S812 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S812
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOD
+#define C0O_PORT                GPIO_PORTD_BASE
+#define C0O_PIN                 GPIO_PIN_7
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOE
+#define CCP1_PORT               GPIO_PORTE_BASE
+#define CCP1_PIN                GPIO_PIN_3
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP2_PORT               GPIO_PORTD_BASE
+#define CCP2_PIN                GPIO_PIN_5
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP3_PORT               GPIO_PORTC_BASE
+#define CCP3_PIN                GPIO_PIN_6
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP4_PORT               GPIO_PORTC_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP5_PORT               GPIO_PORTB_BASE
+#define CCP5_PIN                GPIO_PIN_5
+
+#define FAULT_PERIPH            SYSCTL_PERIPH_GPIOD
+#define FAULT_PORT              GPIO_PORTD_BASE
+#define FAULT_PIN               GPIO_PIN_6
+
+#define I2CSCL_PERIPH           SYSCTL_PERIPH_GPIOB
+#define I2CSCL_PORT             GPIO_PORTB_BASE
+#define I2CSCL_PIN              GPIO_PIN_2
+
+#define I2CSDA_PERIPH           SYSCTL_PERIPH_GPIOB
+#define I2CSDA_PORT             GPIO_PORTB_BASE
+#define I2CSDA_PIN              GPIO_PIN_3
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM0_PORT               GPIO_PORTD_BASE
+#define PWM0_PIN                GPIO_PIN_0
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM1_PORT               GPIO_PORTD_BASE
+#define PWM1_PIN                GPIO_PIN_1
+
+#define SSICLK_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSICLK_PORT             GPIO_PORTA_BASE
+#define SSICLK_PIN              GPIO_PIN_2
+
+#define SSIFSS_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSIFSS_PORT             GPIO_PORTA_BASE
+#define SSIFSS_PIN              GPIO_PIN_3
+
+#define SSIRX_PERIPH            SYSCTL_PERIPH_GPIOA
+#define SSIRX_PORT              GPIO_PORTA_BASE
+#define SSIRX_PIN               GPIO_PIN_4
+
+#define SSITX_PERIPH            SYSCTL_PERIPH_GPIOA
+#define SSITX_PORT              GPIO_PORTA_BASE
+#define SSITX_PIN               GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#endif // PART_LM3S812
+
+//*****************************************************************************
+//
+// LM3S815 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S815
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOD
+#define C0O_PORT                GPIO_PORTD_BASE
+#define C0O_PIN                 GPIO_PIN_7
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1O_PERIPH              SYSCTL_PERIPH_GPIOC
+#define C1O_PORT                GPIO_PORTC_BASE
+#define C1O_PIN                 GPIO_PIN_5
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_5
+
+#define C2_MINUS_PERIPH         SYSCTL_PERIPH_GPIOC
+#define C2_MINUS_PORT           GPIO_PORTC_BASE
+#define C2_MINUS_PIN            GPIO_PIN_7
+
+#define C2_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C2_PLUS_PORT            GPIO_PORTC_BASE
+#define C2_PLUS_PIN             GPIO_PIN_6
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP0_PORT               GPIO_PORTD_BASE
+#define CCP0_PIN                GPIO_PIN_4
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOE
+#define CCP1_PORT               GPIO_PORTE_BASE
+#define CCP1_PIN                GPIO_PIN_3
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP2_PORT               GPIO_PORTD_BASE
+#define CCP2_PIN                GPIO_PIN_5
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP3_PORT               GPIO_PORTC_BASE
+#define CCP3_PIN                GPIO_PIN_6
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOE
+#define CCP4_PORT               GPIO_PORTE_BASE
+#define CCP4_PIN                GPIO_PIN_2
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP5_PORT               GPIO_PORTC_BASE
+#define CCP5_PIN                GPIO_PIN_4
+
+#define FAULT_PERIPH            SYSCTL_PERIPH_GPIOD
+#define FAULT_PORT              GPIO_PORTD_BASE
+#define FAULT_PIN               GPIO_PIN_6
+
+#define I2CSCL_PERIPH           SYSCTL_PERIPH_GPIOB
+#define I2CSCL_PORT             GPIO_PORTB_BASE
+#define I2CSCL_PIN              GPIO_PIN_2
+
+#define I2CSDA_PERIPH           SYSCTL_PERIPH_GPIOB
+#define I2CSDA_PORT             GPIO_PORTB_BASE
+#define I2CSDA_PIN              GPIO_PIN_3
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM0_PORT               GPIO_PORTD_BASE
+#define PWM0_PIN                GPIO_PIN_0
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM1_PORT               GPIO_PORTD_BASE
+#define PWM1_PIN                GPIO_PIN_1
+
+#define PWM2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define PWM2_PORT               GPIO_PORTB_BASE
+#define PWM2_PIN                GPIO_PIN_0
+
+#define PWM3_PERIPH             SYSCTL_PERIPH_GPIOB
+#define PWM3_PORT               GPIO_PORTB_BASE
+#define PWM3_PIN                GPIO_PIN_1
+
+#define PWM4_PERIPH             SYSCTL_PERIPH_GPIOE
+#define PWM4_PORT               GPIO_PORTE_BASE
+#define PWM4_PIN                GPIO_PIN_0
+
+#define PWM5_PERIPH             SYSCTL_PERIPH_GPIOE
+#define PWM5_PORT               GPIO_PORTE_BASE
+#define PWM5_PIN                GPIO_PIN_1
+
+#define SSICLK_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSICLK_PORT             GPIO_PORTA_BASE
+#define SSICLK_PIN              GPIO_PIN_2
+
+#define SSIFSS_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSIFSS_PORT             GPIO_PORTA_BASE
+#define SSIFSS_PIN              GPIO_PIN_3
+
+#define SSIRX_PERIPH            SYSCTL_PERIPH_GPIOA
+#define SSIRX_PORT              GPIO_PORTA_BASE
+#define SSIRX_PIN               GPIO_PIN_4
+
+#define SSITX_PERIPH            SYSCTL_PERIPH_GPIOA
+#define SSITX_PORT              GPIO_PORTA_BASE
+#define SSITX_PIN               GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#endif // PART_LM3S815
+
+//*****************************************************************************
+//
+// LM3S817 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S817
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOB
+#define C0O_PORT                GPIO_PORTB_BASE
+#define C0O_PIN                 GPIO_PIN_5
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP0_PORT               GPIO_PORTD_BASE
+#define CCP0_PIN                GPIO_PIN_4
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP1_PORT               GPIO_PORTC_BASE
+#define CCP1_PIN                GPIO_PIN_5
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP2_PORT               GPIO_PORTD_BASE
+#define CCP2_PIN                GPIO_PIN_5
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP3_PORT               GPIO_PORTC_BASE
+#define CCP3_PIN                GPIO_PIN_6
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP4_PORT               GPIO_PORTC_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP5_PORT               GPIO_PORTC_BASE
+#define CCP5_PIN                GPIO_PIN_4
+
+#define FAULT_PERIPH            SYSCTL_PERIPH_GPIOB
+#define FAULT_PORT              GPIO_PORTB_BASE
+#define FAULT_PIN               GPIO_PIN_3
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM0_PORT               GPIO_PORTD_BASE
+#define PWM0_PIN                GPIO_PIN_0
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM1_PORT               GPIO_PORTD_BASE
+#define PWM1_PIN                GPIO_PIN_1
+
+#define PWM2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define PWM2_PORT               GPIO_PORTB_BASE
+#define PWM2_PIN                GPIO_PIN_0
+
+#define PWM3_PERIPH             SYSCTL_PERIPH_GPIOB
+#define PWM3_PORT               GPIO_PORTB_BASE
+#define PWM3_PIN                GPIO_PIN_1
+
+#define PWM4_PERIPH             SYSCTL_PERIPH_GPIOE
+#define PWM4_PORT               GPIO_PORTE_BASE
+#define PWM4_PIN                GPIO_PIN_0
+
+#define PWM5_PERIPH             SYSCTL_PERIPH_GPIOE
+#define PWM5_PORT               GPIO_PORTE_BASE
+#define PWM5_PIN                GPIO_PIN_1
+
+#define SSICLK_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSICLK_PORT             GPIO_PORTA_BASE
+#define SSICLK_PIN              GPIO_PIN_2
+
+#define SSIFSS_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSIFSS_PORT             GPIO_PORTA_BASE
+#define SSIFSS_PIN              GPIO_PIN_3
+
+#define SSIRX_PERIPH            SYSCTL_PERIPH_GPIOA
+#define SSIRX_PORT              GPIO_PORTA_BASE
+#define SSIRX_PIN               GPIO_PIN_4
+
+#define SSITX_PERIPH            SYSCTL_PERIPH_GPIOA
+#define SSITX_PORT              GPIO_PORTA_BASE
+#define SSITX_PIN               GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#endif // PART_LM3S817
+
+//*****************************************************************************
+//
+// LM3S818 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S818
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOB
+#define C0O_PORT                GPIO_PORTB_BASE
+#define C0O_PIN                 GPIO_PIN_5
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP0_PORT               GPIO_PORTD_BASE
+#define CCP0_PIN                GPIO_PIN_4
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP1_PORT               GPIO_PORTC_BASE
+#define CCP1_PIN                GPIO_PIN_5
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP2_PORT               GPIO_PORTD_BASE
+#define CCP2_PIN                GPIO_PIN_5
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP4_PORT               GPIO_PORTC_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define FAULT_PERIPH            SYSCTL_PERIPH_GPIOB
+#define FAULT_PORT              GPIO_PORTB_BASE
+#define FAULT_PIN               GPIO_PIN_3
+
+#define IDX_PERIPH              SYSCTL_PERIPH_GPIOB
+#define IDX_PORT                GPIO_PORTB_BASE
+#define IDX_PIN                 GPIO_PIN_2
+
+#define PHA_PERIPH              SYSCTL_PERIPH_GPIOC
+#define PHA_PORT                GPIO_PORTC_BASE
+#define PHA_PIN                 GPIO_PIN_4
+
+#define PHB_PERIPH              SYSCTL_PERIPH_GPIOC
+#define PHB_PORT                GPIO_PORTC_BASE
+#define PHB_PIN                 GPIO_PIN_6
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM0_PORT               GPIO_PORTD_BASE
+#define PWM0_PIN                GPIO_PIN_0
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM1_PORT               GPIO_PORTD_BASE
+#define PWM1_PIN                GPIO_PIN_1
+
+#define PWM2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define PWM2_PORT               GPIO_PORTB_BASE
+#define PWM2_PIN                GPIO_PIN_0
+
+#define PWM3_PERIPH             SYSCTL_PERIPH_GPIOB
+#define PWM3_PORT               GPIO_PORTB_BASE
+#define PWM3_PIN                GPIO_PIN_1
+
+#define PWM4_PERIPH             SYSCTL_PERIPH_GPIOE
+#define PWM4_PORT               GPIO_PORTE_BASE
+#define PWM4_PIN                GPIO_PIN_0
+
+#define PWM5_PERIPH             SYSCTL_PERIPH_GPIOE
+#define PWM5_PORT               GPIO_PORTE_BASE
+#define PWM5_PIN                GPIO_PIN_1
+
+#define SSICLK_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSICLK_PORT             GPIO_PORTA_BASE
+#define SSICLK_PIN              GPIO_PIN_2
+
+#define SSIFSS_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSIFSS_PORT             GPIO_PORTA_BASE
+#define SSIFSS_PIN              GPIO_PIN_3
+
+#define SSIRX_PERIPH            SYSCTL_PERIPH_GPIOA
+#define SSIRX_PORT              GPIO_PORTA_BASE
+#define SSIRX_PIN               GPIO_PIN_4
+
+#define SSITX_PERIPH            SYSCTL_PERIPH_GPIOA
+#define SSITX_PORT              GPIO_PORTA_BASE
+#define SSITX_PIN               GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#endif // PART_LM3S818
+
+//*****************************************************************************
+//
+// LM3S828 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S828
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP1_PORT               GPIO_PORTC_BASE
+#define CCP1_PIN                GPIO_PIN_5
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_1
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP3_PORT               GPIO_PORTC_BASE
+#define CCP3_PIN                GPIO_PIN_6
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP4_PORT               GPIO_PORTC_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP5_PORT               GPIO_PORTB_BASE
+#define CCP5_PIN                GPIO_PIN_5
+
+#define I2CSCL_PERIPH           SYSCTL_PERIPH_GPIOB
+#define I2CSCL_PORT             GPIO_PORTB_BASE
+#define I2CSCL_PIN              GPIO_PIN_2
+
+#define I2CSDA_PERIPH           SYSCTL_PERIPH_GPIOB
+#define I2CSDA_PORT             GPIO_PORTB_BASE
+#define I2CSDA_PIN              GPIO_PIN_3
+
+#define SSICLK_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSICLK_PORT             GPIO_PORTA_BASE
+#define SSICLK_PIN              GPIO_PIN_2
+
+#define SSIFSS_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSIFSS_PORT             GPIO_PORTA_BASE
+#define SSIFSS_PIN              GPIO_PIN_3
+
+#define SSIRX_PERIPH            SYSCTL_PERIPH_GPIOA
+#define SSIRX_PORT              GPIO_PORTA_BASE
+#define SSIRX_PIN               GPIO_PIN_4
+
+#define SSITX_PERIPH            SYSCTL_PERIPH_GPIOA
+#define SSITX_PORT              GPIO_PORTA_BASE
+#define SSITX_PIN               GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#endif // PART_LM3S828
+
+//*****************************************************************************
+//
+// LM3S1110 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1110
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOD
+#define C0O_PORT                GPIO_PORTD_BASE
+#define C0O_PIN                 GPIO_PIN_7
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1O_PERIPH              SYSCTL_PERIPH_GPIOE
+#define C1O_PORT                GPIO_PORTE_BASE
+#define C1O_PIN                 GPIO_PIN_6
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_5
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP1_PORT               GPIO_PORTA_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#endif // PART_LM3S1110
+
+//*****************************************************************************
+//
+// LM3S1133 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1133
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOC
+#define C0O_PORT                GPIO_PORTC_BASE
+#define C0O_PIN                 GPIO_PIN_5
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP1_PORT               GPIO_PORTA_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_1
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP3_PORT               GPIO_PORTC_BASE
+#define CCP3_PIN                GPIO_PIN_6
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP4_PORT               GPIO_PORTA_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP5_PORT               GPIO_PORTB_BASE
+#define CCP5_PIN                GPIO_PIN_5
+
+#define CCP6_PERIPH             SYSCTL_PERIPH_GPIOH
+#define CCP6_PORT               GPIO_PORTH_BASE
+#define CCP6_PIN                GPIO_PIN_0
+
+#define CCP7_PERIPH             SYSCTL_PERIPH_GPIOH
+#define CCP7_PORT               GPIO_PORTH_BASE
+#define CCP7_PIN                GPIO_PIN_1
+
+#define FAULT_PERIPH            SYSCTL_PERIPH_GPIOD
+#define FAULT_PORT              GPIO_PORTD_BASE
+#define FAULT_PIN               GPIO_PIN_6
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM0_PORT               GPIO_PORTD_BASE
+#define PWM0_PIN                GPIO_PIN_0
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM1_PORT               GPIO_PORTD_BASE
+#define PWM1_PIN                GPIO_PIN_1
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SSI1CLK_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1CLK_PORT            GPIO_PORTE_BASE
+#define SSI1CLK_PIN             GPIO_PIN_0
+
+#define SSI1FSS_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1FSS_PORT            GPIO_PORTE_BASE
+#define SSI1FSS_PIN             GPIO_PIN_1
+
+#define SSI1RX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1RX_PORT             GPIO_PORTE_BASE
+#define SSI1RX_PIN              GPIO_PIN_2
+
+#define SSI1TX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1TX_PORT             GPIO_PORTE_BASE
+#define SSI1TX_PIN              GPIO_PIN_3
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#define U2RX_PERIPH             SYSCTL_PERIPH_GPIOG
+#define U2RX_PORT               GPIO_PORTG_BASE
+#define U2RX_PIN                GPIO_PIN_0
+
+#define U2TX_PERIPH             SYSCTL_PERIPH_GPIOG
+#define U2TX_PORT               GPIO_PORTG_BASE
+#define U2TX_PIN                GPIO_PIN_1
+
+#endif // PART_LM3S1133
+
+//*****************************************************************************
+//
+// LM3S1138 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1138
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOF
+#define C0O_PORT                GPIO_PORTF_BASE
+#define C0O_PIN                 GPIO_PIN_4
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1O_PERIPH              SYSCTL_PERIPH_GPIOF
+#define C1O_PORT                GPIO_PORTF_BASE
+#define C1O_PIN                 GPIO_PIN_5
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_5
+
+#define C2O_PERIPH              SYSCTL_PERIPH_GPIOC
+#define C2O_PORT                GPIO_PORTC_BASE
+#define C2O_PIN                 GPIO_PIN_6
+
+#define C2_MINUS_PERIPH         SYSCTL_PERIPH_GPIOC
+#define C2_MINUS_PORT           GPIO_PORTC_BASE
+#define C2_MINUS_PIN            GPIO_PIN_7
+
+#define C2_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C2_PLUS_PORT            GPIO_PORTC_BASE
+#define C2_PLUS_PIN             GPIO_PIN_6
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOF
+#define CCP1_PORT               GPIO_PORTF_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_1
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOG
+#define CCP3_PORT               GPIO_PORTG_BASE
+#define CCP3_PIN                GPIO_PIN_4
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOF
+#define CCP4_PORT               GPIO_PORTF_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP5_PORT               GPIO_PORTC_BASE
+#define CCP5_PIN                GPIO_PIN_4
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define I2C1SCL_PERIPH          SYSCTL_PERIPH_GPIOA
+#define I2C1SCL_PORT            GPIO_PORTA_BASE
+#define I2C1SCL_PIN             GPIO_PIN_6
+
+#define I2C1SDA_PERIPH          SYSCTL_PERIPH_GPIOA
+#define I2C1SDA_PORT            GPIO_PORTA_BASE
+#define I2C1SDA_PIN             GPIO_PIN_7
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SSI1CLK_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1CLK_PORT            GPIO_PORTE_BASE
+#define SSI1CLK_PIN             GPIO_PIN_0
+
+#define SSI1FSS_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1FSS_PORT            GPIO_PORTE_BASE
+#define SSI1FSS_PIN             GPIO_PIN_1
+
+#define SSI1RX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1RX_PORT             GPIO_PORTE_BASE
+#define SSI1RX_PIN              GPIO_PIN_2
+
+#define SSI1TX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1TX_PORT             GPIO_PORTE_BASE
+#define SSI1TX_PIN              GPIO_PIN_3
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#define U2RX_PERIPH             SYSCTL_PERIPH_GPIOG
+#define U2RX_PORT               GPIO_PORTG_BASE
+#define U2RX_PIN                GPIO_PIN_0
+
+#define U2TX_PERIPH             SYSCTL_PERIPH_GPIOG
+#define U2TX_PORT               GPIO_PORTG_BASE
+#define U2TX_PIN                GPIO_PIN_1
+
+#endif // PART_LM3S1138
+
+//*****************************************************************************
+//
+// LM3S1150 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1150
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOF
+#define C0O_PORT                GPIO_PORTF_BASE
+#define C0O_PIN                 GPIO_PIN_4
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1O_PERIPH              SYSCTL_PERIPH_GPIOF
+#define C1O_PORT                GPIO_PORTF_BASE
+#define C1O_PIN                 GPIO_PIN_5
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_5
+
+#define C2_MINUS_PERIPH         SYSCTL_PERIPH_GPIOC
+#define C2_MINUS_PORT           GPIO_PORTC_BASE
+#define C2_MINUS_PIN            GPIO_PIN_7
+
+#define C2_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C2_PLUS_PORT            GPIO_PORTC_BASE
+#define C2_PLUS_PIN             GPIO_PIN_6
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP1_PORT               GPIO_PORTA_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_1
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP3_PORT               GPIO_PORTD_BASE
+#define CCP3_PIN                GPIO_PIN_4
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP4_PORT               GPIO_PORTA_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP5_PORT               GPIO_PORTC_BASE
+#define CCP5_PIN                GPIO_PIN_4
+
+#define FAULT_PERIPH            SYSCTL_PERIPH_GPIOD
+#define FAULT_PORT              GPIO_PORTD_BASE
+#define FAULT_PIN               GPIO_PIN_6
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define IDX0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define IDX0_PORT               GPIO_PORTD_BASE
+#define IDX0_PIN                GPIO_PIN_7
+
+#define PHA0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PHA0_PORT               GPIO_PORTD_BASE
+#define PHA0_PIN                GPIO_PIN_1
+
+#define PHB0_PERIPH             SYSCTL_PERIPH_GPIOF
+#define PHB0_PORT               GPIO_PORTF_BASE
+#define PHB0_PIN                GPIO_PIN_0
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM0_PORT               GPIO_PORTD_BASE
+#define PWM0_PIN                GPIO_PIN_0
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOF
+#define PWM1_PORT               GPIO_PORTF_BASE
+#define PWM1_PIN                GPIO_PIN_1
+
+#define PWM2_PERIPH             SYSCTL_PERIPH_GPIOH
+#define PWM2_PORT               GPIO_PORTH_BASE
+#define PWM2_PIN                GPIO_PIN_0
+
+#define PWM3_PERIPH             SYSCTL_PERIPH_GPIOH
+#define PWM3_PORT               GPIO_PORTH_BASE
+#define PWM3_PIN                GPIO_PIN_1
+
+#define PWM4_PERIPH             SYSCTL_PERIPH_GPIOE
+#define PWM4_PORT               GPIO_PORTE_BASE
+#define PWM4_PIN                GPIO_PIN_6
+
+#define PWM5_PERIPH             SYSCTL_PERIPH_GPIOE
+#define PWM5_PORT               GPIO_PORTE_BASE
+#define PWM5_PIN                GPIO_PIN_7
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SSI1CLK_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1CLK_PORT            GPIO_PORTE_BASE
+#define SSI1CLK_PIN             GPIO_PIN_0
+
+#define SSI1FSS_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1FSS_PORT            GPIO_PORTE_BASE
+#define SSI1FSS_PIN             GPIO_PIN_1
+
+#define SSI1RX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1RX_PORT             GPIO_PORTE_BASE
+#define SSI1RX_PIN              GPIO_PIN_2
+
+#define SSI1TX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1TX_PORT             GPIO_PORTE_BASE
+#define SSI1TX_PIN              GPIO_PIN_3
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#define U2RX_PERIPH             SYSCTL_PERIPH_GPIOG
+#define U2RX_PORT               GPIO_PORTG_BASE
+#define U2RX_PIN                GPIO_PIN_0
+
+#define U2TX_PERIPH             SYSCTL_PERIPH_GPIOG
+#define U2TX_PORT               GPIO_PORTG_BASE
+#define U2TX_PIN                GPIO_PIN_1
+
+#endif // PART_LM3S1150
+
+//*****************************************************************************
+//
+// LM3S1162 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1162
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOD
+#define C0O_PORT                GPIO_PORTD_BASE
+#define C0O_PIN                 GPIO_PIN_7
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1O_PERIPH              SYSCTL_PERIPH_GPIOF
+#define C1O_PORT                GPIO_PORTF_BASE
+#define C1O_PIN                 GPIO_PIN_5
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_5
+
+#define C2_MINUS_PERIPH         SYSCTL_PERIPH_GPIOC
+#define C2_MINUS_PORT           GPIO_PORTC_BASE
+#define C2_MINUS_PIN            GPIO_PIN_7
+
+#define C2_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C2_PLUS_PORT            GPIO_PORTC_BASE
+#define C2_PLUS_PIN             GPIO_PIN_6
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP1_PORT               GPIO_PORTA_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_1
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP3_PORT               GPIO_PORTD_BASE
+#define CCP3_PIN                GPIO_PIN_4
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP4_PORT               GPIO_PORTA_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP5_PORT               GPIO_PORTC_BASE
+#define CCP5_PIN                GPIO_PIN_4
+
+#define FAULT_PERIPH            SYSCTL_PERIPH_GPIOD
+#define FAULT_PORT              GPIO_PORTD_BASE
+#define FAULT_PIN               GPIO_PIN_6
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM0_PORT               GPIO_PORTD_BASE
+#define PWM0_PIN                GPIO_PIN_0
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM1_PORT               GPIO_PORTD_BASE
+#define PWM1_PIN                GPIO_PIN_1
+
+#define PWM2_PERIPH             SYSCTL_PERIPH_GPIOH
+#define PWM2_PORT               GPIO_PORTH_BASE
+#define PWM2_PIN                GPIO_PIN_0
+
+#define PWM3_PERIPH             SYSCTL_PERIPH_GPIOH
+#define PWM3_PORT               GPIO_PORTH_BASE
+#define PWM3_PIN                GPIO_PIN_1
+
+#define PWM4_PERIPH             SYSCTL_PERIPH_GPIOF
+#define PWM4_PORT               GPIO_PORTF_BASE
+#define PWM4_PIN                GPIO_PIN_2
+
+#define PWM5_PERIPH             SYSCTL_PERIPH_GPIOF
+#define PWM5_PORT               GPIO_PORTF_BASE
+#define PWM5_PIN                GPIO_PIN_3
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SSI1CLK_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1CLK_PORT            GPIO_PORTE_BASE
+#define SSI1CLK_PIN             GPIO_PIN_0
+
+#define SSI1FSS_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1FSS_PORT            GPIO_PORTE_BASE
+#define SSI1FSS_PIN             GPIO_PIN_1
+
+#define SSI1RX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1RX_PORT             GPIO_PORTE_BASE
+#define SSI1RX_PIN              GPIO_PIN_2
+
+#define SSI1TX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1TX_PORT             GPIO_PORTE_BASE
+#define SSI1TX_PIN              GPIO_PIN_3
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#define U2RX_PERIPH             SYSCTL_PERIPH_GPIOG
+#define U2RX_PORT               GPIO_PORTG_BASE
+#define U2RX_PIN                GPIO_PIN_0
+
+#define U2TX_PERIPH             SYSCTL_PERIPH_GPIOG
+#define U2TX_PORT               GPIO_PORTG_BASE
+#define U2TX_PIN                GPIO_PIN_1
+
+#endif // PART_LM3S1162
+
+//*****************************************************************************
+//
+// LM3S1165 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1165
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOC
+#define C0O_PORT                GPIO_PORTC_BASE
+#define C0O_PIN                 GPIO_PIN_5
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP1_PORT               GPIO_PORTA_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP2_PORT               GPIO_PORTD_BASE
+#define CCP2_PIN                GPIO_PIN_5
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP3_PORT               GPIO_PORTC_BASE
+#define CCP3_PIN                GPIO_PIN_6
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP4_PORT               GPIO_PORTA_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP5_PORT               GPIO_PORTC_BASE
+#define CCP5_PIN                GPIO_PIN_4
+
+#define CCP6_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP6_PORT               GPIO_PORTB_BASE
+#define CCP6_PIN                GPIO_PIN_5
+
+#define CCP7_PERIPH             SYSCTL_PERIPH_GPIOH
+#define CCP7_PORT               GPIO_PORTH_BASE
+#define CCP7_PIN                GPIO_PIN_1
+
+#define FAULT_PERIPH            SYSCTL_PERIPH_GPIOD
+#define FAULT_PORT              GPIO_PORTD_BASE
+#define FAULT_PIN               GPIO_PIN_6
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM0_PORT               GPIO_PORTD_BASE
+#define PWM0_PIN                GPIO_PIN_0
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM1_PORT               GPIO_PORTD_BASE
+#define PWM1_PIN                GPIO_PIN_1
+
+#define PWM2_PERIPH             SYSCTL_PERIPH_GPIOH
+#define PWM2_PORT               GPIO_PORTH_BASE
+#define PWM2_PIN                GPIO_PIN_0
+
+#define PWM3_PERIPH             SYSCTL_PERIPH_GPIOB
+#define PWM3_PORT               GPIO_PORTB_BASE
+#define PWM3_PIN                GPIO_PIN_1
+
+#define PWM4_PERIPH             SYSCTL_PERIPH_GPIOF
+#define PWM4_PORT               GPIO_PORTF_BASE
+#define PWM4_PIN                GPIO_PIN_2
+
+#define PWM5_PERIPH             SYSCTL_PERIPH_GPIOF
+#define PWM5_PORT               GPIO_PORTF_BASE
+#define PWM5_PIN                GPIO_PIN_3
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SSI1CLK_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1CLK_PORT            GPIO_PORTE_BASE
+#define SSI1CLK_PIN             GPIO_PIN_0
+
+#define SSI1FSS_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1FSS_PORT            GPIO_PORTE_BASE
+#define SSI1FSS_PIN             GPIO_PIN_1
+
+#define SSI1RX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1RX_PORT             GPIO_PORTE_BASE
+#define SSI1RX_PIN              GPIO_PIN_2
+
+#define SSI1TX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1TX_PORT             GPIO_PORTE_BASE
+#define SSI1TX_PIN              GPIO_PIN_3
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#define U2RX_PERIPH             SYSCTL_PERIPH_GPIOG
+#define U2RX_PORT               GPIO_PORTG_BASE
+#define U2RX_PIN                GPIO_PIN_0
+
+#define U2TX_PERIPH             SYSCTL_PERIPH_GPIOG
+#define U2TX_PORT               GPIO_PORTG_BASE
+#define U2TX_PIN                GPIO_PIN_1
+
+#endif // PART_LM3S1165
+
+//*****************************************************************************
+//
+// LM3S1332 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1332
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOD
+#define C0O_PORT                GPIO_PORTD_BASE
+#define C0O_PIN                 GPIO_PIN_7
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_5
+
+#define C2_MINUS_PERIPH         SYSCTL_PERIPH_GPIOC
+#define C2_MINUS_PORT           GPIO_PORTC_BASE
+#define C2_MINUS_PIN            GPIO_PIN_7
+
+#define C2_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C2_PLUS_PORT            GPIO_PORTC_BASE
+#define C2_PLUS_PIN             GPIO_PIN_6
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP1_PORT               GPIO_PORTA_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_1
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP3_PORT               GPIO_PORTD_BASE
+#define CCP3_PIN                GPIO_PIN_4
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP4_PORT               GPIO_PORTA_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP5_PORT               GPIO_PORTC_BASE
+#define CCP5_PIN                GPIO_PIN_4
+
+#define CCP6_PERIPH             SYSCTL_PERIPH_GPIOH
+#define CCP6_PORT               GPIO_PORTH_BASE
+#define CCP6_PIN                GPIO_PIN_0
+
+#define CCP7_PERIPH             SYSCTL_PERIPH_GPIOH
+#define CCP7_PORT               GPIO_PORTH_BASE
+#define CCP7_PIN                GPIO_PIN_1
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#endif // PART_LM3S1332
+
+//*****************************************************************************
+//
+// LM3S1435 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1435
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOB
+#define C0O_PORT                GPIO_PORTB_BASE
+#define C0O_PIN                 GPIO_PIN_5
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP1_PORT               GPIO_PORTA_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_1
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP3_PORT               GPIO_PORTC_BASE
+#define CCP3_PIN                GPIO_PIN_6
+
+#define FAULT_PERIPH            SYSCTL_PERIPH_GPIOD
+#define FAULT_PORT              GPIO_PORTD_BASE
+#define FAULT_PIN               GPIO_PIN_6
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM0_PORT               GPIO_PORTD_BASE
+#define PWM0_PIN                GPIO_PIN_0
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM1_PORT               GPIO_PORTD_BASE
+#define PWM1_PIN                GPIO_PIN_1
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#endif // PART_LM3S1435
+
+//*****************************************************************************
+//
+// LM3S1439 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1439
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOC
+#define C0O_PORT                GPIO_PORTC_BASE
+#define C0O_PIN                 GPIO_PIN_5
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP1_PORT               GPIO_PORTA_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_1
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP3_PORT               GPIO_PORTC_BASE
+#define CCP3_PIN                GPIO_PIN_6
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP4_PORT               GPIO_PORTA_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP5_PORT               GPIO_PORTB_BASE
+#define CCP5_PIN                GPIO_PIN_5
+
+#define FAULT_PERIPH            SYSCTL_PERIPH_GPIOD
+#define FAULT_PORT              GPIO_PORTD_BASE
+#define FAULT_PIN               GPIO_PIN_6
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define IDX0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define IDX0_PORT               GPIO_PORTD_BASE
+#define IDX0_PIN                GPIO_PIN_7
+
+#define PHA0_PERIPH             SYSCTL_PERIPH_GPIOC
+#define PHA0_PORT               GPIO_PORTC_BASE
+#define PHA0_PIN                GPIO_PIN_4
+
+#define PHB0_PERIPH             SYSCTL_PERIPH_GPIOC
+#define PHB0_PORT               GPIO_PORTC_BASE
+#define PHB0_PIN                GPIO_PIN_7
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM0_PORT               GPIO_PORTD_BASE
+#define PWM0_PIN                GPIO_PIN_0
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM1_PORT               GPIO_PORTD_BASE
+#define PWM1_PIN                GPIO_PIN_1
+
+#define PWM2_PERIPH             SYSCTL_PERIPH_GPIOH
+#define PWM2_PORT               GPIO_PORTH_BASE
+#define PWM2_PIN                GPIO_PIN_0
+
+#define PWM3_PERIPH             SYSCTL_PERIPH_GPIOH
+#define PWM3_PORT               GPIO_PORTH_BASE
+#define PWM3_PIN                GPIO_PIN_1
+
+#define PWM4_PERIPH             SYSCTL_PERIPH_GPIOF
+#define PWM4_PORT               GPIO_PORTF_BASE
+#define PWM4_PIN                GPIO_PIN_2
+
+#define PWM5_PERIPH             SYSCTL_PERIPH_GPIOF
+#define PWM5_PORT               GPIO_PORTF_BASE
+#define PWM5_PIN                GPIO_PIN_3
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SSI1CLK_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1CLK_PORT            GPIO_PORTE_BASE
+#define SSI1CLK_PIN             GPIO_PIN_0
+
+#define SSI1FSS_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1FSS_PORT            GPIO_PORTE_BASE
+#define SSI1FSS_PIN             GPIO_PIN_1
+
+#define SSI1RX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1RX_PORT             GPIO_PORTE_BASE
+#define SSI1RX_PIN              GPIO_PIN_2
+
+#define SSI1TX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1TX_PORT             GPIO_PORTE_BASE
+#define SSI1TX_PIN              GPIO_PIN_3
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#endif // PART_LM3S1439
+
+//*****************************************************************************
+//
+// LM3S1512 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1512
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOF
+#define C0O_PORT                GPIO_PORTF_BASE
+#define C0O_PIN                 GPIO_PIN_4
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1O_PERIPH              SYSCTL_PERIPH_GPIOF
+#define C1O_PORT                GPIO_PORTF_BASE
+#define C1O_PIN                 GPIO_PIN_5
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_5
+
+#define C2O_PERIPH              SYSCTL_PERIPH_GPIOF
+#define C2O_PORT                GPIO_PORTF_BASE
+#define C2O_PIN                 GPIO_PIN_6
+
+#define C2_MINUS_PERIPH         SYSCTL_PERIPH_GPIOC
+#define C2_MINUS_PORT           GPIO_PORTC_BASE
+#define C2_MINUS_PIN            GPIO_PIN_7
+
+#define C2_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C2_PLUS_PORT            GPIO_PORTC_BASE
+#define C2_PLUS_PIN             GPIO_PIN_6
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP1_PORT               GPIO_PORTD_BASE
+#define CCP1_PIN                GPIO_PIN_7
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_1
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP3_PORT               GPIO_PORTD_BASE
+#define CCP3_PIN                GPIO_PIN_4
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP4_PORT               GPIO_PORTD_BASE
+#define CCP4_PIN                GPIO_PIN_5
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP5_PORT               GPIO_PORTC_BASE
+#define CCP5_PIN                GPIO_PIN_4
+
+#define CCP6_PERIPH             SYSCTL_PERIPH_GPIOH
+#define CCP6_PORT               GPIO_PORTH_BASE
+#define CCP6_PIN                GPIO_PIN_0
+
+#define CCP7_PERIPH             SYSCTL_PERIPH_GPIOH
+#define CCP7_PORT               GPIO_PORTH_BASE
+#define CCP7_PIN                GPIO_PIN_1
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define I2C1SCL_PERIPH          SYSCTL_PERIPH_GPIOA
+#define I2C1SCL_PORT            GPIO_PORTA_BASE
+#define I2C1SCL_PIN             GPIO_PIN_6
+
+#define I2C1SDA_PERIPH          SYSCTL_PERIPH_GPIOA
+#define I2C1SDA_PORT            GPIO_PORTA_BASE
+#define I2C1SDA_PIN             GPIO_PIN_7
+
+#define IDX0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define IDX0_PORT               GPIO_PORTD_BASE
+#define IDX0_PIN                GPIO_PIN_0
+
+#define PHA0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PHA0_PORT               GPIO_PORTD_BASE
+#define PHA0_PIN                GPIO_PIN_1
+
+#define PHB0_PERIPH             SYSCTL_PERIPH_GPIOF
+#define PHB0_PORT               GPIO_PORTF_BASE
+#define PHB0_PIN                GPIO_PIN_0
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SSI1CLK_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1CLK_PORT            GPIO_PORTE_BASE
+#define SSI1CLK_PIN             GPIO_PIN_0
+
+#define SSI1FSS_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1FSS_PORT            GPIO_PORTE_BASE
+#define SSI1FSS_PIN             GPIO_PIN_1
+
+#define SSI1RX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1RX_PORT             GPIO_PORTE_BASE
+#define SSI1RX_PIN              GPIO_PIN_2
+
+#define SSI1TX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1TX_PORT             GPIO_PORTE_BASE
+#define SSI1TX_PIN              GPIO_PIN_3
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#define U2RX_PERIPH             SYSCTL_PERIPH_GPIOG
+#define U2RX_PORT               GPIO_PORTG_BASE
+#define U2RX_PIN                GPIO_PIN_0
+
+#define U2TX_PERIPH             SYSCTL_PERIPH_GPIOG
+#define U2TX_PORT               GPIO_PORTG_BASE
+#define U2TX_PIN                GPIO_PIN_1
+
+#endif // PART_LM3S1512
+
+//*****************************************************************************
+//
+// LM3S1538 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1538
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP1_PORT               GPIO_PORTB_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_1
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP3_PORT               GPIO_PORTC_BASE
+#define CCP3_PIN                GPIO_PIN_6
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP4_PORT               GPIO_PORTC_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP5_PORT               GPIO_PORTB_BASE
+#define CCP5_PIN                GPIO_PIN_5
+
+#define CCP6_PERIPH             SYSCTL_PERIPH_GPIOH
+#define CCP6_PORT               GPIO_PORTH_BASE
+#define CCP6_PIN                GPIO_PIN_0
+
+#define CCP7_PERIPH             SYSCTL_PERIPH_GPIOH
+#define CCP7_PORT               GPIO_PORTH_BASE
+#define CCP7_PIN                GPIO_PIN_1
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define I2C1SCL_PERIPH          SYSCTL_PERIPH_GPIOA
+#define I2C1SCL_PORT            GPIO_PORTA_BASE
+#define I2C1SCL_PIN             GPIO_PIN_6
+
+#define I2C1SDA_PERIPH          SYSCTL_PERIPH_GPIOA
+#define I2C1SDA_PORT            GPIO_PORTA_BASE
+#define I2C1SDA_PIN             GPIO_PIN_7
+
+#define IDX0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define IDX0_PORT               GPIO_PORTD_BASE
+#define IDX0_PIN                GPIO_PIN_0
+
+#define PHA0_PERIPH             SYSCTL_PERIPH_GPIOC
+#define PHA0_PORT               GPIO_PORTC_BASE
+#define PHA0_PIN                GPIO_PIN_4
+
+#define PHB0_PERIPH             SYSCTL_PERIPH_GPIOF
+#define PHB0_PORT               GPIO_PORTF_BASE
+#define PHB0_PIN                GPIO_PIN_0
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SSI1CLK_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1CLK_PORT            GPIO_PORTE_BASE
+#define SSI1CLK_PIN             GPIO_PIN_0
+
+#define SSI1FSS_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1FSS_PORT            GPIO_PORTE_BASE
+#define SSI1FSS_PIN             GPIO_PIN_1
+
+#define SSI1RX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1RX_PORT             GPIO_PORTE_BASE
+#define SSI1RX_PIN              GPIO_PIN_2
+
+#define SSI1TX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1TX_PORT             GPIO_PORTE_BASE
+#define SSI1TX_PIN              GPIO_PIN_3
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#define U2RX_PERIPH             SYSCTL_PERIPH_GPIOG
+#define U2RX_PORT               GPIO_PORTG_BASE
+#define U2RX_PIN                GPIO_PIN_0
+
+#define U2TX_PERIPH             SYSCTL_PERIPH_GPIOG
+#define U2TX_PORT               GPIO_PORTG_BASE
+#define U2TX_PIN                GPIO_PIN_1
+
+#endif // PART_LM3S1538
+
+//*****************************************************************************
+//
+// LM3S1601 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1601
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOF
+#define C0O_PORT                GPIO_PORTF_BASE
+#define C0O_PIN                 GPIO_PIN_4
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1O_PERIPH              SYSCTL_PERIPH_GPIOE
+#define C1O_PORT                GPIO_PORTE_BASE
+#define C1O_PIN                 GPIO_PIN_6
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_5
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP1_PORT               GPIO_PORTD_BASE
+#define CCP1_PIN                GPIO_PIN_7
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_1
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP3_PORT               GPIO_PORTC_BASE
+#define CCP3_PIN                GPIO_PIN_6
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP4_PORT               GPIO_PORTC_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP5_PORT               GPIO_PORTC_BASE
+#define CCP5_PIN                GPIO_PIN_4
+
+#define CCP6_PERIPH             SYSCTL_PERIPH_GPIOH
+#define CCP6_PORT               GPIO_PORTH_BASE
+#define CCP6_PIN                GPIO_PIN_0
+
+#define CCP7_PERIPH             SYSCTL_PERIPH_GPIOH
+#define CCP7_PORT               GPIO_PORTH_BASE
+#define CCP7_PIN                GPIO_PIN_1
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define I2C1SCL_PERIPH          SYSCTL_PERIPH_GPIOA
+#define I2C1SCL_PORT            GPIO_PORTA_BASE
+#define I2C1SCL_PIN             GPIO_PIN_6
+
+#define I2C1SDA_PERIPH          SYSCTL_PERIPH_GPIOA
+#define I2C1SDA_PORT            GPIO_PORTA_BASE
+#define I2C1SDA_PIN             GPIO_PIN_7
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SSI1CLK_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1CLK_PORT            GPIO_PORTE_BASE
+#define SSI1CLK_PIN             GPIO_PIN_0
+
+#define SSI1FSS_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1FSS_PORT            GPIO_PORTE_BASE
+#define SSI1FSS_PIN             GPIO_PIN_1
+
+#define SSI1RX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1RX_PORT             GPIO_PORTE_BASE
+#define SSI1RX_PIN              GPIO_PIN_2
+
+#define SSI1TX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1TX_PORT             GPIO_PORTE_BASE
+#define SSI1TX_PIN              GPIO_PIN_3
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#define U2RX_PERIPH             SYSCTL_PERIPH_GPIOG
+#define U2RX_PORT               GPIO_PORTG_BASE
+#define U2RX_PIN                GPIO_PIN_0
+
+#define U2TX_PERIPH             SYSCTL_PERIPH_GPIOG
+#define U2TX_PORT               GPIO_PORTG_BASE
+#define U2TX_PIN                GPIO_PIN_1
+
+#endif // PART_LM3S1601
+
+//*****************************************************************************
+//
+// LM3S1607 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1607
+
+#define ADC0_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC0_PORT               GPIO_PORTE_BASE
+#define ADC0_PIN                GPIO_PIN_3
+
+#define ADC1_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC1_PORT               GPIO_PORTE_BASE
+#define ADC1_PIN                GPIO_PIN_2
+
+#define ADC2_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC2_PORT               GPIO_PORTE_BASE
+#define ADC2_PIN                GPIO_PIN_1
+
+#define ADC3_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC3_PORT               GPIO_PORTE_BASE
+#define ADC3_PIN                GPIO_PIN_0
+
+#define ADC4_PERIPH             SYSCTL_PERIPH_GPIOD
+#define ADC4_PORT               GPIO_PORTD_BASE
+#define ADC4_PIN                GPIO_PIN_3
+
+#define ADC5_PERIPH             SYSCTL_PERIPH_GPIOD
+#define ADC5_PORT               GPIO_PORTD_BASE
+#define ADC5_PIN                GPIO_PIN_2
+
+#define ADC6_PERIPH             SYSCTL_PERIPH_GPIOD
+#define ADC6_PORT               GPIO_PORTD_BASE
+#define ADC6_PIN                GPIO_PIN_1
+
+#define ADC7_PERIPH             SYSCTL_PERIPH_GPIOD
+#define ADC7_PORT               GPIO_PORTD_BASE
+#define ADC7_PIN                GPIO_PIN_0
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_5
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP1_PORT               GPIO_PORTC_BASE
+#define CCP1_PIN                GPIO_PIN_5
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP2_PORT               GPIO_PORTC_BASE
+#define CCP2_PIN                GPIO_PIN_4
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP3_PORT               GPIO_PORTC_BASE
+#define CCP3_PIN                GPIO_PIN_6
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP4_PORT               GPIO_PORTC_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP5_PORT               GPIO_PORTB_BASE
+#define CCP5_PIN                GPIO_PIN_6
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define I2C1SCL_PERIPH          SYSCTL_PERIPH_GPIOA
+#define I2C1SCL_PORT            GPIO_PORTA_BASE
+#define I2C1SCL_PIN             GPIO_PIN_6
+
+#define I2C1SDA_PERIPH          SYSCTL_PERIPH_GPIOA
+#define I2C1SDA_PORT            GPIO_PORTA_BASE
+#define I2C1SDA_PIN             GPIO_PIN_7
+
+#define NMI_PERIPH              SYSCTL_PERIPH_GPIOB
+#define NMI_PORT                GPIO_PORTB_BASE
+#define NMI_PIN                 GPIO_PIN_7
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOB
+#define U1RX_PORT               GPIO_PORTB_BASE
+#define U1RX_PIN                GPIO_PIN_0
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOB
+#define U1TX_PORT               GPIO_PORTB_BASE
+#define U1TX_PIN                GPIO_PIN_1
+
+#define U2RX_PERIPH             SYSCTL_PERIPH_GPIOB
+#define U2RX_PORT               GPIO_PORTB_BASE
+#define U2RX_PIN                GPIO_PIN_4
+
+#define U2TX_PERIPH             SYSCTL_PERIPH_GPIOE
+#define U2TX_PORT               GPIO_PORTE_BASE
+#define U2TX_PIN                GPIO_PIN_4
+
+#endif // PART_LM3S1607
+
+//*****************************************************************************
+//
+// LM3S1608 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1608
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOF
+#define C0O_PORT                GPIO_PORTF_BASE
+#define C0O_PIN                 GPIO_PIN_4
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1O_PERIPH              SYSCTL_PERIPH_GPIOF
+#define C1O_PORT                GPIO_PORTF_BASE
+#define C1O_PIN                 GPIO_PIN_5
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_5
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOF
+#define CCP1_PORT               GPIO_PORTF_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_1
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP3_PORT               GPIO_PORTC_BASE
+#define CCP3_PIN                GPIO_PIN_6
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP4_PORT               GPIO_PORTC_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP5_PORT               GPIO_PORTC_BASE
+#define CCP5_PIN                GPIO_PIN_4
+
+#define CCP6_PERIPH             SYSCTL_PERIPH_GPIOH
+#define CCP6_PORT               GPIO_PORTH_BASE
+#define CCP6_PIN                GPIO_PIN_0
+
+#define CCP7_PERIPH             SYSCTL_PERIPH_GPIOH
+#define CCP7_PORT               GPIO_PORTH_BASE
+#define CCP7_PIN                GPIO_PIN_1
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define I2C1SCL_PERIPH          SYSCTL_PERIPH_GPIOA
+#define I2C1SCL_PORT            GPIO_PORTA_BASE
+#define I2C1SCL_PIN             GPIO_PIN_6
+
+#define I2C1SDA_PERIPH          SYSCTL_PERIPH_GPIOA
+#define I2C1SDA_PORT            GPIO_PORTA_BASE
+#define I2C1SDA_PIN             GPIO_PIN_7
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SSI1CLK_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1CLK_PORT            GPIO_PORTE_BASE
+#define SSI1CLK_PIN             GPIO_PIN_0
+
+#define SSI1FSS_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1FSS_PORT            GPIO_PORTE_BASE
+#define SSI1FSS_PIN             GPIO_PIN_1
+
+#define SSI1RX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1RX_PORT             GPIO_PORTE_BASE
+#define SSI1RX_PIN              GPIO_PIN_2
+
+#define SSI1TX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1TX_PORT             GPIO_PORTE_BASE
+#define SSI1TX_PIN              GPIO_PIN_3
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#endif // PART_LM3S1608
+
+//*****************************************************************************
+//
+// LM3S1620 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1620
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOF
+#define C0O_PORT                GPIO_PORTF_BASE
+#define C0O_PIN                 GPIO_PIN_4
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1O_PERIPH              SYSCTL_PERIPH_GPIOF
+#define C1O_PORT                GPIO_PORTF_BASE
+#define C1O_PIN                 GPIO_PIN_5
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_5
+
+#define C2_MINUS_PERIPH         SYSCTL_PERIPH_GPIOC
+#define C2_MINUS_PORT           GPIO_PORTC_BASE
+#define C2_MINUS_PIN            GPIO_PIN_7
+
+#define C2_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C2_PLUS_PORT            GPIO_PORTC_BASE
+#define C2_PLUS_PIN             GPIO_PIN_6
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP1_PORT               GPIO_PORTA_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_1
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP3_PORT               GPIO_PORTD_BASE
+#define CCP3_PIN                GPIO_PIN_4
+
+#define FAULT_PERIPH            SYSCTL_PERIPH_GPIOD
+#define FAULT_PORT              GPIO_PORTD_BASE
+#define FAULT_PIN               GPIO_PIN_6
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define IDX0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define IDX0_PORT               GPIO_PORTD_BASE
+#define IDX0_PIN                GPIO_PIN_7
+
+#define PHA0_PERIPH             SYSCTL_PERIPH_GPIOC
+#define PHA0_PORT               GPIO_PORTC_BASE
+#define PHA0_PIN                GPIO_PIN_4
+
+#define PHB0_PERIPH             SYSCTL_PERIPH_GPIOF
+#define PHB0_PORT               GPIO_PORTF_BASE
+#define PHB0_PIN                GPIO_PIN_0
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM0_PORT               GPIO_PORTD_BASE
+#define PWM0_PIN                GPIO_PIN_0
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM1_PORT               GPIO_PORTD_BASE
+#define PWM1_PIN                GPIO_PIN_1
+
+#define PWM2_PERIPH             SYSCTL_PERIPH_GPIOH
+#define PWM2_PORT               GPIO_PORTH_BASE
+#define PWM2_PIN                GPIO_PIN_0
+
+#define PWM3_PERIPH             SYSCTL_PERIPH_GPIOH
+#define PWM3_PORT               GPIO_PORTH_BASE
+#define PWM3_PIN                GPIO_PIN_1
+
+#define PWM4_PERIPH             SYSCTL_PERIPH_GPIOE
+#define PWM4_PORT               GPIO_PORTE_BASE
+#define PWM4_PIN                GPIO_PIN_6
+
+#define PWM5_PERIPH             SYSCTL_PERIPH_GPIOE
+#define PWM5_PORT               GPIO_PORTE_BASE
+#define PWM5_PIN                GPIO_PIN_7
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SSI1CLK_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1CLK_PORT            GPIO_PORTE_BASE
+#define SSI1CLK_PIN             GPIO_PIN_0
+
+#define SSI1FSS_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1FSS_PORT            GPIO_PORTE_BASE
+#define SSI1FSS_PIN             GPIO_PIN_1
+
+#define SSI1RX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1RX_PORT             GPIO_PORTE_BASE
+#define SSI1RX_PIN              GPIO_PIN_2
+
+#define SSI1TX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1TX_PORT             GPIO_PORTE_BASE
+#define SSI1TX_PIN              GPIO_PIN_3
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#endif // PART_LM3S1620
+
+//*****************************************************************************
+//
+// LM3S1621 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1621
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+
+#define GPIO_PA4_SSI0RX         0x00001001
+
+#define GPIO_PA5_SSI0TX         0x00001401
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_U1CTS          0x00001809
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_U1DCD          0x00001C09
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_U1RX           0x00011007
+#define GPIO_PB4_EPI0S23        0x00011008
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+#define GPIO_PB5_EPI0S22        0x00011408
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_CCP5           0x00011806
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_EPI0S2         0x00021008
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_CCP3           0x00021405
+#define GPIO_PC5_EPI0S3         0x00021408
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+#define GPIO_PC6_EPI0S4         0x00021808
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_C1O            0x00021C07
+#define GPIO_PC7_EPI0S5         0x00021C08
+
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+#define GPIO_PD0_U1CTS          0x00030009
+
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_U1DCD          0x00030409
+#define GPIO_PD1_CCP2           0x0003040A
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_CCP5           0x00030804
+#define GPIO_PD2_EPI0S20        0x00030808
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_CCP0           0x00030C04
+#define GPIO_PD3_EPI0S21        0x00030C08
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+#define GPIO_PD4_U1RI           0x00031009
+#define GPIO_PD4_EPI0S19        0x0003100A
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_U2RX           0x00031409
+#define GPIO_PD5_EPI0S28        0x0003140A
+
+#define GPIO_PD6_U2TX           0x00031809
+#define GPIO_PD6_EPI0S29        0x0003180A
+
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+#define GPIO_PD7_U1DTR          0x00031C09
+#define GPIO_PD7_EPI0S30        0x00031C0A
+
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+#define GPIO_PE0_EPI0S8         0x00040008
+
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+#define GPIO_PE1_EPI0S9         0x00040408
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_CCP2           0x00040805
+#define GPIO_PE2_EPI0S24        0x00040808
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_CCP7           0x00040C05
+#define GPIO_PE3_EPI0S25        0x00040C08
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+
+#define GPIO_PE5_CCP5           0x00041401
+
+#define GPIO_PE6_C1O            0x00041802
+#define GPIO_PE6_U1CTS          0x00041809
+
+#define GPIO_PE7_U1DCD          0x00041C09
+
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_U1RTS          0x00050409
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_SSI1CLK        0x00050809
+
+#define GPIO_PF3_SSI1FSS        0x00050C09
+
+#define GPIO_PF4_CCP0           0x00051001
+#define GPIO_PF4_C0O            0x00051002
+#define GPIO_PF4_EPI0S12        0x00051008
+#define GPIO_PF4_SSI1RX         0x00051009
+
+#define GPIO_PF5_CCP2           0x00051401
+#define GPIO_PF5_C1O            0x00051402
+#define GPIO_PF5_EPI0S15        0x00051408
+#define GPIO_PF5_SSI1TX         0x00051409
+
+#define GPIO_PF6_CCP1           0x00051801
+#define GPIO_PF6_U1RTS          0x0005180A
+
+#define GPIO_PF7_CCP4           0x00051C01
+#define GPIO_PF7_EPI0S12        0x00051C08
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_I2C1SCL        0x00060003
+#define GPIO_PG0_EPI0S13        0x00060008
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_I2C1SDA        0x00060403
+#define GPIO_PG1_EPI0S14        0x00060408
+
+#define GPIO_PG4_CCP3           0x00061001
+#define GPIO_PG4_EPI0S15        0x00061008
+#define GPIO_PG4_U1RI           0x0006100A
+
+#define GPIO_PG5_CCP5           0x00061401
+#define GPIO_PG5_U1DTR          0x0006140A
+
+#define GPIO_PG6_U1RI           0x0006180A
+
+#define GPIO_PG7_CCP5           0x00061C08
+#define GPIO_PG7_EPI0S31        0x00061C09
+
+#define GPIO_PH0_CCP6           0x00070001
+#define GPIO_PH0_EPI0S6         0x00070008
+
+#define GPIO_PH1_CCP7           0x00070401
+#define GPIO_PH1_EPI0S7         0x00070408
+
+#define GPIO_PH2_C1O            0x00070802
+#define GPIO_PH2_EPI0S1         0x00070808
+
+#define GPIO_PH3_EPI0S0         0x00070C08
+
+#define GPIO_PH4_EPI0S10        0x00071008
+#define GPIO_PH4_SSI1CLK        0x0007100B
+
+#define GPIO_PH5_EPI0S11        0x00071408
+#define GPIO_PH5_SSI1FSS        0x0007140B
+
+#define GPIO_PH6_EPI0S26        0x00071808
+#define GPIO_PH6_SSI1RX         0x0007180B
+
+#define GPIO_PH7_EPI0S27        0x00071C08
+#define GPIO_PH7_SSI1TX         0x00071C0B
+
+#define GPIO_PJ0_EPI0S16        0x00080008
+#define GPIO_PJ0_I2C1SCL        0x0008000B
+
+#define GPIO_PJ1_EPI0S17        0x00080408
+#define GPIO_PJ1_I2C1SDA        0x0008040B
+
+#define GPIO_PJ2_EPI0S18        0x00080808
+#define GPIO_PJ2_CCP0           0x00080809
+
+#endif // PART_LM3S1621
+
+//*****************************************************************************
+//
+// LM3S1625 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1625
+
+#define ADC0_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC0_PORT               GPIO_PORTE_BASE
+#define ADC0_PIN                GPIO_PIN_3
+
+#define ADC1_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC1_PORT               GPIO_PORTE_BASE
+#define ADC1_PIN                GPIO_PIN_2
+
+#define ADC2_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC2_PORT               GPIO_PORTE_BASE
+#define ADC2_PIN                GPIO_PIN_1
+
+#define ADC3_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC3_PORT               GPIO_PORTE_BASE
+#define ADC3_PIN                GPIO_PIN_0
+
+#define ADC4_PERIPH             SYSCTL_PERIPH_GPIOD
+#define ADC4_PORT               GPIO_PORTD_BASE
+#define ADC4_PIN                GPIO_PIN_3
+
+#define ADC5_PERIPH             SYSCTL_PERIPH_GPIOD
+#define ADC5_PORT               GPIO_PORTD_BASE
+#define ADC5_PIN                GPIO_PIN_2
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOB
+#define C0O_PORT                GPIO_PORTB_BASE
+#define C0O_PIN                 GPIO_PIN_5
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP0_PORT               GPIO_PORTC_BASE
+#define CCP0_PIN                GPIO_PIN_7
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP1_PORT               GPIO_PORTC_BASE
+#define CCP1_PIN                GPIO_PIN_5
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP2_PORT               GPIO_PORTC_BASE
+#define CCP2_PIN                GPIO_PIN_4
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP3_PORT               GPIO_PORTC_BASE
+#define CCP3_PIN                GPIO_PIN_6
+
+#define FAULT0_PERIPH           SYSCTL_PERIPH_GPIOE
+#define FAULT0_PORT             GPIO_PORTE_BASE
+#define FAULT0_PIN              GPIO_PIN_4
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define I2C1SCL_PERIPH          SYSCTL_PERIPH_GPIOA
+#define I2C1SCL_PORT            GPIO_PORTA_BASE
+#define I2C1SCL_PIN             GPIO_PIN_6
+
+#define I2C1SDA_PERIPH          SYSCTL_PERIPH_GPIOA
+#define I2C1SDA_PORT            GPIO_PORTA_BASE
+#define I2C1SDA_PIN             GPIO_PIN_7
+
+#define NMI_PERIPH              SYSCTL_PERIPH_GPIOB
+#define NMI_PORT                GPIO_PORTB_BASE
+#define NMI_PIN                 GPIO_PIN_7
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM0_PORT               GPIO_PORTD_BASE
+#define PWM0_PIN                GPIO_PIN_0
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM1_PORT               GPIO_PORTD_BASE
+#define PWM1_PIN                GPIO_PIN_1
+
+#define PWM2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define PWM2_PORT               GPIO_PORTB_BASE
+#define PWM2_PIN                GPIO_PIN_0
+
+#define PWM3_PERIPH             SYSCTL_PERIPH_GPIOB
+#define PWM3_PORT               GPIO_PORTB_BASE
+#define PWM3_PIN                GPIO_PIN_1
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#endif // PART_LM3S1625
+
+//*****************************************************************************
+//
+// LM3S1626 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1626
+
+#define ADC0_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC0_PORT               GPIO_PORTE_BASE
+#define ADC0_PIN                GPIO_PIN_3
+
+#define ADC1_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC1_PORT               GPIO_PORTE_BASE
+#define ADC1_PIN                GPIO_PIN_2
+
+#define ADC2_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC2_PORT               GPIO_PORTE_BASE
+#define ADC2_PIN                GPIO_PIN_1
+
+#define ADC3_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC3_PORT               GPIO_PORTE_BASE
+#define ADC3_PIN                GPIO_PIN_0
+
+#define ADC4_PERIPH             SYSCTL_PERIPH_GPIOD
+#define ADC4_PORT               GPIO_PORTD_BASE
+#define ADC4_PIN                GPIO_PIN_3
+
+#define ADC5_PERIPH             SYSCTL_PERIPH_GPIOD
+#define ADC5_PORT               GPIO_PORTD_BASE
+#define ADC5_PIN                GPIO_PIN_2
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP0_PORT               GPIO_PORTC_BASE
+#define CCP0_PIN                GPIO_PIN_6
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP1_PORT               GPIO_PORTB_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP2_PORT               GPIO_PORTC_BASE
+#define CCP2_PIN                GPIO_PIN_4
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP3_PORT               GPIO_PORTC_BASE
+#define CCP3_PIN                GPIO_PIN_5
+
+#define FAULT0_PERIPH           SYSCTL_PERIPH_GPIOE
+#define FAULT0_PORT             GPIO_PORTE_BASE
+#define FAULT0_PIN              GPIO_PIN_4
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define IDX0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define IDX0_PORT               GPIO_PORTD_BASE
+#define IDX0_PIN                GPIO_PIN_0
+
+#define NMI_PERIPH              SYSCTL_PERIPH_GPIOB
+#define NMI_PORT                GPIO_PORTB_BASE
+#define NMI_PIN                 GPIO_PIN_7
+
+#define PHA0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PHA0_PORT               GPIO_PORTD_BASE
+#define PHA0_PIN                GPIO_PIN_1
+
+#define PHB0_PERIPH             SYSCTL_PERIPH_GPIOC
+#define PHB0_PORT               GPIO_PORTC_BASE
+#define PHB0_PIN                GPIO_PIN_7
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOA
+#define PWM0_PORT               GPIO_PORTA_BASE
+#define PWM0_PIN                GPIO_PIN_6
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOA
+#define PWM1_PORT               GPIO_PORTA_BASE
+#define PWM1_PIN                GPIO_PIN_7
+
+#define PWM2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define PWM2_PORT               GPIO_PORTB_BASE
+#define PWM2_PIN                GPIO_PIN_0
+
+#define PWM3_PERIPH             SYSCTL_PERIPH_GPIOB
+#define PWM3_PORT               GPIO_PORTB_BASE
+#define PWM3_PIN                GPIO_PIN_1
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOB
+#define U1RX_PORT               GPIO_PORTB_BASE
+#define U1RX_PIN                GPIO_PIN_4
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOB
+#define U1TX_PORT               GPIO_PORTB_BASE
+#define U1TX_PIN                GPIO_PIN_5
+
+#endif // PART_LM3S1626
+
+//*****************************************************************************
+//
+// LM3S1627 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1627
+
+#define ADC0_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC0_PORT               GPIO_PORTE_BASE
+#define ADC0_PIN                GPIO_PIN_3
+
+#define ADC1_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC1_PORT               GPIO_PORTE_BASE
+#define ADC1_PIN                GPIO_PIN_2
+
+#define ADC2_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC2_PORT               GPIO_PORTE_BASE
+#define ADC2_PIN                GPIO_PIN_1
+
+#define ADC3_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC3_PORT               GPIO_PORTE_BASE
+#define ADC3_PIN                GPIO_PIN_0
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP0_PORT               GPIO_PORTC_BASE
+#define CCP0_PIN                GPIO_PIN_6
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP1_PORT               GPIO_PORTB_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_5
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP3_PORT               GPIO_PORTC_BASE
+#define CCP3_PIN                GPIO_PIN_5
+
+#define FAULT0_PERIPH           SYSCTL_PERIPH_GPIOE
+#define FAULT0_PORT             GPIO_PORTE_BASE
+#define FAULT0_PIN              GPIO_PIN_4
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define IDX0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define IDX0_PORT               GPIO_PORTB_BASE
+#define IDX0_PIN                GPIO_PIN_4
+
+#define NMI_PERIPH              SYSCTL_PERIPH_GPIOB
+#define NMI_PORT                GPIO_PORTB_BASE
+#define NMI_PIN                 GPIO_PIN_7
+
+#define PHA0_PERIPH             SYSCTL_PERIPH_GPIOC
+#define PHA0_PORT               GPIO_PORTC_BASE
+#define PHA0_PIN                GPIO_PIN_4
+
+#define PHB0_PERIPH             SYSCTL_PERIPH_GPIOC
+#define PHB0_PORT               GPIO_PORTC_BASE
+#define PHB0_PIN                GPIO_PIN_7
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM0_PORT               GPIO_PORTD_BASE
+#define PWM0_PIN                GPIO_PIN_0
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM1_PORT               GPIO_PORTD_BASE
+#define PWM1_PIN                GPIO_PIN_1
+
+#define PWM2_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM2_PORT               GPIO_PORTD_BASE
+#define PWM2_PIN                GPIO_PIN_2
+
+#define PWM3_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM3_PORT               GPIO_PORTD_BASE
+#define PWM3_PIN                GPIO_PIN_3
+
+#define PWM4_PERIPH             SYSCTL_PERIPH_GPIOA
+#define PWM4_PORT               GPIO_PORTA_BASE
+#define PWM4_PIN                GPIO_PIN_6
+
+#define PWM5_PERIPH             SYSCTL_PERIPH_GPIOA
+#define PWM5_PORT               GPIO_PORTA_BASE
+#define PWM5_PIN                GPIO_PIN_7
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOB
+#define U1RX_PORT               GPIO_PORTB_BASE
+#define U1RX_PIN                GPIO_PIN_0
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOB
+#define U1TX_PORT               GPIO_PORTB_BASE
+#define U1TX_PIN                GPIO_PIN_1
+
+#endif // PART_LM3S1627
+
+//*****************************************************************************
+//
+// LM3S1635 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1635
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOF
+#define C0O_PORT                GPIO_PORTF_BASE
+#define C0O_PIN                 GPIO_PIN_4
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1O_PERIPH              SYSCTL_PERIPH_GPIOF
+#define C1O_PORT                GPIO_PORTF_BASE
+#define C1O_PIN                 GPIO_PIN_5
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_5
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP0_PORT               GPIO_PORTD_BASE
+#define CCP0_PIN                GPIO_PIN_4
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP1_PORT               GPIO_PORTD_BASE
+#define CCP1_PIN                GPIO_PIN_7
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP2_PORT               GPIO_PORTD_BASE
+#define CCP2_PIN                GPIO_PIN_5
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP3_PORT               GPIO_PORTC_BASE
+#define CCP3_PIN                GPIO_PIN_6
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP4_PORT               GPIO_PORTC_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP5_PORT               GPIO_PORTC_BASE
+#define CCP5_PIN                GPIO_PIN_4
+
+#define CCP6_PERIPH             SYSCTL_PERIPH_GPIOH
+#define CCP6_PORT               GPIO_PORTH_BASE
+#define CCP6_PIN                GPIO_PIN_0
+
+#define CCP7_PERIPH             SYSCTL_PERIPH_GPIOH
+#define CCP7_PORT               GPIO_PORTH_BASE
+#define CCP7_PIN                GPIO_PIN_1
+
+#define FAULT_PERIPH            SYSCTL_PERIPH_GPIOD
+#define FAULT_PORT              GPIO_PORTD_BASE
+#define FAULT_PIN               GPIO_PIN_6
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define I2C1SCL_PERIPH          SYSCTL_PERIPH_GPIOA
+#define I2C1SCL_PORT            GPIO_PORTA_BASE
+#define I2C1SCL_PIN             GPIO_PIN_6
+
+#define I2C1SDA_PERIPH          SYSCTL_PERIPH_GPIOA
+#define I2C1SDA_PORT            GPIO_PORTA_BASE
+#define I2C1SDA_PIN             GPIO_PIN_7
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM0_PORT               GPIO_PORTD_BASE
+#define PWM0_PIN                GPIO_PIN_0
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM1_PORT               GPIO_PORTD_BASE
+#define PWM1_PIN                GPIO_PIN_1
+
+#define PWM2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define PWM2_PORT               GPIO_PORTB_BASE
+#define PWM2_PIN                GPIO_PIN_0
+
+#define PWM3_PERIPH             SYSCTL_PERIPH_GPIOB
+#define PWM3_PORT               GPIO_PORTB_BASE
+#define PWM3_PIN                GPIO_PIN_1
+
+#define PWM4_PERIPH             SYSCTL_PERIPH_GPIOF
+#define PWM4_PORT               GPIO_PORTF_BASE
+#define PWM4_PIN                GPIO_PIN_2
+
+#define PWM5_PERIPH             SYSCTL_PERIPH_GPIOF
+#define PWM5_PORT               GPIO_PORTF_BASE
+#define PWM5_PIN                GPIO_PIN_3
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SSI1CLK_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1CLK_PORT            GPIO_PORTE_BASE
+#define SSI1CLK_PIN             GPIO_PIN_0
+
+#define SSI1FSS_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1FSS_PORT            GPIO_PORTE_BASE
+#define SSI1FSS_PIN             GPIO_PIN_1
+
+#define SSI1RX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1RX_PORT             GPIO_PORTE_BASE
+#define SSI1RX_PIN              GPIO_PIN_2
+
+#define SSI1TX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1TX_PORT             GPIO_PORTE_BASE
+#define SSI1TX_PIN              GPIO_PIN_3
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#define U2RX_PERIPH             SYSCTL_PERIPH_GPIOG
+#define U2RX_PORT               GPIO_PORTG_BASE
+#define U2RX_PIN                GPIO_PIN_0
+
+#define U2TX_PERIPH             SYSCTL_PERIPH_GPIOG
+#define U2TX_PORT               GPIO_PORTG_BASE
+#define U2TX_PIN                GPIO_PIN_1
+
+#endif // PART_LM3S1635
+
+//*****************************************************************************
+//
+// LM3S1637 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1637
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOC
+#define C0O_PORT                GPIO_PORTC_BASE
+#define C0O_PIN                 GPIO_PIN_5
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP1_PORT               GPIO_PORTA_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_1
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP3_PORT               GPIO_PORTC_BASE
+#define CCP3_PIN                GPIO_PIN_6
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP4_PORT               GPIO_PORTA_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP5_PORT               GPIO_PORTB_BASE
+#define CCP5_PIN                GPIO_PIN_5
+
+#define FAULT_PERIPH            SYSCTL_PERIPH_GPIOD
+#define FAULT_PORT              GPIO_PORTD_BASE
+#define FAULT_PIN               GPIO_PIN_6
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define IDX0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define IDX0_PORT               GPIO_PORTD_BASE
+#define IDX0_PIN                GPIO_PIN_7
+
+#define PHA0_PERIPH             SYSCTL_PERIPH_GPIOC
+#define PHA0_PORT               GPIO_PORTC_BASE
+#define PHA0_PIN                GPIO_PIN_4
+
+#define PHB0_PERIPH             SYSCTL_PERIPH_GPIOC
+#define PHB0_PORT               GPIO_PORTC_BASE
+#define PHB0_PIN                GPIO_PIN_7
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM0_PORT               GPIO_PORTD_BASE
+#define PWM0_PIN                GPIO_PIN_0
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM1_PORT               GPIO_PORTD_BASE
+#define PWM1_PIN                GPIO_PIN_1
+
+#define PWM2_PERIPH             SYSCTL_PERIPH_GPIOH
+#define PWM2_PORT               GPIO_PORTH_BASE
+#define PWM2_PIN                GPIO_PIN_0
+
+#define PWM3_PERIPH             SYSCTL_PERIPH_GPIOH
+#define PWM3_PORT               GPIO_PORTH_BASE
+#define PWM3_PIN                GPIO_PIN_1
+
+#define PWM4_PERIPH             SYSCTL_PERIPH_GPIOE
+#define PWM4_PORT               GPIO_PORTE_BASE
+#define PWM4_PIN                GPIO_PIN_0
+
+#define PWM5_PERIPH             SYSCTL_PERIPH_GPIOE
+#define PWM5_PORT               GPIO_PORTE_BASE
+#define PWM5_PIN                GPIO_PIN_1
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#define U2RX_PERIPH             SYSCTL_PERIPH_GPIOG
+#define U2RX_PORT               GPIO_PORTG_BASE
+#define U2RX_PIN                GPIO_PIN_0
+
+#define U2TX_PERIPH             SYSCTL_PERIPH_GPIOG
+#define U2TX_PORT               GPIO_PORTG_BASE
+#define U2TX_PIN                GPIO_PIN_1
+
+#endif // PART_LM3S1637
+
+//*****************************************************************************
+//
+// LM3S1651 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1651
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_PWM4           0x00000804
+#define GPIO_PA2_I2S0RXSD       0x00000809
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_PWM5           0x00000C04
+#define GPIO_PA3_I2S0RXMCLK     0x00000C09
+
+#define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_I2S0TXSCK      0x00001009
+
+#define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_I2S0TXWS       0x00001409
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_PWM0           0x00001804
+#define GPIO_PA6_PWM4           0x00001805
+#define GPIO_PA6_U1CTS          0x00001809
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_PWM1           0x00001C04
+#define GPIO_PA7_PWM5           0x00001C05
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_U1DCD          0x00001C09
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_PWM2           0x00010002
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_PWM3           0x00010402
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_IDX0           0x00010802
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_FAULT0         0x00010C02
+#define GPIO_PB3_FAULT3         0x00010C04
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_IDX0           0x00011006
+#define GPIO_PB4_U1RX           0x00011007
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_FAULT1         0x00011804
+#define GPIO_PB6_IDX0           0x00011805
+#define GPIO_PB6_CCP5           0x00011806
+#define GPIO_PB6_I2S0TXSCK      0x00011809
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_PHA0           0x00021002
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_FAULT2         0x00021404
+#define GPIO_PC5_CCP3           0x00021405
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_PHB0           0x00021802
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_PHB0           0x00021C02
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_C1O            0x00021C07
+
+#define GPIO_PD0_PWM0           0x00030001
+#define GPIO_PD0_IDX0           0x00030003
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+#define GPIO_PD0_I2S0RXSCK      0x00030008
+#define GPIO_PD0_U1CTS          0x00030009
+
+#define GPIO_PD1_PWM1           0x00030401
+#define GPIO_PD1_PHA0           0x00030403
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_I2S0RXWS       0x00030408
+#define GPIO_PD1_U1DCD          0x00030409
+#define GPIO_PD1_CCP2           0x0003040A
+#define GPIO_PD1_PHB1           0x0003040B
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_PWM2           0x00030803
+#define GPIO_PD2_CCP5           0x00030804
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_PWM3           0x00030C03
+#define GPIO_PD3_CCP0           0x00030C04
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+#define GPIO_PD4_I2S0RXSD       0x00031008
+#define GPIO_PD4_U1RI           0x00031009
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_I2S0RXMCLK     0x00031408
+#define GPIO_PD5_U2RX           0x00031409
+
+#define GPIO_PD6_FAULT0         0x00031801
+#define GPIO_PD6_I2S0TXSCK      0x00031808
+#define GPIO_PD6_U2TX           0x00031809
+
+#define GPIO_PD7_IDX0           0x00031C01
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+#define GPIO_PD7_I2S0TXWS       0x00031C08
+#define GPIO_PD7_U1DTR          0x00031C09
+
+#define GPIO_PE0_PWM4           0x00040001
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+
+#define GPIO_PE1_PWM5           0x00040401
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_FAULT0         0x00040403
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_PHB1           0x00040803
+#define GPIO_PE2_PHA0           0x00040804
+#define GPIO_PE2_CCP2           0x00040805
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_PHA1           0x00040C03
+#define GPIO_PE3_PHB0           0x00040C04
+#define GPIO_PE3_CCP7           0x00040C05
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_FAULT0         0x00041004
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+#define GPIO_PE4_I2S0TXWS       0x00041009
+
+#define GPIO_PE5_CCP5           0x00041401
+#define GPIO_PE5_I2S0TXSD       0x00041409
+
+#define GPIO_PE6_PWM4           0x00041801
+#define GPIO_PE6_C1O            0x00041802
+#define GPIO_PE6_U1CTS          0x00041809
+
+#define GPIO_PE7_PWM5           0x00041C01
+#define GPIO_PE7_U1DCD          0x00041C09
+
+#define GPIO_PF0_PHB0           0x00050002
+#define GPIO_PF0_PWM0           0x00050003
+#define GPIO_PF0_I2S0TXSD       0x00050008
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_IDX1           0x00050402
+#define GPIO_PF1_PWM1           0x00050403
+#define GPIO_PF1_I2S0TXMCLK     0x00050408
+#define GPIO_PF1_U1RTS          0x00050409
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_PWM4           0x00050802
+#define GPIO_PF2_PWM2           0x00050804
+#define GPIO_PF2_SSI1CLK        0x00050809
+
+#define GPIO_PF3_PWM5           0x00050C02
+#define GPIO_PF3_PWM3           0x00050C04
+#define GPIO_PF3_SSI1FSS        0x00050C09
+
+#define GPIO_PF4_CCP0           0x00051001
+#define GPIO_PF4_C0O            0x00051002
+#define GPIO_PF4_FAULT0         0x00051004
+#define GPIO_PF4_SSI1RX         0x00051009
+
+#define GPIO_PF5_CCP2           0x00051401
+#define GPIO_PF5_C1O            0x00051402
+#define GPIO_PF5_SSI1TX         0x00051409
+
+#define GPIO_PF6_CCP1           0x00051801
+#define GPIO_PF6_PHA0           0x00051804
+#define GPIO_PF6_I2S0TXMCLK     0x00051809
+#define GPIO_PF6_U1RTS          0x0005180A
+
+#define GPIO_PF7_CCP4           0x00051C01
+#define GPIO_PF7_PHB0           0x00051C04
+#define GPIO_PF7_FAULT1         0x00051C09
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_PWM0           0x00060002
+#define GPIO_PG0_I2C1SCL        0x00060003
+#define GPIO_PG0_PWM4           0x00060004
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_PWM1           0x00060402
+#define GPIO_PG1_I2C1SDA        0x00060403
+#define GPIO_PG1_PWM5           0x00060404
+
+#define GPIO_PG2_PWM0           0x00060801
+#define GPIO_PG2_FAULT0         0x00060804
+#define GPIO_PG2_IDX1           0x00060808
+#define GPIO_PG2_I2S0RXSD       0x00060809
+
+#define GPIO_PG3_PWM1           0x00060C01
+#define GPIO_PG3_FAULT2         0x00060C04
+#define GPIO_PG3_FAULT0         0x00060C08
+#define GPIO_PG3_I2S0RXMCLK     0x00060C09
+
+#define GPIO_PG4_CCP3           0x00061001
+#define GPIO_PG4_FAULT1         0x00061004
+#define GPIO_PG4_U1RI           0x0006100A
+
+#define GPIO_PG5_CCP5           0x00061401
+#define GPIO_PG5_IDX0           0x00061404
+#define GPIO_PG5_FAULT1         0x00061405
+#define GPIO_PG5_I2S0RXSCK      0x00061409
+#define GPIO_PG5_U1DTR          0x0006140A
+
+#define GPIO_PG6_PHA1           0x00061801
+#define GPIO_PG6_FAULT1         0x00061808
+#define GPIO_PG6_I2S0RXWS       0x00061809
+#define GPIO_PG6_U1RI           0x0006180A
+
+#define GPIO_PG7_PHB1           0x00061C01
+#define GPIO_PG7_CCP5           0x00061C08
+
+#define GPIO_PH0_CCP6           0x00070001
+#define GPIO_PH0_PWM2           0x00070002
+#define GPIO_PH0_PWM4           0x00070009
+
+#define GPIO_PH1_CCP7           0x00070401
+#define GPIO_PH1_PWM3           0x00070402
+#define GPIO_PH1_PWM5           0x00070409
+
+#define GPIO_PH2_IDX1           0x00070801
+#define GPIO_PH2_C1O            0x00070802
+#define GPIO_PH2_FAULT3         0x00070804
+
+#define GPIO_PH3_PHB0           0x00070C01
+#define GPIO_PH3_FAULT0         0x00070C02
+
+#define GPIO_PH4_SSI1CLK        0x0007100B
+
+#define GPIO_PH5_FAULT2         0x0007140A
+#define GPIO_PH5_SSI1FSS        0x0007140B
+
+#define GPIO_PH6_PWM4           0x0007180A
+#define GPIO_PH6_SSI1RX         0x0007180B
+
+#define GPIO_PH7_PWM5           0x00071C0A
+#define GPIO_PH7_SSI1TX         0x00071C0B
+
+#define GPIO_PJ0_PWM0           0x0008000A
+#define GPIO_PJ0_I2C1SCL        0x0008000B
+
+#define GPIO_PJ1_PWM1           0x0008040A
+#define GPIO_PJ1_I2C1SDA        0x0008040B
+
+#define GPIO_PJ2_CCP0           0x00080809
+#define GPIO_PJ2_FAULT0         0x0008080A
+
+#endif // PART_LM3S1651
+
+//*****************************************************************************
+//
+// LM3S1751 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1751
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOC
+#define C0O_PORT                GPIO_PORTC_BASE
+#define C0O_PIN                 GPIO_PIN_5
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP1_PORT               GPIO_PORTA_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_1
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP3_PORT               GPIO_PORTC_BASE
+#define CCP3_PIN                GPIO_PIN_6
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP4_PORT               GPIO_PORTA_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP5_PORT               GPIO_PORTB_BASE
+#define CCP5_PIN                GPIO_PIN_5
+
+#define FAULT_PERIPH            SYSCTL_PERIPH_GPIOD
+#define FAULT_PORT              GPIO_PORTD_BASE
+#define FAULT_PIN               GPIO_PIN_6
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM0_PORT               GPIO_PORTD_BASE
+#define PWM0_PIN                GPIO_PIN_0
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM1_PORT               GPIO_PORTD_BASE
+#define PWM1_PIN                GPIO_PIN_1
+
+#define PWM2_PERIPH             SYSCTL_PERIPH_GPIOH
+#define PWM2_PORT               GPIO_PORTH_BASE
+#define PWM2_PIN                GPIO_PIN_0
+
+#define PWM3_PERIPH             SYSCTL_PERIPH_GPIOH
+#define PWM3_PORT               GPIO_PORTH_BASE
+#define PWM3_PIN                GPIO_PIN_1
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SSI1CLK_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1CLK_PORT            GPIO_PORTE_BASE
+#define SSI1CLK_PIN             GPIO_PIN_0
+
+#define SSI1FSS_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1FSS_PORT            GPIO_PORTE_BASE
+#define SSI1FSS_PIN             GPIO_PIN_1
+
+#define SSI1RX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1RX_PORT             GPIO_PORTE_BASE
+#define SSI1RX_PIN              GPIO_PIN_2
+
+#define SSI1TX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1TX_PORT             GPIO_PORTE_BASE
+#define SSI1TX_PIN              GPIO_PIN_3
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#define U2RX_PERIPH             SYSCTL_PERIPH_GPIOG
+#define U2RX_PORT               GPIO_PORTG_BASE
+#define U2RX_PIN                GPIO_PIN_0
+
+#define U2TX_PERIPH             SYSCTL_PERIPH_GPIOG
+#define U2TX_PORT               GPIO_PORTG_BASE
+#define U2TX_PIN                GPIO_PIN_1
+
+#endif // PART_LM3S1751
+
+//*****************************************************************************
+//
+// LM3S1776 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1776
+
+#define ADC0_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC0_PORT               GPIO_PORTE_BASE
+#define ADC0_PIN                GPIO_PIN_3
+
+#define ADC1_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC1_PORT               GPIO_PORTE_BASE
+#define ADC1_PIN                GPIO_PIN_2
+
+#define ADC2_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC2_PORT               GPIO_PORTE_BASE
+#define ADC2_PIN                GPIO_PIN_1
+
+#define ADC3_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC3_PORT               GPIO_PORTE_BASE
+#define ADC3_PIN                GPIO_PIN_0
+
+#define ADC4_PERIPH             SYSCTL_PERIPH_GPIOD
+#define ADC4_PORT               GPIO_PORTD_BASE
+#define ADC4_PIN                GPIO_PIN_3
+
+#define ADC5_PERIPH             SYSCTL_PERIPH_GPIOD
+#define ADC5_PORT               GPIO_PORTD_BASE
+#define ADC5_PIN                GPIO_PIN_2
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP0_PORT               GPIO_PORTC_BASE
+#define CCP0_PIN                GPIO_PIN_7
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_5
+
+#define FAULT0_PERIPH           SYSCTL_PERIPH_GPIOE
+#define FAULT0_PORT             GPIO_PORTE_BASE
+#define FAULT0_PIN              GPIO_PIN_4
+
+#define FAULT1_PERIPH           SYSCTL_PERIPH_GPIOB
+#define FAULT1_PORT             GPIO_PORTB_BASE
+#define FAULT1_PIN              GPIO_PIN_6
+
+#define FAULT2_PERIPH           SYSCTL_PERIPH_GPIOC
+#define FAULT2_PORT             GPIO_PORTC_BASE
+#define FAULT2_PIN              GPIO_PIN_5
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define NMI_PERIPH              SYSCTL_PERIPH_GPIOB
+#define NMI_PORT                GPIO_PORTB_BASE
+#define NMI_PIN                 GPIO_PIN_7
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM0_PORT               GPIO_PORTD_BASE
+#define PWM0_PIN                GPIO_PIN_0
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM1_PORT               GPIO_PORTD_BASE
+#define PWM1_PIN                GPIO_PIN_1
+
+#define PWM2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define PWM2_PORT               GPIO_PORTB_BASE
+#define PWM2_PIN                GPIO_PIN_0
+
+#define PWM3_PERIPH             SYSCTL_PERIPH_GPIOB
+#define PWM3_PORT               GPIO_PORTB_BASE
+#define PWM3_PIN                GPIO_PIN_1
+
+#define PWM4_PERIPH             SYSCTL_PERIPH_GPIOA
+#define PWM4_PORT               GPIO_PORTA_BASE
+#define PWM4_PIN                GPIO_PIN_6
+
+#define PWM5_PERIPH             SYSCTL_PERIPH_GPIOA
+#define PWM5_PORT               GPIO_PORTA_BASE
+#define PWM5_PIN                GPIO_PIN_7
+
+#define PWM6_PERIPH             SYSCTL_PERIPH_GPIOC
+#define PWM6_PORT               GPIO_PORTC_BASE
+#define PWM6_PIN                GPIO_PIN_4
+
+#define PWM7_PERIPH             SYSCTL_PERIPH_GPIOC
+#define PWM7_PORT               GPIO_PORTC_BASE
+#define PWM7_PIN                GPIO_PIN_6
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#endif // PART_LM3S1776
+
+//*****************************************************************************
+//
+// LM3S1811 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1811
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+
+#define GPIO_PA4_SSI0RX         0x00001001
+
+#define GPIO_PA5_SSI0TX         0x00001401
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_U1CTS          0x00001809
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_U1DCD          0x00001C09
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_U1RX           0x00011007
+#define GPIO_PB4_EPI0S23        0x00011008
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+#define GPIO_PB5_EPI0S22        0x00011408
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_CCP5           0x00011806
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_EPI0S2         0x00021008
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_CCP3           0x00021405
+#define GPIO_PC5_EPI0S3         0x00021408
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+#define GPIO_PC6_EPI0S4         0x00021808
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_C1O            0x00021C07
+#define GPIO_PC7_EPI0S5         0x00021C08
+
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+#define GPIO_PD0_U1CTS          0x00030009
+
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_U1DCD          0x00030409
+#define GPIO_PD1_CCP2           0x0003040A
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_CCP5           0x00030804
+#define GPIO_PD2_EPI0S20        0x00030808
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_CCP0           0x00030C04
+#define GPIO_PD3_EPI0S21        0x00030C08
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+#define GPIO_PD4_U1RI           0x00031009
+#define GPIO_PD4_EPI0S19        0x0003100A
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_U2RX           0x00031409
+#define GPIO_PD5_EPI0S28        0x0003140A
+
+#define GPIO_PD6_U2TX           0x00031809
+#define GPIO_PD6_EPI0S29        0x0003180A
+
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+#define GPIO_PD7_U1DTR          0x00031C09
+#define GPIO_PD7_EPI0S30        0x00031C0A
+
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+#define GPIO_PE0_EPI0S8         0x00040008
+
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+#define GPIO_PE1_EPI0S9         0x00040408
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_CCP2           0x00040805
+#define GPIO_PE2_EPI0S24        0x00040808
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_CCP7           0x00040C05
+#define GPIO_PE3_EPI0S25        0x00040C08
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+
+#define GPIO_PE5_CCP5           0x00041401
+
+#define GPIO_PE6_C1O            0x00041802
+#define GPIO_PE6_U1CTS          0x00041809
+
+#define GPIO_PE7_U1DCD          0x00041C09
+
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_U1RTS          0x00050409
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_SSI1CLK        0x00050809
+
+#define GPIO_PF3_SSI1FSS        0x00050C09
+
+#define GPIO_PF4_CCP0           0x00051001
+#define GPIO_PF4_C0O            0x00051002
+#define GPIO_PF4_EPI0S12        0x00051008
+#define GPIO_PF4_SSI1RX         0x00051009
+
+#define GPIO_PF5_CCP2           0x00051401
+#define GPIO_PF5_C1O            0x00051402
+#define GPIO_PF5_EPI0S15        0x00051408
+#define GPIO_PF5_SSI1TX         0x00051409
+
+#define GPIO_PF6_CCP1           0x00051801
+#define GPIO_PF6_U1RTS          0x0005180A
+
+#define GPIO_PF7_CCP4           0x00051C01
+#define GPIO_PF7_EPI0S12        0x00051C08
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_I2C1SCL        0x00060003
+#define GPIO_PG0_EPI0S13        0x00060008
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_I2C1SDA        0x00060403
+#define GPIO_PG1_EPI0S14        0x00060408
+
+#define GPIO_PG4_CCP3           0x00061001
+#define GPIO_PG4_EPI0S15        0x00061008
+#define GPIO_PG4_U1RI           0x0006100A
+
+#define GPIO_PG5_CCP5           0x00061401
+#define GPIO_PG5_U1DTR          0x0006140A
+
+#define GPIO_PG6_U1RI           0x0006180A
+
+#define GPIO_PG7_CCP5           0x00061C08
+#define GPIO_PG7_EPI0S31        0x00061C09
+
+#define GPIO_PH0_CCP6           0x00070001
+#define GPIO_PH0_EPI0S6         0x00070008
+
+#define GPIO_PH1_CCP7           0x00070401
+#define GPIO_PH1_EPI0S7         0x00070408
+
+#define GPIO_PH2_C1O            0x00070802
+#define GPIO_PH2_EPI0S1         0x00070808
+
+#define GPIO_PH3_EPI0S0         0x00070C08
+
+#define GPIO_PH4_EPI0S10        0x00071008
+#define GPIO_PH4_SSI1CLK        0x0007100B
+
+#define GPIO_PH5_EPI0S11        0x00071408
+#define GPIO_PH5_SSI1FSS        0x0007140B
+
+#define GPIO_PH6_EPI0S26        0x00071808
+#define GPIO_PH6_SSI1RX         0x0007180B
+
+#define GPIO_PH7_EPI0S27        0x00071C08
+#define GPIO_PH7_SSI1TX         0x00071C0B
+
+#define GPIO_PJ0_EPI0S16        0x00080008
+#define GPIO_PJ0_I2C1SCL        0x0008000B
+
+#define GPIO_PJ1_EPI0S17        0x00080408
+#define GPIO_PJ1_I2C1SDA        0x0008040B
+
+#define GPIO_PJ2_EPI0S18        0x00080808
+#define GPIO_PJ2_CCP0           0x00080809
+
+#endif // PART_LM3S1811
+
+//*****************************************************************************
+//
+// LM3S1816 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1816
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+
+#define GPIO_PA4_SSI0RX         0x00001001
+
+#define GPIO_PA5_SSI0TX         0x00001401
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_CCP3           0x00001C07
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_U1RX           0x00011007
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_CCP5           0x00011806
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_CCP3           0x00021405
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_C1O            0x00021C07
+
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_CCP2           0x0003040A
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_CCP5           0x00030804
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_CCP0           0x00030C04
+
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_CCP2           0x00040805
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_CCP7           0x00040C05
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+
+#endif // PART_LM3S1816
+
+//*****************************************************************************
+//
+// LM3S1850 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1850
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOF
+#define C0O_PORT                GPIO_PORTF_BASE
+#define C0O_PIN                 GPIO_PIN_4
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1O_PERIPH              SYSCTL_PERIPH_GPIOE
+#define C1O_PORT                GPIO_PORTE_BASE
+#define C1O_PIN                 GPIO_PIN_6
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_5
+
+#define C2_MINUS_PERIPH         SYSCTL_PERIPH_GPIOC
+#define C2_MINUS_PORT           GPIO_PORTC_BASE
+#define C2_MINUS_PIN            GPIO_PIN_7
+
+#define C2_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C2_PLUS_PORT            GPIO_PORTC_BASE
+#define C2_PLUS_PIN             GPIO_PIN_6
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP1_PORT               GPIO_PORTA_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_1
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP3_PORT               GPIO_PORTD_BASE
+#define CCP3_PIN                GPIO_PIN_4
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP4_PORT               GPIO_PORTA_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP5_PORT               GPIO_PORTC_BASE
+#define CCP5_PIN                GPIO_PIN_4
+
+#define FAULT_PERIPH            SYSCTL_PERIPH_GPIOD
+#define FAULT_PORT              GPIO_PORTD_BASE
+#define FAULT_PIN               GPIO_PIN_6
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define IDX0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define IDX0_PORT               GPIO_PORTD_BASE
+#define IDX0_PIN                GPIO_PIN_7
+
+#define PHA0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PHA0_PORT               GPIO_PORTD_BASE
+#define PHA0_PIN                GPIO_PIN_1
+
+#define PHB0_PERIPH             SYSCTL_PERIPH_GPIOF
+#define PHB0_PORT               GPIO_PORTF_BASE
+#define PHB0_PIN                GPIO_PIN_0
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM0_PORT               GPIO_PORTD_BASE
+#define PWM0_PIN                GPIO_PIN_0
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOF
+#define PWM1_PORT               GPIO_PORTF_BASE
+#define PWM1_PIN                GPIO_PIN_1
+
+#define PWM2_PERIPH             SYSCTL_PERIPH_GPIOH
+#define PWM2_PORT               GPIO_PORTH_BASE
+#define PWM2_PIN                GPIO_PIN_0
+
+#define PWM3_PERIPH             SYSCTL_PERIPH_GPIOH
+#define PWM3_PORT               GPIO_PORTH_BASE
+#define PWM3_PIN                GPIO_PIN_1
+
+#define PWM4_PERIPH             SYSCTL_PERIPH_GPIOE
+#define PWM4_PORT               GPIO_PORTE_BASE
+#define PWM4_PIN                GPIO_PIN_0
+
+#define PWM5_PERIPH             SYSCTL_PERIPH_GPIOE
+#define PWM5_PORT               GPIO_PORTE_BASE
+#define PWM5_PIN                GPIO_PIN_1
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#endif // PART_LM3S1850
+
+//*****************************************************************************
+//
+// LM3S1911 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1911
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOF
+#define C0O_PORT                GPIO_PORTF_BASE
+#define C0O_PIN                 GPIO_PIN_4
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1O_PERIPH              SYSCTL_PERIPH_GPIOE
+#define C1O_PORT                GPIO_PORTE_BASE
+#define C1O_PIN                 GPIO_PIN_6
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_5
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP1_PORT               GPIO_PORTD_BASE
+#define CCP1_PIN                GPIO_PIN_7
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_1
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP3_PORT               GPIO_PORTC_BASE
+#define CCP3_PIN                GPIO_PIN_6
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP4_PORT               GPIO_PORTC_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP5_PORT               GPIO_PORTC_BASE
+#define CCP5_PIN                GPIO_PIN_4
+
+#define CCP6_PERIPH             SYSCTL_PERIPH_GPIOH
+#define CCP6_PORT               GPIO_PORTH_BASE
+#define CCP6_PIN                GPIO_PIN_0
+
+#define CCP7_PERIPH             SYSCTL_PERIPH_GPIOH
+#define CCP7_PORT               GPIO_PORTH_BASE
+#define CCP7_PIN                GPIO_PIN_1
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define I2C1SCL_PERIPH          SYSCTL_PERIPH_GPIOA
+#define I2C1SCL_PORT            GPIO_PORTA_BASE
+#define I2C1SCL_PIN             GPIO_PIN_6
+
+#define I2C1SDA_PERIPH          SYSCTL_PERIPH_GPIOA
+#define I2C1SDA_PORT            GPIO_PORTA_BASE
+#define I2C1SDA_PIN             GPIO_PIN_7
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SSI1CLK_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1CLK_PORT            GPIO_PORTE_BASE
+#define SSI1CLK_PIN             GPIO_PIN_0
+
+#define SSI1FSS_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1FSS_PORT            GPIO_PORTE_BASE
+#define SSI1FSS_PIN             GPIO_PIN_1
+
+#define SSI1RX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1RX_PORT             GPIO_PORTE_BASE
+#define SSI1RX_PIN              GPIO_PIN_2
+
+#define SSI1TX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1TX_PORT             GPIO_PORTE_BASE
+#define SSI1TX_PIN              GPIO_PIN_3
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#define U2RX_PERIPH             SYSCTL_PERIPH_GPIOG
+#define U2RX_PORT               GPIO_PORTG_BASE
+#define U2RX_PIN                GPIO_PIN_0
+
+#define U2TX_PERIPH             SYSCTL_PERIPH_GPIOG
+#define U2TX_PORT               GPIO_PORTG_BASE
+#define U2TX_PIN                GPIO_PIN_1
+
+#endif // PART_LM3S1911
+
+//*****************************************************************************
+//
+// LM3S1918 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1918
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOF
+#define C0O_PORT                GPIO_PORTF_BASE
+#define C0O_PIN                 GPIO_PIN_4
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1O_PERIPH              SYSCTL_PERIPH_GPIOF
+#define C1O_PORT                GPIO_PORTF_BASE
+#define C1O_PIN                 GPIO_PIN_5
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_5
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOF
+#define CCP1_PORT               GPIO_PORTF_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_1
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP3_PORT               GPIO_PORTC_BASE
+#define CCP3_PIN                GPIO_PIN_6
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP4_PORT               GPIO_PORTC_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP5_PORT               GPIO_PORTC_BASE
+#define CCP5_PIN                GPIO_PIN_4
+
+#define CCP6_PERIPH             SYSCTL_PERIPH_GPIOH
+#define CCP6_PORT               GPIO_PORTH_BASE
+#define CCP6_PIN                GPIO_PIN_0
+
+#define CCP7_PERIPH             SYSCTL_PERIPH_GPIOH
+#define CCP7_PORT               GPIO_PORTH_BASE
+#define CCP7_PIN                GPIO_PIN_1
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define I2C1SCL_PERIPH          SYSCTL_PERIPH_GPIOA
+#define I2C1SCL_PORT            GPIO_PORTA_BASE
+#define I2C1SCL_PIN             GPIO_PIN_6
+
+#define I2C1SDA_PERIPH          SYSCTL_PERIPH_GPIOA
+#define I2C1SDA_PORT            GPIO_PORTA_BASE
+#define I2C1SDA_PIN             GPIO_PIN_7
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SSI1CLK_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1CLK_PORT            GPIO_PORTE_BASE
+#define SSI1CLK_PIN             GPIO_PIN_0
+
+#define SSI1FSS_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1FSS_PORT            GPIO_PORTE_BASE
+#define SSI1FSS_PIN             GPIO_PIN_1
+
+#define SSI1RX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1RX_PORT             GPIO_PORTE_BASE
+#define SSI1RX_PIN              GPIO_PIN_2
+
+#define SSI1TX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1TX_PORT             GPIO_PORTE_BASE
+#define SSI1TX_PIN              GPIO_PIN_3
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#endif // PART_LM3S1918
+
+//*****************************************************************************
+//
+// LM3S1937 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1937
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOB
+#define C0O_PORT                GPIO_PORTB_BASE
+#define C0O_PIN                 GPIO_PIN_5
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP1_PORT               GPIO_PORTA_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_1
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP3_PORT               GPIO_PORTC_BASE
+#define CCP3_PIN                GPIO_PIN_6
+
+#define FAULT_PERIPH            SYSCTL_PERIPH_GPIOD
+#define FAULT_PORT              GPIO_PORTD_BASE
+#define FAULT_PIN               GPIO_PIN_6
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM0_PORT               GPIO_PORTD_BASE
+#define PWM0_PIN                GPIO_PIN_0
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM1_PORT               GPIO_PORTD_BASE
+#define PWM1_PIN                GPIO_PIN_1
+
+#define PWM2_PERIPH             SYSCTL_PERIPH_GPIOH
+#define PWM2_PORT               GPIO_PORTH_BASE
+#define PWM2_PIN                GPIO_PIN_0
+
+#define PWM3_PERIPH             SYSCTL_PERIPH_GPIOH
+#define PWM3_PORT               GPIO_PORTH_BASE
+#define PWM3_PIN                GPIO_PIN_1
+
+#define PWM4_PERIPH             SYSCTL_PERIPH_GPIOE
+#define PWM4_PORT               GPIO_PORTE_BASE
+#define PWM4_PIN                GPIO_PIN_0
+
+#define PWM5_PERIPH             SYSCTL_PERIPH_GPIOE
+#define PWM5_PORT               GPIO_PORTE_BASE
+#define PWM5_PIN                GPIO_PIN_1
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#endif // PART_LM3S1937
+
+//*****************************************************************************
+//
+// LM3S1958 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1958
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP1_PORT               GPIO_PORTB_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_1
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP3_PORT               GPIO_PORTC_BASE
+#define CCP3_PIN                GPIO_PIN_6
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP4_PORT               GPIO_PORTC_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP5_PORT               GPIO_PORTB_BASE
+#define CCP5_PIN                GPIO_PIN_5
+
+#define CCP6_PERIPH             SYSCTL_PERIPH_GPIOH
+#define CCP6_PORT               GPIO_PORTH_BASE
+#define CCP6_PIN                GPIO_PIN_0
+
+#define CCP7_PERIPH             SYSCTL_PERIPH_GPIOH
+#define CCP7_PORT               GPIO_PORTH_BASE
+#define CCP7_PIN                GPIO_PIN_1
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define I2C1SCL_PERIPH          SYSCTL_PERIPH_GPIOA
+#define I2C1SCL_PORT            GPIO_PORTA_BASE
+#define I2C1SCL_PIN             GPIO_PIN_6
+
+#define I2C1SDA_PERIPH          SYSCTL_PERIPH_GPIOA
+#define I2C1SDA_PORT            GPIO_PORTA_BASE
+#define I2C1SDA_PIN             GPIO_PIN_7
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SSI1CLK_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1CLK_PORT            GPIO_PORTE_BASE
+#define SSI1CLK_PIN             GPIO_PIN_0
+
+#define SSI1FSS_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1FSS_PORT            GPIO_PORTE_BASE
+#define SSI1FSS_PIN             GPIO_PIN_1
+
+#define SSI1RX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1RX_PORT             GPIO_PORTE_BASE
+#define SSI1RX_PIN              GPIO_PIN_2
+
+#define SSI1TX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1TX_PORT             GPIO_PORTE_BASE
+#define SSI1TX_PIN              GPIO_PIN_3
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#define U2RX_PERIPH             SYSCTL_PERIPH_GPIOG
+#define U2RX_PORT               GPIO_PORTG_BASE
+#define U2RX_PIN                GPIO_PIN_0
+
+#define U2TX_PERIPH             SYSCTL_PERIPH_GPIOG
+#define U2TX_PORT               GPIO_PORTG_BASE
+#define U2TX_PIN                GPIO_PIN_1
+
+#endif // PART_LM3S1958
+
+//*****************************************************************************
+//
+// LM3S1960 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1960
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOF
+#define C0O_PORT                GPIO_PORTF_BASE
+#define C0O_PIN                 GPIO_PIN_4
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1O_PERIPH              SYSCTL_PERIPH_GPIOF
+#define C1O_PORT                GPIO_PORTF_BASE
+#define C1O_PIN                 GPIO_PIN_5
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_5
+
+#define C2O_PERIPH              SYSCTL_PERIPH_GPIOF
+#define C2O_PORT                GPIO_PORTF_BASE
+#define C2O_PIN                 GPIO_PIN_6
+
+#define C2_MINUS_PERIPH         SYSCTL_PERIPH_GPIOC
+#define C2_MINUS_PORT           GPIO_PORTC_BASE
+#define C2_MINUS_PIN            GPIO_PIN_7
+
+#define C2_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C2_PLUS_PORT            GPIO_PORTC_BASE
+#define C2_PLUS_PIN             GPIO_PIN_6
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP0_PORT               GPIO_PORTD_BASE
+#define CCP0_PIN                GPIO_PIN_4
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP1_PORT               GPIO_PORTD_BASE
+#define CCP1_PIN                GPIO_PIN_7
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP2_PORT               GPIO_PORTD_BASE
+#define CCP2_PIN                GPIO_PIN_5
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOE
+#define CCP3_PORT               GPIO_PORTE_BASE
+#define CCP3_PIN                GPIO_PIN_4
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOF
+#define CCP4_PORT               GPIO_PORTF_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP5_PORT               GPIO_PORTC_BASE
+#define CCP5_PIN                GPIO_PIN_4
+
+#define CCP6_PERIPH             SYSCTL_PERIPH_GPIOH
+#define CCP6_PORT               GPIO_PORTH_BASE
+#define CCP6_PIN                GPIO_PIN_0
+
+#define CCP7_PERIPH             SYSCTL_PERIPH_GPIOH
+#define CCP7_PORT               GPIO_PORTH_BASE
+#define CCP7_PIN                GPIO_PIN_1
+
+#define FAULT_PERIPH            SYSCTL_PERIPH_GPIOD
+#define FAULT_PORT              GPIO_PORTD_BASE
+#define FAULT_PIN               GPIO_PIN_6
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define I2C1SCL_PERIPH          SYSCTL_PERIPH_GPIOA
+#define I2C1SCL_PORT            GPIO_PORTA_BASE
+#define I2C1SCL_PIN             GPIO_PIN_6
+
+#define I2C1SDA_PERIPH          SYSCTL_PERIPH_GPIOA
+#define I2C1SDA_PORT            GPIO_PORTA_BASE
+#define I2C1SDA_PIN             GPIO_PIN_7
+
+#define IDX0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define IDX0_PORT               GPIO_PORTD_BASE
+#define IDX0_PIN                GPIO_PIN_0
+
+#define IDX1_PERIPH             SYSCTL_PERIPH_GPIOH
+#define IDX1_PORT               GPIO_PORTH_BASE
+#define IDX1_PIN                GPIO_PIN_2
+
+#define PHA0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PHA0_PORT               GPIO_PORTD_BASE
+#define PHA0_PIN                GPIO_PIN_1
+
+#define PHA1_PERIPH             SYSCTL_PERIPH_GPIOG
+#define PHA1_PORT               GPIO_PORTG_BASE
+#define PHA1_PIN                GPIO_PIN_6
+
+#define PHB0_PERIPH             SYSCTL_PERIPH_GPIOH
+#define PHB0_PORT               GPIO_PORTH_BASE
+#define PHB0_PIN                GPIO_PIN_3
+
+#define PHB1_PERIPH             SYSCTL_PERIPH_GPIOG
+#define PHB1_PORT               GPIO_PORTG_BASE
+#define PHB1_PIN                GPIO_PIN_7
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOF
+#define PWM0_PORT               GPIO_PORTF_BASE
+#define PWM0_PIN                GPIO_PIN_0
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOF
+#define PWM1_PORT               GPIO_PORTF_BASE
+#define PWM1_PIN                GPIO_PIN_1
+
+#define PWM2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define PWM2_PORT               GPIO_PORTB_BASE
+#define PWM2_PIN                GPIO_PIN_0
+
+#define PWM3_PERIPH             SYSCTL_PERIPH_GPIOB
+#define PWM3_PORT               GPIO_PORTB_BASE
+#define PWM3_PIN                GPIO_PIN_1
+
+#define PWM4_PERIPH             SYSCTL_PERIPH_GPIOE
+#define PWM4_PORT               GPIO_PORTE_BASE
+#define PWM4_PIN                GPIO_PIN_6
+
+#define PWM5_PERIPH             SYSCTL_PERIPH_GPIOE
+#define PWM5_PORT               GPIO_PORTE_BASE
+#define PWM5_PIN                GPIO_PIN_7
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SSI1CLK_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1CLK_PORT            GPIO_PORTE_BASE
+#define SSI1CLK_PIN             GPIO_PIN_0
+
+#define SSI1FSS_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1FSS_PORT            GPIO_PORTE_BASE
+#define SSI1FSS_PIN             GPIO_PIN_1
+
+#define SSI1RX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1RX_PORT             GPIO_PORTE_BASE
+#define SSI1RX_PIN              GPIO_PIN_2
+
+#define SSI1TX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1TX_PORT             GPIO_PORTE_BASE
+#define SSI1TX_PIN              GPIO_PIN_3
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#define U2RX_PERIPH             SYSCTL_PERIPH_GPIOG
+#define U2RX_PORT               GPIO_PORTG_BASE
+#define U2RX_PIN                GPIO_PIN_0
+
+#define U2TX_PERIPH             SYSCTL_PERIPH_GPIOG
+#define U2TX_PORT               GPIO_PORTG_BASE
+#define U2TX_PIN                GPIO_PIN_1
+
+#endif // PART_LM3S1960
+
+//*****************************************************************************
+//
+// LM3S1968 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1968
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOF
+#define C0O_PORT                GPIO_PORTF_BASE
+#define C0O_PIN                 GPIO_PIN_4
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_5
+
+#define C2_MINUS_PERIPH         SYSCTL_PERIPH_GPIOC
+#define C2_MINUS_PORT           GPIO_PORTC_BASE
+#define C2_MINUS_PIN            GPIO_PIN_7
+
+#define C2_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C2_PLUS_PORT            GPIO_PORTC_BASE
+#define C2_PLUS_PIN             GPIO_PIN_6
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOF
+#define CCP1_PORT               GPIO_PORTF_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_1
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOG
+#define CCP3_PORT               GPIO_PORTG_BASE
+#define CCP3_PIN                GPIO_PIN_4
+
+#define FAULT_PERIPH            SYSCTL_PERIPH_GPIOH
+#define FAULT_PORT              GPIO_PORTH_BASE
+#define FAULT_PIN               GPIO_PIN_3
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define I2C1SCL_PERIPH          SYSCTL_PERIPH_GPIOA
+#define I2C1SCL_PORT            GPIO_PORTA_BASE
+#define I2C1SCL_PIN             GPIO_PIN_6
+
+#define I2C1SDA_PERIPH          SYSCTL_PERIPH_GPIOA
+#define I2C1SDA_PORT            GPIO_PORTA_BASE
+#define I2C1SDA_PIN             GPIO_PIN_7
+
+#define IDX0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define IDX0_PORT               GPIO_PORTD_BASE
+#define IDX0_PIN                GPIO_PIN_0
+
+#define IDX1_PERIPH             SYSCTL_PERIPH_GPIOF
+#define IDX1_PORT               GPIO_PORTF_BASE
+#define IDX1_PIN                GPIO_PIN_1
+
+#define PHA0_PERIPH             SYSCTL_PERIPH_GPIOC
+#define PHA0_PORT               GPIO_PORTC_BASE
+#define PHA0_PIN                GPIO_PIN_4
+
+#define PHA1_PERIPH             SYSCTL_PERIPH_GPIOG
+#define PHA1_PORT               GPIO_PORTG_BASE
+#define PHA1_PIN                GPIO_PIN_6
+
+#define PHB0_PERIPH             SYSCTL_PERIPH_GPIOF
+#define PHB0_PORT               GPIO_PORTF_BASE
+#define PHB0_PIN                GPIO_PIN_0
+
+#define PHB1_PERIPH             SYSCTL_PERIPH_GPIOG
+#define PHB1_PORT               GPIO_PORTG_BASE
+#define PHB1_PIN                GPIO_PIN_7
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOG
+#define PWM0_PORT               GPIO_PORTG_BASE
+#define PWM0_PIN                GPIO_PIN_2
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM1_PORT               GPIO_PORTD_BASE
+#define PWM1_PIN                GPIO_PIN_1
+
+#define PWM2_PERIPH             SYSCTL_PERIPH_GPIOH
+#define PWM2_PORT               GPIO_PORTH_BASE
+#define PWM2_PIN                GPIO_PIN_0
+
+#define PWM3_PERIPH             SYSCTL_PERIPH_GPIOH
+#define PWM3_PORT               GPIO_PORTH_BASE
+#define PWM3_PIN                GPIO_PIN_1
+
+#define PWM4_PERIPH             SYSCTL_PERIPH_GPIOF
+#define PWM4_PORT               GPIO_PORTF_BASE
+#define PWM4_PIN                GPIO_PIN_2
+
+#define PWM5_PERIPH             SYSCTL_PERIPH_GPIOF
+#define PWM5_PORT               GPIO_PORTF_BASE
+#define PWM5_PIN                GPIO_PIN_3
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SSI1CLK_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1CLK_PORT            GPIO_PORTE_BASE
+#define SSI1CLK_PIN             GPIO_PIN_0
+
+#define SSI1FSS_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1FSS_PORT            GPIO_PORTE_BASE
+#define SSI1FSS_PIN             GPIO_PIN_1
+
+#define SSI1RX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1RX_PORT             GPIO_PORTE_BASE
+#define SSI1RX_PIN              GPIO_PIN_2
+
+#define SSI1TX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1TX_PORT             GPIO_PORTE_BASE
+#define SSI1TX_PIN              GPIO_PIN_3
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#define U2RX_PERIPH             SYSCTL_PERIPH_GPIOG
+#define U2RX_PORT               GPIO_PORTG_BASE
+#define U2RX_PIN                GPIO_PIN_0
+
+#define U2TX_PERIPH             SYSCTL_PERIPH_GPIOG
+#define U2TX_PORT               GPIO_PORTG_BASE
+#define U2TX_PIN                GPIO_PIN_1
+
+#endif // PART_LM3S1968
+
+//*****************************************************************************
+//
+// LM3S1B21 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1B21
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+
+#define GPIO_PA4_SSI0RX         0x00001001
+
+#define GPIO_PA5_SSI0TX         0x00001401
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_U1CTS          0x00001809
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_U1DCD          0x00001C09
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_U1RX           0x00011007
+#define GPIO_PB4_EPI0S23        0x00011008
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+#define GPIO_PB5_EPI0S22        0x00011408
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_CCP5           0x00011806
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_EPI0S2         0x00021008
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_CCP3           0x00021405
+#define GPIO_PC5_EPI0S3         0x00021408
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+#define GPIO_PC6_EPI0S4         0x00021808
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_C1O            0x00021C07
+#define GPIO_PC7_EPI0S5         0x00021C08
+
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+#define GPIO_PD0_U1CTS          0x00030009
+
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_U1DCD          0x00030409
+#define GPIO_PD1_CCP2           0x0003040A
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_CCP5           0x00030804
+#define GPIO_PD2_EPI0S20        0x00030808
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_CCP0           0x00030C04
+#define GPIO_PD3_EPI0S21        0x00030C08
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+#define GPIO_PD4_U1RI           0x00031009
+#define GPIO_PD4_EPI0S19        0x0003100A
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_U2RX           0x00031409
+#define GPIO_PD5_EPI0S28        0x0003140A
+
+#define GPIO_PD6_U2TX           0x00031809
+#define GPIO_PD6_EPI0S29        0x0003180A
+
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+#define GPIO_PD7_U1DTR          0x00031C09
+#define GPIO_PD7_EPI0S30        0x00031C0A
+
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+#define GPIO_PE0_EPI0S8         0x00040008
+
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+#define GPIO_PE1_EPI0S9         0x00040408
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_CCP2           0x00040805
+#define GPIO_PE2_EPI0S24        0x00040808
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_CCP7           0x00040C05
+#define GPIO_PE3_EPI0S25        0x00040C08
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+
+#define GPIO_PE5_CCP5           0x00041401
+
+#define GPIO_PE6_C1O            0x00041802
+#define GPIO_PE6_U1CTS          0x00041809
+
+#define GPIO_PE7_U1DCD          0x00041C09
+
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_U1RTS          0x00050409
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_SSI1CLK        0x00050809
+
+#define GPIO_PF3_SSI1FSS        0x00050C09
+
+#define GPIO_PF4_CCP0           0x00051001
+#define GPIO_PF4_C0O            0x00051002
+#define GPIO_PF4_EPI0S12        0x00051008
+#define GPIO_PF4_SSI1RX         0x00051009
+
+#define GPIO_PF5_CCP2           0x00051401
+#define GPIO_PF5_C1O            0x00051402
+#define GPIO_PF5_EPI0S15        0x00051408
+#define GPIO_PF5_SSI1TX         0x00051409
+
+#define GPIO_PF6_CCP1           0x00051801
+#define GPIO_PF6_U1RTS          0x0005180A
+
+#define GPIO_PF7_CCP4           0x00051C01
+#define GPIO_PF7_EPI0S12        0x00051C08
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_I2C1SCL        0x00060003
+#define GPIO_PG0_EPI0S13        0x00060008
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_I2C1SDA        0x00060403
+#define GPIO_PG1_EPI0S14        0x00060408
+
+#define GPIO_PG4_CCP3           0x00061001
+#define GPIO_PG4_EPI0S15        0x00061008
+#define GPIO_PG4_U1RI           0x0006100A
+
+#define GPIO_PG5_CCP5           0x00061401
+#define GPIO_PG5_U1DTR          0x0006140A
+
+#define GPIO_PG6_U1RI           0x0006180A
+
+#define GPIO_PG7_CCP5           0x00061C08
+#define GPIO_PG7_EPI0S31        0x00061C09
+
+#define GPIO_PH0_CCP6           0x00070001
+#define GPIO_PH0_EPI0S6         0x00070008
+
+#define GPIO_PH1_CCP7           0x00070401
+#define GPIO_PH1_EPI0S7         0x00070408
+
+#define GPIO_PH2_C1O            0x00070802
+#define GPIO_PH2_EPI0S1         0x00070808
+
+#define GPIO_PH3_EPI0S0         0x00070C08
+
+#define GPIO_PH4_EPI0S10        0x00071008
+#define GPIO_PH4_SSI1CLK        0x0007100B
+
+#define GPIO_PH5_EPI0S11        0x00071408
+#define GPIO_PH5_SSI1FSS        0x0007140B
+
+#define GPIO_PH6_EPI0S26        0x00071808
+#define GPIO_PH6_SSI1RX         0x0007180B
+
+#define GPIO_PH7_EPI0S27        0x00071C08
+#define GPIO_PH7_SSI1TX         0x00071C0B
+
+#define GPIO_PJ0_EPI0S16        0x00080008
+#define GPIO_PJ0_I2C1SCL        0x0008000B
+
+#define GPIO_PJ1_EPI0S17        0x00080408
+#define GPIO_PJ1_I2C1SDA        0x0008040B
+
+#define GPIO_PJ2_EPI0S18        0x00080808
+#define GPIO_PJ2_CCP0           0x00080809
+
+#endif // PART_LM3S1B21
+
+//*****************************************************************************
+//
+// LM3S1C21 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1C21
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+
+#define GPIO_PA4_SSI0RX         0x00001001
+
+#define GPIO_PA5_SSI0TX         0x00001401
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_U1CTS          0x00001809
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_U1DCD          0x00001C09
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_U1RX           0x00011007
+#define GPIO_PB4_EPI0S23        0x00011008
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+#define GPIO_PB5_EPI0S22        0x00011408
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_CCP5           0x00011806
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_EPI0S2         0x00021008
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_CCP3           0x00021405
+#define GPIO_PC5_EPI0S3         0x00021408
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+#define GPIO_PC6_EPI0S4         0x00021808
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_C1O            0x00021C07
+#define GPIO_PC7_EPI0S5         0x00021C08
+
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+#define GPIO_PD0_U1CTS          0x00030009
+
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_U1DCD          0x00030409
+#define GPIO_PD1_CCP2           0x0003040A
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_CCP5           0x00030804
+#define GPIO_PD2_EPI0S20        0x00030808
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_CCP0           0x00030C04
+#define GPIO_PD3_EPI0S21        0x00030C08
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+#define GPIO_PD4_U1RI           0x00031009
+#define GPIO_PD4_EPI0S19        0x0003100A
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_U2RX           0x00031409
+#define GPIO_PD5_EPI0S28        0x0003140A
+
+#define GPIO_PD6_U2TX           0x00031809
+#define GPIO_PD6_EPI0S29        0x0003180A
+
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+#define GPIO_PD7_U1DTR          0x00031C09
+#define GPIO_PD7_EPI0S30        0x00031C0A
+
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+#define GPIO_PE0_EPI0S8         0x00040008
+
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+#define GPIO_PE1_EPI0S9         0x00040408
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_CCP2           0x00040805
+#define GPIO_PE2_EPI0S24        0x00040808
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_CCP7           0x00040C05
+#define GPIO_PE3_EPI0S25        0x00040C08
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+
+#define GPIO_PE5_CCP5           0x00041401
+
+#define GPIO_PE6_C1O            0x00041802
+#define GPIO_PE6_U1CTS          0x00041809
+
+#define GPIO_PE7_U1DCD          0x00041C09
+
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_U1RTS          0x00050409
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_SSI1CLK        0x00050809
+
+#define GPIO_PF3_SSI1FSS        0x00050C09
+
+#define GPIO_PF4_CCP0           0x00051001
+#define GPIO_PF4_C0O            0x00051002
+#define GPIO_PF4_EPI0S12        0x00051008
+#define GPIO_PF4_SSI1RX         0x00051009
+
+#define GPIO_PF5_CCP2           0x00051401
+#define GPIO_PF5_C1O            0x00051402
+#define GPIO_PF5_EPI0S15        0x00051408
+#define GPIO_PF5_SSI1TX         0x00051409
+
+#define GPIO_PF6_CCP1           0x00051801
+#define GPIO_PF6_U1RTS          0x0005180A
+
+#define GPIO_PF7_CCP4           0x00051C01
+#define GPIO_PF7_EPI0S12        0x00051C08
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_I2C1SCL        0x00060003
+#define GPIO_PG0_EPI0S13        0x00060008
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_I2C1SDA        0x00060403
+#define GPIO_PG1_EPI0S14        0x00060408
+
+#define GPIO_PG4_CCP3           0x00061001
+#define GPIO_PG4_EPI0S15        0x00061008
+#define GPIO_PG4_U1RI           0x0006100A
+
+#define GPIO_PG5_CCP5           0x00061401
+#define GPIO_PG5_U1DTR          0x0006140A
+
+#define GPIO_PG6_U1RI           0x0006180A
+
+#define GPIO_PG7_CCP5           0x00061C08
+#define GPIO_PG7_EPI0S31        0x00061C09
+
+#define GPIO_PH0_CCP6           0x00070001
+#define GPIO_PH0_EPI0S6         0x00070008
+
+#define GPIO_PH1_CCP7           0x00070401
+#define GPIO_PH1_EPI0S7         0x00070408
+
+#define GPIO_PH2_C1O            0x00070802
+#define GPIO_PH2_EPI0S1         0x00070808
+
+#define GPIO_PH3_EPI0S0         0x00070C08
+
+#define GPIO_PH4_EPI0S10        0x00071008
+#define GPIO_PH4_SSI1CLK        0x0007100B
+
+#define GPIO_PH5_EPI0S11        0x00071408
+#define GPIO_PH5_SSI1FSS        0x0007140B
+
+#define GPIO_PH6_EPI0S26        0x00071808
+#define GPIO_PH6_SSI1RX         0x0007180B
+
+#define GPIO_PH7_EPI0S27        0x00071C08
+#define GPIO_PH7_SSI1TX         0x00071C0B
+
+#define GPIO_PJ0_EPI0S16        0x00080008
+#define GPIO_PJ0_I2C1SCL        0x0008000B
+
+#define GPIO_PJ1_EPI0S17        0x00080408
+#define GPIO_PJ1_I2C1SDA        0x0008040B
+
+#define GPIO_PJ2_EPI0S18        0x00080808
+#define GPIO_PJ2_CCP0           0x00080809
+
+#endif // PART_LM3S1C21
+
+//*****************************************************************************
+//
+// LM3S1C26 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1C26
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+
+#define GPIO_PA4_SSI0RX         0x00001001
+
+#define GPIO_PA5_SSI0TX         0x00001401
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_CCP3           0x00001C07
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_U1RX           0x00011007
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_CCP5           0x00011806
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_CCP3           0x00021405
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_C1O            0x00021C07
+
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_CCP2           0x0003040A
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_CCP5           0x00030804
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_CCP0           0x00030C04
+
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_CCP2           0x00040805
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_CCP7           0x00040C05
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+
+#endif // PART_LM3S1C26
+
+//*****************************************************************************
+//
+// LM3S1C58 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1C58
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+
+#define GPIO_PA4_SSI0RX         0x00001001
+
+#define GPIO_PA5_SSI0TX         0x00001401
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_CCP3           0x00001C07
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_U1RX           0x00011007
+
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_CCP5           0x00011806
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_CCP3           0x00021405
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_CCP2           0x0003040A
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_CCP5           0x00030804
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_CCP0           0x00030C04
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_U2RX           0x00031409
+
+#define GPIO_PD6_U2TX           0x00031809
+
+#define GPIO_PD7_CCP1           0x00031C03
+
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_CCP2           0x00040805
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_CCP7           0x00040C05
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+
+#define GPIO_PE5_CCP5           0x00041401
+
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_SSI1CLK        0x00050809
+
+#define GPIO_PF3_SSI1FSS        0x00050C09
+
+#define GPIO_PF4_CCP0           0x00051001
+#define GPIO_PF4_SSI1RX         0x00051009
+
+#define GPIO_PF5_CCP2           0x00051401
+#define GPIO_PF5_SSI1TX         0x00051409
+
+#define GPIO_PF6_CCP1           0x00051801
+
+#define GPIO_PF7_CCP4           0x00051C01
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_I2C1SCL        0x00060003
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_I2C1SDA        0x00060403
+
+#define GPIO_PG4_CCP3           0x00061001
+
+#define GPIO_PG5_CCP5           0x00061401
+
+#define GPIO_PG7_CCP5           0x00061C08
+
+#define GPIO_PH0_CCP6           0x00070001
+
+#define GPIO_PH1_CCP7           0x00070401
+
+#endif // PART_LM3S1C58
+
+//*****************************************************************************
+//
+// LM3S1D21 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1D21
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+
+#define GPIO_PA4_SSI0RX         0x00001001
+
+#define GPIO_PA5_SSI0TX         0x00001401
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_U1CTS          0x00001809
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_U1DCD          0x00001C09
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_U1RX           0x00011007
+#define GPIO_PB4_EPI0S23        0x00011008
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+#define GPIO_PB5_EPI0S22        0x00011408
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_CCP5           0x00011806
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_EPI0S2         0x00021008
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_CCP3           0x00021405
+#define GPIO_PC5_EPI0S3         0x00021408
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+#define GPIO_PC6_EPI0S4         0x00021808
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_C1O            0x00021C07
+#define GPIO_PC7_EPI0S5         0x00021C08
+
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+#define GPIO_PD0_U1CTS          0x00030009
+
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_U1DCD          0x00030409
+#define GPIO_PD1_CCP2           0x0003040A
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_CCP5           0x00030804
+#define GPIO_PD2_EPI0S20        0x00030808
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_CCP0           0x00030C04
+#define GPIO_PD3_EPI0S21        0x00030C08
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+#define GPIO_PD4_U1RI           0x00031009
+#define GPIO_PD4_EPI0S19        0x0003100A
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_U2RX           0x00031409
+#define GPIO_PD5_EPI0S28        0x0003140A
+
+#define GPIO_PD6_U2TX           0x00031809
+#define GPIO_PD6_EPI0S29        0x0003180A
+
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+#define GPIO_PD7_U1DTR          0x00031C09
+#define GPIO_PD7_EPI0S30        0x00031C0A
+
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+#define GPIO_PE0_EPI0S8         0x00040008
+
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+#define GPIO_PE1_EPI0S9         0x00040408
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_CCP2           0x00040805
+#define GPIO_PE2_EPI0S24        0x00040808
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_CCP7           0x00040C05
+#define GPIO_PE3_EPI0S25        0x00040C08
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+
+#define GPIO_PE5_CCP5           0x00041401
+
+#define GPIO_PE6_C1O            0x00041802
+#define GPIO_PE6_U1CTS          0x00041809
+
+#define GPIO_PE7_U1DCD          0x00041C09
+
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_U1RTS          0x00050409
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_SSI1CLK        0x00050809
+
+#define GPIO_PF3_SSI1FSS        0x00050C09
+
+#define GPIO_PF4_CCP0           0x00051001
+#define GPIO_PF4_C0O            0x00051002
+#define GPIO_PF4_EPI0S12        0x00051008
+#define GPIO_PF4_SSI1RX         0x00051009
+
+#define GPIO_PF5_CCP2           0x00051401
+#define GPIO_PF5_C1O            0x00051402
+#define GPIO_PF5_EPI0S15        0x00051408
+#define GPIO_PF5_SSI1TX         0x00051409
+
+#define GPIO_PF6_CCP1           0x00051801
+#define GPIO_PF6_U1RTS          0x0005180A
+
+#define GPIO_PF7_CCP4           0x00051C01
+#define GPIO_PF7_EPI0S12        0x00051C08
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_I2C1SCL        0x00060003
+#define GPIO_PG0_EPI0S13        0x00060008
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_I2C1SDA        0x00060403
+#define GPIO_PG1_EPI0S14        0x00060408
+
+#define GPIO_PG4_CCP3           0x00061001
+#define GPIO_PG4_EPI0S15        0x00061008
+#define GPIO_PG4_U1RI           0x0006100A
+
+#define GPIO_PG5_CCP5           0x00061401
+#define GPIO_PG5_U1DTR          0x0006140A
+
+#define GPIO_PG6_U1RI           0x0006180A
+
+#define GPIO_PG7_CCP5           0x00061C08
+#define GPIO_PG7_EPI0S31        0x00061C09
+
+#define GPIO_PH0_CCP6           0x00070001
+#define GPIO_PH0_EPI0S6         0x00070008
+
+#define GPIO_PH1_CCP7           0x00070401
+#define GPIO_PH1_EPI0S7         0x00070408
+
+#define GPIO_PH2_C1O            0x00070802
+#define GPIO_PH2_EPI0S1         0x00070808
+
+#define GPIO_PH3_EPI0S0         0x00070C08
+
+#define GPIO_PH4_EPI0S10        0x00071008
+#define GPIO_PH4_SSI1CLK        0x0007100B
+
+#define GPIO_PH5_EPI0S11        0x00071408
+#define GPIO_PH5_SSI1FSS        0x0007140B
+
+#define GPIO_PH6_EPI0S26        0x00071808
+#define GPIO_PH6_SSI1RX         0x0007180B
+
+#define GPIO_PH7_EPI0S27        0x00071C08
+#define GPIO_PH7_SSI1TX         0x00071C0B
+
+#define GPIO_PJ0_EPI0S16        0x00080008
+#define GPIO_PJ0_I2C1SCL        0x0008000B
+
+#define GPIO_PJ1_EPI0S17        0x00080408
+#define GPIO_PJ1_I2C1SDA        0x0008040B
+
+#define GPIO_PJ2_EPI0S18        0x00080808
+#define GPIO_PJ2_CCP0           0x00080809
+
+#endif // PART_LM3S1D21
+
+//*****************************************************************************
+//
+// LM3S1D26 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1D26
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+
+#define GPIO_PA4_SSI0RX         0x00001001
+
+#define GPIO_PA5_SSI0TX         0x00001401
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_CCP3           0x00001C07
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_U1RX           0x00011007
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_CCP5           0x00011806
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_CCP3           0x00021405
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_C1O            0x00021C07
+
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_CCP2           0x0003040A
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_CCP5           0x00030804
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_CCP0           0x00030C04
+
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_CCP2           0x00040805
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_CCP7           0x00040C05
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+
+#endif // PART_LM3S1D26
+
+//*****************************************************************************
+//
+// LM3S1F11 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1F11
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+
+#define GPIO_PA4_SSI0RX         0x00001001
+
+#define GPIO_PA5_SSI0TX         0x00001401
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_U1CTS          0x00001809
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_U1DCD          0x00001C09
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_U1RX           0x00011007
+#define GPIO_PB4_EPI0S23        0x00011008
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+#define GPIO_PB5_EPI0S22        0x00011408
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_CCP5           0x00011806
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_EPI0S2         0x00021008
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_CCP3           0x00021405
+#define GPIO_PC5_EPI0S3         0x00021408
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+#define GPIO_PC6_EPI0S4         0x00021808
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_C1O            0x00021C07
+#define GPIO_PC7_EPI0S5         0x00021C08
+
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+#define GPIO_PD0_U1CTS          0x00030009
+
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_U1DCD          0x00030409
+#define GPIO_PD1_CCP2           0x0003040A
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_CCP5           0x00030804
+#define GPIO_PD2_EPI0S20        0x00030808
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_CCP0           0x00030C04
+#define GPIO_PD3_EPI0S21        0x00030C08
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+#define GPIO_PD4_U1RI           0x00031009
+#define GPIO_PD4_EPI0S19        0x0003100A
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_U2RX           0x00031409
+#define GPIO_PD5_EPI0S28        0x0003140A
+
+#define GPIO_PD6_U2TX           0x00031809
+#define GPIO_PD6_EPI0S29        0x0003180A
+
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+#define GPIO_PD7_U1DTR          0x00031C09
+#define GPIO_PD7_EPI0S30        0x00031C0A
+
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+#define GPIO_PE0_EPI0S8         0x00040008
+
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+#define GPIO_PE1_EPI0S9         0x00040408
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_CCP2           0x00040805
+#define GPIO_PE2_EPI0S24        0x00040808
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_CCP7           0x00040C05
+#define GPIO_PE3_EPI0S25        0x00040C08
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+
+#define GPIO_PE5_CCP5           0x00041401
+
+#define GPIO_PE6_C1O            0x00041802
+#define GPIO_PE6_U1CTS          0x00041809
+
+#define GPIO_PE7_U1DCD          0x00041C09
+
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_U1RTS          0x00050409
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_SSI1CLK        0x00050809
+
+#define GPIO_PF3_SSI1FSS        0x00050C09
+
+#define GPIO_PF4_CCP0           0x00051001
+#define GPIO_PF4_C0O            0x00051002
+#define GPIO_PF4_EPI0S12        0x00051008
+#define GPIO_PF4_SSI1RX         0x00051009
+
+#define GPIO_PF5_CCP2           0x00051401
+#define GPIO_PF5_C1O            0x00051402
+#define GPIO_PF5_EPI0S15        0x00051408
+#define GPIO_PF5_SSI1TX         0x00051409
+
+#define GPIO_PF6_CCP1           0x00051801
+#define GPIO_PF6_U1RTS          0x0005180A
+
+#define GPIO_PF7_CCP4           0x00051C01
+#define GPIO_PF7_EPI0S12        0x00051C08
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_I2C1SCL        0x00060003
+#define GPIO_PG0_EPI0S13        0x00060008
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_I2C1SDA        0x00060403
+#define GPIO_PG1_EPI0S14        0x00060408
+
+#define GPIO_PG4_CCP3           0x00061001
+#define GPIO_PG4_EPI0S15        0x00061008
+#define GPIO_PG4_U1RI           0x0006100A
+
+#define GPIO_PG5_CCP5           0x00061401
+#define GPIO_PG5_U1DTR          0x0006140A
+
+#define GPIO_PG6_U1RI           0x0006180A
+
+#define GPIO_PG7_CCP5           0x00061C08
+#define GPIO_PG7_EPI0S31        0x00061C09
+
+#define GPIO_PH0_CCP6           0x00070001
+#define GPIO_PH0_EPI0S6         0x00070008
+
+#define GPIO_PH1_CCP7           0x00070401
+#define GPIO_PH1_EPI0S7         0x00070408
+
+#define GPIO_PH2_C1O            0x00070802
+#define GPIO_PH2_EPI0S1         0x00070808
+
+#define GPIO_PH3_EPI0S0         0x00070C08
+
+#define GPIO_PH4_EPI0S10        0x00071008
+#define GPIO_PH4_SSI1CLK        0x0007100B
+
+#define GPIO_PH5_EPI0S11        0x00071408
+#define GPIO_PH5_SSI1FSS        0x0007140B
+
+#define GPIO_PH6_EPI0S26        0x00071808
+#define GPIO_PH6_SSI1RX         0x0007180B
+
+#define GPIO_PH7_EPI0S27        0x00071C08
+#define GPIO_PH7_SSI1TX         0x00071C0B
+
+#define GPIO_PJ0_EPI0S16        0x00080008
+#define GPIO_PJ0_I2C1SCL        0x0008000B
+
+#define GPIO_PJ1_EPI0S17        0x00080408
+#define GPIO_PJ1_I2C1SDA        0x0008040B
+
+#define GPIO_PJ2_EPI0S18        0x00080808
+#define GPIO_PJ2_CCP0           0x00080809
+
+#endif // PART_LM3S1F11
+
+//*****************************************************************************
+//
+// LM3S1F16 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1F16
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+
+#define GPIO_PA4_SSI0RX         0x00001001
+
+#define GPIO_PA5_SSI0TX         0x00001401
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_CCP3           0x00001C07
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_U1RX           0x00011007
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_CCP5           0x00011806
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_CCP3           0x00021405
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_C1O            0x00021C07
+
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_CCP2           0x0003040A
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_CCP5           0x00030804
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_CCP0           0x00030C04
+
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_CCP2           0x00040805
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_CCP7           0x00040C05
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+
+#endif // PART_LM3S1F16
+
+//*****************************************************************************
+//
+// LM3S1G21 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1G21
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+
+#define GPIO_PA4_SSI0RX         0x00001001
+
+#define GPIO_PA5_SSI0TX         0x00001401
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_U1CTS          0x00001809
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_U1DCD          0x00001C09
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_U1RX           0x00011007
+#define GPIO_PB4_EPI0S23        0x00011008
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+#define GPIO_PB5_EPI0S22        0x00011408
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_CCP5           0x00011806
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_EPI0S2         0x00021008
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_CCP3           0x00021405
+#define GPIO_PC5_EPI0S3         0x00021408
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+#define GPIO_PC6_EPI0S4         0x00021808
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_C1O            0x00021C07
+#define GPIO_PC7_EPI0S5         0x00021C08
+
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+#define GPIO_PD0_U1CTS          0x00030009
+
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_U1DCD          0x00030409
+#define GPIO_PD1_CCP2           0x0003040A
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_CCP5           0x00030804
+#define GPIO_PD2_EPI0S20        0x00030808
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_CCP0           0x00030C04
+#define GPIO_PD3_EPI0S21        0x00030C08
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+#define GPIO_PD4_U1RI           0x00031009
+#define GPIO_PD4_EPI0S19        0x0003100A
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_U2RX           0x00031409
+#define GPIO_PD5_EPI0S28        0x0003140A
+
+#define GPIO_PD6_U2TX           0x00031809
+#define GPIO_PD6_EPI0S29        0x0003180A
+
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+#define GPIO_PD7_U1DTR          0x00031C09
+#define GPIO_PD7_EPI0S30        0x00031C0A
+
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+#define GPIO_PE0_EPI0S8         0x00040008
+
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+#define GPIO_PE1_EPI0S9         0x00040408
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_CCP2           0x00040805
+#define GPIO_PE2_EPI0S24        0x00040808
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_CCP7           0x00040C05
+#define GPIO_PE3_EPI0S25        0x00040C08
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+
+#define GPIO_PE5_CCP5           0x00041401
+
+#define GPIO_PE6_C1O            0x00041802
+#define GPIO_PE6_U1CTS          0x00041809
+
+#define GPIO_PE7_U1DCD          0x00041C09
+
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_U1RTS          0x00050409
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_SSI1CLK        0x00050809
+
+#define GPIO_PF3_SSI1FSS        0x00050C09
+
+#define GPIO_PF4_CCP0           0x00051001
+#define GPIO_PF4_C0O            0x00051002
+#define GPIO_PF4_EPI0S12        0x00051008
+#define GPIO_PF4_SSI1RX         0x00051009
+
+#define GPIO_PF5_CCP2           0x00051401
+#define GPIO_PF5_C1O            0x00051402
+#define GPIO_PF5_EPI0S15        0x00051408
+#define GPIO_PF5_SSI1TX         0x00051409
+
+#define GPIO_PF6_CCP1           0x00051801
+#define GPIO_PF6_U1RTS          0x0005180A
+
+#define GPIO_PF7_CCP4           0x00051C01
+#define GPIO_PF7_EPI0S12        0x00051C08
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_I2C1SCL        0x00060003
+#define GPIO_PG0_EPI0S13        0x00060008
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_I2C1SDA        0x00060403
+#define GPIO_PG1_EPI0S14        0x00060408
+
+#define GPIO_PG4_CCP3           0x00061001
+#define GPIO_PG4_EPI0S15        0x00061008
+#define GPIO_PG4_U1RI           0x0006100A
+
+#define GPIO_PG5_CCP5           0x00061401
+#define GPIO_PG5_U1DTR          0x0006140A
+
+#define GPIO_PG6_U1RI           0x0006180A
+
+#define GPIO_PG7_CCP5           0x00061C08
+#define GPIO_PG7_EPI0S31        0x00061C09
+
+#define GPIO_PH0_CCP6           0x00070001
+#define GPIO_PH0_EPI0S6         0x00070008
+
+#define GPIO_PH1_CCP7           0x00070401
+#define GPIO_PH1_EPI0S7         0x00070408
+
+#define GPIO_PH2_C1O            0x00070802
+#define GPIO_PH2_EPI0S1         0x00070808
+
+#define GPIO_PH3_EPI0S0         0x00070C08
+
+#define GPIO_PH4_EPI0S10        0x00071008
+#define GPIO_PH4_SSI1CLK        0x0007100B
+
+#define GPIO_PH5_EPI0S11        0x00071408
+#define GPIO_PH5_SSI1FSS        0x0007140B
+
+#define GPIO_PH6_EPI0S26        0x00071808
+#define GPIO_PH6_SSI1RX         0x0007180B
+
+#define GPIO_PH7_EPI0S27        0x00071C08
+#define GPIO_PH7_SSI1TX         0x00071C0B
+
+#define GPIO_PJ0_EPI0S16        0x00080008
+#define GPIO_PJ0_I2C1SCL        0x0008000B
+
+#define GPIO_PJ1_EPI0S17        0x00080408
+#define GPIO_PJ1_I2C1SDA        0x0008040B
+
+#define GPIO_PJ2_EPI0S18        0x00080808
+#define GPIO_PJ2_CCP0           0x00080809
+
+#endif // PART_LM3S1G21
+
+//*****************************************************************************
+//
+// LM3S1G58 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1G58
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+
+#define GPIO_PA4_SSI0RX         0x00001001
+
+#define GPIO_PA5_SSI0TX         0x00001401
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_CCP3           0x00001C07
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_U1RX           0x00011007
+
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_CCP5           0x00011806
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_CCP3           0x00021405
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_CCP2           0x0003040A
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_CCP5           0x00030804
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_CCP0           0x00030C04
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_U2RX           0x00031409
+
+#define GPIO_PD6_U2TX           0x00031809
+
+#define GPIO_PD7_CCP1           0x00031C03
+
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_CCP2           0x00040805
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_CCP7           0x00040C05
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+
+#define GPIO_PE5_CCP5           0x00041401
+
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_SSI1CLK        0x00050809
+
+#define GPIO_PF3_SSI1FSS        0x00050C09
+
+#define GPIO_PF4_CCP0           0x00051001
+#define GPIO_PF4_SSI1RX         0x00051009
+
+#define GPIO_PF5_CCP2           0x00051401
+#define GPIO_PF5_SSI1TX         0x00051409
+
+#define GPIO_PF6_CCP1           0x00051801
+
+#define GPIO_PF7_CCP4           0x00051C01
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_I2C1SCL        0x00060003
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_I2C1SDA        0x00060403
+
+#define GPIO_PG4_CCP3           0x00061001
+
+#define GPIO_PG5_CCP5           0x00061401
+
+#define GPIO_PG7_CCP5           0x00061C08
+
+#define GPIO_PH0_CCP6           0x00070001
+
+#define GPIO_PH1_CCP7           0x00070401
+
+#endif // PART_LM3S1G58
+
+//*****************************************************************************
+//
+// LM3S1H11 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1H11
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+
+#define GPIO_PA4_SSI0RX         0x00001001
+
+#define GPIO_PA5_SSI0TX         0x00001401
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_U1CTS          0x00001809
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_U1DCD          0x00001C09
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_U1RX           0x00011007
+#define GPIO_PB4_EPI0S23        0x00011008
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+#define GPIO_PB5_EPI0S22        0x00011408
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_CCP5           0x00011806
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_EPI0S2         0x00021008
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_CCP3           0x00021405
+#define GPIO_PC5_EPI0S3         0x00021408
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+#define GPIO_PC6_EPI0S4         0x00021808
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_C1O            0x00021C07
+#define GPIO_PC7_EPI0S5         0x00021C08
+
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+#define GPIO_PD0_U1CTS          0x00030009
+
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_U1DCD          0x00030409
+#define GPIO_PD1_CCP2           0x0003040A
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_CCP5           0x00030804
+#define GPIO_PD2_EPI0S20        0x00030808
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_CCP0           0x00030C04
+#define GPIO_PD3_EPI0S21        0x00030C08
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+#define GPIO_PD4_U1RI           0x00031009
+#define GPIO_PD4_EPI0S19        0x0003100A
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_U2RX           0x00031409
+#define GPIO_PD5_EPI0S28        0x0003140A
+
+#define GPIO_PD6_U2TX           0x00031809
+#define GPIO_PD6_EPI0S29        0x0003180A
+
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+#define GPIO_PD7_U1DTR          0x00031C09
+#define GPIO_PD7_EPI0S30        0x00031C0A
+
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+#define GPIO_PE0_EPI0S8         0x00040008
+
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+#define GPIO_PE1_EPI0S9         0x00040408
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_CCP2           0x00040805
+#define GPIO_PE2_EPI0S24        0x00040808
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_CCP7           0x00040C05
+#define GPIO_PE3_EPI0S25        0x00040C08
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+
+#define GPIO_PE5_CCP5           0x00041401
+
+#define GPIO_PE6_C1O            0x00041802
+#define GPIO_PE6_U1CTS          0x00041809
+
+#define GPIO_PE7_U1DCD          0x00041C09
+
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_U1RTS          0x00050409
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_SSI1CLK        0x00050809
+
+#define GPIO_PF3_SSI1FSS        0x00050C09
+
+#define GPIO_PF4_CCP0           0x00051001
+#define GPIO_PF4_C0O            0x00051002
+#define GPIO_PF4_EPI0S12        0x00051008
+#define GPIO_PF4_SSI1RX         0x00051009
+
+#define GPIO_PF5_CCP2           0x00051401
+#define GPIO_PF5_C1O            0x00051402
+#define GPIO_PF5_EPI0S15        0x00051408
+#define GPIO_PF5_SSI1TX         0x00051409
+
+#define GPIO_PF6_CCP1           0x00051801
+#define GPIO_PF6_U1RTS          0x0005180A
+
+#define GPIO_PF7_CCP4           0x00051C01
+#define GPIO_PF7_EPI0S12        0x00051C08
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_I2C1SCL        0x00060003
+#define GPIO_PG0_EPI0S13        0x00060008
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_I2C1SDA        0x00060403
+#define GPIO_PG1_EPI0S14        0x00060408
+
+#define GPIO_PG4_CCP3           0x00061001
+#define GPIO_PG4_EPI0S15        0x00061008
+#define GPIO_PG4_U1RI           0x0006100A
+
+#define GPIO_PG5_CCP5           0x00061401
+#define GPIO_PG5_U1DTR          0x0006140A
+
+#define GPIO_PG6_U1RI           0x0006180A
+
+#define GPIO_PG7_CCP5           0x00061C08
+#define GPIO_PG7_EPI0S31        0x00061C09
+
+#define GPIO_PH0_CCP6           0x00070001
+#define GPIO_PH0_EPI0S6         0x00070008
+
+#define GPIO_PH1_CCP7           0x00070401
+#define GPIO_PH1_EPI0S7         0x00070408
+
+#define GPIO_PH2_C1O            0x00070802
+#define GPIO_PH2_EPI0S1         0x00070808
+
+#define GPIO_PH3_EPI0S0         0x00070C08
+
+#define GPIO_PH4_EPI0S10        0x00071008
+#define GPIO_PH4_SSI1CLK        0x0007100B
+
+#define GPIO_PH5_EPI0S11        0x00071408
+#define GPIO_PH5_SSI1FSS        0x0007140B
+
+#define GPIO_PH6_EPI0S26        0x00071808
+#define GPIO_PH6_SSI1RX         0x0007180B
+
+#define GPIO_PH7_EPI0S27        0x00071C08
+#define GPIO_PH7_SSI1TX         0x00071C0B
+
+#define GPIO_PJ0_EPI0S16        0x00080008
+#define GPIO_PJ0_I2C1SCL        0x0008000B
+
+#define GPIO_PJ1_EPI0S17        0x00080408
+#define GPIO_PJ1_I2C1SDA        0x0008040B
+
+#define GPIO_PJ2_EPI0S18        0x00080808
+#define GPIO_PJ2_CCP0           0x00080809
+
+#endif // PART_LM3S1H11
+
+//*****************************************************************************
+//
+// LM3S1H16 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1H16
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+
+#define GPIO_PA4_SSI0RX         0x00001001
+
+#define GPIO_PA5_SSI0TX         0x00001401
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_CCP3           0x00001C07
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_U1RX           0x00011007
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_CCP5           0x00011806
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_CCP3           0x00021405
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_C1O            0x00021C07
+
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_CCP2           0x0003040A
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_CCP5           0x00030804
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_CCP0           0x00030C04
+
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_CCP2           0x00040805
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_CCP7           0x00040C05
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+
+#endif // PART_LM3S1H16
+
+//*****************************************************************************
+//
+// LM3S1J11 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1J11
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+
+#define GPIO_PA4_SSI0RX         0x00001001
+
+#define GPIO_PA5_SSI0TX         0x00001401
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_U1CTS          0x00001809
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_U1DCD          0x00001C09
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_U1RX           0x00011007
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_CCP5           0x00011806
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_CCP3           0x00021405
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_C1O            0x00021C07
+
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_U1CTS          0x00030009
+
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_U1DCD          0x00030409
+#define GPIO_PD1_CCP2           0x0003040A
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP5           0x00030804
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP0           0x00030C04
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+#define GPIO_PD4_U1RI           0x00031009
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_U2RX           0x00031409
+
+#define GPIO_PD6_U2TX           0x00031809
+
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+#define GPIO_PD7_U1DTR          0x00031C09
+
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_CCP2           0x00040404
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_CCP2           0x00040805
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+
+#define GPIO_PE5_CCP5           0x00041401
+
+#define GPIO_PE6_C1O            0x00041802
+#define GPIO_PE6_U1CTS          0x00041809
+
+#define GPIO_PE7_U1DCD          0x00041C09
+
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_U1RTS          0x00050409
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_SSI1CLK        0x00050809
+
+#define GPIO_PF3_SSI1FSS        0x00050C09
+
+#define GPIO_PF4_CCP0           0x00051001
+#define GPIO_PF4_C0O            0x00051002
+#define GPIO_PF4_SSI1RX         0x00051009
+
+#define GPIO_PF5_CCP2           0x00051401
+#define GPIO_PF5_C1O            0x00051402
+#define GPIO_PF5_SSI1TX         0x00051409
+
+#define GPIO_PF6_CCP1           0x00051801
+#define GPIO_PF6_U1RTS          0x0005180A
+
+#define GPIO_PF7_CCP4           0x00051C01
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_I2C1SCL        0x00060003
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_I2C1SDA        0x00060403
+
+#define GPIO_PG4_CCP3           0x00061001
+#define GPIO_PG4_U1RI           0x0006100A
+
+#define GPIO_PG5_CCP5           0x00061401
+#define GPIO_PG5_U1DTR          0x0006140A
+
+#define GPIO_PG6_U1RI           0x0006180A
+
+#define GPIO_PG7_CCP5           0x00061C08
+
+#define GPIO_PH2_C1O            0x00070802
+
+#define GPIO_PH4_SSI1CLK        0x0007100B
+
+#define GPIO_PH5_SSI1FSS        0x0007140B
+
+#define GPIO_PH6_SSI1RX         0x0007180B
+
+#define GPIO_PH7_SSI1TX         0x00071C0B
+
+#define GPIO_PJ0_I2C1SCL        0x0008000B
+
+#define GPIO_PJ1_I2C1SDA        0x0008040B
+
+#define GPIO_PJ2_CCP0           0x00080809
+
+#endif // PART_LM3S1J11
+
+//*****************************************************************************
+//
+// LM3S1J16 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1J16
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+
+#define GPIO_PA4_SSI0RX         0x00001001
+
+#define GPIO_PA5_SSI0TX         0x00001401
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_CCP3           0x00001C07
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_U1RX           0x00011007
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_CCP5           0x00011806
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_CCP3           0x00021405
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_C1O            0x00021C07
+
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP2           0x0003040A
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP5           0x00030804
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP0           0x00030C04
+
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_CCP2           0x00040404
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_CCP2           0x00040805
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+
+#endif // PART_LM3S1J16
+
+//*****************************************************************************
+//
+// LM3S1N11 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1N11
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+
+#define GPIO_PA4_SSI0RX         0x00001001
+
+#define GPIO_PA5_SSI0TX         0x00001401
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_U1CTS          0x00001809
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_U1DCD          0x00001C09
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_U1RX           0x00011007
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_CCP5           0x00011806
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_CCP3           0x00021405
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_C1O            0x00021C07
+
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_U1CTS          0x00030009
+
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_U1DCD          0x00030409
+#define GPIO_PD1_CCP2           0x0003040A
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP5           0x00030804
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP0           0x00030C04
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+#define GPIO_PD4_U1RI           0x00031009
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_U2RX           0x00031409
+
+#define GPIO_PD6_U2TX           0x00031809
+
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+#define GPIO_PD7_U1DTR          0x00031C09
+
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_CCP2           0x00040404
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_CCP2           0x00040805
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+
+#define GPIO_PE5_CCP5           0x00041401
+
+#define GPIO_PE6_C1O            0x00041802
+#define GPIO_PE6_U1CTS          0x00041809
+
+#define GPIO_PE7_U1DCD          0x00041C09
+
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_U1RTS          0x00050409
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_SSI1CLK        0x00050809
+
+#define GPIO_PF3_SSI1FSS        0x00050C09
+
+#define GPIO_PF4_CCP0           0x00051001
+#define GPIO_PF4_C0O            0x00051002
+#define GPIO_PF4_SSI1RX         0x00051009
+
+#define GPIO_PF5_CCP2           0x00051401
+#define GPIO_PF5_C1O            0x00051402
+#define GPIO_PF5_SSI1TX         0x00051409
+
+#define GPIO_PF6_CCP1           0x00051801
+#define GPIO_PF6_U1RTS          0x0005180A
+
+#define GPIO_PF7_CCP4           0x00051C01
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_I2C1SCL        0x00060003
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_I2C1SDA        0x00060403
+
+#define GPIO_PG4_CCP3           0x00061001
+#define GPIO_PG4_U1RI           0x0006100A
+
+#define GPIO_PG5_CCP5           0x00061401
+#define GPIO_PG5_U1DTR          0x0006140A
+
+#define GPIO_PG6_U1RI           0x0006180A
+
+#define GPIO_PG7_CCP5           0x00061C08
+
+#define GPIO_PH2_C1O            0x00070802
+
+#define GPIO_PH4_SSI1CLK        0x0007100B
+
+#define GPIO_PH5_SSI1FSS        0x0007140B
+
+#define GPIO_PH6_SSI1RX         0x0007180B
+
+#define GPIO_PH7_SSI1TX         0x00071C0B
+
+#define GPIO_PJ0_I2C1SCL        0x0008000B
+
+#define GPIO_PJ1_I2C1SDA        0x0008040B
+
+#define GPIO_PJ2_CCP0           0x00080809
+
+#endif // PART_LM3S1N11
+
+//*****************************************************************************
+//
+// LM3S1N16 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1N16
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+
+#define GPIO_PA4_SSI0RX         0x00001001
+
+#define GPIO_PA5_SSI0TX         0x00001401
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_CCP3           0x00001C07
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_U1RX           0x00011007
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_CCP5           0x00011806
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_CCP3           0x00021405
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_C1O            0x00021C07
+
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP2           0x0003040A
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP5           0x00030804
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP0           0x00030C04
+
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_CCP2           0x00040404
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_CCP2           0x00040805
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+
+#endif // PART_LM3S1N16
+
+//*****************************************************************************
+//
+// LM3S1P51 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1P51
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_PWM4           0x00000804
+#define GPIO_PA2_I2S0RXSD       0x00000809
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_PWM5           0x00000C04
+#define GPIO_PA3_I2S0RXMCLK     0x00000C09
+
+#define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_I2S0TXSCK      0x00001009
+
+#define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_I2S0TXWS       0x00001409
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_PWM0           0x00001804
+#define GPIO_PA6_PWM4           0x00001805
+#define GPIO_PA6_U1CTS          0x00001809
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_PWM1           0x00001C04
+#define GPIO_PA7_PWM5           0x00001C05
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_U1DCD          0x00001C09
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_PWM2           0x00010002
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_PWM3           0x00010402
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_IDX0           0x00010802
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_FAULT0         0x00010C02
+#define GPIO_PB3_FAULT3         0x00010C04
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_IDX0           0x00011006
+#define GPIO_PB4_U1RX           0x00011007
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_FAULT1         0x00011804
+#define GPIO_PB6_IDX0           0x00011805
+#define GPIO_PB6_CCP5           0x00011806
+#define GPIO_PB6_I2S0TXSCK      0x00011809
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_PHA0           0x00021002
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_FAULT2         0x00021404
+#define GPIO_PC5_CCP3           0x00021405
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_PHB0           0x00021802
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_PHB0           0x00021C02
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_C1O            0x00021C07
+
+#define GPIO_PD0_PWM0           0x00030001
+#define GPIO_PD0_IDX0           0x00030003
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+#define GPIO_PD0_I2S0RXSCK      0x00030008
+#define GPIO_PD0_U1CTS          0x00030009
+
+#define GPIO_PD1_PWM1           0x00030401
+#define GPIO_PD1_PHA0           0x00030403
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_I2S0RXWS       0x00030408
+#define GPIO_PD1_U1DCD          0x00030409
+#define GPIO_PD1_CCP2           0x0003040A
+#define GPIO_PD1_PHB1           0x0003040B
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_PWM2           0x00030803
+#define GPIO_PD2_CCP5           0x00030804
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_PWM3           0x00030C03
+#define GPIO_PD3_CCP0           0x00030C04
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+#define GPIO_PD4_I2S0RXSD       0x00031008
+#define GPIO_PD4_U1RI           0x00031009
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_I2S0RXMCLK     0x00031408
+#define GPIO_PD5_U2RX           0x00031409
+
+#define GPIO_PD6_FAULT0         0x00031801
+#define GPIO_PD6_I2S0TXSCK      0x00031808
+#define GPIO_PD6_U2TX           0x00031809
+
+#define GPIO_PD7_IDX0           0x00031C01
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+#define GPIO_PD7_I2S0TXWS       0x00031C08
+#define GPIO_PD7_U1DTR          0x00031C09
+
+#define GPIO_PE0_PWM4           0x00040001
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+
+#define GPIO_PE1_PWM5           0x00040401
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_FAULT0         0x00040403
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_PHB1           0x00040803
+#define GPIO_PE2_PHA0           0x00040804
+#define GPIO_PE2_CCP2           0x00040805
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_PHA1           0x00040C03
+#define GPIO_PE3_PHB0           0x00040C04
+#define GPIO_PE3_CCP7           0x00040C05
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_FAULT0         0x00041004
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+#define GPIO_PE4_I2S0TXWS       0x00041009
+
+#define GPIO_PE5_CCP5           0x00041401
+#define GPIO_PE5_I2S0TXSD       0x00041409
+
+#define GPIO_PE6_PWM4           0x00041801
+#define GPIO_PE6_C1O            0x00041802
+#define GPIO_PE6_U1CTS          0x00041809
+
+#define GPIO_PE7_PWM5           0x00041C01
+#define GPIO_PE7_U1DCD          0x00041C09
+
+#define GPIO_PF0_PHB0           0x00050002
+#define GPIO_PF0_PWM0           0x00050003
+#define GPIO_PF0_I2S0TXSD       0x00050008
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_IDX1           0x00050402
+#define GPIO_PF1_PWM1           0x00050403
+#define GPIO_PF1_I2S0TXMCLK     0x00050408
+#define GPIO_PF1_U1RTS          0x00050409
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_PWM4           0x00050802
+#define GPIO_PF2_PWM2           0x00050804
+#define GPIO_PF2_SSI1CLK        0x00050809
+
+#define GPIO_PF3_PWM5           0x00050C02
+#define GPIO_PF3_PWM3           0x00050C04
+#define GPIO_PF3_SSI1FSS        0x00050C09
+
+#define GPIO_PF4_CCP0           0x00051001
+#define GPIO_PF4_C0O            0x00051002
+#define GPIO_PF4_FAULT0         0x00051004
+#define GPIO_PF4_SSI1RX         0x00051009
+
+#define GPIO_PF5_CCP2           0x00051401
+#define GPIO_PF5_C1O            0x00051402
+#define GPIO_PF5_SSI1TX         0x00051409
+
+#define GPIO_PF6_CCP1           0x00051801
+#define GPIO_PF6_PHA0           0x00051804
+#define GPIO_PF6_I2S0TXMCLK     0x00051809
+#define GPIO_PF6_U1RTS          0x0005180A
+
+#define GPIO_PF7_CCP4           0x00051C01
+#define GPIO_PF7_PHB0           0x00051C04
+#define GPIO_PF7_FAULT1         0x00051C09
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_PWM0           0x00060002
+#define GPIO_PG0_I2C1SCL        0x00060003
+#define GPIO_PG0_PWM4           0x00060004
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_PWM1           0x00060402
+#define GPIO_PG1_I2C1SDA        0x00060403
+#define GPIO_PG1_PWM5           0x00060404
+
+#define GPIO_PG2_PWM0           0x00060801
+#define GPIO_PG2_FAULT0         0x00060804
+#define GPIO_PG2_IDX1           0x00060808
+#define GPIO_PG2_I2S0RXSD       0x00060809
+
+#define GPIO_PG3_PWM1           0x00060C01
+#define GPIO_PG3_FAULT2         0x00060C04
+#define GPIO_PG3_FAULT0         0x00060C08
+#define GPIO_PG3_I2S0RXMCLK     0x00060C09
+
+#define GPIO_PG4_CCP3           0x00061001
+#define GPIO_PG4_FAULT1         0x00061004
+#define GPIO_PG4_U1RI           0x0006100A
+
+#define GPIO_PG5_CCP5           0x00061401
+#define GPIO_PG5_IDX0           0x00061404
+#define GPIO_PG5_FAULT1         0x00061405
+#define GPIO_PG5_I2S0RXSCK      0x00061409
+#define GPIO_PG5_U1DTR          0x0006140A
+
+#define GPIO_PG6_PHA1           0x00061801
+#define GPIO_PG6_FAULT1         0x00061808
+#define GPIO_PG6_I2S0RXWS       0x00061809
+#define GPIO_PG6_U1RI           0x0006180A
+
+#define GPIO_PG7_PHB1           0x00061C01
+#define GPIO_PG7_CCP5           0x00061C08
+
+#define GPIO_PH0_CCP6           0x00070001
+#define GPIO_PH0_PWM2           0x00070002
+#define GPIO_PH0_PWM4           0x00070009
+
+#define GPIO_PH1_CCP7           0x00070401
+#define GPIO_PH1_PWM3           0x00070402
+#define GPIO_PH1_PWM5           0x00070409
+
+#define GPIO_PH2_IDX1           0x00070801
+#define GPIO_PH2_C1O            0x00070802
+#define GPIO_PH2_FAULT3         0x00070804
+
+#define GPIO_PH3_PHB0           0x00070C01
+#define GPIO_PH3_FAULT0         0x00070C02
+
+#define GPIO_PH4_SSI1CLK        0x0007100B
+
+#define GPIO_PH5_FAULT2         0x0007140A
+#define GPIO_PH5_SSI1FSS        0x0007140B
+
+#define GPIO_PH6_PWM4           0x0007180A
+#define GPIO_PH6_SSI1RX         0x0007180B
+
+#define GPIO_PH7_PWM5           0x00071C0A
+#define GPIO_PH7_SSI1TX         0x00071C0B
+
+#define GPIO_PJ0_PWM0           0x0008000A
+#define GPIO_PJ0_I2C1SCL        0x0008000B
+
+#define GPIO_PJ1_PWM1           0x0008040A
+#define GPIO_PJ1_I2C1SDA        0x0008040B
+
+#define GPIO_PJ2_CCP0           0x00080809
+#define GPIO_PJ2_FAULT0         0x0008080A
+
+#endif // PART_LM3S1P51
+
+//*****************************************************************************
+//
+// LM3S1R21 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1R21
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+
+#define GPIO_PA4_SSI0RX         0x00001001
+
+#define GPIO_PA5_SSI0TX         0x00001401
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_U1CTS          0x00001809
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_U1DCD          0x00001C09
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_U1RX           0x00011007
+#define GPIO_PB4_EPI0S23        0x00011008
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+#define GPIO_PB5_EPI0S22        0x00011408
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_CCP5           0x00011806
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_EPI0S2         0x00021008
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_CCP3           0x00021405
+#define GPIO_PC5_EPI0S3         0x00021408
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+#define GPIO_PC6_EPI0S4         0x00021808
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_C1O            0x00021C07
+#define GPIO_PC7_EPI0S5         0x00021C08
+
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+#define GPIO_PD0_U1CTS          0x00030009
+
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_U1DCD          0x00030409
+#define GPIO_PD1_CCP2           0x0003040A
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_CCP5           0x00030804
+#define GPIO_PD2_EPI0S20        0x00030808
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_CCP0           0x00030C04
+#define GPIO_PD3_EPI0S21        0x00030C08
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+#define GPIO_PD4_U1RI           0x00031009
+#define GPIO_PD4_EPI0S19        0x0003100A
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_U2RX           0x00031409
+#define GPIO_PD5_EPI0S28        0x0003140A
+
+#define GPIO_PD6_U2TX           0x00031809
+#define GPIO_PD6_EPI0S29        0x0003180A
+
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+#define GPIO_PD7_U1DTR          0x00031C09
+#define GPIO_PD7_EPI0S30        0x00031C0A
+
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+#define GPIO_PE0_EPI0S8         0x00040008
+
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+#define GPIO_PE1_EPI0S9         0x00040408
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_CCP2           0x00040805
+#define GPIO_PE2_EPI0S24        0x00040808
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_CCP7           0x00040C05
+#define GPIO_PE3_EPI0S25        0x00040C08
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+
+#define GPIO_PE5_CCP5           0x00041401
+
+#define GPIO_PE6_C1O            0x00041802
+#define GPIO_PE6_U1CTS          0x00041809
+
+#define GPIO_PE7_U1DCD          0x00041C09
+
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_U1RTS          0x00050409
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_SSI1CLK        0x00050809
+
+#define GPIO_PF3_SSI1FSS        0x00050C09
+
+#define GPIO_PF4_CCP0           0x00051001
+#define GPIO_PF4_C0O            0x00051002
+#define GPIO_PF4_EPI0S12        0x00051008
+#define GPIO_PF4_SSI1RX         0x00051009
+
+#define GPIO_PF5_CCP2           0x00051401
+#define GPIO_PF5_C1O            0x00051402
+#define GPIO_PF5_EPI0S15        0x00051408
+#define GPIO_PF5_SSI1TX         0x00051409
+
+#define GPIO_PF6_CCP1           0x00051801
+#define GPIO_PF6_U1RTS          0x0005180A
+
+#define GPIO_PF7_CCP4           0x00051C01
+#define GPIO_PF7_EPI0S12        0x00051C08
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_I2C1SCL        0x00060003
+#define GPIO_PG0_EPI0S13        0x00060008
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_I2C1SDA        0x00060403
+#define GPIO_PG1_EPI0S14        0x00060408
+
+#define GPIO_PG4_CCP3           0x00061001
+#define GPIO_PG4_EPI0S15        0x00061008
+#define GPIO_PG4_U1RI           0x0006100A
+
+#define GPIO_PG5_CCP5           0x00061401
+#define GPIO_PG5_U1DTR          0x0006140A
+
+#define GPIO_PG6_U1RI           0x0006180A
+
+#define GPIO_PG7_CCP5           0x00061C08
+#define GPIO_PG7_EPI0S31        0x00061C09
+
+#define GPIO_PH0_CCP6           0x00070001
+#define GPIO_PH0_EPI0S6         0x00070008
+
+#define GPIO_PH1_CCP7           0x00070401
+#define GPIO_PH1_EPI0S7         0x00070408
+
+#define GPIO_PH2_C1O            0x00070802
+#define GPIO_PH2_EPI0S1         0x00070808
+
+#define GPIO_PH3_EPI0S0         0x00070C08
+
+#define GPIO_PH4_EPI0S10        0x00071008
+#define GPIO_PH4_SSI1CLK        0x0007100B
+
+#define GPIO_PH5_EPI0S11        0x00071408
+#define GPIO_PH5_SSI1FSS        0x0007140B
+
+#define GPIO_PH6_EPI0S26        0x00071808
+#define GPIO_PH6_SSI1RX         0x0007180B
+
+#define GPIO_PH7_EPI0S27        0x00071C08
+#define GPIO_PH7_SSI1TX         0x00071C0B
+
+#define GPIO_PJ0_EPI0S16        0x00080008
+#define GPIO_PJ0_I2C1SCL        0x0008000B
+
+#define GPIO_PJ1_EPI0S17        0x00080408
+#define GPIO_PJ1_I2C1SDA        0x0008040B
+
+#define GPIO_PJ2_EPI0S18        0x00080808
+#define GPIO_PJ2_CCP0           0x00080809
+
+#endif // PART_LM3S1R21
+
+//*****************************************************************************
+//
+// LM3S1R26 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1R26
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+
+#define GPIO_PA4_SSI0RX         0x00001001
+
+#define GPIO_PA5_SSI0TX         0x00001401
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_CCP3           0x00001C07
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_U1RX           0x00011007
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_CCP5           0x00011806
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_CCP3           0x00021405
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_C1O            0x00021C07
+
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_CCP2           0x0003040A
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_CCP5           0x00030804
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_CCP0           0x00030C04
+
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_CCP2           0x00040805
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_CCP7           0x00040C05
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+
+#endif // PART_LM3S1R26
+
+//*****************************************************************************
+//
+// LM3S1W16 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1W16
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+
+#define GPIO_PA4_SSI0RX         0x00001001
+
+#define GPIO_PA5_SSI0TX         0x00001401
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_CCP3           0x00001C07
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_U1RX           0x00011007
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_CCP5           0x00011806
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_CCP3           0x00021405
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_C1O            0x00021C07
+
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP2           0x0003040A
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP5           0x00030804
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP0           0x00030C04
+
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_CCP2           0x00040404
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_CCP2           0x00040805
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+
+#endif // PART_LM3S1W16
+
+//*****************************************************************************
+//
+// LM3S1Z16 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1Z16
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+
+#define GPIO_PA4_SSI0RX         0x00001001
+
+#define GPIO_PA5_SSI0TX         0x00001401
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_CCP3           0x00001C07
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_U1RX           0x00011007
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_CCP5           0x00011806
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_CCP3           0x00021405
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_C1O            0x00021C07
+
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP2           0x0003040A
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP5           0x00030804
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP0           0x00030C04
+
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_CCP2           0x00040404
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_CCP2           0x00040805
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+
+#endif // PART_LM3S1Z16
+
+//*****************************************************************************
+//
+// LM3S2016 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2016
+
+#define CAN0RX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0RX_PORT             GPIO_PORTD_BASE
+#define CAN0RX_PIN              GPIO_PIN_0
+
+#define CAN0TX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0TX_PORT             GPIO_PORTD_BASE
+#define CAN0TX_PIN              GPIO_PIN_1
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP1_PORT               GPIO_PORTA_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_1
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP3_PORT               GPIO_PORTC_BASE
+#define CCP3_PIN                GPIO_PIN_6
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#endif // PART_LM3S2016
+
+//*****************************************************************************
+//
+// LM3S2110 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2110
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOD
+#define C0O_PORT                GPIO_PORTD_BASE
+#define C0O_PIN                 GPIO_PIN_7
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_5
+
+#define C2_MINUS_PERIPH         SYSCTL_PERIPH_GPIOC
+#define C2_MINUS_PORT           GPIO_PORTC_BASE
+#define C2_MINUS_PIN            GPIO_PIN_7
+
+#define C2_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C2_PLUS_PORT            GPIO_PORTC_BASE
+#define C2_PLUS_PIN             GPIO_PIN_6
+
+#define CAN0RX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0RX_PORT             GPIO_PORTD_BASE
+#define CAN0RX_PIN              GPIO_PIN_0
+
+#define CAN0TX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0TX_PORT             GPIO_PORTD_BASE
+#define CAN0TX_PIN              GPIO_PIN_1
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP1_PORT               GPIO_PORTA_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_1
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP3_PORT               GPIO_PORTD_BASE
+#define CCP3_PIN                GPIO_PIN_4
+
+#define FAULT_PERIPH            SYSCTL_PERIPH_GPIOD
+#define FAULT_PORT              GPIO_PORTD_BASE
+#define FAULT_PIN               GPIO_PIN_6
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOF
+#define PWM0_PORT               GPIO_PORTF_BASE
+#define PWM0_PIN                GPIO_PIN_0
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOF
+#define PWM1_PORT               GPIO_PORTF_BASE
+#define PWM1_PIN                GPIO_PIN_1
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#endif // PART_LM3S2110
+
+//*****************************************************************************
+//
+// LM3S2139 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2139
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOD
+#define C0O_PORT                GPIO_PORTD_BASE
+#define C0O_PIN                 GPIO_PIN_7
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_5
+
+#define C2_MINUS_PERIPH         SYSCTL_PERIPH_GPIOC
+#define C2_MINUS_PORT           GPIO_PORTC_BASE
+#define C2_MINUS_PIN            GPIO_PIN_7
+
+#define C2_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C2_PLUS_PORT            GPIO_PORTC_BASE
+#define C2_PLUS_PIN             GPIO_PIN_6
+
+#define CAN0RX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0RX_PORT             GPIO_PORTD_BASE
+#define CAN0RX_PIN              GPIO_PIN_0
+
+#define CAN0TX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0TX_PORT             GPIO_PORTD_BASE
+#define CAN0TX_PIN              GPIO_PIN_1
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP1_PORT               GPIO_PORTA_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_1
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP3_PORT               GPIO_PORTD_BASE
+#define CCP3_PIN                GPIO_PIN_4
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP4_PORT               GPIO_PORTA_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP5_PORT               GPIO_PORTC_BASE
+#define CCP5_PIN                GPIO_PIN_4
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#endif // PART_LM3S2139
+
+//*****************************************************************************
+//
+// LM3S2276 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2276
+
+#define ADC0_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC0_PORT               GPIO_PORTE_BASE
+#define ADC0_PIN                GPIO_PIN_3
+
+#define ADC1_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC1_PORT               GPIO_PORTE_BASE
+#define ADC1_PIN                GPIO_PIN_2
+
+#define ADC2_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC2_PORT               GPIO_PORTE_BASE
+#define ADC2_PIN                GPIO_PIN_1
+
+#define ADC3_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC3_PORT               GPIO_PORTE_BASE
+#define ADC3_PIN                GPIO_PIN_0
+
+#define ADC4_PERIPH             SYSCTL_PERIPH_GPIOD
+#define ADC4_PORT               GPIO_PORTD_BASE
+#define ADC4_PIN                GPIO_PIN_3
+
+#define ADC5_PERIPH             SYSCTL_PERIPH_GPIOD
+#define ADC5_PORT               GPIO_PORTD_BASE
+#define ADC5_PIN                GPIO_PIN_2
+
+#define CAN0RX_PERIPH           SYSCTL_PERIPH_GPIOB
+#define CAN0RX_PORT             GPIO_PORTB_BASE
+#define CAN0RX_PIN              GPIO_PIN_4
+
+#define CAN0TX_PERIPH           SYSCTL_PERIPH_GPIOB
+#define CAN0TX_PORT             GPIO_PORTB_BASE
+#define CAN0TX_PIN              GPIO_PIN_5
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP0_PORT               GPIO_PORTC_BASE
+#define CCP0_PIN                GPIO_PIN_7
+
+#define FAULT0_PERIPH           SYSCTL_PERIPH_GPIOE
+#define FAULT0_PORT             GPIO_PORTE_BASE
+#define FAULT0_PIN              GPIO_PIN_4
+
+#define FAULT1_PERIPH           SYSCTL_PERIPH_GPIOB
+#define FAULT1_PORT             GPIO_PORTB_BASE
+#define FAULT1_PIN              GPIO_PIN_6
+
+#define FAULT2_PERIPH           SYSCTL_PERIPH_GPIOC
+#define FAULT2_PORT             GPIO_PORTC_BASE
+#define FAULT2_PIN              GPIO_PIN_5
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define NMI_PERIPH              SYSCTL_PERIPH_GPIOB
+#define NMI_PORT                GPIO_PORTB_BASE
+#define NMI_PIN                 GPIO_PIN_7
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM0_PORT               GPIO_PORTD_BASE
+#define PWM0_PIN                GPIO_PIN_0
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM1_PORT               GPIO_PORTD_BASE
+#define PWM1_PIN                GPIO_PIN_1
+
+#define PWM2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define PWM2_PORT               GPIO_PORTB_BASE
+#define PWM2_PIN                GPIO_PIN_0
+
+#define PWM3_PERIPH             SYSCTL_PERIPH_GPIOB
+#define PWM3_PORT               GPIO_PORTB_BASE
+#define PWM3_PIN                GPIO_PIN_1
+
+#define PWM4_PERIPH             SYSCTL_PERIPH_GPIOA
+#define PWM4_PORT               GPIO_PORTA_BASE
+#define PWM4_PIN                GPIO_PIN_6
+
+#define PWM5_PERIPH             SYSCTL_PERIPH_GPIOA
+#define PWM5_PORT               GPIO_PORTA_BASE
+#define PWM5_PIN                GPIO_PIN_7
+
+#define PWM6_PERIPH             SYSCTL_PERIPH_GPIOC
+#define PWM6_PORT               GPIO_PORTC_BASE
+#define PWM6_PIN                GPIO_PIN_4
+
+#define PWM7_PERIPH             SYSCTL_PERIPH_GPIOC
+#define PWM7_PORT               GPIO_PORTC_BASE
+#define PWM7_PIN                GPIO_PIN_6
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#endif // PART_LM3S2276
+
+//*****************************************************************************
+//
+// LM3S2410 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2410
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOD
+#define C0O_PORT                GPIO_PORTD_BASE
+#define C0O_PIN                 GPIO_PIN_7
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1O_PERIPH              SYSCTL_PERIPH_GPIOE
+#define C1O_PORT                GPIO_PORTE_BASE
+#define C1O_PIN                 GPIO_PIN_6
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_5
+
+#define CAN0RX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0RX_PORT             GPIO_PORTD_BASE
+#define CAN0RX_PIN              GPIO_PIN_0
+
+#define CAN0TX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0TX_PORT             GPIO_PORTD_BASE
+#define CAN0TX_PIN              GPIO_PIN_1
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP1_PORT               GPIO_PORTA_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_1
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP3_PORT               GPIO_PORTC_BASE
+#define CCP3_PIN                GPIO_PIN_6
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#endif // PART_LM3S2410
+
+//*****************************************************************************
+//
+// LM3S2412 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2412
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOD
+#define C0O_PORT                GPIO_PORTD_BASE
+#define C0O_PIN                 GPIO_PIN_7
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_5
+
+#define CAN0RX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0RX_PORT             GPIO_PORTD_BASE
+#define CAN0RX_PIN              GPIO_PIN_0
+
+#define CAN0TX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0TX_PORT             GPIO_PORTD_BASE
+#define CAN0TX_PIN              GPIO_PIN_1
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP1_PORT               GPIO_PORTA_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_1
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP3_PORT               GPIO_PORTC_BASE
+#define CCP3_PIN                GPIO_PIN_6
+
+#define FAULT_PERIPH            SYSCTL_PERIPH_GPIOD
+#define FAULT_PORT              GPIO_PORTD_BASE
+#define FAULT_PIN               GPIO_PIN_6
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOF
+#define PWM0_PORT               GPIO_PORTF_BASE
+#define PWM0_PIN                GPIO_PIN_0
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOF
+#define PWM1_PORT               GPIO_PORTF_BASE
+#define PWM1_PIN                GPIO_PIN_1
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#endif // PART_LM3S2412
+
+//*****************************************************************************
+//
+// LM3S2432 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2432
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOD
+#define C0O_PORT                GPIO_PORTD_BASE
+#define C0O_PIN                 GPIO_PIN_7
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_5
+
+#define CAN0RX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0RX_PORT             GPIO_PORTD_BASE
+#define CAN0RX_PIN              GPIO_PIN_0
+
+#define CAN0TX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0TX_PORT             GPIO_PORTD_BASE
+#define CAN0TX_PIN              GPIO_PIN_1
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP1_PORT               GPIO_PORTA_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_1
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP3_PORT               GPIO_PORTC_BASE
+#define CCP3_PIN                GPIO_PIN_6
+
+#define FAULT_PERIPH            SYSCTL_PERIPH_GPIOD
+#define FAULT_PORT              GPIO_PORTD_BASE
+#define FAULT_PIN               GPIO_PIN_6
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOF
+#define PWM0_PORT               GPIO_PORTF_BASE
+#define PWM0_PIN                GPIO_PIN_0
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOF
+#define PWM1_PORT               GPIO_PORTF_BASE
+#define PWM1_PIN                GPIO_PIN_1
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#endif // PART_LM3S2432
+
+//*****************************************************************************
+//
+// LM3S2533 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2533
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOD
+#define C0O_PORT                GPIO_PORTD_BASE
+#define C0O_PIN                 GPIO_PIN_7
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_5
+
+#define C2_MINUS_PERIPH         SYSCTL_PERIPH_GPIOC
+#define C2_MINUS_PORT           GPIO_PORTC_BASE
+#define C2_MINUS_PIN            GPIO_PIN_7
+
+#define C2_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C2_PLUS_PORT            GPIO_PORTC_BASE
+#define C2_PLUS_PIN             GPIO_PIN_6
+
+#define CAN0RX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0RX_PORT             GPIO_PORTD_BASE
+#define CAN0RX_PIN              GPIO_PIN_0
+
+#define CAN0TX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0TX_PORT             GPIO_PORTD_BASE
+#define CAN0TX_PIN              GPIO_PIN_1
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP1_PORT               GPIO_PORTA_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_1
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP3_PORT               GPIO_PORTD_BASE
+#define CCP3_PIN                GPIO_PIN_4
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP4_PORT               GPIO_PORTA_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP5_PORT               GPIO_PORTC_BASE
+#define CCP5_PIN                GPIO_PIN_4
+
+#define FAULT_PERIPH            SYSCTL_PERIPH_GPIOD
+#define FAULT_PORT              GPIO_PORTD_BASE
+#define FAULT_PIN               GPIO_PIN_6
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOF
+#define PWM0_PORT               GPIO_PORTF_BASE
+#define PWM0_PIN                GPIO_PIN_0
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOF
+#define PWM1_PORT               GPIO_PORTF_BASE
+#define PWM1_PIN                GPIO_PIN_1
+
+#define PWM2_PERIPH             SYSCTL_PERIPH_GPIOH
+#define PWM2_PORT               GPIO_PORTH_BASE
+#define PWM2_PIN                GPIO_PIN_0
+
+#define PWM3_PERIPH             SYSCTL_PERIPH_GPIOH
+#define PWM3_PORT               GPIO_PORTH_BASE
+#define PWM3_PIN                GPIO_PIN_1
+
+#define PWM4_PERIPH             SYSCTL_PERIPH_GPIOE
+#define PWM4_PORT               GPIO_PORTE_BASE
+#define PWM4_PIN                GPIO_PIN_0
+
+#define PWM5_PERIPH             SYSCTL_PERIPH_GPIOE
+#define PWM5_PORT               GPIO_PORTE_BASE
+#define PWM5_PIN                GPIO_PIN_1
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#endif // PART_LM3S2533
+
+//*****************************************************************************
+//
+// LM3S2601 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2601
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOF
+#define C0O_PORT                GPIO_PORTF_BASE
+#define C0O_PIN                 GPIO_PIN_4
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1O_PERIPH              SYSCTL_PERIPH_GPIOE
+#define C1O_PORT                GPIO_PORTE_BASE
+#define C1O_PIN                 GPIO_PIN_6
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_5
+
+#define CAN0RX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0RX_PORT             GPIO_PORTD_BASE
+#define CAN0RX_PIN              GPIO_PIN_0
+
+#define CAN0TX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0TX_PORT             GPIO_PORTD_BASE
+#define CAN0TX_PIN              GPIO_PIN_1
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP1_PORT               GPIO_PORTD_BASE
+#define CCP1_PIN                GPIO_PIN_7
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_1
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP3_PORT               GPIO_PORTC_BASE
+#define CCP3_PIN                GPIO_PIN_6
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP4_PORT               GPIO_PORTC_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP5_PORT               GPIO_PORTC_BASE
+#define CCP5_PIN                GPIO_PIN_4
+
+#define CCP6_PERIPH             SYSCTL_PERIPH_GPIOH
+#define CCP6_PORT               GPIO_PORTH_BASE
+#define CCP6_PIN                GPIO_PIN_0
+
+#define CCP7_PERIPH             SYSCTL_PERIPH_GPIOH
+#define CCP7_PORT               GPIO_PORTH_BASE
+#define CCP7_PIN                GPIO_PIN_1
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define I2C1SCL_PERIPH          SYSCTL_PERIPH_GPIOA
+#define I2C1SCL_PORT            GPIO_PORTA_BASE
+#define I2C1SCL_PIN             GPIO_PIN_6
+
+#define I2C1SDA_PERIPH          SYSCTL_PERIPH_GPIOA
+#define I2C1SDA_PORT            GPIO_PORTA_BASE
+#define I2C1SDA_PIN             GPIO_PIN_7
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SSI1CLK_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1CLK_PORT            GPIO_PORTE_BASE
+#define SSI1CLK_PIN             GPIO_PIN_0
+
+#define SSI1FSS_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1FSS_PORT            GPIO_PORTE_BASE
+#define SSI1FSS_PIN             GPIO_PIN_1
+
+#define SSI1RX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1RX_PORT             GPIO_PORTE_BASE
+#define SSI1RX_PIN              GPIO_PIN_2
+
+#define SSI1TX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1TX_PORT             GPIO_PORTE_BASE
+#define SSI1TX_PIN              GPIO_PIN_3
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#define U2RX_PERIPH             SYSCTL_PERIPH_GPIOG
+#define U2RX_PORT               GPIO_PORTG_BASE
+#define U2RX_PIN                GPIO_PIN_0
+
+#define U2TX_PERIPH             SYSCTL_PERIPH_GPIOG
+#define U2TX_PORT               GPIO_PORTG_BASE
+#define U2TX_PIN                GPIO_PIN_1
+
+#endif // PART_LM3S2601
+
+//*****************************************************************************
+//
+// LM3S2608 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2608
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOF
+#define C0O_PORT                GPIO_PORTF_BASE
+#define C0O_PIN                 GPIO_PIN_4
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1O_PERIPH              SYSCTL_PERIPH_GPIOF
+#define C1O_PORT                GPIO_PORTF_BASE
+#define C1O_PIN                 GPIO_PIN_5
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_5
+
+#define CAN0RX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0RX_PORT             GPIO_PORTD_BASE
+#define CAN0RX_PIN              GPIO_PIN_0
+
+#define CAN0TX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0TX_PORT             GPIO_PORTD_BASE
+#define CAN0TX_PIN              GPIO_PIN_1
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOF
+#define CCP1_PORT               GPIO_PORTF_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_1
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP3_PORT               GPIO_PORTC_BASE
+#define CCP3_PIN                GPIO_PIN_6
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP4_PORT               GPIO_PORTC_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP5_PORT               GPIO_PORTC_BASE
+#define CCP5_PIN                GPIO_PIN_4
+
+#define CCP6_PERIPH             SYSCTL_PERIPH_GPIOH
+#define CCP6_PORT               GPIO_PORTH_BASE
+#define CCP6_PIN                GPIO_PIN_0
+
+#define CCP7_PERIPH             SYSCTL_PERIPH_GPIOH
+#define CCP7_PORT               GPIO_PORTH_BASE
+#define CCP7_PIN                GPIO_PIN_1
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define I2C1SCL_PERIPH          SYSCTL_PERIPH_GPIOA
+#define I2C1SCL_PORT            GPIO_PORTA_BASE
+#define I2C1SCL_PIN             GPIO_PIN_6
+
+#define I2C1SDA_PERIPH          SYSCTL_PERIPH_GPIOA
+#define I2C1SDA_PORT            GPIO_PORTA_BASE
+#define I2C1SDA_PIN             GPIO_PIN_7
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SSI1CLK_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1CLK_PORT            GPIO_PORTE_BASE
+#define SSI1CLK_PIN             GPIO_PIN_0
+
+#define SSI1FSS_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1FSS_PORT            GPIO_PORTE_BASE
+#define SSI1FSS_PIN             GPIO_PIN_1
+
+#define SSI1RX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1RX_PORT             GPIO_PORTE_BASE
+#define SSI1RX_PIN              GPIO_PIN_2
+
+#define SSI1TX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1TX_PORT             GPIO_PORTE_BASE
+#define SSI1TX_PIN              GPIO_PIN_3
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#endif // PART_LM3S2608
+
+//*****************************************************************************
+//
+// LM3S2616 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2616
+
+#define ADC0_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC0_PORT               GPIO_PORTE_BASE
+#define ADC0_PIN                GPIO_PIN_3
+
+#define ADC1_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC1_PORT               GPIO_PORTE_BASE
+#define ADC1_PIN                GPIO_PIN_2
+
+#define ADC2_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC2_PORT               GPIO_PORTE_BASE
+#define ADC2_PIN                GPIO_PIN_1
+
+#define ADC3_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC3_PORT               GPIO_PORTE_BASE
+#define ADC3_PIN                GPIO_PIN_0
+
+#define ADC4_PERIPH             SYSCTL_PERIPH_GPIOD
+#define ADC4_PORT               GPIO_PORTD_BASE
+#define ADC4_PIN                GPIO_PIN_3
+
+#define ADC5_PERIPH             SYSCTL_PERIPH_GPIOD
+#define ADC5_PORT               GPIO_PORTD_BASE
+#define ADC5_PIN                GPIO_PIN_2
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOC
+#define C0O_PORT                GPIO_PORTC_BASE
+#define C0O_PIN                 GPIO_PIN_5
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1O_PERIPH              SYSCTL_PERIPH_GPIOC
+#define C1O_PORT                GPIO_PORTC_BASE
+#define C1O_PIN                 GPIO_PIN_7
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_7
+
+#define CAN0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define CAN0RX_PORT             GPIO_PORTA_BASE
+#define CAN0RX_PIN              GPIO_PIN_4
+
+#define CAN0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define CAN0TX_PORT             GPIO_PORTA_BASE
+#define CAN0TX_PIN              GPIO_PIN_5
+
+#define FAULT0_PERIPH           SYSCTL_PERIPH_GPIOE
+#define FAULT0_PORT             GPIO_PORTE_BASE
+#define FAULT0_PIN              GPIO_PIN_4
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define IDX0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define IDX0_PORT               GPIO_PORTD_BASE
+#define IDX0_PIN                GPIO_PIN_0
+
+#define NMI_PERIPH              SYSCTL_PERIPH_GPIOB
+#define NMI_PORT                GPIO_PORTB_BASE
+#define NMI_PIN                 GPIO_PIN_7
+
+#define PHA0_PERIPH             SYSCTL_PERIPH_GPIOC
+#define PHA0_PORT               GPIO_PORTC_BASE
+#define PHA0_PIN                GPIO_PIN_4
+
+#define PHB0_PERIPH             SYSCTL_PERIPH_GPIOC
+#define PHB0_PORT               GPIO_PORTC_BASE
+#define PHB0_PIN                GPIO_PIN_6
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOA
+#define PWM0_PORT               GPIO_PORTA_BASE
+#define PWM0_PIN                GPIO_PIN_6
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOA
+#define PWM1_PORT               GPIO_PORTA_BASE
+#define PWM1_PIN                GPIO_PIN_7
+
+#define PWM2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define PWM2_PORT               GPIO_PORTB_BASE
+#define PWM2_PIN                GPIO_PIN_0
+
+#define PWM3_PERIPH             SYSCTL_PERIPH_GPIOB
+#define PWM3_PORT               GPIO_PORTB_BASE
+#define PWM3_PIN                GPIO_PIN_1
+
+#define PWM4_PERIPH             SYSCTL_PERIPH_GPIOA
+#define PWM4_PORT               GPIO_PORTA_BASE
+#define PWM4_PIN                GPIO_PIN_2
+
+#define PWM5_PERIPH             SYSCTL_PERIPH_GPIOA
+#define PWM5_PORT               GPIO_PORTA_BASE
+#define PWM5_PIN                GPIO_PIN_3
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#endif // PART_LM3S2616
+
+//*****************************************************************************
+//
+// LM3S2620 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2620
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOF
+#define C0O_PORT                GPIO_PORTF_BASE
+#define C0O_PIN                 GPIO_PIN_4
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1O_PERIPH              SYSCTL_PERIPH_GPIOE
+#define C1O_PORT                GPIO_PORTE_BASE
+#define C1O_PIN                 GPIO_PIN_6
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_5
+
+#define C2O_PERIPH              SYSCTL_PERIPH_GPIOE
+#define C2O_PORT                GPIO_PORTE_BASE
+#define C2O_PIN                 GPIO_PIN_7
+
+#define C2_MINUS_PERIPH         SYSCTL_PERIPH_GPIOC
+#define C2_MINUS_PORT           GPIO_PORTC_BASE
+#define C2_MINUS_PIN            GPIO_PIN_7
+
+#define C2_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C2_PLUS_PORT            GPIO_PORTC_BASE
+#define C2_PLUS_PIN             GPIO_PIN_6
+
+#define CAN0RX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0RX_PORT             GPIO_PORTD_BASE
+#define CAN0RX_PIN              GPIO_PIN_0
+
+#define CAN0TX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0TX_PORT             GPIO_PORTD_BASE
+#define CAN0TX_PIN              GPIO_PIN_1
+
+#define CAN1RX_PERIPH           SYSCTL_PERIPH_GPIOF
+#define CAN1RX_PORT             GPIO_PORTF_BASE
+#define CAN1RX_PIN              GPIO_PIN_0
+
+#define CAN1TX_PERIPH           SYSCTL_PERIPH_GPIOF
+#define CAN1TX_PORT             GPIO_PORTF_BASE
+#define CAN1TX_PIN              GPIO_PIN_1
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP1_PORT               GPIO_PORTA_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_1
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP3_PORT               GPIO_PORTD_BASE
+#define CCP3_PIN                GPIO_PIN_4
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP4_PORT               GPIO_PORTA_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOE
+#define CCP5_PORT               GPIO_PORTE_BASE
+#define CCP5_PIN                GPIO_PIN_5
+
+#define FAULT_PERIPH            SYSCTL_PERIPH_GPIOD
+#define FAULT_PORT              GPIO_PORTD_BASE
+#define FAULT_PIN               GPIO_PIN_6
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define IDX0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define IDX0_PORT               GPIO_PORTD_BASE
+#define IDX0_PIN                GPIO_PIN_7
+
+#define PHA0_PERIPH             SYSCTL_PERIPH_GPIOC
+#define PHA0_PORT               GPIO_PORTC_BASE
+#define PHA0_PIN                GPIO_PIN_4
+
+#define PHB0_PERIPH             SYSCTL_PERIPH_GPIOH
+#define PHB0_PORT               GPIO_PORTH_BASE
+#define PHB0_PIN                GPIO_PIN_3
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOG
+#define PWM0_PORT               GPIO_PORTG_BASE
+#define PWM0_PIN                GPIO_PIN_0
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOG
+#define PWM1_PORT               GPIO_PORTG_BASE
+#define PWM1_PIN                GPIO_PIN_1
+
+#define PWM2_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM2_PORT               GPIO_PORTD_BASE
+#define PWM2_PIN                GPIO_PIN_2
+
+#define PWM3_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM3_PORT               GPIO_PORTD_BASE
+#define PWM3_PIN                GPIO_PIN_3
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#endif // PART_LM3S2620
+
+//*****************************************************************************
+//
+// LM3S2637 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2637
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOD
+#define C0O_PORT                GPIO_PORTD_BASE
+#define C0O_PIN                 GPIO_PIN_7
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1O_PERIPH              SYSCTL_PERIPH_GPIOF
+#define C1O_PORT                GPIO_PORTF_BASE
+#define C1O_PIN                 GPIO_PIN_5
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_5
+
+#define C2_MINUS_PERIPH         SYSCTL_PERIPH_GPIOC
+#define C2_MINUS_PORT           GPIO_PORTC_BASE
+#define C2_MINUS_PIN            GPIO_PIN_7
+
+#define C2_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C2_PLUS_PORT            GPIO_PORTC_BASE
+#define C2_PLUS_PIN             GPIO_PIN_6
+
+#define CAN0RX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0RX_PORT             GPIO_PORTD_BASE
+#define CAN0RX_PIN              GPIO_PIN_0
+
+#define CAN0TX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0TX_PORT             GPIO_PORTD_BASE
+#define CAN0TX_PIN              GPIO_PIN_1
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP1_PORT               GPIO_PORTA_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_1
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP3_PORT               GPIO_PORTD_BASE
+#define CCP3_PIN                GPIO_PIN_4
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP4_PORT               GPIO_PORTA_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP5_PORT               GPIO_PORTC_BASE
+#define CCP5_PIN                GPIO_PIN_4
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#endif // PART_LM3S2637
+
+//*****************************************************************************
+//
+// LM3S2651 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2651
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOC
+#define C0O_PORT                GPIO_PORTC_BASE
+#define C0O_PIN                 GPIO_PIN_5
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define CAN0RX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0RX_PORT             GPIO_PORTD_BASE
+#define CAN0RX_PIN              GPIO_PIN_0
+
+#define CAN0TX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0TX_PORT             GPIO_PORTD_BASE
+#define CAN0TX_PIN              GPIO_PIN_1
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP1_PORT               GPIO_PORTA_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_1
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP3_PORT               GPIO_PORTC_BASE
+#define CCP3_PIN                GPIO_PIN_6
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP4_PORT               GPIO_PORTA_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP5_PORT               GPIO_PORTB_BASE
+#define CCP5_PIN                GPIO_PIN_5
+
+#define FAULT_PERIPH            SYSCTL_PERIPH_GPIOD
+#define FAULT_PORT              GPIO_PORTD_BASE
+#define FAULT_PIN               GPIO_PIN_6
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOF
+#define PWM0_PORT               GPIO_PORTF_BASE
+#define PWM0_PIN                GPIO_PIN_0
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOF
+#define PWM1_PORT               GPIO_PORTF_BASE
+#define PWM1_PIN                GPIO_PIN_1
+
+#define PWM2_PERIPH             SYSCTL_PERIPH_GPIOH
+#define PWM2_PORT               GPIO_PORTH_BASE
+#define PWM2_PIN                GPIO_PIN_0
+
+#define PWM3_PERIPH             SYSCTL_PERIPH_GPIOH
+#define PWM3_PORT               GPIO_PORTH_BASE
+#define PWM3_PIN                GPIO_PIN_1
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SSI1CLK_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1CLK_PORT            GPIO_PORTE_BASE
+#define SSI1CLK_PIN             GPIO_PIN_0
+
+#define SSI1FSS_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1FSS_PORT            GPIO_PORTE_BASE
+#define SSI1FSS_PIN             GPIO_PIN_1
+
+#define SSI1RX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1RX_PORT             GPIO_PORTE_BASE
+#define SSI1RX_PIN              GPIO_PIN_2
+
+#define SSI1TX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1TX_PORT             GPIO_PORTE_BASE
+#define SSI1TX_PIN              GPIO_PIN_3
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#define U2RX_PERIPH             SYSCTL_PERIPH_GPIOG
+#define U2RX_PORT               GPIO_PORTG_BASE
+#define U2RX_PIN                GPIO_PIN_0
+
+#define U2TX_PERIPH             SYSCTL_PERIPH_GPIOG
+#define U2TX_PORT               GPIO_PORTG_BASE
+#define U2TX_PIN                GPIO_PIN_1
+
+#endif // PART_LM3S2651
+
+//*****************************************************************************
+//
+// LM3S2671 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2671
+
+#define ADC0_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC0_PORT               GPIO_PORTE_BASE
+#define ADC0_PIN                GPIO_PIN_3
+
+#define ADC1_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC1_PORT               GPIO_PORTE_BASE
+#define ADC1_PIN                GPIO_PIN_2
+
+#define ADC2_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC2_PORT               GPIO_PORTE_BASE
+#define ADC2_PIN                GPIO_PIN_1
+
+#define ADC3_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC3_PORT               GPIO_PORTE_BASE
+#define ADC3_PIN                GPIO_PIN_0
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOB
+#define C0O_PORT                GPIO_PORTB_BASE
+#define C0O_PIN                 GPIO_PIN_6
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1O_PERIPH              SYSCTL_PERIPH_GPIOC
+#define C1O_PORT                GPIO_PORTC_BASE
+#define C1O_PIN                 GPIO_PIN_7
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_7
+
+#define C2O_PERIPH              SYSCTL_PERIPH_GPIOC
+#define C2O_PORT                GPIO_PORTC_BASE
+#define C2O_PIN                 GPIO_PIN_6
+
+#define C2_MINUS_PERIPH         SYSCTL_PERIPH_GPIOC
+#define C2_MINUS_PORT           GPIO_PORTC_BASE
+#define C2_MINUS_PIN            GPIO_PIN_5
+
+#define C2_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C2_PLUS_PORT            GPIO_PORTC_BASE
+#define C2_PLUS_PIN             GPIO_PIN_6
+
+#define CAN0RX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0RX_PORT             GPIO_PORTD_BASE
+#define CAN0RX_PIN              GPIO_PIN_0
+
+#define CAN0TX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0TX_PORT             GPIO_PORTD_BASE
+#define CAN0TX_PIN              GPIO_PIN_1
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP1_PORT               GPIO_PORTB_BASE
+#define CCP1_PIN                GPIO_PIN_1
+
+#define FAULT0_PERIPH           SYSCTL_PERIPH_GPIOE
+#define FAULT0_PORT             GPIO_PORTE_BASE
+#define FAULT0_PIN              GPIO_PIN_4
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define NMI_PERIPH              SYSCTL_PERIPH_GPIOB
+#define NMI_PORT                GPIO_PORTB_BASE
+#define NMI_PIN                 GPIO_PIN_7
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOA
+#define PWM0_PORT               GPIO_PORTA_BASE
+#define PWM0_PIN                GPIO_PIN_6
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOA
+#define PWM1_PORT               GPIO_PORTA_BASE
+#define PWM1_PIN                GPIO_PIN_7
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#endif // PART_LM3S2671
+
+//*****************************************************************************
+//
+// LM3S2678 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2678
+
+#define ADC0_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC0_PORT               GPIO_PORTE_BASE
+#define ADC0_PIN                GPIO_PIN_3
+
+#define ADC1_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC1_PORT               GPIO_PORTE_BASE
+#define ADC1_PIN                GPIO_PIN_2
+
+#define ADC2_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC2_PORT               GPIO_PORTE_BASE
+#define ADC2_PIN                GPIO_PIN_1
+
+#define ADC3_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC3_PORT               GPIO_PORTE_BASE
+#define ADC3_PIN                GPIO_PIN_0
+
+#define ADC4_PERIPH             SYSCTL_PERIPH_GPIOD
+#define ADC4_PORT               GPIO_PORTD_BASE
+#define ADC4_PIN                GPIO_PIN_3
+
+#define ADC5_PERIPH             SYSCTL_PERIPH_GPIOD
+#define ADC5_PORT               GPIO_PORTD_BASE
+#define ADC5_PIN                GPIO_PIN_2
+
+#define ADC6_PERIPH             SYSCTL_PERIPH_GPIOD
+#define ADC6_PORT               GPIO_PORTD_BASE
+#define ADC6_PIN                GPIO_PIN_1
+
+#define ADC7_PERIPH             SYSCTL_PERIPH_GPIOD
+#define ADC7_PORT               GPIO_PORTD_BASE
+#define ADC7_PIN                GPIO_PIN_0
+
+#define CAN0RX_PERIPH           SYSCTL_PERIPH_GPIOB
+#define CAN0RX_PORT             GPIO_PORTB_BASE
+#define CAN0RX_PIN              GPIO_PIN_4
+
+#define CAN0TX_PERIPH           SYSCTL_PERIPH_GPIOB
+#define CAN0TX_PORT             GPIO_PORTB_BASE
+#define CAN0TX_PIN              GPIO_PIN_5
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP0_PORT               GPIO_PORTC_BASE
+#define CCP0_PIN                GPIO_PIN_6
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP1_PORT               GPIO_PORTC_BASE
+#define CCP1_PIN                GPIO_PIN_5
+
+#define FAULT0_PERIPH           SYSCTL_PERIPH_GPIOB
+#define FAULT0_PORT             GPIO_PORTB_BASE
+#define FAULT0_PIN              GPIO_PIN_3
+
+#define FAULT1_PERIPH           SYSCTL_PERIPH_GPIOB
+#define FAULT1_PORT             GPIO_PORTB_BASE
+#define FAULT1_PIN              GPIO_PIN_6
+
+#define IDX0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define IDX0_PORT               GPIO_PORTB_BASE
+#define IDX0_PIN                GPIO_PIN_2
+
+#define NMI_PERIPH              SYSCTL_PERIPH_GPIOB
+#define NMI_PORT                GPIO_PORTB_BASE
+#define NMI_PIN                 GPIO_PIN_7
+
+#define PHA0_PERIPH             SYSCTL_PERIPH_GPIOC
+#define PHA0_PORT               GPIO_PORTC_BASE
+#define PHA0_PIN                GPIO_PIN_4
+
+#define PHB0_PERIPH             SYSCTL_PERIPH_GPIOC
+#define PHB0_PORT               GPIO_PORTC_BASE
+#define PHB0_PIN                GPIO_PIN_7
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOA
+#define PWM0_PORT               GPIO_PORTA_BASE
+#define PWM0_PIN                GPIO_PIN_6
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOA
+#define PWM1_PORT               GPIO_PORTA_BASE
+#define PWM1_PIN                GPIO_PIN_7
+
+#define PWM2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define PWM2_PORT               GPIO_PORTB_BASE
+#define PWM2_PIN                GPIO_PIN_0
+
+#define PWM3_PERIPH             SYSCTL_PERIPH_GPIOB
+#define PWM3_PORT               GPIO_PORTB_BASE
+#define PWM3_PIN                GPIO_PIN_1
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#endif // PART_LM3S2678
+
+//*****************************************************************************
+//
+// LM3S2730 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2730
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOD
+#define C0O_PORT                GPIO_PORTD_BASE
+#define C0O_PIN                 GPIO_PIN_7
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1O_PERIPH              SYSCTL_PERIPH_GPIOE
+#define C1O_PORT                GPIO_PORTE_BASE
+#define C1O_PIN                 GPIO_PIN_6
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_5
+
+#define CAN0RX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0RX_PORT             GPIO_PORTD_BASE
+#define CAN0RX_PIN              GPIO_PIN_0
+
+#define CAN0TX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0TX_PORT             GPIO_PORTD_BASE
+#define CAN0TX_PIN              GPIO_PIN_1
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP1_PORT               GPIO_PORTA_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_1
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP3_PORT               GPIO_PORTC_BASE
+#define CCP3_PIN                GPIO_PIN_6
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#endif // PART_LM3S2730
+
+//*****************************************************************************
+//
+// LM3S2739 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2739
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOC
+#define C0O_PORT                GPIO_PORTC_BASE
+#define C0O_PIN                 GPIO_PIN_5
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define CAN0RX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0RX_PORT             GPIO_PORTD_BASE
+#define CAN0RX_PIN              GPIO_PIN_0
+
+#define CAN0TX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0TX_PORT             GPIO_PORTD_BASE
+#define CAN0TX_PIN              GPIO_PIN_1
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP1_PORT               GPIO_PORTA_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_1
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP3_PORT               GPIO_PORTC_BASE
+#define CCP3_PIN                GPIO_PIN_6
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP4_PORT               GPIO_PORTA_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP5_PORT               GPIO_PORTB_BASE
+#define CCP5_PIN                GPIO_PIN_5
+
+#define FAULT_PERIPH            SYSCTL_PERIPH_GPIOD
+#define FAULT_PORT              GPIO_PORTD_BASE
+#define FAULT_PIN               GPIO_PIN_6
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define IDX0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define IDX0_PORT               GPIO_PORTD_BASE
+#define IDX0_PIN                GPIO_PIN_7
+
+#define PHA0_PERIPH             SYSCTL_PERIPH_GPIOC
+#define PHA0_PORT               GPIO_PORTC_BASE
+#define PHA0_PIN                GPIO_PIN_4
+
+#define PHB0_PERIPH             SYSCTL_PERIPH_GPIOC
+#define PHB0_PORT               GPIO_PORTC_BASE
+#define PHB0_PIN                GPIO_PIN_7
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOF
+#define PWM0_PORT               GPIO_PORTF_BASE
+#define PWM0_PIN                GPIO_PIN_0
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOF
+#define PWM1_PORT               GPIO_PORTF_BASE
+#define PWM1_PIN                GPIO_PIN_1
+
+#define PWM2_PERIPH             SYSCTL_PERIPH_GPIOH
+#define PWM2_PORT               GPIO_PORTH_BASE
+#define PWM2_PIN                GPIO_PIN_0
+
+#define PWM3_PERIPH             SYSCTL_PERIPH_GPIOH
+#define PWM3_PORT               GPIO_PORTH_BASE
+#define PWM3_PIN                GPIO_PIN_1
+
+#define PWM4_PERIPH             SYSCTL_PERIPH_GPIOE
+#define PWM4_PORT               GPIO_PORTE_BASE
+#define PWM4_PIN                GPIO_PIN_0
+
+#define PWM5_PERIPH             SYSCTL_PERIPH_GPIOE
+#define PWM5_PORT               GPIO_PORTE_BASE
+#define PWM5_PIN                GPIO_PIN_1
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#endif // PART_LM3S2739
+
+//*****************************************************************************
+//
+// LM3S2776 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2776
+
+#define ADC0_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC0_PORT               GPIO_PORTE_BASE
+#define ADC0_PIN                GPIO_PIN_3
+
+#define ADC1_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC1_PORT               GPIO_PORTE_BASE
+#define ADC1_PIN                GPIO_PIN_2
+
+#define ADC2_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC2_PORT               GPIO_PORTE_BASE
+#define ADC2_PIN                GPIO_PIN_1
+
+#define ADC3_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC3_PORT               GPIO_PORTE_BASE
+#define ADC3_PIN                GPIO_PIN_0
+
+#define ADC4_PERIPH             SYSCTL_PERIPH_GPIOD
+#define ADC4_PORT               GPIO_PORTD_BASE
+#define ADC4_PIN                GPIO_PIN_3
+
+#define ADC5_PERIPH             SYSCTL_PERIPH_GPIOD
+#define ADC5_PORT               GPIO_PORTD_BASE
+#define ADC5_PIN                GPIO_PIN_2
+
+#define CAN0RX_PERIPH           SYSCTL_PERIPH_GPIOB
+#define CAN0RX_PORT             GPIO_PORTB_BASE
+#define CAN0RX_PIN              GPIO_PIN_4
+
+#define CAN0TX_PERIPH           SYSCTL_PERIPH_GPIOB
+#define CAN0TX_PORT             GPIO_PORTB_BASE
+#define CAN0TX_PIN              GPIO_PIN_5
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP0_PORT               GPIO_PORTC_BASE
+#define CCP0_PIN                GPIO_PIN_7
+
+#define FAULT0_PERIPH           SYSCTL_PERIPH_GPIOE
+#define FAULT0_PORT             GPIO_PORTE_BASE
+#define FAULT0_PIN              GPIO_PIN_4
+
+#define FAULT1_PERIPH           SYSCTL_PERIPH_GPIOB
+#define FAULT1_PORT             GPIO_PORTB_BASE
+#define FAULT1_PIN              GPIO_PIN_6
+
+#define FAULT2_PERIPH           SYSCTL_PERIPH_GPIOC
+#define FAULT2_PORT             GPIO_PORTC_BASE
+#define FAULT2_PIN              GPIO_PIN_5
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define NMI_PERIPH              SYSCTL_PERIPH_GPIOB
+#define NMI_PORT                GPIO_PORTB_BASE
+#define NMI_PIN                 GPIO_PIN_7
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM0_PORT               GPIO_PORTD_BASE
+#define PWM0_PIN                GPIO_PIN_0
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM1_PORT               GPIO_PORTD_BASE
+#define PWM1_PIN                GPIO_PIN_1
+
+#define PWM2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define PWM2_PORT               GPIO_PORTB_BASE
+#define PWM2_PIN                GPIO_PIN_0
+
+#define PWM3_PERIPH             SYSCTL_PERIPH_GPIOB
+#define PWM3_PORT               GPIO_PORTB_BASE
+#define PWM3_PIN                GPIO_PIN_1
+
+#define PWM4_PERIPH             SYSCTL_PERIPH_GPIOA
+#define PWM4_PORT               GPIO_PORTA_BASE
+#define PWM4_PIN                GPIO_PIN_6
+
+#define PWM5_PERIPH             SYSCTL_PERIPH_GPIOA
+#define PWM5_PORT               GPIO_PORTA_BASE
+#define PWM5_PIN                GPIO_PIN_7
+
+#define PWM6_PERIPH             SYSCTL_PERIPH_GPIOC
+#define PWM6_PORT               GPIO_PORTC_BASE
+#define PWM6_PIN                GPIO_PIN_4
+
+#define PWM7_PERIPH             SYSCTL_PERIPH_GPIOC
+#define PWM7_PORT               GPIO_PORTC_BASE
+#define PWM7_PIN                GPIO_PIN_6
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#endif // PART_LM3S2776
+
+//*****************************************************************************
+//
+// LM3S2793 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2793
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_PWM4           0x00000804
+#define GPIO_PA2_I2S0RXSD       0x00000809
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_PWM5           0x00000C04
+#define GPIO_PA3_I2S0RXMCLK     0x00000C09
+
+#define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_PWM6           0x00001004
+#define GPIO_PA4_CAN0RX         0x00001005
+#define GPIO_PA4_I2S0TXSCK      0x00001009
+
+#define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_PWM7           0x00001404
+#define GPIO_PA5_CAN0TX         0x00001405
+#define GPIO_PA5_I2S0TXWS       0x00001409
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_PWM0           0x00001804
+#define GPIO_PA6_PWM4           0x00001805
+#define GPIO_PA6_CAN0RX         0x00001806
+#define GPIO_PA6_U1CTS          0x00001809
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_PWM1           0x00001C04
+#define GPIO_PA7_PWM5           0x00001C05
+#define GPIO_PA7_CAN0TX         0x00001C06
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_U1DCD          0x00001C09
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_PWM2           0x00010002
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_PWM3           0x00010402
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_IDX0           0x00010802
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_FAULT0         0x00010C02
+#define GPIO_PB3_FAULT3         0x00010C04
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_CAN0RX         0x00011005
+#define GPIO_PB4_IDX0           0x00011006
+#define GPIO_PB4_U1RX           0x00011007
+#define GPIO_PB4_EPI0S23        0x00011008
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CAN0TX         0x00011405
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+#define GPIO_PB5_EPI0S22        0x00011408
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_FAULT1         0x00011804
+#define GPIO_PB6_IDX0           0x00011805
+#define GPIO_PB6_CCP5           0x00011806
+#define GPIO_PB6_I2S0TXSCK      0x00011809
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_PHA0           0x00021002
+#define GPIO_PC4_PWM6           0x00021004
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_EPI0S2         0x00021008
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_FAULT2         0x00021404
+#define GPIO_PC5_CCP3           0x00021405
+#define GPIO_PC5_EPI0S3         0x00021408
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_PHB0           0x00021802
+#define GPIO_PC6_C2O            0x00021803
+#define GPIO_PC6_PWM7           0x00021804
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+#define GPIO_PC6_EPI0S4         0x00021808
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_PHB0           0x00021C02
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_C1O            0x00021C07
+#define GPIO_PC7_EPI0S5         0x00021C08
+
+#define GPIO_PD0_PWM0           0x00030001
+#define GPIO_PD0_CAN0RX         0x00030002
+#define GPIO_PD0_IDX0           0x00030003
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+#define GPIO_PD0_I2S0RXSCK      0x00030008
+#define GPIO_PD0_U1CTS          0x00030009
+
+#define GPIO_PD1_PWM1           0x00030401
+#define GPIO_PD1_CAN0TX         0x00030402
+#define GPIO_PD1_PHA0           0x00030403
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_I2S0RXWS       0x00030408
+#define GPIO_PD1_U1DCD          0x00030409
+#define GPIO_PD1_CCP2           0x0003040A
+#define GPIO_PD1_PHB1           0x0003040B
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_PWM2           0x00030803
+#define GPIO_PD2_CCP5           0x00030804
+#define GPIO_PD2_EPI0S20        0x00030808
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_PWM3           0x00030C03
+#define GPIO_PD3_CCP0           0x00030C04
+#define GPIO_PD3_EPI0S21        0x00030C08
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+#define GPIO_PD4_I2S0RXSD       0x00031008
+#define GPIO_PD4_U1RI           0x00031009
+#define GPIO_PD4_EPI0S19        0x0003100A
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_I2S0RXMCLK     0x00031408
+#define GPIO_PD5_U2RX           0x00031409
+#define GPIO_PD5_EPI0S28        0x0003140A
+
+#define GPIO_PD6_FAULT0         0x00031801
+#define GPIO_PD6_I2S0TXSCK      0x00031808
+#define GPIO_PD6_U2TX           0x00031809
+#define GPIO_PD6_EPI0S29        0x0003180A
+
+#define GPIO_PD7_IDX0           0x00031C01
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+#define GPIO_PD7_I2S0TXWS       0x00031C08
+#define GPIO_PD7_U1DTR          0x00031C09
+#define GPIO_PD7_EPI0S30        0x00031C0A
+
+#define GPIO_PE0_PWM4           0x00040001
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+#define GPIO_PE0_EPI0S8         0x00040008
+
+#define GPIO_PE1_PWM5           0x00040401
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_FAULT0         0x00040403
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+#define GPIO_PE1_EPI0S9         0x00040408
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_PHB1           0x00040803
+#define GPIO_PE2_PHA0           0x00040804
+#define GPIO_PE2_CCP2           0x00040805
+#define GPIO_PE2_EPI0S24        0x00040808
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_PHA1           0x00040C03
+#define GPIO_PE3_PHB0           0x00040C04
+#define GPIO_PE3_CCP7           0x00040C05
+#define GPIO_PE3_EPI0S25        0x00040C08
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_FAULT0         0x00041004
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+#define GPIO_PE4_I2S0TXWS       0x00041009
+
+#define GPIO_PE5_CCP5           0x00041401
+#define GPIO_PE5_I2S0TXSD       0x00041409
+
+#define GPIO_PE6_PWM4           0x00041801
+#define GPIO_PE6_C1O            0x00041802
+#define GPIO_PE6_U1CTS          0x00041809
+
+#define GPIO_PE7_PWM5           0x00041C01
+#define GPIO_PE7_C2O            0x00041C02
+#define GPIO_PE7_U1DCD          0x00041C09
+
+#define GPIO_PF0_CAN1RX         0x00050001
+#define GPIO_PF0_PHB0           0x00050002
+#define GPIO_PF0_PWM0           0x00050003
+#define GPIO_PF0_I2S0TXSD       0x00050008
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_CAN1TX         0x00050401
+#define GPIO_PF1_IDX1           0x00050402
+#define GPIO_PF1_PWM1           0x00050403
+#define GPIO_PF1_I2S0TXMCLK     0x00050408
+#define GPIO_PF1_U1RTS          0x00050409
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_PWM4           0x00050802
+#define GPIO_PF2_PWM2           0x00050804
+#define GPIO_PF2_SSI1CLK        0x00050809
+
+#define GPIO_PF3_PWM5           0x00050C02
+#define GPIO_PF3_PWM3           0x00050C04
+#define GPIO_PF3_SSI1FSS        0x00050C09
+
+#define GPIO_PF4_CCP0           0x00051001
+#define GPIO_PF4_C0O            0x00051002
+#define GPIO_PF4_FAULT0         0x00051004
+#define GPIO_PF4_EPI0S12        0x00051008
+#define GPIO_PF4_SSI1RX         0x00051009
+
+#define GPIO_PF5_CCP2           0x00051401
+#define GPIO_PF5_C1O            0x00051402
+#define GPIO_PF5_EPI0S15        0x00051408
+#define GPIO_PF5_SSI1TX         0x00051409
+
+#define GPIO_PF6_CCP1           0x00051801
+#define GPIO_PF6_C2O            0x00051802
+#define GPIO_PF6_PHA0           0x00051804
+#define GPIO_PF6_I2S0TXMCLK     0x00051809
+#define GPIO_PF6_U1RTS          0x0005180A
+
+#define GPIO_PF7_CCP4           0x00051C01
+#define GPIO_PF7_PHB0           0x00051C04
+#define GPIO_PF7_EPI0S12        0x00051C08
+#define GPIO_PF7_FAULT1         0x00051C09
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_PWM0           0x00060002
+#define GPIO_PG0_I2C1SCL        0x00060003
+#define GPIO_PG0_PWM4           0x00060004
+#define GPIO_PG0_EPI0S13        0x00060008
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_PWM1           0x00060402
+#define GPIO_PG1_I2C1SDA        0x00060403
+#define GPIO_PG1_PWM5           0x00060404
+#define GPIO_PG1_EPI0S14        0x00060408
+
+#define GPIO_PG2_PWM0           0x00060801
+#define GPIO_PG2_FAULT0         0x00060804
+#define GPIO_PG2_IDX1           0x00060808
+#define GPIO_PG2_I2S0RXSD       0x00060809
+
+#define GPIO_PG3_PWM1           0x00060C01
+#define GPIO_PG3_FAULT2         0x00060C04
+#define GPIO_PG3_FAULT0         0x00060C08
+#define GPIO_PG3_I2S0RXMCLK     0x00060C09
+
+#define GPIO_PG4_CCP3           0x00061001
+#define GPIO_PG4_FAULT1         0x00061004
+#define GPIO_PG4_EPI0S15        0x00061008
+#define GPIO_PG4_PWM6           0x00061009
+#define GPIO_PG4_U1RI           0x0006100A
+
+#define GPIO_PG5_CCP5           0x00061401
+#define GPIO_PG5_IDX0           0x00061404
+#define GPIO_PG5_FAULT1         0x00061405
+#define GPIO_PG5_PWM7           0x00061408
+#define GPIO_PG5_I2S0RXSCK      0x00061409
+#define GPIO_PG5_U1DTR          0x0006140A
+
+#define GPIO_PG6_PHA1           0x00061801
+#define GPIO_PG6_PWM6           0x00061804
+#define GPIO_PG6_FAULT1         0x00061808
+#define GPIO_PG6_I2S0RXWS       0x00061809
+#define GPIO_PG6_U1RI           0x0006180A
+
+#define GPIO_PG7_PHB1           0x00061C01
+#define GPIO_PG7_PWM7           0x00061C04
+#define GPIO_PG7_CCP5           0x00061C08
+#define GPIO_PG7_EPI0S31        0x00061C09
+
+#define GPIO_PH0_CCP6           0x00070001
+#define GPIO_PH0_PWM2           0x00070002
+#define GPIO_PH0_EPI0S6         0x00070008
+#define GPIO_PH0_PWM4           0x00070009
+
+#define GPIO_PH1_CCP7           0x00070401
+#define GPIO_PH1_PWM3           0x00070402
+#define GPIO_PH1_EPI0S7         0x00070408
+#define GPIO_PH1_PWM5           0x00070409
+
+#define GPIO_PH2_IDX1           0x00070801
+#define GPIO_PH2_C1O            0x00070802
+#define GPIO_PH2_FAULT3         0x00070804
+#define GPIO_PH2_EPI0S1         0x00070808
+
+#define GPIO_PH3_PHB0           0x00070C01
+#define GPIO_PH3_FAULT0         0x00070C02
+#define GPIO_PH3_EPI0S0         0x00070C08
+
+#define GPIO_PH4_EPI0S10        0x00071008
+#define GPIO_PH4_SSI1CLK        0x0007100B
+
+#define GPIO_PH5_EPI0S11        0x00071408
+#define GPIO_PH5_FAULT2         0x0007140A
+#define GPIO_PH5_SSI1FSS        0x0007140B
+
+#define GPIO_PH6_EPI0S26        0x00071808
+#define GPIO_PH6_PWM4           0x0007180A
+#define GPIO_PH6_SSI1RX         0x0007180B
+
+#define GPIO_PH7_EPI0S27        0x00071C08
+#define GPIO_PH7_PWM5           0x00071C0A
+#define GPIO_PH7_SSI1TX         0x00071C0B
+
+#define GPIO_PJ0_EPI0S16        0x00080008
+#define GPIO_PJ0_PWM0           0x0008000A
+#define GPIO_PJ0_I2C1SCL        0x0008000B
+
+#define GPIO_PJ1_EPI0S17        0x00080408
+#define GPIO_PJ1_PWM1           0x0008040A
+#define GPIO_PJ1_I2C1SDA        0x0008040B
+
+#define GPIO_PJ2_EPI0S18        0x00080808
+#define GPIO_PJ2_CCP0           0x00080809
+#define GPIO_PJ2_FAULT0         0x0008080A
+
+#endif // PART_LM3S2793
+
+//*****************************************************************************
+//
+// LM3S2911 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2911
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOF
+#define C0O_PORT                GPIO_PORTF_BASE
+#define C0O_PIN                 GPIO_PIN_4
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1O_PERIPH              SYSCTL_PERIPH_GPIOE
+#define C1O_PORT                GPIO_PORTE_BASE
+#define C1O_PIN                 GPIO_PIN_6
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_5
+
+#define CAN0RX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0RX_PORT             GPIO_PORTD_BASE
+#define CAN0RX_PIN              GPIO_PIN_0
+
+#define CAN0TX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0TX_PORT             GPIO_PORTD_BASE
+#define CAN0TX_PIN              GPIO_PIN_1
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP1_PORT               GPIO_PORTD_BASE
+#define CCP1_PIN                GPIO_PIN_7
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_1
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP3_PORT               GPIO_PORTC_BASE
+#define CCP3_PIN                GPIO_PIN_6
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP4_PORT               GPIO_PORTC_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP5_PORT               GPIO_PORTC_BASE
+#define CCP5_PIN                GPIO_PIN_4
+
+#define CCP6_PERIPH             SYSCTL_PERIPH_GPIOH
+#define CCP6_PORT               GPIO_PORTH_BASE
+#define CCP6_PIN                GPIO_PIN_0
+
+#define CCP7_PERIPH             SYSCTL_PERIPH_GPIOH
+#define CCP7_PORT               GPIO_PORTH_BASE
+#define CCP7_PIN                GPIO_PIN_1
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define I2C1SCL_PERIPH          SYSCTL_PERIPH_GPIOA
+#define I2C1SCL_PORT            GPIO_PORTA_BASE
+#define I2C1SCL_PIN             GPIO_PIN_6
+
+#define I2C1SDA_PERIPH          SYSCTL_PERIPH_GPIOA
+#define I2C1SDA_PORT            GPIO_PORTA_BASE
+#define I2C1SDA_PIN             GPIO_PIN_7
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SSI1CLK_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1CLK_PORT            GPIO_PORTE_BASE
+#define SSI1CLK_PIN             GPIO_PIN_0
+
+#define SSI1FSS_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1FSS_PORT            GPIO_PORTE_BASE
+#define SSI1FSS_PIN             GPIO_PIN_1
+
+#define SSI1RX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1RX_PORT             GPIO_PORTE_BASE
+#define SSI1RX_PIN              GPIO_PIN_2
+
+#define SSI1TX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1TX_PORT             GPIO_PORTE_BASE
+#define SSI1TX_PIN              GPIO_PIN_3
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#define U2RX_PERIPH             SYSCTL_PERIPH_GPIOG
+#define U2RX_PORT               GPIO_PORTG_BASE
+#define U2RX_PIN                GPIO_PIN_0
+
+#define U2TX_PERIPH             SYSCTL_PERIPH_GPIOG
+#define U2TX_PORT               GPIO_PORTG_BASE
+#define U2TX_PIN                GPIO_PIN_1
+
+#endif // PART_LM3S2911
+
+//*****************************************************************************
+//
+// LM3S2918 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2918
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOF
+#define C0O_PORT                GPIO_PORTF_BASE
+#define C0O_PIN                 GPIO_PIN_4
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1O_PERIPH              SYSCTL_PERIPH_GPIOF
+#define C1O_PORT                GPIO_PORTF_BASE
+#define C1O_PIN                 GPIO_PIN_5
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_5
+
+#define CAN0RX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0RX_PORT             GPIO_PORTD_BASE
+#define CAN0RX_PIN              GPIO_PIN_0
+
+#define CAN0TX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0TX_PORT             GPIO_PORTD_BASE
+#define CAN0TX_PIN              GPIO_PIN_1
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOF
+#define CCP1_PORT               GPIO_PORTF_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_1
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP3_PORT               GPIO_PORTC_BASE
+#define CCP3_PIN                GPIO_PIN_6
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP4_PORT               GPIO_PORTC_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP5_PORT               GPIO_PORTC_BASE
+#define CCP5_PIN                GPIO_PIN_4
+
+#define CCP6_PERIPH             SYSCTL_PERIPH_GPIOH
+#define CCP6_PORT               GPIO_PORTH_BASE
+#define CCP6_PIN                GPIO_PIN_0
+
+#define CCP7_PERIPH             SYSCTL_PERIPH_GPIOH
+#define CCP7_PORT               GPIO_PORTH_BASE
+#define CCP7_PIN                GPIO_PIN_1
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define I2C1SCL_PERIPH          SYSCTL_PERIPH_GPIOA
+#define I2C1SCL_PORT            GPIO_PORTA_BASE
+#define I2C1SCL_PIN             GPIO_PIN_6
+
+#define I2C1SDA_PERIPH          SYSCTL_PERIPH_GPIOA
+#define I2C1SDA_PORT            GPIO_PORTA_BASE
+#define I2C1SDA_PIN             GPIO_PIN_7
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SSI1CLK_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1CLK_PORT            GPIO_PORTE_BASE
+#define SSI1CLK_PIN             GPIO_PIN_0
+
+#define SSI1FSS_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1FSS_PORT            GPIO_PORTE_BASE
+#define SSI1FSS_PIN             GPIO_PIN_1
+
+#define SSI1RX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1RX_PORT             GPIO_PORTE_BASE
+#define SSI1RX_PIN              GPIO_PIN_2
+
+#define SSI1TX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1TX_PORT             GPIO_PORTE_BASE
+#define SSI1TX_PIN              GPIO_PIN_3
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#endif // PART_LM3S2918
+
+//*****************************************************************************
+//
+// LM3S2939 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2939
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOF
+#define C0O_PORT                GPIO_PORTF_BASE
+#define C0O_PIN                 GPIO_PIN_4
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1O_PERIPH              SYSCTL_PERIPH_GPIOF
+#define C1O_PORT                GPIO_PORTF_BASE
+#define C1O_PIN                 GPIO_PIN_5
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_5
+
+#define C2_MINUS_PERIPH         SYSCTL_PERIPH_GPIOC
+#define C2_MINUS_PORT           GPIO_PORTC_BASE
+#define C2_MINUS_PIN            GPIO_PIN_7
+
+#define C2_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C2_PLUS_PORT            GPIO_PORTC_BASE
+#define C2_PLUS_PIN             GPIO_PIN_6
+
+#define CAN0RX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0RX_PORT             GPIO_PORTD_BASE
+#define CAN0RX_PIN              GPIO_PIN_0
+
+#define CAN0TX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0TX_PORT             GPIO_PORTD_BASE
+#define CAN0TX_PIN              GPIO_PIN_1
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP1_PORT               GPIO_PORTA_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_1
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP3_PORT               GPIO_PORTD_BASE
+#define CCP3_PIN                GPIO_PIN_4
+
+#define FAULT_PERIPH            SYSCTL_PERIPH_GPIOD
+#define FAULT_PORT              GPIO_PORTD_BASE
+#define FAULT_PIN               GPIO_PIN_6
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define IDX0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define IDX0_PORT               GPIO_PORTD_BASE
+#define IDX0_PIN                GPIO_PIN_7
+
+#define PHA0_PERIPH             SYSCTL_PERIPH_GPIOC
+#define PHA0_PORT               GPIO_PORTC_BASE
+#define PHA0_PIN                GPIO_PIN_4
+
+#define PHB0_PERIPH             SYSCTL_PERIPH_GPIOH
+#define PHB0_PORT               GPIO_PORTH_BASE
+#define PHB0_PIN                GPIO_PIN_3
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOF
+#define PWM0_PORT               GPIO_PORTF_BASE
+#define PWM0_PIN                GPIO_PIN_0
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOF
+#define PWM1_PORT               GPIO_PORTF_BASE
+#define PWM1_PIN                GPIO_PIN_1
+
+#define PWM2_PERIPH             SYSCTL_PERIPH_GPIOH
+#define PWM2_PORT               GPIO_PORTH_BASE
+#define PWM2_PIN                GPIO_PIN_0
+
+#define PWM3_PERIPH             SYSCTL_PERIPH_GPIOH
+#define PWM3_PORT               GPIO_PORTH_BASE
+#define PWM3_PIN                GPIO_PIN_1
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#define U2RX_PERIPH             SYSCTL_PERIPH_GPIOG
+#define U2RX_PORT               GPIO_PORTG_BASE
+#define U2RX_PIN                GPIO_PIN_0
+
+#define U2TX_PERIPH             SYSCTL_PERIPH_GPIOG
+#define U2TX_PORT               GPIO_PORTG_BASE
+#define U2TX_PIN                GPIO_PIN_1
+
+#endif // PART_LM3S2939
+
+//*****************************************************************************
+//
+// LM3S2948 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2948
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOF
+#define C0O_PORT                GPIO_PORTF_BASE
+#define C0O_PIN                 GPIO_PIN_4
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_5
+
+#define C2_MINUS_PERIPH         SYSCTL_PERIPH_GPIOC
+#define C2_MINUS_PORT           GPIO_PORTC_BASE
+#define C2_MINUS_PIN            GPIO_PIN_7
+
+#define C2_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C2_PLUS_PORT            GPIO_PORTC_BASE
+#define C2_PLUS_PIN             GPIO_PIN_6
+
+#define CAN0RX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0RX_PORT             GPIO_PORTD_BASE
+#define CAN0RX_PIN              GPIO_PIN_0
+
+#define CAN0TX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0TX_PORT             GPIO_PORTD_BASE
+#define CAN0TX_PIN              GPIO_PIN_1
+
+#define CAN1RX_PERIPH           SYSCTL_PERIPH_GPIOF
+#define CAN1RX_PORT             GPIO_PORTF_BASE
+#define CAN1RX_PIN              GPIO_PIN_0
+
+#define CAN1TX_PERIPH           SYSCTL_PERIPH_GPIOF
+#define CAN1TX_PORT             GPIO_PORTF_BASE
+#define CAN1TX_PIN              GPIO_PIN_1
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP1_PORT               GPIO_PORTA_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_1
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOG
+#define CCP3_PORT               GPIO_PORTG_BASE
+#define CCP3_PIN                GPIO_PIN_4
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP4_PORT               GPIO_PORTA_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP5_PORT               GPIO_PORTC_BASE
+#define CCP5_PIN                GPIO_PIN_4
+
+#define CCP6_PERIPH             SYSCTL_PERIPH_GPIOH
+#define CCP6_PORT               GPIO_PORTH_BASE
+#define CCP6_PIN                GPIO_PIN_0
+
+#define CCP7_PERIPH             SYSCTL_PERIPH_GPIOH
+#define CCP7_PORT               GPIO_PORTH_BASE
+#define CCP7_PIN                GPIO_PIN_1
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SSI1CLK_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1CLK_PORT            GPIO_PORTE_BASE
+#define SSI1CLK_PIN             GPIO_PIN_0
+
+#define SSI1FSS_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1FSS_PORT            GPIO_PORTE_BASE
+#define SSI1FSS_PIN             GPIO_PIN_1
+
+#define SSI1RX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1RX_PORT             GPIO_PORTE_BASE
+#define SSI1RX_PIN              GPIO_PIN_2
+
+#define SSI1TX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1TX_PORT             GPIO_PORTE_BASE
+#define SSI1TX_PIN              GPIO_PIN_3
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#define U2RX_PERIPH             SYSCTL_PERIPH_GPIOG
+#define U2RX_PORT               GPIO_PORTG_BASE
+#define U2RX_PIN                GPIO_PIN_0
+
+#define U2TX_PERIPH             SYSCTL_PERIPH_GPIOG
+#define U2TX_PORT               GPIO_PORTG_BASE
+#define U2TX_PIN                GPIO_PIN_1
+
+#endif // PART_LM3S2948
+
+//*****************************************************************************
+//
+// LM3S2950 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2950
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOF
+#define C0O_PORT                GPIO_PORTF_BASE
+#define C0O_PIN                 GPIO_PIN_4
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1O_PERIPH              SYSCTL_PERIPH_GPIOF
+#define C1O_PORT                GPIO_PORTF_BASE
+#define C1O_PIN                 GPIO_PIN_5
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_5
+
+#define C2O_PERIPH              SYSCTL_PERIPH_GPIOF
+#define C2O_PORT                GPIO_PORTF_BASE
+#define C2O_PIN                 GPIO_PIN_6
+
+#define C2_MINUS_PERIPH         SYSCTL_PERIPH_GPIOC
+#define C2_MINUS_PORT           GPIO_PORTC_BASE
+#define C2_MINUS_PIN            GPIO_PIN_7
+
+#define C2_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C2_PLUS_PORT            GPIO_PORTC_BASE
+#define C2_PLUS_PIN             GPIO_PIN_6
+
+#define CAN0RX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0RX_PORT             GPIO_PORTD_BASE
+#define CAN0RX_PIN              GPIO_PIN_0
+
+#define CAN0TX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0TX_PORT             GPIO_PORTD_BASE
+#define CAN0TX_PIN              GPIO_PIN_1
+
+#define CAN1RX_PERIPH           SYSCTL_PERIPH_GPIOF
+#define CAN1RX_PORT             GPIO_PORTF_BASE
+#define CAN1RX_PIN              GPIO_PIN_0
+
+#define CAN1TX_PERIPH           SYSCTL_PERIPH_GPIOF
+#define CAN1TX_PORT             GPIO_PORTF_BASE
+#define CAN1TX_PIN              GPIO_PIN_1
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP1_PORT               GPIO_PORTA_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_1
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP3_PORT               GPIO_PORTD_BASE
+#define CCP3_PIN                GPIO_PIN_4
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP4_PORT               GPIO_PORTA_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOE
+#define CCP5_PORT               GPIO_PORTE_BASE
+#define CCP5_PIN                GPIO_PIN_5
+
+#define FAULT_PERIPH            SYSCTL_PERIPH_GPIOD
+#define FAULT_PORT              GPIO_PORTD_BASE
+#define FAULT_PIN               GPIO_PIN_6
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define IDX0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define IDX0_PORT               GPIO_PORTD_BASE
+#define IDX0_PIN                GPIO_PIN_7
+
+#define PHA0_PERIPH             SYSCTL_PERIPH_GPIOC
+#define PHA0_PORT               GPIO_PORTC_BASE
+#define PHA0_PIN                GPIO_PIN_4
+
+#define PHB0_PERIPH             SYSCTL_PERIPH_GPIOH
+#define PHB0_PORT               GPIO_PORTH_BASE
+#define PHB0_PIN                GPIO_PIN_3
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOG
+#define PWM0_PORT               GPIO_PORTG_BASE
+#define PWM0_PIN                GPIO_PIN_2
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOG
+#define PWM1_PORT               GPIO_PORTG_BASE
+#define PWM1_PIN                GPIO_PIN_3
+
+#define PWM2_PERIPH             SYSCTL_PERIPH_GPIOH
+#define PWM2_PORT               GPIO_PORTH_BASE
+#define PWM2_PIN                GPIO_PIN_0
+
+#define PWM3_PERIPH             SYSCTL_PERIPH_GPIOH
+#define PWM3_PORT               GPIO_PORTH_BASE
+#define PWM3_PIN                GPIO_PIN_1
+
+#define PWM4_PERIPH             SYSCTL_PERIPH_GPIOE
+#define PWM4_PORT               GPIO_PORTE_BASE
+#define PWM4_PIN                GPIO_PIN_6
+
+#define PWM5_PERIPH             SYSCTL_PERIPH_GPIOE
+#define PWM5_PORT               GPIO_PORTE_BASE
+#define PWM5_PIN                GPIO_PIN_7
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SSI1CLK_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1CLK_PORT            GPIO_PORTE_BASE
+#define SSI1CLK_PIN             GPIO_PIN_0
+
+#define SSI1FSS_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1FSS_PORT            GPIO_PORTE_BASE
+#define SSI1FSS_PIN             GPIO_PIN_1
+
+#define SSI1RX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1RX_PORT             GPIO_PORTE_BASE
+#define SSI1RX_PIN              GPIO_PIN_2
+
+#define SSI1TX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1TX_PORT             GPIO_PORTE_BASE
+#define SSI1TX_PIN              GPIO_PIN_3
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#define U2RX_PERIPH             SYSCTL_PERIPH_GPIOG
+#define U2RX_PORT               GPIO_PORTG_BASE
+#define U2RX_PIN                GPIO_PIN_0
+
+#define U2TX_PERIPH             SYSCTL_PERIPH_GPIOG
+#define U2TX_PORT               GPIO_PORTG_BASE
+#define U2TX_PIN                GPIO_PIN_1
+
+#endif // PART_LM3S2950
+
+//*****************************************************************************
+//
+// LM3S2965 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2965
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOF
+#define C0O_PORT                GPIO_PORTF_BASE
+#define C0O_PIN                 GPIO_PIN_4
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_5
+
+#define C2_MINUS_PERIPH         SYSCTL_PERIPH_GPIOC
+#define C2_MINUS_PORT           GPIO_PORTC_BASE
+#define C2_MINUS_PIN            GPIO_PIN_7
+
+#define C2_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C2_PLUS_PORT            GPIO_PORTC_BASE
+#define C2_PLUS_PIN             GPIO_PIN_6
+
+#define CAN0RX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0RX_PORT             GPIO_PORTD_BASE
+#define CAN0RX_PIN              GPIO_PIN_0
+
+#define CAN0TX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0TX_PORT             GPIO_PORTD_BASE
+#define CAN0TX_PIN              GPIO_PIN_1
+
+#define CAN1RX_PERIPH           SYSCTL_PERIPH_GPIOF
+#define CAN1RX_PORT             GPIO_PORTF_BASE
+#define CAN1RX_PIN              GPIO_PIN_0
+
+#define CAN1TX_PERIPH           SYSCTL_PERIPH_GPIOF
+#define CAN1TX_PORT             GPIO_PORTF_BASE
+#define CAN1TX_PIN              GPIO_PIN_1
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOF
+#define CCP1_PORT               GPIO_PORTF_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_1
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP3_PORT               GPIO_PORTD_BASE
+#define CCP3_PIN                GPIO_PIN_4
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP4_PORT               GPIO_PORTD_BASE
+#define CCP4_PIN                GPIO_PIN_5
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOG
+#define CCP5_PORT               GPIO_PORTG_BASE
+#define CCP5_PIN                GPIO_PIN_5
+
+#define FAULT_PERIPH            SYSCTL_PERIPH_GPIOD
+#define FAULT_PORT              GPIO_PORTD_BASE
+#define FAULT_PIN               GPIO_PIN_6
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define I2C1SCL_PERIPH          SYSCTL_PERIPH_GPIOA
+#define I2C1SCL_PORT            GPIO_PORTA_BASE
+#define I2C1SCL_PIN             GPIO_PIN_6
+
+#define I2C1SDA_PERIPH          SYSCTL_PERIPH_GPIOA
+#define I2C1SDA_PORT            GPIO_PORTA_BASE
+#define I2C1SDA_PIN             GPIO_PIN_7
+
+#define IDX0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define IDX0_PORT               GPIO_PORTD_BASE
+#define IDX0_PIN                GPIO_PIN_7
+
+#define IDX1_PERIPH             SYSCTL_PERIPH_GPIOH
+#define IDX1_PORT               GPIO_PORTH_BASE
+#define IDX1_PIN                GPIO_PIN_2
+
+#define PHA0_PERIPH             SYSCTL_PERIPH_GPIOC
+#define PHA0_PORT               GPIO_PORTC_BASE
+#define PHA0_PIN                GPIO_PIN_4
+
+#define PHA1_PERIPH             SYSCTL_PERIPH_GPIOG
+#define PHA1_PORT               GPIO_PORTG_BASE
+#define PHA1_PIN                GPIO_PIN_6
+
+#define PHB0_PERIPH             SYSCTL_PERIPH_GPIOH
+#define PHB0_PORT               GPIO_PORTH_BASE
+#define PHB0_PIN                GPIO_PIN_3
+
+#define PHB1_PERIPH             SYSCTL_PERIPH_GPIOG
+#define PHB1_PORT               GPIO_PORTG_BASE
+#define PHB1_PIN                GPIO_PIN_7
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOG
+#define PWM0_PORT               GPIO_PORTG_BASE
+#define PWM0_PIN                GPIO_PIN_2
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOG
+#define PWM1_PORT               GPIO_PORTG_BASE
+#define PWM1_PIN                GPIO_PIN_3
+
+#define PWM2_PERIPH             SYSCTL_PERIPH_GPIOH
+#define PWM2_PORT               GPIO_PORTH_BASE
+#define PWM2_PIN                GPIO_PIN_0
+
+#define PWM3_PERIPH             SYSCTL_PERIPH_GPIOH
+#define PWM3_PORT               GPIO_PORTH_BASE
+#define PWM3_PIN                GPIO_PIN_1
+
+#define PWM4_PERIPH             SYSCTL_PERIPH_GPIOF
+#define PWM4_PORT               GPIO_PORTF_BASE
+#define PWM4_PIN                GPIO_PIN_2
+
+#define PWM5_PERIPH             SYSCTL_PERIPH_GPIOF
+#define PWM5_PORT               GPIO_PORTF_BASE
+#define PWM5_PIN                GPIO_PIN_3
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SSI1CLK_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1CLK_PORT            GPIO_PORTE_BASE
+#define SSI1CLK_PIN             GPIO_PIN_0
+
+#define SSI1FSS_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1FSS_PORT            GPIO_PORTE_BASE
+#define SSI1FSS_PIN             GPIO_PIN_1
+
+#define SSI1RX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1RX_PORT             GPIO_PORTE_BASE
+#define SSI1RX_PIN              GPIO_PIN_2
+
+#define SSI1TX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1TX_PORT             GPIO_PORTE_BASE
+#define SSI1TX_PIN              GPIO_PIN_3
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#define U2RX_PERIPH             SYSCTL_PERIPH_GPIOG
+#define U2RX_PORT               GPIO_PORTG_BASE
+#define U2RX_PIN                GPIO_PIN_0
+
+#define U2TX_PERIPH             SYSCTL_PERIPH_GPIOG
+#define U2TX_PORT               GPIO_PORTG_BASE
+#define U2TX_PIN                GPIO_PIN_1
+
+#endif // PART_LM3S2965
+
+//*****************************************************************************
+//
+// LM3S2B93 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2B93
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_PWM4           0x00000804
+#define GPIO_PA2_I2S0RXSD       0x00000809
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_PWM5           0x00000C04
+#define GPIO_PA3_I2S0RXMCLK     0x00000C09
+
+#define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_PWM6           0x00001004
+#define GPIO_PA4_CAN0RX         0x00001005
+#define GPIO_PA4_I2S0TXSCK      0x00001009
+
+#define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_PWM7           0x00001404
+#define GPIO_PA5_CAN0TX         0x00001405
+#define GPIO_PA5_I2S0TXWS       0x00001409
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_PWM0           0x00001804
+#define GPIO_PA6_PWM4           0x00001805
+#define GPIO_PA6_CAN0RX         0x00001806
+#define GPIO_PA6_U1CTS          0x00001809
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_PWM1           0x00001C04
+#define GPIO_PA7_PWM5           0x00001C05
+#define GPIO_PA7_CAN0TX         0x00001C06
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_U1DCD          0x00001C09
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_PWM2           0x00010002
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_PWM3           0x00010402
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_IDX0           0x00010802
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_FAULT0         0x00010C02
+#define GPIO_PB3_FAULT3         0x00010C04
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_CAN0RX         0x00011005
+#define GPIO_PB4_IDX0           0x00011006
+#define GPIO_PB4_U1RX           0x00011007
+#define GPIO_PB4_EPI0S23        0x00011008
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CAN0TX         0x00011405
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+#define GPIO_PB5_EPI0S22        0x00011408
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_FAULT1         0x00011804
+#define GPIO_PB6_IDX0           0x00011805
+#define GPIO_PB6_CCP5           0x00011806
+#define GPIO_PB6_I2S0TXSCK      0x00011809
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_PHA0           0x00021002
+#define GPIO_PC4_PWM6           0x00021004
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_EPI0S2         0x00021008
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_FAULT2         0x00021404
+#define GPIO_PC5_CCP3           0x00021405
+#define GPIO_PC5_EPI0S3         0x00021408
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_PHB0           0x00021802
+#define GPIO_PC6_C2O            0x00021803
+#define GPIO_PC6_PWM7           0x00021804
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+#define GPIO_PC6_EPI0S4         0x00021808
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_PHB0           0x00021C02
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_C1O            0x00021C07
+#define GPIO_PC7_EPI0S5         0x00021C08
+
+#define GPIO_PD0_PWM0           0x00030001
+#define GPIO_PD0_CAN0RX         0x00030002
+#define GPIO_PD0_IDX0           0x00030003
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+#define GPIO_PD0_I2S0RXSCK      0x00030008
+#define GPIO_PD0_U1CTS          0x00030009
+
+#define GPIO_PD1_PWM1           0x00030401
+#define GPIO_PD1_CAN0TX         0x00030402
+#define GPIO_PD1_PHA0           0x00030403
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_I2S0RXWS       0x00030408
+#define GPIO_PD1_U1DCD          0x00030409
+#define GPIO_PD1_CCP2           0x0003040A
+#define GPIO_PD1_PHB1           0x0003040B
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_PWM2           0x00030803
+#define GPIO_PD2_CCP5           0x00030804
+#define GPIO_PD2_EPI0S20        0x00030808
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_PWM3           0x00030C03
+#define GPIO_PD3_CCP0           0x00030C04
+#define GPIO_PD3_EPI0S21        0x00030C08
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+#define GPIO_PD4_I2S0RXSD       0x00031008
+#define GPIO_PD4_U1RI           0x00031009
+#define GPIO_PD4_EPI0S19        0x0003100A
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_I2S0RXMCLK     0x00031408
+#define GPIO_PD5_U2RX           0x00031409
+#define GPIO_PD5_EPI0S28        0x0003140A
+
+#define GPIO_PD6_FAULT0         0x00031801
+#define GPIO_PD6_I2S0TXSCK      0x00031808
+#define GPIO_PD6_U2TX           0x00031809
+#define GPIO_PD6_EPI0S29        0x0003180A
+
+#define GPIO_PD7_IDX0           0x00031C01
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+#define GPIO_PD7_I2S0TXWS       0x00031C08
+#define GPIO_PD7_U1DTR          0x00031C09
+#define GPIO_PD7_EPI0S30        0x00031C0A
+
+#define GPIO_PE0_PWM4           0x00040001
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+#define GPIO_PE0_EPI0S8         0x00040008
+
+#define GPIO_PE1_PWM5           0x00040401
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_FAULT0         0x00040403
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+#define GPIO_PE1_EPI0S9         0x00040408
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_PHB1           0x00040803
+#define GPIO_PE2_PHA0           0x00040804
+#define GPIO_PE2_CCP2           0x00040805
+#define GPIO_PE2_EPI0S24        0x00040808
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_PHA1           0x00040C03
+#define GPIO_PE3_PHB0           0x00040C04
+#define GPIO_PE3_CCP7           0x00040C05
+#define GPIO_PE3_EPI0S25        0x00040C08
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_FAULT0         0x00041004
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+#define GPIO_PE4_I2S0TXWS       0x00041009
+
+#define GPIO_PE5_CCP5           0x00041401
+#define GPIO_PE5_I2S0TXSD       0x00041409
+
+#define GPIO_PE6_PWM4           0x00041801
+#define GPIO_PE6_C1O            0x00041802
+#define GPIO_PE6_U1CTS          0x00041809
+
+#define GPIO_PE7_PWM5           0x00041C01
+#define GPIO_PE7_C2O            0x00041C02
+#define GPIO_PE7_U1DCD          0x00041C09
+
+#define GPIO_PF0_CAN1RX         0x00050001
+#define GPIO_PF0_PHB0           0x00050002
+#define GPIO_PF0_PWM0           0x00050003
+#define GPIO_PF0_I2S0TXSD       0x00050008
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_CAN1TX         0x00050401
+#define GPIO_PF1_IDX1           0x00050402
+#define GPIO_PF1_PWM1           0x00050403
+#define GPIO_PF1_I2S0TXMCLK     0x00050408
+#define GPIO_PF1_U1RTS          0x00050409
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_PWM4           0x00050802
+#define GPIO_PF2_PWM2           0x00050804
+#define GPIO_PF2_SSI1CLK        0x00050809
+
+#define GPIO_PF3_PWM5           0x00050C02
+#define GPIO_PF3_PWM3           0x00050C04
+#define GPIO_PF3_SSI1FSS        0x00050C09
+
+#define GPIO_PF4_CCP0           0x00051001
+#define GPIO_PF4_C0O            0x00051002
+#define GPIO_PF4_FAULT0         0x00051004
+#define GPIO_PF4_EPI0S12        0x00051008
+#define GPIO_PF4_SSI1RX         0x00051009
+
+#define GPIO_PF5_CCP2           0x00051401
+#define GPIO_PF5_C1O            0x00051402
+#define GPIO_PF5_EPI0S15        0x00051408
+#define GPIO_PF5_SSI1TX         0x00051409
+
+#define GPIO_PF6_CCP1           0x00051801
+#define GPIO_PF6_C2O            0x00051802
+#define GPIO_PF6_PHA0           0x00051804
+#define GPIO_PF6_I2S0TXMCLK     0x00051809
+#define GPIO_PF6_U1RTS          0x0005180A
+
+#define GPIO_PF7_CCP4           0x00051C01
+#define GPIO_PF7_PHB0           0x00051C04
+#define GPIO_PF7_EPI0S12        0x00051C08
+#define GPIO_PF7_FAULT1         0x00051C09
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_PWM0           0x00060002
+#define GPIO_PG0_I2C1SCL        0x00060003
+#define GPIO_PG0_PWM4           0x00060004
+#define GPIO_PG0_EPI0S13        0x00060008
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_PWM1           0x00060402
+#define GPIO_PG1_I2C1SDA        0x00060403
+#define GPIO_PG1_PWM5           0x00060404
+#define GPIO_PG1_EPI0S14        0x00060408
+
+#define GPIO_PG2_PWM0           0x00060801
+#define GPIO_PG2_FAULT0         0x00060804
+#define GPIO_PG2_IDX1           0x00060808
+#define GPIO_PG2_I2S0RXSD       0x00060809
+
+#define GPIO_PG3_PWM1           0x00060C01
+#define GPIO_PG3_FAULT2         0x00060C04
+#define GPIO_PG3_FAULT0         0x00060C08
+#define GPIO_PG3_I2S0RXMCLK     0x00060C09
+
+#define GPIO_PG4_CCP3           0x00061001
+#define GPIO_PG4_FAULT1         0x00061004
+#define GPIO_PG4_EPI0S15        0x00061008
+#define GPIO_PG4_PWM6           0x00061009
+#define GPIO_PG4_U1RI           0x0006100A
+
+#define GPIO_PG5_CCP5           0x00061401
+#define GPIO_PG5_IDX0           0x00061404
+#define GPIO_PG5_FAULT1         0x00061405
+#define GPIO_PG5_PWM7           0x00061408
+#define GPIO_PG5_I2S0RXSCK      0x00061409
+#define GPIO_PG5_U1DTR          0x0006140A
+
+#define GPIO_PG6_PHA1           0x00061801
+#define GPIO_PG6_PWM6           0x00061804
+#define GPIO_PG6_FAULT1         0x00061808
+#define GPIO_PG6_I2S0RXWS       0x00061809
+#define GPIO_PG6_U1RI           0x0006180A
+
+#define GPIO_PG7_PHB1           0x00061C01
+#define GPIO_PG7_PWM7           0x00061C04
+#define GPIO_PG7_CCP5           0x00061C08
+#define GPIO_PG7_EPI0S31        0x00061C09
+
+#define GPIO_PH0_CCP6           0x00070001
+#define GPIO_PH0_PWM2           0x00070002
+#define GPIO_PH0_EPI0S6         0x00070008
+#define GPIO_PH0_PWM4           0x00070009
+
+#define GPIO_PH1_CCP7           0x00070401
+#define GPIO_PH1_PWM3           0x00070402
+#define GPIO_PH1_EPI0S7         0x00070408
+#define GPIO_PH1_PWM5           0x00070409
+
+#define GPIO_PH2_IDX1           0x00070801
+#define GPIO_PH2_C1O            0x00070802
+#define GPIO_PH2_FAULT3         0x00070804
+#define GPIO_PH2_EPI0S1         0x00070808
+
+#define GPIO_PH3_PHB0           0x00070C01
+#define GPIO_PH3_FAULT0         0x00070C02
+#define GPIO_PH3_EPI0S0         0x00070C08
+
+#define GPIO_PH4_EPI0S10        0x00071008
+#define GPIO_PH4_SSI1CLK        0x0007100B
+
+#define GPIO_PH5_EPI0S11        0x00071408
+#define GPIO_PH5_FAULT2         0x0007140A
+#define GPIO_PH5_SSI1FSS        0x0007140B
+
+#define GPIO_PH6_EPI0S26        0x00071808
+#define GPIO_PH6_PWM4           0x0007180A
+#define GPIO_PH6_SSI1RX         0x0007180B
+
+#define GPIO_PH7_EPI0S27        0x00071C08
+#define GPIO_PH7_PWM5           0x00071C0A
+#define GPIO_PH7_SSI1TX         0x00071C0B
+
+#define GPIO_PJ0_EPI0S16        0x00080008
+#define GPIO_PJ0_PWM0           0x0008000A
+#define GPIO_PJ0_I2C1SCL        0x0008000B
+
+#define GPIO_PJ1_EPI0S17        0x00080408
+#define GPIO_PJ1_PWM1           0x0008040A
+#define GPIO_PJ1_I2C1SDA        0x0008040B
+
+#define GPIO_PJ2_EPI0S18        0x00080808
+#define GPIO_PJ2_CCP0           0x00080809
+#define GPIO_PJ2_FAULT0         0x0008080A
+
+#endif // PART_LM3S2B93
+
+//*****************************************************************************
+//
+// LM3S2D93 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2D93
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_PWM4           0x00000804
+#define GPIO_PA2_I2S0RXSD       0x00000809
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_PWM5           0x00000C04
+#define GPIO_PA3_I2S0RXMCLK     0x00000C09
+
+#define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_PWM6           0x00001004
+#define GPIO_PA4_CAN0RX         0x00001005
+#define GPIO_PA4_I2S0TXSCK      0x00001009
+
+#define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_PWM7           0x00001404
+#define GPIO_PA5_CAN0TX         0x00001405
+#define GPIO_PA5_I2S0TXWS       0x00001409
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_PWM0           0x00001804
+#define GPIO_PA6_PWM4           0x00001805
+#define GPIO_PA6_CAN0RX         0x00001806
+#define GPIO_PA6_U1CTS          0x00001809
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_PWM1           0x00001C04
+#define GPIO_PA7_PWM5           0x00001C05
+#define GPIO_PA7_CAN0TX         0x00001C06
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_U1DCD          0x00001C09
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_PWM2           0x00010002
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_PWM3           0x00010402
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_IDX0           0x00010802
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_FAULT0         0x00010C02
+#define GPIO_PB3_FAULT3         0x00010C04
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_CAN0RX         0x00011005
+#define GPIO_PB4_IDX0           0x00011006
+#define GPIO_PB4_U1RX           0x00011007
+#define GPIO_PB4_EPI0S23        0x00011008
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CAN0TX         0x00011405
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+#define GPIO_PB5_EPI0S22        0x00011408
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_FAULT1         0x00011804
+#define GPIO_PB6_IDX0           0x00011805
+#define GPIO_PB6_CCP5           0x00011806
+#define GPIO_PB6_I2S0TXSCK      0x00011809
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_PHA0           0x00021002
+#define GPIO_PC4_PWM6           0x00021004
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_EPI0S2         0x00021008
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_FAULT2         0x00021404
+#define GPIO_PC5_CCP3           0x00021405
+#define GPIO_PC5_EPI0S3         0x00021408
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_PHB0           0x00021802
+#define GPIO_PC6_C2O            0x00021803
+#define GPIO_PC6_PWM7           0x00021804
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+#define GPIO_PC6_EPI0S4         0x00021808
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_PHB0           0x00021C02
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_C1O            0x00021C07
+#define GPIO_PC7_EPI0S5         0x00021C08
+
+#define GPIO_PD0_PWM0           0x00030001
+#define GPIO_PD0_CAN0RX         0x00030002
+#define GPIO_PD0_IDX0           0x00030003
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+#define GPIO_PD0_I2S0RXSCK      0x00030008
+#define GPIO_PD0_U1CTS          0x00030009
+
+#define GPIO_PD1_PWM1           0x00030401
+#define GPIO_PD1_CAN0TX         0x00030402
+#define GPIO_PD1_PHA0           0x00030403
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_I2S0RXWS       0x00030408
+#define GPIO_PD1_U1DCD          0x00030409
+#define GPIO_PD1_CCP2           0x0003040A
+#define GPIO_PD1_PHB1           0x0003040B
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_PWM2           0x00030803
+#define GPIO_PD2_CCP5           0x00030804
+#define GPIO_PD2_EPI0S20        0x00030808
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_PWM3           0x00030C03
+#define GPIO_PD3_CCP0           0x00030C04
+#define GPIO_PD3_EPI0S21        0x00030C08
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+#define GPIO_PD4_I2S0RXSD       0x00031008
+#define GPIO_PD4_U1RI           0x00031009
+#define GPIO_PD4_EPI0S19        0x0003100A
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_I2S0RXMCLK     0x00031408
+#define GPIO_PD5_U2RX           0x00031409
+#define GPIO_PD5_EPI0S28        0x0003140A
+
+#define GPIO_PD6_FAULT0         0x00031801
+#define GPIO_PD6_I2S0TXSCK      0x00031808
+#define GPIO_PD6_U2TX           0x00031809
+#define GPIO_PD6_EPI0S29        0x0003180A
+
+#define GPIO_PD7_IDX0           0x00031C01
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+#define GPIO_PD7_I2S0TXWS       0x00031C08
+#define GPIO_PD7_U1DTR          0x00031C09
+#define GPIO_PD7_EPI0S30        0x00031C0A
+
+#define GPIO_PE0_PWM4           0x00040001
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+#define GPIO_PE0_EPI0S8         0x00040008
+
+#define GPIO_PE1_PWM5           0x00040401
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_FAULT0         0x00040403
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+#define GPIO_PE1_EPI0S9         0x00040408
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_PHB1           0x00040803
+#define GPIO_PE2_PHA0           0x00040804
+#define GPIO_PE2_CCP2           0x00040805
+#define GPIO_PE2_EPI0S24        0x00040808
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_PHA1           0x00040C03
+#define GPIO_PE3_PHB0           0x00040C04
+#define GPIO_PE3_CCP7           0x00040C05
+#define GPIO_PE3_EPI0S25        0x00040C08
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_FAULT0         0x00041004
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+#define GPIO_PE4_I2S0TXWS       0x00041009
+
+#define GPIO_PE5_CCP5           0x00041401
+#define GPIO_PE5_I2S0TXSD       0x00041409
+
+#define GPIO_PE6_PWM4           0x00041801
+#define GPIO_PE6_C1O            0x00041802
+#define GPIO_PE6_U1CTS          0x00041809
+
+#define GPIO_PE7_PWM5           0x00041C01
+#define GPIO_PE7_C2O            0x00041C02
+#define GPIO_PE7_U1DCD          0x00041C09
+
+#define GPIO_PF0_CAN1RX         0x00050001
+#define GPIO_PF0_PHB0           0x00050002
+#define GPIO_PF0_PWM0           0x00050003
+#define GPIO_PF0_I2S0TXSD       0x00050008
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_CAN1TX         0x00050401
+#define GPIO_PF1_IDX1           0x00050402
+#define GPIO_PF1_PWM1           0x00050403
+#define GPIO_PF1_I2S0TXMCLK     0x00050408
+#define GPIO_PF1_U1RTS          0x00050409
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_PWM4           0x00050802
+#define GPIO_PF2_PWM2           0x00050804
+#define GPIO_PF2_SSI1CLK        0x00050809
+
+#define GPIO_PF3_PWM5           0x00050C02
+#define GPIO_PF3_PWM3           0x00050C04
+#define GPIO_PF3_SSI1FSS        0x00050C09
+
+#define GPIO_PF4_CCP0           0x00051001
+#define GPIO_PF4_C0O            0x00051002
+#define GPIO_PF4_FAULT0         0x00051004
+#define GPIO_PF4_EPI0S12        0x00051008
+#define GPIO_PF4_SSI1RX         0x00051009
+
+#define GPIO_PF5_CCP2           0x00051401
+#define GPIO_PF5_C1O            0x00051402
+#define GPIO_PF5_EPI0S15        0x00051408
+#define GPIO_PF5_SSI1TX         0x00051409
+
+#define GPIO_PF6_CCP1           0x00051801
+#define GPIO_PF6_C2O            0x00051802
+#define GPIO_PF6_PHA0           0x00051804
+#define GPIO_PF6_I2S0TXMCLK     0x00051809
+#define GPIO_PF6_U1RTS          0x0005180A
+
+#define GPIO_PF7_CCP4           0x00051C01
+#define GPIO_PF7_PHB0           0x00051C04
+#define GPIO_PF7_EPI0S12        0x00051C08
+#define GPIO_PF7_FAULT1         0x00051C09
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_PWM0           0x00060002
+#define GPIO_PG0_I2C1SCL        0x00060003
+#define GPIO_PG0_PWM4           0x00060004
+#define GPIO_PG0_EPI0S13        0x00060008
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_PWM1           0x00060402
+#define GPIO_PG1_I2C1SDA        0x00060403
+#define GPIO_PG1_PWM5           0x00060404
+#define GPIO_PG1_EPI0S14        0x00060408
+
+#define GPIO_PG2_PWM0           0x00060801
+#define GPIO_PG2_FAULT0         0x00060804
+#define GPIO_PG2_IDX1           0x00060808
+#define GPIO_PG2_I2S0RXSD       0x00060809
+
+#define GPIO_PG3_PWM1           0x00060C01
+#define GPIO_PG3_FAULT2         0x00060C04
+#define GPIO_PG3_FAULT0         0x00060C08
+#define GPIO_PG3_I2S0RXMCLK     0x00060C09
+
+#define GPIO_PG4_CCP3           0x00061001
+#define GPIO_PG4_FAULT1         0x00061004
+#define GPIO_PG4_EPI0S15        0x00061008
+#define GPIO_PG4_PWM6           0x00061009
+#define GPIO_PG4_U1RI           0x0006100A
+
+#define GPIO_PG5_CCP5           0x00061401
+#define GPIO_PG5_IDX0           0x00061404
+#define GPIO_PG5_FAULT1         0x00061405
+#define GPIO_PG5_PWM7           0x00061408
+#define GPIO_PG5_I2S0RXSCK      0x00061409
+#define GPIO_PG5_U1DTR          0x0006140A
+
+#define GPIO_PG6_PHA1           0x00061801
+#define GPIO_PG6_PWM6           0x00061804
+#define GPIO_PG6_FAULT1         0x00061808
+#define GPIO_PG6_I2S0RXWS       0x00061809
+#define GPIO_PG6_U1RI           0x0006180A
+
+#define GPIO_PG7_PHB1           0x00061C01
+#define GPIO_PG7_PWM7           0x00061C04
+#define GPIO_PG7_CCP5           0x00061C08
+#define GPIO_PG7_EPI0S31        0x00061C09
+
+#define GPIO_PH0_CCP6           0x00070001
+#define GPIO_PH0_PWM2           0x00070002
+#define GPIO_PH0_EPI0S6         0x00070008
+#define GPIO_PH0_PWM4           0x00070009
+
+#define GPIO_PH1_CCP7           0x00070401
+#define GPIO_PH1_PWM3           0x00070402
+#define GPIO_PH1_EPI0S7         0x00070408
+#define GPIO_PH1_PWM5           0x00070409
+
+#define GPIO_PH2_IDX1           0x00070801
+#define GPIO_PH2_C1O            0x00070802
+#define GPIO_PH2_FAULT3         0x00070804
+#define GPIO_PH2_EPI0S1         0x00070808
+
+#define GPIO_PH3_PHB0           0x00070C01
+#define GPIO_PH3_FAULT0         0x00070C02
+#define GPIO_PH3_EPI0S0         0x00070C08
+
+#define GPIO_PH4_EPI0S10        0x00071008
+#define GPIO_PH4_SSI1CLK        0x0007100B
+
+#define GPIO_PH5_EPI0S11        0x00071408
+#define GPIO_PH5_FAULT2         0x0007140A
+#define GPIO_PH5_SSI1FSS        0x0007140B
+
+#define GPIO_PH6_EPI0S26        0x00071808
+#define GPIO_PH6_PWM4           0x0007180A
+#define GPIO_PH6_SSI1RX         0x0007180B
+
+#define GPIO_PH7_EPI0S27        0x00071C08
+#define GPIO_PH7_PWM5           0x00071C0A
+#define GPIO_PH7_SSI1TX         0x00071C0B
+
+#define GPIO_PJ0_EPI0S16        0x00080008
+#define GPIO_PJ0_PWM0           0x0008000A
+#define GPIO_PJ0_I2C1SCL        0x0008000B
+
+#define GPIO_PJ1_EPI0S17        0x00080408
+#define GPIO_PJ1_PWM1           0x0008040A
+#define GPIO_PJ1_I2C1SDA        0x0008040B
+
+#define GPIO_PJ2_EPI0S18        0x00080808
+#define GPIO_PJ2_CCP0           0x00080809
+#define GPIO_PJ2_FAULT0         0x0008080A
+
+#endif // PART_LM3S2D93
+
+//*****************************************************************************
+//
+// LM3S2U93 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2U93
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_PWM4           0x00000804
+#define GPIO_PA2_I2S0RXSD       0x00000809
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_PWM5           0x00000C04
+#define GPIO_PA3_I2S0RXMCLK     0x00000C09
+
+#define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_PWM6           0x00001004
+#define GPIO_PA4_CAN0RX         0x00001005
+#define GPIO_PA4_I2S0TXSCK      0x00001009
+
+#define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_PWM7           0x00001404
+#define GPIO_PA5_CAN0TX         0x00001405
+#define GPIO_PA5_I2S0TXWS       0x00001409
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_PWM0           0x00001804
+#define GPIO_PA6_PWM4           0x00001805
+#define GPIO_PA6_CAN0RX         0x00001806
+#define GPIO_PA6_U1CTS          0x00001809
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_PWM1           0x00001C04
+#define GPIO_PA7_PWM5           0x00001C05
+#define GPIO_PA7_CAN0TX         0x00001C06
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_U1DCD          0x00001C09
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_PWM2           0x00010002
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_PWM3           0x00010402
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_IDX0           0x00010802
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_FAULT0         0x00010C02
+#define GPIO_PB3_FAULT3         0x00010C04
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_CAN0RX         0x00011005
+#define GPIO_PB4_IDX0           0x00011006
+#define GPIO_PB4_U1RX           0x00011007
+#define GPIO_PB4_EPI0S23        0x00011008
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CAN0TX         0x00011405
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+#define GPIO_PB5_EPI0S22        0x00011408
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_FAULT1         0x00011804
+#define GPIO_PB6_IDX0           0x00011805
+#define GPIO_PB6_CCP5           0x00011806
+#define GPIO_PB6_I2S0TXSCK      0x00011809
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_PHA0           0x00021002
+#define GPIO_PC4_PWM6           0x00021004
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_EPI0S2         0x00021008
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_FAULT2         0x00021404
+#define GPIO_PC5_CCP3           0x00021405
+#define GPIO_PC5_EPI0S3         0x00021408
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_PHB0           0x00021802
+#define GPIO_PC6_C2O            0x00021803
+#define GPIO_PC6_PWM7           0x00021804
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+#define GPIO_PC6_EPI0S4         0x00021808
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_PHB0           0x00021C02
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_C1O            0x00021C07
+#define GPIO_PC7_EPI0S5         0x00021C08
+
+#define GPIO_PD0_PWM0           0x00030001
+#define GPIO_PD0_CAN0RX         0x00030002
+#define GPIO_PD0_IDX0           0x00030003
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+#define GPIO_PD0_I2S0RXSCK      0x00030008
+#define GPIO_PD0_U1CTS          0x00030009
+
+#define GPIO_PD1_PWM1           0x00030401
+#define GPIO_PD1_CAN0TX         0x00030402
+#define GPIO_PD1_PHA0           0x00030403
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_I2S0RXWS       0x00030408
+#define GPIO_PD1_U1DCD          0x00030409
+#define GPIO_PD1_CCP2           0x0003040A
+#define GPIO_PD1_PHB1           0x0003040B
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_PWM2           0x00030803
+#define GPIO_PD2_CCP5           0x00030804
+#define GPIO_PD2_EPI0S20        0x00030808
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_PWM3           0x00030C03
+#define GPIO_PD3_CCP0           0x00030C04
+#define GPIO_PD3_EPI0S21        0x00030C08
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+#define GPIO_PD4_I2S0RXSD       0x00031008
+#define GPIO_PD4_U1RI           0x00031009
+#define GPIO_PD4_EPI0S19        0x0003100A
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_I2S0RXMCLK     0x00031408
+#define GPIO_PD5_U2RX           0x00031409
+#define GPIO_PD5_EPI0S28        0x0003140A
+
+#define GPIO_PD6_FAULT0         0x00031801
+#define GPIO_PD6_I2S0TXSCK      0x00031808
+#define GPIO_PD6_U2TX           0x00031809
+#define GPIO_PD6_EPI0S29        0x0003180A
+
+#define GPIO_PD7_IDX0           0x00031C01
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+#define GPIO_PD7_I2S0TXWS       0x00031C08
+#define GPIO_PD7_U1DTR          0x00031C09
+#define GPIO_PD7_EPI0S30        0x00031C0A
+
+#define GPIO_PE0_PWM4           0x00040001
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+#define GPIO_PE0_EPI0S8         0x00040008
+
+#define GPIO_PE1_PWM5           0x00040401
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_FAULT0         0x00040403
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+#define GPIO_PE1_EPI0S9         0x00040408
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_PHB1           0x00040803
+#define GPIO_PE2_PHA0           0x00040804
+#define GPIO_PE2_CCP2           0x00040805
+#define GPIO_PE2_EPI0S24        0x00040808
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_PHA1           0x00040C03
+#define GPIO_PE3_PHB0           0x00040C04
+#define GPIO_PE3_CCP7           0x00040C05
+#define GPIO_PE3_EPI0S25        0x00040C08
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_FAULT0         0x00041004
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+#define GPIO_PE4_I2S0TXWS       0x00041009
+
+#define GPIO_PE5_CCP5           0x00041401
+#define GPIO_PE5_I2S0TXSD       0x00041409
+
+#define GPIO_PE6_PWM4           0x00041801
+#define GPIO_PE6_C1O            0x00041802
+#define GPIO_PE6_U1CTS          0x00041809
+
+#define GPIO_PE7_PWM5           0x00041C01
+#define GPIO_PE7_C2O            0x00041C02
+#define GPIO_PE7_U1DCD          0x00041C09
+
+#define GPIO_PF0_CAN1RX         0x00050001
+#define GPIO_PF0_PHB0           0x00050002
+#define GPIO_PF0_PWM0           0x00050003
+#define GPIO_PF0_I2S0TXSD       0x00050008
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_CAN1TX         0x00050401
+#define GPIO_PF1_IDX1           0x00050402
+#define GPIO_PF1_PWM1           0x00050403
+#define GPIO_PF1_I2S0TXMCLK     0x00050408
+#define GPIO_PF1_U1RTS          0x00050409
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_PWM4           0x00050802
+#define GPIO_PF2_PWM2           0x00050804
+#define GPIO_PF2_SSI1CLK        0x00050809
+
+#define GPIO_PF3_PWM5           0x00050C02
+#define GPIO_PF3_PWM3           0x00050C04
+#define GPIO_PF3_SSI1FSS        0x00050C09
+
+#define GPIO_PF4_CCP0           0x00051001
+#define GPIO_PF4_C0O            0x00051002
+#define GPIO_PF4_FAULT0         0x00051004
+#define GPIO_PF4_EPI0S12        0x00051008
+#define GPIO_PF4_SSI1RX         0x00051009
+
+#define GPIO_PF5_CCP2           0x00051401
+#define GPIO_PF5_C1O            0x00051402
+#define GPIO_PF5_EPI0S15        0x00051408
+#define GPIO_PF5_SSI1TX         0x00051409
+
+#define GPIO_PF6_CCP1           0x00051801
+#define GPIO_PF6_C2O            0x00051802
+#define GPIO_PF6_PHA0           0x00051804
+#define GPIO_PF6_I2S0TXMCLK     0x00051809
+#define GPIO_PF6_U1RTS          0x0005180A
+
+#define GPIO_PF7_CCP4           0x00051C01
+#define GPIO_PF7_PHB0           0x00051C04
+#define GPIO_PF7_EPI0S12        0x00051C08
+#define GPIO_PF7_FAULT1         0x00051C09
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_PWM0           0x00060002
+#define GPIO_PG0_I2C1SCL        0x00060003
+#define GPIO_PG0_PWM4           0x00060004
+#define GPIO_PG0_EPI0S13        0x00060008
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_PWM1           0x00060402
+#define GPIO_PG1_I2C1SDA        0x00060403
+#define GPIO_PG1_PWM5           0x00060404
+#define GPIO_PG1_EPI0S14        0x00060408
+
+#define GPIO_PG2_PWM0           0x00060801
+#define GPIO_PG2_FAULT0         0x00060804
+#define GPIO_PG2_IDX1           0x00060808
+#define GPIO_PG2_I2S0RXSD       0x00060809
+
+#define GPIO_PG3_PWM1           0x00060C01
+#define GPIO_PG3_FAULT2         0x00060C04
+#define GPIO_PG3_FAULT0         0x00060C08
+#define GPIO_PG3_I2S0RXMCLK     0x00060C09
+
+#define GPIO_PG4_CCP3           0x00061001
+#define GPIO_PG4_FAULT1         0x00061004
+#define GPIO_PG4_EPI0S15        0x00061008
+#define GPIO_PG4_PWM6           0x00061009
+#define GPIO_PG4_U1RI           0x0006100A
+
+#define GPIO_PG5_CCP5           0x00061401
+#define GPIO_PG5_IDX0           0x00061404
+#define GPIO_PG5_FAULT1         0x00061405
+#define GPIO_PG5_PWM7           0x00061408
+#define GPIO_PG5_I2S0RXSCK      0x00061409
+#define GPIO_PG5_U1DTR          0x0006140A
+
+#define GPIO_PG6_PHA1           0x00061801
+#define GPIO_PG6_PWM6           0x00061804
+#define GPIO_PG6_FAULT1         0x00061808
+#define GPIO_PG6_I2S0RXWS       0x00061809
+#define GPIO_PG6_U1RI           0x0006180A
+
+#define GPIO_PG7_PHB1           0x00061C01
+#define GPIO_PG7_PWM7           0x00061C04
+#define GPIO_PG7_CCP5           0x00061C08
+#define GPIO_PG7_EPI0S31        0x00061C09
+
+#define GPIO_PH0_CCP6           0x00070001
+#define GPIO_PH0_PWM2           0x00070002
+#define GPIO_PH0_EPI0S6         0x00070008
+#define GPIO_PH0_PWM4           0x00070009
+
+#define GPIO_PH1_CCP7           0x00070401
+#define GPIO_PH1_PWM3           0x00070402
+#define GPIO_PH1_EPI0S7         0x00070408
+#define GPIO_PH1_PWM5           0x00070409
+
+#define GPIO_PH2_IDX1           0x00070801
+#define GPIO_PH2_C1O            0x00070802
+#define GPIO_PH2_FAULT3         0x00070804
+#define GPIO_PH2_EPI0S1         0x00070808
+
+#define GPIO_PH3_PHB0           0x00070C01
+#define GPIO_PH3_FAULT0         0x00070C02
+#define GPIO_PH3_EPI0S0         0x00070C08
+
+#define GPIO_PH4_EPI0S10        0x00071008
+#define GPIO_PH4_SSI1CLK        0x0007100B
+
+#define GPIO_PH5_EPI0S11        0x00071408
+#define GPIO_PH5_FAULT2         0x0007140A
+#define GPIO_PH5_SSI1FSS        0x0007140B
+
+#define GPIO_PH6_EPI0S26        0x00071808
+#define GPIO_PH6_PWM4           0x0007180A
+#define GPIO_PH6_SSI1RX         0x0007180B
+
+#define GPIO_PH7_EPI0S27        0x00071C08
+#define GPIO_PH7_PWM5           0x00071C0A
+#define GPIO_PH7_SSI1TX         0x00071C0B
+
+#define GPIO_PJ0_EPI0S16        0x00080008
+#define GPIO_PJ0_PWM0           0x0008000A
+#define GPIO_PJ0_I2C1SCL        0x0008000B
+
+#define GPIO_PJ1_EPI0S17        0x00080408
+#define GPIO_PJ1_PWM1           0x0008040A
+#define GPIO_PJ1_I2C1SDA        0x0008040B
+
+#define GPIO_PJ2_EPI0S18        0x00080808
+#define GPIO_PJ2_CCP0           0x00080809
+#define GPIO_PJ2_FAULT0         0x0008080A
+
+#endif // PART_LM3S2U93
+
+//*****************************************************************************
+//
+// LM3S3634 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S3634
+
+#define ADC0_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC0_PORT               GPIO_PORTE_BASE
+#define ADC0_PIN                GPIO_PIN_3
+
+#define ADC1_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC1_PORT               GPIO_PORTE_BASE
+#define ADC1_PIN                GPIO_PIN_2
+
+#define ADC2_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC2_PORT               GPIO_PORTE_BASE
+#define ADC2_PIN                GPIO_PIN_1
+
+#define ADC3_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC3_PORT               GPIO_PORTE_BASE
+#define ADC3_PIN                GPIO_PIN_0
+
+#define ADC4_PERIPH             SYSCTL_PERIPH_GPIOD
+#define ADC4_PORT               GPIO_PORTD_BASE
+#define ADC4_PIN                GPIO_PIN_3
+
+#define ADC5_PERIPH             SYSCTL_PERIPH_GPIOD
+#define ADC5_PORT               GPIO_PORTD_BASE
+#define ADC5_PIN                GPIO_PIN_2
+
+#define ADC6_PERIPH             SYSCTL_PERIPH_GPIOD
+#define ADC6_PORT               GPIO_PORTD_BASE
+#define ADC6_PIN                GPIO_PIN_1
+
+#define ADC7_PERIPH             SYSCTL_PERIPH_GPIOD
+#define ADC7_PORT               GPIO_PORTD_BASE
+#define ADC7_PIN                GPIO_PIN_0
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_5
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP1_PORT               GPIO_PORTB_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP2_PORT               GPIO_PORTC_BASE
+#define CCP2_PIN                GPIO_PIN_4
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOE
+#define CCP3_PORT               GPIO_PORTE_BASE
+#define CCP3_PIN                GPIO_PIN_4
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP4_PORT               GPIO_PORTC_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define I2C1SCL_PERIPH          SYSCTL_PERIPH_GPIOA
+#define I2C1SCL_PORT            GPIO_PORTA_BASE
+#define I2C1SCL_PIN             GPIO_PIN_6
+
+#define I2C1SDA_PERIPH          SYSCTL_PERIPH_GPIOA
+#define I2C1SDA_PORT            GPIO_PORTA_BASE
+#define I2C1SDA_PIN             GPIO_PIN_7
+
+#define NMI_PERIPH              SYSCTL_PERIPH_GPIOB
+#define NMI_PORT                GPIO_PORTB_BASE
+#define NMI_PIN                 GPIO_PIN_7
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOB
+#define U1RX_PORT               GPIO_PORTB_BASE
+#define U1RX_PIN                GPIO_PIN_0
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOB
+#define U1TX_PORT               GPIO_PORTB_BASE
+#define U1TX_PIN                GPIO_PIN_1
+
+#define USB0EPEN_PERIPH         SYSCTL_PERIPH_GPIOC
+#define USB0EPEN_PORT           GPIO_PORTC_BASE
+#define USB0EPEN_PIN            GPIO_PIN_5
+
+#define USB0PFLT_PERIPH         SYSCTL_PERIPH_GPIOC
+#define USB0PFLT_PORT           GPIO_PORTC_BASE
+#define USB0PFLT_PIN            GPIO_PIN_6
+
+#endif // PART_LM3S3634
+
+//*****************************************************************************
+//
+// LM3S3651 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S3651
+
+#define ADC0_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC0_PORT               GPIO_PORTE_BASE
+#define ADC0_PIN                GPIO_PIN_3
+
+#define ADC1_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC1_PORT               GPIO_PORTE_BASE
+#define ADC1_PIN                GPIO_PIN_2
+
+#define ADC2_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC2_PORT               GPIO_PORTE_BASE
+#define ADC2_PIN                GPIO_PIN_1
+
+#define ADC3_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC3_PORT               GPIO_PORTE_BASE
+#define ADC3_PIN                GPIO_PIN_0
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOB
+#define C0O_PORT                GPIO_PORTB_BASE
+#define C0O_PIN                 GPIO_PIN_6
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_7
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP0_PORT               GPIO_PORTD_BASE
+#define CCP0_PIN                GPIO_PIN_3
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP1_PORT               GPIO_PORTA_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP2_PORT               GPIO_PORTC_BASE
+#define CCP2_PIN                GPIO_PIN_4
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOE
+#define CCP3_PORT               GPIO_PORTE_BASE
+#define CCP3_PIN                GPIO_PIN_4
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP4_PORT               GPIO_PORTA_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP5_PORT               GPIO_PORTD_BASE
+#define CCP5_PIN                GPIO_PIN_2
+
+#define CCP6_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP6_PORT               GPIO_PORTD_BASE
+#define CCP6_PIN                GPIO_PIN_0
+
+#define CCP7_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP7_PORT               GPIO_PORTD_BASE
+#define CCP7_PIN                GPIO_PIN_1
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define NMI_PERIPH              SYSCTL_PERIPH_GPIOB
+#define NMI_PORT                GPIO_PORTB_BASE
+#define NMI_PIN                 GPIO_PIN_7
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define USB0EPEN_PERIPH         SYSCTL_PERIPH_GPIOC
+#define USB0EPEN_PORT           GPIO_PORTC_BASE
+#define USB0EPEN_PIN            GPIO_PIN_5
+
+#define USB0ID_PERIPH           SYSCTL_PERIPH_GPIOB
+#define USB0ID_PORT             GPIO_PORTB_BASE
+#define USB0ID_PIN              GPIO_PIN_0
+
+#define USB0PFLT_PERIPH         SYSCTL_PERIPH_GPIOC
+#define USB0PFLT_PORT           GPIO_PORTC_BASE
+#define USB0PFLT_PIN            GPIO_PIN_6
+
+#define USB0VBUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define USB0VBUS_PORT           GPIO_PORTB_BASE
+#define USB0VBUS_PIN            GPIO_PIN_1
+
+#endif // PART_LM3S3651
+
+//*****************************************************************************
+//
+// LM3S3654 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S3654
+
+#define GPIO_PA0_U0RX           0x00000001
+
+#define GPIO_PA1_U0TX           0x00000401
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+
+#define GPIO_PA4_SSI0RX         0x00001001
+
+#define GPIO_PA5_SSI0TX         0x00001401
+
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_USB0EPEN       0x00001808
+
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_USB0PFLT       0x00001C08
+
+#define GPIO_PB0_CCP0           0x00010001
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_CCP1           0x00010404
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+#define GPIO_PB2_USB0EPEN       0x00010808
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_USB0PFLT       0x00010C08
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CCP2           0x00011406
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_CCP5           0x00011806
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_CCP3           0x00021405
+#define GPIO_PC5_USB0EPEN       0x00021406
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_CCP0           0x00021806
+#define GPIO_PC6_USB0PFLT       0x00021807
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_USB0PFLT       0x00021C06
+#define GPIO_PC7_C1O            0x00021C07
+
+#define GPIO_PD0_CCP6           0x00030006
+
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_CCP2           0x0003040A
+
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_CCP5           0x00030804
+
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_CCP0           0x00030C04
+
+#define GPIO_PE0_CCP3           0x00040003
+#define GPIO_PE0_USB0PFLT       0x00040009
+
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_CCP2           0x00040805
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_CCP7           0x00040C05
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_CCP2           0x00041006
+
+#endif // PART_LM3S3654
+
+//*****************************************************************************
+//
+// LM3S3739 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S3739
+
+#define ADC0_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC0_PORT               GPIO_PORTE_BASE
+#define ADC0_PIN                GPIO_PIN_7
+
+#define ADC1_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC1_PORT               GPIO_PORTE_BASE
+#define ADC1_PIN                GPIO_PIN_6
+
+#define ADC2_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC2_PORT               GPIO_PORTE_BASE
+#define ADC2_PIN                GPIO_PIN_5
+
+#define ADC3_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC3_PORT               GPIO_PORTE_BASE
+#define ADC3_PIN                GPIO_PIN_4
+
+#define ADC4_PERIPH             SYSCTL_PERIPH_GPIOD
+#define ADC4_PORT               GPIO_PORTD_BASE
+#define ADC4_PIN                GPIO_PIN_7
+
+#define ADC5_PERIPH             SYSCTL_PERIPH_GPIOD
+#define ADC5_PORT               GPIO_PORTD_BASE
+#define ADC5_PIN                GPIO_PIN_6
+
+#define ADC6_PERIPH             SYSCTL_PERIPH_GPIOD
+#define ADC6_PORT               GPIO_PORTD_BASE
+#define ADC6_PIN                GPIO_PIN_5
+
+#define ADC7_PERIPH             SYSCTL_PERIPH_GPIOD
+#define ADC7_PORT               GPIO_PORTD_BASE
+#define ADC7_PIN                GPIO_PIN_4
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOF
+#define C0O_PORT                GPIO_PORTF_BASE
+#define C0O_PIN                 GPIO_PIN_4
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1O_PERIPH              SYSCTL_PERIPH_GPIOF
+#define C1O_PORT                GPIO_PORTF_BASE
+#define C1O_PIN                 GPIO_PIN_5
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_5
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP0_PORT               GPIO_PORTC_BASE
+#define CCP0_PIN                GPIO_PIN_6
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOF
+#define CCP1_PORT               GPIO_PORTF_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP2_PORT               GPIO_PORTC_BASE
+#define CCP2_PIN                GPIO_PIN_4
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOG
+#define CCP3_PORT               GPIO_PORTG_BASE
+#define CCP3_PIN                GPIO_PIN_4
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP4_PORT               GPIO_PORTC_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP5_PORT               GPIO_PORTD_BASE
+#define CCP5_PIN                GPIO_PIN_2
+
+#define CCP6_PERIPH             SYSCTL_PERIPH_GPIOH
+#define CCP6_PORT               GPIO_PORTH_BASE
+#define CCP6_PIN                GPIO_PIN_0
+
+#define CCP7_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP7_PORT               GPIO_PORTD_BASE
+#define CCP7_PIN                GPIO_PIN_3
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define I2C1SCL_PERIPH          SYSCTL_PERIPH_GPIOA
+#define I2C1SCL_PORT            GPIO_PORTA_BASE
+#define I2C1SCL_PIN             GPIO_PIN_6
+
+#define I2C1SDA_PERIPH          SYSCTL_PERIPH_GPIOA
+#define I2C1SDA_PORT            GPIO_PORTA_BASE
+#define I2C1SDA_PIN             GPIO_PIN_7
+
+#define NMI_PERIPH              SYSCTL_PERIPH_GPIOB
+#define NMI_PORT                GPIO_PORTB_BASE
+#define NMI_PIN                 GPIO_PIN_7
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SSI1CLK_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1CLK_PORT            GPIO_PORTE_BASE
+#define SSI1CLK_PIN             GPIO_PIN_0
+
+#define SSI1FSS_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1FSS_PORT            GPIO_PORTE_BASE
+#define SSI1FSS_PIN             GPIO_PIN_1
+
+#define SSI1RX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1RX_PORT             GPIO_PORTE_BASE
+#define SSI1RX_PIN              GPIO_PIN_2
+
+#define SSI1TX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1TX_PORT             GPIO_PORTE_BASE
+#define SSI1TX_PIN              GPIO_PIN_3
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOB
+#define U1RX_PORT               GPIO_PORTB_BASE
+#define U1RX_PIN                GPIO_PIN_0
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOB
+#define U1TX_PORT               GPIO_PORTB_BASE
+#define U1TX_PIN                GPIO_PIN_1
+
+#define U2RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U2RX_PORT               GPIO_PORTD_BASE
+#define U2RX_PIN                GPIO_PIN_0
+
+#define U2TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U2TX_PORT               GPIO_PORTD_BASE
+#define U2TX_PIN                GPIO_PIN_1
+
+#define USB0EPEN_PERIPH         SYSCTL_PERIPH_GPIOH
+#define USB0EPEN_PORT           GPIO_PORTH_BASE
+#define USB0EPEN_PIN            GPIO_PIN_3
+
+#define USB0PFLT_PERIPH         SYSCTL_PERIPH_GPIOH
+#define USB0PFLT_PORT           GPIO_PORTH_BASE
+#define USB0PFLT_PIN            GPIO_PIN_4
+
+#endif // PART_LM3S3739
+
+//*****************************************************************************
+//
+// LM3S3748 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S3748
+
+#define ADC0_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC0_PORT               GPIO_PORTE_BASE
+#define ADC0_PIN                GPIO_PIN_7
+
+#define ADC1_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC1_PORT               GPIO_PORTE_BASE
+#define ADC1_PIN                GPIO_PIN_6
+
+#define ADC2_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC2_PORT               GPIO_PORTE_BASE
+#define ADC2_PIN                GPIO_PIN_5
+
+#define ADC3_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC3_PORT               GPIO_PORTE_BASE
+#define ADC3_PIN                GPIO_PIN_4
+
+#define ADC4_PERIPH             SYSCTL_PERIPH_GPIOD
+#define ADC4_PORT               GPIO_PORTD_BASE
+#define ADC4_PIN                GPIO_PIN_7
+
+#define ADC5_PERIPH             SYSCTL_PERIPH_GPIOD
+#define ADC5_PORT               GPIO_PORTD_BASE
+#define ADC5_PIN                GPIO_PIN_6
+
+#define ADC6_PERIPH             SYSCTL_PERIPH_GPIOD
+#define ADC6_PORT               GPIO_PORTD_BASE
+#define ADC6_PIN                GPIO_PIN_5
+
+#define ADC7_PERIPH             SYSCTL_PERIPH_GPIOD
+#define ADC7_PORT               GPIO_PORTD_BASE
+#define ADC7_PIN                GPIO_PIN_4
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_5
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP0_PORT               GPIO_PORTD_BASE
+#define CCP0_PIN                GPIO_PIN_3
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOF
+#define CCP1_PORT               GPIO_PORTF_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOF
+#define CCP2_PORT               GPIO_PORTF_BASE
+#define CCP2_PIN                GPIO_PIN_5
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOG
+#define CCP3_PORT               GPIO_PORTG_BASE
+#define CCP3_PIN                GPIO_PIN_4
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP4_PORT               GPIO_PORTC_BASE
+#define CCP4_PIN                GPIO_PIN_4
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP5_PORT               GPIO_PORTD_BASE
+#define CCP5_PIN                GPIO_PIN_2
+
+#define CCP6_PERIPH             SYSCTL_PERIPH_GPIOH
+#define CCP6_PORT               GPIO_PORTH_BASE
+#define CCP6_PIN                GPIO_PIN_0
+
+#define CCP7_PERIPH             SYSCTL_PERIPH_GPIOH
+#define CCP7_PORT               GPIO_PORTH_BASE
+#define CCP7_PIN                GPIO_PIN_1
+
+#define FAULT0_PERIPH           SYSCTL_PERIPH_GPIOF
+#define FAULT0_PORT             GPIO_PORTF_BASE
+#define FAULT0_PIN              GPIO_PIN_4
+
+#define FAULT1_PERIPH           SYSCTL_PERIPH_GPIOG
+#define FAULT1_PORT             GPIO_PORTG_BASE
+#define FAULT1_PIN              GPIO_PIN_5
+
+#define FAULT2_PERIPH           SYSCTL_PERIPH_GPIOG
+#define FAULT2_PORT             GPIO_PORTG_BASE
+#define FAULT2_PIN              GPIO_PIN_3
+
+#define FAULT3_PERIPH           SYSCTL_PERIPH_GPIOH
+#define FAULT3_PORT             GPIO_PORTH_BASE
+#define FAULT3_PIN              GPIO_PIN_2
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define I2C1SCL_PERIPH          SYSCTL_PERIPH_GPIOA
+#define I2C1SCL_PORT            GPIO_PORTA_BASE
+#define I2C1SCL_PIN             GPIO_PIN_6
+
+#define I2C1SDA_PERIPH          SYSCTL_PERIPH_GPIOA
+#define I2C1SDA_PORT            GPIO_PORTA_BASE
+#define I2C1SDA_PIN             GPIO_PIN_7
+
+#define IDX0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define IDX0_PORT               GPIO_PORTD_BASE
+#define IDX0_PIN                GPIO_PIN_0
+
+#define NMI_PERIPH              SYSCTL_PERIPH_GPIOB
+#define NMI_PORT                GPIO_PORTB_BASE
+#define NMI_PIN                 GPIO_PIN_7
+
+#define PHA0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PHA0_PORT               GPIO_PORTD_BASE
+#define PHA0_PIN                GPIO_PIN_1
+
+#define PHB0_PERIPH             SYSCTL_PERIPH_GPIOF
+#define PHB0_PORT               GPIO_PORTF_BASE
+#define PHB0_PIN                GPIO_PIN_7
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOF
+#define PWM0_PORT               GPIO_PORTF_BASE
+#define PWM0_PIN                GPIO_PIN_0
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOF
+#define PWM1_PORT               GPIO_PORTF_BASE
+#define PWM1_PIN                GPIO_PIN_1
+
+#define PWM2_PERIPH             SYSCTL_PERIPH_GPIOF
+#define PWM2_PORT               GPIO_PORTF_BASE
+#define PWM2_PIN                GPIO_PIN_2
+
+#define PWM3_PERIPH             SYSCTL_PERIPH_GPIOF
+#define PWM3_PORT               GPIO_PORTF_BASE
+#define PWM3_PIN                GPIO_PIN_3
+
+#define PWM4_PERIPH             SYSCTL_PERIPH_GPIOG
+#define PWM4_PORT               GPIO_PORTG_BASE
+#define PWM4_PIN                GPIO_PIN_0
+
+#define PWM5_PERIPH             SYSCTL_PERIPH_GPIOG
+#define PWM5_PORT               GPIO_PORTG_BASE
+#define PWM5_PIN                GPIO_PIN_1
+
+#define PWM6_PERIPH             SYSCTL_PERIPH_GPIOG
+#define PWM6_PORT               GPIO_PORTG_BASE
+#define PWM6_PIN                GPIO_PIN_6
+
+#define PWM7_PERIPH             SYSCTL_PERIPH_GPIOG
+#define PWM7_PORT               GPIO_PORTG_BASE
+#define PWM7_PIN                GPIO_PIN_7
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SSI1CLK_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1CLK_PORT            GPIO_PORTE_BASE
+#define SSI1CLK_PIN             GPIO_PIN_0
+
+#define SSI1FSS_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1FSS_PORT            GPIO_PORTE_BASE
+#define SSI1FSS_PIN             GPIO_PIN_1
+
+#define SSI1RX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1RX_PORT             GPIO_PORTE_BASE
+#define SSI1RX_PIN              GPIO_PIN_2
+
+#define SSI1TX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1TX_PORT             GPIO_PORTE_BASE
+#define SSI1TX_PIN              GPIO_PIN_3
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOC
+#define U1RX_PORT               GPIO_PORTC_BASE
+#define U1RX_PIN                GPIO_PIN_6
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOC
+#define U1TX_PORT               GPIO_PORTC_BASE
+#define U1TX_PIN                GPIO_PIN_7
+
+#define USB0EPEN_PERIPH         SYSCTL_PERIPH_GPIOH
+#define USB0EPEN_PORT           GPIO_PORTH_BASE
+#define USB0EPEN_PIN            GPIO_PIN_3
+
+#define USB0PFLT_PERIPH         SYSCTL_PERIPH_GPIOH
+#define USB0PFLT_PORT           GPIO_PORTH_BASE
+#define USB0PFLT_PIN            GPIO_PIN_4
+
+#endif // PART_LM3S3748
+
+//*****************************************************************************
+//
+// LM3S3749 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S3749
+
+#define ADC0_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC0_PORT               GPIO_PORTE_BASE
+#define ADC0_PIN                GPIO_PIN_7
+
+#define ADC1_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC1_PORT               GPIO_PORTE_BASE
+#define ADC1_PIN                GPIO_PIN_6
+
+#define ADC2_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC2_PORT               GPIO_PORTE_BASE
+#define ADC2_PIN                GPIO_PIN_5
+
+#define ADC3_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC3_PORT               GPIO_PORTE_BASE
+#define ADC3_PIN                GPIO_PIN_4
+
+#define ADC4_PERIPH             SYSCTL_PERIPH_GPIOD
+#define ADC4_PORT               GPIO_PORTD_BASE
+#define ADC4_PIN                GPIO_PIN_7
+
+#define ADC5_PERIPH             SYSCTL_PERIPH_GPIOD
+#define ADC5_PORT               GPIO_PORTD_BASE
+#define ADC5_PIN                GPIO_PIN_6
+
+#define ADC6_PERIPH             SYSCTL_PERIPH_GPIOD
+#define ADC6_PORT               GPIO_PORTD_BASE
+#define ADC6_PIN                GPIO_PIN_5
+
+#define ADC7_PERIPH             SYSCTL_PERIPH_GPIOD
+#define ADC7_PORT               GPIO_PORTD_BASE
+#define ADC7_PIN                GPIO_PIN_4
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOF
+#define C0O_PORT                GPIO_PORTF_BASE
+#define C0O_PIN                 GPIO_PIN_4
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1O_PERIPH              SYSCTL_PERIPH_GPIOC
+#define C1O_PORT                GPIO_PORTC_BASE
+#define C1O_PIN                 GPIO_PIN_7
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_5
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP0_PORT               GPIO_PORTD_BASE
+#define CCP0_PIN                GPIO_PIN_3
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP1_PORT               GPIO_PORTA_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOF
+#define CCP2_PORT               GPIO_PORTF_BASE
+#define CCP2_PIN                GPIO_PIN_5
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP3_PORT               GPIO_PORTA_BASE
+#define CCP3_PIN                GPIO_PIN_7
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOF
+#define CCP4_PORT               GPIO_PORTF_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP5_PORT               GPIO_PORTC_BASE
+#define CCP5_PIN                GPIO_PIN_4
+
+#define CCP6_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP6_PORT               GPIO_PORTD_BASE
+#define CCP6_PIN                GPIO_PIN_2
+
+#define FAULT0_PERIPH           SYSCTL_PERIPH_GPIOG
+#define FAULT0_PORT             GPIO_PORTG_BASE
+#define FAULT0_PIN              GPIO_PIN_2
+
+#define FAULT1_PERIPH           SYSCTL_PERIPH_GPIOG
+#define FAULT1_PORT             GPIO_PORTG_BASE
+#define FAULT1_PIN              GPIO_PIN_4
+
+#define FAULT2_PERIPH           SYSCTL_PERIPH_GPIOG
+#define FAULT2_PORT             GPIO_PORTG_BASE
+#define FAULT2_PIN              GPIO_PIN_3
+
+#define FAULT3_PERIPH           SYSCTL_PERIPH_GPIOH
+#define FAULT3_PORT             GPIO_PORTH_BASE
+#define FAULT3_PIN              GPIO_PIN_2
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define I2C1SCL_PERIPH          SYSCTL_PERIPH_GPIOG
+#define I2C1SCL_PORT            GPIO_PORTG_BASE
+#define I2C1SCL_PIN             GPIO_PIN_0
+
+#define I2C1SDA_PERIPH          SYSCTL_PERIPH_GPIOG
+#define I2C1SDA_PORT            GPIO_PORTG_BASE
+#define I2C1SDA_PIN             GPIO_PIN_1
+
+#define IDX0_PERIPH             SYSCTL_PERIPH_GPIOG
+#define IDX0_PORT               GPIO_PORTG_BASE
+#define IDX0_PIN                GPIO_PIN_5
+
+#define NMI_PERIPH              SYSCTL_PERIPH_GPIOB
+#define NMI_PORT                GPIO_PORTB_BASE
+#define NMI_PIN                 GPIO_PIN_7
+
+#define PHA0_PERIPH             SYSCTL_PERIPH_GPIOF
+#define PHA0_PORT               GPIO_PORTF_BASE
+#define PHA0_PIN                GPIO_PIN_6
+
+#define PHB0_PERIPH             SYSCTL_PERIPH_GPIOC
+#define PHB0_PORT               GPIO_PORTC_BASE
+#define PHB0_PIN                GPIO_PIN_6
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOF
+#define PWM0_PORT               GPIO_PORTF_BASE
+#define PWM0_PIN                GPIO_PIN_0
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOF
+#define PWM1_PORT               GPIO_PORTF_BASE
+#define PWM1_PIN                GPIO_PIN_1
+
+#define PWM2_PERIPH             SYSCTL_PERIPH_GPIOH
+#define PWM2_PORT               GPIO_PORTH_BASE
+#define PWM2_PIN                GPIO_PIN_0
+
+#define PWM3_PERIPH             SYSCTL_PERIPH_GPIOH
+#define PWM3_PORT               GPIO_PORTH_BASE
+#define PWM3_PIN                GPIO_PIN_1
+
+#define PWM4_PERIPH             SYSCTL_PERIPH_GPIOF
+#define PWM4_PORT               GPIO_PORTF_BASE
+#define PWM4_PIN                GPIO_PIN_2
+
+#define PWM5_PERIPH             SYSCTL_PERIPH_GPIOF
+#define PWM5_PORT               GPIO_PORTF_BASE
+#define PWM5_PIN                GPIO_PIN_3
+
+#define PWM6_PERIPH             SYSCTL_PERIPH_GPIOG
+#define PWM6_PORT               GPIO_PORTG_BASE
+#define PWM6_PIN                GPIO_PIN_6
+
+#define PWM7_PERIPH             SYSCTL_PERIPH_GPIOG
+#define PWM7_PORT               GPIO_PORTG_BASE
+#define PWM7_PIN                GPIO_PIN_7
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SSI1CLK_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1CLK_PORT            GPIO_PORTE_BASE
+#define SSI1CLK_PIN             GPIO_PIN_0
+
+#define SSI1FSS_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1FSS_PORT            GPIO_PORTE_BASE
+#define SSI1FSS_PIN             GPIO_PIN_1
+
+#define SSI1RX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1RX_PORT             GPIO_PORTE_BASE
+#define SSI1RX_PIN              GPIO_PIN_2
+
+#define SSI1TX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1TX_PORT             GPIO_PORTE_BASE
+#define SSI1TX_PIN              GPIO_PIN_3
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOB
+#define U1RX_PORT               GPIO_PORTB_BASE
+#define U1RX_PIN                GPIO_PIN_0
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOB
+#define U1TX_PORT               GPIO_PORTB_BASE
+#define U1TX_PIN                GPIO_PIN_1
+
+#define U2RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U2RX_PORT               GPIO_PORTD_BASE
+#define U2RX_PIN                GPIO_PIN_0
+
+#define U2TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U2TX_PORT               GPIO_PORTD_BASE
+#define U2TX_PIN                GPIO_PIN_1
+
+#define USB0EPEN_PERIPH         SYSCTL_PERIPH_GPIOH
+#define USB0EPEN_PORT           GPIO_PORTH_BASE
+#define USB0EPEN_PIN            GPIO_PIN_3
+
+#define USB0PFLT_PERIPH         SYSCTL_PERIPH_GPIOH
+#define USB0PFLT_PORT           GPIO_PORTH_BASE
+#define USB0PFLT_PIN            GPIO_PIN_4
+
+#endif // PART_LM3S3749
+
+//*****************************************************************************
+//
+// LM3S3826 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S3826
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+
+#define GPIO_PA4_SSI0RX         0x00001001
+
+#define GPIO_PA5_SSI0TX         0x00001401
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_CCP3           0x00001C07
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_U1RX           0x00011007
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_CCP5           0x00011806
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_CCP3           0x00021405
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_C1O            0x00021C07
+
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP2           0x0003040A
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP5           0x00030804
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP0           0x00030C04
+
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_CCP2           0x00040404
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_CCP2           0x00040805
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+
+#endif // PART_LM3S3826
+
+//*****************************************************************************
+//
+// LM3S3J26 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S3J26
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+
+#define GPIO_PA4_SSI0RX         0x00001001
+
+#define GPIO_PA5_SSI0TX         0x00001401
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_CCP3           0x00001C07
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_U1RX           0x00011007
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_CCP5           0x00011806
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_CCP3           0x00021405
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_C1O            0x00021C07
+
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP2           0x0003040A
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP5           0x00030804
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP0           0x00030C04
+
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_CCP2           0x00040404
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_CCP2           0x00040805
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+
+#endif // PART_LM3S3J26
+
+//*****************************************************************************
+//
+// LM3S3N26 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S3N26
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+
+#define GPIO_PA4_SSI0RX         0x00001001
+
+#define GPIO_PA5_SSI0TX         0x00001401
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_CCP3           0x00001C07
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_U1RX           0x00011007
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_CCP5           0x00011806
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_CCP3           0x00021405
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_C1O            0x00021C07
+
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP2           0x0003040A
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP5           0x00030804
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP0           0x00030C04
+
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_CCP2           0x00040404
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_CCP2           0x00040805
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+
+#endif // PART_LM3S3N26
+
+//*****************************************************************************
+//
+// LM3S3W26 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S3W26
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+
+#define GPIO_PA4_SSI0RX         0x00001001
+
+#define GPIO_PA5_SSI0TX         0x00001401
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_CCP3           0x00001C07
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_U1RX           0x00011007
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_CCP5           0x00011806
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_CCP3           0x00021405
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_C1O            0x00021C07
+
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP2           0x0003040A
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP5           0x00030804
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP0           0x00030C04
+
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_CCP2           0x00040404
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_CCP2           0x00040805
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+
+#endif // PART_LM3S3W26
+
+//*****************************************************************************
+//
+// LM3S3Z26 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S3Z26
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+
+#define GPIO_PA4_SSI0RX         0x00001001
+
+#define GPIO_PA5_SSI0TX         0x00001401
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_CCP3           0x00001C07
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_U1RX           0x00011007
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_CCP5           0x00011806
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_CCP3           0x00021405
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_C1O            0x00021C07
+
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP2           0x0003040A
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP5           0x00030804
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP0           0x00030C04
+
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_CCP2           0x00040404
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_CCP2           0x00040805
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+
+#endif // PART_LM3S3Z26
+
+//*****************************************************************************
+//
+// LM3S5632 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S5632
+
+#define ADC0_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC0_PORT               GPIO_PORTE_BASE
+#define ADC0_PIN                GPIO_PIN_3
+
+#define ADC1_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC1_PORT               GPIO_PORTE_BASE
+#define ADC1_PIN                GPIO_PIN_2
+
+#define ADC2_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC2_PORT               GPIO_PORTE_BASE
+#define ADC2_PIN                GPIO_PIN_1
+
+#define ADC3_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC3_PORT               GPIO_PORTE_BASE
+#define ADC3_PIN                GPIO_PIN_0
+
+#define ADC4_PERIPH             SYSCTL_PERIPH_GPIOD
+#define ADC4_PORT               GPIO_PORTD_BASE
+#define ADC4_PIN                GPIO_PIN_3
+
+#define ADC5_PERIPH             SYSCTL_PERIPH_GPIOD
+#define ADC5_PORT               GPIO_PORTD_BASE
+#define ADC5_PIN                GPIO_PIN_2
+
+#define CAN0RX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0RX_PORT             GPIO_PORTD_BASE
+#define CAN0RX_PIN              GPIO_PIN_0
+
+#define CAN0TX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0TX_PORT             GPIO_PORTD_BASE
+#define CAN0TX_PIN              GPIO_PIN_1
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_5
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP1_PORT               GPIO_PORTB_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP2_PORT               GPIO_PORTC_BASE
+#define CCP2_PIN                GPIO_PIN_4
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOE
+#define CCP3_PORT               GPIO_PORTE_BASE
+#define CCP3_PIN                GPIO_PIN_4
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP4_PORT               GPIO_PORTC_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define I2C1SCL_PERIPH          SYSCTL_PERIPH_GPIOA
+#define I2C1SCL_PORT            GPIO_PORTA_BASE
+#define I2C1SCL_PIN             GPIO_PIN_6
+
+#define I2C1SDA_PERIPH          SYSCTL_PERIPH_GPIOA
+#define I2C1SDA_PORT            GPIO_PORTA_BASE
+#define I2C1SDA_PIN             GPIO_PIN_7
+
+#define NMI_PERIPH              SYSCTL_PERIPH_GPIOB
+#define NMI_PORT                GPIO_PORTB_BASE
+#define NMI_PIN                 GPIO_PIN_7
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOB
+#define U1RX_PORT               GPIO_PORTB_BASE
+#define U1RX_PIN                GPIO_PIN_0
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOB
+#define U1TX_PORT               GPIO_PORTB_BASE
+#define U1TX_PIN                GPIO_PIN_1
+
+#define USB0EPEN_PERIPH         SYSCTL_PERIPH_GPIOC
+#define USB0EPEN_PORT           GPIO_PORTC_BASE
+#define USB0EPEN_PIN            GPIO_PIN_5
+
+#define USB0PFLT_PERIPH         SYSCTL_PERIPH_GPIOC
+#define USB0PFLT_PORT           GPIO_PORTC_BASE
+#define USB0PFLT_PIN            GPIO_PIN_6
+
+#endif // PART_LM3S5632
+
+//*****************************************************************************
+//
+// LM3S5651 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S5651
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_PWM4           0x00000804
+#define GPIO_PA2_I2S0RXSD       0x00000809
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_PWM5           0x00000C04
+#define GPIO_PA3_I2S0RXMCLK     0x00000C09
+
+#define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_CAN0RX         0x00001005
+#define GPIO_PA4_I2S0TXSCK      0x00001009
+
+#define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_CAN0TX         0x00001405
+#define GPIO_PA5_I2S0TXWS       0x00001409
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_PWM0           0x00001804
+#define GPIO_PA6_PWM4           0x00001805
+#define GPIO_PA6_CAN0RX         0x00001806
+#define GPIO_PA6_USB0EPEN       0x00001808
+#define GPIO_PA6_U1CTS          0x00001809
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_PWM1           0x00001C04
+#define GPIO_PA7_PWM5           0x00001C05
+#define GPIO_PA7_CAN0TX         0x00001C06
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_USB0PFLT       0x00001C08
+#define GPIO_PA7_U1DCD          0x00001C09
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_PWM2           0x00010002
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_PWM3           0x00010402
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_IDX0           0x00010802
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+#define GPIO_PB2_USB0EPEN       0x00010808
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_FAULT0         0x00010C02
+#define GPIO_PB3_FAULT3         0x00010C04
+#define GPIO_PB3_USB0PFLT       0x00010C08
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_CAN0RX         0x00011005
+#define GPIO_PB4_IDX0           0x00011006
+#define GPIO_PB4_U1RX           0x00011007
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CAN0TX         0x00011405
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_FAULT1         0x00011804
+#define GPIO_PB6_IDX0           0x00011805
+#define GPIO_PB6_CCP5           0x00011806
+#define GPIO_PB6_I2S0TXSCK      0x00011809
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_PHA0           0x00021002
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_FAULT2         0x00021404
+#define GPIO_PC5_CCP3           0x00021405
+#define GPIO_PC5_USB0EPEN       0x00021406
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_PHB0           0x00021802
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+#define GPIO_PC6_USB0PFLT       0x00021807
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_PHB0           0x00021C02
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_USB0PFLT       0x00021C06
+#define GPIO_PC7_C1O            0x00021C07
+
+#define GPIO_PD0_PWM0           0x00030001
+#define GPIO_PD0_CAN0RX         0x00030002
+#define GPIO_PD0_IDX0           0x00030003
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+#define GPIO_PD0_I2S0RXSCK      0x00030008
+#define GPIO_PD0_U1CTS          0x00030009
+
+#define GPIO_PD1_PWM1           0x00030401
+#define GPIO_PD1_CAN0TX         0x00030402
+#define GPIO_PD1_PHA0           0x00030403
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_I2S0RXWS       0x00030408
+#define GPIO_PD1_U1DCD          0x00030409
+#define GPIO_PD1_CCP2           0x0003040A
+#define GPIO_PD1_PHB1           0x0003040B
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_PWM2           0x00030803
+#define GPIO_PD2_CCP5           0x00030804
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_PWM3           0x00030C03
+#define GPIO_PD3_CCP0           0x00030C04
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+#define GPIO_PD4_I2S0RXSD       0x00031008
+#define GPIO_PD4_U1RI           0x00031009
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_I2S0RXMCLK     0x00031408
+#define GPIO_PD5_U2RX           0x00031409
+
+#define GPIO_PD6_FAULT0         0x00031801
+#define GPIO_PD6_I2S0TXSCK      0x00031808
+#define GPIO_PD6_U2TX           0x00031809
+
+#define GPIO_PD7_IDX0           0x00031C01
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+#define GPIO_PD7_I2S0TXWS       0x00031C08
+#define GPIO_PD7_U1DTR          0x00031C09
+
+#define GPIO_PE0_PWM4           0x00040001
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+#define GPIO_PE0_USB0PFLT       0x00040009
+
+#define GPIO_PE1_PWM5           0x00040401
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_FAULT0         0x00040403
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_PHB1           0x00040803
+#define GPIO_PE2_PHA0           0x00040804
+#define GPIO_PE2_CCP2           0x00040805
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_PHA1           0x00040C03
+#define GPIO_PE3_PHB0           0x00040C04
+#define GPIO_PE3_CCP7           0x00040C05
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_FAULT0         0x00041004
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+#define GPIO_PE4_I2S0TXWS       0x00041009
+
+#define GPIO_PE5_CCP5           0x00041401
+#define GPIO_PE5_I2S0TXSD       0x00041409
+
+#define GPIO_PE6_PWM4           0x00041801
+#define GPIO_PE6_C1O            0x00041802
+#define GPIO_PE6_U1CTS          0x00041809
+
+#define GPIO_PE7_PWM5           0x00041C01
+#define GPIO_PE7_U1DCD          0x00041C09
+
+#define GPIO_PF0_CAN1RX         0x00050001
+#define GPIO_PF0_PHB0           0x00050002
+#define GPIO_PF0_PWM0           0x00050003
+#define GPIO_PF0_I2S0TXSD       0x00050008
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_CAN1TX         0x00050401
+#define GPIO_PF1_IDX1           0x00050402
+#define GPIO_PF1_PWM1           0x00050403
+#define GPIO_PF1_I2S0TXMCLK     0x00050408
+#define GPIO_PF1_U1RTS          0x00050409
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_PWM4           0x00050802
+#define GPIO_PF2_PWM2           0x00050804
+#define GPIO_PF2_SSI1CLK        0x00050809
+
+#define GPIO_PF3_PWM5           0x00050C02
+#define GPIO_PF3_PWM3           0x00050C04
+#define GPIO_PF3_SSI1FSS        0x00050C09
+
+#define GPIO_PF4_CCP0           0x00051001
+#define GPIO_PF4_C0O            0x00051002
+#define GPIO_PF4_FAULT0         0x00051004
+#define GPIO_PF4_SSI1RX         0x00051009
+
+#define GPIO_PF5_CCP2           0x00051401
+#define GPIO_PF5_C1O            0x00051402
+#define GPIO_PF5_SSI1TX         0x00051409
+
+#define GPIO_PF6_CCP1           0x00051801
+#define GPIO_PF6_PHA0           0x00051804
+#define GPIO_PF6_I2S0TXMCLK     0x00051809
+#define GPIO_PF6_U1RTS          0x0005180A
+
+#define GPIO_PF7_CCP4           0x00051C01
+#define GPIO_PF7_PHB0           0x00051C04
+#define GPIO_PF7_FAULT1         0x00051C09
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_PWM0           0x00060002
+#define GPIO_PG0_I2C1SCL        0x00060003
+#define GPIO_PG0_PWM4           0x00060004
+#define GPIO_PG0_USB0EPEN       0x00060007
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_PWM1           0x00060402
+#define GPIO_PG1_I2C1SDA        0x00060403
+#define GPIO_PG1_PWM5           0x00060404
+
+#define GPIO_PG2_PWM0           0x00060801
+#define GPIO_PG2_FAULT0         0x00060804
+#define GPIO_PG2_IDX1           0x00060808
+#define GPIO_PG2_I2S0RXSD       0x00060809
+
+#define GPIO_PG3_PWM1           0x00060C01
+#define GPIO_PG3_FAULT2         0x00060C04
+#define GPIO_PG3_FAULT0         0x00060C08
+#define GPIO_PG3_I2S0RXMCLK     0x00060C09
+
+#define GPIO_PG4_CCP3           0x00061001
+#define GPIO_PG4_FAULT1         0x00061004
+#define GPIO_PG4_U1RI           0x0006100A
+
+#define GPIO_PG5_CCP5           0x00061401
+#define GPIO_PG5_IDX0           0x00061404
+#define GPIO_PG5_FAULT1         0x00061405
+#define GPIO_PG5_I2S0RXSCK      0x00061409
+#define GPIO_PG5_U1DTR          0x0006140A
+
+#define GPIO_PG6_PHA1           0x00061801
+#define GPIO_PG6_FAULT1         0x00061808
+#define GPIO_PG6_I2S0RXWS       0x00061809
+#define GPIO_PG6_U1RI           0x0006180A
+
+#define GPIO_PG7_PHB1           0x00061C01
+#define GPIO_PG7_CCP5           0x00061C08
+
+#define GPIO_PH0_CCP6           0x00070001
+#define GPIO_PH0_PWM2           0x00070002
+#define GPIO_PH0_PWM4           0x00070009
+
+#define GPIO_PH1_CCP7           0x00070401
+#define GPIO_PH1_PWM3           0x00070402
+#define GPIO_PH1_PWM5           0x00070409
+
+#define GPIO_PH2_IDX1           0x00070801
+#define GPIO_PH2_C1O            0x00070802
+#define GPIO_PH2_FAULT3         0x00070804
+
+#define GPIO_PH3_PHB0           0x00070C01
+#define GPIO_PH3_FAULT0         0x00070C02
+#define GPIO_PH3_USB0EPEN       0x00070C04
+
+#define GPIO_PH4_USB0PFLT       0x00071004
+#define GPIO_PH4_SSI1CLK        0x0007100B
+
+#define GPIO_PH5_FAULT2         0x0007140A
+#define GPIO_PH5_SSI1FSS        0x0007140B
+
+#define GPIO_PH6_PWM4           0x0007180A
+#define GPIO_PH6_SSI1RX         0x0007180B
+
+#define GPIO_PH7_PWM5           0x00071C0A
+#define GPIO_PH7_SSI1TX         0x00071C0B
+
+#define GPIO_PJ0_PWM0           0x0008000A
+#define GPIO_PJ0_I2C1SCL        0x0008000B
+
+#define GPIO_PJ1_USB0PFLT       0x00080409
+#define GPIO_PJ1_PWM1           0x0008040A
+#define GPIO_PJ1_I2C1SDA        0x0008040B
+
+#define GPIO_PJ2_CCP0           0x00080809
+#define GPIO_PJ2_FAULT0         0x0008080A
+
+#endif // PART_LM3S5651
+
+//*****************************************************************************
+//
+// LM3S5652 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S5652
+
+#define ADC0_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC0_PORT               GPIO_PORTE_BASE
+#define ADC0_PIN                GPIO_PIN_3
+
+#define ADC1_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC1_PORT               GPIO_PORTE_BASE
+#define ADC1_PIN                GPIO_PIN_2
+
+#define ADC2_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC2_PORT               GPIO_PORTE_BASE
+#define ADC2_PIN                GPIO_PIN_1
+
+#define ADC3_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC3_PORT               GPIO_PORTE_BASE
+#define ADC3_PIN                GPIO_PIN_0
+
+#define ADC4_PERIPH             SYSCTL_PERIPH_GPIOD
+#define ADC4_PORT               GPIO_PORTD_BASE
+#define ADC4_PIN                GPIO_PIN_3
+
+#define ADC5_PERIPH             SYSCTL_PERIPH_GPIOD
+#define ADC5_PORT               GPIO_PORTD_BASE
+#define ADC5_PIN                GPIO_PIN_2
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define CAN0RX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0RX_PORT             GPIO_PORTD_BASE
+#define CAN0RX_PIN              GPIO_PIN_0
+
+#define CAN0TX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0TX_PORT             GPIO_PORTD_BASE
+#define CAN0TX_PIN              GPIO_PIN_1
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_5
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP1_PORT               GPIO_PORTA_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOE
+#define CCP2_PORT               GPIO_PORTE_BASE
+#define CCP2_PIN                GPIO_PIN_4
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP3_PORT               GPIO_PORTA_BASE
+#define CCP3_PIN                GPIO_PIN_7
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP4_PORT               GPIO_PORTC_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP5_PORT               GPIO_PORTC_BASE
+#define CCP5_PIN                GPIO_PIN_4
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define NMI_PERIPH              SYSCTL_PERIPH_GPIOB
+#define NMI_PORT                GPIO_PORTB_BASE
+#define NMI_PIN                 GPIO_PIN_7
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define USB0EPEN_PERIPH         SYSCTL_PERIPH_GPIOC
+#define USB0EPEN_PORT           GPIO_PORTC_BASE
+#define USB0EPEN_PIN            GPIO_PIN_5
+
+#define USB0ID_PERIPH           SYSCTL_PERIPH_GPIOB
+#define USB0ID_PORT             GPIO_PORTB_BASE
+#define USB0ID_PIN              GPIO_PIN_0
+
+#define USB0PFLT_PERIPH         SYSCTL_PERIPH_GPIOC
+#define USB0PFLT_PORT           GPIO_PORTC_BASE
+#define USB0PFLT_PIN            GPIO_PIN_6
+
+#define USB0VBUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define USB0VBUS_PORT           GPIO_PORTB_BASE
+#define USB0VBUS_PIN            GPIO_PIN_1
+
+#endif // PART_LM3S5652
+
+//*****************************************************************************
+//
+// LM3S5656 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S5656
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_PWM4           0x00000804
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_PWM5           0x00000C04
+
+#define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_CAN0RX         0x00001005
+
+#define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_CAN0TX         0x00001405
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_PWM0           0x00001804
+#define GPIO_PA6_PWM4           0x00001805
+#define GPIO_PA6_CAN0RX         0x00001806
+#define GPIO_PA6_USB0EPEN       0x00001808
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_PWM1           0x00001C04
+#define GPIO_PA7_PWM5           0x00001C05
+#define GPIO_PA7_CAN0TX         0x00001C06
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_USB0PFLT       0x00001C08
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_PWM2           0x00010002
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_PWM3           0x00010402
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_IDX0           0x00010802
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+#define GPIO_PB2_USB0EPEN       0x00010808
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_FAULT0         0x00010C02
+#define GPIO_PB3_FAULT3         0x00010C04
+#define GPIO_PB3_USB0PFLT       0x00010C08
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_CAN0RX         0x00011005
+#define GPIO_PB4_IDX0           0x00011006
+#define GPIO_PB4_U1RX           0x00011007
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CAN0TX         0x00011405
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_FAULT1         0x00011804
+#define GPIO_PB6_IDX0           0x00011805
+#define GPIO_PB6_CCP5           0x00011806
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_PHA0           0x00021002
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_FAULT2         0x00021404
+#define GPIO_PC5_CCP3           0x00021405
+#define GPIO_PC5_USB0EPEN       0x00021406
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_PHB0           0x00021802
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+#define GPIO_PC6_USB0PFLT       0x00021807
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_PHB0           0x00021C02
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_USB0PFLT       0x00021C06
+#define GPIO_PC7_C1O            0x00021C07
+
+#define GPIO_PD0_PWM0           0x00030001
+#define GPIO_PD0_CAN0RX         0x00030002
+#define GPIO_PD0_IDX0           0x00030003
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+
+#define GPIO_PD1_PWM1           0x00030401
+#define GPIO_PD1_CAN0TX         0x00030402
+#define GPIO_PD1_PHA0           0x00030403
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_CCP2           0x0003040A
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_PWM2           0x00030803
+#define GPIO_PD2_CCP5           0x00030804
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_PWM3           0x00030C03
+#define GPIO_PD3_CCP0           0x00030C04
+
+#define GPIO_PE0_PWM4           0x00040001
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+#define GPIO_PE0_USB0PFLT       0x00040009
+
+#define GPIO_PE1_PWM5           0x00040401
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_FAULT0         0x00040403
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_PHA0           0x00040804
+#define GPIO_PE2_CCP2           0x00040805
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_PHB0           0x00040C04
+#define GPIO_PE3_CCP7           0x00040C05
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_FAULT0         0x00041004
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+
+#endif // PART_LM3S5656
+
+//*****************************************************************************
+//
+// LM3S5662 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S5662
+
+#define ADC0_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC0_PORT               GPIO_PORTE_BASE
+#define ADC0_PIN                GPIO_PIN_3
+
+#define ADC1_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC1_PORT               GPIO_PORTE_BASE
+#define ADC1_PIN                GPIO_PIN_2
+
+#define ADC2_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC2_PORT               GPIO_PORTE_BASE
+#define ADC2_PIN                GPIO_PIN_1
+
+#define ADC3_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC3_PORT               GPIO_PORTE_BASE
+#define ADC3_PIN                GPIO_PIN_0
+
+#define CAN0RX_PERIPH           SYSCTL_PERIPH_GPIOB
+#define CAN0RX_PORT             GPIO_PORTB_BASE
+#define CAN0RX_PIN              GPIO_PIN_4
+
+#define CAN0TX_PERIPH           SYSCTL_PERIPH_GPIOB
+#define CAN0TX_PORT             GPIO_PORTB_BASE
+#define CAN0TX_PIN              GPIO_PIN_5
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_2
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP1_PORT               GPIO_PORTB_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP2_PORT               GPIO_PORTC_BASE
+#define CCP2_PIN                GPIO_PIN_4
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOE
+#define CCP3_PORT               GPIO_PORTE_BASE
+#define CCP3_PIN                GPIO_PIN_4
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP4_PORT               GPIO_PORTC_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define FAULT0_PERIPH           SYSCTL_PERIPH_GPIOB
+#define FAULT0_PORT             GPIO_PORTB_BASE
+#define FAULT0_PIN              GPIO_PIN_3
+
+#define NMI_PERIPH              SYSCTL_PERIPH_GPIOB
+#define NMI_PORT                GPIO_PORTB_BASE
+#define NMI_PIN                 GPIO_PIN_7
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM0_PORT               GPIO_PORTD_BASE
+#define PWM0_PIN                GPIO_PIN_0
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM1_PORT               GPIO_PORTD_BASE
+#define PWM1_PIN                GPIO_PIN_1
+
+#define PWM2_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM2_PORT               GPIO_PORTD_BASE
+#define PWM2_PIN                GPIO_PIN_2
+
+#define PWM3_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM3_PORT               GPIO_PORTD_BASE
+#define PWM3_PIN                GPIO_PIN_3
+
+#define PWM4_PERIPH             SYSCTL_PERIPH_GPIOA
+#define PWM4_PORT               GPIO_PORTA_BASE
+#define PWM4_PIN                GPIO_PIN_6
+
+#define PWM5_PERIPH             SYSCTL_PERIPH_GPIOA
+#define PWM5_PORT               GPIO_PORTA_BASE
+#define PWM5_PIN                GPIO_PIN_7
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define USB0EPEN_PERIPH         SYSCTL_PERIPH_GPIOC
+#define USB0EPEN_PORT           GPIO_PORTC_BASE
+#define USB0EPEN_PIN            GPIO_PIN_5
+
+#define USB0ID_PERIPH           SYSCTL_PERIPH_GPIOB
+#define USB0ID_PORT             GPIO_PORTB_BASE
+#define USB0ID_PIN              GPIO_PIN_0
+
+#define USB0PFLT_PERIPH         SYSCTL_PERIPH_GPIOC
+#define USB0PFLT_PORT           GPIO_PORTC_BASE
+#define USB0PFLT_PIN            GPIO_PIN_6
+
+#define USB0VBUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define USB0VBUS_PORT           GPIO_PORTB_BASE
+#define USB0VBUS_PIN            GPIO_PIN_1
+
+#endif // PART_LM3S5662
+
+//*****************************************************************************
+//
+// LM3S5732 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S5732
+
+#define ADC0_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC0_PORT               GPIO_PORTE_BASE
+#define ADC0_PIN                GPIO_PIN_3
+
+#define ADC1_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC1_PORT               GPIO_PORTE_BASE
+#define ADC1_PIN                GPIO_PIN_2
+
+#define ADC2_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC2_PORT               GPIO_PORTE_BASE
+#define ADC2_PIN                GPIO_PIN_1
+
+#define ADC3_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC3_PORT               GPIO_PORTE_BASE
+#define ADC3_PIN                GPIO_PIN_0
+
+#define ADC4_PERIPH             SYSCTL_PERIPH_GPIOD
+#define ADC4_PORT               GPIO_PORTD_BASE
+#define ADC4_PIN                GPIO_PIN_3
+
+#define ADC5_PERIPH             SYSCTL_PERIPH_GPIOD
+#define ADC5_PORT               GPIO_PORTD_BASE
+#define ADC5_PIN                GPIO_PIN_2
+
+#define CAN0RX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0RX_PORT             GPIO_PORTD_BASE
+#define CAN0RX_PIN              GPIO_PIN_0
+
+#define CAN0TX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0TX_PORT             GPIO_PORTD_BASE
+#define CAN0TX_PIN              GPIO_PIN_1
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_5
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP1_PORT               GPIO_PORTB_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP2_PORT               GPIO_PORTC_BASE
+#define CCP2_PIN                GPIO_PIN_4
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOE
+#define CCP3_PORT               GPIO_PORTE_BASE
+#define CCP3_PIN                GPIO_PIN_4
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP4_PORT               GPIO_PORTC_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define I2C1SCL_PERIPH          SYSCTL_PERIPH_GPIOA
+#define I2C1SCL_PORT            GPIO_PORTA_BASE
+#define I2C1SCL_PIN             GPIO_PIN_6
+
+#define I2C1SDA_PERIPH          SYSCTL_PERIPH_GPIOA
+#define I2C1SDA_PORT            GPIO_PORTA_BASE
+#define I2C1SDA_PIN             GPIO_PIN_7
+
+#define NMI_PERIPH              SYSCTL_PERIPH_GPIOB
+#define NMI_PORT                GPIO_PORTB_BASE
+#define NMI_PIN                 GPIO_PIN_7
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOB
+#define U1RX_PORT               GPIO_PORTB_BASE
+#define U1RX_PIN                GPIO_PIN_0
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOB
+#define U1TX_PORT               GPIO_PORTB_BASE
+#define U1TX_PIN                GPIO_PIN_1
+
+#define USB0EPEN_PERIPH         SYSCTL_PERIPH_GPIOC
+#define USB0EPEN_PORT           GPIO_PORTC_BASE
+#define USB0EPEN_PIN            GPIO_PIN_5
+
+#define USB0PFLT_PERIPH         SYSCTL_PERIPH_GPIOC
+#define USB0PFLT_PORT           GPIO_PORTC_BASE
+#define USB0PFLT_PIN            GPIO_PIN_6
+
+#endif // PART_LM3S5732
+
+//*****************************************************************************
+//
+// LM3S5737 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S5737
+
+#define ADC0_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC0_PORT               GPIO_PORTE_BASE
+#define ADC0_PIN                GPIO_PIN_7
+
+#define ADC1_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC1_PORT               GPIO_PORTE_BASE
+#define ADC1_PIN                GPIO_PIN_6
+
+#define ADC2_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC2_PORT               GPIO_PORTE_BASE
+#define ADC2_PIN                GPIO_PIN_5
+
+#define ADC3_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC3_PORT               GPIO_PORTE_BASE
+#define ADC3_PIN                GPIO_PIN_4
+
+#define ADC4_PERIPH             SYSCTL_PERIPH_GPIOD
+#define ADC4_PORT               GPIO_PORTD_BASE
+#define ADC4_PIN                GPIO_PIN_7
+
+#define ADC5_PERIPH             SYSCTL_PERIPH_GPIOD
+#define ADC5_PORT               GPIO_PORTD_BASE
+#define ADC5_PIN                GPIO_PIN_6
+
+#define ADC6_PERIPH             SYSCTL_PERIPH_GPIOD
+#define ADC6_PORT               GPIO_PORTD_BASE
+#define ADC6_PIN                GPIO_PIN_5
+
+#define ADC7_PERIPH             SYSCTL_PERIPH_GPIOD
+#define ADC7_PORT               GPIO_PORTD_BASE
+#define ADC7_PIN                GPIO_PIN_4
+
+#define CAN0RX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0RX_PORT             GPIO_PORTD_BASE
+#define CAN0RX_PIN              GPIO_PIN_0
+
+#define CAN0TX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0TX_PORT             GPIO_PORTD_BASE
+#define CAN0TX_PIN              GPIO_PIN_1
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP1_PORT               GPIO_PORTB_BASE
+#define CCP1_PIN                GPIO_PIN_1
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_5
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define I2C1SCL_PERIPH          SYSCTL_PERIPH_GPIOA
+#define I2C1SCL_PORT            GPIO_PORTA_BASE
+#define I2C1SCL_PIN             GPIO_PIN_6
+
+#define I2C1SDA_PERIPH          SYSCTL_PERIPH_GPIOA
+#define I2C1SDA_PORT            GPIO_PORTA_BASE
+#define I2C1SDA_PIN             GPIO_PIN_7
+
+#define NMI_PERIPH              SYSCTL_PERIPH_GPIOB
+#define NMI_PORT                GPIO_PORTB_BASE
+#define NMI_PIN                 GPIO_PIN_7
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SSI1CLK_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1CLK_PORT            GPIO_PORTE_BASE
+#define SSI1CLK_PIN             GPIO_PIN_0
+
+#define SSI1FSS_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1FSS_PORT            GPIO_PORTE_BASE
+#define SSI1FSS_PIN             GPIO_PIN_1
+
+#define SSI1RX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1RX_PORT             GPIO_PORTE_BASE
+#define SSI1RX_PIN              GPIO_PIN_2
+
+#define SSI1TX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1TX_PORT             GPIO_PORTE_BASE
+#define SSI1TX_PIN              GPIO_PIN_3
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define USB0EPEN_PERIPH         SYSCTL_PERIPH_GPIOC
+#define USB0EPEN_PORT           GPIO_PORTC_BASE
+#define USB0EPEN_PIN            GPIO_PIN_5
+
+#define USB0PFLT_PERIPH         SYSCTL_PERIPH_GPIOC
+#define USB0PFLT_PORT           GPIO_PORTC_BASE
+#define USB0PFLT_PIN            GPIO_PIN_6
+
+#endif // PART_LM3S5737
+
+//*****************************************************************************
+//
+// LM3S5739 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S5739
+
+#define ADC0_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC0_PORT               GPIO_PORTE_BASE
+#define ADC0_PIN                GPIO_PIN_7
+
+#define ADC1_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC1_PORT               GPIO_PORTE_BASE
+#define ADC1_PIN                GPIO_PIN_6
+
+#define ADC2_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC2_PORT               GPIO_PORTE_BASE
+#define ADC2_PIN                GPIO_PIN_5
+
+#define ADC3_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC3_PORT               GPIO_PORTE_BASE
+#define ADC3_PIN                GPIO_PIN_4
+
+#define ADC4_PERIPH             SYSCTL_PERIPH_GPIOD
+#define ADC4_PORT               GPIO_PORTD_BASE
+#define ADC4_PIN                GPIO_PIN_7
+
+#define ADC5_PERIPH             SYSCTL_PERIPH_GPIOD
+#define ADC5_PORT               GPIO_PORTD_BASE
+#define ADC5_PIN                GPIO_PIN_6
+
+#define ADC6_PERIPH             SYSCTL_PERIPH_GPIOD
+#define ADC6_PORT               GPIO_PORTD_BASE
+#define ADC6_PIN                GPIO_PIN_5
+
+#define ADC7_PERIPH             SYSCTL_PERIPH_GPIOD
+#define ADC7_PORT               GPIO_PORTD_BASE
+#define ADC7_PIN                GPIO_PIN_4
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOF
+#define C0O_PORT                GPIO_PORTF_BASE
+#define C0O_PIN                 GPIO_PIN_4
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1O_PERIPH              SYSCTL_PERIPH_GPIOF
+#define C1O_PORT                GPIO_PORTF_BASE
+#define C1O_PIN                 GPIO_PIN_5
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_5
+
+#define CAN0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define CAN0RX_PORT             GPIO_PORTA_BASE
+#define CAN0RX_PIN              GPIO_PIN_6
+
+#define CAN0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define CAN0TX_PORT             GPIO_PORTA_BASE
+#define CAN0TX_PIN              GPIO_PIN_7
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP0_PORT               GPIO_PORTC_BASE
+#define CCP0_PIN                GPIO_PIN_6
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOF
+#define CCP1_PORT               GPIO_PORTF_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP2_PORT               GPIO_PORTC_BASE
+#define CCP2_PIN                GPIO_PIN_4
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOG
+#define CCP3_PORT               GPIO_PORTG_BASE
+#define CCP3_PIN                GPIO_PIN_4
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP4_PORT               GPIO_PORTC_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP5_PORT               GPIO_PORTD_BASE
+#define CCP5_PIN                GPIO_PIN_2
+
+#define CCP6_PERIPH             SYSCTL_PERIPH_GPIOH
+#define CCP6_PORT               GPIO_PORTH_BASE
+#define CCP6_PIN                GPIO_PIN_0
+
+#define CCP7_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP7_PORT               GPIO_PORTD_BASE
+#define CCP7_PIN                GPIO_PIN_3
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define I2C1SCL_PERIPH          SYSCTL_PERIPH_GPIOG
+#define I2C1SCL_PORT            GPIO_PORTG_BASE
+#define I2C1SCL_PIN             GPIO_PIN_0
+
+#define I2C1SDA_PERIPH          SYSCTL_PERIPH_GPIOG
+#define I2C1SDA_PORT            GPIO_PORTG_BASE
+#define I2C1SDA_PIN             GPIO_PIN_1
+
+#define NMI_PERIPH              SYSCTL_PERIPH_GPIOB
+#define NMI_PORT                GPIO_PORTB_BASE
+#define NMI_PIN                 GPIO_PIN_7
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SSI1CLK_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1CLK_PORT            GPIO_PORTE_BASE
+#define SSI1CLK_PIN             GPIO_PIN_0
+
+#define SSI1FSS_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1FSS_PORT            GPIO_PORTE_BASE
+#define SSI1FSS_PIN             GPIO_PIN_1
+
+#define SSI1RX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1RX_PORT             GPIO_PORTE_BASE
+#define SSI1RX_PIN              GPIO_PIN_2
+
+#define SSI1TX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1TX_PORT             GPIO_PORTE_BASE
+#define SSI1TX_PIN              GPIO_PIN_3
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOB
+#define U1RX_PORT               GPIO_PORTB_BASE
+#define U1RX_PIN                GPIO_PIN_0
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOB
+#define U1TX_PORT               GPIO_PORTB_BASE
+#define U1TX_PIN                GPIO_PIN_1
+
+#define U2RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U2RX_PORT               GPIO_PORTD_BASE
+#define U2RX_PIN                GPIO_PIN_0
+
+#define U2TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U2TX_PORT               GPIO_PORTD_BASE
+#define U2TX_PIN                GPIO_PIN_1
+
+#define USB0EPEN_PERIPH         SYSCTL_PERIPH_GPIOH
+#define USB0EPEN_PORT           GPIO_PORTH_BASE
+#define USB0EPEN_PIN            GPIO_PIN_3
+
+#define USB0PFLT_PERIPH         SYSCTL_PERIPH_GPIOH
+#define USB0PFLT_PORT           GPIO_PORTH_BASE
+#define USB0PFLT_PIN            GPIO_PIN_4
+
+#endif // PART_LM3S5739
+
+//*****************************************************************************
+//
+// LM3S5747 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S5747
+
+#define ADC0_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC0_PORT               GPIO_PORTE_BASE
+#define ADC0_PIN                GPIO_PIN_7
+
+#define ADC1_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC1_PORT               GPIO_PORTE_BASE
+#define ADC1_PIN                GPIO_PIN_6
+
+#define ADC2_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC2_PORT               GPIO_PORTE_BASE
+#define ADC2_PIN                GPIO_PIN_5
+
+#define ADC3_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC3_PORT               GPIO_PORTE_BASE
+#define ADC3_PIN                GPIO_PIN_4
+
+#define ADC4_PERIPH             SYSCTL_PERIPH_GPIOD
+#define ADC4_PORT               GPIO_PORTD_BASE
+#define ADC4_PIN                GPIO_PIN_7
+
+#define ADC5_PERIPH             SYSCTL_PERIPH_GPIOD
+#define ADC5_PORT               GPIO_PORTD_BASE
+#define ADC5_PIN                GPIO_PIN_6
+
+#define ADC6_PERIPH             SYSCTL_PERIPH_GPIOD
+#define ADC6_PORT               GPIO_PORTD_BASE
+#define ADC6_PIN                GPIO_PIN_5
+
+#define ADC7_PERIPH             SYSCTL_PERIPH_GPIOD
+#define ADC7_PORT               GPIO_PORTD_BASE
+#define ADC7_PIN                GPIO_PIN_4
+
+#define CAN0RX_PERIPH           SYSCTL_PERIPH_GPIOB
+#define CAN0RX_PORT             GPIO_PORTB_BASE
+#define CAN0RX_PIN              GPIO_PIN_4
+
+#define CAN0TX_PERIPH           SYSCTL_PERIPH_GPIOB
+#define CAN0TX_PORT             GPIO_PORTB_BASE
+#define CAN0TX_PIN              GPIO_PIN_5
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP1_PORT               GPIO_PORTA_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define FAULT0_PERIPH           SYSCTL_PERIPH_GPIOE
+#define FAULT0_PORT             GPIO_PORTE_BASE
+#define FAULT0_PIN              GPIO_PIN_1
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define NMI_PERIPH              SYSCTL_PERIPH_GPIOB
+#define NMI_PORT                GPIO_PORTB_BASE
+#define NMI_PIN                 GPIO_PIN_7
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM0_PORT               GPIO_PORTD_BASE
+#define PWM0_PIN                GPIO_PIN_0
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM1_PORT               GPIO_PORTD_BASE
+#define PWM1_PIN                GPIO_PIN_1
+
+#define PWM2_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM2_PORT               GPIO_PORTD_BASE
+#define PWM2_PIN                GPIO_PIN_2
+
+#define PWM3_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM3_PORT               GPIO_PORTD_BASE
+#define PWM3_PIN                GPIO_PIN_3
+
+#define PWM4_PERIPH             SYSCTL_PERIPH_GPIOF
+#define PWM4_PORT               GPIO_PORTF_BASE
+#define PWM4_PIN                GPIO_PIN_2
+
+#define PWM5_PERIPH             SYSCTL_PERIPH_GPIOF
+#define PWM5_PORT               GPIO_PORTF_BASE
+#define PWM5_PIN                GPIO_PIN_3
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define USB0EPEN_PERIPH         SYSCTL_PERIPH_GPIOC
+#define USB0EPEN_PORT           GPIO_PORTC_BASE
+#define USB0EPEN_PIN            GPIO_PIN_5
+
+#define USB0PFLT_PERIPH         SYSCTL_PERIPH_GPIOC
+#define USB0PFLT_PORT           GPIO_PORTC_BASE
+#define USB0PFLT_PIN            GPIO_PIN_6
+
+#endif // PART_LM3S5747
+
+//*****************************************************************************
+//
+// LM3S5749 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S5749
+
+#define ADC0_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC0_PORT               GPIO_PORTE_BASE
+#define ADC0_PIN                GPIO_PIN_7
+
+#define ADC1_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC1_PORT               GPIO_PORTE_BASE
+#define ADC1_PIN                GPIO_PIN_6
+
+#define ADC2_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC2_PORT               GPIO_PORTE_BASE
+#define ADC2_PIN                GPIO_PIN_5
+
+#define ADC3_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC3_PORT               GPIO_PORTE_BASE
+#define ADC3_PIN                GPIO_PIN_4
+
+#define ADC4_PERIPH             SYSCTL_PERIPH_GPIOD
+#define ADC4_PORT               GPIO_PORTD_BASE
+#define ADC4_PIN                GPIO_PIN_7
+
+#define ADC5_PERIPH             SYSCTL_PERIPH_GPIOD
+#define ADC5_PORT               GPIO_PORTD_BASE
+#define ADC5_PIN                GPIO_PIN_6
+
+#define ADC6_PERIPH             SYSCTL_PERIPH_GPIOD
+#define ADC6_PORT               GPIO_PORTD_BASE
+#define ADC6_PIN                GPIO_PIN_5
+
+#define ADC7_PERIPH             SYSCTL_PERIPH_GPIOD
+#define ADC7_PORT               GPIO_PORTD_BASE
+#define ADC7_PIN                GPIO_PIN_4
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOF
+#define C0O_PORT                GPIO_PORTF_BASE
+#define C0O_PIN                 GPIO_PIN_4
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1O_PERIPH              SYSCTL_PERIPH_GPIOF
+#define C1O_PORT                GPIO_PORTF_BASE
+#define C1O_PIN                 GPIO_PIN_5
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_5
+
+#define CAN0RX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0RX_PORT             GPIO_PORTD_BASE
+#define CAN0RX_PIN              GPIO_PIN_0
+
+#define CAN0TX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0TX_PORT             GPIO_PORTD_BASE
+#define CAN0TX_PIN              GPIO_PIN_1
+
+#define CAN1RX_PERIPH           SYSCTL_PERIPH_GPIOF
+#define CAN1RX_PORT             GPIO_PORTF_BASE
+#define CAN1RX_PIN              GPIO_PIN_0
+
+#define CAN1TX_PERIPH           SYSCTL_PERIPH_GPIOF
+#define CAN1TX_PORT             GPIO_PORTF_BASE
+#define CAN1TX_PIN              GPIO_PIN_1
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP1_PORT               GPIO_PORTB_BASE
+#define CCP1_PIN                GPIO_PIN_1
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP2_PORT               GPIO_PORTC_BASE
+#define CCP2_PIN                GPIO_PIN_4
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP3_PORT               GPIO_PORTC_BASE
+#define CCP3_PIN                GPIO_PIN_6
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP4_PORT               GPIO_PORTC_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define FAULT0_PERIPH           SYSCTL_PERIPH_GPIOG
+#define FAULT0_PORT             GPIO_PORTG_BASE
+#define FAULT0_PIN              GPIO_PIN_2
+
+#define FAULT1_PERIPH           SYSCTL_PERIPH_GPIOG
+#define FAULT1_PORT             GPIO_PORTG_BASE
+#define FAULT1_PIN              GPIO_PIN_4
+
+#define FAULT2_PERIPH           SYSCTL_PERIPH_GPIOG
+#define FAULT2_PORT             GPIO_PORTG_BASE
+#define FAULT2_PIN              GPIO_PIN_3
+
+#define FAULT3_PERIPH           SYSCTL_PERIPH_GPIOH
+#define FAULT3_PORT             GPIO_PORTH_BASE
+#define FAULT3_PIN              GPIO_PIN_2
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define I2C1SCL_PERIPH          SYSCTL_PERIPH_GPIOA
+#define I2C1SCL_PORT            GPIO_PORTA_BASE
+#define I2C1SCL_PIN             GPIO_PIN_6
+
+#define I2C1SDA_PERIPH          SYSCTL_PERIPH_GPIOA
+#define I2C1SDA_PORT            GPIO_PORTA_BASE
+#define I2C1SDA_PIN             GPIO_PIN_7
+
+#define IDX0_PERIPH             SYSCTL_PERIPH_GPIOG
+#define IDX0_PORT               GPIO_PORTG_BASE
+#define IDX0_PIN                GPIO_PIN_5
+
+#define NMI_PERIPH              SYSCTL_PERIPH_GPIOB
+#define NMI_PORT                GPIO_PORTB_BASE
+#define NMI_PIN                 GPIO_PIN_7
+
+#define PHA0_PERIPH             SYSCTL_PERIPH_GPIOF
+#define PHA0_PORT               GPIO_PORTF_BASE
+#define PHA0_PIN                GPIO_PIN_6
+
+#define PHB0_PERIPH             SYSCTL_PERIPH_GPIOF
+#define PHB0_PORT               GPIO_PORTF_BASE
+#define PHB0_PIN                GPIO_PIN_7
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOG
+#define PWM0_PORT               GPIO_PORTG_BASE
+#define PWM0_PIN                GPIO_PIN_0
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOG
+#define PWM1_PORT               GPIO_PORTG_BASE
+#define PWM1_PIN                GPIO_PIN_1
+
+#define PWM2_PERIPH             SYSCTL_PERIPH_GPIOH
+#define PWM2_PORT               GPIO_PORTH_BASE
+#define PWM2_PIN                GPIO_PIN_0
+
+#define PWM3_PERIPH             SYSCTL_PERIPH_GPIOH
+#define PWM3_PORT               GPIO_PORTH_BASE
+#define PWM3_PIN                GPIO_PIN_1
+
+#define PWM4_PERIPH             SYSCTL_PERIPH_GPIOF
+#define PWM4_PORT               GPIO_PORTF_BASE
+#define PWM4_PIN                GPIO_PIN_2
+
+#define PWM5_PERIPH             SYSCTL_PERIPH_GPIOF
+#define PWM5_PORT               GPIO_PORTF_BASE
+#define PWM5_PIN                GPIO_PIN_3
+
+#define PWM6_PERIPH             SYSCTL_PERIPH_GPIOG
+#define PWM6_PORT               GPIO_PORTG_BASE
+#define PWM6_PIN                GPIO_PIN_6
+
+#define PWM7_PERIPH             SYSCTL_PERIPH_GPIOG
+#define PWM7_PORT               GPIO_PORTG_BASE
+#define PWM7_PIN                GPIO_PIN_7
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SSI1CLK_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1CLK_PORT            GPIO_PORTE_BASE
+#define SSI1CLK_PIN             GPIO_PIN_0
+
+#define SSI1FSS_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1FSS_PORT            GPIO_PORTE_BASE
+#define SSI1FSS_PIN             GPIO_PIN_1
+
+#define SSI1RX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1RX_PORT             GPIO_PORTE_BASE
+#define SSI1RX_PIN              GPIO_PIN_2
+
+#define SSI1TX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1TX_PORT             GPIO_PORTE_BASE
+#define SSI1TX_PIN              GPIO_PIN_3
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#define USB0EPEN_PERIPH         SYSCTL_PERIPH_GPIOH
+#define USB0EPEN_PORT           GPIO_PORTH_BASE
+#define USB0EPEN_PIN            GPIO_PIN_3
+
+#define USB0PFLT_PERIPH         SYSCTL_PERIPH_GPIOH
+#define USB0PFLT_PORT           GPIO_PORTH_BASE
+#define USB0PFLT_PIN            GPIO_PIN_4
+
+#endif // PART_LM3S5749
+
+//*****************************************************************************
+//
+// LM3S5752 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S5752
+
+#define ADC0_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC0_PORT               GPIO_PORTE_BASE
+#define ADC0_PIN                GPIO_PIN_3
+
+#define ADC1_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC1_PORT               GPIO_PORTE_BASE
+#define ADC1_PIN                GPIO_PIN_2
+
+#define ADC2_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC2_PORT               GPIO_PORTE_BASE
+#define ADC2_PIN                GPIO_PIN_1
+
+#define ADC3_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC3_PORT               GPIO_PORTE_BASE
+#define ADC3_PIN                GPIO_PIN_0
+
+#define ADC4_PERIPH             SYSCTL_PERIPH_GPIOD
+#define ADC4_PORT               GPIO_PORTD_BASE
+#define ADC4_PIN                GPIO_PIN_3
+
+#define ADC5_PERIPH             SYSCTL_PERIPH_GPIOD
+#define ADC5_PORT               GPIO_PORTD_BASE
+#define ADC5_PIN                GPIO_PIN_2
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define CAN0RX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0RX_PORT             GPIO_PORTD_BASE
+#define CAN0RX_PIN              GPIO_PIN_0
+
+#define CAN0TX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0TX_PORT             GPIO_PORTD_BASE
+#define CAN0TX_PIN              GPIO_PIN_1
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_5
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP1_PORT               GPIO_PORTA_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOE
+#define CCP2_PORT               GPIO_PORTE_BASE
+#define CCP2_PIN                GPIO_PIN_4
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP3_PORT               GPIO_PORTA_BASE
+#define CCP3_PIN                GPIO_PIN_7
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP4_PORT               GPIO_PORTC_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP5_PORT               GPIO_PORTC_BASE
+#define CCP5_PIN                GPIO_PIN_4
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define NMI_PERIPH              SYSCTL_PERIPH_GPIOB
+#define NMI_PORT                GPIO_PORTB_BASE
+#define NMI_PIN                 GPIO_PIN_7
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define USB0EPEN_PERIPH         SYSCTL_PERIPH_GPIOC
+#define USB0EPEN_PORT           GPIO_PORTC_BASE
+#define USB0EPEN_PIN            GPIO_PIN_5
+
+#define USB0ID_PERIPH           SYSCTL_PERIPH_GPIOB
+#define USB0ID_PORT             GPIO_PORTB_BASE
+#define USB0ID_PIN              GPIO_PIN_0
+
+#define USB0PFLT_PERIPH         SYSCTL_PERIPH_GPIOC
+#define USB0PFLT_PORT           GPIO_PORTC_BASE
+#define USB0PFLT_PIN            GPIO_PIN_6
+
+#define USB0VBUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define USB0VBUS_PORT           GPIO_PORTB_BASE
+#define USB0VBUS_PIN            GPIO_PIN_1
+
+#endif // PART_LM3S5752
+
+//*****************************************************************************
+//
+// LM3S5762 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S5762
+
+#define ADC0_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC0_PORT               GPIO_PORTE_BASE
+#define ADC0_PIN                GPIO_PIN_3
+
+#define ADC1_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC1_PORT               GPIO_PORTE_BASE
+#define ADC1_PIN                GPIO_PIN_2
+
+#define ADC2_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC2_PORT               GPIO_PORTE_BASE
+#define ADC2_PIN                GPIO_PIN_1
+
+#define ADC3_PERIPH             SYSCTL_PERIPH_GPIOE
+#define ADC3_PORT               GPIO_PORTE_BASE
+#define ADC3_PIN                GPIO_PIN_0
+
+#define CAN0RX_PERIPH           SYSCTL_PERIPH_GPIOB
+#define CAN0RX_PORT             GPIO_PORTB_BASE
+#define CAN0RX_PIN              GPIO_PIN_4
+
+#define CAN0TX_PERIPH           SYSCTL_PERIPH_GPIOB
+#define CAN0TX_PORT             GPIO_PORTB_BASE
+#define CAN0TX_PIN              GPIO_PIN_5
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_2
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP1_PORT               GPIO_PORTB_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP2_PORT               GPIO_PORTC_BASE
+#define CCP2_PIN                GPIO_PIN_4
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOE
+#define CCP3_PORT               GPIO_PORTE_BASE
+#define CCP3_PIN                GPIO_PIN_4
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP4_PORT               GPIO_PORTC_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define FAULT0_PERIPH           SYSCTL_PERIPH_GPIOB
+#define FAULT0_PORT             GPIO_PORTB_BASE
+#define FAULT0_PIN              GPIO_PIN_3
+
+#define NMI_PERIPH              SYSCTL_PERIPH_GPIOB
+#define NMI_PORT                GPIO_PORTB_BASE
+#define NMI_PIN                 GPIO_PIN_7
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM0_PORT               GPIO_PORTD_BASE
+#define PWM0_PIN                GPIO_PIN_0
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM1_PORT               GPIO_PORTD_BASE
+#define PWM1_PIN                GPIO_PIN_1
+
+#define PWM2_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM2_PORT               GPIO_PORTD_BASE
+#define PWM2_PIN                GPIO_PIN_2
+
+#define PWM3_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM3_PORT               GPIO_PORTD_BASE
+#define PWM3_PIN                GPIO_PIN_3
+
+#define PWM4_PERIPH             SYSCTL_PERIPH_GPIOA
+#define PWM4_PORT               GPIO_PORTA_BASE
+#define PWM4_PIN                GPIO_PIN_6
+
+#define PWM5_PERIPH             SYSCTL_PERIPH_GPIOA
+#define PWM5_PORT               GPIO_PORTA_BASE
+#define PWM5_PIN                GPIO_PIN_7
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define USB0EPEN_PERIPH         SYSCTL_PERIPH_GPIOC
+#define USB0EPEN_PORT           GPIO_PORTC_BASE
+#define USB0EPEN_PIN            GPIO_PIN_5
+
+#define USB0ID_PERIPH           SYSCTL_PERIPH_GPIOB
+#define USB0ID_PORT             GPIO_PORTB_BASE
+#define USB0ID_PIN              GPIO_PIN_0
+
+#define USB0PFLT_PERIPH         SYSCTL_PERIPH_GPIOC
+#define USB0PFLT_PORT           GPIO_PORTC_BASE
+#define USB0PFLT_PIN            GPIO_PIN_6
+
+#define USB0VBUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define USB0VBUS_PORT           GPIO_PORTB_BASE
+#define USB0VBUS_PIN            GPIO_PIN_1
+
+#endif // PART_LM3S5762
+
+//*****************************************************************************
+//
+// LM3S5791 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S5791
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_PWM4           0x00000804
+#define GPIO_PA2_I2S0RXSD       0x00000809
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_PWM5           0x00000C04
+#define GPIO_PA3_I2S0RXMCLK     0x00000C09
+
+#define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_PWM6           0x00001004
+#define GPIO_PA4_CAN0RX         0x00001005
+#define GPIO_PA4_I2S0TXSCK      0x00001009
+
+#define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_PWM7           0x00001404
+#define GPIO_PA5_CAN0TX         0x00001405
+#define GPIO_PA5_I2S0TXWS       0x00001409
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_PWM0           0x00001804
+#define GPIO_PA6_PWM4           0x00001805
+#define GPIO_PA6_CAN0RX         0x00001806
+#define GPIO_PA6_USB0EPEN       0x00001808
+#define GPIO_PA6_U1CTS          0x00001809
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_PWM1           0x00001C04
+#define GPIO_PA7_PWM5           0x00001C05
+#define GPIO_PA7_CAN0TX         0x00001C06
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_USB0PFLT       0x00001C08
+#define GPIO_PA7_U1DCD          0x00001C09
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_PWM2           0x00010002
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_PWM3           0x00010402
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_IDX0           0x00010802
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+#define GPIO_PB2_USB0EPEN       0x00010808
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_FAULT0         0x00010C02
+#define GPIO_PB3_FAULT3         0x00010C04
+#define GPIO_PB3_USB0PFLT       0x00010C08
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_CAN0RX         0x00011005
+#define GPIO_PB4_IDX0           0x00011006
+#define GPIO_PB4_U1RX           0x00011007
+#define GPIO_PB4_EPI0S23        0x00011008
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CAN0TX         0x00011405
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+#define GPIO_PB5_EPI0S22        0x00011408
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_FAULT1         0x00011804
+#define GPIO_PB6_IDX0           0x00011805
+#define GPIO_PB6_CCP5           0x00011806
+#define GPIO_PB6_I2S0TXSCK      0x00011809
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_PHA0           0x00021002
+#define GPIO_PC4_PWM6           0x00021004
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_EPI0S2         0x00021008
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_FAULT2         0x00021404
+#define GPIO_PC5_CCP3           0x00021405
+#define GPIO_PC5_USB0EPEN       0x00021406
+#define GPIO_PC5_EPI0S3         0x00021408
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_PHB0           0x00021802
+#define GPIO_PC6_C2O            0x00021803
+#define GPIO_PC6_PWM7           0x00021804
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+#define GPIO_PC6_USB0PFLT       0x00021807
+#define GPIO_PC6_EPI0S4         0x00021808
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_PHB0           0x00021C02
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_USB0PFLT       0x00021C06
+#define GPIO_PC7_C1O            0x00021C07
+#define GPIO_PC7_EPI0S5         0x00021C08
+
+#define GPIO_PD0_PWM0           0x00030001
+#define GPIO_PD0_CAN0RX         0x00030002
+#define GPIO_PD0_IDX0           0x00030003
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+#define GPIO_PD0_I2S0RXSCK      0x00030008
+#define GPIO_PD0_U1CTS          0x00030009
+
+#define GPIO_PD1_PWM1           0x00030401
+#define GPIO_PD1_CAN0TX         0x00030402
+#define GPIO_PD1_PHA0           0x00030403
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_I2S0RXWS       0x00030408
+#define GPIO_PD1_U1DCD          0x00030409
+#define GPIO_PD1_CCP2           0x0003040A
+#define GPIO_PD1_PHB1           0x0003040B
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_PWM2           0x00030803
+#define GPIO_PD2_CCP5           0x00030804
+#define GPIO_PD2_EPI0S20        0x00030808
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_PWM3           0x00030C03
+#define GPIO_PD3_CCP0           0x00030C04
+#define GPIO_PD3_EPI0S21        0x00030C08
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+#define GPIO_PD4_I2S0RXSD       0x00031008
+#define GPIO_PD4_U1RI           0x00031009
+#define GPIO_PD4_EPI0S19        0x0003100A
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_I2S0RXMCLK     0x00031408
+#define GPIO_PD5_U2RX           0x00031409
+#define GPIO_PD5_EPI0S28        0x0003140A
+
+#define GPIO_PD6_FAULT0         0x00031801
+#define GPIO_PD6_I2S0TXSCK      0x00031808
+#define GPIO_PD6_U2TX           0x00031809
+#define GPIO_PD6_EPI0S29        0x0003180A
+
+#define GPIO_PD7_IDX0           0x00031C01
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+#define GPIO_PD7_I2S0TXWS       0x00031C08
+#define GPIO_PD7_U1DTR          0x00031C09
+#define GPIO_PD7_EPI0S30        0x00031C0A
+
+#define GPIO_PE0_PWM4           0x00040001
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+#define GPIO_PE0_EPI0S8         0x00040008
+#define GPIO_PE0_USB0PFLT       0x00040009
+
+#define GPIO_PE1_PWM5           0x00040401
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_FAULT0         0x00040403
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+#define GPIO_PE1_EPI0S9         0x00040408
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_PHB1           0x00040803
+#define GPIO_PE2_PHA0           0x00040804
+#define GPIO_PE2_CCP2           0x00040805
+#define GPIO_PE2_EPI0S24        0x00040808
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_PHA1           0x00040C03
+#define GPIO_PE3_PHB0           0x00040C04
+#define GPIO_PE3_CCP7           0x00040C05
+#define GPIO_PE3_EPI0S25        0x00040C08
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_FAULT0         0x00041004
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+#define GPIO_PE4_I2S0TXWS       0x00041009
+
+#define GPIO_PE5_CCP5           0x00041401
+#define GPIO_PE5_I2S0TXSD       0x00041409
+
+#define GPIO_PE6_PWM4           0x00041801
+#define GPIO_PE6_C1O            0x00041802
+#define GPIO_PE6_U1CTS          0x00041809
+
+#define GPIO_PE7_PWM5           0x00041C01
+#define GPIO_PE7_C2O            0x00041C02
+#define GPIO_PE7_U1DCD          0x00041C09
+
+#define GPIO_PF0_CAN1RX         0x00050001
+#define GPIO_PF0_PHB0           0x00050002
+#define GPIO_PF0_PWM0           0x00050003
+#define GPIO_PF0_I2S0TXSD       0x00050008
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_CAN1TX         0x00050401
+#define GPIO_PF1_IDX1           0x00050402
+#define GPIO_PF1_PWM1           0x00050403
+#define GPIO_PF1_I2S0TXMCLK     0x00050408
+#define GPIO_PF1_U1RTS          0x00050409
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_PWM4           0x00050802
+#define GPIO_PF2_PWM2           0x00050804
+#define GPIO_PF2_SSI1CLK        0x00050809
+
+#define GPIO_PF3_PWM5           0x00050C02
+#define GPIO_PF3_PWM3           0x00050C04
+#define GPIO_PF3_SSI1FSS        0x00050C09
+
+#define GPIO_PF4_CCP0           0x00051001
+#define GPIO_PF4_C0O            0x00051002
+#define GPIO_PF4_FAULT0         0x00051004
+#define GPIO_PF4_EPI0S12        0x00051008
+#define GPIO_PF4_SSI1RX         0x00051009
+
+#define GPIO_PF5_CCP2           0x00051401
+#define GPIO_PF5_C1O            0x00051402
+#define GPIO_PF5_EPI0S15        0x00051408
+#define GPIO_PF5_SSI1TX         0x00051409
+
+#define GPIO_PF6_CCP1           0x00051801
+#define GPIO_PF6_C2O            0x00051802
+#define GPIO_PF6_PHA0           0x00051804
+#define GPIO_PF6_I2S0TXMCLK     0x00051809
+#define GPIO_PF6_U1RTS          0x0005180A
+
+#define GPIO_PF7_CCP4           0x00051C01
+#define GPIO_PF7_PHB0           0x00051C04
+#define GPIO_PF7_EPI0S12        0x00051C08
+#define GPIO_PF7_FAULT1         0x00051C09
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_PWM0           0x00060002
+#define GPIO_PG0_I2C1SCL        0x00060003
+#define GPIO_PG0_PWM4           0x00060004
+#define GPIO_PG0_USB0EPEN       0x00060007
+#define GPIO_PG0_EPI0S13        0x00060008
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_PWM1           0x00060402
+#define GPIO_PG1_I2C1SDA        0x00060403
+#define GPIO_PG1_PWM5           0x00060404
+#define GPIO_PG1_EPI0S14        0x00060408
+
+#define GPIO_PG2_PWM0           0x00060801
+#define GPIO_PG2_FAULT0         0x00060804
+#define GPIO_PG2_IDX1           0x00060808
+#define GPIO_PG2_I2S0RXSD       0x00060809
+
+#define GPIO_PG3_PWM1           0x00060C01
+#define GPIO_PG3_FAULT2         0x00060C04
+#define GPIO_PG3_FAULT0         0x00060C08
+#define GPIO_PG3_I2S0RXMCLK     0x00060C09
+
+#define GPIO_PG4_CCP3           0x00061001
+#define GPIO_PG4_FAULT1         0x00061004
+#define GPIO_PG4_EPI0S15        0x00061008
+#define GPIO_PG4_PWM6           0x00061009
+#define GPIO_PG4_U1RI           0x0006100A
+
+#define GPIO_PG5_CCP5           0x00061401
+#define GPIO_PG5_IDX0           0x00061404
+#define GPIO_PG5_FAULT1         0x00061405
+#define GPIO_PG5_PWM7           0x00061408
+#define GPIO_PG5_I2S0RXSCK      0x00061409
+#define GPIO_PG5_U1DTR          0x0006140A
+
+#define GPIO_PG6_PHA1           0x00061801
+#define GPIO_PG6_PWM6           0x00061804
+#define GPIO_PG6_FAULT1         0x00061808
+#define GPIO_PG6_I2S0RXWS       0x00061809
+#define GPIO_PG6_U1RI           0x0006180A
+
+#define GPIO_PG7_PHB1           0x00061C01
+#define GPIO_PG7_PWM7           0x00061C04
+#define GPIO_PG7_CCP5           0x00061C08
+#define GPIO_PG7_EPI0S31        0x00061C09
+
+#define GPIO_PH0_CCP6           0x00070001
+#define GPIO_PH0_PWM2           0x00070002
+#define GPIO_PH0_EPI0S6         0x00070008
+#define GPIO_PH0_PWM4           0x00070009
+
+#define GPIO_PH1_CCP7           0x00070401
+#define GPIO_PH1_PWM3           0x00070402
+#define GPIO_PH1_EPI0S7         0x00070408
+#define GPIO_PH1_PWM5           0x00070409
+
+#define GPIO_PH2_IDX1           0x00070801
+#define GPIO_PH2_C1O            0x00070802
+#define GPIO_PH2_FAULT3         0x00070804
+#define GPIO_PH2_EPI0S1         0x00070808
+
+#define GPIO_PH3_PHB0           0x00070C01
+#define GPIO_PH3_FAULT0         0x00070C02
+#define GPIO_PH3_USB0EPEN       0x00070C04
+#define GPIO_PH3_EPI0S0         0x00070C08
+
+#define GPIO_PH4_USB0PFLT       0x00071004
+#define GPIO_PH4_EPI0S10        0x00071008
+#define GPIO_PH4_SSI1CLK        0x0007100B
+
+#define GPIO_PH5_EPI0S11        0x00071408
+#define GPIO_PH5_FAULT2         0x0007140A
+#define GPIO_PH5_SSI1FSS        0x0007140B
+
+#define GPIO_PH6_EPI0S26        0x00071808
+#define GPIO_PH6_PWM4           0x0007180A
+#define GPIO_PH6_SSI1RX         0x0007180B
+
+#define GPIO_PH7_EPI0S27        0x00071C08
+#define GPIO_PH7_PWM5           0x00071C0A
+#define GPIO_PH7_SSI1TX         0x00071C0B
+
+#define GPIO_PJ0_EPI0S16        0x00080008
+#define GPIO_PJ0_PWM0           0x0008000A
+#define GPIO_PJ0_I2C1SCL        0x0008000B
+
+#define GPIO_PJ1_EPI0S17        0x00080408
+#define GPIO_PJ1_USB0PFLT       0x00080409
+#define GPIO_PJ1_PWM1           0x0008040A
+#define GPIO_PJ1_I2C1SDA        0x0008040B
+
+#define GPIO_PJ2_EPI0S18        0x00080808
+#define GPIO_PJ2_CCP0           0x00080809
+#define GPIO_PJ2_FAULT0         0x0008080A
+
+#define GPIO_PJ3_EPI0S19        0x00080C08
+#define GPIO_PJ3_U1CTS          0x00080C09
+#define GPIO_PJ3_CCP6           0x00080C0A
+
+#define GPIO_PJ4_EPI0S28        0x00081008
+#define GPIO_PJ4_U1DCD          0x00081009
+#define GPIO_PJ4_CCP4           0x0008100A
+
+#define GPIO_PJ5_EPI0S29        0x00081408
+#define GPIO_PJ5_U1DSR          0x00081409
+#define GPIO_PJ5_CCP2           0x0008140A
+
+#define GPIO_PJ6_EPI0S30        0x00081808
+#define GPIO_PJ6_U1RTS          0x00081809
+#define GPIO_PJ6_CCP1           0x0008180A
+
+#define GPIO_PJ7_U1DTR          0x00081C09
+#define GPIO_PJ7_CCP0           0x00081C0A
+
+#endif // PART_LM3S5791
+
+//*****************************************************************************
+//
+// LM3S5951 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S5951
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_PWM4           0x00000804
+#define GPIO_PA2_I2S0RXSD       0x00000809
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_PWM5           0x00000C04
+#define GPIO_PA3_I2S0RXMCLK     0x00000C09
+
+#define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_CAN0RX         0x00001005
+#define GPIO_PA4_I2S0TXSCK      0x00001009
+
+#define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_CAN0TX         0x00001405
+#define GPIO_PA5_I2S0TXWS       0x00001409
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_PWM0           0x00001804
+#define GPIO_PA6_PWM4           0x00001805
+#define GPIO_PA6_CAN0RX         0x00001806
+#define GPIO_PA6_USB0EPEN       0x00001808
+#define GPIO_PA6_U1CTS          0x00001809
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_PWM1           0x00001C04
+#define GPIO_PA7_PWM5           0x00001C05
+#define GPIO_PA7_CAN0TX         0x00001C06
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_USB0PFLT       0x00001C08
+#define GPIO_PA7_U1DCD          0x00001C09
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_PWM2           0x00010002
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_PWM3           0x00010402
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_IDX0           0x00010802
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+#define GPIO_PB2_USB0EPEN       0x00010808
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_FAULT0         0x00010C02
+#define GPIO_PB3_FAULT3         0x00010C04
+#define GPIO_PB3_USB0PFLT       0x00010C08
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_CAN0RX         0x00011005
+#define GPIO_PB4_IDX0           0x00011006
+#define GPIO_PB4_U1RX           0x00011007
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CAN0TX         0x00011405
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_FAULT1         0x00011804
+#define GPIO_PB6_IDX0           0x00011805
+#define GPIO_PB6_CCP5           0x00011806
+#define GPIO_PB6_I2S0TXSCK      0x00011809
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_PHA0           0x00021002
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_FAULT2         0x00021404
+#define GPIO_PC5_CCP3           0x00021405
+#define GPIO_PC5_USB0EPEN       0x00021406
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_PHB0           0x00021802
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+#define GPIO_PC6_USB0PFLT       0x00021807
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_PHB0           0x00021C02
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_USB0PFLT       0x00021C06
+#define GPIO_PC7_C1O            0x00021C07
+
+#define GPIO_PD0_PWM0           0x00030001
+#define GPIO_PD0_CAN0RX         0x00030002
+#define GPIO_PD0_IDX0           0x00030003
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+#define GPIO_PD0_I2S0RXSCK      0x00030008
+#define GPIO_PD0_U1CTS          0x00030009
+
+#define GPIO_PD1_PWM1           0x00030401
+#define GPIO_PD1_CAN0TX         0x00030402
+#define GPIO_PD1_PHA0           0x00030403
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_I2S0RXWS       0x00030408
+#define GPIO_PD1_U1DCD          0x00030409
+#define GPIO_PD1_CCP2           0x0003040A
+#define GPIO_PD1_PHB1           0x0003040B
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_PWM2           0x00030803
+#define GPIO_PD2_CCP5           0x00030804
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_PWM3           0x00030C03
+#define GPIO_PD3_CCP0           0x00030C04
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+#define GPIO_PD4_I2S0RXSD       0x00031008
+#define GPIO_PD4_U1RI           0x00031009
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_I2S0RXMCLK     0x00031408
+#define GPIO_PD5_U2RX           0x00031409
+
+#define GPIO_PD6_FAULT0         0x00031801
+#define GPIO_PD6_I2S0TXSCK      0x00031808
+#define GPIO_PD6_U2TX           0x00031809
+
+#define GPIO_PD7_IDX0           0x00031C01
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+#define GPIO_PD7_I2S0TXWS       0x00031C08
+#define GPIO_PD7_U1DTR          0x00031C09
+
+#define GPIO_PE0_PWM4           0x00040001
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+#define GPIO_PE0_USB0PFLT       0x00040009
+
+#define GPIO_PE1_PWM5           0x00040401
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_FAULT0         0x00040403
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_PHB1           0x00040803
+#define GPIO_PE2_PHA0           0x00040804
+#define GPIO_PE2_CCP2           0x00040805
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_PHA1           0x00040C03
+#define GPIO_PE3_PHB0           0x00040C04
+#define GPIO_PE3_CCP7           0x00040C05
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_FAULT0         0x00041004
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+#define GPIO_PE4_I2S0TXWS       0x00041009
+
+#define GPIO_PE5_CCP5           0x00041401
+#define GPIO_PE5_I2S0TXSD       0x00041409
+
+#define GPIO_PE6_PWM4           0x00041801
+#define GPIO_PE6_C1O            0x00041802
+#define GPIO_PE6_U1CTS          0x00041809
+
+#define GPIO_PE7_PWM5           0x00041C01
+#define GPIO_PE7_U1DCD          0x00041C09
+
+#define GPIO_PF0_CAN1RX         0x00050001
+#define GPIO_PF0_PHB0           0x00050002
+#define GPIO_PF0_PWM0           0x00050003
+#define GPIO_PF0_I2S0TXSD       0x00050008
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_CAN1TX         0x00050401
+#define GPIO_PF1_IDX1           0x00050402
+#define GPIO_PF1_PWM1           0x00050403
+#define GPIO_PF1_I2S0TXMCLK     0x00050408
+#define GPIO_PF1_U1RTS          0x00050409
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_PWM4           0x00050802
+#define GPIO_PF2_PWM2           0x00050804
+#define GPIO_PF2_SSI1CLK        0x00050809
+
+#define GPIO_PF3_PWM5           0x00050C02
+#define GPIO_PF3_PWM3           0x00050C04
+#define GPIO_PF3_SSI1FSS        0x00050C09
+
+#define GPIO_PF4_CCP0           0x00051001
+#define GPIO_PF4_C0O            0x00051002
+#define GPIO_PF4_FAULT0         0x00051004
+#define GPIO_PF4_SSI1RX         0x00051009
+
+#define GPIO_PF5_CCP2           0x00051401
+#define GPIO_PF5_C1O            0x00051402
+#define GPIO_PF5_SSI1TX         0x00051409
+
+#define GPIO_PF6_CCP1           0x00051801
+#define GPIO_PF6_PHA0           0x00051804
+#define GPIO_PF6_I2S0TXMCLK     0x00051809
+#define GPIO_PF6_U1RTS          0x0005180A
+
+#define GPIO_PF7_CCP4           0x00051C01
+#define GPIO_PF7_PHB0           0x00051C04
+#define GPIO_PF7_FAULT1         0x00051C09
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_PWM0           0x00060002
+#define GPIO_PG0_I2C1SCL        0x00060003
+#define GPIO_PG0_PWM4           0x00060004
+#define GPIO_PG0_USB0EPEN       0x00060007
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_PWM1           0x00060402
+#define GPIO_PG1_I2C1SDA        0x00060403
+#define GPIO_PG1_PWM5           0x00060404
+
+#define GPIO_PG2_PWM0           0x00060801
+#define GPIO_PG2_FAULT0         0x00060804
+#define GPIO_PG2_IDX1           0x00060808
+#define GPIO_PG2_I2S0RXSD       0x00060809
+
+#define GPIO_PG3_PWM1           0x00060C01
+#define GPIO_PG3_FAULT2         0x00060C04
+#define GPIO_PG3_FAULT0         0x00060C08
+#define GPIO_PG3_I2S0RXMCLK     0x00060C09
+
+#define GPIO_PG4_CCP3           0x00061001
+#define GPIO_PG4_FAULT1         0x00061004
+#define GPIO_PG4_U1RI           0x0006100A
+
+#define GPIO_PG5_CCP5           0x00061401
+#define GPIO_PG5_IDX0           0x00061404
+#define GPIO_PG5_FAULT1         0x00061405
+#define GPIO_PG5_I2S0RXSCK      0x00061409
+#define GPIO_PG5_U1DTR          0x0006140A
+
+#define GPIO_PG6_PHA1           0x00061801
+#define GPIO_PG6_FAULT1         0x00061808
+#define GPIO_PG6_I2S0RXWS       0x00061809
+#define GPIO_PG6_U1RI           0x0006180A
+
+#define GPIO_PG7_PHB1           0x00061C01
+#define GPIO_PG7_CCP5           0x00061C08
+
+#define GPIO_PH0_CCP6           0x00070001
+#define GPIO_PH0_PWM2           0x00070002
+#define GPIO_PH0_PWM4           0x00070009
+
+#define GPIO_PH1_CCP7           0x00070401
+#define GPIO_PH1_PWM3           0x00070402
+#define GPIO_PH1_PWM5           0x00070409
+
+#define GPIO_PH2_IDX1           0x00070801
+#define GPIO_PH2_C1O            0x00070802
+#define GPIO_PH2_FAULT3         0x00070804
+
+#define GPIO_PH3_PHB0           0x00070C01
+#define GPIO_PH3_FAULT0         0x00070C02
+#define GPIO_PH3_USB0EPEN       0x00070C04
+
+#define GPIO_PH4_USB0PFLT       0x00071004
+#define GPIO_PH4_SSI1CLK        0x0007100B
+
+#define GPIO_PH5_FAULT2         0x0007140A
+#define GPIO_PH5_SSI1FSS        0x0007140B
+
+#define GPIO_PH6_PWM4           0x0007180A
+#define GPIO_PH6_SSI1RX         0x0007180B
+
+#define GPIO_PH7_PWM5           0x00071C0A
+#define GPIO_PH7_SSI1TX         0x00071C0B
+
+#define GPIO_PJ0_PWM0           0x0008000A
+#define GPIO_PJ0_I2C1SCL        0x0008000B
+
+#define GPIO_PJ1_USB0PFLT       0x00080409
+#define GPIO_PJ1_PWM1           0x0008040A
+#define GPIO_PJ1_I2C1SDA        0x0008040B
+
+#define GPIO_PJ2_CCP0           0x00080809
+#define GPIO_PJ2_FAULT0         0x0008080A
+
+#endif // PART_LM3S5951
+
+//*****************************************************************************
+//
+// LM3S5956 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S5956
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_PWM4           0x00000804
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_PWM5           0x00000C04
+
+#define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_CAN0RX         0x00001005
+
+#define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_CAN0TX         0x00001405
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_PWM0           0x00001804
+#define GPIO_PA6_PWM4           0x00001805
+#define GPIO_PA6_CAN0RX         0x00001806
+#define GPIO_PA6_USB0EPEN       0x00001808
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_PWM1           0x00001C04
+#define GPIO_PA7_PWM5           0x00001C05
+#define GPIO_PA7_CAN0TX         0x00001C06
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_USB0PFLT       0x00001C08
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_PWM2           0x00010002
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_PWM3           0x00010402
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_IDX0           0x00010802
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+#define GPIO_PB2_USB0EPEN       0x00010808
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_FAULT0         0x00010C02
+#define GPIO_PB3_FAULT3         0x00010C04
+#define GPIO_PB3_USB0PFLT       0x00010C08
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_CAN0RX         0x00011005
+#define GPIO_PB4_IDX0           0x00011006
+#define GPIO_PB4_U1RX           0x00011007
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CAN0TX         0x00011405
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_FAULT1         0x00011804
+#define GPIO_PB6_IDX0           0x00011805
+#define GPIO_PB6_CCP5           0x00011806
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_PHA0           0x00021002
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_FAULT2         0x00021404
+#define GPIO_PC5_CCP3           0x00021405
+#define GPIO_PC5_USB0EPEN       0x00021406
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_PHB0           0x00021802
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+#define GPIO_PC6_USB0PFLT       0x00021807
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_PHB0           0x00021C02
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_USB0PFLT       0x00021C06
+#define GPIO_PC7_C1O            0x00021C07
+
+#define GPIO_PD0_PWM0           0x00030001
+#define GPIO_PD0_CAN0RX         0x00030002
+#define GPIO_PD0_IDX0           0x00030003
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+
+#define GPIO_PD1_PWM1           0x00030401
+#define GPIO_PD1_CAN0TX         0x00030402
+#define GPIO_PD1_PHA0           0x00030403
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_CCP2           0x0003040A
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_PWM2           0x00030803
+#define GPIO_PD2_CCP5           0x00030804
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_PWM3           0x00030C03
+#define GPIO_PD3_CCP0           0x00030C04
+
+#define GPIO_PE0_PWM4           0x00040001
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+#define GPIO_PE0_USB0PFLT       0x00040009
+
+#define GPIO_PE1_PWM5           0x00040401
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_FAULT0         0x00040403
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_PHA0           0x00040804
+#define GPIO_PE2_CCP2           0x00040805
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_PHB0           0x00040C04
+#define GPIO_PE3_CCP7           0x00040C05
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_FAULT0         0x00041004
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+
+#endif // PART_LM3S5956
+
+//*****************************************************************************
+//
+// LM3S5B91 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S5B91
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_PWM4           0x00000804
+#define GPIO_PA2_I2S0RXSD       0x00000809
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_PWM5           0x00000C04
+#define GPIO_PA3_I2S0RXMCLK     0x00000C09
+
+#define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_PWM6           0x00001004
+#define GPIO_PA4_CAN0RX         0x00001005
+#define GPIO_PA4_I2S0TXSCK      0x00001009
+
+#define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_PWM7           0x00001404
+#define GPIO_PA5_CAN0TX         0x00001405
+#define GPIO_PA5_I2S0TXWS       0x00001409
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_PWM0           0x00001804
+#define GPIO_PA6_PWM4           0x00001805
+#define GPIO_PA6_CAN0RX         0x00001806
+#define GPIO_PA6_USB0EPEN       0x00001808
+#define GPIO_PA6_U1CTS          0x00001809
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_PWM1           0x00001C04
+#define GPIO_PA7_PWM5           0x00001C05
+#define GPIO_PA7_CAN0TX         0x00001C06
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_USB0PFLT       0x00001C08
+#define GPIO_PA7_U1DCD          0x00001C09
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_PWM2           0x00010002
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_PWM3           0x00010402
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_IDX0           0x00010802
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+#define GPIO_PB2_USB0EPEN       0x00010808
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_FAULT0         0x00010C02
+#define GPIO_PB3_FAULT3         0x00010C04
+#define GPIO_PB3_USB0PFLT       0x00010C08
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_CAN0RX         0x00011005
+#define GPIO_PB4_IDX0           0x00011006
+#define GPIO_PB4_U1RX           0x00011007
+#define GPIO_PB4_EPI0S23        0x00011008
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CAN0TX         0x00011405
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+#define GPIO_PB5_EPI0S22        0x00011408
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_FAULT1         0x00011804
+#define GPIO_PB6_IDX0           0x00011805
+#define GPIO_PB6_CCP5           0x00011806
+#define GPIO_PB6_I2S0TXSCK      0x00011809
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_PHA0           0x00021002
+#define GPIO_PC4_PWM6           0x00021004
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_EPI0S2         0x00021008
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_FAULT2         0x00021404
+#define GPIO_PC5_CCP3           0x00021405
+#define GPIO_PC5_USB0EPEN       0x00021406
+#define GPIO_PC5_EPI0S3         0x00021408
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_PHB0           0x00021802
+#define GPIO_PC6_C2O            0x00021803
+#define GPIO_PC6_PWM7           0x00021804
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+#define GPIO_PC6_USB0PFLT       0x00021807
+#define GPIO_PC6_EPI0S4         0x00021808
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_PHB0           0x00021C02
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_USB0PFLT       0x00021C06
+#define GPIO_PC7_C1O            0x00021C07
+#define GPIO_PC7_EPI0S5         0x00021C08
+
+#define GPIO_PD0_PWM0           0x00030001
+#define GPIO_PD0_CAN0RX         0x00030002
+#define GPIO_PD0_IDX0           0x00030003
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+#define GPIO_PD0_I2S0RXSCK      0x00030008
+#define GPIO_PD0_U1CTS          0x00030009
+
+#define GPIO_PD1_PWM1           0x00030401
+#define GPIO_PD1_CAN0TX         0x00030402
+#define GPIO_PD1_PHA0           0x00030403
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_I2S0RXWS       0x00030408
+#define GPIO_PD1_U1DCD          0x00030409
+#define GPIO_PD1_CCP2           0x0003040A
+#define GPIO_PD1_PHB1           0x0003040B
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_PWM2           0x00030803
+#define GPIO_PD2_CCP5           0x00030804
+#define GPIO_PD2_EPI0S20        0x00030808
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_PWM3           0x00030C03
+#define GPIO_PD3_CCP0           0x00030C04
+#define GPIO_PD3_EPI0S21        0x00030C08
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+#define GPIO_PD4_I2S0RXSD       0x00031008
+#define GPIO_PD4_U1RI           0x00031009
+#define GPIO_PD4_EPI0S19        0x0003100A
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_I2S0RXMCLK     0x00031408
+#define GPIO_PD5_U2RX           0x00031409
+#define GPIO_PD5_EPI0S28        0x0003140A
+
+#define GPIO_PD6_FAULT0         0x00031801
+#define GPIO_PD6_I2S0TXSCK      0x00031808
+#define GPIO_PD6_U2TX           0x00031809
+#define GPIO_PD6_EPI0S29        0x0003180A
+
+#define GPIO_PD7_IDX0           0x00031C01
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+#define GPIO_PD7_I2S0TXWS       0x00031C08
+#define GPIO_PD7_U1DTR          0x00031C09
+#define GPIO_PD7_EPI0S30        0x00031C0A
+
+#define GPIO_PE0_PWM4           0x00040001
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+#define GPIO_PE0_EPI0S8         0x00040008
+#define GPIO_PE0_USB0PFLT       0x00040009
+
+#define GPIO_PE1_PWM5           0x00040401
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_FAULT0         0x00040403
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+#define GPIO_PE1_EPI0S9         0x00040408
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_PHB1           0x00040803
+#define GPIO_PE2_PHA0           0x00040804
+#define GPIO_PE2_CCP2           0x00040805
+#define GPIO_PE2_EPI0S24        0x00040808
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_PHA1           0x00040C03
+#define GPIO_PE3_PHB0           0x00040C04
+#define GPIO_PE3_CCP7           0x00040C05
+#define GPIO_PE3_EPI0S25        0x00040C08
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_FAULT0         0x00041004
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+#define GPIO_PE4_I2S0TXWS       0x00041009
+
+#define GPIO_PE5_CCP5           0x00041401
+#define GPIO_PE5_I2S0TXSD       0x00041409
+
+#define GPIO_PE6_PWM4           0x00041801
+#define GPIO_PE6_C1O            0x00041802
+#define GPIO_PE6_U1CTS          0x00041809
+
+#define GPIO_PE7_PWM5           0x00041C01
+#define GPIO_PE7_C2O            0x00041C02
+#define GPIO_PE7_U1DCD          0x00041C09
+
+#define GPIO_PF0_CAN1RX         0x00050001
+#define GPIO_PF0_PHB0           0x00050002
+#define GPIO_PF0_PWM0           0x00050003
+#define GPIO_PF0_I2S0TXSD       0x00050008
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_CAN1TX         0x00050401
+#define GPIO_PF1_IDX1           0x00050402
+#define GPIO_PF1_PWM1           0x00050403
+#define GPIO_PF1_I2S0TXMCLK     0x00050408
+#define GPIO_PF1_U1RTS          0x00050409
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_PWM4           0x00050802
+#define GPIO_PF2_PWM2           0x00050804
+#define GPIO_PF2_SSI1CLK        0x00050809
+
+#define GPIO_PF3_PWM5           0x00050C02
+#define GPIO_PF3_PWM3           0x00050C04
+#define GPIO_PF3_SSI1FSS        0x00050C09
+
+#define GPIO_PF4_CCP0           0x00051001
+#define GPIO_PF4_C0O            0x00051002
+#define GPIO_PF4_FAULT0         0x00051004
+#define GPIO_PF4_EPI0S12        0x00051008
+#define GPIO_PF4_SSI1RX         0x00051009
+
+#define GPIO_PF5_CCP2           0x00051401
+#define GPIO_PF5_C1O            0x00051402
+#define GPIO_PF5_EPI0S15        0x00051408
+#define GPIO_PF5_SSI1TX         0x00051409
+
+#define GPIO_PF6_CCP1           0x00051801
+#define GPIO_PF6_C2O            0x00051802
+#define GPIO_PF6_PHA0           0x00051804
+#define GPIO_PF6_I2S0TXMCLK     0x00051809
+#define GPIO_PF6_U1RTS          0x0005180A
+
+#define GPIO_PF7_CCP4           0x00051C01
+#define GPIO_PF7_PHB0           0x00051C04
+#define GPIO_PF7_EPI0S12        0x00051C08
+#define GPIO_PF7_FAULT1         0x00051C09
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_PWM0           0x00060002
+#define GPIO_PG0_I2C1SCL        0x00060003
+#define GPIO_PG0_PWM4           0x00060004
+#define GPIO_PG0_USB0EPEN       0x00060007
+#define GPIO_PG0_EPI0S13        0x00060008
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_PWM1           0x00060402
+#define GPIO_PG1_I2C1SDA        0x00060403
+#define GPIO_PG1_PWM5           0x00060404
+#define GPIO_PG1_EPI0S14        0x00060408
+
+#define GPIO_PG2_PWM0           0x00060801
+#define GPIO_PG2_FAULT0         0x00060804
+#define GPIO_PG2_IDX1           0x00060808
+#define GPIO_PG2_I2S0RXSD       0x00060809
+
+#define GPIO_PG3_PWM1           0x00060C01
+#define GPIO_PG3_FAULT2         0x00060C04
+#define GPIO_PG3_FAULT0         0x00060C08
+#define GPIO_PG3_I2S0RXMCLK     0x00060C09
+
+#define GPIO_PG4_CCP3           0x00061001
+#define GPIO_PG4_FAULT1         0x00061004
+#define GPIO_PG4_EPI0S15        0x00061008
+#define GPIO_PG4_PWM6           0x00061009
+#define GPIO_PG4_U1RI           0x0006100A
+
+#define GPIO_PG5_CCP5           0x00061401
+#define GPIO_PG5_IDX0           0x00061404
+#define GPIO_PG5_FAULT1         0x00061405
+#define GPIO_PG5_PWM7           0x00061408
+#define GPIO_PG5_I2S0RXSCK      0x00061409
+#define GPIO_PG5_U1DTR          0x0006140A
+
+#define GPIO_PG6_PHA1           0x00061801
+#define GPIO_PG6_PWM6           0x00061804
+#define GPIO_PG6_FAULT1         0x00061808
+#define GPIO_PG6_I2S0RXWS       0x00061809
+#define GPIO_PG6_U1RI           0x0006180A
+
+#define GPIO_PG7_PHB1           0x00061C01
+#define GPIO_PG7_PWM7           0x00061C04
+#define GPIO_PG7_CCP5           0x00061C08
+#define GPIO_PG7_EPI0S31        0x00061C09
+
+#define GPIO_PH0_CCP6           0x00070001
+#define GPIO_PH0_PWM2           0x00070002
+#define GPIO_PH0_EPI0S6         0x00070008
+#define GPIO_PH0_PWM4           0x00070009
+
+#define GPIO_PH1_CCP7           0x00070401
+#define GPIO_PH1_PWM3           0x00070402
+#define GPIO_PH1_EPI0S7         0x00070408
+#define GPIO_PH1_PWM5           0x00070409
+
+#define GPIO_PH2_IDX1           0x00070801
+#define GPIO_PH2_C1O            0x00070802
+#define GPIO_PH2_FAULT3         0x00070804
+#define GPIO_PH2_EPI0S1         0x00070808
+
+#define GPIO_PH3_PHB0           0x00070C01
+#define GPIO_PH3_FAULT0         0x00070C02
+#define GPIO_PH3_USB0EPEN       0x00070C04
+#define GPIO_PH3_EPI0S0         0x00070C08
+
+#define GPIO_PH4_USB0PFLT       0x00071004
+#define GPIO_PH4_EPI0S10        0x00071008
+#define GPIO_PH4_SSI1CLK        0x0007100B
+
+#define GPIO_PH5_EPI0S11        0x00071408
+#define GPIO_PH5_FAULT2         0x0007140A
+#define GPIO_PH5_SSI1FSS        0x0007140B
+
+#define GPIO_PH6_EPI0S26        0x00071808
+#define GPIO_PH6_PWM4           0x0007180A
+#define GPIO_PH6_SSI1RX         0x0007180B
+
+#define GPIO_PH7_EPI0S27        0x00071C08
+#define GPIO_PH7_PWM5           0x00071C0A
+#define GPIO_PH7_SSI1TX         0x00071C0B
+
+#define GPIO_PJ0_EPI0S16        0x00080008
+#define GPIO_PJ0_PWM0           0x0008000A
+#define GPIO_PJ0_I2C1SCL        0x0008000B
+
+#define GPIO_PJ1_EPI0S17        0x00080408
+#define GPIO_PJ1_USB0PFLT       0x00080409
+#define GPIO_PJ1_PWM1           0x0008040A
+#define GPIO_PJ1_I2C1SDA        0x0008040B
+
+#define GPIO_PJ2_EPI0S18        0x00080808
+#define GPIO_PJ2_CCP0           0x00080809
+#define GPIO_PJ2_FAULT0         0x0008080A
+
+#define GPIO_PJ3_EPI0S19        0x00080C08
+#define GPIO_PJ3_U1CTS          0x00080C09
+#define GPIO_PJ3_CCP6           0x00080C0A
+
+#define GPIO_PJ4_EPI0S28        0x00081008
+#define GPIO_PJ4_U1DCD          0x00081009
+#define GPIO_PJ4_CCP4           0x0008100A
+
+#define GPIO_PJ5_EPI0S29        0x00081408
+#define GPIO_PJ5_U1DSR          0x00081409
+#define GPIO_PJ5_CCP2           0x0008140A
+
+#define GPIO_PJ6_EPI0S30        0x00081808
+#define GPIO_PJ6_U1RTS          0x00081809
+#define GPIO_PJ6_CCP1           0x0008180A
+
+#define GPIO_PJ7_U1DTR          0x00081C09
+#define GPIO_PJ7_CCP0           0x00081C0A
+
+#endif // PART_LM3S5B91
+
+//*****************************************************************************
+//
+// LM3S5C31 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S5C31
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_PWM4           0x00000804
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_PWM5           0x00000C04
+
+#define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_CAN0RX         0x00001005
+
+#define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_CAN0TX         0x00001405
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_PWM0           0x00001804
+#define GPIO_PA6_PWM4           0x00001805
+#define GPIO_PA6_CAN0RX         0x00001806
+#define GPIO_PA6_U1CTS          0x00001809
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_PWM1           0x00001C04
+#define GPIO_PA7_PWM5           0x00001C05
+#define GPIO_PA7_CAN0TX         0x00001C06
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_U1DCD          0x00001C09
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_PWM2           0x00010002
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_PWM3           0x00010402
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_IDX0           0x00010802
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_FAULT0         0x00010C02
+#define GPIO_PB3_FAULT3         0x00010C04
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_CAN0RX         0x00011005
+#define GPIO_PB4_IDX0           0x00011006
+#define GPIO_PB4_U1RX           0x00011007
+#define GPIO_PB4_EPI0S23        0x00011008
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CAN0TX         0x00011405
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+#define GPIO_PB5_EPI0S22        0x00011408
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_FAULT1         0x00011804
+#define GPIO_PB6_IDX0           0x00011805
+#define GPIO_PB6_CCP5           0x00011806
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_PHA0           0x00021002
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_EPI0S2         0x00021008
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_FAULT2         0x00021404
+#define GPIO_PC5_CCP3           0x00021405
+#define GPIO_PC5_EPI0S3         0x00021408
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_PHB0           0x00021802
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+#define GPIO_PC6_EPI0S4         0x00021808
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_PHB0           0x00021C02
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_C1O            0x00021C07
+#define GPIO_PC7_EPI0S5         0x00021C08
+
+#define GPIO_PD0_PWM0           0x00030001
+#define GPIO_PD0_CAN0RX         0x00030002
+#define GPIO_PD0_IDX0           0x00030003
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_U1CTS          0x00030009
+
+#define GPIO_PD1_PWM1           0x00030401
+#define GPIO_PD1_CAN0TX         0x00030402
+#define GPIO_PD1_PHA0           0x00030403
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_U1DCD          0x00030409
+#define GPIO_PD1_CCP2           0x0003040A
+#define GPIO_PD1_PHB1           0x0003040B
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_PWM2           0x00030803
+#define GPIO_PD2_CCP5           0x00030804
+#define GPIO_PD2_EPI0S20        0x00030808
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_PWM3           0x00030C03
+#define GPIO_PD3_CCP0           0x00030C04
+#define GPIO_PD3_EPI0S21        0x00030C08
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+#define GPIO_PD4_U1RI           0x00031009
+#define GPIO_PD4_EPI0S19        0x0003100A
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_U2RX           0x00031409
+#define GPIO_PD5_EPI0S28        0x0003140A
+
+#define GPIO_PD6_FAULT0         0x00031801
+#define GPIO_PD6_U2TX           0x00031809
+#define GPIO_PD6_EPI0S29        0x0003180A
+
+#define GPIO_PD7_IDX0           0x00031C01
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+#define GPIO_PD7_U1DTR          0x00031C09
+#define GPIO_PD7_EPI0S30        0x00031C0A
+
+#define GPIO_PE0_PWM4           0x00040001
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+#define GPIO_PE0_EPI0S8         0x00040008
+
+#define GPIO_PE1_PWM5           0x00040401
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_FAULT0         0x00040403
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_EPI0S9         0x00040408
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_PHB1           0x00040803
+#define GPIO_PE2_PHA0           0x00040804
+#define GPIO_PE2_CCP2           0x00040805
+#define GPIO_PE2_EPI0S24        0x00040808
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_PHA1           0x00040C03
+#define GPIO_PE3_PHB0           0x00040C04
+#define GPIO_PE3_EPI0S25        0x00040C08
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_FAULT0         0x00041004
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+
+#define GPIO_PE5_CCP5           0x00041401
+
+#define GPIO_PE6_PWM4           0x00041801
+#define GPIO_PE6_C1O            0x00041802
+#define GPIO_PE6_U1CTS          0x00041809
+
+#define GPIO_PE7_PWM5           0x00041C01
+#define GPIO_PE7_U1DCD          0x00041C09
+
+#define GPIO_PF0_PHB0           0x00050002
+#define GPIO_PF0_PWM0           0x00050003
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_IDX1           0x00050402
+#define GPIO_PF1_PWM1           0x00050403
+#define GPIO_PF1_U1RTS          0x00050409
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_PWM4           0x00050802
+#define GPIO_PF2_PWM2           0x00050804
+#define GPIO_PF2_SSI1CLK        0x00050809
+
+#define GPIO_PF3_PWM5           0x00050C02
+#define GPIO_PF3_PWM3           0x00050C04
+#define GPIO_PF3_SSI1FSS        0x00050C09
+
+#define GPIO_PF4_CCP0           0x00051001
+#define GPIO_PF4_C0O            0x00051002
+#define GPIO_PF4_FAULT0         0x00051004
+#define GPIO_PF4_EPI0S12        0x00051008
+#define GPIO_PF4_SSI1RX         0x00051009
+
+#define GPIO_PF5_CCP2           0x00051401
+#define GPIO_PF5_C1O            0x00051402
+#define GPIO_PF5_EPI0S15        0x00051408
+#define GPIO_PF5_SSI1TX         0x00051409
+
+#define GPIO_PF6_CCP1           0x00051801
+#define GPIO_PF6_PHA0           0x00051804
+#define GPIO_PF6_U1RTS          0x0005180A
+
+#define GPIO_PF7_CCP4           0x00051C01
+#define GPIO_PF7_PHB0           0x00051C04
+#define GPIO_PF7_EPI0S12        0x00051C08
+#define GPIO_PF7_FAULT1         0x00051C09
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_PWM0           0x00060002
+#define GPIO_PG0_I2C1SCL        0x00060003
+#define GPIO_PG0_PWM4           0x00060004
+#define GPIO_PG0_EPI0S13        0x00060008
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_PWM1           0x00060402
+#define GPIO_PG1_I2C1SDA        0x00060403
+#define GPIO_PG1_PWM5           0x00060404
+#define GPIO_PG1_EPI0S14        0x00060408
+
+#define GPIO_PG2_PWM0           0x00060801
+#define GPIO_PG2_FAULT0         0x00060804
+#define GPIO_PG2_IDX1           0x00060808
+
+#define GPIO_PG3_PWM1           0x00060C01
+#define GPIO_PG3_FAULT2         0x00060C04
+#define GPIO_PG3_FAULT0         0x00060C08
+
+#define GPIO_PG4_CCP3           0x00061001
+#define GPIO_PG4_FAULT1         0x00061004
+#define GPIO_PG4_EPI0S15        0x00061008
+#define GPIO_PG4_U1RI           0x0006100A
+
+#define GPIO_PG5_CCP5           0x00061401
+#define GPIO_PG5_IDX0           0x00061404
+#define GPIO_PG5_FAULT1         0x00061405
+#define GPIO_PG5_U1DTR          0x0006140A
+
+#define GPIO_PG6_PHA1           0x00061801
+#define GPIO_PG6_FAULT1         0x00061808
+#define GPIO_PG6_U1RI           0x0006180A
+
+#define GPIO_PG7_PHB1           0x00061C01
+#define GPIO_PG7_CCP5           0x00061C08
+#define GPIO_PG7_EPI0S31        0x00061C09
+
+#define GPIO_PH0_PWM2           0x00070002
+#define GPIO_PH0_EPI0S6         0x00070008
+#define GPIO_PH0_PWM4           0x00070009
+
+#define GPIO_PH1_PWM3           0x00070402
+#define GPIO_PH1_EPI0S7         0x00070408
+#define GPIO_PH1_PWM5           0x00070409
+
+#define GPIO_PH2_IDX1           0x00070801
+#define GPIO_PH2_C1O            0x00070802
+#define GPIO_PH2_FAULT3         0x00070804
+#define GPIO_PH2_EPI0S1         0x00070808
+
+#define GPIO_PH3_PHB0           0x00070C01
+#define GPIO_PH3_FAULT0         0x00070C02
+#define GPIO_PH3_EPI0S0         0x00070C08
+
+#define GPIO_PH4_EPI0S10        0x00071008
+#define GPIO_PH4_SSI1CLK        0x0007100B
+
+#define GPIO_PH5_EPI0S11        0x00071408
+#define GPIO_PH5_FAULT2         0x0007140A
+#define GPIO_PH5_SSI1FSS        0x0007140B
+
+#define GPIO_PH6_EPI0S26        0x00071808
+#define GPIO_PH6_PWM4           0x0007180A
+#define GPIO_PH6_SSI1RX         0x0007180B
+
+#define GPIO_PH7_EPI0S27        0x00071C08
+#define GPIO_PH7_PWM5           0x00071C0A
+#define GPIO_PH7_SSI1TX         0x00071C0B
+
+#define GPIO_PJ0_EPI0S16        0x00080008
+#define GPIO_PJ0_PWM0           0x0008000A
+#define GPIO_PJ0_I2C1SCL        0x0008000B
+
+#define GPIO_PJ1_EPI0S17        0x00080408
+#define GPIO_PJ1_PWM1           0x0008040A
+#define GPIO_PJ1_I2C1SDA        0x0008040B
+
+#define GPIO_PJ2_EPI0S18        0x00080808
+#define GPIO_PJ2_CCP0           0x00080809
+#define GPIO_PJ2_FAULT0         0x0008080A
+
+#endif // PART_LM3S5C31
+
+//*****************************************************************************
+//
+// LM3S5C36 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S5C36
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_PWM4           0x00000804
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_PWM5           0x00000C04
+
+#define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_PWM6           0x00001004
+#define GPIO_PA4_CAN0RX         0x00001005
+
+#define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_PWM7           0x00001404
+#define GPIO_PA5_CAN0TX         0x00001405
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_PWM0           0x00001804
+#define GPIO_PA6_PWM4           0x00001805
+#define GPIO_PA6_CAN0RX         0x00001806
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_PWM1           0x00001C04
+#define GPIO_PA7_PWM5           0x00001C05
+#define GPIO_PA7_CAN0TX         0x00001C06
+#define GPIO_PA7_CCP3           0x00001C07
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_PWM2           0x00010002
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_PWM3           0x00010402
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_IDX0           0x00010802
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_FAULT0         0x00010C02
+#define GPIO_PB3_FAULT3         0x00010C04
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_CAN0RX         0x00011005
+#define GPIO_PB4_IDX0           0x00011006
+#define GPIO_PB4_U1RX           0x00011007
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CAN0TX         0x00011405
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_FAULT1         0x00011804
+#define GPIO_PB6_IDX0           0x00011805
+#define GPIO_PB6_CCP5           0x00011806
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_PHA0           0x00021002
+#define GPIO_PC4_PWM6           0x00021004
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_FAULT2         0x00021404
+#define GPIO_PC5_CCP3           0x00021405
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_PHB0           0x00021802
+#define GPIO_PC6_PWM7           0x00021804
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_PHB0           0x00021C02
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_C1O            0x00021C07
+
+#define GPIO_PD0_PWM0           0x00030001
+#define GPIO_PD0_CAN0RX         0x00030002
+#define GPIO_PD0_IDX0           0x00030003
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+
+#define GPIO_PD1_PWM1           0x00030401
+#define GPIO_PD1_CAN0TX         0x00030402
+#define GPIO_PD1_PHA0           0x00030403
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_CCP2           0x0003040A
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_PWM2           0x00030803
+#define GPIO_PD2_CCP5           0x00030804
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_PWM3           0x00030C03
+#define GPIO_PD3_CCP0           0x00030C04
+
+#define GPIO_PE0_PWM4           0x00040001
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+
+#define GPIO_PE1_PWM5           0x00040401
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_FAULT0         0x00040403
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_PHA0           0x00040804
+#define GPIO_PE2_CCP2           0x00040805
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_PHB0           0x00040C04
+#define GPIO_PE3_CCP7           0x00040C05
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_FAULT0         0x00041004
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+
+#endif // PART_LM3S5C36
+
+//*****************************************************************************
+//
+// LM3S5C51 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S5C51
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_PWM4           0x00000804
+#define GPIO_PA2_I2S0RXSD       0x00000809
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_PWM5           0x00000C04
+#define GPIO_PA3_I2S0RXMCLK     0x00000C09
+
+#define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_CAN0RX         0x00001005
+#define GPIO_PA4_I2S0TXSCK      0x00001009
+
+#define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_CAN0TX         0x00001405
+#define GPIO_PA5_I2S0TXWS       0x00001409
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_PWM0           0x00001804
+#define GPIO_PA6_PWM4           0x00001805
+#define GPIO_PA6_CAN0RX         0x00001806
+#define GPIO_PA6_USB0EPEN       0x00001808
+#define GPIO_PA6_U1CTS          0x00001809
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_PWM1           0x00001C04
+#define GPIO_PA7_PWM5           0x00001C05
+#define GPIO_PA7_CAN0TX         0x00001C06
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_USB0PFLT       0x00001C08
+#define GPIO_PA7_U1DCD          0x00001C09
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_PWM2           0x00010002
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_PWM3           0x00010402
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_IDX0           0x00010802
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+#define GPIO_PB2_USB0EPEN       0x00010808
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_FAULT0         0x00010C02
+#define GPIO_PB3_FAULT3         0x00010C04
+#define GPIO_PB3_USB0PFLT       0x00010C08
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_CAN0RX         0x00011005
+#define GPIO_PB4_IDX0           0x00011006
+#define GPIO_PB4_U1RX           0x00011007
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CAN0TX         0x00011405
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_FAULT1         0x00011804
+#define GPIO_PB6_IDX0           0x00011805
+#define GPIO_PB6_CCP5           0x00011806
+#define GPIO_PB6_I2S0TXSCK      0x00011809
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_PHA0           0x00021002
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_FAULT2         0x00021404
+#define GPIO_PC5_CCP3           0x00021405
+#define GPIO_PC5_USB0EPEN       0x00021406
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_PHB0           0x00021802
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+#define GPIO_PC6_USB0PFLT       0x00021807
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_PHB0           0x00021C02
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_USB0PFLT       0x00021C06
+#define GPIO_PC7_C1O            0x00021C07
+
+#define GPIO_PD0_PWM0           0x00030001
+#define GPIO_PD0_CAN0RX         0x00030002
+#define GPIO_PD0_IDX0           0x00030003
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+#define GPIO_PD0_I2S0RXSCK      0x00030008
+#define GPIO_PD0_U1CTS          0x00030009
+
+#define GPIO_PD1_PWM1           0x00030401
+#define GPIO_PD1_CAN0TX         0x00030402
+#define GPIO_PD1_PHA0           0x00030403
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_I2S0RXWS       0x00030408
+#define GPIO_PD1_U1DCD          0x00030409
+#define GPIO_PD1_CCP2           0x0003040A
+#define GPIO_PD1_PHB1           0x0003040B
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_PWM2           0x00030803
+#define GPIO_PD2_CCP5           0x00030804
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_PWM3           0x00030C03
+#define GPIO_PD3_CCP0           0x00030C04
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+#define GPIO_PD4_I2S0RXSD       0x00031008
+#define GPIO_PD4_U1RI           0x00031009
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_I2S0RXMCLK     0x00031408
+#define GPIO_PD5_U2RX           0x00031409
+
+#define GPIO_PD6_FAULT0         0x00031801
+#define GPIO_PD6_I2S0TXSCK      0x00031808
+#define GPIO_PD6_U2TX           0x00031809
+
+#define GPIO_PD7_IDX0           0x00031C01
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+#define GPIO_PD7_I2S0TXWS       0x00031C08
+#define GPIO_PD7_U1DTR          0x00031C09
+
+#define GPIO_PE0_PWM4           0x00040001
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+#define GPIO_PE0_USB0PFLT       0x00040009
+
+#define GPIO_PE1_PWM5           0x00040401
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_FAULT0         0x00040403
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_PHB1           0x00040803
+#define GPIO_PE2_PHA0           0x00040804
+#define GPIO_PE2_CCP2           0x00040805
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_PHA1           0x00040C03
+#define GPIO_PE3_PHB0           0x00040C04
+#define GPIO_PE3_CCP7           0x00040C05
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_FAULT0         0x00041004
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+#define GPIO_PE4_I2S0TXWS       0x00041009
+
+#define GPIO_PE5_CCP5           0x00041401
+#define GPIO_PE5_I2S0TXSD       0x00041409
+
+#define GPIO_PE6_PWM4           0x00041801
+#define GPIO_PE6_C1O            0x00041802
+#define GPIO_PE6_U1CTS          0x00041809
+
+#define GPIO_PE7_PWM5           0x00041C01
+#define GPIO_PE7_U1DCD          0x00041C09
+
+#define GPIO_PF0_CAN1RX         0x00050001
+#define GPIO_PF0_PHB0           0x00050002
+#define GPIO_PF0_PWM0           0x00050003
+#define GPIO_PF0_I2S0TXSD       0x00050008
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_CAN1TX         0x00050401
+#define GPIO_PF1_IDX1           0x00050402
+#define GPIO_PF1_PWM1           0x00050403
+#define GPIO_PF1_I2S0TXMCLK     0x00050408
+#define GPIO_PF1_U1RTS          0x00050409
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_PWM4           0x00050802
+#define GPIO_PF2_PWM2           0x00050804
+#define GPIO_PF2_SSI1CLK        0x00050809
+
+#define GPIO_PF3_PWM5           0x00050C02
+#define GPIO_PF3_PWM3           0x00050C04
+#define GPIO_PF3_SSI1FSS        0x00050C09
+
+#define GPIO_PF4_CCP0           0x00051001
+#define GPIO_PF4_C0O            0x00051002
+#define GPIO_PF4_FAULT0         0x00051004
+#define GPIO_PF4_SSI1RX         0x00051009
+
+#define GPIO_PF5_CCP2           0x00051401
+#define GPIO_PF5_C1O            0x00051402
+#define GPIO_PF5_SSI1TX         0x00051409
+
+#define GPIO_PF6_CCP1           0x00051801
+#define GPIO_PF6_PHA0           0x00051804
+#define GPIO_PF6_I2S0TXMCLK     0x00051809
+#define GPIO_PF6_U1RTS          0x0005180A
+
+#define GPIO_PF7_CCP4           0x00051C01
+#define GPIO_PF7_PHB0           0x00051C04
+#define GPIO_PF7_FAULT1         0x00051C09
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_PWM0           0x00060002
+#define GPIO_PG0_I2C1SCL        0x00060003
+#define GPIO_PG0_PWM4           0x00060004
+#define GPIO_PG0_USB0EPEN       0x00060007
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_PWM1           0x00060402
+#define GPIO_PG1_I2C1SDA        0x00060403
+#define GPIO_PG1_PWM5           0x00060404
+
+#define GPIO_PG2_PWM0           0x00060801
+#define GPIO_PG2_FAULT0         0x00060804
+#define GPIO_PG2_IDX1           0x00060808
+#define GPIO_PG2_I2S0RXSD       0x00060809
+
+#define GPIO_PG3_PWM1           0x00060C01
+#define GPIO_PG3_FAULT2         0x00060C04
+#define GPIO_PG3_FAULT0         0x00060C08
+#define GPIO_PG3_I2S0RXMCLK     0x00060C09
+
+#define GPIO_PG4_CCP3           0x00061001
+#define GPIO_PG4_FAULT1         0x00061004
+#define GPIO_PG4_U1RI           0x0006100A
+
+#define GPIO_PG5_CCP5           0x00061401
+#define GPIO_PG5_IDX0           0x00061404
+#define GPIO_PG5_FAULT1         0x00061405
+#define GPIO_PG5_I2S0RXSCK      0x00061409
+#define GPIO_PG5_U1DTR          0x0006140A
+
+#define GPIO_PG6_PHA1           0x00061801
+#define GPIO_PG6_FAULT1         0x00061808
+#define GPIO_PG6_I2S0RXWS       0x00061809
+#define GPIO_PG6_U1RI           0x0006180A
+
+#define GPIO_PG7_PHB1           0x00061C01
+#define GPIO_PG7_CCP5           0x00061C08
+
+#define GPIO_PH0_CCP6           0x00070001
+#define GPIO_PH0_PWM2           0x00070002
+#define GPIO_PH0_PWM4           0x00070009
+
+#define GPIO_PH1_CCP7           0x00070401
+#define GPIO_PH1_PWM3           0x00070402
+#define GPIO_PH1_PWM5           0x00070409
+
+#define GPIO_PH2_IDX1           0x00070801
+#define GPIO_PH2_C1O            0x00070802
+#define GPIO_PH2_FAULT3         0x00070804
+
+#define GPIO_PH3_PHB0           0x00070C01
+#define GPIO_PH3_FAULT0         0x00070C02
+#define GPIO_PH3_USB0EPEN       0x00070C04
+
+#define GPIO_PH4_USB0PFLT       0x00071004
+#define GPIO_PH4_SSI1CLK        0x0007100B
+
+#define GPIO_PH5_FAULT2         0x0007140A
+#define GPIO_PH5_SSI1FSS        0x0007140B
+
+#define GPIO_PH6_PWM4           0x0007180A
+#define GPIO_PH6_SSI1RX         0x0007180B
+
+#define GPIO_PH7_PWM5           0x00071C0A
+#define GPIO_PH7_SSI1TX         0x00071C0B
+
+#define GPIO_PJ0_PWM0           0x0008000A
+#define GPIO_PJ0_I2C1SCL        0x0008000B
+
+#define GPIO_PJ1_USB0PFLT       0x00080409
+#define GPIO_PJ1_PWM1           0x0008040A
+#define GPIO_PJ1_I2C1SDA        0x0008040B
+
+#define GPIO_PJ2_CCP0           0x00080809
+#define GPIO_PJ2_FAULT0         0x0008080A
+
+#endif // PART_LM3S5C51
+
+//*****************************************************************************
+//
+// LM3S5C56 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S5C56
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_PWM4           0x00000804
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_PWM5           0x00000C04
+
+#define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_CAN0RX         0x00001005
+
+#define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_CAN0TX         0x00001405
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_PWM0           0x00001804
+#define GPIO_PA6_PWM4           0x00001805
+#define GPIO_PA6_CAN0RX         0x00001806
+#define GPIO_PA6_USB0EPEN       0x00001808
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_PWM1           0x00001C04
+#define GPIO_PA7_PWM5           0x00001C05
+#define GPIO_PA7_CAN0TX         0x00001C06
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_USB0PFLT       0x00001C08
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_PWM2           0x00010002
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_PWM3           0x00010402
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_IDX0           0x00010802
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+#define GPIO_PB2_USB0EPEN       0x00010808
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_FAULT0         0x00010C02
+#define GPIO_PB3_FAULT3         0x00010C04
+#define GPIO_PB3_USB0PFLT       0x00010C08
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_CAN0RX         0x00011005
+#define GPIO_PB4_IDX0           0x00011006
+#define GPIO_PB4_U1RX           0x00011007
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CAN0TX         0x00011405
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_FAULT1         0x00011804
+#define GPIO_PB6_IDX0           0x00011805
+#define GPIO_PB6_CCP5           0x00011806
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_PHA0           0x00021002
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_FAULT2         0x00021404
+#define GPIO_PC5_CCP3           0x00021405
+#define GPIO_PC5_USB0EPEN       0x00021406
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_PHB0           0x00021802
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+#define GPIO_PC6_USB0PFLT       0x00021807
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_PHB0           0x00021C02
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_USB0PFLT       0x00021C06
+#define GPIO_PC7_C1O            0x00021C07
+
+#define GPIO_PD0_PWM0           0x00030001
+#define GPIO_PD0_CAN0RX         0x00030002
+#define GPIO_PD0_IDX0           0x00030003
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+
+#define GPIO_PD1_PWM1           0x00030401
+#define GPIO_PD1_CAN0TX         0x00030402
+#define GPIO_PD1_PHA0           0x00030403
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_CCP2           0x0003040A
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_PWM2           0x00030803
+#define GPIO_PD2_CCP5           0x00030804
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_PWM3           0x00030C03
+#define GPIO_PD3_CCP0           0x00030C04
+
+#define GPIO_PE0_PWM4           0x00040001
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+#define GPIO_PE0_USB0PFLT       0x00040009
+
+#define GPIO_PE1_PWM5           0x00040401
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_FAULT0         0x00040403
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_PHA0           0x00040804
+#define GPIO_PE2_CCP2           0x00040805
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_PHB0           0x00040C04
+#define GPIO_PE3_CCP7           0x00040C05
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_FAULT0         0x00041004
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+
+#endif // PART_LM3S5C56
+
+//*****************************************************************************
+//
+// LM3S5D51 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S5D51
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_PWM4           0x00000804
+#define GPIO_PA2_I2S0RXSD       0x00000809
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_PWM5           0x00000C04
+#define GPIO_PA3_I2S0RXMCLK     0x00000C09
+
+#define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_CAN0RX         0x00001005
+#define GPIO_PA4_I2S0TXSCK      0x00001009
+
+#define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_CAN0TX         0x00001405
+#define GPIO_PA5_I2S0TXWS       0x00001409
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_PWM0           0x00001804
+#define GPIO_PA6_PWM4           0x00001805
+#define GPIO_PA6_CAN0RX         0x00001806
+#define GPIO_PA6_USB0EPEN       0x00001808
+#define GPIO_PA6_U1CTS          0x00001809
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_PWM1           0x00001C04
+#define GPIO_PA7_PWM5           0x00001C05
+#define GPIO_PA7_CAN0TX         0x00001C06
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_USB0PFLT       0x00001C08
+#define GPIO_PA7_U1DCD          0x00001C09
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_PWM2           0x00010002
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_PWM3           0x00010402
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_IDX0           0x00010802
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+#define GPIO_PB2_USB0EPEN       0x00010808
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_FAULT0         0x00010C02
+#define GPIO_PB3_FAULT3         0x00010C04
+#define GPIO_PB3_USB0PFLT       0x00010C08
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_CAN0RX         0x00011005
+#define GPIO_PB4_IDX0           0x00011006
+#define GPIO_PB4_U1RX           0x00011007
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CAN0TX         0x00011405
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_FAULT1         0x00011804
+#define GPIO_PB6_IDX0           0x00011805
+#define GPIO_PB6_CCP5           0x00011806
+#define GPIO_PB6_I2S0TXSCK      0x00011809
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_PHA0           0x00021002
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_FAULT2         0x00021404
+#define GPIO_PC5_CCP3           0x00021405
+#define GPIO_PC5_USB0EPEN       0x00021406
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_PHB0           0x00021802
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+#define GPIO_PC6_USB0PFLT       0x00021807
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_PHB0           0x00021C02
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_USB0PFLT       0x00021C06
+#define GPIO_PC7_C1O            0x00021C07
+
+#define GPIO_PD0_PWM0           0x00030001
+#define GPIO_PD0_CAN0RX         0x00030002
+#define GPIO_PD0_IDX0           0x00030003
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+#define GPIO_PD0_I2S0RXSCK      0x00030008
+#define GPIO_PD0_U1CTS          0x00030009
+
+#define GPIO_PD1_PWM1           0x00030401
+#define GPIO_PD1_CAN0TX         0x00030402
+#define GPIO_PD1_PHA0           0x00030403
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_I2S0RXWS       0x00030408
+#define GPIO_PD1_U1DCD          0x00030409
+#define GPIO_PD1_CCP2           0x0003040A
+#define GPIO_PD1_PHB1           0x0003040B
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_PWM2           0x00030803
+#define GPIO_PD2_CCP5           0x00030804
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_PWM3           0x00030C03
+#define GPIO_PD3_CCP0           0x00030C04
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+#define GPIO_PD4_I2S0RXSD       0x00031008
+#define GPIO_PD4_U1RI           0x00031009
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_I2S0RXMCLK     0x00031408
+#define GPIO_PD5_U2RX           0x00031409
+
+#define GPIO_PD6_FAULT0         0x00031801
+#define GPIO_PD6_I2S0TXSCK      0x00031808
+#define GPIO_PD6_U2TX           0x00031809
+
+#define GPIO_PD7_IDX0           0x00031C01
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+#define GPIO_PD7_I2S0TXWS       0x00031C08
+#define GPIO_PD7_U1DTR          0x00031C09
+
+#define GPIO_PE0_PWM4           0x00040001
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+#define GPIO_PE0_USB0PFLT       0x00040009
+
+#define GPIO_PE1_PWM5           0x00040401
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_FAULT0         0x00040403
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_PHB1           0x00040803
+#define GPIO_PE2_PHA0           0x00040804
+#define GPIO_PE2_CCP2           0x00040805
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_PHA1           0x00040C03
+#define GPIO_PE3_PHB0           0x00040C04
+#define GPIO_PE3_CCP7           0x00040C05
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_FAULT0         0x00041004
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+#define GPIO_PE4_I2S0TXWS       0x00041009
+
+#define GPIO_PE5_CCP5           0x00041401
+#define GPIO_PE5_I2S0TXSD       0x00041409
+
+#define GPIO_PE6_PWM4           0x00041801
+#define GPIO_PE6_C1O            0x00041802
+#define GPIO_PE6_U1CTS          0x00041809
+
+#define GPIO_PE7_PWM5           0x00041C01
+#define GPIO_PE7_U1DCD          0x00041C09
+
+#define GPIO_PF0_CAN1RX         0x00050001
+#define GPIO_PF0_PHB0           0x00050002
+#define GPIO_PF0_PWM0           0x00050003
+#define GPIO_PF0_I2S0TXSD       0x00050008
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_CAN1TX         0x00050401
+#define GPIO_PF1_IDX1           0x00050402
+#define GPIO_PF1_PWM1           0x00050403
+#define GPIO_PF1_I2S0TXMCLK     0x00050408
+#define GPIO_PF1_U1RTS          0x00050409
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_PWM4           0x00050802
+#define GPIO_PF2_PWM2           0x00050804
+#define GPIO_PF2_SSI1CLK        0x00050809
+
+#define GPIO_PF3_PWM5           0x00050C02
+#define GPIO_PF3_PWM3           0x00050C04
+#define GPIO_PF3_SSI1FSS        0x00050C09
+
+#define GPIO_PF4_CCP0           0x00051001
+#define GPIO_PF4_C0O            0x00051002
+#define GPIO_PF4_FAULT0         0x00051004
+#define GPIO_PF4_SSI1RX         0x00051009
+
+#define GPIO_PF5_CCP2           0x00051401
+#define GPIO_PF5_C1O            0x00051402
+#define GPIO_PF5_SSI1TX         0x00051409
+
+#define GPIO_PF6_CCP1           0x00051801
+#define GPIO_PF6_PHA0           0x00051804
+#define GPIO_PF6_I2S0TXMCLK     0x00051809
+#define GPIO_PF6_U1RTS          0x0005180A
+
+#define GPIO_PF7_CCP4           0x00051C01
+#define GPIO_PF7_PHB0           0x00051C04
+#define GPIO_PF7_FAULT1         0x00051C09
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_PWM0           0x00060002
+#define GPIO_PG0_I2C1SCL        0x00060003
+#define GPIO_PG0_PWM4           0x00060004
+#define GPIO_PG0_USB0EPEN       0x00060007
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_PWM1           0x00060402
+#define GPIO_PG1_I2C1SDA        0x00060403
+#define GPIO_PG1_PWM5           0x00060404
+
+#define GPIO_PG2_PWM0           0x00060801
+#define GPIO_PG2_FAULT0         0x00060804
+#define GPIO_PG2_IDX1           0x00060808
+#define GPIO_PG2_I2S0RXSD       0x00060809
+
+#define GPIO_PG3_PWM1           0x00060C01
+#define GPIO_PG3_FAULT2         0x00060C04
+#define GPIO_PG3_FAULT0         0x00060C08
+#define GPIO_PG3_I2S0RXMCLK     0x00060C09
+
+#define GPIO_PG4_CCP3           0x00061001
+#define GPIO_PG4_FAULT1         0x00061004
+#define GPIO_PG4_U1RI           0x0006100A
+
+#define GPIO_PG5_CCP5           0x00061401
+#define GPIO_PG5_IDX0           0x00061404
+#define GPIO_PG5_FAULT1         0x00061405
+#define GPIO_PG5_I2S0RXSCK      0x00061409
+#define GPIO_PG5_U1DTR          0x0006140A
+
+#define GPIO_PG6_PHA1           0x00061801
+#define GPIO_PG6_FAULT1         0x00061808
+#define GPIO_PG6_I2S0RXWS       0x00061809
+#define GPIO_PG6_U1RI           0x0006180A
+
+#define GPIO_PG7_PHB1           0x00061C01
+#define GPIO_PG7_CCP5           0x00061C08
+
+#define GPIO_PH0_CCP6           0x00070001
+#define GPIO_PH0_PWM2           0x00070002
+#define GPIO_PH0_PWM4           0x00070009
+
+#define GPIO_PH1_CCP7           0x00070401
+#define GPIO_PH1_PWM3           0x00070402
+#define GPIO_PH1_PWM5           0x00070409
+
+#define GPIO_PH2_IDX1           0x00070801
+#define GPIO_PH2_C1O            0x00070802
+#define GPIO_PH2_FAULT3         0x00070804
+
+#define GPIO_PH3_PHB0           0x00070C01
+#define GPIO_PH3_FAULT0         0x00070C02
+#define GPIO_PH3_USB0EPEN       0x00070C04
+
+#define GPIO_PH4_USB0PFLT       0x00071004
+#define GPIO_PH4_SSI1CLK        0x0007100B
+
+#define GPIO_PH5_FAULT2         0x0007140A
+#define GPIO_PH5_SSI1FSS        0x0007140B
+
+#define GPIO_PH6_PWM4           0x0007180A
+#define GPIO_PH6_SSI1RX         0x0007180B
+
+#define GPIO_PH7_PWM5           0x00071C0A
+#define GPIO_PH7_SSI1TX         0x00071C0B
+
+#define GPIO_PJ0_PWM0           0x0008000A
+#define GPIO_PJ0_I2C1SCL        0x0008000B
+
+#define GPIO_PJ1_USB0PFLT       0x00080409
+#define GPIO_PJ1_PWM1           0x0008040A
+#define GPIO_PJ1_I2C1SDA        0x0008040B
+
+#define GPIO_PJ2_CCP0           0x00080809
+#define GPIO_PJ2_FAULT0         0x0008080A
+
+#endif // PART_LM3S5D51
+
+//*****************************************************************************
+//
+// LM3S5D56 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S5D56
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_PWM4           0x00000804
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_PWM5           0x00000C04
+
+#define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_CAN0RX         0x00001005
+
+#define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_CAN0TX         0x00001405
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_PWM0           0x00001804
+#define GPIO_PA6_PWM4           0x00001805
+#define GPIO_PA6_CAN0RX         0x00001806
+#define GPIO_PA6_USB0EPEN       0x00001808
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_PWM1           0x00001C04
+#define GPIO_PA7_PWM5           0x00001C05
+#define GPIO_PA7_CAN0TX         0x00001C06
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_USB0PFLT       0x00001C08
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_PWM2           0x00010002
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_PWM3           0x00010402
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_IDX0           0x00010802
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+#define GPIO_PB2_USB0EPEN       0x00010808
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_FAULT0         0x00010C02
+#define GPIO_PB3_FAULT3         0x00010C04
+#define GPIO_PB3_USB0PFLT       0x00010C08
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_CAN0RX         0x00011005
+#define GPIO_PB4_IDX0           0x00011006
+#define GPIO_PB4_U1RX           0x00011007
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CAN0TX         0x00011405
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_FAULT1         0x00011804
+#define GPIO_PB6_IDX0           0x00011805
+#define GPIO_PB6_CCP5           0x00011806
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_PHA0           0x00021002
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_FAULT2         0x00021404
+#define GPIO_PC5_CCP3           0x00021405
+#define GPIO_PC5_USB0EPEN       0x00021406
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_PHB0           0x00021802
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+#define GPIO_PC6_USB0PFLT       0x00021807
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_PHB0           0x00021C02
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_USB0PFLT       0x00021C06
+#define GPIO_PC7_C1O            0x00021C07
+
+#define GPIO_PD0_PWM0           0x00030001
+#define GPIO_PD0_CAN0RX         0x00030002
+#define GPIO_PD0_IDX0           0x00030003
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+
+#define GPIO_PD1_PWM1           0x00030401
+#define GPIO_PD1_CAN0TX         0x00030402
+#define GPIO_PD1_PHA0           0x00030403
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_CCP2           0x0003040A
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_PWM2           0x00030803
+#define GPIO_PD2_CCP5           0x00030804
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_PWM3           0x00030C03
+#define GPIO_PD3_CCP0           0x00030C04
+
+#define GPIO_PE0_PWM4           0x00040001
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+#define GPIO_PE0_USB0PFLT       0x00040009
+
+#define GPIO_PE1_PWM5           0x00040401
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_FAULT0         0x00040403
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_PHA0           0x00040804
+#define GPIO_PE2_CCP2           0x00040805
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_PHB0           0x00040C04
+#define GPIO_PE3_CCP7           0x00040C05
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_FAULT0         0x00041004
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+
+#endif // PART_LM3S5D56
+
+//*****************************************************************************
+//
+// LM3S5D91 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S5D91
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_PWM4           0x00000804
+#define GPIO_PA2_I2S0RXSD       0x00000809
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_PWM5           0x00000C04
+#define GPIO_PA3_I2S0RXMCLK     0x00000C09
+
+#define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_PWM6           0x00001004
+#define GPIO_PA4_CAN0RX         0x00001005
+#define GPIO_PA4_I2S0TXSCK      0x00001009
+
+#define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_PWM7           0x00001404
+#define GPIO_PA5_CAN0TX         0x00001405
+#define GPIO_PA5_I2S0TXWS       0x00001409
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_PWM0           0x00001804
+#define GPIO_PA6_PWM4           0x00001805
+#define GPIO_PA6_CAN0RX         0x00001806
+#define GPIO_PA6_USB0EPEN       0x00001808
+#define GPIO_PA6_U1CTS          0x00001809
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_PWM1           0x00001C04
+#define GPIO_PA7_PWM5           0x00001C05
+#define GPIO_PA7_CAN0TX         0x00001C06
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_USB0PFLT       0x00001C08
+#define GPIO_PA7_U1DCD          0x00001C09
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_PWM2           0x00010002
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_PWM3           0x00010402
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_IDX0           0x00010802
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+#define GPIO_PB2_USB0EPEN       0x00010808
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_FAULT0         0x00010C02
+#define GPIO_PB3_FAULT3         0x00010C04
+#define GPIO_PB3_USB0PFLT       0x00010C08
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_CAN0RX         0x00011005
+#define GPIO_PB4_IDX0           0x00011006
+#define GPIO_PB4_U1RX           0x00011007
+#define GPIO_PB4_EPI0S23        0x00011008
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CAN0TX         0x00011405
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+#define GPIO_PB5_EPI0S22        0x00011408
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_FAULT1         0x00011804
+#define GPIO_PB6_IDX0           0x00011805
+#define GPIO_PB6_CCP5           0x00011806
+#define GPIO_PB6_I2S0TXSCK      0x00011809
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_PHA0           0x00021002
+#define GPIO_PC4_PWM6           0x00021004
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_EPI0S2         0x00021008
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_FAULT2         0x00021404
+#define GPIO_PC5_CCP3           0x00021405
+#define GPIO_PC5_USB0EPEN       0x00021406
+#define GPIO_PC5_EPI0S3         0x00021408
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_PHB0           0x00021802
+#define GPIO_PC6_C2O            0x00021803
+#define GPIO_PC6_PWM7           0x00021804
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+#define GPIO_PC6_USB0PFLT       0x00021807
+#define GPIO_PC6_EPI0S4         0x00021808
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_PHB0           0x00021C02
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_USB0PFLT       0x00021C06
+#define GPIO_PC7_C1O            0x00021C07
+#define GPIO_PC7_EPI0S5         0x00021C08
+
+#define GPIO_PD0_PWM0           0x00030001
+#define GPIO_PD0_CAN0RX         0x00030002
+#define GPIO_PD0_IDX0           0x00030003
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+#define GPIO_PD0_I2S0RXSCK      0x00030008
+#define GPIO_PD0_U1CTS          0x00030009
+
+#define GPIO_PD1_PWM1           0x00030401
+#define GPIO_PD1_CAN0TX         0x00030402
+#define GPIO_PD1_PHA0           0x00030403
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_I2S0RXWS       0x00030408
+#define GPIO_PD1_U1DCD          0x00030409
+#define GPIO_PD1_CCP2           0x0003040A
+#define GPIO_PD1_PHB1           0x0003040B
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_PWM2           0x00030803
+#define GPIO_PD2_CCP5           0x00030804
+#define GPIO_PD2_EPI0S20        0x00030808
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_PWM3           0x00030C03
+#define GPIO_PD3_CCP0           0x00030C04
+#define GPIO_PD3_EPI0S21        0x00030C08
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+#define GPIO_PD4_I2S0RXSD       0x00031008
+#define GPIO_PD4_U1RI           0x00031009
+#define GPIO_PD4_EPI0S19        0x0003100A
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_I2S0RXMCLK     0x00031408
+#define GPIO_PD5_U2RX           0x00031409
+#define GPIO_PD5_EPI0S28        0x0003140A
+
+#define GPIO_PD6_FAULT0         0x00031801
+#define GPIO_PD6_I2S0TXSCK      0x00031808
+#define GPIO_PD6_U2TX           0x00031809
+#define GPIO_PD6_EPI0S29        0x0003180A
+
+#define GPIO_PD7_IDX0           0x00031C01
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+#define GPIO_PD7_I2S0TXWS       0x00031C08
+#define GPIO_PD7_U1DTR          0x00031C09
+#define GPIO_PD7_EPI0S30        0x00031C0A
+
+#define GPIO_PE0_PWM4           0x00040001
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+#define GPIO_PE0_EPI0S8         0x00040008
+#define GPIO_PE0_USB0PFLT       0x00040009
+
+#define GPIO_PE1_PWM5           0x00040401
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_FAULT0         0x00040403
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+#define GPIO_PE1_EPI0S9         0x00040408
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_PHB1           0x00040803
+#define GPIO_PE2_PHA0           0x00040804
+#define GPIO_PE2_CCP2           0x00040805
+#define GPIO_PE2_EPI0S24        0x00040808
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_PHA1           0x00040C03
+#define GPIO_PE3_PHB0           0x00040C04
+#define GPIO_PE3_CCP7           0x00040C05
+#define GPIO_PE3_EPI0S25        0x00040C08
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_FAULT0         0x00041004
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+#define GPIO_PE4_I2S0TXWS       0x00041009
+
+#define GPIO_PE5_CCP5           0x00041401
+#define GPIO_PE5_I2S0TXSD       0x00041409
+
+#define GPIO_PE6_PWM4           0x00041801
+#define GPIO_PE6_C1O            0x00041802
+#define GPIO_PE6_U1CTS          0x00041809
+
+#define GPIO_PE7_PWM5           0x00041C01
+#define GPIO_PE7_C2O            0x00041C02
+#define GPIO_PE7_U1DCD          0x00041C09
+
+#define GPIO_PF0_CAN1RX         0x00050001
+#define GPIO_PF0_PHB0           0x00050002
+#define GPIO_PF0_PWM0           0x00050003
+#define GPIO_PF0_I2S0TXSD       0x00050008
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_CAN1TX         0x00050401
+#define GPIO_PF1_IDX1           0x00050402
+#define GPIO_PF1_PWM1           0x00050403
+#define GPIO_PF1_I2S0TXMCLK     0x00050408
+#define GPIO_PF1_U1RTS          0x00050409
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_PWM4           0x00050802
+#define GPIO_PF2_PWM2           0x00050804
+#define GPIO_PF2_SSI1CLK        0x00050809
+
+#define GPIO_PF3_PWM5           0x00050C02
+#define GPIO_PF3_PWM3           0x00050C04
+#define GPIO_PF3_SSI1FSS        0x00050C09
+
+#define GPIO_PF4_CCP0           0x00051001
+#define GPIO_PF4_C0O            0x00051002
+#define GPIO_PF4_FAULT0         0x00051004
+#define GPIO_PF4_EPI0S12        0x00051008
+#define GPIO_PF4_SSI1RX         0x00051009
+
+#define GPIO_PF5_CCP2           0x00051401
+#define GPIO_PF5_C1O            0x00051402
+#define GPIO_PF5_EPI0S15        0x00051408
+#define GPIO_PF5_SSI1TX         0x00051409
+
+#define GPIO_PF6_CCP1           0x00051801
+#define GPIO_PF6_C2O            0x00051802
+#define GPIO_PF6_PHA0           0x00051804
+#define GPIO_PF6_I2S0TXMCLK     0x00051809
+#define GPIO_PF6_U1RTS          0x0005180A
+
+#define GPIO_PF7_CCP4           0x00051C01
+#define GPIO_PF7_PHB0           0x00051C04
+#define GPIO_PF7_EPI0S12        0x00051C08
+#define GPIO_PF7_FAULT1         0x00051C09
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_PWM0           0x00060002
+#define GPIO_PG0_I2C1SCL        0x00060003
+#define GPIO_PG0_PWM4           0x00060004
+#define GPIO_PG0_USB0EPEN       0x00060007
+#define GPIO_PG0_EPI0S13        0x00060008
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_PWM1           0x00060402
+#define GPIO_PG1_I2C1SDA        0x00060403
+#define GPIO_PG1_PWM5           0x00060404
+#define GPIO_PG1_EPI0S14        0x00060408
+
+#define GPIO_PG2_PWM0           0x00060801
+#define GPIO_PG2_FAULT0         0x00060804
+#define GPIO_PG2_IDX1           0x00060808
+#define GPIO_PG2_I2S0RXSD       0x00060809
+
+#define GPIO_PG3_PWM1           0x00060C01
+#define GPIO_PG3_FAULT2         0x00060C04
+#define GPIO_PG3_FAULT0         0x00060C08
+#define GPIO_PG3_I2S0RXMCLK     0x00060C09
+
+#define GPIO_PG4_CCP3           0x00061001
+#define GPIO_PG4_FAULT1         0x00061004
+#define GPIO_PG4_EPI0S15        0x00061008
+#define GPIO_PG4_PWM6           0x00061009
+#define GPIO_PG4_U1RI           0x0006100A
+
+#define GPIO_PG5_CCP5           0x00061401
+#define GPIO_PG5_IDX0           0x00061404
+#define GPIO_PG5_FAULT1         0x00061405
+#define GPIO_PG5_PWM7           0x00061408
+#define GPIO_PG5_I2S0RXSCK      0x00061409
+#define GPIO_PG5_U1DTR          0x0006140A
+
+#define GPIO_PG6_PHA1           0x00061801
+#define GPIO_PG6_PWM6           0x00061804
+#define GPIO_PG6_FAULT1         0x00061808
+#define GPIO_PG6_I2S0RXWS       0x00061809
+#define GPIO_PG6_U1RI           0x0006180A
+
+#define GPIO_PG7_PHB1           0x00061C01
+#define GPIO_PG7_PWM7           0x00061C04
+#define GPIO_PG7_CCP5           0x00061C08
+#define GPIO_PG7_EPI0S31        0x00061C09
+
+#define GPIO_PH0_CCP6           0x00070001
+#define GPIO_PH0_PWM2           0x00070002
+#define GPIO_PH0_EPI0S6         0x00070008
+#define GPIO_PH0_PWM4           0x00070009
+
+#define GPIO_PH1_CCP7           0x00070401
+#define GPIO_PH1_PWM3           0x00070402
+#define GPIO_PH1_EPI0S7         0x00070408
+#define GPIO_PH1_PWM5           0x00070409
+
+#define GPIO_PH2_IDX1           0x00070801
+#define GPIO_PH2_C1O            0x00070802
+#define GPIO_PH2_FAULT3         0x00070804
+#define GPIO_PH2_EPI0S1         0x00070808
+
+#define GPIO_PH3_PHB0           0x00070C01
+#define GPIO_PH3_FAULT0         0x00070C02
+#define GPIO_PH3_USB0EPEN       0x00070C04
+#define GPIO_PH3_EPI0S0         0x00070C08
+
+#define GPIO_PH4_USB0PFLT       0x00071004
+#define GPIO_PH4_EPI0S10        0x00071008
+#define GPIO_PH4_SSI1CLK        0x0007100B
+
+#define GPIO_PH5_EPI0S11        0x00071408
+#define GPIO_PH5_FAULT2         0x0007140A
+#define GPIO_PH5_SSI1FSS        0x0007140B
+
+#define GPIO_PH6_EPI0S26        0x00071808
+#define GPIO_PH6_PWM4           0x0007180A
+#define GPIO_PH6_SSI1RX         0x0007180B
+
+#define GPIO_PH7_EPI0S27        0x00071C08
+#define GPIO_PH7_PWM5           0x00071C0A
+#define GPIO_PH7_SSI1TX         0x00071C0B
+
+#define GPIO_PJ0_EPI0S16        0x00080008
+#define GPIO_PJ0_PWM0           0x0008000A
+#define GPIO_PJ0_I2C1SCL        0x0008000B
+
+#define GPIO_PJ1_EPI0S17        0x00080408
+#define GPIO_PJ1_USB0PFLT       0x00080409
+#define GPIO_PJ1_PWM1           0x0008040A
+#define GPIO_PJ1_I2C1SDA        0x0008040B
+
+#define GPIO_PJ2_EPI0S18        0x00080808
+#define GPIO_PJ2_CCP0           0x00080809
+#define GPIO_PJ2_FAULT0         0x0008080A
+
+#define GPIO_PJ3_EPI0S19        0x00080C08
+#define GPIO_PJ3_U1CTS          0x00080C09
+#define GPIO_PJ3_CCP6           0x00080C0A
+
+#define GPIO_PJ4_EPI0S28        0x00081008
+#define GPIO_PJ4_U1DCD          0x00081009
+#define GPIO_PJ4_CCP4           0x0008100A
+
+#define GPIO_PJ5_EPI0S29        0x00081408
+#define GPIO_PJ5_U1DSR          0x00081409
+#define GPIO_PJ5_CCP2           0x0008140A
+
+#define GPIO_PJ6_EPI0S30        0x00081808
+#define GPIO_PJ6_U1RTS          0x00081809
+#define GPIO_PJ6_CCP1           0x0008180A
+
+#define GPIO_PJ7_U1DTR          0x00081C09
+#define GPIO_PJ7_CCP0           0x00081C0A
+
+#endif // PART_LM3S5D91
+
+//*****************************************************************************
+//
+// LM3S5G31 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S5G31
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_PWM4           0x00000804
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_PWM5           0x00000C04
+
+#define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_CAN0RX         0x00001005
+
+#define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_CAN0TX         0x00001405
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_PWM0           0x00001804
+#define GPIO_PA6_PWM4           0x00001805
+#define GPIO_PA6_CAN0RX         0x00001806
+#define GPIO_PA6_U1CTS          0x00001809
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_PWM1           0x00001C04
+#define GPIO_PA7_PWM5           0x00001C05
+#define GPIO_PA7_CAN0TX         0x00001C06
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_U1DCD          0x00001C09
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_PWM2           0x00010002
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_PWM3           0x00010402
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_IDX0           0x00010802
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_FAULT0         0x00010C02
+#define GPIO_PB3_FAULT3         0x00010C04
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_CAN0RX         0x00011005
+#define GPIO_PB4_IDX0           0x00011006
+#define GPIO_PB4_U1RX           0x00011007
+#define GPIO_PB4_EPI0S23        0x00011008
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CAN0TX         0x00011405
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+#define GPIO_PB5_EPI0S22        0x00011408
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_FAULT1         0x00011804
+#define GPIO_PB6_IDX0           0x00011805
+#define GPIO_PB6_CCP5           0x00011806
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_PHA0           0x00021002
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_EPI0S2         0x00021008
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_FAULT2         0x00021404
+#define GPIO_PC5_CCP3           0x00021405
+#define GPIO_PC5_EPI0S3         0x00021408
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_PHB0           0x00021802
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+#define GPIO_PC6_EPI0S4         0x00021808
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_PHB0           0x00021C02
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_C1O            0x00021C07
+#define GPIO_PC7_EPI0S5         0x00021C08
+
+#define GPIO_PD0_PWM0           0x00030001
+#define GPIO_PD0_CAN0RX         0x00030002
+#define GPIO_PD0_IDX0           0x00030003
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_U1CTS          0x00030009
+
+#define GPIO_PD1_PWM1           0x00030401
+#define GPIO_PD1_CAN0TX         0x00030402
+#define GPIO_PD1_PHA0           0x00030403
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_U1DCD          0x00030409
+#define GPIO_PD1_CCP2           0x0003040A
+#define GPIO_PD1_PHB1           0x0003040B
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_PWM2           0x00030803
+#define GPIO_PD2_CCP5           0x00030804
+#define GPIO_PD2_EPI0S20        0x00030808
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_PWM3           0x00030C03
+#define GPIO_PD3_CCP0           0x00030C04
+#define GPIO_PD3_EPI0S21        0x00030C08
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+#define GPIO_PD4_U1RI           0x00031009
+#define GPIO_PD4_EPI0S19        0x0003100A
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_U2RX           0x00031409
+#define GPIO_PD5_EPI0S28        0x0003140A
+
+#define GPIO_PD6_FAULT0         0x00031801
+#define GPIO_PD6_U2TX           0x00031809
+#define GPIO_PD6_EPI0S29        0x0003180A
+
+#define GPIO_PD7_IDX0           0x00031C01
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+#define GPIO_PD7_U1DTR          0x00031C09
+#define GPIO_PD7_EPI0S30        0x00031C0A
+
+#define GPIO_PE0_PWM4           0x00040001
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+#define GPIO_PE0_EPI0S8         0x00040008
+
+#define GPIO_PE1_PWM5           0x00040401
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_FAULT0         0x00040403
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_EPI0S9         0x00040408
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_PHB1           0x00040803
+#define GPIO_PE2_PHA0           0x00040804
+#define GPIO_PE2_CCP2           0x00040805
+#define GPIO_PE2_EPI0S24        0x00040808
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_PHA1           0x00040C03
+#define GPIO_PE3_PHB0           0x00040C04
+#define GPIO_PE3_EPI0S25        0x00040C08
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_FAULT0         0x00041004
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+
+#define GPIO_PE5_CCP5           0x00041401
+
+#define GPIO_PE6_PWM4           0x00041801
+#define GPIO_PE6_C1O            0x00041802
+#define GPIO_PE6_U1CTS          0x00041809
+
+#define GPIO_PE7_PWM5           0x00041C01
+#define GPIO_PE7_U1DCD          0x00041C09
+
+#define GPIO_PF0_PHB0           0x00050002
+#define GPIO_PF0_PWM0           0x00050003
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_IDX1           0x00050402
+#define GPIO_PF1_PWM1           0x00050403
+#define GPIO_PF1_U1RTS          0x00050409
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_PWM4           0x00050802
+#define GPIO_PF2_PWM2           0x00050804
+#define GPIO_PF2_SSI1CLK        0x00050809
+
+#define GPIO_PF3_PWM5           0x00050C02
+#define GPIO_PF3_PWM3           0x00050C04
+#define GPIO_PF3_SSI1FSS        0x00050C09
+
+#define GPIO_PF4_CCP0           0x00051001
+#define GPIO_PF4_C0O            0x00051002
+#define GPIO_PF4_FAULT0         0x00051004
+#define GPIO_PF4_EPI0S12        0x00051008
+#define GPIO_PF4_SSI1RX         0x00051009
+
+#define GPIO_PF5_CCP2           0x00051401
+#define GPIO_PF5_C1O            0x00051402
+#define GPIO_PF5_EPI0S15        0x00051408
+#define GPIO_PF5_SSI1TX         0x00051409
+
+#define GPIO_PF6_CCP1           0x00051801
+#define GPIO_PF6_PHA0           0x00051804
+#define GPIO_PF6_U1RTS          0x0005180A
+
+#define GPIO_PF7_CCP4           0x00051C01
+#define GPIO_PF7_PHB0           0x00051C04
+#define GPIO_PF7_EPI0S12        0x00051C08
+#define GPIO_PF7_FAULT1         0x00051C09
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_PWM0           0x00060002
+#define GPIO_PG0_I2C1SCL        0x00060003
+#define GPIO_PG0_PWM4           0x00060004
+#define GPIO_PG0_EPI0S13        0x00060008
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_PWM1           0x00060402
+#define GPIO_PG1_I2C1SDA        0x00060403
+#define GPIO_PG1_PWM5           0x00060404
+#define GPIO_PG1_EPI0S14        0x00060408
+
+#define GPIO_PG2_PWM0           0x00060801
+#define GPIO_PG2_FAULT0         0x00060804
+#define GPIO_PG2_IDX1           0x00060808
+
+#define GPIO_PG3_PWM1           0x00060C01
+#define GPIO_PG3_FAULT2         0x00060C04
+#define GPIO_PG3_FAULT0         0x00060C08
+
+#define GPIO_PG4_CCP3           0x00061001
+#define GPIO_PG4_FAULT1         0x00061004
+#define GPIO_PG4_EPI0S15        0x00061008
+#define GPIO_PG4_U1RI           0x0006100A
+
+#define GPIO_PG5_CCP5           0x00061401
+#define GPIO_PG5_IDX0           0x00061404
+#define GPIO_PG5_FAULT1         0x00061405
+#define GPIO_PG5_U1DTR          0x0006140A
+
+#define GPIO_PG6_PHA1           0x00061801
+#define GPIO_PG6_FAULT1         0x00061808
+#define GPIO_PG6_U1RI           0x0006180A
+
+#define GPIO_PG7_PHB1           0x00061C01
+#define GPIO_PG7_CCP5           0x00061C08
+#define GPIO_PG7_EPI0S31        0x00061C09
+
+#define GPIO_PH0_PWM2           0x00070002
+#define GPIO_PH0_EPI0S6         0x00070008
+#define GPIO_PH0_PWM4           0x00070009
+
+#define GPIO_PH1_PWM3           0x00070402
+#define GPIO_PH1_EPI0S7         0x00070408
+#define GPIO_PH1_PWM5           0x00070409
+
+#define GPIO_PH2_IDX1           0x00070801
+#define GPIO_PH2_C1O            0x00070802
+#define GPIO_PH2_FAULT3         0x00070804
+#define GPIO_PH2_EPI0S1         0x00070808
+
+#define GPIO_PH3_PHB0           0x00070C01
+#define GPIO_PH3_FAULT0         0x00070C02
+#define GPIO_PH3_EPI0S0         0x00070C08
+
+#define GPIO_PH4_EPI0S10        0x00071008
+#define GPIO_PH4_SSI1CLK        0x0007100B
+
+#define GPIO_PH5_EPI0S11        0x00071408
+#define GPIO_PH5_FAULT2         0x0007140A
+#define GPIO_PH5_SSI1FSS        0x0007140B
+
+#define GPIO_PH6_EPI0S26        0x00071808
+#define GPIO_PH6_PWM4           0x0007180A
+#define GPIO_PH6_SSI1RX         0x0007180B
+
+#define GPIO_PH7_EPI0S27        0x00071C08
+#define GPIO_PH7_PWM5           0x00071C0A
+#define GPIO_PH7_SSI1TX         0x00071C0B
+
+#define GPIO_PJ0_EPI0S16        0x00080008
+#define GPIO_PJ0_PWM0           0x0008000A
+#define GPIO_PJ0_I2C1SCL        0x0008000B
+
+#define GPIO_PJ1_EPI0S17        0x00080408
+#define GPIO_PJ1_PWM1           0x0008040A
+#define GPIO_PJ1_I2C1SDA        0x0008040B
+
+#define GPIO_PJ2_EPI0S18        0x00080808
+#define GPIO_PJ2_CCP0           0x00080809
+#define GPIO_PJ2_FAULT0         0x0008080A
+
+#endif // PART_LM3S5G31
+
+//*****************************************************************************
+//
+// LM3S5G36 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S5G36
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_PWM4           0x00000804
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_PWM5           0x00000C04
+
+#define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_PWM6           0x00001004
+#define GPIO_PA4_CAN0RX         0x00001005
+
+#define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_PWM7           0x00001404
+#define GPIO_PA5_CAN0TX         0x00001405
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_PWM0           0x00001804
+#define GPIO_PA6_PWM4           0x00001805
+#define GPIO_PA6_CAN0RX         0x00001806
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_PWM1           0x00001C04
+#define GPIO_PA7_PWM5           0x00001C05
+#define GPIO_PA7_CAN0TX         0x00001C06
+#define GPIO_PA7_CCP3           0x00001C07
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_PWM2           0x00010002
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_PWM3           0x00010402
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_IDX0           0x00010802
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_FAULT0         0x00010C02
+#define GPIO_PB3_FAULT3         0x00010C04
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_CAN0RX         0x00011005
+#define GPIO_PB4_IDX0           0x00011006
+#define GPIO_PB4_U1RX           0x00011007
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CAN0TX         0x00011405
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_FAULT1         0x00011804
+#define GPIO_PB6_IDX0           0x00011805
+#define GPIO_PB6_CCP5           0x00011806
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_PHA0           0x00021002
+#define GPIO_PC4_PWM6           0x00021004
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_FAULT2         0x00021404
+#define GPIO_PC5_CCP3           0x00021405
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_PHB0           0x00021802
+#define GPIO_PC6_PWM7           0x00021804
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_PHB0           0x00021C02
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_C1O            0x00021C07
+
+#define GPIO_PD0_PWM0           0x00030001
+#define GPIO_PD0_CAN0RX         0x00030002
+#define GPIO_PD0_IDX0           0x00030003
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+
+#define GPIO_PD1_PWM1           0x00030401
+#define GPIO_PD1_CAN0TX         0x00030402
+#define GPIO_PD1_PHA0           0x00030403
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_CCP2           0x0003040A
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_PWM2           0x00030803
+#define GPIO_PD2_CCP5           0x00030804
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_PWM3           0x00030C03
+#define GPIO_PD3_CCP0           0x00030C04
+
+#define GPIO_PE0_PWM4           0x00040001
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+
+#define GPIO_PE1_PWM5           0x00040401
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_FAULT0         0x00040403
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_PHA0           0x00040804
+#define GPIO_PE2_CCP2           0x00040805
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_PHB0           0x00040C04
+#define GPIO_PE3_CCP7           0x00040C05
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_FAULT0         0x00041004
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+
+#endif // PART_LM3S5G36
+
+//*****************************************************************************
+//
+// LM3S5G51 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S5G51
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_PWM4           0x00000804
+#define GPIO_PA2_I2S0RXSD       0x00000809
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_PWM5           0x00000C04
+#define GPIO_PA3_I2S0RXMCLK     0x00000C09
+
+#define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_CAN0RX         0x00001005
+#define GPIO_PA4_I2S0TXSCK      0x00001009
+
+#define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_CAN0TX         0x00001405
+#define GPIO_PA5_I2S0TXWS       0x00001409
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_PWM0           0x00001804
+#define GPIO_PA6_PWM4           0x00001805
+#define GPIO_PA6_CAN0RX         0x00001806
+#define GPIO_PA6_USB0EPEN       0x00001808
+#define GPIO_PA6_U1CTS          0x00001809
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_PWM1           0x00001C04
+#define GPIO_PA7_PWM5           0x00001C05
+#define GPIO_PA7_CAN0TX         0x00001C06
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_USB0PFLT       0x00001C08
+#define GPIO_PA7_U1DCD          0x00001C09
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_PWM2           0x00010002
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_PWM3           0x00010402
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_IDX0           0x00010802
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+#define GPIO_PB2_USB0EPEN       0x00010808
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_FAULT0         0x00010C02
+#define GPIO_PB3_FAULT3         0x00010C04
+#define GPIO_PB3_USB0PFLT       0x00010C08
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_CAN0RX         0x00011005
+#define GPIO_PB4_IDX0           0x00011006
+#define GPIO_PB4_U1RX           0x00011007
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CAN0TX         0x00011405
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_FAULT1         0x00011804
+#define GPIO_PB6_IDX0           0x00011805
+#define GPIO_PB6_CCP5           0x00011806
+#define GPIO_PB6_I2S0TXSCK      0x00011809
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_PHA0           0x00021002
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_FAULT2         0x00021404
+#define GPIO_PC5_CCP3           0x00021405
+#define GPIO_PC5_USB0EPEN       0x00021406
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_PHB0           0x00021802
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+#define GPIO_PC6_USB0PFLT       0x00021807
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_PHB0           0x00021C02
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_USB0PFLT       0x00021C06
+#define GPIO_PC7_C1O            0x00021C07
+
+#define GPIO_PD0_PWM0           0x00030001
+#define GPIO_PD0_CAN0RX         0x00030002
+#define GPIO_PD0_IDX0           0x00030003
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+#define GPIO_PD0_I2S0RXSCK      0x00030008
+#define GPIO_PD0_U1CTS          0x00030009
+
+#define GPIO_PD1_PWM1           0x00030401
+#define GPIO_PD1_CAN0TX         0x00030402
+#define GPIO_PD1_PHA0           0x00030403
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_I2S0RXWS       0x00030408
+#define GPIO_PD1_U1DCD          0x00030409
+#define GPIO_PD1_CCP2           0x0003040A
+#define GPIO_PD1_PHB1           0x0003040B
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_PWM2           0x00030803
+#define GPIO_PD2_CCP5           0x00030804
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_PWM3           0x00030C03
+#define GPIO_PD3_CCP0           0x00030C04
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+#define GPIO_PD4_I2S0RXSD       0x00031008
+#define GPIO_PD4_U1RI           0x00031009
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_I2S0RXMCLK     0x00031408
+#define GPIO_PD5_U2RX           0x00031409
+
+#define GPIO_PD6_FAULT0         0x00031801
+#define GPIO_PD6_I2S0TXSCK      0x00031808
+#define GPIO_PD6_U2TX           0x00031809
+
+#define GPIO_PD7_IDX0           0x00031C01
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+#define GPIO_PD7_I2S0TXWS       0x00031C08
+#define GPIO_PD7_U1DTR          0x00031C09
+
+#define GPIO_PE0_PWM4           0x00040001
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+#define GPIO_PE0_USB0PFLT       0x00040009
+
+#define GPIO_PE1_PWM5           0x00040401
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_FAULT0         0x00040403
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_PHB1           0x00040803
+#define GPIO_PE2_PHA0           0x00040804
+#define GPIO_PE2_CCP2           0x00040805
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_PHA1           0x00040C03
+#define GPIO_PE3_PHB0           0x00040C04
+#define GPIO_PE3_CCP7           0x00040C05
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_FAULT0         0x00041004
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+#define GPIO_PE4_I2S0TXWS       0x00041009
+
+#define GPIO_PE5_CCP5           0x00041401
+#define GPIO_PE5_I2S0TXSD       0x00041409
+
+#define GPIO_PE6_PWM4           0x00041801
+#define GPIO_PE6_C1O            0x00041802
+#define GPIO_PE6_U1CTS          0x00041809
+
+#define GPIO_PE7_PWM5           0x00041C01
+#define GPIO_PE7_U1DCD          0x00041C09
+
+#define GPIO_PF0_CAN1RX         0x00050001
+#define GPIO_PF0_PHB0           0x00050002
+#define GPIO_PF0_PWM0           0x00050003
+#define GPIO_PF0_I2S0TXSD       0x00050008
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_CAN1TX         0x00050401
+#define GPIO_PF1_IDX1           0x00050402
+#define GPIO_PF1_PWM1           0x00050403
+#define GPIO_PF1_I2S0TXMCLK     0x00050408
+#define GPIO_PF1_U1RTS          0x00050409
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_PWM4           0x00050802
+#define GPIO_PF2_PWM2           0x00050804
+#define GPIO_PF2_SSI1CLK        0x00050809
+
+#define GPIO_PF3_PWM5           0x00050C02
+#define GPIO_PF3_PWM3           0x00050C04
+#define GPIO_PF3_SSI1FSS        0x00050C09
+
+#define GPIO_PF4_CCP0           0x00051001
+#define GPIO_PF4_C0O            0x00051002
+#define GPIO_PF4_FAULT0         0x00051004
+#define GPIO_PF4_SSI1RX         0x00051009
+
+#define GPIO_PF5_CCP2           0x00051401
+#define GPIO_PF5_C1O            0x00051402
+#define GPIO_PF5_SSI1TX         0x00051409
+
+#define GPIO_PF6_CCP1           0x00051801
+#define GPIO_PF6_PHA0           0x00051804
+#define GPIO_PF6_I2S0TXMCLK     0x00051809
+#define GPIO_PF6_U1RTS          0x0005180A
+
+#define GPIO_PF7_CCP4           0x00051C01
+#define GPIO_PF7_PHB0           0x00051C04
+#define GPIO_PF7_FAULT1         0x00051C09
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_PWM0           0x00060002
+#define GPIO_PG0_I2C1SCL        0x00060003
+#define GPIO_PG0_PWM4           0x00060004
+#define GPIO_PG0_USB0EPEN       0x00060007
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_PWM1           0x00060402
+#define GPIO_PG1_I2C1SDA        0x00060403
+#define GPIO_PG1_PWM5           0x00060404
+
+#define GPIO_PG2_PWM0           0x00060801
+#define GPIO_PG2_FAULT0         0x00060804
+#define GPIO_PG2_IDX1           0x00060808
+#define GPIO_PG2_I2S0RXSD       0x00060809
+
+#define GPIO_PG3_PWM1           0x00060C01
+#define GPIO_PG3_FAULT2         0x00060C04
+#define GPIO_PG3_FAULT0         0x00060C08
+#define GPIO_PG3_I2S0RXMCLK     0x00060C09
+
+#define GPIO_PG4_CCP3           0x00061001
+#define GPIO_PG4_FAULT1         0x00061004
+#define GPIO_PG4_U1RI           0x0006100A
+
+#define GPIO_PG5_CCP5           0x00061401
+#define GPIO_PG5_IDX0           0x00061404
+#define GPIO_PG5_FAULT1         0x00061405
+#define GPIO_PG5_I2S0RXSCK      0x00061409
+#define GPIO_PG5_U1DTR          0x0006140A
+
+#define GPIO_PG6_PHA1           0x00061801
+#define GPIO_PG6_FAULT1         0x00061808
+#define GPIO_PG6_I2S0RXWS       0x00061809
+#define GPIO_PG6_U1RI           0x0006180A
+
+#define GPIO_PG7_PHB1           0x00061C01
+#define GPIO_PG7_CCP5           0x00061C08
+
+#define GPIO_PH0_CCP6           0x00070001
+#define GPIO_PH0_PWM2           0x00070002
+#define GPIO_PH0_PWM4           0x00070009
+
+#define GPIO_PH1_CCP7           0x00070401
+#define GPIO_PH1_PWM3           0x00070402
+#define GPIO_PH1_PWM5           0x00070409
+
+#define GPIO_PH2_IDX1           0x00070801
+#define GPIO_PH2_C1O            0x00070802
+#define GPIO_PH2_FAULT3         0x00070804
+
+#define GPIO_PH3_PHB0           0x00070C01
+#define GPIO_PH3_FAULT0         0x00070C02
+#define GPIO_PH3_USB0EPEN       0x00070C04
+
+#define GPIO_PH4_USB0PFLT       0x00071004
+#define GPIO_PH4_SSI1CLK        0x0007100B
+
+#define GPIO_PH5_FAULT2         0x0007140A
+#define GPIO_PH5_SSI1FSS        0x0007140B
+
+#define GPIO_PH6_PWM4           0x0007180A
+#define GPIO_PH6_SSI1RX         0x0007180B
+
+#define GPIO_PH7_PWM5           0x00071C0A
+#define GPIO_PH7_SSI1TX         0x00071C0B
+
+#define GPIO_PJ0_PWM0           0x0008000A
+#define GPIO_PJ0_I2C1SCL        0x0008000B
+
+#define GPIO_PJ1_USB0PFLT       0x00080409
+#define GPIO_PJ1_PWM1           0x0008040A
+#define GPIO_PJ1_I2C1SDA        0x0008040B
+
+#define GPIO_PJ2_CCP0           0x00080809
+#define GPIO_PJ2_FAULT0         0x0008080A
+
+#endif // PART_LM3S5G51
+
+//*****************************************************************************
+//
+// LM3S5G56 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S5G56
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_PWM4           0x00000804
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_PWM5           0x00000C04
+
+#define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_CAN0RX         0x00001005
+
+#define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_CAN0TX         0x00001405
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_PWM0           0x00001804
+#define GPIO_PA6_PWM4           0x00001805
+#define GPIO_PA6_CAN0RX         0x00001806
+#define GPIO_PA6_USB0EPEN       0x00001808
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_PWM1           0x00001C04
+#define GPIO_PA7_PWM5           0x00001C05
+#define GPIO_PA7_CAN0TX         0x00001C06
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_USB0PFLT       0x00001C08
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_PWM2           0x00010002
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_PWM3           0x00010402
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_IDX0           0x00010802
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+#define GPIO_PB2_USB0EPEN       0x00010808
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_FAULT0         0x00010C02
+#define GPIO_PB3_FAULT3         0x00010C04
+#define GPIO_PB3_USB0PFLT       0x00010C08
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_CAN0RX         0x00011005
+#define GPIO_PB4_IDX0           0x00011006
+#define GPIO_PB4_U1RX           0x00011007
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CAN0TX         0x00011405
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_FAULT1         0x00011804
+#define GPIO_PB6_IDX0           0x00011805
+#define GPIO_PB6_CCP5           0x00011806
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_PHA0           0x00021002
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_FAULT2         0x00021404
+#define GPIO_PC5_CCP3           0x00021405
+#define GPIO_PC5_USB0EPEN       0x00021406
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_PHB0           0x00021802
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+#define GPIO_PC6_USB0PFLT       0x00021807
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_PHB0           0x00021C02
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_USB0PFLT       0x00021C06
+#define GPIO_PC7_C1O            0x00021C07
+
+#define GPIO_PD0_PWM0           0x00030001
+#define GPIO_PD0_CAN0RX         0x00030002
+#define GPIO_PD0_IDX0           0x00030003
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+
+#define GPIO_PD1_PWM1           0x00030401
+#define GPIO_PD1_CAN0TX         0x00030402
+#define GPIO_PD1_PHA0           0x00030403
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_CCP2           0x0003040A
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_PWM2           0x00030803
+#define GPIO_PD2_CCP5           0x00030804
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_PWM3           0x00030C03
+#define GPIO_PD3_CCP0           0x00030C04
+
+#define GPIO_PE0_PWM4           0x00040001
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+#define GPIO_PE0_USB0PFLT       0x00040009
+
+#define GPIO_PE1_PWM5           0x00040401
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_FAULT0         0x00040403
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_PHA0           0x00040804
+#define GPIO_PE2_CCP2           0x00040805
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_PHB0           0x00040C04
+#define GPIO_PE3_CCP7           0x00040C05
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_FAULT0         0x00041004
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+
+#endif // PART_LM3S5G56
+
+//*****************************************************************************
+//
+// LM3S5K31 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S5K31
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_PWM4           0x00000804
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_PWM5           0x00000C04
+
+#define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_CAN0RX         0x00001005
+
+#define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_CAN0TX         0x00001405
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_PWM0           0x00001804
+#define GPIO_PA6_PWM4           0x00001805
+#define GPIO_PA6_CAN0RX         0x00001806
+#define GPIO_PA6_U1CTS          0x00001809
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_PWM1           0x00001C04
+#define GPIO_PA7_PWM5           0x00001C05
+#define GPIO_PA7_CAN0TX         0x00001C06
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_U1DCD          0x00001C09
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_PWM2           0x00010002
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_PWM3           0x00010402
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_IDX0           0x00010802
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_FAULT0         0x00010C02
+#define GPIO_PB3_FAULT3         0x00010C04
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_CAN0RX         0x00011005
+#define GPIO_PB4_IDX0           0x00011006
+#define GPIO_PB4_U1RX           0x00011007
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CAN0TX         0x00011405
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_FAULT1         0x00011804
+#define GPIO_PB6_IDX0           0x00011805
+#define GPIO_PB6_CCP5           0x00011806
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_PHA0           0x00021002
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_FAULT2         0x00021404
+#define GPIO_PC5_CCP3           0x00021405
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_PHB0           0x00021802
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_PHB0           0x00021C02
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_C1O            0x00021C07
+
+#define GPIO_PD0_PWM0           0x00030001
+#define GPIO_PD0_CAN0RX         0x00030002
+#define GPIO_PD0_IDX0           0x00030003
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_U1CTS          0x00030009
+
+#define GPIO_PD1_PWM1           0x00030401
+#define GPIO_PD1_CAN0TX         0x00030402
+#define GPIO_PD1_PHA0           0x00030403
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_U1DCD          0x00030409
+#define GPIO_PD1_CCP2           0x0003040A
+#define GPIO_PD1_PHB1           0x0003040B
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_PWM2           0x00030803
+#define GPIO_PD2_CCP5           0x00030804
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_PWM3           0x00030C03
+#define GPIO_PD3_CCP0           0x00030C04
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+#define GPIO_PD4_U1RI           0x00031009
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_U2RX           0x00031409
+
+#define GPIO_PD6_FAULT0         0x00031801
+#define GPIO_PD6_U2TX           0x00031809
+
+#define GPIO_PD7_IDX0           0x00031C01
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+#define GPIO_PD7_U1DTR          0x00031C09
+
+#define GPIO_PE0_PWM4           0x00040001
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+
+#define GPIO_PE1_PWM5           0x00040401
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_FAULT0         0x00040403
+#define GPIO_PE1_CCP2           0x00040404
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_PHB1           0x00040803
+#define GPIO_PE2_PHA0           0x00040804
+#define GPIO_PE2_CCP2           0x00040805
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_PHA1           0x00040C03
+#define GPIO_PE3_PHB0           0x00040C04
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_FAULT0         0x00041004
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+
+#define GPIO_PE5_CCP5           0x00041401
+
+#define GPIO_PE6_PWM4           0x00041801
+#define GPIO_PE6_C1O            0x00041802
+#define GPIO_PE6_U1CTS          0x00041809
+
+#define GPIO_PE7_PWM5           0x00041C01
+#define GPIO_PE7_U1DCD          0x00041C09
+
+#define GPIO_PF0_PHB0           0x00050002
+#define GPIO_PF0_PWM0           0x00050003
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_IDX1           0x00050402
+#define GPIO_PF1_PWM1           0x00050403
+#define GPIO_PF1_U1RTS          0x00050409
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_PWM4           0x00050802
+#define GPIO_PF2_PWM2           0x00050804
+#define GPIO_PF2_SSI1CLK        0x00050809
+
+#define GPIO_PF3_PWM5           0x00050C02
+#define GPIO_PF3_PWM3           0x00050C04
+#define GPIO_PF3_SSI1FSS        0x00050C09
+
+#define GPIO_PF4_CCP0           0x00051001
+#define GPIO_PF4_C0O            0x00051002
+#define GPIO_PF4_FAULT0         0x00051004
+#define GPIO_PF4_SSI1RX         0x00051009
+
+#define GPIO_PF5_CCP2           0x00051401
+#define GPIO_PF5_C1O            0x00051402
+#define GPIO_PF5_SSI1TX         0x00051409
+
+#define GPIO_PF6_CCP1           0x00051801
+#define GPIO_PF6_PHA0           0x00051804
+#define GPIO_PF6_U1RTS          0x0005180A
+
+#define GPIO_PF7_CCP4           0x00051C01
+#define GPIO_PF7_PHB0           0x00051C04
+#define GPIO_PF7_FAULT1         0x00051C09
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_PWM0           0x00060002
+#define GPIO_PG0_I2C1SCL        0x00060003
+#define GPIO_PG0_PWM4           0x00060004
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_PWM1           0x00060402
+#define GPIO_PG1_I2C1SDA        0x00060403
+#define GPIO_PG1_PWM5           0x00060404
+
+#define GPIO_PG2_PWM0           0x00060801
+#define GPIO_PG2_FAULT0         0x00060804
+#define GPIO_PG2_IDX1           0x00060808
+
+#define GPIO_PG3_PWM1           0x00060C01
+#define GPIO_PG3_FAULT2         0x00060C04
+#define GPIO_PG3_FAULT0         0x00060C08
+
+#define GPIO_PG4_CCP3           0x00061001
+#define GPIO_PG4_FAULT1         0x00061004
+#define GPIO_PG4_U1RI           0x0006100A
+
+#define GPIO_PG5_CCP5           0x00061401
+#define GPIO_PG5_IDX0           0x00061404
+#define GPIO_PG5_FAULT1         0x00061405
+#define GPIO_PG5_U1DTR          0x0006140A
+
+#define GPIO_PG6_PHA1           0x00061801
+#define GPIO_PG6_FAULT1         0x00061808
+#define GPIO_PG6_U1RI           0x0006180A
+
+#define GPIO_PG7_PHB1           0x00061C01
+#define GPIO_PG7_CCP5           0x00061C08
+
+#define GPIO_PH0_PWM2           0x00070002
+#define GPIO_PH0_PWM4           0x00070009
+
+#define GPIO_PH1_PWM3           0x00070402
+#define GPIO_PH1_PWM5           0x00070409
+
+#define GPIO_PH2_IDX1           0x00070801
+#define GPIO_PH2_C1O            0x00070802
+#define GPIO_PH2_FAULT3         0x00070804
+
+#define GPIO_PH3_PHB0           0x00070C01
+#define GPIO_PH3_FAULT0         0x00070C02
+
+#define GPIO_PH4_SSI1CLK        0x0007100B
+
+#define GPIO_PH5_FAULT2         0x0007140A
+#define GPIO_PH5_SSI1FSS        0x0007140B
+
+#define GPIO_PH6_PWM4           0x0007180A
+#define GPIO_PH6_SSI1RX         0x0007180B
+
+#define GPIO_PH7_PWM5           0x00071C0A
+#define GPIO_PH7_SSI1TX         0x00071C0B
+
+#define GPIO_PJ0_PWM0           0x0008000A
+#define GPIO_PJ0_I2C1SCL        0x0008000B
+
+#define GPIO_PJ1_PWM1           0x0008040A
+#define GPIO_PJ1_I2C1SDA        0x0008040B
+
+#define GPIO_PJ2_CCP0           0x00080809
+#define GPIO_PJ2_FAULT0         0x0008080A
+
+#endif // PART_LM3S5K31
+
+//*****************************************************************************
+//
+// LM3S5K36 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S5K36
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_PWM4           0x00000804
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_PWM5           0x00000C04
+
+#define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_CAN0RX         0x00001005
+
+#define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_CAN0TX         0x00001405
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_PWM0           0x00001804
+#define GPIO_PA6_PWM4           0x00001805
+#define GPIO_PA6_CAN0RX         0x00001806
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_PWM1           0x00001C04
+#define GPIO_PA7_PWM5           0x00001C05
+#define GPIO_PA7_CAN0TX         0x00001C06
+#define GPIO_PA7_CCP3           0x00001C07
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_PWM2           0x00010002
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_PWM3           0x00010402
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_IDX0           0x00010802
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_FAULT0         0x00010C02
+#define GPIO_PB3_FAULT3         0x00010C04
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_CAN0RX         0x00011005
+#define GPIO_PB4_IDX0           0x00011006
+#define GPIO_PB4_U1RX           0x00011007
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CAN0TX         0x00011405
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_FAULT1         0x00011804
+#define GPIO_PB6_IDX0           0x00011805
+#define GPIO_PB6_CCP5           0x00011806
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_PHA0           0x00021002
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_FAULT2         0x00021404
+#define GPIO_PC5_CCP3           0x00021405
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_PHB0           0x00021802
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_PHB0           0x00021C02
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_C1O            0x00021C07
+
+#define GPIO_PD0_PWM0           0x00030001
+#define GPIO_PD0_CAN0RX         0x00030002
+#define GPIO_PD0_IDX0           0x00030003
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+
+#define GPIO_PD1_PWM1           0x00030401
+#define GPIO_PD1_CAN0TX         0x00030402
+#define GPIO_PD1_PHA0           0x00030403
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP2           0x0003040A
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_PWM2           0x00030803
+#define GPIO_PD2_CCP5           0x00030804
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_PWM3           0x00030C03
+#define GPIO_PD3_CCP0           0x00030C04
+
+#define GPIO_PE0_PWM4           0x00040001
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+
+#define GPIO_PE1_PWM5           0x00040401
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_FAULT0         0x00040403
+#define GPIO_PE1_CCP2           0x00040404
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_PHA0           0x00040804
+#define GPIO_PE2_CCP2           0x00040805
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_PHB0           0x00040C04
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_FAULT0         0x00041004
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+
+#endif // PART_LM3S5K36
+
+//*****************************************************************************
+//
+// LM3S5P31 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S5P31
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_PWM4           0x00000804
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_PWM5           0x00000C04
+
+#define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_CAN0RX         0x00001005
+
+#define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_CAN0TX         0x00001405
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_PWM0           0x00001804
+#define GPIO_PA6_PWM4           0x00001805
+#define GPIO_PA6_CAN0RX         0x00001806
+#define GPIO_PA6_U1CTS          0x00001809
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_PWM1           0x00001C04
+#define GPIO_PA7_PWM5           0x00001C05
+#define GPIO_PA7_CAN0TX         0x00001C06
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_U1DCD          0x00001C09
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_PWM2           0x00010002
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_PWM3           0x00010402
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_IDX0           0x00010802
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_FAULT0         0x00010C02
+#define GPIO_PB3_FAULT3         0x00010C04
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_CAN0RX         0x00011005
+#define GPIO_PB4_IDX0           0x00011006
+#define GPIO_PB4_U1RX           0x00011007
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CAN0TX         0x00011405
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_FAULT1         0x00011804
+#define GPIO_PB6_IDX0           0x00011805
+#define GPIO_PB6_CCP5           0x00011806
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_PHA0           0x00021002
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_FAULT2         0x00021404
+#define GPIO_PC5_CCP3           0x00021405
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_PHB0           0x00021802
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_PHB0           0x00021C02
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_C1O            0x00021C07
+
+#define GPIO_PD0_PWM0           0x00030001
+#define GPIO_PD0_CAN0RX         0x00030002
+#define GPIO_PD0_IDX0           0x00030003
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_U1CTS          0x00030009
+
+#define GPIO_PD1_PWM1           0x00030401
+#define GPIO_PD1_CAN0TX         0x00030402
+#define GPIO_PD1_PHA0           0x00030403
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_U1DCD          0x00030409
+#define GPIO_PD1_CCP2           0x0003040A
+#define GPIO_PD1_PHB1           0x0003040B
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_PWM2           0x00030803
+#define GPIO_PD2_CCP5           0x00030804
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_PWM3           0x00030C03
+#define GPIO_PD3_CCP0           0x00030C04
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+#define GPIO_PD4_U1RI           0x00031009
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_U2RX           0x00031409
+
+#define GPIO_PD6_FAULT0         0x00031801
+#define GPIO_PD6_U2TX           0x00031809
+
+#define GPIO_PD7_IDX0           0x00031C01
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+#define GPIO_PD7_U1DTR          0x00031C09
+
+#define GPIO_PE0_PWM4           0x00040001
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+
+#define GPIO_PE1_PWM5           0x00040401
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_FAULT0         0x00040403
+#define GPIO_PE1_CCP2           0x00040404
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_PHB1           0x00040803
+#define GPIO_PE2_PHA0           0x00040804
+#define GPIO_PE2_CCP2           0x00040805
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_PHA1           0x00040C03
+#define GPIO_PE3_PHB0           0x00040C04
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_FAULT0         0x00041004
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+
+#define GPIO_PE5_CCP5           0x00041401
+
+#define GPIO_PE6_PWM4           0x00041801
+#define GPIO_PE6_C1O            0x00041802
+#define GPIO_PE6_U1CTS          0x00041809
+
+#define GPIO_PE7_PWM5           0x00041C01
+#define GPIO_PE7_U1DCD          0x00041C09
+
+#define GPIO_PF0_PHB0           0x00050002
+#define GPIO_PF0_PWM0           0x00050003
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_IDX1           0x00050402
+#define GPIO_PF1_PWM1           0x00050403
+#define GPIO_PF1_U1RTS          0x00050409
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_PWM4           0x00050802
+#define GPIO_PF2_PWM2           0x00050804
+#define GPIO_PF2_SSI1CLK        0x00050809
+
+#define GPIO_PF3_PWM5           0x00050C02
+#define GPIO_PF3_PWM3           0x00050C04
+#define GPIO_PF3_SSI1FSS        0x00050C09
+
+#define GPIO_PF4_CCP0           0x00051001
+#define GPIO_PF4_C0O            0x00051002
+#define GPIO_PF4_FAULT0         0x00051004
+#define GPIO_PF4_SSI1RX         0x00051009
+
+#define GPIO_PF5_CCP2           0x00051401
+#define GPIO_PF5_C1O            0x00051402
+#define GPIO_PF5_SSI1TX         0x00051409
+
+#define GPIO_PF6_CCP1           0x00051801
+#define GPIO_PF6_PHA0           0x00051804
+#define GPIO_PF6_U1RTS          0x0005180A
+
+#define GPIO_PF7_CCP4           0x00051C01
+#define GPIO_PF7_PHB0           0x00051C04
+#define GPIO_PF7_FAULT1         0x00051C09
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_PWM0           0x00060002
+#define GPIO_PG0_I2C1SCL        0x00060003
+#define GPIO_PG0_PWM4           0x00060004
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_PWM1           0x00060402
+#define GPIO_PG1_I2C1SDA        0x00060403
+#define GPIO_PG1_PWM5           0x00060404
+
+#define GPIO_PG2_PWM0           0x00060801
+#define GPIO_PG2_FAULT0         0x00060804
+#define GPIO_PG2_IDX1           0x00060808
+
+#define GPIO_PG3_PWM1           0x00060C01
+#define GPIO_PG3_FAULT2         0x00060C04
+#define GPIO_PG3_FAULT0         0x00060C08
+
+#define GPIO_PG4_CCP3           0x00061001
+#define GPIO_PG4_FAULT1         0x00061004
+#define GPIO_PG4_U1RI           0x0006100A
+
+#define GPIO_PG5_CCP5           0x00061401
+#define GPIO_PG5_IDX0           0x00061404
+#define GPIO_PG5_FAULT1         0x00061405
+#define GPIO_PG5_U1DTR          0x0006140A
+
+#define GPIO_PG6_PHA1           0x00061801
+#define GPIO_PG6_FAULT1         0x00061808
+#define GPIO_PG6_U1RI           0x0006180A
+
+#define GPIO_PG7_PHB1           0x00061C01
+#define GPIO_PG7_CCP5           0x00061C08
+
+#define GPIO_PH0_PWM2           0x00070002
+#define GPIO_PH0_PWM4           0x00070009
+
+#define GPIO_PH1_PWM3           0x00070402
+#define GPIO_PH1_PWM5           0x00070409
+
+#define GPIO_PH2_IDX1           0x00070801
+#define GPIO_PH2_C1O            0x00070802
+#define GPIO_PH2_FAULT3         0x00070804
+
+#define GPIO_PH3_PHB0           0x00070C01
+#define GPIO_PH3_FAULT0         0x00070C02
+
+#define GPIO_PH4_SSI1CLK        0x0007100B
+
+#define GPIO_PH5_FAULT2         0x0007140A
+#define GPIO_PH5_SSI1FSS        0x0007140B
+
+#define GPIO_PH6_PWM4           0x0007180A
+#define GPIO_PH6_SSI1RX         0x0007180B
+
+#define GPIO_PH7_PWM5           0x00071C0A
+#define GPIO_PH7_SSI1TX         0x00071C0B
+
+#define GPIO_PJ0_PWM0           0x0008000A
+#define GPIO_PJ0_I2C1SCL        0x0008000B
+
+#define GPIO_PJ1_PWM1           0x0008040A
+#define GPIO_PJ1_I2C1SDA        0x0008040B
+
+#define GPIO_PJ2_CCP0           0x00080809
+#define GPIO_PJ2_FAULT0         0x0008080A
+
+#endif // PART_LM3S5P31
+
+//*****************************************************************************
+//
+// LM3S5P36 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S5P36
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_PWM4           0x00000804
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_PWM5           0x00000C04
+
+#define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_CAN0RX         0x00001005
+
+#define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_CAN0TX         0x00001405
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_PWM0           0x00001804
+#define GPIO_PA6_PWM4           0x00001805
+#define GPIO_PA6_CAN0RX         0x00001806
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_PWM1           0x00001C04
+#define GPIO_PA7_PWM5           0x00001C05
+#define GPIO_PA7_CAN0TX         0x00001C06
+#define GPIO_PA7_CCP3           0x00001C07
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_PWM2           0x00010002
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_PWM3           0x00010402
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_IDX0           0x00010802
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_FAULT0         0x00010C02
+#define GPIO_PB3_FAULT3         0x00010C04
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_CAN0RX         0x00011005
+#define GPIO_PB4_IDX0           0x00011006
+#define GPIO_PB4_U1RX           0x00011007
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CAN0TX         0x00011405
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_FAULT1         0x00011804
+#define GPIO_PB6_IDX0           0x00011805
+#define GPIO_PB6_CCP5           0x00011806
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_PHA0           0x00021002
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_FAULT2         0x00021404
+#define GPIO_PC5_CCP3           0x00021405
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_PHB0           0x00021802
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_PHB0           0x00021C02
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_C1O            0x00021C07
+
+#define GPIO_PD0_PWM0           0x00030001
+#define GPIO_PD0_CAN0RX         0x00030002
+#define GPIO_PD0_IDX0           0x00030003
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+
+#define GPIO_PD1_PWM1           0x00030401
+#define GPIO_PD1_CAN0TX         0x00030402
+#define GPIO_PD1_PHA0           0x00030403
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP2           0x0003040A
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_PWM2           0x00030803
+#define GPIO_PD2_CCP5           0x00030804
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_PWM3           0x00030C03
+#define GPIO_PD3_CCP0           0x00030C04
+
+#define GPIO_PE0_PWM4           0x00040001
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+
+#define GPIO_PE1_PWM5           0x00040401
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_FAULT0         0x00040403
+#define GPIO_PE1_CCP2           0x00040404
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_PHA0           0x00040804
+#define GPIO_PE2_CCP2           0x00040805
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_PHB0           0x00040C04
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_FAULT0         0x00041004
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+
+#endif // PART_LM3S5P36
+
+//*****************************************************************************
+//
+// LM3S5P3B Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S5P3B
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_PWM4           0x00000804
+#define GPIO_PA2_I2S0RXSD       0x00000809
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_PWM5           0x00000C04
+#define GPIO_PA3_I2S0RXMCLK     0x00000C09
+
+#define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_CAN0RX         0x00001005
+#define GPIO_PA4_I2S0TXSCK      0x00001009
+
+#define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_CAN0TX         0x00001405
+#define GPIO_PA5_I2S0TXWS       0x00001409
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_PWM0           0x00001804
+#define GPIO_PA6_PWM4           0x00001805
+#define GPIO_PA6_CAN0RX         0x00001806
+#define GPIO_PA6_U1CTS          0x00001809
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_PWM1           0x00001C04
+#define GPIO_PA7_PWM5           0x00001C05
+#define GPIO_PA7_CAN0TX         0x00001C06
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_U1DCD          0x00001C09
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_PWM2           0x00010002
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_PWM3           0x00010402
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_IDX0           0x00010802
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_FAULT0         0x00010C02
+#define GPIO_PB3_FAULT3         0x00010C04
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_CAN0RX         0x00011005
+#define GPIO_PB4_IDX0           0x00011006
+#define GPIO_PB4_U1RX           0x00011007
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CAN0TX         0x00011405
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_FAULT1         0x00011804
+#define GPIO_PB6_IDX0           0x00011805
+#define GPIO_PB6_CCP5           0x00011806
+#define GPIO_PB6_I2S0TXSCK      0x00011809
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_PHA0           0x00021002
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_FAULT2         0x00021404
+#define GPIO_PC5_CCP3           0x00021405
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_PHB0           0x00021802
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_PHB0           0x00021C02
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_C1O            0x00021C07
+
+#define GPIO_PD0_PWM0           0x00030001
+#define GPIO_PD0_CAN0RX         0x00030002
+#define GPIO_PD0_IDX0           0x00030003
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_I2S0RXSCK      0x00030008
+#define GPIO_PD0_U1CTS          0x00030009
+
+#define GPIO_PD1_PWM1           0x00030401
+#define GPIO_PD1_CAN0TX         0x00030402
+#define GPIO_PD1_PHA0           0x00030403
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_I2S0RXWS       0x00030408
+#define GPIO_PD1_U1DCD          0x00030409
+#define GPIO_PD1_CCP2           0x0003040A
+#define GPIO_PD1_PHB1           0x0003040B
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_PWM2           0x00030803
+#define GPIO_PD2_CCP5           0x00030804
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_PWM3           0x00030C03
+#define GPIO_PD3_CCP0           0x00030C04
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+#define GPIO_PD4_I2S0RXSD       0x00031008
+#define GPIO_PD4_U1RI           0x00031009
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_I2S0RXMCLK     0x00031408
+#define GPIO_PD5_U2RX           0x00031409
+
+#define GPIO_PD6_FAULT0         0x00031801
+#define GPIO_PD6_I2S0TXSCK      0x00031808
+#define GPIO_PD6_U2TX           0x00031809
+
+#define GPIO_PD7_IDX0           0x00031C01
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+#define GPIO_PD7_I2S0TXWS       0x00031C08
+#define GPIO_PD7_U1DTR          0x00031C09
+
+#define GPIO_PE0_PWM4           0x00040001
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+
+#define GPIO_PE1_PWM5           0x00040401
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_FAULT0         0x00040403
+#define GPIO_PE1_CCP2           0x00040404
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_PHB1           0x00040803
+#define GPIO_PE2_PHA0           0x00040804
+#define GPIO_PE2_CCP2           0x00040805
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_PHA1           0x00040C03
+#define GPIO_PE3_PHB0           0x00040C04
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_FAULT0         0x00041004
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+#define GPIO_PE4_I2S0TXWS       0x00041009
+
+#define GPIO_PE5_CCP5           0x00041401
+#define GPIO_PE5_I2S0TXSD       0x00041409
+
+#define GPIO_PE6_PWM4           0x00041801
+#define GPIO_PE6_C1O            0x00041802
+#define GPIO_PE6_U1CTS          0x00041809
+
+#define GPIO_PE7_PWM5           0x00041C01
+#define GPIO_PE7_U1DCD          0x00041C09
+
+#define GPIO_PF0_PHB0           0x00050002
+#define GPIO_PF0_PWM0           0x00050003
+#define GPIO_PF0_I2S0TXSD       0x00050008
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_IDX1           0x00050402
+#define GPIO_PF1_PWM1           0x00050403
+#define GPIO_PF1_I2S0TXMCLK     0x00050408
+#define GPIO_PF1_U1RTS          0x00050409
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_PWM4           0x00050802
+#define GPIO_PF2_PWM2           0x00050804
+#define GPIO_PF2_SSI1CLK        0x00050809
+
+#define GPIO_PF3_PWM5           0x00050C02
+#define GPIO_PF3_PWM3           0x00050C04
+#define GPIO_PF3_SSI1FSS        0x00050C09
+
+#define GPIO_PF4_CCP0           0x00051001
+#define GPIO_PF4_C0O            0x00051002
+#define GPIO_PF4_FAULT0         0x00051004
+#define GPIO_PF4_SSI1RX         0x00051009
+
+#define GPIO_PF5_CCP2           0x00051401
+#define GPIO_PF5_C1O            0x00051402
+#define GPIO_PF5_SSI1TX         0x00051409
+
+#define GPIO_PF6_CCP1           0x00051801
+#define GPIO_PF6_PHA0           0x00051804
+#define GPIO_PF6_I2S0TXMCLK     0x00051809
+#define GPIO_PF6_U1RTS          0x0005180A
+
+#define GPIO_PF7_CCP4           0x00051C01
+#define GPIO_PF7_PHB0           0x00051C04
+#define GPIO_PF7_FAULT1         0x00051C09
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_PWM0           0x00060002
+#define GPIO_PG0_I2C1SCL        0x00060003
+#define GPIO_PG0_PWM4           0x00060004
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_PWM1           0x00060402
+#define GPIO_PG1_I2C1SDA        0x00060403
+#define GPIO_PG1_PWM5           0x00060404
+
+#define GPIO_PG2_PWM0           0x00060801
+#define GPIO_PG2_FAULT0         0x00060804
+#define GPIO_PG2_IDX1           0x00060808
+#define GPIO_PG2_I2S0RXSD       0x00060809
+
+#define GPIO_PG3_PWM1           0x00060C01
+#define GPIO_PG3_FAULT2         0x00060C04
+#define GPIO_PG3_FAULT0         0x00060C08
+#define GPIO_PG3_I2S0RXMCLK     0x00060C09
+
+#define GPIO_PG4_CCP3           0x00061001
+#define GPIO_PG4_FAULT1         0x00061004
+#define GPIO_PG4_U1RI           0x0006100A
+
+#define GPIO_PG5_CCP5           0x00061401
+#define GPIO_PG5_IDX0           0x00061404
+#define GPIO_PG5_FAULT1         0x00061405
+#define GPIO_PG5_I2S0RXSCK      0x00061409
+#define GPIO_PG5_U1DTR          0x0006140A
+
+#define GPIO_PG6_PHA1           0x00061801
+#define GPIO_PG6_FAULT1         0x00061808
+#define GPIO_PG6_I2S0RXWS       0x00061809
+#define GPIO_PG6_U1RI           0x0006180A
+
+#define GPIO_PG7_PHB1           0x00061C01
+#define GPIO_PG7_CCP5           0x00061C08
+
+#define GPIO_PH0_PWM2           0x00070002
+#define GPIO_PH0_PWM4           0x00070009
+
+#define GPIO_PH1_PWM3           0x00070402
+#define GPIO_PH1_PWM5           0x00070409
+
+#define GPIO_PH2_IDX1           0x00070801
+#define GPIO_PH2_C1O            0x00070802
+#define GPIO_PH2_FAULT3         0x00070804
+
+#define GPIO_PH3_PHB0           0x00070C01
+#define GPIO_PH3_FAULT0         0x00070C02
+
+#define GPIO_PH4_SSI1CLK        0x0007100B
+
+#define GPIO_PH5_FAULT2         0x0007140A
+#define GPIO_PH5_SSI1FSS        0x0007140B
+
+#define GPIO_PH6_PWM4           0x0007180A
+#define GPIO_PH6_SSI1RX         0x0007180B
+
+#define GPIO_PH7_PWM5           0x00071C0A
+#define GPIO_PH7_SSI1TX         0x00071C0B
+
+#define GPIO_PJ0_PWM0           0x0008000A
+#define GPIO_PJ0_I2C1SCL        0x0008000B
+
+#define GPIO_PJ1_PWM1           0x0008040A
+#define GPIO_PJ1_I2C1SDA        0x0008040B
+
+#define GPIO_PJ2_CCP0           0x00080809
+#define GPIO_PJ2_FAULT0         0x0008080A
+
+#endif // PART_LM3S5P3B
+
+//*****************************************************************************
+//
+// LM3S5P51 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S5P51
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_PWM4           0x00000804
+#define GPIO_PA2_I2S0RXSD       0x00000809
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_PWM5           0x00000C04
+#define GPIO_PA3_I2S0RXMCLK     0x00000C09
+
+#define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_CAN0RX         0x00001005
+#define GPIO_PA4_I2S0TXSCK      0x00001009
+
+#define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_CAN0TX         0x00001405
+#define GPIO_PA5_I2S0TXWS       0x00001409
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_PWM0           0x00001804
+#define GPIO_PA6_PWM4           0x00001805
+#define GPIO_PA6_CAN0RX         0x00001806
+#define GPIO_PA6_USB0EPEN       0x00001808
+#define GPIO_PA6_U1CTS          0x00001809
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_PWM1           0x00001C04
+#define GPIO_PA7_PWM5           0x00001C05
+#define GPIO_PA7_CAN0TX         0x00001C06
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_USB0PFLT       0x00001C08
+#define GPIO_PA7_U1DCD          0x00001C09
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_PWM2           0x00010002
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_PWM3           0x00010402
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_IDX0           0x00010802
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+#define GPIO_PB2_USB0EPEN       0x00010808
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_FAULT0         0x00010C02
+#define GPIO_PB3_FAULT3         0x00010C04
+#define GPIO_PB3_USB0PFLT       0x00010C08
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_CAN0RX         0x00011005
+#define GPIO_PB4_IDX0           0x00011006
+#define GPIO_PB4_U1RX           0x00011007
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CAN0TX         0x00011405
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_FAULT1         0x00011804
+#define GPIO_PB6_IDX0           0x00011805
+#define GPIO_PB6_CCP5           0x00011806
+#define GPIO_PB6_I2S0TXSCK      0x00011809
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_PHA0           0x00021002
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_FAULT2         0x00021404
+#define GPIO_PC5_CCP3           0x00021405
+#define GPIO_PC5_USB0EPEN       0x00021406
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_PHB0           0x00021802
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+#define GPIO_PC6_USB0PFLT       0x00021807
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_PHB0           0x00021C02
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_USB0PFLT       0x00021C06
+#define GPIO_PC7_C1O            0x00021C07
+
+#define GPIO_PD0_PWM0           0x00030001
+#define GPIO_PD0_CAN0RX         0x00030002
+#define GPIO_PD0_IDX0           0x00030003
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+#define GPIO_PD0_I2S0RXSCK      0x00030008
+#define GPIO_PD0_U1CTS          0x00030009
+
+#define GPIO_PD1_PWM1           0x00030401
+#define GPIO_PD1_CAN0TX         0x00030402
+#define GPIO_PD1_PHA0           0x00030403
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_I2S0RXWS       0x00030408
+#define GPIO_PD1_U1DCD          0x00030409
+#define GPIO_PD1_CCP2           0x0003040A
+#define GPIO_PD1_PHB1           0x0003040B
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_PWM2           0x00030803
+#define GPIO_PD2_CCP5           0x00030804
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_PWM3           0x00030C03
+#define GPIO_PD3_CCP0           0x00030C04
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+#define GPIO_PD4_I2S0RXSD       0x00031008
+#define GPIO_PD4_U1RI           0x00031009
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_I2S0RXMCLK     0x00031408
+#define GPIO_PD5_U2RX           0x00031409
+
+#define GPIO_PD6_FAULT0         0x00031801
+#define GPIO_PD6_I2S0TXSCK      0x00031808
+#define GPIO_PD6_U2TX           0x00031809
+
+#define GPIO_PD7_IDX0           0x00031C01
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+#define GPIO_PD7_I2S0TXWS       0x00031C08
+#define GPIO_PD7_U1DTR          0x00031C09
+
+#define GPIO_PE0_PWM4           0x00040001
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+#define GPIO_PE0_USB0PFLT       0x00040009
+
+#define GPIO_PE1_PWM5           0x00040401
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_FAULT0         0x00040403
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_PHB1           0x00040803
+#define GPIO_PE2_PHA0           0x00040804
+#define GPIO_PE2_CCP2           0x00040805
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_PHA1           0x00040C03
+#define GPIO_PE3_PHB0           0x00040C04
+#define GPIO_PE3_CCP7           0x00040C05
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_FAULT0         0x00041004
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+#define GPIO_PE4_I2S0TXWS       0x00041009
+
+#define GPIO_PE5_CCP5           0x00041401
+#define GPIO_PE5_I2S0TXSD       0x00041409
+
+#define GPIO_PE6_PWM4           0x00041801
+#define GPIO_PE6_C1O            0x00041802
+#define GPIO_PE6_U1CTS          0x00041809
+
+#define GPIO_PE7_PWM5           0x00041C01
+#define GPIO_PE7_U1DCD          0x00041C09
+
+#define GPIO_PF0_CAN1RX         0x00050001
+#define GPIO_PF0_PHB0           0x00050002
+#define GPIO_PF0_PWM0           0x00050003
+#define GPIO_PF0_I2S0TXSD       0x00050008
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_CAN1TX         0x00050401
+#define GPIO_PF1_IDX1           0x00050402
+#define GPIO_PF1_PWM1           0x00050403
+#define GPIO_PF1_I2S0TXMCLK     0x00050408
+#define GPIO_PF1_U1RTS          0x00050409
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_PWM4           0x00050802
+#define GPIO_PF2_PWM2           0x00050804
+#define GPIO_PF2_SSI1CLK        0x00050809
+
+#define GPIO_PF3_PWM5           0x00050C02
+#define GPIO_PF3_PWM3           0x00050C04
+#define GPIO_PF3_SSI1FSS        0x00050C09
+
+#define GPIO_PF4_CCP0           0x00051001
+#define GPIO_PF4_C0O            0x00051002
+#define GPIO_PF4_FAULT0         0x00051004
+#define GPIO_PF4_SSI1RX         0x00051009
+
+#define GPIO_PF5_CCP2           0x00051401
+#define GPIO_PF5_C1O            0x00051402
+#define GPIO_PF5_SSI1TX         0x00051409
+
+#define GPIO_PF6_CCP1           0x00051801
+#define GPIO_PF6_PHA0           0x00051804
+#define GPIO_PF6_I2S0TXMCLK     0x00051809
+#define GPIO_PF6_U1RTS          0x0005180A
+
+#define GPIO_PF7_CCP4           0x00051C01
+#define GPIO_PF7_PHB0           0x00051C04
+#define GPIO_PF7_FAULT1         0x00051C09
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_PWM0           0x00060002
+#define GPIO_PG0_I2C1SCL        0x00060003
+#define GPIO_PG0_PWM4           0x00060004
+#define GPIO_PG0_USB0EPEN       0x00060007
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_PWM1           0x00060402
+#define GPIO_PG1_I2C1SDA        0x00060403
+#define GPIO_PG1_PWM5           0x00060404
+
+#define GPIO_PG2_PWM0           0x00060801
+#define GPIO_PG2_FAULT0         0x00060804
+#define GPIO_PG2_IDX1           0x00060808
+#define GPIO_PG2_I2S0RXSD       0x00060809
+
+#define GPIO_PG3_PWM1           0x00060C01
+#define GPIO_PG3_FAULT2         0x00060C04
+#define GPIO_PG3_FAULT0         0x00060C08
+#define GPIO_PG3_I2S0RXMCLK     0x00060C09
+
+#define GPIO_PG4_CCP3           0x00061001
+#define GPIO_PG4_FAULT1         0x00061004
+#define GPIO_PG4_U1RI           0x0006100A
+
+#define GPIO_PG5_CCP5           0x00061401
+#define GPIO_PG5_IDX0           0x00061404
+#define GPIO_PG5_FAULT1         0x00061405
+#define GPIO_PG5_I2S0RXSCK      0x00061409
+#define GPIO_PG5_U1DTR          0x0006140A
+
+#define GPIO_PG6_PHA1           0x00061801
+#define GPIO_PG6_FAULT1         0x00061808
+#define GPIO_PG6_I2S0RXWS       0x00061809
+#define GPIO_PG6_U1RI           0x0006180A
+
+#define GPIO_PG7_PHB1           0x00061C01
+#define GPIO_PG7_CCP5           0x00061C08
+
+#define GPIO_PH0_CCP6           0x00070001
+#define GPIO_PH0_PWM2           0x00070002
+#define GPIO_PH0_PWM4           0x00070009
+
+#define GPIO_PH1_CCP7           0x00070401
+#define GPIO_PH1_PWM3           0x00070402
+#define GPIO_PH1_PWM5           0x00070409
+
+#define GPIO_PH2_IDX1           0x00070801
+#define GPIO_PH2_C1O            0x00070802
+#define GPIO_PH2_FAULT3         0x00070804
+
+#define GPIO_PH3_PHB0           0x00070C01
+#define GPIO_PH3_FAULT0         0x00070C02
+#define GPIO_PH3_USB0EPEN       0x00070C04
+
+#define GPIO_PH4_USB0PFLT       0x00071004
+#define GPIO_PH4_SSI1CLK        0x0007100B
+
+#define GPIO_PH5_FAULT2         0x0007140A
+#define GPIO_PH5_SSI1FSS        0x0007140B
+
+#define GPIO_PH6_PWM4           0x0007180A
+#define GPIO_PH6_SSI1RX         0x0007180B
+
+#define GPIO_PH7_PWM5           0x00071C0A
+#define GPIO_PH7_SSI1TX         0x00071C0B
+
+#define GPIO_PJ0_PWM0           0x0008000A
+#define GPIO_PJ0_I2C1SCL        0x0008000B
+
+#define GPIO_PJ1_USB0PFLT       0x00080409
+#define GPIO_PJ1_PWM1           0x0008040A
+#define GPIO_PJ1_I2C1SDA        0x0008040B
+
+#define GPIO_PJ2_CCP0           0x00080809
+#define GPIO_PJ2_FAULT0         0x0008080A
+
+#endif // PART_LM3S5P51
+
+//*****************************************************************************
+//
+// LM3S5P56 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S5P56
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_PWM4           0x00000804
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_PWM5           0x00000C04
+
+#define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_CAN0RX         0x00001005
+
+#define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_CAN0TX         0x00001405
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_PWM0           0x00001804
+#define GPIO_PA6_PWM4           0x00001805
+#define GPIO_PA6_CAN0RX         0x00001806
+#define GPIO_PA6_USB0EPEN       0x00001808
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_PWM1           0x00001C04
+#define GPIO_PA7_PWM5           0x00001C05
+#define GPIO_PA7_CAN0TX         0x00001C06
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_USB0PFLT       0x00001C08
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_PWM2           0x00010002
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_PWM3           0x00010402
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_IDX0           0x00010802
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+#define GPIO_PB2_USB0EPEN       0x00010808
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_FAULT0         0x00010C02
+#define GPIO_PB3_FAULT3         0x00010C04
+#define GPIO_PB3_USB0PFLT       0x00010C08
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_CAN0RX         0x00011005
+#define GPIO_PB4_IDX0           0x00011006
+#define GPIO_PB4_U1RX           0x00011007
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CAN0TX         0x00011405
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_FAULT1         0x00011804
+#define GPIO_PB6_IDX0           0x00011805
+#define GPIO_PB6_CCP5           0x00011806
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_PHA0           0x00021002
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_FAULT2         0x00021404
+#define GPIO_PC5_CCP3           0x00021405
+#define GPIO_PC5_USB0EPEN       0x00021406
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_PHB0           0x00021802
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+#define GPIO_PC6_USB0PFLT       0x00021807
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_PHB0           0x00021C02
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_USB0PFLT       0x00021C06
+#define GPIO_PC7_C1O            0x00021C07
+
+#define GPIO_PD0_PWM0           0x00030001
+#define GPIO_PD0_CAN0RX         0x00030002
+#define GPIO_PD0_IDX0           0x00030003
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+
+#define GPIO_PD1_PWM1           0x00030401
+#define GPIO_PD1_CAN0TX         0x00030402
+#define GPIO_PD1_PHA0           0x00030403
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_CCP2           0x0003040A
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_PWM2           0x00030803
+#define GPIO_PD2_CCP5           0x00030804
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_PWM3           0x00030C03
+#define GPIO_PD3_CCP0           0x00030C04
+
+#define GPIO_PE0_PWM4           0x00040001
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+#define GPIO_PE0_USB0PFLT       0x00040009
+
+#define GPIO_PE1_PWM5           0x00040401
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_FAULT0         0x00040403
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_PHA0           0x00040804
+#define GPIO_PE2_CCP2           0x00040805
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_PHB0           0x00040C04
+#define GPIO_PE3_CCP7           0x00040C05
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_FAULT0         0x00041004
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+
+#endif // PART_LM3S5P56
+
+//*****************************************************************************
+//
+// LM3S5R31 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S5R31
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_PWM4           0x00000804
+#define GPIO_PA2_I2S0RXSD       0x00000809
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_PWM5           0x00000C04
+#define GPIO_PA3_I2S0RXMCLK     0x00000C09
+
+#define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_PWM6           0x00001004
+#define GPIO_PA4_CAN0RX         0x00001005
+#define GPIO_PA4_I2S0TXSCK      0x00001009
+
+#define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_PWM7           0x00001404
+#define GPIO_PA5_CAN0TX         0x00001405
+#define GPIO_PA5_I2S0TXWS       0x00001409
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_PWM0           0x00001804
+#define GPIO_PA6_PWM4           0x00001805
+#define GPIO_PA6_CAN0RX         0x00001806
+#define GPIO_PA6_U1CTS          0x00001809
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_PWM1           0x00001C04
+#define GPIO_PA7_PWM5           0x00001C05
+#define GPIO_PA7_CAN0TX         0x00001C06
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_U1DCD          0x00001C09
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_PWM2           0x00010002
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_PWM3           0x00010402
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_IDX0           0x00010802
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_FAULT0         0x00010C02
+#define GPIO_PB3_FAULT3         0x00010C04
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_CAN0RX         0x00011005
+#define GPIO_PB4_IDX0           0x00011006
+#define GPIO_PB4_U1RX           0x00011007
+#define GPIO_PB4_EPI0S23        0x00011008
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CAN0TX         0x00011405
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+#define GPIO_PB5_EPI0S22        0x00011408
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_FAULT1         0x00011804
+#define GPIO_PB6_IDX0           0x00011805
+#define GPIO_PB6_CCP5           0x00011806
+#define GPIO_PB6_I2S0TXSCK      0x00011809
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_PHA0           0x00021002
+#define GPIO_PC4_PWM6           0x00021004
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_EPI0S2         0x00021008
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_FAULT2         0x00021404
+#define GPIO_PC5_CCP3           0x00021405
+#define GPIO_PC5_EPI0S3         0x00021408
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_PHB0           0x00021802
+#define GPIO_PC6_PWM7           0x00021804
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+#define GPIO_PC6_EPI0S4         0x00021808
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_PHB0           0x00021C02
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_C1O            0x00021C07
+#define GPIO_PC7_EPI0S5         0x00021C08
+
+#define GPIO_PD0_PWM0           0x00030001
+#define GPIO_PD0_CAN0RX         0x00030002
+#define GPIO_PD0_IDX0           0x00030003
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+#define GPIO_PD0_I2S0RXSCK      0x00030008
+#define GPIO_PD0_U1CTS          0x00030009
+
+#define GPIO_PD1_PWM1           0x00030401
+#define GPIO_PD1_CAN0TX         0x00030402
+#define GPIO_PD1_PHA0           0x00030403
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_I2S0RXWS       0x00030408
+#define GPIO_PD1_U1DCD          0x00030409
+#define GPIO_PD1_CCP2           0x0003040A
+#define GPIO_PD1_PHB1           0x0003040B
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_PWM2           0x00030803
+#define GPIO_PD2_CCP5           0x00030804
+#define GPIO_PD2_EPI0S20        0x00030808
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_PWM3           0x00030C03
+#define GPIO_PD3_CCP0           0x00030C04
+#define GPIO_PD3_EPI0S21        0x00030C08
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+#define GPIO_PD4_I2S0RXSD       0x00031008
+#define GPIO_PD4_U1RI           0x00031009
+#define GPIO_PD4_EPI0S19        0x0003100A
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_I2S0RXMCLK     0x00031408
+#define GPIO_PD5_U2RX           0x00031409
+#define GPIO_PD5_EPI0S28        0x0003140A
+
+#define GPIO_PD6_FAULT0         0x00031801
+#define GPIO_PD6_I2S0TXSCK      0x00031808
+#define GPIO_PD6_U2TX           0x00031809
+#define GPIO_PD6_EPI0S29        0x0003180A
+
+#define GPIO_PD7_IDX0           0x00031C01
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+#define GPIO_PD7_I2S0TXWS       0x00031C08
+#define GPIO_PD7_U1DTR          0x00031C09
+#define GPIO_PD7_EPI0S30        0x00031C0A
+
+#define GPIO_PE0_PWM4           0x00040001
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+#define GPIO_PE0_EPI0S8         0x00040008
+
+#define GPIO_PE1_PWM5           0x00040401
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_FAULT0         0x00040403
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+#define GPIO_PE1_EPI0S9         0x00040408
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_PHB1           0x00040803
+#define GPIO_PE2_PHA0           0x00040804
+#define GPIO_PE2_CCP2           0x00040805
+#define GPIO_PE2_EPI0S24        0x00040808
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_PHA1           0x00040C03
+#define GPIO_PE3_PHB0           0x00040C04
+#define GPIO_PE3_CCP7           0x00040C05
+#define GPIO_PE3_EPI0S25        0x00040C08
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_FAULT0         0x00041004
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+#define GPIO_PE4_I2S0TXWS       0x00041009
+
+#define GPIO_PE5_CCP5           0x00041401
+#define GPIO_PE5_I2S0TXSD       0x00041409
+
+#define GPIO_PE6_PWM4           0x00041801
+#define GPIO_PE6_C1O            0x00041802
+#define GPIO_PE6_U1CTS          0x00041809
+
+#define GPIO_PE7_PWM5           0x00041C01
+#define GPIO_PE7_U1DCD          0x00041C09
+
+#define GPIO_PF0_PHB0           0x00050002
+#define GPIO_PF0_PWM0           0x00050003
+#define GPIO_PF0_I2S0TXSD       0x00050008
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_IDX1           0x00050402
+#define GPIO_PF1_PWM1           0x00050403
+#define GPIO_PF1_I2S0TXMCLK     0x00050408
+#define GPIO_PF1_U1RTS          0x00050409
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_PWM4           0x00050802
+#define GPIO_PF2_PWM2           0x00050804
+#define GPIO_PF2_SSI1CLK        0x00050809
+
+#define GPIO_PF3_PWM5           0x00050C02
+#define GPIO_PF3_PWM3           0x00050C04
+#define GPIO_PF3_SSI1FSS        0x00050C09
+
+#define GPIO_PF4_CCP0           0x00051001
+#define GPIO_PF4_C0O            0x00051002
+#define GPIO_PF4_FAULT0         0x00051004
+#define GPIO_PF4_EPI0S12        0x00051008
+#define GPIO_PF4_SSI1RX         0x00051009
+
+#define GPIO_PF5_CCP2           0x00051401
+#define GPIO_PF5_C1O            0x00051402
+#define GPIO_PF5_EPI0S15        0x00051408
+#define GPIO_PF5_SSI1TX         0x00051409
+
+#define GPIO_PF6_CCP1           0x00051801
+#define GPIO_PF6_PHA0           0x00051804
+#define GPIO_PF6_I2S0TXMCLK     0x00051809
+#define GPIO_PF6_U1RTS          0x0005180A
+
+#define GPIO_PF7_CCP4           0x00051C01
+#define GPIO_PF7_PHB0           0x00051C04
+#define GPIO_PF7_EPI0S12        0x00051C08
+#define GPIO_PF7_FAULT1         0x00051C09
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_PWM0           0x00060002
+#define GPIO_PG0_I2C1SCL        0x00060003
+#define GPIO_PG0_PWM4           0x00060004
+#define GPIO_PG0_EPI0S13        0x00060008
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_PWM1           0x00060402
+#define GPIO_PG1_I2C1SDA        0x00060403
+#define GPIO_PG1_PWM5           0x00060404
+#define GPIO_PG1_EPI0S14        0x00060408
+
+#define GPIO_PG2_PWM0           0x00060801
+#define GPIO_PG2_FAULT0         0x00060804
+#define GPIO_PG2_IDX1           0x00060808
+#define GPIO_PG2_I2S0RXSD       0x00060809
+
+#define GPIO_PG3_PWM1           0x00060C01
+#define GPIO_PG3_FAULT2         0x00060C04
+#define GPIO_PG3_FAULT0         0x00060C08
+#define GPIO_PG3_I2S0RXMCLK     0x00060C09
+
+#define GPIO_PG4_CCP3           0x00061001
+#define GPIO_PG4_FAULT1         0x00061004
+#define GPIO_PG4_EPI0S15        0x00061008
+#define GPIO_PG4_PWM6           0x00061009
+#define GPIO_PG4_U1RI           0x0006100A
+
+#define GPIO_PG5_CCP5           0x00061401
+#define GPIO_PG5_IDX0           0x00061404
+#define GPIO_PG5_FAULT1         0x00061405
+#define GPIO_PG5_PWM7           0x00061408
+#define GPIO_PG5_I2S0RXSCK      0x00061409
+#define GPIO_PG5_U1DTR          0x0006140A
+
+#define GPIO_PG6_PHA1           0x00061801
+#define GPIO_PG6_PWM6           0x00061804
+#define GPIO_PG6_FAULT1         0x00061808
+#define GPIO_PG6_I2S0RXWS       0x00061809
+#define GPIO_PG6_U1RI           0x0006180A
+
+#define GPIO_PG7_PHB1           0x00061C01
+#define GPIO_PG7_PWM7           0x00061C04
+#define GPIO_PG7_CCP5           0x00061C08
+#define GPIO_PG7_EPI0S31        0x00061C09
+
+#define GPIO_PH0_CCP6           0x00070001
+#define GPIO_PH0_PWM2           0x00070002
+#define GPIO_PH0_EPI0S6         0x00070008
+#define GPIO_PH0_PWM4           0x00070009
+
+#define GPIO_PH1_CCP7           0x00070401
+#define GPIO_PH1_PWM3           0x00070402
+#define GPIO_PH1_EPI0S7         0x00070408
+#define GPIO_PH1_PWM5           0x00070409
+
+#define GPIO_PH2_IDX1           0x00070801
+#define GPIO_PH2_C1O            0x00070802
+#define GPIO_PH2_FAULT3         0x00070804
+#define GPIO_PH2_EPI0S1         0x00070808
+
+#define GPIO_PH3_PHB0           0x00070C01
+#define GPIO_PH3_FAULT0         0x00070C02
+#define GPIO_PH3_EPI0S0         0x00070C08
+
+#define GPIO_PH4_EPI0S10        0x00071008
+#define GPIO_PH4_SSI1CLK        0x0007100B
+
+#define GPIO_PH5_EPI0S11        0x00071408
+#define GPIO_PH5_FAULT2         0x0007140A
+#define GPIO_PH5_SSI1FSS        0x0007140B
+
+#define GPIO_PH6_EPI0S26        0x00071808
+#define GPIO_PH6_PWM4           0x0007180A
+#define GPIO_PH6_SSI1RX         0x0007180B
+
+#define GPIO_PH7_EPI0S27        0x00071C08
+#define GPIO_PH7_PWM5           0x00071C0A
+#define GPIO_PH7_SSI1TX         0x00071C0B
+
+#define GPIO_PJ0_EPI0S16        0x00080008
+#define GPIO_PJ0_PWM0           0x0008000A
+#define GPIO_PJ0_I2C1SCL        0x0008000B
+
+#define GPIO_PJ1_EPI0S17        0x00080408
+#define GPIO_PJ1_PWM1           0x0008040A
+#define GPIO_PJ1_I2C1SDA        0x0008040B
+
+#define GPIO_PJ2_EPI0S18        0x00080808
+#define GPIO_PJ2_CCP0           0x00080809
+#define GPIO_PJ2_FAULT0         0x0008080A
+
+#endif // PART_LM3S5R31
+
+//*****************************************************************************
+//
+// LM3S5R36 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S5R36
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_PWM4           0x00000804
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_PWM5           0x00000C04
+
+#define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_PWM6           0x00001004
+#define GPIO_PA4_CAN0RX         0x00001005
+
+#define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_PWM7           0x00001404
+#define GPIO_PA5_CAN0TX         0x00001405
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_PWM0           0x00001804
+#define GPIO_PA6_PWM4           0x00001805
+#define GPIO_PA6_CAN0RX         0x00001806
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_PWM1           0x00001C04
+#define GPIO_PA7_PWM5           0x00001C05
+#define GPIO_PA7_CAN0TX         0x00001C06
+#define GPIO_PA7_CCP3           0x00001C07
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_PWM2           0x00010002
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_PWM3           0x00010402
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_IDX0           0x00010802
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_FAULT0         0x00010C02
+#define GPIO_PB3_FAULT3         0x00010C04
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_CAN0RX         0x00011005
+#define GPIO_PB4_IDX0           0x00011006
+#define GPIO_PB4_U1RX           0x00011007
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CAN0TX         0x00011405
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_FAULT1         0x00011804
+#define GPIO_PB6_IDX0           0x00011805
+#define GPIO_PB6_CCP5           0x00011806
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_PHA0           0x00021002
+#define GPIO_PC4_PWM6           0x00021004
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_FAULT2         0x00021404
+#define GPIO_PC5_CCP3           0x00021405
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_PHB0           0x00021802
+#define GPIO_PC6_PWM7           0x00021804
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_PHB0           0x00021C02
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_C1O            0x00021C07
+
+#define GPIO_PD0_PWM0           0x00030001
+#define GPIO_PD0_CAN0RX         0x00030002
+#define GPIO_PD0_IDX0           0x00030003
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+
+#define GPIO_PD1_PWM1           0x00030401
+#define GPIO_PD1_CAN0TX         0x00030402
+#define GPIO_PD1_PHA0           0x00030403
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_CCP2           0x0003040A
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_PWM2           0x00030803
+#define GPIO_PD2_CCP5           0x00030804
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_PWM3           0x00030C03
+#define GPIO_PD3_CCP0           0x00030C04
+
+#define GPIO_PE0_PWM4           0x00040001
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+
+#define GPIO_PE1_PWM5           0x00040401
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_FAULT0         0x00040403
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_PHA0           0x00040804
+#define GPIO_PE2_CCP2           0x00040805
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_PHB0           0x00040C04
+#define GPIO_PE3_CCP7           0x00040C05
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_FAULT0         0x00041004
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+
+#endif // PART_LM3S5R36
+
+//*****************************************************************************
+//
+// LM3S5T36 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S5T36
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_PWM4           0x00000804
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_PWM5           0x00000C04
+
+#define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_CAN0RX         0x00001005
+
+#define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_CAN0TX         0x00001405
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_PWM0           0x00001804
+#define GPIO_PA6_PWM4           0x00001805
+#define GPIO_PA6_CAN0RX         0x00001806
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_PWM1           0x00001C04
+#define GPIO_PA7_PWM5           0x00001C05
+#define GPIO_PA7_CAN0TX         0x00001C06
+#define GPIO_PA7_CCP3           0x00001C07
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_PWM2           0x00010002
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_PWM3           0x00010402
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_IDX0           0x00010802
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_FAULT0         0x00010C02
+#define GPIO_PB3_FAULT3         0x00010C04
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_CAN0RX         0x00011005
+#define GPIO_PB4_IDX0           0x00011006
+#define GPIO_PB4_U1RX           0x00011007
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CAN0TX         0x00011405
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_FAULT1         0x00011804
+#define GPIO_PB6_IDX0           0x00011805
+#define GPIO_PB6_CCP5           0x00011806
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_PHA0           0x00021002
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_FAULT2         0x00021404
+#define GPIO_PC5_CCP3           0x00021405
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_PHB0           0x00021802
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_PHB0           0x00021C02
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_C1O            0x00021C07
+
+#define GPIO_PD0_PWM0           0x00030001
+#define GPIO_PD0_CAN0RX         0x00030002
+#define GPIO_PD0_IDX0           0x00030003
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+
+#define GPIO_PD1_PWM1           0x00030401
+#define GPIO_PD1_CAN0TX         0x00030402
+#define GPIO_PD1_PHA0           0x00030403
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP2           0x0003040A
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_PWM2           0x00030803
+#define GPIO_PD2_CCP5           0x00030804
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_PWM3           0x00030C03
+#define GPIO_PD3_CCP0           0x00030C04
+
+#define GPIO_PE0_PWM4           0x00040001
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+
+#define GPIO_PE1_PWM5           0x00040401
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_FAULT0         0x00040403
+#define GPIO_PE1_CCP2           0x00040404
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_PHA0           0x00040804
+#define GPIO_PE2_CCP2           0x00040805
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_PHB0           0x00040C04
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_FAULT0         0x00041004
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+
+#endif // PART_LM3S5T36
+
+//*****************************************************************************
+//
+// LM3S5U91 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S5U91
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_PWM4           0x00000804
+#define GPIO_PA2_I2S0RXSD       0x00000809
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_PWM5           0x00000C04
+#define GPIO_PA3_I2S0RXMCLK     0x00000C09
+
+#define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_PWM6           0x00001004
+#define GPIO_PA4_CAN0RX         0x00001005
+#define GPIO_PA4_I2S0TXSCK      0x00001009
+
+#define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_PWM7           0x00001404
+#define GPIO_PA5_CAN0TX         0x00001405
+#define GPIO_PA5_I2S0TXWS       0x00001409
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_PWM0           0x00001804
+#define GPIO_PA6_PWM4           0x00001805
+#define GPIO_PA6_CAN0RX         0x00001806
+#define GPIO_PA6_USB0EPEN       0x00001808
+#define GPIO_PA6_U1CTS          0x00001809
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_PWM1           0x00001C04
+#define GPIO_PA7_PWM5           0x00001C05
+#define GPIO_PA7_CAN0TX         0x00001C06
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_USB0PFLT       0x00001C08
+#define GPIO_PA7_U1DCD          0x00001C09
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_PWM2           0x00010002
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_PWM3           0x00010402
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_IDX0           0x00010802
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+#define GPIO_PB2_USB0EPEN       0x00010808
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_FAULT0         0x00010C02
+#define GPIO_PB3_FAULT3         0x00010C04
+#define GPIO_PB3_USB0PFLT       0x00010C08
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_CAN0RX         0x00011005
+#define GPIO_PB4_IDX0           0x00011006
+#define GPIO_PB4_U1RX           0x00011007
+#define GPIO_PB4_EPI0S23        0x00011008
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CAN0TX         0x00011405
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+#define GPIO_PB5_EPI0S22        0x00011408
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_FAULT1         0x00011804
+#define GPIO_PB6_IDX0           0x00011805
+#define GPIO_PB6_CCP5           0x00011806
+#define GPIO_PB6_I2S0TXSCK      0x00011809
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_PHA0           0x00021002
+#define GPIO_PC4_PWM6           0x00021004
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_EPI0S2         0x00021008
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_FAULT2         0x00021404
+#define GPIO_PC5_CCP3           0x00021405
+#define GPIO_PC5_USB0EPEN       0x00021406
+#define GPIO_PC5_EPI0S3         0x00021408
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_PHB0           0x00021802
+#define GPIO_PC6_C2O            0x00021803
+#define GPIO_PC6_PWM7           0x00021804
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+#define GPIO_PC6_USB0PFLT       0x00021807
+#define GPIO_PC6_EPI0S4         0x00021808
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_PHB0           0x00021C02
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_USB0PFLT       0x00021C06
+#define GPIO_PC7_C1O            0x00021C07
+#define GPIO_PC7_EPI0S5         0x00021C08
+
+#define GPIO_PD0_PWM0           0x00030001
+#define GPIO_PD0_CAN0RX         0x00030002
+#define GPIO_PD0_IDX0           0x00030003
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+#define GPIO_PD0_I2S0RXSCK      0x00030008
+#define GPIO_PD0_U1CTS          0x00030009
+
+#define GPIO_PD1_PWM1           0x00030401
+#define GPIO_PD1_CAN0TX         0x00030402
+#define GPIO_PD1_PHA0           0x00030403
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_I2S0RXWS       0x00030408
+#define GPIO_PD1_U1DCD          0x00030409
+#define GPIO_PD1_CCP2           0x0003040A
+#define GPIO_PD1_PHB1           0x0003040B
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_PWM2           0x00030803
+#define GPIO_PD2_CCP5           0x00030804
+#define GPIO_PD2_EPI0S20        0x00030808
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_PWM3           0x00030C03
+#define GPIO_PD3_CCP0           0x00030C04
+#define GPIO_PD3_EPI0S21        0x00030C08
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+#define GPIO_PD4_I2S0RXSD       0x00031008
+#define GPIO_PD4_U1RI           0x00031009
+#define GPIO_PD4_EPI0S19        0x0003100A
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_I2S0RXMCLK     0x00031408
+#define GPIO_PD5_U2RX           0x00031409
+#define GPIO_PD5_EPI0S28        0x0003140A
+
+#define GPIO_PD6_FAULT0         0x00031801
+#define GPIO_PD6_I2S0TXSCK      0x00031808
+#define GPIO_PD6_U2TX           0x00031809
+#define GPIO_PD6_EPI0S29        0x0003180A
+
+#define GPIO_PD7_IDX0           0x00031C01
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+#define GPIO_PD7_I2S0TXWS       0x00031C08
+#define GPIO_PD7_U1DTR          0x00031C09
+#define GPIO_PD7_EPI0S30        0x00031C0A
+
+#define GPIO_PE0_PWM4           0x00040001
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+#define GPIO_PE0_EPI0S8         0x00040008
+#define GPIO_PE0_USB0PFLT       0x00040009
+
+#define GPIO_PE1_PWM5           0x00040401
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_FAULT0         0x00040403
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+#define GPIO_PE1_EPI0S9         0x00040408
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_PHB1           0x00040803
+#define GPIO_PE2_PHA0           0x00040804
+#define GPIO_PE2_CCP2           0x00040805
+#define GPIO_PE2_EPI0S24        0x00040808
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_PHA1           0x00040C03
+#define GPIO_PE3_PHB0           0x00040C04
+#define GPIO_PE3_CCP7           0x00040C05
+#define GPIO_PE3_EPI0S25        0x00040C08
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_FAULT0         0x00041004
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+#define GPIO_PE4_I2S0TXWS       0x00041009
+
+#define GPIO_PE5_CCP5           0x00041401
+#define GPIO_PE5_I2S0TXSD       0x00041409
+
+#define GPIO_PE6_PWM4           0x00041801
+#define GPIO_PE6_C1O            0x00041802
+#define GPIO_PE6_U1CTS          0x00041809
+
+#define GPIO_PE7_PWM5           0x00041C01
+#define GPIO_PE7_C2O            0x00041C02
+#define GPIO_PE7_U1DCD          0x00041C09
+
+#define GPIO_PF0_CAN1RX         0x00050001
+#define GPIO_PF0_PHB0           0x00050002
+#define GPIO_PF0_PWM0           0x00050003
+#define GPIO_PF0_I2S0TXSD       0x00050008
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_CAN1TX         0x00050401
+#define GPIO_PF1_IDX1           0x00050402
+#define GPIO_PF1_PWM1           0x00050403
+#define GPIO_PF1_I2S0TXMCLK     0x00050408
+#define GPIO_PF1_U1RTS          0x00050409
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_PWM4           0x00050802
+#define GPIO_PF2_PWM2           0x00050804
+#define GPIO_PF2_SSI1CLK        0x00050809
+
+#define GPIO_PF3_PWM5           0x00050C02
+#define GPIO_PF3_PWM3           0x00050C04
+#define GPIO_PF3_SSI1FSS        0x00050C09
+
+#define GPIO_PF4_CCP0           0x00051001
+#define GPIO_PF4_C0O            0x00051002
+#define GPIO_PF4_FAULT0         0x00051004
+#define GPIO_PF4_EPI0S12        0x00051008
+#define GPIO_PF4_SSI1RX         0x00051009
+
+#define GPIO_PF5_CCP2           0x00051401
+#define GPIO_PF5_C1O            0x00051402
+#define GPIO_PF5_EPI0S15        0x00051408
+#define GPIO_PF5_SSI1TX         0x00051409
+
+#define GPIO_PF6_CCP1           0x00051801
+#define GPIO_PF6_C2O            0x00051802
+#define GPIO_PF6_PHA0           0x00051804
+#define GPIO_PF6_I2S0TXMCLK     0x00051809
+#define GPIO_PF6_U1RTS          0x0005180A
+
+#define GPIO_PF7_CCP4           0x00051C01
+#define GPIO_PF7_PHB0           0x00051C04
+#define GPIO_PF7_EPI0S12        0x00051C08
+#define GPIO_PF7_FAULT1         0x00051C09
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_PWM0           0x00060002
+#define GPIO_PG0_I2C1SCL        0x00060003
+#define GPIO_PG0_PWM4           0x00060004
+#define GPIO_PG0_USB0EPEN       0x00060007
+#define GPIO_PG0_EPI0S13        0x00060008
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_PWM1           0x00060402
+#define GPIO_PG1_I2C1SDA        0x00060403
+#define GPIO_PG1_PWM5           0x00060404
+#define GPIO_PG1_EPI0S14        0x00060408
+
+#define GPIO_PG2_PWM0           0x00060801
+#define GPIO_PG2_FAULT0         0x00060804
+#define GPIO_PG2_IDX1           0x00060808
+#define GPIO_PG2_I2S0RXSD       0x00060809
+
+#define GPIO_PG3_PWM1           0x00060C01
+#define GPIO_PG3_FAULT2         0x00060C04
+#define GPIO_PG3_FAULT0         0x00060C08
+#define GPIO_PG3_I2S0RXMCLK     0x00060C09
+
+#define GPIO_PG4_CCP3           0x00061001
+#define GPIO_PG4_FAULT1         0x00061004
+#define GPIO_PG4_EPI0S15        0x00061008
+#define GPIO_PG4_PWM6           0x00061009
+#define GPIO_PG4_U1RI           0x0006100A
+
+#define GPIO_PG5_CCP5           0x00061401
+#define GPIO_PG5_IDX0           0x00061404
+#define GPIO_PG5_FAULT1         0x00061405
+#define GPIO_PG5_PWM7           0x00061408
+#define GPIO_PG5_I2S0RXSCK      0x00061409
+#define GPIO_PG5_U1DTR          0x0006140A
+
+#define GPIO_PG6_PHA1           0x00061801
+#define GPIO_PG6_PWM6           0x00061804
+#define GPIO_PG6_FAULT1         0x00061808
+#define GPIO_PG6_I2S0RXWS       0x00061809
+#define GPIO_PG6_U1RI           0x0006180A
+
+#define GPIO_PG7_PHB1           0x00061C01
+#define GPIO_PG7_PWM7           0x00061C04
+#define GPIO_PG7_CCP5           0x00061C08
+#define GPIO_PG7_EPI0S31        0x00061C09
+
+#define GPIO_PH0_CCP6           0x00070001
+#define GPIO_PH0_PWM2           0x00070002
+#define GPIO_PH0_EPI0S6         0x00070008
+#define GPIO_PH0_PWM4           0x00070009
+
+#define GPIO_PH1_CCP7           0x00070401
+#define GPIO_PH1_PWM3           0x00070402
+#define GPIO_PH1_EPI0S7         0x00070408
+#define GPIO_PH1_PWM5           0x00070409
+
+#define GPIO_PH2_IDX1           0x00070801
+#define GPIO_PH2_C1O            0x00070802
+#define GPIO_PH2_FAULT3         0x00070804
+#define GPIO_PH2_EPI0S1         0x00070808
+
+#define GPIO_PH3_PHB0           0x00070C01
+#define GPIO_PH3_FAULT0         0x00070C02
+#define GPIO_PH3_USB0EPEN       0x00070C04
+#define GPIO_PH3_EPI0S0         0x00070C08
+
+#define GPIO_PH4_USB0PFLT       0x00071004
+#define GPIO_PH4_EPI0S10        0x00071008
+#define GPIO_PH4_SSI1CLK        0x0007100B
+
+#define GPIO_PH5_EPI0S11        0x00071408
+#define GPIO_PH5_FAULT2         0x0007140A
+#define GPIO_PH5_SSI1FSS        0x0007140B
+
+#define GPIO_PH6_EPI0S26        0x00071808
+#define GPIO_PH6_PWM4           0x0007180A
+#define GPIO_PH6_SSI1RX         0x0007180B
+
+#define GPIO_PH7_EPI0S27        0x00071C08
+#define GPIO_PH7_PWM5           0x00071C0A
+#define GPIO_PH7_SSI1TX         0x00071C0B
+
+#define GPIO_PJ0_EPI0S16        0x00080008
+#define GPIO_PJ0_PWM0           0x0008000A
+#define GPIO_PJ0_I2C1SCL        0x0008000B
+
+#define GPIO_PJ1_EPI0S17        0x00080408
+#define GPIO_PJ1_USB0PFLT       0x00080409
+#define GPIO_PJ1_PWM1           0x0008040A
+#define GPIO_PJ1_I2C1SDA        0x0008040B
+
+#define GPIO_PJ2_EPI0S18        0x00080808
+#define GPIO_PJ2_CCP0           0x00080809
+#define GPIO_PJ2_FAULT0         0x0008080A
+
+#define GPIO_PJ3_EPI0S19        0x00080C08
+#define GPIO_PJ3_U1CTS          0x00080C09
+#define GPIO_PJ3_CCP6           0x00080C0A
+
+#define GPIO_PJ4_EPI0S28        0x00081008
+#define GPIO_PJ4_U1DCD          0x00081009
+#define GPIO_PJ4_CCP4           0x0008100A
+
+#define GPIO_PJ5_EPI0S29        0x00081408
+#define GPIO_PJ5_U1DSR          0x00081409
+#define GPIO_PJ5_CCP2           0x0008140A
+
+#define GPIO_PJ6_EPI0S30        0x00081808
+#define GPIO_PJ6_U1RTS          0x00081809
+#define GPIO_PJ6_CCP1           0x0008180A
+
+#define GPIO_PJ7_U1DTR          0x00081C09
+#define GPIO_PJ7_CCP0           0x00081C0A
+
+#endif // PART_LM3S5U91
+
+//*****************************************************************************
+//
+// LM3S5Y36 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S5Y36
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_PWM4           0x00000804
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_PWM5           0x00000C04
+
+#define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_CAN0RX         0x00001005
+
+#define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_CAN0TX         0x00001405
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_PWM0           0x00001804
+#define GPIO_PA6_PWM4           0x00001805
+#define GPIO_PA6_CAN0RX         0x00001806
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_PWM1           0x00001C04
+#define GPIO_PA7_PWM5           0x00001C05
+#define GPIO_PA7_CAN0TX         0x00001C06
+#define GPIO_PA7_CCP3           0x00001C07
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_PWM2           0x00010002
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_PWM3           0x00010402
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_IDX0           0x00010802
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_FAULT0         0x00010C02
+#define GPIO_PB3_FAULT3         0x00010C04
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_CAN0RX         0x00011005
+#define GPIO_PB4_IDX0           0x00011006
+#define GPIO_PB4_U1RX           0x00011007
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CAN0TX         0x00011405
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_FAULT1         0x00011804
+#define GPIO_PB6_IDX0           0x00011805
+#define GPIO_PB6_CCP5           0x00011806
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_PHA0           0x00021002
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_FAULT2         0x00021404
+#define GPIO_PC5_CCP3           0x00021405
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_PHB0           0x00021802
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_PHB0           0x00021C02
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_C1O            0x00021C07
+
+#define GPIO_PD0_PWM0           0x00030001
+#define GPIO_PD0_CAN0RX         0x00030002
+#define GPIO_PD0_IDX0           0x00030003
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+
+#define GPIO_PD1_PWM1           0x00030401
+#define GPIO_PD1_CAN0TX         0x00030402
+#define GPIO_PD1_PHA0           0x00030403
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP2           0x0003040A
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_PWM2           0x00030803
+#define GPIO_PD2_CCP5           0x00030804
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_PWM3           0x00030C03
+#define GPIO_PD3_CCP0           0x00030C04
+
+#define GPIO_PE0_PWM4           0x00040001
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+
+#define GPIO_PE1_PWM5           0x00040401
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_FAULT0         0x00040403
+#define GPIO_PE1_CCP2           0x00040404
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_PHA0           0x00040804
+#define GPIO_PE2_CCP2           0x00040805
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_PHB0           0x00040C04
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_FAULT0         0x00041004
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+
+#endif // PART_LM3S5Y36
+
+//*****************************************************************************
+//
+// LM3S6100 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S6100
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOB
+#define C0O_PORT                GPIO_PORTB_BASE
+#define C0O_PIN                 GPIO_PIN_5
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP1_PORT               GPIO_PORTA_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_1
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP3_PORT               GPIO_PORTC_BASE
+#define CCP3_PIN                GPIO_PIN_6
+
+#define LED0_PERIPH             SYSCTL_PERIPH_GPIOF
+#define LED0_PORT               GPIO_PORTF_BASE
+#define LED0_PIN                GPIO_PIN_3
+
+#define LED1_PERIPH             SYSCTL_PERIPH_GPIOF
+#define LED1_PORT               GPIO_PORTF_BASE
+#define LED1_PIN                GPIO_PIN_2
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#endif // PART_LM3S6100
+
+//*****************************************************************************
+//
+// LM3S6110 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S6110
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOD
+#define C0O_PORT                GPIO_PORTD_BASE
+#define C0O_PIN                 GPIO_PIN_7
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_5
+
+#define C2_MINUS_PERIPH         SYSCTL_PERIPH_GPIOC
+#define C2_MINUS_PORT           GPIO_PORTC_BASE
+#define C2_MINUS_PIN            GPIO_PIN_7
+
+#define C2_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C2_PLUS_PORT            GPIO_PORTC_BASE
+#define C2_PLUS_PIN             GPIO_PIN_6
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP1_PORT               GPIO_PORTA_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_1
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP3_PORT               GPIO_PORTD_BASE
+#define CCP3_PIN                GPIO_PIN_4
+
+#define FAULT_PERIPH            SYSCTL_PERIPH_GPIOB
+#define FAULT_PORT              GPIO_PORTB_BASE
+#define FAULT_PIN               GPIO_PIN_3
+
+#define LED0_PERIPH             SYSCTL_PERIPH_GPIOF
+#define LED0_PORT               GPIO_PORTF_BASE
+#define LED0_PIN                GPIO_PIN_3
+
+#define LED1_PERIPH             SYSCTL_PERIPH_GPIOF
+#define LED1_PORT               GPIO_PORTF_BASE
+#define LED1_PIN                GPIO_PIN_2
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM0_PORT               GPIO_PORTD_BASE
+#define PWM0_PIN                GPIO_PIN_0
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM1_PORT               GPIO_PORTD_BASE
+#define PWM1_PIN                GPIO_PIN_1
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#endif // PART_LM3S6110
+
+//*****************************************************************************
+//
+// LM3S6420 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S6420
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOD
+#define C0O_PORT                GPIO_PORTD_BASE
+#define C0O_PIN                 GPIO_PIN_7
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1O_PERIPH              SYSCTL_PERIPH_GPIOE
+#define C1O_PORT                GPIO_PORTE_BASE
+#define C1O_PIN                 GPIO_PIN_6
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_5
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP1_PORT               GPIO_PORTA_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_1
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP3_PORT               GPIO_PORTC_BASE
+#define CCP3_PIN                GPIO_PIN_6
+
+#define LED0_PERIPH             SYSCTL_PERIPH_GPIOF
+#define LED0_PORT               GPIO_PORTF_BASE
+#define LED0_PIN                GPIO_PIN_3
+
+#define LED1_PERIPH             SYSCTL_PERIPH_GPIOF
+#define LED1_PORT               GPIO_PORTF_BASE
+#define LED1_PIN                GPIO_PIN_2
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#endif // PART_LM3S6420
+
+//*****************************************************************************
+//
+// LM3S6422 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S6422
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOD
+#define C0O_PORT                GPIO_PORTD_BASE
+#define C0O_PIN                 GPIO_PIN_7
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1O_PERIPH              SYSCTL_PERIPH_GPIOC
+#define C1O_PORT                GPIO_PORTC_BASE
+#define C1O_PIN                 GPIO_PIN_5
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_5
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP1_PORT               GPIO_PORTA_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_1
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP3_PORT               GPIO_PORTC_BASE
+#define CCP3_PIN                GPIO_PIN_6
+
+#define LED0_PERIPH             SYSCTL_PERIPH_GPIOF
+#define LED0_PORT               GPIO_PORTF_BASE
+#define LED0_PIN                GPIO_PIN_3
+
+#define LED1_PERIPH             SYSCTL_PERIPH_GPIOF
+#define LED1_PORT               GPIO_PORTF_BASE
+#define LED1_PIN                GPIO_PIN_2
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#endif // PART_LM3S6422
+
+//*****************************************************************************
+//
+// LM3S6432 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S6432
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOD
+#define C0O_PORT                GPIO_PORTD_BASE
+#define C0O_PIN                 GPIO_PIN_7
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_5
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP1_PORT               GPIO_PORTA_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_1
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP3_PORT               GPIO_PORTC_BASE
+#define CCP3_PIN                GPIO_PIN_6
+
+#define FAULT_PERIPH            SYSCTL_PERIPH_GPIOD
+#define FAULT_PORT              GPIO_PORTD_BASE
+#define FAULT_PIN               GPIO_PIN_6
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define LED0_PERIPH             SYSCTL_PERIPH_GPIOF
+#define LED0_PORT               GPIO_PORTF_BASE
+#define LED0_PIN                GPIO_PIN_3
+
+#define LED1_PERIPH             SYSCTL_PERIPH_GPIOF
+#define LED1_PORT               GPIO_PORTF_BASE
+#define LED1_PIN                GPIO_PIN_2
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM0_PORT               GPIO_PORTD_BASE
+#define PWM0_PIN                GPIO_PIN_0
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM1_PORT               GPIO_PORTD_BASE
+#define PWM1_PIN                GPIO_PIN_1
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#endif // PART_LM3S6432
+
+//*****************************************************************************
+//
+// LM3S6537 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S6537
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOD
+#define C0O_PORT                GPIO_PORTD_BASE
+#define C0O_PIN                 GPIO_PIN_7
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_5
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP0_PORT               GPIO_PORTD_BASE
+#define CCP0_PIN                GPIO_PIN_4
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP1_PORT               GPIO_PORTA_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP2_PORT               GPIO_PORTD_BASE
+#define CCP2_PIN                GPIO_PIN_5
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP3_PORT               GPIO_PORTC_BASE
+#define CCP3_PIN                GPIO_PIN_6
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP4_PORT               GPIO_PORTA_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP5_PORT               GPIO_PORTC_BASE
+#define CCP5_PIN                GPIO_PIN_4
+
+#define FAULT_PERIPH            SYSCTL_PERIPH_GPIOD
+#define FAULT_PORT              GPIO_PORTD_BASE
+#define FAULT_PIN               GPIO_PIN_6
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define LED0_PERIPH             SYSCTL_PERIPH_GPIOF
+#define LED0_PORT               GPIO_PORTF_BASE
+#define LED0_PIN                GPIO_PIN_3
+
+#define LED1_PERIPH             SYSCTL_PERIPH_GPIOF
+#define LED1_PORT               GPIO_PORTF_BASE
+#define LED1_PIN                GPIO_PIN_2
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM0_PORT               GPIO_PORTD_BASE
+#define PWM0_PIN                GPIO_PIN_0
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM1_PORT               GPIO_PORTD_BASE
+#define PWM1_PIN                GPIO_PIN_1
+
+#define PWM2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define PWM2_PORT               GPIO_PORTB_BASE
+#define PWM2_PIN                GPIO_PIN_0
+
+#define PWM3_PERIPH             SYSCTL_PERIPH_GPIOB
+#define PWM3_PORT               GPIO_PORTB_BASE
+#define PWM3_PIN                GPIO_PIN_1
+
+#define PWM4_PERIPH             SYSCTL_PERIPH_GPIOE
+#define PWM4_PORT               GPIO_PORTE_BASE
+#define PWM4_PIN                GPIO_PIN_0
+
+#define PWM5_PERIPH             SYSCTL_PERIPH_GPIOE
+#define PWM5_PORT               GPIO_PORTE_BASE
+#define PWM5_PIN                GPIO_PIN_1
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#endif // PART_LM3S6537
+
+//*****************************************************************************
+//
+// LM3S6610 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S6610
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOC
+#define C0O_PORT                GPIO_PORTC_BASE
+#define C0O_PIN                 GPIO_PIN_5
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1O_PERIPH              SYSCTL_PERIPH_GPIOE
+#define C1O_PORT                GPIO_PORTE_BASE
+#define C1O_PIN                 GPIO_PIN_6
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_5
+
+#define C2O_PERIPH              SYSCTL_PERIPH_GPIOE
+#define C2O_PORT                GPIO_PORTE_BASE
+#define C2O_PIN                 GPIO_PIN_7
+
+#define C2_MINUS_PERIPH         SYSCTL_PERIPH_GPIOC
+#define C2_MINUS_PORT           GPIO_PORTC_BASE
+#define C2_MINUS_PIN            GPIO_PIN_7
+
+#define C2_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C2_PLUS_PORT            GPIO_PORTC_BASE
+#define C2_PLUS_PIN             GPIO_PIN_6
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP0_PORT               GPIO_PORTD_BASE
+#define CCP0_PIN                GPIO_PIN_4
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP1_PORT               GPIO_PORTA_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP2_PORT               GPIO_PORTD_BASE
+#define CCP2_PIN                GPIO_PIN_5
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOE
+#define CCP3_PORT               GPIO_PORTE_BASE
+#define CCP3_PIN                GPIO_PIN_0
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP4_PORT               GPIO_PORTA_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP5_PORT               GPIO_PORTC_BASE
+#define CCP5_PIN                GPIO_PIN_4
+
+#define FAULT_PERIPH            SYSCTL_PERIPH_GPIOD
+#define FAULT_PORT              GPIO_PORTD_BASE
+#define FAULT_PIN               GPIO_PIN_6
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define IDX0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define IDX0_PORT               GPIO_PORTD_BASE
+#define IDX0_PIN                GPIO_PIN_7
+
+#define LED0_PERIPH             SYSCTL_PERIPH_GPIOF
+#define LED0_PORT               GPIO_PORTF_BASE
+#define LED0_PIN                GPIO_PIN_3
+
+#define LED1_PERIPH             SYSCTL_PERIPH_GPIOF
+#define LED1_PORT               GPIO_PORTF_BASE
+#define LED1_PIN                GPIO_PIN_2
+
+#define PHA0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PHA0_PORT               GPIO_PORTD_BASE
+#define PHA0_PIN                GPIO_PIN_1
+
+#define PHB0_PERIPH             SYSCTL_PERIPH_GPIOF
+#define PHB0_PORT               GPIO_PORTF_BASE
+#define PHB0_PIN                GPIO_PIN_0
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM0_PORT               GPIO_PORTD_BASE
+#define PWM0_PIN                GPIO_PIN_0
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOF
+#define PWM1_PORT               GPIO_PORTF_BASE
+#define PWM1_PIN                GPIO_PIN_1
+
+#define PWM2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define PWM2_PORT               GPIO_PORTB_BASE
+#define PWM2_PIN                GPIO_PIN_0
+
+#define PWM3_PERIPH             SYSCTL_PERIPH_GPIOB
+#define PWM3_PORT               GPIO_PORTB_BASE
+#define PWM3_PIN                GPIO_PIN_1
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#define U2RX_PERIPH             SYSCTL_PERIPH_GPIOG
+#define U2RX_PORT               GPIO_PORTG_BASE
+#define U2RX_PIN                GPIO_PIN_0
+
+#define U2TX_PERIPH             SYSCTL_PERIPH_GPIOG
+#define U2TX_PORT               GPIO_PORTG_BASE
+#define U2TX_PIN                GPIO_PIN_1
+
+#endif // PART_LM3S6610
+
+//*****************************************************************************
+//
+// LM3S6611 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S6611
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOC
+#define C0O_PORT                GPIO_PORTC_BASE
+#define C0O_PIN                 GPIO_PIN_5
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1O_PERIPH              SYSCTL_PERIPH_GPIOE
+#define C1O_PORT                GPIO_PORTE_BASE
+#define C1O_PIN                 GPIO_PIN_6
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_5
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP1_PORT               GPIO_PORTD_BASE
+#define CCP1_PIN                GPIO_PIN_7
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_1
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP3_PORT               GPIO_PORTC_BASE
+#define CCP3_PIN                GPIO_PIN_6
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP4_PORT               GPIO_PORTC_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP5_PORT               GPIO_PORTC_BASE
+#define CCP5_PIN                GPIO_PIN_4
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define I2C1SCL_PERIPH          SYSCTL_PERIPH_GPIOA
+#define I2C1SCL_PORT            GPIO_PORTA_BASE
+#define I2C1SCL_PIN             GPIO_PIN_6
+
+#define I2C1SDA_PERIPH          SYSCTL_PERIPH_GPIOA
+#define I2C1SDA_PORT            GPIO_PORTA_BASE
+#define I2C1SDA_PIN             GPIO_PIN_7
+
+#define LED0_PERIPH             SYSCTL_PERIPH_GPIOF
+#define LED0_PORT               GPIO_PORTF_BASE
+#define LED0_PIN                GPIO_PIN_3
+
+#define LED1_PERIPH             SYSCTL_PERIPH_GPIOF
+#define LED1_PORT               GPIO_PORTF_BASE
+#define LED1_PIN                GPIO_PIN_2
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SSI1CLK_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1CLK_PORT            GPIO_PORTE_BASE
+#define SSI1CLK_PIN             GPIO_PIN_0
+
+#define SSI1FSS_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1FSS_PORT            GPIO_PORTE_BASE
+#define SSI1FSS_PIN             GPIO_PIN_1
+
+#define SSI1RX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1RX_PORT             GPIO_PORTE_BASE
+#define SSI1RX_PIN              GPIO_PIN_2
+
+#define SSI1TX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1TX_PORT             GPIO_PORTE_BASE
+#define SSI1TX_PIN              GPIO_PIN_3
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#define U2RX_PERIPH             SYSCTL_PERIPH_GPIOG
+#define U2RX_PORT               GPIO_PORTG_BASE
+#define U2RX_PIN                GPIO_PIN_0
+
+#define U2TX_PERIPH             SYSCTL_PERIPH_GPIOG
+#define U2TX_PORT               GPIO_PORTG_BASE
+#define U2TX_PIN                GPIO_PIN_1
+
+#endif // PART_LM3S6611
+
+//*****************************************************************************
+//
+// LM3S6618 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S6618
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOC
+#define C0O_PORT                GPIO_PORTC_BASE
+#define C0O_PIN                 GPIO_PIN_5
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_5
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP1_PORT               GPIO_PORTA_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_1
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP3_PORT               GPIO_PORTC_BASE
+#define CCP3_PIN                GPIO_PIN_6
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP4_PORT               GPIO_PORTC_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP5_PORT               GPIO_PORTC_BASE
+#define CCP5_PIN                GPIO_PIN_4
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define I2C1SCL_PERIPH          SYSCTL_PERIPH_GPIOG
+#define I2C1SCL_PORT            GPIO_PORTG_BASE
+#define I2C1SCL_PIN             GPIO_PIN_0
+
+#define I2C1SDA_PERIPH          SYSCTL_PERIPH_GPIOA
+#define I2C1SDA_PORT            GPIO_PORTA_BASE
+#define I2C1SDA_PIN             GPIO_PIN_7
+
+#define LED0_PERIPH             SYSCTL_PERIPH_GPIOF
+#define LED0_PORT               GPIO_PORTF_BASE
+#define LED0_PIN                GPIO_PIN_3
+
+#define LED1_PERIPH             SYSCTL_PERIPH_GPIOF
+#define LED1_PORT               GPIO_PORTF_BASE
+#define LED1_PIN                GPIO_PIN_2
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SSI1CLK_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1CLK_PORT            GPIO_PORTE_BASE
+#define SSI1CLK_PIN             GPIO_PIN_0
+
+#define SSI1FSS_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1FSS_PORT            GPIO_PORTE_BASE
+#define SSI1FSS_PIN             GPIO_PIN_1
+
+#define SSI1RX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1RX_PORT             GPIO_PORTE_BASE
+#define SSI1RX_PIN              GPIO_PIN_2
+
+#define SSI1TX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1TX_PORT             GPIO_PORTE_BASE
+#define SSI1TX_PIN              GPIO_PIN_3
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#endif // PART_LM3S6618
+
+//*****************************************************************************
+//
+// LM3S6633 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S6633
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOC
+#define C0O_PORT                GPIO_PORTC_BASE
+#define C0O_PIN                 GPIO_PIN_5
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP1_PORT               GPIO_PORTA_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_1
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP3_PORT               GPIO_PORTC_BASE
+#define CCP3_PIN                GPIO_PIN_6
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP4_PORT               GPIO_PORTA_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP5_PORT               GPIO_PORTB_BASE
+#define CCP5_PIN                GPIO_PIN_5
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define LED0_PERIPH             SYSCTL_PERIPH_GPIOF
+#define LED0_PORT               GPIO_PORTF_BASE
+#define LED0_PIN                GPIO_PIN_3
+
+#define LED1_PERIPH             SYSCTL_PERIPH_GPIOF
+#define LED1_PORT               GPIO_PORTF_BASE
+#define LED1_PIN                GPIO_PIN_2
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#endif // PART_LM3S6633
+
+//*****************************************************************************
+//
+// LM3S6637 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S6637
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOD
+#define C0O_PORT                GPIO_PORTD_BASE
+#define C0O_PIN                 GPIO_PIN_7
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1O_PERIPH              SYSCTL_PERIPH_GPIOC
+#define C1O_PORT                GPIO_PORTC_BASE
+#define C1O_PIN                 GPIO_PIN_5
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_5
+
+#define C2O_PERIPH              SYSCTL_PERIPH_GPIOC
+#define C2O_PORT                GPIO_PORTC_BASE
+#define C2O_PIN                 GPIO_PIN_6
+
+#define C2_MINUS_PERIPH         SYSCTL_PERIPH_GPIOC
+#define C2_MINUS_PORT           GPIO_PORTC_BASE
+#define C2_MINUS_PIN            GPIO_PIN_7
+
+#define C2_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C2_PLUS_PORT            GPIO_PORTC_BASE
+#define C2_PLUS_PIN             GPIO_PIN_6
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP1_PORT               GPIO_PORTA_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_1
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP3_PORT               GPIO_PORTD_BASE
+#define CCP3_PIN                GPIO_PIN_4
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP4_PORT               GPIO_PORTA_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP5_PORT               GPIO_PORTC_BASE
+#define CCP5_PIN                GPIO_PIN_4
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define LED0_PERIPH             SYSCTL_PERIPH_GPIOF
+#define LED0_PORT               GPIO_PORTF_BASE
+#define LED0_PIN                GPIO_PIN_3
+
+#define LED1_PERIPH             SYSCTL_PERIPH_GPIOF
+#define LED1_PORT               GPIO_PORTF_BASE
+#define LED1_PIN                GPIO_PIN_2
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#endif // PART_LM3S6637
+
+//*****************************************************************************
+//
+// LM3S6730 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S6730
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOD
+#define C0O_PORT                GPIO_PORTD_BASE
+#define C0O_PIN                 GPIO_PIN_7
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1O_PERIPH              SYSCTL_PERIPH_GPIOE
+#define C1O_PORT                GPIO_PORTE_BASE
+#define C1O_PIN                 GPIO_PIN_6
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_5
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP1_PORT               GPIO_PORTA_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_1
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP3_PORT               GPIO_PORTC_BASE
+#define CCP3_PIN                GPIO_PIN_6
+
+#define LED0_PERIPH             SYSCTL_PERIPH_GPIOF
+#define LED0_PORT               GPIO_PORTF_BASE
+#define LED0_PIN                GPIO_PIN_3
+
+#define LED1_PERIPH             SYSCTL_PERIPH_GPIOF
+#define LED1_PORT               GPIO_PORTF_BASE
+#define LED1_PIN                GPIO_PIN_2
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#endif // PART_LM3S6730
+
+//*****************************************************************************
+//
+// LM3S6753 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S6753
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOD
+#define C0O_PORT                GPIO_PORTD_BASE
+#define C0O_PIN                 GPIO_PIN_7
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_5
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP0_PORT               GPIO_PORTD_BASE
+#define CCP0_PIN                GPIO_PIN_4
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP1_PORT               GPIO_PORTA_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP2_PORT               GPIO_PORTD_BASE
+#define CCP2_PIN                GPIO_PIN_5
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP3_PORT               GPIO_PORTC_BASE
+#define CCP3_PIN                GPIO_PIN_6
+
+#define FAULT_PERIPH            SYSCTL_PERIPH_GPIOD
+#define FAULT_PORT              GPIO_PORTD_BASE
+#define FAULT_PIN               GPIO_PIN_6
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define IDX0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define IDX0_PORT               GPIO_PORTD_BASE
+#define IDX0_PIN                GPIO_PIN_0
+
+#define LED0_PERIPH             SYSCTL_PERIPH_GPIOF
+#define LED0_PORT               GPIO_PORTF_BASE
+#define LED0_PIN                GPIO_PIN_3
+
+#define LED1_PERIPH             SYSCTL_PERIPH_GPIOF
+#define LED1_PORT               GPIO_PORTF_BASE
+#define LED1_PIN                GPIO_PIN_2
+
+#define PHA0_PERIPH             SYSCTL_PERIPH_GPIOC
+#define PHA0_PORT               GPIO_PORTC_BASE
+#define PHA0_PIN                GPIO_PIN_4
+
+#define PHB0_PERIPH             SYSCTL_PERIPH_GPIOC
+#define PHB0_PORT               GPIO_PORTC_BASE
+#define PHB0_PIN                GPIO_PIN_7
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOF
+#define PWM0_PORT               GPIO_PORTF_BASE
+#define PWM0_PIN                GPIO_PIN_0
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM1_PORT               GPIO_PORTD_BASE
+#define PWM1_PIN                GPIO_PIN_1
+
+#define PWM2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define PWM2_PORT               GPIO_PORTB_BASE
+#define PWM2_PIN                GPIO_PIN_0
+
+#define PWM3_PERIPH             SYSCTL_PERIPH_GPIOB
+#define PWM3_PORT               GPIO_PORTB_BASE
+#define PWM3_PIN                GPIO_PIN_1
+
+#define PWM4_PERIPH             SYSCTL_PERIPH_GPIOE
+#define PWM4_PORT               GPIO_PORTE_BASE
+#define PWM4_PIN                GPIO_PIN_0
+
+#define PWM5_PERIPH             SYSCTL_PERIPH_GPIOE
+#define PWM5_PORT               GPIO_PORTE_BASE
+#define PWM5_PIN                GPIO_PIN_1
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#endif // PART_LM3S6753
+
+//*****************************************************************************
+//
+// LM3S6816 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S6816
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP1_PORT               GPIO_PORTA_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_1
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP3_PORT               GPIO_PORTC_BASE
+#define CCP3_PIN                GPIO_PIN_6
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP4_PORT               GPIO_PORTA_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP5_PORT               GPIO_PORTB_BASE
+#define CCP5_PIN                GPIO_PIN_5
+
+#define FAULT_PERIPH            SYSCTL_PERIPH_GPIOE
+#define FAULT_PORT              GPIO_PORTE_BASE
+#define FAULT_PIN               GPIO_PIN_1
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define LED0_PERIPH             SYSCTL_PERIPH_GPIOF
+#define LED0_PORT               GPIO_PORTF_BASE
+#define LED0_PIN                GPIO_PIN_3
+
+#define LED1_PERIPH             SYSCTL_PERIPH_GPIOF
+#define LED1_PORT               GPIO_PORTF_BASE
+#define LED1_PIN                GPIO_PIN_2
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM0_PORT               GPIO_PORTD_BASE
+#define PWM0_PIN                GPIO_PIN_0
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM1_PORT               GPIO_PORTD_BASE
+#define PWM1_PIN                GPIO_PIN_1
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#define U2RX_PERIPH             SYSCTL_PERIPH_GPIOG
+#define U2RX_PORT               GPIO_PORTG_BASE
+#define U2RX_PIN                GPIO_PIN_0
+
+#define U2TX_PERIPH             SYSCTL_PERIPH_GPIOG
+#define U2TX_PORT               GPIO_PORTG_BASE
+#define U2TX_PIN                GPIO_PIN_1
+
+#endif // PART_LM3S6816
+
+//*****************************************************************************
+//
+// LM3S6911 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S6911
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOC
+#define C0O_PORT                GPIO_PORTC_BASE
+#define C0O_PIN                 GPIO_PIN_5
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1O_PERIPH              SYSCTL_PERIPH_GPIOE
+#define C1O_PORT                GPIO_PORTE_BASE
+#define C1O_PIN                 GPIO_PIN_6
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_5
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP1_PORT               GPIO_PORTD_BASE
+#define CCP1_PIN                GPIO_PIN_7
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_1
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP3_PORT               GPIO_PORTC_BASE
+#define CCP3_PIN                GPIO_PIN_6
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP4_PORT               GPIO_PORTC_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP5_PORT               GPIO_PORTC_BASE
+#define CCP5_PIN                GPIO_PIN_4
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define I2C1SCL_PERIPH          SYSCTL_PERIPH_GPIOA
+#define I2C1SCL_PORT            GPIO_PORTA_BASE
+#define I2C1SCL_PIN             GPIO_PIN_6
+
+#define I2C1SDA_PERIPH          SYSCTL_PERIPH_GPIOA
+#define I2C1SDA_PORT            GPIO_PORTA_BASE
+#define I2C1SDA_PIN             GPIO_PIN_7
+
+#define LED0_PERIPH             SYSCTL_PERIPH_GPIOF
+#define LED0_PORT               GPIO_PORTF_BASE
+#define LED0_PIN                GPIO_PIN_3
+
+#define LED1_PERIPH             SYSCTL_PERIPH_GPIOF
+#define LED1_PORT               GPIO_PORTF_BASE
+#define LED1_PIN                GPIO_PIN_2
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SSI1CLK_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1CLK_PORT            GPIO_PORTE_BASE
+#define SSI1CLK_PIN             GPIO_PIN_0
+
+#define SSI1FSS_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1FSS_PORT            GPIO_PORTE_BASE
+#define SSI1FSS_PIN             GPIO_PIN_1
+
+#define SSI1RX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1RX_PORT             GPIO_PORTE_BASE
+#define SSI1RX_PIN              GPIO_PIN_2
+
+#define SSI1TX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1TX_PORT             GPIO_PORTE_BASE
+#define SSI1TX_PIN              GPIO_PIN_3
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#define U2RX_PERIPH             SYSCTL_PERIPH_GPIOG
+#define U2RX_PORT               GPIO_PORTG_BASE
+#define U2RX_PIN                GPIO_PIN_0
+
+#define U2TX_PERIPH             SYSCTL_PERIPH_GPIOG
+#define U2TX_PORT               GPIO_PORTG_BASE
+#define U2TX_PIN                GPIO_PIN_1
+
+#endif // PART_LM3S6911
+
+//*****************************************************************************
+//
+// LM3S6916 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S6916
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP1_PORT               GPIO_PORTA_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_1
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP3_PORT               GPIO_PORTC_BASE
+#define CCP3_PIN                GPIO_PIN_6
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP4_PORT               GPIO_PORTA_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP5_PORT               GPIO_PORTB_BASE
+#define CCP5_PIN                GPIO_PIN_5
+
+#define FAULT_PERIPH            SYSCTL_PERIPH_GPIOE
+#define FAULT_PORT              GPIO_PORTE_BASE
+#define FAULT_PIN               GPIO_PIN_1
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define LED0_PERIPH             SYSCTL_PERIPH_GPIOF
+#define LED0_PORT               GPIO_PORTF_BASE
+#define LED0_PIN                GPIO_PIN_3
+
+#define LED1_PERIPH             SYSCTL_PERIPH_GPIOF
+#define LED1_PORT               GPIO_PORTF_BASE
+#define LED1_PIN                GPIO_PIN_2
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM0_PORT               GPIO_PORTD_BASE
+#define PWM0_PIN                GPIO_PIN_0
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM1_PORT               GPIO_PORTD_BASE
+#define PWM1_PIN                GPIO_PIN_1
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#define U2RX_PERIPH             SYSCTL_PERIPH_GPIOG
+#define U2RX_PORT               GPIO_PORTG_BASE
+#define U2RX_PIN                GPIO_PIN_0
+
+#define U2TX_PERIPH             SYSCTL_PERIPH_GPIOG
+#define U2TX_PORT               GPIO_PORTG_BASE
+#define U2TX_PIN                GPIO_PIN_1
+
+#endif // PART_LM3S6916
+
+//*****************************************************************************
+//
+// LM3S6918 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S6918
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOC
+#define C0O_PORT                GPIO_PORTC_BASE
+#define C0O_PIN                 GPIO_PIN_5
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_5
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP1_PORT               GPIO_PORTA_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_1
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP3_PORT               GPIO_PORTC_BASE
+#define CCP3_PIN                GPIO_PIN_6
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP4_PORT               GPIO_PORTC_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP5_PORT               GPIO_PORTC_BASE
+#define CCP5_PIN                GPIO_PIN_4
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define I2C1SCL_PERIPH          SYSCTL_PERIPH_GPIOG
+#define I2C1SCL_PORT            GPIO_PORTG_BASE
+#define I2C1SCL_PIN             GPIO_PIN_0
+
+#define I2C1SDA_PERIPH          SYSCTL_PERIPH_GPIOA
+#define I2C1SDA_PORT            GPIO_PORTA_BASE
+#define I2C1SDA_PIN             GPIO_PIN_7
+
+#define LED0_PERIPH             SYSCTL_PERIPH_GPIOF
+#define LED0_PORT               GPIO_PORTF_BASE
+#define LED0_PIN                GPIO_PIN_3
+
+#define LED1_PERIPH             SYSCTL_PERIPH_GPIOF
+#define LED1_PORT               GPIO_PORTF_BASE
+#define LED1_PIN                GPIO_PIN_2
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SSI1CLK_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1CLK_PORT            GPIO_PORTE_BASE
+#define SSI1CLK_PIN             GPIO_PIN_0
+
+#define SSI1FSS_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1FSS_PORT            GPIO_PORTE_BASE
+#define SSI1FSS_PIN             GPIO_PIN_1
+
+#define SSI1RX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1RX_PORT             GPIO_PORTE_BASE
+#define SSI1RX_PIN              GPIO_PIN_2
+
+#define SSI1TX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1TX_PORT             GPIO_PORTE_BASE
+#define SSI1TX_PIN              GPIO_PIN_3
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#endif // PART_LM3S6918
+
+//*****************************************************************************
+//
+// LM3S6938 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S6938
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOB
+#define C0O_PORT                GPIO_PORTB_BASE
+#define C0O_PIN                 GPIO_PIN_6
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1O_PERIPH              SYSCTL_PERIPH_GPIOC
+#define C1O_PORT                GPIO_PORTC_BASE
+#define C1O_PIN                 GPIO_PIN_5
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_5
+
+#define C2_MINUS_PERIPH         SYSCTL_PERIPH_GPIOC
+#define C2_MINUS_PORT           GPIO_PORTC_BASE
+#define C2_MINUS_PIN            GPIO_PIN_7
+
+#define C2_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C2_PLUS_PORT            GPIO_PORTC_BASE
+#define C2_PLUS_PIN             GPIO_PIN_6
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP1_PORT               GPIO_PORTA_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_1
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOE
+#define CCP3_PORT               GPIO_PORTE_BASE
+#define CCP3_PIN                GPIO_PIN_0
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP4_PORT               GPIO_PORTA_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP5_PORT               GPIO_PORTC_BASE
+#define CCP5_PIN                GPIO_PIN_4
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define LED0_PERIPH             SYSCTL_PERIPH_GPIOF
+#define LED0_PORT               GPIO_PORTF_BASE
+#define LED0_PIN                GPIO_PIN_3
+
+#define LED1_PERIPH             SYSCTL_PERIPH_GPIOF
+#define LED1_PORT               GPIO_PORTF_BASE
+#define LED1_PIN                GPIO_PIN_2
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#define U2RX_PERIPH             SYSCTL_PERIPH_GPIOG
+#define U2RX_PORT               GPIO_PORTG_BASE
+#define U2RX_PIN                GPIO_PIN_0
+
+#define U2TX_PERIPH             SYSCTL_PERIPH_GPIOG
+#define U2TX_PORT               GPIO_PORTG_BASE
+#define U2TX_PIN                GPIO_PIN_1
+
+#endif // PART_LM3S6938
+
+//*****************************************************************************
+//
+// LM3S6950 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S6950
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOB
+#define C0O_PORT                GPIO_PORTB_BASE
+#define C0O_PIN                 GPIO_PIN_6
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1O_PERIPH              SYSCTL_PERIPH_GPIOC
+#define C1O_PORT                GPIO_PORTC_BASE
+#define C1O_PIN                 GPIO_PIN_5
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_5
+
+#define C2O_PERIPH              SYSCTL_PERIPH_GPIOC
+#define C2O_PORT                GPIO_PORTC_BASE
+#define C2O_PIN                 GPIO_PIN_6
+
+#define C2_MINUS_PERIPH         SYSCTL_PERIPH_GPIOC
+#define C2_MINUS_PORT           GPIO_PORTC_BASE
+#define C2_MINUS_PIN            GPIO_PIN_7
+
+#define C2_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C2_PLUS_PORT            GPIO_PORTC_BASE
+#define C2_PLUS_PIN             GPIO_PIN_6
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP0_PORT               GPIO_PORTD_BASE
+#define CCP0_PIN                GPIO_PIN_4
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP1_PORT               GPIO_PORTA_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP2_PORT               GPIO_PORTD_BASE
+#define CCP2_PIN                GPIO_PIN_5
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOE
+#define CCP3_PORT               GPIO_PORTE_BASE
+#define CCP3_PIN                GPIO_PIN_4
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP4_PORT               GPIO_PORTA_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP5_PORT               GPIO_PORTC_BASE
+#define CCP5_PIN                GPIO_PIN_4
+
+#define FAULT_PERIPH            SYSCTL_PERIPH_GPIOD
+#define FAULT_PORT              GPIO_PORTD_BASE
+#define FAULT_PIN               GPIO_PIN_6
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define IDX0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define IDX0_PORT               GPIO_PORTD_BASE
+#define IDX0_PIN                GPIO_PIN_7
+
+#define LED0_PERIPH             SYSCTL_PERIPH_GPIOF
+#define LED0_PORT               GPIO_PORTF_BASE
+#define LED0_PIN                GPIO_PIN_3
+
+#define LED1_PERIPH             SYSCTL_PERIPH_GPIOF
+#define LED1_PORT               GPIO_PORTF_BASE
+#define LED1_PIN                GPIO_PIN_2
+
+#define PHA0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PHA0_PORT               GPIO_PORTD_BASE
+#define PHA0_PIN                GPIO_PIN_1
+
+#define PHB0_PERIPH             SYSCTL_PERIPH_GPIOF
+#define PHB0_PORT               GPIO_PORTF_BASE
+#define PHB0_PIN                GPIO_PIN_0
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM0_PORT               GPIO_PORTD_BASE
+#define PWM0_PIN                GPIO_PIN_0
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOF
+#define PWM1_PORT               GPIO_PORTF_BASE
+#define PWM1_PIN                GPIO_PIN_1
+
+#define PWM2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define PWM2_PORT               GPIO_PORTB_BASE
+#define PWM2_PIN                GPIO_PIN_0
+
+#define PWM3_PERIPH             SYSCTL_PERIPH_GPIOB
+#define PWM3_PORT               GPIO_PORTB_BASE
+#define PWM3_PIN                GPIO_PIN_1
+
+#define PWM4_PERIPH             SYSCTL_PERIPH_GPIOE
+#define PWM4_PORT               GPIO_PORTE_BASE
+#define PWM4_PIN                GPIO_PIN_6
+
+#define PWM5_PERIPH             SYSCTL_PERIPH_GPIOE
+#define PWM5_PORT               GPIO_PORTE_BASE
+#define PWM5_PIN                GPIO_PIN_7
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SSI1CLK_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1CLK_PORT            GPIO_PORTE_BASE
+#define SSI1CLK_PIN             GPIO_PIN_0
+
+#define SSI1FSS_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1FSS_PORT            GPIO_PORTE_BASE
+#define SSI1FSS_PIN             GPIO_PIN_1
+
+#define SSI1RX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1RX_PORT             GPIO_PORTE_BASE
+#define SSI1RX_PIN              GPIO_PIN_2
+
+#define SSI1TX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1TX_PORT             GPIO_PORTE_BASE
+#define SSI1TX_PIN              GPIO_PIN_3
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#define U2RX_PERIPH             SYSCTL_PERIPH_GPIOG
+#define U2RX_PORT               GPIO_PORTG_BASE
+#define U2RX_PIN                GPIO_PIN_0
+
+#define U2TX_PERIPH             SYSCTL_PERIPH_GPIOG
+#define U2TX_PORT               GPIO_PORTG_BASE
+#define U2TX_PIN                GPIO_PIN_1
+
+#endif // PART_LM3S6950
+
+//*****************************************************************************
+//
+// LM3S6952 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S6952
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOB
+#define C0O_PORT                GPIO_PORTB_BASE
+#define C0O_PIN                 GPIO_PIN_6
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1O_PERIPH              SYSCTL_PERIPH_GPIOC
+#define C1O_PORT                GPIO_PORTC_BASE
+#define C1O_PIN                 GPIO_PIN_5
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_5
+
+#define C2_MINUS_PERIPH         SYSCTL_PERIPH_GPIOC
+#define C2_MINUS_PORT           GPIO_PORTC_BASE
+#define C2_MINUS_PIN            GPIO_PIN_7
+
+#define C2_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C2_PLUS_PORT            GPIO_PORTC_BASE
+#define C2_PLUS_PIN             GPIO_PIN_6
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP0_PORT               GPIO_PORTD_BASE
+#define CCP0_PIN                GPIO_PIN_4
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP1_PORT               GPIO_PORTA_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP2_PORT               GPIO_PORTD_BASE
+#define CCP2_PIN                GPIO_PIN_5
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOE
+#define CCP3_PORT               GPIO_PORTE_BASE
+#define CCP3_PIN                GPIO_PIN_0
+
+#define FAULT_PERIPH            SYSCTL_PERIPH_GPIOD
+#define FAULT_PORT              GPIO_PORTD_BASE
+#define FAULT_PIN               GPIO_PIN_6
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define IDX0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define IDX0_PORT               GPIO_PORTD_BASE
+#define IDX0_PIN                GPIO_PIN_7
+
+#define LED0_PERIPH             SYSCTL_PERIPH_GPIOF
+#define LED0_PORT               GPIO_PORTF_BASE
+#define LED0_PIN                GPIO_PIN_3
+
+#define LED1_PERIPH             SYSCTL_PERIPH_GPIOF
+#define LED1_PORT               GPIO_PORTF_BASE
+#define LED1_PIN                GPIO_PIN_2
+
+#define PHA0_PERIPH             SYSCTL_PERIPH_GPIOC
+#define PHA0_PORT               GPIO_PORTC_BASE
+#define PHA0_PIN                GPIO_PIN_4
+
+#define PHB0_PERIPH             SYSCTL_PERIPH_GPIOF
+#define PHB0_PORT               GPIO_PORTF_BASE
+#define PHB0_PIN                GPIO_PIN_0
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM0_PORT               GPIO_PORTD_BASE
+#define PWM0_PIN                GPIO_PIN_0
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM1_PORT               GPIO_PORTD_BASE
+#define PWM1_PIN                GPIO_PIN_1
+
+#define PWM2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define PWM2_PORT               GPIO_PORTB_BASE
+#define PWM2_PIN                GPIO_PIN_0
+
+#define PWM3_PERIPH             SYSCTL_PERIPH_GPIOB
+#define PWM3_PORT               GPIO_PORTB_BASE
+#define PWM3_PIN                GPIO_PIN_1
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#define U2RX_PERIPH             SYSCTL_PERIPH_GPIOG
+#define U2RX_PORT               GPIO_PORTG_BASE
+#define U2RX_PIN                GPIO_PIN_0
+
+#define U2TX_PERIPH             SYSCTL_PERIPH_GPIOG
+#define U2TX_PORT               GPIO_PORTG_BASE
+#define U2TX_PIN                GPIO_PIN_1
+
+#endif // PART_LM3S6952
+
+//*****************************************************************************
+//
+// LM3S6965 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S6965
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOC
+#define C0O_PORT                GPIO_PORTC_BASE
+#define C0O_PIN                 GPIO_PIN_5
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_5
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP0_PORT               GPIO_PORTD_BASE
+#define CCP0_PIN                GPIO_PIN_4
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP1_PORT               GPIO_PORTD_BASE
+#define CCP1_PIN                GPIO_PIN_7
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP2_PORT               GPIO_PORTD_BASE
+#define CCP2_PIN                GPIO_PIN_5
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP3_PORT               GPIO_PORTC_BASE
+#define CCP3_PIN                GPIO_PIN_6
+
+#define FAULT_PERIPH            SYSCTL_PERIPH_GPIOD
+#define FAULT_PORT              GPIO_PORTD_BASE
+#define FAULT_PIN               GPIO_PIN_6
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define I2C1SCL_PERIPH          SYSCTL_PERIPH_GPIOA
+#define I2C1SCL_PORT            GPIO_PORTA_BASE
+#define I2C1SCL_PIN             GPIO_PIN_6
+
+#define I2C1SDA_PERIPH          SYSCTL_PERIPH_GPIOA
+#define I2C1SDA_PORT            GPIO_PORTA_BASE
+#define I2C1SDA_PIN             GPIO_PIN_7
+
+#define IDX0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define IDX0_PORT               GPIO_PORTD_BASE
+#define IDX0_PIN                GPIO_PIN_0
+
+#define IDX1_PERIPH             SYSCTL_PERIPH_GPIOF
+#define IDX1_PORT               GPIO_PORTF_BASE
+#define IDX1_PIN                GPIO_PIN_1
+
+#define LED0_PERIPH             SYSCTL_PERIPH_GPIOF
+#define LED0_PORT               GPIO_PORTF_BASE
+#define LED0_PIN                GPIO_PIN_3
+
+#define LED1_PERIPH             SYSCTL_PERIPH_GPIOF
+#define LED1_PORT               GPIO_PORTF_BASE
+#define LED1_PIN                GPIO_PIN_2
+
+#define PHA0_PERIPH             SYSCTL_PERIPH_GPIOC
+#define PHA0_PORT               GPIO_PORTC_BASE
+#define PHA0_PIN                GPIO_PIN_4
+
+#define PHA1_PERIPH             SYSCTL_PERIPH_GPIOE
+#define PHA1_PORT               GPIO_PORTE_BASE
+#define PHA1_PIN                GPIO_PIN_3
+
+#define PHB0_PERIPH             SYSCTL_PERIPH_GPIOC
+#define PHB0_PORT               GPIO_PORTC_BASE
+#define PHB0_PIN                GPIO_PIN_7
+
+#define PHB1_PERIPH             SYSCTL_PERIPH_GPIOE
+#define PHB1_PORT               GPIO_PORTE_BASE
+#define PHB1_PIN                GPIO_PIN_2
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOF
+#define PWM0_PORT               GPIO_PORTF_BASE
+#define PWM0_PIN                GPIO_PIN_0
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM1_PORT               GPIO_PORTD_BASE
+#define PWM1_PIN                GPIO_PIN_1
+
+#define PWM2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define PWM2_PORT               GPIO_PORTB_BASE
+#define PWM2_PIN                GPIO_PIN_0
+
+#define PWM3_PERIPH             SYSCTL_PERIPH_GPIOB
+#define PWM3_PORT               GPIO_PORTB_BASE
+#define PWM3_PIN                GPIO_PIN_1
+
+#define PWM4_PERIPH             SYSCTL_PERIPH_GPIOE
+#define PWM4_PORT               GPIO_PORTE_BASE
+#define PWM4_PIN                GPIO_PIN_0
+
+#define PWM5_PERIPH             SYSCTL_PERIPH_GPIOE
+#define PWM5_PORT               GPIO_PORTE_BASE
+#define PWM5_PIN                GPIO_PIN_1
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#define U2RX_PERIPH             SYSCTL_PERIPH_GPIOG
+#define U2RX_PORT               GPIO_PORTG_BASE
+#define U2RX_PIN                GPIO_PIN_0
+
+#define U2TX_PERIPH             SYSCTL_PERIPH_GPIOG
+#define U2TX_PORT               GPIO_PORTG_BASE
+#define U2TX_PIN                GPIO_PIN_1
+
+#endif // PART_LM3S6965
+
+//*****************************************************************************
+//
+// LM3S6C11 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S6C11
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+
+#define GPIO_PA4_SSI0RX         0x00001001
+
+#define GPIO_PA5_SSI0TX         0x00001401
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_CCP3           0x00001C07
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_U1RX           0x00011007
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_CCP5           0x00011806
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_CCP3           0x00021405
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_C1O            0x00021C07
+
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_CCP2           0x0003040A
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_CCP5           0x00030804
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_CCP0           0x00030C04
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_U2RX           0x00031409
+
+#define GPIO_PD6_U2TX           0x00031809
+
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_CCP2           0x00040805
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_CCP7           0x00040C05
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+
+#define GPIO_PE5_CCP5           0x00041401
+
+#define GPIO_PE6_C1O            0x00041802
+
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_LED1           0x00050801
+#define GPIO_PF2_SSI1CLK        0x00050809
+
+#define GPIO_PF3_LED0           0x00050C01
+#define GPIO_PF3_SSI1FSS        0x00050C09
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_I2C1SCL        0x00060003
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_I2C1SDA        0x00060403
+
+#endif // PART_LM3S6C11
+
+//*****************************************************************************
+//
+// LM3S6C65 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S6C65
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_PWM4           0x00000804
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_PWM5           0x00000C04
+
+#define GPIO_PA4_SSI0RX         0x00001001
+
+#define GPIO_PA5_SSI0TX         0x00001401
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_PWM0           0x00001804
+#define GPIO_PA6_PWM4           0x00001805
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_PWM1           0x00001C04
+#define GPIO_PA7_PWM5           0x00001C05
+#define GPIO_PA7_CCP3           0x00001C07
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_PWM2           0x00010002
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_PWM3           0x00010402
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_IDX0           0x00010802
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_FAULT0         0x00010C02
+#define GPIO_PB3_FAULT3         0x00010C04
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_IDX0           0x00011006
+#define GPIO_PB4_U1RX           0x00011007
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_FAULT1         0x00011804
+#define GPIO_PB6_IDX0           0x00011805
+#define GPIO_PB6_CCP5           0x00011806
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_PHA0           0x00021002
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_FAULT2         0x00021404
+#define GPIO_PC5_CCP3           0x00021405
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_PHB0           0x00021802
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_PHB0           0x00021C02
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_C1O            0x00021C07
+
+#define GPIO_PD0_PWM0           0x00030001
+#define GPIO_PD0_IDX0           0x00030003
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+
+#define GPIO_PD1_PWM1           0x00030401
+#define GPIO_PD1_PHA0           0x00030403
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_CCP2           0x0003040A
+#define GPIO_PD1_PHB1           0x0003040B
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_PWM2           0x00030803
+#define GPIO_PD2_CCP5           0x00030804
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_PWM3           0x00030C03
+#define GPIO_PD3_CCP0           0x00030C04
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_U2RX           0x00031409
+
+#define GPIO_PD6_FAULT0         0x00031801
+#define GPIO_PD6_U2TX           0x00031809
+
+#define GPIO_PD7_IDX0           0x00031C01
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+
+#define GPIO_PE0_PWM4           0x00040001
+#define GPIO_PE0_CCP3           0x00040003
+
+#define GPIO_PE1_PWM5           0x00040401
+#define GPIO_PE1_FAULT0         0x00040403
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_PHB1           0x00040803
+#define GPIO_PE2_PHA0           0x00040804
+#define GPIO_PE2_CCP2           0x00040805
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_PHA1           0x00040C03
+#define GPIO_PE3_PHB0           0x00040C04
+#define GPIO_PE3_CCP7           0x00040C05
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_FAULT0         0x00041004
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+
+#define GPIO_PE5_CCP5           0x00041401
+
+#define GPIO_PE6_PWM4           0x00041801
+#define GPIO_PE6_C1O            0x00041802
+
+#define GPIO_PE7_PWM5           0x00041C01
+
+#define GPIO_PF0_PHB0           0x00050002
+#define GPIO_PF0_PWM0           0x00050003
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_IDX1           0x00050402
+#define GPIO_PF1_PWM1           0x00050403
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_LED1           0x00050801
+#define GPIO_PF2_PWM4           0x00050802
+#define GPIO_PF2_PWM2           0x00050804
+
+#define GPIO_PF3_LED0           0x00050C01
+#define GPIO_PF3_PWM5           0x00050C02
+#define GPIO_PF3_PWM3           0x00050C04
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_PWM0           0x00060002
+#define GPIO_PG0_I2C1SCL        0x00060003
+#define GPIO_PG0_PWM4           0x00060004
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_PWM1           0x00060402
+#define GPIO_PG1_I2C1SDA        0x00060403
+#define GPIO_PG1_PWM5           0x00060404
+
+#endif // PART_LM3S6C65
+
+//*****************************************************************************
+//
+// LM3S6G11 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S6G11
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+
+#define GPIO_PA4_SSI0RX         0x00001001
+
+#define GPIO_PA5_SSI0TX         0x00001401
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_CCP3           0x00001C07
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_U1RX           0x00011007
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_CCP5           0x00011806
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_CCP3           0x00021405
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_C1O            0x00021C07
+
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_CCP2           0x0003040A
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_CCP5           0x00030804
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_CCP0           0x00030C04
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_U2RX           0x00031409
+
+#define GPIO_PD6_U2TX           0x00031809
+
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_CCP2           0x00040805
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_CCP7           0x00040C05
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+
+#define GPIO_PE5_CCP5           0x00041401
+
+#define GPIO_PE6_C1O            0x00041802
+
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_LED1           0x00050801
+#define GPIO_PF2_SSI1CLK        0x00050809
+
+#define GPIO_PF3_LED0           0x00050C01
+#define GPIO_PF3_SSI1FSS        0x00050C09
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_I2C1SCL        0x00060003
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_I2C1SDA        0x00060403
+
+#endif // PART_LM3S6G11
+
+//*****************************************************************************
+//
+// LM3S6G65 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S6G65
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_PWM4           0x00000804
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_PWM5           0x00000C04
+
+#define GPIO_PA4_SSI0RX         0x00001001
+
+#define GPIO_PA5_SSI0TX         0x00001401
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_PWM0           0x00001804
+#define GPIO_PA6_PWM4           0x00001805
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_PWM1           0x00001C04
+#define GPIO_PA7_PWM5           0x00001C05
+#define GPIO_PA7_CCP3           0x00001C07
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_PWM2           0x00010002
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_PWM3           0x00010402
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_IDX0           0x00010802
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_FAULT0         0x00010C02
+#define GPIO_PB3_FAULT3         0x00010C04
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_IDX0           0x00011006
+#define GPIO_PB4_U1RX           0x00011007
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_FAULT1         0x00011804
+#define GPIO_PB6_IDX0           0x00011805
+#define GPIO_PB6_CCP5           0x00011806
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_PHA0           0x00021002
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_FAULT2         0x00021404
+#define GPIO_PC5_CCP3           0x00021405
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_PHB0           0x00021802
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_PHB0           0x00021C02
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_C1O            0x00021C07
+
+#define GPIO_PD0_PWM0           0x00030001
+#define GPIO_PD0_IDX0           0x00030003
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+
+#define GPIO_PD1_PWM1           0x00030401
+#define GPIO_PD1_PHA0           0x00030403
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_CCP2           0x0003040A
+#define GPIO_PD1_PHB1           0x0003040B
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_PWM2           0x00030803
+#define GPIO_PD2_CCP5           0x00030804
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_PWM3           0x00030C03
+#define GPIO_PD3_CCP0           0x00030C04
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_U2RX           0x00031409
+
+#define GPIO_PD6_FAULT0         0x00031801
+#define GPIO_PD6_U2TX           0x00031809
+
+#define GPIO_PD7_IDX0           0x00031C01
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+
+#define GPIO_PE0_PWM4           0x00040001
+#define GPIO_PE0_CCP3           0x00040003
+
+#define GPIO_PE1_PWM5           0x00040401
+#define GPIO_PE1_FAULT0         0x00040403
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_PHB1           0x00040803
+#define GPIO_PE2_PHA0           0x00040804
+#define GPIO_PE2_CCP2           0x00040805
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_PHA1           0x00040C03
+#define GPIO_PE3_PHB0           0x00040C04
+#define GPIO_PE3_CCP7           0x00040C05
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_FAULT0         0x00041004
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+
+#define GPIO_PE5_CCP5           0x00041401
+
+#define GPIO_PE6_PWM4           0x00041801
+#define GPIO_PE6_C1O            0x00041802
+
+#define GPIO_PE7_PWM5           0x00041C01
+
+#define GPIO_PF0_PHB0           0x00050002
+#define GPIO_PF0_PWM0           0x00050003
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_IDX1           0x00050402
+#define GPIO_PF1_PWM1           0x00050403
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_LED1           0x00050801
+#define GPIO_PF2_PWM4           0x00050802
+#define GPIO_PF2_PWM2           0x00050804
+
+#define GPIO_PF3_LED0           0x00050C01
+#define GPIO_PF3_PWM5           0x00050C02
+#define GPIO_PF3_PWM3           0x00050C04
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_PWM0           0x00060002
+#define GPIO_PG0_I2C1SCL        0x00060003
+#define GPIO_PG0_PWM4           0x00060004
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_PWM1           0x00060402
+#define GPIO_PG1_I2C1SDA        0x00060403
+#define GPIO_PG1_PWM5           0x00060404
+
+#endif // PART_LM3S6G65
+
+//*****************************************************************************
+//
+// LM3S8530 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S8530
+
+#define CAN0RX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0RX_PORT             GPIO_PORTD_BASE
+#define CAN0RX_PIN              GPIO_PIN_0
+
+#define CAN0TX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0TX_PORT             GPIO_PORTD_BASE
+#define CAN0TX_PIN              GPIO_PIN_1
+
+#define CAN1RX_PERIPH           SYSCTL_PERIPH_GPIOF
+#define CAN1RX_PORT             GPIO_PORTF_BASE
+#define CAN1RX_PIN              GPIO_PIN_0
+
+#define CAN1TX_PERIPH           SYSCTL_PERIPH_GPIOF
+#define CAN1TX_PORT             GPIO_PORTF_BASE
+#define CAN1TX_PIN              GPIO_PIN_1
+
+#define CAN2RX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define CAN2RX_PORT             GPIO_PORTE_BASE
+#define CAN2RX_PIN              GPIO_PIN_4
+
+#define CAN2TX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define CAN2TX_PORT             GPIO_PORTE_BASE
+#define CAN2TX_PIN              GPIO_PIN_5
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP1_PORT               GPIO_PORTA_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define LED0_PERIPH             SYSCTL_PERIPH_GPIOF
+#define LED0_PORT               GPIO_PORTF_BASE
+#define LED0_PIN                GPIO_PIN_3
+
+#define LED1_PERIPH             SYSCTL_PERIPH_GPIOF
+#define LED1_PORT               GPIO_PORTF_BASE
+#define LED1_PIN                GPIO_PIN_2
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SSI1CLK_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1CLK_PORT            GPIO_PORTE_BASE
+#define SSI1CLK_PIN             GPIO_PIN_0
+
+#define SSI1FSS_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1FSS_PORT            GPIO_PORTE_BASE
+#define SSI1FSS_PIN             GPIO_PIN_1
+
+#define SSI1RX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1RX_PORT             GPIO_PORTE_BASE
+#define SSI1RX_PIN              GPIO_PIN_2
+
+#define SSI1TX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1TX_PORT             GPIO_PORTE_BASE
+#define SSI1TX_PIN              GPIO_PIN_3
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#endif // PART_LM3S8530
+
+//*****************************************************************************
+//
+// LM3S8538 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S8538
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOB
+#define C0O_PORT                GPIO_PORTB_BASE
+#define C0O_PIN                 GPIO_PIN_6
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1O_PERIPH              SYSCTL_PERIPH_GPIOC
+#define C1O_PORT                GPIO_PORTC_BASE
+#define C1O_PIN                 GPIO_PIN_5
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_5
+
+#define C2_MINUS_PERIPH         SYSCTL_PERIPH_GPIOC
+#define C2_MINUS_PORT           GPIO_PORTC_BASE
+#define C2_MINUS_PIN            GPIO_PIN_7
+
+#define C2_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C2_PLUS_PORT            GPIO_PORTC_BASE
+#define C2_PLUS_PIN             GPIO_PIN_6
+
+#define CAN0RX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0RX_PORT             GPIO_PORTD_BASE
+#define CAN0RX_PIN              GPIO_PIN_0
+
+#define CAN0TX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0TX_PORT             GPIO_PORTD_BASE
+#define CAN0TX_PIN              GPIO_PIN_1
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP1_PORT               GPIO_PORTA_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_1
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOE
+#define CCP3_PORT               GPIO_PORTE_BASE
+#define CCP3_PIN                GPIO_PIN_0
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define LED0_PERIPH             SYSCTL_PERIPH_GPIOF
+#define LED0_PORT               GPIO_PORTF_BASE
+#define LED0_PIN                GPIO_PIN_3
+
+#define LED1_PERIPH             SYSCTL_PERIPH_GPIOF
+#define LED1_PORT               GPIO_PORTF_BASE
+#define LED1_PIN                GPIO_PIN_2
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#endif // PART_LM3S8538
+
+//*****************************************************************************
+//
+// LM3S8630 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S8630
+
+#define CAN0RX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0RX_PORT             GPIO_PORTD_BASE
+#define CAN0RX_PIN              GPIO_PIN_0
+
+#define CAN0TX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0TX_PORT             GPIO_PORTD_BASE
+#define CAN0TX_PIN              GPIO_PIN_1
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP1_PORT               GPIO_PORTA_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define LED0_PERIPH             SYSCTL_PERIPH_GPIOF
+#define LED0_PORT               GPIO_PORTF_BASE
+#define LED0_PIN                GPIO_PIN_3
+
+#define LED1_PERIPH             SYSCTL_PERIPH_GPIOF
+#define LED1_PORT               GPIO_PORTF_BASE
+#define LED1_PIN                GPIO_PIN_2
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#endif // PART_LM3S8630
+
+//*****************************************************************************
+//
+// LM3S8730 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S8730
+
+#define CAN0RX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0RX_PORT             GPIO_PORTD_BASE
+#define CAN0RX_PIN              GPIO_PIN_0
+
+#define CAN0TX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0TX_PORT             GPIO_PORTD_BASE
+#define CAN0TX_PIN              GPIO_PIN_1
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP1_PORT               GPIO_PORTA_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define LED0_PERIPH             SYSCTL_PERIPH_GPIOF
+#define LED0_PORT               GPIO_PORTF_BASE
+#define LED0_PIN                GPIO_PIN_3
+
+#define LED1_PERIPH             SYSCTL_PERIPH_GPIOF
+#define LED1_PORT               GPIO_PORTF_BASE
+#define LED1_PIN                GPIO_PIN_2
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#endif // PART_LM3S8730
+
+//*****************************************************************************
+//
+// LM3S8733 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S8733
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOD
+#define C0O_PORT                GPIO_PORTD_BASE
+#define C0O_PIN                 GPIO_PIN_7
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1O_PERIPH              SYSCTL_PERIPH_GPIOC
+#define C1O_PORT                GPIO_PORTC_BASE
+#define C1O_PIN                 GPIO_PIN_5
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_5
+
+#define C2_MINUS_PERIPH         SYSCTL_PERIPH_GPIOC
+#define C2_MINUS_PORT           GPIO_PORTC_BASE
+#define C2_MINUS_PIN            GPIO_PIN_7
+
+#define C2_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C2_PLUS_PORT            GPIO_PORTC_BASE
+#define C2_PLUS_PIN             GPIO_PIN_6
+
+#define CAN0RX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0RX_PORT             GPIO_PORTD_BASE
+#define CAN0RX_PIN              GPIO_PIN_0
+
+#define CAN0TX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0TX_PORT             GPIO_PORTD_BASE
+#define CAN0TX_PIN              GPIO_PIN_1
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP1_PORT               GPIO_PORTA_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_1
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP3_PORT               GPIO_PORTD_BASE
+#define CCP3_PIN                GPIO_PIN_4
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define LED0_PERIPH             SYSCTL_PERIPH_GPIOF
+#define LED0_PORT               GPIO_PORTF_BASE
+#define LED0_PIN                GPIO_PIN_3
+
+#define LED1_PERIPH             SYSCTL_PERIPH_GPIOF
+#define LED1_PORT               GPIO_PORTF_BASE
+#define LED1_PIN                GPIO_PIN_2
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#endif // PART_LM3S8733
+
+//*****************************************************************************
+//
+// LM3S8738 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S8738
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOC
+#define C0O_PORT                GPIO_PORTC_BASE
+#define C0O_PIN                 GPIO_PIN_5
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define CAN0RX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0RX_PORT             GPIO_PORTD_BASE
+#define CAN0RX_PIN              GPIO_PIN_0
+
+#define CAN0TX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0TX_PORT             GPIO_PORTD_BASE
+#define CAN0TX_PIN              GPIO_PIN_1
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP1_PORT               GPIO_PORTA_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_1
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP3_PORT               GPIO_PORTC_BASE
+#define CCP3_PIN                GPIO_PIN_6
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP4_PORT               GPIO_PORTA_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP5_PORT               GPIO_PORTB_BASE
+#define CCP5_PIN                GPIO_PIN_5
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define LED0_PERIPH             SYSCTL_PERIPH_GPIOF
+#define LED0_PORT               GPIO_PORTF_BASE
+#define LED0_PIN                GPIO_PIN_3
+
+#define LED1_PERIPH             SYSCTL_PERIPH_GPIOF
+#define LED1_PORT               GPIO_PORTF_BASE
+#define LED1_PIN                GPIO_PIN_2
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SSI1CLK_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1CLK_PORT            GPIO_PORTE_BASE
+#define SSI1CLK_PIN             GPIO_PIN_0
+
+#define SSI1FSS_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1FSS_PORT            GPIO_PORTE_BASE
+#define SSI1FSS_PIN             GPIO_PIN_1
+
+#define SSI1RX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1RX_PORT             GPIO_PORTE_BASE
+#define SSI1RX_PIN              GPIO_PIN_2
+
+#define SSI1TX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1TX_PORT             GPIO_PORTE_BASE
+#define SSI1TX_PIN              GPIO_PIN_3
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#define U2RX_PERIPH             SYSCTL_PERIPH_GPIOG
+#define U2RX_PORT               GPIO_PORTG_BASE
+#define U2RX_PIN                GPIO_PIN_0
+
+#define U2TX_PERIPH             SYSCTL_PERIPH_GPIOG
+#define U2TX_PORT               GPIO_PORTG_BASE
+#define U2TX_PIN                GPIO_PIN_1
+
+#endif // PART_LM3S8738
+
+//*****************************************************************************
+//
+// LM3S8930 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S8930
+
+#define CAN0RX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0RX_PORT             GPIO_PORTD_BASE
+#define CAN0RX_PIN              GPIO_PIN_0
+
+#define CAN0TX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0TX_PORT             GPIO_PORTD_BASE
+#define CAN0TX_PIN              GPIO_PIN_1
+
+#define CAN1RX_PERIPH           SYSCTL_PERIPH_GPIOF
+#define CAN1RX_PORT             GPIO_PORTF_BASE
+#define CAN1RX_PIN              GPIO_PIN_0
+
+#define CAN1TX_PERIPH           SYSCTL_PERIPH_GPIOF
+#define CAN1TX_PORT             GPIO_PORTF_BASE
+#define CAN1TX_PIN              GPIO_PIN_1
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP1_PORT               GPIO_PORTA_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define LED0_PERIPH             SYSCTL_PERIPH_GPIOF
+#define LED0_PORT               GPIO_PORTF_BASE
+#define LED0_PIN                GPIO_PIN_3
+
+#define LED1_PERIPH             SYSCTL_PERIPH_GPIOF
+#define LED1_PORT               GPIO_PORTF_BASE
+#define LED1_PIN                GPIO_PIN_2
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#endif // PART_LM3S8930
+
+//*****************************************************************************
+//
+// LM3S8933 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S8933
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOD
+#define C0O_PORT                GPIO_PORTD_BASE
+#define C0O_PIN                 GPIO_PIN_7
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1O_PERIPH              SYSCTL_PERIPH_GPIOC
+#define C1O_PORT                GPIO_PORTC_BASE
+#define C1O_PIN                 GPIO_PIN_5
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_5
+
+#define C2_MINUS_PERIPH         SYSCTL_PERIPH_GPIOC
+#define C2_MINUS_PORT           GPIO_PORTC_BASE
+#define C2_MINUS_PIN            GPIO_PIN_7
+
+#define C2_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C2_PLUS_PORT            GPIO_PORTC_BASE
+#define C2_PLUS_PIN             GPIO_PIN_6
+
+#define CAN0RX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0RX_PORT             GPIO_PORTD_BASE
+#define CAN0RX_PIN              GPIO_PIN_0
+
+#define CAN0TX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0TX_PORT             GPIO_PORTD_BASE
+#define CAN0TX_PIN              GPIO_PIN_1
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP1_PORT               GPIO_PORTA_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_1
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP3_PORT               GPIO_PORTD_BASE
+#define CCP3_PIN                GPIO_PIN_4
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define LED0_PERIPH             SYSCTL_PERIPH_GPIOF
+#define LED0_PORT               GPIO_PORTF_BASE
+#define LED0_PIN                GPIO_PIN_3
+
+#define LED1_PERIPH             SYSCTL_PERIPH_GPIOF
+#define LED1_PORT               GPIO_PORTF_BASE
+#define LED1_PIN                GPIO_PIN_2
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#endif // PART_LM3S8933
+
+//*****************************************************************************
+//
+// LM3S8938 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S8938
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOB
+#define C0O_PORT                GPIO_PORTB_BASE
+#define C0O_PIN                 GPIO_PIN_6
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define C1O_PERIPH              SYSCTL_PERIPH_GPIOC
+#define C1O_PORT                GPIO_PORTC_BASE
+#define C1O_PIN                 GPIO_PIN_5
+
+#define C1_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C1_MINUS_PORT           GPIO_PORTB_BASE
+#define C1_MINUS_PIN            GPIO_PIN_5
+
+#define C1_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C1_PLUS_PORT            GPIO_PORTC_BASE
+#define C1_PLUS_PIN             GPIO_PIN_5
+
+#define C2O_PERIPH              SYSCTL_PERIPH_GPIOC
+#define C2O_PORT                GPIO_PORTC_BASE
+#define C2O_PIN                 GPIO_PIN_6
+
+#define C2_MINUS_PERIPH         SYSCTL_PERIPH_GPIOC
+#define C2_MINUS_PORT           GPIO_PORTC_BASE
+#define C2_MINUS_PIN            GPIO_PIN_7
+
+#define C2_PLUS_PERIPH          SYSCTL_PERIPH_GPIOC
+#define C2_PLUS_PORT            GPIO_PORTC_BASE
+#define C2_PLUS_PIN             GPIO_PIN_6
+
+#define CAN0RX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0RX_PORT             GPIO_PORTD_BASE
+#define CAN0RX_PIN              GPIO_PIN_0
+
+#define CAN0TX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0TX_PORT             GPIO_PORTD_BASE
+#define CAN0TX_PIN              GPIO_PIN_1
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOE
+#define CCP1_PORT               GPIO_PORTE_BASE
+#define CCP1_PIN                GPIO_PIN_3
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_1
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOE
+#define CCP3_PORT               GPIO_PORTE_BASE
+#define CCP3_PIN                GPIO_PIN_0
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOE
+#define CCP4_PORT               GPIO_PORTE_BASE
+#define CCP4_PIN                GPIO_PIN_2
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP5_PORT               GPIO_PORTC_BASE
+#define CCP5_PIN                GPIO_PIN_4
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define I2C1SCL_PERIPH          SYSCTL_PERIPH_GPIOA
+#define I2C1SCL_PORT            GPIO_PORTA_BASE
+#define I2C1SCL_PIN             GPIO_PIN_6
+
+#define I2C1SDA_PERIPH          SYSCTL_PERIPH_GPIOA
+#define I2C1SDA_PORT            GPIO_PORTA_BASE
+#define I2C1SDA_PIN             GPIO_PIN_7
+
+#define LED0_PERIPH             SYSCTL_PERIPH_GPIOF
+#define LED0_PORT               GPIO_PORTF_BASE
+#define LED0_PIN                GPIO_PIN_3
+
+#define LED1_PERIPH             SYSCTL_PERIPH_GPIOF
+#define LED1_PORT               GPIO_PORTF_BASE
+#define LED1_PIN                GPIO_PIN_2
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#define U2RX_PERIPH             SYSCTL_PERIPH_GPIOG
+#define U2RX_PORT               GPIO_PORTG_BASE
+#define U2RX_PIN                GPIO_PIN_0
+
+#define U2TX_PERIPH             SYSCTL_PERIPH_GPIOG
+#define U2TX_PORT               GPIO_PORTG_BASE
+#define U2TX_PIN                GPIO_PIN_1
+
+#endif // PART_LM3S8938
+
+//*****************************************************************************
+//
+// LM3S8962 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S8962
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOB
+#define C0O_PORT                GPIO_PORTB_BASE
+#define C0O_PIN                 GPIO_PIN_5
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define CAN0RX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0RX_PORT             GPIO_PORTD_BASE
+#define CAN0RX_PIN              GPIO_PIN_0
+
+#define CAN0TX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0TX_PORT             GPIO_PORTD_BASE
+#define CAN0TX_PIN              GPIO_PIN_1
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define CCP0_PORT               GPIO_PORTD_BASE
+#define CCP0_PIN                GPIO_PIN_4
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP1_PORT               GPIO_PORTA_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define FAULT_PERIPH            SYSCTL_PERIPH_GPIOD
+#define FAULT_PORT              GPIO_PORTD_BASE
+#define FAULT_PIN               GPIO_PIN_6
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define IDX0_PERIPH             SYSCTL_PERIPH_GPIOD
+#define IDX0_PORT               GPIO_PORTD_BASE
+#define IDX0_PIN                GPIO_PIN_7
+
+#define IDX1_PERIPH             SYSCTL_PERIPH_GPIOF
+#define IDX1_PORT               GPIO_PORTF_BASE
+#define IDX1_PIN                GPIO_PIN_1
+
+#define LED0_PERIPH             SYSCTL_PERIPH_GPIOF
+#define LED0_PORT               GPIO_PORTF_BASE
+#define LED0_PIN                GPIO_PIN_3
+
+#define LED1_PERIPH             SYSCTL_PERIPH_GPIOF
+#define LED1_PORT               GPIO_PORTF_BASE
+#define LED1_PIN                GPIO_PIN_2
+
+#define PHA0_PERIPH             SYSCTL_PERIPH_GPIOC
+#define PHA0_PORT               GPIO_PORTC_BASE
+#define PHA0_PIN                GPIO_PIN_4
+
+#define PHA1_PERIPH             SYSCTL_PERIPH_GPIOE
+#define PHA1_PORT               GPIO_PORTE_BASE
+#define PHA1_PIN                GPIO_PIN_3
+
+#define PHB0_PERIPH             SYSCTL_PERIPH_GPIOC
+#define PHB0_PORT               GPIO_PORTC_BASE
+#define PHB0_PIN                GPIO_PIN_6
+
+#define PHB1_PERIPH             SYSCTL_PERIPH_GPIOE
+#define PHB1_PORT               GPIO_PORTE_BASE
+#define PHB1_PIN                GPIO_PIN_2
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOF
+#define PWM0_PORT               GPIO_PORTF_BASE
+#define PWM0_PIN                GPIO_PIN_0
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOG
+#define PWM1_PORT               GPIO_PORTG_BASE
+#define PWM1_PIN                GPIO_PIN_1
+
+#define PWM2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define PWM2_PORT               GPIO_PORTB_BASE
+#define PWM2_PIN                GPIO_PIN_0
+
+#define PWM3_PERIPH             SYSCTL_PERIPH_GPIOB
+#define PWM3_PORT               GPIO_PORTB_BASE
+#define PWM3_PIN                GPIO_PIN_1
+
+#define PWM4_PERIPH             SYSCTL_PERIPH_GPIOE
+#define PWM4_PORT               GPIO_PORTE_BASE
+#define PWM4_PIN                GPIO_PIN_0
+
+#define PWM5_PERIPH             SYSCTL_PERIPH_GPIOE
+#define PWM5_PORT               GPIO_PORTE_BASE
+#define PWM5_PIN                GPIO_PIN_1
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#endif // PART_LM3S8962
+
+//*****************************************************************************
+//
+// LM3S8970 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S8970
+
+#define CAN0RX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0RX_PORT             GPIO_PORTD_BASE
+#define CAN0RX_PIN              GPIO_PIN_0
+
+#define CAN0TX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0TX_PORT             GPIO_PORTD_BASE
+#define CAN0TX_PIN              GPIO_PIN_1
+
+#define CAN1RX_PERIPH           SYSCTL_PERIPH_GPIOF
+#define CAN1RX_PORT             GPIO_PORTF_BASE
+#define CAN1RX_PIN              GPIO_PIN_0
+
+#define CAN1TX_PERIPH           SYSCTL_PERIPH_GPIOF
+#define CAN1TX_PORT             GPIO_PORTF_BASE
+#define CAN1TX_PIN              GPIO_PIN_1
+
+#define CAN2RX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define CAN2RX_PORT             GPIO_PORTE_BASE
+#define CAN2RX_PIN              GPIO_PIN_4
+
+#define CAN2TX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define CAN2TX_PORT             GPIO_PORTE_BASE
+#define CAN2TX_PIN              GPIO_PIN_5
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP1_PORT               GPIO_PORTA_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define I2C0SCL_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SCL_PORT            GPIO_PORTB_BASE
+#define I2C0SCL_PIN             GPIO_PIN_2
+
+#define I2C0SDA_PERIPH          SYSCTL_PERIPH_GPIOB
+#define I2C0SDA_PORT            GPIO_PORTB_BASE
+#define I2C0SDA_PIN             GPIO_PIN_3
+
+#define LED0_PERIPH             SYSCTL_PERIPH_GPIOF
+#define LED0_PORT               GPIO_PORTF_BASE
+#define LED0_PIN                GPIO_PIN_3
+
+#define LED1_PERIPH             SYSCTL_PERIPH_GPIOF
+#define LED1_PORT               GPIO_PORTF_BASE
+#define LED1_PIN                GPIO_PIN_2
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SSI1CLK_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1CLK_PORT            GPIO_PORTE_BASE
+#define SSI1CLK_PIN             GPIO_PIN_0
+
+#define SSI1FSS_PERIPH          SYSCTL_PERIPH_GPIOE
+#define SSI1FSS_PORT            GPIO_PORTE_BASE
+#define SSI1FSS_PIN             GPIO_PIN_1
+
+#define SSI1RX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1RX_PORT             GPIO_PORTE_BASE
+#define SSI1RX_PIN              GPIO_PIN_2
+
+#define SSI1TX_PERIPH           SYSCTL_PERIPH_GPIOE
+#define SSI1TX_PORT             GPIO_PORTE_BASE
+#define SSI1TX_PIN              GPIO_PIN_3
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#define U1RX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1RX_PORT               GPIO_PORTD_BASE
+#define U1RX_PIN                GPIO_PIN_2
+
+#define U1TX_PERIPH             SYSCTL_PERIPH_GPIOD
+#define U1TX_PORT               GPIO_PORTD_BASE
+#define U1TX_PIN                GPIO_PIN_3
+
+#endif // PART_LM3S8970
+
+//*****************************************************************************
+//
+// LM3S8971 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S8971
+
+#define C0O_PERIPH              SYSCTL_PERIPH_GPIOC
+#define C0O_PORT                GPIO_PORTC_BASE
+#define C0O_PIN                 GPIO_PIN_5
+
+#define C0_MINUS_PERIPH         SYSCTL_PERIPH_GPIOB
+#define C0_MINUS_PORT           GPIO_PORTB_BASE
+#define C0_MINUS_PIN            GPIO_PIN_4
+
+#define C0_PLUS_PERIPH          SYSCTL_PERIPH_GPIOB
+#define C0_PLUS_PORT            GPIO_PORTB_BASE
+#define C0_PLUS_PIN             GPIO_PIN_6
+
+#define CAN0RX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0RX_PORT             GPIO_PORTD_BASE
+#define CAN0RX_PIN              GPIO_PIN_0
+
+#define CAN0TX_PERIPH           SYSCTL_PERIPH_GPIOD
+#define CAN0TX_PORT             GPIO_PORTD_BASE
+#define CAN0TX_PIN              GPIO_PIN_1
+
+#define CCP0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP0_PORT               GPIO_PORTB_BASE
+#define CCP0_PIN                GPIO_PIN_0
+
+#define CCP1_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP1_PORT               GPIO_PORTA_BASE
+#define CCP1_PIN                GPIO_PIN_6
+
+#define CCP2_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP2_PORT               GPIO_PORTB_BASE
+#define CCP2_PIN                GPIO_PIN_1
+
+#define CCP3_PERIPH             SYSCTL_PERIPH_GPIOC
+#define CCP3_PORT               GPIO_PORTC_BASE
+#define CCP3_PIN                GPIO_PIN_6
+
+#define CCP4_PERIPH             SYSCTL_PERIPH_GPIOA
+#define CCP4_PORT               GPIO_PORTA_BASE
+#define CCP4_PIN                GPIO_PIN_7
+
+#define CCP5_PERIPH             SYSCTL_PERIPH_GPIOB
+#define CCP5_PORT               GPIO_PORTB_BASE
+#define CCP5_PIN                GPIO_PIN_5
+
+#define FAULT_PERIPH            SYSCTL_PERIPH_GPIOB
+#define FAULT_PORT              GPIO_PORTB_BASE
+#define FAULT_PIN               GPIO_PIN_3
+
+#define IDX0_PERIPH             SYSCTL_PERIPH_GPIOB
+#define IDX0_PORT               GPIO_PORTB_BASE
+#define IDX0_PIN                GPIO_PIN_2
+
+#define LED0_PERIPH             SYSCTL_PERIPH_GPIOF
+#define LED0_PORT               GPIO_PORTF_BASE
+#define LED0_PIN                GPIO_PIN_3
+
+#define LED1_PERIPH             SYSCTL_PERIPH_GPIOF
+#define LED1_PORT               GPIO_PORTF_BASE
+#define LED1_PIN                GPIO_PIN_2
+
+#define PHA0_PERIPH             SYSCTL_PERIPH_GPIOC
+#define PHA0_PORT               GPIO_PORTC_BASE
+#define PHA0_PIN                GPIO_PIN_4
+
+#define PHB0_PERIPH             SYSCTL_PERIPH_GPIOC
+#define PHB0_PORT               GPIO_PORTC_BASE
+#define PHB0_PIN                GPIO_PIN_7
+
+#define PWM0_PERIPH             SYSCTL_PERIPH_GPIOF
+#define PWM0_PORT               GPIO_PORTF_BASE
+#define PWM0_PIN                GPIO_PIN_0
+
+#define PWM1_PERIPH             SYSCTL_PERIPH_GPIOF
+#define PWM1_PORT               GPIO_PORTF_BASE
+#define PWM1_PIN                GPIO_PIN_1
+
+#define PWM2_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM2_PORT               GPIO_PORTD_BASE
+#define PWM2_PIN                GPIO_PIN_2
+
+#define PWM3_PERIPH             SYSCTL_PERIPH_GPIOD
+#define PWM3_PORT               GPIO_PORTD_BASE
+#define PWM3_PIN                GPIO_PIN_3
+
+#define PWM4_PERIPH             SYSCTL_PERIPH_GPIOE
+#define PWM4_PORT               GPIO_PORTE_BASE
+#define PWM4_PIN                GPIO_PIN_0
+
+#define PWM5_PERIPH             SYSCTL_PERIPH_GPIOE
+#define PWM5_PORT               GPIO_PORTE_BASE
+#define PWM5_PIN                GPIO_PIN_1
+
+#define SSI0CLK_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0CLK_PORT            GPIO_PORTA_BASE
+#define SSI0CLK_PIN             GPIO_PIN_2
+
+#define SSI0FSS_PERIPH          SYSCTL_PERIPH_GPIOA
+#define SSI0FSS_PORT            GPIO_PORTA_BASE
+#define SSI0FSS_PIN             GPIO_PIN_3
+
+#define SSI0RX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0RX_PORT             GPIO_PORTA_BASE
+#define SSI0RX_PIN              GPIO_PIN_4
+
+#define SSI0TX_PERIPH           SYSCTL_PERIPH_GPIOA
+#define SSI0TX_PORT             GPIO_PORTA_BASE
+#define SSI0TX_PIN              GPIO_PIN_5
+
+#define SWCLK_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWCLK_PORT              GPIO_PORTC_BASE
+#define SWCLK_PIN               GPIO_PIN_0
+
+#define SWDIO_PERIPH            SYSCTL_PERIPH_GPIOC
+#define SWDIO_PORT              GPIO_PORTC_BASE
+#define SWDIO_PIN               GPIO_PIN_1
+
+#define SWO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define SWO_PORT                GPIO_PORTC_BASE
+#define SWO_PIN                 GPIO_PIN_3
+
+#define TCK_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TCK_PORT                GPIO_PORTC_BASE
+#define TCK_PIN                 GPIO_PIN_0
+
+#define TDI_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDI_PORT                GPIO_PORTC_BASE
+#define TDI_PIN                 GPIO_PIN_2
+
+#define TDO_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TDO_PORT                GPIO_PORTC_BASE
+#define TDO_PIN                 GPIO_PIN_3
+
+#define TMS_PERIPH              SYSCTL_PERIPH_GPIOC
+#define TMS_PORT                GPIO_PORTC_BASE
+#define TMS_PIN                 GPIO_PIN_1
+
+#define TRST_PERIPH             SYSCTL_PERIPH_GPIOB
+#define TRST_PORT               GPIO_PORTB_BASE
+#define TRST_PIN                GPIO_PIN_7
+
+#define U0RX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0RX_PORT               GPIO_PORTA_BASE
+#define U0RX_PIN                GPIO_PIN_0
+
+#define U0TX_PERIPH             SYSCTL_PERIPH_GPIOA
+#define U0TX_PORT               GPIO_PORTA_BASE
+#define U0TX_PIN                GPIO_PIN_1
+
+#endif // PART_LM3S8971
+
+//*****************************************************************************
+//
+// LM3S8C62 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S8C62
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_PWM4           0x00000804
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_PWM5           0x00000C04
+
+#define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_CAN0RX         0x00001005
+
+#define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_CAN0TX         0x00001405
+
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_PWM0           0x00001804
+#define GPIO_PA6_PWM4           0x00001805
+#define GPIO_PA6_CAN0RX         0x00001806
+
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_PWM1           0x00001C04
+#define GPIO_PA7_PWM5           0x00001C05
+#define GPIO_PA7_CAN0TX         0x00001C06
+#define GPIO_PA7_CCP3           0x00001C07
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_PWM2           0x00010002
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_PWM3           0x00010402
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_IDX0           0x00010802
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_FAULT0         0x00010C02
+#define GPIO_PB3_FAULT3         0x00010C04
+
+#define GPIO_PB4_CAN0RX         0x00011005
+#define GPIO_PB4_IDX0           0x00011006
+#define GPIO_PB4_U1RX           0x00011007
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CAN0TX         0x00011405
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_FAULT1         0x00011804
+#define GPIO_PB6_IDX0           0x00011805
+#define GPIO_PB6_CCP5           0x00011806
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_PHA0           0x00021002
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_FAULT2         0x00021404
+#define GPIO_PC5_CCP3           0x00021405
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_PHB0           0x00021802
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_PHB0           0x00021C02
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_C1O            0x00021C07
+
+#define GPIO_PD0_PWM0           0x00030001
+#define GPIO_PD0_CAN0RX         0x00030002
+#define GPIO_PD0_IDX0           0x00030003
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+
+#define GPIO_PD1_PWM1           0x00030401
+#define GPIO_PD1_CAN0TX         0x00030402
+#define GPIO_PD1_PHA0           0x00030403
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_CCP2           0x0003040A
+#define GPIO_PD1_PHB1           0x0003040B
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_PWM2           0x00030803
+#define GPIO_PD2_CCP5           0x00030804
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_PWM3           0x00030C03
+#define GPIO_PD3_CCP0           0x00030C04
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+
+#define GPIO_PD6_FAULT0         0x00031801
+
+#define GPIO_PD7_IDX0           0x00031C01
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+
+#define GPIO_PE0_PWM4           0x00040001
+#define GPIO_PE0_CCP3           0x00040003
+
+#define GPIO_PE1_PWM5           0x00040401
+#define GPIO_PE1_FAULT0         0x00040403
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_PHB1           0x00040803
+#define GPIO_PE2_PHA0           0x00040804
+#define GPIO_PE2_CCP2           0x00040805
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_PHA1           0x00040C03
+#define GPIO_PE3_PHB0           0x00040C04
+#define GPIO_PE3_CCP7           0x00040C05
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_FAULT0         0x00041004
+#define GPIO_PE4_CCP2           0x00041006
+
+#define GPIO_PE5_CCP5           0x00041401
+
+#define GPIO_PE6_PWM4           0x00041801
+#define GPIO_PE6_C1O            0x00041802
+
+#define GPIO_PE7_PWM5           0x00041C01
+
+#define GPIO_PF0_PHB0           0x00050002
+#define GPIO_PF0_PWM0           0x00050003
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_IDX1           0x00050402
+#define GPIO_PF1_PWM1           0x00050403
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_LED1           0x00050801
+#define GPIO_PF2_PWM4           0x00050802
+#define GPIO_PF2_PWM2           0x00050804
+
+#define GPIO_PF3_LED0           0x00050C01
+#define GPIO_PF3_PWM5           0x00050C02
+#define GPIO_PF3_PWM3           0x00050C04
+
+#define GPIO_PG0_PWM0           0x00060002
+#define GPIO_PG0_PWM4           0x00060004
+
+#define GPIO_PG1_PWM1           0x00060402
+#define GPIO_PG1_PWM5           0x00060404
+
+#endif // PART_LM3S8C62
+
+//*****************************************************************************
+//
+// LM3S8G62 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S8G62
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_PWM4           0x00000804
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_PWM5           0x00000C04
+
+#define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_CAN0RX         0x00001005
+
+#define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_CAN0TX         0x00001405
+
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_PWM0           0x00001804
+#define GPIO_PA6_PWM4           0x00001805
+#define GPIO_PA6_CAN0RX         0x00001806
+
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_PWM1           0x00001C04
+#define GPIO_PA7_PWM5           0x00001C05
+#define GPIO_PA7_CAN0TX         0x00001C06
+#define GPIO_PA7_CCP3           0x00001C07
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_PWM2           0x00010002
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_PWM3           0x00010402
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_IDX0           0x00010802
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_FAULT0         0x00010C02
+#define GPIO_PB3_FAULT3         0x00010C04
+
+#define GPIO_PB4_CAN0RX         0x00011005
+#define GPIO_PB4_IDX0           0x00011006
+#define GPIO_PB4_U1RX           0x00011007
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CAN0TX         0x00011405
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_FAULT1         0x00011804
+#define GPIO_PB6_IDX0           0x00011805
+#define GPIO_PB6_CCP5           0x00011806
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_PHA0           0x00021002
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_FAULT2         0x00021404
+#define GPIO_PC5_CCP3           0x00021405
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_PHB0           0x00021802
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_PHB0           0x00021C02
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_C1O            0x00021C07
+
+#define GPIO_PD0_PWM0           0x00030001
+#define GPIO_PD0_CAN0RX         0x00030002
+#define GPIO_PD0_IDX0           0x00030003
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+
+#define GPIO_PD1_PWM1           0x00030401
+#define GPIO_PD1_CAN0TX         0x00030402
+#define GPIO_PD1_PHA0           0x00030403
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_CCP2           0x0003040A
+#define GPIO_PD1_PHB1           0x0003040B
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_PWM2           0x00030803
+#define GPIO_PD2_CCP5           0x00030804
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_PWM3           0x00030C03
+#define GPIO_PD3_CCP0           0x00030C04
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+
+#define GPIO_PD6_FAULT0         0x00031801
+
+#define GPIO_PD7_IDX0           0x00031C01
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+
+#define GPIO_PE0_PWM4           0x00040001
+#define GPIO_PE0_CCP3           0x00040003
+
+#define GPIO_PE1_PWM5           0x00040401
+#define GPIO_PE1_FAULT0         0x00040403
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_PHB1           0x00040803
+#define GPIO_PE2_PHA0           0x00040804
+#define GPIO_PE2_CCP2           0x00040805
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_PHA1           0x00040C03
+#define GPIO_PE3_PHB0           0x00040C04
+#define GPIO_PE3_CCP7           0x00040C05
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_FAULT0         0x00041004
+#define GPIO_PE4_CCP2           0x00041006
+
+#define GPIO_PE5_CCP5           0x00041401
+
+#define GPIO_PE6_PWM4           0x00041801
+#define GPIO_PE6_C1O            0x00041802
+
+#define GPIO_PE7_PWM5           0x00041C01
+
+#define GPIO_PF0_PHB0           0x00050002
+#define GPIO_PF0_PWM0           0x00050003
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_IDX1           0x00050402
+#define GPIO_PF1_PWM1           0x00050403
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_LED1           0x00050801
+#define GPIO_PF2_PWM4           0x00050802
+#define GPIO_PF2_PWM2           0x00050804
+
+#define GPIO_PF3_LED0           0x00050C01
+#define GPIO_PF3_PWM5           0x00050C02
+#define GPIO_PF3_PWM3           0x00050C04
+
+#define GPIO_PG0_PWM0           0x00060002
+#define GPIO_PG0_PWM4           0x00060004
+
+#define GPIO_PG1_PWM1           0x00060402
+#define GPIO_PG1_PWM5           0x00060404
+
+#endif // PART_LM3S8G62
+
+//*****************************************************************************
+//
+// LM3S9781 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S9781
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_I2S0RXSD       0x00000809
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_I2S0RXMCLK     0x00000C09
+
+#define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_CAN0RX         0x00001005
+#define GPIO_PA4_I2S0TXSCK      0x00001009
+
+#define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_CAN0TX         0x00001405
+#define GPIO_PA5_I2S0TXWS       0x00001409
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_CAN0RX         0x00001806
+#define GPIO_PA6_USB0EPEN       0x00001808
+#define GPIO_PA6_U1CTS          0x00001809
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_CAN0TX         0x00001C06
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_USB0PFLT       0x00001C08
+#define GPIO_PA7_U1DCD          0x00001C09
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+#define GPIO_PB2_USB0EPEN       0x00010808
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_USB0PFLT       0x00010C08
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_CAN0RX         0x00011005
+#define GPIO_PB4_U1RX           0x00011007
+#define GPIO_PB4_EPI0S23        0x00011008
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CAN0TX         0x00011405
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+#define GPIO_PB5_EPI0S22        0x00011408
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_CCP5           0x00011806
+#define GPIO_PB6_I2S0TXSCK      0x00011809
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_EPI0S2         0x00021008
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_CCP3           0x00021405
+#define GPIO_PC5_USB0EPEN       0x00021406
+#define GPIO_PC5_EPI0S3         0x00021408
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_C2O            0x00021803
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+#define GPIO_PC6_USB0PFLT       0x00021807
+#define GPIO_PC6_EPI0S4         0x00021808
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_USB0PFLT       0x00021C06
+#define GPIO_PC7_C1O            0x00021C07
+#define GPIO_PC7_EPI0S5         0x00021C08
+
+#define GPIO_PD0_CAN0RX         0x00030002
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+#define GPIO_PD0_I2S0RXSCK      0x00030008
+#define GPIO_PD0_U1CTS          0x00030009
+
+#define GPIO_PD1_CAN0TX         0x00030402
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_I2S0RXWS       0x00030408
+#define GPIO_PD1_U1DCD          0x00030409
+#define GPIO_PD1_CCP2           0x0003040A
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_CCP5           0x00030804
+#define GPIO_PD2_EPI0S20        0x00030808
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_CCP0           0x00030C04
+#define GPIO_PD3_EPI0S21        0x00030C08
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+#define GPIO_PD4_I2S0RXSD       0x00031008
+#define GPIO_PD4_U1RI           0x00031009
+#define GPIO_PD4_EPI0S19        0x0003100A
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_I2S0RXMCLK     0x00031408
+#define GPIO_PD5_U2RX           0x00031409
+#define GPIO_PD5_EPI0S28        0x0003140A
+
+#define GPIO_PD6_I2S0TXSCK      0x00031808
+#define GPIO_PD6_U2TX           0x00031809
+#define GPIO_PD6_EPI0S29        0x0003180A
+
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+#define GPIO_PD7_I2S0TXWS       0x00031C08
+#define GPIO_PD7_U1DTR          0x00031C09
+#define GPIO_PD7_EPI0S30        0x00031C0A
+
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+#define GPIO_PE0_EPI0S8         0x00040008
+#define GPIO_PE0_USB0PFLT       0x00040009
+
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+#define GPIO_PE1_EPI0S9         0x00040408
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_CCP2           0x00040805
+#define GPIO_PE2_EPI0S24        0x00040808
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_CCP7           0x00040C05
+#define GPIO_PE3_EPI0S25        0x00040C08
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_CAN2RX         0x00041002
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+#define GPIO_PE4_I2S0TXWS       0x00041009
+
+#define GPIO_PE5_CCP5           0x00041401
+#define GPIO_PE5_CAN2TX         0x00041402
+#define GPIO_PE5_I2S0TXSD       0x00041409
+
+#define GPIO_PE6_C1O            0x00041802
+#define GPIO_PE6_U1CTS          0x00041809
+
+#define GPIO_PE7_C2O            0x00041C02
+#define GPIO_PE7_U1DCD          0x00041C09
+
+#define GPIO_PF0_CAN1RX         0x00050001
+#define GPIO_PF0_I2S0TXSD       0x00050008
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_CAN1TX         0x00050401
+#define GPIO_PF1_I2S0TXMCLK     0x00050408
+#define GPIO_PF1_U1RTS          0x00050409
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_LED1           0x00050801
+#define GPIO_PF2_SSI1CLK        0x00050809
+
+#define GPIO_PF3_LED0           0x00050C01
+#define GPIO_PF3_SSI1FSS        0x00050C09
+
+#define GPIO_PF4_CCP0           0x00051001
+#define GPIO_PF4_C0O            0x00051002
+#define GPIO_PF4_EPI0S12        0x00051008
+#define GPIO_PF4_SSI1RX         0x00051009
+
+#define GPIO_PF5_CCP2           0x00051401
+#define GPIO_PF5_C1O            0x00051402
+#define GPIO_PF5_EPI0S15        0x00051408
+#define GPIO_PF5_SSI1TX         0x00051409
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_I2C1SCL        0x00060003
+#define GPIO_PG0_USB0EPEN       0x00060007
+#define GPIO_PG0_EPI0S13        0x00060008
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_I2C1SDA        0x00060403
+#define GPIO_PG1_EPI0S14        0x00060408
+
+#define GPIO_PG7_CCP5           0x00061C08
+#define GPIO_PG7_EPI0S31        0x00061C09
+
+#define GPIO_PH0_CCP6           0x00070001
+#define GPIO_PH0_EPI0S6         0x00070008
+
+#define GPIO_PH1_CCP7           0x00070401
+#define GPIO_PH1_EPI0S7         0x00070408
+
+#define GPIO_PH2_C1O            0x00070802
+#define GPIO_PH2_EPI0S1         0x00070808
+
+#define GPIO_PH3_USB0EPEN       0x00070C04
+#define GPIO_PH3_EPI0S0         0x00070C08
+
+#define GPIO_PH4_USB0PFLT       0x00071004
+#define GPIO_PH4_EPI0S10        0x00071008
+#define GPIO_PH4_SSI1CLK        0x0007100B
+
+#define GPIO_PH5_EPI0S11        0x00071408
+#define GPIO_PH5_SSI1FSS        0x0007140B
+
+#define GPIO_PH6_EPI0S26        0x00071808
+#define GPIO_PH6_SSI1RX         0x0007180B
+
+#define GPIO_PH7_EPI0S27        0x00071C08
+#define GPIO_PH7_SSI1TX         0x00071C0B
+
+#define GPIO_PJ0_EPI0S16        0x00080008
+#define GPIO_PJ0_I2C1SCL        0x0008000B
+
+#define GPIO_PJ1_EPI0S17        0x00080408
+#define GPIO_PJ1_USB0PFLT       0x00080409
+#define GPIO_PJ1_I2C1SDA        0x0008040B
+
+#define GPIO_PJ2_EPI0S18        0x00080808
+#define GPIO_PJ2_CCP0           0x00080809
+
+#define GPIO_PJ3_EPI0S19        0x00080C08
+#define GPIO_PJ3_U1CTS          0x00080C09
+#define GPIO_PJ3_CCP6           0x00080C0A
+
+#define GPIO_PJ4_EPI0S28        0x00081008
+#define GPIO_PJ4_U1DCD          0x00081009
+#define GPIO_PJ4_CCP4           0x0008100A
+
+#define GPIO_PJ5_EPI0S29        0x00081408
+#define GPIO_PJ5_U1DSR          0x00081409
+#define GPIO_PJ5_CCP2           0x0008140A
+
+#define GPIO_PJ6_EPI0S30        0x00081808
+#define GPIO_PJ6_U1RTS          0x00081809
+#define GPIO_PJ6_CCP1           0x0008180A
+
+#define GPIO_PJ7_U1DTR          0x00081C09
+#define GPIO_PJ7_CCP0           0x00081C0A
+
+#endif // PART_LM3S9781
+
+//*****************************************************************************
+//
+// LM3S9790 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S9790
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_I2S0RXSD       0x00000809
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_I2S0RXMCLK     0x00000C09
+
+#define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_CAN0RX         0x00001005
+#define GPIO_PA4_I2S0TXSCK      0x00001009
+
+#define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_CAN0TX         0x00001405
+#define GPIO_PA5_I2S0TXWS       0x00001409
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_CAN0RX         0x00001806
+#define GPIO_PA6_USB0EPEN       0x00001808
+#define GPIO_PA6_U1CTS          0x00001809
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_CAN0TX         0x00001C06
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_USB0PFLT       0x00001C08
+#define GPIO_PA7_U1DCD          0x00001C09
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+#define GPIO_PB2_USB0EPEN       0x00010808
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_USB0PFLT       0x00010C08
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_CAN0RX         0x00011005
+#define GPIO_PB4_U1RX           0x00011007
+#define GPIO_PB4_EPI0S23        0x00011008
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CAN0TX         0x00011405
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+#define GPIO_PB5_EPI0S22        0x00011408
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_CCP5           0x00011806
+#define GPIO_PB6_I2S0TXSCK      0x00011809
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_EPI0S2         0x00021008
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_CCP3           0x00021405
+#define GPIO_PC5_USB0EPEN       0x00021406
+#define GPIO_PC5_EPI0S3         0x00021408
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_C2O            0x00021803
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+#define GPIO_PC6_USB0PFLT       0x00021807
+#define GPIO_PC6_EPI0S4         0x00021808
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_USB0PFLT       0x00021C06
+#define GPIO_PC7_C1O            0x00021C07
+#define GPIO_PC7_EPI0S5         0x00021C08
+
+#define GPIO_PD0_CAN0RX         0x00030002
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+#define GPIO_PD0_I2S0RXSCK      0x00030008
+#define GPIO_PD0_U1CTS          0x00030009
+
+#define GPIO_PD1_CAN0TX         0x00030402
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_I2S0RXWS       0x00030408
+#define GPIO_PD1_U1DCD          0x00030409
+#define GPIO_PD1_CCP2           0x0003040A
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_CCP5           0x00030804
+#define GPIO_PD2_EPI0S20        0x00030808
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_CCP0           0x00030C04
+#define GPIO_PD3_EPI0S21        0x00030C08
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+#define GPIO_PD4_I2S0RXSD       0x00031008
+#define GPIO_PD4_U1RI           0x00031009
+#define GPIO_PD4_EPI0S19        0x0003100A
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_I2S0RXMCLK     0x00031408
+#define GPIO_PD5_U2RX           0x00031409
+#define GPIO_PD5_EPI0S28        0x0003140A
+
+#define GPIO_PD6_I2S0TXSCK      0x00031808
+#define GPIO_PD6_U2TX           0x00031809
+#define GPIO_PD6_EPI0S29        0x0003180A
+
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+#define GPIO_PD7_I2S0TXWS       0x00031C08
+#define GPIO_PD7_U1DTR          0x00031C09
+#define GPIO_PD7_EPI0S30        0x00031C0A
+
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+#define GPIO_PE0_EPI0S8         0x00040008
+#define GPIO_PE0_USB0PFLT       0x00040009
+
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+#define GPIO_PE1_EPI0S9         0x00040408
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_CCP2           0x00040805
+#define GPIO_PE2_EPI0S24        0x00040808
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_CCP7           0x00040C05
+#define GPIO_PE3_EPI0S25        0x00040C08
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+#define GPIO_PE4_I2S0TXWS       0x00041009
+
+#define GPIO_PE5_CCP5           0x00041401
+#define GPIO_PE5_I2S0TXSD       0x00041409
+
+#define GPIO_PE6_C1O            0x00041802
+#define GPIO_PE6_U1CTS          0x00041809
+
+#define GPIO_PE7_C2O            0x00041C02
+#define GPIO_PE7_U1DCD          0x00041C09
+
+#define GPIO_PF0_CAN1RX         0x00050001
+#define GPIO_PF0_I2S0TXSD       0x00050008
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_CAN1TX         0x00050401
+#define GPIO_PF1_I2S0TXMCLK     0x00050408
+#define GPIO_PF1_U1RTS          0x00050409
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_LED1           0x00050801
+#define GPIO_PF2_SSI1CLK        0x00050809
+
+#define GPIO_PF3_LED0           0x00050C01
+#define GPIO_PF3_SSI1FSS        0x00050C09
+
+#define GPIO_PF4_CCP0           0x00051001
+#define GPIO_PF4_C0O            0x00051002
+#define GPIO_PF4_EPI0S12        0x00051008
+#define GPIO_PF4_SSI1RX         0x00051009
+
+#define GPIO_PF5_CCP2           0x00051401
+#define GPIO_PF5_C1O            0x00051402
+#define GPIO_PF5_EPI0S15        0x00051408
+#define GPIO_PF5_SSI1TX         0x00051409
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_I2C1SCL        0x00060003
+#define GPIO_PG0_USB0EPEN       0x00060007
+#define GPIO_PG0_EPI0S13        0x00060008
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_I2C1SDA        0x00060403
+#define GPIO_PG1_EPI0S14        0x00060408
+
+#define GPIO_PG7_CCP5           0x00061C08
+#define GPIO_PG7_EPI0S31        0x00061C09
+
+#define GPIO_PH0_CCP6           0x00070001
+#define GPIO_PH0_EPI0S6         0x00070008
+
+#define GPIO_PH1_CCP7           0x00070401
+#define GPIO_PH1_EPI0S7         0x00070408
+
+#define GPIO_PH2_C1O            0x00070802
+#define GPIO_PH2_EPI0S1         0x00070808
+
+#define GPIO_PH3_USB0EPEN       0x00070C04
+#define GPIO_PH3_EPI0S0         0x00070C08
+
+#define GPIO_PH4_USB0PFLT       0x00071004
+#define GPIO_PH4_EPI0S10        0x00071008
+#define GPIO_PH4_SSI1CLK        0x0007100B
+
+#define GPIO_PH5_EPI0S11        0x00071408
+#define GPIO_PH5_SSI1FSS        0x0007140B
+
+#define GPIO_PH6_EPI0S26        0x00071808
+#define GPIO_PH6_SSI1RX         0x0007180B
+
+#define GPIO_PH7_EPI0S27        0x00071C08
+#define GPIO_PH7_SSI1TX         0x00071C0B
+
+#define GPIO_PJ0_EPI0S16        0x00080008
+#define GPIO_PJ0_I2C1SCL        0x0008000B
+
+#define GPIO_PJ1_EPI0S17        0x00080408
+#define GPIO_PJ1_USB0PFLT       0x00080409
+#define GPIO_PJ1_I2C1SDA        0x0008040B
+
+#define GPIO_PJ2_EPI0S18        0x00080808
+#define GPIO_PJ2_CCP0           0x00080809
+
+#endif // PART_LM3S9790
+
+//*****************************************************************************
+//
+// LM3S9792 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S9792
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_PWM4           0x00000804
+#define GPIO_PA2_I2S0RXSD       0x00000809
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_PWM5           0x00000C04
+#define GPIO_PA3_I2S0RXMCLK     0x00000C09
+
+#define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_PWM6           0x00001004
+#define GPIO_PA4_CAN0RX         0x00001005
+#define GPIO_PA4_I2S0TXSCK      0x00001009
+
+#define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_PWM7           0x00001404
+#define GPIO_PA5_CAN0TX         0x00001405
+#define GPIO_PA5_I2S0TXWS       0x00001409
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_PWM0           0x00001804
+#define GPIO_PA6_PWM4           0x00001805
+#define GPIO_PA6_CAN0RX         0x00001806
+#define GPIO_PA6_USB0EPEN       0x00001808
+#define GPIO_PA6_U1CTS          0x00001809
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_PWM1           0x00001C04
+#define GPIO_PA7_PWM5           0x00001C05
+#define GPIO_PA7_CAN0TX         0x00001C06
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_USB0PFLT       0x00001C08
+#define GPIO_PA7_U1DCD          0x00001C09
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_PWM2           0x00010002
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_PWM3           0x00010402
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_IDX0           0x00010802
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+#define GPIO_PB2_USB0EPEN       0x00010808
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_FAULT0         0x00010C02
+#define GPIO_PB3_FAULT3         0x00010C04
+#define GPIO_PB3_USB0PFLT       0x00010C08
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_CAN0RX         0x00011005
+#define GPIO_PB4_IDX0           0x00011006
+#define GPIO_PB4_U1RX           0x00011007
+#define GPIO_PB4_EPI0S23        0x00011008
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CAN0TX         0x00011405
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+#define GPIO_PB5_EPI0S22        0x00011408
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_FAULT1         0x00011804
+#define GPIO_PB6_IDX0           0x00011805
+#define GPIO_PB6_CCP5           0x00011806
+#define GPIO_PB6_I2S0TXSCK      0x00011809
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_PHA0           0x00021002
+#define GPIO_PC4_PWM6           0x00021004
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_EPI0S2         0x00021008
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_FAULT2         0x00021404
+#define GPIO_PC5_CCP3           0x00021405
+#define GPIO_PC5_USB0EPEN       0x00021406
+#define GPIO_PC5_EPI0S3         0x00021408
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_PHB0           0x00021802
+#define GPIO_PC6_C2O            0x00021803
+#define GPIO_PC6_PWM7           0x00021804
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+#define GPIO_PC6_USB0PFLT       0x00021807
+#define GPIO_PC6_EPI0S4         0x00021808
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_PHB0           0x00021C02
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_USB0PFLT       0x00021C06
+#define GPIO_PC7_C1O            0x00021C07
+#define GPIO_PC7_EPI0S5         0x00021C08
+
+#define GPIO_PD0_PWM0           0x00030001
+#define GPIO_PD0_CAN0RX         0x00030002
+#define GPIO_PD0_IDX0           0x00030003
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+#define GPIO_PD0_I2S0RXSCK      0x00030008
+#define GPIO_PD0_U1CTS          0x00030009
+
+#define GPIO_PD1_PWM1           0x00030401
+#define GPIO_PD1_CAN0TX         0x00030402
+#define GPIO_PD1_PHA0           0x00030403
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_I2S0RXWS       0x00030408
+#define GPIO_PD1_U1DCD          0x00030409
+#define GPIO_PD1_CCP2           0x0003040A
+#define GPIO_PD1_PHB1           0x0003040B
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_PWM2           0x00030803
+#define GPIO_PD2_CCP5           0x00030804
+#define GPIO_PD2_EPI0S20        0x00030808
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_PWM3           0x00030C03
+#define GPIO_PD3_CCP0           0x00030C04
+#define GPIO_PD3_EPI0S21        0x00030C08
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+#define GPIO_PD4_I2S0RXSD       0x00031008
+#define GPIO_PD4_U1RI           0x00031009
+#define GPIO_PD4_EPI0S19        0x0003100A
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_I2S0RXMCLK     0x00031408
+#define GPIO_PD5_U2RX           0x00031409
+#define GPIO_PD5_EPI0S28        0x0003140A
+
+#define GPIO_PD6_FAULT0         0x00031801
+#define GPIO_PD6_I2S0TXSCK      0x00031808
+#define GPIO_PD6_U2TX           0x00031809
+#define GPIO_PD6_EPI0S29        0x0003180A
+
+#define GPIO_PD7_IDX0           0x00031C01
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+#define GPIO_PD7_I2S0TXWS       0x00031C08
+#define GPIO_PD7_U1DTR          0x00031C09
+#define GPIO_PD7_EPI0S30        0x00031C0A
+
+#define GPIO_PE0_PWM4           0x00040001
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+#define GPIO_PE0_EPI0S8         0x00040008
+#define GPIO_PE0_USB0PFLT       0x00040009
+
+#define GPIO_PE1_PWM5           0x00040401
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_FAULT0         0x00040403
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+#define GPIO_PE1_EPI0S9         0x00040408
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_PHB1           0x00040803
+#define GPIO_PE2_PHA0           0x00040804
+#define GPIO_PE2_CCP2           0x00040805
+#define GPIO_PE2_EPI0S24        0x00040808
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_PHA1           0x00040C03
+#define GPIO_PE3_PHB0           0x00040C04
+#define GPIO_PE3_CCP7           0x00040C05
+#define GPIO_PE3_EPI0S25        0x00040C08
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_FAULT0         0x00041004
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+#define GPIO_PE4_I2S0TXWS       0x00041009
+
+#define GPIO_PE5_CCP5           0x00041401
+#define GPIO_PE5_I2S0TXSD       0x00041409
+
+#define GPIO_PE6_PWM4           0x00041801
+#define GPIO_PE6_C1O            0x00041802
+#define GPIO_PE6_U1CTS          0x00041809
+
+#define GPIO_PE7_PWM5           0x00041C01
+#define GPIO_PE7_C2O            0x00041C02
+#define GPIO_PE7_U1DCD          0x00041C09
+
+#define GPIO_PF0_CAN1RX         0x00050001
+#define GPIO_PF0_PHB0           0x00050002
+#define GPIO_PF0_PWM0           0x00050003
+#define GPIO_PF0_I2S0TXSD       0x00050008
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_CAN1TX         0x00050401
+#define GPIO_PF1_IDX1           0x00050402
+#define GPIO_PF1_PWM1           0x00050403
+#define GPIO_PF1_I2S0TXMCLK     0x00050408
+#define GPIO_PF1_U1RTS          0x00050409
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_LED1           0x00050801
+#define GPIO_PF2_PWM4           0x00050802
+#define GPIO_PF2_PWM2           0x00050804
+#define GPIO_PF2_SSI1CLK        0x00050809
+
+#define GPIO_PF3_LED0           0x00050C01
+#define GPIO_PF3_PWM5           0x00050C02
+#define GPIO_PF3_PWM3           0x00050C04
+#define GPIO_PF3_SSI1FSS        0x00050C09
+
+#define GPIO_PF4_CCP0           0x00051001
+#define GPIO_PF4_C0O            0x00051002
+#define GPIO_PF4_FAULT0         0x00051004
+#define GPIO_PF4_EPI0S12        0x00051008
+#define GPIO_PF4_SSI1RX         0x00051009
+
+#define GPIO_PF5_CCP2           0x00051401
+#define GPIO_PF5_C1O            0x00051402
+#define GPIO_PF5_EPI0S15        0x00051408
+#define GPIO_PF5_SSI1TX         0x00051409
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_PWM0           0x00060002
+#define GPIO_PG0_I2C1SCL        0x00060003
+#define GPIO_PG0_PWM4           0x00060004
+#define GPIO_PG0_USB0EPEN       0x00060007
+#define GPIO_PG0_EPI0S13        0x00060008
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_PWM1           0x00060402
+#define GPIO_PG1_I2C1SDA        0x00060403
+#define GPIO_PG1_PWM5           0x00060404
+#define GPIO_PG1_EPI0S14        0x00060408
+
+#define GPIO_PG7_PHB1           0x00061C01
+#define GPIO_PG7_PWM7           0x00061C04
+#define GPIO_PG7_CCP5           0x00061C08
+#define GPIO_PG7_EPI0S31        0x00061C09
+
+#define GPIO_PH0_CCP6           0x00070001
+#define GPIO_PH0_PWM2           0x00070002
+#define GPIO_PH0_EPI0S6         0x00070008
+#define GPIO_PH0_PWM4           0x00070009
+
+#define GPIO_PH1_CCP7           0x00070401
+#define GPIO_PH1_PWM3           0x00070402
+#define GPIO_PH1_EPI0S7         0x00070408
+#define GPIO_PH1_PWM5           0x00070409
+
+#define GPIO_PH2_IDX1           0x00070801
+#define GPIO_PH2_C1O            0x00070802
+#define GPIO_PH2_FAULT3         0x00070804
+#define GPIO_PH2_EPI0S1         0x00070808
+
+#define GPIO_PH3_PHB0           0x00070C01
+#define GPIO_PH3_FAULT0         0x00070C02
+#define GPIO_PH3_USB0EPEN       0x00070C04
+#define GPIO_PH3_EPI0S0         0x00070C08
+
+#define GPIO_PH4_USB0PFLT       0x00071004
+#define GPIO_PH4_EPI0S10        0x00071008
+#define GPIO_PH4_SSI1CLK        0x0007100B
+
+#define GPIO_PH5_EPI0S11        0x00071408
+#define GPIO_PH5_FAULT2         0x0007140A
+#define GPIO_PH5_SSI1FSS        0x0007140B
+
+#define GPIO_PH6_EPI0S26        0x00071808
+#define GPIO_PH6_PWM4           0x0007180A
+#define GPIO_PH6_SSI1RX         0x0007180B
+
+#define GPIO_PH7_EPI0S27        0x00071C08
+#define GPIO_PH7_PWM5           0x00071C0A
+#define GPIO_PH7_SSI1TX         0x00071C0B
+
+#define GPIO_PJ0_EPI0S16        0x00080008
+#define GPIO_PJ0_PWM0           0x0008000A
+#define GPIO_PJ0_I2C1SCL        0x0008000B
+
+#define GPIO_PJ1_EPI0S17        0x00080408
+#define GPIO_PJ1_USB0PFLT       0x00080409
+#define GPIO_PJ1_PWM1           0x0008040A
+#define GPIO_PJ1_I2C1SDA        0x0008040B
+
+#define GPIO_PJ2_EPI0S18        0x00080808
+#define GPIO_PJ2_CCP0           0x00080809
+#define GPIO_PJ2_FAULT0         0x0008080A
+
+#define GPIO_PJ3_EPI0S19        0x00080C08
+#define GPIO_PJ3_U1CTS          0x00080C09
+#define GPIO_PJ3_CCP6           0x00080C0A
+
+#define GPIO_PJ4_EPI0S28        0x00081008
+#define GPIO_PJ4_U1DCD          0x00081009
+#define GPIO_PJ4_CCP4           0x0008100A
+
+#define GPIO_PJ5_EPI0S29        0x00081408
+#define GPIO_PJ5_U1DSR          0x00081409
+#define GPIO_PJ5_CCP2           0x0008140A
+
+#define GPIO_PJ6_EPI0S30        0x00081808
+#define GPIO_PJ6_U1RTS          0x00081809
+#define GPIO_PJ6_CCP1           0x0008180A
+
+#define GPIO_PJ7_U1DTR          0x00081C09
+#define GPIO_PJ7_CCP0           0x00081C0A
+
+#endif // PART_LM3S9792
+
+//*****************************************************************************
+//
+// LM3S9971 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S9971
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_TXD2           0x00000803
+#define GPIO_PA2_PWM4           0x00000804
+#define GPIO_PA2_I2S0RXSD       0x00000809
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_TXD1           0x00000C03
+#define GPIO_PA3_PWM5           0x00000C04
+#define GPIO_PA3_I2S0RXMCLK     0x00000C09
+
+#define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_TXD0           0x00001003
+#define GPIO_PA4_CAN0RX         0x00001005
+#define GPIO_PA4_I2S0TXSCK      0x00001009
+
+#define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_RXDV           0x00001403
+#define GPIO_PA5_CAN0TX         0x00001405
+#define GPIO_PA5_I2S0TXWS       0x00001409
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_RXCK           0x00001803
+#define GPIO_PA6_PWM0           0x00001804
+#define GPIO_PA6_PWM4           0x00001805
+#define GPIO_PA6_CAN0RX         0x00001806
+#define GPIO_PA6_USB0EPEN       0x00001808
+#define GPIO_PA6_U1CTS          0x00001809
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_RXER           0x00001C03
+#define GPIO_PA7_PWM1           0x00001C04
+#define GPIO_PA7_PWM5           0x00001C05
+#define GPIO_PA7_CAN0TX         0x00001C06
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_USB0PFLT       0x00001C08
+#define GPIO_PA7_U1DCD          0x00001C09
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_PWM2           0x00010002
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_PWM3           0x00010402
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_IDX0           0x00010802
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+#define GPIO_PB2_USB0EPEN       0x00010808
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_FAULT0         0x00010C02
+#define GPIO_PB3_FAULT3         0x00010C04
+#define GPIO_PB3_USB0PFLT       0x00010C08
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_CAN0RX         0x00011005
+#define GPIO_PB4_IDX0           0x00011006
+#define GPIO_PB4_U1RX           0x00011007
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CAN0TX         0x00011405
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_FAULT1         0x00011804
+#define GPIO_PB6_IDX0           0x00011805
+#define GPIO_PB6_CCP5           0x00011806
+#define GPIO_PB6_I2S0TXSCK      0x00011809
+
+#define GPIO_PB7_NMI            0x00011C04
+#define GPIO_PB7_RXD1           0x00011C07
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_PHA0           0x00021002
+#define GPIO_PC4_TXD3           0x00021003
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_FAULT2         0x00021404
+#define GPIO_PC5_CCP3           0x00021405
+#define GPIO_PC5_USB0EPEN       0x00021406
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_PHB0           0x00021802
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+#define GPIO_PC6_USB0PFLT       0x00021807
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_PHB0           0x00021C02
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_USB0PFLT       0x00021C06
+#define GPIO_PC7_C1O            0x00021C07
+
+#define GPIO_PD0_PWM0           0x00030001
+#define GPIO_PD0_CAN0RX         0x00030002
+#define GPIO_PD0_IDX0           0x00030003
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+#define GPIO_PD0_RXDV           0x00030007
+#define GPIO_PD0_I2S0RXSCK      0x00030008
+#define GPIO_PD0_U1CTS          0x00030009
+
+#define GPIO_PD1_PWM1           0x00030401
+#define GPIO_PD1_CAN0TX         0x00030402
+#define GPIO_PD1_PHA0           0x00030403
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_TXER           0x00030407
+#define GPIO_PD1_I2S0RXWS       0x00030408
+#define GPIO_PD1_U1DCD          0x00030409
+#define GPIO_PD1_CCP2           0x0003040A
+#define GPIO_PD1_PHB1           0x0003040B
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_PWM2           0x00030803
+#define GPIO_PD2_CCP5           0x00030804
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_PWM3           0x00030C03
+#define GPIO_PD3_CCP0           0x00030C04
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+#define GPIO_PD4_TXD3           0x00031004
+#define GPIO_PD4_I2S0RXSD       0x00031008
+#define GPIO_PD4_U1RI           0x00031009
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_TXD2           0x00031404
+#define GPIO_PD5_I2S0RXMCLK     0x00031408
+#define GPIO_PD5_U2RX           0x00031409
+
+#define GPIO_PD6_FAULT0         0x00031801
+#define GPIO_PD6_TXD1           0x00031804
+#define GPIO_PD6_I2S0TXSCK      0x00031808
+#define GPIO_PD6_U2TX           0x00031809
+
+#define GPIO_PD7_IDX0           0x00031C01
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+#define GPIO_PD7_TXD0           0x00031C04
+#define GPIO_PD7_I2S0TXWS       0x00031C08
+#define GPIO_PD7_U1DTR          0x00031C09
+
+#define GPIO_PE0_PWM4           0x00040001
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+#define GPIO_PE0_USB0PFLT       0x00040009
+
+#define GPIO_PE1_PWM5           0x00040401
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_FAULT0         0x00040403
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_PHB1           0x00040803
+#define GPIO_PE2_PHA0           0x00040804
+#define GPIO_PE2_CCP2           0x00040805
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_PHA1           0x00040C03
+#define GPIO_PE3_PHB0           0x00040C04
+#define GPIO_PE3_CCP7           0x00040C05
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_FAULT0         0x00041004
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+#define GPIO_PE4_RXD0           0x00041007
+#define GPIO_PE4_I2S0TXWS       0x00041009
+
+#define GPIO_PE5_CCP5           0x00041401
+#define GPIO_PE5_I2S0TXSD       0x00041409
+
+#define GPIO_PE6_PWM4           0x00041801
+#define GPIO_PE6_C1O            0x00041802
+#define GPIO_PE6_U1CTS          0x00041809
+
+#define GPIO_PE7_PWM5           0x00041C01
+#define GPIO_PE7_U1DCD          0x00041C09
+
+#define GPIO_PF0_CAN1RX         0x00050001
+#define GPIO_PF0_PHB0           0x00050002
+#define GPIO_PF0_PWM0           0x00050003
+#define GPIO_PF0_RXCK           0x00050004
+#define GPIO_PF0_I2S0TXSD       0x00050008
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_CAN1TX         0x00050401
+#define GPIO_PF1_IDX1           0x00050402
+#define GPIO_PF1_PWM1           0x00050403
+#define GPIO_PF1_RXER           0x00050404
+#define GPIO_PF1_I2S0TXMCLK     0x00050408
+#define GPIO_PF1_U1RTS          0x00050409
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_PWM4           0x00050802
+#define GPIO_PF2_PHYINT         0x00050803
+#define GPIO_PF2_PWM2           0x00050804
+#define GPIO_PF2_SSI1CLK        0x00050809
+
+#define GPIO_PF3_PWM5           0x00050C02
+#define GPIO_PF3_MDC            0x00050C03
+#define GPIO_PF3_PWM3           0x00050C04
+#define GPIO_PF3_SSI1FSS        0x00050C09
+
+#define GPIO_PF4_CCP0           0x00051001
+#define GPIO_PF4_C0O            0x00051002
+#define GPIO_PF4_MDIO           0x00051003
+#define GPIO_PF4_FAULT0         0x00051004
+#define GPIO_PF4_SSI1RX         0x00051009
+
+#define GPIO_PF5_CCP2           0x00051401
+#define GPIO_PF5_C1O            0x00051402
+#define GPIO_PF5_RXD3           0x00051403
+#define GPIO_PF5_SSI1TX         0x00051409
+
+#define GPIO_PF6_CCP1           0x00051801
+#define GPIO_PF6_RXD2           0x00051803
+#define GPIO_PF6_PHA0           0x00051804
+#define GPIO_PF6_I2S0TXMCLK     0x00051809
+#define GPIO_PF6_U1RTS          0x0005180A
+
+#define GPIO_PF7_CCP4           0x00051C01
+#define GPIO_PF7_RXD1           0x00051C03
+#define GPIO_PF7_PHB0           0x00051C04
+#define GPIO_PF7_FAULT1         0x00051C09
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_PWM0           0x00060002
+#define GPIO_PG0_I2C1SCL        0x00060003
+#define GPIO_PG0_PWM4           0x00060004
+#define GPIO_PG0_USB0EPEN       0x00060007
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_PWM1           0x00060402
+#define GPIO_PG1_I2C1SDA        0x00060403
+#define GPIO_PG1_PWM5           0x00060404
+
+#define GPIO_PG2_PWM0           0x00060801
+#define GPIO_PG2_COL            0x00060803
+#define GPIO_PG2_FAULT0         0x00060804
+#define GPIO_PG2_IDX1           0x00060808
+#define GPIO_PG2_I2S0RXSD       0x00060809
+
+#define GPIO_PG3_PWM1           0x00060C01
+#define GPIO_PG3_CRS            0x00060C03
+#define GPIO_PG3_FAULT2         0x00060C04
+#define GPIO_PG3_FAULT0         0x00060C08
+#define GPIO_PG3_I2S0RXMCLK     0x00060C09
+
+#define GPIO_PG4_CCP3           0x00061001
+#define GPIO_PG4_RXD0           0x00061003
+#define GPIO_PG4_FAULT1         0x00061004
+#define GPIO_PG4_U1RI           0x0006100A
+
+#define GPIO_PG5_CCP5           0x00061401
+#define GPIO_PG5_TXEN           0x00061403
+#define GPIO_PG5_IDX0           0x00061404
+#define GPIO_PG5_FAULT1         0x00061405
+#define GPIO_PG5_I2S0RXSCK      0x00061409
+#define GPIO_PG5_U1DTR          0x0006140A
+
+#define GPIO_PG6_PHA1           0x00061801
+#define GPIO_PG6_TXCK           0x00061803
+#define GPIO_PG6_FAULT1         0x00061808
+#define GPIO_PG6_I2S0RXWS       0x00061809
+#define GPIO_PG6_U1RI           0x0006180A
+
+#define GPIO_PG7_PHB1           0x00061C01
+#define GPIO_PG7_TXER           0x00061C03
+#define GPIO_PG7_CCP5           0x00061C08
+
+#define GPIO_PH0_CCP6           0x00070001
+#define GPIO_PH0_PWM2           0x00070002
+#define GPIO_PH0_PWM4           0x00070009
+
+#define GPIO_PH1_CCP7           0x00070401
+#define GPIO_PH1_PWM3           0x00070402
+#define GPIO_PH1_PWM5           0x00070409
+
+#define GPIO_PH2_IDX1           0x00070801
+#define GPIO_PH2_C1O            0x00070802
+#define GPIO_PH2_FAULT3         0x00070804
+#define GPIO_PH2_TXD3           0x00070809
+
+#define GPIO_PH3_PHB0           0x00070C01
+#define GPIO_PH3_FAULT0         0x00070C02
+#define GPIO_PH3_USB0EPEN       0x00070C04
+#define GPIO_PH3_TXD2           0x00070C09
+
+#define GPIO_PH4_USB0PFLT       0x00071004
+#define GPIO_PH4_TXD1           0x00071009
+#define GPIO_PH4_SSI1CLK        0x0007100B
+
+#define GPIO_PH5_TXD0           0x00071409
+#define GPIO_PH5_FAULT2         0x0007140A
+#define GPIO_PH5_SSI1FSS        0x0007140B
+
+#define GPIO_PH6_RXDV           0x00071809
+#define GPIO_PH6_PWM4           0x0007180A
+#define GPIO_PH6_SSI1RX         0x0007180B
+
+#define GPIO_PH7_RXCK           0x00071C03
+#define GPIO_PH7_PWM5           0x00071C0A
+#define GPIO_PH7_SSI1TX         0x00071C0B
+
+#define GPIO_PJ0_RXER           0x00080003
+#define GPIO_PJ0_PWM0           0x0008000A
+#define GPIO_PJ0_I2C1SCL        0x0008000B
+
+#define GPIO_PJ1_USB0PFLT       0x00080409
+#define GPIO_PJ1_PWM1           0x0008040A
+#define GPIO_PJ1_I2C1SDA        0x0008040B
+
+#define GPIO_PJ2_CCP0           0x00080809
+#define GPIO_PJ2_FAULT0         0x0008080A
+
+#define GPIO_PJ3_U1CTS          0x00080C09
+#define GPIO_PJ3_CCP6           0x00080C0A
+
+#define GPIO_PJ4_U1DCD          0x00081009
+#define GPIO_PJ4_CCP4           0x0008100A
+
+#define GPIO_PJ5_U1DSR          0x00081409
+#define GPIO_PJ5_CCP2           0x0008140A
+
+#define GPIO_PJ6_U1RTS          0x00081809
+#define GPIO_PJ6_CCP1           0x0008180A
+
+#define GPIO_PJ7_U1DTR          0x00081C09
+#define GPIO_PJ7_CCP0           0x00081C0A
+
+#endif // PART_LM3S9971
+
+//*****************************************************************************
+//
+// LM3S9997 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S9997
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_PWM4           0x00000804
+#define GPIO_PA2_I2S0RXSD       0x00000809
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_PWM5           0x00000C04
+#define GPIO_PA3_I2S0RXMCLK     0x00000C09
+
+#define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_CAN0RX         0x00001005
+#define GPIO_PA4_I2S0TXSCK      0x00001009
+
+#define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_CAN0TX         0x00001405
+#define GPIO_PA5_I2S0TXWS       0x00001409
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_PWM0           0x00001804
+#define GPIO_PA6_PWM4           0x00001805
+#define GPIO_PA6_CAN0RX         0x00001806
+#define GPIO_PA6_USB0EPEN       0x00001808
+#define GPIO_PA6_U1CTS          0x00001809
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_PWM1           0x00001C04
+#define GPIO_PA7_PWM5           0x00001C05
+#define GPIO_PA7_CAN0TX         0x00001C06
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_USB0PFLT       0x00001C08
+#define GPIO_PA7_U1DCD          0x00001C09
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_PWM2           0x00010002
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_PWM3           0x00010402
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_IDX0           0x00010802
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+#define GPIO_PB2_USB0EPEN       0x00010808
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_FAULT0         0x00010C02
+#define GPIO_PB3_FAULT3         0x00010C04
+#define GPIO_PB3_USB0PFLT       0x00010C08
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_CAN0RX         0x00011005
+#define GPIO_PB4_IDX0           0x00011006
+#define GPIO_PB4_U1RX           0x00011007
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CAN0TX         0x00011405
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_FAULT1         0x00011804
+#define GPIO_PB6_IDX0           0x00011805
+#define GPIO_PB6_CCP5           0x00011806
+#define GPIO_PB6_I2S0TXSCK      0x00011809
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_PHA0           0x00021002
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_FAULT2         0x00021404
+#define GPIO_PC5_CCP3           0x00021405
+#define GPIO_PC5_USB0EPEN       0x00021406
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_PHB0           0x00021802
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+#define GPIO_PC6_USB0PFLT       0x00021807
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_PHB0           0x00021C02
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_USB0PFLT       0x00021C06
+#define GPIO_PC7_C1O            0x00021C07
+
+#define GPIO_PD0_PWM0           0x00030001
+#define GPIO_PD0_CAN0RX         0x00030002
+#define GPIO_PD0_IDX0           0x00030003
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+#define GPIO_PD0_I2S0RXSCK      0x00030008
+#define GPIO_PD0_U1CTS          0x00030009
+
+#define GPIO_PD1_PWM1           0x00030401
+#define GPIO_PD1_CAN0TX         0x00030402
+#define GPIO_PD1_PHA0           0x00030403
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_I2S0RXWS       0x00030408
+#define GPIO_PD1_U1DCD          0x00030409
+#define GPIO_PD1_CCP2           0x0003040A
+#define GPIO_PD1_PHB1           0x0003040B
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_PWM2           0x00030803
+#define GPIO_PD2_CCP5           0x00030804
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_PWM3           0x00030C03
+#define GPIO_PD3_CCP0           0x00030C04
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+#define GPIO_PD4_I2S0RXSD       0x00031008
+#define GPIO_PD4_U1RI           0x00031009
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_I2S0RXMCLK     0x00031408
+#define GPIO_PD5_U2RX           0x00031409
+
+#define GPIO_PD6_FAULT0         0x00031801
+#define GPIO_PD6_I2S0TXSCK      0x00031808
+#define GPIO_PD6_U2TX           0x00031809
+
+#define GPIO_PD7_IDX0           0x00031C01
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+#define GPIO_PD7_I2S0TXWS       0x00031C08
+#define GPIO_PD7_U1DTR          0x00031C09
+
+#define GPIO_PE0_PWM4           0x00040001
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+#define GPIO_PE0_USB0PFLT       0x00040009
+
+#define GPIO_PE1_PWM5           0x00040401
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_FAULT0         0x00040403
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_PHB1           0x00040803
+#define GPIO_PE2_PHA0           0x00040804
+#define GPIO_PE2_CCP2           0x00040805
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_PHA1           0x00040C03
+#define GPIO_PE3_PHB0           0x00040C04
+#define GPIO_PE3_CCP7           0x00040C05
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_FAULT0         0x00041004
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+#define GPIO_PE4_I2S0TXWS       0x00041009
+
+#define GPIO_PE5_CCP5           0x00041401
+#define GPIO_PE5_I2S0TXSD       0x00041409
+
+#define GPIO_PE6_PWM4           0x00041801
+#define GPIO_PE6_C1O            0x00041802
+#define GPIO_PE6_U1CTS          0x00041809
+
+#define GPIO_PE7_PWM5           0x00041C01
+#define GPIO_PE7_U1DCD          0x00041C09
+
+#define GPIO_PF0_CAN1RX         0x00050001
+#define GPIO_PF0_PHB0           0x00050002
+#define GPIO_PF0_PWM0           0x00050003
+#define GPIO_PF0_I2S0TXSD       0x00050008
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_CAN1TX         0x00050401
+#define GPIO_PF1_IDX1           0x00050402
+#define GPIO_PF1_PWM1           0x00050403
+#define GPIO_PF1_I2S0TXMCLK     0x00050408
+#define GPIO_PF1_U1RTS          0x00050409
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_LED1           0x00050801
+#define GPIO_PF2_PWM4           0x00050802
+#define GPIO_PF2_PWM2           0x00050804
+#define GPIO_PF2_SSI1CLK        0x00050809
+
+#define GPIO_PF3_LED0           0x00050C01
+#define GPIO_PF3_PWM5           0x00050C02
+#define GPIO_PF3_PWM3           0x00050C04
+#define GPIO_PF3_SSI1FSS        0x00050C09
+
+#define GPIO_PF4_CCP0           0x00051001
+#define GPIO_PF4_C0O            0x00051002
+#define GPIO_PF4_FAULT0         0x00051004
+#define GPIO_PF4_SSI1RX         0x00051009
+
+#define GPIO_PF5_CCP2           0x00051401
+#define GPIO_PF5_C1O            0x00051402
+#define GPIO_PF5_SSI1TX         0x00051409
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_PWM0           0x00060002
+#define GPIO_PG0_I2C1SCL        0x00060003
+#define GPIO_PG0_PWM4           0x00060004
+#define GPIO_PG0_USB0EPEN       0x00060007
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_PWM1           0x00060402
+#define GPIO_PG1_I2C1SDA        0x00060403
+#define GPIO_PG1_PWM5           0x00060404
+
+#define GPIO_PG7_PHB1           0x00061C01
+#define GPIO_PG7_CCP5           0x00061C08
+
+#define GPIO_PH0_CCP6           0x00070001
+#define GPIO_PH0_PWM2           0x00070002
+#define GPIO_PH0_PWM4           0x00070009
+
+#define GPIO_PH1_CCP7           0x00070401
+#define GPIO_PH1_PWM3           0x00070402
+#define GPIO_PH1_PWM5           0x00070409
+
+#define GPIO_PH2_IDX1           0x00070801
+#define GPIO_PH2_C1O            0x00070802
+#define GPIO_PH2_FAULT3         0x00070804
+
+#define GPIO_PH3_PHB0           0x00070C01
+#define GPIO_PH3_FAULT0         0x00070C02
+#define GPIO_PH3_USB0EPEN       0x00070C04
+
+#define GPIO_PH4_USB0PFLT       0x00071004
+#define GPIO_PH4_SSI1CLK        0x0007100B
+
+#define GPIO_PH5_FAULT2         0x0007140A
+#define GPIO_PH5_SSI1FSS        0x0007140B
+
+#define GPIO_PH6_PWM4           0x0007180A
+#define GPIO_PH6_SSI1RX         0x0007180B
+
+#define GPIO_PH7_PWM5           0x00071C0A
+#define GPIO_PH7_SSI1TX         0x00071C0B
+
+#define GPIO_PJ0_PWM0           0x0008000A
+#define GPIO_PJ0_I2C1SCL        0x0008000B
+
+#define GPIO_PJ1_USB0PFLT       0x00080409
+#define GPIO_PJ1_PWM1           0x0008040A
+#define GPIO_PJ1_I2C1SDA        0x0008040B
+
+#define GPIO_PJ2_CCP0           0x00080809
+#define GPIO_PJ2_FAULT0         0x0008080A
+
+#endif // PART_LM3S9997
+
+//*****************************************************************************
+//
+// LM3S9B81 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S9B81
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_I2S0RXSD       0x00000809
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_I2S0RXMCLK     0x00000C09
+
+#define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_CAN0RX         0x00001005
+#define GPIO_PA4_I2S0TXSCK      0x00001009
+
+#define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_CAN0TX         0x00001405
+#define GPIO_PA5_I2S0TXWS       0x00001409
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_CAN0RX         0x00001806
+#define GPIO_PA6_USB0EPEN       0x00001808
+#define GPIO_PA6_U1CTS          0x00001809
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_CAN0TX         0x00001C06
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_USB0PFLT       0x00001C08
+#define GPIO_PA7_U1DCD          0x00001C09
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+#define GPIO_PB2_USB0EPEN       0x00010808
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_USB0PFLT       0x00010C08
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_CAN0RX         0x00011005
+#define GPIO_PB4_U1RX           0x00011007
+#define GPIO_PB4_EPI0S23        0x00011008
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CAN0TX         0x00011405
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+#define GPIO_PB5_EPI0S22        0x00011408
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_CCP5           0x00011806
+#define GPIO_PB6_I2S0TXSCK      0x00011809
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_EPI0S2         0x00021008
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_CCP3           0x00021405
+#define GPIO_PC5_USB0EPEN       0x00021406
+#define GPIO_PC5_EPI0S3         0x00021408
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_C2O            0x00021803
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+#define GPIO_PC6_USB0PFLT       0x00021807
+#define GPIO_PC6_EPI0S4         0x00021808
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_USB0PFLT       0x00021C06
+#define GPIO_PC7_C1O            0x00021C07
+#define GPIO_PC7_EPI0S5         0x00021C08
+
+#define GPIO_PD0_CAN0RX         0x00030002
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+#define GPIO_PD0_I2S0RXSCK      0x00030008
+#define GPIO_PD0_U1CTS          0x00030009
+
+#define GPIO_PD1_CAN0TX         0x00030402
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_I2S0RXWS       0x00030408
+#define GPIO_PD1_U1DCD          0x00030409
+#define GPIO_PD1_CCP2           0x0003040A
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_CCP5           0x00030804
+#define GPIO_PD2_EPI0S20        0x00030808
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_CCP0           0x00030C04
+#define GPIO_PD3_EPI0S21        0x00030C08
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+#define GPIO_PD4_I2S0RXSD       0x00031008
+#define GPIO_PD4_U1RI           0x00031009
+#define GPIO_PD4_EPI0S19        0x0003100A
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_I2S0RXMCLK     0x00031408
+#define GPIO_PD5_U2RX           0x00031409
+#define GPIO_PD5_EPI0S28        0x0003140A
+
+#define GPIO_PD6_I2S0TXSCK      0x00031808
+#define GPIO_PD6_U2TX           0x00031809
+#define GPIO_PD6_EPI0S29        0x0003180A
+
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+#define GPIO_PD7_I2S0TXWS       0x00031C08
+#define GPIO_PD7_U1DTR          0x00031C09
+#define GPIO_PD7_EPI0S30        0x00031C0A
+
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+#define GPIO_PE0_EPI0S8         0x00040008
+#define GPIO_PE0_USB0PFLT       0x00040009
+
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+#define GPIO_PE1_EPI0S9         0x00040408
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_CCP2           0x00040805
+#define GPIO_PE2_EPI0S24        0x00040808
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_CCP7           0x00040C05
+#define GPIO_PE3_EPI0S25        0x00040C08
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_CAN2RX         0x00041002
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+#define GPIO_PE4_I2S0TXWS       0x00041009
+
+#define GPIO_PE5_CCP5           0x00041401
+#define GPIO_PE5_CAN2TX         0x00041402
+#define GPIO_PE5_I2S0TXSD       0x00041409
+
+#define GPIO_PE6_C1O            0x00041802
+#define GPIO_PE6_U1CTS          0x00041809
+
+#define GPIO_PE7_C2O            0x00041C02
+#define GPIO_PE7_U1DCD          0x00041C09
+
+#define GPIO_PF0_CAN1RX         0x00050001
+#define GPIO_PF0_I2S0TXSD       0x00050008
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_CAN1TX         0x00050401
+#define GPIO_PF1_I2S0TXMCLK     0x00050408
+#define GPIO_PF1_U1RTS          0x00050409
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_LED1           0x00050801
+#define GPIO_PF2_SSI1CLK        0x00050809
+
+#define GPIO_PF3_LED0           0x00050C01
+#define GPIO_PF3_SSI1FSS        0x00050C09
+
+#define GPIO_PF4_CCP0           0x00051001
+#define GPIO_PF4_C0O            0x00051002
+#define GPIO_PF4_EPI0S12        0x00051008
+#define GPIO_PF4_SSI1RX         0x00051009
+
+#define GPIO_PF5_CCP2           0x00051401
+#define GPIO_PF5_C1O            0x00051402
+#define GPIO_PF5_EPI0S15        0x00051408
+#define GPIO_PF5_SSI1TX         0x00051409
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_I2C1SCL        0x00060003
+#define GPIO_PG0_USB0EPEN       0x00060007
+#define GPIO_PG0_EPI0S13        0x00060008
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_I2C1SDA        0x00060403
+#define GPIO_PG1_EPI0S14        0x00060408
+
+#define GPIO_PG7_CCP5           0x00061C08
+#define GPIO_PG7_EPI0S31        0x00061C09
+
+#define GPIO_PH0_CCP6           0x00070001
+#define GPIO_PH0_EPI0S6         0x00070008
+
+#define GPIO_PH1_CCP7           0x00070401
+#define GPIO_PH1_EPI0S7         0x00070408
+
+#define GPIO_PH2_C1O            0x00070802
+#define GPIO_PH2_EPI0S1         0x00070808
+
+#define GPIO_PH3_USB0EPEN       0x00070C04
+#define GPIO_PH3_EPI0S0         0x00070C08
+
+#define GPIO_PH4_USB0PFLT       0x00071004
+#define GPIO_PH4_EPI0S10        0x00071008
+#define GPIO_PH4_SSI1CLK        0x0007100B
+
+#define GPIO_PH5_EPI0S11        0x00071408
+#define GPIO_PH5_SSI1FSS        0x0007140B
+
+#define GPIO_PH6_EPI0S26        0x00071808
+#define GPIO_PH6_SSI1RX         0x0007180B
+
+#define GPIO_PH7_EPI0S27        0x00071C08
+#define GPIO_PH7_SSI1TX         0x00071C0B
+
+#define GPIO_PJ0_EPI0S16        0x00080008
+#define GPIO_PJ0_I2C1SCL        0x0008000B
+
+#define GPIO_PJ1_EPI0S17        0x00080408
+#define GPIO_PJ1_USB0PFLT       0x00080409
+#define GPIO_PJ1_I2C1SDA        0x0008040B
+
+#define GPIO_PJ2_EPI0S18        0x00080808
+#define GPIO_PJ2_CCP0           0x00080809
+
+#define GPIO_PJ3_EPI0S19        0x00080C08
+#define GPIO_PJ3_U1CTS          0x00080C09
+#define GPIO_PJ3_CCP6           0x00080C0A
+
+#define GPIO_PJ4_EPI0S28        0x00081008
+#define GPIO_PJ4_U1DCD          0x00081009
+#define GPIO_PJ4_CCP4           0x0008100A
+
+#define GPIO_PJ5_EPI0S29        0x00081408
+#define GPIO_PJ5_U1DSR          0x00081409
+#define GPIO_PJ5_CCP2           0x0008140A
+
+#define GPIO_PJ6_EPI0S30        0x00081808
+#define GPIO_PJ6_U1RTS          0x00081809
+#define GPIO_PJ6_CCP1           0x0008180A
+
+#define GPIO_PJ7_U1DTR          0x00081C09
+#define GPIO_PJ7_CCP0           0x00081C0A
+
+#endif // PART_LM3S9B81
+
+//*****************************************************************************
+//
+// LM3S9B90 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S9B90
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_I2S0RXSD       0x00000809
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_I2S0RXMCLK     0x00000C09
+
+#define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_CAN0RX         0x00001005
+#define GPIO_PA4_I2S0TXSCK      0x00001009
+
+#define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_CAN0TX         0x00001405
+#define GPIO_PA5_I2S0TXWS       0x00001409
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_CAN0RX         0x00001806
+#define GPIO_PA6_USB0EPEN       0x00001808
+#define GPIO_PA6_U1CTS          0x00001809
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_CAN0TX         0x00001C06
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_USB0PFLT       0x00001C08
+#define GPIO_PA7_U1DCD          0x00001C09
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+#define GPIO_PB2_USB0EPEN       0x00010808
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_USB0PFLT       0x00010C08
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_CAN0RX         0x00011005
+#define GPIO_PB4_U1RX           0x00011007
+#define GPIO_PB4_EPI0S23        0x00011008
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CAN0TX         0x00011405
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+#define GPIO_PB5_EPI0S22        0x00011408
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_CCP5           0x00011806
+#define GPIO_PB6_I2S0TXSCK      0x00011809
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_EPI0S2         0x00021008
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_CCP3           0x00021405
+#define GPIO_PC5_USB0EPEN       0x00021406
+#define GPIO_PC5_EPI0S3         0x00021408
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_C2O            0x00021803
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+#define GPIO_PC6_USB0PFLT       0x00021807
+#define GPIO_PC6_EPI0S4         0x00021808
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_USB0PFLT       0x00021C06
+#define GPIO_PC7_C1O            0x00021C07
+#define GPIO_PC7_EPI0S5         0x00021C08
+
+#define GPIO_PD0_CAN0RX         0x00030002
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+#define GPIO_PD0_I2S0RXSCK      0x00030008
+#define GPIO_PD0_U1CTS          0x00030009
+
+#define GPIO_PD1_CAN0TX         0x00030402
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_I2S0RXWS       0x00030408
+#define GPIO_PD1_U1DCD          0x00030409
+#define GPIO_PD1_CCP2           0x0003040A
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_CCP5           0x00030804
+#define GPIO_PD2_EPI0S20        0x00030808
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_CCP0           0x00030C04
+#define GPIO_PD3_EPI0S21        0x00030C08
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+#define GPIO_PD4_I2S0RXSD       0x00031008
+#define GPIO_PD4_U1RI           0x00031009
+#define GPIO_PD4_EPI0S19        0x0003100A
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_I2S0RXMCLK     0x00031408
+#define GPIO_PD5_U2RX           0x00031409
+#define GPIO_PD5_EPI0S28        0x0003140A
+
+#define GPIO_PD6_I2S0TXSCK      0x00031808
+#define GPIO_PD6_U2TX           0x00031809
+#define GPIO_PD6_EPI0S29        0x0003180A
+
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+#define GPIO_PD7_I2S0TXWS       0x00031C08
+#define GPIO_PD7_U1DTR          0x00031C09
+#define GPIO_PD7_EPI0S30        0x00031C0A
+
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+#define GPIO_PE0_EPI0S8         0x00040008
+#define GPIO_PE0_USB0PFLT       0x00040009
+
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+#define GPIO_PE1_EPI0S9         0x00040408
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_CCP2           0x00040805
+#define GPIO_PE2_EPI0S24        0x00040808
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_CCP7           0x00040C05
+#define GPIO_PE3_EPI0S25        0x00040C08
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+#define GPIO_PE4_I2S0TXWS       0x00041009
+
+#define GPIO_PE5_CCP5           0x00041401
+#define GPIO_PE5_I2S0TXSD       0x00041409
+
+#define GPIO_PE6_C1O            0x00041802
+#define GPIO_PE6_U1CTS          0x00041809
+
+#define GPIO_PE7_C2O            0x00041C02
+#define GPIO_PE7_U1DCD          0x00041C09
+
+#define GPIO_PF0_CAN1RX         0x00050001
+#define GPIO_PF0_I2S0TXSD       0x00050008
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_CAN1TX         0x00050401
+#define GPIO_PF1_I2S0TXMCLK     0x00050408
+#define GPIO_PF1_U1RTS          0x00050409
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_LED1           0x00050801
+#define GPIO_PF2_SSI1CLK        0x00050809
+
+#define GPIO_PF3_LED0           0x00050C01
+#define GPIO_PF3_SSI1FSS        0x00050C09
+
+#define GPIO_PF4_CCP0           0x00051001
+#define GPIO_PF4_C0O            0x00051002
+#define GPIO_PF4_EPI0S12        0x00051008
+#define GPIO_PF4_SSI1RX         0x00051009
+
+#define GPIO_PF5_CCP2           0x00051401
+#define GPIO_PF5_C1O            0x00051402
+#define GPIO_PF5_EPI0S15        0x00051408
+#define GPIO_PF5_SSI1TX         0x00051409
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_I2C1SCL        0x00060003
+#define GPIO_PG0_USB0EPEN       0x00060007
+#define GPIO_PG0_EPI0S13        0x00060008
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_I2C1SDA        0x00060403
+#define GPIO_PG1_EPI0S14        0x00060408
+
+#define GPIO_PG7_CCP5           0x00061C08
+#define GPIO_PG7_EPI0S31        0x00061C09
+
+#define GPIO_PH0_CCP6           0x00070001
+#define GPIO_PH0_EPI0S6         0x00070008
+
+#define GPIO_PH1_CCP7           0x00070401
+#define GPIO_PH1_EPI0S7         0x00070408
+
+#define GPIO_PH2_C1O            0x00070802
+#define GPIO_PH2_EPI0S1         0x00070808
+
+#define GPIO_PH3_USB0EPEN       0x00070C04
+#define GPIO_PH3_EPI0S0         0x00070C08
+
+#define GPIO_PH4_USB0PFLT       0x00071004
+#define GPIO_PH4_EPI0S10        0x00071008
+#define GPIO_PH4_SSI1CLK        0x0007100B
+
+#define GPIO_PH5_EPI0S11        0x00071408
+#define GPIO_PH5_SSI1FSS        0x0007140B
+
+#define GPIO_PH6_EPI0S26        0x00071808
+#define GPIO_PH6_SSI1RX         0x0007180B
+
+#define GPIO_PH7_EPI0S27        0x00071C08
+#define GPIO_PH7_SSI1TX         0x00071C0B
+
+#define GPIO_PJ0_EPI0S16        0x00080008
+#define GPIO_PJ0_I2C1SCL        0x0008000B
+
+#define GPIO_PJ1_EPI0S17        0x00080408
+#define GPIO_PJ1_USB0PFLT       0x00080409
+#define GPIO_PJ1_I2C1SDA        0x0008040B
+
+#define GPIO_PJ2_EPI0S18        0x00080808
+#define GPIO_PJ2_CCP0           0x00080809
+
+#endif // PART_LM3S9B90
+
+//*****************************************************************************
+//
+// LM3S9B92 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S9B92
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_PWM4           0x00000804
+#define GPIO_PA2_I2S0RXSD       0x00000809
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_PWM5           0x00000C04
+#define GPIO_PA3_I2S0RXMCLK     0x00000C09
+
+#define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_PWM6           0x00001004
+#define GPIO_PA4_CAN0RX         0x00001005
+#define GPIO_PA4_I2S0TXSCK      0x00001009
+
+#define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_PWM7           0x00001404
+#define GPIO_PA5_CAN0TX         0x00001405
+#define GPIO_PA5_I2S0TXWS       0x00001409
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_PWM0           0x00001804
+#define GPIO_PA6_PWM4           0x00001805
+#define GPIO_PA6_CAN0RX         0x00001806
+#define GPIO_PA6_USB0EPEN       0x00001808
+#define GPIO_PA6_U1CTS          0x00001809
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_PWM1           0x00001C04
+#define GPIO_PA7_PWM5           0x00001C05
+#define GPIO_PA7_CAN0TX         0x00001C06
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_USB0PFLT       0x00001C08
+#define GPIO_PA7_U1DCD          0x00001C09
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_PWM2           0x00010002
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_PWM3           0x00010402
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_IDX0           0x00010802
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+#define GPIO_PB2_USB0EPEN       0x00010808
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_FAULT0         0x00010C02
+#define GPIO_PB3_FAULT3         0x00010C04
+#define GPIO_PB3_USB0PFLT       0x00010C08
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_CAN0RX         0x00011005
+#define GPIO_PB4_IDX0           0x00011006
+#define GPIO_PB4_U1RX           0x00011007
+#define GPIO_PB4_EPI0S23        0x00011008
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CAN0TX         0x00011405
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+#define GPIO_PB5_EPI0S22        0x00011408
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_FAULT1         0x00011804
+#define GPIO_PB6_IDX0           0x00011805
+#define GPIO_PB6_CCP5           0x00011806
+#define GPIO_PB6_I2S0TXSCK      0x00011809
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_PHA0           0x00021002
+#define GPIO_PC4_PWM6           0x00021004
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_EPI0S2         0x00021008
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_FAULT2         0x00021404
+#define GPIO_PC5_CCP3           0x00021405
+#define GPIO_PC5_USB0EPEN       0x00021406
+#define GPIO_PC5_EPI0S3         0x00021408
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_PHB0           0x00021802
+#define GPIO_PC6_C2O            0x00021803
+#define GPIO_PC6_PWM7           0x00021804
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+#define GPIO_PC6_USB0PFLT       0x00021807
+#define GPIO_PC6_EPI0S4         0x00021808
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_PHB0           0x00021C02
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_USB0PFLT       0x00021C06
+#define GPIO_PC7_C1O            0x00021C07
+#define GPIO_PC7_EPI0S5         0x00021C08
+
+#define GPIO_PD0_PWM0           0x00030001
+#define GPIO_PD0_CAN0RX         0x00030002
+#define GPIO_PD0_IDX0           0x00030003
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+#define GPIO_PD0_I2S0RXSCK      0x00030008
+#define GPIO_PD0_U1CTS          0x00030009
+
+#define GPIO_PD1_PWM1           0x00030401
+#define GPIO_PD1_CAN0TX         0x00030402
+#define GPIO_PD1_PHA0           0x00030403
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_I2S0RXWS       0x00030408
+#define GPIO_PD1_U1DCD          0x00030409
+#define GPIO_PD1_CCP2           0x0003040A
+#define GPIO_PD1_PHB1           0x0003040B
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_PWM2           0x00030803
+#define GPIO_PD2_CCP5           0x00030804
+#define GPIO_PD2_EPI0S20        0x00030808
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_PWM3           0x00030C03
+#define GPIO_PD3_CCP0           0x00030C04
+#define GPIO_PD3_EPI0S21        0x00030C08
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+#define GPIO_PD4_I2S0RXSD       0x00031008
+#define GPIO_PD4_U1RI           0x00031009
+#define GPIO_PD4_EPI0S19        0x0003100A
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_I2S0RXMCLK     0x00031408
+#define GPIO_PD5_U2RX           0x00031409
+#define GPIO_PD5_EPI0S28        0x0003140A
+
+#define GPIO_PD6_FAULT0         0x00031801
+#define GPIO_PD6_I2S0TXSCK      0x00031808
+#define GPIO_PD6_U2TX           0x00031809
+#define GPIO_PD6_EPI0S29        0x0003180A
+
+#define GPIO_PD7_IDX0           0x00031C01
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+#define GPIO_PD7_I2S0TXWS       0x00031C08
+#define GPIO_PD7_U1DTR          0x00031C09
+#define GPIO_PD7_EPI0S30        0x00031C0A
+
+#define GPIO_PE0_PWM4           0x00040001
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+#define GPIO_PE0_EPI0S8         0x00040008
+#define GPIO_PE0_USB0PFLT       0x00040009
+
+#define GPIO_PE1_PWM5           0x00040401
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_FAULT0         0x00040403
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+#define GPIO_PE1_EPI0S9         0x00040408
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_PHB1           0x00040803
+#define GPIO_PE2_PHA0           0x00040804
+#define GPIO_PE2_CCP2           0x00040805
+#define GPIO_PE2_EPI0S24        0x00040808
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_PHA1           0x00040C03
+#define GPIO_PE3_PHB0           0x00040C04
+#define GPIO_PE3_CCP7           0x00040C05
+#define GPIO_PE3_EPI0S25        0x00040C08
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_FAULT0         0x00041004
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+#define GPIO_PE4_I2S0TXWS       0x00041009
+
+#define GPIO_PE5_CCP5           0x00041401
+#define GPIO_PE5_I2S0TXSD       0x00041409
+
+#define GPIO_PE6_PWM4           0x00041801
+#define GPIO_PE6_C1O            0x00041802
+#define GPIO_PE6_U1CTS          0x00041809
+
+#define GPIO_PE7_PWM5           0x00041C01
+#define GPIO_PE7_C2O            0x00041C02
+#define GPIO_PE7_U1DCD          0x00041C09
+
+#define GPIO_PF0_CAN1RX         0x00050001
+#define GPIO_PF0_PHB0           0x00050002
+#define GPIO_PF0_PWM0           0x00050003
+#define GPIO_PF0_I2S0TXSD       0x00050008
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_CAN1TX         0x00050401
+#define GPIO_PF1_IDX1           0x00050402
+#define GPIO_PF1_PWM1           0x00050403
+#define GPIO_PF1_I2S0TXMCLK     0x00050408
+#define GPIO_PF1_U1RTS          0x00050409
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_LED1           0x00050801
+#define GPIO_PF2_PWM4           0x00050802
+#define GPIO_PF2_PWM2           0x00050804
+#define GPIO_PF2_SSI1CLK        0x00050809
+
+#define GPIO_PF3_LED0           0x00050C01
+#define GPIO_PF3_PWM5           0x00050C02
+#define GPIO_PF3_PWM3           0x00050C04
+#define GPIO_PF3_SSI1FSS        0x00050C09
+
+#define GPIO_PF4_CCP0           0x00051001
+#define GPIO_PF4_C0O            0x00051002
+#define GPIO_PF4_FAULT0         0x00051004
+#define GPIO_PF4_EPI0S12        0x00051008
+#define GPIO_PF4_SSI1RX         0x00051009
+
+#define GPIO_PF5_CCP2           0x00051401
+#define GPIO_PF5_C1O            0x00051402
+#define GPIO_PF5_EPI0S15        0x00051408
+#define GPIO_PF5_SSI1TX         0x00051409
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_PWM0           0x00060002
+#define GPIO_PG0_I2C1SCL        0x00060003
+#define GPIO_PG0_PWM4           0x00060004
+#define GPIO_PG0_USB0EPEN       0x00060007
+#define GPIO_PG0_EPI0S13        0x00060008
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_PWM1           0x00060402
+#define GPIO_PG1_I2C1SDA        0x00060403
+#define GPIO_PG1_PWM5           0x00060404
+#define GPIO_PG1_EPI0S14        0x00060408
+
+#define GPIO_PG7_PHB1           0x00061C01
+#define GPIO_PG7_PWM7           0x00061C04
+#define GPIO_PG7_CCP5           0x00061C08
+#define GPIO_PG7_EPI0S31        0x00061C09
+
+#define GPIO_PH0_CCP6           0x00070001
+#define GPIO_PH0_PWM2           0x00070002
+#define GPIO_PH0_EPI0S6         0x00070008
+#define GPIO_PH0_PWM4           0x00070009
+
+#define GPIO_PH1_CCP7           0x00070401
+#define GPIO_PH1_PWM3           0x00070402
+#define GPIO_PH1_EPI0S7         0x00070408
+#define GPIO_PH1_PWM5           0x00070409
+
+#define GPIO_PH2_IDX1           0x00070801
+#define GPIO_PH2_C1O            0x00070802
+#define GPIO_PH2_FAULT3         0x00070804
+#define GPIO_PH2_EPI0S1         0x00070808
+
+#define GPIO_PH3_PHB0           0x00070C01
+#define GPIO_PH3_FAULT0         0x00070C02
+#define GPIO_PH3_USB0EPEN       0x00070C04
+#define GPIO_PH3_EPI0S0         0x00070C08
+
+#define GPIO_PH4_USB0PFLT       0x00071004
+#define GPIO_PH4_EPI0S10        0x00071008
+#define GPIO_PH4_SSI1CLK        0x0007100B
+
+#define GPIO_PH5_EPI0S11        0x00071408
+#define GPIO_PH5_FAULT2         0x0007140A
+#define GPIO_PH5_SSI1FSS        0x0007140B
+
+#define GPIO_PH6_EPI0S26        0x00071808
+#define GPIO_PH6_PWM4           0x0007180A
+#define GPIO_PH6_SSI1RX         0x0007180B
+
+#define GPIO_PH7_EPI0S27        0x00071C08
+#define GPIO_PH7_PWM5           0x00071C0A
+#define GPIO_PH7_SSI1TX         0x00071C0B
+
+#define GPIO_PJ0_EPI0S16        0x00080008
+#define GPIO_PJ0_PWM0           0x0008000A
+#define GPIO_PJ0_I2C1SCL        0x0008000B
+
+#define GPIO_PJ1_EPI0S17        0x00080408
+#define GPIO_PJ1_USB0PFLT       0x00080409
+#define GPIO_PJ1_PWM1           0x0008040A
+#define GPIO_PJ1_I2C1SDA        0x0008040B
+
+#define GPIO_PJ2_EPI0S18        0x00080808
+#define GPIO_PJ2_CCP0           0x00080809
+#define GPIO_PJ2_FAULT0         0x0008080A
+
+#define GPIO_PJ3_EPI0S19        0x00080C08
+#define GPIO_PJ3_U1CTS          0x00080C09
+#define GPIO_PJ3_CCP6           0x00080C0A
+
+#define GPIO_PJ4_EPI0S28        0x00081008
+#define GPIO_PJ4_U1DCD          0x00081009
+#define GPIO_PJ4_CCP4           0x0008100A
+
+#define GPIO_PJ5_EPI0S29        0x00081408
+#define GPIO_PJ5_U1DSR          0x00081409
+#define GPIO_PJ5_CCP2           0x0008140A
+
+#define GPIO_PJ6_EPI0S30        0x00081808
+#define GPIO_PJ6_U1RTS          0x00081809
+#define GPIO_PJ6_CCP1           0x0008180A
+
+#define GPIO_PJ7_U1DTR          0x00081C09
+#define GPIO_PJ7_CCP0           0x00081C0A
+
+#endif // PART_LM3S9B92
+
+//*****************************************************************************
+//
+// LM3S9B95 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S9B95
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_PWM4           0x00000804
+#define GPIO_PA2_I2S0RXSD       0x00000809
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_PWM5           0x00000C04
+#define GPIO_PA3_I2S0RXMCLK     0x00000C09
+
+#define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_PWM6           0x00001004
+#define GPIO_PA4_CAN0RX         0x00001005
+#define GPIO_PA4_I2S0TXSCK      0x00001009
+
+#define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_PWM7           0x00001404
+#define GPIO_PA5_CAN0TX         0x00001405
+#define GPIO_PA5_I2S0TXWS       0x00001409
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_PWM0           0x00001804
+#define GPIO_PA6_PWM4           0x00001805
+#define GPIO_PA6_CAN0RX         0x00001806
+#define GPIO_PA6_USB0EPEN       0x00001808
+#define GPIO_PA6_U1CTS          0x00001809
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_PWM1           0x00001C04
+#define GPIO_PA7_PWM5           0x00001C05
+#define GPIO_PA7_CAN0TX         0x00001C06
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_USB0PFLT       0x00001C08
+#define GPIO_PA7_U1DCD          0x00001C09
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_PWM2           0x00010002
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_PWM3           0x00010402
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_IDX0           0x00010802
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+#define GPIO_PB2_USB0EPEN       0x00010808
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_FAULT0         0x00010C02
+#define GPIO_PB3_FAULT3         0x00010C04
+#define GPIO_PB3_USB0PFLT       0x00010C08
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_CAN0RX         0x00011005
+#define GPIO_PB4_IDX0           0x00011006
+#define GPIO_PB4_U1RX           0x00011007
+#define GPIO_PB4_EPI0S23        0x00011008
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CAN0TX         0x00011405
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+#define GPIO_PB5_EPI0S22        0x00011408
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_FAULT1         0x00011804
+#define GPIO_PB6_IDX0           0x00011805
+#define GPIO_PB6_CCP5           0x00011806
+#define GPIO_PB6_I2S0TXSCK      0x00011809
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_PHA0           0x00021002
+#define GPIO_PC4_PWM6           0x00021004
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_EPI0S2         0x00021008
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_FAULT2         0x00021404
+#define GPIO_PC5_CCP3           0x00021405
+#define GPIO_PC5_USB0EPEN       0x00021406
+#define GPIO_PC5_EPI0S3         0x00021408
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_PHB0           0x00021802
+#define GPIO_PC6_C2O            0x00021803
+#define GPIO_PC6_PWM7           0x00021804
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+#define GPIO_PC6_USB0PFLT       0x00021807
+#define GPIO_PC6_EPI0S4         0x00021808
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_PHB0           0x00021C02
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_USB0PFLT       0x00021C06
+#define GPIO_PC7_C1O            0x00021C07
+#define GPIO_PC7_EPI0S5         0x00021C08
+
+#define GPIO_PD0_PWM0           0x00030001
+#define GPIO_PD0_CAN0RX         0x00030002
+#define GPIO_PD0_IDX0           0x00030003
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+#define GPIO_PD0_I2S0RXSCK      0x00030008
+#define GPIO_PD0_U1CTS          0x00030009
+
+#define GPIO_PD1_PWM1           0x00030401
+#define GPIO_PD1_CAN0TX         0x00030402
+#define GPIO_PD1_PHA0           0x00030403
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_I2S0RXWS       0x00030408
+#define GPIO_PD1_U1DCD          0x00030409
+#define GPIO_PD1_CCP2           0x0003040A
+#define GPIO_PD1_PHB1           0x0003040B
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_PWM2           0x00030803
+#define GPIO_PD2_CCP5           0x00030804
+#define GPIO_PD2_EPI0S20        0x00030808
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_PWM3           0x00030C03
+#define GPIO_PD3_CCP0           0x00030C04
+#define GPIO_PD3_EPI0S21        0x00030C08
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+#define GPIO_PD4_I2S0RXSD       0x00031008
+#define GPIO_PD4_U1RI           0x00031009
+#define GPIO_PD4_EPI0S19        0x0003100A
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_I2S0RXMCLK     0x00031408
+#define GPIO_PD5_U2RX           0x00031409
+#define GPIO_PD5_EPI0S28        0x0003140A
+
+#define GPIO_PD6_FAULT0         0x00031801
+#define GPIO_PD6_I2S0TXSCK      0x00031808
+#define GPIO_PD6_U2TX           0x00031809
+#define GPIO_PD6_EPI0S29        0x0003180A
+
+#define GPIO_PD7_IDX0           0x00031C01
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+#define GPIO_PD7_I2S0TXWS       0x00031C08
+#define GPIO_PD7_U1DTR          0x00031C09
+#define GPIO_PD7_EPI0S30        0x00031C0A
+
+#define GPIO_PE0_PWM4           0x00040001
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+#define GPIO_PE0_EPI0S8         0x00040008
+#define GPIO_PE0_USB0PFLT       0x00040009
+
+#define GPIO_PE1_PWM5           0x00040401
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_FAULT0         0x00040403
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+#define GPIO_PE1_EPI0S9         0x00040408
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_PHB1           0x00040803
+#define GPIO_PE2_PHA0           0x00040804
+#define GPIO_PE2_CCP2           0x00040805
+#define GPIO_PE2_EPI0S24        0x00040808
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_PHA1           0x00040C03
+#define GPIO_PE3_PHB0           0x00040C04
+#define GPIO_PE3_CCP7           0x00040C05
+#define GPIO_PE3_EPI0S25        0x00040C08
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_FAULT0         0x00041004
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+#define GPIO_PE4_I2S0TXWS       0x00041009
+
+#define GPIO_PE5_CCP5           0x00041401
+#define GPIO_PE5_I2S0TXSD       0x00041409
+
+#define GPIO_PE6_PWM4           0x00041801
+#define GPIO_PE6_C1O            0x00041802
+#define GPIO_PE6_U1CTS          0x00041809
+
+#define GPIO_PE7_PWM5           0x00041C01
+#define GPIO_PE7_C2O            0x00041C02
+#define GPIO_PE7_U1DCD          0x00041C09
+
+#define GPIO_PF0_CAN1RX         0x00050001
+#define GPIO_PF0_PHB0           0x00050002
+#define GPIO_PF0_PWM0           0x00050003
+#define GPIO_PF0_I2S0TXSD       0x00050008
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_CAN1TX         0x00050401
+#define GPIO_PF1_IDX1           0x00050402
+#define GPIO_PF1_PWM1           0x00050403
+#define GPIO_PF1_I2S0TXMCLK     0x00050408
+#define GPIO_PF1_U1RTS          0x00050409
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_LED1           0x00050801
+#define GPIO_PF2_PWM4           0x00050802
+#define GPIO_PF2_PWM2           0x00050804
+#define GPIO_PF2_SSI1CLK        0x00050809
+
+#define GPIO_PF3_LED0           0x00050C01
+#define GPIO_PF3_PWM5           0x00050C02
+#define GPIO_PF3_PWM3           0x00050C04
+#define GPIO_PF3_SSI1FSS        0x00050C09
+
+#define GPIO_PF4_CCP0           0x00051001
+#define GPIO_PF4_C0O            0x00051002
+#define GPIO_PF4_FAULT0         0x00051004
+#define GPIO_PF4_EPI0S12        0x00051008
+#define GPIO_PF4_SSI1RX         0x00051009
+
+#define GPIO_PF5_CCP2           0x00051401
+#define GPIO_PF5_C1O            0x00051402
+#define GPIO_PF5_EPI0S15        0x00051408
+#define GPIO_PF5_SSI1TX         0x00051409
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_PWM0           0x00060002
+#define GPIO_PG0_I2C1SCL        0x00060003
+#define GPIO_PG0_PWM4           0x00060004
+#define GPIO_PG0_USB0EPEN       0x00060007
+#define GPIO_PG0_EPI0S13        0x00060008
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_PWM1           0x00060402
+#define GPIO_PG1_I2C1SDA        0x00060403
+#define GPIO_PG1_PWM5           0x00060404
+#define GPIO_PG1_EPI0S14        0x00060408
+
+#define GPIO_PG7_PHB1           0x00061C01
+#define GPIO_PG7_PWM7           0x00061C04
+#define GPIO_PG7_CCP5           0x00061C08
+#define GPIO_PG7_EPI0S31        0x00061C09
+
+#define GPIO_PH0_CCP6           0x00070001
+#define GPIO_PH0_PWM2           0x00070002
+#define GPIO_PH0_EPI0S6         0x00070008
+#define GPIO_PH0_PWM4           0x00070009
+
+#define GPIO_PH1_CCP7           0x00070401
+#define GPIO_PH1_PWM3           0x00070402
+#define GPIO_PH1_EPI0S7         0x00070408
+#define GPIO_PH1_PWM5           0x00070409
+
+#define GPIO_PH2_IDX1           0x00070801
+#define GPIO_PH2_C1O            0x00070802
+#define GPIO_PH2_FAULT3         0x00070804
+#define GPIO_PH2_EPI0S1         0x00070808
+
+#define GPIO_PH3_PHB0           0x00070C01
+#define GPIO_PH3_FAULT0         0x00070C02
+#define GPIO_PH3_USB0EPEN       0x00070C04
+#define GPIO_PH3_EPI0S0         0x00070C08
+
+#define GPIO_PH4_USB0PFLT       0x00071004
+#define GPIO_PH4_EPI0S10        0x00071008
+#define GPIO_PH4_SSI1CLK        0x0007100B
+
+#define GPIO_PH5_EPI0S11        0x00071408
+#define GPIO_PH5_FAULT2         0x0007140A
+#define GPIO_PH5_SSI1FSS        0x0007140B
+
+#define GPIO_PH6_EPI0S26        0x00071808
+#define GPIO_PH6_PWM4           0x0007180A
+#define GPIO_PH6_SSI1RX         0x0007180B
+
+#define GPIO_PH7_EPI0S27        0x00071C08
+#define GPIO_PH7_PWM5           0x00071C0A
+#define GPIO_PH7_SSI1TX         0x00071C0B
+
+#define GPIO_PJ0_EPI0S16        0x00080008
+#define GPIO_PJ0_PWM0           0x0008000A
+#define GPIO_PJ0_I2C1SCL        0x0008000B
+
+#define GPIO_PJ1_EPI0S17        0x00080408
+#define GPIO_PJ1_USB0PFLT       0x00080409
+#define GPIO_PJ1_PWM1           0x0008040A
+#define GPIO_PJ1_I2C1SDA        0x0008040B
+
+#define GPIO_PJ2_EPI0S18        0x00080808
+#define GPIO_PJ2_CCP0           0x00080809
+#define GPIO_PJ2_FAULT0         0x0008080A
+
+#define GPIO_PJ3_EPI0S19        0x00080C08
+#define GPIO_PJ3_U1CTS          0x00080C09
+#define GPIO_PJ3_CCP6           0x00080C0A
+
+#define GPIO_PJ4_EPI0S28        0x00081008
+#define GPIO_PJ4_U1DCD          0x00081009
+#define GPIO_PJ4_CCP4           0x0008100A
+
+#define GPIO_PJ5_EPI0S29        0x00081408
+#define GPIO_PJ5_U1DSR          0x00081409
+#define GPIO_PJ5_CCP2           0x0008140A
+
+#define GPIO_PJ6_EPI0S30        0x00081808
+#define GPIO_PJ6_U1RTS          0x00081809
+#define GPIO_PJ6_CCP1           0x0008180A
+
+#define GPIO_PJ7_U1DTR          0x00081C09
+#define GPIO_PJ7_CCP0           0x00081C0A
+
+#endif // PART_LM3S9B95
+
+//*****************************************************************************
+//
+// LM3S9B96 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S9B96
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_PWM4           0x00000804
+#define GPIO_PA2_I2S0RXSD       0x00000809
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_PWM5           0x00000C04
+#define GPIO_PA3_I2S0RXMCLK     0x00000C09
+
+#define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_PWM6           0x00001004
+#define GPIO_PA4_CAN0RX         0x00001005
+#define GPIO_PA4_I2S0TXSCK      0x00001009
+
+#define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_PWM7           0x00001404
+#define GPIO_PA5_CAN0TX         0x00001405
+#define GPIO_PA5_I2S0TXWS       0x00001409
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_PWM0           0x00001804
+#define GPIO_PA6_PWM4           0x00001805
+#define GPIO_PA6_CAN0RX         0x00001806
+#define GPIO_PA6_USB0EPEN       0x00001808
+#define GPIO_PA6_U1CTS          0x00001809
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_PWM1           0x00001C04
+#define GPIO_PA7_PWM5           0x00001C05
+#define GPIO_PA7_CAN0TX         0x00001C06
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_USB0PFLT       0x00001C08
+#define GPIO_PA7_U1DCD          0x00001C09
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_PWM2           0x00010002
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_PWM3           0x00010402
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_IDX0           0x00010802
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+#define GPIO_PB2_USB0EPEN       0x00010808
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_FAULT0         0x00010C02
+#define GPIO_PB3_FAULT3         0x00010C04
+#define GPIO_PB3_USB0PFLT       0x00010C08
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_CAN0RX         0x00011005
+#define GPIO_PB4_IDX0           0x00011006
+#define GPIO_PB4_U1RX           0x00011007
+#define GPIO_PB4_EPI0S23        0x00011008
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CAN0TX         0x00011405
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+#define GPIO_PB5_EPI0S22        0x00011408
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_FAULT1         0x00011804
+#define GPIO_PB6_IDX0           0x00011805
+#define GPIO_PB6_CCP5           0x00011806
+#define GPIO_PB6_I2S0TXSCK      0x00011809
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_PHA0           0x00021002
+#define GPIO_PC4_PWM6           0x00021004
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_EPI0S2         0x00021008
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_FAULT2         0x00021404
+#define GPIO_PC5_CCP3           0x00021405
+#define GPIO_PC5_USB0EPEN       0x00021406
+#define GPIO_PC5_EPI0S3         0x00021408
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_PHB0           0x00021802
+#define GPIO_PC6_C2O            0x00021803
+#define GPIO_PC6_PWM7           0x00021804
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+#define GPIO_PC6_USB0PFLT       0x00021807
+#define GPIO_PC6_EPI0S4         0x00021808
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_PHB0           0x00021C02
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_USB0PFLT       0x00021C06
+#define GPIO_PC7_C1O            0x00021C07
+#define GPIO_PC7_EPI0S5         0x00021C08
+
+#define GPIO_PD0_PWM0           0x00030001
+#define GPIO_PD0_CAN0RX         0x00030002
+#define GPIO_PD0_IDX0           0x00030003
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+#define GPIO_PD0_I2S0RXSCK      0x00030008
+#define GPIO_PD0_U1CTS          0x00030009
+
+#define GPIO_PD1_PWM1           0x00030401
+#define GPIO_PD1_CAN0TX         0x00030402
+#define GPIO_PD1_PHA0           0x00030403
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_I2S0RXWS       0x00030408
+#define GPIO_PD1_U1DCD          0x00030409
+#define GPIO_PD1_CCP2           0x0003040A
+#define GPIO_PD1_PHB1           0x0003040B
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_PWM2           0x00030803
+#define GPIO_PD2_CCP5           0x00030804
+#define GPIO_PD2_EPI0S20        0x00030808
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_PWM3           0x00030C03
+#define GPIO_PD3_CCP0           0x00030C04
+#define GPIO_PD3_EPI0S21        0x00030C08
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+#define GPIO_PD4_I2S0RXSD       0x00031008
+#define GPIO_PD4_U1RI           0x00031009
+#define GPIO_PD4_EPI0S19        0x0003100A
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_I2S0RXMCLK     0x00031408
+#define GPIO_PD5_U2RX           0x00031409
+#define GPIO_PD5_EPI0S28        0x0003140A
+
+#define GPIO_PD6_FAULT0         0x00031801
+#define GPIO_PD6_I2S0TXSCK      0x00031808
+#define GPIO_PD6_U2TX           0x00031809
+#define GPIO_PD6_EPI0S29        0x0003180A
+
+#define GPIO_PD7_IDX0           0x00031C01
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+#define GPIO_PD7_I2S0TXWS       0x00031C08
+#define GPIO_PD7_U1DTR          0x00031C09
+#define GPIO_PD7_EPI0S30        0x00031C0A
+
+#define GPIO_PE0_PWM4           0x00040001
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+#define GPIO_PE0_EPI0S8         0x00040008
+#define GPIO_PE0_USB0PFLT       0x00040009
+
+#define GPIO_PE1_PWM5           0x00040401
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_FAULT0         0x00040403
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+#define GPIO_PE1_EPI0S9         0x00040408
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_PHB1           0x00040803
+#define GPIO_PE2_PHA0           0x00040804
+#define GPIO_PE2_CCP2           0x00040805
+#define GPIO_PE2_EPI0S24        0x00040808
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_PHA1           0x00040C03
+#define GPIO_PE3_PHB0           0x00040C04
+#define GPIO_PE3_CCP7           0x00040C05
+#define GPIO_PE3_EPI0S25        0x00040C08
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_FAULT0         0x00041004
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+#define GPIO_PE4_I2S0TXWS       0x00041009
+
+#define GPIO_PE5_CCP5           0x00041401
+#define GPIO_PE5_I2S0TXSD       0x00041409
+
+#define GPIO_PE6_PWM4           0x00041801
+#define GPIO_PE6_C1O            0x00041802
+#define GPIO_PE6_U1CTS          0x00041809
+
+#define GPIO_PE7_PWM5           0x00041C01
+#define GPIO_PE7_C2O            0x00041C02
+#define GPIO_PE7_U1DCD          0x00041C09
+
+#define GPIO_PF0_CAN1RX         0x00050001
+#define GPIO_PF0_PHB0           0x00050002
+#define GPIO_PF0_PWM0           0x00050003
+#define GPIO_PF0_I2S0TXSD       0x00050008
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_CAN1TX         0x00050401
+#define GPIO_PF1_IDX1           0x00050402
+#define GPIO_PF1_PWM1           0x00050403
+#define GPIO_PF1_I2S0TXMCLK     0x00050408
+#define GPIO_PF1_U1RTS          0x00050409
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_LED1           0x00050801
+#define GPIO_PF2_PWM4           0x00050802
+#define GPIO_PF2_PWM2           0x00050804
+#define GPIO_PF2_SSI1CLK        0x00050809
+
+#define GPIO_PF3_LED0           0x00050C01
+#define GPIO_PF3_PWM5           0x00050C02
+#define GPIO_PF3_PWM3           0x00050C04
+#define GPIO_PF3_SSI1FSS        0x00050C09
+
+#define GPIO_PF4_CCP0           0x00051001
+#define GPIO_PF4_C0O            0x00051002
+#define GPIO_PF4_FAULT0         0x00051004
+#define GPIO_PF4_EPI0S12        0x00051008
+#define GPIO_PF4_SSI1RX         0x00051009
+
+#define GPIO_PF5_CCP2           0x00051401
+#define GPIO_PF5_C1O            0x00051402
+#define GPIO_PF5_EPI0S15        0x00051408
+#define GPIO_PF5_SSI1TX         0x00051409
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_PWM0           0x00060002
+#define GPIO_PG0_I2C1SCL        0x00060003
+#define GPIO_PG0_PWM4           0x00060004
+#define GPIO_PG0_USB0EPEN       0x00060007
+#define GPIO_PG0_EPI0S13        0x00060008
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_PWM1           0x00060402
+#define GPIO_PG1_I2C1SDA        0x00060403
+#define GPIO_PG1_PWM5           0x00060404
+#define GPIO_PG1_EPI0S14        0x00060408
+
+#define GPIO_PG7_PHB1           0x00061C01
+#define GPIO_PG7_PWM7           0x00061C04
+#define GPIO_PG7_CCP5           0x00061C08
+#define GPIO_PG7_EPI0S31        0x00061C09
+
+#define GPIO_PH0_CCP6           0x00070001
+#define GPIO_PH0_PWM2           0x00070002
+#define GPIO_PH0_EPI0S6         0x00070008
+#define GPIO_PH0_PWM4           0x00070009
+
+#define GPIO_PH1_CCP7           0x00070401
+#define GPIO_PH1_PWM3           0x00070402
+#define GPIO_PH1_EPI0S7         0x00070408
+#define GPIO_PH1_PWM5           0x00070409
+
+#define GPIO_PH2_IDX1           0x00070801
+#define GPIO_PH2_C1O            0x00070802
+#define GPIO_PH2_FAULT3         0x00070804
+#define GPIO_PH2_EPI0S1         0x00070808
+
+#define GPIO_PH3_PHB0           0x00070C01
+#define GPIO_PH3_FAULT0         0x00070C02
+#define GPIO_PH3_USB0EPEN       0x00070C04
+#define GPIO_PH3_EPI0S0         0x00070C08
+
+#define GPIO_PH4_USB0PFLT       0x00071004
+#define GPIO_PH4_EPI0S10        0x00071008
+#define GPIO_PH4_SSI1CLK        0x0007100B
+
+#define GPIO_PH5_EPI0S11        0x00071408
+#define GPIO_PH5_FAULT2         0x0007140A
+#define GPIO_PH5_SSI1FSS        0x0007140B
+
+#define GPIO_PH6_EPI0S26        0x00071808
+#define GPIO_PH6_PWM4           0x0007180A
+#define GPIO_PH6_SSI1RX         0x0007180B
+
+#define GPIO_PH7_EPI0S27        0x00071C08
+#define GPIO_PH7_PWM5           0x00071C0A
+#define GPIO_PH7_SSI1TX         0x00071C0B
+
+#define GPIO_PJ0_EPI0S16        0x00080008
+#define GPIO_PJ0_PWM0           0x0008000A
+#define GPIO_PJ0_I2C1SCL        0x0008000B
+
+#define GPIO_PJ1_EPI0S17        0x00080408
+#define GPIO_PJ1_USB0PFLT       0x00080409
+#define GPIO_PJ1_PWM1           0x0008040A
+#define GPIO_PJ1_I2C1SDA        0x0008040B
+
+#define GPIO_PJ2_EPI0S18        0x00080808
+#define GPIO_PJ2_CCP0           0x00080809
+#define GPIO_PJ2_FAULT0         0x0008080A
+
+#define GPIO_PJ3_EPI0S19        0x00080C08
+#define GPIO_PJ3_U1CTS          0x00080C09
+#define GPIO_PJ3_CCP6           0x00080C0A
+
+#define GPIO_PJ4_EPI0S28        0x00081008
+#define GPIO_PJ4_U1DCD          0x00081009
+#define GPIO_PJ4_CCP4           0x0008100A
+
+#define GPIO_PJ5_EPI0S29        0x00081408
+#define GPIO_PJ5_U1DSR          0x00081409
+#define GPIO_PJ5_CCP2           0x0008140A
+
+#define GPIO_PJ6_EPI0S30        0x00081808
+#define GPIO_PJ6_U1RTS          0x00081809
+#define GPIO_PJ6_CCP1           0x0008180A
+
+#define GPIO_PJ7_U1DTR          0x00081C09
+#define GPIO_PJ7_CCP0           0x00081C0A
+
+#endif // PART_LM3S9B96
+
+//*****************************************************************************
+//
+// LM3S9BN2 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S9BN2
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_TXD2           0x00000803
+#define GPIO_PA2_PWM4           0x00000804
+#define GPIO_PA2_I2S0RXSD       0x00000809
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_TXD1           0x00000C03
+#define GPIO_PA3_PWM5           0x00000C04
+#define GPIO_PA3_I2S0RXMCLK     0x00000C09
+
+#define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_TXD0           0x00001003
+#define GPIO_PA4_PWM6           0x00001004
+#define GPIO_PA4_CAN0RX         0x00001005
+#define GPIO_PA4_I2S0TXSCK      0x00001009
+
+#define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_RXDV           0x00001403
+#define GPIO_PA5_PWM7           0x00001404
+#define GPIO_PA5_CAN0TX         0x00001405
+#define GPIO_PA5_I2S0TXWS       0x00001409
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_RXCK           0x00001803
+#define GPIO_PA6_PWM0           0x00001804
+#define GPIO_PA6_PWM4           0x00001805
+#define GPIO_PA6_CAN0RX         0x00001806
+#define GPIO_PA6_USB0EPEN       0x00001808
+#define GPIO_PA6_U1CTS          0x00001809
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_RXER           0x00001C03
+#define GPIO_PA7_PWM1           0x00001C04
+#define GPIO_PA7_PWM5           0x00001C05
+#define GPIO_PA7_CAN0TX         0x00001C06
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_USB0PFLT       0x00001C08
+#define GPIO_PA7_U1DCD          0x00001C09
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_PWM2           0x00010002
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_PWM3           0x00010402
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_IDX0           0x00010802
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+#define GPIO_PB2_USB0EPEN       0x00010808
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_FAULT0         0x00010C02
+#define GPIO_PB3_FAULT3         0x00010C04
+#define GPIO_PB3_USB0PFLT       0x00010C08
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_CAN0RX         0x00011005
+#define GPIO_PB4_IDX0           0x00011006
+#define GPIO_PB4_U1RX           0x00011007
+#define GPIO_PB4_EPI0S23        0x00011008
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CAN0TX         0x00011405
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+#define GPIO_PB5_EPI0S22        0x00011408
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_FAULT1         0x00011804
+#define GPIO_PB6_IDX0           0x00011805
+#define GPIO_PB6_CCP5           0x00011806
+#define GPIO_PB6_I2S0TXSCK      0x00011809
+
+#define GPIO_PB7_NMI            0x00011C04
+#define GPIO_PB7_RXD1           0x00011C07
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_PHA0           0x00021002
+#define GPIO_PC4_TXD3           0x00021003
+#define GPIO_PC4_PWM6           0x00021004
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_EPI0S2         0x00021008
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_FAULT2         0x00021404
+#define GPIO_PC5_CCP3           0x00021405
+#define GPIO_PC5_USB0EPEN       0x00021406
+#define GPIO_PC5_EPI0S3         0x00021408
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_PHB0           0x00021802
+#define GPIO_PC6_C2O            0x00021803
+#define GPIO_PC6_PWM7           0x00021804
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+#define GPIO_PC6_USB0PFLT       0x00021807
+#define GPIO_PC6_EPI0S4         0x00021808
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_PHB0           0x00021C02
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_USB0PFLT       0x00021C06
+#define GPIO_PC7_C1O            0x00021C07
+#define GPIO_PC7_EPI0S5         0x00021C08
+
+#define GPIO_PD0_PWM0           0x00030001
+#define GPIO_PD0_CAN0RX         0x00030002
+#define GPIO_PD0_IDX0           0x00030003
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+#define GPIO_PD0_RXDV           0x00030007
+#define GPIO_PD0_I2S0RXSCK      0x00030008
+#define GPIO_PD0_U1CTS          0x00030009
+
+#define GPIO_PD1_PWM1           0x00030401
+#define GPIO_PD1_CAN0TX         0x00030402
+#define GPIO_PD1_PHA0           0x00030403
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_TXER           0x00030407
+#define GPIO_PD1_I2S0RXWS       0x00030408
+#define GPIO_PD1_U1DCD          0x00030409
+#define GPIO_PD1_CCP2           0x0003040A
+#define GPIO_PD1_PHB1           0x0003040B
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_PWM2           0x00030803
+#define GPIO_PD2_CCP5           0x00030804
+#define GPIO_PD2_EPI0S20        0x00030808
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_PWM3           0x00030C03
+#define GPIO_PD3_CCP0           0x00030C04
+#define GPIO_PD3_EPI0S21        0x00030C08
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+#define GPIO_PD4_TXD3           0x00031004
+#define GPIO_PD4_I2S0RXSD       0x00031008
+#define GPIO_PD4_U1RI           0x00031009
+#define GPIO_PD4_EPI0S19        0x0003100A
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_TXD2           0x00031404
+#define GPIO_PD5_I2S0RXMCLK     0x00031408
+#define GPIO_PD5_U2RX           0x00031409
+#define GPIO_PD5_EPI0S28        0x0003140A
+
+#define GPIO_PD6_FAULT0         0x00031801
+#define GPIO_PD6_TXD1           0x00031804
+#define GPIO_PD6_I2S0TXSCK      0x00031808
+#define GPIO_PD6_U2TX           0x00031809
+#define GPIO_PD6_EPI0S29        0x0003180A
+
+#define GPIO_PD7_IDX0           0x00031C01
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+#define GPIO_PD7_TXD0           0x00031C04
+#define GPIO_PD7_I2S0TXWS       0x00031C08
+#define GPIO_PD7_U1DTR          0x00031C09
+#define GPIO_PD7_EPI0S30        0x00031C0A
+
+#define GPIO_PE0_PWM4           0x00040001
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+#define GPIO_PE0_EPI0S8         0x00040008
+#define GPIO_PE0_USB0PFLT       0x00040009
+
+#define GPIO_PE1_PWM5           0x00040401
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_FAULT0         0x00040403
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+#define GPIO_PE1_EPI0S9         0x00040408
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_PHB1           0x00040803
+#define GPIO_PE2_PHA0           0x00040804
+#define GPIO_PE2_CCP2           0x00040805
+#define GPIO_PE2_EPI0S24        0x00040808
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_PHA1           0x00040C03
+#define GPIO_PE3_PHB0           0x00040C04
+#define GPIO_PE3_CCP7           0x00040C05
+#define GPIO_PE3_EPI0S25        0x00040C08
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_FAULT0         0x00041004
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+#define GPIO_PE4_RXD0           0x00041007
+#define GPIO_PE4_I2S0TXWS       0x00041009
+
+#define GPIO_PE5_CCP5           0x00041401
+#define GPIO_PE5_I2S0TXSD       0x00041409
+
+#define GPIO_PE6_PWM4           0x00041801
+#define GPIO_PE6_C1O            0x00041802
+#define GPIO_PE6_U1CTS          0x00041809
+
+#define GPIO_PE7_PWM5           0x00041C01
+#define GPIO_PE7_C2O            0x00041C02
+#define GPIO_PE7_U1DCD          0x00041C09
+
+#define GPIO_PF0_CAN1RX         0x00050001
+#define GPIO_PF0_PHB0           0x00050002
+#define GPIO_PF0_PWM0           0x00050003
+#define GPIO_PF0_RXCK           0x00050004
+#define GPIO_PF0_I2S0TXSD       0x00050008
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_CAN1TX         0x00050401
+#define GPIO_PF1_IDX1           0x00050402
+#define GPIO_PF1_PWM1           0x00050403
+#define GPIO_PF1_RXER           0x00050404
+#define GPIO_PF1_I2S0TXMCLK     0x00050408
+#define GPIO_PF1_U1RTS          0x00050409
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_PWM4           0x00050802
+#define GPIO_PF2_PHYINT         0x00050803
+#define GPIO_PF2_PWM2           0x00050804
+#define GPIO_PF2_SSI1CLK        0x00050809
+
+#define GPIO_PF3_PWM5           0x00050C02
+#define GPIO_PF3_MDC            0x00050C03
+#define GPIO_PF3_PWM3           0x00050C04
+#define GPIO_PF3_SSI1FSS        0x00050C09
+
+#define GPIO_PF4_CCP0           0x00051001
+#define GPIO_PF4_C0O            0x00051002
+#define GPIO_PF4_MDIO           0x00051003
+#define GPIO_PF4_FAULT0         0x00051004
+#define GPIO_PF4_EPI0S12        0x00051008
+#define GPIO_PF4_SSI1RX         0x00051009
+
+#define GPIO_PF5_CCP2           0x00051401
+#define GPIO_PF5_C1O            0x00051402
+#define GPIO_PF5_RXD3           0x00051403
+#define GPIO_PF5_EPI0S15        0x00051408
+#define GPIO_PF5_SSI1TX         0x00051409
+
+#define GPIO_PF6_CCP1           0x00051801
+#define GPIO_PF6_C2O            0x00051802
+#define GPIO_PF6_RXD2           0x00051803
+#define GPIO_PF6_PHA0           0x00051804
+#define GPIO_PF6_I2S0TXMCLK     0x00051809
+#define GPIO_PF6_U1RTS          0x0005180A
+
+#define GPIO_PF7_CCP4           0x00051C01
+#define GPIO_PF7_RXD1           0x00051C03
+#define GPIO_PF7_PHB0           0x00051C04
+#define GPIO_PF7_EPI0S12        0x00051C08
+#define GPIO_PF7_FAULT1         0x00051C09
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_PWM0           0x00060002
+#define GPIO_PG0_I2C1SCL        0x00060003
+#define GPIO_PG0_PWM4           0x00060004
+#define GPIO_PG0_USB0EPEN       0x00060007
+#define GPIO_PG0_EPI0S13        0x00060008
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_PWM1           0x00060402
+#define GPIO_PG1_I2C1SDA        0x00060403
+#define GPIO_PG1_PWM5           0x00060404
+#define GPIO_PG1_EPI0S14        0x00060408
+
+#define GPIO_PG2_PWM0           0x00060801
+#define GPIO_PG2_COL            0x00060803
+#define GPIO_PG2_FAULT0         0x00060804
+#define GPIO_PG2_IDX1           0x00060808
+#define GPIO_PG2_I2S0RXSD       0x00060809
+
+#define GPIO_PG3_PWM1           0x00060C01
+#define GPIO_PG3_CRS            0x00060C03
+#define GPIO_PG3_FAULT2         0x00060C04
+#define GPIO_PG3_FAULT0         0x00060C08
+#define GPIO_PG3_I2S0RXMCLK     0x00060C09
+
+#define GPIO_PG4_CCP3           0x00061001
+#define GPIO_PG4_RXD0           0x00061003
+#define GPIO_PG4_FAULT1         0x00061004
+#define GPIO_PG4_EPI0S15        0x00061008
+#define GPIO_PG4_PWM6           0x00061009
+#define GPIO_PG4_U1RI           0x0006100A
+
+#define GPIO_PG5_CCP5           0x00061401
+#define GPIO_PG5_TXEN           0x00061403
+#define GPIO_PG5_IDX0           0x00061404
+#define GPIO_PG5_FAULT1         0x00061405
+#define GPIO_PG5_PWM7           0x00061408
+#define GPIO_PG5_I2S0RXSCK      0x00061409
+#define GPIO_PG5_U1DTR          0x0006140A
+
+#define GPIO_PG6_PHA1           0x00061801
+#define GPIO_PG6_TXCK           0x00061803
+#define GPIO_PG6_PWM6           0x00061804
+#define GPIO_PG6_FAULT1         0x00061808
+#define GPIO_PG6_I2S0RXWS       0x00061809
+#define GPIO_PG6_U1RI           0x0006180A
+
+#define GPIO_PG7_PHB1           0x00061C01
+#define GPIO_PG7_TXER           0x00061C03
+#define GPIO_PG7_PWM7           0x00061C04
+#define GPIO_PG7_CCP5           0x00061C08
+#define GPIO_PG7_EPI0S31        0x00061C09
+
+#define GPIO_PH0_CCP6           0x00070001
+#define GPIO_PH0_PWM2           0x00070002
+#define GPIO_PH0_EPI0S6         0x00070008
+#define GPIO_PH0_PWM4           0x00070009
+
+#define GPIO_PH1_CCP7           0x00070401
+#define GPIO_PH1_PWM3           0x00070402
+#define GPIO_PH1_EPI0S7         0x00070408
+#define GPIO_PH1_PWM5           0x00070409
+
+#define GPIO_PH2_IDX1           0x00070801
+#define GPIO_PH2_C1O            0x00070802
+#define GPIO_PH2_FAULT3         0x00070804
+#define GPIO_PH2_EPI0S1         0x00070808
+#define GPIO_PH2_TXD3           0x00070809
+
+#define GPIO_PH3_PHB0           0x00070C01
+#define GPIO_PH3_FAULT0         0x00070C02
+#define GPIO_PH3_USB0EPEN       0x00070C04
+#define GPIO_PH3_EPI0S0         0x00070C08
+#define GPIO_PH3_TXD2           0x00070C09
+
+#define GPIO_PH4_USB0PFLT       0x00071004
+#define GPIO_PH4_EPI0S10        0x00071008
+#define GPIO_PH4_TXD1           0x00071009
+#define GPIO_PH4_SSI1CLK        0x0007100B
+
+#define GPIO_PH5_EPI0S11        0x00071408
+#define GPIO_PH5_TXD0           0x00071409
+#define GPIO_PH5_FAULT2         0x0007140A
+#define GPIO_PH5_SSI1FSS        0x0007140B
+
+#define GPIO_PH6_EPI0S26        0x00071808
+#define GPIO_PH6_RXDV           0x00071809
+#define GPIO_PH6_PWM4           0x0007180A
+#define GPIO_PH6_SSI1RX         0x0007180B
+
+#define GPIO_PH7_RXCK           0x00071C03
+#define GPIO_PH7_EPI0S27        0x00071C08
+#define GPIO_PH7_PWM5           0x00071C0A
+#define GPIO_PH7_SSI1TX         0x00071C0B
+
+#define GPIO_PJ0_RXER           0x00080003
+#define GPIO_PJ0_EPI0S16        0x00080008
+#define GPIO_PJ0_PWM0           0x0008000A
+#define GPIO_PJ0_I2C1SCL        0x0008000B
+
+#define GPIO_PJ1_EPI0S17        0x00080408
+#define GPIO_PJ1_USB0PFLT       0x00080409
+#define GPIO_PJ1_PWM1           0x0008040A
+#define GPIO_PJ1_I2C1SDA        0x0008040B
+
+#define GPIO_PJ2_EPI0S18        0x00080808
+#define GPIO_PJ2_CCP0           0x00080809
+#define GPIO_PJ2_FAULT0         0x0008080A
+
+#define GPIO_PJ3_EPI0S19        0x00080C08
+#define GPIO_PJ3_U1CTS          0x00080C09
+#define GPIO_PJ3_CCP6           0x00080C0A
+
+#define GPIO_PJ4_EPI0S28        0x00081008
+#define GPIO_PJ4_U1DCD          0x00081009
+#define GPIO_PJ4_CCP4           0x0008100A
+
+#define GPIO_PJ5_EPI0S29        0x00081408
+#define GPIO_PJ5_U1DSR          0x00081409
+#define GPIO_PJ5_CCP2           0x0008140A
+
+#define GPIO_PJ6_EPI0S30        0x00081808
+#define GPIO_PJ6_U1RTS          0x00081809
+#define GPIO_PJ6_CCP1           0x0008180A
+
+#define GPIO_PJ7_U1DTR          0x00081C09
+#define GPIO_PJ7_CCP0           0x00081C0A
+
+#endif // PART_LM3S9BN2
+
+//*****************************************************************************
+//
+// LM3S9BN5 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S9BN5
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_TXD2           0x00000803
+#define GPIO_PA2_PWM4           0x00000804
+#define GPIO_PA2_I2S0RXSD       0x00000809
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_TXD1           0x00000C03
+#define GPIO_PA3_PWM5           0x00000C04
+#define GPIO_PA3_I2S0RXMCLK     0x00000C09
+
+#define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_TXD0           0x00001003
+#define GPIO_PA4_PWM6           0x00001004
+#define GPIO_PA4_CAN0RX         0x00001005
+#define GPIO_PA4_I2S0TXSCK      0x00001009
+
+#define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_RXDV           0x00001403
+#define GPIO_PA5_PWM7           0x00001404
+#define GPIO_PA5_CAN0TX         0x00001405
+#define GPIO_PA5_I2S0TXWS       0x00001409
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_RXCK           0x00001803
+#define GPIO_PA6_PWM0           0x00001804
+#define GPIO_PA6_PWM4           0x00001805
+#define GPIO_PA6_CAN0RX         0x00001806
+#define GPIO_PA6_USB0EPEN       0x00001808
+#define GPIO_PA6_U1CTS          0x00001809
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_RXER           0x00001C03
+#define GPIO_PA7_PWM1           0x00001C04
+#define GPIO_PA7_PWM5           0x00001C05
+#define GPIO_PA7_CAN0TX         0x00001C06
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_USB0PFLT       0x00001C08
+#define GPIO_PA7_U1DCD          0x00001C09
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_PWM2           0x00010002
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_PWM3           0x00010402
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_IDX0           0x00010802
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+#define GPIO_PB2_USB0EPEN       0x00010808
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_FAULT0         0x00010C02
+#define GPIO_PB3_FAULT3         0x00010C04
+#define GPIO_PB3_USB0PFLT       0x00010C08
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_CAN0RX         0x00011005
+#define GPIO_PB4_IDX0           0x00011006
+#define GPIO_PB4_U1RX           0x00011007
+#define GPIO_PB4_EPI0S23        0x00011008
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CAN0TX         0x00011405
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+#define GPIO_PB5_EPI0S22        0x00011408
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_FAULT1         0x00011804
+#define GPIO_PB6_IDX0           0x00011805
+#define GPIO_PB6_CCP5           0x00011806
+#define GPIO_PB6_I2S0TXSCK      0x00011809
+
+#define GPIO_PB7_NMI            0x00011C04
+#define GPIO_PB7_RXD1           0x00011C07
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_PHA0           0x00021002
+#define GPIO_PC4_TXD3           0x00021003
+#define GPIO_PC4_PWM6           0x00021004
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_EPI0S2         0x00021008
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_FAULT2         0x00021404
+#define GPIO_PC5_CCP3           0x00021405
+#define GPIO_PC5_USB0EPEN       0x00021406
+#define GPIO_PC5_EPI0S3         0x00021408
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_PHB0           0x00021802
+#define GPIO_PC6_C2O            0x00021803
+#define GPIO_PC6_PWM7           0x00021804
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+#define GPIO_PC6_USB0PFLT       0x00021807
+#define GPIO_PC6_EPI0S4         0x00021808
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_PHB0           0x00021C02
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_USB0PFLT       0x00021C06
+#define GPIO_PC7_C1O            0x00021C07
+#define GPIO_PC7_EPI0S5         0x00021C08
+
+#define GPIO_PD0_PWM0           0x00030001
+#define GPIO_PD0_CAN0RX         0x00030002
+#define GPIO_PD0_IDX0           0x00030003
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+#define GPIO_PD0_RXDV           0x00030007
+#define GPIO_PD0_I2S0RXSCK      0x00030008
+#define GPIO_PD0_U1CTS          0x00030009
+
+#define GPIO_PD1_PWM1           0x00030401
+#define GPIO_PD1_CAN0TX         0x00030402
+#define GPIO_PD1_PHA0           0x00030403
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_TXER           0x00030407
+#define GPIO_PD1_I2S0RXWS       0x00030408
+#define GPIO_PD1_U1DCD          0x00030409
+#define GPIO_PD1_CCP2           0x0003040A
+#define GPIO_PD1_PHB1           0x0003040B
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_PWM2           0x00030803
+#define GPIO_PD2_CCP5           0x00030804
+#define GPIO_PD2_EPI0S20        0x00030808
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_PWM3           0x00030C03
+#define GPIO_PD3_CCP0           0x00030C04
+#define GPIO_PD3_EPI0S21        0x00030C08
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+#define GPIO_PD4_TXD3           0x00031004
+#define GPIO_PD4_I2S0RXSD       0x00031008
+#define GPIO_PD4_U1RI           0x00031009
+#define GPIO_PD4_EPI0S19        0x0003100A
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_TXD2           0x00031404
+#define GPIO_PD5_I2S0RXMCLK     0x00031408
+#define GPIO_PD5_U2RX           0x00031409
+#define GPIO_PD5_EPI0S28        0x0003140A
+
+#define GPIO_PD6_FAULT0         0x00031801
+#define GPIO_PD6_TXD1           0x00031804
+#define GPIO_PD6_I2S0TXSCK      0x00031808
+#define GPIO_PD6_U2TX           0x00031809
+#define GPIO_PD6_EPI0S29        0x0003180A
+
+#define GPIO_PD7_IDX0           0x00031C01
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+#define GPIO_PD7_TXD0           0x00031C04
+#define GPIO_PD7_I2S0TXWS       0x00031C08
+#define GPIO_PD7_U1DTR          0x00031C09
+#define GPIO_PD7_EPI0S30        0x00031C0A
+
+#define GPIO_PE0_PWM4           0x00040001
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+#define GPIO_PE0_EPI0S8         0x00040008
+#define GPIO_PE0_USB0PFLT       0x00040009
+
+#define GPIO_PE1_PWM5           0x00040401
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_FAULT0         0x00040403
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+#define GPIO_PE1_EPI0S9         0x00040408
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_PHB1           0x00040803
+#define GPIO_PE2_PHA0           0x00040804
+#define GPIO_PE2_CCP2           0x00040805
+#define GPIO_PE2_EPI0S24        0x00040808
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_PHA1           0x00040C03
+#define GPIO_PE3_PHB0           0x00040C04
+#define GPIO_PE3_CCP7           0x00040C05
+#define GPIO_PE3_EPI0S25        0x00040C08
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_FAULT0         0x00041004
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+#define GPIO_PE4_RXD0           0x00041007
+#define GPIO_PE4_I2S0TXWS       0x00041009
+
+#define GPIO_PE5_CCP5           0x00041401
+#define GPIO_PE5_I2S0TXSD       0x00041409
+
+#define GPIO_PE6_PWM4           0x00041801
+#define GPIO_PE6_C1O            0x00041802
+#define GPIO_PE6_U1CTS          0x00041809
+
+#define GPIO_PE7_PWM5           0x00041C01
+#define GPIO_PE7_C2O            0x00041C02
+#define GPIO_PE7_U1DCD          0x00041C09
+
+#define GPIO_PF0_CAN1RX         0x00050001
+#define GPIO_PF0_PHB0           0x00050002
+#define GPIO_PF0_PWM0           0x00050003
+#define GPIO_PF0_RXCK           0x00050004
+#define GPIO_PF0_I2S0TXSD       0x00050008
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_CAN1TX         0x00050401
+#define GPIO_PF1_IDX1           0x00050402
+#define GPIO_PF1_PWM1           0x00050403
+#define GPIO_PF1_RXER           0x00050404
+#define GPIO_PF1_I2S0TXMCLK     0x00050408
+#define GPIO_PF1_U1RTS          0x00050409
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_PWM4           0x00050802
+#define GPIO_PF2_PHYINT         0x00050803
+#define GPIO_PF2_PWM2           0x00050804
+#define GPIO_PF2_SSI1CLK        0x00050809
+
+#define GPIO_PF3_PWM5           0x00050C02
+#define GPIO_PF3_MDC            0x00050C03
+#define GPIO_PF3_PWM3           0x00050C04
+#define GPIO_PF3_SSI1FSS        0x00050C09
+
+#define GPIO_PF4_CCP0           0x00051001
+#define GPIO_PF4_C0O            0x00051002
+#define GPIO_PF4_MDIO           0x00051003
+#define GPIO_PF4_FAULT0         0x00051004
+#define GPIO_PF4_EPI0S12        0x00051008
+#define GPIO_PF4_SSI1RX         0x00051009
+
+#define GPIO_PF5_CCP2           0x00051401
+#define GPIO_PF5_C1O            0x00051402
+#define GPIO_PF5_RXD3           0x00051403
+#define GPIO_PF5_EPI0S15        0x00051408
+#define GPIO_PF5_SSI1TX         0x00051409
+
+#define GPIO_PF6_CCP1           0x00051801
+#define GPIO_PF6_C2O            0x00051802
+#define GPIO_PF6_RXD2           0x00051803
+#define GPIO_PF6_PHA0           0x00051804
+#define GPIO_PF6_I2S0TXMCLK     0x00051809
+#define GPIO_PF6_U1RTS          0x0005180A
+
+#define GPIO_PF7_CCP4           0x00051C01
+#define GPIO_PF7_RXD1           0x00051C03
+#define GPIO_PF7_PHB0           0x00051C04
+#define GPIO_PF7_EPI0S12        0x00051C08
+#define GPIO_PF7_FAULT1         0x00051C09
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_PWM0           0x00060002
+#define GPIO_PG0_I2C1SCL        0x00060003
+#define GPIO_PG0_PWM4           0x00060004
+#define GPIO_PG0_USB0EPEN       0x00060007
+#define GPIO_PG0_EPI0S13        0x00060008
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_PWM1           0x00060402
+#define GPIO_PG1_I2C1SDA        0x00060403
+#define GPIO_PG1_PWM5           0x00060404
+#define GPIO_PG1_EPI0S14        0x00060408
+
+#define GPIO_PG2_PWM0           0x00060801
+#define GPIO_PG2_COL            0x00060803
+#define GPIO_PG2_FAULT0         0x00060804
+#define GPIO_PG2_IDX1           0x00060808
+#define GPIO_PG2_I2S0RXSD       0x00060809
+
+#define GPIO_PG3_PWM1           0x00060C01
+#define GPIO_PG3_CRS            0x00060C03
+#define GPIO_PG3_FAULT2         0x00060C04
+#define GPIO_PG3_FAULT0         0x00060C08
+#define GPIO_PG3_I2S0RXMCLK     0x00060C09
+
+#define GPIO_PG4_CCP3           0x00061001
+#define GPIO_PG4_RXD0           0x00061003
+#define GPIO_PG4_FAULT1         0x00061004
+#define GPIO_PG4_EPI0S15        0x00061008
+#define GPIO_PG4_PWM6           0x00061009
+#define GPIO_PG4_U1RI           0x0006100A
+
+#define GPIO_PG5_CCP5           0x00061401
+#define GPIO_PG5_TXEN           0x00061403
+#define GPIO_PG5_IDX0           0x00061404
+#define GPIO_PG5_FAULT1         0x00061405
+#define GPIO_PG5_PWM7           0x00061408
+#define GPIO_PG5_I2S0RXSCK      0x00061409
+#define GPIO_PG5_U1DTR          0x0006140A
+
+#define GPIO_PG6_PHA1           0x00061801
+#define GPIO_PG6_TXCK           0x00061803
+#define GPIO_PG6_PWM6           0x00061804
+#define GPIO_PG6_FAULT1         0x00061808
+#define GPIO_PG6_I2S0RXWS       0x00061809
+#define GPIO_PG6_U1RI           0x0006180A
+
+#define GPIO_PG7_PHB1           0x00061C01
+#define GPIO_PG7_TXER           0x00061C03
+#define GPIO_PG7_PWM7           0x00061C04
+#define GPIO_PG7_CCP5           0x00061C08
+#define GPIO_PG7_EPI0S31        0x00061C09
+
+#define GPIO_PH0_CCP6           0x00070001
+#define GPIO_PH0_PWM2           0x00070002
+#define GPIO_PH0_EPI0S6         0x00070008
+#define GPIO_PH0_PWM4           0x00070009
+
+#define GPIO_PH1_CCP7           0x00070401
+#define GPIO_PH1_PWM3           0x00070402
+#define GPIO_PH1_EPI0S7         0x00070408
+#define GPIO_PH1_PWM5           0x00070409
+
+#define GPIO_PH2_IDX1           0x00070801
+#define GPIO_PH2_C1O            0x00070802
+#define GPIO_PH2_FAULT3         0x00070804
+#define GPIO_PH2_EPI0S1         0x00070808
+#define GPIO_PH2_TXD3           0x00070809
+
+#define GPIO_PH3_PHB0           0x00070C01
+#define GPIO_PH3_FAULT0         0x00070C02
+#define GPIO_PH3_USB0EPEN       0x00070C04
+#define GPIO_PH3_EPI0S0         0x00070C08
+#define GPIO_PH3_TXD2           0x00070C09
+
+#define GPIO_PH4_USB0PFLT       0x00071004
+#define GPIO_PH4_EPI0S10        0x00071008
+#define GPIO_PH4_TXD1           0x00071009
+#define GPIO_PH4_SSI1CLK        0x0007100B
+
+#define GPIO_PH5_EPI0S11        0x00071408
+#define GPIO_PH5_TXD0           0x00071409
+#define GPIO_PH5_FAULT2         0x0007140A
+#define GPIO_PH5_SSI1FSS        0x0007140B
+
+#define GPIO_PH6_EPI0S26        0x00071808
+#define GPIO_PH6_RXDV           0x00071809
+#define GPIO_PH6_PWM4           0x0007180A
+#define GPIO_PH6_SSI1RX         0x0007180B
+
+#define GPIO_PH7_RXCK           0x00071C03
+#define GPIO_PH7_EPI0S27        0x00071C08
+#define GPIO_PH7_PWM5           0x00071C0A
+#define GPIO_PH7_SSI1TX         0x00071C0B
+
+#define GPIO_PJ0_RXER           0x00080003
+#define GPIO_PJ0_EPI0S16        0x00080008
+#define GPIO_PJ0_PWM0           0x0008000A
+#define GPIO_PJ0_I2C1SCL        0x0008000B
+
+#define GPIO_PJ1_EPI0S17        0x00080408
+#define GPIO_PJ1_USB0PFLT       0x00080409
+#define GPIO_PJ1_PWM1           0x0008040A
+#define GPIO_PJ1_I2C1SDA        0x0008040B
+
+#define GPIO_PJ2_EPI0S18        0x00080808
+#define GPIO_PJ2_CCP0           0x00080809
+#define GPIO_PJ2_FAULT0         0x0008080A
+
+#define GPIO_PJ3_EPI0S19        0x00080C08
+#define GPIO_PJ3_U1CTS          0x00080C09
+#define GPIO_PJ3_CCP6           0x00080C0A
+
+#define GPIO_PJ4_EPI0S28        0x00081008
+#define GPIO_PJ4_U1DCD          0x00081009
+#define GPIO_PJ4_CCP4           0x0008100A
+
+#define GPIO_PJ5_EPI0S29        0x00081408
+#define GPIO_PJ5_U1DSR          0x00081409
+#define GPIO_PJ5_CCP2           0x0008140A
+
+#define GPIO_PJ6_EPI0S30        0x00081808
+#define GPIO_PJ6_U1RTS          0x00081809
+#define GPIO_PJ6_CCP1           0x0008180A
+
+#define GPIO_PJ7_U1DTR          0x00081C09
+#define GPIO_PJ7_CCP0           0x00081C0A
+
+#endif // PART_LM3S9BN5
+
+//*****************************************************************************
+//
+// LM3S9BN6 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S9BN6
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_TXD2           0x00000803
+#define GPIO_PA2_PWM4           0x00000804
+#define GPIO_PA2_I2S0RXSD       0x00000809
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_TXD1           0x00000C03
+#define GPIO_PA3_PWM5           0x00000C04
+#define GPIO_PA3_I2S0RXMCLK     0x00000C09
+
+#define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_TXD0           0x00001003
+#define GPIO_PA4_PWM6           0x00001004
+#define GPIO_PA4_CAN0RX         0x00001005
+#define GPIO_PA4_I2S0TXSCK      0x00001009
+
+#define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_RXDV           0x00001403
+#define GPIO_PA5_PWM7           0x00001404
+#define GPIO_PA5_CAN0TX         0x00001405
+#define GPIO_PA5_I2S0TXWS       0x00001409
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_RXCK           0x00001803
+#define GPIO_PA6_PWM0           0x00001804
+#define GPIO_PA6_PWM4           0x00001805
+#define GPIO_PA6_CAN0RX         0x00001806
+#define GPIO_PA6_USB0EPEN       0x00001808
+#define GPIO_PA6_U1CTS          0x00001809
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_RXER           0x00001C03
+#define GPIO_PA7_PWM1           0x00001C04
+#define GPIO_PA7_PWM5           0x00001C05
+#define GPIO_PA7_CAN0TX         0x00001C06
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_USB0PFLT       0x00001C08
+#define GPIO_PA7_U1DCD          0x00001C09
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_PWM2           0x00010002
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_PWM3           0x00010402
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_IDX0           0x00010802
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+#define GPIO_PB2_USB0EPEN       0x00010808
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_FAULT0         0x00010C02
+#define GPIO_PB3_FAULT3         0x00010C04
+#define GPIO_PB3_USB0PFLT       0x00010C08
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_CAN0RX         0x00011005
+#define GPIO_PB4_IDX0           0x00011006
+#define GPIO_PB4_U1RX           0x00011007
+#define GPIO_PB4_EPI0S23        0x00011008
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CAN0TX         0x00011405
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+#define GPIO_PB5_EPI0S22        0x00011408
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_FAULT1         0x00011804
+#define GPIO_PB6_IDX0           0x00011805
+#define GPIO_PB6_CCP5           0x00011806
+#define GPIO_PB6_I2S0TXSCK      0x00011809
+
+#define GPIO_PB7_NMI            0x00011C04
+#define GPIO_PB7_RXD1           0x00011C07
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_PHA0           0x00021002
+#define GPIO_PC4_TXD3           0x00021003
+#define GPIO_PC4_PWM6           0x00021004
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_EPI0S2         0x00021008
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_FAULT2         0x00021404
+#define GPIO_PC5_CCP3           0x00021405
+#define GPIO_PC5_USB0EPEN       0x00021406
+#define GPIO_PC5_EPI0S3         0x00021408
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_PHB0           0x00021802
+#define GPIO_PC6_C2O            0x00021803
+#define GPIO_PC6_PWM7           0x00021804
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+#define GPIO_PC6_USB0PFLT       0x00021807
+#define GPIO_PC6_EPI0S4         0x00021808
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_PHB0           0x00021C02
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_USB0PFLT       0x00021C06
+#define GPIO_PC7_C1O            0x00021C07
+#define GPIO_PC7_EPI0S5         0x00021C08
+
+#define GPIO_PD0_PWM0           0x00030001
+#define GPIO_PD0_CAN0RX         0x00030002
+#define GPIO_PD0_IDX0           0x00030003
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+#define GPIO_PD0_RXDV           0x00030007
+#define GPIO_PD0_I2S0RXSCK      0x00030008
+#define GPIO_PD0_U1CTS          0x00030009
+
+#define GPIO_PD1_PWM1           0x00030401
+#define GPIO_PD1_CAN0TX         0x00030402
+#define GPIO_PD1_PHA0           0x00030403
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_TXER           0x00030407
+#define GPIO_PD1_I2S0RXWS       0x00030408
+#define GPIO_PD1_U1DCD          0x00030409
+#define GPIO_PD1_CCP2           0x0003040A
+#define GPIO_PD1_PHB1           0x0003040B
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_PWM2           0x00030803
+#define GPIO_PD2_CCP5           0x00030804
+#define GPIO_PD2_EPI0S20        0x00030808
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_PWM3           0x00030C03
+#define GPIO_PD3_CCP0           0x00030C04
+#define GPIO_PD3_EPI0S21        0x00030C08
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+#define GPIO_PD4_TXD3           0x00031004
+#define GPIO_PD4_I2S0RXSD       0x00031008
+#define GPIO_PD4_U1RI           0x00031009
+#define GPIO_PD4_EPI0S19        0x0003100A
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_TXD2           0x00031404
+#define GPIO_PD5_I2S0RXMCLK     0x00031408
+#define GPIO_PD5_U2RX           0x00031409
+#define GPIO_PD5_EPI0S28        0x0003140A
+
+#define GPIO_PD6_FAULT0         0x00031801
+#define GPIO_PD6_TXD1           0x00031804
+#define GPIO_PD6_I2S0TXSCK      0x00031808
+#define GPIO_PD6_U2TX           0x00031809
+#define GPIO_PD6_EPI0S29        0x0003180A
+
+#define GPIO_PD7_IDX0           0x00031C01
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+#define GPIO_PD7_TXD0           0x00031C04
+#define GPIO_PD7_I2S0TXWS       0x00031C08
+#define GPIO_PD7_U1DTR          0x00031C09
+#define GPIO_PD7_EPI0S30        0x00031C0A
+
+#define GPIO_PE0_PWM4           0x00040001
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+#define GPIO_PE0_EPI0S8         0x00040008
+#define GPIO_PE0_USB0PFLT       0x00040009
+
+#define GPIO_PE1_PWM5           0x00040401
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_FAULT0         0x00040403
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+#define GPIO_PE1_EPI0S9         0x00040408
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_PHB1           0x00040803
+#define GPIO_PE2_PHA0           0x00040804
+#define GPIO_PE2_CCP2           0x00040805
+#define GPIO_PE2_EPI0S24        0x00040808
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_PHA1           0x00040C03
+#define GPIO_PE3_PHB0           0x00040C04
+#define GPIO_PE3_CCP7           0x00040C05
+#define GPIO_PE3_EPI0S25        0x00040C08
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_FAULT0         0x00041004
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+#define GPIO_PE4_RXD0           0x00041007
+#define GPIO_PE4_I2S0TXWS       0x00041009
+
+#define GPIO_PE5_CCP5           0x00041401
+#define GPIO_PE5_I2S0TXSD       0x00041409
+
+#define GPIO_PE6_PWM4           0x00041801
+#define GPIO_PE6_C1O            0x00041802
+#define GPIO_PE6_U1CTS          0x00041809
+
+#define GPIO_PE7_PWM5           0x00041C01
+#define GPIO_PE7_C2O            0x00041C02
+#define GPIO_PE7_U1DCD          0x00041C09
+
+#define GPIO_PF0_CAN1RX         0x00050001
+#define GPIO_PF0_PHB0           0x00050002
+#define GPIO_PF0_PWM0           0x00050003
+#define GPIO_PF0_RXCK           0x00050004
+#define GPIO_PF0_I2S0TXSD       0x00050008
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_CAN1TX         0x00050401
+#define GPIO_PF1_IDX1           0x00050402
+#define GPIO_PF1_PWM1           0x00050403
+#define GPIO_PF1_RXER           0x00050404
+#define GPIO_PF1_I2S0TXMCLK     0x00050408
+#define GPIO_PF1_U1RTS          0x00050409
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_PWM4           0x00050802
+#define GPIO_PF2_PHYINT         0x00050803
+#define GPIO_PF2_PWM2           0x00050804
+#define GPIO_PF2_SSI1CLK        0x00050809
+
+#define GPIO_PF3_PWM5           0x00050C02
+#define GPIO_PF3_MDC            0x00050C03
+#define GPIO_PF3_PWM3           0x00050C04
+#define GPIO_PF3_SSI1FSS        0x00050C09
+
+#define GPIO_PF4_CCP0           0x00051001
+#define GPIO_PF4_C0O            0x00051002
+#define GPIO_PF4_MDIO           0x00051003
+#define GPIO_PF4_FAULT0         0x00051004
+#define GPIO_PF4_EPI0S12        0x00051008
+#define GPIO_PF4_SSI1RX         0x00051009
+
+#define GPIO_PF5_CCP2           0x00051401
+#define GPIO_PF5_C1O            0x00051402
+#define GPIO_PF5_RXD3           0x00051403
+#define GPIO_PF5_EPI0S15        0x00051408
+#define GPIO_PF5_SSI1TX         0x00051409
+
+#define GPIO_PF6_CCP1           0x00051801
+#define GPIO_PF6_C2O            0x00051802
+#define GPIO_PF6_RXD2           0x00051803
+#define GPIO_PF6_PHA0           0x00051804
+#define GPIO_PF6_I2S0TXMCLK     0x00051809
+#define GPIO_PF6_U1RTS          0x0005180A
+
+#define GPIO_PF7_CCP4           0x00051C01
+#define GPIO_PF7_RXD1           0x00051C03
+#define GPIO_PF7_PHB0           0x00051C04
+#define GPIO_PF7_EPI0S12        0x00051C08
+#define GPIO_PF7_FAULT1         0x00051C09
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_PWM0           0x00060002
+#define GPIO_PG0_I2C1SCL        0x00060003
+#define GPIO_PG0_PWM4           0x00060004
+#define GPIO_PG0_USB0EPEN       0x00060007
+#define GPIO_PG0_EPI0S13        0x00060008
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_PWM1           0x00060402
+#define GPIO_PG1_I2C1SDA        0x00060403
+#define GPIO_PG1_PWM5           0x00060404
+#define GPIO_PG1_EPI0S14        0x00060408
+
+#define GPIO_PG2_PWM0           0x00060801
+#define GPIO_PG2_COL            0x00060803
+#define GPIO_PG2_FAULT0         0x00060804
+#define GPIO_PG2_IDX1           0x00060808
+#define GPIO_PG2_I2S0RXSD       0x00060809
+
+#define GPIO_PG3_PWM1           0x00060C01
+#define GPIO_PG3_CRS            0x00060C03
+#define GPIO_PG3_FAULT2         0x00060C04
+#define GPIO_PG3_FAULT0         0x00060C08
+#define GPIO_PG3_I2S0RXMCLK     0x00060C09
+
+#define GPIO_PG4_CCP3           0x00061001
+#define GPIO_PG4_RXD0           0x00061003
+#define GPIO_PG4_FAULT1         0x00061004
+#define GPIO_PG4_EPI0S15        0x00061008
+#define GPIO_PG4_PWM6           0x00061009
+#define GPIO_PG4_U1RI           0x0006100A
+
+#define GPIO_PG5_CCP5           0x00061401
+#define GPIO_PG5_TXEN           0x00061403
+#define GPIO_PG5_IDX0           0x00061404
+#define GPIO_PG5_FAULT1         0x00061405
+#define GPIO_PG5_PWM7           0x00061408
+#define GPIO_PG5_I2S0RXSCK      0x00061409
+#define GPIO_PG5_U1DTR          0x0006140A
+
+#define GPIO_PG6_PHA1           0x00061801
+#define GPIO_PG6_TXCK           0x00061803
+#define GPIO_PG6_PWM6           0x00061804
+#define GPIO_PG6_FAULT1         0x00061808
+#define GPIO_PG6_I2S0RXWS       0x00061809
+#define GPIO_PG6_U1RI           0x0006180A
+
+#define GPIO_PG7_PHB1           0x00061C01
+#define GPIO_PG7_TXER           0x00061C03
+#define GPIO_PG7_PWM7           0x00061C04
+#define GPIO_PG7_CCP5           0x00061C08
+#define GPIO_PG7_EPI0S31        0x00061C09
+
+#define GPIO_PH0_CCP6           0x00070001
+#define GPIO_PH0_PWM2           0x00070002
+#define GPIO_PH0_EPI0S6         0x00070008
+#define GPIO_PH0_PWM4           0x00070009
+
+#define GPIO_PH1_CCP7           0x00070401
+#define GPIO_PH1_PWM3           0x00070402
+#define GPIO_PH1_EPI0S7         0x00070408
+#define GPIO_PH1_PWM5           0x00070409
+
+#define GPIO_PH2_IDX1           0x00070801
+#define GPIO_PH2_C1O            0x00070802
+#define GPIO_PH2_FAULT3         0x00070804
+#define GPIO_PH2_EPI0S1         0x00070808
+#define GPIO_PH2_TXD3           0x00070809
+
+#define GPIO_PH3_PHB0           0x00070C01
+#define GPIO_PH3_FAULT0         0x00070C02
+#define GPIO_PH3_USB0EPEN       0x00070C04
+#define GPIO_PH3_EPI0S0         0x00070C08
+#define GPIO_PH3_TXD2           0x00070C09
+
+#define GPIO_PH4_USB0PFLT       0x00071004
+#define GPIO_PH4_EPI0S10        0x00071008
+#define GPIO_PH4_TXD1           0x00071009
+#define GPIO_PH4_SSI1CLK        0x0007100B
+
+#define GPIO_PH5_EPI0S11        0x00071408
+#define GPIO_PH5_TXD0           0x00071409
+#define GPIO_PH5_FAULT2         0x0007140A
+#define GPIO_PH5_SSI1FSS        0x0007140B
+
+#define GPIO_PH6_EPI0S26        0x00071808
+#define GPIO_PH6_RXDV           0x00071809
+#define GPIO_PH6_PWM4           0x0007180A
+#define GPIO_PH6_SSI1RX         0x0007180B
+
+#define GPIO_PH7_RXCK           0x00071C03
+#define GPIO_PH7_EPI0S27        0x00071C08
+#define GPIO_PH7_PWM5           0x00071C0A
+#define GPIO_PH7_SSI1TX         0x00071C0B
+
+#define GPIO_PJ0_RXER           0x00080003
+#define GPIO_PJ0_EPI0S16        0x00080008
+#define GPIO_PJ0_PWM0           0x0008000A
+#define GPIO_PJ0_I2C1SCL        0x0008000B
+
+#define GPIO_PJ1_EPI0S17        0x00080408
+#define GPIO_PJ1_USB0PFLT       0x00080409
+#define GPIO_PJ1_PWM1           0x0008040A
+#define GPIO_PJ1_I2C1SDA        0x0008040B
+
+#define GPIO_PJ2_EPI0S18        0x00080808
+#define GPIO_PJ2_CCP0           0x00080809
+#define GPIO_PJ2_FAULT0         0x0008080A
+
+#define GPIO_PJ3_EPI0S19        0x00080C08
+#define GPIO_PJ3_U1CTS          0x00080C09
+#define GPIO_PJ3_CCP6           0x00080C0A
+
+#define GPIO_PJ4_EPI0S28        0x00081008
+#define GPIO_PJ4_U1DCD          0x00081009
+#define GPIO_PJ4_CCP4           0x0008100A
+
+#define GPIO_PJ5_EPI0S29        0x00081408
+#define GPIO_PJ5_U1DSR          0x00081409
+#define GPIO_PJ5_CCP2           0x0008140A
+
+#define GPIO_PJ6_EPI0S30        0x00081808
+#define GPIO_PJ6_U1RTS          0x00081809
+#define GPIO_PJ6_CCP1           0x0008180A
+
+#define GPIO_PJ7_U1DTR          0x00081C09
+#define GPIO_PJ7_CCP0           0x00081C0A
+
+#endif // PART_LM3S9BN6
+
+//*****************************************************************************
+//
+// LM3S9C97 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S9C97
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_PWM4           0x00000804
+#define GPIO_PA2_I2S0RXSD       0x00000809
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_PWM5           0x00000C04
+#define GPIO_PA3_I2S0RXMCLK     0x00000C09
+
+#define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_CAN0RX         0x00001005
+#define GPIO_PA4_I2S0TXSCK      0x00001009
+
+#define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_CAN0TX         0x00001405
+#define GPIO_PA5_I2S0TXWS       0x00001409
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_PWM0           0x00001804
+#define GPIO_PA6_PWM4           0x00001805
+#define GPIO_PA6_CAN0RX         0x00001806
+#define GPIO_PA6_USB0EPEN       0x00001808
+#define GPIO_PA6_U1CTS          0x00001809
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_PWM1           0x00001C04
+#define GPIO_PA7_PWM5           0x00001C05
+#define GPIO_PA7_CAN0TX         0x00001C06
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_USB0PFLT       0x00001C08
+#define GPIO_PA7_U1DCD          0x00001C09
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_PWM2           0x00010002
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_PWM3           0x00010402
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_IDX0           0x00010802
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+#define GPIO_PB2_USB0EPEN       0x00010808
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_FAULT0         0x00010C02
+#define GPIO_PB3_FAULT3         0x00010C04
+#define GPIO_PB3_USB0PFLT       0x00010C08
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_CAN0RX         0x00011005
+#define GPIO_PB4_IDX0           0x00011006
+#define GPIO_PB4_U1RX           0x00011007
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CAN0TX         0x00011405
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_FAULT1         0x00011804
+#define GPIO_PB6_IDX0           0x00011805
+#define GPIO_PB6_CCP5           0x00011806
+#define GPIO_PB6_I2S0TXSCK      0x00011809
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_PHA0           0x00021002
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_FAULT2         0x00021404
+#define GPIO_PC5_CCP3           0x00021405
+#define GPIO_PC5_USB0EPEN       0x00021406
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_PHB0           0x00021802
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+#define GPIO_PC6_USB0PFLT       0x00021807
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_PHB0           0x00021C02
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_USB0PFLT       0x00021C06
+#define GPIO_PC7_C1O            0x00021C07
+
+#define GPIO_PD0_PWM0           0x00030001
+#define GPIO_PD0_CAN0RX         0x00030002
+#define GPIO_PD0_IDX0           0x00030003
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+#define GPIO_PD0_I2S0RXSCK      0x00030008
+#define GPIO_PD0_U1CTS          0x00030009
+
+#define GPIO_PD1_PWM1           0x00030401
+#define GPIO_PD1_CAN0TX         0x00030402
+#define GPIO_PD1_PHA0           0x00030403
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_I2S0RXWS       0x00030408
+#define GPIO_PD1_U1DCD          0x00030409
+#define GPIO_PD1_CCP2           0x0003040A
+#define GPIO_PD1_PHB1           0x0003040B
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_PWM2           0x00030803
+#define GPIO_PD2_CCP5           0x00030804
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_PWM3           0x00030C03
+#define GPIO_PD3_CCP0           0x00030C04
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+#define GPIO_PD4_I2S0RXSD       0x00031008
+#define GPIO_PD4_U1RI           0x00031009
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_I2S0RXMCLK     0x00031408
+#define GPIO_PD5_U2RX           0x00031409
+
+#define GPIO_PD6_FAULT0         0x00031801
+#define GPIO_PD6_I2S0TXSCK      0x00031808
+#define GPIO_PD6_U2TX           0x00031809
+
+#define GPIO_PD7_IDX0           0x00031C01
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+#define GPIO_PD7_I2S0TXWS       0x00031C08
+#define GPIO_PD7_U1DTR          0x00031C09
+
+#define GPIO_PE0_PWM4           0x00040001
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+#define GPIO_PE0_USB0PFLT       0x00040009
+
+#define GPIO_PE1_PWM5           0x00040401
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_FAULT0         0x00040403
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_PHB1           0x00040803
+#define GPIO_PE2_PHA0           0x00040804
+#define GPIO_PE2_CCP2           0x00040805
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_PHA1           0x00040C03
+#define GPIO_PE3_PHB0           0x00040C04
+#define GPIO_PE3_CCP7           0x00040C05
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_FAULT0         0x00041004
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+#define GPIO_PE4_I2S0TXWS       0x00041009
+
+#define GPIO_PE5_CCP5           0x00041401
+#define GPIO_PE5_I2S0TXSD       0x00041409
+
+#define GPIO_PE6_PWM4           0x00041801
+#define GPIO_PE6_C1O            0x00041802
+#define GPIO_PE6_U1CTS          0x00041809
+
+#define GPIO_PE7_PWM5           0x00041C01
+#define GPIO_PE7_U1DCD          0x00041C09
+
+#define GPIO_PF0_CAN1RX         0x00050001
+#define GPIO_PF0_PHB0           0x00050002
+#define GPIO_PF0_PWM0           0x00050003
+#define GPIO_PF0_I2S0TXSD       0x00050008
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_CAN1TX         0x00050401
+#define GPIO_PF1_IDX1           0x00050402
+#define GPIO_PF1_PWM1           0x00050403
+#define GPIO_PF1_I2S0TXMCLK     0x00050408
+#define GPIO_PF1_U1RTS          0x00050409
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_LED1           0x00050801
+#define GPIO_PF2_PWM4           0x00050802
+#define GPIO_PF2_PWM2           0x00050804
+#define GPIO_PF2_SSI1CLK        0x00050809
+
+#define GPIO_PF3_LED0           0x00050C01
+#define GPIO_PF3_PWM5           0x00050C02
+#define GPIO_PF3_PWM3           0x00050C04
+#define GPIO_PF3_SSI1FSS        0x00050C09
+
+#define GPIO_PF4_CCP0           0x00051001
+#define GPIO_PF4_C0O            0x00051002
+#define GPIO_PF4_FAULT0         0x00051004
+#define GPIO_PF4_SSI1RX         0x00051009
+
+#define GPIO_PF5_CCP2           0x00051401
+#define GPIO_PF5_C1O            0x00051402
+#define GPIO_PF5_SSI1TX         0x00051409
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_PWM0           0x00060002
+#define GPIO_PG0_I2C1SCL        0x00060003
+#define GPIO_PG0_PWM4           0x00060004
+#define GPIO_PG0_USB0EPEN       0x00060007
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_PWM1           0x00060402
+#define GPIO_PG1_I2C1SDA        0x00060403
+#define GPIO_PG1_PWM5           0x00060404
+
+#define GPIO_PG7_PHB1           0x00061C01
+#define GPIO_PG7_CCP5           0x00061C08
+
+#define GPIO_PH0_CCP6           0x00070001
+#define GPIO_PH0_PWM2           0x00070002
+#define GPIO_PH0_PWM4           0x00070009
+
+#define GPIO_PH1_CCP7           0x00070401
+#define GPIO_PH1_PWM3           0x00070402
+#define GPIO_PH1_PWM5           0x00070409
+
+#define GPIO_PH2_IDX1           0x00070801
+#define GPIO_PH2_C1O            0x00070802
+#define GPIO_PH2_FAULT3         0x00070804
+
+#define GPIO_PH3_PHB0           0x00070C01
+#define GPIO_PH3_FAULT0         0x00070C02
+#define GPIO_PH3_USB0EPEN       0x00070C04
+
+#define GPIO_PH4_USB0PFLT       0x00071004
+#define GPIO_PH4_SSI1CLK        0x0007100B
+
+#define GPIO_PH5_FAULT2         0x0007140A
+#define GPIO_PH5_SSI1FSS        0x0007140B
+
+#define GPIO_PH6_PWM4           0x0007180A
+#define GPIO_PH6_SSI1RX         0x0007180B
+
+#define GPIO_PH7_PWM5           0x00071C0A
+#define GPIO_PH7_SSI1TX         0x00071C0B
+
+#define GPIO_PJ0_PWM0           0x0008000A
+#define GPIO_PJ0_I2C1SCL        0x0008000B
+
+#define GPIO_PJ1_USB0PFLT       0x00080409
+#define GPIO_PJ1_PWM1           0x0008040A
+#define GPIO_PJ1_I2C1SDA        0x0008040B
+
+#define GPIO_PJ2_CCP0           0x00080809
+#define GPIO_PJ2_FAULT0         0x0008080A
+
+#endif // PART_LM3S9C97
+
+//*****************************************************************************
+//
+// LM3S9CN5 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S9CN5
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_TXD2           0x00000803
+#define GPIO_PA2_PWM4           0x00000804
+#define GPIO_PA2_I2S0RXSD       0x00000809
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_TXD1           0x00000C03
+#define GPIO_PA3_PWM5           0x00000C04
+#define GPIO_PA3_I2S0RXMCLK     0x00000C09
+
+#define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_TXD0           0x00001003
+#define GPIO_PA4_PWM6           0x00001004
+#define GPIO_PA4_CAN0RX         0x00001005
+#define GPIO_PA4_I2S0TXSCK      0x00001009
+
+#define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_RXDV           0x00001403
+#define GPIO_PA5_PWM7           0x00001404
+#define GPIO_PA5_CAN0TX         0x00001405
+#define GPIO_PA5_I2S0TXWS       0x00001409
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_RXCK           0x00001803
+#define GPIO_PA6_PWM0           0x00001804
+#define GPIO_PA6_PWM4           0x00001805
+#define GPIO_PA6_CAN0RX         0x00001806
+#define GPIO_PA6_USB0EPEN       0x00001808
+#define GPIO_PA6_U1CTS          0x00001809
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_RXER           0x00001C03
+#define GPIO_PA7_PWM1           0x00001C04
+#define GPIO_PA7_PWM5           0x00001C05
+#define GPIO_PA7_CAN0TX         0x00001C06
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_USB0PFLT       0x00001C08
+#define GPIO_PA7_U1DCD          0x00001C09
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_PWM2           0x00010002
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_PWM3           0x00010402
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_IDX0           0x00010802
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+#define GPIO_PB2_USB0EPEN       0x00010808
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_FAULT0         0x00010C02
+#define GPIO_PB3_FAULT3         0x00010C04
+#define GPIO_PB3_USB0PFLT       0x00010C08
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_CAN0RX         0x00011005
+#define GPIO_PB4_IDX0           0x00011006
+#define GPIO_PB4_U1RX           0x00011007
+#define GPIO_PB4_EPI0S23        0x00011008
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CAN0TX         0x00011405
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+#define GPIO_PB5_EPI0S22        0x00011408
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_FAULT1         0x00011804
+#define GPIO_PB6_IDX0           0x00011805
+#define GPIO_PB6_CCP5           0x00011806
+#define GPIO_PB6_I2S0TXSCK      0x00011809
+
+#define GPIO_PB7_NMI            0x00011C04
+#define GPIO_PB7_RXD1           0x00011C07
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_PHA0           0x00021002
+#define GPIO_PC4_TXD3           0x00021003
+#define GPIO_PC4_PWM6           0x00021004
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_EPI0S2         0x00021008
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_FAULT2         0x00021404
+#define GPIO_PC5_CCP3           0x00021405
+#define GPIO_PC5_USB0EPEN       0x00021406
+#define GPIO_PC5_EPI0S3         0x00021408
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_PHB0           0x00021802
+#define GPIO_PC6_C2O            0x00021803
+#define GPIO_PC6_PWM7           0x00021804
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+#define GPIO_PC6_USB0PFLT       0x00021807
+#define GPIO_PC6_EPI0S4         0x00021808
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_PHB0           0x00021C02
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_USB0PFLT       0x00021C06
+#define GPIO_PC7_C1O            0x00021C07
+#define GPIO_PC7_EPI0S5         0x00021C08
+
+#define GPIO_PD0_PWM0           0x00030001
+#define GPIO_PD0_CAN0RX         0x00030002
+#define GPIO_PD0_IDX0           0x00030003
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+#define GPIO_PD0_RXDV           0x00030007
+#define GPIO_PD0_I2S0RXSCK      0x00030008
+#define GPIO_PD0_U1CTS          0x00030009
+
+#define GPIO_PD1_PWM1           0x00030401
+#define GPIO_PD1_CAN0TX         0x00030402
+#define GPIO_PD1_PHA0           0x00030403
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_TXER           0x00030407
+#define GPIO_PD1_I2S0RXWS       0x00030408
+#define GPIO_PD1_U1DCD          0x00030409
+#define GPIO_PD1_CCP2           0x0003040A
+#define GPIO_PD1_PHB1           0x0003040B
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_PWM2           0x00030803
+#define GPIO_PD2_CCP5           0x00030804
+#define GPIO_PD2_EPI0S20        0x00030808
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_PWM3           0x00030C03
+#define GPIO_PD3_CCP0           0x00030C04
+#define GPIO_PD3_EPI0S21        0x00030C08
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+#define GPIO_PD4_TXD3           0x00031004
+#define GPIO_PD4_I2S0RXSD       0x00031008
+#define GPIO_PD4_U1RI           0x00031009
+#define GPIO_PD4_EPI0S19        0x0003100A
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_TXD2           0x00031404
+#define GPIO_PD5_I2S0RXMCLK     0x00031408
+#define GPIO_PD5_U2RX           0x00031409
+#define GPIO_PD5_EPI0S28        0x0003140A
+
+#define GPIO_PD6_FAULT0         0x00031801
+#define GPIO_PD6_TXD1           0x00031804
+#define GPIO_PD6_I2S0TXSCK      0x00031808
+#define GPIO_PD6_U2TX           0x00031809
+#define GPIO_PD6_EPI0S29        0x0003180A
+
+#define GPIO_PD7_IDX0           0x00031C01
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+#define GPIO_PD7_TXD0           0x00031C04
+#define GPIO_PD7_I2S0TXWS       0x00031C08
+#define GPIO_PD7_U1DTR          0x00031C09
+#define GPIO_PD7_EPI0S30        0x00031C0A
+
+#define GPIO_PE0_PWM4           0x00040001
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+#define GPIO_PE0_EPI0S8         0x00040008
+#define GPIO_PE0_USB0PFLT       0x00040009
+
+#define GPIO_PE1_PWM5           0x00040401
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_FAULT0         0x00040403
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+#define GPIO_PE1_EPI0S9         0x00040408
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_PHB1           0x00040803
+#define GPIO_PE2_PHA0           0x00040804
+#define GPIO_PE2_CCP2           0x00040805
+#define GPIO_PE2_EPI0S24        0x00040808
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_PHA1           0x00040C03
+#define GPIO_PE3_PHB0           0x00040C04
+#define GPIO_PE3_CCP7           0x00040C05
+#define GPIO_PE3_EPI0S25        0x00040C08
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_FAULT0         0x00041004
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+#define GPIO_PE4_RXD0           0x00041007
+#define GPIO_PE4_I2S0TXWS       0x00041009
+
+#define GPIO_PE5_CCP5           0x00041401
+#define GPIO_PE5_I2S0TXSD       0x00041409
+
+#define GPIO_PE6_PWM4           0x00041801
+#define GPIO_PE6_C1O            0x00041802
+#define GPIO_PE6_U1CTS          0x00041809
+
+#define GPIO_PE7_PWM5           0x00041C01
+#define GPIO_PE7_C2O            0x00041C02
+#define GPIO_PE7_U1DCD          0x00041C09
+
+#define GPIO_PF0_CAN1RX         0x00050001
+#define GPIO_PF0_PHB0           0x00050002
+#define GPIO_PF0_PWM0           0x00050003
+#define GPIO_PF0_RXCK           0x00050004
+#define GPIO_PF0_I2S0TXSD       0x00050008
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_CAN1TX         0x00050401
+#define GPIO_PF1_IDX1           0x00050402
+#define GPIO_PF1_PWM1           0x00050403
+#define GPIO_PF1_RXER           0x00050404
+#define GPIO_PF1_I2S0TXMCLK     0x00050408
+#define GPIO_PF1_U1RTS          0x00050409
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_PWM4           0x00050802
+#define GPIO_PF2_PHYINT         0x00050803
+#define GPIO_PF2_PWM2           0x00050804
+#define GPIO_PF2_SSI1CLK        0x00050809
+
+#define GPIO_PF3_PWM5           0x00050C02
+#define GPIO_PF3_MDC            0x00050C03
+#define GPIO_PF3_PWM3           0x00050C04
+#define GPIO_PF3_SSI1FSS        0x00050C09
+
+#define GPIO_PF4_CCP0           0x00051001
+#define GPIO_PF4_C0O            0x00051002
+#define GPIO_PF4_MDIO           0x00051003
+#define GPIO_PF4_FAULT0         0x00051004
+#define GPIO_PF4_EPI0S12        0x00051008
+#define GPIO_PF4_SSI1RX         0x00051009
+
+#define GPIO_PF5_CCP2           0x00051401
+#define GPIO_PF5_C1O            0x00051402
+#define GPIO_PF5_RXD3           0x00051403
+#define GPIO_PF5_EPI0S15        0x00051408
+#define GPIO_PF5_SSI1TX         0x00051409
+
+#define GPIO_PF6_CCP1           0x00051801
+#define GPIO_PF6_C2O            0x00051802
+#define GPIO_PF6_RXD2           0x00051803
+#define GPIO_PF6_PHA0           0x00051804
+#define GPIO_PF6_I2S0TXMCLK     0x00051809
+#define GPIO_PF6_U1RTS          0x0005180A
+
+#define GPIO_PF7_CCP4           0x00051C01
+#define GPIO_PF7_RXD1           0x00051C03
+#define GPIO_PF7_PHB0           0x00051C04
+#define GPIO_PF7_EPI0S12        0x00051C08
+#define GPIO_PF7_FAULT1         0x00051C09
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_PWM0           0x00060002
+#define GPIO_PG0_I2C1SCL        0x00060003
+#define GPIO_PG0_PWM4           0x00060004
+#define GPIO_PG0_USB0EPEN       0x00060007
+#define GPIO_PG0_EPI0S13        0x00060008
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_PWM1           0x00060402
+#define GPIO_PG1_I2C1SDA        0x00060403
+#define GPIO_PG1_PWM5           0x00060404
+#define GPIO_PG1_EPI0S14        0x00060408
+
+#define GPIO_PG2_PWM0           0x00060801
+#define GPIO_PG2_COL            0x00060803
+#define GPIO_PG2_FAULT0         0x00060804
+#define GPIO_PG2_IDX1           0x00060808
+#define GPIO_PG2_I2S0RXSD       0x00060809
+
+#define GPIO_PG3_PWM1           0x00060C01
+#define GPIO_PG3_CRS            0x00060C03
+#define GPIO_PG3_FAULT2         0x00060C04
+#define GPIO_PG3_FAULT0         0x00060C08
+#define GPIO_PG3_I2S0RXMCLK     0x00060C09
+
+#define GPIO_PG4_CCP3           0x00061001
+#define GPIO_PG4_RXD0           0x00061003
+#define GPIO_PG4_FAULT1         0x00061004
+#define GPIO_PG4_EPI0S15        0x00061008
+#define GPIO_PG4_PWM6           0x00061009
+#define GPIO_PG4_U1RI           0x0006100A
+
+#define GPIO_PG5_CCP5           0x00061401
+#define GPIO_PG5_TXEN           0x00061403
+#define GPIO_PG5_IDX0           0x00061404
+#define GPIO_PG5_FAULT1         0x00061405
+#define GPIO_PG5_PWM7           0x00061408
+#define GPIO_PG5_I2S0RXSCK      0x00061409
+#define GPIO_PG5_U1DTR          0x0006140A
+
+#define GPIO_PG6_PHA1           0x00061801
+#define GPIO_PG6_TXCK           0x00061803
+#define GPIO_PG6_PWM6           0x00061804
+#define GPIO_PG6_FAULT1         0x00061808
+#define GPIO_PG6_I2S0RXWS       0x00061809
+#define GPIO_PG6_U1RI           0x0006180A
+
+#define GPIO_PG7_PHB1           0x00061C01
+#define GPIO_PG7_TXER           0x00061C03
+#define GPIO_PG7_PWM7           0x00061C04
+#define GPIO_PG7_CCP5           0x00061C08
+#define GPIO_PG7_EPI0S31        0x00061C09
+
+#define GPIO_PH0_CCP6           0x00070001
+#define GPIO_PH0_PWM2           0x00070002
+#define GPIO_PH0_EPI0S6         0x00070008
+#define GPIO_PH0_PWM4           0x00070009
+
+#define GPIO_PH1_CCP7           0x00070401
+#define GPIO_PH1_PWM3           0x00070402
+#define GPIO_PH1_EPI0S7         0x00070408
+#define GPIO_PH1_PWM5           0x00070409
+
+#define GPIO_PH2_IDX1           0x00070801
+#define GPIO_PH2_C1O            0x00070802
+#define GPIO_PH2_FAULT3         0x00070804
+#define GPIO_PH2_EPI0S1         0x00070808
+#define GPIO_PH2_TXD3           0x00070809
+
+#define GPIO_PH3_PHB0           0x00070C01
+#define GPIO_PH3_FAULT0         0x00070C02
+#define GPIO_PH3_USB0EPEN       0x00070C04
+#define GPIO_PH3_EPI0S0         0x00070C08
+#define GPIO_PH3_TXD2           0x00070C09
+
+#define GPIO_PH4_USB0PFLT       0x00071004
+#define GPIO_PH4_EPI0S10        0x00071008
+#define GPIO_PH4_TXD1           0x00071009
+#define GPIO_PH4_SSI1CLK        0x0007100B
+
+#define GPIO_PH5_EPI0S11        0x00071408
+#define GPIO_PH5_TXD0           0x00071409
+#define GPIO_PH5_FAULT2         0x0007140A
+#define GPIO_PH5_SSI1FSS        0x0007140B
+
+#define GPIO_PH6_EPI0S26        0x00071808
+#define GPIO_PH6_RXDV           0x00071809
+#define GPIO_PH6_PWM4           0x0007180A
+#define GPIO_PH6_SSI1RX         0x0007180B
+
+#define GPIO_PH7_RXCK           0x00071C03
+#define GPIO_PH7_EPI0S27        0x00071C08
+#define GPIO_PH7_PWM5           0x00071C0A
+#define GPIO_PH7_SSI1TX         0x00071C0B
+
+#define GPIO_PJ0_RXER           0x00080003
+#define GPIO_PJ0_EPI0S16        0x00080008
+#define GPIO_PJ0_PWM0           0x0008000A
+#define GPIO_PJ0_I2C1SCL        0x0008000B
+
+#define GPIO_PJ1_EPI0S17        0x00080408
+#define GPIO_PJ1_USB0PFLT       0x00080409
+#define GPIO_PJ1_PWM1           0x0008040A
+#define GPIO_PJ1_I2C1SDA        0x0008040B
+
+#define GPIO_PJ2_EPI0S18        0x00080808
+#define GPIO_PJ2_CCP0           0x00080809
+#define GPIO_PJ2_FAULT0         0x0008080A
+
+#define GPIO_PJ3_EPI0S19        0x00080C08
+#define GPIO_PJ3_U1CTS          0x00080C09
+#define GPIO_PJ3_CCP6           0x00080C0A
+
+#define GPIO_PJ4_EPI0S28        0x00081008
+#define GPIO_PJ4_U1DCD          0x00081009
+#define GPIO_PJ4_CCP4           0x0008100A
+
+#define GPIO_PJ5_EPI0S29        0x00081408
+#define GPIO_PJ5_U1DSR          0x00081409
+#define GPIO_PJ5_CCP2           0x0008140A
+
+#define GPIO_PJ6_EPI0S30        0x00081808
+#define GPIO_PJ6_U1RTS          0x00081809
+#define GPIO_PJ6_CCP1           0x0008180A
+
+#define GPIO_PJ7_U1DTR          0x00081C09
+#define GPIO_PJ7_CCP0           0x00081C0A
+
+#endif // PART_LM3S9CN5
+
+//*****************************************************************************
+//
+// LM3S9D81 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S9D81
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_I2S0RXSD       0x00000809
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_I2S0RXMCLK     0x00000C09
+
+#define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_CAN0RX         0x00001005
+#define GPIO_PA4_I2S0TXSCK      0x00001009
+
+#define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_CAN0TX         0x00001405
+#define GPIO_PA5_I2S0TXWS       0x00001409
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_CAN0RX         0x00001806
+#define GPIO_PA6_USB0EPEN       0x00001808
+#define GPIO_PA6_U1CTS          0x00001809
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_CAN0TX         0x00001C06
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_USB0PFLT       0x00001C08
+#define GPIO_PA7_U1DCD          0x00001C09
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+#define GPIO_PB2_USB0EPEN       0x00010808
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_USB0PFLT       0x00010C08
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_CAN0RX         0x00011005
+#define GPIO_PB4_U1RX           0x00011007
+#define GPIO_PB4_EPI0S23        0x00011008
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CAN0TX         0x00011405
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+#define GPIO_PB5_EPI0S22        0x00011408
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_CCP5           0x00011806
+#define GPIO_PB6_I2S0TXSCK      0x00011809
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_EPI0S2         0x00021008
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_CCP3           0x00021405
+#define GPIO_PC5_USB0EPEN       0x00021406
+#define GPIO_PC5_EPI0S3         0x00021408
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_C2O            0x00021803
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+#define GPIO_PC6_USB0PFLT       0x00021807
+#define GPIO_PC6_EPI0S4         0x00021808
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_USB0PFLT       0x00021C06
+#define GPIO_PC7_C1O            0x00021C07
+#define GPIO_PC7_EPI0S5         0x00021C08
+
+#define GPIO_PD0_CAN0RX         0x00030002
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+#define GPIO_PD0_I2S0RXSCK      0x00030008
+#define GPIO_PD0_U1CTS          0x00030009
+
+#define GPIO_PD1_CAN0TX         0x00030402
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_I2S0RXWS       0x00030408
+#define GPIO_PD1_U1DCD          0x00030409
+#define GPIO_PD1_CCP2           0x0003040A
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_CCP5           0x00030804
+#define GPIO_PD2_EPI0S20        0x00030808
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_CCP0           0x00030C04
+#define GPIO_PD3_EPI0S21        0x00030C08
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+#define GPIO_PD4_I2S0RXSD       0x00031008
+#define GPIO_PD4_U1RI           0x00031009
+#define GPIO_PD4_EPI0S19        0x0003100A
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_I2S0RXMCLK     0x00031408
+#define GPIO_PD5_U2RX           0x00031409
+#define GPIO_PD5_EPI0S28        0x0003140A
+
+#define GPIO_PD6_I2S0TXSCK      0x00031808
+#define GPIO_PD6_U2TX           0x00031809
+#define GPIO_PD6_EPI0S29        0x0003180A
+
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+#define GPIO_PD7_I2S0TXWS       0x00031C08
+#define GPIO_PD7_U1DTR          0x00031C09
+#define GPIO_PD7_EPI0S30        0x00031C0A
+
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+#define GPIO_PE0_EPI0S8         0x00040008
+#define GPIO_PE0_USB0PFLT       0x00040009
+
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+#define GPIO_PE1_EPI0S9         0x00040408
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_CCP2           0x00040805
+#define GPIO_PE2_EPI0S24        0x00040808
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_CCP7           0x00040C05
+#define GPIO_PE3_EPI0S25        0x00040C08
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_CAN2RX         0x00041002
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+#define GPIO_PE4_I2S0TXWS       0x00041009
+
+#define GPIO_PE5_CCP5           0x00041401
+#define GPIO_PE5_CAN2TX         0x00041402
+#define GPIO_PE5_I2S0TXSD       0x00041409
+
+#define GPIO_PE6_C1O            0x00041802
+#define GPIO_PE6_U1CTS          0x00041809
+
+#define GPIO_PE7_C2O            0x00041C02
+#define GPIO_PE7_U1DCD          0x00041C09
+
+#define GPIO_PF0_CAN1RX         0x00050001
+#define GPIO_PF0_I2S0TXSD       0x00050008
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_CAN1TX         0x00050401
+#define GPIO_PF1_I2S0TXMCLK     0x00050408
+#define GPIO_PF1_U1RTS          0x00050409
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_LED1           0x00050801
+#define GPIO_PF2_SSI1CLK        0x00050809
+
+#define GPIO_PF3_LED0           0x00050C01
+#define GPIO_PF3_SSI1FSS        0x00050C09
+
+#define GPIO_PF4_CCP0           0x00051001
+#define GPIO_PF4_C0O            0x00051002
+#define GPIO_PF4_EPI0S12        0x00051008
+#define GPIO_PF4_SSI1RX         0x00051009
+
+#define GPIO_PF5_CCP2           0x00051401
+#define GPIO_PF5_C1O            0x00051402
+#define GPIO_PF5_EPI0S15        0x00051408
+#define GPIO_PF5_SSI1TX         0x00051409
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_I2C1SCL        0x00060003
+#define GPIO_PG0_USB0EPEN       0x00060007
+#define GPIO_PG0_EPI0S13        0x00060008
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_I2C1SDA        0x00060403
+#define GPIO_PG1_EPI0S14        0x00060408
+
+#define GPIO_PG7_CCP5           0x00061C08
+#define GPIO_PG7_EPI0S31        0x00061C09
+
+#define GPIO_PH0_CCP6           0x00070001
+#define GPIO_PH0_EPI0S6         0x00070008
+
+#define GPIO_PH1_CCP7           0x00070401
+#define GPIO_PH1_EPI0S7         0x00070408
+
+#define GPIO_PH2_C1O            0x00070802
+#define GPIO_PH2_EPI0S1         0x00070808
+
+#define GPIO_PH3_USB0EPEN       0x00070C04
+#define GPIO_PH3_EPI0S0         0x00070C08
+
+#define GPIO_PH4_USB0PFLT       0x00071004
+#define GPIO_PH4_EPI0S10        0x00071008
+#define GPIO_PH4_SSI1CLK        0x0007100B
+
+#define GPIO_PH5_EPI0S11        0x00071408
+#define GPIO_PH5_SSI1FSS        0x0007140B
+
+#define GPIO_PH6_EPI0S26        0x00071808
+#define GPIO_PH6_SSI1RX         0x0007180B
+
+#define GPIO_PH7_EPI0S27        0x00071C08
+#define GPIO_PH7_SSI1TX         0x00071C0B
+
+#define GPIO_PJ0_EPI0S16        0x00080008
+#define GPIO_PJ0_I2C1SCL        0x0008000B
+
+#define GPIO_PJ1_EPI0S17        0x00080408
+#define GPIO_PJ1_USB0PFLT       0x00080409
+#define GPIO_PJ1_I2C1SDA        0x0008040B
+
+#define GPIO_PJ2_EPI0S18        0x00080808
+#define GPIO_PJ2_CCP0           0x00080809
+
+#define GPIO_PJ3_EPI0S19        0x00080C08
+#define GPIO_PJ3_U1CTS          0x00080C09
+#define GPIO_PJ3_CCP6           0x00080C0A
+
+#define GPIO_PJ4_EPI0S28        0x00081008
+#define GPIO_PJ4_U1DCD          0x00081009
+#define GPIO_PJ4_CCP4           0x0008100A
+
+#define GPIO_PJ5_EPI0S29        0x00081408
+#define GPIO_PJ5_U1DSR          0x00081409
+#define GPIO_PJ5_CCP2           0x0008140A
+
+#define GPIO_PJ6_EPI0S30        0x00081808
+#define GPIO_PJ6_U1RTS          0x00081809
+#define GPIO_PJ6_CCP1           0x0008180A
+
+#define GPIO_PJ7_U1DTR          0x00081C09
+#define GPIO_PJ7_CCP0           0x00081C0A
+
+#endif // PART_LM3S9D81
+
+//*****************************************************************************
+//
+// LM3S9D90 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S9D90
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_I2S0RXSD       0x00000809
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_I2S0RXMCLK     0x00000C09
+
+#define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_CAN0RX         0x00001005
+#define GPIO_PA4_I2S0TXSCK      0x00001009
+
+#define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_CAN0TX         0x00001405
+#define GPIO_PA5_I2S0TXWS       0x00001409
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_CAN0RX         0x00001806
+#define GPIO_PA6_USB0EPEN       0x00001808
+#define GPIO_PA6_U1CTS          0x00001809
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_CAN0TX         0x00001C06
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_USB0PFLT       0x00001C08
+#define GPIO_PA7_U1DCD          0x00001C09
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+#define GPIO_PB2_USB0EPEN       0x00010808
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_USB0PFLT       0x00010C08
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_CAN0RX         0x00011005
+#define GPIO_PB4_U1RX           0x00011007
+#define GPIO_PB4_EPI0S23        0x00011008
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CAN0TX         0x00011405
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+#define GPIO_PB5_EPI0S22        0x00011408
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_CCP5           0x00011806
+#define GPIO_PB6_I2S0TXSCK      0x00011809
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_EPI0S2         0x00021008
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_CCP3           0x00021405
+#define GPIO_PC5_USB0EPEN       0x00021406
+#define GPIO_PC5_EPI0S3         0x00021408
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_C2O            0x00021803
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+#define GPIO_PC6_USB0PFLT       0x00021807
+#define GPIO_PC6_EPI0S4         0x00021808
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_USB0PFLT       0x00021C06
+#define GPIO_PC7_C1O            0x00021C07
+#define GPIO_PC7_EPI0S5         0x00021C08
+
+#define GPIO_PD0_CAN0RX         0x00030002
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+#define GPIO_PD0_I2S0RXSCK      0x00030008
+#define GPIO_PD0_U1CTS          0x00030009
+
+#define GPIO_PD1_CAN0TX         0x00030402
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_I2S0RXWS       0x00030408
+#define GPIO_PD1_U1DCD          0x00030409
+#define GPIO_PD1_CCP2           0x0003040A
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_CCP5           0x00030804
+#define GPIO_PD2_EPI0S20        0x00030808
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_CCP0           0x00030C04
+#define GPIO_PD3_EPI0S21        0x00030C08
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+#define GPIO_PD4_I2S0RXSD       0x00031008
+#define GPIO_PD4_U1RI           0x00031009
+#define GPIO_PD4_EPI0S19        0x0003100A
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_I2S0RXMCLK     0x00031408
+#define GPIO_PD5_U2RX           0x00031409
+#define GPIO_PD5_EPI0S28        0x0003140A
+
+#define GPIO_PD6_I2S0TXSCK      0x00031808
+#define GPIO_PD6_U2TX           0x00031809
+#define GPIO_PD6_EPI0S29        0x0003180A
+
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+#define GPIO_PD7_I2S0TXWS       0x00031C08
+#define GPIO_PD7_U1DTR          0x00031C09
+#define GPIO_PD7_EPI0S30        0x00031C0A
+
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+#define GPIO_PE0_EPI0S8         0x00040008
+#define GPIO_PE0_USB0PFLT       0x00040009
+
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+#define GPIO_PE1_EPI0S9         0x00040408
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_CCP2           0x00040805
+#define GPIO_PE2_EPI0S24        0x00040808
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_CCP7           0x00040C05
+#define GPIO_PE3_EPI0S25        0x00040C08
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+#define GPIO_PE4_I2S0TXWS       0x00041009
+
+#define GPIO_PE5_CCP5           0x00041401
+#define GPIO_PE5_I2S0TXSD       0x00041409
+
+#define GPIO_PE6_C1O            0x00041802
+#define GPIO_PE6_U1CTS          0x00041809
+
+#define GPIO_PE7_C2O            0x00041C02
+#define GPIO_PE7_U1DCD          0x00041C09
+
+#define GPIO_PF0_CAN1RX         0x00050001
+#define GPIO_PF0_I2S0TXSD       0x00050008
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_CAN1TX         0x00050401
+#define GPIO_PF1_I2S0TXMCLK     0x00050408
+#define GPIO_PF1_U1RTS          0x00050409
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_LED1           0x00050801
+#define GPIO_PF2_SSI1CLK        0x00050809
+
+#define GPIO_PF3_LED0           0x00050C01
+#define GPIO_PF3_SSI1FSS        0x00050C09
+
+#define GPIO_PF4_CCP0           0x00051001
+#define GPIO_PF4_C0O            0x00051002
+#define GPIO_PF4_EPI0S12        0x00051008
+#define GPIO_PF4_SSI1RX         0x00051009
+
+#define GPIO_PF5_CCP2           0x00051401
+#define GPIO_PF5_C1O            0x00051402
+#define GPIO_PF5_EPI0S15        0x00051408
+#define GPIO_PF5_SSI1TX         0x00051409
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_I2C1SCL        0x00060003
+#define GPIO_PG0_USB0EPEN       0x00060007
+#define GPIO_PG0_EPI0S13        0x00060008
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_I2C1SDA        0x00060403
+#define GPIO_PG1_EPI0S14        0x00060408
+
+#define GPIO_PG7_CCP5           0x00061C08
+#define GPIO_PG7_EPI0S31        0x00061C09
+
+#define GPIO_PH0_CCP6           0x00070001
+#define GPIO_PH0_EPI0S6         0x00070008
+
+#define GPIO_PH1_CCP7           0x00070401
+#define GPIO_PH1_EPI0S7         0x00070408
+
+#define GPIO_PH2_C1O            0x00070802
+#define GPIO_PH2_EPI0S1         0x00070808
+
+#define GPIO_PH3_USB0EPEN       0x00070C04
+#define GPIO_PH3_EPI0S0         0x00070C08
+
+#define GPIO_PH4_USB0PFLT       0x00071004
+#define GPIO_PH4_EPI0S10        0x00071008
+#define GPIO_PH4_SSI1CLK        0x0007100B
+
+#define GPIO_PH5_EPI0S11        0x00071408
+#define GPIO_PH5_SSI1FSS        0x0007140B
+
+#define GPIO_PH6_EPI0S26        0x00071808
+#define GPIO_PH6_SSI1RX         0x0007180B
+
+#define GPIO_PH7_EPI0S27        0x00071C08
+#define GPIO_PH7_SSI1TX         0x00071C0B
+
+#define GPIO_PJ0_EPI0S16        0x00080008
+#define GPIO_PJ0_I2C1SCL        0x0008000B
+
+#define GPIO_PJ1_EPI0S17        0x00080408
+#define GPIO_PJ1_USB0PFLT       0x00080409
+#define GPIO_PJ1_I2C1SDA        0x0008040B
+
+#define GPIO_PJ2_EPI0S18        0x00080808
+#define GPIO_PJ2_CCP0           0x00080809
+
+#endif // PART_LM3S9D90
+
+//*****************************************************************************
+//
+// LM3S9D92 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S9D92
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_PWM4           0x00000804
+#define GPIO_PA2_I2S0RXSD       0x00000809
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_PWM5           0x00000C04
+#define GPIO_PA3_I2S0RXMCLK     0x00000C09
+
+#define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_PWM6           0x00001004
+#define GPIO_PA4_CAN0RX         0x00001005
+#define GPIO_PA4_I2S0TXSCK      0x00001009
+
+#define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_PWM7           0x00001404
+#define GPIO_PA5_CAN0TX         0x00001405
+#define GPIO_PA5_I2S0TXWS       0x00001409
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_PWM0           0x00001804
+#define GPIO_PA6_PWM4           0x00001805
+#define GPIO_PA6_CAN0RX         0x00001806
+#define GPIO_PA6_USB0EPEN       0x00001808
+#define GPIO_PA6_U1CTS          0x00001809
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_PWM1           0x00001C04
+#define GPIO_PA7_PWM5           0x00001C05
+#define GPIO_PA7_CAN0TX         0x00001C06
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_USB0PFLT       0x00001C08
+#define GPIO_PA7_U1DCD          0x00001C09
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_PWM2           0x00010002
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_PWM3           0x00010402
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_IDX0           0x00010802
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+#define GPIO_PB2_USB0EPEN       0x00010808
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_FAULT0         0x00010C02
+#define GPIO_PB3_FAULT3         0x00010C04
+#define GPIO_PB3_USB0PFLT       0x00010C08
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_CAN0RX         0x00011005
+#define GPIO_PB4_IDX0           0x00011006
+#define GPIO_PB4_U1RX           0x00011007
+#define GPIO_PB4_EPI0S23        0x00011008
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CAN0TX         0x00011405
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+#define GPIO_PB5_EPI0S22        0x00011408
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_FAULT1         0x00011804
+#define GPIO_PB6_IDX0           0x00011805
+#define GPIO_PB6_CCP5           0x00011806
+#define GPIO_PB6_I2S0TXSCK      0x00011809
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_PHA0           0x00021002
+#define GPIO_PC4_PWM6           0x00021004
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_EPI0S2         0x00021008
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_FAULT2         0x00021404
+#define GPIO_PC5_CCP3           0x00021405
+#define GPIO_PC5_USB0EPEN       0x00021406
+#define GPIO_PC5_EPI0S3         0x00021408
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_PHB0           0x00021802
+#define GPIO_PC6_C2O            0x00021803
+#define GPIO_PC6_PWM7           0x00021804
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+#define GPIO_PC6_USB0PFLT       0x00021807
+#define GPIO_PC6_EPI0S4         0x00021808
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_PHB0           0x00021C02
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_USB0PFLT       0x00021C06
+#define GPIO_PC7_C1O            0x00021C07
+#define GPIO_PC7_EPI0S5         0x00021C08
+
+#define GPIO_PD0_PWM0           0x00030001
+#define GPIO_PD0_CAN0RX         0x00030002
+#define GPIO_PD0_IDX0           0x00030003
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+#define GPIO_PD0_I2S0RXSCK      0x00030008
+#define GPIO_PD0_U1CTS          0x00030009
+
+#define GPIO_PD1_PWM1           0x00030401
+#define GPIO_PD1_CAN0TX         0x00030402
+#define GPIO_PD1_PHA0           0x00030403
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_I2S0RXWS       0x00030408
+#define GPIO_PD1_U1DCD          0x00030409
+#define GPIO_PD1_CCP2           0x0003040A
+#define GPIO_PD1_PHB1           0x0003040B
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_PWM2           0x00030803
+#define GPIO_PD2_CCP5           0x00030804
+#define GPIO_PD2_EPI0S20        0x00030808
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_PWM3           0x00030C03
+#define GPIO_PD3_CCP0           0x00030C04
+#define GPIO_PD3_EPI0S21        0x00030C08
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+#define GPIO_PD4_I2S0RXSD       0x00031008
+#define GPIO_PD4_U1RI           0x00031009
+#define GPIO_PD4_EPI0S19        0x0003100A
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_I2S0RXMCLK     0x00031408
+#define GPIO_PD5_U2RX           0x00031409
+#define GPIO_PD5_EPI0S28        0x0003140A
+
+#define GPIO_PD6_FAULT0         0x00031801
+#define GPIO_PD6_I2S0TXSCK      0x00031808
+#define GPIO_PD6_U2TX           0x00031809
+#define GPIO_PD6_EPI0S29        0x0003180A
+
+#define GPIO_PD7_IDX0           0x00031C01
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+#define GPIO_PD7_I2S0TXWS       0x00031C08
+#define GPIO_PD7_U1DTR          0x00031C09
+#define GPIO_PD7_EPI0S30        0x00031C0A
+
+#define GPIO_PE0_PWM4           0x00040001
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+#define GPIO_PE0_EPI0S8         0x00040008
+#define GPIO_PE0_USB0PFLT       0x00040009
+
+#define GPIO_PE1_PWM5           0x00040401
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_FAULT0         0x00040403
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+#define GPIO_PE1_EPI0S9         0x00040408
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_PHB1           0x00040803
+#define GPIO_PE2_PHA0           0x00040804
+#define GPIO_PE2_CCP2           0x00040805
+#define GPIO_PE2_EPI0S24        0x00040808
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_PHA1           0x00040C03
+#define GPIO_PE3_PHB0           0x00040C04
+#define GPIO_PE3_CCP7           0x00040C05
+#define GPIO_PE3_EPI0S25        0x00040C08
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_FAULT0         0x00041004
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+#define GPIO_PE4_I2S0TXWS       0x00041009
+
+#define GPIO_PE5_CCP5           0x00041401
+#define GPIO_PE5_I2S0TXSD       0x00041409
+
+#define GPIO_PE6_PWM4           0x00041801
+#define GPIO_PE6_C1O            0x00041802
+#define GPIO_PE6_U1CTS          0x00041809
+
+#define GPIO_PE7_PWM5           0x00041C01
+#define GPIO_PE7_C2O            0x00041C02
+#define GPIO_PE7_U1DCD          0x00041C09
+
+#define GPIO_PF0_CAN1RX         0x00050001
+#define GPIO_PF0_PHB0           0x00050002
+#define GPIO_PF0_PWM0           0x00050003
+#define GPIO_PF0_I2S0TXSD       0x00050008
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_CAN1TX         0x00050401
+#define GPIO_PF1_IDX1           0x00050402
+#define GPIO_PF1_PWM1           0x00050403
+#define GPIO_PF1_I2S0TXMCLK     0x00050408
+#define GPIO_PF1_U1RTS          0x00050409
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_LED1           0x00050801
+#define GPIO_PF2_PWM4           0x00050802
+#define GPIO_PF2_PWM2           0x00050804
+#define GPIO_PF2_SSI1CLK        0x00050809
+
+#define GPIO_PF3_LED0           0x00050C01
+#define GPIO_PF3_PWM5           0x00050C02
+#define GPIO_PF3_PWM3           0x00050C04
+#define GPIO_PF3_SSI1FSS        0x00050C09
+
+#define GPIO_PF4_CCP0           0x00051001
+#define GPIO_PF4_C0O            0x00051002
+#define GPIO_PF4_FAULT0         0x00051004
+#define GPIO_PF4_EPI0S12        0x00051008
+#define GPIO_PF4_SSI1RX         0x00051009
+
+#define GPIO_PF5_CCP2           0x00051401
+#define GPIO_PF5_C1O            0x00051402
+#define GPIO_PF5_EPI0S15        0x00051408
+#define GPIO_PF5_SSI1TX         0x00051409
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_PWM0           0x00060002
+#define GPIO_PG0_I2C1SCL        0x00060003
+#define GPIO_PG0_PWM4           0x00060004
+#define GPIO_PG0_USB0EPEN       0x00060007
+#define GPIO_PG0_EPI0S13        0x00060008
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_PWM1           0x00060402
+#define GPIO_PG1_I2C1SDA        0x00060403
+#define GPIO_PG1_PWM5           0x00060404
+#define GPIO_PG1_EPI0S14        0x00060408
+
+#define GPIO_PG7_PHB1           0x00061C01
+#define GPIO_PG7_PWM7           0x00061C04
+#define GPIO_PG7_CCP5           0x00061C08
+#define GPIO_PG7_EPI0S31        0x00061C09
+
+#define GPIO_PH0_CCP6           0x00070001
+#define GPIO_PH0_PWM2           0x00070002
+#define GPIO_PH0_EPI0S6         0x00070008
+#define GPIO_PH0_PWM4           0x00070009
+
+#define GPIO_PH1_CCP7           0x00070401
+#define GPIO_PH1_PWM3           0x00070402
+#define GPIO_PH1_EPI0S7         0x00070408
+#define GPIO_PH1_PWM5           0x00070409
+
+#define GPIO_PH2_IDX1           0x00070801
+#define GPIO_PH2_C1O            0x00070802
+#define GPIO_PH2_FAULT3         0x00070804
+#define GPIO_PH2_EPI0S1         0x00070808
+
+#define GPIO_PH3_PHB0           0x00070C01
+#define GPIO_PH3_FAULT0         0x00070C02
+#define GPIO_PH3_USB0EPEN       0x00070C04
+#define GPIO_PH3_EPI0S0         0x00070C08
+
+#define GPIO_PH4_USB0PFLT       0x00071004
+#define GPIO_PH4_EPI0S10        0x00071008
+#define GPIO_PH4_SSI1CLK        0x0007100B
+
+#define GPIO_PH5_EPI0S11        0x00071408
+#define GPIO_PH5_FAULT2         0x0007140A
+#define GPIO_PH5_SSI1FSS        0x0007140B
+
+#define GPIO_PH6_EPI0S26        0x00071808
+#define GPIO_PH6_PWM4           0x0007180A
+#define GPIO_PH6_SSI1RX         0x0007180B
+
+#define GPIO_PH7_EPI0S27        0x00071C08
+#define GPIO_PH7_PWM5           0x00071C0A
+#define GPIO_PH7_SSI1TX         0x00071C0B
+
+#define GPIO_PJ0_EPI0S16        0x00080008
+#define GPIO_PJ0_PWM0           0x0008000A
+#define GPIO_PJ0_I2C1SCL        0x0008000B
+
+#define GPIO_PJ1_EPI0S17        0x00080408
+#define GPIO_PJ1_USB0PFLT       0x00080409
+#define GPIO_PJ1_PWM1           0x0008040A
+#define GPIO_PJ1_I2C1SDA        0x0008040B
+
+#define GPIO_PJ2_EPI0S18        0x00080808
+#define GPIO_PJ2_CCP0           0x00080809
+#define GPIO_PJ2_FAULT0         0x0008080A
+
+#define GPIO_PJ3_EPI0S19        0x00080C08
+#define GPIO_PJ3_U1CTS          0x00080C09
+#define GPIO_PJ3_CCP6           0x00080C0A
+
+#define GPIO_PJ4_EPI0S28        0x00081008
+#define GPIO_PJ4_U1DCD          0x00081009
+#define GPIO_PJ4_CCP4           0x0008100A
+
+#define GPIO_PJ5_EPI0S29        0x00081408
+#define GPIO_PJ5_U1DSR          0x00081409
+#define GPIO_PJ5_CCP2           0x0008140A
+
+#define GPIO_PJ6_EPI0S30        0x00081808
+#define GPIO_PJ6_U1RTS          0x00081809
+#define GPIO_PJ6_CCP1           0x0008180A
+
+#define GPIO_PJ7_U1DTR          0x00081C09
+#define GPIO_PJ7_CCP0           0x00081C0A
+
+#endif // PART_LM3S9D92
+
+//*****************************************************************************
+//
+// LM3S9D95 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S9D95
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_PWM4           0x00000804
+#define GPIO_PA2_I2S0RXSD       0x00000809
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_PWM5           0x00000C04
+#define GPIO_PA3_I2S0RXMCLK     0x00000C09
+
+#define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_PWM6           0x00001004
+#define GPIO_PA4_CAN0RX         0x00001005
+#define GPIO_PA4_I2S0TXSCK      0x00001009
+
+#define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_PWM7           0x00001404
+#define GPIO_PA5_CAN0TX         0x00001405
+#define GPIO_PA5_I2S0TXWS       0x00001409
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_PWM0           0x00001804
+#define GPIO_PA6_PWM4           0x00001805
+#define GPIO_PA6_CAN0RX         0x00001806
+#define GPIO_PA6_USB0EPEN       0x00001808
+#define GPIO_PA6_U1CTS          0x00001809
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_PWM1           0x00001C04
+#define GPIO_PA7_PWM5           0x00001C05
+#define GPIO_PA7_CAN0TX         0x00001C06
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_USB0PFLT       0x00001C08
+#define GPIO_PA7_U1DCD          0x00001C09
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_PWM2           0x00010002
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_PWM3           0x00010402
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_IDX0           0x00010802
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+#define GPIO_PB2_USB0EPEN       0x00010808
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_FAULT0         0x00010C02
+#define GPIO_PB3_FAULT3         0x00010C04
+#define GPIO_PB3_USB0PFLT       0x00010C08
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_CAN0RX         0x00011005
+#define GPIO_PB4_IDX0           0x00011006
+#define GPIO_PB4_U1RX           0x00011007
+#define GPIO_PB4_EPI0S23        0x00011008
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CAN0TX         0x00011405
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+#define GPIO_PB5_EPI0S22        0x00011408
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_FAULT1         0x00011804
+#define GPIO_PB6_IDX0           0x00011805
+#define GPIO_PB6_CCP5           0x00011806
+#define GPIO_PB6_I2S0TXSCK      0x00011809
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_PHA0           0x00021002
+#define GPIO_PC4_PWM6           0x00021004
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_EPI0S2         0x00021008
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_FAULT2         0x00021404
+#define GPIO_PC5_CCP3           0x00021405
+#define GPIO_PC5_USB0EPEN       0x00021406
+#define GPIO_PC5_EPI0S3         0x00021408
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_PHB0           0x00021802
+#define GPIO_PC6_C2O            0x00021803
+#define GPIO_PC6_PWM7           0x00021804
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+#define GPIO_PC6_USB0PFLT       0x00021807
+#define GPIO_PC6_EPI0S4         0x00021808
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_PHB0           0x00021C02
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_USB0PFLT       0x00021C06
+#define GPIO_PC7_C1O            0x00021C07
+#define GPIO_PC7_EPI0S5         0x00021C08
+
+#define GPIO_PD0_PWM0           0x00030001
+#define GPIO_PD0_CAN0RX         0x00030002
+#define GPIO_PD0_IDX0           0x00030003
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+#define GPIO_PD0_I2S0RXSCK      0x00030008
+#define GPIO_PD0_U1CTS          0x00030009
+
+#define GPIO_PD1_PWM1           0x00030401
+#define GPIO_PD1_CAN0TX         0x00030402
+#define GPIO_PD1_PHA0           0x00030403
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_I2S0RXWS       0x00030408
+#define GPIO_PD1_U1DCD          0x00030409
+#define GPIO_PD1_CCP2           0x0003040A
+#define GPIO_PD1_PHB1           0x0003040B
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_PWM2           0x00030803
+#define GPIO_PD2_CCP5           0x00030804
+#define GPIO_PD2_EPI0S20        0x00030808
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_PWM3           0x00030C03
+#define GPIO_PD3_CCP0           0x00030C04
+#define GPIO_PD3_EPI0S21        0x00030C08
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+#define GPIO_PD4_I2S0RXSD       0x00031008
+#define GPIO_PD4_U1RI           0x00031009
+#define GPIO_PD4_EPI0S19        0x0003100A
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_I2S0RXMCLK     0x00031408
+#define GPIO_PD5_U2RX           0x00031409
+#define GPIO_PD5_EPI0S28        0x0003140A
+
+#define GPIO_PD6_FAULT0         0x00031801
+#define GPIO_PD6_I2S0TXSCK      0x00031808
+#define GPIO_PD6_U2TX           0x00031809
+#define GPIO_PD6_EPI0S29        0x0003180A
+
+#define GPIO_PD7_IDX0           0x00031C01
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+#define GPIO_PD7_I2S0TXWS       0x00031C08
+#define GPIO_PD7_U1DTR          0x00031C09
+#define GPIO_PD7_EPI0S30        0x00031C0A
+
+#define GPIO_PE0_PWM4           0x00040001
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+#define GPIO_PE0_EPI0S8         0x00040008
+#define GPIO_PE0_USB0PFLT       0x00040009
+
+#define GPIO_PE1_PWM5           0x00040401
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_FAULT0         0x00040403
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+#define GPIO_PE1_EPI0S9         0x00040408
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_PHB1           0x00040803
+#define GPIO_PE2_PHA0           0x00040804
+#define GPIO_PE2_CCP2           0x00040805
+#define GPIO_PE2_EPI0S24        0x00040808
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_PHA1           0x00040C03
+#define GPIO_PE3_PHB0           0x00040C04
+#define GPIO_PE3_CCP7           0x00040C05
+#define GPIO_PE3_EPI0S25        0x00040C08
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_FAULT0         0x00041004
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+#define GPIO_PE4_I2S0TXWS       0x00041009
+
+#define GPIO_PE5_CCP5           0x00041401
+#define GPIO_PE5_I2S0TXSD       0x00041409
+
+#define GPIO_PE6_PWM4           0x00041801
+#define GPIO_PE6_C1O            0x00041802
+#define GPIO_PE6_U1CTS          0x00041809
+
+#define GPIO_PE7_PWM5           0x00041C01
+#define GPIO_PE7_C2O            0x00041C02
+#define GPIO_PE7_U1DCD          0x00041C09
+
+#define GPIO_PF0_CAN1RX         0x00050001
+#define GPIO_PF0_PHB0           0x00050002
+#define GPIO_PF0_PWM0           0x00050003
+#define GPIO_PF0_I2S0TXSD       0x00050008
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_CAN1TX         0x00050401
+#define GPIO_PF1_IDX1           0x00050402
+#define GPIO_PF1_PWM1           0x00050403
+#define GPIO_PF1_I2S0TXMCLK     0x00050408
+#define GPIO_PF1_U1RTS          0x00050409
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_LED1           0x00050801
+#define GPIO_PF2_PWM4           0x00050802
+#define GPIO_PF2_PWM2           0x00050804
+#define GPIO_PF2_SSI1CLK        0x00050809
+
+#define GPIO_PF3_LED0           0x00050C01
+#define GPIO_PF3_PWM5           0x00050C02
+#define GPIO_PF3_PWM3           0x00050C04
+#define GPIO_PF3_SSI1FSS        0x00050C09
+
+#define GPIO_PF4_CCP0           0x00051001
+#define GPIO_PF4_C0O            0x00051002
+#define GPIO_PF4_FAULT0         0x00051004
+#define GPIO_PF4_EPI0S12        0x00051008
+#define GPIO_PF4_SSI1RX         0x00051009
+
+#define GPIO_PF5_CCP2           0x00051401
+#define GPIO_PF5_C1O            0x00051402
+#define GPIO_PF5_EPI0S15        0x00051408
+#define GPIO_PF5_SSI1TX         0x00051409
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_PWM0           0x00060002
+#define GPIO_PG0_I2C1SCL        0x00060003
+#define GPIO_PG0_PWM4           0x00060004
+#define GPIO_PG0_USB0EPEN       0x00060007
+#define GPIO_PG0_EPI0S13        0x00060008
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_PWM1           0x00060402
+#define GPIO_PG1_I2C1SDA        0x00060403
+#define GPIO_PG1_PWM5           0x00060404
+#define GPIO_PG1_EPI0S14        0x00060408
+
+#define GPIO_PG7_PHB1           0x00061C01
+#define GPIO_PG7_PWM7           0x00061C04
+#define GPIO_PG7_CCP5           0x00061C08
+#define GPIO_PG7_EPI0S31        0x00061C09
+
+#define GPIO_PH0_CCP6           0x00070001
+#define GPIO_PH0_PWM2           0x00070002
+#define GPIO_PH0_EPI0S6         0x00070008
+#define GPIO_PH0_PWM4           0x00070009
+
+#define GPIO_PH1_CCP7           0x00070401
+#define GPIO_PH1_PWM3           0x00070402
+#define GPIO_PH1_EPI0S7         0x00070408
+#define GPIO_PH1_PWM5           0x00070409
+
+#define GPIO_PH2_IDX1           0x00070801
+#define GPIO_PH2_C1O            0x00070802
+#define GPIO_PH2_FAULT3         0x00070804
+#define GPIO_PH2_EPI0S1         0x00070808
+
+#define GPIO_PH3_PHB0           0x00070C01
+#define GPIO_PH3_FAULT0         0x00070C02
+#define GPIO_PH3_USB0EPEN       0x00070C04
+#define GPIO_PH3_EPI0S0         0x00070C08
+
+#define GPIO_PH4_USB0PFLT       0x00071004
+#define GPIO_PH4_EPI0S10        0x00071008
+#define GPIO_PH4_SSI1CLK        0x0007100B
+
+#define GPIO_PH5_EPI0S11        0x00071408
+#define GPIO_PH5_FAULT2         0x0007140A
+#define GPIO_PH5_SSI1FSS        0x0007140B
+
+#define GPIO_PH6_EPI0S26        0x00071808
+#define GPIO_PH6_PWM4           0x0007180A
+#define GPIO_PH6_SSI1RX         0x0007180B
+
+#define GPIO_PH7_EPI0S27        0x00071C08
+#define GPIO_PH7_PWM5           0x00071C0A
+#define GPIO_PH7_SSI1TX         0x00071C0B
+
+#define GPIO_PJ0_EPI0S16        0x00080008
+#define GPIO_PJ0_PWM0           0x0008000A
+#define GPIO_PJ0_I2C1SCL        0x0008000B
+
+#define GPIO_PJ1_EPI0S17        0x00080408
+#define GPIO_PJ1_USB0PFLT       0x00080409
+#define GPIO_PJ1_PWM1           0x0008040A
+#define GPIO_PJ1_I2C1SDA        0x0008040B
+
+#define GPIO_PJ2_EPI0S18        0x00080808
+#define GPIO_PJ2_CCP0           0x00080809
+#define GPIO_PJ2_FAULT0         0x0008080A
+
+#define GPIO_PJ3_EPI0S19        0x00080C08
+#define GPIO_PJ3_U1CTS          0x00080C09
+#define GPIO_PJ3_CCP6           0x00080C0A
+
+#define GPIO_PJ4_EPI0S28        0x00081008
+#define GPIO_PJ4_U1DCD          0x00081009
+#define GPIO_PJ4_CCP4           0x0008100A
+
+#define GPIO_PJ5_EPI0S29        0x00081408
+#define GPIO_PJ5_U1DSR          0x00081409
+#define GPIO_PJ5_CCP2           0x0008140A
+
+#define GPIO_PJ6_EPI0S30        0x00081808
+#define GPIO_PJ6_U1RTS          0x00081809
+#define GPIO_PJ6_CCP1           0x0008180A
+
+#define GPIO_PJ7_U1DTR          0x00081C09
+#define GPIO_PJ7_CCP0           0x00081C0A
+
+#endif // PART_LM3S9D95
+
+//*****************************************************************************
+//
+// LM3S9D96 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S9D96
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_PWM4           0x00000804
+#define GPIO_PA2_I2S0RXSD       0x00000809
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_PWM5           0x00000C04
+#define GPIO_PA3_I2S0RXMCLK     0x00000C09
+
+#define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_PWM6           0x00001004
+#define GPIO_PA4_CAN0RX         0x00001005
+#define GPIO_PA4_I2S0TXSCK      0x00001009
+
+#define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_PWM7           0x00001404
+#define GPIO_PA5_CAN0TX         0x00001405
+#define GPIO_PA5_I2S0TXWS       0x00001409
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_PWM0           0x00001804
+#define GPIO_PA6_PWM4           0x00001805
+#define GPIO_PA6_CAN0RX         0x00001806
+#define GPIO_PA6_USB0EPEN       0x00001808
+#define GPIO_PA6_U1CTS          0x00001809
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_PWM1           0x00001C04
+#define GPIO_PA7_PWM5           0x00001C05
+#define GPIO_PA7_CAN0TX         0x00001C06
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_USB0PFLT       0x00001C08
+#define GPIO_PA7_U1DCD          0x00001C09
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_PWM2           0x00010002
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_PWM3           0x00010402
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_IDX0           0x00010802
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+#define GPIO_PB2_USB0EPEN       0x00010808
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_FAULT0         0x00010C02
+#define GPIO_PB3_FAULT3         0x00010C04
+#define GPIO_PB3_USB0PFLT       0x00010C08
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_CAN0RX         0x00011005
+#define GPIO_PB4_IDX0           0x00011006
+#define GPIO_PB4_U1RX           0x00011007
+#define GPIO_PB4_EPI0S23        0x00011008
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CAN0TX         0x00011405
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+#define GPIO_PB5_EPI0S22        0x00011408
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_FAULT1         0x00011804
+#define GPIO_PB6_IDX0           0x00011805
+#define GPIO_PB6_CCP5           0x00011806
+#define GPIO_PB6_I2S0TXSCK      0x00011809
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_PHA0           0x00021002
+#define GPIO_PC4_PWM6           0x00021004
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_EPI0S2         0x00021008
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_FAULT2         0x00021404
+#define GPIO_PC5_CCP3           0x00021405
+#define GPIO_PC5_USB0EPEN       0x00021406
+#define GPIO_PC5_EPI0S3         0x00021408
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_PHB0           0x00021802
+#define GPIO_PC6_C2O            0x00021803
+#define GPIO_PC6_PWM7           0x00021804
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+#define GPIO_PC6_USB0PFLT       0x00021807
+#define GPIO_PC6_EPI0S4         0x00021808
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_PHB0           0x00021C02
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_USB0PFLT       0x00021C06
+#define GPIO_PC7_C1O            0x00021C07
+#define GPIO_PC7_EPI0S5         0x00021C08
+
+#define GPIO_PD0_PWM0           0x00030001
+#define GPIO_PD0_CAN0RX         0x00030002
+#define GPIO_PD0_IDX0           0x00030003
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+#define GPIO_PD0_I2S0RXSCK      0x00030008
+#define GPIO_PD0_U1CTS          0x00030009
+
+#define GPIO_PD1_PWM1           0x00030401
+#define GPIO_PD1_CAN0TX         0x00030402
+#define GPIO_PD1_PHA0           0x00030403
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_I2S0RXWS       0x00030408
+#define GPIO_PD1_U1DCD          0x00030409
+#define GPIO_PD1_CCP2           0x0003040A
+#define GPIO_PD1_PHB1           0x0003040B
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_PWM2           0x00030803
+#define GPIO_PD2_CCP5           0x00030804
+#define GPIO_PD2_EPI0S20        0x00030808
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_PWM3           0x00030C03
+#define GPIO_PD3_CCP0           0x00030C04
+#define GPIO_PD3_EPI0S21        0x00030C08
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+#define GPIO_PD4_I2S0RXSD       0x00031008
+#define GPIO_PD4_U1RI           0x00031009
+#define GPIO_PD4_EPI0S19        0x0003100A
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_I2S0RXMCLK     0x00031408
+#define GPIO_PD5_U2RX           0x00031409
+#define GPIO_PD5_EPI0S28        0x0003140A
+
+#define GPIO_PD6_FAULT0         0x00031801
+#define GPIO_PD6_I2S0TXSCK      0x00031808
+#define GPIO_PD6_U2TX           0x00031809
+#define GPIO_PD6_EPI0S29        0x0003180A
+
+#define GPIO_PD7_IDX0           0x00031C01
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+#define GPIO_PD7_I2S0TXWS       0x00031C08
+#define GPIO_PD7_U1DTR          0x00031C09
+#define GPIO_PD7_EPI0S30        0x00031C0A
+
+#define GPIO_PE0_PWM4           0x00040001
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+#define GPIO_PE0_EPI0S8         0x00040008
+#define GPIO_PE0_USB0PFLT       0x00040009
+
+#define GPIO_PE1_PWM5           0x00040401
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_FAULT0         0x00040403
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+#define GPIO_PE1_EPI0S9         0x00040408
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_PHB1           0x00040803
+#define GPIO_PE2_PHA0           0x00040804
+#define GPIO_PE2_CCP2           0x00040805
+#define GPIO_PE2_EPI0S24        0x00040808
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_PHA1           0x00040C03
+#define GPIO_PE3_PHB0           0x00040C04
+#define GPIO_PE3_CCP7           0x00040C05
+#define GPIO_PE3_EPI0S25        0x00040C08
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_FAULT0         0x00041004
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+#define GPIO_PE4_I2S0TXWS       0x00041009
+
+#define GPIO_PE5_CCP5           0x00041401
+#define GPIO_PE5_I2S0TXSD       0x00041409
+
+#define GPIO_PE6_PWM4           0x00041801
+#define GPIO_PE6_C1O            0x00041802
+#define GPIO_PE6_U1CTS          0x00041809
+
+#define GPIO_PE7_PWM5           0x00041C01
+#define GPIO_PE7_C2O            0x00041C02
+#define GPIO_PE7_U1DCD          0x00041C09
+
+#define GPIO_PF0_CAN1RX         0x00050001
+#define GPIO_PF0_PHB0           0x00050002
+#define GPIO_PF0_PWM0           0x00050003
+#define GPIO_PF0_I2S0TXSD       0x00050008
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_CAN1TX         0x00050401
+#define GPIO_PF1_IDX1           0x00050402
+#define GPIO_PF1_PWM1           0x00050403
+#define GPIO_PF1_I2S0TXMCLK     0x00050408
+#define GPIO_PF1_U1RTS          0x00050409
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_LED1           0x00050801
+#define GPIO_PF2_PWM4           0x00050802
+#define GPIO_PF2_PWM2           0x00050804
+#define GPIO_PF2_SSI1CLK        0x00050809
+
+#define GPIO_PF3_LED0           0x00050C01
+#define GPIO_PF3_PWM5           0x00050C02
+#define GPIO_PF3_PWM3           0x00050C04
+#define GPIO_PF3_SSI1FSS        0x00050C09
+
+#define GPIO_PF4_CCP0           0x00051001
+#define GPIO_PF4_C0O            0x00051002
+#define GPIO_PF4_FAULT0         0x00051004
+#define GPIO_PF4_EPI0S12        0x00051008
+#define GPIO_PF4_SSI1RX         0x00051009
+
+#define GPIO_PF5_CCP2           0x00051401
+#define GPIO_PF5_C1O            0x00051402
+#define GPIO_PF5_EPI0S15        0x00051408
+#define GPIO_PF5_SSI1TX         0x00051409
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_PWM0           0x00060002
+#define GPIO_PG0_I2C1SCL        0x00060003
+#define GPIO_PG0_PWM4           0x00060004
+#define GPIO_PG0_USB0EPEN       0x00060007
+#define GPIO_PG0_EPI0S13        0x00060008
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_PWM1           0x00060402
+#define GPIO_PG1_I2C1SDA        0x00060403
+#define GPIO_PG1_PWM5           0x00060404
+#define GPIO_PG1_EPI0S14        0x00060408
+
+#define GPIO_PG7_PHB1           0x00061C01
+#define GPIO_PG7_PWM7           0x00061C04
+#define GPIO_PG7_CCP5           0x00061C08
+#define GPIO_PG7_EPI0S31        0x00061C09
+
+#define GPIO_PH0_CCP6           0x00070001
+#define GPIO_PH0_PWM2           0x00070002
+#define GPIO_PH0_EPI0S6         0x00070008
+#define GPIO_PH0_PWM4           0x00070009
+
+#define GPIO_PH1_CCP7           0x00070401
+#define GPIO_PH1_PWM3           0x00070402
+#define GPIO_PH1_EPI0S7         0x00070408
+#define GPIO_PH1_PWM5           0x00070409
+
+#define GPIO_PH2_IDX1           0x00070801
+#define GPIO_PH2_C1O            0x00070802
+#define GPIO_PH2_FAULT3         0x00070804
+#define GPIO_PH2_EPI0S1         0x00070808
+
+#define GPIO_PH3_PHB0           0x00070C01
+#define GPIO_PH3_FAULT0         0x00070C02
+#define GPIO_PH3_USB0EPEN       0x00070C04
+#define GPIO_PH3_EPI0S0         0x00070C08
+
+#define GPIO_PH4_USB0PFLT       0x00071004
+#define GPIO_PH4_EPI0S10        0x00071008
+#define GPIO_PH4_SSI1CLK        0x0007100B
+
+#define GPIO_PH5_EPI0S11        0x00071408
+#define GPIO_PH5_FAULT2         0x0007140A
+#define GPIO_PH5_SSI1FSS        0x0007140B
+
+#define GPIO_PH6_EPI0S26        0x00071808
+#define GPIO_PH6_PWM4           0x0007180A
+#define GPIO_PH6_SSI1RX         0x0007180B
+
+#define GPIO_PH7_EPI0S27        0x00071C08
+#define GPIO_PH7_PWM5           0x00071C0A
+#define GPIO_PH7_SSI1TX         0x00071C0B
+
+#define GPIO_PJ0_EPI0S16        0x00080008
+#define GPIO_PJ0_PWM0           0x0008000A
+#define GPIO_PJ0_I2C1SCL        0x0008000B
+
+#define GPIO_PJ1_EPI0S17        0x00080408
+#define GPIO_PJ1_USB0PFLT       0x00080409
+#define GPIO_PJ1_PWM1           0x0008040A
+#define GPIO_PJ1_I2C1SDA        0x0008040B
+
+#define GPIO_PJ2_EPI0S18        0x00080808
+#define GPIO_PJ2_CCP0           0x00080809
+#define GPIO_PJ2_FAULT0         0x0008080A
+
+#define GPIO_PJ3_EPI0S19        0x00080C08
+#define GPIO_PJ3_U1CTS          0x00080C09
+#define GPIO_PJ3_CCP6           0x00080C0A
+
+#define GPIO_PJ4_EPI0S28        0x00081008
+#define GPIO_PJ4_U1DCD          0x00081009
+#define GPIO_PJ4_CCP4           0x0008100A
+
+#define GPIO_PJ5_EPI0S29        0x00081408
+#define GPIO_PJ5_U1DSR          0x00081409
+#define GPIO_PJ5_CCP2           0x0008140A
+
+#define GPIO_PJ6_EPI0S30        0x00081808
+#define GPIO_PJ6_U1RTS          0x00081809
+#define GPIO_PJ6_CCP1           0x0008180A
+
+#define GPIO_PJ7_U1DTR          0x00081C09
+#define GPIO_PJ7_CCP0           0x00081C0A
+
+#endif // PART_LM3S9D96
+
+//*****************************************************************************
+//
+// LM3S9DN5 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S9DN5
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_TXD2           0x00000803
+#define GPIO_PA2_PWM4           0x00000804
+#define GPIO_PA2_I2S0RXSD       0x00000809
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_TXD1           0x00000C03
+#define GPIO_PA3_PWM5           0x00000C04
+#define GPIO_PA3_I2S0RXMCLK     0x00000C09
+
+#define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_TXD0           0x00001003
+#define GPIO_PA4_PWM6           0x00001004
+#define GPIO_PA4_CAN0RX         0x00001005
+#define GPIO_PA4_I2S0TXSCK      0x00001009
+
+#define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_RXDV           0x00001403
+#define GPIO_PA5_PWM7           0x00001404
+#define GPIO_PA5_CAN0TX         0x00001405
+#define GPIO_PA5_I2S0TXWS       0x00001409
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_RXCK           0x00001803
+#define GPIO_PA6_PWM0           0x00001804
+#define GPIO_PA6_PWM4           0x00001805
+#define GPIO_PA6_CAN0RX         0x00001806
+#define GPIO_PA6_USB0EPEN       0x00001808
+#define GPIO_PA6_U1CTS          0x00001809
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_RXER           0x00001C03
+#define GPIO_PA7_PWM1           0x00001C04
+#define GPIO_PA7_PWM5           0x00001C05
+#define GPIO_PA7_CAN0TX         0x00001C06
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_USB0PFLT       0x00001C08
+#define GPIO_PA7_U1DCD          0x00001C09
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_PWM2           0x00010002
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_PWM3           0x00010402
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_IDX0           0x00010802
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+#define GPIO_PB2_USB0EPEN       0x00010808
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_FAULT0         0x00010C02
+#define GPIO_PB3_FAULT3         0x00010C04
+#define GPIO_PB3_USB0PFLT       0x00010C08
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_CAN0RX         0x00011005
+#define GPIO_PB4_IDX0           0x00011006
+#define GPIO_PB4_U1RX           0x00011007
+#define GPIO_PB4_EPI0S23        0x00011008
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CAN0TX         0x00011405
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+#define GPIO_PB5_EPI0S22        0x00011408
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_FAULT1         0x00011804
+#define GPIO_PB6_IDX0           0x00011805
+#define GPIO_PB6_CCP5           0x00011806
+#define GPIO_PB6_I2S0TXSCK      0x00011809
+
+#define GPIO_PB7_NMI            0x00011C04
+#define GPIO_PB7_RXD1           0x00011C07
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_PHA0           0x00021002
+#define GPIO_PC4_TXD3           0x00021003
+#define GPIO_PC4_PWM6           0x00021004
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_EPI0S2         0x00021008
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_FAULT2         0x00021404
+#define GPIO_PC5_CCP3           0x00021405
+#define GPIO_PC5_USB0EPEN       0x00021406
+#define GPIO_PC5_EPI0S3         0x00021408
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_PHB0           0x00021802
+#define GPIO_PC6_C2O            0x00021803
+#define GPIO_PC6_PWM7           0x00021804
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+#define GPIO_PC6_USB0PFLT       0x00021807
+#define GPIO_PC6_EPI0S4         0x00021808
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_PHB0           0x00021C02
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_USB0PFLT       0x00021C06
+#define GPIO_PC7_C1O            0x00021C07
+#define GPIO_PC7_EPI0S5         0x00021C08
+
+#define GPIO_PD0_PWM0           0x00030001
+#define GPIO_PD0_CAN0RX         0x00030002
+#define GPIO_PD0_IDX0           0x00030003
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+#define GPIO_PD0_RXDV           0x00030007
+#define GPIO_PD0_I2S0RXSCK      0x00030008
+#define GPIO_PD0_U1CTS          0x00030009
+
+#define GPIO_PD1_PWM1           0x00030401
+#define GPIO_PD1_CAN0TX         0x00030402
+#define GPIO_PD1_PHA0           0x00030403
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_TXER           0x00030407
+#define GPIO_PD1_I2S0RXWS       0x00030408
+#define GPIO_PD1_U1DCD          0x00030409
+#define GPIO_PD1_CCP2           0x0003040A
+#define GPIO_PD1_PHB1           0x0003040B
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_PWM2           0x00030803
+#define GPIO_PD2_CCP5           0x00030804
+#define GPIO_PD2_EPI0S20        0x00030808
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_PWM3           0x00030C03
+#define GPIO_PD3_CCP0           0x00030C04
+#define GPIO_PD3_EPI0S21        0x00030C08
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+#define GPIO_PD4_TXD3           0x00031004
+#define GPIO_PD4_I2S0RXSD       0x00031008
+#define GPIO_PD4_U1RI           0x00031009
+#define GPIO_PD4_EPI0S19        0x0003100A
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_TXD2           0x00031404
+#define GPIO_PD5_I2S0RXMCLK     0x00031408
+#define GPIO_PD5_U2RX           0x00031409
+#define GPIO_PD5_EPI0S28        0x0003140A
+
+#define GPIO_PD6_FAULT0         0x00031801
+#define GPIO_PD6_TXD1           0x00031804
+#define GPIO_PD6_I2S0TXSCK      0x00031808
+#define GPIO_PD6_U2TX           0x00031809
+#define GPIO_PD6_EPI0S29        0x0003180A
+
+#define GPIO_PD7_IDX0           0x00031C01
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+#define GPIO_PD7_TXD0           0x00031C04
+#define GPIO_PD7_I2S0TXWS       0x00031C08
+#define GPIO_PD7_U1DTR          0x00031C09
+#define GPIO_PD7_EPI0S30        0x00031C0A
+
+#define GPIO_PE0_PWM4           0x00040001
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+#define GPIO_PE0_EPI0S8         0x00040008
+#define GPIO_PE0_USB0PFLT       0x00040009
+
+#define GPIO_PE1_PWM5           0x00040401
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_FAULT0         0x00040403
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+#define GPIO_PE1_EPI0S9         0x00040408
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_PHB1           0x00040803
+#define GPIO_PE2_PHA0           0x00040804
+#define GPIO_PE2_CCP2           0x00040805
+#define GPIO_PE2_EPI0S24        0x00040808
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_PHA1           0x00040C03
+#define GPIO_PE3_PHB0           0x00040C04
+#define GPIO_PE3_CCP7           0x00040C05
+#define GPIO_PE3_EPI0S25        0x00040C08
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_FAULT0         0x00041004
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+#define GPIO_PE4_RXD0           0x00041007
+#define GPIO_PE4_I2S0TXWS       0x00041009
+
+#define GPIO_PE5_CCP5           0x00041401
+#define GPIO_PE5_I2S0TXSD       0x00041409
+
+#define GPIO_PE6_PWM4           0x00041801
+#define GPIO_PE6_C1O            0x00041802
+#define GPIO_PE6_U1CTS          0x00041809
+
+#define GPIO_PE7_PWM5           0x00041C01
+#define GPIO_PE7_C2O            0x00041C02
+#define GPIO_PE7_U1DCD          0x00041C09
+
+#define GPIO_PF0_CAN1RX         0x00050001
+#define GPIO_PF0_PHB0           0x00050002
+#define GPIO_PF0_PWM0           0x00050003
+#define GPIO_PF0_RXCK           0x00050004
+#define GPIO_PF0_I2S0TXSD       0x00050008
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_CAN1TX         0x00050401
+#define GPIO_PF1_IDX1           0x00050402
+#define GPIO_PF1_PWM1           0x00050403
+#define GPIO_PF1_RXER           0x00050404
+#define GPIO_PF1_I2S0TXMCLK     0x00050408
+#define GPIO_PF1_U1RTS          0x00050409
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_PWM4           0x00050802
+#define GPIO_PF2_PHYINT         0x00050803
+#define GPIO_PF2_PWM2           0x00050804
+#define GPIO_PF2_SSI1CLK        0x00050809
+
+#define GPIO_PF3_PWM5           0x00050C02
+#define GPIO_PF3_MDC            0x00050C03
+#define GPIO_PF3_PWM3           0x00050C04
+#define GPIO_PF3_SSI1FSS        0x00050C09
+
+#define GPIO_PF4_CCP0           0x00051001
+#define GPIO_PF4_C0O            0x00051002
+#define GPIO_PF4_MDIO           0x00051003
+#define GPIO_PF4_FAULT0         0x00051004
+#define GPIO_PF4_EPI0S12        0x00051008
+#define GPIO_PF4_SSI1RX         0x00051009
+
+#define GPIO_PF5_CCP2           0x00051401
+#define GPIO_PF5_C1O            0x00051402
+#define GPIO_PF5_RXD3           0x00051403
+#define GPIO_PF5_EPI0S15        0x00051408
+#define GPIO_PF5_SSI1TX         0x00051409
+
+#define GPIO_PF6_CCP1           0x00051801
+#define GPIO_PF6_C2O            0x00051802
+#define GPIO_PF6_RXD2           0x00051803
+#define GPIO_PF6_PHA0           0x00051804
+#define GPIO_PF6_I2S0TXMCLK     0x00051809
+#define GPIO_PF6_U1RTS          0x0005180A
+
+#define GPIO_PF7_CCP4           0x00051C01
+#define GPIO_PF7_RXD1           0x00051C03
+#define GPIO_PF7_PHB0           0x00051C04
+#define GPIO_PF7_EPI0S12        0x00051C08
+#define GPIO_PF7_FAULT1         0x00051C09
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_PWM0           0x00060002
+#define GPIO_PG0_I2C1SCL        0x00060003
+#define GPIO_PG0_PWM4           0x00060004
+#define GPIO_PG0_USB0EPEN       0x00060007
+#define GPIO_PG0_EPI0S13        0x00060008
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_PWM1           0x00060402
+#define GPIO_PG1_I2C1SDA        0x00060403
+#define GPIO_PG1_PWM5           0x00060404
+#define GPIO_PG1_EPI0S14        0x00060408
+
+#define GPIO_PG2_PWM0           0x00060801
+#define GPIO_PG2_COL            0x00060803
+#define GPIO_PG2_FAULT0         0x00060804
+#define GPIO_PG2_IDX1           0x00060808
+#define GPIO_PG2_I2S0RXSD       0x00060809
+
+#define GPIO_PG3_PWM1           0x00060C01
+#define GPIO_PG3_CRS            0x00060C03
+#define GPIO_PG3_FAULT2         0x00060C04
+#define GPIO_PG3_FAULT0         0x00060C08
+#define GPIO_PG3_I2S0RXMCLK     0x00060C09
+
+#define GPIO_PG4_CCP3           0x00061001
+#define GPIO_PG4_RXD0           0x00061003
+#define GPIO_PG4_FAULT1         0x00061004
+#define GPIO_PG4_EPI0S15        0x00061008
+#define GPIO_PG4_PWM6           0x00061009
+#define GPIO_PG4_U1RI           0x0006100A
+
+#define GPIO_PG5_CCP5           0x00061401
+#define GPIO_PG5_TXEN           0x00061403
+#define GPIO_PG5_IDX0           0x00061404
+#define GPIO_PG5_FAULT1         0x00061405
+#define GPIO_PG5_PWM7           0x00061408
+#define GPIO_PG5_I2S0RXSCK      0x00061409
+#define GPIO_PG5_U1DTR          0x0006140A
+
+#define GPIO_PG6_PHA1           0x00061801
+#define GPIO_PG6_TXCK           0x00061803
+#define GPIO_PG6_PWM6           0x00061804
+#define GPIO_PG6_FAULT1         0x00061808
+#define GPIO_PG6_I2S0RXWS       0x00061809
+#define GPIO_PG6_U1RI           0x0006180A
+
+#define GPIO_PG7_PHB1           0x00061C01
+#define GPIO_PG7_TXER           0x00061C03
+#define GPIO_PG7_PWM7           0x00061C04
+#define GPIO_PG7_CCP5           0x00061C08
+#define GPIO_PG7_EPI0S31        0x00061C09
+
+#define GPIO_PH0_CCP6           0x00070001
+#define GPIO_PH0_PWM2           0x00070002
+#define GPIO_PH0_EPI0S6         0x00070008
+#define GPIO_PH0_PWM4           0x00070009
+
+#define GPIO_PH1_CCP7           0x00070401
+#define GPIO_PH1_PWM3           0x00070402
+#define GPIO_PH1_EPI0S7         0x00070408
+#define GPIO_PH1_PWM5           0x00070409
+
+#define GPIO_PH2_IDX1           0x00070801
+#define GPIO_PH2_C1O            0x00070802
+#define GPIO_PH2_FAULT3         0x00070804
+#define GPIO_PH2_EPI0S1         0x00070808
+#define GPIO_PH2_TXD3           0x00070809
+
+#define GPIO_PH3_PHB0           0x00070C01
+#define GPIO_PH3_FAULT0         0x00070C02
+#define GPIO_PH3_USB0EPEN       0x00070C04
+#define GPIO_PH3_EPI0S0         0x00070C08
+#define GPIO_PH3_TXD2           0x00070C09
+
+#define GPIO_PH4_USB0PFLT       0x00071004
+#define GPIO_PH4_EPI0S10        0x00071008
+#define GPIO_PH4_TXD1           0x00071009
+#define GPIO_PH4_SSI1CLK        0x0007100B
+
+#define GPIO_PH5_EPI0S11        0x00071408
+#define GPIO_PH5_TXD0           0x00071409
+#define GPIO_PH5_FAULT2         0x0007140A
+#define GPIO_PH5_SSI1FSS        0x0007140B
+
+#define GPIO_PH6_EPI0S26        0x00071808
+#define GPIO_PH6_RXDV           0x00071809
+#define GPIO_PH6_PWM4           0x0007180A
+#define GPIO_PH6_SSI1RX         0x0007180B
+
+#define GPIO_PH7_RXCK           0x00071C03
+#define GPIO_PH7_EPI0S27        0x00071C08
+#define GPIO_PH7_PWM5           0x00071C0A
+#define GPIO_PH7_SSI1TX         0x00071C0B
+
+#define GPIO_PJ0_RXER           0x00080003
+#define GPIO_PJ0_EPI0S16        0x00080008
+#define GPIO_PJ0_PWM0           0x0008000A
+#define GPIO_PJ0_I2C1SCL        0x0008000B
+
+#define GPIO_PJ1_EPI0S17        0x00080408
+#define GPIO_PJ1_USB0PFLT       0x00080409
+#define GPIO_PJ1_PWM1           0x0008040A
+#define GPIO_PJ1_I2C1SDA        0x0008040B
+
+#define GPIO_PJ2_EPI0S18        0x00080808
+#define GPIO_PJ2_CCP0           0x00080809
+#define GPIO_PJ2_FAULT0         0x0008080A
+
+#define GPIO_PJ3_EPI0S19        0x00080C08
+#define GPIO_PJ3_U1CTS          0x00080C09
+#define GPIO_PJ3_CCP6           0x00080C0A
+
+#define GPIO_PJ4_EPI0S28        0x00081008
+#define GPIO_PJ4_U1DCD          0x00081009
+#define GPIO_PJ4_CCP4           0x0008100A
+
+#define GPIO_PJ5_EPI0S29        0x00081408
+#define GPIO_PJ5_U1DSR          0x00081409
+#define GPIO_PJ5_CCP2           0x0008140A
+
+#define GPIO_PJ6_EPI0S30        0x00081808
+#define GPIO_PJ6_U1RTS          0x00081809
+#define GPIO_PJ6_CCP1           0x0008180A
+
+#define GPIO_PJ7_U1DTR          0x00081C09
+#define GPIO_PJ7_CCP0           0x00081C0A
+
+#endif // PART_LM3S9DN5
+
+//*****************************************************************************
+//
+// LM3S9DN6 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S9DN6
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_TXD2           0x00000803
+#define GPIO_PA2_PWM4           0x00000804
+#define GPIO_PA2_I2S0RXSD       0x00000809
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_TXD1           0x00000C03
+#define GPIO_PA3_PWM5           0x00000C04
+#define GPIO_PA3_I2S0RXMCLK     0x00000C09
+
+#define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_TXD0           0x00001003
+#define GPIO_PA4_PWM6           0x00001004
+#define GPIO_PA4_CAN0RX         0x00001005
+#define GPIO_PA4_I2S0TXSCK      0x00001009
+
+#define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_RXDV           0x00001403
+#define GPIO_PA5_PWM7           0x00001404
+#define GPIO_PA5_CAN0TX         0x00001405
+#define GPIO_PA5_I2S0TXWS       0x00001409
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_RXCK           0x00001803
+#define GPIO_PA6_PWM0           0x00001804
+#define GPIO_PA6_PWM4           0x00001805
+#define GPIO_PA6_CAN0RX         0x00001806
+#define GPIO_PA6_USB0EPEN       0x00001808
+#define GPIO_PA6_U1CTS          0x00001809
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_RXER           0x00001C03
+#define GPIO_PA7_PWM1           0x00001C04
+#define GPIO_PA7_PWM5           0x00001C05
+#define GPIO_PA7_CAN0TX         0x00001C06
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_USB0PFLT       0x00001C08
+#define GPIO_PA7_U1DCD          0x00001C09
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_PWM2           0x00010002
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_PWM3           0x00010402
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_IDX0           0x00010802
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+#define GPIO_PB2_USB0EPEN       0x00010808
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_FAULT0         0x00010C02
+#define GPIO_PB3_FAULT3         0x00010C04
+#define GPIO_PB3_USB0PFLT       0x00010C08
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_CAN0RX         0x00011005
+#define GPIO_PB4_IDX0           0x00011006
+#define GPIO_PB4_U1RX           0x00011007
+#define GPIO_PB4_EPI0S23        0x00011008
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CAN0TX         0x00011405
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+#define GPIO_PB5_EPI0S22        0x00011408
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_FAULT1         0x00011804
+#define GPIO_PB6_IDX0           0x00011805
+#define GPIO_PB6_CCP5           0x00011806
+#define GPIO_PB6_I2S0TXSCK      0x00011809
+
+#define GPIO_PB7_NMI            0x00011C04
+#define GPIO_PB7_RXD1           0x00011C07
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_PHA0           0x00021002
+#define GPIO_PC4_TXD3           0x00021003
+#define GPIO_PC4_PWM6           0x00021004
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_EPI0S2         0x00021008
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_FAULT2         0x00021404
+#define GPIO_PC5_CCP3           0x00021405
+#define GPIO_PC5_USB0EPEN       0x00021406
+#define GPIO_PC5_EPI0S3         0x00021408
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_PHB0           0x00021802
+#define GPIO_PC6_C2O            0x00021803
+#define GPIO_PC6_PWM7           0x00021804
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+#define GPIO_PC6_USB0PFLT       0x00021807
+#define GPIO_PC6_EPI0S4         0x00021808
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_PHB0           0x00021C02
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_USB0PFLT       0x00021C06
+#define GPIO_PC7_C1O            0x00021C07
+#define GPIO_PC7_EPI0S5         0x00021C08
+
+#define GPIO_PD0_PWM0           0x00030001
+#define GPIO_PD0_CAN0RX         0x00030002
+#define GPIO_PD0_IDX0           0x00030003
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+#define GPIO_PD0_RXDV           0x00030007
+#define GPIO_PD0_I2S0RXSCK      0x00030008
+#define GPIO_PD0_U1CTS          0x00030009
+
+#define GPIO_PD1_PWM1           0x00030401
+#define GPIO_PD1_CAN0TX         0x00030402
+#define GPIO_PD1_PHA0           0x00030403
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_TXER           0x00030407
+#define GPIO_PD1_I2S0RXWS       0x00030408
+#define GPIO_PD1_U1DCD          0x00030409
+#define GPIO_PD1_CCP2           0x0003040A
+#define GPIO_PD1_PHB1           0x0003040B
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_PWM2           0x00030803
+#define GPIO_PD2_CCP5           0x00030804
+#define GPIO_PD2_EPI0S20        0x00030808
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_PWM3           0x00030C03
+#define GPIO_PD3_CCP0           0x00030C04
+#define GPIO_PD3_EPI0S21        0x00030C08
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+#define GPIO_PD4_TXD3           0x00031004
+#define GPIO_PD4_I2S0RXSD       0x00031008
+#define GPIO_PD4_U1RI           0x00031009
+#define GPIO_PD4_EPI0S19        0x0003100A
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_TXD2           0x00031404
+#define GPIO_PD5_I2S0RXMCLK     0x00031408
+#define GPIO_PD5_U2RX           0x00031409
+#define GPIO_PD5_EPI0S28        0x0003140A
+
+#define GPIO_PD6_FAULT0         0x00031801
+#define GPIO_PD6_TXD1           0x00031804
+#define GPIO_PD6_I2S0TXSCK      0x00031808
+#define GPIO_PD6_U2TX           0x00031809
+#define GPIO_PD6_EPI0S29        0x0003180A
+
+#define GPIO_PD7_IDX0           0x00031C01
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+#define GPIO_PD7_TXD0           0x00031C04
+#define GPIO_PD7_I2S0TXWS       0x00031C08
+#define GPIO_PD7_U1DTR          0x00031C09
+#define GPIO_PD7_EPI0S30        0x00031C0A
+
+#define GPIO_PE0_PWM4           0x00040001
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+#define GPIO_PE0_EPI0S8         0x00040008
+#define GPIO_PE0_USB0PFLT       0x00040009
+
+#define GPIO_PE1_PWM5           0x00040401
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_FAULT0         0x00040403
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+#define GPIO_PE1_EPI0S9         0x00040408
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_PHB1           0x00040803
+#define GPIO_PE2_PHA0           0x00040804
+#define GPIO_PE2_CCP2           0x00040805
+#define GPIO_PE2_EPI0S24        0x00040808
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_PHA1           0x00040C03
+#define GPIO_PE3_PHB0           0x00040C04
+#define GPIO_PE3_CCP7           0x00040C05
+#define GPIO_PE3_EPI0S25        0x00040C08
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_FAULT0         0x00041004
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+#define GPIO_PE4_RXD0           0x00041007
+#define GPIO_PE4_I2S0TXWS       0x00041009
+
+#define GPIO_PE5_CCP5           0x00041401
+#define GPIO_PE5_I2S0TXSD       0x00041409
+
+#define GPIO_PE6_PWM4           0x00041801
+#define GPIO_PE6_C1O            0x00041802
+#define GPIO_PE6_U1CTS          0x00041809
+
+#define GPIO_PE7_PWM5           0x00041C01
+#define GPIO_PE7_C2O            0x00041C02
+#define GPIO_PE7_U1DCD          0x00041C09
+
+#define GPIO_PF0_CAN1RX         0x00050001
+#define GPIO_PF0_PHB0           0x00050002
+#define GPIO_PF0_PWM0           0x00050003
+#define GPIO_PF0_RXCK           0x00050004
+#define GPIO_PF0_I2S0TXSD       0x00050008
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_CAN1TX         0x00050401
+#define GPIO_PF1_IDX1           0x00050402
+#define GPIO_PF1_PWM1           0x00050403
+#define GPIO_PF1_RXER           0x00050404
+#define GPIO_PF1_I2S0TXMCLK     0x00050408
+#define GPIO_PF1_U1RTS          0x00050409
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_PWM4           0x00050802
+#define GPIO_PF2_PHYINT         0x00050803
+#define GPIO_PF2_PWM2           0x00050804
+#define GPIO_PF2_SSI1CLK        0x00050809
+
+#define GPIO_PF3_PWM5           0x00050C02
+#define GPIO_PF3_MDC            0x00050C03
+#define GPIO_PF3_PWM3           0x00050C04
+#define GPIO_PF3_SSI1FSS        0x00050C09
+
+#define GPIO_PF4_CCP0           0x00051001
+#define GPIO_PF4_C0O            0x00051002
+#define GPIO_PF4_MDIO           0x00051003
+#define GPIO_PF4_FAULT0         0x00051004
+#define GPIO_PF4_EPI0S12        0x00051008
+#define GPIO_PF4_SSI1RX         0x00051009
+
+#define GPIO_PF5_CCP2           0x00051401
+#define GPIO_PF5_C1O            0x00051402
+#define GPIO_PF5_RXD3           0x00051403
+#define GPIO_PF5_EPI0S15        0x00051408
+#define GPIO_PF5_SSI1TX         0x00051409
+
+#define GPIO_PF6_CCP1           0x00051801
+#define GPIO_PF6_C2O            0x00051802
+#define GPIO_PF6_RXD2           0x00051803
+#define GPIO_PF6_PHA0           0x00051804
+#define GPIO_PF6_I2S0TXMCLK     0x00051809
+#define GPIO_PF6_U1RTS          0x0005180A
+
+#define GPIO_PF7_CCP4           0x00051C01
+#define GPIO_PF7_RXD1           0x00051C03
+#define GPIO_PF7_PHB0           0x00051C04
+#define GPIO_PF7_EPI0S12        0x00051C08
+#define GPIO_PF7_FAULT1         0x00051C09
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_PWM0           0x00060002
+#define GPIO_PG0_I2C1SCL        0x00060003
+#define GPIO_PG0_PWM4           0x00060004
+#define GPIO_PG0_USB0EPEN       0x00060007
+#define GPIO_PG0_EPI0S13        0x00060008
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_PWM1           0x00060402
+#define GPIO_PG1_I2C1SDA        0x00060403
+#define GPIO_PG1_PWM5           0x00060404
+#define GPIO_PG1_EPI0S14        0x00060408
+
+#define GPIO_PG2_PWM0           0x00060801
+#define GPIO_PG2_COL            0x00060803
+#define GPIO_PG2_FAULT0         0x00060804
+#define GPIO_PG2_IDX1           0x00060808
+#define GPIO_PG2_I2S0RXSD       0x00060809
+
+#define GPIO_PG3_PWM1           0x00060C01
+#define GPIO_PG3_CRS            0x00060C03
+#define GPIO_PG3_FAULT2         0x00060C04
+#define GPIO_PG3_FAULT0         0x00060C08
+#define GPIO_PG3_I2S0RXMCLK     0x00060C09
+
+#define GPIO_PG4_CCP3           0x00061001
+#define GPIO_PG4_RXD0           0x00061003
+#define GPIO_PG4_FAULT1         0x00061004
+#define GPIO_PG4_EPI0S15        0x00061008
+#define GPIO_PG4_PWM6           0x00061009
+#define GPIO_PG4_U1RI           0x0006100A
+
+#define GPIO_PG5_CCP5           0x00061401
+#define GPIO_PG5_TXEN           0x00061403
+#define GPIO_PG5_IDX0           0x00061404
+#define GPIO_PG5_FAULT1         0x00061405
+#define GPIO_PG5_PWM7           0x00061408
+#define GPIO_PG5_I2S0RXSCK      0x00061409
+#define GPIO_PG5_U1DTR          0x0006140A
+
+#define GPIO_PG6_PHA1           0x00061801
+#define GPIO_PG6_TXCK           0x00061803
+#define GPIO_PG6_PWM6           0x00061804
+#define GPIO_PG6_FAULT1         0x00061808
+#define GPIO_PG6_I2S0RXWS       0x00061809
+#define GPIO_PG6_U1RI           0x0006180A
+
+#define GPIO_PG7_PHB1           0x00061C01
+#define GPIO_PG7_TXER           0x00061C03
+#define GPIO_PG7_PWM7           0x00061C04
+#define GPIO_PG7_CCP5           0x00061C08
+#define GPIO_PG7_EPI0S31        0x00061C09
+
+#define GPIO_PH0_CCP6           0x00070001
+#define GPIO_PH0_PWM2           0x00070002
+#define GPIO_PH0_EPI0S6         0x00070008
+#define GPIO_PH0_PWM4           0x00070009
+
+#define GPIO_PH1_CCP7           0x00070401
+#define GPIO_PH1_PWM3           0x00070402
+#define GPIO_PH1_EPI0S7         0x00070408
+#define GPIO_PH1_PWM5           0x00070409
+
+#define GPIO_PH2_IDX1           0x00070801
+#define GPIO_PH2_C1O            0x00070802
+#define GPIO_PH2_FAULT3         0x00070804
+#define GPIO_PH2_EPI0S1         0x00070808
+#define GPIO_PH2_TXD3           0x00070809
+
+#define GPIO_PH3_PHB0           0x00070C01
+#define GPIO_PH3_FAULT0         0x00070C02
+#define GPIO_PH3_USB0EPEN       0x00070C04
+#define GPIO_PH3_EPI0S0         0x00070C08
+#define GPIO_PH3_TXD2           0x00070C09
+
+#define GPIO_PH4_USB0PFLT       0x00071004
+#define GPIO_PH4_EPI0S10        0x00071008
+#define GPIO_PH4_TXD1           0x00071009
+#define GPIO_PH4_SSI1CLK        0x0007100B
+
+#define GPIO_PH5_EPI0S11        0x00071408
+#define GPIO_PH5_TXD0           0x00071409
+#define GPIO_PH5_FAULT2         0x0007140A
+#define GPIO_PH5_SSI1FSS        0x0007140B
+
+#define GPIO_PH6_EPI0S26        0x00071808
+#define GPIO_PH6_RXDV           0x00071809
+#define GPIO_PH6_PWM4           0x0007180A
+#define GPIO_PH6_SSI1RX         0x0007180B
+
+#define GPIO_PH7_RXCK           0x00071C03
+#define GPIO_PH7_EPI0S27        0x00071C08
+#define GPIO_PH7_PWM5           0x00071C0A
+#define GPIO_PH7_SSI1TX         0x00071C0B
+
+#define GPIO_PJ0_RXER           0x00080003
+#define GPIO_PJ0_EPI0S16        0x00080008
+#define GPIO_PJ0_PWM0           0x0008000A
+#define GPIO_PJ0_I2C1SCL        0x0008000B
+
+#define GPIO_PJ1_EPI0S17        0x00080408
+#define GPIO_PJ1_USB0PFLT       0x00080409
+#define GPIO_PJ1_PWM1           0x0008040A
+#define GPIO_PJ1_I2C1SDA        0x0008040B
+
+#define GPIO_PJ2_EPI0S18        0x00080808
+#define GPIO_PJ2_CCP0           0x00080809
+#define GPIO_PJ2_FAULT0         0x0008080A
+
+#define GPIO_PJ3_EPI0S19        0x00080C08
+#define GPIO_PJ3_U1CTS          0x00080C09
+#define GPIO_PJ3_CCP6           0x00080C0A
+
+#define GPIO_PJ4_EPI0S28        0x00081008
+#define GPIO_PJ4_U1DCD          0x00081009
+#define GPIO_PJ4_CCP4           0x0008100A
+
+#define GPIO_PJ5_EPI0S29        0x00081408
+#define GPIO_PJ5_U1DSR          0x00081409
+#define GPIO_PJ5_CCP2           0x0008140A
+
+#define GPIO_PJ6_EPI0S30        0x00081808
+#define GPIO_PJ6_U1RTS          0x00081809
+#define GPIO_PJ6_CCP1           0x0008180A
+
+#define GPIO_PJ7_U1DTR          0x00081C09
+#define GPIO_PJ7_CCP0           0x00081C0A
+
+#endif // PART_LM3S9DN6
+
+//*****************************************************************************
+//
+// LM3S9G97 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S9G97
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_PWM4           0x00000804
+#define GPIO_PA2_I2S0RXSD       0x00000809
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_PWM5           0x00000C04
+#define GPIO_PA3_I2S0RXMCLK     0x00000C09
+
+#define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_CAN0RX         0x00001005
+#define GPIO_PA4_I2S0TXSCK      0x00001009
+
+#define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_CAN0TX         0x00001405
+#define GPIO_PA5_I2S0TXWS       0x00001409
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_PWM0           0x00001804
+#define GPIO_PA6_PWM4           0x00001805
+#define GPIO_PA6_CAN0RX         0x00001806
+#define GPIO_PA6_USB0EPEN       0x00001808
+#define GPIO_PA6_U1CTS          0x00001809
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_PWM1           0x00001C04
+#define GPIO_PA7_PWM5           0x00001C05
+#define GPIO_PA7_CAN0TX         0x00001C06
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_USB0PFLT       0x00001C08
+#define GPIO_PA7_U1DCD          0x00001C09
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_PWM2           0x00010002
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_PWM3           0x00010402
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_IDX0           0x00010802
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+#define GPIO_PB2_USB0EPEN       0x00010808
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_FAULT0         0x00010C02
+#define GPIO_PB3_FAULT3         0x00010C04
+#define GPIO_PB3_USB0PFLT       0x00010C08
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_CAN0RX         0x00011005
+#define GPIO_PB4_IDX0           0x00011006
+#define GPIO_PB4_U1RX           0x00011007
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CAN0TX         0x00011405
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_FAULT1         0x00011804
+#define GPIO_PB6_IDX0           0x00011805
+#define GPIO_PB6_CCP5           0x00011806
+#define GPIO_PB6_I2S0TXSCK      0x00011809
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_PHA0           0x00021002
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_FAULT2         0x00021404
+#define GPIO_PC5_CCP3           0x00021405
+#define GPIO_PC5_USB0EPEN       0x00021406
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_PHB0           0x00021802
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+#define GPIO_PC6_USB0PFLT       0x00021807
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_PHB0           0x00021C02
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_USB0PFLT       0x00021C06
+#define GPIO_PC7_C1O            0x00021C07
+
+#define GPIO_PD0_PWM0           0x00030001
+#define GPIO_PD0_CAN0RX         0x00030002
+#define GPIO_PD0_IDX0           0x00030003
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+#define GPIO_PD0_I2S0RXSCK      0x00030008
+#define GPIO_PD0_U1CTS          0x00030009
+
+#define GPIO_PD1_PWM1           0x00030401
+#define GPIO_PD1_CAN0TX         0x00030402
+#define GPIO_PD1_PHA0           0x00030403
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_I2S0RXWS       0x00030408
+#define GPIO_PD1_U1DCD          0x00030409
+#define GPIO_PD1_CCP2           0x0003040A
+#define GPIO_PD1_PHB1           0x0003040B
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_PWM2           0x00030803
+#define GPIO_PD2_CCP5           0x00030804
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_PWM3           0x00030C03
+#define GPIO_PD3_CCP0           0x00030C04
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+#define GPIO_PD4_I2S0RXSD       0x00031008
+#define GPIO_PD4_U1RI           0x00031009
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_I2S0RXMCLK     0x00031408
+#define GPIO_PD5_U2RX           0x00031409
+
+#define GPIO_PD6_FAULT0         0x00031801
+#define GPIO_PD6_I2S0TXSCK      0x00031808
+#define GPIO_PD6_U2TX           0x00031809
+
+#define GPIO_PD7_IDX0           0x00031C01
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+#define GPIO_PD7_I2S0TXWS       0x00031C08
+#define GPIO_PD7_U1DTR          0x00031C09
+
+#define GPIO_PE0_PWM4           0x00040001
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+#define GPIO_PE0_USB0PFLT       0x00040009
+
+#define GPIO_PE1_PWM5           0x00040401
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_FAULT0         0x00040403
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_PHB1           0x00040803
+#define GPIO_PE2_PHA0           0x00040804
+#define GPIO_PE2_CCP2           0x00040805
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_PHA1           0x00040C03
+#define GPIO_PE3_PHB0           0x00040C04
+#define GPIO_PE3_CCP7           0x00040C05
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_FAULT0         0x00041004
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+#define GPIO_PE4_I2S0TXWS       0x00041009
+
+#define GPIO_PE5_CCP5           0x00041401
+#define GPIO_PE5_I2S0TXSD       0x00041409
+
+#define GPIO_PE6_PWM4           0x00041801
+#define GPIO_PE6_C1O            0x00041802
+#define GPIO_PE6_U1CTS          0x00041809
+
+#define GPIO_PE7_PWM5           0x00041C01
+#define GPIO_PE7_U1DCD          0x00041C09
+
+#define GPIO_PF0_CAN1RX         0x00050001
+#define GPIO_PF0_PHB0           0x00050002
+#define GPIO_PF0_PWM0           0x00050003
+#define GPIO_PF0_I2S0TXSD       0x00050008
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_CAN1TX         0x00050401
+#define GPIO_PF1_IDX1           0x00050402
+#define GPIO_PF1_PWM1           0x00050403
+#define GPIO_PF1_I2S0TXMCLK     0x00050408
+#define GPIO_PF1_U1RTS          0x00050409
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_LED1           0x00050801
+#define GPIO_PF2_PWM4           0x00050802
+#define GPIO_PF2_PWM2           0x00050804
+#define GPIO_PF2_SSI1CLK        0x00050809
+
+#define GPIO_PF3_LED0           0x00050C01
+#define GPIO_PF3_PWM5           0x00050C02
+#define GPIO_PF3_PWM3           0x00050C04
+#define GPIO_PF3_SSI1FSS        0x00050C09
+
+#define GPIO_PF4_CCP0           0x00051001
+#define GPIO_PF4_C0O            0x00051002
+#define GPIO_PF4_FAULT0         0x00051004
+#define GPIO_PF4_SSI1RX         0x00051009
+
+#define GPIO_PF5_CCP2           0x00051401
+#define GPIO_PF5_C1O            0x00051402
+#define GPIO_PF5_SSI1TX         0x00051409
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_PWM0           0x00060002
+#define GPIO_PG0_I2C1SCL        0x00060003
+#define GPIO_PG0_PWM4           0x00060004
+#define GPIO_PG0_USB0EPEN       0x00060007
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_PWM1           0x00060402
+#define GPIO_PG1_I2C1SDA        0x00060403
+#define GPIO_PG1_PWM5           0x00060404
+
+#define GPIO_PG7_PHB1           0x00061C01
+#define GPIO_PG7_CCP5           0x00061C08
+
+#define GPIO_PH0_CCP6           0x00070001
+#define GPIO_PH0_PWM2           0x00070002
+#define GPIO_PH0_PWM4           0x00070009
+
+#define GPIO_PH1_CCP7           0x00070401
+#define GPIO_PH1_PWM3           0x00070402
+#define GPIO_PH1_PWM5           0x00070409
+
+#define GPIO_PH2_IDX1           0x00070801
+#define GPIO_PH2_C1O            0x00070802
+#define GPIO_PH2_FAULT3         0x00070804
+
+#define GPIO_PH3_PHB0           0x00070C01
+#define GPIO_PH3_FAULT0         0x00070C02
+#define GPIO_PH3_USB0EPEN       0x00070C04
+
+#define GPIO_PH4_USB0PFLT       0x00071004
+#define GPIO_PH4_SSI1CLK        0x0007100B
+
+#define GPIO_PH5_FAULT2         0x0007140A
+#define GPIO_PH5_SSI1FSS        0x0007140B
+
+#define GPIO_PH6_PWM4           0x0007180A
+#define GPIO_PH6_SSI1RX         0x0007180B
+
+#define GPIO_PH7_PWM5           0x00071C0A
+#define GPIO_PH7_SSI1TX         0x00071C0B
+
+#define GPIO_PJ0_PWM0           0x0008000A
+#define GPIO_PJ0_I2C1SCL        0x0008000B
+
+#define GPIO_PJ1_USB0PFLT       0x00080409
+#define GPIO_PJ1_PWM1           0x0008040A
+#define GPIO_PJ1_I2C1SDA        0x0008040B
+
+#define GPIO_PJ2_CCP0           0x00080809
+#define GPIO_PJ2_FAULT0         0x0008080A
+
+#endif // PART_LM3S9G97
+
+//*****************************************************************************
+//
+// LM3S9GN5 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S9GN5
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_TXD2           0x00000803
+#define GPIO_PA2_PWM4           0x00000804
+#define GPIO_PA2_I2S0RXSD       0x00000809
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_TXD1           0x00000C03
+#define GPIO_PA3_PWM5           0x00000C04
+#define GPIO_PA3_I2S0RXMCLK     0x00000C09
+
+#define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_TXD0           0x00001003
+#define GPIO_PA4_PWM6           0x00001004
+#define GPIO_PA4_CAN0RX         0x00001005
+#define GPIO_PA4_I2S0TXSCK      0x00001009
+
+#define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_RXDV           0x00001403
+#define GPIO_PA5_PWM7           0x00001404
+#define GPIO_PA5_CAN0TX         0x00001405
+#define GPIO_PA5_I2S0TXWS       0x00001409
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_RXCK           0x00001803
+#define GPIO_PA6_PWM0           0x00001804
+#define GPIO_PA6_PWM4           0x00001805
+#define GPIO_PA6_CAN0RX         0x00001806
+#define GPIO_PA6_USB0EPEN       0x00001808
+#define GPIO_PA6_U1CTS          0x00001809
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_RXER           0x00001C03
+#define GPIO_PA7_PWM1           0x00001C04
+#define GPIO_PA7_PWM5           0x00001C05
+#define GPIO_PA7_CAN0TX         0x00001C06
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_USB0PFLT       0x00001C08
+#define GPIO_PA7_U1DCD          0x00001C09
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_PWM2           0x00010002
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_PWM3           0x00010402
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_IDX0           0x00010802
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+#define GPIO_PB2_USB0EPEN       0x00010808
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_FAULT0         0x00010C02
+#define GPIO_PB3_FAULT3         0x00010C04
+#define GPIO_PB3_USB0PFLT       0x00010C08
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_CAN0RX         0x00011005
+#define GPIO_PB4_IDX0           0x00011006
+#define GPIO_PB4_U1RX           0x00011007
+#define GPIO_PB4_EPI0S23        0x00011008
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CAN0TX         0x00011405
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+#define GPIO_PB5_EPI0S22        0x00011408
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_FAULT1         0x00011804
+#define GPIO_PB6_IDX0           0x00011805
+#define GPIO_PB6_CCP5           0x00011806
+#define GPIO_PB6_I2S0TXSCK      0x00011809
+
+#define GPIO_PB7_NMI            0x00011C04
+#define GPIO_PB7_RXD1           0x00011C07
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_PHA0           0x00021002
+#define GPIO_PC4_TXD3           0x00021003
+#define GPIO_PC4_PWM6           0x00021004
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_EPI0S2         0x00021008
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_FAULT2         0x00021404
+#define GPIO_PC5_CCP3           0x00021405
+#define GPIO_PC5_USB0EPEN       0x00021406
+#define GPIO_PC5_EPI0S3         0x00021408
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_PHB0           0x00021802
+#define GPIO_PC6_C2O            0x00021803
+#define GPIO_PC6_PWM7           0x00021804
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+#define GPIO_PC6_USB0PFLT       0x00021807
+#define GPIO_PC6_EPI0S4         0x00021808
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_PHB0           0x00021C02
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_USB0PFLT       0x00021C06
+#define GPIO_PC7_C1O            0x00021C07
+#define GPIO_PC7_EPI0S5         0x00021C08
+
+#define GPIO_PD0_PWM0           0x00030001
+#define GPIO_PD0_CAN0RX         0x00030002
+#define GPIO_PD0_IDX0           0x00030003
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+#define GPIO_PD0_RXDV           0x00030007
+#define GPIO_PD0_I2S0RXSCK      0x00030008
+#define GPIO_PD0_U1CTS          0x00030009
+
+#define GPIO_PD1_PWM1           0x00030401
+#define GPIO_PD1_CAN0TX         0x00030402
+#define GPIO_PD1_PHA0           0x00030403
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_TXER           0x00030407
+#define GPIO_PD1_I2S0RXWS       0x00030408
+#define GPIO_PD1_U1DCD          0x00030409
+#define GPIO_PD1_CCP2           0x0003040A
+#define GPIO_PD1_PHB1           0x0003040B
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_PWM2           0x00030803
+#define GPIO_PD2_CCP5           0x00030804
+#define GPIO_PD2_EPI0S20        0x00030808
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_PWM3           0x00030C03
+#define GPIO_PD3_CCP0           0x00030C04
+#define GPIO_PD3_EPI0S21        0x00030C08
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+#define GPIO_PD4_TXD3           0x00031004
+#define GPIO_PD4_I2S0RXSD       0x00031008
+#define GPIO_PD4_U1RI           0x00031009
+#define GPIO_PD4_EPI0S19        0x0003100A
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_TXD2           0x00031404
+#define GPIO_PD5_I2S0RXMCLK     0x00031408
+#define GPIO_PD5_U2RX           0x00031409
+#define GPIO_PD5_EPI0S28        0x0003140A
+
+#define GPIO_PD6_FAULT0         0x00031801
+#define GPIO_PD6_TXD1           0x00031804
+#define GPIO_PD6_I2S0TXSCK      0x00031808
+#define GPIO_PD6_U2TX           0x00031809
+#define GPIO_PD6_EPI0S29        0x0003180A
+
+#define GPIO_PD7_IDX0           0x00031C01
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+#define GPIO_PD7_TXD0           0x00031C04
+#define GPIO_PD7_I2S0TXWS       0x00031C08
+#define GPIO_PD7_U1DTR          0x00031C09
+#define GPIO_PD7_EPI0S30        0x00031C0A
+
+#define GPIO_PE0_PWM4           0x00040001
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+#define GPIO_PE0_EPI0S8         0x00040008
+#define GPIO_PE0_USB0PFLT       0x00040009
+
+#define GPIO_PE1_PWM5           0x00040401
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_FAULT0         0x00040403
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+#define GPIO_PE1_EPI0S9         0x00040408
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_PHB1           0x00040803
+#define GPIO_PE2_PHA0           0x00040804
+#define GPIO_PE2_CCP2           0x00040805
+#define GPIO_PE2_EPI0S24        0x00040808
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_PHA1           0x00040C03
+#define GPIO_PE3_PHB0           0x00040C04
+#define GPIO_PE3_CCP7           0x00040C05
+#define GPIO_PE3_EPI0S25        0x00040C08
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_FAULT0         0x00041004
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+#define GPIO_PE4_RXD0           0x00041007
+#define GPIO_PE4_I2S0TXWS       0x00041009
+
+#define GPIO_PE5_CCP5           0x00041401
+#define GPIO_PE5_I2S0TXSD       0x00041409
+
+#define GPIO_PE6_PWM4           0x00041801
+#define GPIO_PE6_C1O            0x00041802
+#define GPIO_PE6_U1CTS          0x00041809
+
+#define GPIO_PE7_PWM5           0x00041C01
+#define GPIO_PE7_C2O            0x00041C02
+#define GPIO_PE7_U1DCD          0x00041C09
+
+#define GPIO_PF0_CAN1RX         0x00050001
+#define GPIO_PF0_PHB0           0x00050002
+#define GPIO_PF0_PWM0           0x00050003
+#define GPIO_PF0_RXCK           0x00050004
+#define GPIO_PF0_I2S0TXSD       0x00050008
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_CAN1TX         0x00050401
+#define GPIO_PF1_IDX1           0x00050402
+#define GPIO_PF1_PWM1           0x00050403
+#define GPIO_PF1_RXER           0x00050404
+#define GPIO_PF1_I2S0TXMCLK     0x00050408
+#define GPIO_PF1_U1RTS          0x00050409
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_PWM4           0x00050802
+#define GPIO_PF2_PHYINT         0x00050803
+#define GPIO_PF2_PWM2           0x00050804
+#define GPIO_PF2_SSI1CLK        0x00050809
+
+#define GPIO_PF3_PWM5           0x00050C02
+#define GPIO_PF3_MDC            0x00050C03
+#define GPIO_PF3_PWM3           0x00050C04
+#define GPIO_PF3_SSI1FSS        0x00050C09
+
+#define GPIO_PF4_CCP0           0x00051001
+#define GPIO_PF4_C0O            0x00051002
+#define GPIO_PF4_MDIO           0x00051003
+#define GPIO_PF4_FAULT0         0x00051004
+#define GPIO_PF4_EPI0S12        0x00051008
+#define GPIO_PF4_SSI1RX         0x00051009
+
+#define GPIO_PF5_CCP2           0x00051401
+#define GPIO_PF5_C1O            0x00051402
+#define GPIO_PF5_RXD3           0x00051403
+#define GPIO_PF5_EPI0S15        0x00051408
+#define GPIO_PF5_SSI1TX         0x00051409
+
+#define GPIO_PF6_CCP1           0x00051801
+#define GPIO_PF6_C2O            0x00051802
+#define GPIO_PF6_RXD2           0x00051803
+#define GPIO_PF6_PHA0           0x00051804
+#define GPIO_PF6_I2S0TXMCLK     0x00051809
+#define GPIO_PF6_U1RTS          0x0005180A
+
+#define GPIO_PF7_CCP4           0x00051C01
+#define GPIO_PF7_RXD1           0x00051C03
+#define GPIO_PF7_PHB0           0x00051C04
+#define GPIO_PF7_EPI0S12        0x00051C08
+#define GPIO_PF7_FAULT1         0x00051C09
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_PWM0           0x00060002
+#define GPIO_PG0_I2C1SCL        0x00060003
+#define GPIO_PG0_PWM4           0x00060004
+#define GPIO_PG0_USB0EPEN       0x00060007
+#define GPIO_PG0_EPI0S13        0x00060008
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_PWM1           0x00060402
+#define GPIO_PG1_I2C1SDA        0x00060403
+#define GPIO_PG1_PWM5           0x00060404
+#define GPIO_PG1_EPI0S14        0x00060408
+
+#define GPIO_PG2_PWM0           0x00060801
+#define GPIO_PG2_COL            0x00060803
+#define GPIO_PG2_FAULT0         0x00060804
+#define GPIO_PG2_IDX1           0x00060808
+#define GPIO_PG2_I2S0RXSD       0x00060809
+
+#define GPIO_PG3_PWM1           0x00060C01
+#define GPIO_PG3_CRS            0x00060C03
+#define GPIO_PG3_FAULT2         0x00060C04
+#define GPIO_PG3_FAULT0         0x00060C08
+#define GPIO_PG3_I2S0RXMCLK     0x00060C09
+
+#define GPIO_PG4_CCP3           0x00061001
+#define GPIO_PG4_RXD0           0x00061003
+#define GPIO_PG4_FAULT1         0x00061004
+#define GPIO_PG4_EPI0S15        0x00061008
+#define GPIO_PG4_PWM6           0x00061009
+#define GPIO_PG4_U1RI           0x0006100A
+
+#define GPIO_PG5_CCP5           0x00061401
+#define GPIO_PG5_TXEN           0x00061403
+#define GPIO_PG5_IDX0           0x00061404
+#define GPIO_PG5_FAULT1         0x00061405
+#define GPIO_PG5_PWM7           0x00061408
+#define GPIO_PG5_I2S0RXSCK      0x00061409
+#define GPIO_PG5_U1DTR          0x0006140A
+
+#define GPIO_PG6_PHA1           0x00061801
+#define GPIO_PG6_TXCK           0x00061803
+#define GPIO_PG6_PWM6           0x00061804
+#define GPIO_PG6_FAULT1         0x00061808
+#define GPIO_PG6_I2S0RXWS       0x00061809
+#define GPIO_PG6_U1RI           0x0006180A
+
+#define GPIO_PG7_PHB1           0x00061C01
+#define GPIO_PG7_TXER           0x00061C03
+#define GPIO_PG7_PWM7           0x00061C04
+#define GPIO_PG7_CCP5           0x00061C08
+#define GPIO_PG7_EPI0S31        0x00061C09
+
+#define GPIO_PH0_CCP6           0x00070001
+#define GPIO_PH0_PWM2           0x00070002
+#define GPIO_PH0_EPI0S6         0x00070008
+#define GPIO_PH0_PWM4           0x00070009
+
+#define GPIO_PH1_CCP7           0x00070401
+#define GPIO_PH1_PWM3           0x00070402
+#define GPIO_PH1_EPI0S7         0x00070408
+#define GPIO_PH1_PWM5           0x00070409
+
+#define GPIO_PH2_IDX1           0x00070801
+#define GPIO_PH2_C1O            0x00070802
+#define GPIO_PH2_FAULT3         0x00070804
+#define GPIO_PH2_EPI0S1         0x00070808
+#define GPIO_PH2_TXD3           0x00070809
+
+#define GPIO_PH3_PHB0           0x00070C01
+#define GPIO_PH3_FAULT0         0x00070C02
+#define GPIO_PH3_USB0EPEN       0x00070C04
+#define GPIO_PH3_EPI0S0         0x00070C08
+#define GPIO_PH3_TXD2           0x00070C09
+
+#define GPIO_PH4_USB0PFLT       0x00071004
+#define GPIO_PH4_EPI0S10        0x00071008
+#define GPIO_PH4_TXD1           0x00071009
+#define GPIO_PH4_SSI1CLK        0x0007100B
+
+#define GPIO_PH5_EPI0S11        0x00071408
+#define GPIO_PH5_TXD0           0x00071409
+#define GPIO_PH5_FAULT2         0x0007140A
+#define GPIO_PH5_SSI1FSS        0x0007140B
+
+#define GPIO_PH6_EPI0S26        0x00071808
+#define GPIO_PH6_RXDV           0x00071809
+#define GPIO_PH6_PWM4           0x0007180A
+#define GPIO_PH6_SSI1RX         0x0007180B
+
+#define GPIO_PH7_RXCK           0x00071C03
+#define GPIO_PH7_EPI0S27        0x00071C08
+#define GPIO_PH7_PWM5           0x00071C0A
+#define GPIO_PH7_SSI1TX         0x00071C0B
+
+#define GPIO_PJ0_RXER           0x00080003
+#define GPIO_PJ0_EPI0S16        0x00080008
+#define GPIO_PJ0_PWM0           0x0008000A
+#define GPIO_PJ0_I2C1SCL        0x0008000B
+
+#define GPIO_PJ1_EPI0S17        0x00080408
+#define GPIO_PJ1_USB0PFLT       0x00080409
+#define GPIO_PJ1_PWM1           0x0008040A
+#define GPIO_PJ1_I2C1SDA        0x0008040B
+
+#define GPIO_PJ2_EPI0S18        0x00080808
+#define GPIO_PJ2_CCP0           0x00080809
+#define GPIO_PJ2_FAULT0         0x0008080A
+
+#define GPIO_PJ3_EPI0S19        0x00080C08
+#define GPIO_PJ3_U1CTS          0x00080C09
+#define GPIO_PJ3_CCP6           0x00080C0A
+
+#define GPIO_PJ4_EPI0S28        0x00081008
+#define GPIO_PJ4_U1DCD          0x00081009
+#define GPIO_PJ4_CCP4           0x0008100A
+
+#define GPIO_PJ5_EPI0S29        0x00081408
+#define GPIO_PJ5_U1DSR          0x00081409
+#define GPIO_PJ5_CCP2           0x0008140A
+
+#define GPIO_PJ6_EPI0S30        0x00081808
+#define GPIO_PJ6_U1RTS          0x00081809
+#define GPIO_PJ6_CCP1           0x0008180A
+
+#define GPIO_PJ7_U1DTR          0x00081C09
+#define GPIO_PJ7_CCP0           0x00081C0A
+
+#endif // PART_LM3S9GN5
+
+//*****************************************************************************
+//
+// LM3S9L71 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S9L71
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_TXD2           0x00000803
+#define GPIO_PA2_PWM4           0x00000804
+#define GPIO_PA2_I2S0RXSD       0x00000809
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_TXD1           0x00000C03
+#define GPIO_PA3_PWM5           0x00000C04
+#define GPIO_PA3_I2S0RXMCLK     0x00000C09
+
+#define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_TXD0           0x00001003
+#define GPIO_PA4_CAN0RX         0x00001005
+#define GPIO_PA4_I2S0TXSCK      0x00001009
+
+#define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_RXDV           0x00001403
+#define GPIO_PA5_CAN0TX         0x00001405
+#define GPIO_PA5_I2S0TXWS       0x00001409
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_RXCK           0x00001803
+#define GPIO_PA6_PWM0           0x00001804
+#define GPIO_PA6_PWM4           0x00001805
+#define GPIO_PA6_CAN0RX         0x00001806
+#define GPIO_PA6_USB0EPEN       0x00001808
+#define GPIO_PA6_U1CTS          0x00001809
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_RXER           0x00001C03
+#define GPIO_PA7_PWM1           0x00001C04
+#define GPIO_PA7_PWM5           0x00001C05
+#define GPIO_PA7_CAN0TX         0x00001C06
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_USB0PFLT       0x00001C08
+#define GPIO_PA7_U1DCD          0x00001C09
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_PWM2           0x00010002
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_PWM3           0x00010402
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_IDX0           0x00010802
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+#define GPIO_PB2_USB0EPEN       0x00010808
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_FAULT0         0x00010C02
+#define GPIO_PB3_FAULT3         0x00010C04
+#define GPIO_PB3_USB0PFLT       0x00010C08
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_CAN0RX         0x00011005
+#define GPIO_PB4_IDX0           0x00011006
+#define GPIO_PB4_U1RX           0x00011007
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CAN0TX         0x00011405
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_FAULT1         0x00011804
+#define GPIO_PB6_IDX0           0x00011805
+#define GPIO_PB6_CCP5           0x00011806
+#define GPIO_PB6_I2S0TXSCK      0x00011809
+
+#define GPIO_PB7_NMI            0x00011C04
+#define GPIO_PB7_RXD1           0x00011C07
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_PHA0           0x00021002
+#define GPIO_PC4_TXD3           0x00021003
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_FAULT2         0x00021404
+#define GPIO_PC5_CCP3           0x00021405
+#define GPIO_PC5_USB0EPEN       0x00021406
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_PHB0           0x00021802
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+#define GPIO_PC6_USB0PFLT       0x00021807
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_PHB0           0x00021C02
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_USB0PFLT       0x00021C06
+#define GPIO_PC7_C1O            0x00021C07
+
+#define GPIO_PD0_PWM0           0x00030001
+#define GPIO_PD0_CAN0RX         0x00030002
+#define GPIO_PD0_IDX0           0x00030003
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+#define GPIO_PD0_RXDV           0x00030007
+#define GPIO_PD0_I2S0RXSCK      0x00030008
+#define GPIO_PD0_U1CTS          0x00030009
+
+#define GPIO_PD1_PWM1           0x00030401
+#define GPIO_PD1_CAN0TX         0x00030402
+#define GPIO_PD1_PHA0           0x00030403
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_TXER           0x00030407
+#define GPIO_PD1_I2S0RXWS       0x00030408
+#define GPIO_PD1_U1DCD          0x00030409
+#define GPIO_PD1_CCP2           0x0003040A
+#define GPIO_PD1_PHB1           0x0003040B
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_PWM2           0x00030803
+#define GPIO_PD2_CCP5           0x00030804
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_PWM3           0x00030C03
+#define GPIO_PD3_CCP0           0x00030C04
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+#define GPIO_PD4_TXD3           0x00031004
+#define GPIO_PD4_I2S0RXSD       0x00031008
+#define GPIO_PD4_U1RI           0x00031009
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_TXD2           0x00031404
+#define GPIO_PD5_I2S0RXMCLK     0x00031408
+#define GPIO_PD5_U2RX           0x00031409
+
+#define GPIO_PD6_FAULT0         0x00031801
+#define GPIO_PD6_TXD1           0x00031804
+#define GPIO_PD6_I2S0TXSCK      0x00031808
+#define GPIO_PD6_U2TX           0x00031809
+
+#define GPIO_PD7_IDX0           0x00031C01
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+#define GPIO_PD7_TXD0           0x00031C04
+#define GPIO_PD7_I2S0TXWS       0x00031C08
+#define GPIO_PD7_U1DTR          0x00031C09
+
+#define GPIO_PE0_PWM4           0x00040001
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+#define GPIO_PE0_USB0PFLT       0x00040009
+
+#define GPIO_PE1_PWM5           0x00040401
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_FAULT0         0x00040403
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_PHB1           0x00040803
+#define GPIO_PE2_PHA0           0x00040804
+#define GPIO_PE2_CCP2           0x00040805
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_PHA1           0x00040C03
+#define GPIO_PE3_PHB0           0x00040C04
+#define GPIO_PE3_CCP7           0x00040C05
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_FAULT0         0x00041004
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+#define GPIO_PE4_RXD0           0x00041007
+#define GPIO_PE4_I2S0TXWS       0x00041009
+
+#define GPIO_PE5_CCP5           0x00041401
+#define GPIO_PE5_I2S0TXSD       0x00041409
+
+#define GPIO_PE6_PWM4           0x00041801
+#define GPIO_PE6_C1O            0x00041802
+#define GPIO_PE6_U1CTS          0x00041809
+
+#define GPIO_PE7_PWM5           0x00041C01
+#define GPIO_PE7_U1DCD          0x00041C09
+
+#define GPIO_PF0_CAN1RX         0x00050001
+#define GPIO_PF0_PHB0           0x00050002
+#define GPIO_PF0_PWM0           0x00050003
+#define GPIO_PF0_RXCK           0x00050004
+#define GPIO_PF0_I2S0TXSD       0x00050008
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_CAN1TX         0x00050401
+#define GPIO_PF1_IDX1           0x00050402
+#define GPIO_PF1_PWM1           0x00050403
+#define GPIO_PF1_RXER           0x00050404
+#define GPIO_PF1_I2S0TXMCLK     0x00050408
+#define GPIO_PF1_U1RTS          0x00050409
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_PWM4           0x00050802
+#define GPIO_PF2_PHYINT         0x00050803
+#define GPIO_PF2_PWM2           0x00050804
+#define GPIO_PF2_SSI1CLK        0x00050809
+
+#define GPIO_PF3_PWM5           0x00050C02
+#define GPIO_PF3_MDC            0x00050C03
+#define GPIO_PF3_PWM3           0x00050C04
+#define GPIO_PF3_SSI1FSS        0x00050C09
+
+#define GPIO_PF4_CCP0           0x00051001
+#define GPIO_PF4_C0O            0x00051002
+#define GPIO_PF4_MDIO           0x00051003
+#define GPIO_PF4_FAULT0         0x00051004
+#define GPIO_PF4_SSI1RX         0x00051009
+
+#define GPIO_PF5_CCP2           0x00051401
+#define GPIO_PF5_C1O            0x00051402
+#define GPIO_PF5_RXD3           0x00051403
+#define GPIO_PF5_SSI1TX         0x00051409
+
+#define GPIO_PF6_CCP1           0x00051801
+#define GPIO_PF6_RXD2           0x00051803
+#define GPIO_PF6_PHA0           0x00051804
+#define GPIO_PF6_I2S0TXMCLK     0x00051809
+#define GPIO_PF6_U1RTS          0x0005180A
+
+#define GPIO_PF7_CCP4           0x00051C01
+#define GPIO_PF7_RXD1           0x00051C03
+#define GPIO_PF7_PHB0           0x00051C04
+#define GPIO_PF7_FAULT1         0x00051C09
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_PWM0           0x00060002
+#define GPIO_PG0_I2C1SCL        0x00060003
+#define GPIO_PG0_PWM4           0x00060004
+#define GPIO_PG0_USB0EPEN       0x00060007
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_PWM1           0x00060402
+#define GPIO_PG1_I2C1SDA        0x00060403
+#define GPIO_PG1_PWM5           0x00060404
+
+#define GPIO_PG2_PWM0           0x00060801
+#define GPIO_PG2_COL            0x00060803
+#define GPIO_PG2_FAULT0         0x00060804
+#define GPIO_PG2_IDX1           0x00060808
+#define GPIO_PG2_I2S0RXSD       0x00060809
+
+#define GPIO_PG3_PWM1           0x00060C01
+#define GPIO_PG3_CRS            0x00060C03
+#define GPIO_PG3_FAULT2         0x00060C04
+#define GPIO_PG3_FAULT0         0x00060C08
+#define GPIO_PG3_I2S0RXMCLK     0x00060C09
+
+#define GPIO_PG4_CCP3           0x00061001
+#define GPIO_PG4_RXD0           0x00061003
+#define GPIO_PG4_FAULT1         0x00061004
+#define GPIO_PG4_U1RI           0x0006100A
+
+#define GPIO_PG5_CCP5           0x00061401
+#define GPIO_PG5_TXEN           0x00061403
+#define GPIO_PG5_IDX0           0x00061404
+#define GPIO_PG5_FAULT1         0x00061405
+#define GPIO_PG5_I2S0RXSCK      0x00061409
+#define GPIO_PG5_U1DTR          0x0006140A
+
+#define GPIO_PG6_PHA1           0x00061801
+#define GPIO_PG6_TXCK           0x00061803
+#define GPIO_PG6_FAULT1         0x00061808
+#define GPIO_PG6_I2S0RXWS       0x00061809
+#define GPIO_PG6_U1RI           0x0006180A
+
+#define GPIO_PG7_PHB1           0x00061C01
+#define GPIO_PG7_TXER           0x00061C03
+#define GPIO_PG7_CCP5           0x00061C08
+
+#define GPIO_PH0_CCP6           0x00070001
+#define GPIO_PH0_PWM2           0x00070002
+#define GPIO_PH0_PWM4           0x00070009
+
+#define GPIO_PH1_CCP7           0x00070401
+#define GPIO_PH1_PWM3           0x00070402
+#define GPIO_PH1_PWM5           0x00070409
+
+#define GPIO_PH2_IDX1           0x00070801
+#define GPIO_PH2_C1O            0x00070802
+#define GPIO_PH2_FAULT3         0x00070804
+#define GPIO_PH2_TXD3           0x00070809
+
+#define GPIO_PH3_PHB0           0x00070C01
+#define GPIO_PH3_FAULT0         0x00070C02
+#define GPIO_PH3_USB0EPEN       0x00070C04
+#define GPIO_PH3_TXD2           0x00070C09
+
+#define GPIO_PH4_USB0PFLT       0x00071004
+#define GPIO_PH4_TXD1           0x00071009
+#define GPIO_PH4_SSI1CLK        0x0007100B
+
+#define GPIO_PH5_TXD0           0x00071409
+#define GPIO_PH5_FAULT2         0x0007140A
+#define GPIO_PH5_SSI1FSS        0x0007140B
+
+#define GPIO_PH6_RXDV           0x00071809
+#define GPIO_PH6_PWM4           0x0007180A
+#define GPIO_PH6_SSI1RX         0x0007180B
+
+#define GPIO_PH7_RXCK           0x00071C03
+#define GPIO_PH7_PWM5           0x00071C0A
+#define GPIO_PH7_SSI1TX         0x00071C0B
+
+#define GPIO_PJ0_RXER           0x00080003
+#define GPIO_PJ0_PWM0           0x0008000A
+#define GPIO_PJ0_I2C1SCL        0x0008000B
+
+#define GPIO_PJ1_USB0PFLT       0x00080409
+#define GPIO_PJ1_PWM1           0x0008040A
+#define GPIO_PJ1_I2C1SDA        0x0008040B
+
+#define GPIO_PJ2_CCP0           0x00080809
+#define GPIO_PJ2_FAULT0         0x0008080A
+
+#define GPIO_PJ3_U1CTS          0x00080C09
+#define GPIO_PJ3_CCP6           0x00080C0A
+
+#define GPIO_PJ4_U1DCD          0x00081009
+#define GPIO_PJ4_CCP4           0x0008100A
+
+#define GPIO_PJ5_U1DSR          0x00081409
+#define GPIO_PJ5_CCP2           0x0008140A
+
+#define GPIO_PJ6_U1RTS          0x00081809
+#define GPIO_PJ6_CCP1           0x0008180A
+
+#define GPIO_PJ7_U1DTR          0x00081C09
+#define GPIO_PJ7_CCP0           0x00081C0A
+
+#endif // PART_LM3S9L71
+
+//*****************************************************************************
+//
+// LM3S9L97 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S9L97
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_PWM4           0x00000804
+#define GPIO_PA2_I2S0RXSD       0x00000809
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_PWM5           0x00000C04
+#define GPIO_PA3_I2S0RXMCLK     0x00000C09
+
+#define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_CAN0RX         0x00001005
+#define GPIO_PA4_I2S0TXSCK      0x00001009
+
+#define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_CAN0TX         0x00001405
+#define GPIO_PA5_I2S0TXWS       0x00001409
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_PWM0           0x00001804
+#define GPIO_PA6_PWM4           0x00001805
+#define GPIO_PA6_CAN0RX         0x00001806
+#define GPIO_PA6_USB0EPEN       0x00001808
+#define GPIO_PA6_U1CTS          0x00001809
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_PWM1           0x00001C04
+#define GPIO_PA7_PWM5           0x00001C05
+#define GPIO_PA7_CAN0TX         0x00001C06
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_USB0PFLT       0x00001C08
+#define GPIO_PA7_U1DCD          0x00001C09
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_PWM2           0x00010002
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_PWM3           0x00010402
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_IDX0           0x00010802
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+#define GPIO_PB2_USB0EPEN       0x00010808
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_FAULT0         0x00010C02
+#define GPIO_PB3_FAULT3         0x00010C04
+#define GPIO_PB3_USB0PFLT       0x00010C08
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_CAN0RX         0x00011005
+#define GPIO_PB4_IDX0           0x00011006
+#define GPIO_PB4_U1RX           0x00011007
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CAN0TX         0x00011405
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_FAULT1         0x00011804
+#define GPIO_PB6_IDX0           0x00011805
+#define GPIO_PB6_CCP5           0x00011806
+#define GPIO_PB6_I2S0TXSCK      0x00011809
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_PHA0           0x00021002
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_FAULT2         0x00021404
+#define GPIO_PC5_CCP3           0x00021405
+#define GPIO_PC5_USB0EPEN       0x00021406
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_PHB0           0x00021802
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+#define GPIO_PC6_USB0PFLT       0x00021807
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_PHB0           0x00021C02
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_USB0PFLT       0x00021C06
+#define GPIO_PC7_C1O            0x00021C07
+
+#define GPIO_PD0_PWM0           0x00030001
+#define GPIO_PD0_CAN0RX         0x00030002
+#define GPIO_PD0_IDX0           0x00030003
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+#define GPIO_PD0_I2S0RXSCK      0x00030008
+#define GPIO_PD0_U1CTS          0x00030009
+
+#define GPIO_PD1_PWM1           0x00030401
+#define GPIO_PD1_CAN0TX         0x00030402
+#define GPIO_PD1_PHA0           0x00030403
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_I2S0RXWS       0x00030408
+#define GPIO_PD1_U1DCD          0x00030409
+#define GPIO_PD1_CCP2           0x0003040A
+#define GPIO_PD1_PHB1           0x0003040B
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_PWM2           0x00030803
+#define GPIO_PD2_CCP5           0x00030804
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_PWM3           0x00030C03
+#define GPIO_PD3_CCP0           0x00030C04
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+#define GPIO_PD4_I2S0RXSD       0x00031008
+#define GPIO_PD4_U1RI           0x00031009
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_I2S0RXMCLK     0x00031408
+#define GPIO_PD5_U2RX           0x00031409
+
+#define GPIO_PD6_FAULT0         0x00031801
+#define GPIO_PD6_I2S0TXSCK      0x00031808
+#define GPIO_PD6_U2TX           0x00031809
+
+#define GPIO_PD7_IDX0           0x00031C01
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+#define GPIO_PD7_I2S0TXWS       0x00031C08
+#define GPIO_PD7_U1DTR          0x00031C09
+
+#define GPIO_PE0_PWM4           0x00040001
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+#define GPIO_PE0_USB0PFLT       0x00040009
+
+#define GPIO_PE1_PWM5           0x00040401
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_FAULT0         0x00040403
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_PHB1           0x00040803
+#define GPIO_PE2_PHA0           0x00040804
+#define GPIO_PE2_CCP2           0x00040805
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_PHA1           0x00040C03
+#define GPIO_PE3_PHB0           0x00040C04
+#define GPIO_PE3_CCP7           0x00040C05
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_FAULT0         0x00041004
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+#define GPIO_PE4_I2S0TXWS       0x00041009
+
+#define GPIO_PE5_CCP5           0x00041401
+#define GPIO_PE5_I2S0TXSD       0x00041409
+
+#define GPIO_PE6_PWM4           0x00041801
+#define GPIO_PE6_C1O            0x00041802
+#define GPIO_PE6_U1CTS          0x00041809
+
+#define GPIO_PE7_PWM5           0x00041C01
+#define GPIO_PE7_U1DCD          0x00041C09
+
+#define GPIO_PF0_CAN1RX         0x00050001
+#define GPIO_PF0_PHB0           0x00050002
+#define GPIO_PF0_PWM0           0x00050003
+#define GPIO_PF0_I2S0TXSD       0x00050008
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_CAN1TX         0x00050401
+#define GPIO_PF1_IDX1           0x00050402
+#define GPIO_PF1_PWM1           0x00050403
+#define GPIO_PF1_I2S0TXMCLK     0x00050408
+#define GPIO_PF1_U1RTS          0x00050409
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_LED1           0x00050801
+#define GPIO_PF2_PWM4           0x00050802
+#define GPIO_PF2_PWM2           0x00050804
+#define GPIO_PF2_SSI1CLK        0x00050809
+
+#define GPIO_PF3_LED0           0x00050C01
+#define GPIO_PF3_PWM5           0x00050C02
+#define GPIO_PF3_PWM3           0x00050C04
+#define GPIO_PF3_SSI1FSS        0x00050C09
+
+#define GPIO_PF4_CCP0           0x00051001
+#define GPIO_PF4_C0O            0x00051002
+#define GPIO_PF4_FAULT0         0x00051004
+#define GPIO_PF4_SSI1RX         0x00051009
+
+#define GPIO_PF5_CCP2           0x00051401
+#define GPIO_PF5_C1O            0x00051402
+#define GPIO_PF5_SSI1TX         0x00051409
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_PWM0           0x00060002
+#define GPIO_PG0_I2C1SCL        0x00060003
+#define GPIO_PG0_PWM4           0x00060004
+#define GPIO_PG0_USB0EPEN       0x00060007
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_PWM1           0x00060402
+#define GPIO_PG1_I2C1SDA        0x00060403
+#define GPIO_PG1_PWM5           0x00060404
+
+#define GPIO_PG7_PHB1           0x00061C01
+#define GPIO_PG7_CCP5           0x00061C08
+
+#define GPIO_PH0_CCP6           0x00070001
+#define GPIO_PH0_PWM2           0x00070002
+#define GPIO_PH0_PWM4           0x00070009
+
+#define GPIO_PH1_CCP7           0x00070401
+#define GPIO_PH1_PWM3           0x00070402
+#define GPIO_PH1_PWM5           0x00070409
+
+#define GPIO_PH2_IDX1           0x00070801
+#define GPIO_PH2_C1O            0x00070802
+#define GPIO_PH2_FAULT3         0x00070804
+
+#define GPIO_PH3_PHB0           0x00070C01
+#define GPIO_PH3_FAULT0         0x00070C02
+#define GPIO_PH3_USB0EPEN       0x00070C04
+
+#define GPIO_PH4_USB0PFLT       0x00071004
+#define GPIO_PH4_SSI1CLK        0x0007100B
+
+#define GPIO_PH5_FAULT2         0x0007140A
+#define GPIO_PH5_SSI1FSS        0x0007140B
+
+#define GPIO_PH6_PWM4           0x0007180A
+#define GPIO_PH6_SSI1RX         0x0007180B
+
+#define GPIO_PH7_PWM5           0x00071C0A
+#define GPIO_PH7_SSI1TX         0x00071C0B
+
+#define GPIO_PJ0_PWM0           0x0008000A
+#define GPIO_PJ0_I2C1SCL        0x0008000B
+
+#define GPIO_PJ1_USB0PFLT       0x00080409
+#define GPIO_PJ1_PWM1           0x0008040A
+#define GPIO_PJ1_I2C1SDA        0x0008040B
+
+#define GPIO_PJ2_CCP0           0x00080809
+#define GPIO_PJ2_FAULT0         0x0008080A
+
+#endif // PART_LM3S9L97
+
+//*****************************************************************************
+//
+// LM3S9U81 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S9U81
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_I2S0RXSD       0x00000809
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_I2S0RXMCLK     0x00000C09
+
+#define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_CAN0RX         0x00001005
+#define GPIO_PA4_I2S0TXSCK      0x00001009
+
+#define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_CAN0TX         0x00001405
+#define GPIO_PA5_I2S0TXWS       0x00001409
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_CAN0RX         0x00001806
+#define GPIO_PA6_USB0EPEN       0x00001808
+#define GPIO_PA6_U1CTS          0x00001809
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_CAN0TX         0x00001C06
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_USB0PFLT       0x00001C08
+#define GPIO_PA7_U1DCD          0x00001C09
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+#define GPIO_PB2_USB0EPEN       0x00010808
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_USB0PFLT       0x00010C08
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_CAN0RX         0x00011005
+#define GPIO_PB4_U1RX           0x00011007
+#define GPIO_PB4_EPI0S23        0x00011008
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CAN0TX         0x00011405
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+#define GPIO_PB5_EPI0S22        0x00011408
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_CCP5           0x00011806
+#define GPIO_PB6_I2S0TXSCK      0x00011809
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_EPI0S2         0x00021008
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_CCP3           0x00021405
+#define GPIO_PC5_USB0EPEN       0x00021406
+#define GPIO_PC5_EPI0S3         0x00021408
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_C2O            0x00021803
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+#define GPIO_PC6_USB0PFLT       0x00021807
+#define GPIO_PC6_EPI0S4         0x00021808
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_USB0PFLT       0x00021C06
+#define GPIO_PC7_C1O            0x00021C07
+#define GPIO_PC7_EPI0S5         0x00021C08
+
+#define GPIO_PD0_CAN0RX         0x00030002
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+#define GPIO_PD0_I2S0RXSCK      0x00030008
+#define GPIO_PD0_U1CTS          0x00030009
+
+#define GPIO_PD1_CAN0TX         0x00030402
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_I2S0RXWS       0x00030408
+#define GPIO_PD1_U1DCD          0x00030409
+#define GPIO_PD1_CCP2           0x0003040A
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_CCP5           0x00030804
+#define GPIO_PD2_EPI0S20        0x00030808
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_CCP0           0x00030C04
+#define GPIO_PD3_EPI0S21        0x00030C08
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+#define GPIO_PD4_I2S0RXSD       0x00031008
+#define GPIO_PD4_U1RI           0x00031009
+#define GPIO_PD4_EPI0S19        0x0003100A
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_I2S0RXMCLK     0x00031408
+#define GPIO_PD5_U2RX           0x00031409
+#define GPIO_PD5_EPI0S28        0x0003140A
+
+#define GPIO_PD6_I2S0TXSCK      0x00031808
+#define GPIO_PD6_U2TX           0x00031809
+#define GPIO_PD6_EPI0S29        0x0003180A
+
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+#define GPIO_PD7_I2S0TXWS       0x00031C08
+#define GPIO_PD7_U1DTR          0x00031C09
+#define GPIO_PD7_EPI0S30        0x00031C0A
+
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+#define GPIO_PE0_EPI0S8         0x00040008
+#define GPIO_PE0_USB0PFLT       0x00040009
+
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+#define GPIO_PE1_EPI0S9         0x00040408
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_CCP2           0x00040805
+#define GPIO_PE2_EPI0S24        0x00040808
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_CCP7           0x00040C05
+#define GPIO_PE3_EPI0S25        0x00040C08
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_CAN2RX         0x00041002
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+#define GPIO_PE4_I2S0TXWS       0x00041009
+
+#define GPIO_PE5_CCP5           0x00041401
+#define GPIO_PE5_CAN2TX         0x00041402
+#define GPIO_PE5_I2S0TXSD       0x00041409
+
+#define GPIO_PE6_C1O            0x00041802
+#define GPIO_PE6_U1CTS          0x00041809
+
+#define GPIO_PE7_C2O            0x00041C02
+#define GPIO_PE7_U1DCD          0x00041C09
+
+#define GPIO_PF0_CAN1RX         0x00050001
+#define GPIO_PF0_I2S0TXSD       0x00050008
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_CAN1TX         0x00050401
+#define GPIO_PF1_I2S0TXMCLK     0x00050408
+#define GPIO_PF1_U1RTS          0x00050409
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_LED1           0x00050801
+#define GPIO_PF2_SSI1CLK        0x00050809
+
+#define GPIO_PF3_LED0           0x00050C01
+#define GPIO_PF3_SSI1FSS        0x00050C09
+
+#define GPIO_PF4_CCP0           0x00051001
+#define GPIO_PF4_C0O            0x00051002
+#define GPIO_PF4_EPI0S12        0x00051008
+#define GPIO_PF4_SSI1RX         0x00051009
+
+#define GPIO_PF5_CCP2           0x00051401
+#define GPIO_PF5_C1O            0x00051402
+#define GPIO_PF5_EPI0S15        0x00051408
+#define GPIO_PF5_SSI1TX         0x00051409
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_I2C1SCL        0x00060003
+#define GPIO_PG0_USB0EPEN       0x00060007
+#define GPIO_PG0_EPI0S13        0x00060008
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_I2C1SDA        0x00060403
+#define GPIO_PG1_EPI0S14        0x00060408
+
+#define GPIO_PG7_CCP5           0x00061C08
+#define GPIO_PG7_EPI0S31        0x00061C09
+
+#define GPIO_PH0_CCP6           0x00070001
+#define GPIO_PH0_EPI0S6         0x00070008
+
+#define GPIO_PH1_CCP7           0x00070401
+#define GPIO_PH1_EPI0S7         0x00070408
+
+#define GPIO_PH2_C1O            0x00070802
+#define GPIO_PH2_EPI0S1         0x00070808
+
+#define GPIO_PH3_USB0EPEN       0x00070C04
+#define GPIO_PH3_EPI0S0         0x00070C08
+
+#define GPIO_PH4_USB0PFLT       0x00071004
+#define GPIO_PH4_EPI0S10        0x00071008
+#define GPIO_PH4_SSI1CLK        0x0007100B
+
+#define GPIO_PH5_EPI0S11        0x00071408
+#define GPIO_PH5_SSI1FSS        0x0007140B
+
+#define GPIO_PH6_EPI0S26        0x00071808
+#define GPIO_PH6_SSI1RX         0x0007180B
+
+#define GPIO_PH7_EPI0S27        0x00071C08
+#define GPIO_PH7_SSI1TX         0x00071C0B
+
+#define GPIO_PJ0_EPI0S16        0x00080008
+#define GPIO_PJ0_I2C1SCL        0x0008000B
+
+#define GPIO_PJ1_EPI0S17        0x00080408
+#define GPIO_PJ1_USB0PFLT       0x00080409
+#define GPIO_PJ1_I2C1SDA        0x0008040B
+
+#define GPIO_PJ2_EPI0S18        0x00080808
+#define GPIO_PJ2_CCP0           0x00080809
+
+#define GPIO_PJ3_EPI0S19        0x00080C08
+#define GPIO_PJ3_U1CTS          0x00080C09
+#define GPIO_PJ3_CCP6           0x00080C0A
+
+#define GPIO_PJ4_EPI0S28        0x00081008
+#define GPIO_PJ4_U1DCD          0x00081009
+#define GPIO_PJ4_CCP4           0x0008100A
+
+#define GPIO_PJ5_EPI0S29        0x00081408
+#define GPIO_PJ5_U1DSR          0x00081409
+#define GPIO_PJ5_CCP2           0x0008140A
+
+#define GPIO_PJ6_EPI0S30        0x00081808
+#define GPIO_PJ6_U1RTS          0x00081809
+#define GPIO_PJ6_CCP1           0x0008180A
+
+#define GPIO_PJ7_U1DTR          0x00081C09
+#define GPIO_PJ7_CCP0           0x00081C0A
+
+#endif // PART_LM3S9U81
+
+//*****************************************************************************
+//
+// LM3S9U90 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S9U90
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_I2S0RXSD       0x00000809
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_I2S0RXMCLK     0x00000C09
+
+#define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_CAN0RX         0x00001005
+#define GPIO_PA4_I2S0TXSCK      0x00001009
+
+#define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_CAN0TX         0x00001405
+#define GPIO_PA5_I2S0TXWS       0x00001409
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_CAN0RX         0x00001806
+#define GPIO_PA6_USB0EPEN       0x00001808
+#define GPIO_PA6_U1CTS          0x00001809
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_CAN0TX         0x00001C06
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_USB0PFLT       0x00001C08
+#define GPIO_PA7_U1DCD          0x00001C09
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+#define GPIO_PB2_USB0EPEN       0x00010808
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_USB0PFLT       0x00010C08
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_CAN0RX         0x00011005
+#define GPIO_PB4_U1RX           0x00011007
+#define GPIO_PB4_EPI0S23        0x00011008
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CAN0TX         0x00011405
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+#define GPIO_PB5_EPI0S22        0x00011408
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_CCP5           0x00011806
+#define GPIO_PB6_I2S0TXSCK      0x00011809
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_EPI0S2         0x00021008
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_CCP3           0x00021405
+#define GPIO_PC5_USB0EPEN       0x00021406
+#define GPIO_PC5_EPI0S3         0x00021408
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_C2O            0x00021803
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+#define GPIO_PC6_USB0PFLT       0x00021807
+#define GPIO_PC6_EPI0S4         0x00021808
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_USB0PFLT       0x00021C06
+#define GPIO_PC7_C1O            0x00021C07
+#define GPIO_PC7_EPI0S5         0x00021C08
+
+#define GPIO_PD0_CAN0RX         0x00030002
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+#define GPIO_PD0_I2S0RXSCK      0x00030008
+#define GPIO_PD0_U1CTS          0x00030009
+
+#define GPIO_PD1_CAN0TX         0x00030402
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_I2S0RXWS       0x00030408
+#define GPIO_PD1_U1DCD          0x00030409
+#define GPIO_PD1_CCP2           0x0003040A
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_CCP5           0x00030804
+#define GPIO_PD2_EPI0S20        0x00030808
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_CCP0           0x00030C04
+#define GPIO_PD3_EPI0S21        0x00030C08
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+#define GPIO_PD4_I2S0RXSD       0x00031008
+#define GPIO_PD4_U1RI           0x00031009
+#define GPIO_PD4_EPI0S19        0x0003100A
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_I2S0RXMCLK     0x00031408
+#define GPIO_PD5_U2RX           0x00031409
+#define GPIO_PD5_EPI0S28        0x0003140A
+
+#define GPIO_PD6_I2S0TXSCK      0x00031808
+#define GPIO_PD6_U2TX           0x00031809
+#define GPIO_PD6_EPI0S29        0x0003180A
+
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+#define GPIO_PD7_I2S0TXWS       0x00031C08
+#define GPIO_PD7_U1DTR          0x00031C09
+#define GPIO_PD7_EPI0S30        0x00031C0A
+
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+#define GPIO_PE0_EPI0S8         0x00040008
+#define GPIO_PE0_USB0PFLT       0x00040009
+
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+#define GPIO_PE1_EPI0S9         0x00040408
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_CCP2           0x00040805
+#define GPIO_PE2_EPI0S24        0x00040808
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_CCP7           0x00040C05
+#define GPIO_PE3_EPI0S25        0x00040C08
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+#define GPIO_PE4_I2S0TXWS       0x00041009
+
+#define GPIO_PE5_CCP5           0x00041401
+#define GPIO_PE5_I2S0TXSD       0x00041409
+
+#define GPIO_PE6_C1O            0x00041802
+#define GPIO_PE6_U1CTS          0x00041809
+
+#define GPIO_PE7_C2O            0x00041C02
+#define GPIO_PE7_U1DCD          0x00041C09
+
+#define GPIO_PF0_CAN1RX         0x00050001
+#define GPIO_PF0_I2S0TXSD       0x00050008
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_CAN1TX         0x00050401
+#define GPIO_PF1_I2S0TXMCLK     0x00050408
+#define GPIO_PF1_U1RTS          0x00050409
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_LED1           0x00050801
+#define GPIO_PF2_SSI1CLK        0x00050809
+
+#define GPIO_PF3_LED0           0x00050C01
+#define GPIO_PF3_SSI1FSS        0x00050C09
+
+#define GPIO_PF4_CCP0           0x00051001
+#define GPIO_PF4_C0O            0x00051002
+#define GPIO_PF4_EPI0S12        0x00051008
+#define GPIO_PF4_SSI1RX         0x00051009
+
+#define GPIO_PF5_CCP2           0x00051401
+#define GPIO_PF5_C1O            0x00051402
+#define GPIO_PF5_EPI0S15        0x00051408
+#define GPIO_PF5_SSI1TX         0x00051409
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_I2C1SCL        0x00060003
+#define GPIO_PG0_USB0EPEN       0x00060007
+#define GPIO_PG0_EPI0S13        0x00060008
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_I2C1SDA        0x00060403
+#define GPIO_PG1_EPI0S14        0x00060408
+
+#define GPIO_PG7_CCP5           0x00061C08
+#define GPIO_PG7_EPI0S31        0x00061C09
+
+#define GPIO_PH0_CCP6           0x00070001
+#define GPIO_PH0_EPI0S6         0x00070008
+
+#define GPIO_PH1_CCP7           0x00070401
+#define GPIO_PH1_EPI0S7         0x00070408
+
+#define GPIO_PH2_C1O            0x00070802
+#define GPIO_PH2_EPI0S1         0x00070808
+
+#define GPIO_PH3_USB0EPEN       0x00070C04
+#define GPIO_PH3_EPI0S0         0x00070C08
+
+#define GPIO_PH4_USB0PFLT       0x00071004
+#define GPIO_PH4_EPI0S10        0x00071008
+#define GPIO_PH4_SSI1CLK        0x0007100B
+
+#define GPIO_PH5_EPI0S11        0x00071408
+#define GPIO_PH5_SSI1FSS        0x0007140B
+
+#define GPIO_PH6_EPI0S26        0x00071808
+#define GPIO_PH6_SSI1RX         0x0007180B
+
+#define GPIO_PH7_EPI0S27        0x00071C08
+#define GPIO_PH7_SSI1TX         0x00071C0B
+
+#define GPIO_PJ0_EPI0S16        0x00080008
+#define GPIO_PJ0_I2C1SCL        0x0008000B
+
+#define GPIO_PJ1_EPI0S17        0x00080408
+#define GPIO_PJ1_USB0PFLT       0x00080409
+#define GPIO_PJ1_I2C1SDA        0x0008040B
+
+#define GPIO_PJ2_EPI0S18        0x00080808
+#define GPIO_PJ2_CCP0           0x00080809
+
+#endif // PART_LM3S9U90
+
+//*****************************************************************************
+//
+// LM3S9U92 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S9U92
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_PWM4           0x00000804
+#define GPIO_PA2_I2S0RXSD       0x00000809
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_PWM5           0x00000C04
+#define GPIO_PA3_I2S0RXMCLK     0x00000C09
+
+#define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_PWM6           0x00001004
+#define GPIO_PA4_CAN0RX         0x00001005
+#define GPIO_PA4_I2S0TXSCK      0x00001009
+
+#define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_PWM7           0x00001404
+#define GPIO_PA5_CAN0TX         0x00001405
+#define GPIO_PA5_I2S0TXWS       0x00001409
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_PWM0           0x00001804
+#define GPIO_PA6_PWM4           0x00001805
+#define GPIO_PA6_CAN0RX         0x00001806
+#define GPIO_PA6_USB0EPEN       0x00001808
+#define GPIO_PA6_U1CTS          0x00001809
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_PWM1           0x00001C04
+#define GPIO_PA7_PWM5           0x00001C05
+#define GPIO_PA7_CAN0TX         0x00001C06
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_USB0PFLT       0x00001C08
+#define GPIO_PA7_U1DCD          0x00001C09
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_PWM2           0x00010002
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_PWM3           0x00010402
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_IDX0           0x00010802
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+#define GPIO_PB2_USB0EPEN       0x00010808
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_FAULT0         0x00010C02
+#define GPIO_PB3_FAULT3         0x00010C04
+#define GPIO_PB3_USB0PFLT       0x00010C08
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_CAN0RX         0x00011005
+#define GPIO_PB4_IDX0           0x00011006
+#define GPIO_PB4_U1RX           0x00011007
+#define GPIO_PB4_EPI0S23        0x00011008
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CAN0TX         0x00011405
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+#define GPIO_PB5_EPI0S22        0x00011408
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_FAULT1         0x00011804
+#define GPIO_PB6_IDX0           0x00011805
+#define GPIO_PB6_CCP5           0x00011806
+#define GPIO_PB6_I2S0TXSCK      0x00011809
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_PHA0           0x00021002
+#define GPIO_PC4_PWM6           0x00021004
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_EPI0S2         0x00021008
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_FAULT2         0x00021404
+#define GPIO_PC5_CCP3           0x00021405
+#define GPIO_PC5_USB0EPEN       0x00021406
+#define GPIO_PC5_EPI0S3         0x00021408
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_PHB0           0x00021802
+#define GPIO_PC6_C2O            0x00021803
+#define GPIO_PC6_PWM7           0x00021804
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+#define GPIO_PC6_USB0PFLT       0x00021807
+#define GPIO_PC6_EPI0S4         0x00021808
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_PHB0           0x00021C02
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_USB0PFLT       0x00021C06
+#define GPIO_PC7_C1O            0x00021C07
+#define GPIO_PC7_EPI0S5         0x00021C08
+
+#define GPIO_PD0_PWM0           0x00030001
+#define GPIO_PD0_CAN0RX         0x00030002
+#define GPIO_PD0_IDX0           0x00030003
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+#define GPIO_PD0_I2S0RXSCK      0x00030008
+#define GPIO_PD0_U1CTS          0x00030009
+
+#define GPIO_PD1_PWM1           0x00030401
+#define GPIO_PD1_CAN0TX         0x00030402
+#define GPIO_PD1_PHA0           0x00030403
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_I2S0RXWS       0x00030408
+#define GPIO_PD1_U1DCD          0x00030409
+#define GPIO_PD1_CCP2           0x0003040A
+#define GPIO_PD1_PHB1           0x0003040B
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_PWM2           0x00030803
+#define GPIO_PD2_CCP5           0x00030804
+#define GPIO_PD2_EPI0S20        0x00030808
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_PWM3           0x00030C03
+#define GPIO_PD3_CCP0           0x00030C04
+#define GPIO_PD3_EPI0S21        0x00030C08
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+#define GPIO_PD4_I2S0RXSD       0x00031008
+#define GPIO_PD4_U1RI           0x00031009
+#define GPIO_PD4_EPI0S19        0x0003100A
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_I2S0RXMCLK     0x00031408
+#define GPIO_PD5_U2RX           0x00031409
+#define GPIO_PD5_EPI0S28        0x0003140A
+
+#define GPIO_PD6_FAULT0         0x00031801
+#define GPIO_PD6_I2S0TXSCK      0x00031808
+#define GPIO_PD6_U2TX           0x00031809
+#define GPIO_PD6_EPI0S29        0x0003180A
+
+#define GPIO_PD7_IDX0           0x00031C01
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+#define GPIO_PD7_I2S0TXWS       0x00031C08
+#define GPIO_PD7_U1DTR          0x00031C09
+#define GPIO_PD7_EPI0S30        0x00031C0A
+
+#define GPIO_PE0_PWM4           0x00040001
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+#define GPIO_PE0_EPI0S8         0x00040008
+#define GPIO_PE0_USB0PFLT       0x00040009
+
+#define GPIO_PE1_PWM5           0x00040401
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_FAULT0         0x00040403
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+#define GPIO_PE1_EPI0S9         0x00040408
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_PHB1           0x00040803
+#define GPIO_PE2_PHA0           0x00040804
+#define GPIO_PE2_CCP2           0x00040805
+#define GPIO_PE2_EPI0S24        0x00040808
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_PHA1           0x00040C03
+#define GPIO_PE3_PHB0           0x00040C04
+#define GPIO_PE3_CCP7           0x00040C05
+#define GPIO_PE3_EPI0S25        0x00040C08
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_FAULT0         0x00041004
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+#define GPIO_PE4_I2S0TXWS       0x00041009
+
+#define GPIO_PE5_CCP5           0x00041401
+#define GPIO_PE5_I2S0TXSD       0x00041409
+
+#define GPIO_PE6_PWM4           0x00041801
+#define GPIO_PE6_C1O            0x00041802
+#define GPIO_PE6_U1CTS          0x00041809
+
+#define GPIO_PE7_PWM5           0x00041C01
+#define GPIO_PE7_C2O            0x00041C02
+#define GPIO_PE7_U1DCD          0x00041C09
+
+#define GPIO_PF0_CAN1RX         0x00050001
+#define GPIO_PF0_PHB0           0x00050002
+#define GPIO_PF0_PWM0           0x00050003
+#define GPIO_PF0_I2S0TXSD       0x00050008
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_CAN1TX         0x00050401
+#define GPIO_PF1_IDX1           0x00050402
+#define GPIO_PF1_PWM1           0x00050403
+#define GPIO_PF1_I2S0TXMCLK     0x00050408
+#define GPIO_PF1_U1RTS          0x00050409
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_LED1           0x00050801
+#define GPIO_PF2_PWM4           0x00050802
+#define GPIO_PF2_PWM2           0x00050804
+#define GPIO_PF2_SSI1CLK        0x00050809
+
+#define GPIO_PF3_LED0           0x00050C01
+#define GPIO_PF3_PWM5           0x00050C02
+#define GPIO_PF3_PWM3           0x00050C04
+#define GPIO_PF3_SSI1FSS        0x00050C09
+
+#define GPIO_PF4_CCP0           0x00051001
+#define GPIO_PF4_C0O            0x00051002
+#define GPIO_PF4_FAULT0         0x00051004
+#define GPIO_PF4_EPI0S12        0x00051008
+#define GPIO_PF4_SSI1RX         0x00051009
+
+#define GPIO_PF5_CCP2           0x00051401
+#define GPIO_PF5_C1O            0x00051402
+#define GPIO_PF5_EPI0S15        0x00051408
+#define GPIO_PF5_SSI1TX         0x00051409
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_PWM0           0x00060002
+#define GPIO_PG0_I2C1SCL        0x00060003
+#define GPIO_PG0_PWM4           0x00060004
+#define GPIO_PG0_USB0EPEN       0x00060007
+#define GPIO_PG0_EPI0S13        0x00060008
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_PWM1           0x00060402
+#define GPIO_PG1_I2C1SDA        0x00060403
+#define GPIO_PG1_PWM5           0x00060404
+#define GPIO_PG1_EPI0S14        0x00060408
+
+#define GPIO_PG7_PHB1           0x00061C01
+#define GPIO_PG7_PWM7           0x00061C04
+#define GPIO_PG7_CCP5           0x00061C08
+#define GPIO_PG7_EPI0S31        0x00061C09
+
+#define GPIO_PH0_CCP6           0x00070001
+#define GPIO_PH0_PWM2           0x00070002
+#define GPIO_PH0_EPI0S6         0x00070008
+#define GPIO_PH0_PWM4           0x00070009
+
+#define GPIO_PH1_CCP7           0x00070401
+#define GPIO_PH1_PWM3           0x00070402
+#define GPIO_PH1_EPI0S7         0x00070408
+#define GPIO_PH1_PWM5           0x00070409
+
+#define GPIO_PH2_IDX1           0x00070801
+#define GPIO_PH2_C1O            0x00070802
+#define GPIO_PH2_FAULT3         0x00070804
+#define GPIO_PH2_EPI0S1         0x00070808
+
+#define GPIO_PH3_PHB0           0x00070C01
+#define GPIO_PH3_FAULT0         0x00070C02
+#define GPIO_PH3_USB0EPEN       0x00070C04
+#define GPIO_PH3_EPI0S0         0x00070C08
+
+#define GPIO_PH4_USB0PFLT       0x00071004
+#define GPIO_PH4_EPI0S10        0x00071008
+#define GPIO_PH4_SSI1CLK        0x0007100B
+
+#define GPIO_PH5_EPI0S11        0x00071408
+#define GPIO_PH5_FAULT2         0x0007140A
+#define GPIO_PH5_SSI1FSS        0x0007140B
+
+#define GPIO_PH6_EPI0S26        0x00071808
+#define GPIO_PH6_PWM4           0x0007180A
+#define GPIO_PH6_SSI1RX         0x0007180B
+
+#define GPIO_PH7_EPI0S27        0x00071C08
+#define GPIO_PH7_PWM5           0x00071C0A
+#define GPIO_PH7_SSI1TX         0x00071C0B
+
+#define GPIO_PJ0_EPI0S16        0x00080008
+#define GPIO_PJ0_PWM0           0x0008000A
+#define GPIO_PJ0_I2C1SCL        0x0008000B
+
+#define GPIO_PJ1_EPI0S17        0x00080408
+#define GPIO_PJ1_USB0PFLT       0x00080409
+#define GPIO_PJ1_PWM1           0x0008040A
+#define GPIO_PJ1_I2C1SDA        0x0008040B
+
+#define GPIO_PJ2_EPI0S18        0x00080808
+#define GPIO_PJ2_CCP0           0x00080809
+#define GPIO_PJ2_FAULT0         0x0008080A
+
+#define GPIO_PJ3_EPI0S19        0x00080C08
+#define GPIO_PJ3_U1CTS          0x00080C09
+#define GPIO_PJ3_CCP6           0x00080C0A
+
+#define GPIO_PJ4_EPI0S28        0x00081008
+#define GPIO_PJ4_U1DCD          0x00081009
+#define GPIO_PJ4_CCP4           0x0008100A
+
+#define GPIO_PJ5_EPI0S29        0x00081408
+#define GPIO_PJ5_U1DSR          0x00081409
+#define GPIO_PJ5_CCP2           0x0008140A
+
+#define GPIO_PJ6_EPI0S30        0x00081808
+#define GPIO_PJ6_U1RTS          0x00081809
+#define GPIO_PJ6_CCP1           0x0008180A
+
+#define GPIO_PJ7_U1DTR          0x00081C09
+#define GPIO_PJ7_CCP0           0x00081C0A
+
+#endif // PART_LM3S9U92
+
+//*****************************************************************************
+//
+// LM3S9U95 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S9U95
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_PWM4           0x00000804
+#define GPIO_PA2_I2S0RXSD       0x00000809
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_PWM5           0x00000C04
+#define GPIO_PA3_I2S0RXMCLK     0x00000C09
+
+#define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_PWM6           0x00001004
+#define GPIO_PA4_CAN0RX         0x00001005
+#define GPIO_PA4_I2S0TXSCK      0x00001009
+
+#define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_PWM7           0x00001404
+#define GPIO_PA5_CAN0TX         0x00001405
+#define GPIO_PA5_I2S0TXWS       0x00001409
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_PWM0           0x00001804
+#define GPIO_PA6_PWM4           0x00001805
+#define GPIO_PA6_CAN0RX         0x00001806
+#define GPIO_PA6_USB0EPEN       0x00001808
+#define GPIO_PA6_U1CTS          0x00001809
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_PWM1           0x00001C04
+#define GPIO_PA7_PWM5           0x00001C05
+#define GPIO_PA7_CAN0TX         0x00001C06
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_USB0PFLT       0x00001C08
+#define GPIO_PA7_U1DCD          0x00001C09
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_PWM2           0x00010002
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_PWM3           0x00010402
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_IDX0           0x00010802
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+#define GPIO_PB2_USB0EPEN       0x00010808
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_FAULT0         0x00010C02
+#define GPIO_PB3_FAULT3         0x00010C04
+#define GPIO_PB3_USB0PFLT       0x00010C08
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_CAN0RX         0x00011005
+#define GPIO_PB4_IDX0           0x00011006
+#define GPIO_PB4_U1RX           0x00011007
+#define GPIO_PB4_EPI0S23        0x00011008
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CAN0TX         0x00011405
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+#define GPIO_PB5_EPI0S22        0x00011408
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_FAULT1         0x00011804
+#define GPIO_PB6_IDX0           0x00011805
+#define GPIO_PB6_CCP5           0x00011806
+#define GPIO_PB6_I2S0TXSCK      0x00011809
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_PHA0           0x00021002
+#define GPIO_PC4_PWM6           0x00021004
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_EPI0S2         0x00021008
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_FAULT2         0x00021404
+#define GPIO_PC5_CCP3           0x00021405
+#define GPIO_PC5_USB0EPEN       0x00021406
+#define GPIO_PC5_EPI0S3         0x00021408
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_PHB0           0x00021802
+#define GPIO_PC6_C2O            0x00021803
+#define GPIO_PC6_PWM7           0x00021804
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+#define GPIO_PC6_USB0PFLT       0x00021807
+#define GPIO_PC6_EPI0S4         0x00021808
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_PHB0           0x00021C02
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_USB0PFLT       0x00021C06
+#define GPIO_PC7_C1O            0x00021C07
+#define GPIO_PC7_EPI0S5         0x00021C08
+
+#define GPIO_PD0_PWM0           0x00030001
+#define GPIO_PD0_CAN0RX         0x00030002
+#define GPIO_PD0_IDX0           0x00030003
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+#define GPIO_PD0_I2S0RXSCK      0x00030008
+#define GPIO_PD0_U1CTS          0x00030009
+
+#define GPIO_PD1_PWM1           0x00030401
+#define GPIO_PD1_CAN0TX         0x00030402
+#define GPIO_PD1_PHA0           0x00030403
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_I2S0RXWS       0x00030408
+#define GPIO_PD1_U1DCD          0x00030409
+#define GPIO_PD1_CCP2           0x0003040A
+#define GPIO_PD1_PHB1           0x0003040B
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_PWM2           0x00030803
+#define GPIO_PD2_CCP5           0x00030804
+#define GPIO_PD2_EPI0S20        0x00030808
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_PWM3           0x00030C03
+#define GPIO_PD3_CCP0           0x00030C04
+#define GPIO_PD3_EPI0S21        0x00030C08
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+#define GPIO_PD4_I2S0RXSD       0x00031008
+#define GPIO_PD4_U1RI           0x00031009
+#define GPIO_PD4_EPI0S19        0x0003100A
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_I2S0RXMCLK     0x00031408
+#define GPIO_PD5_U2RX           0x00031409
+#define GPIO_PD5_EPI0S28        0x0003140A
+
+#define GPIO_PD6_FAULT0         0x00031801
+#define GPIO_PD6_I2S0TXSCK      0x00031808
+#define GPIO_PD6_U2TX           0x00031809
+#define GPIO_PD6_EPI0S29        0x0003180A
+
+#define GPIO_PD7_IDX0           0x00031C01
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+#define GPIO_PD7_I2S0TXWS       0x00031C08
+#define GPIO_PD7_U1DTR          0x00031C09
+#define GPIO_PD7_EPI0S30        0x00031C0A
+
+#define GPIO_PE0_PWM4           0x00040001
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+#define GPIO_PE0_EPI0S8         0x00040008
+#define GPIO_PE0_USB0PFLT       0x00040009
+
+#define GPIO_PE1_PWM5           0x00040401
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_FAULT0         0x00040403
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+#define GPIO_PE1_EPI0S9         0x00040408
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_PHB1           0x00040803
+#define GPIO_PE2_PHA0           0x00040804
+#define GPIO_PE2_CCP2           0x00040805
+#define GPIO_PE2_EPI0S24        0x00040808
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_PHA1           0x00040C03
+#define GPIO_PE3_PHB0           0x00040C04
+#define GPIO_PE3_CCP7           0x00040C05
+#define GPIO_PE3_EPI0S25        0x00040C08
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_FAULT0         0x00041004
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+#define GPIO_PE4_I2S0TXWS       0x00041009
+
+#define GPIO_PE5_CCP5           0x00041401
+#define GPIO_PE5_I2S0TXSD       0x00041409
+
+#define GPIO_PE6_PWM4           0x00041801
+#define GPIO_PE6_C1O            0x00041802
+#define GPIO_PE6_U1CTS          0x00041809
+
+#define GPIO_PE7_PWM5           0x00041C01
+#define GPIO_PE7_C2O            0x00041C02
+#define GPIO_PE7_U1DCD          0x00041C09
+
+#define GPIO_PF0_CAN1RX         0x00050001
+#define GPIO_PF0_PHB0           0x00050002
+#define GPIO_PF0_PWM0           0x00050003
+#define GPIO_PF0_I2S0TXSD       0x00050008
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_CAN1TX         0x00050401
+#define GPIO_PF1_IDX1           0x00050402
+#define GPIO_PF1_PWM1           0x00050403
+#define GPIO_PF1_I2S0TXMCLK     0x00050408
+#define GPIO_PF1_U1RTS          0x00050409
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_LED1           0x00050801
+#define GPIO_PF2_PWM4           0x00050802
+#define GPIO_PF2_PWM2           0x00050804
+#define GPIO_PF2_SSI1CLK        0x00050809
+
+#define GPIO_PF3_LED0           0x00050C01
+#define GPIO_PF3_PWM5           0x00050C02
+#define GPIO_PF3_PWM3           0x00050C04
+#define GPIO_PF3_SSI1FSS        0x00050C09
+
+#define GPIO_PF4_CCP0           0x00051001
+#define GPIO_PF4_C0O            0x00051002
+#define GPIO_PF4_FAULT0         0x00051004
+#define GPIO_PF4_EPI0S12        0x00051008
+#define GPIO_PF4_SSI1RX         0x00051009
+
+#define GPIO_PF5_CCP2           0x00051401
+#define GPIO_PF5_C1O            0x00051402
+#define GPIO_PF5_EPI0S15        0x00051408
+#define GPIO_PF5_SSI1TX         0x00051409
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_PWM0           0x00060002
+#define GPIO_PG0_I2C1SCL        0x00060003
+#define GPIO_PG0_PWM4           0x00060004
+#define GPIO_PG0_USB0EPEN       0x00060007
+#define GPIO_PG0_EPI0S13        0x00060008
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_PWM1           0x00060402
+#define GPIO_PG1_I2C1SDA        0x00060403
+#define GPIO_PG1_PWM5           0x00060404
+#define GPIO_PG1_EPI0S14        0x00060408
+
+#define GPIO_PG7_PHB1           0x00061C01
+#define GPIO_PG7_PWM7           0x00061C04
+#define GPIO_PG7_CCP5           0x00061C08
+#define GPIO_PG7_EPI0S31        0x00061C09
+
+#define GPIO_PH0_CCP6           0x00070001
+#define GPIO_PH0_PWM2           0x00070002
+#define GPIO_PH0_EPI0S6         0x00070008
+#define GPIO_PH0_PWM4           0x00070009
+
+#define GPIO_PH1_CCP7           0x00070401
+#define GPIO_PH1_PWM3           0x00070402
+#define GPIO_PH1_EPI0S7         0x00070408
+#define GPIO_PH1_PWM5           0x00070409
+
+#define GPIO_PH2_IDX1           0x00070801
+#define GPIO_PH2_C1O            0x00070802
+#define GPIO_PH2_FAULT3         0x00070804
+#define GPIO_PH2_EPI0S1         0x00070808
+
+#define GPIO_PH3_PHB0           0x00070C01
+#define GPIO_PH3_FAULT0         0x00070C02
+#define GPIO_PH3_USB0EPEN       0x00070C04
+#define GPIO_PH3_EPI0S0         0x00070C08
+
+#define GPIO_PH4_USB0PFLT       0x00071004
+#define GPIO_PH4_EPI0S10        0x00071008
+#define GPIO_PH4_SSI1CLK        0x0007100B
+
+#define GPIO_PH5_EPI0S11        0x00071408
+#define GPIO_PH5_FAULT2         0x0007140A
+#define GPIO_PH5_SSI1FSS        0x0007140B
+
+#define GPIO_PH6_EPI0S26        0x00071808
+#define GPIO_PH6_PWM4           0x0007180A
+#define GPIO_PH6_SSI1RX         0x0007180B
+
+#define GPIO_PH7_EPI0S27        0x00071C08
+#define GPIO_PH7_PWM5           0x00071C0A
+#define GPIO_PH7_SSI1TX         0x00071C0B
+
+#define GPIO_PJ0_EPI0S16        0x00080008
+#define GPIO_PJ0_PWM0           0x0008000A
+#define GPIO_PJ0_I2C1SCL        0x0008000B
+
+#define GPIO_PJ1_EPI0S17        0x00080408
+#define GPIO_PJ1_USB0PFLT       0x00080409
+#define GPIO_PJ1_PWM1           0x0008040A
+#define GPIO_PJ1_I2C1SDA        0x0008040B
+
+#define GPIO_PJ2_EPI0S18        0x00080808
+#define GPIO_PJ2_CCP0           0x00080809
+#define GPIO_PJ2_FAULT0         0x0008080A
+
+#define GPIO_PJ3_EPI0S19        0x00080C08
+#define GPIO_PJ3_U1CTS          0x00080C09
+#define GPIO_PJ3_CCP6           0x00080C0A
+
+#define GPIO_PJ4_EPI0S28        0x00081008
+#define GPIO_PJ4_U1DCD          0x00081009
+#define GPIO_PJ4_CCP4           0x0008100A
+
+#define GPIO_PJ5_EPI0S29        0x00081408
+#define GPIO_PJ5_U1DSR          0x00081409
+#define GPIO_PJ5_CCP2           0x0008140A
+
+#define GPIO_PJ6_EPI0S30        0x00081808
+#define GPIO_PJ6_U1RTS          0x00081809
+#define GPIO_PJ6_CCP1           0x0008180A
+
+#define GPIO_PJ7_U1DTR          0x00081C09
+#define GPIO_PJ7_CCP0           0x00081C0A
+
+#endif // PART_LM3S9U95
+
+//*****************************************************************************
+//
+// LM3S9U96 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S9U96
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_I2C1SCL        0x00000008
+#define GPIO_PA0_U1RX           0x00000009
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_I2C1SDA        0x00000408
+#define GPIO_PA1_U1TX           0x00000409
+
+#define GPIO_PA2_SSI0CLK        0x00000801
+#define GPIO_PA2_PWM4           0x00000804
+#define GPIO_PA2_I2S0RXSD       0x00000809
+
+#define GPIO_PA3_SSI0FSS        0x00000C01
+#define GPIO_PA3_PWM5           0x00000C04
+#define GPIO_PA3_I2S0RXMCLK     0x00000C09
+
+#define GPIO_PA4_SSI0RX         0x00001001
+#define GPIO_PA4_PWM6           0x00001004
+#define GPIO_PA4_CAN0RX         0x00001005
+#define GPIO_PA4_I2S0TXSCK      0x00001009
+
+#define GPIO_PA5_SSI0TX         0x00001401
+#define GPIO_PA5_PWM7           0x00001404
+#define GPIO_PA5_CAN0TX         0x00001405
+#define GPIO_PA5_I2S0TXWS       0x00001409
+
+#define GPIO_PA6_I2C1SCL        0x00001801
+#define GPIO_PA6_CCP1           0x00001802
+#define GPIO_PA6_PWM0           0x00001804
+#define GPIO_PA6_PWM4           0x00001805
+#define GPIO_PA6_CAN0RX         0x00001806
+#define GPIO_PA6_USB0EPEN       0x00001808
+#define GPIO_PA6_U1CTS          0x00001809
+
+#define GPIO_PA7_I2C1SDA        0x00001C01
+#define GPIO_PA7_CCP4           0x00001C02
+#define GPIO_PA7_PWM1           0x00001C04
+#define GPIO_PA7_PWM5           0x00001C05
+#define GPIO_PA7_CAN0TX         0x00001C06
+#define GPIO_PA7_CCP3           0x00001C07
+#define GPIO_PA7_USB0PFLT       0x00001C08
+#define GPIO_PA7_U1DCD          0x00001C09
+
+#define GPIO_PB0_CCP0           0x00010001
+#define GPIO_PB0_PWM2           0x00010002
+#define GPIO_PB0_U1RX           0x00010005
+
+#define GPIO_PB1_CCP2           0x00010401
+#define GPIO_PB1_PWM3           0x00010402
+#define GPIO_PB1_CCP1           0x00010404
+#define GPIO_PB1_U1TX           0x00010405
+
+#define GPIO_PB2_I2C0SCL        0x00010801
+#define GPIO_PB2_IDX0           0x00010802
+#define GPIO_PB2_CCP3           0x00010804
+#define GPIO_PB2_CCP0           0x00010805
+#define GPIO_PB2_USB0EPEN       0x00010808
+
+#define GPIO_PB3_I2C0SDA        0x00010C01
+#define GPIO_PB3_FAULT0         0x00010C02
+#define GPIO_PB3_FAULT3         0x00010C04
+#define GPIO_PB3_USB0PFLT       0x00010C08
+
+#define GPIO_PB4_U2RX           0x00011004
+#define GPIO_PB4_CAN0RX         0x00011005
+#define GPIO_PB4_IDX0           0x00011006
+#define GPIO_PB4_U1RX           0x00011007
+#define GPIO_PB4_EPI0S23        0x00011008
+
+#define GPIO_PB5_C0O            0x00011401
+#define GPIO_PB5_CCP5           0x00011402
+#define GPIO_PB5_CCP6           0x00011403
+#define GPIO_PB5_CCP0           0x00011404
+#define GPIO_PB5_CAN0TX         0x00011405
+#define GPIO_PB5_CCP2           0x00011406
+#define GPIO_PB5_U1TX           0x00011407
+#define GPIO_PB5_EPI0S22        0x00011408
+
+#define GPIO_PB6_CCP1           0x00011801
+#define GPIO_PB6_CCP7           0x00011802
+#define GPIO_PB6_C0O            0x00011803
+#define GPIO_PB6_FAULT1         0x00011804
+#define GPIO_PB6_IDX0           0x00011805
+#define GPIO_PB6_CCP5           0x00011806
+#define GPIO_PB6_I2S0TXSCK      0x00011809
+
+#define GPIO_PB7_NMI            0x00011C04
+
+#define GPIO_PC0_TCK            0x00020003
+#define GPIO_PC0_SWCLK          0x00020003
+
+#define GPIO_PC1_TMS            0x00020403
+#define GPIO_PC1_SWDIO          0x00020403
+
+#define GPIO_PC2_TDI            0x00020803
+
+#define GPIO_PC3_SWO            0x00020C03
+#define GPIO_PC3_TDO            0x00020C03
+
+#define GPIO_PC4_CCP5           0x00021001
+#define GPIO_PC4_PHA0           0x00021002
+#define GPIO_PC4_PWM6           0x00021004
+#define GPIO_PC4_CCP2           0x00021005
+#define GPIO_PC4_CCP4           0x00021006
+#define GPIO_PC4_EPI0S2         0x00021008
+#define GPIO_PC4_CCP1           0x00021009
+
+#define GPIO_PC5_CCP1           0x00021401
+#define GPIO_PC5_C1O            0x00021402
+#define GPIO_PC5_C0O            0x00021403
+#define GPIO_PC5_FAULT2         0x00021404
+#define GPIO_PC5_CCP3           0x00021405
+#define GPIO_PC5_USB0EPEN       0x00021406
+#define GPIO_PC5_EPI0S3         0x00021408
+
+#define GPIO_PC6_CCP3           0x00021801
+#define GPIO_PC6_PHB0           0x00021802
+#define GPIO_PC6_C2O            0x00021803
+#define GPIO_PC6_PWM7           0x00021804
+#define GPIO_PC6_U1RX           0x00021805
+#define GPIO_PC6_CCP0           0x00021806
+#define GPIO_PC6_USB0PFLT       0x00021807
+#define GPIO_PC6_EPI0S4         0x00021808
+
+#define GPIO_PC7_CCP4           0x00021C01
+#define GPIO_PC7_PHB0           0x00021C02
+#define GPIO_PC7_CCP0           0x00021C04
+#define GPIO_PC7_U1TX           0x00021C05
+#define GPIO_PC7_USB0PFLT       0x00021C06
+#define GPIO_PC7_C1O            0x00021C07
+#define GPIO_PC7_EPI0S5         0x00021C08
+
+#define GPIO_PD0_PWM0           0x00030001
+#define GPIO_PD0_CAN0RX         0x00030002
+#define GPIO_PD0_IDX0           0x00030003
+#define GPIO_PD0_U2RX           0x00030004
+#define GPIO_PD0_U1RX           0x00030005
+#define GPIO_PD0_CCP6           0x00030006
+#define GPIO_PD0_I2S0RXSCK      0x00030008
+#define GPIO_PD0_U1CTS          0x00030009
+
+#define GPIO_PD1_PWM1           0x00030401
+#define GPIO_PD1_CAN0TX         0x00030402
+#define GPIO_PD1_PHA0           0x00030403
+#define GPIO_PD1_U2TX           0x00030404
+#define GPIO_PD1_U1TX           0x00030405
+#define GPIO_PD1_CCP7           0x00030406
+#define GPIO_PD1_I2S0RXWS       0x00030408
+#define GPIO_PD1_U1DCD          0x00030409
+#define GPIO_PD1_CCP2           0x0003040A
+#define GPIO_PD1_PHB1           0x0003040B
+
+#define GPIO_PD2_U1RX           0x00030801
+#define GPIO_PD2_CCP6           0x00030802
+#define GPIO_PD2_PWM2           0x00030803
+#define GPIO_PD2_CCP5           0x00030804
+#define GPIO_PD2_EPI0S20        0x00030808
+
+#define GPIO_PD3_U1TX           0x00030C01
+#define GPIO_PD3_CCP7           0x00030C02
+#define GPIO_PD3_PWM3           0x00030C03
+#define GPIO_PD3_CCP0           0x00030C04
+#define GPIO_PD3_EPI0S21        0x00030C08
+
+#define GPIO_PD4_CCP0           0x00031001
+#define GPIO_PD4_CCP3           0x00031002
+#define GPIO_PD4_I2S0RXSD       0x00031008
+#define GPIO_PD4_U1RI           0x00031009
+#define GPIO_PD4_EPI0S19        0x0003100A
+
+#define GPIO_PD5_CCP2           0x00031401
+#define GPIO_PD5_CCP4           0x00031402
+#define GPIO_PD5_I2S0RXMCLK     0x00031408
+#define GPIO_PD5_U2RX           0x00031409
+#define GPIO_PD5_EPI0S28        0x0003140A
+
+#define GPIO_PD6_FAULT0         0x00031801
+#define GPIO_PD6_I2S0TXSCK      0x00031808
+#define GPIO_PD6_U2TX           0x00031809
+#define GPIO_PD6_EPI0S29        0x0003180A
+
+#define GPIO_PD7_IDX0           0x00031C01
+#define GPIO_PD7_C0O            0x00031C02
+#define GPIO_PD7_CCP1           0x00031C03
+#define GPIO_PD7_I2S0TXWS       0x00031C08
+#define GPIO_PD7_U1DTR          0x00031C09
+#define GPIO_PD7_EPI0S30        0x00031C0A
+
+#define GPIO_PE0_PWM4           0x00040001
+#define GPIO_PE0_SSI1CLK        0x00040002
+#define GPIO_PE0_CCP3           0x00040003
+#define GPIO_PE0_EPI0S8         0x00040008
+#define GPIO_PE0_USB0PFLT       0x00040009
+
+#define GPIO_PE1_PWM5           0x00040401
+#define GPIO_PE1_SSI1FSS        0x00040402
+#define GPIO_PE1_FAULT0         0x00040403
+#define GPIO_PE1_CCP2           0x00040404
+#define GPIO_PE1_CCP6           0x00040405
+#define GPIO_PE1_EPI0S9         0x00040408
+
+#define GPIO_PE2_CCP4           0x00040801
+#define GPIO_PE2_SSI1RX         0x00040802
+#define GPIO_PE2_PHB1           0x00040803
+#define GPIO_PE2_PHA0           0x00040804
+#define GPIO_PE2_CCP2           0x00040805
+#define GPIO_PE2_EPI0S24        0x00040808
+
+#define GPIO_PE3_CCP1           0x00040C01
+#define GPIO_PE3_SSI1TX         0x00040C02
+#define GPIO_PE3_PHA1           0x00040C03
+#define GPIO_PE3_PHB0           0x00040C04
+#define GPIO_PE3_CCP7           0x00040C05
+#define GPIO_PE3_EPI0S25        0x00040C08
+
+#define GPIO_PE4_CCP3           0x00041001
+#define GPIO_PE4_FAULT0         0x00041004
+#define GPIO_PE4_U2TX           0x00041005
+#define GPIO_PE4_CCP2           0x00041006
+#define GPIO_PE4_I2S0TXWS       0x00041009
+
+#define GPIO_PE5_CCP5           0x00041401
+#define GPIO_PE5_I2S0TXSD       0x00041409
+
+#define GPIO_PE6_PWM4           0x00041801
+#define GPIO_PE6_C1O            0x00041802
+#define GPIO_PE6_U1CTS          0x00041809
+
+#define GPIO_PE7_PWM5           0x00041C01
+#define GPIO_PE7_C2O            0x00041C02
+#define GPIO_PE7_U1DCD          0x00041C09
+
+#define GPIO_PF0_CAN1RX         0x00050001
+#define GPIO_PF0_PHB0           0x00050002
+#define GPIO_PF0_PWM0           0x00050003
+#define GPIO_PF0_I2S0TXSD       0x00050008
+#define GPIO_PF0_U1DSR          0x00050009
+
+#define GPIO_PF1_CAN1TX         0x00050401
+#define GPIO_PF1_IDX1           0x00050402
+#define GPIO_PF1_PWM1           0x00050403
+#define GPIO_PF1_I2S0TXMCLK     0x00050408
+#define GPIO_PF1_U1RTS          0x00050409
+#define GPIO_PF1_CCP3           0x0005040A
+
+#define GPIO_PF2_LED1           0x00050801
+#define GPIO_PF2_PWM4           0x00050802
+#define GPIO_PF2_PWM2           0x00050804
+#define GPIO_PF2_SSI1CLK        0x00050809
+
+#define GPIO_PF3_LED0           0x00050C01
+#define GPIO_PF3_PWM5           0x00050C02
+#define GPIO_PF3_PWM3           0x00050C04
+#define GPIO_PF3_SSI1FSS        0x00050C09
+
+#define GPIO_PF4_CCP0           0x00051001
+#define GPIO_PF4_C0O            0x00051002
+#define GPIO_PF4_FAULT0         0x00051004
+#define GPIO_PF4_EPI0S12        0x00051008
+#define GPIO_PF4_SSI1RX         0x00051009
+
+#define GPIO_PF5_CCP2           0x00051401
+#define GPIO_PF5_C1O            0x00051402
+#define GPIO_PF5_EPI0S15        0x00051408
+#define GPIO_PF5_SSI1TX         0x00051409
+
+#define GPIO_PG0_U2RX           0x00060001
+#define GPIO_PG0_PWM0           0x00060002
+#define GPIO_PG0_I2C1SCL        0x00060003
+#define GPIO_PG0_PWM4           0x00060004
+#define GPIO_PG0_USB0EPEN       0x00060007
+#define GPIO_PG0_EPI0S13        0x00060008
+
+#define GPIO_PG1_U2TX           0x00060401
+#define GPIO_PG1_PWM1           0x00060402
+#define GPIO_PG1_I2C1SDA        0x00060403
+#define GPIO_PG1_PWM5           0x00060404
+#define GPIO_PG1_EPI0S14        0x00060408
+
+#define GPIO_PG7_PHB1           0x00061C01
+#define GPIO_PG7_PWM7           0x00061C04
+#define GPIO_PG7_CCP5           0x00061C08
+#define GPIO_PG7_EPI0S31        0x00061C09
+
+#define GPIO_PH0_CCP6           0x00070001
+#define GPIO_PH0_PWM2           0x00070002
+#define GPIO_PH0_EPI0S6         0x00070008
+#define GPIO_PH0_PWM4           0x00070009
+
+#define GPIO_PH1_CCP7           0x00070401
+#define GPIO_PH1_PWM3           0x00070402
+#define GPIO_PH1_EPI0S7         0x00070408
+#define GPIO_PH1_PWM5           0x00070409
+
+#define GPIO_PH2_IDX1           0x00070801
+#define GPIO_PH2_C1O            0x00070802
+#define GPIO_PH2_FAULT3         0x00070804
+#define GPIO_PH2_EPI0S1         0x00070808
+
+#define GPIO_PH3_PHB0           0x00070C01
+#define GPIO_PH3_FAULT0         0x00070C02
+#define GPIO_PH3_USB0EPEN       0x00070C04
+#define GPIO_PH3_EPI0S0         0x00070C08
+
+#define GPIO_PH4_USB0PFLT       0x00071004
+#define GPIO_PH4_EPI0S10        0x00071008
+#define GPIO_PH4_SSI1CLK        0x0007100B
+
+#define GPIO_PH5_EPI0S11        0x00071408
+#define GPIO_PH5_FAULT2         0x0007140A
+#define GPIO_PH5_SSI1FSS        0x0007140B
+
+#define GPIO_PH6_EPI0S26        0x00071808
+#define GPIO_PH6_PWM4           0x0007180A
+#define GPIO_PH6_SSI1RX         0x0007180B
+
+#define GPIO_PH7_EPI0S27        0x00071C08
+#define GPIO_PH7_PWM5           0x00071C0A
+#define GPIO_PH7_SSI1TX         0x00071C0B
+
+#define GPIO_PJ0_EPI0S16        0x00080008
+#define GPIO_PJ0_PWM0           0x0008000A
+#define GPIO_PJ0_I2C1SCL        0x0008000B
+
+#define GPIO_PJ1_EPI0S17        0x00080408
+#define GPIO_PJ1_USB0PFLT       0x00080409
+#define GPIO_PJ1_PWM1           0x0008040A
+#define GPIO_PJ1_I2C1SDA        0x0008040B
+
+#define GPIO_PJ2_EPI0S18        0x00080808
+#define GPIO_PJ2_CCP0           0x00080809
+#define GPIO_PJ2_FAULT0         0x0008080A
+
+#define GPIO_PJ3_EPI0S19        0x00080C08
+#define GPIO_PJ3_U1CTS          0x00080C09
+#define GPIO_PJ3_CCP6           0x00080C0A
+
+#define GPIO_PJ4_EPI0S28        0x00081008
+#define GPIO_PJ4_U1DCD          0x00081009
+#define GPIO_PJ4_CCP4           0x0008100A
+
+#define GPIO_PJ5_EPI0S29        0x00081408
+#define GPIO_PJ5_U1DSR          0x00081409
+#define GPIO_PJ5_CCP2           0x0008140A
+
+#define GPIO_PJ6_EPI0S30        0x00081808
+#define GPIO_PJ6_U1RTS          0x00081809
+#define GPIO_PJ6_CCP1           0x0008180A
+
+#define GPIO_PJ7_U1DTR          0x00081C09
+#define GPIO_PJ7_CCP0           0x00081C0A
+
+#endif // PART_LM3S9U96
+
+//*****************************************************************************
+//
+// Pin Mapping Functions
+//
+// This section describes the code that is responsible for handling the
+// mapping of peripheral functions to their physical location on the pins of
+// a device.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Definitions to support mapping GPIO Ports and Pins to their function.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Configures the specified ADC pin to function as an ADC pin.
+//
+// \param ulName is one of the valid names for the ADC pins.
+//
+// This function takes on of the valid names for an ADC pin and configures
+// the pin for its ADC functionality depending on the part that is defined.
+//
+// The valid names for the pins are as follows: \b ADC0, \b ADC1, \b ADC2,
+// \b ADC3, \b ADC4, \b ADC5, \b ADC6, or \b ADC7.
+//
+// \sa GPIOPinTypeADC() in order to configure multiple ADC pins at once.
+//
+// \return None.
+//
+//*****************************************************************************
+#define PinTypeADC(ulName)      GPIOPinTypeADC(ulName##_PORT, ulName##_PIN)
+
+//*****************************************************************************
+//
+// Configures the specified CAN pin to function as a CAN pin.
+//
+// \param ulName is one of the valid names for the CAN pins.
+//
+// This function takes one of the valid names for a CAN pin and configures
+// the pin for its CAN functionality depending on the part that is defined.
+//
+// The valid names for the pins are as follows: \b CAN0RX, \b CAN0TX,
+// \b CAN1RX, \b CAN1TX, \b CAN2RX, or \b CAN2TX.
+//
+// \sa GPIOPinTypeCAN() in order to configure multiple CAN pins at once.
+//
+// \return None.
+//
+//*****************************************************************************
+#define PinTypeCAN(ulName)      GPIOPinTypeCAN(ulName##_PORT, ulName##_PIN)
+
+//*****************************************************************************
+//
+// Configures the specified comparator pin to function as a comparator pin.
+//
+// \param ulName is one of the valid names for the Comparator pins.
+//
+// This function takes one of the valid names for a comparator pin and
+// configures the pin for its comparator functionality depending on the part
+// that is defined.
+//
+// The valid names for the pins are as follows: \b C0_MINUS, \b C0_PLUS,
+// \b C1_MINUS, \b C1_PLUS, \b C2_MINUS, or \b C2_PLUS.
+//
+// \sa GPIOPinTypeComparator() in order to configure multiple comparator pins
+// at once.
+//
+// \return None.
+//
+//*****************************************************************************
+#define PinTypeComparator(ulName)                                    \
+                                GPIOPinTypeComparator(ulName##_PORT, \
+                                                      ulName##_PIN)
+
+//*****************************************************************************
+//
+// Configures the specified I2C pin to function as an I2C pin.
+//
+// \param ulName is one of the valid names for the I2C pins.
+//
+// This function takes one of the valid names for an I2C pin and configures
+// the pin for its I2C functionality depending on the part that is defined.
+//
+// The valid names for the pins are as follows: \b I2C0SCL, \b I2C0SDA,
+// \b I2C1SCL, or \b I2C1SDA.
+//
+// \sa GPIOPinTypeI2C() in order to configure multiple I2C pins at once.
+//
+// \return None.
+//
+//*****************************************************************************
+#define PinTypeI2C(ulName)      GPIOPinTypeI2C(ulName##_PORT, ulName##_PIN)
+
+//*****************************************************************************
+//
+// Configures the specified Ethernet LED to function as an Ethernet LED pin.
+//
+// \param ulName is one of the valid names for the Ethernet LED pins.
+//
+// This function takes one of the valid names for an Ethernet LED pin and
+// configures the pin for its Ethernet LED functionality depending on the part
+// that is defined.
+//
+// The valid names for the pins are as follows: \b LED0 or \b LED1.
+//
+// sa GPIOPinTypeEthernetLED() in order to configure multiple Ethernet LED
+// pins at once.
+//
+// \return None.
+//
+//*****************************************************************************
+#define PinTypeEthernetLED(ulName)                                    \
+                                GPIOPinTypeEthernetLED(ulName##_PORT, \
+                                                       ulName##_PIN)
+
+//*****************************************************************************
+//
+// Configures the specified PWM pin to function as a PWM pin.
+//
+// \param ulName is one of the valid names for the PWM pins.
+//
+// This function takes one of the valid names for a PWM pin and configures
+// the pin for its PWM functionality depending on the part that is defined.
+//
+// The valid names for the pins are as follows: \b PWM0, \b PWM1, \b PWM2,
+// \b PWM3, \b PWM4, \b PWM5, or \b FAULT.
+//
+// \sa GPIOPinTypePWM() in order to configure multiple PWM pins at once.
+//
+// \return None.
+//
+//*****************************************************************************
+#define PinTypePWM(ulName)      GPIOPinTypePWM(ulName##_PORT, ulName##_PIN)
+
+//*****************************************************************************
+//
+// Configures the specified QEI pin to function as a QEI pin.
+//
+// \param ulName is one of the valid names for the QEI pins.
+//
+// This function takes one of the valid names for a QEI pin and configures
+// the pin for its QEI functionality depending on the part that is defined.
+//
+// The valid names for the pins are as follows: \b PHA0, \b PHB0, \b IDX0,
+// \b PHA1, \b PHB1, or \b IDX1.
+//
+// \sa GPIOPinTypeQEI() in order to configure multiple QEI pins at once.
+//
+// \return None.
+//
+//*****************************************************************************
+#define PinTypeQEI(ulName)      GPIOPinTypeQEI(ulName##_PORT, ulName##_PIN)
+
+//*****************************************************************************
+//
+// Configures the specified SSI pin to function as an SSI pin.
+//
+// \param ulName is one of the valid names for the SSI pins.
+//
+// This function takes one of the valid names for an SSI pin and configures
+// the pin for its SSI functionality depending on the part that is defined.
+//
+// The valid names for the pins are as follows: \b SSI0CLK, \b SSI0FSS,
+// \b SSI0RX, \b SSI0TX, \b SSI1CLK, \b SSI1FSS, \b SSI1RX, or \b SSI1TX.
+//
+// \sa GPIOPinTypeSSI() in order to configure multiple SSI pins at once.
+//
+// \return None.
+//
+//*****************************************************************************
+#define PinTypeSSI(ulName)      GPIOPinTypeSSI(ulName##_PORT, ulName##_PIN)
+
+//*****************************************************************************
+//
+// Configures the specified Timer pin to function as a Timer pin.
+//
+// \param ulName is one of the valid names for the Timer pins.
+//
+// This function takes one of the valid names for a Timer pin and configures
+// the pin for its Timer functionality depending on the part that is defined.
+//
+// The valid names for the pins are as follows: \b CCP0, \b CCP1, \b CCP2,
+// \b CCP3, \b CCP4, \b CCP5, \b CCP6, or \b CCP7.
+//
+// \sa GPIOPinTypeTimer() in order to configure multiple CCP pins at once.
+//
+// \return None.
+//
+//*****************************************************************************
+#define PinTypeTimer(ulName)    GPIOPinTypeTimer(ulName##_PORT, ulName##_PIN)
+
+//*****************************************************************************
+//
+// Configures the specified UART pin to function as a UART pin.
+//
+// \param ulName is one of the valid names for the UART pins.
+//
+// This function takes one of the valid names for a UART pin and configures
+// the pin for its UART functionality depending on the part that is defined.
+//
+// The valid names for the pins are as follows: \b U0RX, \b U0TX, \b U1RX,
+// \b U1TX, \b U2RX, or \b U2TX.
+//
+// \sa GPIOPinTypeUART() in order to configure multiple UART pins at once.
+//
+// \return None.
+//
+//*****************************************************************************
+#define PinTypeUART(ulName)     GPIOPinTypeUART(ulName##_PORT, ulName##_PIN)
+
+//*****************************************************************************
+//
+//! Configures the specified USB digital pin to function as a USB pin.
+//!
+//! \param ulName is one of the valid names for a USB digital pin.
+//!
+//! This function takes one of the valid names for a USB digital pin and
+//! configures the pin for its USB functionality depending on the part that is
+//! defined.
+//!
+//! The valid names for the pins are as follows: \b EPEN or \b PFAULT.
+//!
+//! \sa GPIOPinTypeUSBDigital() in order to configure multiple USB pins at
+//! once.
+//!
+//! \return None.
+//
+//*****************************************************************************
+#define PinTypeUSBDigital(ulName)                                    \
+                                GPIOPinTypeUSBDigital(ulName##_PORT, \
+                                                      ulName##_PIN)
+
+//*****************************************************************************
+//
+//! Enables the peripheral port used by the given pin.
+//!
+//! \param ulName is one of the valid names for a pin.
+//!
+//! This function takes one of the valid names for a pin function and
+//! enables the peripheral port for that pin depending on the part that is
+//! defined.
+//!
+//! Any valid pin name can be used.
+//!
+//! \sa SysCtlPeripheralEnable() in order to enable a single port when
+//! multiple pins are on the same port.
+//!
+//! \return None.
+//
+//*****************************************************************************
+#define PeripheralEnable(ulName)                                    \
+                                SysCtlPeripheralEnable(ulName##_PERIPH)
+
+#endif // __PIN_MAP_H__
diff --git a/src/platform/lm3s/pwm.c b/src/platform/lm3s/driverlib/pwm.c
similarity index 93%
rename from src/platform/lm3s/pwm.c
rename to src/platform/lm3s/driverlib/pwm.c
index 3d131a46..34928bd5 100755
--- a/src/platform/lm3s/pwm.c
+++ b/src/platform/lm3s/driverlib/pwm.c
@@ -2,26 +2,23 @@
 //
 // pwm.c - API for the PWM modules
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2011 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
+// This is part of revision 7611 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -32,14 +29,14 @@
 //
 //*****************************************************************************
 
-#include "hw_ints.h"
-#include "hw_memmap.h"
-#include "hw_pwm.h"
-#include "hw_sysctl.h"
-#include "hw_types.h"
-#include "debug.h"
-#include "interrupt.h"
-#include "pwm.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_pwm.h"
+#include "inc/hw_sysctl.h"
+#include "inc/hw_types.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+#include "driverlib/pwm.h"
 
 //*****************************************************************************
 //
@@ -1221,14 +1218,14 @@ PWMGenIntStatus(unsigned long ulBase, unsigned long ulGen, tBoolean bMasked)
 //! \b PWM_INT_CNT_LOAD, \b PWM_INT_CNT_AU, \b PWM_INT_CNT_AD,
 //! \b PWM_INT_CNT_BU, or \b PWM_INT_CNT_BD.
 //!
-//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
-//! several clock cycles before the interrupt source is actually cleared.
+//! \note Because there is a write buffer in the Cortex-M3 processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
 //! Therefore, it is recommended that the interrupt source be cleared early in
 //! the interrupt handler (as opposed to the very last action) to avoid
 //! returning from the interrupt handler before the interrupt source is
 //! actually cleared.  Failure to do so may result in the interrupt handler
-//! being immediately reentered (since NVIC still sees the interrupt source
-//! asserted).
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
 //!
 //! \return None.
 //
@@ -1334,14 +1331,14 @@ PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault)
 //! used instead since it supports all fault interrupts supported on devices
 //! with and without extended PWM fault handling support.
 //!
-//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
-//! several clock cycles before the interrupt source is actually cleared.
+//! \note Because there is a write buffer in the Cortex-M3 processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
 //! Therefore, it is recommended that the interrupt source be cleared early in
 //! the interrupt handler (as opposed to the very last action) to avoid
 //! returning from the interrupt handler before the interrupt source is
 //! actually cleared.  Failure to do so may result in the interrupt handler
-//! being immediately reentered (since NVIC still sees the interrupt source
-//! asserted).
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
 //!
 //! \return None.
 //
@@ -1418,13 +1415,14 @@ PWMIntStatus(unsigned long ulBase, tBoolean bMasked)
 //! generators.  On a device without extended PWM fault handling, the interrupt
 //! is directly related to the state of the single FAULT pin.
 //!
-//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
-//! several cycles before the interrupt source is actually cleared.  Therefore,
-//! it is recommended that the interrupt source be cleared early in the
-//! interrupt handler (as opposed to the very last action) to avoid returning
-//! from the interrupt handler before the interrupt source is actually cleared.
-//! Failure to do so may result in the interrupt handler being immediately
-//! reentered (since NVIC still sees the interrupt source asserted).
+//! \note Because there is a write buffer in the Cortex-M3 processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared.  Failure to do so may result in the interrupt handler
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
 //!
 //! \return None.
 //
@@ -1510,11 +1508,15 @@ PWMGenFaultConfigure(unsigned long ulBase, unsigned long ulGen,
 //! \param ulGen is the PWM generator whose fault triggers are being set.  Must
 //! be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
 //! \param ulGroup indicates the subset of possible faults that are to be
-//! configured.  This must be \b PWM_FAULT_GROUP_0.
+//! configured.  This must be \b PWM_FAULT_GROUP_0 or \b PWM_FAULT_GROUP_1.
 //! \param ulFaultTriggers defines the set of inputs that are to contribute
 //! towards generation of the fault signal to the given PWM generator.  For
 //! \b PWM_FAULT_GROUP_0, this will be the logical OR of \b PWM_FAULT_FAULT0,
-//! \b PWM_FAULT_FAULT1, \b PWM_FAULT_FAULT2, or \b PWM_FAULT_FAULT3.
+//! \b PWM_FAULT_FAULT1, \b PWM_FAULT_FAULT2, or \b PWM_FAULT_FAULT3.  For
+//! \b PWM_FAULT_GROUP_1, this will be the logical OR of \b PWM_FAULT_DCMP0,
+//! \b PWM_FAULT_DCMP1, \b PWM_FAULT_DCMP2, \b PWM_FAULT_DCMP3,
+//! \b PWM_FAULT_DCMP4, \b PWM_FAULT_DCMP5, \b PWM_FAULT_DCMP6, or
+//! \b PWM_FAULT_DCMP7.
 //!
 //! This function allows selection of the set of fault inputs that will be
 //! combined to generate a fault condition to a given PWM generator.  By
@@ -1545,8 +1547,14 @@ PWMGenFaultTriggerSet(unsigned long ulBase, unsigned long ulGen,
     ASSERT(ulBase == PWM_BASE);
     ASSERT(PWMGenValid(ulGen));
     ASSERT((ulGroup == PWM_FAULT_GROUP_0) || (ulGroup == PWM_FAULT_GROUP_1));
-    ASSERT((ulFaultTriggers & ~(PWM_FAULT_FAULT0 | PWM_FAULT_FAULT1 |
-                                PWM_FAULT_FAULT2 | PWM_FAULT_FAULT3)) == 0);
+    ASSERT((ulGroup == PWM_FAULT_GROUP_0) &&
+           ((ulFaultTriggers & ~(PWM_FAULT_FAULT0 | PWM_FAULT_FAULT1 |
+                                 PWM_FAULT_FAULT2 | PWM_FAULT_FAULT3)) == 0));
+    ASSERT((ulGroup == PWM_FAULT_GROUP_1) &&
+           ((ulFaultTriggers & ~(PWM_FAULT_DCMP0 | PWM_FAULT_DCMP1 |
+                                 PWM_FAULT_DCMP2 | PWM_FAULT_DCMP3 |
+                                 PWM_FAULT_DCMP4 | PWM_FAULT_DCMP5 |
+                                 PWM_FAULT_DCMP6 | PWM_FAULT_DCMP7)) == 0));
 
     //
     // Write the fault triggers to the appropriate register.
@@ -1572,7 +1580,7 @@ PWMGenFaultTriggerSet(unsigned long ulBase, unsigned long ulGen,
 //! \param ulGen is the PWM generator whose fault triggers are being queried.
 //! Must be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
 //! \param ulGroup indicates the subset of faults that are being queried.  This
-//! must be \b PWM_FAULT_GROUP_0.
+//! must be \b PWM_FAULT_GROUP_0 or \b PWM_FAULT_GROUP_1.
 //!
 //! This function allows an application to query the current set of inputs that
 //! contribute towards the generation of a fault condition to a given PWM
@@ -1584,7 +1592,10 @@ PWMGenFaultTriggerSet(unsigned long ulBase, unsigned long ulGen,
 //! \return Returns the current fault triggers configured for the fault group
 //! provided.  For \b PWM_FAULT_GROUP_0, the returned value will be a logical
 //! OR of \b PWM_FAULT_FAULT0, \b PWM_FAULT_FAULT1, \b PWM_FAULT_FAULT2, or
-//! \b PWM_FAULT_FAULT3.
+//! \b PWM_FAULT_FAULT3.  For \b PWM_FAULT_GROUP_1, the return value will be
+//! the logical OR of \b PWM_FAULT_DCMP0, \b PWM_FAULT_DCMP1,
+//! \b PWM_FAULT_DCMP2, \b PWM_FAULT_DCMP3, \b PWM_FAULT_DCMP4,
+//! \b PWM_FAULT_DCMP5, \b PWM_FAULT_DCMP6, or \b PWM_FAULT_DCMP7.
 //
 //*****************************************************************************
 unsigned long
@@ -1621,7 +1632,7 @@ PWMGenFaultTriggerGet(unsigned long ulBase, unsigned long ulGen,
 //! queried.  Must be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or
 //! \b PWM_GEN_3.
 //! \param ulGroup indicates the subset of faults that are being queried.  This
-//! must be \b PWM_FAULT_GROUP_0.
+//! must be \b PWM_FAULT_GROUP_0 or \b PWM_FAULT_GROUP_1.
 //!
 //! This function allows an application to query the current state of each of
 //! the fault trigger inputs to a given PWM generator.  The current state of
@@ -1640,7 +1651,10 @@ PWMGenFaultTriggerGet(unsigned long ulBase, unsigned long ulGen,
 //! generator.  A set bit indicates that the associated trigger is active.  For
 //! \b PWM_FAULT_GROUP_0, the returned value will be a logical OR of
 //! \b PWM_FAULT_FAULT0, \b PWM_FAULT_FAULT1, \b PWM_FAULT_FAULT2, or
-//! \b PWM_FAULT_FAULT3.
+//! \b PWM_FAULT_FAULT3.  For \b PWM_FAULT_GROUP_1, the return value will be
+//! the logical OR of \b PWM_FAULT_DCMP0, \b PWM_FAULT_DCMP1,
+//! \b PWM_FAULT_DCMP2, \b PWM_FAULT_DCMP3, \b PWM_FAULT_DCMP4,
+//! \b PWM_FAULT_DCMP5, \b PWM_FAULT_DCMP6, or \b PWM_FAULT_DCMP7.
 //
 //*****************************************************************************
 unsigned long
@@ -1677,7 +1691,7 @@ PWMGenFaultStatus(unsigned long ulBase, unsigned long ulGen,
 //! queried.  Must be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or
 //! \b PWM_GEN_3.
 //! \param ulGroup indicates the subset of faults that are being queried.  This
-//! must be \b PWM_FAULT_GROUP_0.
+//! must be \b PWM_FAULT_GROUP_0 or \b PWM_FAULT_GROUP_1.
 //! \param ulFaultTriggers is the set of fault triggers which are to be
 //! cleared.
 //!
@@ -1702,8 +1716,14 @@ PWMGenFaultClear(unsigned long ulBase, unsigned long ulGen,
     ASSERT(ulBase == PWM_BASE);
     ASSERT(PWMGenValid(ulGen));
     ASSERT((ulGroup == PWM_FAULT_GROUP_0) || (ulGroup == PWM_FAULT_GROUP_1));
-    ASSERT((ulFaultTriggers & ~(PWM_FAULT_FAULT0 | PWM_FAULT_FAULT1 |
-                                PWM_FAULT_FAULT2 | PWM_FAULT_FAULT3)) == 0);
+    ASSERT((ulGroup == PWM_FAULT_GROUP_0) &&
+           ((ulFaultTriggers & ~(PWM_FAULT_FAULT0 | PWM_FAULT_FAULT1 |
+                                 PWM_FAULT_FAULT2 | PWM_FAULT_FAULT3)) == 0));
+    ASSERT((ulGroup == PWM_FAULT_GROUP_1) &&
+           ((ulFaultTriggers & ~(PWM_FAULT_DCMP0 | PWM_FAULT_DCMP1 |
+                                 PWM_FAULT_DCMP2 | PWM_FAULT_DCMP3 |
+                                 PWM_FAULT_DCMP4 | PWM_FAULT_DCMP5 |
+                                 PWM_FAULT_DCMP6 | PWM_FAULT_DCMP7)) == 0));
 
     //
     // Clear the given faults.
diff --git a/src/platform/lm3s/pwm.h b/src/platform/lm3s/driverlib/pwm.h
similarity index 91%
rename from src/platform/lm3s/pwm.h
rename to src/platform/lm3s/driverlib/pwm.h
index 966db8a8..69e7ca1e 100755
--- a/src/platform/lm3s/pwm.h
+++ b/src/platform/lm3s/driverlib/pwm.h
@@ -2,26 +2,23 @@
 //
 // pwm.h - API function protoypes for Pulse Width Modulation (PWM) ports
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2011 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
+// This is part of revision 7611 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -184,6 +181,15 @@ extern "C"
 //*****************************************************************************
 #define PWM_FAULT_GROUP_1       1
 
+#define PWM_FAULT_DCMP0         0x00000001
+#define PWM_FAULT_DCMP1         0x00000002
+#define PWM_FAULT_DCMP2         0x00000004
+#define PWM_FAULT_DCMP3         0x00000008
+#define PWM_FAULT_DCMP4         0x00000010
+#define PWM_FAULT_DCMP5         0x00000020
+#define PWM_FAULT_DCMP6         0x00000040
+#define PWM_FAULT_DCMP7         0x00000080
+
 //*****************************************************************************
 //
 // Defines to identify the sense of each of the external FAULTn signals
diff --git a/src/platform/lm3s/driverlib/rom.h b/src/platform/lm3s/driverlib/rom.h
new file mode 100755
index 00000000..19ff5d88
--- /dev/null
+++ b/src/platform/lm3s/driverlib/rom.h
@@ -0,0 +1,4607 @@
+//*****************************************************************************
+//
+// rom.h - Macros to facilitate calling functions in the ROM.
+//
+// Copyright (c) 2007-2011 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 7611 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __ROM_H__
+#define __ROM_H__
+
+//*****************************************************************************
+//
+// Pointers to the main API tables.
+//
+//*****************************************************************************
+#define ROM_APITABLE            ((unsigned long *)0x01000010)
+#define ROM_VERSION             (ROM_APITABLE[0])
+#define ROM_UARTTABLE           ((unsigned long *)(ROM_APITABLE[1]))
+#define ROM_SSITABLE            ((unsigned long *)(ROM_APITABLE[2]))
+#define ROM_I2CTABLE            ((unsigned long *)(ROM_APITABLE[3]))
+#define ROM_GPIOTABLE           ((unsigned long *)(ROM_APITABLE[4]))
+#define ROM_ADCTABLE            ((unsigned long *)(ROM_APITABLE[5]))
+#define ROM_COMPARATORTABLE     ((unsigned long *)(ROM_APITABLE[6]))
+#define ROM_FLASHTABLE          ((unsigned long *)(ROM_APITABLE[7]))
+#define ROM_PWMTABLE            ((unsigned long *)(ROM_APITABLE[8]))
+#define ROM_QEITABLE            ((unsigned long *)(ROM_APITABLE[9]))
+#define ROM_SYSTICKTABLE        ((unsigned long *)(ROM_APITABLE[10]))
+#define ROM_TIMERTABLE          ((unsigned long *)(ROM_APITABLE[11]))
+#define ROM_WATCHDOGTABLE       ((unsigned long *)(ROM_APITABLE[12]))
+#define ROM_SYSCTLTABLE         ((unsigned long *)(ROM_APITABLE[13]))
+#define ROM_INTERRUPTTABLE      ((unsigned long *)(ROM_APITABLE[14]))
+#define ROM_ETHERNETTABLE       ((unsigned long *)(ROM_APITABLE[15]))
+#define ROM_USBTABLE            ((unsigned long *)(ROM_APITABLE[16]))
+#define ROM_UDMATABLE           ((unsigned long *)(ROM_APITABLE[17]))
+#define ROM_CANTABLE            ((unsigned long *)(ROM_APITABLE[18]))
+#define ROM_HIBERNATETABLE      ((unsigned long *)(ROM_APITABLE[19]))
+#define ROM_MPUTABLE            ((unsigned long *)(ROM_APITABLE[20]))
+#define ROM_SOFTWARETABLE       ((unsigned long *)(ROM_APITABLE[21]))
+#define ROM_I2STABLE            ((unsigned long *)(ROM_APITABLE[22]))
+#define ROM_EPITABLE            ((unsigned long *)(ROM_APITABLE[23]))
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the ADC API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_ADCSequenceDataGet                                                \
+        ((long (*)(unsigned long ulBase,                                      \
+                   unsigned long ulSequenceNum,                               \
+                   unsigned long *pulBuffer))ROM_ADCTABLE[0])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_ADCIntDisable                                                     \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulSequenceNum))ROM_ADCTABLE[1])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_ADCIntEnable                                                      \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulSequenceNum))ROM_ADCTABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_ADCIntStatus                                                      \
+        ((unsigned long (*)(unsigned long ulBase,                             \
+                            unsigned long ulSequenceNum,                      \
+                            tBoolean bMasked))ROM_ADCTABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_ADCIntClear                                                       \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulSequenceNum))ROM_ADCTABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_ADCSequenceEnable                                                 \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulSequenceNum))ROM_ADCTABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_ADCSequenceDisable                                                \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulSequenceNum))ROM_ADCTABLE[6])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_ADCSequenceConfigure                                              \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulSequenceNum,                               \
+                   unsigned long ulTrigger,                                   \
+                   unsigned long ulPriority))ROM_ADCTABLE[7])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_ADCSequenceStepConfigure                                          \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulSequenceNum,                               \
+                   unsigned long ulStep,                                      \
+                   unsigned long ulConfig))ROM_ADCTABLE[8])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_ADCSequenceOverflow                                               \
+        ((long (*)(unsigned long ulBase,                                      \
+                   unsigned long ulSequenceNum))ROM_ADCTABLE[9])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_ADCSequenceOverflowClear                                          \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulSequenceNum))ROM_ADCTABLE[10])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_ADCSequenceUnderflow                                              \
+        ((long (*)(unsigned long ulBase,                                      \
+                   unsigned long ulSequenceNum))ROM_ADCTABLE[11])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_ADCSequenceUnderflowClear                                         \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulSequenceNum))ROM_ADCTABLE[12])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_ADCProcessorTrigger                                               \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulSequenceNum))ROM_ADCTABLE[13])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_ADCHardwareOversampleConfigure                                    \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulFactor))ROM_ADCTABLE[14])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_ADCComparatorConfigure                                            \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulComp,                                      \
+                   unsigned long ulConfig))ROM_ADCTABLE[15])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_ADCComparatorRegionSet                                            \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulComp,                                      \
+                   unsigned long ulLowRef,                                    \
+                   unsigned long ulHighRef))ROM_ADCTABLE[16])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_ADCComparatorReset                                                \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulComp,                                      \
+                   tBoolean bTrigger,                                         \
+                   tBoolean bInterrupt))ROM_ADCTABLE[17])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_ADCComparatorIntDisable                                           \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulSequenceNum))ROM_ADCTABLE[18])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_ADCComparatorIntEnable                                            \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulSequenceNum))ROM_ADCTABLE[19])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_ADCComparatorIntStatus                                            \
+        ((unsigned long (*)(unsigned long ulBase))ROM_ADCTABLE[20])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_ADCComparatorIntClear                                             \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulStatus))ROM_ADCTABLE[21])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_ADCReferenceSet                                                   \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulRef))ROM_ADCTABLE[22])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_ADCReferenceGet                                                   \
+        ((unsigned long (*)(unsigned long ulBase))ROM_ADCTABLE[23])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_ADCPhaseDelaySet                                                  \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulPhase))ROM_ADCTABLE[24])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_ADCPhaseDelayGet                                                  \
+        ((unsigned long (*)(unsigned long ulBase))ROM_ADCTABLE[25])
+#endif
+#if defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_ADCResolutionSet                                                  \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulResolution))ROM_ADCTABLE[26])
+#endif
+#if defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_ADCResolutionGet                                                  \
+        ((unsigned long (*)(unsigned long ulBase))ROM_ADCTABLE[27])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the CAN API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_CANIntClear                                                       \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulIntClr))ROM_CANTABLE[0])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_CANInit                                                           \
+        ((void (*)(unsigned long ulBase))ROM_CANTABLE[1])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_CANEnable                                                         \
+        ((void (*)(unsigned long ulBase))ROM_CANTABLE[2])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_CANDisable                                                        \
+        ((void (*)(unsigned long ulBase))ROM_CANTABLE[3])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_CANBitTimingSet                                                   \
+        ((void (*)(unsigned long ulBase,                                      \
+                   tCANBitClkParms *pClkParms))ROM_CANTABLE[4])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_CANBitTimingGet                                                   \
+        ((void (*)(unsigned long ulBase,                                      \
+                   tCANBitClkParms *pClkParms))ROM_CANTABLE[5])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_CANMessageSet                                                     \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulObjID,                                     \
+                   tCANMsgObject *pMsgObject,                                 \
+                   tMsgObjType eMsgType))ROM_CANTABLE[6])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_CANMessageGet                                                     \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulObjID,                                     \
+                   tCANMsgObject *pMsgObject,                                 \
+                   tBoolean bClrPendingInt))ROM_CANTABLE[7])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_CANStatusGet                                                      \
+        ((unsigned long (*)(unsigned long ulBase,                             \
+                            tCANStsReg eStatusReg))ROM_CANTABLE[8])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_CANMessageClear                                                   \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulObjID))ROM_CANTABLE[9])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_CANIntEnable                                                      \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulIntFlags))ROM_CANTABLE[10])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_CANIntDisable                                                     \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulIntFlags))ROM_CANTABLE[11])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_CANIntStatus                                                      \
+        ((unsigned long (*)(unsigned long ulBase,                             \
+                            tCANIntStsReg eIntStsReg))ROM_CANTABLE[12])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_CANRetryGet                                                       \
+        ((tBoolean (*)(unsigned long ulBase))ROM_CANTABLE[13])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_CANRetrySet                                                       \
+        ((void (*)(unsigned long ulBase,                                      \
+                   tBoolean bAutoRetry))ROM_CANTABLE[14])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_CANErrCntrGet                                                     \
+        ((tBoolean (*)(unsigned long ulBase,                                  \
+                       unsigned long *pulRxCount,                             \
+                       unsigned long *pulTxCount))ROM_CANTABLE[15])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_CANBitRateSet                                                     \
+        ((unsigned long (*)(unsigned long ulBase,                             \
+                            unsigned long ulSourceClock,                      \
+                            unsigned long ulBitRate))ROM_CANTABLE[16])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the Comparator API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_ComparatorIntClear                                                \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulComp))ROM_COMPARATORTABLE[0])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_ComparatorConfigure                                               \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulComp,                                      \
+                   unsigned long ulConfig))ROM_COMPARATORTABLE[1])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_ComparatorRefSet                                                  \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulRef))ROM_COMPARATORTABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_ComparatorValueGet                                                \
+        ((tBoolean (*)(unsigned long ulBase,                                  \
+                       unsigned long ulComp))ROM_COMPARATORTABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_ComparatorIntEnable                                               \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulComp))ROM_COMPARATORTABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_ComparatorIntDisable                                              \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulComp))ROM_COMPARATORTABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_ComparatorIntStatus                                               \
+        ((tBoolean (*)(unsigned long ulBase,                                  \
+                       unsigned long ulComp,                                  \
+                       tBoolean bMasked))ROM_COMPARATORTABLE[6])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the EPI API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_EPIIntStatus                                                      \
+        ((unsigned long (*)(unsigned long ulBase,                             \
+                            tBoolean bMasked))ROM_EPITABLE[0])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_EPIModeSet                                                        \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulMode))ROM_EPITABLE[1])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_EPIDividerSet                                                     \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulDivider))ROM_EPITABLE[2])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_EPIConfigSDRAMSet                                                 \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulConfig,                                    \
+                   unsigned long ulRefresh))ROM_EPITABLE[3])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_EPIConfigGPModeSet                                                \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulConfig,                                    \
+                   unsigned long ulFrameCount,                                \
+                   unsigned long ulMaxWait))ROM_EPITABLE[4])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_EPIConfigHB8Set                                                   \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulConfig,                                    \
+                   unsigned long ulMaxWait))ROM_EPITABLE[5])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_EPIConfigHB16Set                                                  \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulConfig,                                    \
+                   unsigned long ulMaxWait))ROM_EPITABLE[6])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_EPIAddressMapSet                                                  \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulMap))ROM_EPITABLE[7])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_EPINonBlockingReadConfigure                                       \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulChannel,                                   \
+                   unsigned long ulDataSize,                                  \
+                   unsigned long ulAddress))ROM_EPITABLE[8])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_EPINonBlockingReadStart                                           \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulChannel,                                   \
+                   unsigned long ulCount))ROM_EPITABLE[9])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_EPINonBlockingReadStop                                            \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulChannel))ROM_EPITABLE[10])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_EPINonBlockingReadCount                                           \
+        ((unsigned long (*)(unsigned long ulBase,                             \
+                            unsigned long ulChannel))ROM_EPITABLE[11])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_EPINonBlockingReadAvail                                           \
+        ((unsigned long (*)(unsigned long ulBase))ROM_EPITABLE[12])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_EPINonBlockingReadGet32                                           \
+        ((unsigned long (*)(unsigned long ulBase,                             \
+                            unsigned long ulCount,                            \
+                            unsigned long *pulBuf))ROM_EPITABLE[13])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_EPINonBlockingReadGet16                                           \
+        ((unsigned long (*)(unsigned long ulBase,                             \
+                            unsigned long ulCount,                            \
+                            unsigned short *pusBuf))ROM_EPITABLE[14])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_EPINonBlockingReadGet8                                            \
+        ((unsigned long (*)(unsigned long ulBase,                             \
+                            unsigned long ulCount,                            \
+                            unsigned char *pucBuf))ROM_EPITABLE[15])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_EPIFIFOConfig                                                     \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulConfig))ROM_EPITABLE[16])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_EPIWriteFIFOCountGet                                              \
+        ((unsigned long (*)(unsigned long ulBase))ROM_EPITABLE[17])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_EPIIntEnable                                                      \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulIntFlags))ROM_EPITABLE[18])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_EPIIntDisable                                                     \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulIntFlags))ROM_EPITABLE[19])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_EPIIntErrorStatus                                                 \
+        ((unsigned long (*)(unsigned long ulBase))ROM_EPITABLE[20])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_EPIIntErrorClear                                                  \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulErrFlags))ROM_EPITABLE[21])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the Ethernet API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_EthernetIntClear                                                  \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulIntFlags))ROM_ETHERNETTABLE[0])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_EthernetInitExpClk                                                \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulEthClk))ROM_ETHERNETTABLE[1])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_EthernetConfigSet                                                 \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulConfig))ROM_ETHERNETTABLE[2])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_EthernetConfigGet                                                 \
+        ((unsigned long (*)(unsigned long ulBase))ROM_ETHERNETTABLE[3])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_EthernetMACAddrSet                                                \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned char *pucMACAddr))ROM_ETHERNETTABLE[4])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_EthernetMACAddrGet                                                \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned char *pucMACAddr))ROM_ETHERNETTABLE[5])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_EthernetEnable                                                    \
+        ((void (*)(unsigned long ulBase))ROM_ETHERNETTABLE[6])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_EthernetDisable                                                   \
+        ((void (*)(unsigned long ulBase))ROM_ETHERNETTABLE[7])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_EthernetPacketAvail                                               \
+        ((tBoolean (*)(unsigned long ulBase))ROM_ETHERNETTABLE[8])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_EthernetSpaceAvail                                                \
+        ((tBoolean (*)(unsigned long ulBase))ROM_ETHERNETTABLE[9])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_EthernetPacketGetNonBlocking                                      \
+        ((long (*)(unsigned long ulBase,                                      \
+                   unsigned char *pucBuf,                                     \
+                   long lBufLen))ROM_ETHERNETTABLE[10])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_EthernetPacketGet                                                 \
+        ((long (*)(unsigned long ulBase,                                      \
+                   unsigned char *pucBuf,                                     \
+                   long lBufLen))ROM_ETHERNETTABLE[11])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_EthernetPacketPutNonBlocking                                      \
+        ((long (*)(unsigned long ulBase,                                      \
+                   unsigned char *pucBuf,                                     \
+                   long lBufLen))ROM_ETHERNETTABLE[12])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_EthernetPacketPut                                                 \
+        ((long (*)(unsigned long ulBase,                                      \
+                   unsigned char *pucBuf,                                     \
+                   long lBufLen))ROM_ETHERNETTABLE[13])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_EthernetIntEnable                                                 \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulIntFlags))ROM_ETHERNETTABLE[14])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_EthernetIntDisable                                                \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulIntFlags))ROM_ETHERNETTABLE[15])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_EthernetIntStatus                                                 \
+        ((unsigned long (*)(unsigned long ulBase,                             \
+                            tBoolean bMasked))ROM_ETHERNETTABLE[16])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_EthernetPHYWrite                                                  \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned char ucRegAddr,                                   \
+                   unsigned long ulData))ROM_ETHERNETTABLE[17])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_EthernetPHYRead                                                   \
+        ((unsigned long (*)(unsigned long ulBase,                             \
+                            unsigned char ucRegAddr))ROM_ETHERNETTABLE[18])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_UpdateEthernet                                                    \
+        ((void (*)(unsigned long ulClock))ROM_ETHERNETTABLE[19])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_EthernetPHYPowerOff                                               \
+        ((void (*)(unsigned long ulBase))ROM_ETHERNETTABLE[21])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_EthernetPHYPowerOn                                                \
+        ((void (*)(unsigned long ulBase))ROM_ETHERNETTABLE[22])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the Flash API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_FlashProgram                                                      \
+        ((long (*)(unsigned long *pulData,                                    \
+                   unsigned long ulAddress,                                   \
+                   unsigned long ulCount))ROM_FLASHTABLE[0])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_FlashUsecGet                                                      \
+        ((unsigned long (*)(void))ROM_FLASHTABLE[1])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_FlashUsecSet                                                      \
+        ((void (*)(unsigned long ulClocks))ROM_FLASHTABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_FlashErase                                                        \
+        ((long (*)(unsigned long ulAddress))ROM_FLASHTABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_FlashProtectGet                                                   \
+        ((tFlashProtection (*)(unsigned long ulAddress))ROM_FLASHTABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_FlashProtectSet                                                   \
+        ((long (*)(unsigned long ulAddress,                                   \
+                   tFlashProtection eProtect))ROM_FLASHTABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_FlashProtectSave                                                  \
+        ((long (*)(void))ROM_FLASHTABLE[6])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_FlashUserGet                                                      \
+        ((long (*)(unsigned long *pulUser0,                                   \
+                   unsigned long *pulUser1))ROM_FLASHTABLE[7])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_FlashUserSet                                                      \
+        ((long (*)(unsigned long ulUser0,                                     \
+                   unsigned long ulUser1))ROM_FLASHTABLE[8])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_FlashUserSave                                                     \
+        ((long (*)(void))ROM_FLASHTABLE[9])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_FlashIntEnable                                                    \
+        ((void (*)(unsigned long ulIntFlags))ROM_FLASHTABLE[10])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_FlashIntDisable                                                   \
+        ((void (*)(unsigned long ulIntFlags))ROM_FLASHTABLE[11])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_FlashIntStatus                                                    \
+        ((unsigned long (*)(tBoolean bMasked))ROM_FLASHTABLE[12])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_FlashIntClear                                                     \
+        ((void (*)(unsigned long ulIntFlags))ROM_FLASHTABLE[13])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the GPIO API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_GPIOPinWrite                                                      \
+        ((void (*)(unsigned long ulPort,                                      \
+                   unsigned char ucPins,                                      \
+                   unsigned char ucVal))ROM_GPIOTABLE[0])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_GPIODirModeSet                                                    \
+        ((void (*)(unsigned long ulPort,                                      \
+                   unsigned char ucPins,                                      \
+                   unsigned long ulPinIO))ROM_GPIOTABLE[1])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_GPIODirModeGet                                                    \
+        ((unsigned long (*)(unsigned long ulPort,                             \
+                            unsigned char ucPin))ROM_GPIOTABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_GPIOIntTypeSet                                                    \
+        ((void (*)(unsigned long ulPort,                                      \
+                   unsigned char ucPins,                                      \
+                   unsigned long ulIntType))ROM_GPIOTABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_GPIOIntTypeGet                                                    \
+        ((unsigned long (*)(unsigned long ulPort,                             \
+                            unsigned char ucPin))ROM_GPIOTABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_GPIOPadConfigSet                                                  \
+        ((void (*)(unsigned long ulPort,                                      \
+                   unsigned char ucPins,                                      \
+                   unsigned long ulStrength,                                  \
+                   unsigned long ulPadType))ROM_GPIOTABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_GPIOPadConfigGet                                                  \
+        ((void (*)(unsigned long ulPort,                                      \
+                   unsigned char ucPin,                                       \
+                   unsigned long *pulStrength,                                \
+                   unsigned long *pulPadType))ROM_GPIOTABLE[6])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_GPIOPinIntEnable                                                  \
+        ((void (*)(unsigned long ulPort,                                      \
+                   unsigned char ucPins))ROM_GPIOTABLE[7])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_GPIOPinIntDisable                                                 \
+        ((void (*)(unsigned long ulPort,                                      \
+                   unsigned char ucPins))ROM_GPIOTABLE[8])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_GPIOPinIntStatus                                                  \
+        ((long (*)(unsigned long ulPort,                                      \
+                   tBoolean bMasked))ROM_GPIOTABLE[9])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_GPIOPinIntClear                                                   \
+        ((void (*)(unsigned long ulPort,                                      \
+                   unsigned char ucPins))ROM_GPIOTABLE[10])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_GPIOPinRead                                                       \
+        ((long (*)(unsigned long ulPort,                                      \
+                   unsigned char ucPins))ROM_GPIOTABLE[11])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_GPIOPinTypeCAN                                                    \
+        ((void (*)(unsigned long ulPort,                                      \
+                   unsigned char ucPins))ROM_GPIOTABLE[12])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_GPIOPinTypeComparator                                             \
+        ((void (*)(unsigned long ulPort,                                      \
+                   unsigned char ucPins))ROM_GPIOTABLE[13])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_GPIOPinTypeGPIOInput                                              \
+        ((void (*)(unsigned long ulPort,                                      \
+                   unsigned char ucPins))ROM_GPIOTABLE[14])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_GPIOPinTypeGPIOOutput                                             \
+        ((void (*)(unsigned long ulPort,                                      \
+                   unsigned char ucPins))ROM_GPIOTABLE[15])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_GPIOPinTypeI2C                                                    \
+        ((void (*)(unsigned long ulPort,                                      \
+                   unsigned char ucPins))ROM_GPIOTABLE[16])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_GPIOPinTypePWM                                                    \
+        ((void (*)(unsigned long ulPort,                                      \
+                   unsigned char ucPins))ROM_GPIOTABLE[17])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_GPIOPinTypeQEI                                                    \
+        ((void (*)(unsigned long ulPort,                                      \
+                   unsigned char ucPins))ROM_GPIOTABLE[18])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_GPIOPinTypeSSI                                                    \
+        ((void (*)(unsigned long ulPort,                                      \
+                   unsigned char ucPins))ROM_GPIOTABLE[19])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_GPIOPinTypeTimer                                                  \
+        ((void (*)(unsigned long ulPort,                                      \
+                   unsigned char ucPins))ROM_GPIOTABLE[20])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_GPIOPinTypeUART                                                   \
+        ((void (*)(unsigned long ulPort,                                      \
+                   unsigned char ucPins))ROM_GPIOTABLE[21])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_GPIOPinTypeGPIOOutputOD                                           \
+        ((void (*)(unsigned long ulPort,                                      \
+                   unsigned char ucPins))ROM_GPIOTABLE[22])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_GPIOPinTypeADC                                                    \
+        ((void (*)(unsigned long ulPort,                                      \
+                   unsigned char ucPins))ROM_GPIOTABLE[23])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_GPIOPinTypeUSBDigital                                             \
+        ((void (*)(unsigned long ulPort,                                      \
+                   unsigned char ucPins))ROM_GPIOTABLE[24])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_GPIOPinTypeI2S                                                    \
+        ((void (*)(unsigned long ulPort,                                      \
+                   unsigned char ucPins))ROM_GPIOTABLE[25])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_GPIOPinConfigure                                                  \
+        ((void (*)(unsigned long ulPinConfig))ROM_GPIOTABLE[26])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_GPIOPinTypeEthernetLED                                            \
+        ((void (*)(unsigned long ulPort,                                      \
+                   unsigned char ucPins))ROM_GPIOTABLE[27])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_GPIOPinTypeUSBAnalog                                              \
+        ((void (*)(unsigned long ulPort,                                      \
+                   unsigned char ucPins))ROM_GPIOTABLE[28])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_GPIOPinTypeEPI                                                    \
+        ((void (*)(unsigned long ulPort,                                      \
+                   unsigned char ucPins))ROM_GPIOTABLE[29])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_GPIOPinTypeEthernetMII                                            \
+        ((void (*)(unsigned long ulPort,                                      \
+                   unsigned char ucPins))ROM_GPIOTABLE[30])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the Hibernate API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_HibernateIntClear                                                 \
+        ((void (*)(unsigned long ulIntFlags))ROM_HIBERNATETABLE[0])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_HibernateEnableExpClk                                             \
+        ((void (*)(unsigned long ulHibClk))ROM_HIBERNATETABLE[1])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_HibernateDisable                                                  \
+        ((void (*)(void))ROM_HIBERNATETABLE[2])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_HibernateClockSelect                                              \
+        ((void (*)(unsigned long ulClockInput))ROM_HIBERNATETABLE[3])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_HibernateRTCEnable                                                \
+        ((void (*)(void))ROM_HIBERNATETABLE[4])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_HibernateRTCDisable                                               \
+        ((void (*)(void))ROM_HIBERNATETABLE[5])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_HibernateWakeSet                                                  \
+        ((void (*)(unsigned long ulWakeFlags))ROM_HIBERNATETABLE[6])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_HibernateWakeGet                                                  \
+        ((unsigned long (*)(void))ROM_HIBERNATETABLE[7])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_HibernateLowBatSet                                                \
+        ((void (*)(unsigned long ulLowBatFlags))ROM_HIBERNATETABLE[8])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_HibernateLowBatGet                                                \
+        ((unsigned long (*)(void))ROM_HIBERNATETABLE[9])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_HibernateRTCSet                                                   \
+        ((void (*)(unsigned long ulRTCValue))ROM_HIBERNATETABLE[10])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_HibernateRTCGet                                                   \
+        ((unsigned long (*)(void))ROM_HIBERNATETABLE[11])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_HibernateRTCMatch0Set                                             \
+        ((void (*)(unsigned long ulMatch))ROM_HIBERNATETABLE[12])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_HibernateRTCMatch0Get                                             \
+        ((unsigned long (*)(void))ROM_HIBERNATETABLE[13])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_HibernateRTCMatch1Set                                             \
+        ((void (*)(unsigned long ulMatch))ROM_HIBERNATETABLE[14])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_HibernateRTCMatch1Get                                             \
+        ((unsigned long (*)(void))ROM_HIBERNATETABLE[15])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_HibernateRTCTrimSet                                               \
+        ((void (*)(unsigned long ulTrim))ROM_HIBERNATETABLE[16])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_HibernateRTCTrimGet                                               \
+        ((unsigned long (*)(void))ROM_HIBERNATETABLE[17])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_HibernateDataSet                                                  \
+        ((void (*)(unsigned long *pulData,                                    \
+                   unsigned long ulCount))ROM_HIBERNATETABLE[18])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_HibernateDataGet                                                  \
+        ((void (*)(unsigned long *pulData,                                    \
+                   unsigned long ulCount))ROM_HIBERNATETABLE[19])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_HibernateRequest                                                  \
+        ((void (*)(void))ROM_HIBERNATETABLE[20])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_HibernateIntEnable                                                \
+        ((void (*)(unsigned long ulIntFlags))ROM_HIBERNATETABLE[21])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_HibernateIntDisable                                               \
+        ((void (*)(unsigned long ulIntFlags))ROM_HIBERNATETABLE[22])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_HibernateIntStatus                                                \
+        ((unsigned long (*)(tBoolean bMasked))ROM_HIBERNATETABLE[23])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_HibernateIsActive                                                 \
+        ((unsigned long (*)(void))ROM_HIBERNATETABLE[24])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the I2C API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_I2CMasterDataPut                                                  \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned char ucData))ROM_I2CTABLE[0])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_I2CMasterInitExpClk                                               \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulI2CClk,                                    \
+                   tBoolean bFast))ROM_I2CTABLE[1])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_I2CSlaveInit                                                      \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned char ucSlaveAddr))ROM_I2CTABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_I2CMasterEnable                                                   \
+        ((void (*)(unsigned long ulBase))ROM_I2CTABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_I2CSlaveEnable                                                    \
+        ((void (*)(unsigned long ulBase))ROM_I2CTABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_I2CMasterDisable                                                  \
+        ((void (*)(unsigned long ulBase))ROM_I2CTABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_I2CSlaveDisable                                                   \
+        ((void (*)(unsigned long ulBase))ROM_I2CTABLE[6])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_I2CMasterIntEnable                                                \
+        ((void (*)(unsigned long ulBase))ROM_I2CTABLE[7])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_I2CSlaveIntEnable                                                 \
+        ((void (*)(unsigned long ulBase))ROM_I2CTABLE[8])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_I2CMasterIntDisable                                               \
+        ((void (*)(unsigned long ulBase))ROM_I2CTABLE[9])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_I2CSlaveIntDisable                                                \
+        ((void (*)(unsigned long ulBase))ROM_I2CTABLE[10])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_I2CMasterIntStatus                                                \
+        ((tBoolean (*)(unsigned long ulBase,                                  \
+                       tBoolean bMasked))ROM_I2CTABLE[11])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_I2CSlaveIntStatus                                                 \
+        ((tBoolean (*)(unsigned long ulBase,                                  \
+                       tBoolean bMasked))ROM_I2CTABLE[12])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_I2CMasterIntClear                                                 \
+        ((void (*)(unsigned long ulBase))ROM_I2CTABLE[13])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_I2CSlaveIntClear                                                  \
+        ((void (*)(unsigned long ulBase))ROM_I2CTABLE[14])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_I2CMasterSlaveAddrSet                                             \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned char ucSlaveAddr,                                 \
+                   tBoolean bReceive))ROM_I2CTABLE[15])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_I2CMasterBusy                                                     \
+        ((tBoolean (*)(unsigned long ulBase))ROM_I2CTABLE[16])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_I2CMasterBusBusy                                                  \
+        ((tBoolean (*)(unsigned long ulBase))ROM_I2CTABLE[17])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_I2CMasterControl                                                  \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulCmd))ROM_I2CTABLE[18])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_I2CMasterErr                                                      \
+        ((unsigned long (*)(unsigned long ulBase))ROM_I2CTABLE[19])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_I2CMasterDataGet                                                  \
+        ((unsigned long (*)(unsigned long ulBase))ROM_I2CTABLE[20])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_I2CSlaveStatus                                                    \
+        ((unsigned long (*)(unsigned long ulBase))ROM_I2CTABLE[21])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_I2CSlaveDataPut                                                   \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned char ucData))ROM_I2CTABLE[22])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_I2CSlaveDataGet                                                   \
+        ((unsigned long (*)(unsigned long ulBase))ROM_I2CTABLE[23])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_UpdateI2C                                                         \
+        ((void (*)(void))ROM_I2CTABLE[24])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_I2CSlaveIntEnableEx                                               \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulIntFlags))ROM_I2CTABLE[25])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_I2CSlaveIntDisableEx                                              \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulIntFlags))ROM_I2CTABLE[26])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_I2CSlaveIntStatusEx                                               \
+        ((unsigned long (*)(unsigned long ulBase,                             \
+                            tBoolean bMasked))ROM_I2CTABLE[27])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_I2CSlaveIntClearEx                                                \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulIntFlags))ROM_I2CTABLE[28])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the I2S API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_I2SIntStatus                                                      \
+        ((unsigned long (*)(unsigned long ulBase,                             \
+                            tBoolean bMasked))ROM_I2STABLE[0])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_I2STxEnable                                                       \
+        ((void (*)(unsigned long ulBase))ROM_I2STABLE[1])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_I2STxDisable                                                      \
+        ((void (*)(unsigned long ulBase))ROM_I2STABLE[2])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_I2STxDataPut                                                      \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulData))ROM_I2STABLE[3])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_I2STxDataPutNonBlocking                                           \
+        ((long (*)(unsigned long ulBase,                                      \
+                   unsigned long ulData))ROM_I2STABLE[4])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_I2STxConfigSet                                                    \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulConfig))ROM_I2STABLE[5])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_I2STxFIFOLimitSet                                                 \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulLevel))ROM_I2STABLE[6])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_I2STxFIFOLimitGet                                                 \
+        ((unsigned long (*)(unsigned long ulBase))ROM_I2STABLE[7])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_I2STxFIFOLevelGet                                                 \
+        ((unsigned long (*)(unsigned long ulBase))ROM_I2STABLE[8])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_I2SRxEnable                                                       \
+        ((void (*)(unsigned long ulBase))ROM_I2STABLE[9])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_I2SRxDisable                                                      \
+        ((void (*)(unsigned long ulBase))ROM_I2STABLE[10])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_I2SRxDataGet                                                      \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long *pulData))ROM_I2STABLE[11])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_I2SRxDataGetNonBlocking                                           \
+        ((long (*)(unsigned long ulBase,                                      \
+                   unsigned long *pulData))ROM_I2STABLE[12])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_I2SRxConfigSet                                                    \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulConfig))ROM_I2STABLE[13])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_I2SRxFIFOLimitSet                                                 \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulLevel))ROM_I2STABLE[14])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_I2SRxFIFOLimitGet                                                 \
+        ((unsigned long (*)(unsigned long ulBase))ROM_I2STABLE[15])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_I2SRxFIFOLevelGet                                                 \
+        ((unsigned long (*)(unsigned long ulBase))ROM_I2STABLE[16])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_I2STxRxEnable                                                     \
+        ((void (*)(unsigned long ulBase))ROM_I2STABLE[17])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_I2STxRxDisable                                                    \
+        ((void (*)(unsigned long ulBase))ROM_I2STABLE[18])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_I2STxRxConfigSet                                                  \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulConfig))ROM_I2STABLE[19])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_I2SMasterClockSelect                                              \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulMClock))ROM_I2STABLE[20])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_I2SIntEnable                                                      \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulIntFlags))ROM_I2STABLE[21])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_I2SIntDisable                                                     \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulIntFlags))ROM_I2STABLE[22])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_I2SIntClear                                                       \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulIntFlags))ROM_I2STABLE[23])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the Interrupt API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_IntEnable                                                         \
+        ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[0])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_IntMasterEnable                                                   \
+        ((tBoolean (*)(void))ROM_INTERRUPTTABLE[1])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_IntMasterDisable                                                  \
+        ((tBoolean (*)(void))ROM_INTERRUPTTABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_IntDisable                                                        \
+        ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_IntPriorityGroupingSet                                            \
+        ((void (*)(unsigned long ulBits))ROM_INTERRUPTTABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_IntPriorityGroupingGet                                            \
+        ((unsigned long (*)(void))ROM_INTERRUPTTABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_IntPrioritySet                                                    \
+        ((void (*)(unsigned long ulInterrupt,                                 \
+                   unsigned char ucPriority))ROM_INTERRUPTTABLE[6])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_IntPriorityGet                                                    \
+        ((long (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[7])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_IntPendSet                                                        \
+        ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[8])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_IntPendClear                                                      \
+        ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[9])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_IntPriorityMaskSet                                                \
+        ((void (*)(unsigned long ulPriorityMask))ROM_INTERRUPTTABLE[10])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_IntPriorityMaskGet                                                \
+        ((unsigned long (*)(void))ROM_INTERRUPTTABLE[11])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the MPU API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_MPUEnable                                                         \
+        ((void (*)(unsigned long ulMPUConfig))ROM_MPUTABLE[0])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_MPUDisable                                                        \
+        ((void (*)(void))ROM_MPUTABLE[1])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_MPURegionCountGet                                                 \
+        ((unsigned long (*)(void))ROM_MPUTABLE[2])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_MPURegionEnable                                                   \
+        ((void (*)(unsigned long ulRegion))ROM_MPUTABLE[3])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_MPURegionDisable                                                  \
+        ((void (*)(unsigned long ulRegion))ROM_MPUTABLE[4])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_MPURegionSet                                                      \
+        ((void (*)(unsigned long ulRegion,                                    \
+                   unsigned long ulAddr,                                      \
+                   unsigned long ulFlags))ROM_MPUTABLE[5])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_MPURegionGet                                                      \
+        ((void (*)(unsigned long ulRegion,                                    \
+                   unsigned long *pulAddr,                                    \
+                   unsigned long *pulFlags))ROM_MPUTABLE[6])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the PWM API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_PWMPulseWidthSet                                                  \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulPWMOut,                                    \
+                   unsigned long ulWidth))ROM_PWMTABLE[0])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_PWMGenConfigure                                                   \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulGen,                                       \
+                   unsigned long ulConfig))ROM_PWMTABLE[1])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_PWMGenPeriodSet                                                   \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulGen,                                       \
+                   unsigned long ulPeriod))ROM_PWMTABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_PWMGenPeriodGet                                                   \
+        ((unsigned long (*)(unsigned long ulBase,                             \
+                            unsigned long ulGen))ROM_PWMTABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_PWMGenEnable                                                      \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulGen))ROM_PWMTABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_PWMGenDisable                                                     \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulGen))ROM_PWMTABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_PWMPulseWidthGet                                                  \
+        ((unsigned long (*)(unsigned long ulBase,                             \
+                            unsigned long ulPWMOut))ROM_PWMTABLE[6])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_PWMDeadBandEnable                                                 \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulGen,                                       \
+                   unsigned short usRise,                                     \
+                   unsigned short usFall))ROM_PWMTABLE[7])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_PWMDeadBandDisable                                                \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulGen))ROM_PWMTABLE[8])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_PWMSyncUpdate                                                     \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulGenBits))ROM_PWMTABLE[9])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_PWMSyncTimeBase                                                   \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulGenBits))ROM_PWMTABLE[10])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_PWMOutputState                                                    \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulPWMOutBits,                                \
+                   tBoolean bEnable))ROM_PWMTABLE[11])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_PWMOutputInvert                                                   \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulPWMOutBits,                                \
+                   tBoolean bInvert))ROM_PWMTABLE[12])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_PWMOutputFault                                                    \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulPWMOutBits,                                \
+                   tBoolean bFaultSuppress))ROM_PWMTABLE[13])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_PWMGenIntTrigEnable                                               \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulGen,                                       \
+                   unsigned long ulIntTrig))ROM_PWMTABLE[14])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_PWMGenIntTrigDisable                                              \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulGen,                                       \
+                   unsigned long ulIntTrig))ROM_PWMTABLE[15])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_PWMGenIntStatus                                                   \
+        ((unsigned long (*)(unsigned long ulBase,                             \
+                            unsigned long ulGen,                              \
+                            tBoolean bMasked))ROM_PWMTABLE[16])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_PWMGenIntClear                                                    \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulGen,                                       \
+                   unsigned long ulInts))ROM_PWMTABLE[17])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_PWMIntEnable                                                      \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulGenFault))ROM_PWMTABLE[18])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_PWMIntDisable                                                     \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulGenFault))ROM_PWMTABLE[19])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_PWMFaultIntClear                                                  \
+        ((void (*)(unsigned long ulBase))ROM_PWMTABLE[20])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_PWMIntStatus                                                      \
+        ((unsigned long (*)(unsigned long ulBase,                             \
+                            tBoolean bMasked))ROM_PWMTABLE[21])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_PWMOutputFaultLevel                                               \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulPWMOutBits,                                \
+                   tBoolean bDriveHigh))ROM_PWMTABLE[22])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_PWMFaultIntClearExt                                               \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulFaultInts))ROM_PWMTABLE[23])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_PWMGenFaultConfigure                                              \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulGen,                                       \
+                   unsigned long ulMinFaultPeriod,                            \
+                   unsigned long ulFaultSenses))ROM_PWMTABLE[24])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_PWMGenFaultTriggerSet                                             \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulGen,                                       \
+                   unsigned long ulGroup,                                     \
+                   unsigned long ulFaultTriggers))ROM_PWMTABLE[25])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_PWMGenFaultTriggerGet                                             \
+        ((unsigned long (*)(unsigned long ulBase,                             \
+                            unsigned long ulGen,                              \
+                            unsigned long ulGroup))ROM_PWMTABLE[26])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_PWMGenFaultStatus                                                 \
+        ((unsigned long (*)(unsigned long ulBase,                             \
+                            unsigned long ulGen,                              \
+                            unsigned long ulGroup))ROM_PWMTABLE[27])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_PWMGenFaultClear                                                  \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulGen,                                       \
+                   unsigned long ulGroup,                                     \
+                   unsigned long ulFaultTriggers))ROM_PWMTABLE[28])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the QEI API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_QEIPositionGet                                                    \
+        ((unsigned long (*)(unsigned long ulBase))ROM_QEITABLE[0])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_QEIEnable                                                         \
+        ((void (*)(unsigned long ulBase))ROM_QEITABLE[1])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_QEIDisable                                                        \
+        ((void (*)(unsigned long ulBase))ROM_QEITABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_QEIConfigure                                                      \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulConfig,                                    \
+                   unsigned long ulMaxPosition))ROM_QEITABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_QEIPositionSet                                                    \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulPosition))ROM_QEITABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_QEIDirectionGet                                                   \
+        ((long (*)(unsigned long ulBase))ROM_QEITABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_QEIErrorGet                                                       \
+        ((tBoolean (*)(unsigned long ulBase))ROM_QEITABLE[6])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_QEIVelocityEnable                                                 \
+        ((void (*)(unsigned long ulBase))ROM_QEITABLE[7])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_QEIVelocityDisable                                                \
+        ((void (*)(unsigned long ulBase))ROM_QEITABLE[8])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_QEIVelocityConfigure                                              \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulPreDiv,                                    \
+                   unsigned long ulPeriod))ROM_QEITABLE[9])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_QEIVelocityGet                                                    \
+        ((unsigned long (*)(unsigned long ulBase))ROM_QEITABLE[10])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_QEIIntEnable                                                      \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulIntFlags))ROM_QEITABLE[11])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_QEIIntDisable                                                     \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulIntFlags))ROM_QEITABLE[12])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_QEIIntStatus                                                      \
+        ((unsigned long (*)(unsigned long ulBase,                             \
+                            tBoolean bMasked))ROM_QEITABLE[13])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_QEIIntClear                                                       \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulIntFlags))ROM_QEITABLE[14])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the SSI API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_SSIDataPut                                                        \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulData))ROM_SSITABLE[0])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_SSIConfigSetExpClk                                                \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulSSIClk,                                    \
+                   unsigned long ulProtocol,                                  \
+                   unsigned long ulMode,                                      \
+                   unsigned long ulBitRate,                                   \
+                   unsigned long ulDataWidth))ROM_SSITABLE[1])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_SSIEnable                                                         \
+        ((void (*)(unsigned long ulBase))ROM_SSITABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_SSIDisable                                                        \
+        ((void (*)(unsigned long ulBase))ROM_SSITABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_SSIIntEnable                                                      \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulIntFlags))ROM_SSITABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_SSIIntDisable                                                     \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulIntFlags))ROM_SSITABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_SSIIntStatus                                                      \
+        ((unsigned long (*)(unsigned long ulBase,                             \
+                            tBoolean bMasked))ROM_SSITABLE[6])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_SSIIntClear                                                       \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulIntFlags))ROM_SSITABLE[7])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_SSIDataPutNonBlocking                                             \
+        ((long (*)(unsigned long ulBase,                                      \
+                   unsigned long ulData))ROM_SSITABLE[8])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_SSIDataGet                                                        \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long *pulData))ROM_SSITABLE[9])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_SSIDataGetNonBlocking                                             \
+        ((long (*)(unsigned long ulBase,                                      \
+                   unsigned long *pulData))ROM_SSITABLE[10])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_UpdateSSI                                                         \
+        ((void (*)(void))ROM_SSITABLE[11])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_SSIDMAEnable                                                      \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulDMAFlags))ROM_SSITABLE[12])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_SSIDMADisable                                                     \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulDMAFlags))ROM_SSITABLE[13])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_SSIBusy                                                           \
+        ((tBoolean (*)(unsigned long ulBase))ROM_SSITABLE[14])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the SysCtl API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_SysCtlSleep                                                       \
+        ((void (*)(void))ROM_SYSCTLTABLE[0])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_SysCtlSRAMSizeGet                                                 \
+        ((unsigned long (*)(void))ROM_SYSCTLTABLE[1])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_SysCtlFlashSizeGet                                                \
+        ((unsigned long (*)(void))ROM_SYSCTLTABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_SysCtlPinPresent                                                  \
+        ((tBoolean (*)(unsigned long ulPin))ROM_SYSCTLTABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_SysCtlPeripheralPresent                                           \
+        ((tBoolean (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_SysCtlPeripheralReset                                             \
+        ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_SysCtlPeripheralEnable                                            \
+        ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[6])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_SysCtlPeripheralDisable                                           \
+        ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[7])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_SysCtlPeripheralSleepEnable                                       \
+        ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[8])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_SysCtlPeripheralSleepDisable                                      \
+        ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[9])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_SysCtlPeripheralDeepSleepEnable                                   \
+        ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[10])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_SysCtlPeripheralDeepSleepDisable                                  \
+        ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[11])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_SysCtlPeripheralClockGating                                       \
+        ((void (*)(tBoolean bEnable))ROM_SYSCTLTABLE[12])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_SysCtlIntEnable                                                   \
+        ((void (*)(unsigned long ulInts))ROM_SYSCTLTABLE[13])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_SysCtlIntDisable                                                  \
+        ((void (*)(unsigned long ulInts))ROM_SYSCTLTABLE[14])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_SysCtlIntClear                                                    \
+        ((void (*)(unsigned long ulInts))ROM_SYSCTLTABLE[15])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_SysCtlIntStatus                                                   \
+        ((unsigned long (*)(tBoolean bMasked))ROM_SYSCTLTABLE[16])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_SysCtlLDOSet                                                      \
+        ((void (*)(unsigned long ulVoltage))ROM_SYSCTLTABLE[17])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_SysCtlLDOGet                                                      \
+        ((unsigned long (*)(void))ROM_SYSCTLTABLE[18])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_SysCtlReset                                                       \
+        ((void (*)(void))ROM_SYSCTLTABLE[19])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_SysCtlDeepSleep                                                   \
+        ((void (*)(void))ROM_SYSCTLTABLE[20])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_SysCtlResetCauseGet                                               \
+        ((unsigned long (*)(void))ROM_SYSCTLTABLE[21])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_SysCtlResetCauseClear                                             \
+        ((void (*)(unsigned long ulCauses))ROM_SYSCTLTABLE[22])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_SysCtlClockSet                                                    \
+        ((void (*)(unsigned long ulConfig))ROM_SYSCTLTABLE[23])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_SysCtlClockGet                                                    \
+        ((unsigned long (*)(void))ROM_SYSCTLTABLE[24])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_SysCtlPWMClockSet                                                 \
+        ((void (*)(unsigned long ulConfig))ROM_SYSCTLTABLE[25])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_SysCtlPWMClockGet                                                 \
+        ((unsigned long (*)(void))ROM_SYSCTLTABLE[26])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_SysCtlADCSpeedSet                                                 \
+        ((void (*)(unsigned long ulSpeed))ROM_SYSCTLTABLE[27])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_SysCtlADCSpeedGet                                                 \
+        ((unsigned long (*)(void))ROM_SYSCTLTABLE[28])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_SysCtlGPIOAHBEnable                                               \
+        ((void (*)(unsigned long ulGPIOPeripheral))ROM_SYSCTLTABLE[29])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_SysCtlGPIOAHBDisable                                              \
+        ((void (*)(unsigned long ulGPIOPeripheral))ROM_SYSCTLTABLE[30])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_SysCtlUSBPLLEnable                                                \
+        ((void (*)(void))ROM_SYSCTLTABLE[31])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_SysCtlUSBPLLDisable                                               \
+        ((void (*)(void))ROM_SYSCTLTABLE[32])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_SysCtlI2SMClkSet                                                  \
+        ((unsigned long (*)(unsigned long ulInputClock,                       \
+                            unsigned long ulMClk))ROM_SYSCTLTABLE[33])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_SysCtlDelay                                                       \
+        ((void (*)(unsigned long ulCount))ROM_SYSCTLTABLE[34])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the SysTick API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_SysTickValueGet                                                   \
+        ((unsigned long (*)(void))ROM_SYSTICKTABLE[0])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_SysTickEnable                                                     \
+        ((void (*)(void))ROM_SYSTICKTABLE[1])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_SysTickDisable                                                    \
+        ((void (*)(void))ROM_SYSTICKTABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_SysTickIntEnable                                                  \
+        ((void (*)(void))ROM_SYSTICKTABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_SysTickIntDisable                                                 \
+        ((void (*)(void))ROM_SYSTICKTABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_SysTickPeriodSet                                                  \
+        ((void (*)(unsigned long ulPeriod))ROM_SYSTICKTABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_SysTickPeriodGet                                                  \
+        ((unsigned long (*)(void))ROM_SYSTICKTABLE[6])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the Timer API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_TimerIntClear                                                     \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulIntFlags))ROM_TIMERTABLE[0])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_TimerEnable                                                       \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulTimer))ROM_TIMERTABLE[1])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_TimerDisable                                                      \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulTimer))ROM_TIMERTABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_TimerConfigure                                                    \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulConfig))ROM_TIMERTABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_TimerControlLevel                                                 \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulTimer,                                     \
+                   tBoolean bInvert))ROM_TIMERTABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_TimerControlTrigger                                               \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulTimer,                                     \
+                   tBoolean bEnable))ROM_TIMERTABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_TimerControlEvent                                                 \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulTimer,                                     \
+                   unsigned long ulEvent))ROM_TIMERTABLE[6])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_TimerControlStall                                                 \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulTimer,                                     \
+                   tBoolean bStall))ROM_TIMERTABLE[7])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_TimerRTCEnable                                                    \
+        ((void (*)(unsigned long ulBase))ROM_TIMERTABLE[8])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_TimerRTCDisable                                                   \
+        ((void (*)(unsigned long ulBase))ROM_TIMERTABLE[9])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_TimerPrescaleSet                                                  \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulTimer,                                     \
+                   unsigned long ulValue))ROM_TIMERTABLE[10])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_TimerPrescaleGet                                                  \
+        ((unsigned long (*)(unsigned long ulBase,                             \
+                            unsigned long ulTimer))ROM_TIMERTABLE[11])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_TimerPrescaleMatchSet                                             \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulTimer,                                     \
+                   unsigned long ulValue))ROM_TIMERTABLE[12])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_TimerPrescaleMatchGet                                             \
+        ((unsigned long (*)(unsigned long ulBase,                             \
+                            unsigned long ulTimer))ROM_TIMERTABLE[13])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_TimerLoadSet                                                      \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulTimer,                                     \
+                   unsigned long ulValue))ROM_TIMERTABLE[14])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_TimerLoadGet                                                      \
+        ((unsigned long (*)(unsigned long ulBase,                             \
+                            unsigned long ulTimer))ROM_TIMERTABLE[15])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_TimerValueGet                                                     \
+        ((unsigned long (*)(unsigned long ulBase,                             \
+                            unsigned long ulTimer))ROM_TIMERTABLE[16])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_TimerMatchSet                                                     \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulTimer,                                     \
+                   unsigned long ulValue))ROM_TIMERTABLE[17])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_TimerMatchGet                                                     \
+        ((unsigned long (*)(unsigned long ulBase,                             \
+                            unsigned long ulTimer))ROM_TIMERTABLE[18])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_TimerIntEnable                                                    \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulIntFlags))ROM_TIMERTABLE[19])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_TimerIntDisable                                                   \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulIntFlags))ROM_TIMERTABLE[20])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_TimerIntStatus                                                    \
+        ((unsigned long (*)(unsigned long ulBase,                             \
+                            tBoolean bMasked))ROM_TIMERTABLE[21])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_TimerControlWaitOnTrigger                                         \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulTimer,                                     \
+                   tBoolean bWait))ROM_TIMERTABLE[22])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the UART API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_UARTCharPut                                                       \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned char ucData))ROM_UARTTABLE[0])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_UARTParityModeSet                                                 \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulParity))ROM_UARTTABLE[1])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_UARTParityModeGet                                                 \
+        ((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_UARTFIFOLevelSet                                                  \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulTxLevel,                                   \
+                   unsigned long ulRxLevel))ROM_UARTTABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_UARTFIFOLevelGet                                                  \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long *pulTxLevel,                                 \
+                   unsigned long *pulRxLevel))ROM_UARTTABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_UARTConfigSetExpClk                                               \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulUARTClk,                                   \
+                   unsigned long ulBaud,                                      \
+                   unsigned long ulConfig))ROM_UARTTABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_UARTConfigGetExpClk                                               \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulUARTClk,                                   \
+                   unsigned long *pulBaud,                                    \
+                   unsigned long *pulConfig))ROM_UARTTABLE[6])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_UARTEnable                                                        \
+        ((void (*)(unsigned long ulBase))ROM_UARTTABLE[7])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_UARTDisable                                                       \
+        ((void (*)(unsigned long ulBase))ROM_UARTTABLE[8])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_UARTEnableSIR                                                     \
+        ((void (*)(unsigned long ulBase,                                      \
+                   tBoolean bLowPower))ROM_UARTTABLE[9])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_UARTDisableSIR                                                    \
+        ((void (*)(unsigned long ulBase))ROM_UARTTABLE[10])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_UARTCharsAvail                                                    \
+        ((tBoolean (*)(unsigned long ulBase))ROM_UARTTABLE[11])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_UARTSpaceAvail                                                    \
+        ((tBoolean (*)(unsigned long ulBase))ROM_UARTTABLE[12])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_UARTCharGetNonBlocking                                            \
+        ((long (*)(unsigned long ulBase))ROM_UARTTABLE[13])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_UARTCharGet                                                       \
+        ((long (*)(unsigned long ulBase))ROM_UARTTABLE[14])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_UARTCharPutNonBlocking                                            \
+        ((tBoolean (*)(unsigned long ulBase,                                  \
+                       unsigned char ucData))ROM_UARTTABLE[15])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_UARTBreakCtl                                                      \
+        ((void (*)(unsigned long ulBase,                                      \
+                   tBoolean bBreakState))ROM_UARTTABLE[16])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_UARTIntEnable                                                     \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulIntFlags))ROM_UARTTABLE[17])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_UARTIntDisable                                                    \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulIntFlags))ROM_UARTTABLE[18])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_UARTIntStatus                                                     \
+        ((unsigned long (*)(unsigned long ulBase,                             \
+                            tBoolean bMasked))ROM_UARTTABLE[19])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_UARTIntClear                                                      \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulIntFlags))ROM_UARTTABLE[20])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_UpdateUART                                                        \
+        ((void (*)(void))ROM_UARTTABLE[21])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_UARTDMAEnable                                                     \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulDMAFlags))ROM_UARTTABLE[22])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_UARTDMADisable                                                    \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulDMAFlags))ROM_UARTTABLE[23])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_UARTFIFOEnable                                                    \
+        ((void (*)(unsigned long ulBase))ROM_UARTTABLE[24])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_UARTFIFODisable                                                   \
+        ((void (*)(unsigned long ulBase))ROM_UARTTABLE[25])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_UARTBusy                                                          \
+        ((tBoolean (*)(unsigned long ulBase))ROM_UARTTABLE[26])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_UARTTxIntModeSet                                                  \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulMode))ROM_UARTTABLE[27])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_UARTTxIntModeGet                                                  \
+        ((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[28])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_UARTRxErrorGet                                                    \
+        ((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[29])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_UARTRxErrorClear                                                  \
+        ((void (*)(unsigned long ulBase))ROM_UARTTABLE[30])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the uDMA API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_uDMAChannelTransferSet                                            \
+        ((void (*)(unsigned long ulChannelStructIndex,                        \
+                   unsigned long ulMode,                                      \
+                   void *pvSrcAddr,                                           \
+                   void *pvDstAddr,                                           \
+                   unsigned long ulTransferSize))ROM_UDMATABLE[0])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_uDMAEnable                                                        \
+        ((void (*)(void))ROM_UDMATABLE[1])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_uDMADisable                                                       \
+        ((void (*)(void))ROM_UDMATABLE[2])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_uDMAErrorStatusGet                                                \
+        ((unsigned long (*)(void))ROM_UDMATABLE[3])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_uDMAErrorStatusClear                                              \
+        ((void (*)(void))ROM_UDMATABLE[4])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_uDMAChannelEnable                                                 \
+        ((void (*)(unsigned long ulChannelNum))ROM_UDMATABLE[5])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_uDMAChannelDisable                                                \
+        ((void (*)(unsigned long ulChannelNum))ROM_UDMATABLE[6])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_uDMAChannelIsEnabled                                              \
+        ((tBoolean (*)(unsigned long ulChannelNum))ROM_UDMATABLE[7])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_uDMAControlBaseSet                                                \
+        ((void (*)(void *pControlTable))ROM_UDMATABLE[8])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_uDMAControlBaseGet                                                \
+        ((void * (*)(void))ROM_UDMATABLE[9])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_uDMAChannelRequest                                                \
+        ((void (*)(unsigned long ulChannelNum))ROM_UDMATABLE[10])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_uDMAChannelAttributeEnable                                        \
+        ((void (*)(unsigned long ulChannelNum,                                \
+                   unsigned long ulAttr))ROM_UDMATABLE[11])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_uDMAChannelAttributeDisable                                       \
+        ((void (*)(unsigned long ulChannelNum,                                \
+                   unsigned long ulAttr))ROM_UDMATABLE[12])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_uDMAChannelAttributeGet                                           \
+        ((unsigned long (*)(unsigned long ulChannelNum))ROM_UDMATABLE[13])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_uDMAChannelControlSet                                             \
+        ((void (*)(unsigned long ulChannelStructIndex,                        \
+                   unsigned long ulControl))ROM_UDMATABLE[14])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_uDMAChannelSizeGet                                                \
+        ((unsigned long (*)(unsigned long ulChannelStructIndex))ROM_UDMATABLE[15])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_uDMAChannelModeGet                                                \
+        ((unsigned long (*)(unsigned long ulChannelStructIndex))ROM_UDMATABLE[16])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_uDMAChannelSelectSecondary                                        \
+        ((void (*)(unsigned long ulSecPeriphs))ROM_UDMATABLE[17])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_uDMAChannelSelectDefault                                          \
+        ((void (*)(unsigned long ulDefPeriphs))ROM_UDMATABLE[18])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_uDMAControlAlternateBaseGet                                       \
+        ((void * (*)(void))ROM_UDMATABLE[21])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_uDMAChannelScatterGatherSet                                       \
+        ((void (*)(unsigned long ulChannelNum,                                \
+                   unsigned ulTaskCount,                                      \
+                   void *pvTaskList,                                          \
+                   unsigned long ulIsPeriphSG))ROM_UDMATABLE[22])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the USB API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_USBIntStatus                                                      \
+        ((unsigned long (*)(unsigned long ulBase))ROM_USBTABLE[0])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_USBDevAddrGet                                                     \
+        ((unsigned long (*)(unsigned long ulBase))ROM_USBTABLE[1])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_USBDevAddrSet                                                     \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulAddress))ROM_USBTABLE[2])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_USBDevConnect                                                     \
+        ((void (*)(unsigned long ulBase))ROM_USBTABLE[3])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_USBDevDisconnect                                                  \
+        ((void (*)(unsigned long ulBase))ROM_USBTABLE[4])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_USBDevEndpointConfigSet                                           \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulEndpoint,                                  \
+                   unsigned long ulMaxPacketSize,                             \
+                   unsigned long ulFlags))ROM_USBTABLE[5])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_USBDevEndpointDataAck                                             \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulEndpoint,                                  \
+                   tBoolean bIsLastPacket))ROM_USBTABLE[6])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_USBDevEndpointStall                                               \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulEndpoint,                                  \
+                   unsigned long ulFlags))ROM_USBTABLE[7])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_USBDevEndpointStallClear                                          \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulEndpoint,                                  \
+                   unsigned long ulFlags))ROM_USBTABLE[8])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_USBDevEndpointStatusClear                                         \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulEndpoint,                                  \
+                   unsigned long ulFlags))ROM_USBTABLE[9])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_USBEndpointDataGet                                                \
+        ((long (*)(unsigned long ulBase,                                      \
+                   unsigned long ulEndpoint,                                  \
+                   unsigned char *pucData,                                    \
+                   unsigned long *pulSize))ROM_USBTABLE[10])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_USBEndpointDataPut                                                \
+        ((long (*)(unsigned long ulBase,                                      \
+                   unsigned long ulEndpoint,                                  \
+                   unsigned char *pucData,                                    \
+                   unsigned long ulSize))ROM_USBTABLE[11])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_USBEndpointDataSend                                               \
+        ((long (*)(unsigned long ulBase,                                      \
+                   unsigned long ulEndpoint,                                  \
+                   unsigned long ulTransType))ROM_USBTABLE[12])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_USBEndpointDataToggleClear                                        \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulEndpoint,                                  \
+                   unsigned long ulFlags))ROM_USBTABLE[13])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_USBEndpointStatus                                                 \
+        ((unsigned long (*)(unsigned long ulBase,                             \
+                            unsigned long ulEndpoint))ROM_USBTABLE[14])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_USBFIFOAddrGet                                                    \
+        ((unsigned long (*)(unsigned long ulBase,                             \
+                            unsigned long ulEndpoint))ROM_USBTABLE[15])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_USBFIFOConfigGet                                                  \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulEndpoint,                                  \
+                   unsigned long *pulFIFOAddress,                             \
+                   unsigned long *pulFIFOSize,                                \
+                   unsigned long ulFlags))ROM_USBTABLE[16])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_USBFIFOConfigSet                                                  \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulEndpoint,                                  \
+                   unsigned long ulFIFOAddress,                               \
+                   unsigned long ulFIFOSize,                                  \
+                   unsigned long ulFlags))ROM_USBTABLE[17])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_USBFIFOFlush                                                      \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulEndpoint,                                  \
+                   unsigned long ulFlags))ROM_USBTABLE[18])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_USBFrameNumberGet                                                 \
+        ((unsigned long (*)(unsigned long ulBase))ROM_USBTABLE[19])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_USBHostAddrGet                                                    \
+        ((unsigned long (*)(unsigned long ulBase,                             \
+                            unsigned long ulEndpoint,                         \
+                            unsigned long ulFlags))ROM_USBTABLE[20])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_USBHostAddrSet                                                    \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulEndpoint,                                  \
+                   unsigned long ulAddr,                                      \
+                   unsigned long ulFlags))ROM_USBTABLE[21])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_USBHostEndpointDataAck                                            \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulEndpoint))ROM_USBTABLE[23])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_USBHostEndpointDataToggle                                         \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulEndpoint,                                  \
+                   tBoolean bDataToggle,                                      \
+                   unsigned long ulFlags))ROM_USBTABLE[24])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_USBHostEndpointStatusClear                                        \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulEndpoint,                                  \
+                   unsigned long ulFlags))ROM_USBTABLE[25])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_USBHostHubAddrGet                                                 \
+        ((unsigned long (*)(unsigned long ulBase,                             \
+                            unsigned long ulEndpoint,                         \
+                            unsigned long ulFlags))ROM_USBTABLE[26])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_USBHostHubAddrSet                                                 \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulEndpoint,                                  \
+                   unsigned long ulAddr,                                      \
+                   unsigned long ulFlags))ROM_USBTABLE[27])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_USBHostPwrDisable                                                 \
+        ((void (*)(unsigned long ulBase))ROM_USBTABLE[28])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_USBHostPwrEnable                                                  \
+        ((void (*)(unsigned long ulBase))ROM_USBTABLE[29])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_USBHostPwrConfig                                                  \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulFlags))ROM_USBTABLE[30])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_USBHostPwrFaultDisable                                            \
+        ((void (*)(unsigned long ulBase))ROM_USBTABLE[31])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_USBHostPwrFaultEnable                                             \
+        ((void (*)(unsigned long ulBase))ROM_USBTABLE[32])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_USBHostRequestIN                                                  \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulEndpoint))ROM_USBTABLE[33])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_USBHostRequestStatus                                              \
+        ((void (*)(unsigned long ulBase))ROM_USBTABLE[34])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_USBHostReset                                                      \
+        ((void (*)(unsigned long ulBase,                                      \
+                   tBoolean bStart))ROM_USBTABLE[35])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_USBHostResume                                                     \
+        ((void (*)(unsigned long ulBase,                                      \
+                   tBoolean bStart))ROM_USBTABLE[36])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_USBHostSpeedGet                                                   \
+        ((unsigned long (*)(unsigned long ulBase))ROM_USBTABLE[37])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_USBHostSuspend                                                    \
+        ((void (*)(unsigned long ulBase))ROM_USBTABLE[38])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_USBIntDisable                                                     \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulIntFlags))ROM_USBTABLE[39])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_USBIntEnable                                                      \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulIntFlags))ROM_USBTABLE[40])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_USBDevEndpointConfigGet                                           \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulEndpoint,                                  \
+                   unsigned long *pulMaxPacketSize,                           \
+                   unsigned long *pulFlags))ROM_USBTABLE[41])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_USBEndpointDMAEnable                                              \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulEndpoint,                                  \
+                   unsigned long ulFlags))ROM_USBTABLE[42])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_USBEndpointDMADisable                                             \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulEndpoint,                                  \
+                   unsigned long ulFlags))ROM_USBTABLE[43])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_USBEndpointDataAvail                                              \
+        ((unsigned long (*)(unsigned long ulBase,                             \
+                            unsigned long ulEndpoint))ROM_USBTABLE[44])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_USBOTGHostRequest                                                 \
+        ((void (*)(unsigned long ulBase,                                      \
+                   tBoolean bHNP))ROM_USBTABLE[45])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_USBModeGet                                                        \
+        ((unsigned long (*)(unsigned long ulBase))ROM_USBTABLE[46])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_USBEndpointDMAChannel                                             \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulEndpoint,                                  \
+                   unsigned long ulChannel))ROM_USBTABLE[47])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_USBIntDisableControl                                              \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulIntFlags))ROM_USBTABLE[48])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_USBIntEnableControl                                               \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulIntFlags))ROM_USBTABLE[49])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_USBIntStatusControl                                               \
+        ((unsigned long (*)(unsigned long ulBase))ROM_USBTABLE[50])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_USBIntDisableEndpoint                                             \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulIntFlags))ROM_USBTABLE[51])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_USBIntEnableEndpoint                                              \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulIntFlags))ROM_USBTABLE[52])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_USBIntStatusEndpoint                                              \
+        ((unsigned long (*)(unsigned long ulBase))ROM_USBTABLE[53])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_USBHostMode                                                       \
+        ((void (*)(unsigned long ulBase))ROM_USBTABLE[54])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_USBDevMode                                                        \
+        ((void (*)(unsigned long ulBase))ROM_USBTABLE[55])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_USBPHYPowerOff                                                    \
+        ((void (*)(unsigned long ulBase))ROM_USBTABLE[56])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_USBPHYPowerOn                                                     \
+        ((void (*)(unsigned long ulBase))ROM_USBTABLE[57])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the Watchdog API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_WatchdogIntClear                                                  \
+        ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[0])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_WatchdogRunning                                                   \
+        ((tBoolean (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[1])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_WatchdogEnable                                                    \
+        ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_WatchdogResetEnable                                               \
+        ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_WatchdogResetDisable                                              \
+        ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_WatchdogLock                                                      \
+        ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_WatchdogUnlock                                                    \
+        ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[6])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_WatchdogLockState                                                 \
+        ((tBoolean (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[7])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_WatchdogReloadSet                                                 \
+        ((void (*)(unsigned long ulBase,                                      \
+                   unsigned long ulLoadVal))ROM_WATCHDOGTABLE[8])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_WatchdogReloadGet                                                 \
+        ((unsigned long (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[9])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_WatchdogValueGet                                                  \
+        ((unsigned long (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[10])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_WatchdogIntEnable                                                 \
+        ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[11])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_WatchdogIntStatus                                                 \
+        ((unsigned long (*)(unsigned long ulBase,                             \
+                            tBoolean bMasked))ROM_WATCHDOGTABLE[12])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_WatchdogStallEnable                                               \
+        ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[13])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+    defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_WatchdogStallDisable                                              \
+        ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[14])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the Software API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_Crc16Array                                                        \
+        ((unsigned short (*)(unsigned long ulWordLen,                         \
+                             const unsigned long *pulData))ROM_SOFTWARETABLE[1])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_Crc16Array3                                                       \
+        ((void (*)(unsigned long ulWordLen,                                   \
+                   const unsigned long *pulData,                              \
+                   unsigned short *pusCrc3))ROM_SOFTWARETABLE[2])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+    defined(TARGET_IS_TEMPEST_RC1) || \
+    defined(TARGET_IS_TEMPEST_RC3) || \
+    defined(TARGET_IS_TEMPEST_RC5) || \
+    defined(TARGET_IS_FIRESTORM_RA2)
+#define ROM_pvAESTable                                                        \
+        ((void *)&(ROM_SOFTWARETABLE[7]))
+#endif
+
+//*****************************************************************************
+//
+// Deprecated ROM functions.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+#ifdef ROM_FlashIntStatus
+#define ROM_FlashIntGetStatus \
+        ROM_FlashIntStatus
+#endif
+#ifdef ROM_USBDevEndpointConfigSet
+#define ROM_USBDevEndpointConfig \
+        ROM_USBDevEndpointConfigSet
+#endif
+#ifdef ROM_USBHostPwrConfig
+#define ROM_USBHostPwrFaultConfig \
+        ROM_USBHostPwrConfig
+#endif
+#endif
+
+#endif // __ROM_H__
diff --git a/src/platform/lm3s/rom_map.h b/src/platform/lm3s/driverlib/rom_map.h
similarity index 75%
rename from src/platform/lm3s/rom_map.h
rename to src/platform/lm3s/driverlib/rom_map.h
index 56aab994..d46dd354 100755
--- a/src/platform/lm3s/rom_map.h
+++ b/src/platform/lm3s/driverlib/rom_map.h
@@ -3,26 +3,23 @@
 // rom_map.h - Macros to facilitate calling functions in the ROM when they are
 //             available and in flash otherwise.
 //
-// Copyright (c) 2008-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2008-2011 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
+// This is part of revision 7611 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -139,6 +136,97 @@
 #define MAP_ADCHardwareOversampleConfigure \
         ADCHardwareOversampleConfigure
 #endif
+#ifdef ROM_ADCComparatorConfigure
+#define MAP_ADCComparatorConfigure \
+        ROM_ADCComparatorConfigure
+#else
+#define MAP_ADCComparatorConfigure \
+        ADCComparatorConfigure
+#endif
+#ifdef ROM_ADCComparatorRegionSet
+#define MAP_ADCComparatorRegionSet \
+        ROM_ADCComparatorRegionSet
+#else
+#define MAP_ADCComparatorRegionSet \
+        ADCComparatorRegionSet
+#endif
+#ifdef ROM_ADCComparatorReset
+#define MAP_ADCComparatorReset \
+        ROM_ADCComparatorReset
+#else
+#define MAP_ADCComparatorReset \
+        ADCComparatorReset
+#endif
+#ifdef ROM_ADCComparatorIntDisable
+#define MAP_ADCComparatorIntDisable \
+        ROM_ADCComparatorIntDisable
+#else
+#define MAP_ADCComparatorIntDisable \
+        ADCComparatorIntDisable
+#endif
+#ifdef ROM_ADCComparatorIntEnable
+#define MAP_ADCComparatorIntEnable \
+        ROM_ADCComparatorIntEnable
+#else
+#define MAP_ADCComparatorIntEnable \
+        ADCComparatorIntEnable
+#endif
+#ifdef ROM_ADCComparatorIntStatus
+#define MAP_ADCComparatorIntStatus \
+        ROM_ADCComparatorIntStatus
+#else
+#define MAP_ADCComparatorIntStatus \
+        ADCComparatorIntStatus
+#endif
+#ifdef ROM_ADCComparatorIntClear
+#define MAP_ADCComparatorIntClear \
+        ROM_ADCComparatorIntClear
+#else
+#define MAP_ADCComparatorIntClear \
+        ADCComparatorIntClear
+#endif
+#ifdef ROM_ADCReferenceSet
+#define MAP_ADCReferenceSet \
+        ROM_ADCReferenceSet
+#else
+#define MAP_ADCReferenceSet \
+        ADCReferenceSet
+#endif
+#ifdef ROM_ADCReferenceGet
+#define MAP_ADCReferenceGet \
+        ROM_ADCReferenceGet
+#else
+#define MAP_ADCReferenceGet \
+        ADCReferenceGet
+#endif
+#ifdef ROM_ADCPhaseDelaySet
+#define MAP_ADCPhaseDelaySet \
+        ROM_ADCPhaseDelaySet
+#else
+#define MAP_ADCPhaseDelaySet \
+        ADCPhaseDelaySet
+#endif
+#ifdef ROM_ADCPhaseDelayGet
+#define MAP_ADCPhaseDelayGet \
+        ROM_ADCPhaseDelayGet
+#else
+#define MAP_ADCPhaseDelayGet \
+        ADCPhaseDelayGet
+#endif
+#ifdef ROM_ADCResolutionSet
+#define MAP_ADCResolutionSet \
+        ROM_ADCResolutionSet
+#else
+#define MAP_ADCResolutionSet \
+        ADCResolutionSet
+#endif
+#ifdef ROM_ADCResolutionGet
+#define MAP_ADCResolutionGet \
+        ROM_ADCResolutionGet
+#else
+#define MAP_ADCResolutionGet \
+        ADCResolutionGet
+#endif
 
 //*****************************************************************************
 //
@@ -257,6 +345,13 @@
 #define MAP_CANErrCntrGet \
         CANErrCntrGet
 #endif
+#ifdef ROM_CANBitRateSet
+#define MAP_CANBitRateSet \
+        ROM_CANBitRateSet
+#else
+#define MAP_CANBitRateSet \
+        CANBitRateSet
+#endif
 
 //*****************************************************************************
 //
@@ -313,6 +408,166 @@
         ComparatorIntStatus
 #endif
 
+//*****************************************************************************
+//
+// Macros for the EPI API.
+//
+//*****************************************************************************
+#ifdef ROM_EPIIntStatus
+#define MAP_EPIIntStatus \
+        ROM_EPIIntStatus
+#else
+#define MAP_EPIIntStatus \
+        EPIIntStatus
+#endif
+#ifdef ROM_EPIModeSet
+#define MAP_EPIModeSet \
+        ROM_EPIModeSet
+#else
+#define MAP_EPIModeSet \
+        EPIModeSet
+#endif
+#ifdef ROM_EPIDividerSet
+#define MAP_EPIDividerSet \
+        ROM_EPIDividerSet
+#else
+#define MAP_EPIDividerSet \
+        EPIDividerSet
+#endif
+#ifdef ROM_EPIConfigSDRAMSet
+#define MAP_EPIConfigSDRAMSet \
+        ROM_EPIConfigSDRAMSet
+#else
+#define MAP_EPIConfigSDRAMSet \
+        EPIConfigSDRAMSet
+#endif
+#ifdef ROM_EPIConfigGPModeSet
+#define MAP_EPIConfigGPModeSet \
+        ROM_EPIConfigGPModeSet
+#else
+#define MAP_EPIConfigGPModeSet \
+        EPIConfigGPModeSet
+#endif
+#ifdef ROM_EPIConfigHB8Set
+#define MAP_EPIConfigHB8Set \
+        ROM_EPIConfigHB8Set
+#else
+#define MAP_EPIConfigHB8Set \
+        EPIConfigHB8Set
+#endif
+#ifdef ROM_EPIConfigHB16Set
+#define MAP_EPIConfigHB16Set \
+        ROM_EPIConfigHB16Set
+#else
+#define MAP_EPIConfigHB16Set \
+        EPIConfigHB16Set
+#endif
+#ifdef ROM_EPIAddressMapSet
+#define MAP_EPIAddressMapSet \
+        ROM_EPIAddressMapSet
+#else
+#define MAP_EPIAddressMapSet \
+        EPIAddressMapSet
+#endif
+#ifdef ROM_EPINonBlockingReadConfigure
+#define MAP_EPINonBlockingReadConfigure \
+        ROM_EPINonBlockingReadConfigure
+#else
+#define MAP_EPINonBlockingReadConfigure \
+        EPINonBlockingReadConfigure
+#endif
+#ifdef ROM_EPINonBlockingReadStart
+#define MAP_EPINonBlockingReadStart \
+        ROM_EPINonBlockingReadStart
+#else
+#define MAP_EPINonBlockingReadStart \
+        EPINonBlockingReadStart
+#endif
+#ifdef ROM_EPINonBlockingReadStop
+#define MAP_EPINonBlockingReadStop \
+        ROM_EPINonBlockingReadStop
+#else
+#define MAP_EPINonBlockingReadStop \
+        EPINonBlockingReadStop
+#endif
+#ifdef ROM_EPINonBlockingReadCount
+#define MAP_EPINonBlockingReadCount \
+        ROM_EPINonBlockingReadCount
+#else
+#define MAP_EPINonBlockingReadCount \
+        EPINonBlockingReadCount
+#endif
+#ifdef ROM_EPINonBlockingReadAvail
+#define MAP_EPINonBlockingReadAvail \
+        ROM_EPINonBlockingReadAvail
+#else
+#define MAP_EPINonBlockingReadAvail \
+        EPINonBlockingReadAvail
+#endif
+#ifdef ROM_EPINonBlockingReadGet32
+#define MAP_EPINonBlockingReadGet32 \
+        ROM_EPINonBlockingReadGet32
+#else
+#define MAP_EPINonBlockingReadGet32 \
+        EPINonBlockingReadGet32
+#endif
+#ifdef ROM_EPINonBlockingReadGet16
+#define MAP_EPINonBlockingReadGet16 \
+        ROM_EPINonBlockingReadGet16
+#else
+#define MAP_EPINonBlockingReadGet16 \
+        EPINonBlockingReadGet16
+#endif
+#ifdef ROM_EPINonBlockingReadGet8
+#define MAP_EPINonBlockingReadGet8 \
+        ROM_EPINonBlockingReadGet8
+#else
+#define MAP_EPINonBlockingReadGet8 \
+        EPINonBlockingReadGet8
+#endif
+#ifdef ROM_EPIFIFOConfig
+#define MAP_EPIFIFOConfig \
+        ROM_EPIFIFOConfig
+#else
+#define MAP_EPIFIFOConfig \
+        EPIFIFOConfig
+#endif
+#ifdef ROM_EPIWriteFIFOCountGet
+#define MAP_EPIWriteFIFOCountGet \
+        ROM_EPIWriteFIFOCountGet
+#else
+#define MAP_EPIWriteFIFOCountGet \
+        EPIWriteFIFOCountGet
+#endif
+#ifdef ROM_EPIIntEnable
+#define MAP_EPIIntEnable \
+        ROM_EPIIntEnable
+#else
+#define MAP_EPIIntEnable \
+        EPIIntEnable
+#endif
+#ifdef ROM_EPIIntDisable
+#define MAP_EPIIntDisable \
+        ROM_EPIIntDisable
+#else
+#define MAP_EPIIntDisable \
+        EPIIntDisable
+#endif
+#ifdef ROM_EPIIntErrorStatus
+#define MAP_EPIIntErrorStatus \
+        ROM_EPIIntErrorStatus
+#else
+#define MAP_EPIIntErrorStatus \
+        EPIIntErrorStatus
+#endif
+#ifdef ROM_EPIIntErrorClear
+#define MAP_EPIIntErrorClear \
+        ROM_EPIIntErrorClear
+#else
+#define MAP_EPIIntErrorClear \
+        EPIIntErrorClear
+#endif
+
 //*****************************************************************************
 //
 // Macros for the Ethernet API.
@@ -451,6 +706,20 @@
 #define MAP_EthernetPHYRead \
         EthernetPHYRead
 #endif
+#ifdef ROM_EthernetPHYPowerOff
+#define MAP_EthernetPHYPowerOff \
+        ROM_EthernetPHYPowerOff
+#else
+#define MAP_EthernetPHYPowerOff \
+        EthernetPHYPowerOff
+#endif
+#ifdef ROM_EthernetPHYPowerOn
+#define MAP_EthernetPHYPowerOn \
+        ROM_EthernetPHYPowerOn
+#else
+#define MAP_EthernetPHYPowerOn \
+        EthernetPHYPowerOn
+#endif
 
 //*****************************************************************************
 //
@@ -541,12 +810,12 @@
 #define MAP_FlashIntDisable \
         FlashIntDisable
 #endif
-#ifdef ROM_FlashIntGetStatus
-#define MAP_FlashIntGetStatus \
-        ROM_FlashIntGetStatus
+#ifdef ROM_FlashIntStatus
+#define MAP_FlashIntStatus \
+        ROM_FlashIntStatus
 #else
-#define MAP_FlashIntGetStatus \
-        FlashIntGetStatus
+#define MAP_FlashIntStatus \
+        FlashIntStatus
 #endif
 #ifdef ROM_FlashIntClear
 #define MAP_FlashIntClear \
@@ -736,6 +1005,48 @@
 #define MAP_GPIOPinTypeUSBDigital \
         GPIOPinTypeUSBDigital
 #endif
+#ifdef ROM_GPIOPinTypeI2S
+#define MAP_GPIOPinTypeI2S \
+        ROM_GPIOPinTypeI2S
+#else
+#define MAP_GPIOPinTypeI2S \
+        GPIOPinTypeI2S
+#endif
+#ifdef ROM_GPIOPinConfigure
+#define MAP_GPIOPinConfigure \
+        ROM_GPIOPinConfigure
+#else
+#define MAP_GPIOPinConfigure \
+        GPIOPinConfigure
+#endif
+#ifdef ROM_GPIOPinTypeEthernetLED
+#define MAP_GPIOPinTypeEthernetLED \
+        ROM_GPIOPinTypeEthernetLED
+#else
+#define MAP_GPIOPinTypeEthernetLED \
+        GPIOPinTypeEthernetLED
+#endif
+#ifdef ROM_GPIOPinTypeUSBAnalog
+#define MAP_GPIOPinTypeUSBAnalog \
+        ROM_GPIOPinTypeUSBAnalog
+#else
+#define MAP_GPIOPinTypeUSBAnalog \
+        GPIOPinTypeUSBAnalog
+#endif
+#ifdef ROM_GPIOPinTypeEPI
+#define MAP_GPIOPinTypeEPI \
+        ROM_GPIOPinTypeEPI
+#else
+#define MAP_GPIOPinTypeEPI \
+        GPIOPinTypeEPI
+#endif
+#ifdef ROM_GPIOPinTypeEthernetMII
+#define MAP_GPIOPinTypeEthernetMII \
+        ROM_GPIOPinTypeEthernetMII
+#else
+#define MAP_GPIOPinTypeEthernetMII \
+        GPIOPinTypeEthernetMII
+#endif
 
 //*****************************************************************************
 //
@@ -1091,6 +1402,208 @@
 #define MAP_I2CSlaveDataGet \
         I2CSlaveDataGet
 #endif
+#ifdef ROM_I2CSlaveIntEnableEx
+#define MAP_I2CSlaveIntEnableEx \
+        ROM_I2CSlaveIntEnableEx
+#else
+#define MAP_I2CSlaveIntEnableEx \
+        I2CSlaveIntEnableEx
+#endif
+#ifdef ROM_I2CSlaveIntDisableEx
+#define MAP_I2CSlaveIntDisableEx \
+        ROM_I2CSlaveIntDisableEx
+#else
+#define MAP_I2CSlaveIntDisableEx \
+        I2CSlaveIntDisableEx
+#endif
+#ifdef ROM_I2CSlaveIntStatusEx
+#define MAP_I2CSlaveIntStatusEx \
+        ROM_I2CSlaveIntStatusEx
+#else
+#define MAP_I2CSlaveIntStatusEx \
+        I2CSlaveIntStatusEx
+#endif
+#ifdef ROM_I2CSlaveIntClearEx
+#define MAP_I2CSlaveIntClearEx \
+        ROM_I2CSlaveIntClearEx
+#else
+#define MAP_I2CSlaveIntClearEx \
+        I2CSlaveIntClearEx
+#endif
+
+//*****************************************************************************
+//
+// Macros for the I2S API.
+//
+//*****************************************************************************
+#ifdef ROM_I2SIntStatus
+#define MAP_I2SIntStatus \
+        ROM_I2SIntStatus
+#else
+#define MAP_I2SIntStatus \
+        I2SIntStatus
+#endif
+#ifdef ROM_I2STxEnable
+#define MAP_I2STxEnable \
+        ROM_I2STxEnable
+#else
+#define MAP_I2STxEnable \
+        I2STxEnable
+#endif
+#ifdef ROM_I2STxDisable
+#define MAP_I2STxDisable \
+        ROM_I2STxDisable
+#else
+#define MAP_I2STxDisable \
+        I2STxDisable
+#endif
+#ifdef ROM_I2STxDataPut
+#define MAP_I2STxDataPut \
+        ROM_I2STxDataPut
+#else
+#define MAP_I2STxDataPut \
+        I2STxDataPut
+#endif
+#ifdef ROM_I2STxDataPutNonBlocking
+#define MAP_I2STxDataPutNonBlocking \
+        ROM_I2STxDataPutNonBlocking
+#else
+#define MAP_I2STxDataPutNonBlocking \
+        I2STxDataPutNonBlocking
+#endif
+#ifdef ROM_I2STxConfigSet
+#define MAP_I2STxConfigSet \
+        ROM_I2STxConfigSet
+#else
+#define MAP_I2STxConfigSet \
+        I2STxConfigSet
+#endif
+#ifdef ROM_I2STxFIFOLimitSet
+#define MAP_I2STxFIFOLimitSet \
+        ROM_I2STxFIFOLimitSet
+#else
+#define MAP_I2STxFIFOLimitSet \
+        I2STxFIFOLimitSet
+#endif
+#ifdef ROM_I2STxFIFOLimitGet
+#define MAP_I2STxFIFOLimitGet \
+        ROM_I2STxFIFOLimitGet
+#else
+#define MAP_I2STxFIFOLimitGet \
+        I2STxFIFOLimitGet
+#endif
+#ifdef ROM_I2STxFIFOLevelGet
+#define MAP_I2STxFIFOLevelGet \
+        ROM_I2STxFIFOLevelGet
+#else
+#define MAP_I2STxFIFOLevelGet \
+        I2STxFIFOLevelGet
+#endif
+#ifdef ROM_I2SRxEnable
+#define MAP_I2SRxEnable \
+        ROM_I2SRxEnable
+#else
+#define MAP_I2SRxEnable \
+        I2SRxEnable
+#endif
+#ifdef ROM_I2SRxDisable
+#define MAP_I2SRxDisable \
+        ROM_I2SRxDisable
+#else
+#define MAP_I2SRxDisable \
+        I2SRxDisable
+#endif
+#ifdef ROM_I2SRxDataGet
+#define MAP_I2SRxDataGet \
+        ROM_I2SRxDataGet
+#else
+#define MAP_I2SRxDataGet \
+        I2SRxDataGet
+#endif
+#ifdef ROM_I2SRxDataGetNonBlocking
+#define MAP_I2SRxDataGetNonBlocking \
+        ROM_I2SRxDataGetNonBlocking
+#else
+#define MAP_I2SRxDataGetNonBlocking \
+        I2SRxDataGetNonBlocking
+#endif
+#ifdef ROM_I2SRxConfigSet
+#define MAP_I2SRxConfigSet \
+        ROM_I2SRxConfigSet
+#else
+#define MAP_I2SRxConfigSet \
+        I2SRxConfigSet
+#endif
+#ifdef ROM_I2SRxFIFOLimitSet
+#define MAP_I2SRxFIFOLimitSet \
+        ROM_I2SRxFIFOLimitSet
+#else
+#define MAP_I2SRxFIFOLimitSet \
+        I2SRxFIFOLimitSet
+#endif
+#ifdef ROM_I2SRxFIFOLimitGet
+#define MAP_I2SRxFIFOLimitGet \
+        ROM_I2SRxFIFOLimitGet
+#else
+#define MAP_I2SRxFIFOLimitGet \
+        I2SRxFIFOLimitGet
+#endif
+#ifdef ROM_I2SRxFIFOLevelGet
+#define MAP_I2SRxFIFOLevelGet \
+        ROM_I2SRxFIFOLevelGet
+#else
+#define MAP_I2SRxFIFOLevelGet \
+        I2SRxFIFOLevelGet
+#endif
+#ifdef ROM_I2STxRxEnable
+#define MAP_I2STxRxEnable \
+        ROM_I2STxRxEnable
+#else
+#define MAP_I2STxRxEnable \
+        I2STxRxEnable
+#endif
+#ifdef ROM_I2STxRxDisable
+#define MAP_I2STxRxDisable \
+        ROM_I2STxRxDisable
+#else
+#define MAP_I2STxRxDisable \
+        I2STxRxDisable
+#endif
+#ifdef ROM_I2STxRxConfigSet
+#define MAP_I2STxRxConfigSet \
+        ROM_I2STxRxConfigSet
+#else
+#define MAP_I2STxRxConfigSet \
+        I2STxRxConfigSet
+#endif
+#ifdef ROM_I2SMasterClockSelect
+#define MAP_I2SMasterClockSelect \
+        ROM_I2SMasterClockSelect
+#else
+#define MAP_I2SMasterClockSelect \
+        I2SMasterClockSelect
+#endif
+#ifdef ROM_I2SIntEnable
+#define MAP_I2SIntEnable \
+        ROM_I2SIntEnable
+#else
+#define MAP_I2SIntEnable \
+        I2SIntEnable
+#endif
+#ifdef ROM_I2SIntDisable
+#define MAP_I2SIntDisable \
+        ROM_I2SIntDisable
+#else
+#define MAP_I2SIntDisable \
+        I2SIntDisable
+#endif
+#ifdef ROM_I2SIntClear
+#define MAP_I2SIntClear \
+        ROM_I2SIntClear
+#else
+#define MAP_I2SIntClear \
+        I2SIntClear
+#endif
 
 //*****************************************************************************
 //
@@ -1153,6 +1666,34 @@
 #define MAP_IntPriorityGet \
         IntPriorityGet
 #endif
+#ifdef ROM_IntPendSet
+#define MAP_IntPendSet \
+        ROM_IntPendSet
+#else
+#define MAP_IntPendSet \
+        IntPendSet
+#endif
+#ifdef ROM_IntPendClear
+#define MAP_IntPendClear \
+        ROM_IntPendClear
+#else
+#define MAP_IntPendClear \
+        IntPendClear
+#endif
+#ifdef ROM_IntPriorityMaskSet
+#define MAP_IntPriorityMaskSet \
+        ROM_IntPriorityMaskSet
+#else
+#define MAP_IntPriorityMaskSet \
+        IntPriorityMaskSet
+#endif
+#ifdef ROM_IntPriorityMaskGet
+#define MAP_IntPriorityMaskGet \
+        ROM_IntPriorityMaskGet
+#else
+#define MAP_IntPriorityMaskGet \
+        IntPriorityMaskGet
+#endif
 
 //*****************************************************************************
 //
@@ -1625,6 +2166,13 @@
 #define MAP_SSIDMADisable \
         SSIDMADisable
 #endif
+#ifdef ROM_SSIBusy
+#define MAP_SSIBusy \
+        ROM_SSIBusy
+#else
+#define MAP_SSIBusy \
+        SSIBusy
+#endif
 
 //*****************************************************************************
 //
@@ -1862,6 +2410,20 @@
 #define MAP_SysCtlUSBPLLDisable \
         SysCtlUSBPLLDisable
 #endif
+#ifdef ROM_SysCtlI2SMClkSet
+#define MAP_SysCtlI2SMClkSet \
+        ROM_SysCtlI2SMClkSet
+#else
+#define MAP_SysCtlI2SMClkSet \
+        SysCtlI2SMClkSet
+#endif
+#ifdef ROM_SysCtlDelay
+#define MAP_SysCtlDelay \
+        ROM_SysCtlDelay
+#else
+#define MAP_SysCtlDelay \
+        SysCtlDelay
+#endif
 
 //*****************************************************************************
 //
@@ -2007,6 +2569,20 @@
 #define MAP_TimerPrescaleGet \
         TimerPrescaleGet
 #endif
+#ifdef ROM_TimerPrescaleMatchSet
+#define MAP_TimerPrescaleMatchSet \
+        ROM_TimerPrescaleMatchSet
+#else
+#define MAP_TimerPrescaleMatchSet \
+        TimerPrescaleMatchSet
+#endif
+#ifdef ROM_TimerPrescaleMatchGet
+#define MAP_TimerPrescaleMatchGet \
+        ROM_TimerPrescaleMatchGet
+#else
+#define MAP_TimerPrescaleMatchGet \
+        TimerPrescaleMatchGet
+#endif
 #ifdef ROM_TimerLoadSet
 #define MAP_TimerLoadSet \
         ROM_TimerLoadSet
@@ -2063,6 +2639,13 @@
 #define MAP_TimerIntStatus \
         TimerIntStatus
 #endif
+#ifdef ROM_TimerControlWaitOnTrigger
+#define MAP_TimerControlWaitOnTrigger \
+        ROM_TimerControlWaitOnTrigger
+#else
+#define MAP_TimerControlWaitOnTrigger \
+        TimerControlWaitOnTrigger
+#endif
 
 //*****************************************************************************
 //
@@ -2230,6 +2813,55 @@
 #define MAP_UARTDMADisable \
         UARTDMADisable
 #endif
+#ifdef ROM_UARTFIFOEnable
+#define MAP_UARTFIFOEnable \
+        ROM_UARTFIFOEnable
+#else
+#define MAP_UARTFIFOEnable \
+        UARTFIFOEnable
+#endif
+#ifdef ROM_UARTFIFODisable
+#define MAP_UARTFIFODisable \
+        ROM_UARTFIFODisable
+#else
+#define MAP_UARTFIFODisable \
+        UARTFIFODisable
+#endif
+#ifdef ROM_UARTBusy
+#define MAP_UARTBusy \
+        ROM_UARTBusy
+#else
+#define MAP_UARTBusy \
+        UARTBusy
+#endif
+#ifdef ROM_UARTTxIntModeSet
+#define MAP_UARTTxIntModeSet \
+        ROM_UARTTxIntModeSet
+#else
+#define MAP_UARTTxIntModeSet \
+        UARTTxIntModeSet
+#endif
+#ifdef ROM_UARTTxIntModeGet
+#define MAP_UARTTxIntModeGet \
+        ROM_UARTTxIntModeGet
+#else
+#define MAP_UARTTxIntModeGet \
+        UARTTxIntModeGet
+#endif
+#ifdef ROM_UARTRxErrorGet
+#define MAP_UARTRxErrorGet \
+        ROM_UARTRxErrorGet
+#else
+#define MAP_UARTRxErrorGet \
+        UARTRxErrorGet
+#endif
+#ifdef ROM_UARTRxErrorClear
+#define MAP_UARTRxErrorClear \
+        ROM_UARTRxErrorClear
+#else
+#define MAP_UARTRxErrorClear \
+        UARTRxErrorClear
+#endif
 
 //*****************************************************************************
 //
@@ -2355,6 +2987,34 @@
 #define MAP_uDMAChannelModeGet \
         uDMAChannelModeGet
 #endif
+#ifdef ROM_uDMAChannelSelectSecondary
+#define MAP_uDMAChannelSelectSecondary \
+        ROM_uDMAChannelSelectSecondary
+#else
+#define MAP_uDMAChannelSelectSecondary \
+        uDMAChannelSelectSecondary
+#endif
+#ifdef ROM_uDMAChannelSelectDefault
+#define MAP_uDMAChannelSelectDefault \
+        ROM_uDMAChannelSelectDefault
+#else
+#define MAP_uDMAChannelSelectDefault \
+        uDMAChannelSelectDefault
+#endif
+#ifdef ROM_uDMAControlAlternateBaseGet
+#define MAP_uDMAControlAlternateBaseGet \
+        ROM_uDMAControlAlternateBaseGet
+#else
+#define MAP_uDMAControlAlternateBaseGet \
+        uDMAControlAlternateBaseGet
+#endif
+#ifdef ROM_uDMAChannelScatterGatherSet
+#define MAP_uDMAChannelScatterGatherSet \
+        ROM_uDMAChannelScatterGatherSet
+#else
+#define MAP_uDMAChannelScatterGatherSet \
+        uDMAChannelScatterGatherSet
+#endif
 
 //*****************************************************************************
 //
@@ -2396,12 +3056,12 @@
 #define MAP_USBDevDisconnect \
         USBDevDisconnect
 #endif
-#ifdef ROM_USBDevEndpointConfig
-#define MAP_USBDevEndpointConfig \
-        ROM_USBDevEndpointConfig
+#ifdef ROM_USBDevEndpointConfigSet
+#define MAP_USBDevEndpointConfigSet \
+        ROM_USBDevEndpointConfigSet
 #else
-#define MAP_USBDevEndpointConfig \
-        USBDevEndpointConfig
+#define MAP_USBDevEndpointConfigSet \
+        USBDevEndpointConfigSet
 #endif
 #ifdef ROM_USBDevEndpointDataAck
 #define MAP_USBDevEndpointDataAck \
@@ -2515,13 +3175,6 @@
 #define MAP_USBHostAddrSet \
         USBHostAddrSet
 #endif
-#ifdef ROM_USBHostEndpointConfig
-#define MAP_USBHostEndpointConfig \
-        ROM_USBHostEndpointConfig
-#else
-#define MAP_USBHostEndpointConfig \
-        USBHostEndpointConfig
-#endif
 #ifdef ROM_USBHostEndpointDataAck
 #define MAP_USBHostEndpointDataAck \
         ROM_USBHostEndpointDataAck
@@ -2571,12 +3224,12 @@
 #define MAP_USBHostPwrEnable \
         USBHostPwrEnable
 #endif
-#ifdef ROM_USBHostPwrFaultConfig
-#define MAP_USBHostPwrFaultConfig \
-        ROM_USBHostPwrFaultConfig
+#ifdef ROM_USBHostPwrConfig
+#define MAP_USBHostPwrConfig \
+        ROM_USBHostPwrConfig
 #else
-#define MAP_USBHostPwrFaultConfig \
-        USBHostPwrFaultConfig
+#define MAP_USBHostPwrConfig \
+        USBHostPwrConfig
 #endif
 #ifdef ROM_USBHostPwrFaultDisable
 #define MAP_USBHostPwrFaultDisable \
@@ -2648,6 +3301,125 @@
 #define MAP_USBIntEnable \
         USBIntEnable
 #endif
+#ifdef ROM_USBDevEndpointConfigGet
+#define MAP_USBDevEndpointConfigGet \
+        ROM_USBDevEndpointConfigGet
+#else
+#define MAP_USBDevEndpointConfigGet \
+        USBDevEndpointConfigGet
+#endif
+#ifdef ROM_USBEndpointDMAEnable
+#define MAP_USBEndpointDMAEnable \
+        ROM_USBEndpointDMAEnable
+#else
+#define MAP_USBEndpointDMAEnable \
+        USBEndpointDMAEnable
+#endif
+#ifdef ROM_USBEndpointDMADisable
+#define MAP_USBEndpointDMADisable \
+        ROM_USBEndpointDMADisable
+#else
+#define MAP_USBEndpointDMADisable \
+        USBEndpointDMADisable
+#endif
+#ifdef ROM_USBEndpointDataAvail
+#define MAP_USBEndpointDataAvail \
+        ROM_USBEndpointDataAvail
+#else
+#define MAP_USBEndpointDataAvail \
+        USBEndpointDataAvail
+#endif
+#ifdef ROM_USBOTGHostRequest
+#define MAP_USBOTGHostRequest \
+        ROM_USBOTGHostRequest
+#else
+#define MAP_USBOTGHostRequest \
+        USBOTGHostRequest
+#endif
+#ifdef ROM_USBModeGet
+#define MAP_USBModeGet \
+        ROM_USBModeGet
+#else
+#define MAP_USBModeGet \
+        USBModeGet
+#endif
+#ifdef ROM_USBEndpointDMAChannel
+#define MAP_USBEndpointDMAChannel \
+        ROM_USBEndpointDMAChannel
+#else
+#define MAP_USBEndpointDMAChannel \
+        USBEndpointDMAChannel
+#endif
+#ifdef ROM_USBIntDisableControl
+#define MAP_USBIntDisableControl \
+        ROM_USBIntDisableControl
+#else
+#define MAP_USBIntDisableControl \
+        USBIntDisableControl
+#endif
+#ifdef ROM_USBIntEnableControl
+#define MAP_USBIntEnableControl \
+        ROM_USBIntEnableControl
+#else
+#define MAP_USBIntEnableControl \
+        USBIntEnableControl
+#endif
+#ifdef ROM_USBIntStatusControl
+#define MAP_USBIntStatusControl \
+        ROM_USBIntStatusControl
+#else
+#define MAP_USBIntStatusControl \
+        USBIntStatusControl
+#endif
+#ifdef ROM_USBIntDisableEndpoint
+#define MAP_USBIntDisableEndpoint \
+        ROM_USBIntDisableEndpoint
+#else
+#define MAP_USBIntDisableEndpoint \
+        USBIntDisableEndpoint
+#endif
+#ifdef ROM_USBIntEnableEndpoint
+#define MAP_USBIntEnableEndpoint \
+        ROM_USBIntEnableEndpoint
+#else
+#define MAP_USBIntEnableEndpoint \
+        USBIntEnableEndpoint
+#endif
+#ifdef ROM_USBIntStatusEndpoint
+#define MAP_USBIntStatusEndpoint \
+        ROM_USBIntStatusEndpoint
+#else
+#define MAP_USBIntStatusEndpoint \
+        USBIntStatusEndpoint
+#endif
+#ifdef ROM_USBHostMode
+#define MAP_USBHostMode \
+        ROM_USBHostMode
+#else
+#define MAP_USBHostMode \
+        USBHostMode
+#endif
+#ifdef ROM_USBDevMode
+#define MAP_USBDevMode \
+        ROM_USBDevMode
+#else
+#define MAP_USBDevMode \
+        USBDevMode
+#endif
+#ifdef ROM_USBPHYPowerOff
+#define MAP_USBPHYPowerOff \
+        ROM_USBPHYPowerOff
+#else
+#define MAP_USBPHYPowerOff \
+        USBPHYPowerOff
+#endif
+#ifdef ROM_USBPHYPowerOn
+#define MAP_USBPHYPowerOn \
+        ROM_USBPHYPowerOn
+#else
+#define MAP_USBPHYPowerOn \
+        USBPHYPowerOn
+#endif
 
 //*****************************************************************************
 //
@@ -2760,4 +3532,18 @@
         WatchdogStallDisable
 #endif
 
+//*****************************************************************************
+//
+// Deprecated ROM functions.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+#define MAP_FlashIntGetStatus \
+        MAP_FlashIntStatus
+#define MAP_USBDevEndpointConfig \
+        MAP_USBDevEndpointConfigSet
+#define MAP_USBHostPwrFaultConfig \
+        MAP_USBHostPwrConfig
+#endif
+
 #endif // __ROM_MAP_H__
diff --git a/src/platform/lm3s/ssi.c b/src/platform/lm3s/driverlib/ssi.c
similarity index 79%
rename from src/platform/lm3s/ssi.c
rename to src/platform/lm3s/driverlib/ssi.c
index e8143b24..6634c482 100755
--- a/src/platform/lm3s/ssi.c
+++ b/src/platform/lm3s/driverlib/ssi.c
@@ -2,26 +2,23 @@
 //
 // ssi.c - Driver for Synchronous Serial Interface.
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2011 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
+// This is part of revision 7611 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -32,13 +29,13 @@
 //
 //*****************************************************************************
 
-#include "hw_ints.h"
-#include "hw_memmap.h"
-#include "hw_ssi.h"
-#include "hw_types.h"
-#include "debug.h"
-#include "interrupt.h"
-#include "ssi.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_ssi.h"
+#include "inc/hw_types.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+#include "driverlib/ssi.h"
 
 //*****************************************************************************
 //
@@ -149,7 +146,7 @@ SSIConfigSetExpClk(unsigned long ulBase, unsigned long ulSSIClk,
     //
     // Set protocol and clock rate.
     //
-    ulSPH_SPO = ulProtocol << 6;
+    ulSPH_SPO = (ulProtocol & 3) << 6;
     ulProtocol &= SSI_CR0_FRF_M;
     ulRegVal = (ulSCR << 8) | ulSPH_SPO | ulProtocol | (ulDataWidth - 1);
     HWREG(ulBase + SSI_O_CR0) = ulRegVal;
@@ -161,8 +158,8 @@ SSIConfigSetExpClk(unsigned long ulBase, unsigned long ulSSIClk,
 //!
 //! \param ulBase specifies the SSI module base address.
 //!
-//! This will enable operation of the synchronous serial interface.  It must be
-//! configured before it is enabled.
+//! This function enables operation of the synchronous serial interface.  The
+//! synchronous serial interface must be configured before it is enabled.
 //!
 //! \return None.
 //
@@ -187,7 +184,7 @@ SSIEnable(unsigned long ulBase)
 //!
 //! \param ulBase specifies the SSI module base address.
 //!
-//! This will disable operation of the synchronous serial interface.
+//! This function disables operation of the synchronous serial interface.
 //!
 //! \return None.
 //
@@ -356,12 +353,12 @@ SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
 //! Gets the current interrupt status.
 //!
 //! \param ulBase specifies the SSI module base address.
-//! \param bMasked is \b false if the raw interrupt status is required and
+//! \param bMasked is \b false if the raw interrupt status is required or
 //! \b true if the masked interrupt status is required.
 //!
-//! This returns the interrupt status for the SSI module.  Either the raw
-//! interrupt status or the status of interrupts that are allowed to reflect to
-//! the processor can be returned.
+//! This function returns the interrupt status for the SSI module.  Either the
+//! raw interrupt status or the status of interrupts that are allowed to
+//! reflect to the processor can be returned.
 //!
 //! \return The current interrupt status, enumerated as a bit field of
 //! \b SSI_TXFF, \b SSI_RXFF, \b SSI_RXTO, and \b SSI_RXOR.
@@ -396,20 +393,20 @@ SSIIntStatus(unsigned long ulBase, tBoolean bMasked)
 //! \param ulBase specifies the SSI module base address.
 //! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
 //!
-//! The specified SSI interrupt sources are cleared, so that
-//! they no longer assert.  This must be done in the interrupt handler to
-//! keep it from being called again immediately upon exit.
-//! The \e ulIntFlags parameter can consist of either or both the \b SSI_RXTO
-//! and \b SSI_RXOR values.
+//! The specified SSI interrupt sources are cleared so that they no longer
+//! assert.  This function must be called in the interrupt handler to keep the
+//! interrupts from being recognized again immediately upon exit.  The
+//! \e ulIntFlags parameter can consist of either or both the \b SSI_RXTO and
+//! \b SSI_RXOR values.
 //!
-//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
-//! several clock cycles before the interrupt source is actually cleared.
+//! \note Because there is a write buffer in the Cortex-M3 processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
 //! Therefore, it is recommended that the interrupt source be cleared early in
 //! the interrupt handler (as opposed to the very last action) to avoid
 //! returning from the interrupt handler before the interrupt source is
 //! actually cleared.  Failure to do so may result in the interrupt handler
-//! being immediately reentered (since NVIC still sees the interrupt source
-//! asserted).
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
 //!
 //! \return None.
 //
@@ -433,15 +430,15 @@ SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags)
 //! Puts a data element into the SSI transmit FIFO.
 //!
 //! \param ulBase specifies the SSI module base address.
-//! \param ulData data to be transmitted over the SSI interface.
+//! \param ulData is the data to be transmitted over the SSI interface.
 //!
-//! This function will place the supplied data into the transmit FIFO of
-//! the specified SSI module.
+//! This function places the supplied data into the transmit FIFO of the
+//! specified SSI module.
 //!
-//! \note The upper 32 - N bits of the \e ulData will be discarded by the
-//! hardware, where N is the data width as configured by SSIConfigSetExpClk().
-//! For example, if the interface is configured for 8-bit data width, the upper
-//! 24 bits of \e ulData will be discarded.
+//! \note The upper 32 - N bits of the \e ulData are discarded by the hardware,
+//! where N is the data width as configured by SSIConfigSetExpClk().  For
+//! example, if the interface is configured for 8-bit data width, the upper 24
+//! bits of \e ulData are discarded.
 //!
 //! \return None.
 //
@@ -474,20 +471,20 @@ SSIDataPut(unsigned long ulBase, unsigned long ulData)
 //! Puts a data element into the SSI transmit FIFO.
 //!
 //! \param ulBase specifies the SSI module base address.
-//! \param ulData data to be transmitted over the SSI interface.
+//! \param ulData is the data to be transmitted over the SSI interface.
 //!
-//! This function will place the supplied data into the transmit FIFO of
-//! the specified SSI module.  If there is no space in the FIFO, then this
-//! function will return a zero.
+//! This function places the supplied data into the transmit FIFO of the
+//! specified SSI module.  If there is no space in the FIFO, then this function
+//! returns a zero.
 //!
 //! This function replaces the original SSIDataNonBlockingPut() API and
 //! performs the same actions.  A macro is provided in ssi.h to map
 //! the original API to this API.
 //!
-//! \note The upper 32 - N bits of the \e ulData will be discarded by the
-//! hardware, where N is the data width as configured by SSIConfigSetExpClk().
-//! For example, if the interface is configured for 8-bit data width, the upper
-//! 24 bits of \e ulData will be discarded.
+//! \note The upper 32 - N bits of the \e ulData are discarded by the hardware,
+//! where N is the data width as configured by SSIConfigSetExpClk().  For
+//! example, if the interface is configured for 8-bit data width, the upper 24
+//! bits of \e ulData are discarded.
 //!
 //! \return Returns the number of elements written to the SSI transmit FIFO.
 //
@@ -521,18 +518,18 @@ SSIDataPutNonBlocking(unsigned long ulBase, unsigned long ulData)
 //! Gets a data element from the SSI receive FIFO.
 //!
 //! \param ulBase specifies the SSI module base address.
-//! \param pulData pointer to a storage location for data that was received
-//! over the SSI interface.
+//! \param pulData is a pointer to a storage location for data that was
+//! received over the SSI interface.
 //!
-//! This function will get received data from the receive FIFO of the specified
-//! SSI module, and place that data into the location specified by the
+//! This function gets received data from the receive FIFO of the specified
+//! SSI module and places that data into the location specified by the
 //! \e pulData parameter.
 //!
-//! \note Only the lower N bits of the value written to \e pulData will contain
+//! \note Only the lower N bits of the value written to \e pulData contain
 //! valid data, where N is the data width as configured by
 //! SSIConfigSetExpClk().  For example, if the interface is configured for
 //! 8-bit data width, only the lower 8 bits of the value written to \e pulData
-//! will contain valid data.
+//! contain valid data.
 //!
 //! \return None.
 //
@@ -563,23 +560,23 @@ SSIDataGet(unsigned long ulBase, unsigned long *pulData)
 //! Gets a data element from the SSI receive FIFO.
 //!
 //! \param ulBase specifies the SSI module base address.
-//! \param pulData pointer to a storage location for data that was received
-//! over the SSI interface.
+//! \param pulData is a pointer to a storage location for data that was
+//! received over the SSI interface.
 //!
-//! This function will get received data from the receive FIFO of
-//! the specified SSI module, and place that data into the location specified
-//! by the \e ulData parameter.  If there is no data in the FIFO, then this
-//! function will return a zero.
+//! This function gets received data from the receive FIFO of the specified SSI
+//! module and places that data into the location specified by the \e ulData
+//! parameter.  If there is no data in the FIFO, then this function returns a
+//! zero.
 //!
 //! This function replaces the original SSIDataNonBlockingGet() API and
 //! performs the same actions.  A macro is provided in ssi.h to map
 //! the original API to this API.
 //!
-//! \note Only the lower N bits of the value written to \e pulData will contain
+//! \note Only the lower N bits of the value written to \e pulData contain
 //! valid data, where N is the data width as configured by
 //! SSIConfigSetExpClk().  For example, if the interface is configured for
 //! 8-bit data width, only the lower 8 bits of the value written to \e pulData
-//! will contain valid data.
+//! contain valid data.
 //!
 //! \return Returns the number of elements read from the SSI receive FIFO.
 //
@@ -636,7 +633,7 @@ SSIDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags)
     ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
 
     //
-    // Set the requested bits in the UART DMA control register.
+    // Set the requested bits in the SSI DMA control register.
     //
     HWREG(ulBase + SSI_O_DMACTL) |= ulDMAFlags;
 }
@@ -667,11 +664,40 @@ SSIDMADisable(unsigned long ulBase, unsigned long ulDMAFlags)
     ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
 
     //
-    // Clear the requested bits in the UART DMA control register.
+    // Clear the requested bits in the SSI DMA control register.
     //
     HWREG(ulBase + SSI_O_DMACTL) &= ~ulDMAFlags;
 }
 
+//*****************************************************************************
+//
+//! Determines whether the SSI transmitter is busy or not.
+//!
+//! \param ulBase is the base address of the SSI port.
+//!
+//! Allows the caller to determine whether all transmitted bytes have cleared
+//! the transmitter hardware.  If \b false is returned, then the transmit FIFO
+//! is empty and all bits of the last transmitted word have left the hardware
+//! shift register.
+//!
+//! \return Returns \b true if the SSI is transmitting or \b false if all
+//! transmissions are complete.
+//
+//*****************************************************************************
+tBoolean
+SSIBusy(unsigned long ulBase)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
+
+    //
+    // Determine if the SSI is busy.
+    //
+    return((HWREG(ulBase + SSI_O_SR) & SSI_SR_BSY) ? true : false);
+}
+
 //*****************************************************************************
 //
 // Close the Doxygen group.
diff --git a/src/platform/lm3s/ssi.h b/src/platform/lm3s/driverlib/ssi.h
similarity index 80%
rename from src/platform/lm3s/ssi.h
rename to src/platform/lm3s/driverlib/ssi.h
index d2b8ee92..c2730471 100755
--- a/src/platform/lm3s/ssi.h
+++ b/src/platform/lm3s/driverlib/ssi.h
@@ -2,26 +2,23 @@
 //
 // ssi.h - Prototypes for the Synchronous Serial Interface Driver.
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2011 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
+// This is part of revision 7611 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -45,8 +42,8 @@ extern "C"
 // as the ulIntFlags parameter, and returned by SSIIntStatus.
 //
 //*****************************************************************************
-#define SSI_TXFF                0x00000008  // TX FIFO half empty or less
-#define SSI_RXFF                0x00000004  // RX FIFO half full or less
+#define SSI_TXFF                0x00000008  // TX FIFO half full or less
+#define SSI_RXFF                0x00000004  // RX FIFO half full or more
 #define SSI_RXTO                0x00000002  // RX timeout
 #define SSI_RXOR                0x00000001  // RX overrun
 
@@ -98,6 +95,7 @@ extern unsigned long SSIIntStatus(unsigned long ulBase, tBoolean bMasked);
 extern void SSIIntUnregister(unsigned long ulBase);
 extern void SSIDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags);
 extern void SSIDMADisable(unsigned long ulBase, unsigned long ulDMAFlags);
+extern tBoolean SSIBusy(unsigned long ulBase);
 
 //*****************************************************************************
 //
@@ -106,7 +104,7 @@ extern void SSIDMADisable(unsigned long ulBase, unsigned long ulDMAFlags);
 //
 //*****************************************************************************
 #ifndef DEPRECATED
-#include "sysctl.h"
+#include "driverlib/sysctl.h"
 #define SSIConfig(a, b, c, d, e)                            \
         SSIConfigSetExpClk(a, SysCtlClockGet(), b, c, d, e)
 #define SSIDataNonBlockingGet(a, b) \
diff --git a/src/platform/lm3s/sysctl.c b/src/platform/lm3s/driverlib/sysctl.c
similarity index 82%
rename from src/platform/lm3s/sysctl.c
rename to src/platform/lm3s/driverlib/sysctl.c
index a66e2abb..8e325835 100755
--- a/src/platform/lm3s/sysctl.c
+++ b/src/platform/lm3s/driverlib/sysctl.c
@@ -2,26 +2,23 @@
 //
 // sysctl.c - Driver for the system controller.
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2011 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
+// This is part of revision 7611 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -32,14 +29,14 @@
 //
 //*****************************************************************************
 
-#include "hw_ints.h"
-#include "hw_nvic.h"
-#include "hw_sysctl.h"
-#include "hw_types.h"
-#include "cpu.h"
-#include "debug.h"
-#include "interrupt.h"
-#include "sysctl.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_nvic.h"
+#include "inc/hw_sysctl.h"
+#include "inc/hw_types.h"
+#include "driverlib/cpu.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+#include "driverlib/sysctl.h"
 
 //*****************************************************************************
 //
@@ -347,19 +344,22 @@ SysCtlPinPresent(unsigned long ulPin)
 //! determine which are present on this device.
 //!
 //! The \e ulPeripheral parameter must be only one of the following values:
-//! \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_CAN0, \b SYSCTL_PERIPH_CAN1,
-//! \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, \b SYSCTL_PERIPH_COMP1,
-//! \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA,
-//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD,
-//! \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG,
-//! \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0,
-//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_IEEE1588, \b SYSCTL_PERIPH_MPU,
-//! \b SYSCTL_PERIPH_PLL, \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_QEI0,
-//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1,
-//! \b SYSCTL_PERIPH_TEMP, \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1,
-//! \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_UART0,
-//! \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UDMA,
-//! \b SYSCTL_PERIPH_USB0, or \b SYSCTL_PERIPH_WDOG.
+//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0,
+//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0,
+//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_EPI0,
+//! \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB,
+//! \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE,
+//! \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH,
+//! \b SYSCTL_PERIPH_GPIOJ, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0,
+//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2S0, \b SYSCTL_PERIPH_IEEE1588,
+//! \b SYSCTL_PERIPH_MPU, \b SYSCTL_PERIPH_PLL, \b SYSCTL_PERIPH_PWM,
+//! \b SYSCTL_PERIPH_QEI0, \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0,
+//! \b SYSCTL_PERIPH_SSI1, \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1,
+//! \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3,
+//! \b SYSCTL_PERIPH_TEMP,
+//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_UART2,
+//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, or
+//! \b SYSCTL_PERIPH_WDOG1.
 //!
 //! \return Returns \b true if the specified peripheral is present and \b false
 //! if it is not.
@@ -381,7 +381,7 @@ SysCtlPeripheralPresent(unsigned long ulPeripheral)
         //
         // USB is a special case since the DC bit is missing for USB0.
         //
-        if(HWREG(SYSCTL_DC6) && SYSCTL_DC6_USB0_M)
+        if(HWREG(SYSCTL_DC6) & SYSCTL_DC6_USB0_M)
         {
             return(true);
         }
@@ -409,22 +409,25 @@ SysCtlPeripheralPresent(unsigned long ulPeripheral)
 //!
 //! This function performs a software reset of the specified peripheral.  An
 //! individual peripheral reset signal is asserted for a brief period and then
-//! deasserted, leaving the peripheral in a operating state but in its reset
+//! deasserted, returning the internal state of the peripheral to its reset
 //! condition.
 //!
 //! The \e ulPeripheral parameter must be only one of the following values:
-//! \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_CAN0, \b SYSCTL_PERIPH_CAN1,
-//! \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, \b SYSCTL_PERIPH_COMP1,
-//! \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA,
-//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD,
-//! \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG,
-//! \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0,
-//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_QEI0,
-//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1,
-//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2,
-//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1,
-//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, or
-//! \b SYSCTL_PERIPH_WDOG.
+//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0,
+//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0,
+//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_EPI0,
+//! \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB,
+//! \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE,
+//! \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH,
+//! \b SYSCTL_PERIPH_GPIOJ, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0,
+//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2S0, \b SYSCTL_PERIPH_PWM,
+//! \b SYSCTL_PERIPH_QEI0, \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0,
+//! \b SYSCTL_PERIPH_SSI1, \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1,
+//! \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3,
+//! \b SYSCTL_PERIPH_TEMP,
+//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_UART2,
+//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, or
+//! \b SYSCTL_PERIPH_WDOG1.
 //!
 //! \return None.
 //
@@ -470,18 +473,21 @@ SysCtlPeripheralReset(unsigned long ulPeripheral)
 //! register reads/writes.
 //!
 //! The \e ulPeripheral parameter must be only one of the following values:
-//! \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_CAN0, \b SYSCTL_PERIPH_CAN1,
-//! \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, \b SYSCTL_PERIPH_COMP1,
-//! \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA,
-//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD,
-//! \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG,
-//! \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0,
-//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_QEI0,
-//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1,
-//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2,
-//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1,
-//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, or
-//! \b SYSCTL_PERIPH_WDOG.
+//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0,
+//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0,
+//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_EPI0,
+//! \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB,
+//! \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE,
+//! \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH,
+//! \b SYSCTL_PERIPH_GPIOJ, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0,
+//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2S0, \b SYSCTL_PERIPH_PWM,
+//! \b SYSCTL_PERIPH_QEI0, \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0,
+//! \b SYSCTL_PERIPH_SSI1, \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1,
+//! \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3,
+//!\b SYSCTL_PERIPH_TEMP,
+//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_UART2,
+//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, or
+//! \b SYSCTL_PERIPH_WDOG1.
 //!
 //! \note It takes five clock cycles after the write to enable a peripheral
 //! before the the peripheral is actually enabled.  During this time, attempts
@@ -517,18 +523,21 @@ SysCtlPeripheralEnable(unsigned long ulPeripheral)
 //! operate or respond to register reads/writes.
 //!
 //! The \e ulPeripheral parameter must be only one of the following values:
-//! \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_CAN0, \b SYSCTL_PERIPH_CAN1,
-//! \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, \b SYSCTL_PERIPH_COMP1,
-//! \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA,
-//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD,
-//! \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG,
-//! \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0,
-//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_QEI0,
-//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1,
-//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2,
-//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1,
-//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, or
-//! \b SYSCTL_PERIPH_WDOG.
+//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0,
+//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0,
+//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_EPI0,
+//! \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB,
+//! \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE,
+//! \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH,
+//! \b SYSCTL_PERIPH_GPIOJ, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0,
+//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2S0, \b SYSCTL_PERIPH_PWM,
+//! \b SYSCTL_PERIPH_QEI0, \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0,
+//! \b SYSCTL_PERIPH_SSI1, \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1,
+//! \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3,
+//! \b SYSCTL_PERIPH_TEMP,
+//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_UART2,
+//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, or
+//! \b SYSCTL_PERIPH_WDOG1.
 //!
 //! \return None.
 //
@@ -565,18 +574,21 @@ SysCtlPeripheralDisable(unsigned long ulPeripheral)
 //! configuration is maintained but has no effect when sleep mode is entered.
 //!
 //! The \e ulPeripheral parameter must be only one of the following values:
-//! \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_CAN0, \b SYSCTL_PERIPH_CAN1,
-//! \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, \b SYSCTL_PERIPH_COMP1,
-//! \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA,
-//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD,
-//! \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG,
-//! \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0,
-//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_QEI0,
-//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1,
-//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2,
-//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1,
-//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, or
-//! \b SYSCTL_PERIPH_WDOG.
+//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0,
+//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0,
+//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_EPI0,
+//! \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB,
+//! \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE,
+//! \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH,
+//! \b SYSCTL_PERIPH_GPIOJ, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0,
+//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2S0, \b SYSCTL_PERIPH_PWM,
+//! \b SYSCTL_PERIPH_QEI0, \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0,
+//! \b SYSCTL_PERIPH_SSI1, \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1,
+//! \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3,
+//! \b SYSCTL_PERIPH_TEMP,
+//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_UART2,
+//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, or
+//! \b SYSCTL_PERIPH_WDOG1.
 //!
 //! \return None.
 //
@@ -614,18 +626,21 @@ SysCtlPeripheralSleepEnable(unsigned long ulPeripheral)
 //! configuration is maintained but has no effect when sleep mode is entered.
 //!
 //! The \e ulPeripheral parameter must be only one of the following values:
-//! \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_CAN0, \b SYSCTL_PERIPH_CAN1,
-//! \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, \b SYSCTL_PERIPH_COMP1,
-//! \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA,
-//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD,
-//! \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG,
-//! \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0,
-//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_QEI0,
-//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1,
-//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2,
-//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1,
-//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, or
-//! \b SYSCTL_PERIPH_WDOG.
+//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0,
+//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0,
+//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_EPI0,
+//! \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB,
+//! \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE,
+//! \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH,
+//! \b SYSCTL_PERIPH_GPIOJ, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0,
+//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2S0, \b SYSCTL_PERIPH_PWM,
+//! \b SYSCTL_PERIPH_QEI0, \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0,
+//! \b SYSCTL_PERIPH_SSI1, \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1,
+//! \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3,
+//! \b SYSCTL_PERIPH_TEMP,
+//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_UART2,
+//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, or
+//! \b SYSCTL_PERIPH_WDOG1.
 //!
 //! \return None.
 //
@@ -663,19 +678,22 @@ SysCtlPeripheralSleepDisable(unsigned long ulPeripheral)
 //! configuration is maintained but has no effect when deep-sleep mode is
 //! entered.
 //!
-//! The \e ulPeripheral parameter must be one of the following values:
-//! \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_CAN0, \b SYSCTL_PERIPH_CAN1,
-//! \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, \b SYSCTL_PERIPH_COMP1,
-//! \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA,
-//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD,
-//! \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG,
-//! \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0,
-//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_QEI0,
-//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1,
-//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2,
-//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1,
-//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, or
-//! \b SYSCTL_PERIPH_WDOG.
+//! The \e ulPeripheral parameter must be only one of the following values:
+//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0,
+//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0,
+//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_EPI0,
+//! \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB,
+//! \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE,
+//! \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH,
+//! \b SYSCTL_PERIPH_GPIOJ, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0,
+//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2S0, \b SYSCTL_PERIPH_PWM,
+//! \b SYSCTL_PERIPH_QEI0, \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0,
+//! \b SYSCTL_PERIPH_SSI1, \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1,
+//! \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3,
+//! \b SYSCTL_PERIPH_TEMP,
+//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_UART2,
+//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, or
+//! \b SYSCTL_PERIPH_WDOG1.
 //!
 //! \return None.
 //
@@ -715,19 +733,22 @@ SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral)
 //! configuration is maintained but has no effect when deep-sleep mode is
 //! entered.
 //!
-//! The \e ulPeripheral parameter must be one of the following values:
-//! \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_CAN0, \b SYSCTL_PERIPH_CAN1,
-//! \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, \b SYSCTL_PERIPH_COMP1,
-//! \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA,
-//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD,
-//! \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG,
-//! \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0,
-//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_QEI0,
-//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1,
-//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2,
-//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1,
-//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, or
-//! \b SYSCTL_PERIPH_WDOG.
+//! The \e ulPeripheral parameter must be only one of the following values:
+//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0,
+//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0,
+//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_EPI0,
+//! \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB,
+//! \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE,
+//! \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH,
+//! \b SYSCTL_PERIPH_GPIOJ, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0,
+//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2S0, \b SYSCTL_PERIPH_PWM,
+//! \b SYSCTL_PERIPH_QEI0, \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0,
+//! \b SYSCTL_PERIPH_SSI1, \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1,
+//! \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3,
+//! \b SYSCTL_PERIPH_TEMP,
+//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_UART2,
+//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, or
+//! \b SYSCTL_PERIPH_WDOG1.
 //!
 //! \return None.
 //
@@ -909,14 +930,14 @@ SysCtlIntDisable(unsigned long ulInts)
 //! longer assert.  This must be done in the interrupt handler to keep it from
 //! being called again immediately upon exit.
 //!
-//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
-//! several clock cycles before the interrupt source is actually cleared.
+//! \note Because there is a write buffer in the Cortex-M3 processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
 //! Therefore, it is recommended that the interrupt source be cleared early in
 //! the interrupt handler (as opposed to the very last action) to avoid
 //! returning from the interrupt handler before the interrupt source is
 //! actually cleared.  Failure to do so may result in the interrupt handler
-//! being immediately reentered (since NVIC still sees the interrupt source
-//! asserted).
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
 //!
 //! \return None.
 //
@@ -1270,6 +1291,121 @@ SysCtlDelay(unsigned long ulCount)
     bx      lr;
 }
 #endif
+//
+// For CCS implement this function in pure assembly.  This prevents the TI
+// compiler from doing funny things with the optimizer.
+//
+#if defined(ccs)
+    __asm("    .sect \".text:SysCtlDelay\"\n"
+          "    .clink\n"
+          "    .thumbfunc SysCtlDelay\n"
+          "    .thumb\n"
+          "    .global SysCtlDelay\n"
+          "SysCtlDelay:\n"
+          "    subs r0, #1\n"
+          "    bne.n SysCtlDelay\n"
+          "    bx lr\n");
+#endif
+
+//*****************************************************************************
+//
+//! Sets the configuration of the main oscillator (MOSC) control.
+//!
+//! \param ulConfig is the required configuration of the MOSC control.
+//!
+//! This function configures the control of the main oscillator.  The
+//! \e ulConfig is specified as follows:
+//!
+//! - \b SYSCTL_MOSC_VALIDATE enables the MOSC verification circuit that
+//!   detects a failure of the main oscillator (such as a loss of the clock).
+//!
+//! \note The availability of MOSC control varies based on the Stellaris part
+//! in use.  Please consult the datasheet for the part you are using to
+//! determine whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlMOSCConfigSet(unsigned long ulConfig)
+{
+    //
+    // Configure the MOSC control.
+    //
+    HWREG(SYSCTL_MOSCCTL) = ulConfig;
+}
+
+//*****************************************************************************
+//
+//! Calibrates the precision internal oscillator.
+//!
+//! \param ulType is the type of calibration to perform.
+//!
+//! This function performs a calibration of the PIOSC.  There are three types
+//! of calibration available; the desired calibration type as specified in
+//! \e ulType is one of:
+//!
+//! - \b SYSCTL_PIOSC_CAL_AUTO to perform automatic calibration using the
+//!   32 kHz clock from the hibernate module as a reference.  This is only
+//!   possible on parts that have a hibernate module and then only if it is
+//!   enabled and the hibernate module's RTC is also enabled.
+//!
+//! - \b SYSCTL_PIOSC_CAL_FACT to reset the PIOSC calibration to the factory
+//!   provided calibration.
+//!
+//! - \b SYSCTL_PIOSC_CAL_USER to set the PIOSC calibration to a user-supplied
+//!   value.  The value to be used is ORed into the lower 7-bits of this value,
+//!   with 0x40 being the ``nominal'' value (in other words, if everything were
+//!   perfect, this would provide exactly 16 MHz).  Values larger than 0x40
+//!   will slow down PIOSC, and values smaller than 0x40 will speed up PIOSC.
+//!
+//! \return None.
+//
+//*****************************************************************************
+unsigned long
+SysCtlPIOSCCalibrate(unsigned long ulType)
+{
+    //
+    // Perform the requested calibration.  If performing user calibration, the
+    // UTEN bit must be set with one write, then the UT field in a second
+    // write, and the UPDATE bit in a final write.  For other calibration
+    // types, a single write to set UPDATE or CAL is all that is required.
+    //
+    if(ulType & (SYSCTL_PIOSCCAL_UTEN | SYSCTL_PIOSCCAL_UPDATE))
+    {
+        HWREG(SYSCTL_PIOSCCAL) = ulType & SYSCTL_PIOSCCAL_UTEN;
+        HWREG(SYSCTL_PIOSCCAL) =
+            ulType & (SYSCTL_PIOSCCAL_UTEN | SYSCTL_PIOSCCAL_UT_M);
+    }
+    HWREG(SYSCTL_PIOSCCAL) = ulType;
+
+    //
+    // See if an automatic calibration was requested.
+    //
+    if(ulType & SYSCTL_PIOSCCAL_CAL)
+    {
+        //
+        // Wait for the automatic calibration to complete.
+        //
+        while((HWREG(SYSCTL_PIOSCSTAT) & SYSCTL_PIOSCSTAT_CR_M) == 0)
+        {
+        }
+
+        //
+        // If the automatic calibration failed, return an error.
+        //
+        if((HWREG(SYSCTL_PIOSCSTAT) & SYSCTL_PIOSCSTAT_CR_M) !=
+           SYSCTL_PIOSCSTAT_CRPASS)
+        {
+            return(0);
+        }
+    }
+
+    //
+    // The calibration was successful.
+    //
+    return(1);
+}
 
 //*****************************************************************************
 //
@@ -1469,15 +1605,15 @@ SysCtlClockSet(unsigned long ulConfig)
                          SYSCTL_RCC_IOSCDIS | SYSCTL_RCC_MOSCDIS);
     ulRCC2 &= ~(SYSCTL_RCC2_SYSDIV2_M);
     ulRCC2 |= ulConfig & SYSCTL_RCC2_SYSDIV2_M;
-    if(ulConfig & SYSCTL_RCC2_USEFRACT)
+    if(ulConfig & SYSCTL_RCC2_DIV400)
     {
         ulRCC |= SYSCTL_RCC_USESYSDIV;
         ulRCC2 &= ~(SYSCTL_RCC_USESYSDIV);
-        ulRCC2 |= ulConfig & (SYSCTL_RCC2_USEFRACT | SYSCTL_RCC2_FRACT);
+        ulRCC2 |= ulConfig & (SYSCTL_RCC2_DIV400 | SYSCTL_RCC2_SYSDIV2LSB);
     }
     else
     {
-        ulRCC2 &= ~(SYSCTL_RCC2_USEFRACT);
+        ulRCC2 &= ~(SYSCTL_RCC2_DIV400);
     }
 
     //
@@ -1745,7 +1881,7 @@ SysCtlClockGet(void)
         //
         if(ulRCC2 & SYSCTL_RCC2_USERCC2)
         {
-            if((ulRCC2 & SYSCTL_RCC2_USEFRACT) &&
+            if((ulRCC2 & SYSCTL_RCC2_DIV400) &&
                (((ulRCC2 & SYSCTL_RCC2_USERCC2) &&
                  !(ulRCC2 & SYSCTL_RCC2_BYPASS2)) ||
                 (!(ulRCC2 & SYSCTL_RCC2_USERCC2) &&
@@ -1753,7 +1889,7 @@ SysCtlClockGet(void)
 
             {
                 ulClk = ((ulClk * 2) / (((ulRCC2 & (SYSCTL_RCC2_SYSDIV2_M |
-                                                    SYSCTL_RCC2_FRACT)) >>
+                                                    SYSCTL_RCC2_SYSDIV2LSB)) >>
                                          (SYSCTL_RCC2_SYSDIV2_S - 1)) + 1));
             }
             else
@@ -1775,6 +1911,45 @@ SysCtlClockGet(void)
     return(ulClk);
 }
 
+//*****************************************************************************
+//
+//! Sets the clocking of the device while in deep-sleep mode.
+//!
+//! \param ulConfig is the required configuration of the device clocking while
+//! in deep-sleep mode.
+//!
+//! This function configures the clocking of the device while in deep-sleep
+//! mode.  The oscillator to be used and the system clock divider are
+//! configured with this function.
+//!
+//! The \e ulConfig parameter is the logical OR of the following values:
+//!
+//! The system clock divider is chosen with one of the following values:
+//! \b SYSCTL_DSLP_DIV_1, \b SYSCTL_DSLP_DIV_2, \b SYSCTL_DSLP_DIV_3, ...
+//! \b SYSCTL_DSLP_DIV_64.
+//!
+//! The oscillator source is chosen with one of the following values:
+//! \b SYSCTL_DSLP_OSC_MAIN, \b SYSCTL_DSLP_OSC_INT, \b SYSCTL_DSLP_OSC_INT30,
+//! or \b SYSCTL_DSLP_OSC_EXT32.  \b SYSCTL_OSC_EXT32 is only available on
+//! devices with the hibernate module, and then only when the hibernate module
+//! has been enabled.
+//!
+//! \note The availability of deep-sleep clocking configuration varies with the
+//! Stellaris part in use.  Please consult the datasheet for the part you are
+//! using to determine whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlDeepSleepClockSet(unsigned long ulConfig)
+{
+    //
+    // Set the deep-sleep clock configuration.
+    //
+    HWREG(SYSCTL_DSLPCLKCFG) = ulConfig;
+}
+
 //*****************************************************************************
 //
 //! Sets the PWM clock configuration.
@@ -1902,8 +2077,6 @@ SysCtlADCSpeedSet(unsigned long ulSpeed)
                            ulSpeed);
     HWREG(SYSCTL_SCGC0) = ((HWREG(SYSCTL_SCGC0) & ~(SYSCTL_SCGC0_ADCSPD_M)) |
                            ulSpeed);
-    HWREG(SYSCTL_DCGC0) = ((HWREG(SYSCTL_DCGC0) & ~(SYSCTL_DCGC0_ADCSPD_M)) |
-                           ulSpeed);
 }
 
 //*****************************************************************************
@@ -2109,7 +2282,7 @@ SysCtlGPIOAHBEnable(unsigned long ulGPIOPeripheral)
     //
     // Enable this GPIO for AHB access.
     //
-    HWREG(SYSCTL_GPIOHSCTL) |= ulGPIOPeripheral & 0xFFFF;
+    HWREG(SYSCTL_GPIOHBCTL) |= ulGPIOPeripheral & 0xFFFF;
 }
 
 //*****************************************************************************
@@ -2149,7 +2322,7 @@ SysCtlGPIOAHBDisable(unsigned long ulGPIOPeripheral)
     //
     // Disable this GPIO for AHB access.
     //
-    HWREG(SYSCTL_GPIOHSCTL) &= ~(ulGPIOPeripheral & 0xFFFF);
+    HWREG(SYSCTL_GPIOHBCTL) &= ~(ulGPIOPeripheral & 0xFFFF);
 }
 
 //*****************************************************************************
diff --git a/src/platform/lm3s/sysctl.h b/src/platform/lm3s/driverlib/sysctl.h
similarity index 77%
rename from src/platform/lm3s/sysctl.h
rename to src/platform/lm3s/driverlib/sysctl.h
index 3ec2efd3..d1d531a4 100755
--- a/src/platform/lm3s/sysctl.h
+++ b/src/platform/lm3s/driverlib/sysctl.h
@@ -2,26 +2,23 @@
 //
 // sysctl.h - Prototypes for the system control driver.
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2011 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
+// This is part of revision 7611 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -197,6 +194,7 @@ extern "C"
 //
 //*****************************************************************************
 #define SYSCTL_CAUSE_LDO        0x00000020  // LDO power not OK reset
+#define SYSCTL_CAUSE_WDOG1      0x00000020  // Watchdog1 reset
 #define SYSCTL_CAUSE_SW         0x00000010  // Software reset
 #define SYSCTL_CAUSE_WDOG       0x00000008  // Watchdog reset
 #define SYSCTL_CAUSE_BOR        0x00000004  // Brown-out reset
@@ -234,9 +232,9 @@ extern "C"
 // API.
 //
 //*****************************************************************************
-#define SYSCTL_ADCSPEED_1MSPS   0x00000300  // 1,000,000 samples per second
-#define SYSCTL_ADCSPEED_500KSPS 0x00000200  // 500,000 samples per second
-#define SYSCTL_ADCSPEED_250KSPS 0x00000100  // 250,000 samples per second
+#define SYSCTL_ADCSPEED_1MSPS   0x00000F00  // 1,000,000 samples per second
+#define SYSCTL_ADCSPEED_500KSPS 0x00000A00  // 500,000 samples per second
+#define SYSCTL_ADCSPEED_250KSPS 0x00000500  // 250,000 samples per second
 #define SYSCTL_ADCSPEED_125KSPS 0x00000000  // 125,000 samples per second
 
 //*****************************************************************************
@@ -402,10 +400,102 @@ extern "C"
 #define SYSCTL_OSC_INT30        0x00000030  // Osc source is int. 30 KHz
 #define SYSCTL_OSC_EXT4_19      0x80000028  // Osc source is ext. 4.19 MHz
 #define SYSCTL_OSC_EXT32        0x80000038  // Osc source is ext. 32 KHz
-#define SYSCTL_INT_PIOSC_DIS    0x00000004  // Disable interal precision osc.
 #define SYSCTL_INT_OSC_DIS      0x00000002  // Disable internal oscillator
 #define SYSCTL_MAIN_OSC_DIS     0x00000001  // Disable main oscillator
 
+//*****************************************************************************
+//
+// The following are values that can be passed to the SysCtlDeepSleepClockSet()
+// API as the ulConfig parameter.
+//
+//*****************************************************************************
+#define SYSCTL_DSLP_DIV_1       0x00000000  // Deep-sleep clock is osc /1
+#define SYSCTL_DSLP_DIV_2       0x00800000  // Deep-sleep clock is osc /2
+#define SYSCTL_DSLP_DIV_3       0x01000000  // Deep-sleep clock is osc /3
+#define SYSCTL_DSLP_DIV_4       0x01800000  // Deep-sleep clock is osc /4
+#define SYSCTL_DSLP_DIV_5       0x02000000  // Deep-sleep clock is osc /5
+#define SYSCTL_DSLP_DIV_6       0x02800000  // Deep-sleep clock is osc /6
+#define SYSCTL_DSLP_DIV_7       0x03000000  // Deep-sleep clock is osc /7
+#define SYSCTL_DSLP_DIV_8       0x03800000  // Deep-sleep clock is osc /8
+#define SYSCTL_DSLP_DIV_9       0x04000000  // Deep-sleep clock is osc /9
+#define SYSCTL_DSLP_DIV_10      0x04800000  // Deep-sleep clock is osc /10
+#define SYSCTL_DSLP_DIV_11      0x05000000  // Deep-sleep clock is osc /11
+#define SYSCTL_DSLP_DIV_12      0x05800000  // Deep-sleep clock is osc /12
+#define SYSCTL_DSLP_DIV_13      0x06000000  // Deep-sleep clock is osc /13
+#define SYSCTL_DSLP_DIV_14      0x06800000  // Deep-sleep clock is osc /14
+#define SYSCTL_DSLP_DIV_15      0x07000000  // Deep-sleep clock is osc /15
+#define SYSCTL_DSLP_DIV_16      0x07800000  // Deep-sleep clock is osc /16
+#define SYSCTL_DSLP_DIV_17      0x08000000  // Deep-sleep clock is osc /17
+#define SYSCTL_DSLP_DIV_18      0x08800000  // Deep-sleep clock is osc /18
+#define SYSCTL_DSLP_DIV_19      0x09000000  // Deep-sleep clock is osc /19
+#define SYSCTL_DSLP_DIV_20      0x09800000  // Deep-sleep clock is osc /20
+#define SYSCTL_DSLP_DIV_21      0x0A000000  // Deep-sleep clock is osc /21
+#define SYSCTL_DSLP_DIV_22      0x0A800000  // Deep-sleep clock is osc /22
+#define SYSCTL_DSLP_DIV_23      0x0B000000  // Deep-sleep clock is osc /23
+#define SYSCTL_DSLP_DIV_24      0x0B800000  // Deep-sleep clock is osc /24
+#define SYSCTL_DSLP_DIV_25      0x0C000000  // Deep-sleep clock is osc /25
+#define SYSCTL_DSLP_DIV_26      0x0C800000  // Deep-sleep clock is osc /26
+#define SYSCTL_DSLP_DIV_27      0x0D000000  // Deep-sleep clock is osc /27
+#define SYSCTL_DSLP_DIV_28      0x0D800000  // Deep-sleep clock is osc /28
+#define SYSCTL_DSLP_DIV_29      0x0E000000  // Deep-sleep clock is osc /29
+#define SYSCTL_DSLP_DIV_30      0x0E800000  // Deep-sleep clock is osc /30
+#define SYSCTL_DSLP_DIV_31      0x0F000000  // Deep-sleep clock is osc /31
+#define SYSCTL_DSLP_DIV_32      0x0F800000  // Deep-sleep clock is osc /32
+#define SYSCTL_DSLP_DIV_33      0x10000000  // Deep-sleep clock is osc /33
+#define SYSCTL_DSLP_DIV_34      0x10800000  // Deep-sleep clock is osc /34
+#define SYSCTL_DSLP_DIV_35      0x11000000  // Deep-sleep clock is osc /35
+#define SYSCTL_DSLP_DIV_36      0x11800000  // Deep-sleep clock is osc /36
+#define SYSCTL_DSLP_DIV_37      0x12000000  // Deep-sleep clock is osc /37
+#define SYSCTL_DSLP_DIV_38      0x12800000  // Deep-sleep clock is osc /38
+#define SYSCTL_DSLP_DIV_39      0x13000000  // Deep-sleep clock is osc /39
+#define SYSCTL_DSLP_DIV_40      0x13800000  // Deep-sleep clock is osc /40
+#define SYSCTL_DSLP_DIV_41      0x14000000  // Deep-sleep clock is osc /41
+#define SYSCTL_DSLP_DIV_42      0x14800000  // Deep-sleep clock is osc /42
+#define SYSCTL_DSLP_DIV_43      0x15000000  // Deep-sleep clock is osc /43
+#define SYSCTL_DSLP_DIV_44      0x15800000  // Deep-sleep clock is osc /44
+#define SYSCTL_DSLP_DIV_45      0x16000000  // Deep-sleep clock is osc /45
+#define SYSCTL_DSLP_DIV_46      0x16800000  // Deep-sleep clock is osc /46
+#define SYSCTL_DSLP_DIV_47      0x17000000  // Deep-sleep clock is osc /47
+#define SYSCTL_DSLP_DIV_48      0x17800000  // Deep-sleep clock is osc /48
+#define SYSCTL_DSLP_DIV_49      0x18000000  // Deep-sleep clock is osc /49
+#define SYSCTL_DSLP_DIV_50      0x18800000  // Deep-sleep clock is osc /50
+#define SYSCTL_DSLP_DIV_51      0x19000000  // Deep-sleep clock is osc /51
+#define SYSCTL_DSLP_DIV_52      0x19800000  // Deep-sleep clock is osc /52
+#define SYSCTL_DSLP_DIV_53      0x1A000000  // Deep-sleep clock is osc /53
+#define SYSCTL_DSLP_DIV_54      0x1A800000  // Deep-sleep clock is osc /54
+#define SYSCTL_DSLP_DIV_55      0x1B000000  // Deep-sleep clock is osc /55
+#define SYSCTL_DSLP_DIV_56      0x1B800000  // Deep-sleep clock is osc /56
+#define SYSCTL_DSLP_DIV_57      0x1C000000  // Deep-sleep clock is osc /57
+#define SYSCTL_DSLP_DIV_58      0x1C800000  // Deep-sleep clock is osc /58
+#define SYSCTL_DSLP_DIV_59      0x1D000000  // Deep-sleep clock is osc /59
+#define SYSCTL_DSLP_DIV_60      0x1D800000  // Deep-sleep clock is osc /60
+#define SYSCTL_DSLP_DIV_61      0x1E000000  // Deep-sleep clock is osc /61
+#define SYSCTL_DSLP_DIV_62      0x1E800000  // Deep-sleep clock is osc /62
+#define SYSCTL_DSLP_DIV_63      0x1F000000  // Deep-sleep clock is osc /63
+#define SYSCTL_DSLP_DIV_64      0x1F800000  // Deep-sleep clock is osc /64
+#define SYSCTL_DSLP_OSC_MAIN    0x00000000  // Osc source is main osc
+#define SYSCTL_DSLP_OSC_INT     0x00000010  // Osc source is int. osc
+#define SYSCTL_DSLP_OSC_INT30   0x00000030  // Osc source is int. 30 KHz
+#define SYSCTL_DSLP_OSC_EXT32   0x00000070  // Osc source is ext. 32 KHz
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the SysCtlPIOSCCalibrate()
+// API as the ulType parameter.
+//
+//*****************************************************************************
+#define SYSCTL_PIOSC_CAL_AUTO   0x00000200  // Automatic calibration
+#define SYSCTL_PIOSC_CAL_FACT   0x00000100  // Factory calibration
+#define SYSCTL_PIOSC_CAL_USER   0x80000100  // User-supplied calibration
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the SysCtlMOSCConfigSet() API
+// as the ulConfig parameter.
+//
+//*****************************************************************************
+#define SYSCTL_MOSC_VALIDATE    0x00000001  // Enable MOSC validation
+
 //*****************************************************************************
 //
 // Prototypes for the APIs.
@@ -440,8 +530,11 @@ extern void SysCtlResetCauseClear(unsigned long ulCauses);
 extern void SysCtlBrownOutConfigSet(unsigned long ulConfig,
                                     unsigned long ulDelay);
 extern void SysCtlDelay(unsigned long ulCount);
+extern void SysCtlMOSCConfigSet(unsigned long ulConfig);
+extern unsigned long SysCtlPIOSCCalibrate(unsigned long ulType);
 extern void SysCtlClockSet(unsigned long ulConfig);
 extern unsigned long SysCtlClockGet(void);
+extern void SysCtlDeepSleepClockSet(unsigned long ulConfig);
 extern void SysCtlPWMClockSet(unsigned long ulConfig);
 extern unsigned long SysCtlPWMClockGet(void);
 extern void SysCtlADCSpeedSet(unsigned long ulSpeed);
diff --git a/src/platform/lm3s/systick.c b/src/platform/lm3s/driverlib/systick.c
similarity index 85%
rename from src/platform/lm3s/systick.c
rename to src/platform/lm3s/driverlib/systick.c
index 09019363..86e53730 100755
--- a/src/platform/lm3s/systick.c
+++ b/src/platform/lm3s/driverlib/systick.c
@@ -2,26 +2,23 @@
 //
 // systick.c - Driver for the SysTick timer in NVIC.
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2011 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
+// This is part of revision 7611 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -32,12 +29,12 @@
 //
 //*****************************************************************************
 
-#include "hw_ints.h"
-#include "hw_nvic.h"
-#include "hw_types.h"
-#include "debug.h"
-#include "interrupt.h"
-#include "systick.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_nvic.h"
+#include "inc/hw_types.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+#include "driverlib/systick.h"
 
 //*****************************************************************************
 //
diff --git a/src/platform/lm3s/systick.h b/src/platform/lm3s/driverlib/systick.h
similarity index 57%
rename from src/platform/lm3s/systick.h
rename to src/platform/lm3s/driverlib/systick.h
index 423275f8..4b144467 100755
--- a/src/platform/lm3s/systick.h
+++ b/src/platform/lm3s/driverlib/systick.h
@@ -2,26 +2,23 @@
 //
 // systick.h - Prototypes for the SysTick driver.
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2011 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
+// This is part of revision 7611 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 
diff --git a/src/platform/lm3s/timer.c b/src/platform/lm3s/driverlib/timer.c
similarity index 75%
rename from src/platform/lm3s/timer.c
rename to src/platform/lm3s/driverlib/timer.c
index 8d05a87c..8fd219a5 100755
--- a/src/platform/lm3s/timer.c
+++ b/src/platform/lm3s/driverlib/timer.c
@@ -2,26 +2,23 @@
 //
 // timer.c - Driver for the timer module.
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2011 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
+// This is part of revision 7611 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -32,13 +29,13 @@
 //
 //*****************************************************************************
 
-#include "hw_ints.h"
-#include "hw_memmap.h"
-#include "hw_timer.h"
-#include "hw_types.h"
-#include "debug.h"
-#include "interrupt.h"
-#include "timer.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_timer.h"
+#include "inc/hw_types.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+#include "driverlib/timer.h"
 
 //*****************************************************************************
 //
@@ -70,7 +67,7 @@ TimerBaseValid(unsigned long ulBase)
 //! \param ulTimer specifies the timer(s) to enable; must be one of \b TIMER_A,
 //! \b TIMER_B, or \b TIMER_BOTH.
 //!
-//! This will enable operation of the timer module.  The timer must be
+//! This function enables operation of the timer module.  The timer must be
 //! configured before it is enabled.
 //!
 //! \return None.
@@ -100,7 +97,7 @@ TimerEnable(unsigned long ulBase, unsigned long ulTimer)
 //! \param ulTimer specifies the timer(s) to disable; must be one of
 //! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH.
 //!
-//! This will disable operation of the timer module.
+//! This function disables operation of the timer module.
 //!
 //! \return None.
 //
@@ -134,8 +131,12 @@ TimerDisable(unsigned long ulBase, unsigned long ulTimer)
 //! state.  The configuration is specified in \e ulConfig as one of the
 //! following values:
 //!
-//! - \b TIMER_CFG_32_BIT_OS - 32-bit one shot timer
+//! - \b TIMER_CFG_32_BIT_OS - 32-bit one-shot timer
+//! - \b TIMER_CFG_32_BIT_OS_UP - 32-bit one-shot timer that counts up instead
+//!   of down (not available on all parts)
 //! - \b TIMER_CFG_32_BIT_PER - 32-bit periodic timer
+//! - \b TIMER_CFG_32_BIT_PER_UP - 32-bit periodic timer that counts up instead
+//!   of down (not available on all parts)
 //! - \b TIMER_CFG_32_RTC - 32-bit real time clock timer
 //! - \b TIMER_CFG_16_BIT_PAIR - Two 16-bit timers
 //!
@@ -144,10 +145,18 @@ TimerDisable(unsigned long ulBase, unsigned long ulTimer)
 //! the result of a logical OR operation between one of the following values
 //! and \e ulConfig:
 //!
-//! - \b TIMER_CFG_A_ONE_SHOT - 16-bit one shot timer
+//! - \b TIMER_CFG_A_ONE_SHOT - 16-bit one-shot timer
+//! - \b TIMER_CFG_A_ONE_SHOT_UP - 16-bit one-shot timer that counts up instead
+//!   of down (not available on all parts)
 //! - \b TIMER_CFG_A_PERIODIC - 16-bit periodic timer
+//! - \b TIMER_CFG_A_PERIODIC_UP - 16-bit periodic timer that counts up instead
+//!   of down (not available on all parts)
 //! - \b TIMER_CFG_A_CAP_COUNT - 16-bit edge count capture
+//! - \b TIMER_CFG_A_CAP_COUNT_UP - 16-bit edge count capture that counts up
+//!   instead of down (not available on all parts)
 //! - \b TIMER_CFG_A_CAP_TIME - 16-bit edge time capture
+//! - \b TIMER_CFG_A_CAP_TIME_UP - 16-bit edge time capture that counts up
+//!   instead of down (not available on all parts)
 //! - \b TIMER_CFG_A_PWM - 16-bit PWM output
 //!
 //! Similarly, the second timer is configured by setting \e ulConfig to
@@ -165,19 +174,27 @@ TimerConfigure(unsigned long ulBase, unsigned long ulConfig)
     //
     ASSERT(TimerBaseValid(ulBase));
     ASSERT((ulConfig == TIMER_CFG_32_BIT_OS) ||
+           (ulConfig == TIMER_CFG_32_BIT_OS_UP) ||
            (ulConfig == TIMER_CFG_32_BIT_PER) ||
+           (ulConfig == TIMER_CFG_32_BIT_PER_UP) ||
            (ulConfig == TIMER_CFG_32_RTC) ||
            ((ulConfig & 0xff000000) == TIMER_CFG_16_BIT_PAIR));
     ASSERT(((ulConfig & 0xff000000) != TIMER_CFG_16_BIT_PAIR) ||
            ((((ulConfig & 0x000000ff) == TIMER_CFG_A_ONE_SHOT) ||
+             ((ulConfig & 0x000000ff) == TIMER_CFG_A_ONE_SHOT_UP) ||
              ((ulConfig & 0x000000ff) == TIMER_CFG_A_PERIODIC) ||
+             ((ulConfig & 0x000000ff) == TIMER_CFG_A_PERIODIC_UP) ||
              ((ulConfig & 0x000000ff) == TIMER_CFG_A_CAP_COUNT) ||
              ((ulConfig & 0x000000ff) == TIMER_CFG_A_CAP_TIME) ||
              ((ulConfig & 0x000000ff) == TIMER_CFG_A_PWM)) &&
             (((ulConfig & 0x0000ff00) == TIMER_CFG_B_ONE_SHOT) ||
+             ((ulConfig & 0x0000ff00) == TIMER_CFG_B_ONE_SHOT_UP) ||
              ((ulConfig & 0x0000ff00) == TIMER_CFG_B_PERIODIC) ||
+             ((ulConfig & 0x0000ff00) == TIMER_CFG_B_PERIODIC_UP) ||
              ((ulConfig & 0x0000ff00) == TIMER_CFG_B_CAP_COUNT) ||
+             ((ulConfig & 0x0000ff00) == TIMER_CFG_B_CAP_COUNT_UP) ||
              ((ulConfig & 0x0000ff00) == TIMER_CFG_B_CAP_TIME) ||
+             ((ulConfig & 0x0000ff00) == TIMER_CFG_B_CAP_TIME_UP) ||
              ((ulConfig & 0x0000ff00) == TIMER_CFG_B_PWM))));
 
     //
@@ -208,8 +225,8 @@ TimerConfigure(unsigned long ulBase, unsigned long ulConfig)
 //! \param bInvert specifies the output level.
 //!
 //! This function sets the PWM output level for the specified timer.  If the
-//! \e bInvert parameter is \b true, then the timer's output will be made
-//! active low; otherwise, it will be made active high.
+//! \e bInvert parameter is \b true, then the timer's output is made active
+//! low; otherwise, it is made active high.
 //!
 //! \return None.
 //
@@ -281,7 +298,7 @@ TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer,
 //! \b TIMER_EVENT_POS_EDGE, \b TIMER_EVENT_NEG_EDGE, or
 //! \b TIMER_EVENT_BOTH_EDGES.
 //!
-//! This function sets the signal edge(s) that will trigger the timer when in
+//! This function sets the signal edge(s) that triggers the timer when in
 //! capture mode.
 //!
 //! \return None.
@@ -301,10 +318,9 @@ TimerControlEvent(unsigned long ulBase, unsigned long ulTimer,
     //
     // Set the event type.
     //
-    ulEvent &= ulTimer & (TIMER_CTL_TAEVENT_M | TIMER_CTL_TBEVENT_M);
-    HWREG(ulBase + TIMER_O_CTL) = ((HWREG(ulBase + TIMER_O_CTL) &
-                                    ~(TIMER_CTL_TAEVENT_M |
-                                      TIMER_CTL_TBEVENT_M)) | ulEvent);
+    ulTimer &= TIMER_CTL_TAEVENT_M | TIMER_CTL_TBEVENT_M;
+    HWREG(ulBase + TIMER_O_CTL) = ((HWREG(ulBase + TIMER_O_CTL) & ~ulTimer) |
+                                   (ulEvent & ulTimer));
 }
 
 //*****************************************************************************
@@ -317,8 +333,8 @@ TimerControlEvent(unsigned long ulBase, unsigned long ulTimer,
 //! \param bStall specifies the response to a stall signal.
 //!
 //! This function controls the stall response for the specified timer.  If the
-//! \e bStall parameter is \b true, then the timer will stop counting if the
-//! processor enters debug mode; otherwise the timer will keep running while in
+//! \e bStall parameter is \b true, then the timer stops counting if the
+//! processor enters debug mode; otherwise the timer keeps running while in
 //! debug mode.
 //!
 //! \return None.
@@ -326,7 +342,7 @@ TimerControlEvent(unsigned long ulBase, unsigned long ulTimer,
 //*****************************************************************************
 void
 TimerControlStall(unsigned long ulBase, unsigned long ulTimer,
-                  tBoolean  bStall)
+                  tBoolean bStall)
 {
     //
     // Check the arguments.
@@ -344,6 +360,67 @@ TimerControlStall(unsigned long ulBase, unsigned long ulTimer,
                                    (HWREG(ulBase + TIMER_O_CTL) & ~(ulTimer)));
 }
 
+//*****************************************************************************
+//
+//! Controls the wait on trigger handling.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer(s) to be adjusted; must be one of
+//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH.
+//! \param bWait specifies if the timer should wait for a trigger input.
+//!
+//! This function controls whether or not a timer waits for a trigger input to
+//! start counting.  When enabled, the previous timer in the trigger chain must
+//! count to its timeout in order for this timer to start counting.  Refer to
+//! the part's data sheet for a description of the trigger chain.
+//!
+//! \note This functionality is not available on all parts.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerControlWaitOnTrigger(unsigned long ulBase, unsigned long ulTimer,
+                          tBoolean bWait)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(TimerBaseValid(ulBase));
+    ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
+           (ulTimer == TIMER_BOTH));
+
+    //
+    // Set the wait on trigger mode for timer A.
+    //
+    if((ulTimer & TIMER_A) != 0)
+    {
+        if(bWait)
+        {
+            HWREG(ulBase + TIMER_O_TAMR) |= TIMER_TAMR_TAWOT;
+        }
+        else
+        {
+            HWREG(ulBase + TIMER_O_TAMR) &= ~(TIMER_TAMR_TAWOT);
+        }
+    }
+
+    //
+    // Set the wait on trigger mode for timer B.
+    //
+    if((ulTimer & TIMER_B) != 0)
+    {
+        if(bWait)
+        {
+            HWREG(ulBase + TIMER_O_TBMR) |= TIMER_TBMR_TBWOT;
+        }
+        else
+        {
+            HWREG(ulBase + TIMER_O_TBMR) &= ~(TIMER_TBMR_TBWOT);
+        }
+    }
+}
+
 //*****************************************************************************
 //
 //! Enable RTC counting.
@@ -351,7 +428,7 @@ TimerControlStall(unsigned long ulBase, unsigned long ulTimer,
 //! \param ulBase is the base address of the timer module.
 //!
 //! This function causes the timer to start counting when in RTC mode.  If not
-//! configured for RTC mode, this will do nothing.
+//! configured for RTC mode, this function does nothing.
 //!
 //! \return None.
 //
@@ -409,6 +486,10 @@ TimerRTCDisable(unsigned long ulBase)
 //! is only operational when in 16-bit mode and is used to extend the range of
 //! the 16-bit timer modes.
 //!
+//! \note The availability of the prescaler varies with the Stellaris part and
+//! timer mode in use.  Please consult the datasheet for the part you are using
+//! to determine whether this support is available.
+//!
 //! \return None.
 //
 //*****************************************************************************
@@ -453,6 +534,10 @@ TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer,
 //! is only operational when in 16-bit mode and is used to extend the range of
 //! the 16-bit timer modes.
 //!
+//! \note The availability of the prescaler varies with the Stellaris part and
+//! timer mode in use.  Please consult the datasheet for the part you are using
+//! to determine whether this support is available.
+//!
 //! \return The value of the timer prescaler.
 //
 //*****************************************************************************
@@ -473,6 +558,92 @@ TimerPrescaleGet(unsigned long ulBase, unsigned long ulTimer)
            HWREG(ulBase + TIMER_O_TBPR));
 }
 
+//*****************************************************************************
+//
+//! Set the timer prescale match value.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A,
+//! \b TIMER_B, or \b TIMER_BOTH.
+//! \param ulValue is the timer prescale match value; must be between 0 and
+//! 255, inclusive.
+//!
+//! This function sets the value of the input clock prescaler match value.
+//! When in a 16-bit mode that uses the counter match and the prescaler, the
+//! prescale match effectively extends the range of the counter to 24-bits.
+//!
+//! \note The availability of the prescaler match varies with the Stellaris
+//! part and timer mode in use.  Please consult the datasheet for the part you
+//! are using to determine whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer,
+                      unsigned long ulValue)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(TimerBaseValid(ulBase));
+    ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
+           (ulTimer == TIMER_BOTH));
+    ASSERT(ulValue < 256);
+
+    //
+    // Set the timer A prescale match if requested.
+    //
+    if(ulTimer & TIMER_A)
+    {
+        HWREG(ulBase + TIMER_O_TAPMR) = ulValue;
+    }
+
+    //
+    // Set the timer B prescale match if requested.
+    //
+    if(ulTimer & TIMER_B)
+    {
+        HWREG(ulBase + TIMER_O_TBPMR) = ulValue;
+    }
+}
+
+//*****************************************************************************
+//
+//! Get the timer prescale match value.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer; must be one of \b TIMER_A or
+//! \b TIMER_B.
+//!
+//! This function gets the value of the input clock prescaler match value.
+//! When in a 16-bit mode that uses the counter match and prescaler, the
+//! prescale match effectively extends the range of the counter to 24-bits.
+//!
+//! \note The availability of the prescaler match varies with the Stellaris
+//! part and timer mode in use.  Please consult the datasheet for the part you
+//! are using to determine whether this support is available.
+//!
+//! \return The value of the timer prescale match.
+//
+//*****************************************************************************
+unsigned long
+TimerPrescaleMatchGet(unsigned long ulBase, unsigned long ulTimer)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(TimerBaseValid(ulBase));
+    ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
+           (ulTimer == TIMER_BOTH));
+
+    //
+    // Return the appropriate prescale match value.
+    //
+    return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAPMR) :
+           HWREG(ulBase + TIMER_O_TBPMR));
+}
+
 //*****************************************************************************
 //
 //! Sets the timer load value.
@@ -663,10 +834,11 @@ TimerMatchGet(unsigned long ulBase, unsigned long ulTimer)
 //! \param pfnHandler is a pointer to the function to be called when the timer
 //! interrupt occurs.
 //!
-//! This sets the handler to be called when a timer interrupt occurs.  This
-//! will enable the global interrupt in the interrupt controller; specific
-//! timer interrupts must be enabled via TimerIntEnable().  It is the interrupt
-//! handler's responsibility to clear the interrupt source via TimerIntClear().
+//! This function sets the handler to be called when a timer interrupt occurs.
+//! In addition, this function enables the global interrupt in the interrupt
+//! controller; specific timer interrupts must be enabled via TimerIntEnable().
+//! It is the interrupt handler's responsibility to clear the interrupt source
+//! via TimerIntClear().
 //!
 //! \sa IntRegister() for important information about registering interrupt
 //! handlers.
@@ -733,9 +905,9 @@ TimerIntRegister(unsigned long ulBase, unsigned long ulTimer,
 //! \param ulTimer specifies the timer(s); must be one of \b TIMER_A,
 //! \b TIMER_B, or \b TIMER_BOTH.
 //!
-//! This function will clear the handler to be called when a timer interrupt
-//! occurs.  This will also mask off the interrupt in the interrupt controller
-//! so that the interrupt handler no longer is called.
+//! This function clears the handler to be called when a timer interrupt
+//! occurs.  This function also masks off the interrupt in the interrupt
+//! controller so that the interrupt handler no longer is called.
 //!
 //! \sa IntRegister() for important information about registering interrupt
 //! handlers.
@@ -871,9 +1043,9 @@ TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
 //! \param bMasked is false if the raw interrupt status is required and true if
 //! the masked interrupt status is required.
 //!
-//! This returns the interrupt status for the timer module.  Either the raw
-//! interrupt status or the status of interrupts that are allowed to reflect to
-//! the processor can be returned.
+//! This function returns the interrupt status for the timer module.  Either
+//! the raw interrupt status or the status of interrupts that are allowed to
+//! reflect to the processor can be returned.
 //!
 //! \return The current interrupt status, enumerated as a bit field of
 //! values described in TimerIntEnable().
@@ -903,20 +1075,20 @@ TimerIntStatus(unsigned long ulBase, tBoolean bMasked)
 //! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
 //!
 //! The specified timer interrupt sources are cleared, so that they no longer
-//! assert.  This must be done in the interrupt handler to keep it from being
-//! called again immediately upon exit.
+//! assert.  This function must be called in the interrupt handler to keep the
+//! interrupt from being triggered again immediately upon exit.
 //!
 //! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
 //! parameter to TimerIntEnable().
 //!
-//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
-//! several clock cycles before the interrupt source is actually cleared.
+//! \note Because there is a write buffer in the Cortex-M3 processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
 //! Therefore, it is recommended that the interrupt source be cleared early in
 //! the interrupt handler (as opposed to the very last action) to avoid
 //! returning from the interrupt handler before the interrupt source is
 //! actually cleared.  Failure to do so may result in the interrupt handler
-//! being immediately reentered (since NVIC still sees the interrupt source
-//! asserted).
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
 //!
 //! \return None.
 //
diff --git a/src/platform/lm3s/timer.h b/src/platform/lm3s/driverlib/timer.h
similarity index 63%
rename from src/platform/lm3s/timer.h
rename to src/platform/lm3s/driverlib/timer.h
index 06a1edd6..e1dabf62 100755
--- a/src/platform/lm3s/timer.h
+++ b/src/platform/lm3s/driverlib/timer.h
@@ -2,26 +2,23 @@
 //
 // timer.h - Prototypes for the timer module
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2011 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
+// This is part of revision 7611 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -44,20 +41,30 @@ extern "C"
 // Values that can be passed to TimerConfigure as the ulConfig parameter.
 //
 //*****************************************************************************
-#define TIMER_CFG_32_BIT_OS     0x00000001  // 32-bit one-shot timer
-#define TIMER_CFG_32_BIT_PER    0x00000002  // 32-bit periodic timer
-#define TIMER_CFG_32_RTC        0x01000000  // 32-bit RTC timer
-#define TIMER_CFG_16_BIT_PAIR   0x04000000  // Two 16-bit timers
-#define TIMER_CFG_A_ONE_SHOT    0x00000001  // Timer A one-shot timer
-#define TIMER_CFG_A_PERIODIC    0x00000002  // Timer A periodic timer
-#define TIMER_CFG_A_CAP_COUNT   0x00000003  // Timer A event counter
-#define TIMER_CFG_A_CAP_TIME    0x00000007  // Timer A event timer
-#define TIMER_CFG_A_PWM         0x0000000A  // Timer A PWM output
-#define TIMER_CFG_B_ONE_SHOT    0x00000100  // Timer B one-shot timer
-#define TIMER_CFG_B_PERIODIC    0x00000200  // Timer B periodic timer
-#define TIMER_CFG_B_CAP_COUNT   0x00000300  // Timer B event counter
-#define TIMER_CFG_B_CAP_TIME    0x00000700  // Timer B event timer
-#define TIMER_CFG_B_PWM         0x00000A00  // Timer B PWM output
+#define TIMER_CFG_32_BIT_OS      0x00000021  // 32-bit one-shot timer
+#define TIMER_CFG_32_BIT_OS_UP   0x00000031  // 32-bit one-shot up-count timer
+#define TIMER_CFG_32_BIT_PER     0x00000022  // 32-bit periodic timer
+#define TIMER_CFG_32_BIT_PER_UP  0x00000032  // 32-bit periodic up-count timer
+#define TIMER_CFG_32_RTC         0x01000000  // 32-bit RTC timer
+#define TIMER_CFG_16_BIT_PAIR    0x04000000  // Two 16-bit timers
+#define TIMER_CFG_A_ONE_SHOT     0x00000021  // Timer A one-shot timer
+#define TIMER_CFG_A_ONE_SHOT_UP  0x00000031  // Timer A one-shot up-count timer
+#define TIMER_CFG_A_PERIODIC     0x00000022  // Timer A periodic timer
+#define TIMER_CFG_A_PERIODIC_UP  0x00000032  // Timer A periodic up-count timer
+#define TIMER_CFG_A_CAP_COUNT    0x00000003  // Timer A event counter
+#define TIMER_CFG_A_CAP_COUNT_UP 0x00000013  // Timer A event up-counter
+#define TIMER_CFG_A_CAP_TIME     0x00000007  // Timer A event timer
+#define TIMER_CFG_A_CAP_TIME_UP  0x00000017  // Timer A event up-count timer
+#define TIMER_CFG_A_PWM          0x0000000A  // Timer A PWM output
+#define TIMER_CFG_B_ONE_SHOT     0x00002100  // Timer B one-shot timer
+#define TIMER_CFG_B_ONE_SHOT_UP  0x00003100  // Timer B one-shot up-count timer
+#define TIMER_CFG_B_PERIODIC     0x00002200  // Timer B periodic timer
+#define TIMER_CFG_B_PERIODIC_UP  0x00003200  // Timer B periodic up-count timer
+#define TIMER_CFG_B_CAP_COUNT    0x00000300  // Timer B event counter
+#define TIMER_CFG_B_CAP_COUNT_UP 0x00001300  // Timer B event up-counter
+#define TIMER_CFG_B_CAP_TIME     0x00000700  // Timer B event timer
+#define TIMER_CFG_B_CAP_TIME_UP  0x00001700  // Timer B event up-count timer
+#define TIMER_CFG_B_PWM          0x00000A00  // Timer B PWM output
 
 //*****************************************************************************
 //
@@ -65,9 +72,11 @@ extern "C"
 // TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus.
 //
 //*****************************************************************************
+#define TIMER_TIMB_MATCH        0x00000800  // TimerB match interrupt
 #define TIMER_CAPB_EVENT        0x00000400  // CaptureB event interrupt
 #define TIMER_CAPB_MATCH        0x00000200  // CaptureB match interrupt
 #define TIMER_TIMB_TIMEOUT      0x00000100  // TimerB time out interrupt
+#define TIMER_TIMA_MATCH        0x00000010  // TimerA match interrupt
 #define TIMER_RTC_MATCH         0x00000008  // RTC interrupt mask
 #define TIMER_CAPA_EVENT        0x00000004  // CaptureA event interrupt
 #define TIMER_CAPA_MATCH        0x00000002  // CaptureA match interrupt
@@ -108,12 +117,19 @@ extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer,
                               unsigned long ulEvent);
 extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer,
                               tBoolean bStall);
+extern void TimerControlWaitOnTrigger(unsigned long ulBase,
+                                      unsigned long ulTimer,
+                                      tBoolean bWait);
 extern void TimerRTCEnable(unsigned long ulBase);
 extern void TimerRTCDisable(unsigned long ulBase);
 extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer,
                              unsigned long ulValue);
 extern unsigned long TimerPrescaleGet(unsigned long ulBase,
                                       unsigned long ulTimer);
+extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer,
+                                  unsigned long ulValue);
+extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase,
+                                           unsigned long ulTimer);
 extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer,
                          unsigned long ulValue);
 extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer);
diff --git a/src/platform/lm3s/uart.c b/src/platform/lm3s/driverlib/uart.c
similarity index 83%
rename from src/platform/lm3s/uart.c
rename to src/platform/lm3s/driverlib/uart.c
index 2f636de2..ed283eb7 100755
--- a/src/platform/lm3s/uart.c
+++ b/src/platform/lm3s/driverlib/uart.c
@@ -2,26 +2,23 @@
 //
 // uart.c - Driver for the UART.
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2011 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
+// This is part of revision 7611 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -32,14 +29,14 @@
 //
 //*****************************************************************************
 
-#include "hw_ints.h"
-#include "hw_memmap.h"
-#include "hw_sysctl.h"
-#include "hw_types.h"
-#include "hw_uart.h"
-#include "debug.h"
-#include "interrupt.h"
-#include "uart.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_sysctl.h"
+#include "inc/hw_types.h"
+#include "inc/hw_uart.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+#include "driverlib/uart.h"
 
 //*****************************************************************************
 //
@@ -81,11 +78,12 @@ UARTBaseValid(unsigned long ulBase)
 //! \param ulBase is the base address of the UART port.
 //! \param ulParity specifies the type of parity to use.
 //!
-//! Sets the type of parity to use for transmitting and expect when receiving.
-//! The \e ulParity parameter must be one of \b UART_CONFIG_PAR_NONE,
-//! \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD, \b UART_CONFIG_PAR_ONE,
-//! or \b UART_CONFIG_PAR_ZERO.  The last two allow direct control of the
-//! parity bit; it will always be either be one or zero based on the mode.
+//! This function sets the type of parity to use for transmitting and expect
+//! when receiving.  The \e ulParity parameter must be one of
+//! \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD,
+//! \b UART_CONFIG_PAR_ONE, or \b UART_CONFIG_PAR_ZERO.  The last two allow
+//! direct control of the parity bit; it is always either one or zero based on
+//! the mode.
 //!
 //! \return None.
 //
@@ -117,7 +115,7 @@ UARTParityModeSet(unsigned long ulBase, unsigned long ulParity)
 //!
 //! \param ulBase is the base address of the UART port.
 //!
-//! This function gets the type of parity used for transmitting data, and
+//! This function gets the type of parity used for transmitting data and
 //! expected when receiving data.
 //!
 //! \return Returns the current parity settings, specified as one of
@@ -153,7 +151,7 @@ UARTParityModeGet(unsigned long ulBase)
 //! \b UART_FIFO_RX6_8, or \b UART_FIFO_RX7_8.
 //!
 //! This function sets the FIFO level at which transmit and receive interrupts
-//! will be generated.
+//! are generated.
 //!
 //! \return None.
 //
@@ -190,13 +188,13 @@ UARTFIFOLevelSet(unsigned long ulBase, unsigned long ulTxLevel,
 //! \param ulBase is the base address of the UART port.
 //! \param pulTxLevel is a pointer to storage for the transmit FIFO level,
 //! returned as one of \b UART_FIFO_TX1_8, \b UART_FIFO_TX2_8,
-//! \b UART_FIFO_TX4_8, \b UART_FIFO_TX6_8, or UART_FIFO_TX7_8.
+//! \b UART_FIFO_TX4_8, \b UART_FIFO_TX6_8, or \b UART_FIFO_TX7_8.
 //! \param pulRxLevel is a pointer to storage for the receive FIFO level,
 //! returned as one of \b UART_FIFO_RX1_8, \b UART_FIFO_RX2_8,
 //! \b UART_FIFO_RX4_8, \b UART_FIFO_RX6_8, or \b UART_FIFO_RX7_8.
 //!
 //! This function gets the FIFO level at which transmit and receive interrupts
-//! will be generated.
+//! are generated.
 //!
 //! \return None.
 //
@@ -234,7 +232,7 @@ UARTFIFOLevelGet(unsigned long ulBase, unsigned long *pulTxLevel,
 //! \param ulConfig is the data format for the port (number of data bits,
 //! number of stop bits, and parity).
 //!
-//! This function will configure the UART for operation in the specified data
+//! This function configures the UART for operation in the specified data
 //! format.  The baud rate is provided in the \e ulBaud parameter and the data
 //! format in the \e ulConfig parameter.
 //!
@@ -248,10 +246,10 @@ UARTFIFOLevelGet(unsigned long ulBase, unsigned long *pulTxLevel,
 //! select the parity mode (no parity bit, even parity bit, odd parity bit,
 //! parity bit always one, and parity bit always zero, respectively).
 //!
-//! The peripheral clock will be the same as the processor clock.  This will be
-//! the value returned by SysCtlClockGet(), or it can be explicitly hard coded
-//! if it is constant and known (to save the code/execution overhead of a call
-//! to SysCtlClockGet()).
+//! The peripheral clock is the same as the processor clock.  The frequency of
+//! the system clock is the value returned by SysCtlClockGet(), or it can be
+//! explicitly hard coded if it is constant and known (to save the
+//! code/execution overhead of a call to SysCtlClockGet()).
 //!
 //! This function replaces the original UARTConfigSet() API and performs the
 //! same actions.  A macro is provided in uart.h to map the original
@@ -346,10 +344,10 @@ UARTConfigSetExpClk(unsigned long ulBase, unsigned long ulUARTClk,
 //! \e pulConfig is enumerated the same as the \e ulConfig parameter of
 //! UARTConfigSetExpClk().
 //!
-//! The peripheral clock will be the same as the processor clock.  This will be
-//! the value returned by SysCtlClockGet(), or it can be explicitly hard coded
-//! if it is constant and known (to save the code/execution overhead of a call
-//! to SysCtlClockGet()).
+//! The peripheral clock is the same as the processor clock.  The frequency of
+//! the system clock is the value returned by SysCtlClockGet(), or it can be
+//! explicitly hard coded if it is constant and known (to save the
+//! code/execution overhead of a call to SysCtlClockGet()).
 //!
 //! This function replaces the original UARTConfigGet() API and performs the
 //! same actions.  A macro is provided in uart.h to map the original
@@ -402,8 +400,8 @@ UARTConfigGetExpClk(unsigned long ulBase, unsigned long ulUARTClk,
 //!
 //! \param ulBase is the base address of the UART port.
 //!
-//! Sets the UARTEN, TXE, and RXE bits, and enables the transmit and receive
-//! FIFOs.
+//! This function sets the UARTEN, TXE, and RXE bits, and enables the transmit
+//! and receive FIFOs.
 //!
 //! \return None.
 //
@@ -434,7 +432,7 @@ UARTEnable(unsigned long ulBase)
 //!
 //! \param ulBase is the base address of the UART port.
 //!
-//! Clears the UARTEN, TXE, and RXE bits, then waits for the end of
+//! This function clears the UARTEN, TXE, and RXE bits, waits for the end of
 //! transmission of the current character, and flushes the transmit FIFO.
 //!
 //! \return None.
@@ -524,10 +522,12 @@ UARTFIFODisable(unsigned long ulBase)
 //! \param ulBase is the base address of the UART port.
 //! \param bLowPower indicates if SIR Low Power Mode is to be used.
 //!
-//! Enables the SIREN control bit for IrDA mode on the UART.  If the
-//! \e bLowPower flag is set, then SIRLP bit will also be set.
+//! This function enables the SIREN control bit for IrDA mode on the UART.  If
+//! the \e bLowPower flag is set, then SIRLP bit will also be set.
 //!
-//! \note SIR (IrDA) operation is not supported on Sandstorm-class devices.
+//! \note The availability of SIR (IrDA) operation varies with the Stellaris
+//! part and UART in use.  Please consult the datasheet for the part you are
+//! using to determine whether this support is available.
 //!
 //! \return None.
 //
@@ -559,9 +559,11 @@ UARTEnableSIR(unsigned long ulBase, tBoolean bLowPower)
 //!
 //! \param ulBase is the base address of the UART port.
 //!
-//! Clears the SIREN (IrDA) and SIRLP (Low Power) bits.
+//! This function clears the SIREN (IrDA) and SIRLP (Low Power) bits.
 //!
-//! \note SIR (IrDA) operation is not supported on Sandstorm-class devices.
+//! \note The availability of SIR (IrDA) operation varies with the Stellaris
+//! part and UART in use.  Please consult the datasheet for the part you are
+//! using to determine whether this support is available.
 //!
 //! \return None.
 //
@@ -582,15 +584,15 @@ UARTDisableSIR(unsigned long ulBase)
 
 //*****************************************************************************
 //
-//! Enables ISO 7816 smart card mode on the specified UART.
+//! Enables ISO7816 smart card mode on the specified UART.
 //!
 //! \param ulBase is the base address of the UART port.
 //!
-//! Enables the SMART control bit for ISO 7816 smart card mode on the UART.
-//! This call also sets 8 bit word length and even parity as required by ISO
-//! 7816.
+//! This function enables the SMART control bit for ISO7816 smart card mode on
+//! the UART.  This call also sets 8 bit word length and even parity as
+//! required by ISO7816.
 //!
-//! \note The availability of ISO 7816 smart card mode varies with the
+//! \note The availability of ISO7816 smart card mode varies with the
 //! Stellaris part and UART in use.  Please consult the datasheet for the part
 //! you are using to determine whether this support is available.
 //!
@@ -606,8 +608,7 @@ UARTSmartCardEnable(unsigned long ulBase)
     // Check the arguments.
     //
     ASSERT(!CLASS_IS_SANDSTORM && !CLASS_IS_FURY && !CLASS_IS_DUSTDEVIL);
-    ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE) ||
-           (ulBase == UART2_BASE));
+    ASSERT(UARTBaseValid(ulBase));
 
     //
     // Set 8 bit word length, even parity, 2 stop bits (even though the STP2
@@ -628,13 +629,14 @@ UARTSmartCardEnable(unsigned long ulBase)
 
 //*****************************************************************************
 //
-//! Disables ISO 7816 smart card mode on the specified UART.
+//! Disables ISO7816 smart card mode on the specified UART.
 //!
 //! \param ulBase is the base address of the UART port.
 //!
-//! Clears the SMART (ISO 7816 smart card) bits in the UART control register.
+//! This function clears the SMART (ISO7816 smart card) bits in the UART
+//! control register.
 //!
-//! \note The availability of ISO 7816 smart card mode varies with the
+//! \note The availability of ISO7816 smart card mode varies with the
 //! Stellaris part and UART in use.  Please consult the datasheet for the part
 //! you are using to determine whether this support is available.
 //!
@@ -648,8 +650,7 @@ UARTSmartCardDisable(unsigned long ulBase)
     // Check the arguments.
     //
     ASSERT(!CLASS_IS_SANDSTORM && !CLASS_IS_FURY && !CLASS_IS_DUSTDEVIL);
-    ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE) ||
-           (ulBase == UART2_BASE));
+    ASSERT(UARTBaseValid(ulBase));
 
     //
     // Disable the SMART bit.
@@ -665,7 +666,8 @@ UARTSmartCardDisable(unsigned long ulBase)
 //! \param ulControl is a bit-mapped flag indicating which modem control bits
 //! should be set.
 //!
-//! Sets the states of the DTR or RTS modem handshake outputs from the UART.
+//! This function sets the states of the DTR or RTS modem handshake outputs
+//! from the UART.
 //!
 //! The \e ulControl parameter is the logical OR of any of the following:
 //!
@@ -707,7 +709,8 @@ UARTModemControlSet(unsigned long ulBase, unsigned long ulControl)
 //! \param ulControl is a bit-mapped flag indicating which modem control bits
 //! should be set.
 //!
-//! Clears the states of the DTR or RTS modem handshake outputs from the UART.
+//! This function clears the states of the DTR or RTS modem handshake outputs
+//! from the UART.
 //!
 //! The \e ulControl parameter is the logical OR of any of the following:
 //!
@@ -747,8 +750,8 @@ UARTModemControlClear(unsigned long ulBase, unsigned long ulControl)
 //!
 //! \param ulBase is the base address of the UART port.
 //!
-//! Returns the current states of each of the two UART modem control signals,
-//! DTR and RTS.
+//! This function returns the current states of each of the two UART modem
+//! control signals, DTR and RTS.
 //!
 //! \note The availability of hardware modem handshake signals varies with the
 //! Stellaris part and UART in use.  Please consult the datasheet for the part
@@ -778,16 +781,16 @@ UARTModemControlGet(unsigned long ulBase)
 //!
 //! \param ulBase is the base address of the UART port.
 //!
-//! Returns the current states of each of the four UART modem status signals,
-//! RI, DCD, DSR and CTS.
+//! This function returns the current states of each of the four UART modem
+//! status signals, RI, DCD, DSR and CTS.
 //!
 //! \note The availability of hardware modem handshake signals varies with the
 //! Stellaris part and UART in use.  Please consult the datasheet for the part
 //! you are using to determine whether this support is available.
 //!
-//! \return Returns the states of the handshake output signals.  This will be a
-//! logical logical OR combination of values \b UART_INPUT_RI, \b
-//! UART_INPUT_DCD, \b UART_INPUT_CTS and \b UART_INPUT_DSR where the
+//! \return Returns the states of the handshake output signals.  This value
+//! will be a logical logical OR combination of values \b UART_INPUT_RI,
+//! \b UART_INPUT_DCD, \b UART_INPUT_CTS and \b UART_INPUT_DSR where the
 //! presence of each flag indicates that the associated signal is asserted.
 //
 //*****************************************************************************
@@ -809,17 +812,18 @@ UARTModemStatusGet(unsigned long ulBase)
 //! Sets the UART hardware flow control mode to be used.
 //!
 //! \param ulBase is the base address of the UART port.
-//! \param ulMode indicates the flow control modes to be used.  This is a
-//! logical OR combination of values \b UART_FLOWCONTROL_TX and \b
-//! UART_FLOWCONTROL_RX to enable hardware transmit (CTS) and receive (RTS)
+//! \param ulMode indicates the flow control modes to be used.  This parameter
+//! is a logical OR combination of values \b UART_FLOWCONTROL_TX and
+//! \b UART_FLOWCONTROL_RX to enable hardware transmit (CTS) and receive (RTS)
 //! flow control or \b UART_FLOWCONTROL_NONE to disable hardware flow control.
 //!
-//! Sets the required hardware flow control modes.  If \e ulMode contains
-//! flag \b UART_FLOWCONTROL_TX, data is only transmitted if the incoming CTS
-//! signal is asserted. If \e ulMode contains flag \b UART_FLOWCONTROL_RX,
-//! the RTS output is controlled by the hardware and is asserted only when
-//! there is space available in the receive FIFO.  If no hardware flow control
-//! is required, UART_FLOWCONTROL_NONE should be passed.
+//! This function sets the required hardware flow control modes.  If \e ulMode
+//! contains flag \b UART_FLOWCONTROL_TX, data is only transmitted if the
+//! incoming CTS signal is asserted. If \e ulMode contains flag
+//! \b UART_FLOWCONTROL_RX, the RTS output is controlled by the hardware and is
+//! asserted only when there is space available in the receive FIFO.  If no
+//! hardware flow control is required, \b UART_FLOWCONTROL_NONE should be
+//! passed.
 //!
 //! \note The availability of hardware flow control varies with the Stellaris
 //! part and UART in use.  Please consult the datasheet for the part you are
@@ -835,8 +839,7 @@ UARTFlowControlSet(unsigned long ulBase, unsigned long ulMode)
     // Check the arguments.
     //
     ASSERT(!CLASS_IS_SANDSTORM && !CLASS_IS_FURY && !CLASS_IS_DUSTDEVIL);
-    ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE) ||
-           (ulBase == UART2_BASE));
+    ASSERT(UARTBaseValid(ulBase));
     ASSERT((ulMode & ~(UART_FLOWCONTROL_TX | UART_FLOWCONTROL_RX)) == 0);
 
     //
@@ -853,7 +856,7 @@ UARTFlowControlSet(unsigned long ulBase, unsigned long ulMode)
 //!
 //! \param ulBase is the base address of the UART port.
 //!
-//! Returns the current hardware flow control mode.
+//! This function returns the current hardware flow control mode.
 //!
 //! \note The availability of hardware flow control varies with the Stellaris
 //! part and UART in use.  Please consult the datasheet for the part you are
@@ -862,8 +865,8 @@ UARTFlowControlSet(unsigned long ulBase, unsigned long ulMode)
 //! \return Returns the current flow control mode in use.  This is a
 //! logical OR combination of values \b UART_FLOWCONTROL_TX if transmit
 //! (CTS) flow control is enabled and \b UART_FLOWCONTROL_RX if receive (RTS)
-//! flow control is in use.  If hardware flow control is disabled, \b
-//! UART_FLOWCONTROL_NONE will be returned.
+//! flow control is in use.  If hardware flow control is disabled,
+//! \b UART_FLOWCONTROL_NONE is returned.
 //
 //*****************************************************************************
 unsigned long
@@ -873,8 +876,7 @@ UARTFlowControlGet(unsigned long ulBase)
     // Check the arguments.
     //
     ASSERT(!CLASS_IS_SANDSTORM && !CLASS_IS_FURY && !CLASS_IS_DUSTDEVIL);
-    ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE) ||
-           (ulBase == UART2_BASE));
+    ASSERT(UARTBaseValid(ulBase));
 
     return(HWREG(ulBase + UART_O_CTL) & (UART_FLOWCONTROL_TX |
                                          UART_FLOWCONTROL_RX));
@@ -894,9 +896,9 @@ UARTFlowControlGet(unsigned long ulBase)
 //! default, the transmit interrupt is asserted when the FIFO level falls past
 //! a threshold set via a call to UARTFIFOLevelSet().  Alternatively, if this
 //! function is called with \e ulMode set to \b UART_TXINT_MODE_EOT, the
-//! transmit interrupt will only be asserted once the transmitter is completely
-//! idle - the transmit FIFO is empty and all bits, including any stop bits,
-//! have cleared the transmitter.
+//! transmit interrupt is asserted once the transmitter is completely idle -
+//! the transmit FIFO is empty and all bits, including any stop bits, have
+//! cleared the transmitter.
 //!
 //! \note The availability of end-of-transmission mode varies with the
 //! Stellaris part in use.  Please consult the datasheet for the part you are
@@ -911,8 +913,7 @@ UARTTxIntModeSet(unsigned long ulBase, unsigned long ulMode)
     //
     // Check the arguments.
     //
-    ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE) ||
-           (ulBase == UART2_BASE));
+    ASSERT(UARTBaseValid(ulBase));
     ASSERT((ulMode == UART_TXINT_MODE_EOT) ||
            (ulMode == UART_TXINT_MODE_FIFO));
 
@@ -931,12 +932,12 @@ UARTTxIntModeSet(unsigned long ulBase, unsigned long ulMode)
 //! \param ulBase is the base address of the UART port.
 //!
 //! This function returns the current operating mode for the UART transmit
-//! interrupt.  The return value will be \b UART_TXINT_MODE_EOT if the
-//! transmit interrupt is currently set to be asserted once the transmitter is
+//! interrupt.  The return value is \b UART_TXINT_MODE_EOT if the transmit
+//! interrupt is currently set to be asserted once the transmitter is
 //! completely idle - the transmit FIFO is empty and all bits, including any
-//! stop bits, have cleared the transmitter.  The return value will be \b
-//! UART_TXINT_MODE_FIFO if the interrupt is set to be asserted based upon the
-//! level of the transmit FIFO.
+//! stop bits, have cleared the transmitter.  The return value is
+//! \b UART_TXINT_MODE_FIFO if the interrupt is set to be asserted based upon
+//! the level of the transmit FIFO.
 //!
 //! \note The availability of end-of-transmission mode varies with the
 //! Stellaris part in use.  Please consult the datasheet for the part you are
@@ -951,8 +952,7 @@ UARTTxIntModeGet(unsigned long ulBase)
     //
     // Check the arguments.
     //
-    ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE) ||
-           (ulBase == UART2_BASE));
+    ASSERT(UARTBaseValid(ulBase));
 
     //
     // Return the current transmit interrupt mode.
@@ -970,7 +970,7 @@ UARTTxIntModeGet(unsigned long ulBase)
 //! This function returns a flag indicating whether or not there is data
 //! available in the receive FIFO.
 //!
-//! \return Returns \b true if there is data in the receive FIFO, and \b false
+//! \return Returns \b true if there is data in the receive FIFO or \b false
 //! if there is no data in the receive FIFO.
 //
 //*****************************************************************************
@@ -997,8 +997,8 @@ UARTCharsAvail(unsigned long ulBase)
 //! This function returns a flag indicating whether or not there is space
 //! available in the transmit FIFO.
 //!
-//! \return Returns \b true if there is space available in the transmit FIFO,
-//! and \b false if there is no space available in the transmit FIFO.
+//! \return Returns \b true if there is space available in the transmit FIFO
+//! or \b false if there is no space available in the transmit FIFO.
 //
 //*****************************************************************************
 tBoolean
@@ -1021,15 +1021,16 @@ UARTSpaceAvail(unsigned long ulBase)
 //!
 //! \param ulBase is the base address of the UART port.
 //!
-//! Gets a character from the receive FIFO for the specified port.
+//! This function gets a character from the receive FIFO for the specified
+//! port.
 //!
 //! This function replaces the original UARTCharNonBlockingGet() API and
 //! performs the same actions.  A macro is provided in uart.h to map
 //! the original API to this API.
 //!
 //! \return Returns the character read from the specified port, cast as a
-//! \e long.  A \b -1 will be returned if there are no characters present in
-//! the receive FIFO.  The UARTCharsAvail() function should be called before
+//! \e long.  A \b -1 is returned if there are no characters present in the
+//! receive FIFO.  The UARTCharsAvail() function should be called before
 //! attempting to call this function.
 //
 //*****************************************************************************
@@ -1066,11 +1067,11 @@ UARTCharGetNonBlocking(unsigned long ulBase)
 //!
 //! \param ulBase is the base address of the UART port.
 //!
-//! Gets a character from the receive FIFO for the specified port.  If there
-//! are no characters available, this function will wait until a character is
-//! received before returning.
+//! This function gets a character from the receive FIFO for the specified
+//! port.  If there are no characters available, this function waits until a
+//! character is received before returning.
 //!
-//! \return Returns the character read from the specified port, cast as an
+//! \return Returns the character read from the specified port, cast as a
 //! \e long.
 //
 //*****************************************************************************
@@ -1102,17 +1103,17 @@ UARTCharGet(unsigned long ulBase)
 //! \param ulBase is the base address of the UART port.
 //! \param ucData is the character to be transmitted.
 //!
-//! Writes the character \e ucData to the transmit FIFO for the specified port.
-//! This function does not block, so if there is no space available, then a
-//! \b false is returned, and the application will have to retry the function
-//! later.
+//! This function writes the character \e ucData to the transmit FIFO for the
+//! specified port.  This function does not block, so if there is no space
+//! available, then a \b false is returned, and the application must retry the
+//! function later.
 //!
 //! This function replaces the original UARTCharNonBlockingPut() API and
 //! performs the same actions.  A macro is provided in uart.h to map
 //! the original API to this API.
 //!
 //! \return Returns \b true if the character was successfully placed in the
-//! transmit FIFO, and \b false if there was no space available in the transmit
+//! transmit FIFO or \b false if there was no space available in the transmit
 //! FIFO.
 //
 //*****************************************************************************
@@ -1155,9 +1156,9 @@ UARTCharPutNonBlocking(unsigned long ulBase, unsigned char ucData)
 //! \param ulBase is the base address of the UART port.
 //! \param ucData is the character to be transmitted.
 //!
-//! Sends the character \e ucData to the transmit FIFO for the specified port.
-//! If there is no space available in the transmit FIFO, this function will
-//! wait until there is space available before returning.
+//! This function sends the character \e ucData to the transmit FIFO for the
+//! specified port.  If there is no space available in the transmit FIFO, this
+//! function waits until there is space available before returning.
 //!
 //! \return None.
 //
@@ -1190,10 +1191,10 @@ UARTCharPut(unsigned long ulBase, unsigned char ucData)
 //! \param ulBase is the base address of the UART port.
 //! \param bBreakState controls the output level.
 //!
-//! Calling this function with \e bBreakState set to \b true will assert a
-//! break condition on the UART.  Calling this function with \e bBreakState set
-//! to \b false will remove the break condition.  For proper transmission of a
-//! break command, the break must be asserted for at least two complete frames.
+//! Calling this function with \e bBreakState set to \b true asserts a break
+//! condition on the UART.  Calling this function with \e bBreakState set to
+//! \b false removes the break condition.  For proper transmission of a break
+//! command, the break must be asserted for at least two complete frames.
 //!
 //! \return None.
 //
@@ -1253,8 +1254,8 @@ UARTBusy(unsigned long ulBase)
 //! UART interrupt occurs.
 //!
 //! This function does the actual registering of the interrupt handler.  This
-//! will enable the global interrupt in the interrupt controller; specific UART
-//! interrupts must be enabled via UARTIntEnable().  It is the interrupt
+//! function enables the global interrupt in the interrupt controller; specific
+//! UART interrupts must be enabled via UARTIntEnable().  It is the interrupt
 //! handler's responsibility to clear the interrupt source.
 //!
 //! \sa IntRegister() for important information about registering interrupt
@@ -1297,9 +1298,9 @@ UARTIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
 //! \param ulBase is the base address of the UART port.
 //!
 //! This function does the actual unregistering of the interrupt handler.  It
-//! will clear the handler to be called when a UART interrupt occurs.  This
-//! will also mask off the interrupt in the interrupt controller so that the
-//! interrupt handler no longer is called.
+//! clears the handler to be called when a UART interrupt occurs.  This
+//! function also masks off the interrupt in the interrupt controller so that
+//! the interrupt handler no longer is called.
 //!
 //! \sa IntRegister() for important information about registering interrupt
 //! handlers.
@@ -1341,9 +1342,9 @@ UARTIntUnregister(unsigned long ulBase)
 //! \param ulBase is the base address of the UART port.
 //! \param ulIntFlags is the bit mask of the interrupt sources to be enabled.
 //!
-//! Enables the indicated UART interrupt sources.  Only the sources that are
-//! enabled can be reflected to the processor interrupt; disabled sources have
-//! no effect on the processor.
+//! This function enables the indicated UART interrupt sources.  Only the
+//! sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
 //!
 //! The \e ulIntFlags parameter is the logical OR of any of the following:
 //!
@@ -1383,9 +1384,9 @@ UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
 //! \param ulBase is the base address of the UART port.
 //! \param ulIntFlags is the bit mask of the interrupt sources to be disabled.
 //!
-//! Disables the indicated UART interrupt sources.  Only the sources that are
-//! enabled can be reflected to the processor interrupt; disabled sources have
-//! no effect on the processor.
+//! This function disables the indicated UART interrupt sources.  Only the
+//! sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
 //!
 //! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
 //! parameter to UARTIntEnable().
@@ -1412,12 +1413,12 @@ UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
 //! Gets the current interrupt status.
 //!
 //! \param ulBase is the base address of the UART port.
-//! \param bMasked is false if the raw interrupt status is required and true
-//! if the masked interrupt status is required.
+//! \param bMasked is \b false if the raw interrupt status is required and
+//! \b true if the masked interrupt status is required.
 //!
-//! This returns the interrupt status for the specified UART.  Either the raw
-//! interrupt status or the status of interrupts that are allowed to reflect to
-//! the processor can be returned.
+//! This function returns the interrupt status for the specified UART.  Either
+//! the raw interrupt status or the status of interrupts that are allowed to
+//! reflect to the processor can be returned.
 //!
 //! \return Returns the current interrupt status, enumerated as a bit field of
 //! values described in UARTIntEnable().
@@ -1453,20 +1454,20 @@ UARTIntStatus(unsigned long ulBase, tBoolean bMasked)
 //! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
 //!
 //! The specified UART interrupt sources are cleared, so that they no longer
-//! assert.  This must be done in the interrupt handler to keep it from being
-//! called again immediately upon exit.
+//! assert.  This function must be called in the interrupt handler to keep the
+//! interrupt from being recognized again immediately upon exit.
 //!
 //! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
 //! parameter to UARTIntEnable().
 //!
-//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
-//! several clock cycles before the interrupt source is actually cleared.
+//! \note Because there is a write buffer in the Cortex-M3 processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
 //! Therefore, it is recommended that the interrupt source be cleared early in
 //! the interrupt handler (as opposed to the very last action) to avoid
 //! returning from the interrupt handler before the interrupt source is
 //! actually cleared.  Failure to do so may result in the interrupt handler
-//! being immediately reentered (since NVIC still sees the interrupt source
-//! asserted).
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
 //!
 //! \return None.
 //
diff --git a/src/platform/lm3s/uart.h b/src/platform/lm3s/driverlib/uart.h
similarity index 90%
rename from src/platform/lm3s/uart.h
rename to src/platform/lm3s/driverlib/uart.h
index 534fb2ab..c6734767 100755
--- a/src/platform/lm3s/uart.h
+++ b/src/platform/lm3s/driverlib/uart.h
@@ -2,26 +2,23 @@
 //
 // uart.h - Defines and Macros for the UART.
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2011 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
+// This is part of revision 7611 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -223,7 +220,7 @@ extern unsigned long UARTTxIntModeGet(unsigned long ulBase);
 //
 //*****************************************************************************
 #ifndef DEPRECATED
-#include "sysctl.h"
+#include "driverlib/sysctl.h"
 #define UARTConfigSet(a, b, c)                         \
         UARTConfigSetExpClk(a, SysCtlClockGet(), b, c)
 #define UARTConfigGet(a, b, c)                         \
diff --git a/src/platform/lm3s/driverlib/udma.c b/src/platform/lm3s/driverlib/udma.c
new file mode 100755
index 00000000..03b4f53d
--- /dev/null
+++ b/src/platform/lm3s/driverlib/udma.c
@@ -0,0 +1,1252 @@
+//*****************************************************************************
+//
+// udma.c - Driver for the micro-DMA controller.
+//
+// Copyright (c) 2007-2011 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 7611 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup udma_api
+//! @{
+//
+//*****************************************************************************
+
+#include "inc/hw_sysctl.h"
+#include "inc/hw_types.h"
+#include "inc/hw_udma.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+#include "driverlib/udma.h"
+
+//*****************************************************************************
+//
+//! Enables the uDMA controller for use.
+//!
+//! This function enables the uDMA controller.  The uDMA controller must be
+//! enabled before it can be configured and used.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAEnable(void)
+{
+    //
+    // Set the master enable bit in the config register.
+    //
+    HWREG(UDMA_CFG) = UDMA_CFG_MASTEN;
+}
+
+//*****************************************************************************
+//
+//! Disables the uDMA controller for use.
+//!
+//! This function disables the uDMA controller.  Once disabled, the uDMA
+//! controller will not operate until re-enabled with uDMAEnable().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMADisable(void)
+{
+    //
+    // Clear the master enable bit in the config register.
+    //
+    HWREG(UDMA_CFG) = 0;
+}
+
+//*****************************************************************************
+//
+//! Gets the uDMA error status.
+//!
+//! This function returns the uDMA error status.  It should be called from
+//! within the uDMA error interrupt handler to determine if a uDMA error
+//! occurred.
+//!
+//! \return Returns non-zero if a uDMA error is pending.
+//
+//*****************************************************************************
+unsigned long
+uDMAErrorStatusGet(void)
+{
+    //
+    // Return the uDMA error status.
+    //
+    return(HWREG(UDMA_ERRCLR));
+}
+
+//*****************************************************************************
+//
+//! Clears the uDMA error interrupt.
+//!
+//! This function clears a pending uDMA error interrupt.  It should be called
+//! from within the uDMA error interrupt handler to clear the interrupt.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAErrorStatusClear(void)
+{
+    //
+    // Clear the uDMA error interrupt.
+    //
+    HWREG(UDMA_ERRCLR) = 1;
+}
+
+//*****************************************************************************
+//
+//! Enables a uDMA channel for operation.
+//!
+//! \param ulChannelNum is the channel number to enable.
+//!
+//! This function enables a specific uDMA channel for use.  This function must
+//! be used to enable a channel before it can be used to perform a uDMA
+//! transfer.
+//!
+//! When a uDMA transfer is completed, the channel will be automatically
+//! disabled by the uDMA controller.  Therefore, this function should be called
+//! prior to starting up any new transfer.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAChannelEnable(unsigned long ulChannelNum)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulChannelNum < 32);
+
+    //
+    // Set the bit for this channel in the enable set register.
+    //
+    HWREG(UDMA_ENASET) = 1 << ulChannelNum;
+}
+
+//*****************************************************************************
+//
+//! Disables a uDMA channel for operation.
+//!
+//! \param ulChannelNum is the channel number to disable.
+//!
+//! This function disables a specific uDMA channel.  Once disabled, a channel
+//! will not respond to uDMA transfer requests until re-enabled via
+//! uDMAChannelEnable().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAChannelDisable(unsigned long ulChannelNum)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulChannelNum < 32);
+
+    //
+    // Set the bit for this channel in the enable clear register.
+    //
+    HWREG(UDMA_ENACLR) = 1 << ulChannelNum;
+}
+
+//*****************************************************************************
+//
+//! Checks if a uDMA channel is enabled for operation.
+//!
+//! \param ulChannelNum is the channel number to check.
+//!
+//! This function checks to see if a specific uDMA channel is enabled.  This
+//! can be used to check the status of a transfer, since the channel will
+//! be automatically disabled at the end of a transfer.
+//!
+//! \return Returns \b true if the channel is enabled, \b false if disabled.
+//
+//*****************************************************************************
+tBoolean
+uDMAChannelIsEnabled(unsigned long ulChannelNum)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulChannelNum < 32);
+
+    //
+    // AND the specified channel bit with the enable register, and return the
+    // result.
+    //
+    return((HWREG(UDMA_ENASET) & (1 << ulChannelNum)) ? true : false);
+}
+
+//*****************************************************************************
+//
+//! Sets the base address for the channel control table.
+//!
+//! \param pControlTable is a pointer to the 1024 byte aligned base address
+//! of the uDMA channel control table.
+//!
+//! This function sets the base address of the channel control table.  This
+//! table resides in system memory and holds control information for each uDMA
+//! channel.  The table must be aligned on a 1024 byte boundary.  The base
+//! address must be set before any of the channel functions can be used.
+//!
+//! The size of the channel control table depends on the number of uDMA
+//! channels, and which transfer modes are used.  Refer to the introductory
+//! text and the microcontroller datasheet for more information about the
+//! channel control table.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAControlBaseSet(void *pControlTable)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(((unsigned long)pControlTable & ~0x3FF) ==
+            (unsigned long)pControlTable);
+    ASSERT((unsigned long)pControlTable >= 0x20000000);
+
+    //
+    // Program the base address into the register.
+    //
+    HWREG(UDMA_CTLBASE) = (unsigned long)pControlTable;
+}
+
+//*****************************************************************************
+//
+//! Gets the base address for the channel control table.
+//!
+//! This function gets the base address of the channel control table.  This
+//! table resides in system memory and holds control information for each uDMA
+//! channel.
+//!
+//! \return Returns a pointer to the base address of the channel control table.
+//
+//*****************************************************************************
+void *
+uDMAControlBaseGet(void)
+{
+    //
+    // Read the current value of the control base register, and return it to
+    // the caller.
+    //
+    return((void *)HWREG(UDMA_CTLBASE));
+}
+
+//*****************************************************************************
+//
+//! Gets the base address for the channel control table alternate structures.
+//!
+//! This function gets the base address of the second half of the channel
+//! control table that holds the alternate control structures for each channel.
+//!
+//! \return Returns a pointer to the base address of the second half of the
+//! channel control table.
+//
+//*****************************************************************************
+void *
+uDMAControlAlternateBaseGet(void)
+{
+    //
+    // Read the current value of the control base register, and return it to
+    // the caller.
+    //
+    return((void *)HWREG(UDMA_ALTBASE));
+}
+
+//*****************************************************************************
+//
+//! Requests a uDMA channel to start a transfer.
+//!
+//! \param ulChannelNum is the channel number on which to request a uDMA
+//! transfer.
+//!
+//! This function allows software to request a uDMA channel to begin a
+//! transfer.  This could be used for performing a memory to memory transfer,
+//! or if for some reason a transfer needs to be initiated by software instead
+//! of the peripheral associated with that channel.
+//!
+//! \note If the channel is \b UDMA_CHANNEL_SW and interrupts are used, then
+//! the completion will be signaled on the uDMA dedicated interrupt.  If a
+//! peripheral channel is used, then the completion will be signaled on the
+//! peripheral's interrupt.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAChannelRequest(unsigned long ulChannelNum)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulChannelNum < 32);
+
+    //
+    // Set the bit for this channel in the software uDMA request register.
+    //
+    HWREG(UDMA_SWREQ) = 1 << ulChannelNum;
+}
+
+//*****************************************************************************
+//
+//! Enables attributes of a uDMA channel.
+//!
+//! \param ulChannelNum is the channel to configure.
+//! \param ulAttr is a combination of attributes for the channel.
+//!
+//! This function is used to enable attributes of a uDMA channel.
+//!
+//! The \e ulAttr parameter is the logical OR of any of the following:
+//!
+//! - \b UDMA_ATTR_USEBURST is used to restrict transfers to use only a burst
+//!   mode.
+//! - \b UDMA_ATTR_ALTSELECT is used to select the alternate control structure
+//!   for this channel (it is very unlikely that this flag should be used).
+//! - \b UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority.
+//! - \b UDMA_ATTR_REQMASK is used to mask the hardware request signal from the
+//!   peripheral for this channel.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAChannelAttributeEnable(unsigned long ulChannelNum, unsigned long ulAttr)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulChannelNum < 32);
+    ASSERT((ulAttr & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT |
+                       UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK)) == 0);
+
+    //
+    // Set the useburst bit for this channel if set in ulConfig.
+    //
+    if(ulAttr & UDMA_ATTR_USEBURST)
+    {
+        HWREG(UDMA_USEBURSTSET) = 1 << ulChannelNum;
+    }
+
+    //
+    // Set the alternate control select bit for this channel,
+    // if set in ulConfig.
+    //
+    if(ulAttr & UDMA_ATTR_ALTSELECT)
+    {
+        HWREG(UDMA_ALTSET) = 1 << ulChannelNum;
+    }
+
+    //
+    // Set the high priority bit for this channel, if set in ulConfig.
+    //
+    if(ulAttr & UDMA_ATTR_HIGH_PRIORITY)
+    {
+        HWREG(UDMA_PRIOSET) = 1 << ulChannelNum;
+    }
+
+    //
+    // Set the request mask bit for this channel, if set in ulConfig.
+    //
+    if(ulAttr & UDMA_ATTR_REQMASK)
+    {
+        HWREG(UDMA_REQMASKSET) = 1 << ulChannelNum;
+    }
+}
+
+//*****************************************************************************
+//
+//! Disables attributes of a uDMA channel.
+//!
+//! \param ulChannelNum is the channel to configure.
+//! \param ulAttr is a combination of attributes for the channel.
+//!
+//! This function is used to disable attributes of a uDMA channel.
+//!
+//! The \e ulAttr parameter is the logical OR of any of the following:
+//!
+//! - \b UDMA_ATTR_USEBURST is used to restrict transfers to use only a burst
+//!   mode.
+//! - \b UDMA_ATTR_ALTSELECT is used to select the alternate control structure
+//!   for this channel.
+//! - \b UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority.
+//! - \b UDMA_ATTR_REQMASK is used to mask the hardware request signal from the
+//!   peripheral for this channel.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAChannelAttributeDisable(unsigned long ulChannelNum, unsigned long ulAttr)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulChannelNum < 32);
+    ASSERT((ulAttr & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT |
+                       UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK)) == 0);
+
+    //
+    // Clear the useburst bit for this channel if set in ulConfig.
+    //
+    if(ulAttr & UDMA_ATTR_USEBURST)
+    {
+        HWREG(UDMA_USEBURSTCLR) = 1 << ulChannelNum;
+    }
+
+    //
+    // Clear the alternate control select bit for this channel, if set in
+    // ulConfig.
+    //
+    if(ulAttr & UDMA_ATTR_ALTSELECT)
+    {
+        HWREG(UDMA_ALTCLR) = 1 << ulChannelNum;
+    }
+
+    //
+    // Clear the high priority bit for this channel, if set in ulConfig.
+    //
+    if(ulAttr & UDMA_ATTR_HIGH_PRIORITY)
+    {
+        HWREG(UDMA_PRIOCLR) = 1 << ulChannelNum;
+    }
+
+    //
+    // Clear the request mask bit for this channel, if set in ulConfig.
+    //
+    if(ulAttr & UDMA_ATTR_REQMASK)
+    {
+        HWREG(UDMA_REQMASKCLR) = 1 << ulChannelNum;
+    }
+}
+
+//*****************************************************************************
+//
+//! Gets the enabled attributes of a uDMA channel.
+//!
+//! \param ulChannelNum is the channel to configure.
+//!
+//! This function returns a combination of flags representing the attributes of
+//! the uDMA channel.
+//!
+//! \return Returns the logical OR of the attributes of the uDMA channel, which
+//! can be any of the following:
+//! - \b UDMA_ATTR_USEBURST is used to restrict transfers to use only a burst
+//!   mode.
+//! - \b UDMA_ATTR_ALTSELECT is used to select the alternate control structure
+//!   for this channel.
+//! - \b UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority.
+//! - \b UDMA_ATTR_REQMASK is used to mask the hardware request signal from the
+//!   peripheral for this channel.
+//
+//*****************************************************************************
+unsigned long
+uDMAChannelAttributeGet(unsigned long ulChannelNum)
+{
+    unsigned long ulAttr = 0;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulChannelNum < 32);
+
+    //
+    // Check to see if useburst bit is set for this channel.
+    //
+    if(HWREG(UDMA_USEBURSTSET) & (1 << ulChannelNum))
+    {
+        ulAttr |= UDMA_ATTR_USEBURST;
+    }
+
+    //
+    // Check to see if the alternate control bit is set for this channel.
+    //
+    if(HWREG(UDMA_ALTSET) & (1 << ulChannelNum))
+    {
+        ulAttr |= UDMA_ATTR_ALTSELECT;
+    }
+
+    //
+    // Check to see if the high priority bit is set for this channel.
+    //
+    if(HWREG(UDMA_PRIOSET) & (1 << ulChannelNum))
+    {
+        ulAttr |= UDMA_ATTR_HIGH_PRIORITY;
+    }
+
+    //
+    // Check to see if the request mask bit is set for this channel.
+    //
+    if(HWREG(UDMA_REQMASKSET) & (1 << ulChannelNum))
+    {
+        ulAttr |= UDMA_ATTR_REQMASK;
+    }
+
+    //
+    // Return the configuration flags.
+    //
+    return(ulAttr);
+}
+
+//*****************************************************************************
+//
+//! Sets the control parameters for a uDMA channel control structure.
+//!
+//! \param ulChannelStructIndex is the logical OR of the uDMA channel number
+//! with \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT.
+//! \param ulControl is logical OR of several control values to set the control
+//! parameters for the channel.
+//!
+//! This function is used to set control parameters for a uDMA transfer.  These
+//! are typically parameters that are not changed often.
+//!
+//! The \e ulChannelStructIndex parameter should be the logical OR of the
+//! channel number with one of \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT to
+//! choose whether the primary or alternate data structure is used.
+//!
+//! The \e ulControl parameter is the logical OR of five values: the data size,
+//! the source address increment, the destination address increment, the
+//! arbitration size, and the use burst flag.  The choices available for each
+//! of these values is described below.
+//!
+//! Choose the data size from one of \b UDMA_SIZE_8, \b UDMA_SIZE_16, or
+//! \b UDMA_SIZE_32 to select a data size of 8, 16, or 32 bits.
+//!
+//! Choose the source address increment from one of \b UDMA_SRC_INC_8,
+//! \b UDMA_SRC_INC_16, \b UDMA_SRC_INC_32, or \b UDMA_SRC_INC_NONE to select
+//! an address increment of 8-bit bytes, 16-bit halfwords, 32-bit words, or
+//! to select non-incrementing.
+//!
+//! Choose the destination address increment from one of \b UDMA_DST_INC_8,
+//! \b UDMA_DST_INC_16, \b UDMA_DST_INC_32, or \b UDMA_DST_INC_NONE to select
+//! an address increment of 8-bit bytes, 16-bit halfwords, 32-bit words, or
+//! to select non-incrementing.
+//!
+//! The arbitration size determines how many items are transferred before
+//! the uDMA controller re-arbitrates for the bus.  Choose the arbitration size
+//! from one of \b UDMA_ARB_1, \b UDMA_ARB_2, \b UDMA_ARB_4, \b UDMA_ARB_8,
+//! through \b UDMA_ARB_1024 to select the arbitration size from 1 to 1024
+//! items, in powers of 2.
+//!
+//! The value \b UDMA_NEXT_USEBURST is used to force the channel to only
+//! respond to burst requests at the tail end of a scatter-gather transfer.
+//!
+//! \note The address increment cannot be smaller than the data size.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAChannelControlSet(unsigned long ulChannelStructIndex,
+                      unsigned long ulControl)
+{
+    tDMAControlTable *pCtl;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulChannelStructIndex < 64);
+    ASSERT(HWREG(UDMA_CTLBASE) != 0);
+
+    //
+    // Get the base address of the control table.
+    //
+    pCtl = (tDMAControlTable *)HWREG(UDMA_CTLBASE);
+
+    //
+    // Get the current control word value and mask off the fields to be
+    // changed, then OR in the new settings.
+    //
+    pCtl[ulChannelStructIndex].ulControl =
+        ((pCtl[ulChannelStructIndex].ulControl &
+          ~(UDMA_CHCTL_DSTINC_M |
+            UDMA_CHCTL_DSTSIZE_M |
+            UDMA_CHCTL_SRCINC_M |
+            UDMA_CHCTL_SRCSIZE_M |
+            UDMA_CHCTL_ARBSIZE_M |
+            UDMA_CHCTL_NXTUSEBURST)) |
+         ulControl);
+}
+
+//*****************************************************************************
+//
+//! Sets the transfer parameters for a uDMA channel control structure.
+//!
+//! \param ulChannelStructIndex is the logical OR of the uDMA channel number
+//! with either \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT.
+//! \param ulMode is the type of uDMA transfer.
+//! \param pvSrcAddr is the source address for the transfer.
+//! \param pvDstAddr is the destination address for the transfer.
+//! \param ulTransferSize is the number of data items to transfer.
+//!
+//! This function is used to set the parameters for a uDMA transfer.  These are
+//! typically parameters that are changed often.  The function
+//! uDMAChannelControlSet() MUST be called at least once for this channel prior
+//! to calling this function.
+//!
+//! The \e ulChannelStructIndex parameter should be the logical OR of the
+//! channel number with one of \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT to
+//! choose whether the primary or alternate data structure is used.
+//!
+//! The \e ulMode parameter should be one of the following values:
+//!
+//! - \b UDMA_MODE_STOP stops the uDMA transfer.  The controller sets the mode
+//!   to this value at the end of a transfer.
+//! - \b UDMA_MODE_BASIC to perform a basic transfer based on request.
+//! - \b UDMA_MODE_AUTO to perform a transfer that will always complete once
+//!   started even if request is removed.
+//! - \b UDMA_MODE_PINGPONG to set up a transfer that switches between the
+//!   primary and alternate control structures for the channel.  This allows
+//!   use of ping-pong buffering for uDMA transfers.
+//! - \b UDMA_MODE_MEM_SCATTER_GATHER to set up a memory scatter-gather
+//!   transfer.
+//! - \b UDMA_MODE_PER_SCATTER_GATHER to set up a peripheral scatter-gather
+//!   transfer.
+//!
+//! The \e pvSrcAddr and \e pvDstAddr parameters are pointers to the first
+//! location of the data to be transferred.  These addresses should be aligned
+//! according to the item size.  The compiler will take care of this if the
+//! pointers are pointing to storage of the appropriate data type.
+//!
+//! The \e ulTransferSize parameter is the number of data items, not the number
+//! of bytes.
+//!
+//! The two scatter/gather modes, memory and peripheral, are actually different
+//! depending on whether the primary or alternate control structure is
+//! selected.  This function will look for the \b UDMA_PRI_SELECT and
+//! \b UDMA_ALT_SELECT flag along with the channel number and will set the
+//! scatter/gather mode as appropriate for the primary or alternate control
+//! structure.
+//!
+//! The channel must also be enabled using uDMAChannelEnable() after calling
+//! this function.  The transfer will not begin until the channel has been set
+//! up and enabled.  Note that the channel is automatically disabled after the
+//! transfer is completed, meaning that uDMAChannelEnable() must be called
+//! again after setting up the next transfer.
+//!
+//! \note Great care must be taken to not modify a channel control structure
+//! that is in use or else the results will be unpredictable, including the
+//! possibility of undesired data transfers to or from memory or peripherals.
+//! For BASIC and AUTO modes, it is safe to make changes when the channel is
+//! disabled, or the uDMAChannelModeGet() returns \b UDMA_MODE_STOP.  For
+//! PINGPONG or one of the SCATTER_GATHER modes, it is safe to modify the
+//! primary or alternate control structure only when the other is being used.
+//! The uDMAChannelModeGet() function will return \b UDMA_MODE_STOP when a
+//! channel control structure is inactive and safe to modify.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAChannelTransferSet(unsigned long ulChannelStructIndex,
+                       unsigned long ulMode, void *pvSrcAddr, void *pvDstAddr,
+                       unsigned long ulTransferSize)
+{
+    tDMAControlTable *pControlTable;
+    unsigned long ulControl;
+    unsigned long ulInc;
+    unsigned long ulBufferBytes;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulChannelStructIndex < 64);
+    ASSERT(HWREG(UDMA_CTLBASE) != 0);
+    ASSERT(ulMode <= UDMA_MODE_PER_SCATTER_GATHER);
+    ASSERT((unsigned long)pvSrcAddr >= 0x20000000);
+    ASSERT((unsigned long)pvDstAddr >= 0x20000000);
+    ASSERT((ulTransferSize != 0) && (ulTransferSize <= 1024));
+
+    //
+    // Get the base address of the control table.
+    //
+    pControlTable = (tDMAControlTable *)HWREG(UDMA_CTLBASE);
+
+    //
+    // Get the current control word value and mask off the mode and size
+    // fields.
+    //
+    ulControl = (pControlTable[ulChannelStructIndex].ulControl &
+                 ~(UDMA_CHCTL_XFERSIZE_M | UDMA_CHCTL_XFERMODE_M));
+
+    //
+    // Adjust the mode if the alt control structure is selected.
+    //
+    if(ulChannelStructIndex & UDMA_ALT_SELECT)
+    {
+        if((ulMode == UDMA_MODE_MEM_SCATTER_GATHER) ||
+           (ulMode == UDMA_MODE_PER_SCATTER_GATHER))
+        {
+            ulMode |= UDMA_MODE_ALT_SELECT;
+        }
+    }
+
+    //
+    // Set the transfer size and mode in the control word (but don't write the
+    // control word yet as it could kick off a transfer).
+    //
+    ulControl |= ulMode | ((ulTransferSize - 1) << 4);
+
+    //
+    // Get the address increment value for the source, from the control word.
+    //
+    ulInc = (ulControl & UDMA_CHCTL_SRCINC_M);
+
+    //
+    // Compute the ending source address of the transfer.  If the source
+    // increment is set to none, then the ending address is the same as the
+    // beginning.
+    //
+    if(ulInc != UDMA_SRC_INC_NONE)
+    {
+        ulInc = ulInc >> 26;
+        ulBufferBytes = ulTransferSize << ulInc;
+        pvSrcAddr = (void *)((unsigned long)pvSrcAddr + ulBufferBytes - 1);
+    }
+
+    //
+    // Load the source ending address into the control block.
+    //
+    pControlTable[ulChannelStructIndex].pvSrcEndAddr = pvSrcAddr;
+
+    //
+    // Get the address increment value for the destination, from the control
+    // word.
+    //
+    ulInc = ulControl & UDMA_CHCTL_DSTINC_M;
+
+    //
+    // Compute the ending destination address of the transfer.  If the
+    // destination increment is set to none, then the ending address is the
+    // same as the beginning.
+    //
+    if(ulInc != UDMA_DST_INC_NONE)
+    {
+        //
+        // There is a special case if this is setting up a scatter-gather
+        // transfer.  The destination pointer needs to point to the end of
+        // the alternate structure for this channel instead of calculating
+        // the end of the buffer in the normal way.
+        //
+        if((ulMode == UDMA_MODE_MEM_SCATTER_GATHER) ||
+           (ulMode == UDMA_MODE_PER_SCATTER_GATHER))
+        {
+            pvDstAddr =
+                (void *)&pControlTable[ulChannelStructIndex |
+                                       UDMA_ALT_SELECT].ulSpare;
+        }
+        //
+        // Not a scatter-gather transfer, calculate end pointer normally.
+        //
+        else
+        {
+            ulInc = ulInc >> 30;
+            ulBufferBytes = ulTransferSize << ulInc;
+            pvDstAddr = (void *)((unsigned long)pvDstAddr + ulBufferBytes - 1);
+        }
+    }
+
+    //
+    // Load the destination ending address into the control block.
+    //
+    pControlTable[ulChannelStructIndex].pvDstEndAddr = pvDstAddr;
+
+    //
+    // Write the new control word value.
+    //
+    pControlTable[ulChannelStructIndex].ulControl = ulControl;
+}
+
+//*****************************************************************************
+//
+//! Configures a uDMA channel for scatter-gather mode.
+//!
+//! \param ulChannelNum is the uDMA channel number.
+//! \param ulTaskCount is the number of scatter-gather tasks to execute.
+//! \param pvTaskList is a pointer to the beginning of the scatter-gather
+//! task list.
+//! \param ulIsPeriphSG is a flag to indicate it is a peripheral scatter-gather
+//! transfer (else it will be memory scatter-gather transfer)
+//!
+//! This function is used to configure a channel for scatter-gather mode.
+//! The caller must have already set up a task list, and pass a pointer to
+//! the start of the task list as the \e pvTaskList parameter.  The
+//! \e ulTaskCount parameter is the count of tasks in the task list, not the
+//! size of the task list.  The flag \e bIsPeriphSG should be used to indicate
+//! if the scatter-gather should be configured for a peripheral or memory
+//! scatter-gather operation.
+//!
+//! \sa uDMATaskStructEntry
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAChannelScatterGatherSet(unsigned long ulChannelNum, unsigned ulTaskCount,
+                            void *pvTaskList, unsigned long ulIsPeriphSG)
+{
+    tDMAControlTable *pControlTable;
+    tDMAControlTable *pTaskTable;
+
+    //
+    // Check the parameters
+    //
+    ASSERT(ulChannelNum < 32);
+    ASSERT(HWREG(UDMA_CTLBASE) != 0);
+    ASSERT(pvTaskList != 0);
+    ASSERT(ulTaskCount <= 1024);
+    ASSERT(ulTaskCount != 0);
+
+    //
+    // Get the base address of the control table.
+    //
+    pControlTable = (tDMAControlTable *)HWREG(UDMA_CTLBASE);
+
+    //
+    // Get a handy pointer to the task list
+    //
+    pTaskTable = (tDMAControlTable *)pvTaskList;
+
+    //
+    // Compute the ending address for the source pointer.  This will be the
+    // last element of the last task in the task table
+    //
+    pControlTable[ulChannelNum].pvSrcEndAddr =
+        &pTaskTable[ulTaskCount - 1].ulSpare;
+
+    //
+    // Compute the ending address for the destination pointer.  This will be
+    // the end of the alternate structure for this channel.
+    //
+    pControlTable[ulChannelNum].pvDstEndAddr =
+        &pControlTable[ulChannelNum | UDMA_ALT_SELECT].ulSpare;
+
+    //
+    // Compute the control word.  Most configurable items are fixed for
+    // scatter-gather.  Item and increment sizes are all 32-bit and arb
+    // size must be 4.  The count is the number of items in the task list
+    // times 4 (4 words per task).
+    //
+    pControlTable[ulChannelNum].ulControl =
+        (UDMA_CHCTL_DSTINC_32 | UDMA_CHCTL_DSTSIZE_32 |
+         UDMA_CHCTL_SRCINC_32 | UDMA_CHCTL_SRCSIZE_32 |
+         UDMA_CHCTL_ARBSIZE_4 |
+         (((ulTaskCount * 4) - 1) << UDMA_CHCTL_XFERSIZE_S) |
+         (ulIsPeriphSG ? UDMA_CHCTL_XFERMODE_PER_SG :
+          UDMA_CHCTL_XFERMODE_MEM_SG));
+}
+
+//*****************************************************************************
+//
+//! Gets the current transfer size for a uDMA channel control structure.
+//!
+//! \param ulChannelStructIndex is the logical OR of the uDMA channel number
+//! with either \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT.
+//!
+//! This function is used to get the uDMA transfer size for a channel.  The
+//! transfer size is the number of items to transfer, where the size of an item
+//! might be 8, 16, or 32 bits.  If a partial transfer has already occurred,
+//! then the number of remaining items will be returned.  If the transfer is
+//! complete, then 0 will be returned.
+//!
+//! \return Returns the number of items remaining to transfer.
+//
+//*****************************************************************************
+unsigned long
+uDMAChannelSizeGet(unsigned long ulChannelStructIndex)
+{
+    tDMAControlTable *pControlTable;
+    unsigned long ulControl;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulChannelStructIndex < 64);
+    ASSERT(HWREG(UDMA_CTLBASE) != 0);
+
+    //
+    // Get the base address of the control table.
+    //
+    pControlTable = (tDMAControlTable *)HWREG(UDMA_CTLBASE);
+
+    //
+    // Get the current control word value and mask off all but the size field
+    // and the mode field.
+    //
+    ulControl = (pControlTable[ulChannelStructIndex].ulControl &
+                 (UDMA_CHCTL_XFERSIZE_M | UDMA_CHCTL_XFERMODE_M));
+
+    //
+    // If the size field and mode field are 0 then the transfer is finished
+    // and there are no more items to transfer
+    //
+    if(ulControl == 0)
+    {
+        return(0);
+    }
+
+    //
+    // Otherwise, if either the size field or more field is non-zero, then
+    // not all the items have been transferred.
+    //
+    else
+    {
+        //
+        // Shift the size field and add one, then return to user.
+        //
+        return((ulControl >> 4) + 1);
+    }
+}
+
+//*****************************************************************************
+//
+//! Gets the transfer mode for a uDMA channel control structure.
+//!
+//! \param ulChannelStructIndex is the logical OR of the uDMA channel number
+//! with either \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT.
+//!
+//! This function is used to get the transfer mode for the uDMA channel.  It
+//! can be used to query the status of a transfer on a channel.  When the
+//! transfer is complete the mode will be \b UDMA_MODE_STOP.
+//!
+//! \return Returns the transfer mode of the specified channel and control
+//! structure, which will be one of the following values: \b UDMA_MODE_STOP,
+//! \b UDMA_MODE_BASIC, \b UDMA_MODE_AUTO, \b UDMA_MODE_PINGPONG,
+//! \b UDMA_MODE_MEM_SCATTER_GATHER, or \b UDMA_MODE_PER_SCATTER_GATHER.
+//
+//*****************************************************************************
+unsigned long
+uDMAChannelModeGet(unsigned long ulChannelStructIndex)
+{
+    tDMAControlTable *pControlTable;
+    unsigned long ulControl;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulChannelStructIndex < 64);
+    ASSERT(HWREG(UDMA_CTLBASE) != 0);
+
+    //
+    // Get the base address of the control table.
+    //
+    pControlTable = (tDMAControlTable *)HWREG(UDMA_CTLBASE);
+
+    //
+    // Get the current control word value and mask off all but the mode field.
+    //
+    ulControl = (pControlTable[ulChannelStructIndex].ulControl &
+                 UDMA_CHCTL_XFERMODE_M);
+
+    //
+    // Check if scatter/gather mode, and if so, mask off the alt bit.
+    //
+    if(((ulControl & ~UDMA_MODE_ALT_SELECT) == UDMA_MODE_MEM_SCATTER_GATHER) ||
+       ((ulControl & ~UDMA_MODE_ALT_SELECT) == UDMA_MODE_PER_SCATTER_GATHER))
+    {
+        ulControl &= ~UDMA_MODE_ALT_SELECT;
+    }
+
+    //
+    // Return the mode to the caller.
+    //
+    return(ulControl);
+}
+
+//*****************************************************************************
+//
+//! Selects the secondary peripheral for a set of uDMA channels.
+//!
+//! \param ulSecPeriphs is the logical or of the uDMA channels for which to
+//! use the secondary peripheral, instead of the default peripheral.
+//!
+//! This function is used to select the secondary peripheral assignment for
+//! a set of uDMA channels.  By selecting the secondary peripheral assignment
+//! for a channel, the default peripheral assignment is no longer available
+//! for that channel.
+//!
+//! The parameter \e ulSecPeriphs can be the logical OR of any of the
+//! following macros.  If one of the macros below is in the list passed
+//! to this function, then the secondary peripheral (marked as \b _SEC_)
+//! will be selected.
+//!
+//! - \b UDMA_DEF_USBEP1RX_SEC_UART2RX
+//! - \b UDMA_DEF_USBEP1TX_SEC_UART2TX
+//! - \b UDMA_DEF_USBEP2RX_SEC_TMR3A
+//! - \b UDMA_DEF_USBEP2TX_SEC_TMR3B
+//! - \b UDMA_DEF_USBEP3RX_SEC_TMR2A
+//! - \b UDMA_DEF_USBEP3TX_SEC_TMR2B
+//! - \b UDMA_DEF_ETH0RX_SEC_TMR2A
+//! - \b UDMA_DEF_ETH0TX_SEC_TMR2B
+//! - \b UDMA_DEF_UART0RX_SEC_UART1RX
+//! - \b UDMA_DEF_UART0TX_SEC_UART1TX
+//! - \b UDMA_DEF_SSI0RX_SEC_SSI1RX
+//! - \b UDMA_DEF_SSI0TX_SEC_SSI1TX
+//! - \b UDMA_DEF_RESERVED_SEC_UART2RX
+//! - \b UDMA_DEF_RESERVED_SEC_UART2TX
+//! - \b UDMA_DEF_ADC00_SEC_TMR2A
+//! - \b UDMA_DEF_ADC01_SEC_TMR2B
+//! - \b UDMA_DEF_ADC02_SEC_RESERVED
+//! - \b UDMA_DEF_ADC03_SEC_RESERVED
+//! - \b UDMA_DEF_TMR0A_SEC_TMR1A
+//! - \b UDMA_DEF_TMR0B_SEC_TMR1B
+//! - \b UDMA_DEF_TMR1A_SEC_EPI0RX
+//! - \b UDMA_DEF_TMR1B_SEC_EPI0TX
+//! - \b UDMA_DEF_UART1RX_SEC_RESERVED
+//! - \b UDMA_DEF_UART1TX_SEC_RESERVED
+//! - \b UDMA_DEF_SSI1RX_SEC_ADC10
+//! - \b UDMA_DEF_SSI1TX_SEC_ADC11
+//! - \b UDMA_DEF_RESERVED_SEC_ADC12
+//! - \b UDMA_DEF_RESERVED_SEC_ADC13
+//! - \b UDMA_DEF_I2S0RX_SEC_RESERVED
+//! - \b UDMA_DEF_I2S0TX_SEC_RESERVED
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAChannelSelectSecondary(unsigned long ulSecPeriphs)
+{
+    //
+    // Select the secondary peripheral for the specified channels.
+    //
+    HWREG(UDMA_CHASGN) |= ulSecPeriphs;
+}
+
+//*****************************************************************************
+//
+//! Selects the default peripheral for a set of uDMA channels.
+//!
+//! \param ulDefPeriphs is the logical or of the uDMA channels for which to
+//! use the default peripheral, instead of the secondary peripheral.
+//!
+//! This function is used to select the default peripheral assignment for
+//! a set of uDMA channels.
+//!
+//! The parameter \e ulDefPeriphs can be the logical OR of any of the
+//! following macros.  If one of the macros below is in the list passed
+//! to this function, then the default peripheral (marked as \b _DEF_)
+//! will be selected.
+//!
+//! - \b UDMA_DEF_USBEP1RX_SEC_UART2RX
+//! - \b UDMA_DEF_USBEP1TX_SEC_UART2TX
+//! - \b UDMA_DEF_USBEP2RX_SEC_TMR3A
+//! - \b UDMA_DEF_USBEP2TX_SEC_TMR3B
+//! - \b UDMA_DEF_USBEP3RX_SEC_TMR2A
+//! - \b UDMA_DEF_USBEP3TX_SEC_TMR2B
+//! - \b UDMA_DEF_ETH0RX_SEC_TMR2A
+//! - \b UDMA_DEF_ETH0TX_SEC_TMR2B
+//! - \b UDMA_DEF_UART0RX_SEC_UART1RX
+//! - \b UDMA_DEF_UART0TX_SEC_UART1TX
+//! - \b UDMA_DEF_SSI0RX_SEC_SSI1RX
+//! - \b UDMA_DEF_SSI0TX_SEC_SSI1TX
+//! - \b UDMA_DEF_RESERVED_SEC_UART2RX
+//! - \b UDMA_DEF_RESERVED_SEC_UART2TX
+//! - \b UDMA_DEF_ADC00_SEC_TMR2A
+//! - \b UDMA_DEF_ADC01_SEC_TMR2B
+//! - \b UDMA_DEF_ADC02_SEC_RESERVED
+//! - \b UDMA_DEF_ADC03_SEC_RESERVED
+//! - \b UDMA_DEF_TMR0A_SEC_TMR1A
+//! - \b UDMA_DEF_TMR0B_SEC_TMR1B
+//! - \b UDMA_DEF_TMR1A_SEC_EPI0RX
+//! - \b UDMA_DEF_TMR1B_SEC_EPI0TX
+//! - \b UDMA_DEF_UART1RX_SEC_RESERVED
+//! - \b UDMA_DEF_UART1TX_SEC_RESERVED
+//! - \b UDMA_DEF_SSI1RX_SEC_ADC10
+//! - \b UDMA_DEF_SSI1TX_SEC_ADC11
+//! - \b UDMA_DEF_RESERVED_SEC_ADC12
+//! - \b UDMA_DEF_RESERVED_SEC_ADC13
+//! - \b UDMA_DEF_I2S0RX_SEC_RESERVED
+//! - \b UDMA_DEF_I2S0TX_SEC_RESERVED
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAChannelSelectDefault(unsigned long ulDefPeriphs)
+{
+    //
+    // Select the default peripheral for the specified channels.
+    //
+    HWREG(UDMA_CHASGN) &= ~ulDefPeriphs;
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the uDMA controller.
+//!
+//! \param ulIntChannel identifies which uDMA interrupt is to be registered.
+//! \param pfnHandler is a pointer to the function to be called when the
+//! interrupt is activated.
+//!
+//! This sets and enables the handler to be called when the uDMA controller
+//! generates an interrupt.  The \e ulIntChannel parameter should be one of the
+//! following:
+//!
+//! - \b UDMA_INT_SW to register an interrupt handler to process interrupts
+//!   from the uDMA software channel (UDMA_CHANNEL_SW)
+//! - \b UDMA_INT_ERR to register an interrupt handler to process uDMA error
+//!   interrupts
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \note The interrupt handler for uDMA is for transfer completion when the
+//! channel UDMA_CHANNEL_SW is used, and for error interrupts.  The
+//! interrupts for each peripheral channel are handled through the individual
+//! peripheral interrupt handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAIntRegister(unsigned long ulIntChannel, void (*pfnHandler)(void))
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(pfnHandler);
+    ASSERT((ulIntChannel == UDMA_INT_SW) || (ulIntChannel == UDMA_INT_ERR));
+
+    //
+    // Register the interrupt handler.
+    //
+    IntRegister(ulIntChannel, pfnHandler);
+
+    //
+    // Enable the memory management fault.
+    //
+    IntEnable(ulIntChannel);
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for the uDMA controller.
+//!
+//! \param ulIntChannel identifies which uDMA interrupt to unregister.
+//!
+//! This function will disable and clear the handler to be called for the
+//! specified uDMA interrupt.  The \e ulIntChannel parameter should be one of
+//! \b UDMA_INT_SW or \b UDMA_INT_ERR as documented for the function
+//! uDMAIntRegister().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAIntUnregister(unsigned long ulIntChannel)
+{
+    //
+    // Disable the interrupt.
+    //
+    IntDisable(ulIntChannel);
+
+    //
+    // Unregister the interrupt handler.
+    //
+    IntUnregister(ulIntChannel);
+}
+
+//*****************************************************************************
+//
+//! Gets the uDMA controller channel interrupt status.
+//!
+//! This function is used to get the interrupt status of the uDMA controller.
+//! The returned value is a 32-bit bit mask that indicates which channels are
+//! requesting an interrupt.  This function can be used from within an
+//! interrupt handler to determine or confirm which uDMA channel has requested
+//! an interrupt.
+//!
+//! \note This function is only available on devices that have the DMA Channel
+//! Interrupt Status Register (DMACHIS).  Please consult the data sheet for
+//! your part.
+//!
+//! \return Returns a 32-bit mask which indicates requesting uDMA channels.
+//! There is a bit for each channel, and a 1 in a bit indicates that channel
+//! is requesting an interrupt.  Multiple bits can be set.
+//
+//*****************************************************************************
+unsigned long
+uDMAIntStatus(void)
+{
+    //
+    // Check feature availability
+    //
+    ASSERT(!CLASS_IS_SANDSTORM);
+    ASSERT(!CLASS_IS_FURY);
+    ASSERT(!CLASS_IS_DUSTDEVIL);
+    ASSERT(!CLASS_IS_TEMPEST);
+
+    //
+    // Return the value of the uDMA interrupt status register
+    //
+    return(HWREG(UDMA_CHIS));
+}
+
+//*****************************************************************************
+//
+//! Clears uDMA interrupt status.
+//!
+//! \param ulChanMask is a 32-bit mask with one bit for each uDMA channel.
+//!
+//! Clears bits in the uDMA interrupt status register according to which bits
+//! are set in \e ulChanMask. There is one bit for each channel. If a a bit
+//! is set in \e ulChanMask, then that corresponding channel's interrupt
+//! status will be cleared (if it was set).
+//!
+//! \note This function is only available on devices that have the DMA Channel
+//! Interrupt Status Register (DMACHIS).  Please consult the data sheet for
+//! your part.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAIntClear(unsigned long ulChanMask)
+{
+    //
+    // Check feature availability
+    //
+    ASSERT(!CLASS_IS_SANDSTORM);
+    ASSERT(!CLASS_IS_FURY);
+    ASSERT(!CLASS_IS_DUSTDEVIL);
+    ASSERT(!CLASS_IS_TEMPEST);
+
+    //
+    // Clear the requested bits in the uDMA interrupt status register
+    //
+    HWREG(UDMA_CHIS) = ulChanMask;
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/src/platform/lm3s/driverlib/udma.h b/src/platform/lm3s/driverlib/udma.h
new file mode 100755
index 00000000..b3b83d40
--- /dev/null
+++ b/src/platform/lm3s/driverlib/udma.h
@@ -0,0 +1,444 @@
+//*****************************************************************************
+//
+// udma.h - Prototypes and macros for the uDMA controller.
+//
+// Copyright (c) 2007-2011 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 7611 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __UDMA_H__
+#define __UDMA_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+//! \addtogroup udma_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// A structure that defines an entry in the channel control table.  These
+// fields are used by the uDMA controller and normally it is not necessary for
+// software to directly read or write fields in the table.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    // The ending source address of the data transfer.
+    //
+    volatile void *pvSrcEndAddr;
+
+    //
+    // The ending destination address of the data transfer.
+    //
+    volatile void *pvDstEndAddr;
+
+    //
+    // The channel control mode.
+    //
+    volatile unsigned long ulControl;
+
+    //
+    // An unused location.
+    //
+    volatile unsigned long ulSpare;
+}
+tDMAControlTable;
+
+//*****************************************************************************
+//
+//! A helper macro for building scatter-gather task table entries.
+//!
+//! \param ulTransferCount is the count of items to transfer for this task.
+//! \param ulItemSize is the bit size of the items to transfer for this task.
+//! \param ulSrcIncrement is the bit size increment for source data.
+//! \param pvSrcAddr is the starting address of the data to transfer.
+//! \param ulDstIncrement is the bit size increment for destination data.
+//! \param pvDstAddr is the starting address of the destination data.
+//! \param ulArbSize is the arbitration size to use for the transfer task.
+//! \param ulMode is the transfer mode for this task.
+//!
+//! This macro is intended to be used to help populate a table of uDMA tasks
+//! for a scatter-gather transfer.  This macro will calculate the values for
+//! the fields of a task structure entry based on the input parameters.
+//!
+//! There are specific requirements for the values of each parameter.  No
+//! checking is done so it is up to the caller to ensure that correct values
+//! are used for the parameters.
+//!
+//! The \e ulTransferCount parameter is the number of items that will be
+//! transferred by this task.  It must be in the range 1-1024.
+//!
+//! The \e ulItemSize parameter is the bit size of the transfer data.  It must
+//! be one of \b UDMA_SIZE_8, \b UDMA_SIZE_16, or \b UDMA_SIZE_32.
+//!
+//! The \e ulSrcIncrement parameter is the increment size for the source data.
+//! It must be one of \b UDMA_SRC_INC_8, \b UDMA_SRC_INC_16,
+//! \b UDMA_SRC_INC_32, or \b UDMA_SRC_INC_NONE.
+//!
+//! The \e pvSrcAddr parameter is a void pointer to the beginning of the source
+//! data.
+//!
+//! The \e ulDstIncrement parameter is the increment size for the destination
+//! data.  It must be one of \b UDMA_DST_INC_8, \b UDMA_DST_INC_16,
+//! \b UDMA_DST_INC_32, or \b UDMA_DST_INC_NONE.
+//!
+//! The \e pvDstAddr parameter is a void pointer to the beginning of the
+//! location where the data will be transferred.
+//!
+//! The \e ulArbSize parameter is the arbitration size for the transfer, and
+//! must be one of \b UDMA_ARB_1, \b UDMA_ARB_2, \b UDMA_ARB_4, and so on
+//! up to \b UDMA_ARB_1024.  This is used to select the arbitration size in
+//! powers of 2, from 1 to 1024.
+//!
+//! The \e ulMode parameter is the mode to use for this transfer task.  It
+//! must be one of \b UDMA_MODE_BASIC, \b UDMA_MODE_AUTO,
+//! \b UDMA_MODE_MEM_SCATTER_GATHER, or \b UDMA_MODE_PER_SCATTER_GATHER.  Note
+//! that normally all tasks will be one of the scatter-gather modes while the
+//! last task is a task list will be AUTO or BASIC.
+//!
+//! This macro is intended to be used to initialize individual entries of
+//! a structure of tDMAControlTable type, like this:
+//!
+//! \verbatim
+//!     tDMAControlTable MyTaskList[] =
+//!     {
+//!         uDMATaskStructEntry(Task1Count, UDMA_SIZE_8,
+//!                             UDMA_SRC_INC_8, MySourceBuf,
+//!                             UDMA_DST_INC_8, MyDestBuf,
+//!                             UDMA_ARB_8, UDMA_MODE_MEM_SCATTER_GATHER),
+//!         uDMATaskStructEntry(Task2Count, ... ),
+//!     }
+//! \endverbatim
+//!
+//! \return Nothing; this is not a function.
+//
+//*****************************************************************************
+#define uDMATaskStructEntry(ulTransferCount,                                  \
+                            ulItemSize,                                       \
+                            ulSrcIncrement,                                   \
+                            pvSrcAddr,                                        \
+                            ulDstIncrement,                                   \
+                            pvDstAddr,                                        \
+                            ulArbSize,                                        \
+                            ulMode)                                           \
+    {                                                                         \
+        (((ulSrcIncrement) == UDMA_SRC_INC_NONE) ? (pvSrcAddr) :              \
+            ((void *)(&((unsigned char *)(pvSrcAddr))[((ulTransferCount) <<   \
+                                         ((ulSrcIncrement) >> 26)) - 1]))),   \
+        (((ulDstIncrement) == UDMA_DST_INC_NONE) ? (pvDstAddr) :              \
+            ((void *)(&((unsigned char *)(pvDstAddr))[((ulTransferCount) <<   \
+                                         ((ulDstIncrement) >> 30)) - 1]))),   \
+        (ulSrcIncrement) | (ulDstIncrement) | (ulItemSize) | (ulArbSize) |    \
+        (((ulTransferCount) - 1) << 4) |                                      \
+        ((((ulMode) == UDMA_MODE_MEM_SCATTER_GATHER) ||                       \
+          ((ulMode) == UDMA_MODE_PER_SCATTER_GATHER)) ?                       \
+                (ulMode) | UDMA_MODE_ALT_SELECT : (ulMode)), 0                \
+    }
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Flags that can be passed to uDMAChannelAttributeEnable(),
+// uDMAChannelAttributeDisable(), and returned from uDMAChannelAttributeGet().
+//
+//*****************************************************************************
+#define UDMA_ATTR_USEBURST      0x00000001
+#define UDMA_ATTR_ALTSELECT     0x00000002
+#define UDMA_ATTR_HIGH_PRIORITY 0x00000004
+#define UDMA_ATTR_REQMASK       0x00000008
+#define UDMA_ATTR_ALL           0x0000000F
+
+//*****************************************************************************
+//
+// DMA control modes that can be passed to uDMAModeSet() and returned
+// uDMAModeGet().
+//
+//*****************************************************************************
+#define UDMA_MODE_STOP          0x00000000
+#define UDMA_MODE_BASIC         0x00000001
+#define UDMA_MODE_AUTO          0x00000002
+#define UDMA_MODE_PINGPONG      0x00000003
+#define UDMA_MODE_MEM_SCATTER_GATHER                                          \
+                                0x00000004
+#define UDMA_MODE_PER_SCATTER_GATHER                                          \
+                                0x00000006
+#define UDMA_MODE_ALT_SELECT    0x00000001
+
+//*****************************************************************************
+//
+// Channel configuration values that can be passed to uDMAControlSet().
+//
+//*****************************************************************************
+#define UDMA_DST_INC_8          0x00000000
+#define UDMA_DST_INC_16         0x40000000
+#define UDMA_DST_INC_32         0x80000000
+#define UDMA_DST_INC_NONE       0xc0000000
+#define UDMA_SRC_INC_8          0x00000000
+#define UDMA_SRC_INC_16         0x04000000
+#define UDMA_SRC_INC_32         0x08000000
+#define UDMA_SRC_INC_NONE       0x0c000000
+#define UDMA_SIZE_8             0x00000000
+#define UDMA_SIZE_16            0x11000000
+#define UDMA_SIZE_32            0x22000000
+#define UDMA_ARB_1              0x00000000
+#define UDMA_ARB_2              0x00004000
+#define UDMA_ARB_4              0x00008000
+#define UDMA_ARB_8              0x0000c000
+#define UDMA_ARB_16             0x00010000
+#define UDMA_ARB_32             0x00014000
+#define UDMA_ARB_64             0x00018000
+#define UDMA_ARB_128            0x0001c000
+#define UDMA_ARB_256            0x00020000
+#define UDMA_ARB_512            0x00024000
+#define UDMA_ARB_1024           0x00028000
+#define UDMA_NEXT_USEBURST      0x00000008
+
+//*****************************************************************************
+//
+// Channel numbers to be passed to API functions that require a channel number
+// ID.
+//
+//*****************************************************************************
+#define UDMA_CHANNEL_USBEP1RX   0
+#define UDMA_CHANNEL_USBEP1TX   1
+#define UDMA_CHANNEL_USBEP2RX   2
+#define UDMA_CHANNEL_USBEP2TX   3
+#define UDMA_CHANNEL_USBEP3RX   4
+#define UDMA_CHANNEL_USBEP3TX   5
+#define UDMA_CHANNEL_ETH0RX     6
+#define UDMA_CHANNEL_ETH0TX     7
+#define UDMA_CHANNEL_UART0RX    8
+#define UDMA_CHANNEL_UART0TX    9
+#define UDMA_CHANNEL_SSI0RX     10
+#define UDMA_CHANNEL_SSI0TX     11
+#define UDMA_CHANNEL_ADC0       14
+#define UDMA_CHANNEL_ADC1       15
+#define UDMA_CHANNEL_ADC2       16
+#define UDMA_CHANNEL_ADC3       17
+#define UDMA_CHANNEL_TMR0A      18
+#define UDMA_CHANNEL_TMR0B      19
+#define UDMA_CHANNEL_TMR1A      20
+#define UDMA_CHANNEL_TMR1B      21
+#define UDMA_CHANNEL_UART1RX    22
+#define UDMA_CHANNEL_UART1TX    23
+#define UDMA_CHANNEL_SSI1RX     24
+#define UDMA_CHANNEL_SSI1TX     25
+#define UDMA_CHANNEL_I2S0RX     28
+#define UDMA_CHANNEL_I2S0TX     29
+#define UDMA_CHANNEL_SW         30
+
+//*****************************************************************************
+//
+// Flags to be OR'd with the channel ID to indicate if the primary or alternate
+// control structure should be used.
+//
+//*****************************************************************************
+#define UDMA_PRI_SELECT         0x00000000
+#define UDMA_ALT_SELECT         0x00000020
+
+//*****************************************************************************
+//
+// uDMA interrupt sources, to be passed to uDMAIntRegister() and
+// uDMAIntUnregister().
+//
+//*****************************************************************************
+#define UDMA_INT_SW             62
+#define UDMA_INT_ERR            63
+
+//*****************************************************************************
+//
+// Channel numbers to be passed to API functions that require a channel number
+// ID.  These are for secondary peripheral assignments.
+//
+//*****************************************************************************
+#define UDMA_SEC_CHANNEL_UART2RX_0                                            \
+                                0
+#define UDMA_SEC_CHANNEL_UART2TX_1                                            \
+                                1
+#define UDMA_SEC_CHANNEL_TMR3A  2
+#define UDMA_SEC_CHANNEL_TMR3B  3
+#define UDMA_SEC_CHANNEL_TMR2A_4                                              \
+                                4
+#define UDMA_SEC_CHANNEL_TMR2B_5                                              \
+                                5
+#define UDMA_SEC_CHANNEL_TMR2A_6                                              \
+                                6
+#define UDMA_SEC_CHANNEL_TMR2B_7                                              \
+                                7
+#define UDMA_SEC_CHANNEL_UART1RX                                              \
+                                8
+#define UDMA_SEC_CHANNEL_UART1TX                                              \
+                                9
+#define UDMA_SEC_CHANNEL_SSI1RX 10
+#define UDMA_SEC_CHANNEL_SSI1TX 11
+#define UDMA_SEC_CHANNEL_UART2RX_12                                           \
+                                12
+#define UDMA_SEC_CHANNEL_UART2TX_13                                           \
+                                13
+#define UDMA_SEC_CHANNEL_TMR2A_14                                             \
+                                14
+#define UDMA_SEC_CHANNEL_TMR2B_15                                             \
+                                15
+#define UDMA_SEC_CHANNEL_TMR1A  18
+#define UDMA_SEC_CHANNEL_TMR1B  19
+#define UDMA_SEC_CHANNEL_EPI0RX 20
+#define UDMA_SEC_CHANNEL_EPI0TX 21
+#define UDMA_SEC_CHANNEL_ADC10  24
+#define UDMA_SEC_CHANNEL_ADC11  25
+#define UDMA_SEC_CHANNEL_ADC12  26
+#define UDMA_SEC_CHANNEL_ADC13  27
+#define UDMA_SEC_CHANNEL_SW     30
+
+//*****************************************************************************
+//
+// uDMA default/secondary peripheral selections, to be passed to
+// uDMAChannelSelectSecondary() and uDMAChannelSelectDefault().
+//
+//*****************************************************************************
+#define UDMA_DEF_USBEP1RX_SEC_UART2RX                                         \
+                                0x00000001
+#define UDMA_DEF_USBEP1TX_SEC_UART2TX                                         \
+                                0x00000002
+#define UDMA_DEF_USBEP2RX_SEC_TMR3A                                           \
+                                0x00000004
+#define UDMA_DEF_USBEP2TX_SEC_TMR3B                                           \
+                                0x00000008
+#define UDMA_DEF_USBEP3RX_SEC_TMR2A                                           \
+                                0x00000010
+#define UDMA_DEF_USBEP3TX_SEC_TMR2B                                           \
+                                0x00000020
+#define UDMA_DEF_ETH0RX_SEC_TMR2A                                             \
+                                0x00000040
+#define UDMA_DEF_ETH0TX_SEC_TMR2B                                             \
+                                0x00000080
+#define UDMA_DEF_UART0RX_SEC_UART1RX                                          \
+                                0x00000100
+#define UDMA_DEF_UART0TX_SEC_UART1TX                                          \
+                                0x00000200
+#define UDMA_DEF_SSI0RX_SEC_SSI1RX                                            \
+                                0x00000400
+#define UDMA_DEF_SSI0TX_SEC_SSI1TX                                            \
+                                0x00000800
+#define UDMA_DEF_RESERVED_SEC_UART2RX                                         \
+                                0x00001000
+#define UDMA_DEF_RESERVED_SEC_UART2TX                                         \
+                                0x00002000
+#define UDMA_DEF_ADC00_SEC_TMR2A                                              \
+                                0x00004000
+#define UDMA_DEF_ADC01_SEC_TMR2B                                              \
+                                0x00008000
+#define UDMA_DEF_ADC02_SEC_RESERVED                                           \
+                                0x00010000
+#define UDMA_DEF_ADC03_SEC_RESERVED                                           \
+                                0x00020000
+#define UDMA_DEF_TMR0A_SEC_TMR1A                                              \
+                                0x00040000
+#define UDMA_DEF_TMR0B_SEC_TMR1B                                              \
+                                0x00080000
+#define UDMA_DEF_TMR1A_SEC_EPI0RX                                             \
+                                0x00100000
+#define UDMA_DEF_TMR1B_SEC_EPI0TX                                             \
+                                0x00200000
+#define UDMA_DEF_UART1RX_SEC_RESERVED                                         \
+                                0x00400000
+#define UDMA_DEF_UART1TX_SEC_RESERVED                                         \
+                                0x00800000
+#define UDMA_DEF_SSI1RX_SEC_ADC10                                             \
+                                0x01000000
+#define UDMA_DEF_SSI1TX_SEC_ADC11                                             \
+                                0x02000000
+#define UDMA_DEF_RESERVED_SEC_ADC12                                           \
+                                0x04000000
+#define UDMA_DEF_RESERVED_SEC_ADC13                                           \
+                                0x08000000
+#define UDMA_DEF_I2S0RX_SEC_RESERVED                                          \
+                                0x10000000
+#define UDMA_DEF_I2S0TX_SEC_RESERVED                                          \
+                                0x20000000
+
+//*****************************************************************************
+//
+// API Function prototypes
+//
+//*****************************************************************************
+extern void uDMAEnable(void);
+extern void uDMADisable(void);
+extern unsigned long uDMAErrorStatusGet(void);
+extern void uDMAErrorStatusClear(void);
+extern void uDMAChannelEnable(unsigned long ulChannelNum);
+extern void uDMAChannelDisable(unsigned long ulChannelNum);
+extern tBoolean uDMAChannelIsEnabled(unsigned long ulChannelNum);
+extern void uDMAControlBaseSet(void *pControlTable);
+extern void *uDMAControlBaseGet(void);
+extern void *uDMAControlAlternateBaseGet(void);
+extern void uDMAChannelRequest(unsigned long ulChannelNum);
+extern void uDMAChannelAttributeEnable(unsigned long ulChannelNum,
+                                       unsigned long ulAttr);
+extern void uDMAChannelAttributeDisable(unsigned long ulChannelNum,
+                                        unsigned long ulAttr);
+extern unsigned long uDMAChannelAttributeGet(unsigned long ulChannelNum);
+extern void uDMAChannelControlSet(unsigned long ulChannelStructIndex,
+                                  unsigned long ulControl);
+extern void uDMAChannelTransferSet(unsigned long ulChannelStructIndex,
+                                   unsigned long ulMode, void *pvSrcAddr,
+                                   void *pvDstAddr,
+                                   unsigned long ulTransferSize);
+extern void uDMAChannelScatterGatherSet(unsigned long ulChannelNum,
+                                        unsigned ulTaskCount, void *pvTaskList,
+                                        unsigned long ulIsPeriphSG);
+extern unsigned long uDMAChannelSizeGet(unsigned long ulChannelStructIndex);
+extern unsigned long uDMAChannelModeGet(unsigned long ulChannelStructIndex);
+extern void uDMAIntRegister(unsigned long ulIntChannel,
+                            void (*pfnHandler)(void));
+extern void uDMAIntUnregister(unsigned long ulIntChannel);
+extern void uDMAChannelSelectDefault(unsigned long ulDefPeriphs);
+extern void uDMAChannelSelectSecondary(unsigned long ulSecPeriphs);
+extern unsigned long uDMAIntStatus(void);
+extern void uDMAIntClear(unsigned long ulChanMask);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif //  __UDMA_H__
diff --git a/src/platform/lm3s/driverlib/usb.c b/src/platform/lm3s/driverlib/usb.c
new file mode 100755
index 00000000..d68b45b2
--- /dev/null
+++ b/src/platform/lm3s/driverlib/usb.c
@@ -0,0 +1,3893 @@
+//*****************************************************************************
+//
+// usb.c - Driver for the USB Interface.
+//
+// Copyright (c) 2007-2011 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 7611 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup usb_api
+//! @{
+//
+//*****************************************************************************
+
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_types.h"
+#include "inc/hw_usb.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+#include "driverlib/udma.h"
+#include "driverlib/usb.h"
+
+//*****************************************************************************
+//
+// Amount to shift the RX interrupt sources by in the flags used in the
+// interrupt calls.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+#define USB_INT_RX_SHIFT        8
+#endif
+#define USB_INTEP_RX_SHIFT      16
+
+//*****************************************************************************
+//
+// Amount to shift the status interrupt sources by in the flags used in the
+// interrupt calls.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+#define USB_INT_STATUS_SHIFT    24
+#endif
+
+//*****************************************************************************
+//
+// Amount to shift the RX endpoint status sources by in the flags used in the
+// calls.
+//
+//*****************************************************************************
+#define USB_RX_EPSTATUS_SHIFT   16
+
+//*****************************************************************************
+//
+// Converts from an endpoint specifier to the offset of the endpoint's
+// control/status registers.
+//
+//*****************************************************************************
+#define EP_OFFSET(Endpoint)     (Endpoint - 0x10)
+
+//*****************************************************************************
+//
+// Sets one of the indexed registers.
+//
+// \param ulBase specifies the USB module base address.
+// \param ulEndpoint is the endpoint index to target for this write.
+// \param ulIndexedReg is the indexed register to write to.
+// \param ucValue is the value to write to the register.
+//
+// This function is used to access the indexed registers for each endpoint.
+// The only registers that are indexed are the FIFO configuration registers
+// which are not used after configuration.
+//
+// \return None.
+//
+//*****************************************************************************
+static void
+USBIndexWrite(unsigned long ulBase, unsigned long ulEndpoint,
+              unsigned long ulIndexedReg, unsigned long ulValue,
+              unsigned long ulSize)
+{
+    unsigned long ulIndex;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulBase == USB0_BASE);
+    ASSERT((ulEndpoint == 0) || (ulEndpoint == 1) || (ulEndpoint == 2) ||
+           (ulEndpoint == 3));
+    ASSERT((ulSize == 1) || (ulSize == 2));
+
+    //
+    // Save the old index in case it was in use.
+    //
+    ulIndex = HWREGB(ulBase + USB_O_EPIDX);
+
+    //
+    // Set the index.
+    //
+    HWREGB(ulBase + USB_O_EPIDX) = ulEndpoint;
+
+    //
+    // Determine the size of the register value.
+    //
+    if(ulSize == 1)
+    {
+        //
+        // Set the value.
+        //
+        HWREGB(ulBase + ulIndexedReg) = ulValue;
+    }
+    else
+    {
+        //
+        // Set the value.
+        //
+        HWREGH(ulBase + ulIndexedReg) = ulValue;
+    }
+
+    //
+    // Restore the old index in case it was in use.
+    //
+    HWREGB(ulBase + USB_O_EPIDX) = ulIndex;
+}
+
+//*****************************************************************************
+//
+// Reads one of the indexed registers.
+//
+// \param ulBase specifies the USB module base address.
+// \param ulEndpoint is the endpoint index to target for this write.
+// \param ulIndexedReg is the indexed register to write to.
+//
+// This function is used internally to access the indexed registers for each
+// endpoint.  The only registers that are indexed are the FIFO configuration
+// registers which are not used after configuration.
+//
+// \return The value in the register requested.
+//
+//*****************************************************************************
+static unsigned long
+USBIndexRead(unsigned long ulBase, unsigned long ulEndpoint,
+             unsigned long ulIndexedReg, unsigned long ulSize)
+{
+    unsigned char ulIndex;
+    unsigned char ulValue;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulBase == USB0_BASE);
+    ASSERT((ulEndpoint == 0) || (ulEndpoint == 1) || (ulEndpoint == 2) ||
+           (ulEndpoint == 3));
+    ASSERT((ulSize == 1) || (ulSize == 2));
+
+    //
+    // Save the old index in case it was in use.
+    //
+    ulIndex = HWREGB(ulBase + USB_O_EPIDX);
+
+    //
+    // Set the index.
+    //
+    HWREGB(ulBase + USB_O_EPIDX) = ulEndpoint;
+
+    //
+    // Determine the size of the register value.
+    //
+    if(ulSize == 1)
+    {
+        //
+        // Get the value.
+        //
+        ulValue = HWREGB(ulBase + ulIndexedReg);
+    }
+    else
+    {
+        //
+        // Get the value.
+        //
+        ulValue = HWREGH(ulBase + ulIndexedReg);
+    }
+
+    //
+    // Restore the old index in case it was in use.
+    //
+    HWREGB(ulBase + USB_O_EPIDX) = ulIndex;
+
+    //
+    // Return the register's value.
+    //
+    return(ulValue);
+}
+
+//*****************************************************************************
+//
+//! Puts the USB bus in a suspended state.
+//!
+//! \param ulBase specifies the USB module base address.
+//!
+//! When used in host mode, this function will put the USB bus in the suspended
+//! state.
+//!
+//! \note This function should only be called in host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostSuspend(unsigned long ulBase)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulBase == USB0_BASE);
+
+    //
+    // Send the suspend signaling to the USB bus.
+    //
+    HWREGB(ulBase + USB_O_POWER) |= USB_POWER_SUSPEND;
+}
+
+//*****************************************************************************
+//
+//! Handles the USB bus reset condition.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param bStart specifies whether to start or stop signaling reset on the USB
+//! bus.
+//!
+//! When this function is called with the \e bStart parameter set to \b true,
+//! this function will cause the start of a reset condition on the USB bus.
+//! The caller should then delay at least 20ms before calling this function
+//! again with the \e bStart parameter set to \b false.
+//!
+//! \note This function should only be called in host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostReset(unsigned long ulBase, tBoolean bStart)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulBase == USB0_BASE);
+
+    //
+    // Send a reset signal to the bus.
+    //
+    if(bStart)
+    {
+        HWREGB(ulBase + USB_O_POWER) |= USB_POWER_RESET;
+    }
+    else
+    {
+        HWREGB(ulBase + USB_O_POWER) &= ~USB_POWER_RESET;
+    }
+}
+
+//*****************************************************************************
+//
+//! Handles the USB bus resume condition.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param bStart specifies if the USB controller is entering or leaving the
+//! resume signaling state.
+//!
+//! When in device mode this function will bring the USB controller out of the
+//! suspend state.  This call should first be made with the \e bStart parameter
+//! set to \b true to start resume signaling.  The device application should
+//! then delay at least 10ms but not more than 15ms before calling this
+//! function with the \e bStart parameter set to \b false.
+//!
+//! When in host mode this function will signal devices to leave the suspend
+//! state.  This call should first be made with the \e bStart parameter set to
+//! \b true to start resume signaling.  The host application should then delay
+//! at least 20ms before calling this function with the \e bStart parameter set
+//! to \b false.  This will cause the controller to complete the resume
+//! signaling on the USB bus.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostResume(unsigned long ulBase, tBoolean bStart)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulBase == USB0_BASE);
+
+    //
+    // Send a resume signal to the bus.
+    //
+    if(bStart)
+    {
+        HWREGB(ulBase + USB_O_POWER) |= USB_POWER_RESUME;
+    }
+    else
+    {
+        HWREGB(ulBase + USB_O_POWER) &= ~USB_POWER_RESUME;
+    }
+}
+
+//*****************************************************************************
+//
+//! Returns the current speed of the USB device connected.
+//!
+//! \param ulBase specifies the USB module base address.
+//!
+//! This function will return the current speed of the USB bus.
+//!
+//! \note This function should only be called in host mode.
+//!
+//! \return Returns either \b USB_LOW_SPEED, \b USB_FULL_SPEED, or
+//! \b USB_UNDEF_SPEED.
+//
+//*****************************************************************************
+unsigned long
+USBHostSpeedGet(unsigned long ulBase)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulBase == USB0_BASE);
+
+    //
+    // If the Full Speed device bit is set, then this is a full speed device.
+    //
+    if(HWREGB(ulBase + USB_O_DEVCTL) & USB_DEVCTL_FSDEV)
+    {
+        return(USB_FULL_SPEED);
+    }
+
+    //
+    // If the Low Speed device bit is set, then this is a low speed device.
+    //
+    if(HWREGB(ulBase + USB_O_DEVCTL) & USB_DEVCTL_LSDEV)
+    {
+        return(USB_LOW_SPEED);
+    }
+
+    //
+    // The device speed is not known.
+    //
+    return(USB_UNDEF_SPEED);
+}
+
+//*****************************************************************************
+//
+//! Returns the status of the USB interrupts.
+//!
+//! \param ulBase specifies the USB module base address.
+//!
+//! This function will read the source of the interrupt for the USB controller.
+//! There are three groups of interrupt sources, IN Endpoints, OUT Endpoints,
+//! and general status changes.  This call will return the current status for
+//! all of these interrupts.  The bit values returned should be compared
+//! against the \b USB_HOST_IN, \b USB_HOST_OUT, \b USB_HOST_EP0,
+//! \b USB_DEV_IN, \b USB_DEV_OUT, and \b USB_DEV_EP0 values.
+//!
+//! \note This call will clear the source of all of the general status
+//! interrupts.
+//!
+//! \note WARNING: This API cannot be used on endpoint numbers greater than
+//! endpoint 3 so USBIntStatusControl() or USBIntStatusEndpoint() should be
+//! used instead.
+//!
+//! \return Returns the status of the sources for the USB controller's
+//! interrupt.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+unsigned long
+USBIntStatus(unsigned long ulBase)
+{
+    unsigned long ulStatus;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulBase == USB0_BASE);
+
+    //
+    // Get the transmit interrupt status.
+    //
+    ulStatus = (HWREGB(ulBase + USB_O_TXIS));
+
+    //
+    // Get the receive interrupt status, these bits go into the second byte of
+    // the returned value.
+    //
+    ulStatus |= (HWREGB(ulBase + USB_O_RXIS) << USB_INT_RX_SHIFT);
+
+    //
+    // Get the general interrupt status, these bits go into the upper 8 bits
+    // of the returned value.
+    //
+    ulStatus |= (HWREGB(ulBase + USB_O_IS) << USB_INT_STATUS_SHIFT);
+
+    //
+    // Add the power fault status.
+    //
+    if(HWREG(ulBase + USB_O_EPCISC) & USB_EPCISC_PF)
+    {
+        //
+        // Indicate a power fault was detected.
+        //
+        ulStatus |= USB_INT_POWER_FAULT;
+
+        //
+        // Clear the power fault interrupt.
+        //
+        HWREGB(ulBase + USB_O_EPCISC) |= USB_EPCISC_PF;
+    }
+
+    if(HWREG(USB0_BASE + USB_O_IDVISC) & USB_IDVRIS_ID)
+    {
+        //
+        // Indicate a id detection was detected.
+        //
+        ulStatus |= USB_INT_MODE_DETECT;
+
+        //
+        // Clear the id detection interrupt.
+        //
+        HWREG(USB0_BASE + USB_O_IDVISC) |= USB_IDVRIS_ID;
+    }
+
+    //
+    // Return the combined interrupt status.
+    //
+    return(ulStatus);
+}
+#endif
+
+//*****************************************************************************
+//
+//! Disables the sources for USB interrupts.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulFlags specifies which interrupts to disable.
+//!
+//! This function will disable the USB controller from generating the
+//! interrupts indicated by the \e ulFlags parameter.  There are three groups
+//! of interrupt sources, IN Endpoints, OUT Endpoints, and general status
+//! changes, specified by \b USB_INT_HOST_IN, \b USB_INT_HOST_OUT,
+//! \b USB_INT_DEV_IN, \b USB_INT_DEV_OUT, and \b USB_INT_STATUS.  If
+//! \b USB_INT_ALL is specified then all interrupts will be disabled.
+//!
+//! \note WARNING: This API cannot be used on endpoint numbers greater than
+//! endpoint 3 so USBIntDisableControl() or USBIntDisableEndpoint() should be
+//! used instead.
+//!
+//! \return None.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+void
+USBIntDisable(unsigned long ulBase, unsigned long ulFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulBase == USB0_BASE);
+    ASSERT((ulFlags & ~(USB_INT_ALL)) == 0);
+
+    //
+    // If any transmit interrupts were disabled then write the transmit
+    // interrupt settings out to the hardware.
+    //
+    if(ulFlags & (USB_INT_HOST_OUT | USB_INT_DEV_IN | USB_INT_EP0))
+    {
+        HWREGH(ulBase + USB_O_TXIE) &=
+            ~(ulFlags & (USB_INT_HOST_OUT | USB_INT_DEV_IN | USB_INT_EP0));
+    }
+
+    //
+    // If any receive interrupts were disabled then write the receive interrupt
+    // settings out to the hardware.
+    //
+    if(ulFlags & (USB_INT_HOST_IN | USB_INT_DEV_OUT))
+    {
+        HWREGH(ulBase + USB_O_RXIE) &=
+            ~((ulFlags & (USB_INT_HOST_IN | USB_INT_DEV_OUT)) >>
+              USB_INT_RX_SHIFT);
+    }
+
+    //
+    // If any general interrupts were disabled then write the general interrupt
+    // settings out to the hardware.
+    //
+    if(ulFlags & USB_INT_STATUS)
+    {
+        HWREGB(ulBase + USB_O_IE) &=
+            ~((ulFlags & USB_INT_STATUS) >> USB_INT_STATUS_SHIFT);
+    }
+
+    //
+    // Disable the power fault interrupt.
+    //
+    if(ulFlags & USB_INT_POWER_FAULT)
+    {
+        HWREG(ulBase + USB_O_EPCIM) = 0;
+    }
+
+    //
+    // Disable the ID pin detect interrupt.
+    //
+    if(ulFlags & USB_INT_MODE_DETECT)
+    {
+        HWREG(USB0_BASE + USB_O_IDVIM) = 0;
+    }
+}
+#endif
+
+//*****************************************************************************
+//
+//! Enables the sources for USB interrupts.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulFlags specifies which interrupts to enable.
+//!
+//! This function will enable the USB controller's ability to generate the
+//! interrupts indicated by the \e ulFlags parameter.  There are three
+//! groups of interrupt sources, IN Endpoints, OUT Endpoints, and
+//! general status changes, specified by \b USB_INT_HOST_IN,
+//! \b USB_INT_HOST_OUT, \b USB_INT_DEV_IN, \b USB_INT_DEV_OUT, and
+//! \b USB_STATUS.  If \b USB_INT_ALL is specified then all interrupts will be
+//! enabled.
+//!
+//! \note A call must be made to enable the interrupt in the main interrupt
+//! controller to receive interrupts.  The USBIntRegister() API performs this
+//! controller level interrupt enable.  However if static interrupt handlers
+//! are used then then a call to IntEnable() must be made in order to allow any
+//! USB interrupts to occur.
+//!
+//! \note WARNING: This API cannot be used on endpoint numbers greater than
+//! endpoint 3 so USBIntEnableControl() or USBIntEnableEndpoint() should be
+//! used instead.
+//!
+//! \return None.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+void
+USBIntEnable(unsigned long ulBase, unsigned long ulFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulBase == USB0_BASE);
+    ASSERT((ulFlags & (~USB_INT_ALL)) == 0);
+
+    //
+    // If any transmit interrupts were enabled then write the transmit
+    // interrupt settings out to the hardware.
+    //
+    if(ulFlags & (USB_INT_HOST_OUT | USB_INT_DEV_IN | USB_INT_EP0))
+    {
+        HWREGH(ulBase + USB_O_TXIE) |=
+            ulFlags & (USB_INT_HOST_OUT | USB_INT_DEV_IN | USB_INT_EP0);
+    }
+
+    //
+    // If any receive interrupts were enabled then write the receive interrupt
+    // settings out to the hardware.
+    //
+    if(ulFlags & (USB_INT_HOST_IN | USB_INT_DEV_OUT))
+    {
+        HWREGH(ulBase + USB_O_RXIE) |=
+            ((ulFlags & (USB_INT_HOST_IN | USB_INT_DEV_OUT)) >>
+             USB_INT_RX_SHIFT);
+    }
+
+    //
+    // If any general interrupts were enabled then write the general interrupt
+    // settings out to the hardware.
+    //
+    if(ulFlags & USB_INT_STATUS)
+    {
+        HWREGB(ulBase + USB_O_IE) |=
+            (ulFlags & USB_INT_STATUS) >> USB_INT_STATUS_SHIFT;
+    }
+
+    //
+    // Enable the power fault interrupt.
+    //
+    if(ulFlags & USB_INT_POWER_FAULT)
+    {
+        HWREG(ulBase + USB_O_EPCIM) = USB_EPCIM_PF;
+    }
+
+    //
+    // Enable the ID pin detect interrupt.
+    //
+    if(ulFlags & USB_INT_MODE_DETECT)
+    {
+        HWREG(USB0_BASE + USB_O_IDVIM) = USB_IDVIM_ID;
+    }
+}
+#endif
+
+//*****************************************************************************
+//
+//! Disables control interrupts on a given USB controller.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulFlags specifies which control interrupts to disable.
+//!
+//! This function will disable the control interrupts for the USB controller
+//! specified by the \e ulBase parameter.  The \e ulFlags parameter specifies
+//! which control interrupts to disable.  The flags passed in the \e ulFlags
+//! parameters should be the definitions that start with \b USB_INTCTRL_* and
+//! not any other \b USB_INT flags.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBIntDisableControl(unsigned long ulBase, unsigned long ulFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulBase == USB0_BASE);
+    ASSERT((ulFlags & ~(USB_INTCTRL_ALL)) == 0);
+
+    //
+    // If any general interrupts were disabled then write the general interrupt
+    // settings out to the hardware.
+    //
+    if(ulFlags & USB_INTCTRL_STATUS)
+    {
+        HWREGB(ulBase + USB_O_IE) &= ~(ulFlags & USB_INTCTRL_STATUS);
+    }
+
+    //
+    // Disable the power fault interrupt.
+    //
+    if(ulFlags & USB_INTCTRL_POWER_FAULT)
+    {
+        HWREG(ulBase + USB_O_EPCIM) = 0;
+    }
+
+    //
+    // Disable the ID pin detect interrupt.
+    //
+    if(ulFlags & USB_INTCTRL_MODE_DETECT)
+    {
+        HWREG(USB0_BASE + USB_O_IDVIM) = 0;
+    }
+}
+
+//*****************************************************************************
+//
+//! Enables control interrupts on a given USB controller.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulFlags specifies which control interrupts to enable.
+//!
+//! This function will enable the control interrupts for the USB controller
+//! specified by the \e ulBase parameter.  The \e ulFlags parameter specifies
+//! which control interrupts to enable.  The flags passed in the \e ulFlags
+//! parameters should be the definitions that start with \b USB_INTCTRL_* and
+//! not any other \b USB_INT flags.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBIntEnableControl(unsigned long ulBase, unsigned long ulFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulBase == USB0_BASE);
+    ASSERT((ulFlags & (~USB_INTCTRL_ALL)) == 0);
+
+    //
+    // If any general interrupts were enabled then write the general interrupt
+    // settings out to the hardware.
+    //
+    if(ulFlags & USB_INTCTRL_STATUS)
+    {
+        HWREGB(ulBase + USB_O_IE) |= ulFlags;
+    }
+
+    //
+    // Enable the power fault interrupt.
+    //
+    if(ulFlags & USB_INTCTRL_POWER_FAULT)
+    {
+        HWREG(ulBase + USB_O_EPCIM) = USB_EPCIM_PF;
+    }
+
+    //
+    // Enable the ID pin detect interrupt.
+    //
+    if(ulFlags & USB_INTCTRL_MODE_DETECT)
+    {
+        HWREG(USB0_BASE + USB_O_IDVIM) = USB_IDVIM_ID;
+    }
+}
+
+//*****************************************************************************
+//
+//! Returns the control interrupt status on a given USB controller.
+//!
+//! \param ulBase specifies the USB module base address.
+//!
+//! This function will read control interrupt status for a USB controller.
+//! This call will return the current status for control interrupts only, the
+//! endpoint interrupt status is retrieved by calling USBIntStatusEndpoint().
+//! The bit values returned should be compared against the \b USB_INTCTRL_*
+//! values.
+//!
+//! The following are the meanings of all \b USB_INCTRL_ flags and the modes
+//! for which they are valid.  These values apply to any calls to
+//! USBIntStatusControl(), USBIntEnableControl(), and USBIntDisableControl().
+//! Some of these flags are only valid in the following modes as indicated in
+//! the parenthesis:  Host, Device, and OTG.
+//!
+//! - \b USB_INTCTRL_ALL - A full mask of all control interrupt sources.
+//! - \b USB_INTCTRL_VBUS_ERR - A VBUS error has occurred (Host Only).
+//! - \b USB_INTCTRL_SESSION - Session Start Detected on A-side of cable
+//!                            (OTG Only).
+//! - \b USB_INTCTRL_SESSION_END - Session End Detected (Device Only)
+//! - \b USB_INTCTRL_DISCONNECT - Device Disconnect Detected (Host Only)
+//! - \b USB_INTCTRL_CONNECT - Device Connect Detected (Host Only)
+//! - \b USB_INTCTRL_SOF - Start of Frame Detected.
+//! - \b USB_INTCTRL_BABBLE - USB controller detected a device signaling past
+//!                           the end of a frame. (Host Only)
+//! - \b USB_INTCTRL_RESET - Reset signaling detected by device. (Device Only)
+//! - \b USB_INTCTRL_RESUME - Resume signaling detected.
+//! - \b USB_INTCTRL_SUSPEND - Suspend signaling detected by device (Device
+//!                            Only)
+//! - \b USB_INTCTRL_MODE_DETECT - OTG cable mode detection has completed
+//!                                (OTG Only)
+//! - \b USB_INTCTRL_POWER_FAULT - Power Fault detected. (Host Only)
+//!
+//! \note This call will clear the source of all of the control status
+//! interrupts.
+//!
+//! \return Returns the status of the control interrupts for a USB controller.
+//
+//*****************************************************************************
+unsigned long
+USBIntStatusControl(unsigned long ulBase)
+{
+    unsigned long ulStatus;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulBase == USB0_BASE);
+
+    //
+    // Get the general interrupt status, these bits go into the upper 8 bits
+    // of the returned value.
+    //
+    ulStatus = HWREGB(ulBase + USB_O_IS);
+
+    //
+    // Add the power fault status.
+    //
+    if(HWREG(ulBase + USB_O_EPCISC) & USB_EPCISC_PF)
+    {
+        //
+        // Indicate a power fault was detected.
+        //
+        ulStatus |= USB_INTCTRL_POWER_FAULT;
+
+        //
+        // Clear the power fault interrupt.
+        //
+        HWREGB(ulBase + USB_O_EPCISC) |= USB_EPCISC_PF;
+    }
+
+    if(HWREG(USB0_BASE + USB_O_IDVISC) & USB_IDVRIS_ID)
+    {
+        //
+        // Indicate a id detection was detected.
+        //
+        ulStatus |= USB_INTCTRL_MODE_DETECT;
+
+        //
+        // Clear the id detection interrupt.
+        //
+        HWREG(USB0_BASE + USB_O_IDVISC) |= USB_IDVRIS_ID;
+    }
+
+    //
+    // Return the combined interrupt status.
+    //
+    return(ulStatus);
+}
+
+//*****************************************************************************
+//
+//! Disables endpoint interrupts on a given USB controller.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulFlags specifies which endpoint interrupts to disable.
+//!
+//! This function will disable endpoint interrupts for the USB controller
+//! specified by the \e ulBase parameter.  The \e ulFlags parameter specifies
+//! which endpoint interrupts to disable.  The flags passed in the \e ulFlags
+//! parameters should be the definitions that start with \b USB_INTEP_* and not
+//! any other \b USB_INT flags.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBIntDisableEndpoint(unsigned long ulBase, unsigned long ulFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulBase == USB0_BASE);
+
+    //
+    // If any transmit interrupts were disabled then write the transmit
+    // interrupt settings out to the hardware.
+    //
+    HWREGH(ulBase + USB_O_TXIE) &=
+        ~(ulFlags & (USB_INTEP_HOST_OUT | USB_INTEP_DEV_IN | USB_INTEP_0));
+
+    //
+    // If any receive interrupts were disabled then write the receive interrupt
+    // settings out to the hardware.
+    //
+    HWREGH(ulBase + USB_O_RXIE) &=
+        ~((ulFlags & (USB_INTEP_HOST_IN | USB_INTEP_DEV_OUT)) >>
+          USB_INTEP_RX_SHIFT);
+}
+
+//*****************************************************************************
+//
+//! Enables endpoint interrupts on a given USB controller.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulFlags specifies which endpoint interrupts to enable.
+//!
+//! This function will enable endpoint interrupts for the USB controller
+//! specified by the \e ulBase parameter.  The \e ulFlags parameter specifies
+//! which endpoint interrupts to enable.  The flags passed in the \e ulFlags
+//! parameters should be the definitions that start with \b USB_INTEP_* and not
+//! any other \b USB_INT flags.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBIntEnableEndpoint(unsigned long ulBase, unsigned long ulFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulBase == USB0_BASE);
+
+    //
+    // Enable any transmit endpoint interrupts.
+    //
+    HWREGH(ulBase + USB_O_TXIE) |=
+           ulFlags & (USB_INTEP_HOST_OUT | USB_INTEP_DEV_IN | USB_INTEP_0);
+
+    //
+    // Enable any receive endpoint interrupts.
+    //
+    HWREGH(ulBase + USB_O_RXIE) |=
+        ((ulFlags & (USB_INTEP_HOST_IN | USB_INTEP_DEV_OUT)) >>
+         USB_INTEP_RX_SHIFT);
+}
+
+//*****************************************************************************
+//
+//! Returns the endpoint interrupt status on a given USB controller.
+//!
+//! \param ulBase specifies the USB module base address.
+//!
+//! This function will read endpoint interrupt status for a USB controller.
+//! This call will return the current status for endpoint interrupts only, the
+//! control interrupt status is retrieved by calling USBIntStatusControl().
+//! The bit values returned should be compared against the \b USB_INTEP_*
+//! values.  These are grouped into classes for \b USB_INTEP_HOST_* and
+//! \b USB_INTEP_DEV_* values to handle both host and device modes with all
+//! endpoints.
+//!
+//! \note This call will clear the source of all of the endpoint interrupts.
+//!
+//! \return Returns the status of the endpoint interrupts for a USB controller.
+//
+//*****************************************************************************
+unsigned long
+USBIntStatusEndpoint(unsigned long ulBase)
+{
+    unsigned long ulStatus;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulBase == USB0_BASE);
+
+    //
+    // Get the transmit interrupt status.
+    //
+    ulStatus = HWREGH(ulBase + USB_O_TXIS);
+
+    ulStatus |= (HWREGH(ulBase + USB_O_RXIS) << USB_INTEP_RX_SHIFT);
+
+    //
+    // Return the combined interrupt status.
+    //
+    return(ulStatus);
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the USB controller.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param pfnHandler is a pointer to the function to be called when a USB
+//! interrupt occurs.
+//!
+//! This sets the handler to be called when a USB interrupt occurs.  This will
+//! also enable the global USB interrupt in the interrupt controller.  The
+//! specific desired USB interrupts must be enabled via a separate call to
+//! USBIntEnable().  It is the interrupt handler's responsibility to clear the
+//! interrupt sources via a calls to USBIntStatusControl() and
+//! USBIntStatusEndpoint().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBIntRegister(unsigned long ulBase, void(*pfnHandler)(void))
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulBase == USB0_BASE);
+
+    //
+    // Register the interrupt handler.
+    //
+    IntRegister(INT_USB0, pfnHandler);
+
+    //
+    // Enable the USB interrupt.
+    //
+    IntEnable(INT_USB0);
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for the USB controller.
+//!
+//! \param ulBase specifies the USB module base address.
+//!
+//! This function unregister the interrupt handler.  This function will also
+//! disable the USB interrupt in the interrupt controller.
+//!
+//! \sa IntRegister() for important information about registering or
+//! unregistering interrupt handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBIntUnregister(unsigned long ulBase)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulBase == USB0_BASE);
+
+    //
+    // Disable the USB interrupt.
+    //
+    IntDisable(INT_USB0);
+
+    //
+    // Unregister the interrupt handler.
+    //
+    IntUnregister(INT_USB0);
+}
+
+//*****************************************************************************
+//
+//! Returns the current status of an endpoint.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint is the endpoint to access.
+//!
+//! This function will return the status of a given endpoint.  If any of these
+//! status bits need to be cleared, then these these values must be cleared by
+//! calling the USBDevEndpointStatusClear() or USBHostEndpointStatusClear()
+//! functions.
+//!
+//! The following are the status flags for host mode:
+//!
+//! - \b USB_HOST_IN_PID_ERROR - PID error on the given endpoint.
+//! - \b USB_HOST_IN_NOT_COMP - The device failed to respond to an IN request.
+//! - \b USB_HOST_IN_STALL - A stall was received on an IN endpoint.
+//! - \b USB_HOST_IN_DATA_ERROR - There was a CRC or bit-stuff error on an IN
+//!   endpoint in Isochronous mode.
+//! - \b USB_HOST_IN_NAK_TO - NAKs received on this IN endpoint for more than
+//!   the specified timeout period.
+//! - \b USB_HOST_IN_ERROR - Failed to communicate with a device using this IN
+//!   endpoint.
+//! - \b USB_HOST_IN_FIFO_FULL - This IN endpoint's FIFO is full.
+//! - \b USB_HOST_IN_PKTRDY - Data packet ready on this IN endpoint.
+//! - \b USB_HOST_OUT_NAK_TO - NAKs received on this OUT endpoint for more than
+//!   the specified timeout period.
+//! - \b USB_HOST_OUT_NOT_COMP - The device failed to respond to an OUT
+//!   request.
+//! - \b USB_HOST_OUT_STALL - A stall was received on this OUT endpoint.
+//! - \b USB_HOST_OUT_ERROR - Failed to communicate with a device using this
+//!   OUT endpoint.
+//! - \b USB_HOST_OUT_FIFO_NE - This endpoint's OUT FIFO is not empty.
+//! - \b USB_HOST_OUT_PKTPEND - The data transfer on this OUT endpoint has not
+//!   completed.
+//! - \b USB_HOST_EP0_NAK_TO - NAKs received on endpoint zero for more than the
+//!   specified timeout period.
+//! - \b USB_HOST_EP0_ERROR - The device failed to respond to a request on
+//!   endpoint zero.
+//! - \b USB_HOST_EP0_IN_STALL - A stall was received on endpoint zero for an
+//!   IN transaction.
+//! - \b USB_HOST_EP0_IN_PKTRDY - Data packet ready on endpoint zero for an IN
+//!   transaction.
+//!
+//! The following are the status flags for device mode:
+//!
+//! - \b USB_DEV_OUT_SENT_STALL - A stall was sent on this OUT endpoint.
+//! - \b USB_DEV_OUT_DATA_ERROR - There was a CRC or bit-stuff error on an OUT
+//!   endpoint.
+//! - \b USB_DEV_OUT_OVERRUN - An OUT packet was not loaded due to a full FIFO.
+//! - \b USB_DEV_OUT_FIFO_FULL - The OUT endpoint's FIFO is full.
+//! - \b USB_DEV_OUT_PKTRDY - There is a data packet ready in the OUT
+//!   endpoint's FIFO.
+//! - \b USB_DEV_IN_NOT_COMP - A larger packet was split up, more data to come.
+//! - \b USB_DEV_IN_SENT_STALL - A stall was sent on this IN endpoint.
+//! - \b USB_DEV_IN_UNDERRUN - Data was requested on the IN endpoint and no
+//!   data was ready.
+//! - \b USB_DEV_IN_FIFO_NE - The IN endpoint's FIFO is not empty.
+//! - \b USB_DEV_IN_PKTPEND - The data transfer on this IN endpoint has not
+//!   completed.
+//! - \b USB_DEV_EP0_SETUP_END - A control transaction ended before Data End
+//!   condition was sent.
+//! - \b USB_DEV_EP0_SENT_STALL - A stall was sent on endpoint zero.
+//! - \b USB_DEV_EP0_IN_PKTPEND - The data transfer on endpoint zero has not
+//!   completed.
+//! - \b USB_DEV_EP0_OUT_PKTRDY - There is a data packet ready in endpoint
+//!   zero's OUT FIFO.
+//!
+//! \return The current status flags for the endpoint depending on mode.
+//
+//*****************************************************************************
+unsigned long
+USBEndpointStatus(unsigned long ulBase, unsigned long ulEndpoint)
+{
+    unsigned long ulStatus;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulBase == USB0_BASE);
+    ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) ||
+           (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) ||
+           (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) ||
+           (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) ||
+           (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) ||
+           (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) ||
+           (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) ||
+           (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15));
+
+    //
+    // Get the TX portion of the endpoint status.
+    //
+    ulStatus = HWREGH(ulBase + EP_OFFSET(ulEndpoint) + USB_O_TXCSRL1);
+
+    //
+    // Get the RX portion of the endpoint status.
+    //
+    ulStatus |= ((HWREGH(ulBase + EP_OFFSET(ulEndpoint) + USB_O_RXCSRL1)) <<
+                 USB_RX_EPSTATUS_SHIFT);
+
+    //
+    // Return the endpoint status.
+    //
+    return(ulStatus);
+}
+
+//*****************************************************************************
+//
+//! Clears the status bits in this endpoint in host mode.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint is the endpoint to access.
+//! \param ulFlags are the status bits that will be cleared.
+//!
+//! This function will clear the status of any bits that are passed in the
+//! \e ulFlags parameter.  The \e ulFlags parameter can take the value returned
+//! from the USBEndpointStatus() call.
+//!
+//! \note This function should only be called in host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostEndpointStatusClear(unsigned long ulBase, unsigned long ulEndpoint,
+                           unsigned long ulFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulBase == USB0_BASE);
+    ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) ||
+           (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) ||
+           (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) ||
+           (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) ||
+           (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) ||
+           (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) ||
+           (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) ||
+           (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15));
+
+    //
+    // Clear the specified flags for the endpoint.
+    //
+    if(ulEndpoint == USB_EP_0)
+    {
+        HWREGB(ulBase + USB_O_CSRL0) &= ~ulFlags;
+    }
+    else
+    {
+        HWREGB(ulBase + USB_O_TXCSRL1 + EP_OFFSET(ulEndpoint)) &= ~ulFlags;
+        HWREGB(ulBase + USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint)) &=
+            ~(ulFlags >> USB_RX_EPSTATUS_SHIFT);
+    }
+}
+
+//*****************************************************************************
+//
+//! Clears the status bits in this endpoint in device mode.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint is the endpoint to access.
+//! \param ulFlags are the status bits that will be cleared.
+//!
+//! This function will clear the status of any bits that are passed in the
+//! \e ulFlags parameter.  The \e ulFlags parameter can take the value returned
+//! from the USBEndpointStatus() call.
+//!
+//! \note This function should only be called in device mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDevEndpointStatusClear(unsigned long ulBase, unsigned long ulEndpoint,
+                          unsigned long ulFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulBase == USB0_BASE);
+    ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) ||
+           (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) ||
+           (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) ||
+           (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) ||
+           (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) ||
+           (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) ||
+           (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) ||
+           (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15));
+
+    //
+    // If this is endpoint 0 then the bits have different meaning and map into
+    // the TX memory location.
+    //
+    if(ulEndpoint == USB_EP_0)
+    {
+        //
+        // Set the Serviced RxPktRdy bit to clear the RxPktRdy.
+        //
+        if(ulFlags & USB_DEV_EP0_OUT_PKTRDY)
+        {
+            HWREGB(ulBase + USB_O_CSRL0) |= USB_CSRL0_RXRDYC;
+        }
+
+        //
+        // Set the serviced Setup End bit to clear the SetupEnd status.
+        //
+        if(ulFlags & USB_DEV_EP0_SETUP_END)
+        {
+            HWREGB(ulBase + USB_O_CSRL0) |= USB_CSRL0_SETENDC;
+        }
+
+        //
+        // Clear the Sent Stall status flag.
+        //
+        if(ulFlags & USB_DEV_EP0_SENT_STALL)
+        {
+            HWREGB(ulBase + USB_O_CSRL0) &= ~(USB_DEV_EP0_SENT_STALL);
+        }
+    }
+    else
+    {
+        //
+        // Clear out any TX flags that were passed in.  Only
+        // USB_DEV_TX_SENT_STALL and USB_DEV_TX_UNDERRUN should be cleared.
+        //
+        HWREGB(ulBase + USB_O_TXCSRL1 + EP_OFFSET(ulEndpoint)) &=
+            ~(ulFlags & (USB_DEV_TX_SENT_STALL | USB_DEV_TX_UNDERRUN));
+
+        //
+        // Clear out valid RX flags that were passed in.  Only
+        // USB_DEV_RX_SENT_STALL, USB_DEV_RX_DATA_ERROR, and USB_DEV_RX_OVERRUN
+        // should be cleared.
+        //
+        HWREGB(ulBase + USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint)) &=
+            ~((ulFlags & (USB_DEV_RX_SENT_STALL | USB_DEV_RX_DATA_ERROR |
+                          USB_DEV_RX_OVERRUN)) >> USB_RX_EPSTATUS_SHIFT);
+    }
+}
+
+//*****************************************************************************
+//
+//! Sets the value data toggle on an endpoint in host mode.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint specifies the endpoint to reset the data toggle.
+//! \param bDataToggle specifies whether to set the state to DATA0 or DATA1.
+//! \param ulFlags specifies whether to set the IN or OUT endpoint.
+//!
+//! This function is used to force the state of the data toggle in host mode.
+//! If the value passed in the \e bDataToggle parameter is \b false, then the
+//! data toggle will be set to the DATA0 state, and if it is \b true it will be
+//! set to the DATA1 state.  The \e ulFlags parameter can be \b USB_EP_HOST_IN
+//! or \b USB_EP_HOST_OUT to access the desired portion of this endpoint.  The
+//! \e ulFlags parameter is ignored for endpoint zero.
+//!
+//! \note This function should only be called in host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostEndpointDataToggle(unsigned long ulBase, unsigned long ulEndpoint,
+                          tBoolean bDataToggle, unsigned long ulFlags)
+{
+    unsigned long ulDataToggle;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulBase == USB0_BASE);
+    ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) ||
+           (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) ||
+           (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) ||
+           (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) ||
+           (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) ||
+           (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) ||
+           (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) ||
+           (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15));
+
+    //
+    // The data toggle defaults to DATA0.
+    //
+    ulDataToggle = 0;
+
+    //
+    // See if the data toggle should be set to DATA1.
+    //
+    if(bDataToggle)
+    {
+        //
+        // Select the data toggle bit based on the endpoint.
+        //
+        if(ulEndpoint == USB_EP_0)
+        {
+            ulDataToggle = USB_CSRH0_DT;
+        }
+        else if(ulFlags == USB_EP_HOST_IN)
+        {
+            ulDataToggle = USB_RXCSRH1_DT;
+        }
+        else
+        {
+            ulDataToggle = USB_TXCSRH1_DT;
+        }
+    }
+
+    //
+    // Set the data toggle based on the endpoint.
+    //
+    if(ulEndpoint == USB_EP_0)
+    {
+        //
+        // Set the write enable and the bit value for endpoint zero.
+        //
+        HWREGB(ulBase + USB_O_CSRH0) =
+            ((HWREGB(ulBase + USB_O_CSRH0) &
+              ~(USB_CSRH0_DTWE | USB_CSRH0_DT)) |
+             (ulDataToggle | USB_CSRH0_DTWE));
+    }
+    else if(ulFlags == USB_EP_HOST_IN)
+    {
+        //
+        // Set the Write enable and the bit value for an IN endpoint.
+        //
+        HWREGB(ulBase + USB_O_RXCSRH1 + EP_OFFSET(ulEndpoint)) =
+            ((HWREGB(ulBase + USB_O_RXCSRH1 + EP_OFFSET(ulEndpoint)) &
+              ~(USB_RXCSRH1_DTWE | USB_RXCSRH1_DT)) |
+             (ulDataToggle | USB_RXCSRH1_DTWE));
+    }
+    else
+    {
+        //
+        // Set the Write enable and the bit value for an OUT endpoint.
+        //
+        HWREGB(ulBase + USB_O_TXCSRH1 + EP_OFFSET(ulEndpoint)) =
+            ((HWREGB(ulBase + USB_O_TXCSRH1 + EP_OFFSET(ulEndpoint)) &
+              ~(USB_TXCSRH1_DTWE | USB_TXCSRH1_DT)) |
+             (ulDataToggle | USB_TXCSRH1_DTWE));
+    }
+}
+
+//*****************************************************************************
+//
+//! Sets the Data toggle on an endpoint to zero.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint specifies the endpoint to reset the data toggle.
+//! \param ulFlags specifies whether to access the IN or OUT endpoint.
+//!
+//! This function will cause the controller to clear the data toggle for an
+//! endpoint.  This call is not valid for endpoint zero and can be made with
+//! host or device controllers.
+//!
+//! The \e ulFlags parameter should be one of \b USB_EP_HOST_OUT,
+//! \b USB_EP_HOST_IN, \b USB_EP_DEV_OUT, or \b USB_EP_DEV_IN.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBEndpointDataToggleClear(unsigned long ulBase, unsigned long ulEndpoint,
+                           unsigned long ulFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulBase == USB0_BASE);
+    ASSERT((ulEndpoint == USB_EP_1) || (ulEndpoint == USB_EP_2) ||
+           (ulEndpoint == USB_EP_3) || (ulEndpoint == USB_EP_4) ||
+           (ulEndpoint == USB_EP_5) || (ulEndpoint == USB_EP_6) ||
+           (ulEndpoint == USB_EP_7) || (ulEndpoint == USB_EP_8) ||
+           (ulEndpoint == USB_EP_9) || (ulEndpoint == USB_EP_10) ||
+           (ulEndpoint == USB_EP_11) || (ulEndpoint == USB_EP_12) ||
+           (ulEndpoint == USB_EP_13) || (ulEndpoint == USB_EP_14) ||
+           (ulEndpoint == USB_EP_15));
+
+    //
+    // See if the transmit or receive data toggle should be cleared.
+    //
+    if(ulFlags & (USB_EP_HOST_OUT | USB_EP_DEV_IN))
+    {
+        HWREGB(ulBase + USB_O_TXCSRL1 + EP_OFFSET(ulEndpoint)) |=
+            USB_TXCSRL1_CLRDT;
+    }
+    else
+    {
+        HWREGB(ulBase + USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint)) |=
+            USB_RXCSRL1_CLRDT;
+    }
+}
+
+//*****************************************************************************
+//
+//! Stalls the specified endpoint in device mode.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint specifies the endpoint to stall.
+//! \param ulFlags specifies whether to stall the IN or OUT endpoint.
+//!
+//! This function will cause to endpoint number passed in to go into a stall
+//! condition.  If the \e ulFlags parameter is \b USB_EP_DEV_IN then the stall
+//! will be issued on the IN portion of this endpoint.  If the \e ulFlags
+//! parameter is \b USB_EP_DEV_OUT then the stall will be issued on the OUT
+//! portion of this endpoint.
+//!
+//! \note This function should only be called in device mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDevEndpointStall(unsigned long ulBase, unsigned long ulEndpoint,
+                    unsigned long ulFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulBase == USB0_BASE);
+    ASSERT((ulFlags & ~(USB_EP_DEV_IN | USB_EP_DEV_OUT)) == 0)
+    ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) ||
+           (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) ||
+           (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) ||
+           (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) ||
+           (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) ||
+           (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) ||
+           (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) ||
+           (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15));
+
+    //
+    // Determine how to stall this endpoint.
+    //
+    if(ulEndpoint == USB_EP_0)
+    {
+        //
+        // Perform a stall on endpoint zero.
+        //
+        HWREGB(ulBase + USB_O_CSRL0) |=
+            (USB_CSRL0_STALL | USB_CSRL0_RXRDYC);
+    }
+    else if(ulFlags == USB_EP_DEV_IN)
+    {
+        //
+        // Perform a stall on an IN endpoint.
+        //
+        HWREGB(ulBase + USB_O_TXCSRL1 + EP_OFFSET(ulEndpoint)) |=
+            USB_TXCSRL1_STALL;
+    }
+    else
+    {
+        //
+        // Perform a stall on an OUT endpoint.
+        //
+        HWREGB(ulBase + USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint)) |=
+            USB_RXCSRL1_STALL;
+    }
+}
+
+//*****************************************************************************
+//
+//! Clears the stall condition on the specified endpoint in device mode.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint specifies which endpoint to remove the stall condition.
+//! \param ulFlags specifies whether to remove the stall condition from the IN
+//! or the OUT portion of this endpoint.
+//!
+//! This function will cause the endpoint number passed in to exit the stall
+//! condition.  If the \e ulFlags parameter is \b USB_EP_DEV_IN then the stall
+//! will be cleared on the IN portion of this endpoint.  If the \e ulFlags
+//! parameter is \b USB_EP_DEV_OUT then the stall will be cleared on the OUT
+//! portion of this endpoint.
+//!
+//! \note This function should only be called in device mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDevEndpointStallClear(unsigned long ulBase, unsigned long ulEndpoint,
+                         unsigned long ulFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulBase == USB0_BASE);
+    ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) ||
+           (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) ||
+           (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) ||
+           (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) ||
+           (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) ||
+           (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) ||
+           (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) ||
+           (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15));
+    ASSERT((ulFlags & ~(USB_EP_DEV_IN | USB_EP_DEV_OUT)) == 0)
+
+    //
+    // Determine how to clear the stall on this endpoint.
+    //
+    if(ulEndpoint == USB_EP_0)
+    {
+        //
+        // Clear the stall on endpoint zero.
+        //
+        HWREGB(ulBase + USB_O_CSRL0) &= ~USB_CSRL0_STALLED;
+    }
+    else if(ulFlags == USB_EP_DEV_IN)
+    {
+        //
+        // Clear the stall on an IN endpoint.
+        //
+        HWREGB(ulBase + USB_O_TXCSRL1 + EP_OFFSET(ulEndpoint)) &=
+            ~(USB_TXCSRL1_STALL | USB_TXCSRL1_STALLED);
+
+        //
+        // Reset the data toggle.
+        //
+        HWREGB(ulBase + USB_O_TXCSRL1 + EP_OFFSET(ulEndpoint)) |=
+            USB_TXCSRL1_CLRDT;
+    }
+    else
+    {
+        //
+        // Clear the stall on an OUT endpoint.
+        //
+        HWREGB(ulBase + USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint)) &=
+            ~(USB_RXCSRL1_STALL | USB_RXCSRL1_STALLED);
+
+        //
+        // Reset the data toggle.
+        //
+        HWREGB(ulBase + USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint)) |=
+            USB_RXCSRL1_CLRDT;
+    }
+}
+
+//*****************************************************************************
+//
+//! Connects the USB controller to the bus in device mode.
+//!
+//! \param ulBase specifies the USB module base address.
+//!
+//! This function will cause the soft connect feature of the USB controller to
+//! be enabled.  Call USBDevDisconnect() to remove the USB device from the bus.
+//!
+//! \note This function should only be called in device mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDevConnect(unsigned long ulBase)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulBase == USB0_BASE);
+
+    //
+    // Enable connection to the USB bus.
+    //
+    HWREGB(ulBase + USB_O_POWER) |= USB_POWER_SOFTCONN;
+}
+
+//*****************************************************************************
+//
+//! Removes the USB controller from the bus in device mode.
+//!
+//! \param ulBase specifies the USB module base address.
+//!
+//! This function will cause the soft connect feature of the USB controller to
+//! remove the device from the USB bus.  A call to USBDevConnect() is needed to
+//! reconnect to the bus.
+//!
+//! \note This function should only be called in device mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDevDisconnect(unsigned long ulBase)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulBase == USB0_BASE);
+
+    //
+    // Disable connection to the USB bus.
+    //
+    HWREGB(ulBase + USB_O_POWER) &= (~USB_POWER_SOFTCONN);
+}
+
+//*****************************************************************************
+//
+//! Sets the address in device mode.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulAddress is the address to use for a device.
+//!
+//! This function will set the device address on the USB bus.  This address was
+//! likely received via a SET ADDRESS command from the host controller.
+//!
+//! \note This function should only be called in device mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDevAddrSet(unsigned long ulBase, unsigned long ulAddress)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulBase == USB0_BASE);
+
+    //
+    // Set the function address in the correct location.
+    //
+    HWREGB(ulBase + USB_O_FADDR) = (unsigned char)ulAddress;
+}
+
+//*****************************************************************************
+//
+//! Returns the current device address in device mode.
+//!
+//! \param ulBase specifies the USB module base address.
+//!
+//! This function will return the current device address.  This address was set
+//! by a call to USBDevAddrSet().
+//!
+//! \note This function should only be called in device mode.
+//!
+//! \return The current device address.
+//
+//*****************************************************************************
+unsigned long
+USBDevAddrGet(unsigned long ulBase)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulBase == USB0_BASE);
+
+    //
+    // Return the function address.
+    //
+    return(HWREGB(ulBase + USB_O_FADDR));
+}
+
+//*****************************************************************************
+//
+//! Sets the base configuration for a host endpoint.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint is the endpoint to access.
+//! \param ulMaxPayload is the maximum payload for this endpoint.
+//! \param ulNAKPollInterval is the either the NAK timeout limit or the polling
+//! interval depending on the type of endpoint.
+//! \param ulTargetEndpoint is the endpoint that the host endpoint is
+//! targeting.
+//! \param ulFlags are used to configure other endpoint settings.
+//!
+//! This function will set the basic configuration for the transmit or receive
+//! portion of an endpoint in host mode.  The \e ulFlags parameter determines
+//! some of the configuration while the other parameters provide the rest.  The
+//! \e ulFlags parameter determines whether this is an IN endpoint
+//! (USB_EP_HOST_IN or USB_EP_DEV_IN) or an OUT endpoint (USB_EP_HOST_OUT or
+//! USB_EP_DEV_OUT), whether this is a Full speed endpoint (USB_EP_SPEED_FULL)
+//! or a Low speed endpoint (USB_EP_SPEED_LOW).
+//!
+//! The \b USB_EP_MODE_ flags control the type of the endpoint.
+//! - \b USB_EP_MODE_CTRL is a control endpoint.
+//! - \b USB_EP_MODE_ISOC is an isochronous endpoint.
+//! - \b USB_EP_MODE_BULK is a bulk endpoint.
+//! - \b USB_EP_MODE_INT is an interrupt endpoint.
+//!
+//! The \e ulNAKPollInterval parameter has different meanings based on the
+//! \b USB_EP_MODE value and whether or not this call is being made for
+//! endpoint zero or another endpoint.  For endpoint zero or any Bulk
+//! endpoints, this value always indicates the number of frames to allow a
+//! device to NAK before considering it a timeout.  If this endpoint is an
+//! isochronous or interrupt endpoint, this value is the polling interval for
+//! this endpoint.
+//!
+//! For interrupt endpoints the polling interval is simply the number of
+//! frames between polling an interrupt endpoint.  For isochronous endpoints
+//! this value represents a polling interval of 2 ^ (\e ulNAKPollInterval - 1)
+//! frames.  When used as a NAK timeout, the \e ulNAKPollInterval value
+//! specifies 2 ^ (\e ulNAKPollInterval - 1) frames before issuing a time out.
+//! There are two special time out values that can be specified when setting
+//! the \e ulNAKPollInterval value.  The first is \b MAX_NAK_LIMIT which is the
+//! maximum value that can be passed in this variable.  The other is
+//! \b DISABLE_NAK_LIMIT which indicates that there should be no limit on the
+//! number of NAKs.
+//!
+//! The \b USB_EP_DMA_MODE_ flags enables the type of DMA used to access the
+//! endpoint's data FIFOs.  The choice of the DMA mode depends on how the DMA
+//! controller is configured and how it is being used.  See the ``Using USB
+//! with the uDMA Controller'' section for more information on DMA
+//! configuration.
+//!
+//! When configuring the OUT portion of an endpoint, the \b USB_EP_AUTO_SET bit
+//! is specified to cause the transmission of data on the USB bus to start
+//! as soon as the number of bytes specified by \e ulMaxPayload have been
+//! written into the OUT FIFO for this endpoint.
+//!
+//! When configuring the IN portion of an endpoint, the \b USB_EP_AUTO_REQUEST
+//! bit can be specified to trigger the request for more data once the FIFO has
+//! been drained enough to fit \e ulMaxPayload bytes.  The \b USB_EP_AUTO_CLEAR
+//! bit can be used to clear the data packet ready flag automatically once the
+//! data has been read from the FIFO.  If this is not used, this flag must be
+//! manually cleared via a call to USBDevEndpointStatusClear() or
+//! USBHostEndpointStatusClear().
+//!
+//! \note This function should only be called in host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostEndpointConfig(unsigned long ulBase, unsigned long ulEndpoint,
+                      unsigned long ulMaxPayload,
+                      unsigned long ulNAKPollInterval,
+                      unsigned long ulTargetEndpoint, unsigned long ulFlags)
+{
+    unsigned long ulRegister;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulBase == USB0_BASE);
+    ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) ||
+           (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) ||
+           (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) ||
+           (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) ||
+           (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) ||
+           (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) ||
+           (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) ||
+           (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15));
+    ASSERT(ulNAKPollInterval <= MAX_NAK_LIMIT);
+
+    //
+    // Endpoint zero is configured differently than the other endpoints, so see
+    // if this is endpoint zero.
+    //
+    if(ulEndpoint == USB_EP_0)
+    {
+        //
+        // Set the NAK timeout.
+        //
+        HWREGB(ulBase + USB_O_NAKLMT) = ulNAKPollInterval;
+
+        //
+        // Set the transfer type information.
+        //
+        HWREGB(ulBase + USB_O_TYPE0) =
+            ((ulFlags & USB_EP_SPEED_FULL) ? USB_TYPE0_SPEED_FULL :
+             USB_TYPE0_SPEED_LOW);
+    }
+    else
+    {
+        //
+        // Start with the target endpoint.
+        //
+        ulRegister = ulTargetEndpoint;
+
+        //
+        // Set the speed for the device using this endpoint.
+        //
+        if(ulFlags & USB_EP_SPEED_FULL)
+        {
+            ulRegister |= USB_TXTYPE1_SPEED_FULL;
+        }
+        else
+        {
+            ulRegister |= USB_TXTYPE1_SPEED_LOW;
+        }
+
+        //
+        // Set the protocol for the device using this endpoint.
+        //
+        switch(ulFlags & USB_EP_MODE_MASK)
+        {
+            //
+            // The bulk protocol is being used.
+            //
+            case USB_EP_MODE_BULK:
+            {
+                ulRegister |= USB_TXTYPE1_PROTO_BULK;
+                break;
+            }
+
+            //
+            // The isochronous protocol is being used.
+            //
+            case USB_EP_MODE_ISOC:
+            {
+                ulRegister |= USB_TXTYPE1_PROTO_ISOC;
+                break;
+            }
+
+            //
+            // The interrupt protocol is being used.
+            //
+            case USB_EP_MODE_INT:
+            {
+                ulRegister |= USB_TXTYPE1_PROTO_INT;
+                break;
+            }
+
+            //
+            // The control protocol is being used.
+            //
+            case USB_EP_MODE_CTRL:
+            {
+                ulRegister |= USB_TXTYPE1_PROTO_CTRL;
+                break;
+            }
+        }
+
+        //
+        // See if the transmit or receive endpoint is being configured.
+        //
+        if(ulFlags & USB_EP_HOST_OUT)
+        {
+            //
+            // Set the transfer type information.
+            //
+            HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_TXTYPE1) =
+                ulRegister;
+
+            //
+            // Set the NAK timeout or polling interval.
+            //
+            HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_TXINTERVAL1) =
+                ulNAKPollInterval;
+
+            //
+            // Set the Maximum Payload per transaction.
+            //
+            HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_TXMAXP1) =
+                ulMaxPayload;
+
+            //
+            // Set the transmit control value to zero.
+            //
+            ulRegister = 0;
+
+            //
+            // Allow auto setting of TxPktRdy when max packet size has been
+            // loaded into the FIFO.
+            //
+            if(ulFlags & USB_EP_AUTO_SET)
+            {
+                ulRegister |= USB_TXCSRH1_AUTOSET;
+            }
+
+            //
+            // Configure the DMA Mode.
+            //
+            if(ulFlags & USB_EP_DMA_MODE_1)
+            {
+                ulRegister |= USB_TXCSRH1_DMAEN | USB_TXCSRH1_DMAMOD;
+            }
+            else if(ulFlags & USB_EP_DMA_MODE_0)
+            {
+                ulRegister |= USB_TXCSRH1_DMAEN;
+            }
+
+            //
+            // Write out the transmit control value.
+            //
+            HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_TXCSRH1) =
+                (unsigned char)ulRegister;
+        }
+        else
+        {
+            //
+            // Set the transfer type information.
+            //
+            HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_RXTYPE1) =
+                ulRegister;
+
+            //
+            // Set the NAK timeout or polling interval.
+            //
+            HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_RXINTERVAL1) =
+                ulNAKPollInterval;
+
+            //
+            // Set the receive control value to zero.
+            //
+            ulRegister = 0;
+
+            //
+            // Allow auto clearing of RxPktRdy when packet of size max packet
+            // has been unloaded from the FIFO.
+            //
+            if(ulFlags & USB_EP_AUTO_CLEAR)
+            {
+                ulRegister |= USB_RXCSRH1_AUTOCL;
+            }
+
+            //
+            // Configure the DMA Mode.
+            //
+            if(ulFlags & USB_EP_DMA_MODE_1)
+            {
+                ulRegister |= USB_RXCSRH1_DMAEN | USB_RXCSRH1_DMAMOD;
+            }
+            else if(ulFlags & USB_EP_DMA_MODE_0)
+            {
+                ulRegister |= USB_RXCSRH1_DMAEN;
+            }
+
+            //
+            // Write out the receive control value.
+            //
+            HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_RXCSRH1) =
+                (unsigned char)ulRegister;
+        }
+    }
+}
+
+//*****************************************************************************
+//
+//! Sets the configuration for an endpoint.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint is the endpoint to access.
+//! \param ulMaxPacketSize is the maximum packet size for this endpoint.
+//! \param ulFlags are used to configure other endpoint settings.
+//!
+//! This function will set the basic configuration for an endpoint in device
+//! mode.  Endpoint zero does not have a dynamic configuration, so this
+//! function should not be called for endpoint zero.  The \e ulFlags parameter
+//! determines some of the configuration while the other parameters provide the
+//! rest.
+//!
+//! The \b USB_EP_MODE_ flags define what the type is for the given endpoint.
+//!
+//! - \b USB_EP_MODE_CTRL is a control endpoint.
+//! - \b USB_EP_MODE_ISOC is an isochronous endpoint.
+//! - \b USB_EP_MODE_BULK is a bulk endpoint.
+//! - \b USB_EP_MODE_INT is an interrupt endpoint.
+//!
+//! The \b USB_EP_DMA_MODE_ flags determines the type of DMA access to the
+//! endpoint data FIFOs.  The choice of the DMA mode depends on how the DMA
+//! controller is configured and how it is being used.  See the ``Using USB
+//! with the uDMA Controller'' section for more information on DMA
+//! configuration.
+//!
+//! When configuring an IN endpoint, the \b USB_EP_AUTO_SET bit can be
+//! specified to cause the automatic transmission of data on the USB bus as
+//! soon as \e ulMaxPacketSize bytes of data are written into the FIFO for
+//! this endpoint.  This is commonly used with DMA as no interaction is
+//! required to start the transmission of data.
+//!
+//! When configuring an OUT endpoint, the \b USB_EP_AUTO_REQUEST bit is
+//! specified to trigger the request for more data once the FIFO has been
+//! drained enough to receive \e ulMaxPacketSize more bytes of data.  Also for
+//! OUT endpoints, the \b USB_EP_AUTO_CLEAR bit can be used to clear the data
+//! packet ready flag automatically once the data has been read from the FIFO.
+//! If this is not used, this flag must be manually cleared via a call to
+//! USBDevEndpointStatusClear().  Both of these settings can be used to remove
+//! the need for extra calls when using the controller in DMA mode.
+//!
+//! \note This function should only be called in device mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDevEndpointConfigSet(unsigned long ulBase, unsigned long ulEndpoint,
+                        unsigned long ulMaxPacketSize, unsigned long ulFlags)
+{
+    unsigned long ulRegister;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulBase == USB0_BASE);
+    ASSERT((ulEndpoint == USB_EP_1) || (ulEndpoint == USB_EP_2) ||
+           (ulEndpoint == USB_EP_3) || (ulEndpoint == USB_EP_4) ||
+           (ulEndpoint == USB_EP_5) || (ulEndpoint == USB_EP_6) ||
+           (ulEndpoint == USB_EP_7) || (ulEndpoint == USB_EP_8) ||
+           (ulEndpoint == USB_EP_9) || (ulEndpoint == USB_EP_10) ||
+           (ulEndpoint == USB_EP_11) || (ulEndpoint == USB_EP_12) ||
+           (ulEndpoint == USB_EP_13) || (ulEndpoint == USB_EP_14) ||
+           (ulEndpoint == USB_EP_15));
+
+    //
+    // Determine if a transmit or receive endpoint is being configured.
+    //
+    if(ulFlags & USB_EP_DEV_IN)
+    {
+        //
+        // Set the maximum packet size.
+        //
+        HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_TXMAXP1) =
+            ulMaxPacketSize;
+
+        //
+        // The transmit control value is zero unless options are enabled.
+        //
+        ulRegister = 0;
+
+        //
+        // Allow auto setting of TxPktRdy when max packet size has been loaded
+        // into the FIFO.
+        //
+        if(ulFlags & USB_EP_AUTO_SET)
+        {
+            ulRegister |= USB_TXCSRH1_AUTOSET;
+        }
+
+        //
+        // Configure the DMA mode.
+        //
+        if(ulFlags & USB_EP_DMA_MODE_1)
+        {
+            ulRegister |= USB_TXCSRH1_DMAEN | USB_TXCSRH1_DMAMOD;
+        }
+        else if(ulFlags & USB_EP_DMA_MODE_0)
+        {
+            ulRegister |= USB_TXCSRH1_DMAEN;
+        }
+
+        //
+        // Enable isochronous mode if requested.
+        //
+        if((ulFlags & USB_EP_MODE_MASK) == USB_EP_MODE_ISOC)
+        {
+            ulRegister |= USB_TXCSRH1_ISO;
+        }
+
+        //
+        // Write the transmit control value.
+        //
+        HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_TXCSRH1) =
+            (unsigned char)ulRegister;
+
+        //
+        // Reset the Data toggle to zero.
+        //
+        HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_TXCSRL1) =
+            USB_TXCSRL1_CLRDT;
+    }
+    else
+    {
+        //
+        // Set the MaxPacketSize.
+        //
+        HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_RXMAXP1) =
+            ulMaxPacketSize;
+
+        //
+        // The receive control value is zero unless options are enabled.
+        //
+        ulRegister = 0;
+
+        //
+        // Allow auto clearing of RxPktRdy when packet of size max packet
+        // has been unloaded from the FIFO.
+        //
+        if(ulFlags & USB_EP_AUTO_CLEAR)
+        {
+            ulRegister = USB_RXCSRH1_AUTOCL;
+        }
+
+        //
+        // Configure the DMA mode.
+        //
+        if(ulFlags & USB_EP_DMA_MODE_1)
+        {
+            ulRegister |= USB_RXCSRH1_DMAEN | USB_RXCSRH1_DMAMOD;
+        }
+        else if(ulFlags & USB_EP_DMA_MODE_0)
+        {
+            ulRegister |= USB_RXCSRH1_DMAEN;
+        }
+
+        //
+        // Enable isochronous mode if requested.
+        //
+        if((ulFlags & USB_EP_MODE_MASK) == USB_EP_MODE_ISOC)
+        {
+            ulRegister |= USB_RXCSRH1_ISO;
+        }
+
+        //
+        // Write the receive control value.
+        //
+        HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_RXCSRH1) =
+            (unsigned char)ulRegister;
+
+        //
+        // Reset the Data toggle to zero.
+        //
+        HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_RXCSRL1) =
+            USB_RXCSRL1_CLRDT;
+    }
+}
+
+//*****************************************************************************
+//
+//! Gets the current configuration for an endpoint.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint is the endpoint to access.
+//! \param pulMaxPacketSize is a pointer which will be written with the
+//! maximum packet size for this endpoint.
+//! \param pulFlags is a pointer which will be written with the current
+//! endpoint settings. On entry to the function, this pointer must contain
+//! either \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT to indicate whether the IN or
+//! OUT endpoint is to be queried.
+//!
+//! This function will return the basic configuration for an endpoint in device
+//! mode. The values returned in \e *pulMaxPacketSize and \e *pulFlags are
+//! equivalent to the \e ulMaxPacketSize and \e ulFlags previously passed to
+//! USBDevEndpointConfigSet() for this endpoint.
+//!
+//! \note This function should only be called in device mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDevEndpointConfigGet(unsigned long ulBase, unsigned long ulEndpoint,
+                        unsigned long *pulMaxPacketSize,
+                        unsigned long *pulFlags)
+{
+    unsigned long ulRegister;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulBase == USB0_BASE);
+    ASSERT(pulMaxPacketSize && pulFlags);
+    ASSERT((ulEndpoint == USB_EP_1) || (ulEndpoint == USB_EP_2) ||
+           (ulEndpoint == USB_EP_3) || (ulEndpoint == USB_EP_4) ||
+           (ulEndpoint == USB_EP_5) || (ulEndpoint == USB_EP_6) ||
+           (ulEndpoint == USB_EP_7) || (ulEndpoint == USB_EP_8) ||
+           (ulEndpoint == USB_EP_9) || (ulEndpoint == USB_EP_10) ||
+           (ulEndpoint == USB_EP_11) || (ulEndpoint == USB_EP_12) ||
+           (ulEndpoint == USB_EP_13) || (ulEndpoint == USB_EP_14) ||
+           (ulEndpoint == USB_EP_15));
+
+    //
+    // Determine if a transmit or receive endpoint is being queried.
+    //
+    if(*pulFlags & USB_EP_DEV_IN)
+    {
+        //
+        // Clear the flags other than the direction bit.
+        //
+        *pulFlags = USB_EP_DEV_IN;
+
+        //
+        // Get the maximum packet size.
+        //
+        *pulMaxPacketSize = (unsigned long)HWREGB(ulBase +
+                                                  EP_OFFSET(ulEndpoint) +
+                                                  USB_O_TXMAXP1);
+
+        //
+        // Get the current transmit control register value.
+        //
+        ulRegister = (unsigned long)HWREGB(ulBase + EP_OFFSET(ulEndpoint) +
+                                           USB_O_TXCSRH1);
+
+        //
+        // Are we allowing auto setting of TxPktRdy when max packet size has
+        // been loaded into the FIFO?
+        //
+        if(ulRegister & USB_TXCSRH1_AUTOSET)
+        {
+            *pulFlags |= USB_EP_AUTO_SET;
+        }
+
+        //
+        // Get the DMA mode.
+        //
+        if(ulRegister & USB_TXCSRH1_DMAEN)
+        {
+            if(ulRegister & USB_TXCSRH1_DMAMOD)
+            {
+                *pulFlags |= USB_EP_DMA_MODE_1;
+            }
+            else
+            {
+                *pulFlags |= USB_EP_DMA_MODE_0;
+            }
+        }
+
+        //
+        // Are we in isochronous mode?
+        //
+        if(ulRegister & USB_TXCSRH1_ISO)
+        {
+            *pulFlags |= USB_EP_MODE_ISOC;
+        }
+        else
+        {
+            //
+            // The hardware doesn't differentiate between bulk, interrupt
+            // and control mode for the endpoint so we just set something
+            // that isn't isochronous.  This ensures that anyone modifying
+            // the returned flags in preparation for a call to
+            // USBDevEndpointConfigSet will not see an unexpected mode change.
+            // If they decode the returned mode, however, they may be in for
+            // a surprise.
+            //
+            *pulFlags |= USB_EP_MODE_BULK;
+        }
+    }
+    else
+    {
+        //
+        // Clear the flags other than the direction bit.
+        //
+        *pulFlags = USB_EP_DEV_OUT;
+
+        //
+        // Get the MaxPacketSize.
+        //
+        *pulMaxPacketSize = (unsigned long)HWREGB(ulBase +
+                                                  EP_OFFSET(ulEndpoint) +
+                                                  USB_O_RXMAXP1);
+
+        //
+        // Get the current receive control register value.
+        //
+        ulRegister = (unsigned long)HWREGB(ulBase + EP_OFFSET(ulEndpoint) +
+                                           USB_O_RXCSRH1);
+
+        //
+        // Are we allowing auto clearing of RxPktRdy when packet of size max
+        // packet has been unloaded from the FIFO?
+        //
+        if(ulRegister & USB_RXCSRH1_AUTOCL)
+        {
+            *pulFlags |= USB_EP_AUTO_CLEAR;
+        }
+
+        //
+        // Get the DMA mode.
+        //
+        if(ulRegister & USB_RXCSRH1_DMAEN)
+        {
+            if(ulRegister & USB_RXCSRH1_DMAMOD)
+            {
+                *pulFlags |= USB_EP_DMA_MODE_1;
+            }
+            else
+            {
+                *pulFlags |= USB_EP_DMA_MODE_0;
+            }
+        }
+
+        //
+        // Are we in isochronous mode?
+        //
+        if(ulRegister & USB_RXCSRH1_ISO)
+        {
+            *pulFlags |= USB_EP_MODE_ISOC;
+        }
+        else
+        {
+            //
+            // The hardware doesn't differentiate between bulk, interrupt
+            // and control mode for the endpoint so we just set something
+            // that isn't isochronous.  This ensures that anyone modifying
+            // the returned flags in preparation for a call to
+            // USBDevEndpointConfigSet will not see an unexpected mode change.
+            // If they decode the returned mode, however, they may be in for
+            // a surprise.
+            //
+            *pulFlags |= USB_EP_MODE_BULK;
+        }
+    }
+}
+
+//*****************************************************************************
+//
+//! Sets the FIFO configuration for an endpoint.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint is the endpoint to access.
+//! \param ulFIFOAddress is the starting address for the FIFO.
+//! \param ulFIFOSize is the size of the FIFO in bytes.
+//! \param ulFlags specifies what information to set in the FIFO configuration.
+//!
+//! This function will set the starting FIFO RAM address and size of the FIFO
+//! for a given endpoint.  Endpoint zero does not have a dynamically
+//! configurable FIFO so this function should not be called for endpoint zero.
+//! The \e ulFIFOSize parameter should be one of the values in the
+//! \b USB_FIFO_SZ_ values.  If the endpoint is going to use double buffering
+//! it should use the values with the \b _DB at the end of the value.  For
+//! example, use \b USB_FIFO_SZ_16_DB to configure an endpoint to have a 16
+//! byte double buffered FIFO.  If a double buffered FIFO is used, then the
+//! actual size of the FIFO will be twice the size indicated by the
+//! \e ulFIFOSize parameter.  This means that the \b USB_FIFO_SZ_16_DB value
+//! will use 32 bytes of the USB controller's FIFO memory.
+//!
+//! The \e ulFIFOAddress value should be a multiple of 8 bytes and directly
+//! indicates the starting address in the USB controller's FIFO RAM.  For
+//! example, a value of 64 indicates that the FIFO should start 64 bytes into
+//! the USB controller's FIFO memory.  The \e ulFlags value specifies whether
+//! the endpoint's OUT or IN FIFO should be configured.  If in host mode, use
+//! \b USB_EP_HOST_OUT or \b USB_EP_HOST_IN, and if in device mode use
+//! \b USB_EP_DEV_OUT or \b USB_EP_DEV_IN.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBFIFOConfigSet(unsigned long ulBase, unsigned long ulEndpoint,
+                 unsigned long ulFIFOAddress, unsigned long ulFIFOSize,
+                 unsigned long ulFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulBase == USB0_BASE);
+    ASSERT((ulEndpoint == USB_EP_1) || (ulEndpoint == USB_EP_2) ||
+           (ulEndpoint == USB_EP_3) || (ulEndpoint == USB_EP_4) ||
+           (ulEndpoint == USB_EP_5) || (ulEndpoint == USB_EP_6) ||
+           (ulEndpoint == USB_EP_7) || (ulEndpoint == USB_EP_8) ||
+           (ulEndpoint == USB_EP_9) || (ulEndpoint == USB_EP_10) ||
+           (ulEndpoint == USB_EP_11) || (ulEndpoint == USB_EP_12) ||
+           (ulEndpoint == USB_EP_13) || (ulEndpoint == USB_EP_14) ||
+           (ulEndpoint == USB_EP_15));
+
+    //
+    // See if the transmit or receive FIFO is being configured.
+    //
+    if(ulFlags & (USB_EP_HOST_OUT | USB_EP_DEV_IN))
+    {
+        //
+        // Set the transmit FIFO location and size for this endpoint.
+        //
+        USBIndexWrite(ulBase, ulEndpoint >> 4, USB_O_TXFIFOSZ, ulFIFOSize, 1);
+        USBIndexWrite(ulBase, ulEndpoint >> 4, USB_O_TXFIFOADD,
+                      ulFIFOAddress >> 3, 2);
+    }
+    else
+    {
+        //
+        // Set the receive FIFO location and size for this endpoint.
+        //
+        USBIndexWrite(ulBase, ulEndpoint >> 4, USB_O_RXFIFOSZ, ulFIFOSize, 1);
+        USBIndexWrite(ulBase, ulEndpoint >> 4, USB_O_RXFIFOADD,
+                      ulFIFOAddress >> 3, 2);
+    }
+}
+
+//*****************************************************************************
+//
+//! Returns the FIFO configuration for an endpoint.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint is the endpoint to access.
+//! \param pulFIFOAddress is the starting address for the FIFO.
+//! \param pulFIFOSize is the size of the FIFO in bytes.
+//! \param ulFlags specifies what information to retrieve from the FIFO
+//! configuration.
+//!
+//! This function will return the starting address and size of the FIFO for a
+//! given endpoint.  Endpoint zero does not have a dynamically configurable
+//! FIFO so this function should not be called for endpoint zero.  The
+//! \e ulFlags parameter specifies whether the endpoint's OUT or IN FIFO should
+//! be read.  If in host mode, the \e ulFlags parameter should be
+//! \b USB_EP_HOST_OUT or \b USB_EP_HOST_IN, and if in device mode the
+//! \e ulFlags parameter should be either \b USB_EP_DEV_OUT or
+//! \b USB_EP_DEV_IN.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBFIFOConfigGet(unsigned long ulBase, unsigned long ulEndpoint,
+                 unsigned long *pulFIFOAddress, unsigned long *pulFIFOSize,
+                 unsigned long ulFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulBase == USB0_BASE);
+    ASSERT((ulEndpoint == USB_EP_1) || (ulEndpoint == USB_EP_2) ||
+           (ulEndpoint == USB_EP_3) || (ulEndpoint == USB_EP_4) ||
+           (ulEndpoint == USB_EP_5) || (ulEndpoint == USB_EP_6) ||
+           (ulEndpoint == USB_EP_7) || (ulEndpoint == USB_EP_8) ||
+           (ulEndpoint == USB_EP_9) || (ulEndpoint == USB_EP_10) ||
+           (ulEndpoint == USB_EP_11) || (ulEndpoint == USB_EP_12) ||
+           (ulEndpoint == USB_EP_13) || (ulEndpoint == USB_EP_14) ||
+           (ulEndpoint == USB_EP_15));
+
+    //
+    // See if the transmit or receive FIFO is being configured.
+    //
+    if(ulFlags & (USB_EP_HOST_OUT | USB_EP_DEV_IN))
+    {
+        //
+        // Get the transmit FIFO location and size for this endpoint.
+        //
+        *pulFIFOAddress = (USBIndexRead(ulBase, ulEndpoint >> 4,
+                                        (unsigned long)USB_O_TXFIFOADD,
+                                        2)) << 3;
+        *pulFIFOSize = USBIndexRead(ulBase, ulEndpoint >> 4,
+                                    (unsigned long)USB_O_TXFIFOSZ, 1);
+
+    }
+    else
+    {
+        //
+        // Get the receive FIFO location and size for this endpoint.
+        //
+        *pulFIFOAddress = (USBIndexRead(ulBase, ulEndpoint >> 4,
+                                        (unsigned long)USB_O_RXFIFOADD,
+                                        2)) << 3;
+        *pulFIFOSize = USBIndexRead(ulBase, ulEndpoint >> 4,
+                                    (unsigned long)USB_O_RXFIFOSZ, 1);
+    }
+}
+
+//*****************************************************************************
+//
+//! Enable DMA on a given endpoint.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint is the endpoint to access.
+//! \param ulFlags specifies which direction and what mode to use when enabling
+//! DMA.
+//!
+//! This function will enable DMA on a given endpoint and set the mode
+//! according to the values in the \e ulFlags parameter.  The \e ulFlags
+//! parameter should have \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT set.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBEndpointDMAEnable(unsigned long ulBase, unsigned long ulEndpoint,
+                     unsigned long ulFlags)
+{
+    //
+    // See if the transmit DMA is being enabled.
+    //
+    if(ulFlags & USB_EP_DEV_IN)
+    {
+        //
+        // Enable DMA on the transmit end point.
+        //
+        HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_TXCSRH1) |=
+            USB_TXCSRH1_DMAEN;
+    }
+    else
+    {
+        //
+        // Enable DMA on the receive end point.
+        //
+        HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_RXCSRH1) |=
+            USB_RXCSRH1_DMAEN;
+    }
+}
+
+//*****************************************************************************
+//
+//! Disable DMA on a given endpoint.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint is the endpoint to access.
+//! \param ulFlags specifies which direction to disable.
+//!
+//! This function will disable DMA on a given end point to allow non-DMA
+//! USB transactions to generate interrupts normally.  The ulFlags should be
+//! \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT all other bits are ignored.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBEndpointDMADisable(unsigned long ulBase, unsigned long ulEndpoint,
+                      unsigned long ulFlags)
+{
+    //
+    // If this was a request to disable DMA on the IN portion of the end point
+    // then handle it.
+    //
+    if(ulFlags & USB_EP_DEV_IN)
+    {
+        //
+        // Just disable DMA leave the mode setting.
+        //
+        HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_TXCSRH1) &=
+               ~USB_TXCSRH1_DMAEN;
+    }
+    else
+    {
+        //
+        // Just disable DMA leave the mode setting.
+        //
+        HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_RXCSRH1) &=
+               ~USB_RXCSRH1_DMAEN;
+    }
+}
+
+//*****************************************************************************
+//
+//! Determine the number of bytes of data available in a given endpoint's FIFO.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint is the endpoint to access.
+//!
+//! This function will return the number of bytes of data currently available
+//! in the FIFO for the given receive (OUT) endpoint.  It may be used prior to
+//! calling USBEndpointDataGet() to determine the size of buffer required to
+//! hold the newly-received packet.
+//!
+//! \return This call will return the number of bytes available in a given
+//! endpoint FIFO.
+//
+//*****************************************************************************
+unsigned long
+USBEndpointDataAvail(unsigned long ulBase, unsigned long ulEndpoint)
+{
+    unsigned long ulRegister;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulBase == USB0_BASE);
+    ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) ||
+           (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) ||
+           (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) ||
+           (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) ||
+           (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) ||
+           (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) ||
+           (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) ||
+           (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15));
+
+    //
+    // Get the address of the receive status register to use, based on the
+    // endpoint.
+    //
+    if(ulEndpoint == USB_EP_0)
+    {
+        ulRegister = USB_O_CSRL0;
+    }
+    else
+    {
+        ulRegister = USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint);
+    }
+
+    //
+    // Is there a packet ready in the FIFO?
+    //
+    if((HWREGH(ulBase + ulRegister) & USB_CSRL0_RXRDY) == 0)
+    {
+        return(0);
+    }
+
+    //
+    // Return the byte count in the FIFO.
+    //
+    return(HWREGH(ulBase + USB_O_COUNT0 + ulEndpoint));
+}
+
+//*****************************************************************************
+//
+//! Retrieves data from the given endpoint's FIFO.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint is the endpoint to access.
+//! \param pucData is a pointer to the data area used to return the data from
+//! the FIFO.
+//! \param pulSize is initially the size of the buffer passed into this call
+//! via the \e pucData parameter.  It will be set to the amount of data
+//! returned in the buffer.
+//!
+//! This function will return the data from the FIFO for the given endpoint.
+//! The \e pulSize parameter should indicate the size of the buffer passed in
+//! the \e pulData parameter.  The data in the \e pulSize parameter will be
+//! changed to match the amount of data returned in the \e pucData parameter.
+//! If a zero byte packet was received this call will not return a error but
+//! will instead just return a zero in the \e pulSize parameter.  The only
+//! error case occurs when there is no data packet available.
+//!
+//! \return This call will return 0, or -1 if no packet was received.
+//
+//*****************************************************************************
+long
+USBEndpointDataGet(unsigned long ulBase, unsigned long ulEndpoint,
+                   unsigned char *pucData, unsigned long *pulSize)
+{
+    unsigned long ulRegister, ulByteCount, ulFIFO;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulBase == USB0_BASE);
+    ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) ||
+           (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) ||
+           (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) ||
+           (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) ||
+           (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) ||
+           (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) ||
+           (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) ||
+           (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15));
+
+    //
+    // Get the address of the receive status register to use, based on the
+    // endpoint.
+    //
+    if(ulEndpoint == USB_EP_0)
+    {
+        ulRegister = USB_O_CSRL0;
+    }
+    else
+    {
+        ulRegister = USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint);
+    }
+
+    //
+    // Don't allow reading of data if the RxPktRdy bit is not set.
+    //
+    if((HWREGH(ulBase + ulRegister) & USB_CSRL0_RXRDY) == 0)
+    {
+        //
+        // Can't read the data because none is available.
+        //
+        *pulSize = 0;
+
+        //
+        // Return a failure since there is no data to read.
+        //
+        return(-1);
+    }
+
+    //
+    // Get the byte count in the FIFO.
+    //
+    ulByteCount = HWREGH(ulBase + USB_O_COUNT0 + ulEndpoint);
+
+    //
+    // Determine how many bytes we will actually copy.
+    //
+    ulByteCount = (ulByteCount < *pulSize) ? ulByteCount : *pulSize;
+
+    //
+    // Return the number of bytes we are going to read.
+    //
+    *pulSize = ulByteCount;
+
+    //
+    // Calculate the FIFO address.
+    //
+    ulFIFO = ulBase + USB_O_FIFO0 + (ulEndpoint >> 2);
+
+    //
+    // Read the data out of the FIFO.
+    //
+    for(; ulByteCount > 0; ulByteCount--)
+    {
+        //
+        // Read a byte at a time from the FIFO.
+        //
+        *pucData++ = HWREGB(ulFIFO);
+    }
+
+    //
+    // Success.
+    //
+    return(0);
+}
+
+//*****************************************************************************
+//
+//! Acknowledge that data was read from the given endpoint's FIFO in device
+//! mode.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint is the endpoint to access.
+//! \param bIsLastPacket indicates if this is the last packet.
+//!
+//! This function acknowledges that the data was read from the endpoint's FIFO.
+//! The \e bIsLastPacket parameter is set to a \b true value if this is the
+//! last in a series of data packets on endpoint zero.  The \e bIsLastPacket
+//! parameter is not used for endpoints other than endpoint zero.  This call
+//! can be used if processing is required between reading the data and
+//! acknowledging that the data has been read.
+//!
+//! \note This function should only be called in device mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDevEndpointDataAck(unsigned long ulBase, unsigned long ulEndpoint,
+                      tBoolean bIsLastPacket)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulBase == USB0_BASE);
+    ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) ||
+           (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) ||
+           (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) ||
+           (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) ||
+           (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) ||
+           (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) ||
+           (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) ||
+           (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15));
+
+    //
+    // Determine which endpoint is being acked.
+    //
+    if(ulEndpoint == USB_EP_0)
+    {
+        //
+        // Clear RxPktRdy, and optionally DataEnd, on endpoint zero.
+        //
+        HWREGB(ulBase + USB_O_CSRL0) =
+            USB_CSRL0_RXRDYC | (bIsLastPacket ? USB_CSRL0_DATAEND : 0);
+    }
+    else
+    {
+        //
+        // Clear RxPktRdy on all other endpoints.
+        //
+        HWREGB(ulBase + USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint)) &=
+            ~(USB_RXCSRL1_RXRDY);
+    }
+}
+
+//*****************************************************************************
+//
+//! Acknowledge that data was read from the given endpoint's FIFO in host
+//! mode.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint is the endpoint to access.
+//!
+//! This function acknowledges that the data was read from the endpoint's FIFO.
+//! This call is used if processing is required between reading the data and
+//! acknowledging that the data has been read.
+//!
+//! \note This function should only be called in host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostEndpointDataAck(unsigned long ulBase, unsigned long ulEndpoint)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulBase == USB0_BASE);
+    ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) ||
+           (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) ||
+           (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) ||
+           (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) ||
+           (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) ||
+           (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) ||
+           (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) ||
+           (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15));
+
+    //
+    // Clear RxPktRdy.
+    //
+    if(ulEndpoint == USB_EP_0)
+    {
+        HWREGB(ulBase + USB_O_CSRL0) &= ~USB_CSRL0_RXRDY;
+    }
+    else
+    {
+        HWREGB(ulBase + USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint)) &=
+            ~(USB_RXCSRL1_RXRDY);
+    }
+}
+
+//*****************************************************************************
+//
+//! Puts data into the given endpoint's FIFO.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint is the endpoint to access.
+//! \param pucData is a pointer to the data area used as the source for the
+//! data to put into the FIFO.
+//! \param ulSize is the amount of data to put into the FIFO.
+//!
+//! This function will put the data from the \e pucData parameter into the FIFO
+//! for this endpoint.  If a packet is already pending for transmission then
+//! this call will not put any of the data into the FIFO and will return -1.
+//! Care should be taken to not write more data than can fit into the FIFO
+//! allocated by the call to USBFIFOConfigSet().
+//!
+//! \return This call will return 0 on success, or -1 to indicate that the FIFO
+//! is in use and cannot be written.
+//
+//*****************************************************************************
+long
+USBEndpointDataPut(unsigned long ulBase, unsigned long ulEndpoint,
+                   unsigned char *pucData, unsigned long ulSize)
+{
+    unsigned long ulFIFO;
+    unsigned char ucTxPktRdy;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulBase == USB0_BASE);
+    ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) ||
+           (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) ||
+           (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) ||
+           (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) ||
+           (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) ||
+           (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) ||
+           (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) ||
+           (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15));
+
+    //
+    // Get the bit position of TxPktRdy based on the endpoint.
+    //
+    if(ulEndpoint == USB_EP_0)
+    {
+        ucTxPktRdy = USB_CSRL0_TXRDY;
+    }
+    else
+    {
+        ucTxPktRdy = USB_TXCSRL1_TXRDY;
+    }
+
+    //
+    // Don't allow transmit of data if the TxPktRdy bit is already set.
+    //
+    if(HWREGB(ulBase + USB_O_CSRL0 + ulEndpoint) & ucTxPktRdy)
+    {
+        return(-1);
+    }
+
+    //
+    // Calculate the FIFO address.
+    //
+    ulFIFO = ulBase + USB_O_FIFO0 + (ulEndpoint >> 2);
+
+    //
+    // Write the data to the FIFO.
+    //
+    for(; ulSize > 0; ulSize--)
+    {
+        HWREGB(ulFIFO) = *pucData++;
+    }
+
+    //
+    // Success.
+    //
+    return(0);
+}
+
+//*****************************************************************************
+//
+//! Starts the transfer of data from an endpoint's FIFO.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint is the endpoint to access.
+//! \param ulTransType is set to indicate what type of data is being sent.
+//!
+//! This function will start the transfer of data from the FIFO for a given
+//! endpoint.  This is necessary if the \b USB_EP_AUTO_SET bit was not enabled
+//! for the endpoint.  Setting the \e ulTransType parameter will allow the
+//! appropriate signaling on the USB bus for the type of transaction being
+//! requested.  The \e ulTransType parameter should be one of the following:
+//!
+//! - USB_TRANS_OUT for OUT transaction on any endpoint in host mode.
+//! - USB_TRANS_IN for IN transaction on any endpoint in device mode.
+//! - USB_TRANS_IN_LAST for the last IN transactions on endpoint zero in a
+//!   sequence of IN transactions.
+//! - USB_TRANS_SETUP for setup transactions on endpoint zero.
+//! - USB_TRANS_STATUS for status results on endpoint zero.
+//!
+//! \return This call will return 0 on success, or -1 if a transmission is
+//! already in progress.
+//
+//*****************************************************************************
+long
+USBEndpointDataSend(unsigned long ulBase, unsigned long ulEndpoint,
+                    unsigned long ulTransType)
+{
+    unsigned long ulTxPktRdy;
+
+    //
+    // CHeck the arguments.
+    //
+    ASSERT(ulBase == USB0_BASE);
+    ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) ||
+           (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) ||
+           (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) ||
+           (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) ||
+           (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) ||
+           (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) ||
+           (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) ||
+           (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15));
+
+    //
+    // Get the bit position of TxPktRdy based on the endpoint.
+    //
+    if(ulEndpoint == USB_EP_0)
+    {
+        ulTxPktRdy = ulTransType & 0xff;
+    }
+    else
+    {
+        ulTxPktRdy = (ulTransType >> 8) & 0xff;
+    }
+
+    //
+    // Don't allow transmit of data if the TxPktRdy bit is already set.
+    //
+    if(HWREGB(ulBase + USB_O_CSRL0 + ulEndpoint) & USB_CSRL0_TXRDY)
+    {
+        return(-1);
+    }
+
+    //
+    // Set TxPktRdy in order to send the data.
+    //
+    HWREGB(ulBase + USB_O_CSRL0 + ulEndpoint) = ulTxPktRdy;
+
+    //
+    // Success.
+    //
+    return(0);
+}
+
+//*****************************************************************************
+//
+//! Forces a flush of an endpoint's FIFO.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint is the endpoint to access.
+//! \param ulFlags specifies if the IN or OUT endpoint should be accessed.
+//!
+//! This function will force the controller to flush out the data in the FIFO.
+//! The function can be called with either host or device controllers and
+//! requires the \e ulFlags parameter be one of \b USB_EP_HOST_OUT,
+//! \b USB_EP_HOST_IN, \b USB_EP_DEV_OUT, or \b USB_EP_DEV_IN.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBFIFOFlush(unsigned long ulBase, unsigned long ulEndpoint,
+             unsigned long ulFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulBase == USB0_BASE);
+    ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) ||
+           (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) ||
+           (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) ||
+           (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) ||
+           (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) ||
+           (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) ||
+           (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) ||
+           (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15));
+
+    //
+    // Endpoint zero has a different register set for FIFO flushing.
+    //
+    if(ulEndpoint == USB_EP_0)
+    {
+        //
+        // Nothing in the FIFO if neither of these bits are set.
+        //
+        if((HWREGB(ulBase + USB_O_CSRL0) &
+            (USB_CSRL0_RXRDY | USB_CSRL0_TXRDY)) != 0)
+        {
+            //
+            // Hit the Flush FIFO bit.
+            //
+            HWREGB(ulBase + USB_O_CSRH0) = USB_CSRH0_FLUSH;
+        }
+    }
+    else
+    {
+        //
+        // Only reset the IN or OUT FIFO.
+        //
+        if(ulFlags & (USB_EP_HOST_OUT | USB_EP_DEV_IN))
+        {
+            //
+            // Make sure the FIFO is not empty.
+            //
+            if(HWREGB(ulBase + USB_O_TXCSRL1 + EP_OFFSET(ulEndpoint)) &
+               USB_TXCSRL1_TXRDY)
+            {
+                //
+                // Hit the Flush FIFO bit.
+                //
+                HWREGB(ulBase + USB_O_TXCSRL1 + EP_OFFSET(ulEndpoint)) |=
+                    USB_TXCSRL1_FLUSH;
+            }
+        }
+        else
+        {
+            //
+            // Make sure that the FIFO is not empty.
+            //
+            if(HWREGB(ulBase + USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint)) &
+               USB_RXCSRL1_RXRDY)
+            {
+                //
+                // Hit the Flush FIFO bit.
+                //
+                HWREGB(ulBase + USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint)) |=
+                    USB_RXCSRL1_FLUSH;
+            }
+        }
+    }
+}
+
+//*****************************************************************************
+//
+//! Schedules a request for an IN transaction on an endpoint in host mode.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint is the endpoint to access.
+//!
+//! This function will schedule a request for an IN transaction.  When the USB
+//! device being communicated with responds the data, the data can be retrieved
+//! by calling USBEndpointDataGet() or via a DMA transfer.
+//!
+//! \note This function should only be called in host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostRequestIN(unsigned long ulBase, unsigned long ulEndpoint)
+{
+    unsigned long ulRegister;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulBase == USB0_BASE);
+    ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) ||
+           (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) ||
+           (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) ||
+           (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) ||
+           (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) ||
+           (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) ||
+           (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) ||
+           (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15));
+
+    //
+    // Endpoint zero uses a different offset than the other endpoints.
+    //
+    if(ulEndpoint == USB_EP_0)
+    {
+        ulRegister = USB_O_CSRL0;
+    }
+    else
+    {
+        ulRegister = USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint);
+    }
+
+    //
+    // Set the request for an IN transaction.
+    //
+    HWREGB(ulBase + ulRegister) = USB_RXCSRL1_REQPKT;
+}
+
+//*****************************************************************************
+//
+//! Issues a request for a status IN transaction on endpoint zero.
+//!
+//! \param ulBase specifies the USB module base address.
+//!
+//! This function is used to cause a request for an status IN transaction from
+//! a device on endpoint zero.  This function can only be used with endpoint
+//! zero as that is the only control endpoint that supports this ability.  This
+//! is used to complete the last phase of a control transaction to a device and
+//! an interrupt will be signaled when the status packet has been received.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostRequestStatus(unsigned long ulBase)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulBase == USB0_BASE);
+
+    //
+    // Set the request for a status IN transaction.
+    //
+    HWREGB(ulBase + USB_O_CSRL0) = USB_CSRL0_REQPKT | USB_CSRL0_STATUS;
+}
+
+//*****************************************************************************
+//
+//! Sets the functional address for the device that is connected to an
+//! endpoint in host mode.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint is the endpoint to access.
+//! \param ulAddr is the functional address for the controller to use for this
+//! endpoint.
+//! \param ulFlags determines if this is an IN or an OUT endpoint.
+//!
+//! This function will set the functional address for a device that is using
+//! this endpoint for communication.  This \e ulAddr parameter is the address
+//! of the target device that this endpoint will be used to communicate with.
+//! The \e ulFlags parameter indicates if the IN or OUT endpoint should be set.
+//!
+//! \note This function should only be called in host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostAddrSet(unsigned long ulBase, unsigned long ulEndpoint,
+               unsigned long ulAddr, unsigned long ulFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulBase == USB0_BASE);
+    ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) ||
+           (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) ||
+           (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) ||
+           (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) ||
+           (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) ||
+           (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) ||
+           (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) ||
+           (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15));
+
+    //
+    // See if the transmit or receive address should be set.
+    //
+    if(ulFlags & USB_EP_HOST_OUT)
+    {
+        //
+        // Set the transmit address.
+        //
+        HWREGB(ulBase + USB_O_TXFUNCADDR0 + (ulEndpoint >> 1)) = ulAddr;
+    }
+    else
+    {
+        //
+        // Set the receive address.
+        //
+        HWREGB(ulBase + USB_O_TXFUNCADDR0 + 4 + (ulEndpoint >> 1)) = ulAddr;
+    }
+}
+
+//*****************************************************************************
+//
+//! Gets the current functional device address for an endpoint.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint is the endpoint to access.
+//! \param ulFlags determines if this is an IN or an OUT endpoint.
+//!
+//! This function returns the current functional address that an endpoint is
+//! using to communicate with a device.  The \e ulFlags parameter determines if
+//! the IN or OUT endpoint's device address is returned.
+//!
+//! \note This function should only be called in host mode.
+//!
+//! \return Returns the current function address being used by an endpoint.
+//
+//*****************************************************************************
+unsigned long
+USBHostAddrGet(unsigned long ulBase, unsigned long ulEndpoint,
+               unsigned long ulFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulBase == USB0_BASE);
+    ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) ||
+           (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) ||
+           (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) ||
+           (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) ||
+           (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) ||
+           (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) ||
+           (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) ||
+           (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15));
+
+    //
+    // See if the transmit or receive address should be returned.
+    //
+    if(ulFlags & USB_EP_HOST_OUT)
+    {
+        //
+        // Return this endpoint's transmit address.
+        //
+        return(HWREGB(ulBase + USB_O_TXFUNCADDR0 + (ulEndpoint >> 1)));
+    }
+    else
+    {
+        //
+        // Return this endpoint's receive address.
+        //
+        return(HWREGB(ulBase + USB_O_TXFUNCADDR0 + 4 + (ulEndpoint >> 1)));
+    }
+}
+
+//*****************************************************************************
+//
+//! Set the hub address for the device that is connected to an endpoint.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint is the endpoint to access.
+//! \param ulAddr is the hub address for the device using this endpoint.
+//! \param ulFlags determines if this is an IN or an OUT endpoint.
+//!
+//! This function will set the hub address for a device that is using this
+//! endpoint for communication.  The \e ulFlags parameter determines if the
+//! device address for the IN or the OUT endpoint is set by this call.
+//!
+//! \note This function should only be called in host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostHubAddrSet(unsigned long ulBase, unsigned long ulEndpoint,
+                  unsigned long ulAddr, unsigned long ulFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulBase == USB0_BASE);
+    ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) ||
+           (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) ||
+           (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) ||
+           (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) ||
+           (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) ||
+           (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) ||
+           (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) ||
+           (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15));
+
+    //
+    // See if the hub transmit or receive address is being set.
+    //
+    if(ulFlags & USB_EP_HOST_OUT)
+    {
+        //
+        // Set the hub transmit address for this endpoint.
+        //
+        HWREGB(ulBase + USB_O_TXHUBADDR0 + (ulEndpoint >> 1)) = ulAddr;
+    }
+    else
+    {
+        //
+        // Set the hub receive address for this endpoint.
+        //
+        HWREGB(ulBase + USB_O_TXHUBADDR0 + 4 + (ulEndpoint >> 1)) = ulAddr;
+    }
+}
+
+//*****************************************************************************
+//
+//! Get the current device hub address for this endpoint.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint is the endpoint to access.
+//! \param ulFlags determines if this is an IN or an OUT endpoint.
+//!
+//! This function will return the current hub address that an endpoint is using
+//! to communicate with a device.  The \e ulFlags parameter determines if the
+//! device address for the IN or OUT endpoint is returned.
+//!
+//! \note This function should only be called in host mode.
+//!
+//! \return This function returns the current hub address being used by an
+//! endpoint.
+//
+//*****************************************************************************
+unsigned long
+USBHostHubAddrGet(unsigned long ulBase, unsigned long ulEndpoint,
+                  unsigned long ulFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulBase == USB0_BASE);
+    ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) ||
+           (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) ||
+           (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) ||
+           (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) ||
+           (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) ||
+           (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) ||
+           (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) ||
+           (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15));
+
+    //
+    // See if the hub transmit or receive address should be returned.
+    //
+    if(ulFlags & USB_EP_HOST_OUT)
+    {
+        //
+        // Return the hub transmit address for this endpoint.
+        //
+        return(HWREGB(ulBase + USB_O_TXHUBADDR0 + (ulEndpoint >> 1)));
+    }
+    else
+    {
+        //
+        // Return the hub receive address for this endpoint.
+        //
+        return(HWREGB(ulBase + USB_O_TXHUBADDR0 + 4 + (ulEndpoint >> 1)));
+    }
+}
+
+//*****************************************************************************
+//
+//! Sets the configuration for USB power fault.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulFlags specifies the configuration of the power fault.
+//!
+//! This function controls how the USB controller uses its external power
+//! control pins (USBnPFTL and USBnEPEN).  The flags specify the power
+//! fault level sensitivity, the power fault action, and the power enable level
+//! and source.
+//!
+//! One of the following can be selected as the power fault level sensitivity:
+//!
+//! - \b USB_HOST_PWRFLT_LOW - An external power fault is indicated by the pin
+//!                            being driven low.
+//! - \b USB_HOST_PWRFLT_HIGH - An external power fault is indicated by the pin
+//!                             being driven high.
+//!
+//! One of the following can be selected as the power fault action:
+//!
+//! - \b USB_HOST_PWRFLT_EP_NONE - No automatic action when power fault
+//!   detected.
+//! - \b USB_HOST_PWRFLT_EP_TRI - Automatically Tri-state the USBnEPEN pin on a
+//!                               power fault.
+//! - \b USB_HOST_PWRFLT_EP_LOW - Automatically drive USBnEPEN pin low on a
+//!                               power fault.
+//! - \b USB_HOST_PWRFLT_EP_HIGH - Automatically drive USBnEPEN pin high on a
+//!                                power fault.
+//!
+//! One of the following can be selected as the power enable level and source:
+//!
+//! - \b USB_HOST_PWREN_MAN_LOW - USBEPEN is driven low by the USB controller
+//!                               when USBHostPwrEnable() is called.
+//! - \b USB_HOST_PWREN_MAN_HIGH - USBEPEN is driven high by the USB controller
+//!                                when USBHostPwrEnable() is called.
+//! - \b USB_HOST_PWREN_AUTOLOW - USBEPEN is driven low by the USB controller
+//!                               automatically if USBOTGSessionRequest() has
+//!                               enabled a session.
+//! - \b USB_HOST_PWREN_AUTOHIGH - USBEPEN is driven high by the USB controller
+//!                                automatically if USBOTGSessionRequest() has
+//!                                enabled a session.
+//!
+//! On devices that support the VBUS glitch filter, the
+//! \b USB_HOST_PWREN_FILTER can be added to ignore small, short drops in VBUS
+//! level caused by high power consumption.  This is mainly used to avoid
+//! causing VBUS errors caused by devices with high in-rush current.
+//!
+//! \note The following values have been deprecated and should no longer be
+//!       used.
+//! - \b USB_HOST_PWREN_LOW - Automatically drive USBnEPEN low when power is
+//!                           enabled.
+//! - \b USB_HOST_PWREN_HIGH - Automatically drive USBnEPEN high when power is
+//!                            enabled.
+//! - \b USB_HOST_PWREN_VBLOW - Automatically drive USBnEPEN low when power is
+//!                             enabled.
+//! - \b USB_HOST_PWREN_VBHIGH - Automatically drive USBnEPEN high when power is
+//!                              enabled.
+//!
+//! \note This function should only be called on microcontrollers that support
+//! host mode or OTG operation.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostPwrConfig(unsigned long ulBase, unsigned long ulFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulBase == USB0_BASE);
+    ASSERT((ulFlags & ~(USB_HOST_PWREN_FILTER | USB_EPC_PFLTACT_M |
+                        USB_EPC_PFLTAEN | USB_EPC_PFLTSEN_HIGH |
+                        USB_EPC_EPEN_M)) == 0);
+
+    //
+    // If requested, enable VBUS droop detection on parts that support this
+    // feature.
+    //
+    HWREG(ulBase + USB_O_VDC) = ulFlags >> 16;
+
+    //
+    // Set the power fault configuration as specified.  This will not change
+    // whether fault detection is enabled or not.
+    //
+    HWREGH(ulBase + USB_O_EPC) =
+        (ulFlags | (HWREGH(ulBase + USB_O_EPC) &
+                    ~(USB_EPC_PFLTACT_M | USB_EPC_PFLTAEN |
+                      USB_EPC_PFLTSEN_HIGH | USB_EPC_EPEN_M)));
+}
+
+//*****************************************************************************
+//
+//! Enables power fault detection.
+//!
+//! \param ulBase specifies the USB module base address.
+//!
+//! This function enables power fault detection in the USB controller.  If the
+//! USBPFLT pin is not in use this function should not be used.
+//!
+//! \note This function should only be called in host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostPwrFaultEnable(unsigned long ulBase)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulBase == USB0_BASE);
+
+    //
+    // Enable power fault input.
+    //
+    HWREGH(ulBase + USB_O_EPC) |= USB_EPC_PFLTEN;
+}
+
+//*****************************************************************************
+//
+//! Disables power fault detection.
+//!
+//! \param ulBase specifies the USB module base address.
+//!
+//! This function disables power fault detection in the USB controller.
+//!
+//! \note This function should only be called in host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostPwrFaultDisable(unsigned long ulBase)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulBase == USB0_BASE);
+
+    //
+    // Enable power fault input.
+    //
+    HWREGH(ulBase + USB_O_EPC) &= ~USB_EPC_PFLTEN;
+}
+
+//*****************************************************************************
+//
+//! Enables the external power pin.
+//!
+//! \param ulBase specifies the USB module base address.
+//!
+//! This function enables the USBEPEN signal to enable an external power supply
+//! in host mode operation.
+//!
+//! \note This function should only be called in host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostPwrEnable(unsigned long ulBase)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulBase == USB0_BASE);
+
+    //
+    // Enable the external power supply enable signal.
+    //
+    HWREGH(ulBase + USB_O_EPC) |= USB_EPC_EPENDE;
+}
+
+//*****************************************************************************
+//
+//! Disables the external power pin.
+//!
+//! \param ulBase specifies the USB module base address.
+//!
+//! This function disables the USBEPEN signal to disable an external power
+//! supply in host mode operation.
+//!
+//! \note This function should only be called in host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostPwrDisable(unsigned long ulBase)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulBase == USB0_BASE);
+
+    //
+    // Disable the external power supply enable signal.
+    //
+    HWREGH(ulBase + USB_O_EPC) &= ~USB_EPC_EPENDE;
+}
+
+//*****************************************************************************
+//
+//! Get the current frame number.
+//!
+//! \param ulBase specifies the USB module base address.
+//!
+//! This function returns the last frame number received.
+//!
+//! \return The last frame number received.
+//
+//*****************************************************************************
+unsigned long
+USBFrameNumberGet(unsigned long ulBase)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulBase == USB0_BASE);
+
+    //
+    // Return the most recent frame number.
+    //
+    return(HWREGH(ulBase + USB_O_FRAME));
+}
+
+//*****************************************************************************
+//
+//! Starts or ends a session.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param bStart specifies if this call starts or ends a session.
+//!
+//! This function is used in OTG mode to start a session request or end a
+//! session.  If the \e bStart parameter is set to \b true, then this function
+//! start a session and if it is \b false it will end a session.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBOTGSessionRequest(unsigned long ulBase, tBoolean bStart)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulBase == USB0_BASE);
+
+    //
+    // Start or end the session as directed.
+    //
+    if(bStart)
+    {
+        HWREGB(ulBase + USB_O_DEVCTL) |= USB_DEVCTL_SESSION;
+    }
+    else
+    {
+        HWREGB(ulBase + USB_O_DEVCTL) &= ~USB_DEVCTL_SESSION;
+    }
+}
+
+//*****************************************************************************
+//
+//! Returns the absolute FIFO address for a given endpoint.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint specifies which endpoint's FIFO address to return.
+//!
+//! This function returns the actual physical address of the FIFO.  This is
+//! needed when the USB is going to be used with the uDMA controller and the
+//! source or destination address needs to be set to the physical FIFO address
+//! for a given endpoint.
+//!
+//! \return None.
+//
+//*****************************************************************************
+unsigned long
+USBFIFOAddrGet(unsigned long ulBase, unsigned long ulEndpoint)
+{
+    //
+    // Return the FIFO address for this endpoint.
+    //
+    return(ulBase + USB_O_FIFO0 + (ulEndpoint >> 2));
+}
+
+//*****************************************************************************
+//
+//! Returns the current operating mode of the controller.
+//!
+//! \param ulBase specifies the USB module base address.
+//!
+//! This function returns the current operating mode on USB controllers with
+//! OTG or Dual mode functionality.
+//!
+//! For OTG controllers:
+//!
+//! The function will return on of the following values on OTG controllers:
+//! \b USB_OTG_MODE_ASIDE_HOST, \b USB_OTG_MODE_ASIDE_DEV,
+//! \b USB_OTG_MODE_BSIDE_HOST, \b USB_OTG_MODE_BSIDE_DEV,
+//! \b USB_OTG_MODE_NONE.
+//!
+//! \b USB_OTG_MODE_ASIDE_HOST indicates that the controller is in host mode
+//! on the A-side of the cable.
+//!
+//! \b USB_OTG_MODE_ASIDE_DEV indicates that the controller is in device mode
+//! on the A-side of the cable.
+//!
+//! \b USB_OTG_MODE_BSIDE_HOST indicates that the controller is in host mode
+//! on the B-side of the cable.
+//!
+//! \b USB_OTG_MODE_BSIDE_DEV indicates that the controller is in device mode
+//! on the B-side of the cable.  If and OTG session request is started with no
+//! cable in place this is the default mode for the controller.
+//!
+//! \b USB_OTG_MODE_NONE indicates that the controller is not attempting to
+//! determine its role in the system.
+//!
+//! For Dual Mode controllers:
+//!
+//! The function will return on of the following values:
+//! \b USB_DUAL_MODE_HOST, \b USB_DUAL_MODE_DEVICE, or
+//! \b USB_DUAL_MODE_NONE.
+//!
+//! \b USB_DUAL_MODE_HOST indicates that the controller is acting as a host.
+//!
+//! \b USB_DUAL_MODE_DEVICE indicates that the controller acting as a device.
+//!
+//! \b USB_DUAL_MODE_NONE indicates that the controller is not active as
+//! either a host or device.
+//!
+//! \return Returns \b USB_OTG_MODE_ASIDE_HOST, \b USB_OTG_MODE_ASIDE_DEV,
+//! \b USB_OTG_MODE_BSIDE_HOST, \b USB_OTG_MODE_BSIDE_DEV,
+//! \b USB_OTG_MODE_NONE, \b USB_DUAL_MODE_HOST, \b USB_DUAL_MODE_DEVICE, or
+//! \b USB_DUAL_MODE_NONE.
+//
+//*****************************************************************************
+unsigned long
+USBModeGet(unsigned long ulBase)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulBase == USB0_BASE);
+
+    //
+    // Checks the current mode in the USB_O_DEVCTL and returns the current
+    // mode.
+    //
+    // USB_OTG_MODE_ASIDE_HOST:  USB_DEVCTL_HOST | USB_DEVCTL_SESSION
+    // USB_OTG_MODE_ASIDE_DEV:   USB_DEVCTL_SESSION
+    // USB_OTG_MODE_BSIDE_HOST:  USB_DEVCTL_DEV | USB_DEVCTL_SESSION |
+    //                           USB_DEVCTL_HOST
+    // USB_OTG_MODE_BSIDE_DEV:   USB_DEVCTL_DEV | USB_DEVCTL_SESSION
+    // USB_OTG_MODE_NONE:        USB_DEVCTL_DEV
+    //
+    return(HWREGB(ulBase + USB_O_DEVCTL) &
+           (USB_DEVCTL_DEV | USB_DEVCTL_HOST | USB_DEVCTL_SESSION |
+            USB_DEVCTL_VBUS_M));
+}
+
+//*****************************************************************************
+//
+//! Sets the DMA channel to use for a given endpoint.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint specifies which endpoint's FIFO address to return.
+//! \param ulChannel specifies which DMA channel to use for which endpoint.
+//!
+//! This function is used to configure which DMA channel to use with a given
+//! endpoint.  Receive DMA channels can only be used with receive endpoints
+//! and transmit DMA channels can only be used with transmit endpoints.  This
+//! allows the 3 receive and 3 transmit DMA channels to be mapped to any
+//! endpoint other than 0.  The values that should be passed into the
+//! \e ulChannel value are the UDMA_CHANNEL_USBEP* values defined in udma.h.
+//!
+//! \note This function only has an effect on microcontrollers that have the
+//! ability to change the DMA channel for an endpoint.  Calling this function
+//! on other devices will have no effect.
+//!
+//! \return None.
+//!
+//*****************************************************************************
+void
+USBEndpointDMAChannel(unsigned long ulBase, unsigned long ulEndpoint,
+                      unsigned long ulChannel)
+{
+    unsigned long ulMask;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulBase == USB0_BASE);
+    ASSERT((ulEndpoint == USB_EP_1) || (ulEndpoint == USB_EP_2) ||
+           (ulEndpoint == USB_EP_3) || (ulEndpoint == USB_EP_4) ||
+           (ulEndpoint == USB_EP_5) || (ulEndpoint == USB_EP_6) ||
+           (ulEndpoint == USB_EP_7) || (ulEndpoint == USB_EP_8) ||
+           (ulEndpoint == USB_EP_9) || (ulEndpoint == USB_EP_10) ||
+           (ulEndpoint == USB_EP_11) || (ulEndpoint == USB_EP_12) ||
+           (ulEndpoint == USB_EP_13) || (ulEndpoint == USB_EP_14) ||
+           (ulEndpoint == USB_EP_15));
+    ASSERT(ulChannel <= UDMA_CHANNEL_USBEP3TX);
+
+    //
+    // The input select mask needs to be shifted into the correct position
+    // based on the channel.
+    //
+    ulMask = 0xf << (ulChannel * 4);
+
+    //
+    // Clear out the current selection for the channel.
+    //
+    ulMask = HWREG(ulBase + USB_O_DMASEL) & (~ulMask);
+
+    //
+    // The input select is now shifted into the correct position based on the
+    // channel.
+    //
+    ulMask |= (USB_EP_TO_INDEX(ulEndpoint)) << (ulChannel * 4);
+
+    //
+    // Write the value out to the register.
+    //
+    HWREG(ulBase + USB_O_DMASEL) = ulMask;
+}
+
+//*****************************************************************************
+//
+//! Change the mode of the USB controller to host.
+//!
+//! \param ulBase specifies the USB module base address.
+//!
+//! This function changes the mode of the USB controller to host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostMode(unsigned long ulBase)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulBase == USB0_BASE);
+
+    //
+    // Force mode in OTG parts that support forcing USB controller mode.
+    // This bit is not writable in USB controllers that do not support
+    // forcing the mode.  Not setting the USB_GPCS_DEVMOD bit makes this a
+    // force of host mode.
+    //
+    HWREGB(ulBase + USB_O_GPCS) = USB_GPCS_DEVMODOTG;
+}
+
+//*****************************************************************************
+//
+//! Change the mode of the USB controller to device.
+//!
+//! \param ulBase specifies the USB module base address.
+//!
+//! This function changes the mode of the USB controller to device mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDevMode(unsigned long ulBase)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulBase == USB0_BASE);
+
+    //
+    // Set the USB controller mode to device.
+    //
+    HWREGB(ulBase + USB_O_GPCS) = USB_GPCS_DEVMODOTG | USB_GPCS_DEVMOD;
+}
+
+//*****************************************************************************
+//
+//! Change the mode of the USB controller to OTG.
+//!
+//! \param ulBase specifies the USB module base address.
+//!
+//! This function changes the mode of the USB controller to OTG mode.  This
+//! is only valid on microcontrollers that have the OTG capabilities.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBOTGMode(unsigned long ulBase)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulBase == USB0_BASE);
+
+    //
+    // Disable the override of the USB controller mode when running on an OTG
+    // device.
+    //
+    HWREGB(ulBase + USB_O_GPCS) = 0;
+}
+
+//*****************************************************************************
+//
+//! Powers off the USB PHY.
+//!
+//! \param ulBase specifies the USB module base address.
+//!
+//! This function will power off the USB PHY, reducing the current consuption
+//! of the device.  While in the powered off state, the USB controller will be
+//! unable to operate.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBPHYPowerOff(unsigned long ulBase)
+{
+    //
+    // Set the PWRDNPHY bit in the PHY, putting it into its low power mode.
+    //
+    HWREGB(ulBase + USB_O_POWER) |= USB_POWER_PWRDNPHY;
+}
+
+//*****************************************************************************
+//
+//! Powers on the USB PHY.
+//!
+//! \param ulBase specifies the USB module base address.
+//!
+//! This function will power on the USB PHY, enabling it return to normal
+//! operation.  By default, the PHY is powered on, so this function only needs
+//! to be called if USBPHYPowerOff() has previously been called.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBPHYPowerOn(unsigned long ulBase)
+{
+    //
+    // Clear the PWRDNPHY bit in the PHY, putting it into normal operating
+    // mode.
+    //
+    HWREGB(ulBase + USB_O_POWER) &= ~USB_POWER_PWRDNPHY;
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/src/platform/lm3s/driverlib/usb.h b/src/platform/lm3s/driverlib/usb.h
new file mode 100755
index 00000000..bdf3c831
--- /dev/null
+++ b/src/platform/lm3s/driverlib/usb.h
@@ -0,0 +1,569 @@
+//*****************************************************************************
+//
+// usb.h - Prototypes for the USB Interface Driver.
+//
+// Copyright (c) 2007-2011 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 7611 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __USB_H__
+#define __USB_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// The following are values that can be passed to USBIntEnableControl() and
+// USBIntDisableControl() as the ulFlags parameter, and are returned from
+// USBIntStatusControl().
+//
+//*****************************************************************************
+#define USB_INTCTRL_ALL         0x000003FF  // All control interrupt sources
+#define USB_INTCTRL_STATUS      0x000000FF  // Status Interrupts
+#define USB_INTCTRL_VBUS_ERR    0x00000080  // VBUS Error
+#define USB_INTCTRL_SESSION     0x00000040  // Session Start Detected
+#define USB_INTCTRL_SESSION_END 0x00000040  // Session End Detected
+#define USB_INTCTRL_DISCONNECT  0x00000020  // Disconnect Detected
+#define USB_INTCTRL_CONNECT     0x00000010  // Device Connect Detected
+#define USB_INTCTRL_SOF         0x00000008  // Start of Frame Detected
+#define USB_INTCTRL_BABBLE      0x00000004  // Babble signaled
+#define USB_INTCTRL_RESET       0x00000004  // Reset signaled
+#define USB_INTCTRL_RESUME      0x00000002  // Resume detected
+#define USB_INTCTRL_SUSPEND     0x00000001  // Suspend detected
+#define USB_INTCTRL_MODE_DETECT 0x00000200  // Mode value valid
+#define USB_INTCTRL_POWER_FAULT 0x00000100  // Power Fault detected
+
+//*****************************************************************************
+//
+// The following are values that can be passed to USBIntEnableEndpoint() and
+// USBIntDisableEndpoint() as the ulFlags parameter, and are returned from
+// USBIntStatusEndpoint().
+//
+//*****************************************************************************
+#define USB_INTEP_ALL           0xFFFFFFFF  // Host IN Interrupts
+#define USB_INTEP_HOST_IN       0xFFFE0000  // Host IN Interrupts
+#define USB_INTEP_HOST_IN_15    0x80000000  // Endpoint 15 Host IN Interrupt
+#define USB_INTEP_HOST_IN_14    0x40000000  // Endpoint 14 Host IN Interrupt
+#define USB_INTEP_HOST_IN_13    0x20000000  // Endpoint 13 Host IN Interrupt
+#define USB_INTEP_HOST_IN_12    0x10000000  // Endpoint 12 Host IN Interrupt
+#define USB_INTEP_HOST_IN_11    0x08000000  // Endpoint 11 Host IN Interrupt
+#define USB_INTEP_HOST_IN_10    0x04000000  // Endpoint 10 Host IN Interrupt
+#define USB_INTEP_HOST_IN_9     0x02000000  // Endpoint 9 Host IN Interrupt
+#define USB_INTEP_HOST_IN_8     0x01000000  // Endpoint 8 Host IN Interrupt
+#define USB_INTEP_HOST_IN_7     0x00800000  // Endpoint 7 Host IN Interrupt
+#define USB_INTEP_HOST_IN_6     0x00400000  // Endpoint 6 Host IN Interrupt
+#define USB_INTEP_HOST_IN_5     0x00200000  // Endpoint 5 Host IN Interrupt
+#define USB_INTEP_HOST_IN_4     0x00100000  // Endpoint 4 Host IN Interrupt
+#define USB_INTEP_HOST_IN_3     0x00080000  // Endpoint 3 Host IN Interrupt
+#define USB_INTEP_HOST_IN_2     0x00040000  // Endpoint 2 Host IN Interrupt
+#define USB_INTEP_HOST_IN_1     0x00020000  // Endpoint 1 Host IN Interrupt
+
+#define USB_INTEP_DEV_OUT       0xFFFE0000  // Device OUT Interrupts
+#define USB_INTEP_DEV_OUT_15    0x80000000  // Endpoint 15 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_14    0x40000000  // Endpoint 14 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_13    0x20000000  // Endpoint 13 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_12    0x10000000  // Endpoint 12 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_11    0x08000000  // Endpoint 11 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_10    0x04000000  // Endpoint 10 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_9     0x02000000  // Endpoint 9 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_8     0x01000000  // Endpoint 8 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_7     0x00800000  // Endpoint 7 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_6     0x00400000  // Endpoint 6 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_5     0x00200000  // Endpoint 5 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_4     0x00100000  // Endpoint 4 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_3     0x00080000  // Endpoint 3 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_2     0x00040000  // Endpoint 2 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_1     0x00020000  // Endpoint 1 Device OUT Interrupt
+
+#define USB_INTEP_HOST_OUT      0x0000FFFE  // Host OUT Interrupts
+#define USB_INTEP_HOST_OUT_15   0x00008000  // Endpoint 15 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_14   0x00004000  // Endpoint 14 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_13   0x00002000  // Endpoint 13 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_12   0x00001000  // Endpoint 12 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_11   0x00000800  // Endpoint 11 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_10   0x00000400  // Endpoint 10 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_9    0x00000200  // Endpoint 9 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_8    0x00000100  // Endpoint 8 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_7    0x00000080  // Endpoint 7 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_6    0x00000040  // Endpoint 6 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_5    0x00000020  // Endpoint 5 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_4    0x00000010  // Endpoint 4 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_3    0x00000008  // Endpoint 3 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_2    0x00000004  // Endpoint 2 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_1    0x00000002  // Endpoint 1 Host OUT Interrupt
+
+#define USB_INTEP_DEV_IN        0x0000FFFE  // Device IN Interrupts
+#define USB_INTEP_DEV_IN_15     0x00008000  // Endpoint 15 Device IN Interrupt
+#define USB_INTEP_DEV_IN_14     0x00004000  // Endpoint 14 Device IN Interrupt
+#define USB_INTEP_DEV_IN_13     0x00002000  // Endpoint 13 Device IN Interrupt
+#define USB_INTEP_DEV_IN_12     0x00001000  // Endpoint 12 Device IN Interrupt
+#define USB_INTEP_DEV_IN_11     0x00000800  // Endpoint 11 Device IN Interrupt
+#define USB_INTEP_DEV_IN_10     0x00000400  // Endpoint 10 Device IN Interrupt
+#define USB_INTEP_DEV_IN_9      0x00000200  // Endpoint 9 Device IN Interrupt
+#define USB_INTEP_DEV_IN_8      0x00000100  // Endpoint 8 Device IN Interrupt
+#define USB_INTEP_DEV_IN_7      0x00000080  // Endpoint 7 Device IN Interrupt
+#define USB_INTEP_DEV_IN_6      0x00000040  // Endpoint 6 Device IN Interrupt
+#define USB_INTEP_DEV_IN_5      0x00000020  // Endpoint 5 Device IN Interrupt
+#define USB_INTEP_DEV_IN_4      0x00000010  // Endpoint 4 Device IN Interrupt
+#define USB_INTEP_DEV_IN_3      0x00000008  // Endpoint 3 Device IN Interrupt
+#define USB_INTEP_DEV_IN_2      0x00000004  // Endpoint 2 Device IN Interrupt
+#define USB_INTEP_DEV_IN_1      0x00000002  // Endpoint 1 Device IN Interrupt
+
+#define USB_INTEP_0             0x00000001  // Endpoint 0 Interrupt
+
+//*****************************************************************************
+//
+// The following are values that are returned from USBSpeedGet().
+//
+//*****************************************************************************
+#define USB_UNDEF_SPEED         0x80000000  // Current speed is undefined
+#define USB_FULL_SPEED          0x00000001  // Current speed is Full Speed
+#define USB_LOW_SPEED           0x00000000  // Current speed is Low Speed
+
+//*****************************************************************************
+//
+// The following are values that are returned from USBEndpointStatus().  The
+// USB_HOST_* values are used when the USB controller is in host mode and the
+// USB_DEV_* values are used when the USB controller is in device mode.
+//
+//*****************************************************************************
+#define USB_HOST_IN_STATUS      0xFFFF0000  // Mask of all host IN interrupts
+#define USB_HOST_IN_PID_ERROR   0x01000000  // Stall on this endpoint received
+#define USB_HOST_IN_NOT_COMP    0x00100000  // Device failed to respond
+#define USB_HOST_IN_STALL       0x00400000  // Stall on this endpoint received
+#define USB_HOST_IN_DATA_ERROR  0x00080000  // CRC or bit-stuff error
+                                            // (ISOC Mode)
+#define USB_HOST_IN_NAK_TO      0x00080000  // NAK received for more than the
+                                            // specified timeout period
+#define USB_HOST_IN_ERROR       0x00040000  // Failed to communicate with a
+                                            // device
+#define USB_HOST_IN_FIFO_FULL   0x00020000  // RX FIFO full
+#define USB_HOST_IN_PKTRDY      0x00010000  // Data packet ready
+#define USB_HOST_OUT_STATUS     0x0000FFFF  // Mask of all host OUT interrupts
+#define USB_HOST_OUT_NAK_TO     0x00000080  // NAK received for more than the
+                                            // specified timeout period
+#define USB_HOST_OUT_NOT_COMP   0x00000080  // No response from device
+                                            // (ISOC mode)
+#define USB_HOST_OUT_STALL      0x00000020  // Stall on this endpoint received
+#define USB_HOST_OUT_ERROR      0x00000004  // Failed to communicate with a
+                                            // device
+#define USB_HOST_OUT_FIFO_NE    0x00000002  // TX FIFO is not empty
+#define USB_HOST_OUT_PKTPEND    0x00000001  // Transmit still being transmitted
+#define USB_HOST_EP0_NAK_TO     0x00000080  // NAK received for more than the
+                                            // specified timeout period
+#define USB_HOST_EP0_STATUS     0x00000040  // This was a status packet
+#define USB_HOST_EP0_ERROR      0x00000010  // Failed to communicate with a
+                                            // device
+#define USB_HOST_EP0_RX_STALL   0x00000004  // Stall on this endpoint received
+#define USB_HOST_EP0_RXPKTRDY   0x00000001  // Receive data packet ready
+#define USB_DEV_RX_SENT_STALL   0x00400000  // Stall was sent on this endpoint
+#define USB_DEV_RX_DATA_ERROR   0x00080000  // CRC error on the data
+#define USB_DEV_RX_OVERRUN      0x00040000  // OUT packet was not loaded due to
+                                            // a full FIFO
+#define USB_DEV_RX_FIFO_FULL    0x00020000  // RX FIFO full
+#define USB_DEV_RX_PKT_RDY      0x00010000  // Data packet ready
+#define USB_DEV_TX_NOT_COMP     0x00000080  // Large packet split up, more data
+                                            // to come
+#define USB_DEV_TX_SENT_STALL   0x00000020  // Stall was sent on this endpoint
+#define USB_DEV_TX_UNDERRUN     0x00000004  // IN received with no data ready
+#define USB_DEV_TX_FIFO_NE      0x00000002  // The TX FIFO is not empty
+#define USB_DEV_TX_TXPKTRDY     0x00000001  // Transmit still being transmitted
+#define USB_DEV_EP0_SETUP_END   0x00000010  // Control transaction ended before
+                                            // Data End seen
+#define USB_DEV_EP0_SENT_STALL  0x00000004  // Stall was sent on this endpoint
+#define USB_DEV_EP0_IN_PKTPEND  0x00000002  // Transmit data packet pending
+#define USB_DEV_EP0_OUT_PKTRDY  0x00000001  // Receive data packet ready
+
+//*****************************************************************************
+//
+// The following are values that can be passed to USBHostEndpointConfig() and
+// USBDevEndpointConfigSet() as the ulFlags parameter.
+//
+//*****************************************************************************
+#define USB_EP_AUTO_SET         0x00000001  // Auto set feature enabled
+#define USB_EP_AUTO_REQUEST     0x00000002  // Auto request feature enabled
+#define USB_EP_AUTO_CLEAR       0x00000004  // Auto clear feature enabled
+#define USB_EP_DMA_MODE_0       0x00000008  // Enable DMA access using mode 0
+#define USB_EP_DMA_MODE_1       0x00000010  // Enable DMA access using mode 1
+#define USB_EP_MODE_ISOC        0x00000000  // Isochronous endpoint
+#define USB_EP_MODE_BULK        0x00000100  // Bulk endpoint
+#define USB_EP_MODE_INT         0x00000200  // Interrupt endpoint
+#define USB_EP_MODE_CTRL        0x00000300  // Control endpoint
+#define USB_EP_MODE_MASK        0x00000300  // Mode Mask
+#define USB_EP_SPEED_LOW        0x00000000  // Low Speed
+#define USB_EP_SPEED_FULL       0x00001000  // Full Speed
+#define USB_EP_HOST_IN          0x00000000  // Host IN endpoint
+#define USB_EP_HOST_OUT         0x00002000  // Host OUT endpoint
+#define USB_EP_DEV_IN           0x00002000  // Device IN endpoint
+#define USB_EP_DEV_OUT          0x00000000  // Device OUT endpoint
+
+//*****************************************************************************
+//
+// The following are values that can be passed to USBHostPwrConfig() as
+// the ulFlags parameter.
+//
+//*****************************************************************************
+#define USB_HOST_PWRFLT_LOW     0x00000010
+#define USB_HOST_PWRFLT_HIGH    0x00000030
+#define USB_HOST_PWRFLT_EP_NONE 0x00000000
+#define USB_HOST_PWRFLT_EP_TRI  0x00000140
+#define USB_HOST_PWRFLT_EP_LOW  0x00000240
+#define USB_HOST_PWRFLT_EP_HIGH 0x00000340
+#ifndef DEPRECATED
+#define USB_HOST_PWREN_LOW      0x00000002
+#define USB_HOST_PWREN_HIGH     0x00000003
+#define USB_HOST_PWREN_VBLOW    0x00000002
+#define USB_HOST_PWREN_VBHIGH   0x00000003
+#endif
+#define USB_HOST_PWREN_MAN_LOW  0x00000000
+#define USB_HOST_PWREN_MAN_HIGH 0x00000001
+#define USB_HOST_PWREN_AUTOLOW  0x00000002
+#define USB_HOST_PWREN_AUTOHIGH 0x00000003
+#define USB_HOST_PWREN_FILTER   0x00010000
+
+//*****************************************************************************
+//
+// The following are special values that can be passed to
+// USBHostEndpointConfig() as the ulNAKPollInterval parameter.
+//
+//*****************************************************************************
+#define MAX_NAK_LIMIT           31          // Maximum NAK interval
+#define DISABLE_NAK_LIMIT       0           // No NAK timeouts
+
+//*****************************************************************************
+//
+// This value specifies the maximum size of transfers on endpoint 0 as 64
+// bytes.  This value is fixed in hardware as the FIFO size for endpoint 0.
+//
+//*****************************************************************************
+#define MAX_PACKET_SIZE_EP0     64
+
+//*****************************************************************************
+//
+// These values are used to indicate which endpoint to access.
+//
+//*****************************************************************************
+#define USB_EP_0                0x00000000  // Endpoint 0
+#define USB_EP_1                0x00000010  // Endpoint 1
+#define USB_EP_2                0x00000020  // Endpoint 2
+#define USB_EP_3                0x00000030  // Endpoint 3
+#define USB_EP_4                0x00000040  // Endpoint 4
+#define USB_EP_5                0x00000050  // Endpoint 5
+#define USB_EP_6                0x00000060  // Endpoint 6
+#define USB_EP_7                0x00000070  // Endpoint 7
+#define USB_EP_8                0x00000080  // Endpoint 8
+#define USB_EP_9                0x00000090  // Endpoint 9
+#define USB_EP_10               0x000000A0  // Endpoint 10
+#define USB_EP_11               0x000000B0  // Endpoint 11
+#define USB_EP_12               0x000000C0  // Endpoint 12
+#define USB_EP_13               0x000000D0  // Endpoint 13
+#define USB_EP_14               0x000000E0  // Endpoint 14
+#define USB_EP_15               0x000000F0  // Endpoint 15
+#define NUM_USB_EP              16          // Number of supported endpoints
+
+//*****************************************************************************
+//
+// These macros allow conversion between 0-based endpoint indices and the
+// USB_EP_x values required when calling various USB APIs.
+//
+//*****************************************************************************
+#define INDEX_TO_USB_EP(x)      ((x) << 4)
+#define USB_EP_TO_INDEX(x)      ((x) >> 4)
+
+//*****************************************************************************
+//
+// The following are values that can be passed to USBFIFOConfigSet() as the
+// ulFIFOSize parameter.
+//
+//*****************************************************************************
+#define USB_FIFO_SZ_8           0x00000000  // 8 byte FIFO
+#define USB_FIFO_SZ_16          0x00000001  // 16 byte FIFO
+#define USB_FIFO_SZ_32          0x00000002  // 32 byte FIFO
+#define USB_FIFO_SZ_64          0x00000003  // 64 byte FIFO
+#define USB_FIFO_SZ_128         0x00000004  // 128 byte FIFO
+#define USB_FIFO_SZ_256         0x00000005  // 256 byte FIFO
+#define USB_FIFO_SZ_512         0x00000006  // 512 byte FIFO
+#define USB_FIFO_SZ_1024        0x00000007  // 1024 byte FIFO
+#define USB_FIFO_SZ_2048        0x00000008  // 2048 byte FIFO
+#define USB_FIFO_SZ_4096        0x00000009  // 4096 byte FIFO
+#define USB_FIFO_SZ_8_DB        0x00000010  // 8 byte double buffered FIFO
+                                            // (occupying 16 bytes)
+#define USB_FIFO_SZ_16_DB       0x00000011  // 16 byte double buffered FIFO
+                                            // (occupying 32 bytes)
+#define USB_FIFO_SZ_32_DB       0x00000012  // 32 byte double buffered FIFO
+                                            // (occupying 64 bytes)
+#define USB_FIFO_SZ_64_DB       0x00000013  // 64 byte double buffered FIFO
+                                            // (occupying 128 bytes)
+#define USB_FIFO_SZ_128_DB      0x00000014  // 128 byte double buffered FIFO
+                                            // (occupying 256 bytes)
+#define USB_FIFO_SZ_256_DB      0x00000015  // 256 byte double buffered FIFO
+                                            // (occupying 512 bytes)
+#define USB_FIFO_SZ_512_DB      0x00000016  // 512 byte double buffered FIFO
+                                            // (occupying 1024 bytes)
+#define USB_FIFO_SZ_1024_DB     0x00000017  // 1024 byte double buffered FIFO
+                                            // (occupying 2048 bytes)
+#define USB_FIFO_SZ_2048_DB     0x00000018  // 2048 byte double buffered FIFO
+                                            // (occupying 4096 bytes)
+
+//*****************************************************************************
+//
+// This macro allow conversion from a FIFO size label as defined above to
+// a number of bytes
+//
+//*****************************************************************************
+#define USB_FIFO_SIZE_DB_FLAG  0x00000010
+#define USB_FIFO_SZ_TO_BYTES(x) ((8 << ((x) & ~ USB_FIFO_SIZE_DB_FLAG)) * \
+                                 (((x) & USB_FIFO_SIZE_DB_FLAG) ? 2 : 1))
+
+//*****************************************************************************
+//
+// The following are values that can be passed to USBEndpointDataSend() as the
+// ulTransType parameter.
+//
+//*****************************************************************************
+#define USB_TRANS_OUT           0x00000102  // Normal OUT transaction
+#define USB_TRANS_IN            0x00000102  // Normal IN transaction
+#define USB_TRANS_IN_LAST       0x0000010a  // Final IN transaction (for
+                                            // endpoint 0 in device mode)
+#define USB_TRANS_SETUP         0x0000110a  // Setup transaction (for endpoint
+                                            // 0)
+#define USB_TRANS_STATUS        0x00000142  // Status transaction (for endpoint
+                                            // 0)
+
+//*****************************************************************************
+//
+// The following are values are returned by the USBModeGet function.
+//
+//*****************************************************************************
+#define USB_DUAL_MODE_HOST      0x00000001  // Dual mode controller is in Host
+                                            // mode.
+#define USB_DUAL_MODE_DEVICE    0x00000081  // Dual mode controller is in
+                                            // Device mode.
+#define USB_DUAL_MODE_NONE      0x00000080  // Dual mode controller mode is not
+                                            // set.
+#define USB_OTG_MODE_ASIDE_HOST 0x0000001d  // OTG controller on the A side of
+                                            // the cable.
+#define USB_OTG_MODE_ASIDE_NPWR 0x00000001  // OTG controller on the A side of
+                                            // the cable.
+#define USB_OTG_MODE_ASIDE_SESS 0x00000009  // OTG controller on the A side of
+                                            // the cable Session Valid.
+#define USB_OTG_MODE_ASIDE_AVAL 0x00000011  // OTG controller on the A side of
+                                            // the cable A valid.
+#define USB_OTG_MODE_ASIDE_DEV  0x00000019  // OTG controller on the A side of
+                                            // the cable.
+#define USB_OTG_MODE_BSIDE_HOST 0x0000009d  // OTG controller on the B side of
+                                            // the cable.
+#define USB_OTG_MODE_BSIDE_DEV  0x00000099  // OTG controller on the B side of
+                                            // the cable.
+#define USB_OTG_MODE_BSIDE_NPWR 0x00000081  // OTG controller on the B side of
+                                            // the cable.
+#define USB_OTG_MODE_NONE       0x00000080  // OTG controller mode is not set.
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern unsigned long USBDevAddrGet(unsigned long ulBase);
+extern void USBDevAddrSet(unsigned long ulBase, unsigned long ulAddress);
+extern void USBDevConnect(unsigned long ulBase);
+extern void USBDevDisconnect(unsigned long ulBase);
+extern void USBDevEndpointConfigSet(unsigned long ulBase,
+                                    unsigned long ulEndpoint,
+                                    unsigned long ulMaxPacketSize,
+                                    unsigned long ulFlags);
+extern void USBDevEndpointConfigGet(unsigned long ulBase,
+                                    unsigned long ulEndpoint,
+                                    unsigned long *pulMaxPacketSize,
+                                    unsigned long *pulFlags);
+extern void USBDevEndpointDataAck(unsigned long ulBase,
+                                  unsigned long ulEndpoint,
+                                  tBoolean bIsLastPacket);
+extern void USBDevEndpointStall(unsigned long ulBase, unsigned long ulEndpoint,
+                                unsigned long ulFlags);
+extern void USBDevEndpointStallClear(unsigned long ulBase,
+                                     unsigned long ulEndpoint,
+                                     unsigned long ulFlags);
+extern void USBDevEndpointStatusClear(unsigned long ulBase,
+                                      unsigned long ulEndpoint,
+                                      unsigned long ulFlags);
+extern unsigned long USBEndpointDataAvail(unsigned long ulBase,
+                                          unsigned long ulEndpoint);
+extern void USBEndpointDMAEnable(unsigned long ulBase, unsigned long ulEndpoint,
+                                 unsigned long ulFlags);
+extern void USBEndpointDMADisable(unsigned long ulBase,
+                                  unsigned long ulEndpoint,
+                                  unsigned long ulFlags);
+extern long USBEndpointDataGet(unsigned long ulBase, unsigned long ulEndpoint,
+                               unsigned char *pucData, unsigned long *pulSize);
+extern long USBEndpointDataPut(unsigned long ulBase, unsigned long ulEndpoint,
+                               unsigned char *pucData, unsigned long ulSize);
+extern long USBEndpointDataSend(unsigned long ulBase, unsigned long ulEndpoint,
+                                unsigned long ulTransType);
+extern void USBEndpointDataToggleClear(unsigned long ulBase,
+                                       unsigned long ulEndpoint,
+                                       unsigned long ulFlags);
+extern unsigned long USBEndpointStatus(unsigned long ulBase,
+                                       unsigned long ulEndpoint);
+extern unsigned long USBFIFOAddrGet(unsigned long ulBase,
+                                    unsigned long ulEndpoint);
+extern void USBFIFOConfigGet(unsigned long ulBase, unsigned long ulEndpoint,
+                             unsigned long *pulFIFOAddress,
+                             unsigned long *pulFIFOSize,
+                             unsigned long ulFlags);
+extern void USBFIFOConfigSet(unsigned long ulBase, unsigned long ulEndpoint,
+                             unsigned long ulFIFOAddress,
+                             unsigned long ulFIFOSize, unsigned long ulFlags);
+extern void USBFIFOFlush(unsigned long ulBase, unsigned long ulEndpoint,
+                         unsigned long ulFlags);
+extern unsigned long USBFrameNumberGet(unsigned long ulBase);
+extern unsigned long USBHostAddrGet(unsigned long ulBase,
+                                    unsigned long ulEndpoint,
+                                    unsigned long ulFlags);
+extern void USBHostAddrSet(unsigned long ulBase, unsigned long ulEndpoint,
+                           unsigned long ulAddr, unsigned long ulFlags);
+extern void USBHostEndpointConfig(unsigned long ulBase,
+                                  unsigned long ulEndpoint,
+                                  unsigned long ulMaxPacketSize,
+                                  unsigned long ulNAKPollInterval,
+                                  unsigned long ulTargetEndpoint,
+                                  unsigned long ulFlags);
+extern void USBHostEndpointDataAck(unsigned long ulBase,
+                                   unsigned long ulEndpoint);
+extern void USBHostEndpointDataToggle(unsigned long ulBase,
+                                      unsigned long ulEndpoint,
+                                      tBoolean bDataToggle,
+                                      unsigned long ulFlags);
+extern void USBHostEndpointStatusClear(unsigned long ulBase,
+                                       unsigned long ulEndpoint,
+                                       unsigned long ulFlags);
+extern unsigned long USBHostHubAddrGet(unsigned long ulBase,
+                                       unsigned long ulEndpoint,
+                                       unsigned long ulFlags);
+extern void USBHostHubAddrSet(unsigned long ulBase, unsigned long ulEndpoint,
+                              unsigned long ulAddr, unsigned long ulFlags);
+extern void USBHostPwrDisable(unsigned long ulBase);
+extern void USBHostPwrEnable(unsigned long ulBase);
+extern void USBHostPwrConfig(unsigned long ulBase, unsigned long ulFlags);
+#ifndef DEPRECATED
+#define USBHostPwrFaultConfig   USBHostPwrConfig
+#endif
+extern void USBHostPwrFaultDisable(unsigned long ulBase);
+extern void USBHostPwrFaultEnable(unsigned long ulBase);
+extern void USBHostRequestIN(unsigned long ulBase, unsigned long ulEndpoint);
+extern void USBHostRequestStatus(unsigned long ulBase);
+extern void USBHostReset(unsigned long ulBase, tBoolean bStart);
+extern void USBHostResume(unsigned long ulBase, tBoolean bStart);
+extern unsigned long USBHostSpeedGet(unsigned long ulBase);
+extern void USBHostSuspend(unsigned long ulBase);
+extern void USBIntDisableControl(unsigned long ulBase,
+                                 unsigned long ulIntFlags);
+extern void USBIntEnableControl(unsigned long ulBase,
+                                unsigned long ulIntFlags);
+extern unsigned long USBIntStatusControl(unsigned long ulBase);
+extern void USBIntDisableEndpoint(unsigned long ulBase,
+                                  unsigned long ulIntFlags);
+extern void USBIntEnableEndpoint(unsigned long ulBase,
+                                 unsigned long ulIntFlags);
+extern unsigned long USBIntStatusEndpoint(unsigned long ulBase);
+extern void USBIntRegister(unsigned long ulBase, void(*pfnHandler)(void));
+extern void USBIntUnregister(unsigned long ulBase);
+extern void USBOTGSessionRequest(unsigned long ulBase, tBoolean bStart);
+extern unsigned long USBModeGet(unsigned long ulBase);
+extern void USBEndpointDMAChannel(unsigned long ulBase,
+                                  unsigned long ulEndpoint,
+                                  unsigned long ulChannel);
+extern void USBHostMode(unsigned long ulBase);
+extern void USBDevMode(unsigned long ulBase);
+extern void USBOTGMode(unsigned long ulBase);
+extern void USBPHYPowerOff(unsigned long ulBase);
+extern void USBPHYPowerOn(unsigned long ulBase);
+
+//*****************************************************************************
+//
+// Several USB APIs have been renamed, with the original function name being
+// deprecated.  These defines and function protypes provide backward
+// compatibility.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+//*****************************************************************************
+//
+// The following are values that can be passed to USBIntEnable() and
+// USBIntDisable() as the ulIntFlags parameter, and are returned from
+// USBIntStatus().
+//
+//*****************************************************************************
+#define USB_INT_ALL             0xFF030E0F  // All Interrupt sources
+#define USB_INT_STATUS          0xFF000000  // Status Interrupts
+#define USB_INT_VBUS_ERR        0x80000000  // VBUS Error
+#define USB_INT_SESSION_START   0x40000000  // Session Start Detected
+#define USB_INT_SESSION_END     0x20000000  // Session End Detected
+#define USB_INT_DISCONNECT      0x20000000  // Disconnect Detected
+#define USB_INT_CONNECT         0x10000000  // Device Connect Detected
+#define USB_INT_SOF             0x08000000  // Start of Frame Detected
+#define USB_INT_BABBLE          0x04000000  // Babble signaled
+#define USB_INT_RESET           0x04000000  // Reset signaled
+#define USB_INT_RESUME          0x02000000  // Resume detected
+#define USB_INT_SUSPEND         0x01000000  // Suspend detected
+#define USB_INT_MODE_DETECT     0x00020000  // Mode value valid
+#define USB_INT_POWER_FAULT     0x00010000  // Power Fault detected
+#define USB_INT_HOST_IN         0x00000E00  // Host IN Interrupts
+#define USB_INT_DEV_OUT         0x00000E00  // Device OUT Interrupts
+#define USB_INT_HOST_IN_EP3     0x00000800  // Endpoint 3 Host IN Interrupt
+#define USB_INT_HOST_IN_EP2     0x00000400  // Endpoint 2 Host IN Interrupt
+#define USB_INT_HOST_IN_EP1     0x00000200  // Endpoint 1 Host IN Interrupt
+#define USB_INT_DEV_OUT_EP3     0x00000800  // Endpoint 3 Device OUT Interrupt
+#define USB_INT_DEV_OUT_EP2     0x00000400  // Endpoint 2 Device OUT Interrupt
+#define USB_INT_DEV_OUT_EP1     0x00000200  // Endpoint 1 Device OUT Interrupt
+#define USB_INT_HOST_OUT        0x0000000E  // Host OUT Interrupts
+#define USB_INT_DEV_IN          0x0000000E  // Device IN Interrupts
+#define USB_INT_HOST_OUT_EP3    0x00000008  // Endpoint 3 HOST_OUT Interrupt
+#define USB_INT_HOST_OUT_EP2    0x00000004  // Endpoint 2 HOST_OUT Interrupt
+#define USB_INT_HOST_OUT_EP1    0x00000002  // Endpoint 1 HOST_OUT Interrupt
+#define USB_INT_DEV_IN_EP3      0x00000008  // Endpoint 3 DEV_IN Interrupt
+#define USB_INT_DEV_IN_EP2      0x00000004  // Endpoint 2 DEV_IN Interrupt
+#define USB_INT_DEV_IN_EP1      0x00000002  // Endpoint 1 DEV_IN Interrupt
+#define USB_INT_EP0             0x00000001  // Endpoint 0 Interrupt
+
+#define USBDevEndpointConfig    USBDevEndpointConfigSet
+extern void USBIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
+extern void USBIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
+extern unsigned long USBIntStatus(unsigned long ulBase);
+#endif
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __USB_H__
diff --git a/src/platform/lm3s/hw_qei.h b/src/platform/lm3s/hw_qei.h
deleted file mode 100755
index 89038607..00000000
--- a/src/platform/lm3s/hw_qei.h
+++ /dev/null
@@ -1,201 +0,0 @@
-//*****************************************************************************
-//
-// hw_qei.h - Macros used when accessing the QEI hardware.
-//
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
-// Software License Agreement
-// 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
-// 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
-// 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4781 of the Stellaris Firmware Development Package.
-//
-//*****************************************************************************
-
-#ifndef __HW_QEI_H__
-#define __HW_QEI_H__
-
-//*****************************************************************************
-//
-// The following are defines for the QEI register offsets.
-//
-//*****************************************************************************
-#define QEI_O_CTL               0x00000000  // Configuration and control reg.
-#define QEI_O_STAT              0x00000004  // Status register
-#define QEI_O_POS               0x00000008  // Current position register
-#define QEI_O_MAXPOS            0x0000000C  // Maximum position register
-#define QEI_O_LOAD              0x00000010  // Velocity timer load register
-#define QEI_O_TIME              0x00000014  // Velocity timer register
-#define QEI_O_COUNT             0x00000018  // Velocity pulse count register
-#define QEI_O_SPEED             0x0000001C  // Velocity speed register
-#define QEI_O_INTEN             0x00000020  // Interrupt enable register
-#define QEI_O_RIS               0x00000024  // Raw interrupt status register
-#define QEI_O_ISC               0x00000028  // Interrupt status register
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the QEI_CTL register.
-//
-//*****************************************************************************
-#define QEI_CTL_FILTCNT_M       0x000F0000  // Input Filter Pre-Scale Count.
-#define QEI_CTL_FILTEN          0x00002000  // Enable Input Filter.
-#define QEI_CTL_STALLEN         0x00001000  // Stall enable
-#define QEI_CTL_INVI            0x00000800  // Invert Index input
-#define QEI_CTL_INVB            0x00000400  // Invert PhB input
-#define QEI_CTL_INVA            0x00000200  // Invert PhA input
-#define QEI_CTL_VELDIV_M        0x000001C0  // Velocity predivider mask
-#define QEI_CTL_VELDIV_1        0x00000000  // Predivide by 1
-#define QEI_CTL_VELDIV_2        0x00000040  // Predivide by 2
-#define QEI_CTL_VELDIV_4        0x00000080  // Predivide by 4
-#define QEI_CTL_VELDIV_8        0x000000C0  // Predivide by 8
-#define QEI_CTL_VELDIV_16       0x00000100  // Predivide by 16
-#define QEI_CTL_VELDIV_32       0x00000140  // Predivide by 32
-#define QEI_CTL_VELDIV_64       0x00000180  // Predivide by 64
-#define QEI_CTL_VELDIV_128      0x000001C0  // Predivide by 128
-#define QEI_CTL_VELEN           0x00000020  // Velocity enable
-#define QEI_CTL_RESMODE         0x00000010  // Position counter reset mode
-#define QEI_CTL_CAPMODE         0x00000008  // Edge capture mode
-#define QEI_CTL_SIGMODE         0x00000004  // Encoder signaling mode
-#define QEI_CTL_SWAP            0x00000002  // Swap input signals
-#define QEI_CTL_ENABLE          0x00000001  // QEI enable
-#define QEI_CTL_FILTCNT_S       16
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the QEI_STAT register.
-//
-//*****************************************************************************
-#define QEI_STAT_DIRECTION      0x00000002  // Direction of rotation
-#define QEI_STAT_ERROR          0x00000001  // Signalling error detected
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the QEI_POS register.
-//
-//*****************************************************************************
-#define QEI_POS_M               0xFFFFFFFF  // Current encoder position
-#define QEI_POS_S               0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the QEI_MAXPOS register.
-//
-//*****************************************************************************
-#define QEI_MAXPOS_M            0xFFFFFFFF  // Maximum encoder position
-#define QEI_MAXPOS_S            0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the QEI_LOAD register.
-//
-//*****************************************************************************
-#define QEI_LOAD_M              0xFFFFFFFF  // Velocity timer load value
-#define QEI_LOAD_S              0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the QEI_TIME register.
-//
-//*****************************************************************************
-#define QEI_TIME_M              0xFFFFFFFF  // Velocity timer current value
-#define QEI_TIME_S              0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the QEI_COUNT register.
-//
-//*****************************************************************************
-#define QEI_COUNT_M             0xFFFFFFFF  // Encoder running pulse count
-#define QEI_COUNT_S             0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the QEI_SPEED register.
-//
-//*****************************************************************************
-#define QEI_SPEED_M             0xFFFFFFFF  // Encoder pulse count
-#define QEI_SPEED_S             0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the QEI_INTEN register.
-//
-//*****************************************************************************
-#define QEI_INTEN_ERROR         0x00000008  // Phase error detected
-#define QEI_INTEN_DIR           0x00000004  // Direction change
-#define QEI_INTEN_TIMER         0x00000002  // Velocity timer expired
-#define QEI_INTEN_INDEX         0x00000001  // Index pulse detected
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the QEI_RIS register.
-//
-//*****************************************************************************
-#define QEI_RIS_ERROR           0x00000008  // Phase error detected
-#define QEI_RIS_DIR             0x00000004  // Direction change
-#define QEI_RIS_TIMER           0x00000002  // Velocity timer expired
-#define QEI_RIS_INDEX           0x00000001  // Index pulse detected
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the QEI_O_ISC register.
-//
-//*****************************************************************************
-#define QEI_ISC_ERROR           0x00000008  // Phase Error Interrupt.
-#define QEI_ISC_DIR             0x00000004  // Direction Change Interrupt.
-#define QEI_ISC_TIMER           0x00000002  // Velocity Timer Expired
-                                            // Interrupt.
-#define QEI_ISC_INDEX           0x00000001  // Index Pulse Interrupt.
-
-//*****************************************************************************
-//
-// The following definitions are deprecated.
-//
-//*****************************************************************************
-#ifndef DEPRECATED
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the QEI_ISC
-// register.
-//
-//*****************************************************************************
-#define QEI_INT_ERROR           0x00000008  // Phase error detected
-#define QEI_INT_DIR             0x00000004  // Direction change
-#define QEI_INT_TIMER           0x00000002  // Velocity timer expired
-#define QEI_INT_INDEX           0x00000001  // Index pulse detected
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the reset values for the QEI
-// registers.
-//
-//*****************************************************************************
-#define QEI_RV_POS              0x00000000  // Current position register
-#define QEI_RV_LOAD             0x00000000  // Velocity timer load register
-#define QEI_RV_CTL              0x00000000  // Configuration and control reg.
-#define QEI_RV_RIS              0x00000000  // Raw interrupt status register
-#define QEI_RV_ISC              0x00000000  // Interrupt status register
-#define QEI_RV_SPEED            0x00000000  // Velocity speed register
-#define QEI_RV_INTEN            0x00000000  // Interrupt enable register
-#define QEI_RV_STAT             0x00000000  // Status register
-#define QEI_RV_COUNT            0x00000000  // Velocity pulse count register
-#define QEI_RV_MAXPOS           0x00000000  // Maximum position register
-#define QEI_RV_TIME             0x00000000  // Velocity timer register
-
-#endif
-
-#endif // __HW_QEI_H__
diff --git a/src/platform/lm3s/hw_adc.h b/src/platform/lm3s/inc/hw_adc.h
similarity index 65%
rename from src/platform/lm3s/hw_adc.h
rename to src/platform/lm3s/inc/hw_adc.h
index 6a290efe..5ad88313 100755
--- a/src/platform/lm3s/hw_adc.h
+++ b/src/platform/lm3s/inc/hw_adc.h
@@ -2,26 +2,23 @@
 //
 // hw_adc.h - Macros used when accessing the ADC hardware.
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2011 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4781 of the Stellaris Firmware Development Package.
+// This is part of revision 7611 of the Stellaris Firmware Development Package.
 //
 //*****************************************************************************
 
@@ -33,48 +30,62 @@
 // The following are defines for the ADC register offsets.
 //
 //*****************************************************************************
-#define ADC_O_ACTSS             0x00000000  // Active sample register
-#define ADC_O_RIS               0x00000004  // Raw interrupt status register
-#define ADC_O_IM                0x00000008  // Interrupt mask register
-#define ADC_O_ISC               0x0000000C  // Interrupt status/clear register
-#define ADC_O_OSTAT             0x00000010  // Overflow status register
-#define ADC_O_EMUX              0x00000014  // Event multiplexer select reg.
-#define ADC_O_USTAT             0x00000018  // Underflow status register
-#define ADC_O_SSPRI             0x00000020  // Channel priority register
-#define ADC_O_PSSI              0x00000028  // Processor sample initiate reg.
-#define ADC_O_SAC               0x00000030  // Sample Averaging Control reg.
+#define ADC_O_ACTSS             0x00000000  // ADC Active Sample Sequencer
+#define ADC_O_RIS               0x00000004  // ADC Raw Interrupt Status
+#define ADC_O_IM                0x00000008  // ADC Interrupt Mask
+#define ADC_O_ISC               0x0000000C  // ADC Interrupt Status and Clear
+#define ADC_O_OSTAT             0x00000010  // ADC Overflow Status
+#define ADC_O_EMUX              0x00000014  // ADC Event Multiplexer Select
+#define ADC_O_USTAT             0x00000018  // ADC Underflow Status
+#define ADC_O_SSPRI             0x00000020  // ADC Sample Sequencer Priority
+#define ADC_O_SPC               0x00000024  // ADC Sample Phase Control
+#define ADC_O_PSSI              0x00000028  // ADC Processor Sample Sequence
+                                            // Initiate
+#define ADC_O_SAC               0x00000030  // ADC Sample Averaging Control
 #define ADC_O_DCISC             0x00000034  // ADC Digital Comparator Interrupt
                                             // Status and Clear
 #define ADC_O_CTL               0x00000038  // ADC Control
-#define ADC_O_SSMUX0            0x00000040  // Multiplexer select 0 register
-#define ADC_O_SSCTL0            0x00000044  // Sample sequence control 0 reg.
-#define ADC_O_SSFIFO0           0x00000048  // Result FIFO 0 register
-#define ADC_O_SSFSTAT0          0x0000004C  // FIFO 0 status register
+#define ADC_O_SSMUX0            0x00000040  // ADC Sample Sequence Input
+                                            // Multiplexer Select 0
+#define ADC_O_SSCTL0            0x00000044  // ADC Sample Sequence Control 0
+#define ADC_O_SSFIFO0           0x00000048  // ADC Sample Sequence Result FIFO
+                                            // 0
+#define ADC_O_SSFSTAT0          0x0000004C  // ADC Sample Sequence FIFO 0
+                                            // Status
 #define ADC_O_SSOP0             0x00000050  // ADC Sample Sequence 0 Operation
 #define ADC_O_SSDC0             0x00000054  // ADC Sample Sequence 0 Digital
                                             // Comparator Select
-#define ADC_O_SSMUX1            0x00000060  // Multiplexer select 1 register
-#define ADC_O_SSCTL1            0x00000064  // Sample sequence control 1 reg.
-#define ADC_O_SSFIFO1           0x00000068  // Result FIFO 1 register
-#define ADC_O_SSFSTAT1          0x0000006C  // FIFO 1 status register
+#define ADC_O_SSMUX1            0x00000060  // ADC Sample Sequence Input
+                                            // Multiplexer Select 1
+#define ADC_O_SSCTL1            0x00000064  // ADC Sample Sequence Control 1
+#define ADC_O_SSFIFO1           0x00000068  // ADC Sample Sequence Result FIFO
+                                            // 1
+#define ADC_O_SSFSTAT1          0x0000006C  // ADC Sample Sequence FIFO 1
+                                            // Status
 #define ADC_O_SSOP1             0x00000070  // ADC Sample Sequence 1 Operation
 #define ADC_O_SSDC1             0x00000074  // ADC Sample Sequence 1 Digital
                                             // Comparator Select
-#define ADC_O_SSMUX2            0x00000080  // Multiplexer select 2 register
-#define ADC_O_SSCTL2            0x00000084  // Sample sequence control 2 reg.
-#define ADC_O_SSFIFO2           0x00000088  // Result FIFO 2 register
-#define ADC_O_SSFSTAT2          0x0000008C  // FIFO 2 status register
+#define ADC_O_SSMUX2            0x00000080  // ADC Sample Sequence Input
+                                            // Multiplexer Select 2
+#define ADC_O_SSCTL2            0x00000084  // ADC Sample Sequence Control 2
+#define ADC_O_SSFIFO2           0x00000088  // ADC Sample Sequence Result FIFO
+                                            // 2
+#define ADC_O_SSFSTAT2          0x0000008C  // ADC Sample Sequence FIFO 2
+                                            // Status
 #define ADC_O_SSOP2             0x00000090  // ADC Sample Sequence 2 Operation
 #define ADC_O_SSDC2             0x00000094  // ADC Sample Sequence 2 Digital
                                             // Comparator Select
-#define ADC_O_SSMUX3            0x000000A0  // Multiplexer select 3 register
-#define ADC_O_SSCTL3            0x000000A4  // Sample sequence control 3 reg.
-#define ADC_O_SSFIFO3           0x000000A8  // Result FIFO 3 register
-#define ADC_O_SSFSTAT3          0x000000AC  // FIFO 3 status register
+#define ADC_O_SSMUX3            0x000000A0  // ADC Sample Sequence Input
+                                            // Multiplexer Select 3
+#define ADC_O_SSCTL3            0x000000A4  // ADC Sample Sequence Control 3
+#define ADC_O_SSFIFO3           0x000000A8  // ADC Sample Sequence Result FIFO
+                                            // 3
+#define ADC_O_SSFSTAT3          0x000000AC  // ADC Sample Sequence FIFO 3
+                                            // Status
 #define ADC_O_SSOP3             0x000000B0  // ADC Sample Sequence 3 Operation
 #define ADC_O_SSDC3             0x000000B4  // ADC Sample Sequence 3 Digital
                                             // Comparator Select
-#define ADC_O_TMLB              0x00000100  // Test mode loopback register
+#define ADC_O_TMLB              0x00000100  // ADC Test Mode Loopback
 #define ADC_O_DCRIC             0x00000D00  // ADC Digital Comparator Reset
                                             // Initial Conditions
 #define ADC_O_DCCTL0            0x00000E00  // ADC Digital Comparator Control 0
@@ -96,157 +107,157 @@
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the ADC_ACTSS register.
+// The following are defines for the bit fields in the ADC_O_ACTSS register.
 //
 //*****************************************************************************
-#define ADC_ACTSS_ASEN3         0x00000008  // Sample sequence 3 enable
-#define ADC_ACTSS_ASEN2         0x00000004  // Sample sequence 2 enable
-#define ADC_ACTSS_ASEN1         0x00000002  // Sample sequence 1 enable
-#define ADC_ACTSS_ASEN0         0x00000001  // Sample sequence 0 enable
+#define ADC_ACTSS_ASEN3         0x00000008  // ADC SS3 Enable
+#define ADC_ACTSS_ASEN2         0x00000004  // ADC SS2 Enable
+#define ADC_ACTSS_ASEN1         0x00000002  // ADC SS1 Enable
+#define ADC_ACTSS_ASEN0         0x00000001  // ADC SS0 Enable
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the ADC_RIS register.
+// The following are defines for the bit fields in the ADC_O_RIS register.
 //
 //*****************************************************************************
 #define ADC_RIS_INRDC           0x00010000  // Digital Comparator Raw Interrupt
-                                            // Status.
-#define ADC_RIS_INR3            0x00000008  // Sample sequence 3 interrupt
-#define ADC_RIS_INR2            0x00000004  // Sample sequence 2 interrupt
-#define ADC_RIS_INR1            0x00000002  // Sample sequence 1 interrupt
-#define ADC_RIS_INR0            0x00000001  // Sample sequence 0 interrupt
+                                            // Status
+#define ADC_RIS_INR3            0x00000008  // SS3 Raw Interrupt Status
+#define ADC_RIS_INR2            0x00000004  // SS2 Raw Interrupt Status
+#define ADC_RIS_INR1            0x00000002  // SS1 Raw Interrupt Status
+#define ADC_RIS_INR0            0x00000001  // SS0 Raw Interrupt Status
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the ADC_IM register.
+// The following are defines for the bit fields in the ADC_O_IM register.
 //
 //*****************************************************************************
 #define ADC_IM_DCONSS3          0x00080000  // Digital Comparator Interrupt on
-                                            // SS3.
+                                            // SS3
 #define ADC_IM_DCONSS2          0x00040000  // Digital Comparator Interrupt on
-                                            // SS2.
+                                            // SS2
 #define ADC_IM_DCONSS1          0x00020000  // Digital Comparator Interrupt on
-                                            // SS1.
+                                            // SS1
 #define ADC_IM_DCONSS0          0x00010000  // Digital Comparator Interrupt on
-                                            // SS0.
-#define ADC_IM_MASK3            0x00000008  // Sample sequence 3 mask
-#define ADC_IM_MASK2            0x00000004  // Sample sequence 2 mask
-#define ADC_IM_MASK1            0x00000002  // Sample sequence 1 mask
-#define ADC_IM_MASK0            0x00000001  // Sample sequence 0 mask
+                                            // SS0
+#define ADC_IM_MASK3            0x00000008  // SS3 Interrupt Mask
+#define ADC_IM_MASK2            0x00000004  // SS2 Interrupt Mask
+#define ADC_IM_MASK1            0x00000002  // SS1 Interrupt Mask
+#define ADC_IM_MASK0            0x00000001  // SS0 Interrupt Mask
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the ADC_ISC register.
+// The following are defines for the bit fields in the ADC_O_ISC register.
 //
 //*****************************************************************************
 #define ADC_ISC_DCINSS3         0x00080000  // Digital Comparator Interrupt
-                                            // Status on SS3.
+                                            // Status on SS3
 #define ADC_ISC_DCINSS2         0x00040000  // Digital Comparator Interrupt
-                                            // Status on SS2.
+                                            // Status on SS2
 #define ADC_ISC_DCINSS1         0x00020000  // Digital Comparator Interrupt
-                                            // Status on SS1.
+                                            // Status on SS1
 #define ADC_ISC_DCINSS0         0x00010000  // Digital Comparator Interrupt
-                                            // Status on SS0.
-#define ADC_ISC_IN3             0x00000008  // Sample sequence 3 interrupt
-#define ADC_ISC_IN2             0x00000004  // Sample sequence 2 interrupt
-#define ADC_ISC_IN1             0x00000002  // Sample sequence 1 interrupt
-#define ADC_ISC_IN0             0x00000001  // Sample sequence 0 interrupt
+                                            // Status on SS0
+#define ADC_ISC_IN3             0x00000008  // SS3 Interrupt Status and Clear
+#define ADC_ISC_IN2             0x00000004  // SS2 Interrupt Status and Clear
+#define ADC_ISC_IN1             0x00000002  // SS1 Interrupt Status and Clear
+#define ADC_ISC_IN0             0x00000001  // SS0 Interrupt Status and Clear
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the ADC_OSTAT register.
+// The following are defines for the bit fields in the ADC_O_OSTAT register.
 //
 //*****************************************************************************
-#define ADC_OSTAT_OV3           0x00000008  // Sample sequence 3 overflow
-#define ADC_OSTAT_OV2           0x00000004  // Sample sequence 2 overflow
-#define ADC_OSTAT_OV1           0x00000002  // Sample sequence 1 overflow
-#define ADC_OSTAT_OV0           0x00000001  // Sample sequence 0 overflow
+#define ADC_OSTAT_OV3           0x00000008  // SS3 FIFO Overflow
+#define ADC_OSTAT_OV2           0x00000004  // SS2 FIFO Overflow
+#define ADC_OSTAT_OV1           0x00000002  // SS1 FIFO Overflow
+#define ADC_OSTAT_OV0           0x00000001  // SS0 FIFO Overflow
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the ADC_EMUX register.
+// The following are defines for the bit fields in the ADC_O_EMUX register.
 //
 //*****************************************************************************
-#define ADC_EMUX_EM3_M          0x0000F000  // Event mux 3 mask
-#define ADC_EMUX_EM3_PROCESSOR  0x00000000  // Processor event
-#define ADC_EMUX_EM3_COMP0      0x00001000  // Analog comparator 0 event
-#define ADC_EMUX_EM3_COMP1      0x00002000  // Analog comparator 1 event
-#define ADC_EMUX_EM3_COMP2      0x00003000  // Analog comparator 2 event
-#define ADC_EMUX_EM3_EXTERNAL   0x00004000  // External event
-#define ADC_EMUX_EM3_TIMER      0x00005000  // Timer event
-#define ADC_EMUX_EM3_PWM0       0x00006000  // PWM0 event
-#define ADC_EMUX_EM3_PWM1       0x00007000  // PWM1 event
-#define ADC_EMUX_EM3_PWM2       0x00008000  // PWM2 event
+#define ADC_EMUX_EM3_M          0x0000F000  // SS3 Trigger Select
+#define ADC_EMUX_EM3_PROCESSOR  0x00000000  // Processor (default)
+#define ADC_EMUX_EM3_COMP0      0x00001000  // Analog Comparator 0
+#define ADC_EMUX_EM3_COMP1      0x00002000  // Analog Comparator 1
+#define ADC_EMUX_EM3_COMP2      0x00003000  // Analog Comparator 2
+#define ADC_EMUX_EM3_EXTERNAL   0x00004000  // External (GPIO PB4)
+#define ADC_EMUX_EM3_TIMER      0x00005000  // Timer
+#define ADC_EMUX_EM3_PWM0       0x00006000  // PWM0
+#define ADC_EMUX_EM3_PWM1       0x00007000  // PWM1
+#define ADC_EMUX_EM3_PWM2       0x00008000  // PWM2
 #define ADC_EMUX_EM3_PWM3       0x00009000  // PWM3
-#define ADC_EMUX_EM3_ALWAYS     0x0000F000  // Always event
-#define ADC_EMUX_EM2_M          0x00000F00  // Event mux 2 mask
-#define ADC_EMUX_EM2_PROCESSOR  0x00000000  // Processor event
-#define ADC_EMUX_EM2_COMP0      0x00000100  // Analog comparator 0 event
-#define ADC_EMUX_EM2_COMP1      0x00000200  // Analog comparator 1 event
-#define ADC_EMUX_EM2_COMP2      0x00000300  // Analog comparator 2 event
-#define ADC_EMUX_EM2_EXTERNAL   0x00000400  // External event
-#define ADC_EMUX_EM2_TIMER      0x00000500  // Timer event
-#define ADC_EMUX_EM2_PWM0       0x00000600  // PWM0 event
-#define ADC_EMUX_EM2_PWM1       0x00000700  // PWM1 event
-#define ADC_EMUX_EM2_PWM2       0x00000800  // PWM2 event
+#define ADC_EMUX_EM3_ALWAYS     0x0000F000  // Always (continuously sample)
+#define ADC_EMUX_EM2_M          0x00000F00  // SS2 Trigger Select
+#define ADC_EMUX_EM2_PROCESSOR  0x00000000  // Processor (default)
+#define ADC_EMUX_EM2_COMP0      0x00000100  // Analog Comparator 0
+#define ADC_EMUX_EM2_COMP1      0x00000200  // Analog Comparator 1
+#define ADC_EMUX_EM2_COMP2      0x00000300  // Analog Comparator 2
+#define ADC_EMUX_EM2_EXTERNAL   0x00000400  // External (GPIO PB4)
+#define ADC_EMUX_EM2_TIMER      0x00000500  // Timer
+#define ADC_EMUX_EM2_PWM0       0x00000600  // PWM0
+#define ADC_EMUX_EM2_PWM1       0x00000700  // PWM1
+#define ADC_EMUX_EM2_PWM2       0x00000800  // PWM2
 #define ADC_EMUX_EM2_PWM3       0x00000900  // PWM3
-#define ADC_EMUX_EM2_ALWAYS     0x00000F00  // Always event
-#define ADC_EMUX_EM1_M          0x000000F0  // Event mux 1 mask
-#define ADC_EMUX_EM1_PROCESSOR  0x00000000  // Processor event
-#define ADC_EMUX_EM1_COMP0      0x00000010  // Analog comparator 0 event
-#define ADC_EMUX_EM1_COMP1      0x00000020  // Analog comparator 1 event
-#define ADC_EMUX_EM1_COMP2      0x00000030  // Analog comparator 2 event
-#define ADC_EMUX_EM1_EXTERNAL   0x00000040  // External event
-#define ADC_EMUX_EM1_TIMER      0x00000050  // Timer event
-#define ADC_EMUX_EM1_PWM0       0x00000060  // PWM0 event
-#define ADC_EMUX_EM1_PWM1       0x00000070  // PWM1 event
-#define ADC_EMUX_EM1_PWM2       0x00000080  // PWM2 event
+#define ADC_EMUX_EM2_ALWAYS     0x00000F00  // Always (continuously sample)
+#define ADC_EMUX_EM1_M          0x000000F0  // SS1 Trigger Select
+#define ADC_EMUX_EM1_PROCESSOR  0x00000000  // Processor (default)
+#define ADC_EMUX_EM1_COMP0      0x00000010  // Analog Comparator 0
+#define ADC_EMUX_EM1_COMP1      0x00000020  // Analog Comparator 1
+#define ADC_EMUX_EM1_COMP2      0x00000030  // Analog Comparator 2
+#define ADC_EMUX_EM1_EXTERNAL   0x00000040  // External (GPIO PB4)
+#define ADC_EMUX_EM1_TIMER      0x00000050  // Timer
+#define ADC_EMUX_EM1_PWM0       0x00000060  // PWM0
+#define ADC_EMUX_EM1_PWM1       0x00000070  // PWM1
+#define ADC_EMUX_EM1_PWM2       0x00000080  // PWM2
 #define ADC_EMUX_EM1_PWM3       0x00000090  // PWM3
-#define ADC_EMUX_EM1_ALWAYS     0x000000F0  // Always event
-#define ADC_EMUX_EM0_M          0x0000000F  // Event mux 0 mask
-#define ADC_EMUX_EM0_PROCESSOR  0x00000000  // Processor event
-#define ADC_EMUX_EM0_COMP0      0x00000001  // Analog comparator 0 event
-#define ADC_EMUX_EM0_COMP1      0x00000002  // Analog comparator 1 event
-#define ADC_EMUX_EM0_COMP2      0x00000003  // Analog comparator 2 event
-#define ADC_EMUX_EM0_EXTERNAL   0x00000004  // External event
-#define ADC_EMUX_EM0_TIMER      0x00000005  // Timer event
-#define ADC_EMUX_EM0_PWM0       0x00000006  // PWM0 event
-#define ADC_EMUX_EM0_PWM1       0x00000007  // PWM1 event
-#define ADC_EMUX_EM0_PWM2       0x00000008  // PWM2 event
+#define ADC_EMUX_EM1_ALWAYS     0x000000F0  // Always (continuously sample)
+#define ADC_EMUX_EM0_M          0x0000000F  // SS0 Trigger Select
+#define ADC_EMUX_EM0_PROCESSOR  0x00000000  // Processor (default)
+#define ADC_EMUX_EM0_COMP0      0x00000001  // Analog Comparator 0
+#define ADC_EMUX_EM0_COMP1      0x00000002  // Analog Comparator 1
+#define ADC_EMUX_EM0_COMP2      0x00000003  // Analog Comparator 2
+#define ADC_EMUX_EM0_EXTERNAL   0x00000004  // External (GPIO PB4)
+#define ADC_EMUX_EM0_TIMER      0x00000005  // Timer
+#define ADC_EMUX_EM0_PWM0       0x00000006  // PWM0
+#define ADC_EMUX_EM0_PWM1       0x00000007  // PWM1
+#define ADC_EMUX_EM0_PWM2       0x00000008  // PWM2
 #define ADC_EMUX_EM0_PWM3       0x00000009  // PWM3
-#define ADC_EMUX_EM0_ALWAYS     0x0000000F  // Always event
+#define ADC_EMUX_EM0_ALWAYS     0x0000000F  // Always (continuously sample)
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the ADC_USTAT register.
+// The following are defines for the bit fields in the ADC_O_USTAT register.
 //
 //*****************************************************************************
-#define ADC_USTAT_UV3           0x00000008  // Sample sequence 3 underflow
-#define ADC_USTAT_UV2           0x00000004  // Sample sequence 2 underflow
-#define ADC_USTAT_UV1           0x00000002  // Sample sequence 1 underflow
-#define ADC_USTAT_UV0           0x00000001  // Sample sequence 0 underflow
+#define ADC_USTAT_UV3           0x00000008  // SS3 FIFO Underflow
+#define ADC_USTAT_UV2           0x00000004  // SS2 FIFO Underflow
+#define ADC_USTAT_UV1           0x00000002  // SS1 FIFO Underflow
+#define ADC_USTAT_UV0           0x00000001  // SS0 FIFO Underflow
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the ADC_SSPRI register.
+// The following are defines for the bit fields in the ADC_O_SSPRI register.
 //
 //*****************************************************************************
-#define ADC_SSPRI_SS3_M         0x00003000  // Sequencer 3 priority mask
+#define ADC_SSPRI_SS3_M         0x00003000  // SS3 Priority
 #define ADC_SSPRI_SS3_1ST       0x00000000  // First priority
 #define ADC_SSPRI_SS3_2ND       0x00001000  // Second priority
 #define ADC_SSPRI_SS3_3RD       0x00002000  // Third priority
 #define ADC_SSPRI_SS3_4TH       0x00003000  // Fourth priority
-#define ADC_SSPRI_SS2_M         0x00000300  // Sequencer 2 priority mask
+#define ADC_SSPRI_SS2_M         0x00000300  // SS2 Priority
 #define ADC_SSPRI_SS2_1ST       0x00000000  // First priority
 #define ADC_SSPRI_SS2_2ND       0x00000100  // Second priority
 #define ADC_SSPRI_SS2_3RD       0x00000200  // Third priority
 #define ADC_SSPRI_SS2_4TH       0x00000300  // Fourth priority
-#define ADC_SSPRI_SS1_M         0x00000030  // Sequencer 1 priority mask
+#define ADC_SSPRI_SS1_M         0x00000030  // SS1 Priority
 #define ADC_SSPRI_SS1_1ST       0x00000000  // First priority
 #define ADC_SSPRI_SS1_2ND       0x00000010  // Second priority
 #define ADC_SSPRI_SS1_3RD       0x00000020  // Third priority
 #define ADC_SSPRI_SS1_4TH       0x00000030  // Fourth priority
-#define ADC_SSPRI_SS0_M         0x00000003  // Sequencer 0 priority mask
+#define ADC_SSPRI_SS0_M         0x00000003  // SS0 Priority
 #define ADC_SSPRI_SS0_1ST       0x00000000  // First priority
 #define ADC_SSPRI_SS0_2ND       0x00000001  // Second priority
 #define ADC_SSPRI_SS0_3RD       0x00000002  // Third priority
@@ -254,64 +265,108 @@
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the ADC_PSSI register.
+// The following are defines for the bit fields in the ADC_O_SPC register.
 //
 //*****************************************************************************
-#define ADC_PSSI_GSYNC          0x80000000  // Global Synchronize.
-#define ADC_PSSI_SYNCWAIT       0x08000000  // Synchronize Wait.
-#define ADC_PSSI_SS3            0x00000008  // Trigger sample sequencer 3
-#define ADC_PSSI_SS2            0x00000004  // Trigger sample sequencer 2
-#define ADC_PSSI_SS1            0x00000002  // Trigger sample sequencer 1
-#define ADC_PSSI_SS0            0x00000001  // Trigger sample sequencer 0
+#define ADC_SPC_PHASE_M         0x0000000F  // Phase Difference
+#define ADC_SPC_PHASE_0         0x00000000  // ADC sample lags by 0.0
+#define ADC_SPC_PHASE_22_5      0x00000001  // ADC sample lags by 22.5
+#define ADC_SPC_PHASE_45        0x00000002  // ADC sample lags by 45.0
+#define ADC_SPC_PHASE_67_5      0x00000003  // ADC sample lags by 67.5
+#define ADC_SPC_PHASE_90        0x00000004  // ADC sample lags by 90.0
+#define ADC_SPC_PHASE_112_5     0x00000005  // ADC sample lags by 112.5
+#define ADC_SPC_PHASE_135       0x00000006  // ADC sample lags by 135.0
+#define ADC_SPC_PHASE_157_5     0x00000007  // ADC sample lags by 157.5
+#define ADC_SPC_PHASE_180       0x00000008  // ADC sample lags by 180.0
+#define ADC_SPC_PHASE_202_5     0x00000009  // ADC sample lags by 202.5
+#define ADC_SPC_PHASE_225       0x0000000A  // ADC sample lags by 225.0
+#define ADC_SPC_PHASE_247_5     0x0000000B  // ADC sample lags by 247.5
+#define ADC_SPC_PHASE_270       0x0000000C  // ADC sample lags by 270.0
+#define ADC_SPC_PHASE_292_5     0x0000000D  // ADC sample lags by 292.5
+#define ADC_SPC_PHASE_315       0x0000000E  // ADC sample lags by 315.0
+#define ADC_SPC_PHASE_337_5     0x0000000F  // ADC sample lags by 337.5
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the ADC_SAC register.
+// The following are defines for the bit fields in the ADC_O_PSSI register.
 //
 //*****************************************************************************
-#define ADC_SAC_AVG_M           0x00000007  // Hardware Averaging Control.
-#define ADC_SAC_AVG_64X         0x00000006  // 64x hardware oversampling
-#define ADC_SAC_AVG_32X         0x00000005  // 32x hardware oversampling
-#define ADC_SAC_AVG_16X         0x00000004  // 16x hardware oversampling
-#define ADC_SAC_AVG_8X          0x00000003  // 8x hardware oversampling
-#define ADC_SAC_AVG_4X          0x00000002  // 4x hardware oversampling
-#define ADC_SAC_AVG_2X          0x00000001  // 2x hardware oversampling
+#define ADC_PSSI_GSYNC          0x80000000  // Global Synchronize
+#define ADC_PSSI_SYNCWAIT       0x08000000  // Synchronize Wait
+#define ADC_PSSI_SS3            0x00000008  // SS3 Initiate
+#define ADC_PSSI_SS2            0x00000004  // SS2 Initiate
+#define ADC_PSSI_SS1            0x00000002  // SS1 Initiate
+#define ADC_PSSI_SS0            0x00000001  // SS0 Initiate
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SAC register.
+//
+//*****************************************************************************
+#define ADC_SAC_AVG_M           0x00000007  // Hardware Averaging Control
 #define ADC_SAC_AVG_OFF         0x00000000  // No hardware oversampling
+#define ADC_SAC_AVG_2X          0x00000001  // 2x hardware oversampling
+#define ADC_SAC_AVG_4X          0x00000002  // 4x hardware oversampling
+#define ADC_SAC_AVG_8X          0x00000003  // 8x hardware oversampling
+#define ADC_SAC_AVG_16X         0x00000004  // 16x hardware oversampling
+#define ADC_SAC_AVG_32X         0x00000005  // 32x hardware oversampling
+#define ADC_SAC_AVG_64X         0x00000006  // 64x hardware oversampling
 
 //*****************************************************************************
 //
-// The following are defines for the the interpretation of the data in the
-// SSFIFOx when the ADC TMLB is enabled.
+// The following are defines for the bit fields in the ADC_O_DCISC register.
 //
 //*****************************************************************************
-#define ADC_SSFIFO_TMLB_CNT_M   0x000003C0  // Continuous Sample Counter.
-#define ADC_SSFIFO_TMLB_CONT    0x00000020  // Continuation Sample Indicator.
-#define ADC_SSFIFO_TMLB_DIFF    0x00000010  // Differential Sample Indicator.
-#define ADC_SSFIFO_TMLB_TS      0x00000008  // Temp Sensor Sample Indicator.
-#define ADC_SSFIFO_TMLB_MUX_M   0x00000007  // Analog Input Indicator.
-#define ADC_SSFIFO_TMLB_CNT_S   6           // Sample counter shift
-#define ADC_SSFIFO_TMLB_MUX_S   0           // Input channel number shift
+#define ADC_DCISC_DCINT7        0x00000080  // Digital Comparator 7 Interrupt
+                                            // Status and Clear
+#define ADC_DCISC_DCINT6        0x00000040  // Digital Comparator 6 Interrupt
+                                            // Status and Clear
+#define ADC_DCISC_DCINT5        0x00000020  // Digital Comparator 5 Interrupt
+                                            // Status and Clear
+#define ADC_DCISC_DCINT4        0x00000010  // Digital Comparator 4 Interrupt
+                                            // Status and Clear
+#define ADC_DCISC_DCINT3        0x00000008  // Digital Comparator 3 Interrupt
+                                            // Status and Clear
+#define ADC_DCISC_DCINT2        0x00000004  // Digital Comparator 2 Interrupt
+                                            // Status and Clear
+#define ADC_DCISC_DCINT1        0x00000002  // Digital Comparator 1 Interrupt
+                                            // Status and Clear
+#define ADC_DCISC_DCINT0        0x00000001  // Digital Comparator 0 Interrupt
+                                            // Status and Clear
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the ADC_TMLB register.
+// The following are defines for the bit fields in the ADC_O_CTL register.
 //
 //*****************************************************************************
-#define ADC_TMLB_LB             0x00000001  // Loopback control signals
+#define ADC_CTL_RES             0x00000010  // Sample Resolution
+#define ADC_CTL_VREF_M          0x00000003  // Voltage Reference Select
+#define ADC_CTL_VREF_INTERNAL   0x00000000  // The internal reference as the
+                                            // voltage reference
+#define ADC_CTL_VREF_EXT_3V     0x00000001  // A 3.0 V external VREFA input is
+                                            // the voltage reference. The ADC
+                                            // conversion range is 0.0 V to the
+                                            // external reference value
+#define ADC_CTL_VREF_EXT_1V     0x00000003  // A 1.0 V external VREFA input is
+                                            // the voltage reference. The ADC
+                                            // conversion range is 0.0 V to
+                                            // three times the external
+                                            // reference value
+#define ADC_CTL_VREF            0x00000001  // Voltage Reference Select
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the ADC_O_SSMUX0 register.
 //
 //*****************************************************************************
-#define ADC_SSMUX0_MUX7_M       0xF0000000  // 8th Sample Input Select.
-#define ADC_SSMUX0_MUX6_M       0x0F000000  // 7th Sample Input Select.
-#define ADC_SSMUX0_MUX5_M       0x00F00000  // 6th Sample Input Select.
-#define ADC_SSMUX0_MUX4_M       0x000F0000  // 5th Sample Input Select.
-#define ADC_SSMUX0_MUX3_M       0x0000F000  // 4th Sample Input Select.
-#define ADC_SSMUX0_MUX2_M       0x00000F00  // 3rd Sample Input Select.
-#define ADC_SSMUX0_MUX1_M       0x000000F0  // 2nd Sample Input Select.
-#define ADC_SSMUX0_MUX0_M       0x0000000F  // 1st Sample Input Select.
+#define ADC_SSMUX0_MUX7_M       0xF0000000  // 8th Sample Input Select
+#define ADC_SSMUX0_MUX6_M       0x0F000000  // 7th Sample Input Select
+#define ADC_SSMUX0_MUX5_M       0x00F00000  // 6th Sample Input Select
+#define ADC_SSMUX0_MUX4_M       0x000F0000  // 5th Sample Input Select
+#define ADC_SSMUX0_MUX3_M       0x0000F000  // 4th Sample Input Select
+#define ADC_SSMUX0_MUX2_M       0x00000F00  // 3rd Sample Input Select
+#define ADC_SSMUX0_MUX1_M       0x000000F0  // 2nd Sample Input Select
+#define ADC_SSMUX0_MUX0_M       0x0000000F  // 1st Sample Input Select
 #define ADC_SSMUX0_MUX7_S       28
 #define ADC_SSMUX0_MUX6_S       24
 #define ADC_SSMUX0_MUX5_S       20
@@ -326,45 +381,45 @@
 // The following are defines for the bit fields in the ADC_O_SSCTL0 register.
 //
 //*****************************************************************************
-#define ADC_SSCTL0_TS7          0x80000000  // 8th Sample Temp Sensor Select.
-#define ADC_SSCTL0_IE7          0x40000000  // 8th Sample Interrupt Enable.
-#define ADC_SSCTL0_END7         0x20000000  // 8th Sample is End of Sequence.
-#define ADC_SSCTL0_D7           0x10000000  // 8th Sample Diff Input Select.
-#define ADC_SSCTL0_TS6          0x08000000  // 7th Sample Temp Sensor Select.
-#define ADC_SSCTL0_IE6          0x04000000  // 7th Sample Interrupt Enable.
-#define ADC_SSCTL0_END6         0x02000000  // 7th Sample is End of Sequence.
-#define ADC_SSCTL0_D6           0x01000000  // 7th Sample Diff Input Select.
-#define ADC_SSCTL0_TS5          0x00800000  // 6th Sample Temp Sensor Select.
-#define ADC_SSCTL0_IE5          0x00400000  // 6th Sample Interrupt Enable.
-#define ADC_SSCTL0_END5         0x00200000  // 6th Sample is End of Sequence.
-#define ADC_SSCTL0_D5           0x00100000  // 6th Sample Diff Input Select.
-#define ADC_SSCTL0_TS4          0x00080000  // 5th Sample Temp Sensor Select.
-#define ADC_SSCTL0_IE4          0x00040000  // 5th Sample Interrupt Enable.
-#define ADC_SSCTL0_END4         0x00020000  // 5th Sample is End of Sequence.
-#define ADC_SSCTL0_D4           0x00010000  // 5th Sample Diff Input Select.
-#define ADC_SSCTL0_TS3          0x00008000  // 4th Sample Temp Sensor Select.
-#define ADC_SSCTL0_IE3          0x00004000  // 4th Sample Interrupt Enable.
-#define ADC_SSCTL0_END3         0x00002000  // 4th Sample is End of Sequence.
-#define ADC_SSCTL0_D3           0x00001000  // 4th Sample Diff Input Select.
-#define ADC_SSCTL0_TS2          0x00000800  // 3rd Sample Temp Sensor Select.
-#define ADC_SSCTL0_IE2          0x00000400  // 3rd Sample Interrupt Enable.
-#define ADC_SSCTL0_END2         0x00000200  // 3rd Sample is End of Sequence.
-#define ADC_SSCTL0_D2           0x00000100  // 3rd Sample Diff Input Select.
-#define ADC_SSCTL0_TS1          0x00000080  // 2nd Sample Temp Sensor Select.
-#define ADC_SSCTL0_IE1          0x00000040  // 2nd Sample Interrupt Enable.
-#define ADC_SSCTL0_END1         0x00000020  // 2nd Sample is End of Sequence.
-#define ADC_SSCTL0_D1           0x00000010  // 2nd Sample Diff Input Select.
-#define ADC_SSCTL0_TS0          0x00000008  // 1st Sample Temp Sensor Select.
-#define ADC_SSCTL0_IE0          0x00000004  // 1st Sample Interrupt Enable.
-#define ADC_SSCTL0_END0         0x00000002  // 1st Sample is End of Sequence.
-#define ADC_SSCTL0_D0           0x00000001  // 1st Sample Diff Input Select.
+#define ADC_SSCTL0_TS7          0x80000000  // 8th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE7          0x40000000  // 8th Sample Interrupt Enable
+#define ADC_SSCTL0_END7         0x20000000  // 8th Sample is End of Sequence
+#define ADC_SSCTL0_D7           0x10000000  // 8th Sample Diff Input Select
+#define ADC_SSCTL0_TS6          0x08000000  // 7th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE6          0x04000000  // 7th Sample Interrupt Enable
+#define ADC_SSCTL0_END6         0x02000000  // 7th Sample is End of Sequence
+#define ADC_SSCTL0_D6           0x01000000  // 7th Sample Diff Input Select
+#define ADC_SSCTL0_TS5          0x00800000  // 6th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE5          0x00400000  // 6th Sample Interrupt Enable
+#define ADC_SSCTL0_END5         0x00200000  // 6th Sample is End of Sequence
+#define ADC_SSCTL0_D5           0x00100000  // 6th Sample Diff Input Select
+#define ADC_SSCTL0_TS4          0x00080000  // 5th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE4          0x00040000  // 5th Sample Interrupt Enable
+#define ADC_SSCTL0_END4         0x00020000  // 5th Sample is End of Sequence
+#define ADC_SSCTL0_D4           0x00010000  // 5th Sample Diff Input Select
+#define ADC_SSCTL0_TS3          0x00008000  // 4th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE3          0x00004000  // 4th Sample Interrupt Enable
+#define ADC_SSCTL0_END3         0x00002000  // 4th Sample is End of Sequence
+#define ADC_SSCTL0_D3           0x00001000  // 4th Sample Diff Input Select
+#define ADC_SSCTL0_TS2          0x00000800  // 3rd Sample Temp Sensor Select
+#define ADC_SSCTL0_IE2          0x00000400  // 3rd Sample Interrupt Enable
+#define ADC_SSCTL0_END2         0x00000200  // 3rd Sample is End of Sequence
+#define ADC_SSCTL0_D2           0x00000100  // 3rd Sample Diff Input Select
+#define ADC_SSCTL0_TS1          0x00000080  // 2nd Sample Temp Sensor Select
+#define ADC_SSCTL0_IE1          0x00000040  // 2nd Sample Interrupt Enable
+#define ADC_SSCTL0_END1         0x00000020  // 2nd Sample is End of Sequence
+#define ADC_SSCTL0_D1           0x00000010  // 2nd Sample Diff Input Select
+#define ADC_SSCTL0_TS0          0x00000008  // 1st Sample Temp Sensor Select
+#define ADC_SSCTL0_IE0          0x00000004  // 1st Sample Interrupt Enable
+#define ADC_SSCTL0_END0         0x00000002  // 1st Sample is End of Sequence
+#define ADC_SSCTL0_D0           0x00000001  // 1st Sample Diff Input Select
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the ADC_O_SSFIFO0 register.
 //
 //*****************************************************************************
-#define ADC_SSFIFO0_DATA_M      0x000003FF  // Conversion Result Data.
+#define ADC_SSFIFO0_DATA_M      0x00000FFF  // Conversion Result Data
 #define ADC_SSFIFO0_DATA_S      0
 
 //*****************************************************************************
@@ -372,162 +427,34 @@
 // The following are defines for the bit fields in the ADC_O_SSFSTAT0 register.
 //
 //*****************************************************************************
-#define ADC_SSFSTAT0_FULL       0x00001000  // FIFO Full.
-#define ADC_SSFSTAT0_EMPTY      0x00000100  // FIFO Empty.
-#define ADC_SSFSTAT0_HPTR_M     0x000000F0  // FIFO Head Pointer.
-#define ADC_SSFSTAT0_TPTR_M     0x0000000F  // FIFO Tail Pointer.
+#define ADC_SSFSTAT0_FULL       0x00001000  // FIFO Full
+#define ADC_SSFSTAT0_EMPTY      0x00000100  // FIFO Empty
+#define ADC_SSFSTAT0_HPTR_M     0x000000F0  // FIFO Head Pointer
+#define ADC_SSFSTAT0_TPTR_M     0x0000000F  // FIFO Tail Pointer
 #define ADC_SSFSTAT0_HPTR_S     4
 #define ADC_SSFSTAT0_TPTR_S     0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the ADC_O_SSMUX1 register.
+// The following are defines for the bit fields in the ADC_O_SSOP0 register.
 //
 //*****************************************************************************
-#define ADC_SSMUX1_MUX3_M       0x0000F000  // 4th Sample Input Select.
-#define ADC_SSMUX1_MUX2_M       0x00000F00  // 3rd Sample Input Select.
-#define ADC_SSMUX1_MUX1_M       0x000000F0  // 2nd Sample Input Select.
-#define ADC_SSMUX1_MUX0_M       0x0000000F  // 1st Sample Input Select.
-#define ADC_SSMUX1_MUX3_S       12
-#define ADC_SSMUX1_MUX2_S       8
-#define ADC_SSMUX1_MUX1_S       4
-#define ADC_SSMUX1_MUX0_S       0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_SSCTL1 register.
-//
-//*****************************************************************************
-#define ADC_SSCTL1_TS3          0x00008000  // 4th Sample Temp Sensor Select.
-#define ADC_SSCTL1_IE3          0x00004000  // 4th Sample Interrupt Enable.
-#define ADC_SSCTL1_END3         0x00002000  // 4th Sample is End of Sequence.
-#define ADC_SSCTL1_D3           0x00001000  // 4th Sample Diff Input Select.
-#define ADC_SSCTL1_TS2          0x00000800  // 3rd Sample Temp Sensor Select.
-#define ADC_SSCTL1_IE2          0x00000400  // 3rd Sample Interrupt Enable.
-#define ADC_SSCTL1_END2         0x00000200  // 3rd Sample is End of Sequence.
-#define ADC_SSCTL1_D2           0x00000100  // 3rd Sample Diff Input Select.
-#define ADC_SSCTL1_TS1          0x00000080  // 2nd Sample Temp Sensor Select.
-#define ADC_SSCTL1_IE1          0x00000040  // 2nd Sample Interrupt Enable.
-#define ADC_SSCTL1_END1         0x00000020  // 2nd Sample is End of Sequence.
-#define ADC_SSCTL1_D1           0x00000010  // 2nd Sample Diff Input Select.
-#define ADC_SSCTL1_TS0          0x00000008  // 1st Sample Temp Sensor Select.
-#define ADC_SSCTL1_IE0          0x00000004  // 1st Sample Interrupt Enable.
-#define ADC_SSCTL1_END0         0x00000002  // 1st Sample is End of Sequence.
-#define ADC_SSCTL1_D0           0x00000001  // 1st Sample Diff Input Select.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_SSFIFO1 register.
-//
-//*****************************************************************************
-#define ADC_SSFIFO1_DATA_M      0x000003FF  // Conversion Result Data.
-#define ADC_SSFIFO1_DATA_S      0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_SSFSTAT1 register.
-//
-//*****************************************************************************
-#define ADC_SSFSTAT1_FULL       0x00001000  // FIFO Full.
-#define ADC_SSFSTAT1_EMPTY      0x00000100  // FIFO Empty.
-#define ADC_SSFSTAT1_HPTR_M     0x000000F0  // FIFO Head Pointer.
-#define ADC_SSFSTAT1_TPTR_M     0x0000000F  // FIFO Tail Pointer.
-#define ADC_SSFSTAT1_HPTR_S     4
-#define ADC_SSFSTAT1_TPTR_S     0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_SSMUX2 register.
-//
-//*****************************************************************************
-#define ADC_SSMUX2_MUX3_M       0x0000F000  // 4th Sample Input Select.
-#define ADC_SSMUX2_MUX2_M       0x00000F00  // 3rd Sample Input Select.
-#define ADC_SSMUX2_MUX1_M       0x000000F0  // 2nd Sample Input Select.
-#define ADC_SSMUX2_MUX0_M       0x0000000F  // 1st Sample Input Select.
-#define ADC_SSMUX2_MUX3_S       12
-#define ADC_SSMUX2_MUX2_S       8
-#define ADC_SSMUX2_MUX1_S       4
-#define ADC_SSMUX2_MUX0_S       0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_SSCTL2 register.
-//
-//*****************************************************************************
-#define ADC_SSCTL2_TS3          0x00008000  // 4th Sample Temp Sensor Select.
-#define ADC_SSCTL2_IE3          0x00004000  // 4th Sample Interrupt Enable.
-#define ADC_SSCTL2_END3         0x00002000  // 4th Sample is End of Sequence.
-#define ADC_SSCTL2_D3           0x00001000  // 4th Sample Diff Input Select.
-#define ADC_SSCTL2_TS2          0x00000800  // 3rd Sample Temp Sensor Select.
-#define ADC_SSCTL2_IE2          0x00000400  // 3rd Sample Interrupt Enable.
-#define ADC_SSCTL2_END2         0x00000200  // 3rd Sample is End of Sequence.
-#define ADC_SSCTL2_D2           0x00000100  // 3rd Sample Diff Input Select.
-#define ADC_SSCTL2_TS1          0x00000080  // 2nd Sample Temp Sensor Select.
-#define ADC_SSCTL2_IE1          0x00000040  // 2nd Sample Interrupt Enable.
-#define ADC_SSCTL2_END1         0x00000020  // 2nd Sample is End of Sequence.
-#define ADC_SSCTL2_D1           0x00000010  // 2nd Sample Diff Input Select.
-#define ADC_SSCTL2_TS0          0x00000008  // 1st Sample Temp Sensor Select.
-#define ADC_SSCTL2_IE0          0x00000004  // 1st Sample Interrupt Enable.
-#define ADC_SSCTL2_END0         0x00000002  // 1st Sample is End of Sequence.
-#define ADC_SSCTL2_D0           0x00000001  // 1st Sample Diff Input Select.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_SSFIFO2 register.
-//
-//*****************************************************************************
-#define ADC_SSFIFO2_DATA_M      0x000003FF  // Conversion Result Data.
-#define ADC_SSFIFO2_DATA_S      0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_SSFSTAT2 register.
-//
-//*****************************************************************************
-#define ADC_SSFSTAT2_FULL       0x00001000  // FIFO Full.
-#define ADC_SSFSTAT2_EMPTY      0x00000100  // FIFO Empty.
-#define ADC_SSFSTAT2_HPTR_M     0x000000F0  // FIFO Head Pointer.
-#define ADC_SSFSTAT2_TPTR_M     0x0000000F  // FIFO Tail Pointer.
-#define ADC_SSFSTAT2_HPTR_S     4
-#define ADC_SSFSTAT2_TPTR_S     0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_SSMUX3 register.
-//
-//*****************************************************************************
-#define ADC_SSMUX3_MUX0_M       0x0000000F  // 1st Sample Input Select.
-#define ADC_SSMUX3_MUX0_S       0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_SSCTL3 register.
-//
-//*****************************************************************************
-#define ADC_SSCTL3_TS0          0x00000008  // 1st Sample Temp Sensor Select.
-#define ADC_SSCTL3_IE0          0x00000004  // 1st Sample Interrupt Enable.
-#define ADC_SSCTL3_END0         0x00000002  // 1st Sample is End of Sequence.
-#define ADC_SSCTL3_D0           0x00000001  // 1st Sample Diff Input Select.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_SSFIFO3 register.
-//
-//*****************************************************************************
-#define ADC_SSFIFO3_DATA_M      0x000003FF  // Conversion Result Data.
-#define ADC_SSFIFO3_DATA_S      0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_SSFSTAT3 register.
-//
-//*****************************************************************************
-#define ADC_SSFSTAT3_FULL       0x00001000  // FIFO Full.
-#define ADC_SSFSTAT3_EMPTY      0x00000100  // FIFO Empty.
-#define ADC_SSFSTAT3_HPTR_M     0x000000F0  // FIFO Head Pointer.
-#define ADC_SSFSTAT3_TPTR_M     0x0000000F  // FIFO Tail Pointer.
-#define ADC_SSFSTAT3_HPTR_S     4
-#define ADC_SSFSTAT3_TPTR_S     0
+#define ADC_SSOP0_S7DCOP        0x10000000  // Sample 7 Digital Comparator
+                                            // Operation
+#define ADC_SSOP0_S6DCOP        0x01000000  // Sample 6 Digital Comparator
+                                            // Operation
+#define ADC_SSOP0_S5DCOP        0x00100000  // Sample 5 Digital Comparator
+                                            // Operation
+#define ADC_SSOP0_S4DCOP        0x00010000  // Sample 4 Digital Comparator
+                                            // Operation
+#define ADC_SSOP0_S3DCOP        0x00001000  // Sample 3 Digital Comparator
+                                            // Operation
+#define ADC_SSOP0_S2DCOP        0x00000100  // Sample 2 Digital Comparator
+                                            // Operation
+#define ADC_SSOP0_S1DCOP        0x00000010  // Sample 1 Digital Comparator
+                                            // Operation
+#define ADC_SSOP0_S0DCOP        0x00000001  // Sample 0 Digital Comparator
+                                            // Operation
 
 //*****************************************************************************
 //
@@ -535,21 +462,21 @@
 //
 //*****************************************************************************
 #define ADC_SSDC0_S7DCSEL_M     0xF0000000  // Sample 7 Digital Comparator
-                                            // Select.
+                                            // Select
 #define ADC_SSDC0_S6DCSEL_M     0x0F000000  // Sample 6 Digital Comparator
-                                            // Select.
+                                            // Select
 #define ADC_SSDC0_S5DCSEL_M     0x00F00000  // Sample 5 Digital Comparator
-                                            // Select.
+                                            // Select
 #define ADC_SSDC0_S4DCSEL_M     0x000F0000  // Sample 4 Digital Comparator
-                                            // Select.
+                                            // Select
 #define ADC_SSDC0_S3DCSEL_M     0x0000F000  // Sample 3 Digital Comparator
-                                            // Select.
+                                            // Select
 #define ADC_SSDC0_S2DCSEL_M     0x00000F00  // Sample 2 Digital Comparator
-                                            // Select.
+                                            // Select
 #define ADC_SSDC0_S1DCSEL_M     0x000000F0  // Sample 1 Digital Comparator
-                                            // Select.
+                                            // Select
 #define ADC_SSDC0_S0DCSEL_M     0x0000000F  // Sample 0 Digital Comparator
-                                            // Select.
+                                            // Select
 #define ADC_SSDC0_S6DCSEL_S     24
 #define ADC_SSDC0_S5DCSEL_S     20
 #define ADC_SSDC0_S4DCSEL_S     16
@@ -558,365 +485,478 @@
 #define ADC_SSDC0_S1DCSEL_S     4
 #define ADC_SSDC0_S0DCSEL_S     0
 
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX1 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX1_MUX3_M       0x0000F000  // 4th Sample Input Select
+#define ADC_SSMUX1_MUX2_M       0x00000F00  // 3rd Sample Input Select
+#define ADC_SSMUX1_MUX1_M       0x000000F0  // 2nd Sample Input Select
+#define ADC_SSMUX1_MUX0_M       0x0000000F  // 1st Sample Input Select
+#define ADC_SSMUX1_MUX3_S       12
+#define ADC_SSMUX1_MUX2_S       8
+#define ADC_SSMUX1_MUX1_S       4
+#define ADC_SSMUX1_MUX0_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL1 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL1_TS3          0x00008000  // 4th Sample Temp Sensor Select
+#define ADC_SSCTL1_IE3          0x00004000  // 4th Sample Interrupt Enable
+#define ADC_SSCTL1_END3         0x00002000  // 4th Sample is End of Sequence
+#define ADC_SSCTL1_D3           0x00001000  // 4th Sample Diff Input Select
+#define ADC_SSCTL1_TS2          0x00000800  // 3rd Sample Temp Sensor Select
+#define ADC_SSCTL1_IE2          0x00000400  // 3rd Sample Interrupt Enable
+#define ADC_SSCTL1_END2         0x00000200  // 3rd Sample is End of Sequence
+#define ADC_SSCTL1_D2           0x00000100  // 3rd Sample Diff Input Select
+#define ADC_SSCTL1_TS1          0x00000080  // 2nd Sample Temp Sensor Select
+#define ADC_SSCTL1_IE1          0x00000040  // 2nd Sample Interrupt Enable
+#define ADC_SSCTL1_END1         0x00000020  // 2nd Sample is End of Sequence
+#define ADC_SSCTL1_D1           0x00000010  // 2nd Sample Diff Input Select
+#define ADC_SSCTL1_TS0          0x00000008  // 1st Sample Temp Sensor Select
+#define ADC_SSCTL1_IE0          0x00000004  // 1st Sample Interrupt Enable
+#define ADC_SSCTL1_END0         0x00000002  // 1st Sample is End of Sequence
+#define ADC_SSCTL1_D0           0x00000001  // 1st Sample Diff Input Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO1 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO1_DATA_M      0x00000FFF  // Conversion Result Data
+#define ADC_SSFIFO1_DATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT1 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT1_FULL       0x00001000  // FIFO Full
+#define ADC_SSFSTAT1_EMPTY      0x00000100  // FIFO Empty
+#define ADC_SSFSTAT1_HPTR_M     0x000000F0  // FIFO Head Pointer
+#define ADC_SSFSTAT1_TPTR_M     0x0000000F  // FIFO Tail Pointer
+#define ADC_SSFSTAT1_HPTR_S     4
+#define ADC_SSFSTAT1_TPTR_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSOP1 register.
+//
+//*****************************************************************************
+#define ADC_SSOP1_S3DCOP        0x00001000  // Sample 3 Digital Comparator
+                                            // Operation
+#define ADC_SSOP1_S2DCOP        0x00000100  // Sample 2 Digital Comparator
+                                            // Operation
+#define ADC_SSOP1_S1DCOP        0x00000010  // Sample 1 Digital Comparator
+                                            // Operation
+#define ADC_SSOP1_S0DCOP        0x00000001  // Sample 0 Digital Comparator
+                                            // Operation
+
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the ADC_O_SSDC1 register.
 //
 //*****************************************************************************
 #define ADC_SSDC1_S3DCSEL_M     0x0000F000  // Sample 3 Digital Comparator
-                                            // Select.
+                                            // Select
 #define ADC_SSDC1_S2DCSEL_M     0x00000F00  // Sample 2 Digital Comparator
-                                            // Select.
+                                            // Select
 #define ADC_SSDC1_S1DCSEL_M     0x000000F0  // Sample 1 Digital Comparator
-                                            // Select.
+                                            // Select
 #define ADC_SSDC1_S0DCSEL_M     0x0000000F  // Sample 0 Digital Comparator
-                                            // Select.
+                                            // Select
 #define ADC_SSDC1_S2DCSEL_S     8
 #define ADC_SSDC1_S1DCSEL_S     4
 #define ADC_SSDC1_S0DCSEL_S     0
 
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX2 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX2_MUX3_M       0x0000F000  // 4th Sample Input Select
+#define ADC_SSMUX2_MUX2_M       0x00000F00  // 3rd Sample Input Select
+#define ADC_SSMUX2_MUX1_M       0x000000F0  // 2nd Sample Input Select
+#define ADC_SSMUX2_MUX0_M       0x0000000F  // 1st Sample Input Select
+#define ADC_SSMUX2_MUX3_S       12
+#define ADC_SSMUX2_MUX2_S       8
+#define ADC_SSMUX2_MUX1_S       4
+#define ADC_SSMUX2_MUX0_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL2 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL2_TS3          0x00008000  // 4th Sample Temp Sensor Select
+#define ADC_SSCTL2_IE3          0x00004000  // 4th Sample Interrupt Enable
+#define ADC_SSCTL2_END3         0x00002000  // 4th Sample is End of Sequence
+#define ADC_SSCTL2_D3           0x00001000  // 4th Sample Diff Input Select
+#define ADC_SSCTL2_TS2          0x00000800  // 3rd Sample Temp Sensor Select
+#define ADC_SSCTL2_IE2          0x00000400  // 3rd Sample Interrupt Enable
+#define ADC_SSCTL2_END2         0x00000200  // 3rd Sample is End of Sequence
+#define ADC_SSCTL2_D2           0x00000100  // 3rd Sample Diff Input Select
+#define ADC_SSCTL2_TS1          0x00000080  // 2nd Sample Temp Sensor Select
+#define ADC_SSCTL2_IE1          0x00000040  // 2nd Sample Interrupt Enable
+#define ADC_SSCTL2_END1         0x00000020  // 2nd Sample is End of Sequence
+#define ADC_SSCTL2_D1           0x00000010  // 2nd Sample Diff Input Select
+#define ADC_SSCTL2_TS0          0x00000008  // 1st Sample Temp Sensor Select
+#define ADC_SSCTL2_IE0          0x00000004  // 1st Sample Interrupt Enable
+#define ADC_SSCTL2_END0         0x00000002  // 1st Sample is End of Sequence
+#define ADC_SSCTL2_D0           0x00000001  // 1st Sample Diff Input Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO2 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO2_DATA_M      0x00000FFF  // Conversion Result Data
+#define ADC_SSFIFO2_DATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT2 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT2_FULL       0x00001000  // FIFO Full
+#define ADC_SSFSTAT2_EMPTY      0x00000100  // FIFO Empty
+#define ADC_SSFSTAT2_HPTR_M     0x000000F0  // FIFO Head Pointer
+#define ADC_SSFSTAT2_TPTR_M     0x0000000F  // FIFO Tail Pointer
+#define ADC_SSFSTAT2_HPTR_S     4
+#define ADC_SSFSTAT2_TPTR_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSOP2 register.
+//
+//*****************************************************************************
+#define ADC_SSOP2_S3DCOP        0x00001000  // Sample 3 Digital Comparator
+                                            // Operation
+#define ADC_SSOP2_S2DCOP        0x00000100  // Sample 2 Digital Comparator
+                                            // Operation
+#define ADC_SSOP2_S1DCOP        0x00000010  // Sample 1 Digital Comparator
+                                            // Operation
+#define ADC_SSOP2_S0DCOP        0x00000001  // Sample 0 Digital Comparator
+                                            // Operation
+
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the ADC_O_SSDC2 register.
 //
 //*****************************************************************************
 #define ADC_SSDC2_S3DCSEL_M     0x0000F000  // Sample 3 Digital Comparator
-                                            // Select.
+                                            // Select
 #define ADC_SSDC2_S2DCSEL_M     0x00000F00  // Sample 2 Digital Comparator
-                                            // Select.
+                                            // Select
 #define ADC_SSDC2_S1DCSEL_M     0x000000F0  // Sample 1 Digital Comparator
-                                            // Select.
+                                            // Select
 #define ADC_SSDC2_S0DCSEL_M     0x0000000F  // Sample 0 Digital Comparator
-                                            // Select.
+                                            // Select
 #define ADC_SSDC2_S2DCSEL_S     8
 #define ADC_SSDC2_S1DCSEL_S     4
 #define ADC_SSDC2_S0DCSEL_S     0
 
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX3 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX3_MUX0_M       0x0000000F  // 1st Sample Input Select
+#define ADC_SSMUX3_MUX0_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL3 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL3_TS0          0x00000008  // 1st Sample Temp Sensor Select
+#define ADC_SSCTL3_IE0          0x00000004  // 1st Sample Interrupt Enable
+#define ADC_SSCTL3_END0         0x00000002  // 1st Sample is End of Sequence
+#define ADC_SSCTL3_D0           0x00000001  // 1st Sample Diff Input Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO3 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO3_DATA_M      0x00000FFF  // Conversion Result Data
+#define ADC_SSFIFO3_DATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT3 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT3_FULL       0x00001000  // FIFO Full
+#define ADC_SSFSTAT3_EMPTY      0x00000100  // FIFO Empty
+#define ADC_SSFSTAT3_HPTR_M     0x000000F0  // FIFO Head Pointer
+#define ADC_SSFSTAT3_TPTR_M     0x0000000F  // FIFO Tail Pointer
+#define ADC_SSFSTAT3_HPTR_S     4
+#define ADC_SSFSTAT3_TPTR_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSOP3 register.
+//
+//*****************************************************************************
+#define ADC_SSOP3_S0DCOP        0x00000001  // Sample 0 Digital Comparator
+                                            // Operation
+
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the ADC_O_SSDC3 register.
 //
 //*****************************************************************************
 #define ADC_SSDC3_S0DCSEL_M     0x0000000F  // Sample 0 Digital Comparator
-                                            // Select.
+                                            // Select
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the ADC_O_DCISC register.
+// The following are defines for the bit fields in the ADC_O_TMLB register.
 //
 //*****************************************************************************
-#define ADC_DCISC_DCINT7        0x00000080  // Digital Comparator 7 Interrupt
-                                            // Status and Clear.
-#define ADC_DCISC_DCINT6        0x00000040  // Digital Comparator 6 Interrupt
-                                            // Status and Clear.
-#define ADC_DCISC_DCINT5        0x00000020  // Digital Comparator 5 Interrupt
-                                            // Status and Clear.
-#define ADC_DCISC_DCINT4        0x00000010  // Digital Comparator 4 Interrupt
-                                            // Status and Clear.
-#define ADC_DCISC_DCINT3        0x00000008  // Digital Comparator 3 Interrupt
-                                            // Status and Clear.
-#define ADC_DCISC_DCINT2        0x00000004  // Digital Comparator 2 Interrupt
-                                            // Status and Clear.
-#define ADC_DCISC_DCINT1        0x00000002  // Digital Comparator 1 Interrupt
-                                            // Status and Clear.
-#define ADC_DCISC_DCINT0        0x00000001  // Digital Comparator 0 Interrupt
-                                            // Status and Clear.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_SSOP0 register.
-//
-//*****************************************************************************
-#define ADC_SSOP0_S7DCOP        0x10000000  // Sample 7 Digital Comparator
-                                            // Operation.
-#define ADC_SSOP0_S6DCOP        0x01000000  // Sample 6 Digital Comparator
-                                            // Operation.
-#define ADC_SSOP0_S5DCOP        0x00100000  // Sample 5 Digital Comparator
-                                            // Operation.
-#define ADC_SSOP0_S4DCOP        0x00010000  // Sample 4 Digital Comparator
-                                            // Operation.
-#define ADC_SSOP0_S3DCOP        0x00001000  // Sample 3 Digital Comparator
-                                            // Operation.
-#define ADC_SSOP0_S2DCOP        0x00000100  // Sample 2 Digital Comparator
-                                            // Operation.
-#define ADC_SSOP0_S1DCOP        0x00000010  // Sample 1 Digital Comparator
-                                            // Operation.
-#define ADC_SSOP0_S0DCOP        0x00000001  // Sample 0 Digital Comparator
-                                            // Operation.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_SSOP1 register.
-//
-//*****************************************************************************
-#define ADC_SSOP1_S3DCOP        0x00001000  // Sample 7 Digital Comparator
-                                            // Operation.
-#define ADC_SSOP1_S2DCOP        0x00000100  // Sample 2 Digital Comparator
-                                            // Operation.
-#define ADC_SSOP1_S1DCOP        0x00000010  // Sample 1 Digital Comparator
-                                            // Operation.
-#define ADC_SSOP1_S0DCOP        0x00000001  // Sample 0 Digital Comparator
-                                            // Operation.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_SSOP2 register.
-//
-//*****************************************************************************
-#define ADC_SSOP2_S3DCOP        0x00001000  // Sample 7 Digital Comparator
-                                            // Operation.
-#define ADC_SSOP2_S2DCOP        0x00000100  // Sample 2 Digital Comparator
-                                            // Operation.
-#define ADC_SSOP2_S1DCOP        0x00000010  // Sample 1 Digital Comparator
-                                            // Operation.
-#define ADC_SSOP2_S0DCOP        0x00000001  // Sample 0 Digital Comparator
-                                            // Operation.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_SSOP3 register.
-//
-//*****************************************************************************
-#define ADC_SSOP3_S0DCOP        0x00000001  // Sample 7 Digital Comparator
-                                            // Operation.
+#define ADC_TMLB_LB             0x00000001  // Loopback Mode Enable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the ADC_O_DCRIC register.
 //
 //*****************************************************************************
-#define ADC_DCRIC_DCTRIG7       0x00800000  // Digital Comparator Trigger 7.
-#define ADC_DCRIC_DCTRIG6       0x00400000  // Digital Comparator Trigger 6.
-#define ADC_DCRIC_DCTRIG5       0x00200000  // Digital Comparator Trigger 5.
-#define ADC_DCRIC_DCTRIG4       0x00100000  // Digital Comparator Trigger 4.
-#define ADC_DCRIC_DCTRIG3       0x00080000  // Digital Comparator Trigger 3.
-#define ADC_DCRIC_DCTRIG2       0x00040000  // Digital Comparator Trigger 2.
-#define ADC_DCRIC_DCTRIG1       0x00020000  // Digital Comparator Trigger 1.
-#define ADC_DCRIC_DCTRIG0       0x00010000  // Digital Comparator Trigger 0.
-#define ADC_DCRIC_DCINT7        0x00000080  // Digital Comparator Interrupt 7.
-#define ADC_DCRIC_DCINT6        0x00000040  // Digital Comparator Interrupt 6.
-#define ADC_DCRIC_DCINT5        0x00000020  // Digital Comparator Interrupt 5.
-#define ADC_DCRIC_DCINT4        0x00000010  // Digital Comparator Interrupt 4.
-#define ADC_DCRIC_DCINT3        0x00000008  // Digital Comparator Interrupt 3.
-#define ADC_DCRIC_DCINT2        0x00000004  // Digital Comparator Interrupt 2.
-#define ADC_DCRIC_DCINT1        0x00000002  // Digital Comparator Interrupt 1.
-#define ADC_DCRIC_DCINT0        0x00000001  // Digital Comparator Interrupt 0.
+#define ADC_DCRIC_DCTRIG7       0x00800000  // Digital Comparator Trigger 7
+#define ADC_DCRIC_DCTRIG6       0x00400000  // Digital Comparator Trigger 6
+#define ADC_DCRIC_DCTRIG5       0x00200000  // Digital Comparator Trigger 5
+#define ADC_DCRIC_DCTRIG4       0x00100000  // Digital Comparator Trigger 4
+#define ADC_DCRIC_DCTRIG3       0x00080000  // Digital Comparator Trigger 3
+#define ADC_DCRIC_DCTRIG2       0x00040000  // Digital Comparator Trigger 2
+#define ADC_DCRIC_DCTRIG1       0x00020000  // Digital Comparator Trigger 1
+#define ADC_DCRIC_DCTRIG0       0x00010000  // Digital Comparator Trigger 0
+#define ADC_DCRIC_DCINT7        0x00000080  // Digital Comparator Interrupt 7
+#define ADC_DCRIC_DCINT6        0x00000040  // Digital Comparator Interrupt 6
+#define ADC_DCRIC_DCINT5        0x00000020  // Digital Comparator Interrupt 5
+#define ADC_DCRIC_DCINT4        0x00000010  // Digital Comparator Interrupt 4
+#define ADC_DCRIC_DCINT3        0x00000008  // Digital Comparator Interrupt 3
+#define ADC_DCRIC_DCINT2        0x00000004  // Digital Comparator Interrupt 2
+#define ADC_DCRIC_DCINT1        0x00000002  // Digital Comparator Interrupt 1
+#define ADC_DCRIC_DCINT0        0x00000001  // Digital Comparator Interrupt 0
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the ADC_O_DCCTL0 register.
 //
 //*****************************************************************************
-#define ADC_DCCTL0_CTE          0x00001000  // Comparison Trigger Enable.
-#define ADC_DCCTL0_CTC_M        0x00000C00  // Comparison Trigger Condition.
-#define ADC_DCCTL0_CTC_LOW      0x00000000  // CV < COMP0 and < COMP1
-#define ADC_DCCTL0_CTC_MID      0x00000400  // COMP0 >= CV < COMP1
-#define ADC_DCCTL0_CTC_HIGH     0x00000C00  // CV <= COMP0 and <= COMP1
-#define ADC_DCCTL0_CTM_M        0x00000300  // Comparison Trigger Mode.
+#define ADC_DCCTL0_CTE          0x00001000  // Comparison Trigger Enable
+#define ADC_DCCTL0_CTC_M        0x00000C00  // Comparison Trigger Condition
+#define ADC_DCCTL0_CTC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL0_CTC_MID      0x00000400  // Mid Band
+#define ADC_DCCTL0_CTC_HIGH     0x00000C00  // High Band
+#define ADC_DCCTL0_CTM_M        0x00000300  // Comparison Trigger Mode
 #define ADC_DCCTL0_CTM_ALWAYS   0x00000000  // Always
 #define ADC_DCCTL0_CTM_ONCE     0x00000100  // Once
-#define ADC_DCCTL0_CTM_HALWAYS  0x00000200  // Hysteresis always
-#define ADC_DCCTL0_CTM_HONCE    0x00000300  // Hysteresis once
-#define ADC_DCCTL0_CIE          0x00000010  // Comparison Interrupt Enable.
-#define ADC_DCCTL0_CIC_M        0x0000000C  // Comparison Interrupt Condition.
-#define ADC_DCCTL0_CIC_LOW      0x00000000  // CV < COMP0 and < COMP1
-#define ADC_DCCTL0_CIC_MID      0x00000004  // COMP0 >= CV < COMP1
-#define ADC_DCCTL0_CIC_HIGH     0x0000000C  // CV <= COMP0 and <= COMP1
-#define ADC_DCCTL0_CIM_M        0x00000003  // Comparison Interrupt Mode.
+#define ADC_DCCTL0_CTM_HALWAYS  0x00000200  // Hysteresis Always
+#define ADC_DCCTL0_CTM_HONCE    0x00000300  // Hysteresis Once
+#define ADC_DCCTL0_CIE          0x00000010  // Comparison Interrupt Enable
+#define ADC_DCCTL0_CIC_M        0x0000000C  // Comparison Interrupt Condition
+#define ADC_DCCTL0_CIC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL0_CIC_MID      0x00000004  // Mid Band
+#define ADC_DCCTL0_CIC_HIGH     0x0000000C  // High Band
+#define ADC_DCCTL0_CIM_M        0x00000003  // Comparison Interrupt Mode
 #define ADC_DCCTL0_CIM_ALWAYS   0x00000000  // Always
 #define ADC_DCCTL0_CIM_ONCE     0x00000001  // Once
-#define ADC_DCCTL0_CIM_HALWAYS  0x00000002  // Hysteresis always
-#define ADC_DCCTL0_CIM_HONCE    0x00000003  // Hysteresis once
+#define ADC_DCCTL0_CIM_HALWAYS  0x00000002  // Hysteresis Always
+#define ADC_DCCTL0_CIM_HONCE    0x00000003  // Hysteresis Once
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the ADC_O_DCCTL1 register.
 //
 //*****************************************************************************
-#define ADC_DCCTL1_CTE          0x00001000  // Comparison Trigger Enable.
-#define ADC_DCCTL1_CTC_M        0x00000C00  // Comparison Trigger Condition.
-#define ADC_DCCTL1_CTC_LOW      0x00000000  // CV < COMP0 and < COMP1
-#define ADC_DCCTL1_CTC_MID      0x00000400  // COMP0 >= CV < COMP1
-#define ADC_DCCTL1_CTC_HIGH     0x00000C00  // CV <= COMP0 and <= COMP1
-#define ADC_DCCTL1_CTM_M        0x00000300  // Comparison Trigger Mode.
+#define ADC_DCCTL1_CTE          0x00001000  // Comparison Trigger Enable
+#define ADC_DCCTL1_CTC_M        0x00000C00  // Comparison Trigger Condition
+#define ADC_DCCTL1_CTC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL1_CTC_MID      0x00000400  // Mid Band
+#define ADC_DCCTL1_CTC_HIGH     0x00000C00  // High Band
+#define ADC_DCCTL1_CTM_M        0x00000300  // Comparison Trigger Mode
 #define ADC_DCCTL1_CTM_ALWAYS   0x00000000  // Always
 #define ADC_DCCTL1_CTM_ONCE     0x00000100  // Once
-#define ADC_DCCTL1_CTM_HALWAYS  0x00000200  // Hysteresis always
-#define ADC_DCCTL1_CTM_HONCE    0x00000300  // Hysteresis once
-#define ADC_DCCTL1_CIE          0x00000010  // Comparison Interrupt Enable.
-#define ADC_DCCTL1_CIC_M        0x0000000C  // Comparison Interrupt Condition.
-#define ADC_DCCTL1_CIC_LOW      0x00000000  // CV < COMP0 and < COMP1
-#define ADC_DCCTL1_CIC_MID      0x00000004  // COMP0 >= CV < COMP1
-#define ADC_DCCTL1_CIC_HIGH     0x0000000C  // CV <= COMP0 and <= COMP1
-#define ADC_DCCTL1_CIM_M        0x00000003  // Comparison Interrupt Mode.
+#define ADC_DCCTL1_CTM_HALWAYS  0x00000200  // Hysteresis Always
+#define ADC_DCCTL1_CTM_HONCE    0x00000300  // Hysteresis Once
+#define ADC_DCCTL1_CIE          0x00000010  // Comparison Interrupt Enable
+#define ADC_DCCTL1_CIC_M        0x0000000C  // Comparison Interrupt Condition
+#define ADC_DCCTL1_CIC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL1_CIC_MID      0x00000004  // Mid Band
+#define ADC_DCCTL1_CIC_HIGH     0x0000000C  // High Band
+#define ADC_DCCTL1_CIM_M        0x00000003  // Comparison Interrupt Mode
 #define ADC_DCCTL1_CIM_ALWAYS   0x00000000  // Always
 #define ADC_DCCTL1_CIM_ONCE     0x00000001  // Once
-#define ADC_DCCTL1_CIM_HALWAYS  0x00000002  // Hysteresis always
-#define ADC_DCCTL1_CIM_HONCE    0x00000003  // Hysteresis once
+#define ADC_DCCTL1_CIM_HALWAYS  0x00000002  // Hysteresis Always
+#define ADC_DCCTL1_CIM_HONCE    0x00000003  // Hysteresis Once
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the ADC_O_DCCTL2 register.
 //
 //*****************************************************************************
-#define ADC_DCCTL2_CTE          0x00001000  // Comparison Trigger Enable.
-#define ADC_DCCTL2_CTC_M        0x00000C00  // Comparison Trigger Condition.
-#define ADC_DCCTL2_CTC_LOW      0x00000000  // CV < COMP0 and < COMP1
-#define ADC_DCCTL2_CTC_MID      0x00000400  // COMP0 >= CV < COMP1
-#define ADC_DCCTL2_CTC_HIGH     0x00000C00  // CV <= COMP0 and <= COMP1
-#define ADC_DCCTL2_CTM_M        0x00000300  // Comparison Trigger Mode.
+#define ADC_DCCTL2_CTE          0x00001000  // Comparison Trigger Enable
+#define ADC_DCCTL2_CTC_M        0x00000C00  // Comparison Trigger Condition
+#define ADC_DCCTL2_CTC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL2_CTC_MID      0x00000400  // Mid Band
+#define ADC_DCCTL2_CTC_HIGH     0x00000C00  // High Band
+#define ADC_DCCTL2_CTM_M        0x00000300  // Comparison Trigger Mode
 #define ADC_DCCTL2_CTM_ALWAYS   0x00000000  // Always
 #define ADC_DCCTL2_CTM_ONCE     0x00000100  // Once
-#define ADC_DCCTL2_CTM_HALWAYS  0x00000200  // Hysteresis always
-#define ADC_DCCTL2_CTM_HONCE    0x00000300  // Hysteresis once
-#define ADC_DCCTL2_CIE          0x00000010  // Comparison Interrupt Enable.
-#define ADC_DCCTL2_CIC_M        0x0000000C  // Comparison Interrupt Condition.
-#define ADC_DCCTL2_CIC_LOW      0x00000000  // CV < COMP0 and < COMP1
-#define ADC_DCCTL2_CIC_MID      0x00000004  // COMP0 >= CV < COMP1
-#define ADC_DCCTL2_CIC_HIGH     0x0000000C  // CV <= COMP0 and <= COMP1
-#define ADC_DCCTL2_CIM_M        0x00000003  // Comparison Interrupt Mode.
+#define ADC_DCCTL2_CTM_HALWAYS  0x00000200  // Hysteresis Always
+#define ADC_DCCTL2_CTM_HONCE    0x00000300  // Hysteresis Once
+#define ADC_DCCTL2_CIE          0x00000010  // Comparison Interrupt Enable
+#define ADC_DCCTL2_CIC_M        0x0000000C  // Comparison Interrupt Condition
+#define ADC_DCCTL2_CIC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL2_CIC_MID      0x00000004  // Mid Band
+#define ADC_DCCTL2_CIC_HIGH     0x0000000C  // High Band
+#define ADC_DCCTL2_CIM_M        0x00000003  // Comparison Interrupt Mode
 #define ADC_DCCTL2_CIM_ALWAYS   0x00000000  // Always
 #define ADC_DCCTL2_CIM_ONCE     0x00000001  // Once
-#define ADC_DCCTL2_CIM_HALWAYS  0x00000002  // Hysteresis always
-#define ADC_DCCTL2_CIM_HONCE    0x00000003  // Hysteresis once
+#define ADC_DCCTL2_CIM_HALWAYS  0x00000002  // Hysteresis Always
+#define ADC_DCCTL2_CIM_HONCE    0x00000003  // Hysteresis Once
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the ADC_O_DCCTL3 register.
 //
 //*****************************************************************************
-#define ADC_DCCTL3_CTE          0x00001000  // Comparison Trigger Enable.
-#define ADC_DCCTL3_CTC_M        0x00000C00  // Comparison Trigger Condition.
-#define ADC_DCCTL3_CTC_LOW      0x00000000  // CV < COMP0 and < COMP1
-#define ADC_DCCTL3_CTC_MID      0x00000400  // COMP0 >= CV < COMP1
-#define ADC_DCCTL3_CTC_HIGH     0x00000C00  // CV <= COMP0 and <= COMP1
-#define ADC_DCCTL3_CTM_M        0x00000300  // Comparison Trigger Mode.
+#define ADC_DCCTL3_CTE          0x00001000  // Comparison Trigger Enable
+#define ADC_DCCTL3_CTC_M        0x00000C00  // Comparison Trigger Condition
+#define ADC_DCCTL3_CTC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL3_CTC_MID      0x00000400  // Mid Band
+#define ADC_DCCTL3_CTC_HIGH     0x00000C00  // High Band
+#define ADC_DCCTL3_CTM_M        0x00000300  // Comparison Trigger Mode
 #define ADC_DCCTL3_CTM_ALWAYS   0x00000000  // Always
 #define ADC_DCCTL3_CTM_ONCE     0x00000100  // Once
-#define ADC_DCCTL3_CTM_HALWAYS  0x00000200  // Hysteresis always
-#define ADC_DCCTL3_CTM_HONCE    0x00000300  // Hysteresis once
-#define ADC_DCCTL3_CIE          0x00000010  // Comparison Interrupt Enable.
-#define ADC_DCCTL3_CIC_M        0x0000000C  // Comparison Interrupt Condition.
-#define ADC_DCCTL3_CIC_LOW      0x00000000  // CV < COMP0 and < COMP1
-#define ADC_DCCTL3_CIC_MID      0x00000004  // COMP0 >= CV < COMP1
-#define ADC_DCCTL3_CIC_HIGH     0x0000000C  // CV <= COMP0 and <= COMP1
-#define ADC_DCCTL3_CIM_M        0x00000003  // Comparison Interrupt Mode.
+#define ADC_DCCTL3_CTM_HALWAYS  0x00000200  // Hysteresis Always
+#define ADC_DCCTL3_CTM_HONCE    0x00000300  // Hysteresis Once
+#define ADC_DCCTL3_CIE          0x00000010  // Comparison Interrupt Enable
+#define ADC_DCCTL3_CIC_M        0x0000000C  // Comparison Interrupt Condition
+#define ADC_DCCTL3_CIC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL3_CIC_MID      0x00000004  // Mid Band
+#define ADC_DCCTL3_CIC_HIGH     0x0000000C  // High Band
+#define ADC_DCCTL3_CIM_M        0x00000003  // Comparison Interrupt Mode
 #define ADC_DCCTL3_CIM_ALWAYS   0x00000000  // Always
 #define ADC_DCCTL3_CIM_ONCE     0x00000001  // Once
-#define ADC_DCCTL3_CIM_HALWAYS  0x00000002  // Hysteresis always
-#define ADC_DCCTL3_CIM_HONCE    0x00000003  // Hysteresis once
+#define ADC_DCCTL3_CIM_HALWAYS  0x00000002  // Hysteresis Always
+#define ADC_DCCTL3_CIM_HONCE    0x00000003  // Hysteresis Once
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the ADC_O_DCCTL4 register.
 //
 //*****************************************************************************
-#define ADC_DCCTL4_CTE          0x00001000  // Comparison Trigger Enable.
-#define ADC_DCCTL4_CTC_M        0x00000C00  // Comparison Trigger Condition.
-#define ADC_DCCTL4_CTC_LOW      0x00000000  // CV < COMP0 and < COMP1
-#define ADC_DCCTL4_CTC_MID      0x00000400  // COMP0 >= CV < COMP1
-#define ADC_DCCTL4_CTC_HIGH     0x00000C00  // CV <= COMP0 and <= COMP1
-#define ADC_DCCTL4_CTM_M        0x00000300  // Comparison Trigger Mode.
+#define ADC_DCCTL4_CTE          0x00001000  // Comparison Trigger Enable
+#define ADC_DCCTL4_CTC_M        0x00000C00  // Comparison Trigger Condition
+#define ADC_DCCTL4_CTC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL4_CTC_MID      0x00000400  // Mid Band
+#define ADC_DCCTL4_CTC_HIGH     0x00000C00  // High Band
+#define ADC_DCCTL4_CTM_M        0x00000300  // Comparison Trigger Mode
 #define ADC_DCCTL4_CTM_ALWAYS   0x00000000  // Always
 #define ADC_DCCTL4_CTM_ONCE     0x00000100  // Once
-#define ADC_DCCTL4_CTM_HALWAYS  0x00000200  // Hysteresis always
-#define ADC_DCCTL4_CTM_HONCE    0x00000300  // Hysteresis once
-#define ADC_DCCTL4_CIE          0x00000010  // Comparison Interrupt Enable.
-#define ADC_DCCTL4_CIC_M        0x0000000C  // Comparison Interrupt Condition.
-#define ADC_DCCTL4_CIC_LOW      0x00000000  // CV < COMP0 and < COMP1
-#define ADC_DCCTL4_CIC_MID      0x00000004  // COMP0 >= CV < COMP1
-#define ADC_DCCTL4_CIC_HIGH     0x0000000C  // CV <= COMP0 and <= COMP1
-#define ADC_DCCTL4_CIM_M        0x00000003  // Comparison Interrupt Mode.
+#define ADC_DCCTL4_CTM_HALWAYS  0x00000200  // Hysteresis Always
+#define ADC_DCCTL4_CTM_HONCE    0x00000300  // Hysteresis Once
+#define ADC_DCCTL4_CIE          0x00000010  // Comparison Interrupt Enable
+#define ADC_DCCTL4_CIC_M        0x0000000C  // Comparison Interrupt Condition
+#define ADC_DCCTL4_CIC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL4_CIC_MID      0x00000004  // Mid Band
+#define ADC_DCCTL4_CIC_HIGH     0x0000000C  // High Band
+#define ADC_DCCTL4_CIM_M        0x00000003  // Comparison Interrupt Mode
 #define ADC_DCCTL4_CIM_ALWAYS   0x00000000  // Always
 #define ADC_DCCTL4_CIM_ONCE     0x00000001  // Once
-#define ADC_DCCTL4_CIM_HALWAYS  0x00000002  // Hysteresis always
-#define ADC_DCCTL4_CIM_HONCE    0x00000003  // Hysteresis once
+#define ADC_DCCTL4_CIM_HALWAYS  0x00000002  // Hysteresis Always
+#define ADC_DCCTL4_CIM_HONCE    0x00000003  // Hysteresis Once
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the ADC_O_DCCTL5 register.
 //
 //*****************************************************************************
-#define ADC_DCCTL5_CTE          0x00001000  // Comparison Trigger Enable.
-#define ADC_DCCTL5_CTC_M        0x00000C00  // Comparison Trigger Condition.
-#define ADC_DCCTL5_CTC_LOW      0x00000000  // CV < COMP0 and < COMP1
-#define ADC_DCCTL5_CTC_MID      0x00000400  // COMP0 >= CV < COMP1
-#define ADC_DCCTL5_CTC_HIGH     0x00000C00  // CV <= COMP0 and <= COMP1
-#define ADC_DCCTL5_CTM_M        0x00000300  // Comparison Trigger Mode.
+#define ADC_DCCTL5_CTE          0x00001000  // Comparison Trigger Enable
+#define ADC_DCCTL5_CTC_M        0x00000C00  // Comparison Trigger Condition
+#define ADC_DCCTL5_CTC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL5_CTC_MID      0x00000400  // Mid Band
+#define ADC_DCCTL5_CTC_HIGH     0x00000C00  // High Band
+#define ADC_DCCTL5_CTM_M        0x00000300  // Comparison Trigger Mode
 #define ADC_DCCTL5_CTM_ALWAYS   0x00000000  // Always
 #define ADC_DCCTL5_CTM_ONCE     0x00000100  // Once
-#define ADC_DCCTL5_CTM_HALWAYS  0x00000200  // Hysteresis always
-#define ADC_DCCTL5_CTM_HONCE    0x00000300  // Hysteresis once
-#define ADC_DCCTL5_CIE          0x00000010  // Comparison Interrupt Enable.
-#define ADC_DCCTL5_CIC_M        0x0000000C  // Comparison Interrupt Condition.
-#define ADC_DCCTL5_CIC_LOW      0x00000000  // CV < COMP0 and < COMP1
-#define ADC_DCCTL5_CIC_MID      0x00000004  // COMP0 >= CV < COMP1
-#define ADC_DCCTL5_CIC_HIGH     0x0000000C  // CV <= COMP0 and <= COMP1
-#define ADC_DCCTL5_CIM_M        0x00000003  // Comparison Interrupt Mode.
+#define ADC_DCCTL5_CTM_HALWAYS  0x00000200  // Hysteresis Always
+#define ADC_DCCTL5_CTM_HONCE    0x00000300  // Hysteresis Once
+#define ADC_DCCTL5_CIE          0x00000010  // Comparison Interrupt Enable
+#define ADC_DCCTL5_CIC_M        0x0000000C  // Comparison Interrupt Condition
+#define ADC_DCCTL5_CIC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL5_CIC_MID      0x00000004  // Mid Band
+#define ADC_DCCTL5_CIC_HIGH     0x0000000C  // High Band
+#define ADC_DCCTL5_CIM_M        0x00000003  // Comparison Interrupt Mode
 #define ADC_DCCTL5_CIM_ALWAYS   0x00000000  // Always
 #define ADC_DCCTL5_CIM_ONCE     0x00000001  // Once
-#define ADC_DCCTL5_CIM_HALWAYS  0x00000002  // Hysteresis always
-#define ADC_DCCTL5_CIM_HONCE    0x00000003  // Hysteresis once
+#define ADC_DCCTL5_CIM_HALWAYS  0x00000002  // Hysteresis Always
+#define ADC_DCCTL5_CIM_HONCE    0x00000003  // Hysteresis Once
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the ADC_O_DCCTL6 register.
 //
 //*****************************************************************************
-#define ADC_DCCTL6_CTE          0x00001000  // Comparison Trigger Enable.
-#define ADC_DCCTL6_CTC_M        0x00000C00  // Comparison Trigger Condition.
-#define ADC_DCCTL6_CTC_LOW      0x00000000  // CV < COMP0 and < COMP1
-#define ADC_DCCTL6_CTC_MID      0x00000400  // COMP0 >= CV < COMP1
-#define ADC_DCCTL6_CTC_HIGH     0x00000C00  // CV <= COMP0 and <= COMP1
-#define ADC_DCCTL6_CTM_M        0x00000300  // Comparison Trigger Mode.
+#define ADC_DCCTL6_CTE          0x00001000  // Comparison Trigger Enable
+#define ADC_DCCTL6_CTC_M        0x00000C00  // Comparison Trigger Condition
+#define ADC_DCCTL6_CTC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL6_CTC_MID      0x00000400  // Mid Band
+#define ADC_DCCTL6_CTC_HIGH     0x00000C00  // High Band
+#define ADC_DCCTL6_CTM_M        0x00000300  // Comparison Trigger Mode
 #define ADC_DCCTL6_CTM_ALWAYS   0x00000000  // Always
 #define ADC_DCCTL6_CTM_ONCE     0x00000100  // Once
-#define ADC_DCCTL6_CTM_HALWAYS  0x00000200  // Hysteresis always
-#define ADC_DCCTL6_CTM_HONCE    0x00000300  // Hysteresis once
-#define ADC_DCCTL6_CIE          0x00000010  // Comparison Interrupt Enable.
-#define ADC_DCCTL6_CIC_M        0x0000000C  // Comparison Interrupt Condition.
-#define ADC_DCCTL6_CIC_LOW      0x00000000  // CV < COMP0 and < COMP1
-#define ADC_DCCTL6_CIC_MID      0x00000004  // COMP0 >= CV < COMP1
-#define ADC_DCCTL6_CIC_HIGH     0x0000000C  // CV <= COMP0 and <= COMP1
-#define ADC_DCCTL6_CIM_M        0x00000003  // Comparison Interrupt Mode.
+#define ADC_DCCTL6_CTM_HALWAYS  0x00000200  // Hysteresis Always
+#define ADC_DCCTL6_CTM_HONCE    0x00000300  // Hysteresis Once
+#define ADC_DCCTL6_CIE          0x00000010  // Comparison Interrupt Enable
+#define ADC_DCCTL6_CIC_M        0x0000000C  // Comparison Interrupt Condition
+#define ADC_DCCTL6_CIC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL6_CIC_MID      0x00000004  // Mid Band
+#define ADC_DCCTL6_CIC_HIGH     0x0000000C  // High Band
+#define ADC_DCCTL6_CIM_M        0x00000003  // Comparison Interrupt Mode
 #define ADC_DCCTL6_CIM_ALWAYS   0x00000000  // Always
 #define ADC_DCCTL6_CIM_ONCE     0x00000001  // Once
-#define ADC_DCCTL6_CIM_HALWAYS  0x00000002  // Hysteresis always
-#define ADC_DCCTL6_CIM_HONCE    0x00000003  // Hysteresis once
+#define ADC_DCCTL6_CIM_HALWAYS  0x00000002  // Hysteresis Always
+#define ADC_DCCTL6_CIM_HONCE    0x00000003  // Hysteresis Once
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the ADC_O_DCCTL7 register.
 //
 //*****************************************************************************
-#define ADC_DCCTL7_CTE          0x00001000  // Comparison Trigger Enable.
-#define ADC_DCCTL7_CTC_M        0x00000C00  // Comparison Trigger Condition.
-#define ADC_DCCTL7_CTC_LOW      0x00000000  // CV < COMP0 and < COMP1
-#define ADC_DCCTL7_CTC_MID      0x00000400  // COMP0 >= CV < COMP1
-#define ADC_DCCTL7_CTC_HIGH     0x00000C00  // CV <= COMP0 and <= COMP1
-#define ADC_DCCTL7_CTM_M        0x00000300  // Comparison Trigger Mode.
+#define ADC_DCCTL7_CTE          0x00001000  // Comparison Trigger Enable
+#define ADC_DCCTL7_CTC_M        0x00000C00  // Comparison Trigger Condition
+#define ADC_DCCTL7_CTC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL7_CTC_MID      0x00000400  // Mid Band
+#define ADC_DCCTL7_CTC_HIGH     0x00000C00  // High Band
+#define ADC_DCCTL7_CTM_M        0x00000300  // Comparison Trigger Mode
 #define ADC_DCCTL7_CTM_ALWAYS   0x00000000  // Always
 #define ADC_DCCTL7_CTM_ONCE     0x00000100  // Once
-#define ADC_DCCTL7_CTM_HALWAYS  0x00000200  // Hysteresis always
-#define ADC_DCCTL7_CTM_HONCE    0x00000300  // Hysteresis once
-#define ADC_DCCTL7_CIE          0x00000010  // Comparison Interrupt Enable.
-#define ADC_DCCTL7_CIC_M        0x0000000C  // Comparison Interrupt Condition.
-#define ADC_DCCTL7_CIC_LOW      0x00000000  // CV < COMP0 and < COMP1
-#define ADC_DCCTL7_CIC_MID      0x00000004  // COMP0 >= CV < COMP1
-#define ADC_DCCTL7_CIC_HIGH     0x0000000C  // CV <= COMP0 and <= COMP1
-#define ADC_DCCTL7_CIM_M        0x00000003  // Comparison Interrupt Mode.
+#define ADC_DCCTL7_CTM_HALWAYS  0x00000200  // Hysteresis Always
+#define ADC_DCCTL7_CTM_HONCE    0x00000300  // Hysteresis Once
+#define ADC_DCCTL7_CIE          0x00000010  // Comparison Interrupt Enable
+#define ADC_DCCTL7_CIC_M        0x0000000C  // Comparison Interrupt Condition
+#define ADC_DCCTL7_CIC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL7_CIC_MID      0x00000004  // Mid Band
+#define ADC_DCCTL7_CIC_HIGH     0x0000000C  // High Band
+#define ADC_DCCTL7_CIM_M        0x00000003  // Comparison Interrupt Mode
 #define ADC_DCCTL7_CIM_ALWAYS   0x00000000  // Always
 #define ADC_DCCTL7_CIM_ONCE     0x00000001  // Once
-#define ADC_DCCTL7_CIM_HALWAYS  0x00000002  // Hysteresis always
-#define ADC_DCCTL7_CIM_HONCE    0x00000003  // Hysteresis once
+#define ADC_DCCTL7_CIM_HALWAYS  0x00000002  // Hysteresis Always
+#define ADC_DCCTL7_CIM_HONCE    0x00000003  // Hysteresis Once
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the ADC_O_DCCMP0 register.
 //
 //*****************************************************************************
-#define ADC_DCCMP0_COMP1_M      0x03FF0000  // Compare 1.
-#define ADC_DCCMP0_COMP0_M      0x000003FF  // Compare 0.
+#define ADC_DCCMP0_COMP1_M      0x0FFF0000  // Compare 1
+#define ADC_DCCMP0_COMP0_M      0x00000FFF  // Compare 0
 #define ADC_DCCMP0_COMP1_S      16
 #define ADC_DCCMP0_COMP0_S      0
 
@@ -925,8 +965,8 @@
 // The following are defines for the bit fields in the ADC_O_DCCMP1 register.
 //
 //*****************************************************************************
-#define ADC_DCCMP1_COMP1_M      0x03FF0000  // Compare 1.
-#define ADC_DCCMP1_COMP0_M      0x000003FF  // Compare 0.
+#define ADC_DCCMP1_COMP1_M      0x0FFF0000  // Compare 1
+#define ADC_DCCMP1_COMP0_M      0x00000FFF  // Compare 0
 #define ADC_DCCMP1_COMP1_S      16
 #define ADC_DCCMP1_COMP0_S      0
 
@@ -935,8 +975,8 @@
 // The following are defines for the bit fields in the ADC_O_DCCMP2 register.
 //
 //*****************************************************************************
-#define ADC_DCCMP2_COMP1_M      0x03FF0000  // Compare 1.
-#define ADC_DCCMP2_COMP0_M      0x000003FF  // Compare 0.
+#define ADC_DCCMP2_COMP1_M      0x0FFF0000  // Compare 1
+#define ADC_DCCMP2_COMP0_M      0x00000FFF  // Compare 0
 #define ADC_DCCMP2_COMP1_S      16
 #define ADC_DCCMP2_COMP0_S      0
 
@@ -945,8 +985,8 @@
 // The following are defines for the bit fields in the ADC_O_DCCMP3 register.
 //
 //*****************************************************************************
-#define ADC_DCCMP3_COMP1_M      0x03FF0000  // Compare 1.
-#define ADC_DCCMP3_COMP0_M      0x000003FF  // Compare 0.
+#define ADC_DCCMP3_COMP1_M      0x0FFF0000  // Compare 1
+#define ADC_DCCMP3_COMP0_M      0x00000FFF  // Compare 0
 #define ADC_DCCMP3_COMP1_S      16
 #define ADC_DCCMP3_COMP0_S      0
 
@@ -955,8 +995,8 @@
 // The following are defines for the bit fields in the ADC_O_DCCMP4 register.
 //
 //*****************************************************************************
-#define ADC_DCCMP4_COMP1_M      0x03FF0000  // Compare 1.
-#define ADC_DCCMP4_COMP0_M      0x000003FF  // Compare 0.
+#define ADC_DCCMP4_COMP1_M      0x0FFF0000  // Compare 1
+#define ADC_DCCMP4_COMP0_M      0x00000FFF  // Compare 0
 #define ADC_DCCMP4_COMP1_S      16
 #define ADC_DCCMP4_COMP0_S      0
 
@@ -965,8 +1005,8 @@
 // The following are defines for the bit fields in the ADC_O_DCCMP5 register.
 //
 //*****************************************************************************
-#define ADC_DCCMP5_COMP1_M      0x03FF0000  // Compare 1.
-#define ADC_DCCMP5_COMP0_M      0x000003FF  // Compare 0.
+#define ADC_DCCMP5_COMP1_M      0x0FFF0000  // Compare 1
+#define ADC_DCCMP5_COMP0_M      0x00000FFF  // Compare 0
 #define ADC_DCCMP5_COMP1_S      16
 #define ADC_DCCMP5_COMP0_S      0
 
@@ -975,8 +1015,8 @@
 // The following are defines for the bit fields in the ADC_O_DCCMP6 register.
 //
 //*****************************************************************************
-#define ADC_DCCMP6_COMP1_M      0x03FF0000  // Compare 1.
-#define ADC_DCCMP6_COMP0_M      0x000003FF  // Compare 0.
+#define ADC_DCCMP6_COMP1_M      0x0FFF0000  // Compare 1
+#define ADC_DCCMP6_COMP0_M      0x00000FFF  // Compare 0
 #define ADC_DCCMP6_COMP1_S      16
 #define ADC_DCCMP6_COMP0_S      0
 
@@ -985,17 +1025,24 @@
 // The following are defines for the bit fields in the ADC_O_DCCMP7 register.
 //
 //*****************************************************************************
-#define ADC_DCCMP7_COMP1_M      0x03FF0000  // Compare 1.
-#define ADC_DCCMP7_COMP0_M      0x000003FF  // Compare 0.
+#define ADC_DCCMP7_COMP1_M      0x0FFF0000  // Compare 1
+#define ADC_DCCMP7_COMP0_M      0x00000FFF  // Compare 0
 #define ADC_DCCMP7_COMP1_S      16
 #define ADC_DCCMP7_COMP0_S      0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the ADC_O_CTL register.
+// The following are defines for the the interpretation of the data in the
+// SSFIFOx when the ADC TMLB is enabled.
 //
 //*****************************************************************************
-#define ADC_CTL_VREF            0x00000001  // Voltage Reference Select.
+#define ADC_SSFIFO_TMLB_CNT_M   0x000003C0  // Continuous Sample Counter
+#define ADC_SSFIFO_TMLB_CONT    0x00000020  // Continuation Sample Indicator
+#define ADC_SSFIFO_TMLB_DIFF    0x00000010  // Differential Sample Indicator
+#define ADC_SSFIFO_TMLB_TS      0x00000008  // Temp Sensor Sample Indicator
+#define ADC_SSFIFO_TMLB_MUX_M   0x00000007  // Analog Input Indicator
+#define ADC_SSFIFO_TMLB_CNT_S   6           // Sample counter shift
+#define ADC_SSFIFO_TMLB_MUX_S   0           // Input channel number shift
 
 //*****************************************************************************
 //
@@ -1006,19 +1053,7 @@
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the ADC sequence register offsets.
-//
-//*****************************************************************************
-#define ADC_O_SEQ               0x00000040  // Offset to the first sequence
-#define ADC_O_SEQ_STEP          0x00000020  // Increment to the next sequence
-#define ADC_O_X_SSFSTAT         0x0000000C  // FIFO status register
-#define ADC_O_X_SSFIFO          0x00000008  // Result FIFO register
-#define ADC_O_X_SSCTL           0x00000004  // Sample sequence control register
-#define ADC_O_X_SSMUX           0x00000000  // Multiplexer select register
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the ADC_EMUX
+// The following are deprecated defines for the bit fields in the ADC_O_EMUX
 // register.
 //
 //*****************************************************************************
@@ -1033,7 +1068,7 @@
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the bit fields in the ADC_SSPRI
+// The following are deprecated defines for the bit fields in the ADC_O_SSPRI
 // register.
 //
 //*****************************************************************************
@@ -1042,11 +1077,23 @@
 #define ADC_SSPRI_SS1_MASK      0x00000030  // Sequencer 1 priority mask
 #define ADC_SSPRI_SS0_MASK      0x00000003  // Sequencer 0 priority mask
 
+//*****************************************************************************
+//
+// The following are deprecated defines for the ADC sequence register offsets..
+//
+//*****************************************************************************
+#define ADC_O_SEQ               0x00000040  // Offset to the first sequence
+#define ADC_O_SEQ_STEP          0x00000020  // Increment to the next sequence
+#define ADC_O_X_SSFSTAT         0x0000000C  // FIFO status register
+#define ADC_O_X_SSFIFO          0x00000008  // Result FIFO register
+#define ADC_O_X_SSCTL           0x00000004  // Sample sequence control register
+#define ADC_O_X_SSMUX           0x00000000  // Multiplexer select register
+
 //*****************************************************************************
 //
 // The following are deprecated defines for the bit fields in the ADC_SSMUX0,
 // ADC_SSMUX1, ADC_SSMUX2, and ADC_SSMUX3 registers. Not all fields are present
-// in all registers.
+// in all registers..
 //
 //*****************************************************************************
 #define ADC_SSMUX_MUX7_MASK     0x70000000  // 8th mux select mask
@@ -1132,11 +1179,11 @@
 // in the SSFIFOx when the ADC TMLB is enabled.
 //
 //*****************************************************************************
-#define ADC_TMLB_CNT_M          0x000003C0  // Continuous Sample Counter.
-#define ADC_TMLB_CONT           0x00000020  // Continuation Sample Indicator.
-#define ADC_TMLB_DIFF           0x00000010  // Differential Sample Indicator.
-#define ADC_TMLB_TS             0x00000008  // Temp Sensor Sample Indicator.
-#define ADC_TMLB_MUX_M          0x00000007  // Analog Input Indicator.
+#define ADC_TMLB_CNT_M          0x000003C0  // Continuous Sample Counter
+#define ADC_TMLB_CONT           0x00000020  // Continuation Sample Indicator
+#define ADC_TMLB_DIFF           0x00000010  // Differential Sample Indicator
+#define ADC_TMLB_TS             0x00000008  // Temp Sensor Sample Indicator
+#define ADC_TMLB_MUX_M          0x00000007  // Analog Input Indicator
 #define ADC_TMLB_CNT_S          6           // Sample counter shift
 #define ADC_TMLB_MUX_S          0           // Input channel number shift
 
diff --git a/src/platform/lm3s/hw_can.h b/src/platform/lm3s/inc/hw_can.h
similarity index 72%
rename from src/platform/lm3s/hw_can.h
rename to src/platform/lm3s/inc/hw_can.h
index c7998558..2a7b9d81 100755
--- a/src/platform/lm3s/hw_can.h
+++ b/src/platform/lm3s/inc/hw_can.h
@@ -1,27 +1,24 @@
 //*****************************************************************************
 //
-// hw_can.h - Defines and macros used when accessing the can.
+// hw_can.h - Defines and macros used when accessing the CAN controllers.
 //
-// Copyright (c) 2006-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2006-2011 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4781 of the Stellaris Firmware Development Package.
+// This is part of revision 7611 of the Stellaris Firmware Development Package.
 //
 //*****************************************************************************
 
@@ -33,39 +30,40 @@
 // The following are defines for the CAN register offsets.
 //
 //*****************************************************************************
-#define CAN_O_CTL               0x00000000  // Control register
-#define CAN_O_STS               0x00000004  // Status register
-#define CAN_O_ERR               0x00000008  // Error register
-#define CAN_O_BIT               0x0000000C  // Bit Timing register
-#define CAN_O_INT               0x00000010  // Interrupt register
-#define CAN_O_TST               0x00000014  // Test register
-#define CAN_O_BRPE              0x00000018  // Baud Rate Prescaler register
-#define CAN_O_IF1CRQ            0x00000020  // Interface 1 Command Request reg.
-#define CAN_O_IF1CMSK           0x00000024  // Interface 1 Command Mask reg.
-#define CAN_O_IF1MSK1           0x00000028  // Interface 1 Mask 1 register
-#define CAN_O_IF1MSK2           0x0000002C  // Interface 1 Mask 2 register
-#define CAN_O_IF1ARB1           0x00000030  // Interface 1 Arbitration 1 reg.
-#define CAN_O_IF1ARB2           0x00000034  // Interface 1 Arbitration 2 reg.
-#define CAN_O_IF1MCTL           0x00000038  // Interface 1 Message Control reg.
-#define CAN_O_IF1DA1            0x0000003C  // Interface 1 DataA 1 register
-#define CAN_O_IF1DA2            0x00000040  // Interface 1 DataA 2 register
-#define CAN_O_IF1DB1            0x00000044  // Interface 1 DataB 1 register
-#define CAN_O_IF1DB2            0x00000048  // Interface 1 DataB 2 register
-#define CAN_O_IF2CRQ            0x00000080  // Interface 2 Command Request reg.
-#define CAN_O_IF2CMSK           0x00000084  // Interface 2 Command Mask reg.
-#define CAN_O_IF2MSK1           0x00000088  // Interface 2 Mask 1 register
-#define CAN_O_IF2MSK2           0x0000008C  // Interface 2 Mask 2 register
-#define CAN_O_IF2ARB1           0x00000090  // Interface 2 Arbitration 1 reg.
-#define CAN_O_IF2ARB2           0x00000094  // Interface 2 Arbitration 2 reg.
-#define CAN_O_IF2MCTL           0x00000098  // Interface 2 Message Control reg.
-#define CAN_O_IF2DA1            0x0000009C  // Interface 2 DataA 1 register
-#define CAN_O_IF2DA2            0x000000A0  // Interface 2 DataA 2 register
-#define CAN_O_IF2DB1            0x000000A4  // Interface 2 DataB 1 register
-#define CAN_O_IF2DB2            0x000000A8  // Interface 2 DataB 2 register
-#define CAN_O_TXRQ1             0x00000100  // Transmission Request 1 register
-#define CAN_O_TXRQ2             0x00000104  // Transmission Request 2 register
-#define CAN_O_NWDA1             0x00000120  // New Data 1 register
-#define CAN_O_NWDA2             0x00000124  // New Data 2 register
+#define CAN_O_CTL               0x00000000  // CAN Control
+#define CAN_O_STS               0x00000004  // CAN Status
+#define CAN_O_ERR               0x00000008  // CAN Error Counter
+#define CAN_O_BIT               0x0000000C  // CAN Bit Timing
+#define CAN_O_INT               0x00000010  // CAN Interrupt
+#define CAN_O_TST               0x00000014  // CAN Test
+#define CAN_O_BRPE              0x00000018  // CAN Baud Rate Prescaler
+                                            // Extension
+#define CAN_O_IF1CRQ            0x00000020  // CAN IF1 Command Request
+#define CAN_O_IF1CMSK           0x00000024  // CAN IF1 Command Mask
+#define CAN_O_IF1MSK1           0x00000028  // CAN IF1 Mask 1
+#define CAN_O_IF1MSK2           0x0000002C  // CAN IF1 Mask 2
+#define CAN_O_IF1ARB1           0x00000030  // CAN IF1 Arbitration 1
+#define CAN_O_IF1ARB2           0x00000034  // CAN IF1 Arbitration 2
+#define CAN_O_IF1MCTL           0x00000038  // CAN IF1 Message Control
+#define CAN_O_IF1DA1            0x0000003C  // CAN IF1 Data A1
+#define CAN_O_IF1DA2            0x00000040  // CAN IF1 Data A2
+#define CAN_O_IF1DB1            0x00000044  // CAN IF1 Data B1
+#define CAN_O_IF1DB2            0x00000048  // CAN IF1 Data B2
+#define CAN_O_IF2CRQ            0x00000080  // CAN IF2 Command Request
+#define CAN_O_IF2CMSK           0x00000084  // CAN IF2 Command Mask
+#define CAN_O_IF2MSK1           0x00000088  // CAN IF2 Mask 1
+#define CAN_O_IF2MSK2           0x0000008C  // CAN IF2 Mask 2
+#define CAN_O_IF2ARB1           0x00000090  // CAN IF2 Arbitration 1
+#define CAN_O_IF2ARB2           0x00000094  // CAN IF2 Arbitration 2
+#define CAN_O_IF2MCTL           0x00000098  // CAN IF2 Message Control
+#define CAN_O_IF2DA1            0x0000009C  // CAN IF2 Data A1
+#define CAN_O_IF2DA2            0x000000A0  // CAN IF2 Data A2
+#define CAN_O_IF2DB1            0x000000A4  // CAN IF2 Data B1
+#define CAN_O_IF2DB2            0x000000A8  // CAN IF2 Data B2
+#define CAN_O_TXRQ1             0x00000100  // CAN Transmission Request 1
+#define CAN_O_TXRQ2             0x00000104  // CAN Transmission Request 2
+#define CAN_O_NWDA1             0x00000120  // CAN New Data 1
+#define CAN_O_NWDA2             0x00000124  // CAN New Data 2
 #define CAN_O_MSG1INT           0x00000140  // CAN Message 1 Interrupt Pending
 #define CAN_O_MSG2INT           0x00000144  // CAN Message 2 Interrupt Pending
 #define CAN_O_MSG1VAL           0x00000160  // CAN Message 1 Valid
@@ -73,58 +71,58 @@
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the CAN_CTL register.
+// The following are defines for the bit fields in the CAN_O_CTL register.
 //
 //*****************************************************************************
-#define CAN_CTL_TEST            0x00000080  // Test mode enable
-#define CAN_CTL_CCE             0x00000040  // Configuration change enable
-#define CAN_CTL_DAR             0x00000020  // Disable automatic retransmission
-#define CAN_CTL_EIE             0x00000008  // Error interrupt enable
-#define CAN_CTL_SIE             0x00000004  // Status change interrupt enable
-#define CAN_CTL_IE              0x00000002  // Module interrupt enable
+#define CAN_CTL_TEST            0x00000080  // Test Mode Enable
+#define CAN_CTL_CCE             0x00000040  // Configuration Change Enable
+#define CAN_CTL_DAR             0x00000020  // Disable Automatic-Retransmission
+#define CAN_CTL_EIE             0x00000008  // Error Interrupt Enable
+#define CAN_CTL_SIE             0x00000004  // Status Interrupt Enable
+#define CAN_CTL_IE              0x00000002  // CAN Interrupt Enable
 #define CAN_CTL_INIT            0x00000001  // Initialization
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the CAN_STS register.
+// The following are defines for the bit fields in the CAN_O_STS register.
 //
 //*****************************************************************************
-#define CAN_STS_BOFF            0x00000080  // Bus Off status
-#define CAN_STS_EWARN           0x00000040  // Error Warning status
-#define CAN_STS_EPASS           0x00000020  // Error Passive status
-#define CAN_STS_RXOK            0x00000010  // Received Message Successful
-#define CAN_STS_TXOK            0x00000008  // Transmitted Message Successful
+#define CAN_STS_BOFF            0x00000080  // Bus-Off Status
+#define CAN_STS_EWARN           0x00000040  // Warning Status
+#define CAN_STS_EPASS           0x00000020  // Error Passive
+#define CAN_STS_RXOK            0x00000010  // Received a Message Successfully
+#define CAN_STS_TXOK            0x00000008  // Transmitted a Message
+                                            // Successfully
 #define CAN_STS_LEC_M           0x00000007  // Last Error Code
-#define CAN_STS_LEC_NONE        0x00000000  // No error
-#define CAN_STS_LEC_STUFF       0x00000001  // Stuff error
-#define CAN_STS_LEC_FORM        0x00000002  // Form(at) error
-#define CAN_STS_LEC_ACK         0x00000003  // Ack error
-#define CAN_STS_LEC_BIT1        0x00000004  // Bit 1 error
-#define CAN_STS_LEC_BIT0        0x00000005  // Bit 0 error
-#define CAN_STS_LEC_CRC         0x00000006  // CRC error
-#define CAN_STS_LEC_NOEVENT     0x00000007  // Unused
+#define CAN_STS_LEC_NONE        0x00000000  // No Error
+#define CAN_STS_LEC_STUFF       0x00000001  // Stuff Error
+#define CAN_STS_LEC_FORM        0x00000002  // Format Error
+#define CAN_STS_LEC_ACK         0x00000003  // ACK Error
+#define CAN_STS_LEC_BIT1        0x00000004  // Bit 1 Error
+#define CAN_STS_LEC_BIT0        0x00000005  // Bit 0 Error
+#define CAN_STS_LEC_CRC         0x00000006  // CRC Error
+#define CAN_STS_LEC_NOEVENT     0x00000007  // No Event
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the CAN_ERR register.
+// The following are defines for the bit fields in the CAN_O_ERR register.
 //
 //*****************************************************************************
-#define CAN_ERR_RP              0x00008000  // Receive error passive status
-#define CAN_ERR_REC_M           0x00007F00  // Receive Error Counter.
-#define CAN_ERR_TEC_M           0x000000FF  // Transmit Error Counter.
-#define CAN_ERR_REC_S           8           // Receive error counter bit pos
-#define CAN_ERR_TEC_S           0           // Transmit error counter bit pos
+#define CAN_ERR_RP              0x00008000  // Received Error Passive
+#define CAN_ERR_REC_M           0x00007F00  // Receive Error Counter
+#define CAN_ERR_TEC_M           0x000000FF  // Transmit Error Counter
+#define CAN_ERR_REC_S           8
+#define CAN_ERR_TEC_S           0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the CAN_BIT register.
+// The following are defines for the bit fields in the CAN_O_BIT register.
 //
 //*****************************************************************************
-#define CAN_BIT_TSEG2_M         0x00007000  // Time Segment after Sample Point.
-#define CAN_BIT_TSEG1_M         0x00000F00  // Time Segment Before Sample
-                                            // Point.
-#define CAN_BIT_SJW_M           0x000000C0  // (Re)Synchronization Jump Width.
-#define CAN_BIT_BRP_M           0x0000003F  // Baud Rate Prescalar.
+#define CAN_BIT_TSEG2_M         0x00007000  // Time Segment after Sample Point
+#define CAN_BIT_TSEG1_M         0x00000F00  // Time Segment Before Sample Point
+#define CAN_BIT_SJW_M           0x000000C0  // (Re)Synchronization Jump Width
+#define CAN_BIT_BRP_M           0x0000003F  // Baud Rate Prescaler
 #define CAN_BIT_TSEG2_S         12
 #define CAN_BIT_TSEG1_S         8
 #define CAN_BIT_SJW_S           6
@@ -132,100 +130,69 @@
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the CAN_INT register.
+// The following are defines for the bit fields in the CAN_O_INT register.
 //
 //*****************************************************************************
-#define CAN_INT_INTID_M         0x0000FFFF  // Interrupt Identifier.
-#define CAN_INT_INTID_NONE      0x00000000  // No Interrupt Pending
+#define CAN_INT_INTID_M         0x0000FFFF  // Interrupt Identifier
+#define CAN_INT_INTID_NONE      0x00000000  // No interrupt pending
 #define CAN_INT_INTID_STATUS    0x00008000  // Status Interrupt
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the CAN_TST register.
+// The following are defines for the bit fields in the CAN_O_TST register.
 //
 //*****************************************************************************
-#define CAN_TST_RX              0x00000080  // CAN_RX pin status
-#define CAN_TST_TX_M            0x00000060  // Overide control of CAN_TX pin
-#define CAN_TST_TX_CANCTL       0x00000000  // CAN core controls CAN_TX
-#define CAN_TST_TX_SAMPLE       0x00000020  // Sample Point on CAN_TX
-#define CAN_TST_TX_DOMINANT     0x00000040  // Dominant value on CAN_TX
-#define CAN_TST_TX_RECESSIVE    0x00000060  // Recessive value on CAN_TX
-#define CAN_TST_LBACK           0x00000010  // Loop back mode
-#define CAN_TST_SILENT          0x00000008  // Silent mode
-#define CAN_TST_BASIC           0x00000004  // Basic mode
+#define CAN_TST_RX              0x00000080  // Receive Observation
+#define CAN_TST_TX_M            0x00000060  // Transmit Control
+#define CAN_TST_TX_CANCTL       0x00000000  // CAN Module Control
+#define CAN_TST_TX_SAMPLE       0x00000020  // Sample Point
+#define CAN_TST_TX_DOMINANT     0x00000040  // Driven Low
+#define CAN_TST_TX_RECESSIVE    0x00000060  // Driven High
+#define CAN_TST_LBACK           0x00000010  // Loopback Mode
+#define CAN_TST_SILENT          0x00000008  // Silent Mode
+#define CAN_TST_BASIC           0x00000004  // Basic Mode
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the CAN_BRPE register.
+// The following are defines for the bit fields in the CAN_O_BRPE register.
 //
 //*****************************************************************************
-#define CAN_BRPE_BRPE_M         0x0000000F  // Baud Rate Prescalar Extension.
+#define CAN_BRPE_BRPE_M         0x0000000F  // Baud Rate Prescaler Extension
 #define CAN_BRPE_BRPE_S         0
 
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_TXRQ1 register.
-//
-//*****************************************************************************
-#define CAN_TXRQ1_TXRQST_M      0x0000FFFF  // Transmission Request Bits.
-#define CAN_TXRQ1_TXRQST_S      0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_TXRQ2 register.
-//
-//*****************************************************************************
-#define CAN_TXRQ2_TXRQST_M      0x0000FFFF  // Transmission Request Bits.
-#define CAN_TXRQ2_TXRQST_S      0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_NWDA1 register.
-//
-//*****************************************************************************
-#define CAN_NWDA1_NEWDAT_M      0x0000FFFF  // New Data Bits.
-#define CAN_NWDA1_NEWDAT_S      0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_NWDA2 register.
-//
-//*****************************************************************************
-#define CAN_NWDA2_NEWDAT_M      0x0000FFFF  // New Data Bits.
-#define CAN_NWDA2_NEWDAT_S      0
-
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the CAN_O_IF1CRQ register.
 //
 //*****************************************************************************
-#define CAN_IF1CRQ_BUSY         0x00008000  // Busy Flag.
-#define CAN_IF1CRQ_MNUM_M       0x0000003F  // Message Number.
+#define CAN_IF1CRQ_BUSY         0x00008000  // Busy Flag
+#define CAN_IF1CRQ_MNUM_M       0x0000003F  // Message Number
 #define CAN_IF1CRQ_MNUM_RSVD    0x00000000  // 0 is not a valid message number;
                                             // it is interpreted as 0x20, or
-                                            // object 32.
+                                            // object 32
+#define CAN_IF1CRQ_MNUM_S       0
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the CAN_O_IF1CMSK register.
 //
 //*****************************************************************************
-#define CAN_IF1CMSK_WRNRD       0x00000080  // Write, Not Read.
-#define CAN_IF1CMSK_MASK        0x00000040  // Access Mask Bits.
-#define CAN_IF1CMSK_ARB         0x00000020  // Access Arbitration Bits.
-#define CAN_IF1CMSK_CONTROL     0x00000010  // Access Control Bits.
-#define CAN_IF1CMSK_CLRINTPND   0x00000008  // Clear Interrupt Pending Bit.
-#define CAN_IF1CMSK_NEWDAT      0x00000004  // Access New Data.
-#define CAN_IF1CMSK_TXRQST      0x00000004  // Access Transmission Request.
-#define CAN_IF1CMSK_DATAA       0x00000002  // Access Data Byte 0 to 3.
-#define CAN_IF1CMSK_DATAB       0x00000001  // Access Data Byte 4 to 7.
+#define CAN_IF1CMSK_WRNRD       0x00000080  // Write, Not Read
+#define CAN_IF1CMSK_MASK        0x00000040  // Access Mask Bits
+#define CAN_IF1CMSK_ARB         0x00000020  // Access Arbitration Bits
+#define CAN_IF1CMSK_CONTROL     0x00000010  // Access Control Bits
+#define CAN_IF1CMSK_CLRINTPND   0x00000008  // Clear Interrupt Pending Bit
+#define CAN_IF1CMSK_NEWDAT      0x00000004  // Access New Data
+#define CAN_IF1CMSK_TXRQST      0x00000004  // Access Transmission Request
+#define CAN_IF1CMSK_DATAA       0x00000002  // Access Data Byte 0 to 3
+#define CAN_IF1CMSK_DATAB       0x00000001  // Access Data Byte 4 to 7
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the CAN_O_IF1MSK1 register.
 //
 //*****************************************************************************
-#define CAN_IF1MSK1_IDMSK_M     0x0000FFFF  // Identifier Mask.
+#define CAN_IF1MSK1_IDMSK_M     0x0000FFFF  // Identifier Mask
 #define CAN_IF1MSK1_IDMSK_S     0
 
 //*****************************************************************************
@@ -233,9 +200,9 @@
 // The following are defines for the bit fields in the CAN_O_IF1MSK2 register.
 //
 //*****************************************************************************
-#define CAN_IF1MSK2_MXTD        0x00008000  // Mask Extended Identifier.
-#define CAN_IF1MSK2_MDIR        0x00004000  // Mask Message Direction.
-#define CAN_IF1MSK2_IDMSK_M     0x00001FFF  // Identifier Mask.
+#define CAN_IF1MSK2_MXTD        0x00008000  // Mask Extended Identifier
+#define CAN_IF1MSK2_MDIR        0x00004000  // Mask Message Direction
+#define CAN_IF1MSK2_IDMSK_M     0x00001FFF  // Identifier Mask
 #define CAN_IF1MSK2_IDMSK_S     0
 
 //*****************************************************************************
@@ -243,7 +210,7 @@
 // The following are defines for the bit fields in the CAN_O_IF1ARB1 register.
 //
 //*****************************************************************************
-#define CAN_IF1ARB1_ID_M        0x0000FFFF  // Message Identifier.
+#define CAN_IF1ARB1_ID_M        0x0000FFFF  // Message Identifier
 #define CAN_IF1ARB1_ID_S        0
 
 //*****************************************************************************
@@ -251,10 +218,10 @@
 // The following are defines for the bit fields in the CAN_O_IF1ARB2 register.
 //
 //*****************************************************************************
-#define CAN_IF1ARB2_MSGVAL      0x00008000  // Message Valid.
-#define CAN_IF1ARB2_XTD         0x00004000  // Extended Identifier.
-#define CAN_IF1ARB2_DIR         0x00002000  // Message Direction.
-#define CAN_IF1ARB2_ID_M        0x00001FFF  // Message Identifier.
+#define CAN_IF1ARB2_MSGVAL      0x00008000  // Message Valid
+#define CAN_IF1ARB2_XTD         0x00004000  // Extended Identifier
+#define CAN_IF1ARB2_DIR         0x00002000  // Message Direction
+#define CAN_IF1ARB2_ID_M        0x00001FFF  // Message Identifier
 #define CAN_IF1ARB2_ID_S        0
 
 //*****************************************************************************
@@ -262,16 +229,16 @@
 // The following are defines for the bit fields in the CAN_O_IF1MCTL register.
 //
 //*****************************************************************************
-#define CAN_IF1MCTL_NEWDAT      0x00008000  // New Data.
-#define CAN_IF1MCTL_MSGLST      0x00004000  // Message Lost.
-#define CAN_IF1MCTL_INTPND      0x00002000  // Interrupt Pending.
-#define CAN_IF1MCTL_UMASK       0x00001000  // Use Acceptance Mask.
-#define CAN_IF1MCTL_TXIE        0x00000800  // Transmit Interrupt Enable.
-#define CAN_IF1MCTL_RXIE        0x00000400  // Receive Interrupt Enable.
-#define CAN_IF1MCTL_RMTEN       0x00000200  // Remote Enable.
-#define CAN_IF1MCTL_TXRQST      0x00000100  // Transmit Request.
-#define CAN_IF1MCTL_EOB         0x00000080  // End of Buffer.
-#define CAN_IF1MCTL_DLC_M       0x0000000F  // Data Length Code.
+#define CAN_IF1MCTL_NEWDAT      0x00008000  // New Data
+#define CAN_IF1MCTL_MSGLST      0x00004000  // Message Lost
+#define CAN_IF1MCTL_INTPND      0x00002000  // Interrupt Pending
+#define CAN_IF1MCTL_UMASK       0x00001000  // Use Acceptance Mask
+#define CAN_IF1MCTL_TXIE        0x00000800  // Transmit Interrupt Enable
+#define CAN_IF1MCTL_RXIE        0x00000400  // Receive Interrupt Enable
+#define CAN_IF1MCTL_RMTEN       0x00000200  // Remote Enable
+#define CAN_IF1MCTL_TXRQST      0x00000100  // Transmit Request
+#define CAN_IF1MCTL_EOB         0x00000080  // End of Buffer
+#define CAN_IF1MCTL_DLC_M       0x0000000F  // Data Length Code
 #define CAN_IF1MCTL_DLC_S       0
 
 //*****************************************************************************
@@ -279,7 +246,7 @@
 // The following are defines for the bit fields in the CAN_O_IF1DA1 register.
 //
 //*****************************************************************************
-#define CAN_IF1DA1_DATA_M       0x0000FFFF  // Data.
+#define CAN_IF1DA1_DATA_M       0x0000FFFF  // Data
 #define CAN_IF1DA1_DATA_S       0
 
 //*****************************************************************************
@@ -287,7 +254,7 @@
 // The following are defines for the bit fields in the CAN_O_IF1DA2 register.
 //
 //*****************************************************************************
-#define CAN_IF1DA2_DATA_M       0x0000FFFF  // Data.
+#define CAN_IF1DA2_DATA_M       0x0000FFFF  // Data
 #define CAN_IF1DA2_DATA_S       0
 
 //*****************************************************************************
@@ -295,7 +262,7 @@
 // The following are defines for the bit fields in the CAN_O_IF1DB1 register.
 //
 //*****************************************************************************
-#define CAN_IF1DB1_DATA_M       0x0000FFFF  // Data.
+#define CAN_IF1DB1_DATA_M       0x0000FFFF  // Data
 #define CAN_IF1DB1_DATA_S       0
 
 //*****************************************************************************
@@ -303,7 +270,7 @@
 // The following are defines for the bit fields in the CAN_O_IF1DB2 register.
 //
 //*****************************************************************************
-#define CAN_IF1DB2_DATA_M       0x0000FFFF  // Data.
+#define CAN_IF1DB2_DATA_M       0x0000FFFF  // Data
 #define CAN_IF1DB2_DATA_S       0
 
 //*****************************************************************************
@@ -311,33 +278,34 @@
 // The following are defines for the bit fields in the CAN_O_IF2CRQ register.
 //
 //*****************************************************************************
-#define CAN_IF2CRQ_BUSY         0x00008000  // Busy Flag.
-#define CAN_IF2CRQ_MNUM_M       0x0000003F  // Message Number.
+#define CAN_IF2CRQ_BUSY         0x00008000  // Busy Flag
+#define CAN_IF2CRQ_MNUM_M       0x0000003F  // Message Number
 #define CAN_IF2CRQ_MNUM_RSVD    0x00000000  // 0 is not a valid message number;
                                             // it is interpreted as 0x20, or
-                                            // object 32.
+                                            // object 32
+#define CAN_IF2CRQ_MNUM_S       0
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the CAN_O_IF2CMSK register.
 //
 //*****************************************************************************
-#define CAN_IF2CMSK_WRNRD       0x00000080  // Write, Not Read.
-#define CAN_IF2CMSK_MASK        0x00000040  // Access Mask Bits.
-#define CAN_IF2CMSK_ARB         0x00000020  // Access Arbitration Bits.
-#define CAN_IF2CMSK_CONTROL     0x00000010  // Access Control Bits.
-#define CAN_IF2CMSK_CLRINTPND   0x00000008  // Clear Interrupt Pending Bit.
-#define CAN_IF2CMSK_NEWDAT      0x00000004  // Access New Data.
-#define CAN_IF2CMSK_TXRQST      0x00000004  // Access Transmission Request.
-#define CAN_IF2CMSK_DATAA       0x00000002  // Access Data Byte 0 to 3.
-#define CAN_IF2CMSK_DATAB       0x00000001  // Access Data Byte 4 to 7.
+#define CAN_IF2CMSK_WRNRD       0x00000080  // Write, Not Read
+#define CAN_IF2CMSK_MASK        0x00000040  // Access Mask Bits
+#define CAN_IF2CMSK_ARB         0x00000020  // Access Arbitration Bits
+#define CAN_IF2CMSK_CONTROL     0x00000010  // Access Control Bits
+#define CAN_IF2CMSK_CLRINTPND   0x00000008  // Clear Interrupt Pending Bit
+#define CAN_IF2CMSK_NEWDAT      0x00000004  // Access New Data
+#define CAN_IF2CMSK_TXRQST      0x00000004  // Access Transmission Request
+#define CAN_IF2CMSK_DATAA       0x00000002  // Access Data Byte 0 to 3
+#define CAN_IF2CMSK_DATAB       0x00000001  // Access Data Byte 4 to 7
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the CAN_O_IF2MSK1 register.
 //
 //*****************************************************************************
-#define CAN_IF2MSK1_IDMSK_M     0x0000FFFF  // Identifier Mask.
+#define CAN_IF2MSK1_IDMSK_M     0x0000FFFF  // Identifier Mask
 #define CAN_IF2MSK1_IDMSK_S     0
 
 //*****************************************************************************
@@ -345,9 +313,9 @@
 // The following are defines for the bit fields in the CAN_O_IF2MSK2 register.
 //
 //*****************************************************************************
-#define CAN_IF2MSK2_MXTD        0x00008000  // Mask Extended Identifier.
-#define CAN_IF2MSK2_MDIR        0x00004000  // Mask Message Direction.
-#define CAN_IF2MSK2_IDMSK_M     0x00001FFF  // Identifier Mask.
+#define CAN_IF2MSK2_MXTD        0x00008000  // Mask Extended Identifier
+#define CAN_IF2MSK2_MDIR        0x00004000  // Mask Message Direction
+#define CAN_IF2MSK2_IDMSK_M     0x00001FFF  // Identifier Mask
 #define CAN_IF2MSK2_IDMSK_S     0
 
 //*****************************************************************************
@@ -355,7 +323,7 @@
 // The following are defines for the bit fields in the CAN_O_IF2ARB1 register.
 //
 //*****************************************************************************
-#define CAN_IF2ARB1_ID_M        0x0000FFFF  // Message Identifier.
+#define CAN_IF2ARB1_ID_M        0x0000FFFF  // Message Identifier
 #define CAN_IF2ARB1_ID_S        0
 
 //*****************************************************************************
@@ -363,10 +331,10 @@
 // The following are defines for the bit fields in the CAN_O_IF2ARB2 register.
 //
 //*****************************************************************************
-#define CAN_IF2ARB2_MSGVAL      0x00008000  // Message Valid.
-#define CAN_IF2ARB2_XTD         0x00004000  // Extended Identifier.
-#define CAN_IF2ARB2_DIR         0x00002000  // Message Direction.
-#define CAN_IF2ARB2_ID_M        0x00001FFF  // Message Identifier.
+#define CAN_IF2ARB2_MSGVAL      0x00008000  // Message Valid
+#define CAN_IF2ARB2_XTD         0x00004000  // Extended Identifier
+#define CAN_IF2ARB2_DIR         0x00002000  // Message Direction
+#define CAN_IF2ARB2_ID_M        0x00001FFF  // Message Identifier
 #define CAN_IF2ARB2_ID_S        0
 
 //*****************************************************************************
@@ -374,16 +342,16 @@
 // The following are defines for the bit fields in the CAN_O_IF2MCTL register.
 //
 //*****************************************************************************
-#define CAN_IF2MCTL_NEWDAT      0x00008000  // New Data.
-#define CAN_IF2MCTL_MSGLST      0x00004000  // Message Lost.
-#define CAN_IF2MCTL_INTPND      0x00002000  // Interrupt Pending.
-#define CAN_IF2MCTL_UMASK       0x00001000  // Use Acceptance Mask.
-#define CAN_IF2MCTL_TXIE        0x00000800  // Transmit Interrupt Enable.
-#define CAN_IF2MCTL_RXIE        0x00000400  // Receive Interrupt Enable.
-#define CAN_IF2MCTL_RMTEN       0x00000200  // Remote Enable.
-#define CAN_IF2MCTL_TXRQST      0x00000100  // Transmit Request.
-#define CAN_IF2MCTL_EOB         0x00000080  // End of Buffer.
-#define CAN_IF2MCTL_DLC_M       0x0000000F  // Data Length Code.
+#define CAN_IF2MCTL_NEWDAT      0x00008000  // New Data
+#define CAN_IF2MCTL_MSGLST      0x00004000  // Message Lost
+#define CAN_IF2MCTL_INTPND      0x00002000  // Interrupt Pending
+#define CAN_IF2MCTL_UMASK       0x00001000  // Use Acceptance Mask
+#define CAN_IF2MCTL_TXIE        0x00000800  // Transmit Interrupt Enable
+#define CAN_IF2MCTL_RXIE        0x00000400  // Receive Interrupt Enable
+#define CAN_IF2MCTL_RMTEN       0x00000200  // Remote Enable
+#define CAN_IF2MCTL_TXRQST      0x00000100  // Transmit Request
+#define CAN_IF2MCTL_EOB         0x00000080  // End of Buffer
+#define CAN_IF2MCTL_DLC_M       0x0000000F  // Data Length Code
 #define CAN_IF2MCTL_DLC_S       0
 
 //*****************************************************************************
@@ -391,7 +359,7 @@
 // The following are defines for the bit fields in the CAN_O_IF2DA1 register.
 //
 //*****************************************************************************
-#define CAN_IF2DA1_DATA_M       0x0000FFFF  // Data.
+#define CAN_IF2DA1_DATA_M       0x0000FFFF  // Data
 #define CAN_IF2DA1_DATA_S       0
 
 //*****************************************************************************
@@ -399,7 +367,7 @@
 // The following are defines for the bit fields in the CAN_O_IF2DA2 register.
 //
 //*****************************************************************************
-#define CAN_IF2DA2_DATA_M       0x0000FFFF  // Data.
+#define CAN_IF2DA2_DATA_M       0x0000FFFF  // Data
 #define CAN_IF2DA2_DATA_S       0
 
 //*****************************************************************************
@@ -407,7 +375,7 @@
 // The following are defines for the bit fields in the CAN_O_IF2DB1 register.
 //
 //*****************************************************************************
-#define CAN_IF2DB1_DATA_M       0x0000FFFF  // Data.
+#define CAN_IF2DB1_DATA_M       0x0000FFFF  // Data
 #define CAN_IF2DB1_DATA_S       0
 
 //*****************************************************************************
@@ -415,15 +383,47 @@
 // The following are defines for the bit fields in the CAN_O_IF2DB2 register.
 //
 //*****************************************************************************
-#define CAN_IF2DB2_DATA_M       0x0000FFFF  // Data.
+#define CAN_IF2DB2_DATA_M       0x0000FFFF  // Data
 #define CAN_IF2DB2_DATA_S       0
 
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_TXRQ1 register.
+//
+//*****************************************************************************
+#define CAN_TXRQ1_TXRQST_M      0x0000FFFF  // Transmission Request Bits
+#define CAN_TXRQ1_TXRQST_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_TXRQ2 register.
+//
+//*****************************************************************************
+#define CAN_TXRQ2_TXRQST_M      0x0000FFFF  // Transmission Request Bits
+#define CAN_TXRQ2_TXRQST_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_NWDA1 register.
+//
+//*****************************************************************************
+#define CAN_NWDA1_NEWDAT_M      0x0000FFFF  // New Data Bits
+#define CAN_NWDA1_NEWDAT_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_NWDA2 register.
+//
+//*****************************************************************************
+#define CAN_NWDA2_NEWDAT_M      0x0000FFFF  // New Data Bits
+#define CAN_NWDA2_NEWDAT_S      0
+
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the CAN_O_MSG1INT register.
 //
 //*****************************************************************************
-#define CAN_MSG1INT_INTPND_M    0x0000FFFF  // Interrupt Pending Bits.
+#define CAN_MSG1INT_INTPND_M    0x0000FFFF  // Interrupt Pending Bits
 #define CAN_MSG1INT_INTPND_S    0
 
 //*****************************************************************************
@@ -431,7 +431,7 @@
 // The following are defines for the bit fields in the CAN_O_MSG2INT register.
 //
 //*****************************************************************************
-#define CAN_MSG2INT_INTPND_M    0x0000FFFF  // Interrupt Pending Bits.
+#define CAN_MSG2INT_INTPND_M    0x0000FFFF  // Interrupt Pending Bits
 #define CAN_MSG2INT_INTPND_S    0
 
 //*****************************************************************************
@@ -439,7 +439,7 @@
 // The following are defines for the bit fields in the CAN_O_MSG1VAL register.
 //
 //*****************************************************************************
-#define CAN_MSG1VAL_MSGVAL_M    0x0000FFFF  // Message Valid Bits.
+#define CAN_MSG1VAL_MSGVAL_M    0x0000FFFF  // Message Valid Bits
 #define CAN_MSG1VAL_MSGVAL_S    0
 
 //*****************************************************************************
@@ -447,7 +447,7 @@
 // The following are defines for the bit fields in the CAN_O_MSG2VAL register.
 //
 //*****************************************************************************
-#define CAN_MSG2VAL_MSGVAL_M    0x0000FFFF  // Message Valid Bits.
+#define CAN_MSG2VAL_MSGVAL_M    0x0000FFFF  // Message Valid Bits
 #define CAN_MSG2VAL_MSGVAL_S    0
 
 //*****************************************************************************
@@ -462,10 +462,128 @@
 // The following are deprecated defines for the CAN register offsets.
 //
 //*****************************************************************************
-#define CAN_O_MSGINT1           0x00000140  // Intr. Pending in Msg Obj 1 reg.
-#define CAN_O_MSGINT2           0x00000144  // Intr. Pending in Msg Obj 2 reg.
-#define CAN_O_MSGVAL1           0x00000160  // Message Valid in Msg Obj 1 reg.
-#define CAN_O_MSGVAL2           0x00000164  // Message Valid in Msg Obj 2 reg.
+#define CAN_O_MSGINT1           0x00000140  // Intr. Pending in Msg Obj 1 reg
+#define CAN_O_MSGINT2           0x00000144  // Intr. Pending in Msg Obj 2 reg
+#define CAN_O_MSGVAL1           0x00000160  // Message Valid in Msg Obj 1 reg
+#define CAN_O_MSGVAL2           0x00000164  // Message Valid in Msg Obj 2 reg
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_O_STS
+// register.
+//
+//*****************************************************************************
+#define CAN_STS_LEC_MSK         0x00000007  // Last Error Code
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_O_ERR
+// register.
+//
+//*****************************************************************************
+#define CAN_ERR_REC_MASK        0x00007F00  // Receive error counter status
+#define CAN_ERR_TEC_MASK        0x000000FF  // Transmit error counter status
+#define CAN_ERR_REC_SHIFT       8           // Receive error counter bit pos
+#define CAN_ERR_TEC_SHIFT       0           // Transmit error counter bit pos
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_O_BIT
+// register.
+//
+//*****************************************************************************
+#define CAN_BIT_TSEG2           0x00007000  // Time segment after sample point
+#define CAN_BIT_TSEG1           0x00000F00  // Time segment before sample point
+#define CAN_BIT_SJW             0x000000C0  // (Re)Synchronization jump width
+#define CAN_BIT_BRP             0x0000003F  // Baud rate prescaler
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_O_INT
+// register.
+//
+//*****************************************************************************
+#define CAN_INT_INTID_MSK       0x0000FFFF  // Interrupt Identifier
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_O_TST
+// register.
+//
+//*****************************************************************************
+#define CAN_TST_TX_MSK          0x00000060  // Overide control of CAN_TX pin
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_O_BRPE
+// register.
+//
+//*****************************************************************************
+#define CAN_BRPE_BRPE           0x0000000F  // Baud rate prescaler extension
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_O_TXRQ1
+// register.
+//
+//*****************************************************************************
+#define CAN_TXRQ1_TXRQST        0x0000FFFF  // Transmission Request Bits
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_O_TXRQ2
+// register.
+//
+//*****************************************************************************
+#define CAN_TXRQ2_TXRQST        0x0000FFFF  // Transmission Request Bits
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_O_NWDA1
+// register.
+//
+//*****************************************************************************
+#define CAN_NWDA1_NEWDATA       0x0000FFFF  // New Data Bits
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_O_NWDA2
+// register.
+//
+//*****************************************************************************
+#define CAN_NWDA2_NEWDATA       0x0000FFFF  // New Data Bits
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_O_MSGINT1
+// register.
+//
+//*****************************************************************************
+#define CAN_MSGINT1_INTPND      0x0000FFFF  // Interrupt Pending Bits
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_O_MSGINT2
+// register.
+//
+//*****************************************************************************
+#define CAN_MSGINT2_INTPND      0x0000FFFF  // Interrupt Pending Bits
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_O_MSGVAL1
+// register.
+//
+//*****************************************************************************
+#define CAN_MSGVAL1_MSGVAL      0x0000FFFF  // Message Valid Bits
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_O_MSGVAL2
+// register.
+//
+//*****************************************************************************
+#define CAN_MSGVAL2_MSGVAL      0x0000FFFF  // Message Valid Bits
 
 //*****************************************************************************
 //
@@ -511,65 +629,11 @@
 #define CAN_RV_IF2ARB1          0x00000000
 #define CAN_RV_IF2DB2           0x00000000
 
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the CAN_STS
-// register.
-//
-//*****************************************************************************
-#define CAN_STS_LEC_MSK         0x00000007  // Last Error Code
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the CAN_ERR
-// register.
-//
-//*****************************************************************************
-#define CAN_ERR_REC_MASK        0x00007F00  // Receive error counter status
-#define CAN_ERR_TEC_MASK        0x000000FF  // Transmit error counter status
-#define CAN_ERR_REC_SHIFT       8           // Receive error counter bit pos
-#define CAN_ERR_TEC_SHIFT       0           // Transmit error counter bit pos
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the CAN_BIT
-// register.
-//
-//*****************************************************************************
-#define CAN_BIT_TSEG2           0x00007000  // Time segment after sample point
-#define CAN_BIT_TSEG1           0x00000F00  // Time segment before sample point
-#define CAN_BIT_SJW             0x000000C0  // (Re)Synchronization jump width
-#define CAN_BIT_BRP             0x0000003F  // Baud rate prescaler
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the CAN_INT
-// register.
-//
-//*****************************************************************************
-#define CAN_INT_INTID_MSK       0x0000FFFF  // Interrupt Identifier
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the CAN_TST
-// register.
-//
-//*****************************************************************************
-#define CAN_TST_TX_MSK          0x00000060  // Overide control of CAN_TX pin
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the CAN_BRPE
-// register.
-//
-//*****************************************************************************
-#define CAN_BRPE_BRPE           0x0000000F  // Baud rate prescaler extension
-
 //*****************************************************************************
 //
 // The following are deprecated defines for the bit fields in the CAN_IF1CRQ
 // and CAN_IF1CRQ registers.
-// Note: All bits may not be available in all registers
+// Note: All bits may not be available in all registers.
 //
 //*****************************************************************************
 #define CAN_IFCRQ_BUSY          0x00008000  // Busy flag status
@@ -579,7 +643,7 @@
 //
 // The following are deprecated defines for the bit fields in the CAN_IF1CMSK
 // and CAN_IF2CMSK registers.
-// Note: All bits may not be available in all registers
+// Note: All bits may not be available in all registers.
 //
 //*****************************************************************************
 #define CAN_IFCMSK_WRNRD        0x00000080  // Write, not Read
@@ -596,7 +660,7 @@
 //
 // The following are deprecated defines for the bit fields in the CAN_IF1MSK1
 // and CAN_IF2MSK1 registers.
-// Note: All bits may not be available in all registers
+// Note: All bits may not be available in all registers.
 //
 //*****************************************************************************
 #define CAN_IFMSK1_MSK          0x0000FFFF  // Identifier Mask
@@ -605,7 +669,7 @@
 //
 // The following are deprecated defines for the bit fields in the CAN_IF1MSK2
 // and CAN_IF2MSK2 registers.
-// Note: All bits may not be available in all registers
+// Note: All bits may not be available in all registers.
 //
 //*****************************************************************************
 #define CAN_IFMSK2_MXTD         0x00008000  // Mask extended identifier
@@ -616,7 +680,7 @@
 //
 // The following are deprecated defines for the bit fields in the CAN_IF1ARB1
 // and CAN_IF2ARB1 registers.
-// Note: All bits may not be available in all registers
+// Note: All bits may not be available in all registers.
 //
 //*****************************************************************************
 #define CAN_IFARB1_ID           0x0000FFFF  // Identifier
@@ -625,7 +689,7 @@
 //
 // The following are deprecated defines for the bit fields in the CAN_IF1ARB2
 // and CAN_IF2ARB2 registers.
-// Note: All bits may not be available in all registers
+// Note: All bits may not be available in all registers.
 //
 //*****************************************************************************
 #define CAN_IFARB2_MSGVAL       0x00008000  // Message valid
@@ -637,7 +701,7 @@
 //
 // The following are deprecated defines for the bit fields in the CAN_IF1MCTL
 // and CAN_IF2MCTL registers.
-// Note: All bits may not be available in all registers
+// Note: All bits may not be available in all registers.
 //
 //*****************************************************************************
 #define CAN_IFMCTL_NEWDAT       0x00008000  // New Data
@@ -655,7 +719,7 @@
 //
 // The following are deprecated defines for the bit fields in the CAN_IF1DA1
 // and CAN_IF2DA1 registers.
-// Note: All bits may not be available in all registers
+// Note: All bits may not be available in all registers.
 //
 //*****************************************************************************
 #define CAN_IFDA1_DATA          0x0000FFFF  // Data - bytes 1 and 0
@@ -664,7 +728,7 @@
 //
 // The following are deprecated defines for the bit fields in the CAN_IF1DA2
 // and CAN_IF2DA2 registers.
-// Note: All bits may not be available in all registers
+// Note: All bits may not be available in all registers.
 //
 //*****************************************************************************
 #define CAN_IFDA2_DATA          0x0000FFFF  // Data - bytes 3 and 2
@@ -673,7 +737,7 @@
 //
 // The following are deprecated defines for the bit fields in the CAN_IF1DB1
 // and CAN_IF2DB1 registers.
-// Note: All bits may not be available in all registers
+// Note: All bits may not be available in all registers.
 //
 //*****************************************************************************
 #define CAN_IFDB1_DATA          0x0000FFFF  // Data - bytes 5 and 4
@@ -682,75 +746,11 @@
 //
 // The following are deprecated defines for the bit fields in the CAN_IF1DB2
 // and CAN_IF2DB2 registers.
-// Note: All bits may not be available in all registers
+// Note: All bits may not be available in all registers.
 //
 //*****************************************************************************
 #define CAN_IFDB2_DATA          0x0000FFFF  // Data - bytes 7 and 6
 
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the CAN_TXRQ1
-// register.
-//
-//*****************************************************************************
-#define CAN_TXRQ1_TXRQST        0x0000FFFF  // Transmission Request Bits
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the CAN_TXRQ2
-// register.
-//
-//*****************************************************************************
-#define CAN_TXRQ2_TXRQST        0x0000FFFF  // Transmission Request Bits
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the CAN_NWDA1
-// register.
-//
-//*****************************************************************************
-#define CAN_NWDA1_NEWDATA       0x0000FFFF  // New Data Bits
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the CAN_NWDA2
-// register.
-//
-//*****************************************************************************
-#define CAN_NWDA2_NEWDATA       0x0000FFFF  // New Data Bits
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the CAN_MSGINT1
-// register.
-//
-//*****************************************************************************
-#define CAN_MSGINT1_INTPND      0x0000FFFF  // Interrupt Pending Bits
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the CAN_MSGINT2
-// register.
-//
-//*****************************************************************************
-#define CAN_MSGINT2_INTPND      0x0000FFFF  // Interrupt Pending Bits
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the CAN_MSGVAL1
-// register.
-//
-//*****************************************************************************
-#define CAN_MSGVAL1_MSGVAL      0x0000FFFF  // Message Valid Bits
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the CAN_MSGVAL2
-// register.
-//
-//*****************************************************************************
-#define CAN_MSGVAL2_MSGVAL      0x0000FFFF  // Message Valid Bits
-
 #endif
 
 #endif // __HW_CAN_H__
diff --git a/src/platform/lm3s/hw_comp.h b/src/platform/lm3s/inc/hw_comp.h
similarity index 82%
rename from src/platform/lm3s/hw_comp.h
rename to src/platform/lm3s/inc/hw_comp.h
index 04699877..69d7ecb9 100755
--- a/src/platform/lm3s/hw_comp.h
+++ b/src/platform/lm3s/inc/hw_comp.h
@@ -2,26 +2,23 @@
 //
 // hw_comp.h - Macros used when accessing the comparator hardware.
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2011 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4781 of the Stellaris Firmware Development Package.
+// This is part of revision 7611 of the Stellaris Firmware Development Package.
 //
 //*****************************************************************************
 
@@ -30,7 +27,7 @@
 
 //*****************************************************************************
 //
-// The following are defines for the comparator register offsets.
+// The following are defines for the Comparator register offsets.
 //
 //*****************************************************************************
 #define COMP_O_ACMIS            0x00000000  // Analog Comparator Masked
@@ -41,12 +38,12 @@
                                             // Enable
 #define COMP_O_ACREFCTL         0x00000010  // Analog Comparator Reference
                                             // Voltage Control
-#define COMP_O_ACSTAT0          0x00000020  // Comp0 status register
-#define COMP_O_ACCTL0           0x00000024  // Comp0 control register
-#define COMP_O_ACSTAT1          0x00000040  // Comp1 status register
-#define COMP_O_ACCTL1           0x00000044  // Comp1 control register
-#define COMP_O_ACSTAT2          0x00000060  // Comp2 status register
-#define COMP_O_ACCTL2           0x00000064  // Comp2 control register
+#define COMP_O_ACSTAT0          0x00000020  // Analog Comparator Status 0
+#define COMP_O_ACCTL0           0x00000024  // Analog Comparator Control 0
+#define COMP_O_ACSTAT1          0x00000040  // Analog Comparator Status 1
+#define COMP_O_ACCTL1           0x00000044  // Analog Comparator Control 1
+#define COMP_O_ACSTAT2          0x00000060  // Analog Comparator Status 2
+#define COMP_O_ACCTL2           0x00000064  // Analog Comparator Control 2
 
 //*****************************************************************************
 //
@@ -54,29 +51,29 @@
 //
 //*****************************************************************************
 #define COMP_ACMIS_IN2          0x00000004  // Comparator 2 Masked Interrupt
-                                            // Status.
+                                            // Status
 #define COMP_ACMIS_IN1          0x00000002  // Comparator 1 Masked Interrupt
-                                            // Status.
+                                            // Status
 #define COMP_ACMIS_IN0          0x00000001  // Comparator 0 Masked Interrupt
-                                            // Status.
+                                            // Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the COMP_O_ACRIS register.
 //
 //*****************************************************************************
-#define COMP_ACRIS_IN2          0x00000004  // Comparator 2 Interrupt Status.
-#define COMP_ACRIS_IN1          0x00000002  // Comparator 1 Interrupt Status.
-#define COMP_ACRIS_IN0          0x00000001  // Comparator 0 Interrupt Status.
+#define COMP_ACRIS_IN2          0x00000004  // Comparator 2 Interrupt Status
+#define COMP_ACRIS_IN1          0x00000002  // Comparator 1 Interrupt Status
+#define COMP_ACRIS_IN0          0x00000001  // Comparator 0 Interrupt Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the COMP_O_ACINTEN register.
 //
 //*****************************************************************************
-#define COMP_ACINTEN_IN2        0x00000004  // Comparator 2 Interrupt Enable.
-#define COMP_ACINTEN_IN1        0x00000002  // Comparator 1 Interrupt Enable.
-#define COMP_ACINTEN_IN0        0x00000001  // Comparator 0 Interrupt Enable.
+#define COMP_ACINTEN_IN2        0x00000004  // Comparator 2 Interrupt Enable
+#define COMP_ACINTEN_IN1        0x00000002  // Comparator 1 Interrupt Enable
+#define COMP_ACINTEN_IN0        0x00000001  // Comparator 0 Interrupt Enable
 
 //*****************************************************************************
 //
@@ -84,9 +81,9 @@
 // register.
 //
 //*****************************************************************************
-#define COMP_ACREFCTL_EN        0x00000200  // Resistor Ladder Enable.
-#define COMP_ACREFCTL_RNG       0x00000100  // Resistor Ladder Range.
-#define COMP_ACREFCTL_VREF_M    0x0000000F  // Resistor Ladder Voltage Ref.
+#define COMP_ACREFCTL_EN        0x00000200  // Resistor Ladder Enable
+#define COMP_ACREFCTL_RNG       0x00000100  // Resistor Ladder Range
+#define COMP_ACREFCTL_VREF_M    0x0000000F  // Resistor Ladder Voltage Ref
 #define COMP_ACREFCTL_VREF_S    0
 
 //*****************************************************************************
@@ -94,93 +91,96 @@
 // The following are defines for the bit fields in the COMP_O_ACSTAT0 register.
 //
 //*****************************************************************************
-#define COMP_ACSTAT0_OVAL       0x00000002  // Comparator Output Value.
+#define COMP_ACSTAT0_OVAL       0x00000002  // Comparator Output Value
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the COMP_O_ACCTL0 register.
 //
 //*****************************************************************************
-#define COMP_ACCTL0_TOEN        0x00000800  // Trigger Output Enable.
-#define COMP_ACCTL0_ASRCP_M     0x00000600  // Analog Source Positive.
-#define COMP_ACCTL0_ASRCP_PIN   0x00000000  // Pin value
+#define COMP_ACCTL0_TOEN        0x00000800  // Trigger Output Enable
+#define COMP_ACCTL0_ASRCP_M     0x00000600  // Analog Source Positive
+#define COMP_ACCTL0_ASRCP_PIN   0x00000000  // Pin value of Cn+
 #define COMP_ACCTL0_ASRCP_PIN0  0x00000200  // Pin value of C0+
 #define COMP_ACCTL0_ASRCP_REF   0x00000400  // Internal voltage reference
-#define COMP_ACCTL0_TSLVAL      0x00000080  // Trigger Sense Level Value.
-#define COMP_ACCTL0_TSEN_M      0x00000060  // Trigger Sense.
+                                            // (VIREF)
+#define COMP_ACCTL0_TSLVAL      0x00000080  // Trigger Sense Level Value
+#define COMP_ACCTL0_TSEN_M      0x00000060  // Trigger Sense
 #define COMP_ACCTL0_TSEN_LEVEL  0x00000000  // Level sense, see TSLVAL
 #define COMP_ACCTL0_TSEN_FALL   0x00000020  // Falling edge
 #define COMP_ACCTL0_TSEN_RISE   0x00000040  // Rising edge
 #define COMP_ACCTL0_TSEN_BOTH   0x00000060  // Either edge
-#define COMP_ACCTL0_ISLVAL      0x00000010  // Interrupt Sense Level Value.
-#define COMP_ACCTL0_ISEN_M      0x0000000C  // Interrupt Sense.
+#define COMP_ACCTL0_ISLVAL      0x00000010  // Interrupt Sense Level Value
+#define COMP_ACCTL0_ISEN_M      0x0000000C  // Interrupt Sense
 #define COMP_ACCTL0_ISEN_LEVEL  0x00000000  // Level sense, see ISLVAL
 #define COMP_ACCTL0_ISEN_FALL   0x00000004  // Falling edge
 #define COMP_ACCTL0_ISEN_RISE   0x00000008  // Rising edge
 #define COMP_ACCTL0_ISEN_BOTH   0x0000000C  // Either edge
-#define COMP_ACCTL0_CINV        0x00000002  // Comparator Output Invert.
+#define COMP_ACCTL0_CINV        0x00000002  // Comparator Output Invert
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the COMP_O_ACSTAT1 register.
 //
 //*****************************************************************************
-#define COMP_ACSTAT1_OVAL       0x00000002  // Comparator Output Value.
+#define COMP_ACSTAT1_OVAL       0x00000002  // Comparator Output Value
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the COMP_O_ACCTL1 register.
 //
 //*****************************************************************************
-#define COMP_ACCTL1_TOEN        0x00000800  // Trigger Output Enable.
-#define COMP_ACCTL1_ASRCP_M     0x00000600  // Analog Source Positive.
-#define COMP_ACCTL1_ASRCP_PIN   0x00000000  // Pin value
+#define COMP_ACCTL1_TOEN        0x00000800  // Trigger Output Enable
+#define COMP_ACCTL1_ASRCP_M     0x00000600  // Analog Source Positive
+#define COMP_ACCTL1_ASRCP_PIN   0x00000000  // Pin value of Cn+
 #define COMP_ACCTL1_ASRCP_PIN0  0x00000200  // Pin value of C0+
 #define COMP_ACCTL1_ASRCP_REF   0x00000400  // Internal voltage reference
-#define COMP_ACCTL1_TSLVAL      0x00000080  // Trigger Sense Level Value.
-#define COMP_ACCTL1_TSEN_M      0x00000060  // Trigger Sense.
+                                            // (VIREF)
+#define COMP_ACCTL1_TSLVAL      0x00000080  // Trigger Sense Level Value
+#define COMP_ACCTL1_TSEN_M      0x00000060  // Trigger Sense
 #define COMP_ACCTL1_TSEN_LEVEL  0x00000000  // Level sense, see TSLVAL
 #define COMP_ACCTL1_TSEN_FALL   0x00000020  // Falling edge
 #define COMP_ACCTL1_TSEN_RISE   0x00000040  // Rising edge
 #define COMP_ACCTL1_TSEN_BOTH   0x00000060  // Either edge
-#define COMP_ACCTL1_ISLVAL      0x00000010  // Interrupt Sense Level Value.
-#define COMP_ACCTL1_ISEN_M      0x0000000C  // Interrupt Sense.
+#define COMP_ACCTL1_ISLVAL      0x00000010  // Interrupt Sense Level Value
+#define COMP_ACCTL1_ISEN_M      0x0000000C  // Interrupt Sense
 #define COMP_ACCTL1_ISEN_LEVEL  0x00000000  // Level sense, see ISLVAL
 #define COMP_ACCTL1_ISEN_FALL   0x00000004  // Falling edge
 #define COMP_ACCTL1_ISEN_RISE   0x00000008  // Rising edge
 #define COMP_ACCTL1_ISEN_BOTH   0x0000000C  // Either edge
-#define COMP_ACCTL1_CINV        0x00000002  // Comparator Output Invert.
+#define COMP_ACCTL1_CINV        0x00000002  // Comparator Output Invert
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the COMP_O_ACSTAT2 register.
 //
 //*****************************************************************************
-#define COMP_ACSTAT2_OVAL       0x00000002  // Comparator Output Value.
+#define COMP_ACSTAT2_OVAL       0x00000002  // Comparator Output Value
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the COMP_O_ACCTL2 register.
 //
 //*****************************************************************************
-#define COMP_ACCTL2_TOEN        0x00000800  // Trigger Output Enable.
-#define COMP_ACCTL2_ASRCP_M     0x00000600  // Analog Source Positive.
-#define COMP_ACCTL2_ASRCP_PIN   0x00000000  // Pin value
+#define COMP_ACCTL2_TOEN        0x00000800  // Trigger Output Enable
+#define COMP_ACCTL2_ASRCP_M     0x00000600  // Analog Source Positive
+#define COMP_ACCTL2_ASRCP_PIN   0x00000000  // Pin value of Cn+
 #define COMP_ACCTL2_ASRCP_PIN0  0x00000200  // Pin value of C0+
 #define COMP_ACCTL2_ASRCP_REF   0x00000400  // Internal voltage reference
-#define COMP_ACCTL2_TSLVAL      0x00000080  // Trigger Sense Level Value.
-#define COMP_ACCTL2_TSEN_M      0x00000060  // Trigger Sense.
+                                            // (VIREF)
+#define COMP_ACCTL2_TSLVAL      0x00000080  // Trigger Sense Level Value
+#define COMP_ACCTL2_TSEN_M      0x00000060  // Trigger Sense
 #define COMP_ACCTL2_TSEN_LEVEL  0x00000000  // Level sense, see TSLVAL
 #define COMP_ACCTL2_TSEN_FALL   0x00000020  // Falling edge
 #define COMP_ACCTL2_TSEN_RISE   0x00000040  // Rising edge
 #define COMP_ACCTL2_TSEN_BOTH   0x00000060  // Either edge
-#define COMP_ACCTL2_ISLVAL      0x00000010  // Interrupt Sense Level Value.
-#define COMP_ACCTL2_ISEN_M      0x0000000C  // Interrupt Sense.
+#define COMP_ACCTL2_ISLVAL      0x00000010  // Interrupt Sense Level Value
+#define COMP_ACCTL2_ISEN_M      0x0000000C  // Interrupt Sense
 #define COMP_ACCTL2_ISEN_LEVEL  0x00000000  // Level sense, see ISLVAL
 #define COMP_ACCTL2_ISEN_FALL   0x00000004  // Falling edge
 #define COMP_ACCTL2_ISEN_RISE   0x00000008  // Rising edge
 #define COMP_ACCTL2_ISEN_BOTH   0x0000000C  // Either edge
-#define COMP_ACCTL2_CINV        0x00000002  // Comparator Output Invert.
+#define COMP_ACCTL2_CINV        0x00000002  // Comparator Output Invert
 
 //*****************************************************************************
 //
@@ -191,13 +191,24 @@
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the comparator register offsets.
+// The following are deprecated defines for the Comparator register offsets.
 //
 //*****************************************************************************
 #define COMP_O_MIS              0x00000000  // Interrupt status register
 #define COMP_O_RIS              0x00000004  // Raw interrupt status register
 #define COMP_O_INTEN            0x00000008  // Interrupt enable register
-#define COMP_O_REFCTL           0x00000010  // Reference voltage control reg.
+#define COMP_O_REFCTL           0x00000010  // Reference voltage control reg
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the COMP_O_REFCTL
+// register.
+//
+//*****************************************************************************
+#define COMP_REFCTL_EN          0x00000200  // Reference voltage enable
+#define COMP_REFCTL_RNG         0x00000100  // Reference voltage range
+#define COMP_REFCTL_VREF_MASK   0x0000000F  // Reference voltage select mask
+#define COMP_REFCTL_VREF_SHIFT  0
 
 //*****************************************************************************
 //
@@ -209,17 +220,6 @@
 #define COMP_INT_1              0x00000002  // Comp1 interrupt
 #define COMP_INT_0              0x00000001  // Comp0 interrupt
 
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the COMP_REFCTL
-// register.
-//
-//*****************************************************************************
-#define COMP_REFCTL_EN          0x00000200  // Reference voltage enable
-#define COMP_REFCTL_RNG         0x00000100  // Reference voltage range
-#define COMP_REFCTL_VREF_MASK   0x0000000F  // Reference voltage select mask
-#define COMP_REFCTL_VREF_SHIFT  0
-
 //*****************************************************************************
 //
 // The following are deprecated defines for the bit fields in the COMP_ACSTAT0,
@@ -270,7 +270,7 @@
 #define COMP_RV_MIS             0x00000000  // Interrupt status register
 #define COMP_RV_ACCTL0          0x00000000  // Comp0 control register
 #define COMP_RV_ACSTAT1         0x00000000  // Comp1 status register
-#define COMP_RV_REFCTL          0x00000000  // Reference voltage control reg.
+#define COMP_RV_REFCTL          0x00000000  // Reference voltage control reg
 
 #endif
 
diff --git a/src/platform/lm3s/hw_epi.h b/src/platform/lm3s/inc/hw_epi.h
similarity index 51%
rename from src/platform/lm3s/hw_epi.h
rename to src/platform/lm3s/inc/hw_epi.h
index b3fdce2d..74066a9b 100755
--- a/src/platform/lm3s/hw_epi.h
+++ b/src/platform/lm3s/inc/hw_epi.h
@@ -2,26 +2,23 @@
 //
 // hw_epi.h - Macros for use in accessing the EPI registers.
 //
-// Copyright (c) 2008-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2008-2011 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4781 of the Stellaris Firmware Development Package.
+// This is part of revision 7611 of the Stellaris Firmware Development Package.
 //
 //*****************************************************************************
 
@@ -30,18 +27,19 @@
 
 //*****************************************************************************
 //
-// The following are defines for the External Peripheral Interface (EPI)
+// The following are defines for the External Peripheral Interface register
+// offsets.
 //
 //*****************************************************************************
 #define EPI_O_CFG               0x00000000  // EPI Configuration
 #define EPI_O_BAUD              0x00000004  // EPI Main Baud Rate
-#define EPI_O_GPCFG             0x00000010  // EPI General Purpose
-                                            // Configuration
-#define EPI_O_SDRAMCFG          0x00000010  // EPI SDRAM Mode Configuration
-#define EPI_O_HB8CFG            0x00000010  // EPI Host-Bus 8 Mode
+#define EPI_O_HB16CFG           0x00000010  // EPI Host-Bus 16 Configuration
+#define EPI_O_GPCFG             0x00000010  // EPI General-Purpose
                                             // Configuration
+#define EPI_O_SDRAMCFG          0x00000010  // EPI SDRAM Configuration
+#define EPI_O_HB8CFG            0x00000010  // EPI Host-Bus 8 Configuration
 #define EPI_O_HB8CFG2           0x00000014  // EPI Host-Bus 8 Configuration 2
-#define EPI_O_SDRAMCFG2         0x00000014  // EPI SDRAM Configuration 2
+#define EPI_O_HB16CFG2          0x00000014  // EPI Host-Bus 16 Configuration 2
 #define EPI_O_GPCFG2            0x00000014  // EPI General-Purpose
                                             // Configuration 2
 #define EPI_O_ADDRMAP           0x0000001C  // EPI Address Map
@@ -74,130 +72,223 @@
 // The following are defines for the bit fields in the EPI_O_CFG register.
 //
 //*****************************************************************************
-#define EPI_CFG_BLKEN           0x00000010  // Block Enable.
-#define EPI_CFG_MODE_M          0x0000000F  // Mode Select.
-#define EPI_CFG_MODE_NONE       0x00000000  // None
+#define EPI_CFG_BLKEN           0x00000010  // Block Enable
+#define EPI_CFG_MODE_M          0x0000000F  // Mode Select
+#define EPI_CFG_MODE_NONE       0x00000000  // General Purpose
 #define EPI_CFG_MODE_SDRAM      0x00000001  // SDRAM
 #define EPI_CFG_MODE_HB8        0x00000002  // 8-Bit Host-Bus (HB8)
+#define EPI_CFG_MODE_HB16       0x00000003  // 16-Bit Host-Bus (HB16)
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the EPI_O_BAUD register.
 //
 //*****************************************************************************
-#define EPI_BAUD_COUNT_M        0x0000FFFF  // Baud Rate Counter.
-#define EPI_BAUD_COUNT_S        0
+#define EPI_BAUD_COUNT1_M       0xFFFF0000  // Baud Rate Counter 1
+#define EPI_BAUD_COUNT0_M       0x0000FFFF  // Baud Rate Counter 0
+#define EPI_BAUD_COUNT1_S       16
+#define EPI_BAUD_COUNT0_S       0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the EPI_O_SDRAMCFG register.
+// The following are defines for the bit fields in the EPI_O_HB16CFG register.
 //
 //*****************************************************************************
-#define EPI_SDRAMCFG_FREQ_M     0xC0000000  // Frequency Range.
-#define EPI_SDRAMCFG_FREQ_NONE  0x00000000  // 0
-#define EPI_SDRAMCFG_FREQ_15MHZ 0x40000000  // 15
-#define EPI_SDRAMCFG_FREQ_30MHZ 0x80000000  // 30
-#define EPI_SDRAMCFG_FREQ_50MHZ 0xC0000000  // 50
-#define EPI_SDRAMCFG_RFSH_M     0x07FF0000  // Refresh Counter.
-#define EPI_SDRAMCFG_SLEEP      0x00000200  // Sleep Mode.
-#define EPI_SDRAMCFG_SIZE_M     0x00000003  // Size of SDRAM.
-#define EPI_SDRAMCFG_SIZE_8MB   0x00000000  // 64Mb (8MB)
-#define EPI_SDRAMCFG_SIZE_16MB  0x00000001  // 128Mb (16MB)
-#define EPI_SDRAMCFG_SIZE_32MB  0x00000002  // 256Mb (32MB)
-#define EPI_SDRAMCFG_SIZE_64MB  0x00000003  // 512Mb (64MB)
-#define EPI_SDRAMCFG_RFSH_S     16
+#define EPI_HB16CFG_XFFEN       0x00800000  // External FIFO FULL Enable
+#define EPI_HB16CFG_XFEEN       0x00400000  // External FIFO EMPTY Enable
+#define EPI_HB16CFG_WRHIGH      0x00200000  // WRITE Strobe Polarity
+#define EPI_HB16CFG_RDHIGH      0x00100000  // READ Strobe Polarity
+#define EPI_HB16CFG_MAXWAIT_M   0x0000FF00  // Maximum Wait
+#define EPI_HB16CFG_WRWS_M      0x000000C0  // CS0n Write Wait States
+#define EPI_HB16CFG_WRWS_0      0x00000000  // No wait states
+#define EPI_HB16CFG_WRWS_1      0x00000040  // 1 wait state
+#define EPI_HB16CFG_WRWS_2      0x00000080  // 2 wait states
+#define EPI_HB16CFG_WRWS_3      0x000000C0  // 3 wait states
+#define EPI_HB16CFG_RDWS_M      0x00000030  // CS0n Read Wait States
+#define EPI_HB16CFG_RDWS_0      0x00000000  // No wait states
+#define EPI_HB16CFG_RDWS_1      0x00000010  // 1 wait state
+#define EPI_HB16CFG_RDWS_2      0x00000020  // 2 wait states
+#define EPI_HB16CFG_RDWS_3      0x00000030  // 3 wait states
+#define EPI_HB16CFG_BSEL        0x00000004  // Byte Select Configuration
+#define EPI_HB16CFG_MODE_M      0x00000003  // Host Bus Sub-Mode
+#define EPI_HB16CFG_MODE_ADMUX  0x00000000  // ADMUX - AD[15:0]
+#define EPI_HB16CFG_MODE_ADNMUX 0x00000001  // ADNONMUX - D[15:0]
+#define EPI_HB16CFG_MODE_SRAM   0x00000002  // Continuous Read - D[15:0]
+#define EPI_HB16CFG_MODE_XFIFO  0x00000003  // XFIFO - D[15:0]
+#define EPI_HB16CFG_MAXWAIT_S   8
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the EPI_O_GPCFG register.
 //
 //*****************************************************************************
-#define EPI_GPCFG_CLKPIN        0x80000000  // Clock Pin.
-#define EPI_GPCFG_CLKGATE       0x40000000  // Clock Gated.
-#define EPI_GPCFG_RDYEN         0x10000000  // Ready Enable.
-#define EPI_GPCFG_FRMPIN        0x08000000  // Framing Pin.
-#define EPI_GPCFG_FRM50         0x04000000  // 50/50 Frame.
-#define EPI_GPCFG_FRMCNT_M      0x03C00000  // Frame Count.
-#define EPI_GPCFG_RW            0x00200000  // Read and Write.
-#define EPI_GPCFG_WR2CYC        0x00080000  // 2-Cycle Writes.
-#define EPI_GPCFG_RD2CYC        0x00040000  // 2-Cycle Reads.
-#define EPI_GPCFG_MAXWAIT_M     0x0000FF00  // Maximum Wait.
-#define EPI_GPCFG_ASIZE_M       0x00000030  // Address Bus Size.
+#define EPI_GPCFG_CLKPIN        0x80000000  // Clock Pin
+#define EPI_GPCFG_CLKGATE       0x40000000  // Clock Gated
+#define EPI_GPCFG_RDYEN         0x10000000  // Ready Enable
+#define EPI_GPCFG_FRMPIN        0x08000000  // Framing Pin
+#define EPI_GPCFG_FRM50         0x04000000  // 50/50 Frame
+#define EPI_GPCFG_FRMCNT_M      0x03C00000  // Frame Count
+#define EPI_GPCFG_RW            0x00200000  // Read and Write
+#define EPI_GPCFG_WR2CYC        0x00080000  // 2-Cycle Writes
+#define EPI_GPCFG_RD2CYC        0x00040000  // 2-Cycle Reads
+#define EPI_GPCFG_MAXWAIT_M     0x0000FF00  // Maximum Wait
+#define EPI_GPCFG_ASIZE_M       0x00000030  // Address Bus Size
 #define EPI_GPCFG_ASIZE_NONE    0x00000000  // No address
-#define EPI_GPCFG_ASIZE_4BIT    0x00000010  // 4 Bits Wide (EPI24 to EPI27)
-#define EPI_GPCFG_ASIZE_12BIT   0x00000020  // 12 Bits Wide (EPI16 to EPI27).
-                                            // Cannot be used with 24-bit data
-#define EPI_GPCFG_ASIZE_20BIT   0x00000030  // 20 Bits Wide
-#define EPI_GPCFG_DSIZE_M       0x00000003  // Size of Data Bus.
-#define EPI_GPCFG_DSIZE_4BIT    0x00000000  // 4 Bits Wide (EPI0 to EPI7)
-#define EPI_GPCFG_DSIZE_16BIT   0x00000001  // 16 Bits Wide (EPI0 to EPI15)
-#define EPI_GPCFG_DSIZE_24BIT   0x00000002  // 24 Bits Wide (EPI0 to EPI23)
-#define EPI_GPCFG_DSIZE_32BIT   0x00000003  // 32 Bits Wide. May not be used
-                                            // with clock (EPI0 to EPI31). This
-                                            // value is normally used for
-                                            // acquisition input and actuator
-                                            // control as well as other general
-                                            // purpose uses.
+#define EPI_GPCFG_ASIZE_4BIT    0x00000010  // Up to 4 bits wide
+#define EPI_GPCFG_ASIZE_12BIT   0x00000020  // Up to 12 bits wide. This size
+                                            // cannot be used with 24-bit data
+#define EPI_GPCFG_ASIZE_20BIT   0x00000030  // Up to 20 bits wide. This size
+                                            // cannot be used with data sizes
+                                            // other than 8
+#define EPI_GPCFG_DSIZE_M       0x00000003  // Size of Data Bus
+#define EPI_GPCFG_DSIZE_4BIT    0x00000000  // 8 Bits Wide (EPI0S0 to EPI0S7)
+#define EPI_GPCFG_DSIZE_16BIT   0x00000001  // 16 Bits Wide (EPI0S0 to EPI0S15)
+#define EPI_GPCFG_DSIZE_24BIT   0x00000002  // 24 Bits Wide (EPI0S0 to EPI0S23)
+#define EPI_GPCFG_DSIZE_32BIT   0x00000003  // 32 Bits Wide (EPI0S0 to EPI0S31)
 #define EPI_GPCFG_FRMCNT_S      22
 #define EPI_GPCFG_MAXWAIT_S     8
 
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_SDRAMCFG register.
+//
+//*****************************************************************************
+#define EPI_SDRAMCFG_FREQ_M     0xC0000000  // Frequency Range
+#define EPI_SDRAMCFG_FREQ_NONE  0x00000000  // 0 - 15 MHz
+#define EPI_SDRAMCFG_FREQ_15MHZ 0x40000000  // 15 - 30 MHz
+#define EPI_SDRAMCFG_FREQ_30MHZ 0x80000000  // 30 - 50 MHz
+#define EPI_SDRAMCFG_FREQ_50MHZ 0xC0000000  // 50 - 100 MHz
+#define EPI_SDRAMCFG_RFSH_M     0x07FF0000  // Refresh Counter
+#define EPI_SDRAMCFG_SLEEP      0x00000200  // Sleep Mode
+#define EPI_SDRAMCFG_SIZE_M     0x00000003  // Size of SDRAM
+#define EPI_SDRAMCFG_SIZE_8MB   0x00000000  // 64 megabits (8MB)
+#define EPI_SDRAMCFG_SIZE_16MB  0x00000001  // 128 megabits (16MB)
+#define EPI_SDRAMCFG_SIZE_32MB  0x00000002  // 256 megabits (32MB)
+#define EPI_SDRAMCFG_SIZE_64MB  0x00000003  // 512 megabits (64MB)
+#define EPI_SDRAMCFG_RFSH_S     16
+
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the EPI_O_HB8CFG register.
 //
 //*****************************************************************************
-#define EPI_HB8CFG_XFFEN        0x00800000  // External FIFO FULL Enable.
-#define EPI_HB8CFG_XFEEN        0x00400000  // External FIFO EMPTY Enable.
-#define EPI_HB8CFG_WRHIGH       0x00200000  // WRITE Strobe Polarity.
-#define EPI_HB8CFG_RDHIGH       0x00100000  // READ Strobe Polarity.
-#define EPI_HB8CFG_MAXWAIT_M    0x0000FF00  // Maximum Wait.
-#define EPI_HB8CFG_WRWS_M       0x000000C0  // Write Wait States.
+#define EPI_HB8CFG_XFFEN        0x00800000  // External FIFO FULL Enable
+#define EPI_HB8CFG_XFEEN        0x00400000  // External FIFO EMPTY Enable
+#define EPI_HB8CFG_WRHIGH       0x00200000  // CS0n WRITE Strobe Polarity
+#define EPI_HB8CFG_RDHIGH       0x00100000  // CS0n READ Strobe Polarity
+#define EPI_HB8CFG_MAXWAIT_M    0x0000FF00  // Maximum Wait
+#define EPI_HB8CFG_WRWS_M       0x000000C0  // Write Wait States
 #define EPI_HB8CFG_WRWS_0       0x00000000  // No wait states
 #define EPI_HB8CFG_WRWS_1       0x00000040  // 1 wait state
 #define EPI_HB8CFG_WRWS_2       0x00000080  // 2 wait states
 #define EPI_HB8CFG_WRWS_3       0x000000C0  // 3 wait states
-#define EPI_HB8CFG_RDWS_M       0x00000030  // Read Wait States.
+#define EPI_HB8CFG_RDWS_M       0x00000030  // Read Wait States
 #define EPI_HB8CFG_RDWS_0       0x00000000  // No wait states
 #define EPI_HB8CFG_RDWS_1       0x00000010  // 1 wait state
 #define EPI_HB8CFG_RDWS_2       0x00000020  // 2 wait states
 #define EPI_HB8CFG_RDWS_3       0x00000030  // 3 wait states
-#define EPI_HB8CFG_MODE_M       0x00000003  // Host Bus Sub-Mode.
+#define EPI_HB8CFG_MODE_M       0x00000003  // Host Bus Sub-Mode
 #define EPI_HB8CFG_MODE_MUX     0x00000000  // ADMUX - AD[7:0]
 #define EPI_HB8CFG_MODE_NMUX    0x00000001  // ADNONMUX - D[7:0]
-#define EPI_HB8CFG_MODE_SRAM    0x00000002  // SRAM
-#define EPI_HB8CFG_MODE_FIFO    0x00000003  // FIFO - D[7:0]
+#define EPI_HB8CFG_MODE_SRAM    0x00000002  // Continuous Read - D[7:0]
+#define EPI_HB8CFG_MODE_FIFO    0x00000003  // XFIFO - D[7:0]
 #define EPI_HB8CFG_MAXWAIT_S    8
 
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB8CFG2 register.
+//
+//*****************************************************************************
+#define EPI_HB8CFG2_WORD        0x80000000  // Word Access Mode
+#define EPI_HB8CFG2_CSBAUD      0x04000000  // Chip Select Baud Rate
+#define EPI_HB8CFG2_CSCFG_M     0x03000000  // Chip Select Configuration
+#define EPI_HB8CFG2_CSCFG_ALE   0x00000000  // ALE Configuration
+#define EPI_HB8CFG2_CSCFG_CS    0x01000000  // CSn Configuration
+#define EPI_HB8CFG2_CSCFG_DCS   0x02000000  // Dual CSn Configuration
+#define EPI_HB8CFG2_CSCFG_ADCS  0x03000000  // ALE with Dual CSn Configuration
+#define EPI_HB8CFG2_WRHIGH      0x00200000  // CS1n WRITE Strobe Polarity
+#define EPI_HB8CFG2_RDHIGH      0x00100000  // CS1n READ Strobe Polarity
+#define EPI_HB8CFG2_WRWS_M      0x000000C0  // CS1n Write Wait States
+#define EPI_HB8CFG2_WRWS_0      0x00000000  // No wait states
+#define EPI_HB8CFG2_WRWS_1      0x00000040  // 1 wait state
+#define EPI_HB8CFG2_WRWS_2      0x00000080  // 2 wait states
+#define EPI_HB8CFG2_WRWS_3      0x000000C0  // 3 wait states
+#define EPI_HB8CFG2_RDWS_M      0x00000030  // CS1n Read Wait States
+#define EPI_HB8CFG2_RDWS_0      0x00000000  // No wait states
+#define EPI_HB8CFG2_RDWS_1      0x00000010  // 1 wait state
+#define EPI_HB8CFG2_RDWS_2      0x00000020  // 2 wait states
+#define EPI_HB8CFG2_RDWS_3      0x00000030  // 3 wait states
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB16CFG2 register.
+//
+//*****************************************************************************
+#define EPI_HB16CFG2_WORD       0x80000000  // Word Access Mode
+#define EPI_HB16CFG2_CSBAUD     0x04000000  // Chip Select Baud Rate
+#define EPI_HB16CFG2_CSCFG_M    0x03000000  // Chip Select Configuration
+#define EPI_HB16CFG2_CSCFG_ALE  0x00000000  // ALE Configuration
+#define EPI_HB16CFG2_CSCFG_CS   0x01000000  // CSn Configuration
+#define EPI_HB16CFG2_CSCFG_DCS  0x02000000  // Dual CSn Configuration
+#define EPI_HB16CFG2_CSCFG_ADCS 0x03000000  // ALE with Dual CSn Configuration
+#define EPI_HB16CFG2_WRHIGH     0x00200000  // CS1n WRITE Strobe Polarity
+#define EPI_HB16CFG2_RDHIGH     0x00100000  // CS1n READ Strobe Polarity
+#define EPI_HB16CFG2_WRWS_M     0x000000C0  // CS1n Write Wait States
+#define EPI_HB16CFG2_WRWS_0     0x00000000  // No wait states
+#define EPI_HB16CFG2_WRWS_1     0x00000040  // 1 wait state
+#define EPI_HB16CFG2_WRWS_2     0x00000080  // 2 wait states
+#define EPI_HB16CFG2_WRWS_3     0x000000C0  // 3 wait states
+#define EPI_HB16CFG2_RDWS_M     0x00000030  // CS1n Read Wait States
+#define EPI_HB16CFG2_RDWS_0     0x00000000  // No wait states
+#define EPI_HB16CFG2_RDWS_1     0x00000010  // 1 wait state
+#define EPI_HB16CFG2_RDWS_2     0x00000020  // 2 wait states
+#define EPI_HB16CFG2_RDWS_3     0x00000030  // 3 wait states
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_GPCFG2 register.
+//
+//*****************************************************************************
+#define EPI_GPCFG2_WORD         0x80000000  // Word Access Mode
+
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the EPI_O_ADDRMAP register.
 //
 //*****************************************************************************
-#define EPI_ADDRMAP_EPSZ_M      0x000000C0  // External Peripheral Size.
-#define EPI_ADDRMAP_EPSZ_256B   0x00000000  // 0x100 (256)
-#define EPI_ADDRMAP_EPSZ_64KB   0x00000040  // 0x10000 (64 KB)
-#define EPI_ADDRMAP_EPSZ_16MB   0x00000080  // 0x1000000 (16 MB)
-#define EPI_ADDRMAP_EPSZ_512MB  0x000000C0  // 0x20000000 (512 MB)
-#define EPI_ADDRMAP_EPADR_M     0x00000030  // External Peripheral Address.
+#define EPI_ADDRMAP_EPSZ_M      0x000000C0  // External Peripheral Size
+#define EPI_ADDRMAP_EPSZ_256B   0x00000000  // 256 bytes; lower address range:
+                                            // 0x00 to 0xFF
+#define EPI_ADDRMAP_EPSZ_64KB   0x00000040  // 64 KB; lower address range:
+                                            // 0x0000 to 0xFFFF
+#define EPI_ADDRMAP_EPSZ_16MB   0x00000080  // 16 MB; lower address range:
+                                            // 0x00.0000 to 0xFF.FFFF
+#define EPI_ADDRMAP_EPSZ_256MB  0x000000C0  // 256 MB; lower address range:
+                                            // 0x000.0000 to 0xFFF.FFFF
+#define EPI_ADDRMAP_EPADR_M     0x00000030  // External Peripheral Address
 #define EPI_ADDRMAP_EPADR_NONE  0x00000000  // Not mapped
-#define EPI_ADDRMAP_EPADR_A000  0x00000010  // At 0xA0000000
-#define EPI_ADDRMAP_EPADR_C000  0x00000020  // At 0xC0000000
-#define EPI_ADDRMAP_ERSZ_M      0x0000000C  // External RAM Size.
-#define EPI_ADDRMAP_ERSZ_256B   0x00000000  // 0x100 (256)
-#define EPI_ADDRMAP_ERSZ_64KB   0x00000004  // 0x10000 (64KB)
-#define EPI_ADDRMAP_ERSZ_16MB   0x00000008  // 0x1000000 (16MB)
-#define EPI_ADDRMAP_ERSZ_512MB  0x0000000C  // 0x20000000 (512MB)
-#define EPI_ADDRMAP_ERADR_M     0x00000003  // External RAM Address.
+#define EPI_ADDRMAP_EPADR_A000  0x00000010  // At 0xA000.0000
+#define EPI_ADDRMAP_EPADR_C000  0x00000020  // At 0xC000.0000
+#define EPI_ADDRMAP_ERSZ_M      0x0000000C  // External RAM Size
+#define EPI_ADDRMAP_ERSZ_256B   0x00000000  // 256 bytes; lower address range:
+                                            // 0x00 to 0xFF
+#define EPI_ADDRMAP_ERSZ_64KB   0x00000004  // 64 KB; lower address range:
+                                            // 0x0000 to 0xFFFF
+#define EPI_ADDRMAP_ERSZ_16MB   0x00000008  // 16 MB; lower address range:
+                                            // 0x00.0000 to 0xFF.FFFF
+#define EPI_ADDRMAP_ERSZ_256MB  0x0000000C  // 256 MB; lower address range:
+                                            // 0x000.0000 to 0xFFF.FFFF
+#define EPI_ADDRMAP_ERADR_M     0x00000003  // External RAM Address
 #define EPI_ADDRMAP_ERADR_NONE  0x00000000  // Not mapped
-#define EPI_ADDRMAP_ERADR_6000  0x00000001  // At 0x60000000
-#define EPI_ADDRMAP_ERADR_8000  0x00000002  // At 0x80000000
+#define EPI_ADDRMAP_ERADR_6000  0x00000001  // At 0x6000.0000
+#define EPI_ADDRMAP_ERADR_8000  0x00000002  // At 0x8000.0000
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the EPI_O_RSIZE0 register.
 //
 //*****************************************************************************
-#define EPI_RSIZE0_SIZE_M       0x00000003  // Current Size.
+#define EPI_RSIZE0_SIZE_M       0x00000003  // Current Size
 #define EPI_RSIZE0_SIZE_8BIT    0x00000001  // Byte (8 bits)
 #define EPI_RSIZE0_SIZE_16BIT   0x00000002  // Half-word (16 bits)
 #define EPI_RSIZE0_SIZE_32BIT   0x00000003  // Word (32 bits)
@@ -207,7 +298,7 @@
 // The following are defines for the bit fields in the EPI_O_RADDR0 register.
 //
 //*****************************************************************************
-#define EPI_RADDR0_ADDR_M       0x1FFFFFFF  // Current Address.
+#define EPI_RADDR0_ADDR_M       0x1FFFFFFF  // Current Address
 #define EPI_RADDR0_ADDR_S       0
 
 //*****************************************************************************
@@ -215,7 +306,7 @@
 // The following are defines for the bit fields in the EPI_O_RPSTD0 register.
 //
 //*****************************************************************************
-#define EPI_RPSTD0_POSTCNT_M    0x00001FFF  // Post Count.
+#define EPI_RPSTD0_POSTCNT_M    0x00001FFF  // Post Count
 #define EPI_RPSTD0_POSTCNT_S    0
 
 //*****************************************************************************
@@ -223,7 +314,7 @@
 // The following are defines for the bit fields in the EPI_O_RSIZE1 register.
 //
 //*****************************************************************************
-#define EPI_RSIZE1_SIZE_M       0x00000003  // Current Size.
+#define EPI_RSIZE1_SIZE_M       0x00000003  // Current Size
 #define EPI_RSIZE1_SIZE_8BIT    0x00000001  // Byte (8 bits)
 #define EPI_RSIZE1_SIZE_16BIT   0x00000002  // Half-word (16 bits)
 #define EPI_RSIZE1_SIZE_32BIT   0x00000003  // Word (32 bits)
@@ -233,7 +324,7 @@
 // The following are defines for the bit fields in the EPI_O_RADDR1 register.
 //
 //*****************************************************************************
-#define EPI_RADDR1_ADDR_M       0x1FFFFFFF  // Current Address.
+#define EPI_RADDR1_ADDR_M       0x1FFFFFFF  // Current Address
 #define EPI_RADDR1_ADDR_S       0
 
 //*****************************************************************************
@@ -241,15 +332,28 @@
 // The following are defines for the bit fields in the EPI_O_RPSTD1 register.
 //
 //*****************************************************************************
-#define EPI_RPSTD1_POSTCNT_M    0x00001FFF  // Post Count.
+#define EPI_RPSTD1_POSTCNT_M    0x00001FFF  // Post Count
 #define EPI_RPSTD1_POSTCNT_S    0
 
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_STAT register.
+//
+//*****************************************************************************
+#define EPI_STAT_CELOW          0x00000200  // Clock Enable Low
+#define EPI_STAT_XFFULL         0x00000100  // External FIFO Full
+#define EPI_STAT_XFEMPTY        0x00000080  // External FIFO Empty
+#define EPI_STAT_INITSEQ        0x00000040  // Initialization Sequence
+#define EPI_STAT_WBUSY          0x00000020  // Write Busy
+#define EPI_STAT_NBRBUSY        0x00000010  // Non-Blocking Read Busy
+#define EPI_STAT_ACTIVE         0x00000001  // Register Active
+
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the EPI_O_RFIFOCNT register.
 //
 //*****************************************************************************
-#define EPI_RFIFOCNT_COUNT_M    0x00000007  // FIFO Count.
+#define EPI_RFIFOCNT_COUNT_M    0x00000007  // FIFO Count
 #define EPI_RFIFOCNT_COUNT_S    0
 
 //*****************************************************************************
@@ -257,7 +361,7 @@
 // The following are defines for the bit fields in the EPI_O_READFIFO register.
 //
 //*****************************************************************************
-#define EPI_READFIFO_DATA_M     0xFFFFFFFF  // Reads Data.
+#define EPI_READFIFO_DATA_M     0xFFFFFFFF  // Reads Data
 #define EPI_READFIFO_DATA_S     0
 
 //*****************************************************************************
@@ -266,7 +370,7 @@
 // register.
 //
 //*****************************************************************************
-#define EPI_READFIFO1_DATA_M    0xFFFFFFFF  // Reads Data.
+#define EPI_READFIFO1_DATA_M    0xFFFFFFFF  // Reads Data
 #define EPI_READFIFO1_DATA_S    0
 
 //*****************************************************************************
@@ -275,7 +379,7 @@
 // register.
 //
 //*****************************************************************************
-#define EPI_READFIFO2_DATA_M    0xFFFFFFFF  // Reads Data.
+#define EPI_READFIFO2_DATA_M    0xFFFFFFFF  // Reads Data
 #define EPI_READFIFO2_DATA_S    0
 
 //*****************************************************************************
@@ -284,7 +388,7 @@
 // register.
 //
 //*****************************************************************************
-#define EPI_READFIFO3_DATA_M    0xFFFFFFFF  // Reads Data.
+#define EPI_READFIFO3_DATA_M    0xFFFFFFFF  // Reads Data
 #define EPI_READFIFO3_DATA_S    0
 
 //*****************************************************************************
@@ -293,7 +397,7 @@
 // register.
 //
 //*****************************************************************************
-#define EPI_READFIFO4_DATA_M    0xFFFFFFFF  // Reads Data.
+#define EPI_READFIFO4_DATA_M    0xFFFFFFFF  // Reads Data
 #define EPI_READFIFO4_DATA_S    0
 
 //*****************************************************************************
@@ -302,7 +406,7 @@
 // register.
 //
 //*****************************************************************************
-#define EPI_READFIFO5_DATA_M    0xFFFFFFFF  // Reads Data.
+#define EPI_READFIFO5_DATA_M    0xFFFFFFFF  // Reads Data
 #define EPI_READFIFO5_DATA_S    0
 
 //*****************************************************************************
@@ -311,7 +415,7 @@
 // register.
 //
 //*****************************************************************************
-#define EPI_READFIFO6_DATA_M    0xFFFFFFFF  // Reads Data.
+#define EPI_READFIFO6_DATA_M    0xFFFFFFFF  // Reads Data
 #define EPI_READFIFO6_DATA_S    0
 
 //*****************************************************************************
@@ -320,7 +424,7 @@
 // register.
 //
 //*****************************************************************************
-#define EPI_READFIFO7_DATA_M    0xFFFFFFFF  // Reads Data.
+#define EPI_READFIFO7_DATA_M    0xFFFFFFFF  // Reads Data
 #define EPI_READFIFO7_DATA_S    0
 
 //*****************************************************************************
@@ -328,101 +432,92 @@
 // The following are defines for the bit fields in the EPI_O_FIFOLVL register.
 //
 //*****************************************************************************
-#define EPI_FIFOLVL_WFERR       0x00020000  // Write Full Error.
-#define EPI_FIFOLVL_RSERR       0x00010000  // Read Stall Error.
-#define EPI_FIFOLVL_WRFIFO_M    0x00000070  // Write FIFO.
-#define EPI_FIFOLVL_WRFIFO_EMPT 0x00000000  // Empty
-#define EPI_FIFOLVL_WRFIFO_1_4  0x00000020  // >= 1/4 full
-#define EPI_FIFOLVL_WRFIFO_1_2  0x00000030  // >= 1/2 full
-#define EPI_FIFOLVL_WRFIFO_3_4  0x00000040  // >= 3/4 full
-#define EPI_FIFOLVL_RDFIFO_M    0x00000007  // Read FIFO.
+#define EPI_FIFOLVL_WFERR       0x00020000  // Write Full Error
+#define EPI_FIFOLVL_RSERR       0x00010000  // Read Stall Error
+#define EPI_FIFOLVL_WRFIFO_M    0x00000070  // Write FIFO
+#define EPI_FIFOLVL_WRFIFO_EMPT 0x00000000  // Trigger when there are 1 to 4
+                                            // spaces available in the WFIFO
+#define EPI_FIFOLVL_WRFIFO_1_4  0x00000020  // Trigger when there are 1 to 3
+                                            // spaces available in the WFIFO
+#define EPI_FIFOLVL_WRFIFO_1_2  0x00000030  // Trigger when there are 1 to 2
+                                            // spaces available in the WFIFO
+#define EPI_FIFOLVL_WRFIFO_3_4  0x00000040  // Trigger when there is 1 space
+                                            // available in the WFIFO
+#define EPI_FIFOLVL_RDFIFO_M    0x00000007  // Read FIFO
 #define EPI_FIFOLVL_RDFIFO_EMPT 0x00000000  // Empty
-#define EPI_FIFOLVL_RDFIFO_1_8  0x00000001  // <= 1/8 full
-#define EPI_FIFOLVL_RDFIFO_1_4  0x00000002  // <= 1/4 full
-#define EPI_FIFOLVL_RDFIFO_1_2  0x00000003  // <= 1/2 full
-#define EPI_FIFOLVL_RDFIFO_3_4  0x00000004  // <= 3/4 full
-#define EPI_FIFOLVL_RDFIFO_7_8  0x00000005  // <= 7/8 full
+#define EPI_FIFOLVL_RDFIFO_1_8  0x00000001  // Trigger when there are 1 or more
+                                            // entries in the NBRFIFO
+#define EPI_FIFOLVL_RDFIFO_1_4  0x00000002  // Trigger when there are 2 or more
+                                            // entries in the NBRFIFO
+#define EPI_FIFOLVL_RDFIFO_1_2  0x00000003  // Trigger when there are 4 or more
+                                            // entries in the NBRFIFO
+#define EPI_FIFOLVL_RDFIFO_3_4  0x00000004  // Trigger when there are 6 or more
+                                            // entries in the NBRFIFO
+#define EPI_FIFOLVL_RDFIFO_7_8  0x00000005  // Trigger when there are 7 or more
+                                            // entries in the NBRFIFO
 #define EPI_FIFOLVL_RDFIFO_FULL 0x00000006  // Trigger when there are 8 entries
-                                            // in the NBRFIFO.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the EPI_O_IM register.
-//
-//*****************************************************************************
-#define EPI_IM_WRIM             0x00000004  // Write Interrupt Mask.
-#define EPI_IM_RDIM             0x00000002  // Read Interrupt Mask.
-#define EPI_IM_ERRIM            0x00000001  // Error Interrupt Mask.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the EPI_O_RIS register.
-//
-//*****************************************************************************
-#define EPI_RIS_WRRIS           0x00000004  // Write Raw Interrupt Status.
-#define EPI_RIS_RDRIS           0x00000002  // Read Raw Interrupt Status.
-#define EPI_RIS_ERRRIS          0x00000001  // Error Raw Interrupt Status.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the EPI_O_MIS register.
-//
-//*****************************************************************************
-#define EPI_MIS_WRMIS           0x00000004  // Write Masked Interrupt Status.
-#define EPI_MIS_RDMIS           0x00000002  // Read Masked Interrupt Status.
-#define EPI_MIS_ERRMIS          0x00000001  // Error Masked Interrupt Status.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the EPI_O_SDRAMCFG2
-// register.
-//
-//*****************************************************************************
-#define EPI_SDRAMCFG2_RCM       0x80000000  // Read Capture Mode.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the EPI_O_HB8CFG2 register.
-//
-//*****************************************************************************
-#define EPI_HB8CFG2_WORD        0x80000000  // Word Access Mode.
-#define EPI_HB8CFG2_CSCFG       0x01000000  // Chip Select Configuration.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the EPI_O_GPCFG2 register.
-//
-//*****************************************************************************
-#define EPI_GPCFG2_WORD         0x80000000  // Word Access Mode.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the EPI_O_STAT register.
-//
-//*****************************************************************************
-#define EPI_STAT_CELOW          0x00000200  // Clock Enable Low.
-#define EPI_STAT_XFFULL         0x00000100  // External FIFO Full.
-#define EPI_STAT_XFEMPTY        0x00000080  // External FIFO Empty.
-#define EPI_STAT_INITSEQ        0x00000040  // Initialization Sequence.
-#define EPI_STAT_WBUSY          0x00000020  // Write Busy.
-#define EPI_STAT_NBRBUSY        0x00000010  // Non-Blocking Read Busy.
-#define EPI_STAT_ACTIVE         0x00000001  // Register Active.
+                                            // in the NBRFIFO
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the EPI_O_WFIFOCNT register.
 //
 //*****************************************************************************
-#define EPI_WFIFOCNT_WTAV_M     0x00000007  // Available Write Transactions.
+#define EPI_WFIFOCNT_WTAV_M     0x00000007  // Available Write Transactions
 #define EPI_WFIFOCNT_WTAV_S     0
 
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_IM register.
+//
+//*****************************************************************************
+#define EPI_IM_WRIM             0x00000004  // Write Interrupt Mask
+#define EPI_IM_RDIM             0x00000002  // Read Interrupt Mask
+#define EPI_IM_ERRIM            0x00000001  // Error Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RIS register.
+//
+//*****************************************************************************
+#define EPI_RIS_WRRIS           0x00000004  // Write Raw Interrupt Status
+#define EPI_RIS_RDRIS           0x00000002  // Read Raw Interrupt Status
+#define EPI_RIS_ERRRIS          0x00000001  // Error Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_MIS register.
+//
+//*****************************************************************************
+#define EPI_MIS_WRMIS           0x00000004  // Write Masked Interrupt Status
+#define EPI_MIS_RDMIS           0x00000002  // Read Masked Interrupt Status
+#define EPI_MIS_ERRMIS          0x00000001  // Error Masked Interrupt Status
+
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the EPI_O_EISC register.
 //
 //*****************************************************************************
-#define EPI_EISC_WTFULL         0x00000004  // Write FIFO Full Error.
-#define EPI_EISC_RSTALL         0x00000002  // Read Stalled Error.
-#define EPI_EISC_TOUT           0x00000001  // Timeout Error.
+#define EPI_EISC_WTFULL         0x00000004  // Write FIFO Full Error
+#define EPI_EISC_RSTALL         0x00000002  // Read Stalled Error
+#define EPI_EISC_TOUT           0x00000001  // Timeout Error
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the EPI_O_BAUD
+// register.
+//
+//*****************************************************************************
+#define EPI_BAUD_COUNT_M        0x0000FFFF  // Baud Rate Counter
+#define EPI_BAUD_COUNT_S        0
+
+#endif
 
 #endif // __HW_EPI_H__
diff --git a/src/platform/lm3s/hw_ethernet.h b/src/platform/lm3s/inc/hw_ethernet.h
similarity index 71%
rename from src/platform/lm3s/hw_ethernet.h
rename to src/platform/lm3s/inc/hw_ethernet.h
index af7dc8ea..3fd69f9f 100755
--- a/src/platform/lm3s/hw_ethernet.h
+++ b/src/platform/lm3s/inc/hw_ethernet.h
@@ -2,26 +2,23 @@
 //
 // hw_ethernet.h - Macros used when accessing the Ethernet hardware.
 //
-// Copyright (c) 2006-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2006-2011 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4781 of the Stellaris Firmware Development Package.
+// This is part of revision 7611 of the Stellaris Firmware Development Package.
 //
 //*****************************************************************************
 
@@ -30,86 +27,115 @@
 
 //*****************************************************************************
 //
-// The following are defines for the MAC register offsets in the Ethernet
-// Controller.
+// The following are defines for the Ethernet MAC register offsets.
 //
 //*****************************************************************************
 #define MAC_O_RIS               0x00000000  // Ethernet MAC Raw Interrupt
-                                            // Status
-#define MAC_O_IACK              0x00000000  // Interrupt Acknowledge Register
-#define MAC_O_IM                0x00000004  // Interrupt Mask Register
-#define MAC_O_RCTL              0x00000008  // Receive Control Register
-#define MAC_O_TCTL              0x0000000C  // Transmit Control Register
-#define MAC_O_DATA              0x00000010  // Data Register
-#define MAC_O_IA0               0x00000014  // Individual Address Register 0
-#define MAC_O_IA1               0x00000018  // Individual Address Register 1
-#define MAC_O_THR               0x0000001C  // Threshold Register
-#define MAC_O_MCTL              0x00000020  // Management Control Register
-#define MAC_O_MDV               0x00000024  // Management Divider Register
-#define MAC_O_MTXD              0x0000002C  // Management Transmit Data Reg
-#define MAC_O_MRXD              0x00000030  // Management Receive Data Reg
-#define MAC_O_NP                0x00000034  // Number of Packets Register
-#define MAC_O_TR                0x00000038  // Transmission Request Register
-#define MAC_O_TS                0x0000003C  // Timer Support Register
+                                            // Status/Acknowledge
+#define MAC_O_IACK              0x00000000  // Ethernet MAC Raw Interrupt
+                                            // Status/Acknowledge
+#define MAC_O_IM                0x00000004  // Ethernet MAC Interrupt Mask
+#define MAC_O_RCTL              0x00000008  // Ethernet MAC Receive Control
+#define MAC_O_TCTL              0x0000000C  // Ethernet MAC Transmit Control
+#define MAC_O_DATA              0x00000010  // Ethernet MAC Data
+#define MAC_O_IA0               0x00000014  // Ethernet MAC Individual Address
+                                            // 0
+#define MAC_O_IA1               0x00000018  // Ethernet MAC Individual Address
+                                            // 1
+#define MAC_O_THR               0x0000001C  // Ethernet MAC Threshold
+#define MAC_O_MCTL              0x00000020  // Ethernet MAC Management Control
+#define MAC_O_MDV               0x00000024  // Ethernet MAC Management Divider
+#define MAC_O_MADD              0x00000028  // Ethernet MAC Management Address
+#define MAC_O_MTXD              0x0000002C  // Ethernet MAC Management Transmit
+                                            // Data
+#define MAC_O_MRXD              0x00000030  // Ethernet MAC Management Receive
+                                            // Data
+#define MAC_O_NP                0x00000034  // Ethernet MAC Number of Packets
+#define MAC_O_TR                0x00000038  // Ethernet MAC Transmission
+                                            // Request
+#define MAC_O_TS                0x0000003C  // Ethernet MAC Timer Support
 #define MAC_O_LED               0x00000040  // Ethernet MAC LED Encoding
-#define MAC_O_MDIX              0x00000044  // MDIX Register
+#define MAC_O_MDIX              0x00000044  // Ethernet PHY MDIX
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the MAC_IACK register.
+// The following are defines for the bit fields in the MAC_O_RIS register.
+//
+//*****************************************************************************
+#define MAC_RIS_PHYINT          0x00000040  // PHY Interrupt
+#define MAC_RIS_MDINT           0x00000020  // MII Transaction Complete
+#define MAC_RIS_RXER            0x00000010  // Receive Error
+#define MAC_RIS_FOV             0x00000008  // FIFO Overrun
+#define MAC_RIS_TXEMP           0x00000004  // Transmit FIFO Empty
+#define MAC_RIS_TXER            0x00000002  // Transmit Error
+#define MAC_RIS_RXINT           0x00000001  // Packet Received
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_IACK register.
 //
 //*****************************************************************************
 #define MAC_IACK_PHYINT         0x00000040  // Clear PHY Interrupt
-#define MAC_IACK_MDINT          0x00000020  // Clear MDI Transaction Complete
-#define MAC_IACK_RXER           0x00000010  // Clear RX Error
-#define MAC_IACK_FOV            0x00000008  // Clear RX FIFO Overrun
-#define MAC_IACK_TXEMP          0x00000004  // Clear TX FIFO Empy
-#define MAC_IACK_TXER           0x00000002  // Clear TX Error
-#define MAC_IACK_RXINT          0x00000001  // Clear RX Packet Available
+#define MAC_IACK_MDINT          0x00000020  // Clear MII Transaction Complete
+#define MAC_IACK_RXER           0x00000010  // Clear Receive Error
+#define MAC_IACK_FOV            0x00000008  // Clear FIFO Overrun
+#define MAC_IACK_TXEMP          0x00000004  // Clear Transmit FIFO Empty
+#define MAC_IACK_TXER           0x00000002  // Clear Transmit Error
+#define MAC_IACK_RXINT          0x00000001  // Clear Packet Received
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the MAC_IM register.
+// The following are defines for the bit fields in the MAC_O_IM register.
 //
 //*****************************************************************************
 #define MAC_IM_PHYINTM          0x00000040  // Mask PHY Interrupt
-#define MAC_IM_MDINTM           0x00000020  // Mask MDI Transaction Complete
-#define MAC_IM_RXERM            0x00000010  // Mask RX Error
-#define MAC_IM_FOVM             0x00000008  // Mask RX FIFO Overrun
-#define MAC_IM_TXEMPM           0x00000004  // Mask TX FIFO Empy
-#define MAC_IM_TXERM            0x00000002  // Mask TX Error
-#define MAC_IM_RXINTM           0x00000001  // Mask RX Packet Available
+#define MAC_IM_MDINTM           0x00000020  // Mask MII Transaction Complete
+#define MAC_IM_RXERM            0x00000010  // Mask Receive Error
+#define MAC_IM_FOVM             0x00000008  // Mask FIFO Overrun
+#define MAC_IM_TXEMPM           0x00000004  // Mask Transmit FIFO Empty
+#define MAC_IM_TXERM            0x00000002  // Mask Transmit Error
+#define MAC_IM_RXINTM           0x00000001  // Mask Packet Received
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the MAC_RCTL register.
+// The following are defines for the bit fields in the MAC_O_RCTL register.
 //
 //*****************************************************************************
-#define MAC_RCTL_RSTFIFO        0x00000010  // Clear the Receive FIFO
-#define MAC_RCTL_BADCRC         0x00000008  // Reject Packets With Bad CRC
+#define MAC_RCTL_RSTFIFO        0x00000010  // Clear Receive FIFO
+#define MAC_RCTL_BADCRC         0x00000008  // Enable Reject Bad CRC
 #define MAC_RCTL_PRMS           0x00000004  // Enable Promiscuous Mode
-#define MAC_RCTL_AMUL           0x00000002  // Enable Multicast Packets
-#define MAC_RCTL_RXEN           0x00000001  // Enable Ethernet Receiver
+#define MAC_RCTL_AMUL           0x00000002  // Enable Multicast Frames
+#define MAC_RCTL_RXEN           0x00000001  // Enable Receiver
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the MAC_TCTL register.
+// The following are defines for the bit fields in the MAC_O_TCTL register.
 //
 //*****************************************************************************
-#define MAC_TCTL_DUPLEX         0x00000010  // Enable Duplex mode
+#define MAC_TCTL_DUPLEX         0x00000010  // Enable Duplex Mode
 #define MAC_TCTL_CRC            0x00000004  // Enable CRC Generation
-#define MAC_TCTL_PADEN          0x00000002  // Enable Automatic Padding
-#define MAC_TCTL_TXEN           0x00000001  // Enable Ethernet Transmitter
+#define MAC_TCTL_PADEN          0x00000002  // Enable Packet Padding
+#define MAC_TCTL_TXEN           0x00000001  // Enable Transmitter
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the MAC_IA0 register.
+// The following are defines for the bit fields in the MAC_O_DATA register.
 //
 //*****************************************************************************
-#define MAC_IA0_MACOCT4_M       0xFF000000  // MAC Address Octet 4.
-#define MAC_IA0_MACOCT3_M       0x00FF0000  // MAC Address Octet 3.
-#define MAC_IA0_MACOCT2_M       0x0000FF00  // MAC Address Octet 2.
-#define MAC_IA0_MACOCT1_M       0x000000FF  // MAC Address Octet 1.
+#define MAC_DATA_TXDATA_M       0xFFFFFFFF  // Transmit FIFO Data
+#define MAC_DATA_RXDATA_M       0xFFFFFFFF  // Receive FIFO Data
+#define MAC_DATA_RXDATA_S       0
+#define MAC_DATA_TXDATA_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_IA0 register.
+//
+//*****************************************************************************
+#define MAC_IA0_MACOCT4_M       0xFF000000  // MAC Address Octet 4
+#define MAC_IA0_MACOCT3_M       0x00FF0000  // MAC Address Octet 3
+#define MAC_IA0_MACOCT2_M       0x0000FF00  // MAC Address Octet 2
+#define MAC_IA0_MACOCT1_M       0x000000FF  // MAC Address Octet 1
 #define MAC_IA0_MACOCT4_S       24
 #define MAC_IA0_MACOCT3_S       16
 #define MAC_IA0_MACOCT2_S       8
@@ -117,85 +143,115 @@
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the MAC_IA1 register.
+// The following are defines for the bit fields in the MAC_O_IA1 register.
 //
 //*****************************************************************************
-#define MAC_IA1_MACOCT6_M       0x0000FF00  // MAC Address Octet 6.
-#define MAC_IA1_MACOCT5_M       0x000000FF  // MAC Address Octet 5.
+#define MAC_IA1_MACOCT6_M       0x0000FF00  // MAC Address Octet 6
+#define MAC_IA1_MACOCT5_M       0x000000FF  // MAC Address Octet 5
 #define MAC_IA1_MACOCT6_S       8
 #define MAC_IA1_MACOCT5_S       0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the MAC_TXTH register.
+// The following are defines for the bit fields in the MAC_O_THR register.
 //
 //*****************************************************************************
-#define MAC_THR_THRESH_M        0x0000003F  // Threshold Value.
+#define MAC_THR_THRESH_M        0x0000003F  // Threshold Value
 #define MAC_THR_THRESH_S        0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the MAC_MCTL register.
+// The following are defines for the bit fields in the MAC_O_MCTL register.
 //
 //*****************************************************************************
-#define MAC_MCTL_REGADR_M       0x000000F8  // MII Register Address.
-#define MAC_MCTL_WRITE          0x00000002  // Next MII Transaction is Write
-#define MAC_MCTL_START          0x00000001  // Start MII Transaction
+#define MAC_MCTL_REGADR_M       0x000000F8  // MII Register Address
+#define MAC_MCTL_WRITE          0x00000002  // MII Register Transaction Type
+#define MAC_MCTL_START          0x00000001  // MII Register Transaction Enable
 #define MAC_MCTL_REGADR_S       3
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the MAC_MDV register.
+// The following are defines for the bit fields in the MAC_O_MDV register.
 //
 //*****************************************************************************
-#define MAC_MDV_DIV_M           0x000000FF  // Clock Divider.
+#define MAC_MDV_DIV_M           0x000000FF  // Clock Divider
 #define MAC_MDV_DIV_S           0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the MAC_MTXD register.
+// The following are defines for the bit fields in the MAC_O_MADD register.
 //
 //*****************************************************************************
-#define MAC_MTXD_MDTX_M         0x0000FFFF  // MII Register Transmit Data.
+#define MAC_MADD_PHYADR_M       0x0000001F  // PHY Address
+#define MAC_MADD_PHYADR_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MTXD register.
+//
+//*****************************************************************************
+#define MAC_MTXD_MDTX_M         0x0000FFFF  // MII Register Transmit Data
 #define MAC_MTXD_MDTX_S         0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the MAC_MRXD register.
+// The following are defines for the bit fields in the MAC_O_MRXD register.
 //
 //*****************************************************************************
-#define MAC_MRXD_MDRX_M         0x0000FFFF  // MII Register Receive Data.
+#define MAC_MRXD_MDRX_M         0x0000FFFF  // MII Register Receive Data
 #define MAC_MRXD_MDRX_S         0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the MAC_NP register.
+// The following are defines for the bit fields in the MAC_O_NP register.
 //
 //*****************************************************************************
 #define MAC_NP_NPR_M            0x0000003F  // Number of Packets in Receive
-                                            // FIFO.
+                                            // FIFO
 #define MAC_NP_NPR_S            0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the MAC_TXRQ register.
+// The following are defines for the bit fields in the MAC_O_TR register.
 //
 //*****************************************************************************
-#define MAC_TR_NEWTX            0x00000001  // Start an Ethernet Transmission
+#define MAC_TR_NEWTX            0x00000001  // New Transmission
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the MAC_TS register.
+// The following are defines for the bit fields in the MAC_O_TS register.
 //
 //*****************************************************************************
-#define MAC_TS_TSEN             0x00000001  // Enable Timestamp Logic
+#define MAC_TS_TSEN             0x00000001  // Time Stamp Enable
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the MAC_MDIX register.
+// The following are defines for the bit fields in the MAC_O_LED register.
 //
 //*****************************************************************************
-#define MAC_MDIX_EN             0x00000001  // MDI/MDI-X Enable.
+#define MAC_LED_LED1_M          0x00000F00  // LED1 Source
+#define MAC_LED_LED1_LINK       0x00000000  // Link OK
+#define MAC_LED_LED1_RXTX       0x00000100  // RX or TX Activity (Default LED1)
+#define MAC_LED_LED1_100        0x00000500  // 100BASE-TX mode
+#define MAC_LED_LED1_10         0x00000600  // 10BASE-T mode
+#define MAC_LED_LED1_DUPLEX     0x00000700  // Full-Duplex
+#define MAC_LED_LED1_LINKACT    0x00000800  // Link OK & Blink=RX or TX
+                                            // Activity
+#define MAC_LED_LED0_M          0x0000000F  // LED0 Source
+#define MAC_LED_LED0_LINK       0x00000000  // Link OK (Default LED0)
+#define MAC_LED_LED0_RXTX       0x00000001  // RX or TX Activity
+#define MAC_LED_LED0_100        0x00000005  // 100BASE-TX mode
+#define MAC_LED_LED0_10         0x00000006  // 10BASE-T mode
+#define MAC_LED_LED0_DUPLEX     0x00000007  // Full-Duplex
+#define MAC_LED_LED0_LINKACT    0x00000008  // Link OK & Blink=RX or TX
+                                            // Activity
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MDIX register.
+//
+//*****************************************************************************
+#define MAC_MDIX_EN             0x00000001  // MDI/MDI-X Enable
 
 //*****************************************************************************
 //
@@ -221,7 +277,7 @@
 #define PHY_MR16                0x00000010  // Ethernet PHY Management Register
                                             // 16 - Vendor-Specific
 #define PHY_MR17                0x00000011  // Ethernet PHY Management Register
-                                            // 17 - Interrupt Control/Status
+                                            // 17 - Mode Control/Status
 #define PHY_MR18                0x00000012  // Ethernet PHY Management Register
                                             // 18 - Diagnostic
 #define PHY_MR19                0x00000013  // Ethernet PHY Management Register
@@ -231,7 +287,7 @@
 #define PHY_MR24                0x00000018  // Ethernet PHY Management Register
                                             // 24 -MDI/MDIX Control
 #define PHY_MR27                0x0000001B  // Ethernet PHY Management Register
-                                            // 27 -Special Control/Status
+                                            // 27 - Special Control/Status
 #define PHY_MR29                0x0000001D  // Ethernet PHY Management Register
                                             // 29 - Interrupt Status
 #define PHY_MR30                0x0000001E  // Ethernet PHY Management Register
@@ -244,46 +300,33 @@
 // The following are defines for the bit fields in the PHY_MR0 register.
 //
 //*****************************************************************************
-#define PHY_MR0_RESET           0x00008000  // Reset Registers.
-#define PHY_MR0_LOOPBK          0x00004000  // Loopback Mode.
-#define PHY_MR0_SPEEDSL         0x00002000  // Speed Select.
-#define PHY_MR0_ANEGEN          0x00001000  // Auto-Negotiation Enable.
-#define PHY_MR0_PWRDN           0x00000800  // Power Down.
-#define PHY_MR0_ISO             0x00000400  // Isolate.
-#define PHY_MR0_RANEG           0x00000200  // Restart Auto-Negotiation.
-#define PHY_MR0_DUPLEX          0x00000100  // Set Duplex Mode.
-#define PHY_MR0_COLT            0x00000080  // Collision Test.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_RIS register.
-//
-//*****************************************************************************
-#define MAC_RIS_PHYINT          0x00000040  // PHY Interrupt.
-#define MAC_RIS_MDINT           0x00000020  // MII Transaction Complete.
-#define MAC_RIS_RXER            0x00000010  // Receive Error.
-#define MAC_RIS_FOV             0x00000008  // FIFO Overrrun.
-#define MAC_RIS_TXEMP           0x00000004  // Transmit FIFO Empty.
-#define MAC_RIS_TXER            0x00000002  // Transmit Error.
-#define MAC_RIS_RXINT           0x00000001  // Packet Received.
+#define PHY_MR0_RESET           0x00008000  // Reset Registers
+#define PHY_MR0_LOOPBK          0x00004000  // Loopback Mode
+#define PHY_MR0_SPEEDSL         0x00002000  // Speed Select
+#define PHY_MR0_ANEGEN          0x00001000  // Auto-Negotiation Enable
+#define PHY_MR0_PWRDN           0x00000800  // Power Down
+#define PHY_MR0_ISO             0x00000400  // Isolate
+#define PHY_MR0_RANEG           0x00000200  // Restart Auto-Negotiation
+#define PHY_MR0_DUPLEX          0x00000100  // Set Duplex Mode
+#define PHY_MR0_COLT            0x00000080  // Collision Test
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the PHY_MR1 register.
 //
 //*****************************************************************************
-#define PHY_MR1_100X_F          0x00004000  // 100BASE-TX Full-Duplex Mode.
-#define PHY_MR1_100X_H          0x00002000  // 100BASE-TX Half-Duplex Mode.
-#define PHY_MR1_10T_F           0x00001000  // 10BASE-T Full-Duplex Mode.
-#define PHY_MR1_10T_H           0x00000800  // 10BASE-T Half-Duplex Mode.
+#define PHY_MR1_100X_F          0x00004000  // 100BASE-TX Full-Duplex Mode
+#define PHY_MR1_100X_H          0x00002000  // 100BASE-TX Half-Duplex Mode
+#define PHY_MR1_10T_F           0x00001000  // 10BASE-T Full-Duplex Mode
+#define PHY_MR1_10T_H           0x00000800  // 10BASE-T Half-Duplex Mode
 #define PHY_MR1_MFPS            0x00000040  // Management Frames with Preamble
-                                            // Suppressed.
-#define PHY_MR1_ANEGC           0x00000020  // Auto-Negotiation Complete.
-#define PHY_MR1_RFAULT          0x00000010  // Remote Fault.
-#define PHY_MR1_ANEGA           0x00000008  // Auto-Negotiation.
-#define PHY_MR1_LINK            0x00000004  // Link Made.
-#define PHY_MR1_JAB             0x00000002  // Jabber Condition.
-#define PHY_MR1_EXTD            0x00000001  // Extended Capabilities.
+                                            // Suppressed
+#define PHY_MR1_ANEGC           0x00000020  // Auto-Negotiation Complete
+#define PHY_MR1_RFAULT          0x00000010  // Remote Fault
+#define PHY_MR1_ANEGA           0x00000008  // Auto-Negotiation
+#define PHY_MR1_LINK            0x00000004  // Link Made
+#define PHY_MR1_JAB             0x00000002  // Jabber Condition
+#define PHY_MR1_EXTD            0x00000001  // Extended Capabilities
 
 //*****************************************************************************
 //
@@ -291,7 +334,7 @@
 //
 //*****************************************************************************
 #define PHY_MR2_OUI_M           0x0000FFFF  // Organizationally Unique
-                                            // Identifier[21:6].
+                                            // Identifier[21:6]
 #define PHY_MR2_OUI_S           0
 
 //*****************************************************************************
@@ -300,9 +343,9 @@
 //
 //*****************************************************************************
 #define PHY_MR3_OUI_M           0x0000FC00  // Organizationally Unique
-                                            // Identifier[5:0].
-#define PHY_MR3_MN_M            0x000003F0  // Model Number.
-#define PHY_MR3_RN_M            0x0000000F  // Revision Number.
+                                            // Identifier[5:0]
+#define PHY_MR3_MN_M            0x000003F0  // Model Number
+#define PHY_MR3_RN_M            0x0000000F  // Revision Number
 #define PHY_MR3_OUI_S           10
 #define PHY_MR3_MN_S            4
 #define PHY_MR3_RN_S            0
@@ -312,13 +355,13 @@
 // The following are defines for the bit fields in the PHY_MR4 register.
 //
 //*****************************************************************************
-#define PHY_MR4_NP              0x00008000  // Next Page.
-#define PHY_MR4_RF              0x00002000  // Remote Fault.
-#define PHY_MR4_A3              0x00000100  // Technology Ability Field[3].
-#define PHY_MR4_A2              0x00000080  // Technology Ability Field[2].
-#define PHY_MR4_A1              0x00000040  // Technology Ability Field[1].
-#define PHY_MR4_A0              0x00000020  // Technology Ability Field[0].
-#define PHY_MR4_S_M             0x0000001F  // Selector Field.
+#define PHY_MR4_NP              0x00008000  // Next Page
+#define PHY_MR4_RF              0x00002000  // Remote Fault
+#define PHY_MR4_A3              0x00000100  // Technology Ability Field [3]
+#define PHY_MR4_A2              0x00000080  // Technology Ability Field [2]
+#define PHY_MR4_A1              0x00000040  // Technology Ability Field [1]
+#define PHY_MR4_A0              0x00000020  // Technology Ability Field [0]
+#define PHY_MR4_S_M             0x0000001F  // Selector Field
 #define PHY_MR4_S_S             0
 
 //*****************************************************************************
@@ -326,11 +369,11 @@
 // The following are defines for the bit fields in the PHY_MR5 register.
 //
 //*****************************************************************************
-#define PHY_MR5_NP              0x00008000  // Next Page.
-#define PHY_MR5_ACK             0x00004000  // Acknowledge.
-#define PHY_MR5_RF              0x00002000  // Remote Fault.
-#define PHY_MR5_A_M             0x00001FE0  // Technology Ability Field.
-#define PHY_MR5_S_M             0x0000001F  // Selector Field.
+#define PHY_MR5_NP              0x00008000  // Next Page
+#define PHY_MR5_ACK             0x00004000  // Acknowledge
+#define PHY_MR5_RF              0x00002000  // Remote Fault
+#define PHY_MR5_A_M             0x00001FE0  // Technology Ability Field
+#define PHY_MR5_S_M             0x0000001F  // Selector Field
 #define PHY_MR5_S_8023          0x00000001  // IEEE Std 802.3
 #define PHY_MR5_S_8029          0x00000002  // IEEE Std 802.9 ISLAN-16T
 #define PHY_MR5_S_8025          0x00000003  // IEEE Std 802.5
@@ -342,37 +385,27 @@
 // The following are defines for the bit fields in the PHY_MR6 register.
 //
 //*****************************************************************************
-#define PHY_MR6_PDF             0x00000010  // Parallel Detection Fault.
-#define PHY_MR6_LPNPA           0x00000008  // Link Partner is Next Page Able.
-#define PHY_MR6_PRX             0x00000002  // New Page Received.
+#define PHY_MR6_PDF             0x00000010  // Parallel Detection Fault
+#define PHY_MR6_LPNPA           0x00000008  // Link Partner is Next Page Able
+#define PHY_MR6_PRX             0x00000002  // New Page Received
 #define PHY_MR6_LPANEGA         0x00000001  // Link Partner is Auto-Negotiation
-                                            // Able.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_DATA register.
-//
-//*****************************************************************************
-#define MAC_DATA_TXDATA_M       0xFFFFFFFF  // Transmit FIFO Data.
-#define MAC_DATA_RXDATA_M       0xFFFFFFFF  // Receive FIFO Data.
-#define MAC_DATA_RXDATA_S       0
-#define MAC_DATA_TXDATA_S       0
+                                            // Able
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the PHY_MR16 register.
 //
 //*****************************************************************************
-#define PHY_MR16_RPTR           0x00008000  // Repeater Mode.
-#define PHY_MR16_INPOL          0x00004000  // Interrupt Polarity.
-#define PHY_MR16_TXHIM          0x00001000  // Transmit High Impedance Mode.
-#define PHY_MR16_SQEI           0x00000800  // SQE Inhibit Testing.
-#define PHY_MR16_NL10           0x00000400  // Natural Loopback Mode.
-#define PHY_MR16_SR_M           0x000003C0  // Silicon Revision Identifier.
-#define PHY_MR16_APOL           0x00000020  // Auto-Polarity Disable.
-#define PHY_MR16_RVSPOL         0x00000010  // Receive Data Polarity.
-#define PHY_MR16_PCSBP          0x00000002  // PCS Bypass.
-#define PHY_MR16_RXCC           0x00000001  // Receive Clock Control.
+#define PHY_MR16_RPTR           0x00008000  // Repeater Mode
+#define PHY_MR16_INPOL          0x00004000  // Interrupt Polarity
+#define PHY_MR16_TXHIM          0x00001000  // Transmit High Impedance Mode
+#define PHY_MR16_SQEI           0x00000800  // SQE Inhibit Testing
+#define PHY_MR16_NL10           0x00000400  // Natural Loopback Mode
+#define PHY_MR16_SR_M           0x000003C0  // Silicon Revision Identifier
+#define PHY_MR16_APOL           0x00000020  // Auto-Polarity Disable
+#define PHY_MR16_RVSPOL         0x00000010  // Receive Data Polarity
+#define PHY_MR16_PCSBP          0x00000002  // PCS Bypass
+#define PHY_MR16_RXCC           0x00000001  // Receive Clock Control
 #define PHY_MR16_SR_S           6
 
 //*****************************************************************************
@@ -380,55 +413,51 @@
 // The following are defines for the bit fields in the PHY_MR17 register.
 //
 //*****************************************************************************
-#define PHY_MR17_JABBER_IE      0x00008000  // Jabber Interrupt Enable.
-#define PHY_MR17_FASTRIP        0x00004000  // 10-BASE-T Fast Mode Enable.
-#define PHY_MR17_RXER_IE        0x00004000  // Receive Error Interrupt Enable.
-#define PHY_MR17_EDPD           0x00002000  // Enable Energy Detect Power Down.
-#define PHY_MR17_PRX_IE         0x00002000  // Page Received Interrupt Enable.
+#define PHY_MR17_JABBER_IE      0x00008000  // Jabber Interrupt Enable
+#define PHY_MR17_FASTRIP        0x00004000  // 10-BASE-T Fast Mode Enable
+#define PHY_MR17_RXER_IE        0x00004000  // Receive Error Interrupt Enable
+#define PHY_MR17_EDPD           0x00002000  // Enable Energy Detect Power Down
+#define PHY_MR17_PRX_IE         0x00002000  // Page Received Interrupt Enable
 #define PHY_MR17_PDF_IE         0x00001000  // Parallel Detection Fault
-                                            // Interrupt Enable.
-#define PHY_MR17_LSQE           0x00000800  // Low Squelch Enable.
-#define PHY_MR17_LPACK_IE       0x00000800  // LP Acknowledge Interrupt Enable.
+                                            // Interrupt Enable
+#define PHY_MR17_LSQE           0x00000800  // Low Squelch Enable
+#define PHY_MR17_LPACK_IE       0x00000800  // LP Acknowledge Interrupt Enable
 #define PHY_MR17_LSCHG_IE       0x00000400  // Link Status Change Interrupt
-                                            // Enable.
-#define PHY_MR17_MDPB           0x00000400  // Management Data Preamble Bypass.
-#define PHY_MR17_RFAULT_IE      0x00000200  // Remote Fault Interrupt Enable.
-#define PHY_MR17_FLPBK          0x00000200  // Far Loopback Mode.
+                                            // Enable
+#define PHY_MR17_RFAULT_IE      0x00000200  // Remote Fault Interrupt Enable
 #define PHY_MR17_ANEGCOMP_IE    0x00000100  // Auto-Negotiation Complete
-                                            // Interrupt Enable.
-#define PHY_MR17_FASTEST        0x00000100  // Auto-Negotiation Test Mode.
-#define PHY_MR17_JABBER_INT     0x00000080  // Jabber Event Interrupt.
-#define PHY_MR17_RXER_INT       0x00000040  // Receive Error Interrupt.
-#define PHY_MR17_PRX_INT        0x00000020  // Page Receive Interrupt.
+                                            // Interrupt Enable
+#define PHY_MR17_FASTEST        0x00000100  // Auto-Negotiation Test Mode
+#define PHY_MR17_JABBER_INT     0x00000080  // Jabber Event Interrupt
+#define PHY_MR17_RXER_INT       0x00000040  // Receive Error Interrupt
+#define PHY_MR17_PRX_INT        0x00000020  // Page Receive Interrupt
 #define PHY_MR17_PDF_INT        0x00000010  // Parallel Detection Fault
-                                            // Interrupt.
-#define PHY_MR17_REFCE          0x00000010  // Reference Clock Enable.
-#define PHY_MR17_LPACK_INT      0x00000008  // LP Acknowledge Interrupt.
-#define PHY_MR17_PADBP          0x00000008  // PHY Address Bypass.
-#define PHY_MR17_LSCHG_INT      0x00000004  // Link Status Change Interrupt.
-#define PHY_MR17_FGLS           0x00000004  // Force Good Link Status.
-#define PHY_MR17_RFAULT_INT     0x00000002  // Remote Fault Interrupt.
-#define PHY_MR17_ENON           0x00000002  // Energy On.
+                                            // Interrupt
+#define PHY_MR17_LPACK_INT      0x00000008  // LP Acknowledge Interrupt
+#define PHY_MR17_LSCHG_INT      0x00000004  // Link Status Change Interrupt
+#define PHY_MR17_FGLS           0x00000004  // Force Good Link Status
+#define PHY_MR17_RFAULT_INT     0x00000002  // Remote Fault Interrupt
+#define PHY_MR17_ENON           0x00000002  // Energy On
 #define PHY_MR17_ANEGCOMP_INT   0x00000001  // Auto-Negotiation Complete
-                                            // Interrupt.
+                                            // Interrupt
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the PHY_MR18 register.
 //
 //*****************************************************************************
-#define PHY_MR18_ANEGF          0x00001000  // Auto-Negotiation Failure.
-#define PHY_MR18_DPLX           0x00000800  // Duplex Mode.
-#define PHY_MR18_RATE           0x00000400  // Rate.
-#define PHY_MR18_RXSD           0x00000200  // Receive Detection.
-#define PHY_MR18_RX_LOCK        0x00000100  // Receive PLL Lock.
+#define PHY_MR18_ANEGF          0x00001000  // Auto-Negotiation Failure
+#define PHY_MR18_DPLX           0x00000800  // Duplex Mode
+#define PHY_MR18_RATE           0x00000400  // Rate
+#define PHY_MR18_RXSD           0x00000200  // Receive Detection
+#define PHY_MR18_RX_LOCK        0x00000100  // Receive PLL Lock
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the PHY_MR19 register.
 //
 //*****************************************************************************
-#define PHY_MR19_TXO_M          0x0000C000  // Transmit Amplitude Selection.
+#define PHY_MR19_TXO_M          0x0000C000  // Transmit Amplitude Selection
 #define PHY_MR19_TXO_00DB       0x00000000  // Gain set for 0.0dB of insertion
                                             // loss
 #define PHY_MR19_TXO_04DB       0x00004000  // Gain set for 0.4dB of insertion
@@ -443,7 +472,7 @@
 // The following are defines for the bit fields in the PHY_MR23 register.
 //
 //*****************************************************************************
-#define PHY_MR23_LED1_M         0x000000F0  // LED1 Source.
+#define PHY_MR23_LED1_M         0x000000F0  // LED1 Source
 #define PHY_MR23_LED1_LINK      0x00000000  // Link OK
 #define PHY_MR23_LED1_RXTX      0x00000010  // RX or TX Activity (Default LED1)
 #define PHY_MR23_LED1_100       0x00000050  // 100BASE-TX mode
@@ -451,7 +480,7 @@
 #define PHY_MR23_LED1_DUPLEX    0x00000070  // Full-Duplex
 #define PHY_MR23_LED1_LINKACT   0x00000080  // Link OK & Blink=RX or TX
                                             // Activity
-#define PHY_MR23_LED0_M         0x0000000F  // LED0 Source.
+#define PHY_MR23_LED0_M         0x0000000F  // LED0 Source
 #define PHY_MR23_LED0_LINK      0x00000000  // Link OK (Default LED0)
 #define PHY_MR23_LED0_RXTX      0x00000001  // RX or TX Activity
 #define PHY_MR23_LED0_100       0x00000005  // 100BASE-TX mode
@@ -465,11 +494,11 @@
 // The following are defines for the bit fields in the PHY_MR24 register.
 //
 //*****************************************************************************
-#define PHY_MR24_PD_MODE        0x00000080  // Parallel Detection Mode.
-#define PHY_MR24_AUTO_SW        0x00000040  // Auto-Switching Enable.
-#define PHY_MR24_MDIX           0x00000020  // Auto-Switching Configuration.
-#define PHY_MR24_MDIX_CM        0x00000010  // Auto-Switching Complete.
-#define PHY_MR24_MDIX_SD_M      0x0000000F  // Auto-Switching Seed.
+#define PHY_MR24_PD_MODE        0x00000080  // Parallel Detection Mode
+#define PHY_MR24_AUTO_SW        0x00000040  // Auto-Switching Enable
+#define PHY_MR24_MDIX           0x00000020  // Auto-Switching Configuration
+#define PHY_MR24_MDIX_CM        0x00000010  // Auto-Switching Complete
+#define PHY_MR24_MDIX_SD_M      0x0000000F  // Auto-Switching Seed
 #define PHY_MR24_MDIX_SD_S      0
 
 //*****************************************************************************
@@ -477,72 +506,50 @@
 // The following are defines for the bit fields in the PHY_MR27 register.
 //
 //*****************************************************************************
-#define PHY_MR27_XPOL           0x00000010  // Polarity State of 10 BASE-T.
+#define PHY_MR27_XPOL           0x00000010  // Polarity State of 10 BASE-T
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the PHY_MR29 register.
 //
 //*****************************************************************************
-#define PHY_MR29_EONIS          0x00000080  // ENERGYON Interrupt.
+#define PHY_MR29_EONIS          0x00000080  // ENERGYON Interrupt
 #define PHY_MR29_ANCOMPIS       0x00000040  // Auto-Negotiation Complete
-                                            // Interrupt.
-#define PHY_MR29_RFLTIS         0x00000020  // Remote Fault Interrupt.
-#define PHY_MR29_LDIS           0x00000010  // Link Down Interrupt.
-#define PHY_MR29_LPACKIS        0x00000008  // Auto-Negotiation LP Acknowledge.
-#define PHY_MR29_PDFIS          0x00000004  // Parallel Detection Fault.
-#define PHY_MR29_PRXIS          0x00000002  // Auto Negotiation Page Received.
+                                            // Interrupt
+#define PHY_MR29_RFLTIS         0x00000020  // Remote Fault Interrupt
+#define PHY_MR29_LDIS           0x00000010  // Link Down Interrupt
+#define PHY_MR29_LPACKIS        0x00000008  // Auto-Negotiation LP Acknowledge
+#define PHY_MR29_PDFIS          0x00000004  // Parallel Detection Fault
+#define PHY_MR29_PRXIS          0x00000002  // Auto Negotiation Page Received
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the PHY_MR30 register.
 //
 //*****************************************************************************
-#define PHY_MR30_EONIM          0x00000080  // ENERGYON Interrupt Enabled.
+#define PHY_MR30_EONIM          0x00000080  // ENERGYON Interrupt Enabled
 #define PHY_MR30_ANCOMPIM       0x00000040  // Auto-Negotiation Complete
-                                            // Interrupt Enabled.
-#define PHY_MR30_RFLTIM         0x00000020  // Remote Fault Interrupt Enabled.
-#define PHY_MR30_LDIM           0x00000010  // Link Down Interrupt Enabled.
+                                            // Interrupt Enabled
+#define PHY_MR30_RFLTIM         0x00000020  // Remote Fault Interrupt Enabled
+#define PHY_MR30_LDIM           0x00000010  // Link Down Interrupt Enabled
 #define PHY_MR30_LPACKIM        0x00000008  // Auto-Negotiation LP Acknowledge
-                                            // Enabled.
-#define PHY_MR30_PDFIM          0x00000004  // Parallel Detection Fault
-                                            // Enabled.
+                                            // Enabled
+#define PHY_MR30_PDFIM          0x00000004  // Parallel Detection Fault Enabled
 #define PHY_MR30_PRXIM          0x00000002  // Auto Negotiation Page Received
-                                            // Enabled.
+                                            // Enabled
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the PHY_MR31 register.
 //
 //*****************************************************************************
-#define PHY_MR31_BPRMG          0x00008000  // Bypass Remove Glitch.
-#define PHY_MR31_AUTODONE       0x00001000  // Auto Negotiation Done.
-#define PHY_MR31_EN4B5B         0x00000040  // Enable 4B5B Encoding/Decoding.
-#define PHY_MR31_SPEED_M        0x0000001C  // HCD Speed Value.
-#define PHY_MR31_SCRDIS         0x00000001  // Scramble Disable.
-#define PHY_MR31_SPEED_S        2
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_LED register.
-//
-//*****************************************************************************
-#define MAC_LED_LED1_M          0x000000F0  // LED1 Source.
-#define MAC_LED_LED1_LINK       0x00000000  // Link OK
-#define MAC_LED_LED1_RXTX       0x00000010  // RX or TX Activity (Default LED1)
-#define MAC_LED_LED1_100        0x00000050  // 100BASE-TX mode
-#define MAC_LED_LED1_10         0x00000060  // 10BASE-T mode
-#define MAC_LED_LED1_DUPLEX     0x00000070  // Full-Duplex
-#define MAC_LED_LED1_LINKACT    0x00000080  // Link OK & Blink=RX or TX
-                                            // Activity
-#define MAC_LED_LED0_M          0x0000000F  // LED0 Source.
-#define MAC_LED_LED0_LINK       0x00000000  // Link OK (Default LED0)
-#define MAC_LED_LED0_RXTX       0x00000001  // RX or TX Activity
-#define MAC_LED_LED0_100        0x00000005  // 100BASE-TX mode
-#define MAC_LED_LED0_10         0x00000006  // 10BASE-T mode
-#define MAC_LED_LED0_DUPLEX     0x00000007  // Full-Duplex
-#define MAC_LED_LED0_LINKACT    0x00000008  // Link OK & Blink=RX or TX
-                                            // Activity
+#define PHY_MR31_AUTODONE       0x00001000  // Auto Negotiation Done
+#define PHY_MR31_SPEED_M        0x0000001C  // HCD Speed Value
+#define PHY_MR31_SPEED_10HD     0x00000004  // 10BASE-T half duplex
+#define PHY_MR31_SPEED_100HD    0x00000008  // 100BASE-T half duplex
+#define PHY_MR31_SPEED_10FD     0x00000014  // 10BASE-T full duplex
+#define PHY_MR31_SPEED_100FD    0x00000018  // 100BASE-T full duplex
+#define PHY_MR31_SCRDIS         0x00000001  // Scramble Disable
 
 //*****************************************************************************
 //
@@ -553,12 +560,105 @@
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the MAC register offsets in the
-// Ethernet Controller.
+// The following are deprecated defines for the Ethernet MAC register offsets.
 //
 //*****************************************************************************
 #define MAC_O_IS                0x00000000  // Interrupt Status Register
-#define MAC_O_MADD              0x00000028  // Management Address Register
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the MAC_O_IS
+// register.
+//
+//*****************************************************************************
+#define MAC_IS_PHYINT           0x00000040  // PHY Interrupt
+#define MAC_IS_MDINT            0x00000020  // MDI Transaction Complete
+#define MAC_IS_RXER             0x00000010  // RX Error
+#define MAC_IS_FOV              0x00000008  // RX FIFO Overrun
+#define MAC_IS_TXEMP            0x00000004  // TX FIFO Empy
+#define MAC_IS_TXER             0x00000002  // TX Error
+#define MAC_IS_RXINT            0x00000001  // RX Packet Available
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the MAC_O_IA0
+// register.
+//
+//*****************************************************************************
+#define MAC_IA0_MACOCT4         0xFF000000  // 4th Octet of MAC address
+#define MAC_IA0_MACOCT3         0x00FF0000  // 3rd Octet of MAC address
+#define MAC_IA0_MACOCT2         0x0000FF00  // 2nd Octet of MAC address
+#define MAC_IA0_MACOCT1         0x000000FF  // 1st Octet of MAC address
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the MAC_O_IA1
+// register.
+//
+//*****************************************************************************
+#define MAC_IA1_MACOCT6         0x0000FF00  // 6th Octet of MAC address
+#define MAC_IA1_MACOCT5         0x000000FF  // 5th Octet of MAC address
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the MAC_O_THR
+// register.
+//
+//*****************************************************************************
+#define MAC_THR_THRESH          0x0000003F  // Transmit Threshold Value
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the MAC_O_MCTL
+// register.
+//
+//*****************************************************************************
+#define MAC_MCTL_REGADR         0x000000F8  // Address for Next MII Transaction
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the MAC_O_MDV
+// register.
+//
+//*****************************************************************************
+#define MAC_MDV_DIV             0x000000FF  // Clock Divider for MDC for TX
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the MAC_O_MTXD
+// register.
+//
+//*****************************************************************************
+#define MAC_MTXD_MDTX           0x0000FFFF  // Data for Next MII Transaction
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the MAC_O_MRXD
+// register.
+//
+//*****************************************************************************
+#define MAC_MRXD_MDRX           0x0000FFFF  // Data Read from Last MII Trans
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the MAC_O_NP
+// register.
+//
+//*****************************************************************************
+#define MAC_NP_NPR              0x0000003F  // Number of RX Frames in FIFO
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the PHY_MR23
+// register.
+//
+//*****************************************************************************
+#define PHY_MR23_LED1_TX        0x00000020  // TX Activity
+#define PHY_MR23_LED1_RX        0x00000030  // RX Activity
+#define PHY_MR23_LED1_COL       0x00000040  // Collision
+#define PHY_MR23_LED0_TX        0x00000002  // TX Activity
+#define PHY_MR23_LED0_RX        0x00000003  // RX Activity
+#define PHY_MR23_LED0_COL       0x00000004  // Collision
 
 //*****************************************************************************
 //
@@ -583,101 +683,6 @@
 #define MAC_RV_IACK             0x00000000
 #define MAC_RV_MADD             0x00000000
 
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the MAC_IS
-// register.
-//
-//*****************************************************************************
-#define MAC_IS_PHYINT           0x00000040  // PHY Interrupt
-#define MAC_IS_MDINT            0x00000020  // MDI Transaction Complete
-#define MAC_IS_RXER             0x00000010  // RX Error
-#define MAC_IS_FOV              0x00000008  // RX FIFO Overrun
-#define MAC_IS_TXEMP            0x00000004  // TX FIFO Empy
-#define MAC_IS_TXER             0x00000002  // TX Error
-#define MAC_IS_RXINT            0x00000001  // RX Packet Available
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the MAC_IA0
-// register.
-//
-//*****************************************************************************
-#define MAC_IA0_MACOCT4         0xFF000000  // 4th Octet of MAC address
-#define MAC_IA0_MACOCT3         0x00FF0000  // 3rd Octet of MAC address
-#define MAC_IA0_MACOCT2         0x0000FF00  // 2nd Octet of MAC address
-#define MAC_IA0_MACOCT1         0x000000FF  // 1st Octet of MAC address
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the MAC_IA1
-// register.
-//
-//*****************************************************************************
-#define MAC_IA1_MACOCT6         0x0000FF00  // 6th Octet of MAC address
-#define MAC_IA1_MACOCT5         0x000000FF  // 5th Octet of MAC address
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the MAC_TXTH
-// register.
-//
-//*****************************************************************************
-#define MAC_THR_THRESH          0x0000003F  // Transmit Threshold Value
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the MAC_MCTL
-// register.
-//
-//*****************************************************************************
-#define MAC_MCTL_REGADR         0x000000F8  // Address for Next MII Transaction
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the MAC_MDV
-// register.
-//
-//*****************************************************************************
-#define MAC_MDV_DIV             0x000000FF  // Clock Divider for MDC for TX
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the MAC_MTXD
-// register.
-//
-//*****************************************************************************
-#define MAC_MTXD_MDTX           0x0000FFFF  // Data for Next MII Transaction
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the MAC_MRXD
-// register.
-//
-//*****************************************************************************
-#define MAC_MRXD_MDRX           0x0000FFFF  // Data Read from Last MII Trans.
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the MAC_NP
-// register.
-//
-//*****************************************************************************
-#define MAC_NP_NPR              0x0000003F  // Number of RX Frames in FIFO
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the PHY_MR23
-// register.
-//
-//*****************************************************************************
-#define PHY_MR23_LED1_TX        0x00000020  // TX Activity
-#define PHY_MR23_LED1_RX        0x00000030  // RX Activity
-#define PHY_MR23_LED1_COL       0x00000040  // Collision
-#define PHY_MR23_LED0_TX        0x00000002  // TX Activity
-#define PHY_MR23_LED0_RX        0x00000003  // RX Activity
-#define PHY_MR23_LED0_COL       0x00000004  // Collision
-
 #endif
 
 #endif // __HW_ETHERNET_H__
diff --git a/src/platform/lm3s/hw_flash.h b/src/platform/lm3s/inc/hw_flash.h
similarity index 58%
rename from src/platform/lm3s/hw_flash.h
rename to src/platform/lm3s/inc/hw_flash.h
index fc60742a..db4e61a7 100755
--- a/src/platform/lm3s/hw_flash.h
+++ b/src/platform/lm3s/inc/hw_flash.h
@@ -2,26 +2,23 @@
 //
 // hw_flash.h - Macros used when accessing the flash controller.
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2011 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4781 of the Stellaris Firmware Development Package.
+// This is part of revision 7611 of the Stellaris Firmware Development Package.
 //
 //*****************************************************************************
 
@@ -33,46 +30,115 @@
 // The following are defines for the FLASH register offsets.
 //
 //*****************************************************************************
-#define FLASH_FMA               0x400FD000  // Memory address register
-#define FLASH_FMD               0x400FD004  // Memory data register
-#define FLASH_FMC               0x400FD008  // Memory control register
-#define FLASH_FCRIS             0x400FD00C  // Raw interrupt status register
-#define FLASH_FCIM              0x400FD010  // Interrupt mask register
-#define FLASH_FCMISC            0x400FD014  // Interrupt status register
+#define FLASH_FMA               0x400FD000  // Flash Memory Address
+#define FLASH_FMD               0x400FD004  // Flash Memory Data
+#define FLASH_FMC               0x400FD008  // Flash Memory Control
+#define FLASH_FCRIS             0x400FD00C  // Flash Controller Raw Interrupt
+                                            // Status
+#define FLASH_FCIM              0x400FD010  // Flash Controller Interrupt Mask
+#define FLASH_FCMISC            0x400FD014  // Flash Controller Masked
+                                            // Interrupt Status and Clear
 #define FLASH_FMC2              0x400FD020  // Flash Memory Control 2
 #define FLASH_FWBVAL            0x400FD030  // Flash Write Buffer Valid
-#define FLASH_FWBN              0x400FD100  // Flash Write Buffer Register n
+#define FLASH_FCTL              0x400FD0F8  // Flash Control
+#define FLASH_FWBN              0x400FD100  // Flash Write Buffer n
 #define FLASH_RMCTL             0x400FE0F0  // ROM Control
-#define FLASH_RMVER             0x400FE0F4  // ROM Version Register
-#define FLASH_FMPRE             0x400FE130  // FLASH read protect register
-#define FLASH_FMPPE             0x400FE134  // FLASH program protect register
-#define FLASH_USECRL            0x400FE140  // uSec reload register
+#define FLASH_FMPRE             0x400FE130  // Flash Memory Protection Read
+                                            // Enable
+#define FLASH_FMPPE             0x400FE134  // Flash Memory Protection Program
+                                            // Enable
+#define FLASH_USECRL            0x400FE140  // USec Reload
 #define FLASH_USERDBG           0x400FE1D0  // User Debug
+#define FLASH_BOOTCFG           0x400FE1D0  // Boot Configuration
 #define FLASH_USERREG0          0x400FE1E0  // User Register 0
 #define FLASH_USERREG1          0x400FE1E4  // User Register 1
 #define FLASH_USERREG2          0x400FE1E8  // User Register 2
 #define FLASH_USERREG3          0x400FE1EC  // User Register 3
-#define FLASH_FMPRE0            0x400FE200  // FLASH read protect register 0
-#define FLASH_FMPRE1            0x400FE204  // FLASH read protect register 1
-#define FLASH_FMPRE2            0x400FE208  // FLASH read protect register 2
-#define FLASH_FMPRE3            0x400FE20C  // FLASH read protect register 3
-#define FLASH_FMPPE0            0x400FE400  // FLASH program protect register 0
-#define FLASH_FMPPE1            0x400FE404  // FLASH program protect register 1
-#define FLASH_FMPPE2            0x400FE408  // FLASH program protect register 2
-#define FLASH_FMPPE3            0x400FE40C  // FLASH program protect register 3
+#define FLASH_FMPRE0            0x400FE200  // Flash Memory Protection Read
+                                            // Enable 0
+#define FLASH_FMPRE1            0x400FE204  // Flash Memory Protection Read
+                                            // Enable 1
+#define FLASH_FMPRE2            0x400FE208  // Flash Memory Protection Read
+                                            // Enable 2
+#define FLASH_FMPRE3            0x400FE20C  // Flash Memory Protection Read
+                                            // Enable 3
+#define FLASH_FMPRE4            0x400FE210  // Flash Memory Protection Read
+                                            // Enable 4
+#define FLASH_FMPRE5            0x400FE214  // Flash Memory Protection Read
+                                            // Enable 5
+#define FLASH_FMPRE6            0x400FE218  // Flash Memory Protection Read
+                                            // Enable 6
+#define FLASH_FMPRE7            0x400FE21C  // Flash Memory Protection Read
+                                            // Enable 7
+#define FLASH_FMPPE0            0x400FE400  // Flash Memory Protection Program
+                                            // Enable 0
+#define FLASH_FMPPE1            0x400FE404  // Flash Memory Protection Program
+                                            // Enable 1
+#define FLASH_FMPPE2            0x400FE408  // Flash Memory Protection Program
+                                            // Enable 2
+#define FLASH_FMPPE3            0x400FE40C  // Flash Memory Protection Program
+                                            // Enable 3
+#define FLASH_FMPPE4            0x400FE410  // Flash Memory Protection Program
+                                            // Enable 4
+#define FLASH_FMPPE5            0x400FE414  // Flash Memory Protection Program
+                                            // Enable 5
+#define FLASH_FMPPE6            0x400FE418  // Flash Memory Protection Program
+                                            // Enable 6
+#define FLASH_FMPPE7            0x400FE41C  // Flash Memory Protection Program
+                                            // Enable 7
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMA register.
+//
+//*****************************************************************************
+#define FLASH_FMA_OFFSET_M      0x0007FFFF  // Address Offset
+#define FLASH_FMA_OFFSET_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMD register.
+//
+//*****************************************************************************
+#define FLASH_FMD_DATA_M        0xFFFFFFFF  // Data Value
+#define FLASH_FMD_DATA_S        0
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the FLASH_FMC register.
 //
 //*****************************************************************************
-#define FLASH_FMC_WRKEY_M       0xFFFF0000  // FLASH write key mask
 #define FLASH_FMC_WRKEY         0xA4420000  // FLASH write key
-#define FLASH_FMC_COMT          0x00000008  // Commit user register
-#define FLASH_FMC_MERASE        0x00000004  // Mass erase FLASH
-#define FLASH_FMC_ERASE         0x00000002  // Erase FLASH page
-#define FLASH_FMC_WRITE         0x00000001  // Write FLASH word
-#define FLASH_FMC_WRKEY_S       16
+#define FLASH_FMC_COMT          0x00000008  // Commit Register Value
+#define FLASH_FMC_MERASE        0x00000004  // Mass Erase Flash Memory
+#define FLASH_FMC_ERASE         0x00000002  // Erase a Page of Flash Memory
+#define FLASH_FMC_WRITE         0x00000001  // Write a Word into Flash Memory
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FCRIS register.
+//
+//*****************************************************************************
+#define FLASH_FCRIS_PRIS        0x00000002  // Programming Raw Interrupt Status
+#define FLASH_FCRIS_ARIS        0x00000001  // Access Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FCIM register.
+//
+//*****************************************************************************
+#define FLASH_FCIM_PMASK        0x00000002  // Programming Interrupt Mask
+#define FLASH_FCIM_AMASK        0x00000001  // Access Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FCMISC register.
+//
+//*****************************************************************************
+#define FLASH_FCMISC_PMISC      0x00000002  // Programming Masked Interrupt
+                                            // Status and Clear
+#define FLASH_FCMISC_AMISC      0x00000001  // Access Masked Interrupt Status
+                                            // and Clear
 
 //*****************************************************************************
 //
@@ -80,34 +146,120 @@
 //
 //*****************************************************************************
 #define FLASH_FMC2_WRKEY        0xA4420000  // FLASH write key
-#define FLASH_FMC2_WRBUF        0x00000001  // Buffered Flash Write.
+#define FLASH_FMC2_WRBUF        0x00000001  // Buffered Flash Memory Write
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the FLASH_FCRIS register.
+// The following are defines for the bit fields in the FLASH_FWBVAL register.
 //
 //*****************************************************************************
-#define FLASH_FCRIS_PRIS        0x00000002  // Programming Raw Interrupt
-                                            // Status.
-#define FLASH_FCRIS_ARIS        0x00000001  // Access Raw Interrupt Status.
+#define FLASH_FWBVAL_FWB_M      0xFFFFFFFF  // Flash Memory Write Buffer
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the FLASH_FCIM register.
+// The following are defines for the bit fields in the FLASH_FCTL register.
 //
 //*****************************************************************************
-#define FLASH_FCIM_PMASK        0x00000002  // Programming Interrupt Mask.
-#define FLASH_FCIM_AMASK        0x00000001  // Access Interrupt Mask.
+#define FLASH_FCTL_USDACK       0x00000002  // User Shut Down Acknowledge
+#define FLASH_FCTL_USDREQ       0x00000001  // User Shut Down Request
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the FLASH_FMIS register.
+// The following are defines for the bit fields in the FLASH_FWBN register.
 //
 //*****************************************************************************
-#define FLASH_FCMISC_PMISC      0x00000002  // Programming Masked Interrupt
-                                            // Status and Clear.
-#define FLASH_FCMISC_AMISC      0x00000001  // Access Masked Interrupt Status
-                                            // and Clear.
+#define FLASH_FWBN_DATA_M       0xFFFFFFFF  // Data
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_RMCTL register.
+//
+//*****************************************************************************
+#define FLASH_RMCTL_BA          0x00000001  // Boot Alias
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USECRL register.
+//
+//*****************************************************************************
+#define FLASH_USECRL_M          0x000000FF  // Microsecond Reload Value
+#define FLASH_USECRL_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERDBG register.
+//
+//*****************************************************************************
+#define FLASH_USERDBG_NW        0x80000000  // User Debug Not Written
+#define FLASH_USERDBG_DATA_M    0x7FFFFFFC  // User Data
+#define FLASH_USERDBG_DBG1      0x00000002  // Debug Control 1
+#define FLASH_USERDBG_DBG0      0x00000001  // Debug Control 0
+#define FLASH_USERDBG_DATA_S    2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_BOOTCFG register.
+//
+//*****************************************************************************
+#define FLASH_BOOTCFG_NW        0x80000000  // Not Written
+#define FLASH_BOOTCFG_PORT_M    0x0000E000  // Boot GPIO Port
+#define FLASH_BOOTCFG_PORT_A    0x00000000  // Port A
+#define FLASH_BOOTCFG_PORT_B    0x00002000  // Port B
+#define FLASH_BOOTCFG_PORT_C    0x00004000  // Port C
+#define FLASH_BOOTCFG_PORT_D    0x00006000  // Port D
+#define FLASH_BOOTCFG_PORT_E    0x00008000  // Port E
+#define FLASH_BOOTCFG_PORT_F    0x0000A000  // Port F
+#define FLASH_BOOTCFG_PORT_G    0x0000C000  // Port G
+#define FLASH_BOOTCFG_PORT_H    0x0000E000  // Port H
+#define FLASH_BOOTCFG_PIN_M     0x00001C00  // Boot GPIO Pin
+#define FLASH_BOOTCFG_PIN_0     0x00000000  // Pin 0
+#define FLASH_BOOTCFG_PIN_1     0x00000400  // Pin 1
+#define FLASH_BOOTCFG_PIN_2     0x00000800  // Pin 2
+#define FLASH_BOOTCFG_PIN_3     0x00000C00  // Pin 3
+#define FLASH_BOOTCFG_PIN_4     0x00001000  // Pin 4
+#define FLASH_BOOTCFG_PIN_5     0x00001400  // Pin 5
+#define FLASH_BOOTCFG_PIN_6     0x00001800  // Pin 6
+#define FLASH_BOOTCFG_PIN_7     0x00001C00  // Pin 7
+#define FLASH_BOOTCFG_POL       0x00000200  // Boot GPIO Polarity
+#define FLASH_BOOTCFG_EN        0x00000100  // Boot GPIO Enable
+#define FLASH_BOOTCFG_DBG1      0x00000002  // Debug Control 1
+#define FLASH_BOOTCFG_DBG0      0x00000001  // Debug Control 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG0 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG0_NW       0x80000000  // Not Written
+#define FLASH_USERREG0_DATA_M   0x7FFFFFFF  // User Data
+#define FLASH_USERREG0_DATA_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG1 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG1_NW       0x80000000  // Not Written
+#define FLASH_USERREG1_DATA_M   0x7FFFFFFF  // User Data
+#define FLASH_USERREG1_DATA_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG2 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG2_NW       0x80000000  // Not Written
+#define FLASH_USERREG2_DATA_M   0x7FFFFFFF  // User Data
+#define FLASH_USERREG2_DATA_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG3 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG3_NW       0x80000000  // Not Written
+#define FLASH_USERREG3_DATA_M   0x7FFFFFFF  // User Data
+#define FLASH_USERREG3_DATA_S   0
 
 //*****************************************************************************
 //
@@ -148,14 +300,6 @@
 #define FLASH_FMP_BLOCK_1       0x00000002  // Enable for block 1
 #define FLASH_FMP_BLOCK_0       0x00000001  // Enable for block 0
 
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the FLASH_USECRL register.
-//
-//*****************************************************************************
-#define FLASH_USECRL_M          0x000000FF  // Microsecond Reload Value.
-#define FLASH_USECRL_S          0
-
 //*****************************************************************************
 //
 // The following are defines for the erase size of the FLASH block that is
@@ -166,112 +310,6 @@
 #define FLASH_PROTECT_SIZE      0x00000800
 #define FLASH_ERASE_SIZE        0x00000400
 
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the FLASH_FMA register.
-//
-//*****************************************************************************
-#define FLASH_FMA_OFFSET_M      0x0003FFFF  // Address Offset.
-#define FLASH_FMA_OFFSET_S      0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the FLASH_FMD register.
-//
-//*****************************************************************************
-#define FLASH_FMD_DATA_M        0xFFFFFFFF  // Data Value.
-#define FLASH_FMD_DATA_S        0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the FLASH_USERDBG register.
-//
-//*****************************************************************************
-#define FLASH_USERDBG_NW        0x80000000  // User Debug Not Written.
-#define FLASH_USERDBG_DATA_M    0x7FFFFFFC  // User Data.
-#define FLASH_USERDBG_DBG1      0x00000002  // Debug Control 1.
-#define FLASH_USERDBG_DBG0      0x00000001  // Debug Control 0.
-#define FLASH_USERDBG_DATA_S    2
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the FLASH_USERREG0 register.
-//
-//*****************************************************************************
-#define FLASH_USERREG0_NW       0x80000000  // Not Written.
-#define FLASH_USERREG0_DATA_M   0x7FFFFFFF  // User Data.
-#define FLASH_USERREG0_DATA_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the FLASH_USERREG1 register.
-//
-//*****************************************************************************
-#define FLASH_USERREG1_NW       0x80000000  // Not Written.
-#define FLASH_USERREG1_DATA_M   0x7FFFFFFF  // User Data.
-#define FLASH_USERREG1_DATA_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the FLASH_RMCTL register.
-//
-//*****************************************************************************
-#define FLASH_RMCTL_BA          0x00000001  // Boot Alias.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the FLASH_RMVER register.
-//
-//*****************************************************************************
-#define FLASH_RMVER_CONT_M      0xFF000000  // ROM Contents.
-#define FLASH_RMVER_CONT_LM     0x00000000  // Stellaris Boot Loader &
-                                            // DriverLib
-#define FLASH_RMVER_CONT_LM_AES 0x02000000  // Stellaris Boot Loader &
-                                            // DriverLib with AES
-#define FLASH_RMVER_CONT_LM_AES_SAFERTOS \
-                                0x03000000  // Stellaris Boot Loader &
-                                            // DriverLib with AES and SAFERTOS
-#define FLASH_RMVER_SIZE_M      0x00FF0000  // ROM Size.
-#define FLASH_RMVER_SIZE_11K    0x00000000  // 11KB Size
-#define FLASH_RMVER_SIZE_23_75K 0x00020000  // 23.75KB Size
-#define FLASH_RMVER_SIZE_28_25K 0x00030000  // 28.25KB Size
-#define FLASH_RMVER_VER_M       0x0000FF00  // ROM Version.
-#define FLASH_RMVER_REV_M       0x000000FF  // ROM Revision.
-#define FLASH_RMVER_VER_S       8
-#define FLASH_RMVER_REV_S       0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the FLASH_USERREG2 register.
-//
-//*****************************************************************************
-#define FLASH_USERREG2_NW       0x80000000  // Not Written.
-#define FLASH_USERREG2_DATA_M   0x7FFFFFFF  // User Data.
-#define FLASH_USERREG2_DATA_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the FLASH_USERREG3 register.
-//
-//*****************************************************************************
-#define FLASH_USERREG3_NW       0x80000000  // Not Written.
-#define FLASH_USERREG3_DATA_M   0x7FFFFFFF  // User Data.
-#define FLASH_USERREG3_DATA_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the FLASH_FWBVAL register.
-//
-//*****************************************************************************
-#define FLASH_FWBVAL_FWB_M      0xFFFFFFFF  // Flash Write Buffer.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the FLASH_FWBN register.
-//
-//*****************************************************************************
-#define FLASH_FWBN_DATA_M       0xFFFFFFFF  // Data.
-
 //*****************************************************************************
 //
 // The following definitions are deprecated.
@@ -279,6 +317,13 @@
 //*****************************************************************************
 #ifndef DEPRECATED
 
+//*****************************************************************************
+//
+// The following are deprecated defines for the FLASH register offsets.
+//
+//*****************************************************************************
+#define FLASH_RMVER             0x400FE0F4  // ROM Version Register
+
 //*****************************************************************************
 //
 // The following are deprecated defines for the bit fields in the FLASH_FMC
@@ -286,6 +331,8 @@
 //
 //*****************************************************************************
 #define FLASH_FMC_WRKEY_MASK    0xFFFF0000  // FLASH write key mask
+#define FLASH_FMC_WRKEY_M       0xFFFF0000  // Flash Memory Write Key
+#define FLASH_FMC_WRKEY_S       16
 
 //*****************************************************************************
 //
@@ -307,13 +354,35 @@
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the bit fields in the FLASH_FMIS
+// The following are deprecated defines for the bit fields in the FLASH_FCMISC
 // register.
 //
 //*****************************************************************************
 #define FLASH_FCMISC_PROGRAM    0x00000002  // Programming status
 #define FLASH_FCMISC_ACCESS     0x00000001  // Invalid access status
 
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the FLASH_RMVER
+// register.
+//
+//*****************************************************************************
+#define FLASH_RMVER_CONT_M      0xFF000000  // ROM Contents
+#define FLASH_RMVER_CONT_LM     0x00000000  // Stellaris Boot Loader &
+                                            // DriverLib
+#define FLASH_RMVER_CONT_LM_AES 0x02000000  // Stellaris Boot Loader &
+                                            // DriverLib with AES
+#define FLASH_RMVER_CONT_LM_AES_SAFERTOS \
+                                0x03000000  // Stellaris Boot Loader &
+                                            // DriverLib with AES and SAFERTOS
+#define FLASH_RMVER_CONT_LM_AES2 \
+                                0x05000000  // Stellaris Boot Loader &
+                                            // DriverLib with AES
+#define FLASH_RMVER_VER_M       0x0000FF00  // ROM Version
+#define FLASH_RMVER_REV_M       0x000000FF  // ROM Revision
+#define FLASH_RMVER_VER_S       8
+#define FLASH_RMVER_REV_S       0
+
 //*****************************************************************************
 //
 // The following are deprecated defines for the bit fields in the FLASH_USECRL
diff --git a/src/platform/lm3s/hw_gpio.h b/src/platform/lm3s/inc/hw_gpio.h
similarity index 84%
rename from src/platform/lm3s/hw_gpio.h
rename to src/platform/lm3s/inc/hw_gpio.h
index 1047093e..11c706ca 100755
--- a/src/platform/lm3s/hw_gpio.h
+++ b/src/platform/lm3s/inc/hw_gpio.h
@@ -2,26 +2,23 @@
 //
 // hw_gpio.h - Defines and Macros for GPIO hardware.
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2011 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4781 of the Stellaris Firmware Development Package.
+// This is part of revision 7611 of the Stellaris Firmware Development Package.
 //
 //*****************************************************************************
 
@@ -30,44 +27,46 @@
 
 //*****************************************************************************
 //
-// The following are defines for the GPIO Register offsets.
+// The following are defines for the GPIO register offsets.
 //
 //*****************************************************************************
-#define GPIO_O_DATA             0x00000000  // Data register.
-#define GPIO_O_DIR              0x00000400  // Data direction register.
-#define GPIO_O_IS               0x00000404  // Interrupt sense register.
-#define GPIO_O_IBE              0x00000408  // Interrupt both edges register.
-#define GPIO_O_IEV              0x0000040C  // Interrupt event register.
-#define GPIO_O_IM               0x00000410  // Interrupt mask register.
-#define GPIO_O_RIS              0x00000414  // Raw interrupt status register.
-#define GPIO_O_MIS              0x00000418  // Masked interrupt status reg.
-#define GPIO_O_ICR              0x0000041C  // Interrupt clear register.
-#define GPIO_O_AFSEL            0x00000420  // Mode control select register.
-#define GPIO_O_DR2R             0x00000500  // 2ma drive select register.
-#define GPIO_O_DR4R             0x00000504  // 4ma drive select register.
-#define GPIO_O_DR8R             0x00000508  // 8ma drive select register.
-#define GPIO_O_ODR              0x0000050C  // Open drain select register.
-#define GPIO_O_PUR              0x00000510  // Pull up select register.
-#define GPIO_O_PDR              0x00000514  // Pull down select register.
-#define GPIO_O_SLR              0x00000518  // Slew rate control enable reg.
-#define GPIO_O_DEN              0x0000051C  // Digital input enable register.
-#define GPIO_O_LOCK             0x00000520  // Lock register.
-#define GPIO_O_CR               0x00000524  // Commit register.
+#define GPIO_O_DATA             0x00000000  // GPIO Data
+#define GPIO_O_DIR              0x00000400  // GPIO Direction
+#define GPIO_O_IS               0x00000404  // GPIO Interrupt Sense
+#define GPIO_O_IBE              0x00000408  // GPIO Interrupt Both Edges
+#define GPIO_O_IEV              0x0000040C  // GPIO Interrupt Event
+#define GPIO_O_IM               0x00000410  // GPIO Interrupt Mask
+#define GPIO_O_RIS              0x00000414  // GPIO Raw Interrupt Status
+#define GPIO_O_MIS              0x00000418  // GPIO Masked Interrupt Status
+#define GPIO_O_ICR              0x0000041C  // GPIO Interrupt Clear
+#define GPIO_O_AFSEL            0x00000420  // GPIO Alternate Function Select
+#define GPIO_O_DR2R             0x00000500  // GPIO 2-mA Drive Select
+#define GPIO_O_DR4R             0x00000504  // GPIO 4-mA Drive Select
+#define GPIO_O_DR8R             0x00000508  // GPIO 8-mA Drive Select
+#define GPIO_O_ODR              0x0000050C  // GPIO Open Drain Select
+#define GPIO_O_PUR              0x00000510  // GPIO Pull-Up Select
+#define GPIO_O_PDR              0x00000514  // GPIO Pull-Down Select
+#define GPIO_O_SLR              0x00000518  // GPIO Slew Rate Control Select
+#define GPIO_O_DEN              0x0000051C  // GPIO Digital Enable
+#define GPIO_O_LOCK             0x00000520  // GPIO Lock
+#define GPIO_O_CR               0x00000524  // GPIO Commit
 #define GPIO_O_AMSEL            0x00000528  // GPIO Analog Mode Select
 #define GPIO_O_PCTL             0x0000052C  // GPIO Port Control
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the GPIO_LOCK register.
+// The following are defines for the bit fields in the GPIO_O_LOCK register.
 //
 //*****************************************************************************
-#define GPIO_LOCK_M             0xFFFFFFFF  // GPIO Lock.
-#define GPIO_LOCK_UNLOCKED      0x00000000  // GPIO_CR register is unlocked
-#define GPIO_LOCK_LOCKED        0x00000001  // GPIO_CR register is locked
+#define GPIO_LOCK_M             0xFFFFFFFF  // GPIO Lock
+#define GPIO_LOCK_UNLOCKED      0x00000000  // The GPIOCR register is unlocked
+                                            // and may be modified
+#define GPIO_LOCK_LOCKED        0x00000001  // The GPIOCR register is locked
+                                            // and may not be modified
 #define GPIO_LOCK_KEY           0x1ACCE551  // Unlocks the GPIO_CR register
 #define GPIO_LOCK_KEY_DD        0x4C4F434B  // Unlocks the GPIO_CR register on
                                             // DustDevil-class devices and
-                                            // later.
+                                            // later
 
 //*****************************************************************************
 //
@@ -85,26 +84,31 @@
 #define GPIO_PCTL_PA1_U1TX      0x00000090  // U1TX on PA1
 #define GPIO_PCTL_PA2_M         0x00000F00  // PA2 mask
 #define GPIO_PCTL_PA2_SSI0CLK   0x00000100  // SSI0CLK on PA2
+#define GPIO_PCTL_PA2_TXD2      0x00000300  // TXD2 on PA2
 #define GPIO_PCTL_PA2_PWM4      0x00000400  // PWM4 on PA2
 #define GPIO_PCTL_PA2_I2S0RXSD  0x00000900  // I2S0RXSD on PA2
 #define GPIO_PCTL_PA3_M         0x0000F000  // PA3 mask
 #define GPIO_PCTL_PA3_SSI0FSS   0x00001000  // SSI0FSS on PA3
+#define GPIO_PCTL_PA3_TXD1      0x00003000  // TXD1 on PA3
 #define GPIO_PCTL_PA3_PWM5      0x00004000  // PWM5 on PA3
 #define GPIO_PCTL_PA3_I2S0RXMCLK \
                                 0x00009000  // I2S0RXMCLK on PA3
 #define GPIO_PCTL_PA4_M         0x000F0000  // PA4 mask
 #define GPIO_PCTL_PA4_SSI0RX    0x00010000  // SSI0RX on PA4
+#define GPIO_PCTL_PA4_TXD0      0x00030000  // TXD0 on PA4
 #define GPIO_PCTL_PA4_PWM6      0x00040000  // PWM6 on PA4
 #define GPIO_PCTL_PA4_CAN0RX    0x00050000  // CAN0RX on PA4
 #define GPIO_PCTL_PA4_I2S0TXSCK 0x00090000  // I2S0TXSCK on PA4
 #define GPIO_PCTL_PA5_M         0x00F00000  // PA5 mask
 #define GPIO_PCTL_PA5_SSI0TX    0x00100000  // SSI0TX on PA5
+#define GPIO_PCTL_PA5_RXDV      0x00300000  // RXDV on PA5
 #define GPIO_PCTL_PA5_PWM7      0x00400000  // PWM7 on PA5
 #define GPIO_PCTL_PA5_CAN0TX    0x00500000  // CAN0TX on PA5
 #define GPIO_PCTL_PA5_I2S0TXWS  0x00900000  // I2S0TXWS on PA5
 #define GPIO_PCTL_PA6_M         0x0F000000  // PA6 mask
 #define GPIO_PCTL_PA6_I2C1SCL   0x01000000  // I2C1SCL on PA6
 #define GPIO_PCTL_PA6_CCP1      0x02000000  // CCP1 on PA6
+#define GPIO_PCTL_PA6_RXCK      0x03000000  // RXCK on PA6
 #define GPIO_PCTL_PA6_PWM0      0x04000000  // PWM0 on PA6
 #define GPIO_PCTL_PA6_PWM4      0x05000000  // PWM4 on PA6
 #define GPIO_PCTL_PA6_CAN0RX    0x06000000  // CAN0RX on PA6
@@ -113,6 +117,7 @@
 #define GPIO_PCTL_PA7_M         0xF0000000  // PA7 mask
 #define GPIO_PCTL_PA7_I2C1SDA   0x10000000  // I2C1SDA on PA7
 #define GPIO_PCTL_PA7_CCP4      0x20000000  // CCP4 on PA7
+#define GPIO_PCTL_PA7_RXER      0x30000000  // RXER on PA7
 #define GPIO_PCTL_PA7_PWM1      0x40000000  // PWM1 on PA7
 #define GPIO_PCTL_PA7_PWM5      0x50000000  // PWM5 on PA7
 #define GPIO_PCTL_PA7_CAN0TX    0x60000000  // CAN0TX on PA7
@@ -171,6 +176,7 @@
 #define GPIO_PCTL_PB6_I2S0TXSCK 0x09000000  // I2S0TXSCK on PB6
 #define GPIO_PCTL_PB7_M         0xF0000000  // PB7 mask
 #define GPIO_PCTL_PB7_NMI       0x40000000  // NMI on PB7
+#define GPIO_PCTL_PB7_RXD1      0x70000000  // RXD1 on PB7
 
 //*****************************************************************************
 //
@@ -189,6 +195,7 @@
 #define GPIO_PCTL_PC4_M         0x000F0000  // PC4 mask
 #define GPIO_PCTL_PC4_CCP5      0x00010000  // CCP5 on PC4
 #define GPIO_PCTL_PC4_PHA0      0x00020000  // PHA0 on PC4
+#define GPIO_PCTL_PC4_TXD3      0x00030000  // TXD3 on PC4
 #define GPIO_PCTL_PC4_PWM6      0x00040000  // PWM6 on PC4
 #define GPIO_PCTL_PC4_CCP2      0x00050000  // CCP2 on PC4
 #define GPIO_PCTL_PC4_CCP4      0x00060000  // CCP4 on PC4
@@ -233,6 +240,7 @@
 #define GPIO_PCTL_PD0_U2RX      0x00000004  // U2RX on PD0
 #define GPIO_PCTL_PD0_U1RX      0x00000005  // U1RX on PD0
 #define GPIO_PCTL_PD0_CCP6      0x00000006  // CCP6 on PD0
+#define GPIO_PCTL_PD0_RXDV      0x00000007  // RXDV on PD0
 #define GPIO_PCTL_PD0_I2S0RXSCK 0x00000008  // I2S0RXSCK on PD0
 #define GPIO_PCTL_PD0_U1CTS     0x00000009  // U1CTS on PD0
 #define GPIO_PCTL_PD1_M         0x000000F0  // PD1 mask
@@ -242,6 +250,7 @@
 #define GPIO_PCTL_PD1_U2TX      0x00000040  // U2TX on PD1
 #define GPIO_PCTL_PD1_U1TX      0x00000050  // U1TX on PD1
 #define GPIO_PCTL_PD1_CCP7      0x00000060  // CCP7 on PD1
+#define GPIO_PCTL_PD1_TXER      0x00000070  // TXER on PD1
 #define GPIO_PCTL_PD1_I2S0RXWS  0x00000080  // I2S0RXWS on PD1
 #define GPIO_PCTL_PD1_U1DCD     0x00000090  // U1DCD on PD1
 #define GPIO_PCTL_PD1_CCP2      0x000000A0  // CCP2 on PD1
@@ -261,18 +270,21 @@
 #define GPIO_PCTL_PD4_M         0x000F0000  // PD4 mask
 #define GPIO_PCTL_PD4_CCP0      0x00010000  // CCP0 on PD4
 #define GPIO_PCTL_PD4_CCP3      0x00020000  // CCP3 on PD4
+#define GPIO_PCTL_PD4_TXD3      0x00040000  // TXD3 on PD4
 #define GPIO_PCTL_PD4_I2S0RXSD  0x00080000  // I2S0RXSD on PD4
 #define GPIO_PCTL_PD4_U1RI      0x00090000  // U1RI on PD4
 #define GPIO_PCTL_PD4_EPI0S19   0x000A0000  // EPI0S19 on PD4
 #define GPIO_PCTL_PD5_M         0x00F00000  // PD5 mask
 #define GPIO_PCTL_PD5_CCP2      0x00100000  // CCP2 on PD5
 #define GPIO_PCTL_PD5_CCP4      0x00200000  // CCP4 on PD5
+#define GPIO_PCTL_PD5_TXD2      0x00400000  // TXD2 on PD5
 #define GPIO_PCTL_PD5_I2S0RXMCLK \
                                 0x00800000  // I2S0RXMCLK on PD5
 #define GPIO_PCTL_PD5_U2RX      0x00900000  // U2RX on PD5
 #define GPIO_PCTL_PD5_EPI0S28   0x00A00000  // EPI0S28 on PD5
 #define GPIO_PCTL_PD6_M         0x0F000000  // PD6 mask
 #define GPIO_PCTL_PD6_FAULT0    0x01000000  // FAULT0 on PD6
+#define GPIO_PCTL_PD6_TXD1      0x04000000  // TXD1 on PD6
 #define GPIO_PCTL_PD6_I2S0TXSCK 0x08000000  // I2S0TXSCK on PD6
 #define GPIO_PCTL_PD6_U2TX      0x09000000  // U2TX on PD6
 #define GPIO_PCTL_PD6_EPI0S29   0x0A000000  // EPI0S29 on PD6
@@ -280,6 +292,7 @@
 #define GPIO_PCTL_PD7_IDX0      0x10000000  // IDX0 on PD7
 #define GPIO_PCTL_PD7_C0O       0x20000000  // C0O on PD7
 #define GPIO_PCTL_PD7_CCP1      0x30000000  // CCP1 on PD7
+#define GPIO_PCTL_PD7_TXD0      0x40000000  // TXD0 on PD7
 #define GPIO_PCTL_PD7_I2S0TXWS  0x80000000  // I2S0TXWS on PD7
 #define GPIO_PCTL_PD7_U1DTR     0x90000000  // U1DTR on PD7
 #define GPIO_PCTL_PD7_EPI0S30   0xA0000000  // EPI0S30 on PD7
@@ -319,12 +332,15 @@
 #define GPIO_PCTL_PE3_EPI0S25   0x00008000  // EPI0S25 on PE3
 #define GPIO_PCTL_PE4_M         0x000F0000  // PE4 mask
 #define GPIO_PCTL_PE4_CCP3      0x00010000  // CCP3 on PE4
+#define GPIO_PCTL_PE4_CAN2RX    0x00020000  // CAN2RX on PE4
 #define GPIO_PCTL_PE4_FAULT0    0x00040000  // FAULT0 on PE4
 #define GPIO_PCTL_PE4_U2TX      0x00050000  // U2TX on PE4
 #define GPIO_PCTL_PE4_CCP2      0x00060000  // CCP2 on PE4
+#define GPIO_PCTL_PE4_RXD0      0x00070000  // RXD0 on PE4
 #define GPIO_PCTL_PE4_I2S0TXWS  0x00090000  // I2S0TXWS on PE4
 #define GPIO_PCTL_PE5_M         0x00F00000  // PE5 mask
 #define GPIO_PCTL_PE5_CCP5      0x00100000  // CCP5 on PE5
+#define GPIO_PCTL_PE5_CAN2TX    0x00200000  // CAN2TX on PE5
 #define GPIO_PCTL_PE5_I2S0TXSD  0x00900000  // I2S0TXSD on PE5
 #define GPIO_PCTL_PE6_M         0x0F000000  // PE6 mask
 #define GPIO_PCTL_PE6_PWM4      0x01000000  // PWM4 on PE6
@@ -345,12 +361,14 @@
 #define GPIO_PCTL_PF0_CAN1RX    0x00000001  // CAN1RX on PF0
 #define GPIO_PCTL_PF0_PHB0      0x00000002  // PHB0 on PF0
 #define GPIO_PCTL_PF0_PWM0      0x00000003  // PWM0 on PF0
+#define GPIO_PCTL_PF0_RXCK      0x00000004  // RXCK on PF0
 #define GPIO_PCTL_PF0_I2S0TXSD  0x00000008  // I2S0TXSD on PF0
 #define GPIO_PCTL_PF0_U1DSR     0x00000009  // U1DSR on PF0
 #define GPIO_PCTL_PF1_M         0x000000F0  // PF1 mask
 #define GPIO_PCTL_PF1_CAN1TX    0x00000010  // CAN1TX on PF1
 #define GPIO_PCTL_PF1_IDX1      0x00000020  // IDX1 on PF1
 #define GPIO_PCTL_PF1_PWM1      0x00000030  // PWM1 on PF1
+#define GPIO_PCTL_PF1_RXER      0x00000040  // RXER on PF1
 #define GPIO_PCTL_PF1_I2S0TXMCLK \
                                 0x00000080  // I2S0TXMCLK on PF1
 #define GPIO_PCTL_PF1_U1RTS     0x00000090  // U1RTS on PF1
@@ -358,33 +376,39 @@
 #define GPIO_PCTL_PF2_M         0x00000F00  // PF2 mask
 #define GPIO_PCTL_PF2_LED1      0x00000100  // LED1 on PF2
 #define GPIO_PCTL_PF2_PWM4      0x00000200  // PWM4 on PF2
+#define GPIO_PCTL_PF2_PHYINT    0x00000300  // PHYINT on PF2
 #define GPIO_PCTL_PF2_PWM2      0x00000400  // PWM2 on PF2
 #define GPIO_PCTL_PF2_SSI1CLK   0x00000900  // SSI1CLK on PF2
 #define GPIO_PCTL_PF3_M         0x0000F000  // PF3 mask
 #define GPIO_PCTL_PF3_LED0      0x00001000  // LED0 on PF3
 #define GPIO_PCTL_PF3_PWM5      0x00002000  // PWM5 on PF3
+#define GPIO_PCTL_PF3_MDC       0x00003000  // MDC on PF3
 #define GPIO_PCTL_PF3_PWM3      0x00004000  // PWM3 on PF3
 #define GPIO_PCTL_PF3_SSI1FSS   0x00009000  // SSI1FSS on PF3
 #define GPIO_PCTL_PF4_M         0x000F0000  // PF4 mask
 #define GPIO_PCTL_PF4_CCP0      0x00010000  // CCP0 on PF4
 #define GPIO_PCTL_PF4_C0O       0x00020000  // C0O on PF4
+#define GPIO_PCTL_PF4_MDIO      0x00030000  // MDIO on PF4
 #define GPIO_PCTL_PF4_FAULT0    0x00040000  // FAULT0 on PF4
 #define GPIO_PCTL_PF4_EPI0S12   0x00080000  // EPI0S12 on PF4
 #define GPIO_PCTL_PF4_SSI1RX    0x00090000  // SSI1RX on PF4
 #define GPIO_PCTL_PF5_M         0x00F00000  // PF5 mask
 #define GPIO_PCTL_PF5_CCP2      0x00100000  // CCP2 on PF5
 #define GPIO_PCTL_PF5_C1O       0x00200000  // C1O on PF5
+#define GPIO_PCTL_PF5_RXD3      0x00300000  // RXD3 on PF5
 #define GPIO_PCTL_PF5_EPI0S15   0x00800000  // EPI0S15 on PF5
 #define GPIO_PCTL_PF5_SSI1TX    0x00900000  // SSI1TX on PF5
 #define GPIO_PCTL_PF6_M         0x0F000000  // PF6 mask
 #define GPIO_PCTL_PF6_CCP1      0x01000000  // CCP1 on PF6
 #define GPIO_PCTL_PF6_C2O       0x02000000  // C2O on PF6
+#define GPIO_PCTL_PF6_RXD2      0x03000000  // RXD2 on PF6
 #define GPIO_PCTL_PF6_PHA0      0x04000000  // PHA0 on PF6
 #define GPIO_PCTL_PF6_I2S0TXMCLK \
                                 0x09000000  // I2S0TXMCLK on PF6
 #define GPIO_PCTL_PF6_U1RTS     0x0A000000  // U1RTS on PF6
 #define GPIO_PCTL_PF7_M         0xF0000000  // PF7 mask
 #define GPIO_PCTL_PF7_CCP4      0x10000000  // CCP4 on PF7
+#define GPIO_PCTL_PF7_RXD1      0x30000000  // RXD1 on PF7
 #define GPIO_PCTL_PF7_PHB0      0x40000000  // PHB0 on PF7
 #define GPIO_PCTL_PF7_EPI0S12   0x80000000  // EPI0S12 on PF7
 #define GPIO_PCTL_PF7_FAULT1    0x90000000  // FAULT1 on PF7
@@ -410,23 +434,27 @@
 #define GPIO_PCTL_PG1_EPI0S14   0x00000080  // EPI0S14 on PG1
 #define GPIO_PCTL_PG2_M         0x00000F00  // PG2 mask
 #define GPIO_PCTL_PG2_PWM0      0x00000100  // PWM0 on PG2
+#define GPIO_PCTL_PG2_COL       0x00000300  // COL on PG2
 #define GPIO_PCTL_PG2_FAULT0    0x00000400  // FAULT0 on PG2
 #define GPIO_PCTL_PG2_IDX1      0x00000800  // IDX1 on PG2
 #define GPIO_PCTL_PG2_I2S0RXSD  0x00000900  // I2S0RXSD on PG2
 #define GPIO_PCTL_PG3_M         0x0000F000  // PG3 mask
 #define GPIO_PCTL_PG3_PWM1      0x00001000  // PWM1 on PG3
+#define GPIO_PCTL_PG3_CRS       0x00003000  // CRS on PG3
 #define GPIO_PCTL_PG3_FAULT2    0x00004000  // FAULT2 on PG3
 #define GPIO_PCTL_PG3_FAULT0    0x00008000  // FAULT0 on PG3
 #define GPIO_PCTL_PG3_I2S0RXMCLK \
                                 0x00009000  // I2S0RXMCLK on PG3
 #define GPIO_PCTL_PG4_M         0x000F0000  // PG4 mask
 #define GPIO_PCTL_PG4_CCP3      0x00010000  // CCP3 on PG4
+#define GPIO_PCTL_PG4_RXD0      0x00030000  // RXD0 on PG4
 #define GPIO_PCTL_PG4_FAULT1    0x00040000  // FAULT1 on PG4
 #define GPIO_PCTL_PG4_EPI0S15   0x00080000  // EPI0S15 on PG4
 #define GPIO_PCTL_PG4_PWM6      0x00090000  // PWM6 on PG4
 #define GPIO_PCTL_PG4_U1RI      0x000A0000  // U1RI on PG4
 #define GPIO_PCTL_PG5_M         0x00F00000  // PG5 mask
 #define GPIO_PCTL_PG5_CCP5      0x00100000  // CCP5 on PG5
+#define GPIO_PCTL_PG5_TXEN      0x00300000  // TXEN on PG5
 #define GPIO_PCTL_PG5_IDX0      0x00400000  // IDX0 on PG5
 #define GPIO_PCTL_PG5_FAULT1    0x00500000  // FAULT1 on PG5
 #define GPIO_PCTL_PG5_PWM7      0x00800000  // PWM7 on PG5
@@ -434,12 +462,14 @@
 #define GPIO_PCTL_PG5_U1DTR     0x00A00000  // U1DTR on PG5
 #define GPIO_PCTL_PG6_M         0x0F000000  // PG6 mask
 #define GPIO_PCTL_PG6_PHA1      0x01000000  // PHA1 on PG6
+#define GPIO_PCTL_PG6_TXCK      0x03000000  // TXCK on PG6
 #define GPIO_PCTL_PG6_PWM6      0x04000000  // PWM6 on PG6
 #define GPIO_PCTL_PG6_FAULT1    0x08000000  // FAULT1 on PG6
 #define GPIO_PCTL_PG6_I2S0RXWS  0x09000000  // I2S0RXWS on PG6
 #define GPIO_PCTL_PG6_U1RI      0x0A000000  // U1RI on PG6
 #define GPIO_PCTL_PG7_M         0xF0000000  // PG7 mask
 #define GPIO_PCTL_PG7_PHB1      0x10000000  // PHB1 on PG7
+#define GPIO_PCTL_PG7_TXER      0x30000000  // TXER on PG7
 #define GPIO_PCTL_PG7_PWM7      0x40000000  // PWM7 on PG7
 #define GPIO_PCTL_PG7_CCP5      0x80000000  // CCP5 on PG7
 #define GPIO_PCTL_PG7_EPI0S31   0x90000000  // EPI0S31 on PG7
@@ -465,24 +495,30 @@
 #define GPIO_PCTL_PH2_C1O       0x00000200  // C1O on PH2
 #define GPIO_PCTL_PH2_FAULT3    0x00000400  // FAULT3 on PH2
 #define GPIO_PCTL_PH2_EPI0S1    0x00000800  // EPI0S1 on PH2
+#define GPIO_PCTL_PH2_TXD3      0x00000900  // TXD3 on PH2
 #define GPIO_PCTL_PH3_M         0x0000F000  // PH3 mask
 #define GPIO_PCTL_PH3_PHB0      0x00001000  // PHB0 on PH3
 #define GPIO_PCTL_PH3_FAULT0    0x00002000  // FAULT0 on PH3
 #define GPIO_PCTL_PH3_USB0EPEN  0x00004000  // USB0EPEN on PH3
 #define GPIO_PCTL_PH3_EPI0S0    0x00008000  // EPI0S0 on PH3
+#define GPIO_PCTL_PH3_TXD2      0x00009000  // TXD2 on PH3
 #define GPIO_PCTL_PH4_M         0x000F0000  // PH4 mask
 #define GPIO_PCTL_PH4_USB0PFLT  0x00040000  // USB0PFLT on PH4
 #define GPIO_PCTL_PH4_EPI0S10   0x00080000  // EPI0S10 on PH4
+#define GPIO_PCTL_PH4_TXD1      0x00090000  // TXD1 on PH4
 #define GPIO_PCTL_PH4_SSI1CLK   0x000B0000  // SSI1CLK on PH4
 #define GPIO_PCTL_PH5_M         0x00F00000  // PH5 mask
 #define GPIO_PCTL_PH5_EPI0S11   0x00800000  // EPI0S11 on PH5
+#define GPIO_PCTL_PH5_TXD0      0x00900000  // TXD0 on PH5
 #define GPIO_PCTL_PH5_FAULT2    0x00A00000  // FAULT2 on PH5
 #define GPIO_PCTL_PH5_SSI1FSS   0x00B00000  // SSI1FSS on PH5
 #define GPIO_PCTL_PH6_M         0x0F000000  // PH6 mask
 #define GPIO_PCTL_PH6_EPI0S26   0x08000000  // EPI0S26 on PH6
+#define GPIO_PCTL_PH6_RXDV      0x09000000  // RXDV on PH6
 #define GPIO_PCTL_PH6_PWM4      0x0A000000  // PWM4 on PH6
 #define GPIO_PCTL_PH6_SSI1RX    0x0B000000  // SSI1RX on PH6
 #define GPIO_PCTL_PH7_M         0xF0000000  // PH7 mask
+#define GPIO_PCTL_PH7_RXCK      0x30000000  // RXCK on PH7
 #define GPIO_PCTL_PH7_EPI0S27   0x80000000  // EPI0S27 on PH7
 #define GPIO_PCTL_PH7_PWM5      0xA0000000  // PWM5 on PH7
 #define GPIO_PCTL_PH7_SSI1TX    0xB0000000  // SSI1TX on PH7
@@ -494,6 +530,7 @@
 //
 //*****************************************************************************
 #define GPIO_PCTL_PJ0_M         0x0000000F  // PJ0 mask
+#define GPIO_PCTL_PJ0_RXER      0x00000003  // RXER on PJ0
 #define GPIO_PCTL_PJ0_EPI0S16   0x00000008  // EPI0S16 on PJ0
 #define GPIO_PCTL_PJ0_PWM0      0x0000000A  // PWM0 on PJ0
 #define GPIO_PCTL_PJ0_I2C1SCL   0x0000000B  // I2C1SCL on PJ0
@@ -535,7 +572,7 @@
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the GPIO Register offsets.
+// The following are deprecated defines for the GPIO register offsets.
 //
 //*****************************************************************************
 #define GPIO_O_PeriphID4        0x00000FD0
@@ -556,9 +593,9 @@
 // The following are deprecated defines for the GPIO Register reset values.
 //
 //*****************************************************************************
-#define GPIO_RV_DEN             0x000000FF  // Digital input enable reg RV.
-#define GPIO_RV_PUR             0x000000FF  // Pull up select reg RV.
-#define GPIO_RV_DR2R            0x000000FF  // 2ma drive select reg RV.
+#define GPIO_RV_DEN             0x000000FF  // Digital input enable reg RV
+#define GPIO_RV_PUR             0x000000FF  // Pull up select reg RV
+#define GPIO_RV_DR2R            0x000000FF  // 2ma drive select reg RV
 #define GPIO_RV_PCellID1        0x000000F0
 #define GPIO_RV_PCellID3        0x000000B1
 #define GPIO_RV_PeriphID0       0x00000061
@@ -566,27 +603,27 @@
 #define GPIO_RV_PCellID0        0x0000000D
 #define GPIO_RV_PCellID2        0x00000005
 #define GPIO_RV_PeriphID2       0x00000004
-#define GPIO_RV_LOCK            0x00000001  // Lock register RV.
+#define GPIO_RV_LOCK            0x00000001  // Lock register RV
 #define GPIO_RV_PeriphID7       0x00000000
-#define GPIO_RV_PDR             0x00000000  // Pull down select reg RV.
-#define GPIO_RV_IC              0x00000000  // Interrupt clear reg RV.
-#define GPIO_RV_SLR             0x00000000  // Slew rate control enable reg RV.
-#define GPIO_RV_ODR             0x00000000  // Open drain select reg RV.
-#define GPIO_RV_IBE             0x00000000  // Interrupt both edges reg RV.
-#define GPIO_RV_AFSEL           0x00000000  // Mode control select reg RV.
-#define GPIO_RV_IS              0x00000000  // Interrupt sense reg RV.
-#define GPIO_RV_IM              0x00000000  // Interrupt mask reg RV.
+#define GPIO_RV_PDR             0x00000000  // Pull down select reg RV
+#define GPIO_RV_IC              0x00000000  // Interrupt clear reg RV
+#define GPIO_RV_SLR             0x00000000  // Slew rate control enable reg RV
+#define GPIO_RV_ODR             0x00000000  // Open drain select reg RV
+#define GPIO_RV_IBE             0x00000000  // Interrupt both edges reg RV
+#define GPIO_RV_AFSEL           0x00000000  // Mode control select reg RV
+#define GPIO_RV_IS              0x00000000  // Interrupt sense reg RV
+#define GPIO_RV_IM              0x00000000  // Interrupt mask reg RV
 #define GPIO_RV_PeriphID4       0x00000000
 #define GPIO_RV_PeriphID5       0x00000000
-#define GPIO_RV_DR8R            0x00000000  // 8ma drive select reg RV.
-#define GPIO_RV_RIS             0x00000000  // Raw interrupt status reg RV.
-#define GPIO_RV_DR4R            0x00000000  // 4ma drive select reg RV.
-#define GPIO_RV_IEV             0x00000000  // Intterupt event reg RV.
-#define GPIO_RV_DIR             0x00000000  // Data direction reg RV.
+#define GPIO_RV_DR8R            0x00000000  // 8ma drive select reg RV
+#define GPIO_RV_RIS             0x00000000  // Raw interrupt status reg RV
+#define GPIO_RV_DR4R            0x00000000  // 4ma drive select reg RV
+#define GPIO_RV_IEV             0x00000000  // Intterupt event reg RV
+#define GPIO_RV_DIR             0x00000000  // Data direction reg RV
 #define GPIO_RV_PeriphID6       0x00000000
 #define GPIO_RV_PeriphID3       0x00000000
-#define GPIO_RV_DATA            0x00000000  // Data register reset value.
-#define GPIO_RV_MIS             0x00000000  // Masked interrupt status reg RV.
+#define GPIO_RV_DATA            0x00000000  // Data register reset value
+#define GPIO_RV_MIS             0x00000000  // Masked interrupt status reg RV
 
 #endif
 
diff --git a/src/platform/lm3s/hw_hibernate.h b/src/platform/lm3s/inc/hw_hibernate.h
similarity index 51%
rename from src/platform/lm3s/hw_hibernate.h
rename to src/platform/lm3s/inc/hw_hibernate.h
index b49e550c..63c0acaa 100755
--- a/src/platform/lm3s/hw_hibernate.h
+++ b/src/platform/lm3s/inc/hw_hibernate.h
@@ -2,26 +2,23 @@
 //
 // hw_hibernate.h - Defines and Macros for the Hibernation module.
 //
-// Copyright (c) 2007-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2007-2011 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4781 of the Stellaris Firmware Development Package.
+// This is part of revision 7611 of the Stellaris Firmware Development Package.
 //
 //*****************************************************************************
 
@@ -33,132 +30,132 @@
 // The following are defines for the Hibernation module register addresses.
 //
 //*****************************************************************************
-#define HIB_RTCC                0x400FC000  // Hibernate RTC counter
-#define HIB_RTCM0               0x400FC004  // Hibernate RTC match 0
-#define HIB_RTCM1               0x400FC008  // Hibernate RTC match 1
-#define HIB_RTCLD               0x400FC00C  // Hibernate RTC load
-#define HIB_CTL                 0x400FC010  // Hibernate RTC control
-#define HIB_IM                  0x400FC014  // Hibernate interrupt mask
-#define HIB_RIS                 0x400FC018  // Hibernate raw interrupt status
-#define HIB_MIS                 0x400FC01C  // Hibernate masked interrupt stat
-#define HIB_IC                  0x400FC020  // Hibernate interrupt clear
-#define HIB_RTCT                0x400FC024  // Hibernate RTC trim
-#define HIB_DATA                0x400FC030  // Hibernate data area
+#define HIB_RTCC                0x400FC000  // Hibernation RTC Counter
+#define HIB_RTCM0               0x400FC004  // Hibernation RTC Match 0
+#define HIB_RTCM1               0x400FC008  // Hibernation RTC Match 1
+#define HIB_RTCLD               0x400FC00C  // Hibernation RTC Load
+#define HIB_CTL                 0x400FC010  // Hibernation Control
+#define HIB_IM                  0x400FC014  // Hibernation Interrupt Mask
+#define HIB_RIS                 0x400FC018  // Hibernation Raw Interrupt Status
+#define HIB_MIS                 0x400FC01C  // Hibernation Masked Interrupt
+                                            // Status
+#define HIB_IC                  0x400FC020  // Hibernation Interrupt Clear
+#define HIB_RTCT                0x400FC024  // Hibernation RTC Trim
+#define HIB_DATA                0x400FC030  // Hibernation Data
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the Hibernate RTC counter
-// register.
+// The following are defines for the bit fields in the HIB_RTCC register.
 //
 //*****************************************************************************
-#define HIB_RTCC_M              0xFFFFFFFF  // RTC Counter.
+#define HIB_RTCC_M              0xFFFFFFFF  // RTC Counter
 #define HIB_RTCC_S              0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the Hibernate RTC match 0
-// register.
+// The following are defines for the bit fields in the HIB_RTCM0 register.
 //
 //*****************************************************************************
-#define HIB_RTCM0_M             0xFFFFFFFF  // RTC Match 0.
+#define HIB_RTCM0_M             0xFFFFFFFF  // RTC Match 0
 #define HIB_RTCM0_S             0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the Hibernate RTC match 1
-// register.
+// The following are defines for the bit fields in the HIB_RTCM1 register.
 //
 //*****************************************************************************
-#define HIB_RTCM1_M             0xFFFFFFFF  // RTC Match 1.
+#define HIB_RTCM1_M             0xFFFFFFFF  // RTC Match 1
 #define HIB_RTCM1_S             0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the Hibernate RTC load
-// register.
+// The following are defines for the bit fields in the HIB_RTCLD register.
 //
 //*****************************************************************************
-#define HIB_RTCLD_M             0xFFFFFFFF  // RTC Load.
+#define HIB_RTCLD_M             0xFFFFFFFF  // RTC Load
 #define HIB_RTCLD_S             0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the Hibernate control
-// register
+// The following are defines for the bit fields in the HIB_CTL register.
 //
 //*****************************************************************************
-#define HIB_CTL_WRC             0x80000000  // Write Complete/Capable.
-#define HIB_CTL_VDD3ON          0x00000100  // VDD Powered.
-#define HIB_CTL_VABORT          0x00000080  // low bat abort
-#define HIB_CTL_CLK32EN         0x00000040  // enable clock/oscillator
-#define HIB_CTL_LOWBATEN        0x00000020  // enable low battery detect
-#define HIB_CTL_PINWEN          0x00000010  // enable wake on WAKE pin
-#define HIB_CTL_RTCWEN          0x00000008  // enable wake on RTC match
-#define HIB_CTL_CLKSEL          0x00000004  // clock input selection
-#define HIB_CTL_HIBREQ          0x00000002  // request hibernation
-#define HIB_CTL_RTCEN           0x00000001  // RTC enable
+#define HIB_CTL_WRC             0x80000000  // Write Complete/Capable
+#define HIB_CTL_VDD3ON          0x00000100  // VDD Powered
+#define HIB_CTL_VABORT          0x00000080  // Power Cut Abort Enable
+#define HIB_CTL_CLK32EN         0x00000040  // Clocking Enable
+#define HIB_CTL_LOWBATEN        0x00000020  // Low Battery Monitoring Enable
+#define HIB_CTL_PINWEN          0x00000010  // External WAKE Pin Enable
+#define HIB_CTL_RTCWEN          0x00000008  // RTC Wake-up Enable
+#define HIB_CTL_CLKSEL          0x00000004  // Hibernation Module Clock Select
+#define HIB_CTL_HIBREQ          0x00000002  // Hibernation Request
+#define HIB_CTL_RTCEN           0x00000001  // RTC Timer Enable
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the Hibernate interrupt mask
-// reg.
+// The following are defines for the bit fields in the HIB_IM register.
 //
 //*****************************************************************************
-#define HIB_IM_EXTW             0x00000008  // wake from external pin interrupt
-#define HIB_IM_LOWBAT           0x00000004  // low battery interrupt
-#define HIB_IM_RTCALT1          0x00000002  // RTC match 1 interrupt
-#define HIB_IM_RTCALT0          0x00000001  // RTC match 0 interrupt
+#define HIB_IM_EXTW             0x00000008  // External Wake-Up Interrupt Mask
+#define HIB_IM_LOWBAT           0x00000004  // Low Battery Voltage Interrupt
+                                            // Mask
+#define HIB_IM_RTCALT1          0x00000002  // RTC Alert 1 Interrupt Mask
+#define HIB_IM_RTCALT0          0x00000001  // RTC Alert 0 Interrupt Mask
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the Hibernate raw interrupt
-// status.
+// The following are defines for the bit fields in the HIB_RIS register.
 //
 //*****************************************************************************
-#define HIB_RIS_EXTW            0x00000008  // wake from external pin interrupt
-#define HIB_RIS_LOWBAT          0x00000004  // low battery interrupt
-#define HIB_RIS_RTCALT1         0x00000002  // RTC match 1 interrupt
-#define HIB_RIS_RTCALT0         0x00000001  // RTC Alert0 Raw Interrupt Status.
+#define HIB_RIS_EXTW            0x00000008  // External Wake-Up Raw Interrupt
+                                            // Status
+#define HIB_RIS_LOWBAT          0x00000004  // Low Battery Voltage Raw
+                                            // Interrupt Status
+#define HIB_RIS_RTCALT1         0x00000002  // RTC Alert 1 Raw Interrupt Status
+#define HIB_RIS_RTCALT0         0x00000001  // RTC Alert 0 Raw Interrupt Status
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the Hibernate masked int
-// status.
+// The following are defines for the bit fields in the HIB_MIS register.
 //
 //*****************************************************************************
-#define HIB_MIS_EXTW            0x00000008  // wake from external pin interrupt
-#define HIB_MIS_LOWBAT          0x00000004  // low battery interrupt
-#define HIB_MIS_RTCALT1         0x00000002  // RTC match 1 interrupt
-#define HIB_MIS_RTCALT0         0x00000001  // RTC Alert0 Masked Interrupt
-                                            // Status.
+#define HIB_MIS_EXTW            0x00000008  // External Wake-Up Masked
+                                            // Interrupt Status
+#define HIB_MIS_LOWBAT          0x00000004  // Low Battery Voltage Masked
+                                            // Interrupt Status
+#define HIB_MIS_RTCALT1         0x00000002  // RTC Alert 1 Masked Interrupt
+                                            // Status
+#define HIB_MIS_RTCALT0         0x00000001  // RTC Alert 0 Masked Interrupt
+                                            // Status
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the Hibernate interrupt
-// clear reg.
+// The following are defines for the bit fields in the HIB_IC register.
 //
 //*****************************************************************************
-#define HIB_IC_EXTW             0x00000008  // wake from external pin interrupt
-#define HIB_IC_LOWBAT           0x00000004  // low battery interrupt
-#define HIB_IC_RTCALT1          0x00000002  // RTC match 1 interrupt
-#define HIB_IC_RTCALT0          0x00000001  // RTC match 0 interrupt
+#define HIB_IC_EXTW             0x00000008  // External Wake-Up Masked
+                                            // Interrupt Clear
+#define HIB_IC_LOWBAT           0x00000004  // Low Battery Voltage Masked
+                                            // Interrupt Clear
+#define HIB_IC_RTCALT1          0x00000002  // RTC Alert1 Masked Interrupt
+                                            // Clear
+#define HIB_IC_RTCALT0          0x00000001  // RTC Alert0 Masked Interrupt
+                                            // Clear
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the Hibernate RTC trim
-// register.
+// The following are defines for the bit fields in the HIB_RTCT register.
 //
 //*****************************************************************************
-#define HIB_RTCT_TRIM_M         0x0000FFFF  // RTC Trim Value.
+#define HIB_RTCT_TRIM_M         0x0000FFFF  // RTC Trim Value
 #define HIB_RTCT_TRIM_S         0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the Hibernate data register.
+// The following are defines for the bit fields in the HIB_DATA register.
 //
 //*****************************************************************************
-#define HIB_DATA_RTD_M          0xFFFFFFFF  // Hibernation Module NV
-                                            // Registers[63:0].
+#define HIB_DATA_RTD_M          0xFFFFFFFF  // Hibernation Module NV Data
 #define HIB_DATA_RTD_S          0
 
 //*****************************************************************************
@@ -178,64 +175,64 @@
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the bit fields in the Hibernate RTC
-// counter register.
+// The following are deprecated defines for the bit fields in the HIB_RTCC
+// register.
 //
 //*****************************************************************************
 #define HIB_RTCC_MASK           0xFFFFFFFF  // RTC counter mask
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the bit fields in the Hibernate RTC
-// match 0 register.
+// The following are deprecated defines for the bit fields in the HIB_RTCM0
+// register.
 //
 //*****************************************************************************
 #define HIB_RTCM0_MASK          0xFFFFFFFF  // RTC match 0 mask
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the bit fields in the Hibernate RTC
-// match 1 register.
+// The following are deprecated defines for the bit fields in the HIB_RTCM1
+// register.
 //
 //*****************************************************************************
 #define HIB_RTCM1_MASK          0xFFFFFFFF  // RTC match 1 mask
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the bit fields in the Hibernate RTC
-// load register.
+// The following are deprecated defines for the bit fields in the HIB_RTCLD
+// register.
 //
 //*****************************************************************************
 #define HIB_RTCLD_MASK          0xFFFFFFFF  // RTC load mask
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the bit fields in the Hibernate raw
-// interrupt status.
+// The following are deprecated defines for the bit fields in the HIB_RIS
+// register.
 //
 //*****************************************************************************
 #define HIB_RID_RTCALT0         0x00000001  // RTC match 0 interrupt
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the bit fields in the Hibernate
-// masked int status.
+// The following are deprecated defines for the bit fields in the HIB_MIS
+// register.
 //
 //*****************************************************************************
 #define HIB_MID_RTCALT0         0x00000001  // RTC match 0 interrupt
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the bit fields in the Hibernate RTC
-// trim register.
+// The following are deprecated defines for the bit fields in the HIB_RTCT
+// register.
 //
 //*****************************************************************************
 #define HIB_RTCT_MASK           0x0000FFFF  // RTC trim mask
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the bit fields in the Hibernate
-// data register.
+// The following are deprecated defines for the bit fields in the HIB_DATA
+// register.
 //
 //*****************************************************************************
 #define HIB_DATA_MASK           0xFFFFFFFF  // NV memory data mask
diff --git a/src/platform/lm3s/hw_i2c.h b/src/platform/lm3s/inc/hw_i2c.h
similarity index 85%
rename from src/platform/lm3s/hw_i2c.h
rename to src/platform/lm3s/inc/hw_i2c.h
index 5e43e4b1..ecb889dd 100755
--- a/src/platform/lm3s/hw_i2c.h
+++ b/src/platform/lm3s/inc/hw_i2c.h
@@ -2,26 +2,23 @@
 //
 // hw_i2c.h - Macros used when accessing the I2C master and slave hardware.
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2011 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4781 of the Stellaris Firmware Development Package.
+// This is part of revision 7611 of the Stellaris Firmware Development Package.
 //
 //*****************************************************************************
 
@@ -30,8 +27,7 @@
 
 //*****************************************************************************
 //
-// The following are defines for the offsets between the I2C master and slave
-// registers.
+// The following are defines for the I2C register offsets.
 //
 //*****************************************************************************
 #define I2C_O_MSA               0x00000000  // I2C Master Slave Address
@@ -58,8 +54,8 @@
 // The following are defines for the bit fields in the I2C_O_MSA register.
 //
 //*****************************************************************************
-#define I2C_MSA_SA_M            0x000000FE  // I2C Slave Address.
-#define I2C_MSA_RS              0x00000001  // Receive not Send
+#define I2C_MSA_SA_M            0x000000FE  // I2C Slave Address
+#define I2C_MSA_RS              0x00000001  // Receive not send
 #define I2C_MSA_SA_S            1
 
 //*****************************************************************************
@@ -67,7 +63,7 @@
 // The following are defines for the bit fields in the I2C_O_SOAR register.
 //
 //*****************************************************************************
-#define I2C_SOAR_OAR_M          0x0000007F  // I2C Slave Own Address.
+#define I2C_SOAR_OAR_M          0x0000007F  // I2C Slave Own Address
 #define I2C_SOAR_OAR_S          0
 
 //*****************************************************************************
@@ -75,34 +71,34 @@
 // The following are defines for the bit fields in the I2C_O_SCSR register.
 //
 //*****************************************************************************
-#define I2C_SCSR_FBR            0x00000004  // First Byte Received.
-#define I2C_SCSR_TREQ           0x00000002  // Transmit Request.
-#define I2C_SCSR_DA             0x00000001  // Device Active.
-#define I2C_SCSR_RREQ           0x00000001  // Receive Request.
+#define I2C_SCSR_FBR            0x00000004  // First Byte Received
+#define I2C_SCSR_TREQ           0x00000002  // Transmit Request
+#define I2C_SCSR_DA             0x00000001  // Device Active
+#define I2C_SCSR_RREQ           0x00000001  // Receive Request
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2C_O_MCS register.
 //
 //*****************************************************************************
-#define I2C_MCS_BUSBSY          0x00000040  // Bus Busy.
-#define I2C_MCS_IDLE            0x00000020  // I2C Idle.
-#define I2C_MCS_ARBLST          0x00000010  // Arbitration Lost.
-#define I2C_MCS_ACK             0x00000008  // Data Acknowledge Enable.
-#define I2C_MCS_DATACK          0x00000008  // Acknowledge Data.
-#define I2C_MCS_ADRACK          0x00000004  // Acknowledge Address.
-#define I2C_MCS_STOP            0x00000004  // Generate STOP.
-#define I2C_MCS_START           0x00000002  // Generate START.
-#define I2C_MCS_ERROR           0x00000002  // Error.
-#define I2C_MCS_RUN             0x00000001  // I2C Master Enable.
-#define I2C_MCS_BUSY            0x00000001  // I2C Busy.
+#define I2C_MCS_BUSBSY          0x00000040  // Bus Busy
+#define I2C_MCS_IDLE            0x00000020  // I2C Idle
+#define I2C_MCS_ARBLST          0x00000010  // Arbitration Lost
+#define I2C_MCS_ACK             0x00000008  // Data Acknowledge Enable
+#define I2C_MCS_DATACK          0x00000008  // Acknowledge Data
+#define I2C_MCS_ADRACK          0x00000004  // Acknowledge Address
+#define I2C_MCS_STOP            0x00000004  // Generate STOP
+#define I2C_MCS_START           0x00000002  // Generate START
+#define I2C_MCS_ERROR           0x00000002  // Error
+#define I2C_MCS_RUN             0x00000001  // I2C Master Enable
+#define I2C_MCS_BUSY            0x00000001  // I2C Busy
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2C_O_SDR register.
 //
 //*****************************************************************************
-#define I2C_SDR_DATA_M          0x000000FF  // Data for Transfer.
+#define I2C_SDR_DATA_M          0x000000FF  // Data for Transfer
 #define I2C_SDR_DATA_S          0
 
 //*****************************************************************************
@@ -110,7 +106,7 @@
 // The following are defines for the bit fields in the I2C_O_MDR register.
 //
 //*****************************************************************************
-#define I2C_MDR_DATA_M          0x000000FF  // Data Transferred.
+#define I2C_MDR_DATA_M          0x000000FF  // Data Transferred
 #define I2C_MDR_DATA_S          0
 
 //*****************************************************************************
@@ -118,7 +114,7 @@
 // The following are defines for the bit fields in the I2C_O_MTPR register.
 //
 //*****************************************************************************
-#define I2C_MTPR_TPR_M          0x000000FF  // SCL Clock Period.
+#define I2C_MTPR_TPR_M          0x0000007F  // SCL Clock Period
 #define I2C_MTPR_TPR_S          0
 
 //*****************************************************************************
@@ -126,9 +122,9 @@
 // The following are defines for the bit fields in the I2C_O_SIMR register.
 //
 //*****************************************************************************
-#define I2C_SIMR_STOPIM         0x00000004  // Stop Condition Interrupt Mask.
-#define I2C_SIMR_STARTIM        0x00000002  // Start Condition Interrupt Mask.
-#define I2C_SIMR_DATAIM         0x00000001  // Data Interrupt Mask.
+#define I2C_SIMR_STOPIM         0x00000004  // Stop Condition Interrupt Mask
+#define I2C_SIMR_STARTIM        0x00000002  // Start Condition Interrupt Mask
+#define I2C_SIMR_DATAIM         0x00000001  // Data Interrupt Mask
 
 //*****************************************************************************
 //
@@ -136,24 +132,24 @@
 //
 //*****************************************************************************
 #define I2C_SRIS_STOPRIS        0x00000004  // Stop Condition Raw Interrupt
-                                            // Status.
+                                            // Status
 #define I2C_SRIS_STARTRIS       0x00000002  // Start Condition Raw Interrupt
-                                            // Status.
-#define I2C_SRIS_DATARIS        0x00000001  // Data Raw Interrupt Status.
+                                            // Status
+#define I2C_SRIS_DATARIS        0x00000001  // Data Raw Interrupt Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2C_O_MIMR register.
 //
 //*****************************************************************************
-#define I2C_MIMR_IM             0x00000001  // Interrupt Mask.
+#define I2C_MIMR_IM             0x00000001  // Interrupt Mask
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2C_O_MRIS register.
 //
 //*****************************************************************************
-#define I2C_MRIS_RIS            0x00000001  // Raw Interrupt Status.
+#define I2C_MRIS_RIS            0x00000001  // Raw Interrupt Status
 
 //*****************************************************************************
 //
@@ -161,42 +157,42 @@
 //
 //*****************************************************************************
 #define I2C_SMIS_STOPMIS        0x00000004  // Stop Condition Masked Interrupt
-                                            // Status.
+                                            // Status
 #define I2C_SMIS_STARTMIS       0x00000002  // Start Condition Masked Interrupt
-                                            // Status.
-#define I2C_SMIS_DATAMIS        0x00000001  // Data Masked Interrupt Status.
+                                            // Status
+#define I2C_SMIS_DATAMIS        0x00000001  // Data Masked Interrupt Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2C_O_SICR register.
 //
 //*****************************************************************************
-#define I2C_SICR_STOPIC         0x00000004  // Stop Condition Interrupt Clear.
-#define I2C_SICR_STARTIC        0x00000002  // Start Condition Interrupt Clear.
-#define I2C_SICR_DATAIC         0x00000001  // Data Clear Interrupt.
+#define I2C_SICR_STOPIC         0x00000004  // Stop Condition Interrupt Clear
+#define I2C_SICR_STARTIC        0x00000002  // Start Condition Interrupt Clear
+#define I2C_SICR_DATAIC         0x00000001  // Data Interrupt Clear
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2C_O_MMIS register.
 //
 //*****************************************************************************
-#define I2C_MMIS_MIS            0x00000001  // Masked Interrupt Status.
+#define I2C_MMIS_MIS            0x00000001  // Masked Interrupt Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2C_O_MICR register.
 //
 //*****************************************************************************
-#define I2C_MICR_IC             0x00000001  // Interrupt Clear.
+#define I2C_MICR_IC             0x00000001  // Interrupt Clear
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2C_O_MCR register.
 //
 //*****************************************************************************
-#define I2C_MCR_SFE             0x00000020  // I2C Slave Function Enable.
-#define I2C_MCR_MFE             0x00000010  // I2C Master Function Enable.
-#define I2C_MCR_LPBK            0x00000001  // I2C Loopback.
+#define I2C_MCR_SFE             0x00000020  // I2C Slave Function Enable
+#define I2C_MCR_MFE             0x00000010  // I2C Master Function Enable
+#define I2C_MCR_LPBK            0x00000001  // I2C Loopback
 
 //*****************************************************************************
 //
@@ -207,12 +203,43 @@
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the offsets between the I2C master
-// and slave registers.
+// The following are deprecated defines for the I2C register offsets.
 //
 //*****************************************************************************
 #define I2C_O_SLAVE             0x00000800  // Offset from master to slave
 
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C_O_SIMR
+// register.
+//
+//*****************************************************************************
+#define I2C_SIMR_IM             0x00000001  // Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C_O_SRIS
+// register.
+//
+//*****************************************************************************
+#define I2C_SRIS_RIS            0x00000001  // Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C_O_SMIS
+// register.
+//
+//*****************************************************************************
+#define I2C_SMIS_MIS            0x00000001  // Masked Interrupt Status
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C_O_SICR
+// register.
+//
+//*****************************************************************************
+#define I2C_SICR_IC             0x00000001  // Clear Interrupt
+
 //*****************************************************************************
 //
 // The following are deprecated defines for the I2C master register offsets.
@@ -375,38 +402,6 @@
 //*****************************************************************************
 #define I2C_SLAVE_SICR_IC       0x00000001  // Slave interrupt clear
 
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the I2C_O_SIMR
-// register.
-//
-//*****************************************************************************
-#define I2C_SIMR_IM             0x00000001  // Interrupt Mask.
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the I2C_O_SRIS
-// register.
-//
-//*****************************************************************************
-#define I2C_SRIS_RIS            0x00000001  // Raw Interrupt Status.
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the I2C_O_SMIS
-// register.
-//
-//*****************************************************************************
-#define I2C_SMIS_MIS            0x00000001  // Masked Interrupt Status.
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the I2C_O_SICR
-// register.
-//
-//*****************************************************************************
-#define I2C_SICR_IC             0x00000001  // Clear Interrupt.
-
 #endif
 
 #endif // __HW_I2C_H__
diff --git a/src/platform/lm3s/hw_i2s.h b/src/platform/lm3s/inc/hw_i2s.h
similarity index 74%
rename from src/platform/lm3s/hw_i2s.h
rename to src/platform/lm3s/inc/hw_i2s.h
index 5443226a..07513b3c 100755
--- a/src/platform/lm3s/hw_i2s.h
+++ b/src/platform/lm3s/inc/hw_i2s.h
@@ -2,26 +2,23 @@
 //
 // hw_i2s.h - Macros for use in accessing the I2S registers.
 //
-// Copyright (c) 2008-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2008-2011 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4781 of the Stellaris Firmware Development Package.
+// This is part of revision 7611 of the Stellaris Firmware Development Package.
 //
 //*****************************************************************************
 
@@ -30,8 +27,8 @@
 
 //*****************************************************************************
 //
-// The following are defines for the Inter-Integrated Circuit Sound (I2S)
-// Interface
+// The following are defines for the Inter-Integrated Circuit Sound register
+// offsets.
 //
 //*****************************************************************************
 #define I2S_O_TXFIFO            0x00000000  // I2S Transmit FIFO Data
@@ -60,7 +57,7 @@
 // The following are defines for the bit fields in the I2S_O_TXFIFO register.
 //
 //*****************************************************************************
-#define I2S_TXFIFO_M            0xFFFFFFFF  // TX Data.
+#define I2S_TXFIFO_M            0xFFFFFFFF  // TX Data
 #define I2S_TXFIFO_S            0
 
 //*****************************************************************************
@@ -69,26 +66,26 @@
 // register.
 //
 //*****************************************************************************
-#define I2S_TXFIFOCFG_CSS       0x00000002  // Compact Stereo Sample Size.
-#define I2S_TXFIFOCFG_LRS       0x00000001  // Left-Right Sample Indicator.
+#define I2S_TXFIFOCFG_CSS       0x00000002  // Compact Stereo Sample Size
+#define I2S_TXFIFOCFG_LRS       0x00000001  // Left-Right Sample Indicator
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2S_O_TXCFG register.
 //
 //*****************************************************************************
-#define I2S_TXCFG_JST           0x20000000  // Justification of Output Data.
-#define I2S_TXCFG_DLY           0x10000000  // Data Delay.
-#define I2S_TXCFG_SCP           0x08000000  // SCLK Polarity.
-#define I2S_TXCFG_LRP           0x04000000  // Left/Right Clock Polarity.
-#define I2S_TXCFG_WM_M          0x03000000  // Write Mode.
+#define I2S_TXCFG_JST           0x20000000  // Justification of Output Data
+#define I2S_TXCFG_DLY           0x10000000  // Data Delay
+#define I2S_TXCFG_SCP           0x08000000  // SCLK Polarity
+#define I2S_TXCFG_LRP           0x04000000  // Left/Right Clock Polarity
+#define I2S_TXCFG_WM_M          0x03000000  // Write Mode
 #define I2S_TXCFG_WM_DUAL       0x00000000  // Stereo mode
 #define I2S_TXCFG_WM_COMPACT    0x01000000  // Compact Stereo mode
 #define I2S_TXCFG_WM_MONO       0x02000000  // Mono mode
-#define I2S_TXCFG_FMT           0x00800000  // FIFO Empty.
-#define I2S_TXCFG_MSL           0x00400000  // SCLK Master/Slave.
-#define I2S_TXCFG_SSZ_M         0x0000FC00  // Sample Size.
-#define I2S_TXCFG_SDSZ_M        0x000003F0  // System Data Size.
+#define I2S_TXCFG_FMT           0x00800000  // FIFO Empty
+#define I2S_TXCFG_MSL           0x00400000  // SCLK Master/Slave
+#define I2S_TXCFG_SSZ_M         0x0000FC00  // Sample Size
+#define I2S_TXCFG_SDSZ_M        0x000003F0  // System Data Size
 #define I2S_TXCFG_SSZ_S         10
 #define I2S_TXCFG_SDSZ_S        4
 
@@ -97,7 +94,7 @@
 // The following are defines for the bit fields in the I2S_O_TXLIMIT register.
 //
 //*****************************************************************************
-#define I2S_TXLIMIT_LIMIT_M     0x0000001F  // FIFO Limit.
+#define I2S_TXLIMIT_LIMIT_M     0x0000001F  // FIFO Limit
 #define I2S_TXLIMIT_LIMIT_S     0
 
 //*****************************************************************************
@@ -106,15 +103,15 @@
 //
 //*****************************************************************************
 #define I2S_TXISM_FFI           0x00010000  // Transmit FIFO Service Request
-                                            // Interrupt.
-#define I2S_TXISM_FFM           0x00000001  // FIFO Interrupt Mask.
+                                            // Interrupt
+#define I2S_TXISM_FFM           0x00000001  // FIFO Interrupt Mask
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2S_O_TXLEV register.
 //
 //*****************************************************************************
-#define I2S_TXLEV_LEVEL_M       0x0000001F  // Number of Audio Samples.
+#define I2S_TXLEV_LEVEL_M       0x0000001F  // Number of Audio Samples
 #define I2S_TXLEV_LEVEL_S       0
 
 //*****************************************************************************
@@ -122,7 +119,7 @@
 // The following are defines for the bit fields in the I2S_O_RXFIFO register.
 //
 //*****************************************************************************
-#define I2S_RXFIFO_M            0xFFFFFFFF  // RX Data.
+#define I2S_RXFIFO_M            0xFFFFFFFF  // RX Data
 #define I2S_RXFIFO_S            0
 
 //*****************************************************************************
@@ -131,23 +128,23 @@
 // register.
 //
 //*****************************************************************************
-#define I2S_RXFIFOCFG_FMM       0x00000004  // FIFO Mono Mode.
-#define I2S_RXFIFOCFG_CSS       0x00000002  // Compact Stereo Sample Size.
-#define I2S_RXFIFOCFG_LRS       0x00000001  // Left-Right Sample Indicator.
+#define I2S_RXFIFOCFG_FMM       0x00000004  // FIFO Mono Mode
+#define I2S_RXFIFOCFG_CSS       0x00000002  // Compact Stereo Sample Size
+#define I2S_RXFIFOCFG_LRS       0x00000001  // Left-Right Sample Indicator
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2S_O_RXCFG register.
 //
 //*****************************************************************************
-#define I2S_RXCFG_JST           0x20000000  // Justification of Input Data.
-#define I2S_RXCFG_DLY           0x10000000  // Data Delay.
-#define I2S_RXCFG_SCP           0x08000000  // SCLK Polarity.
-#define I2S_RXCFG_LRP           0x04000000  // Left/Right Clock Polarity.
-#define I2S_RXCFG_RM            0x01000000  // Read Mode.
-#define I2S_RXCFG_MSL           0x00400000  // SCLK Master/Slave.
-#define I2S_RXCFG_SSZ_M         0x0000FC00  // Sample Size.
-#define I2S_RXCFG_SDSZ_M        0x000003F0  // System Data Size.
+#define I2S_RXCFG_JST           0x20000000  // Justification of Input Data
+#define I2S_RXCFG_DLY           0x10000000  // Data Delay
+#define I2S_RXCFG_SCP           0x08000000  // SCLK Polarity
+#define I2S_RXCFG_LRP           0x04000000  // Left/Right Clock Polarity
+#define I2S_RXCFG_RM            0x01000000  // Read Mode
+#define I2S_RXCFG_MSL           0x00400000  // SCLK Master/Slave
+#define I2S_RXCFG_SSZ_M         0x0000FC00  // Sample Size
+#define I2S_RXCFG_SDSZ_M        0x000003F0  // System Data Size
 #define I2S_RXCFG_SSZ_S         10
 #define I2S_RXCFG_SDSZ_S        4
 
@@ -156,7 +153,7 @@
 // The following are defines for the bit fields in the I2S_O_RXLIMIT register.
 //
 //*****************************************************************************
-#define I2S_RXLIMIT_LIMIT_M     0x0000001F  // FIFO Limit.
+#define I2S_RXLIMIT_LIMIT_M     0x0000001F  // FIFO Limit
 #define I2S_RXLIMIT_LIMIT_S     0
 
 //*****************************************************************************
@@ -165,15 +162,15 @@
 //
 //*****************************************************************************
 #define I2S_RXISM_FFI           0x00010000  // Receive FIFO Service Request
-                                            // Interrupt.
-#define I2S_RXISM_FFM           0x00000001  // FIFO Interrupt Mask.
+                                            // Interrupt
+#define I2S_RXISM_FFM           0x00000001  // FIFO Interrupt Mask
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2S_O_RXLEV register.
 //
 //*****************************************************************************
-#define I2S_RXLEV_LEVEL_M       0x0000001F  // Number of Audio Samples.
+#define I2S_RXLEV_LEVEL_M       0x0000001F  // Number of Audio Samples
 #define I2S_RXLEV_LEVEL_S       0
 
 //*****************************************************************************
@@ -181,53 +178,47 @@
 // The following are defines for the bit fields in the I2S_O_CFG register.
 //
 //*****************************************************************************
-#define I2S_CFG_RXSLV           0x00000020  // When clear, this bit configures
-                                            // the receiver to use the
-                                            // externally driven I2S0RXMCLK
-                                            // signal.
-#define I2S_CFG_TXSLV           0x00000010  // When clear, this bit configures
-                                            // the transmitter to use the
-                                            // externally driven I2S0TXMCLK
-                                            // signal.
-#define I2S_CFG_RXEN            0x00000002  // Serial Receive Engine Enable.
-#define I2S_CFG_TXEN            0x00000001  // Serial Transmit Engine Enable.
+#define I2S_CFG_RXSLV           0x00000020  // Use External I2S0RXMCLK
+#define I2S_CFG_TXSLV           0x00000010  // Use External I2S0TXMCLK
+#define I2S_CFG_RXEN            0x00000002  // Serial Receive Engine Enable
+#define I2S_CFG_TXEN            0x00000001  // Serial Transmit Engine Enable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2S_O_IM register.
 //
 //*****************************************************************************
-#define I2S_IM_RXRE             0x00000020  // Receive FIFO Read Error.
-#define I2S_IM_RXFSR            0x00000010  // Receive FIFO Service Request.
-#define I2S_IM_TXWE             0x00000002  // Transmit FIFO Write Error.
-#define I2S_IM_TXFSR            0x00000001  // Transmit FIFO Service Request.
+#define I2S_IM_RXRE             0x00000020  // Receive FIFO Read Error
+#define I2S_IM_RXFSR            0x00000010  // Receive FIFO Service Request
+#define I2S_IM_TXWE             0x00000002  // Transmit FIFO Write Error
+#define I2S_IM_TXFSR            0x00000001  // Transmit FIFO Service Request
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2S_O_RIS register.
 //
 //*****************************************************************************
-#define I2S_RIS_RXRE            0x00000020  // Receive FIFO Read Error.
-#define I2S_RIS_RXFSR           0x00000010  // Receive FIFO Service Request.
-#define I2S_RIS_TXWE            0x00000002  // Transmit FIFO Write Error.
-#define I2S_RIS_TXFSR           0x00000001  // Transmit FIFO Service Request.
+#define I2S_RIS_RXRE            0x00000020  // Receive FIFO Read Error
+#define I2S_RIS_RXFSR           0x00000010  // Receive FIFO Service Request
+#define I2S_RIS_TXWE            0x00000002  // Transmit FIFO Write Error
+#define I2S_RIS_TXFSR           0x00000001  // Transmit FIFO Service Request
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2S_O_MIS register.
 //
 //*****************************************************************************
-#define I2S_MIS_RXRE            0x00000020  // Receive FIFO Read Error.
-#define I2S_MIS_RXFSR           0x00000010  // Receive FIFO Service Request.
-#define I2S_MIS_TXWE            0x00000002  // Transmit FIFO Write Error.
-#define I2S_MIS_TXFSR           0x00000001  // Transmit FIFO Service Request.
+#define I2S_MIS_RXRE            0x00000020  // Receive FIFO Read Error
+#define I2S_MIS_RXFSR           0x00000010  // Receive FIFO Service Request
+#define I2S_MIS_TXWE            0x00000002  // Transmit FIFO Write Error
+#define I2S_MIS_TXFSR           0x00000001  // Transmit FIFO Service Request
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2S_O_IC register.
 //
 //*****************************************************************************
-#define I2S_IC_RXRE             0x00000020  // Receive FIFO Read Error.
-#define I2S_IC_TXWE             0x00000002  // Transmit FIFO Write Error.
+#define I2S_IC_RXRE             0x00000020  // Receive FIFO Read Error
+#define I2S_IC_TXWE             0x00000002  // Transmit FIFO Write Error
 
 #endif // __HW_I2S_H__
diff --git a/src/platform/lm3s/hw_ints.h b/src/platform/lm3s/inc/hw_ints.h
similarity index 83%
rename from src/platform/lm3s/hw_ints.h
rename to src/platform/lm3s/inc/hw_ints.h
index 5df84f0c..ef78acad 100755
--- a/src/platform/lm3s/hw_ints.h
+++ b/src/platform/lm3s/inc/hw_ints.h
@@ -2,26 +2,23 @@
 //
 // hw_ints.h - Macros that define the interrupt assignment on Stellaris.
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2011 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4781 of the Stellaris Firmware Development Package.
+// This is part of revision 7611 of the Stellaris Firmware Development Package.
 //
 //*****************************************************************************
 
@@ -62,10 +59,10 @@
 #define INT_PWM1                27          // PWM Generator 1
 #define INT_PWM2                28          // PWM Generator 2
 #define INT_QEI0                29          // Quadrature Encoder 0
-#define INT_ADC0                30          // ADC Sequence 0
-#define INT_ADC1                31          // ADC Sequence 1
-#define INT_ADC2                32          // ADC Sequence 2
-#define INT_ADC3                33          // ADC Sequence 3
+#define INT_ADC0SS0             30          // ADC0 Sequence 0
+#define INT_ADC0SS1             31          // ADC0 Sequence 1
+#define INT_ADC0SS2             32          // ADC0 Sequence 2
+#define INT_ADC0SS3             33          // ADC0 Sequence 3
 #define INT_WATCHDOG            34          // Watchdog timer
 #define INT_TIMER0A             35          // Timer 0 subtimer A
 #define INT_TIMER0B             36          // Timer 0 subtimer B
@@ -109,7 +106,7 @@
 // The following are defines for the total number of interrupts.
 //
 //*****************************************************************************
-#define NUM_INTERRUPTS          70
+#define NUM_INTERRUPTS          71
 
 //*****************************************************************************
 //
@@ -134,6 +131,10 @@
 #define INT_SSI                 23          // SSI Rx and Tx
 #define INT_I2C                 24          // I2C Master and Slave
 #define INT_QEI                 29          // Quadrature Encoder
+#define INT_ADC0                30          // ADC Sequence 0
+#define INT_ADC1                31          // ADC Sequence 1
+#define INT_ADC2                32          // ADC Sequence 2
+#define INT_ADC3                33          // ADC Sequence 3
 
 #endif
 
diff --git a/src/platform/lm3s/hw_memmap.h b/src/platform/lm3s/inc/hw_memmap.h
similarity index 82%
rename from src/platform/lm3s/hw_memmap.h
rename to src/platform/lm3s/inc/hw_memmap.h
index 2b526378..4eff0e41 100755
--- a/src/platform/lm3s/hw_memmap.h
+++ b/src/platform/lm3s/inc/hw_memmap.h
@@ -2,26 +2,23 @@
 //
 // hw_memmap.h - Macros defining the memory map of Stellaris.
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2011 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4781 of the Stellaris Firmware Development Package.
+// This is part of revision 7611 of the Stellaris Firmware Development Package.
 //
 //*****************************************************************************
 
diff --git a/src/platform/lm3s/hw_nvic.h b/src/platform/lm3s/inc/hw_nvic.h
similarity index 62%
rename from src/platform/lm3s/hw_nvic.h
rename to src/platform/lm3s/inc/hw_nvic.h
index 0fb885e2..030c5994 100755
--- a/src/platform/lm3s/hw_nvic.h
+++ b/src/platform/lm3s/inc/hw_nvic.h
@@ -2,26 +2,23 @@
 //
 // hw_nvic.h - Macros used when accessing the NVIC hardware.
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2011 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4781 of the Stellaris Firmware Development Package.
+// This is part of revision 7611 of the Stellaris Firmware Development Package.
 //
 //*****************************************************************************
 
@@ -33,60 +30,72 @@
 // The following are defines for the NVIC register addresses.
 //
 //*****************************************************************************
-#define NVIC_INT_TYPE           0xE000E004  // Interrupt Controller Type Reg.
-#define NVIC_ST_CTRL            0xE000E010  // SysTick Control and Status Reg.
+#define NVIC_INT_TYPE           0xE000E004  // Interrupt Controller Type Reg
+#define NVIC_ACTLR              0xE000E008  // Auxiliary Control
+#define NVIC_ST_CTRL            0xE000E010  // SysTick Control and Status
+                                            // Register
 #define NVIC_ST_RELOAD          0xE000E014  // SysTick Reload Value Register
 #define NVIC_ST_CURRENT         0xE000E018  // SysTick Current Value Register
-#define NVIC_ST_CAL             0xE000E01C  // SysTick Calibration Value Reg.
-#define NVIC_EN0                0xE000E100  // IRQ 0 to 31 Set Enable Register
-#define NVIC_EN1                0xE000E104  // IRQ 32 to 63 Set Enable Register
-#define NVIC_DIS0               0xE000E180  // IRQ 0 to 31 Clear Enable Reg.
-#define NVIC_DIS1               0xE000E184  // IRQ 32 to 63 Clear Enable Reg.
-#define NVIC_PEND0              0xE000E200  // IRQ 0 to 31 Set Pending Register
-#define NVIC_PEND1              0xE000E204  // IRQ 32 to 63 Set Pending Reg.
-#define NVIC_UNPEND0            0xE000E280  // IRQ 0 to 31 Clear Pending Reg.
-#define NVIC_UNPEND1            0xE000E284  // IRQ 32 to 63 Clear Pending Reg.
-#define NVIC_ACTIVE0            0xE000E300  // IRQ 0 to 31 Active Register
-#define NVIC_ACTIVE1            0xE000E304  // IRQ 32 to 63 Active Register
-#define NVIC_PRI0               0xE000E400  // IRQ 0 to 3 Priority Register
-#define NVIC_PRI1               0xE000E404  // IRQ 4 to 7 Priority Register
-#define NVIC_PRI2               0xE000E408  // IRQ 8 to 11 Priority Register
-#define NVIC_PRI3               0xE000E40C  // IRQ 12 to 15 Priority Register
-#define NVIC_PRI4               0xE000E410  // IRQ 16 to 19 Priority Register
-#define NVIC_PRI5               0xE000E414  // IRQ 20 to 23 Priority Register
-#define NVIC_PRI6               0xE000E418  // IRQ 24 to 27 Priority Register
-#define NVIC_PRI7               0xE000E41C  // IRQ 28 to 31 Priority Register
-#define NVIC_PRI8               0xE000E420  // IRQ 32 to 35 Priority Register
-#define NVIC_PRI9               0xE000E424  // IRQ 36 to 39 Priority Register
-#define NVIC_PRI10              0xE000E428  // IRQ 40 to 43 Priority Register
-#define NVIC_PRI11              0xE000E42C  // IRQ 44 to 47 Priority Register
-#define NVIC_PRI12              0xE000E430  // IRQ 48 to 51 Priority Register
-#define NVIC_PRI13              0xE000E434  // IRQ 52 to 55 Priority Register
-#define NVIC_CPUID              0xE000ED00  // CPUID Base Register
-#define NVIC_INT_CTRL           0xE000ED04  // Interrupt Control State Register
-#define NVIC_VTABLE             0xE000ED08  // Vector Table Offset Register
-#define NVIC_APINT              0xE000ED0C  // App. Int & Reset Control Reg.
-#define NVIC_SYS_CTRL           0xE000ED10  // System Control Register
-#define NVIC_CFG_CTRL           0xE000ED14  // Configuration Control Register
-#define NVIC_SYS_PRI1           0xE000ED18  // Sys. Handlers 4 to 7 Priority
-#define NVIC_SYS_PRI2           0xE000ED1C  // Sys. Handlers 8 to 11 Priority
-#define NVIC_SYS_PRI3           0xE000ED20  // Sys. Handlers 12 to 15 Priority
+#define NVIC_ST_CAL             0xE000E01C  // SysTick Calibration Value Reg
+#define NVIC_EN0                0xE000E100  // Interrupt 0-31 Set Enable
+#define NVIC_EN1                0xE000E104  // Interrupt 32-54 Set Enable
+#define NVIC_DIS0               0xE000E180  // Interrupt 0-31 Clear Enable
+#define NVIC_DIS1               0xE000E184  // Interrupt 32-54 Clear Enable
+#define NVIC_PEND0              0xE000E200  // Interrupt 0-31 Set Pending
+#define NVIC_PEND1              0xE000E204  // Interrupt 32-54 Set Pending
+#define NVIC_UNPEND0            0xE000E280  // Interrupt 0-31 Clear Pending
+#define NVIC_UNPEND1            0xE000E284  // Interrupt 32-54 Clear Pending
+#define NVIC_ACTIVE0            0xE000E300  // Interrupt 0-31 Active Bit
+#define NVIC_ACTIVE1            0xE000E304  // Interrupt 32-54 Active Bit
+#define NVIC_PRI0               0xE000E400  // Interrupt 0-3 Priority
+#define NVIC_PRI1               0xE000E404  // Interrupt 4-7 Priority
+#define NVIC_PRI2               0xE000E408  // Interrupt 8-11 Priority
+#define NVIC_PRI3               0xE000E40C  // Interrupt 12-15 Priority
+#define NVIC_PRI4               0xE000E410  // Interrupt 16-19 Priority
+#define NVIC_PRI5               0xE000E414  // Interrupt 20-23 Priority
+#define NVIC_PRI6               0xE000E418  // Interrupt 24-27 Priority
+#define NVIC_PRI7               0xE000E41C  // Interrupt 28-31 Priority
+#define NVIC_PRI8               0xE000E420  // Interrupt 32-35 Priority
+#define NVIC_PRI9               0xE000E424  // Interrupt 36-39 Priority
+#define NVIC_PRI10              0xE000E428  // Interrupt 40-43 Priority
+#define NVIC_PRI11              0xE000E42C  // Interrupt 44-47 Priority
+#define NVIC_PRI12              0xE000E430  // Interrupt 48-51 Priority
+#define NVIC_PRI13              0xE000E434  // Interrupt 52-53 Priority
+#define NVIC_CPUID              0xE000ED00  // CPU ID Base
+#define NVIC_INT_CTRL           0xE000ED04  // Interrupt Control and State
+#define NVIC_VTABLE             0xE000ED08  // Vector Table Offset
+#define NVIC_APINT              0xE000ED0C  // Application Interrupt and Reset
+                                            // Control
+#define NVIC_SYS_CTRL           0xE000ED10  // System Control
+#define NVIC_CFG_CTRL           0xE000ED14  // Configuration and Control
+#define NVIC_SYS_PRI1           0xE000ED18  // System Handler Priority 1
+#define NVIC_SYS_PRI2           0xE000ED1C  // System Handler Priority 2
+#define NVIC_SYS_PRI3           0xE000ED20  // System Handler Priority 3
 #define NVIC_SYS_HND_CTRL       0xE000ED24  // System Handler Control and State
-#define NVIC_FAULT_STAT         0xE000ED28  // Configurable Fault Status Reg.
-#define NVIC_HFAULT_STAT        0xE000ED2C  // Hard Fault Status Register
+#define NVIC_FAULT_STAT         0xE000ED28  // Configurable Fault Status
+#define NVIC_HFAULT_STAT        0xE000ED2C  // Hard Fault Status
 #define NVIC_DEBUG_STAT         0xE000ED30  // Debug Status Register
-#define NVIC_MM_ADDR            0xE000ED34  // Mem Manage Address Register
-#define NVIC_FAULT_ADDR         0xE000ED38  // Bus Fault Address Register
-#define NVIC_MPU_TYPE           0xE000ED90  // MPU Type Register
-#define NVIC_MPU_CTRL           0xE000ED94  // MPU Control Register
-#define NVIC_MPU_NUMBER         0xE000ED98  // MPU Region Number Register
-#define NVIC_MPU_BASE           0xE000ED9C  // MPU Region Base Address Register
-#define NVIC_MPU_ATTR           0xE000EDA0  // MPU Region Attribute & Size Reg.
-#define NVIC_DBG_CTRL           0xE000EDF0  // Debug Control and Status Reg.
+#define NVIC_MM_ADDR            0xE000ED34  // Memory Management Fault Address
+#define NVIC_FAULT_ADDR         0xE000ED38  // Bus Fault Address
+#define NVIC_MPU_TYPE           0xE000ED90  // MPU Type
+#define NVIC_MPU_CTRL           0xE000ED94  // MPU Control
+#define NVIC_MPU_NUMBER         0xE000ED98  // MPU Region Number
+#define NVIC_MPU_BASE           0xE000ED9C  // MPU Region Base Address
+#define NVIC_MPU_ATTR           0xE000EDA0  // MPU Region Attribute and Size
+#define NVIC_MPU_BASE1          0xE000EDA4  // MPU Region Base Address Alias 1
+#define NVIC_MPU_ATTR1          0xE000EDA8  // MPU Region Attribute and Size
+                                            // Alias 1
+#define NVIC_MPU_BASE2          0xE000EDAC  // MPU Region Base Address Alias 2
+#define NVIC_MPU_ATTR2          0xE000EDB0  // MPU Region Attribute and Size
+                                            // Alias 2
+#define NVIC_MPU_BASE3          0xE000EDB4  // MPU Region Base Address Alias 3
+#define NVIC_MPU_ATTR3          0xE000EDB8  // MPU Region Attribute and Size
+                                            // Alias 3
+#define NVIC_DBG_CTRL           0xE000EDF0  // Debug Control and Status Reg
 #define NVIC_DBG_XFER           0xE000EDF4  // Debug Core Reg. Transfer Select
 #define NVIC_DBG_DATA           0xE000EDF8  // Debug Core Register Data
 #define NVIC_DBG_INT            0xE000EDFC  // Debug Reset Interrupt Control
-#define NVIC_SW_TRIG            0xE000EF00  // Software Trigger Interrupt Reg.
+#define NVIC_SW_TRIG            0xE000EF00  // Software Trigger Interrupt
 
 //*****************************************************************************
 //
@@ -96,22 +105,32 @@
 #define NVIC_INT_TYPE_LINES_M   0x0000001F  // Number of interrupt lines (x32)
 #define NVIC_INT_TYPE_LINES_S   0
 
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTLR register.
+//
+//*****************************************************************************
+#define NVIC_ACTLR_DISFOLD      0x00000004  // Disable IT Folding
+#define NVIC_ACTLR_DISWBUF      0x00000002  // Disable Write Buffer
+#define NVIC_ACTLR_DISMCYC      0x00000001  // Disable Interrupts of Multiple
+                                            // Cycle Instructions
+
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_ST_CTRL register.
 //
 //*****************************************************************************
-#define NVIC_ST_CTRL_COUNT      0x00010000  // Count flag
+#define NVIC_ST_CTRL_COUNT      0x00010000  // Count Flag
 #define NVIC_ST_CTRL_CLK_SRC    0x00000004  // Clock Source
-#define NVIC_ST_CTRL_INTEN      0x00000002  // Interrupt enable
-#define NVIC_ST_CTRL_ENABLE     0x00000001  // Counter mode
+#define NVIC_ST_CTRL_INTEN      0x00000002  // Interrupt Enable
+#define NVIC_ST_CTRL_ENABLE     0x00000001  // Enable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_ST_RELOAD register.
 //
 //*****************************************************************************
-#define NVIC_ST_RELOAD_M        0x00FFFFFF  // Counter load value
+#define NVIC_ST_RELOAD_M        0x00FFFFFF  // Reload Value
 #define NVIC_ST_RELOAD_S        0
 
 //*****************************************************************************
@@ -120,7 +139,7 @@
 // register.
 //
 //*****************************************************************************
-#define NVIC_ST_CURRENT_M       0x00FFFFFF  // Counter current value
+#define NVIC_ST_CURRENT_M       0x00FFFFFF  // Current Value
 #define NVIC_ST_CURRENT_S       0
 
 //*****************************************************************************
@@ -138,538 +157,590 @@
 // The following are defines for the bit fields in the NVIC_EN0 register.
 //
 //*****************************************************************************
-#define NVIC_EN0_INT31          0x80000000  // Interrupt 31 enable
-#define NVIC_EN0_INT30          0x40000000  // Interrupt 30 enable
-#define NVIC_EN0_INT29          0x20000000  // Interrupt 29 enable
-#define NVIC_EN0_INT28          0x10000000  // Interrupt 28 enable
-#define NVIC_EN0_INT27          0x08000000  // Interrupt 27 enable
-#define NVIC_EN0_INT26          0x04000000  // Interrupt 26 enable
-#define NVIC_EN0_INT25          0x02000000  // Interrupt 25 enable
-#define NVIC_EN0_INT24          0x01000000  // Interrupt 24 enable
-#define NVIC_EN0_INT23          0x00800000  // Interrupt 23 enable
-#define NVIC_EN0_INT22          0x00400000  // Interrupt 22 enable
-#define NVIC_EN0_INT21          0x00200000  // Interrupt 21 enable
-#define NVIC_EN0_INT20          0x00100000  // Interrupt 20 enable
-#define NVIC_EN0_INT19          0x00080000  // Interrupt 19 enable
-#define NVIC_EN0_INT18          0x00040000  // Interrupt 18 enable
-#define NVIC_EN0_INT17          0x00020000  // Interrupt 17 enable
-#define NVIC_EN0_INT16          0x00010000  // Interrupt 16 enable
-#define NVIC_EN0_INT15          0x00008000  // Interrupt 15 enable
-#define NVIC_EN0_INT14          0x00004000  // Interrupt 14 enable
-#define NVIC_EN0_INT13          0x00002000  // Interrupt 13 enable
-#define NVIC_EN0_INT12          0x00001000  // Interrupt 12 enable
-#define NVIC_EN0_INT11          0x00000800  // Interrupt 11 enable
-#define NVIC_EN0_INT10          0x00000400  // Interrupt 10 enable
-#define NVIC_EN0_INT9           0x00000200  // Interrupt 9 enable
-#define NVIC_EN0_INT8           0x00000100  // Interrupt 8 enable
-#define NVIC_EN0_INT7           0x00000080  // Interrupt 7 enable
-#define NVIC_EN0_INT6           0x00000040  // Interrupt 6 enable
-#define NVIC_EN0_INT5           0x00000020  // Interrupt 5 enable
-#define NVIC_EN0_INT4           0x00000010  // Interrupt 4 enable
-#define NVIC_EN0_INT3           0x00000008  // Interrupt 3 enable
-#define NVIC_EN0_INT2           0x00000004  // Interrupt 2 enable
-#define NVIC_EN0_INT1           0x00000002  // Interrupt 1 enable
+#define NVIC_EN0_INT_M          0xFFFFFFFF  // Interrupt Enable
 #define NVIC_EN0_INT0           0x00000001  // Interrupt 0 enable
+#define NVIC_EN0_INT1           0x00000002  // Interrupt 1 enable
+#define NVIC_EN0_INT2           0x00000004  // Interrupt 2 enable
+#define NVIC_EN0_INT3           0x00000008  // Interrupt 3 enable
+#define NVIC_EN0_INT4           0x00000010  // Interrupt 4 enable
+#define NVIC_EN0_INT5           0x00000020  // Interrupt 5 enable
+#define NVIC_EN0_INT6           0x00000040  // Interrupt 6 enable
+#define NVIC_EN0_INT7           0x00000080  // Interrupt 7 enable
+#define NVIC_EN0_INT8           0x00000100  // Interrupt 8 enable
+#define NVIC_EN0_INT9           0x00000200  // Interrupt 9 enable
+#define NVIC_EN0_INT10          0x00000400  // Interrupt 10 enable
+#define NVIC_EN0_INT11          0x00000800  // Interrupt 11 enable
+#define NVIC_EN0_INT12          0x00001000  // Interrupt 12 enable
+#define NVIC_EN0_INT13          0x00002000  // Interrupt 13 enable
+#define NVIC_EN0_INT14          0x00004000  // Interrupt 14 enable
+#define NVIC_EN0_INT15          0x00008000  // Interrupt 15 enable
+#define NVIC_EN0_INT16          0x00010000  // Interrupt 16 enable
+#define NVIC_EN0_INT17          0x00020000  // Interrupt 17 enable
+#define NVIC_EN0_INT18          0x00040000  // Interrupt 18 enable
+#define NVIC_EN0_INT19          0x00080000  // Interrupt 19 enable
+#define NVIC_EN0_INT20          0x00100000  // Interrupt 20 enable
+#define NVIC_EN0_INT21          0x00200000  // Interrupt 21 enable
+#define NVIC_EN0_INT22          0x00400000  // Interrupt 22 enable
+#define NVIC_EN0_INT23          0x00800000  // Interrupt 23 enable
+#define NVIC_EN0_INT24          0x01000000  // Interrupt 24 enable
+#define NVIC_EN0_INT25          0x02000000  // Interrupt 25 enable
+#define NVIC_EN0_INT26          0x04000000  // Interrupt 26 enable
+#define NVIC_EN0_INT27          0x08000000  // Interrupt 27 enable
+#define NVIC_EN0_INT28          0x10000000  // Interrupt 28 enable
+#define NVIC_EN0_INT29          0x20000000  // Interrupt 29 enable
+#define NVIC_EN0_INT30          0x40000000  // Interrupt 30 enable
+#define NVIC_EN0_INT31          0x80000000  // Interrupt 31 enable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_EN1 register.
 //
 //*****************************************************************************
-#define NVIC_EN1_INT59          0x08000000  // Interrupt 59 enable
-#define NVIC_EN1_INT58          0x04000000  // Interrupt 58 enable
-#define NVIC_EN1_INT57          0x02000000  // Interrupt 57 enable
-#define NVIC_EN1_INT56          0x01000000  // Interrupt 56 enable
-#define NVIC_EN1_INT55          0x00800000  // Interrupt 55 enable
-#define NVIC_EN1_INT54          0x00400000  // Interrupt 54 enable
-#define NVIC_EN1_INT53          0x00200000  // Interrupt 53 enable
-#define NVIC_EN1_INT52          0x00100000  // Interrupt 52 enable
-#define NVIC_EN1_INT51          0x00080000  // Interrupt 51 enable
-#define NVIC_EN1_INT50          0x00040000  // Interrupt 50 enable
-#define NVIC_EN1_INT49          0x00020000  // Interrupt 49 enable
-#define NVIC_EN1_INT48          0x00010000  // Interrupt 48 enable
-#define NVIC_EN1_INT47          0x00008000  // Interrupt 47 enable
-#define NVIC_EN1_INT46          0x00004000  // Interrupt 46 enable
-#define NVIC_EN1_INT45          0x00002000  // Interrupt 45 enable
-#define NVIC_EN1_INT44          0x00001000  // Interrupt 44 enable
-#define NVIC_EN1_INT43          0x00000800  // Interrupt 43 enable
-#define NVIC_EN1_INT42          0x00000400  // Interrupt 42 enable
-#define NVIC_EN1_INT41          0x00000200  // Interrupt 41 enable
-#define NVIC_EN1_INT40          0x00000100  // Interrupt 40 enable
-#define NVIC_EN1_INT39          0x00000080  // Interrupt 39 enable
-#define NVIC_EN1_INT38          0x00000040  // Interrupt 38 enable
-#define NVIC_EN1_INT37          0x00000020  // Interrupt 37 enable
-#define NVIC_EN1_INT36          0x00000010  // Interrupt 36 enable
-#define NVIC_EN1_INT35          0x00000008  // Interrupt 35 enable
-#define NVIC_EN1_INT34          0x00000004  // Interrupt 34 enable
-#define NVIC_EN1_INT33          0x00000002  // Interrupt 33 enable
+#define NVIC_EN1_INT_M          0x007FFFFF  // Interrupt Enable
 #define NVIC_EN1_INT32          0x00000001  // Interrupt 32 enable
+#define NVIC_EN1_INT33          0x00000002  // Interrupt 33 enable
+#define NVIC_EN1_INT34          0x00000004  // Interrupt 34 enable
+#define NVIC_EN1_INT35          0x00000008  // Interrupt 35 enable
+#define NVIC_EN1_INT36          0x00000010  // Interrupt 36 enable
+#define NVIC_EN1_INT37          0x00000020  // Interrupt 37 enable
+#define NVIC_EN1_INT38          0x00000040  // Interrupt 38 enable
+#define NVIC_EN1_INT39          0x00000080  // Interrupt 39 enable
+#define NVIC_EN1_INT40          0x00000100  // Interrupt 40 enable
+#define NVIC_EN1_INT41          0x00000200  // Interrupt 41 enable
+#define NVIC_EN1_INT42          0x00000400  // Interrupt 42 enable
+#define NVIC_EN1_INT43          0x00000800  // Interrupt 43 enable
+#define NVIC_EN1_INT44          0x00001000  // Interrupt 44 enable
+#define NVIC_EN1_INT45          0x00002000  // Interrupt 45 enable
+#define NVIC_EN1_INT46          0x00004000  // Interrupt 46 enable
+#define NVIC_EN1_INT47          0x00008000  // Interrupt 47 enable
+#define NVIC_EN1_INT48          0x00010000  // Interrupt 48 enable
+#define NVIC_EN1_INT49          0x00020000  // Interrupt 49 enable
+#define NVIC_EN1_INT50          0x00040000  // Interrupt 50 enable
+#define NVIC_EN1_INT51          0x00080000  // Interrupt 51 enable
+#define NVIC_EN1_INT52          0x00100000  // Interrupt 52 enable
+#define NVIC_EN1_INT53          0x00200000  // Interrupt 53 enable
+#define NVIC_EN1_INT54          0x00400000  // Interrupt 54 enable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_DIS0 register.
 //
 //*****************************************************************************
-#define NVIC_DIS0_INT31         0x80000000  // Interrupt 31 disable
-#define NVIC_DIS0_INT30         0x40000000  // Interrupt 30 disable
-#define NVIC_DIS0_INT29         0x20000000  // Interrupt 29 disable
-#define NVIC_DIS0_INT28         0x10000000  // Interrupt 28 disable
-#define NVIC_DIS0_INT27         0x08000000  // Interrupt 27 disable
-#define NVIC_DIS0_INT26         0x04000000  // Interrupt 26 disable
-#define NVIC_DIS0_INT25         0x02000000  // Interrupt 25 disable
-#define NVIC_DIS0_INT24         0x01000000  // Interrupt 24 disable
-#define NVIC_DIS0_INT23         0x00800000  // Interrupt 23 disable
-#define NVIC_DIS0_INT22         0x00400000  // Interrupt 22 disable
-#define NVIC_DIS0_INT21         0x00200000  // Interrupt 21 disable
-#define NVIC_DIS0_INT20         0x00100000  // Interrupt 20 disable
-#define NVIC_DIS0_INT19         0x00080000  // Interrupt 19 disable
-#define NVIC_DIS0_INT18         0x00040000  // Interrupt 18 disable
-#define NVIC_DIS0_INT17         0x00020000  // Interrupt 17 disable
-#define NVIC_DIS0_INT16         0x00010000  // Interrupt 16 disable
-#define NVIC_DIS0_INT15         0x00008000  // Interrupt 15 disable
-#define NVIC_DIS0_INT14         0x00004000  // Interrupt 14 disable
-#define NVIC_DIS0_INT13         0x00002000  // Interrupt 13 disable
-#define NVIC_DIS0_INT12         0x00001000  // Interrupt 12 disable
-#define NVIC_DIS0_INT11         0x00000800  // Interrupt 11 disable
-#define NVIC_DIS0_INT10         0x00000400  // Interrupt 10 disable
-#define NVIC_DIS0_INT9          0x00000200  // Interrupt 9 disable
-#define NVIC_DIS0_INT8          0x00000100  // Interrupt 8 disable
-#define NVIC_DIS0_INT7          0x00000080  // Interrupt 7 disable
-#define NVIC_DIS0_INT6          0x00000040  // Interrupt 6 disable
-#define NVIC_DIS0_INT5          0x00000020  // Interrupt 5 disable
-#define NVIC_DIS0_INT4          0x00000010  // Interrupt 4 disable
-#define NVIC_DIS0_INT3          0x00000008  // Interrupt 3 disable
-#define NVIC_DIS0_INT2          0x00000004  // Interrupt 2 disable
-#define NVIC_DIS0_INT1          0x00000002  // Interrupt 1 disable
+#define NVIC_DIS0_INT_M         0xFFFFFFFF  // Interrupt Disable
 #define NVIC_DIS0_INT0          0x00000001  // Interrupt 0 disable
+#define NVIC_DIS0_INT1          0x00000002  // Interrupt 1 disable
+#define NVIC_DIS0_INT2          0x00000004  // Interrupt 2 disable
+#define NVIC_DIS0_INT3          0x00000008  // Interrupt 3 disable
+#define NVIC_DIS0_INT4          0x00000010  // Interrupt 4 disable
+#define NVIC_DIS0_INT5          0x00000020  // Interrupt 5 disable
+#define NVIC_DIS0_INT6          0x00000040  // Interrupt 6 disable
+#define NVIC_DIS0_INT7          0x00000080  // Interrupt 7 disable
+#define NVIC_DIS0_INT8          0x00000100  // Interrupt 8 disable
+#define NVIC_DIS0_INT9          0x00000200  // Interrupt 9 disable
+#define NVIC_DIS0_INT10         0x00000400  // Interrupt 10 disable
+#define NVIC_DIS0_INT11         0x00000800  // Interrupt 11 disable
+#define NVIC_DIS0_INT12         0x00001000  // Interrupt 12 disable
+#define NVIC_DIS0_INT13         0x00002000  // Interrupt 13 disable
+#define NVIC_DIS0_INT14         0x00004000  // Interrupt 14 disable
+#define NVIC_DIS0_INT15         0x00008000  // Interrupt 15 disable
+#define NVIC_DIS0_INT16         0x00010000  // Interrupt 16 disable
+#define NVIC_DIS0_INT17         0x00020000  // Interrupt 17 disable
+#define NVIC_DIS0_INT18         0x00040000  // Interrupt 18 disable
+#define NVIC_DIS0_INT19         0x00080000  // Interrupt 19 disable
+#define NVIC_DIS0_INT20         0x00100000  // Interrupt 20 disable
+#define NVIC_DIS0_INT21         0x00200000  // Interrupt 21 disable
+#define NVIC_DIS0_INT22         0x00400000  // Interrupt 22 disable
+#define NVIC_DIS0_INT23         0x00800000  // Interrupt 23 disable
+#define NVIC_DIS0_INT24         0x01000000  // Interrupt 24 disable
+#define NVIC_DIS0_INT25         0x02000000  // Interrupt 25 disable
+#define NVIC_DIS0_INT26         0x04000000  // Interrupt 26 disable
+#define NVIC_DIS0_INT27         0x08000000  // Interrupt 27 disable
+#define NVIC_DIS0_INT28         0x10000000  // Interrupt 28 disable
+#define NVIC_DIS0_INT29         0x20000000  // Interrupt 29 disable
+#define NVIC_DIS0_INT30         0x40000000  // Interrupt 30 disable
+#define NVIC_DIS0_INT31         0x80000000  // Interrupt 31 disable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_DIS1 register.
 //
 //*****************************************************************************
-#define NVIC_DIS1_INT59         0x08000000  // Interrupt 59 disable
-#define NVIC_DIS1_INT58         0x04000000  // Interrupt 58 disable
-#define NVIC_DIS1_INT57         0x02000000  // Interrupt 57 disable
-#define NVIC_DIS1_INT56         0x01000000  // Interrupt 56 disable
-#define NVIC_DIS1_INT55         0x00800000  // Interrupt 55 disable
-#define NVIC_DIS1_INT54         0x00400000  // Interrupt 54 disable
-#define NVIC_DIS1_INT53         0x00200000  // Interrupt 53 disable
-#define NVIC_DIS1_INT52         0x00100000  // Interrupt 52 disable
-#define NVIC_DIS1_INT51         0x00080000  // Interrupt 51 disable
-#define NVIC_DIS1_INT50         0x00040000  // Interrupt 50 disable
-#define NVIC_DIS1_INT49         0x00020000  // Interrupt 49 disable
-#define NVIC_DIS1_INT48         0x00010000  // Interrupt 48 disable
-#define NVIC_DIS1_INT47         0x00008000  // Interrupt 47 disable
-#define NVIC_DIS1_INT46         0x00004000  // Interrupt 46 disable
-#define NVIC_DIS1_INT45         0x00002000  // Interrupt 45 disable
-#define NVIC_DIS1_INT44         0x00001000  // Interrupt 44 disable
-#define NVIC_DIS1_INT43         0x00000800  // Interrupt 43 disable
-#define NVIC_DIS1_INT42         0x00000400  // Interrupt 42 disable
-#define NVIC_DIS1_INT41         0x00000200  // Interrupt 41 disable
-#define NVIC_DIS1_INT40         0x00000100  // Interrupt 40 disable
-#define NVIC_DIS1_INT39         0x00000080  // Interrupt 39 disable
-#define NVIC_DIS1_INT38         0x00000040  // Interrupt 38 disable
-#define NVIC_DIS1_INT37         0x00000020  // Interrupt 37 disable
-#define NVIC_DIS1_INT36         0x00000010  // Interrupt 36 disable
-#define NVIC_DIS1_INT35         0x00000008  // Interrupt 35 disable
-#define NVIC_DIS1_INT34         0x00000004  // Interrupt 34 disable
-#define NVIC_DIS1_INT33         0x00000002  // Interrupt 33 disable
+#define NVIC_DIS1_INT_M         0x00FFFFFF  // Interrupt Disable
 #define NVIC_DIS1_INT32         0x00000001  // Interrupt 32 disable
+#define NVIC_DIS1_INT33         0x00000002  // Interrupt 33 disable
+#define NVIC_DIS1_INT34         0x00000004  // Interrupt 34 disable
+#define NVIC_DIS1_INT35         0x00000008  // Interrupt 35 disable
+#define NVIC_DIS1_INT36         0x00000010  // Interrupt 36 disable
+#define NVIC_DIS1_INT37         0x00000020  // Interrupt 37 disable
+#define NVIC_DIS1_INT38         0x00000040  // Interrupt 38 disable
+#define NVIC_DIS1_INT39         0x00000080  // Interrupt 39 disable
+#define NVIC_DIS1_INT40         0x00000100  // Interrupt 40 disable
+#define NVIC_DIS1_INT41         0x00000200  // Interrupt 41 disable
+#define NVIC_DIS1_INT42         0x00000400  // Interrupt 42 disable
+#define NVIC_DIS1_INT43         0x00000800  // Interrupt 43 disable
+#define NVIC_DIS1_INT44         0x00001000  // Interrupt 44 disable
+#define NVIC_DIS1_INT45         0x00002000  // Interrupt 45 disable
+#define NVIC_DIS1_INT46         0x00004000  // Interrupt 46 disable
+#define NVIC_DIS1_INT47         0x00008000  // Interrupt 47 disable
+#define NVIC_DIS1_INT48         0x00010000  // Interrupt 48 disable
+#define NVIC_DIS1_INT49         0x00020000  // Interrupt 49 disable
+#define NVIC_DIS1_INT50         0x00040000  // Interrupt 50 disable
+#define NVIC_DIS1_INT51         0x00080000  // Interrupt 51 disable
+#define NVIC_DIS1_INT52         0x00100000  // Interrupt 52 disable
+#define NVIC_DIS1_INT53         0x00200000  // Interrupt 53 disable
+#define NVIC_DIS1_INT54         0x00400000  // Interrupt 54 disable
+#define NVIC_DIS1_INT55         0x00800000  // Interrupt 55 disable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_PEND0 register.
 //
 //*****************************************************************************
-#define NVIC_PEND0_INT31        0x80000000  // Interrupt 31 pend
-#define NVIC_PEND0_INT30        0x40000000  // Interrupt 30 pend
-#define NVIC_PEND0_INT29        0x20000000  // Interrupt 29 pend
-#define NVIC_PEND0_INT28        0x10000000  // Interrupt 28 pend
-#define NVIC_PEND0_INT27        0x08000000  // Interrupt 27 pend
-#define NVIC_PEND0_INT26        0x04000000  // Interrupt 26 pend
-#define NVIC_PEND0_INT25        0x02000000  // Interrupt 25 pend
-#define NVIC_PEND0_INT24        0x01000000  // Interrupt 24 pend
-#define NVIC_PEND0_INT23        0x00800000  // Interrupt 23 pend
-#define NVIC_PEND0_INT22        0x00400000  // Interrupt 22 pend
-#define NVIC_PEND0_INT21        0x00200000  // Interrupt 21 pend
-#define NVIC_PEND0_INT20        0x00100000  // Interrupt 20 pend
-#define NVIC_PEND0_INT19        0x00080000  // Interrupt 19 pend
-#define NVIC_PEND0_INT18        0x00040000  // Interrupt 18 pend
-#define NVIC_PEND0_INT17        0x00020000  // Interrupt 17 pend
-#define NVIC_PEND0_INT16        0x00010000  // Interrupt 16 pend
-#define NVIC_PEND0_INT15        0x00008000  // Interrupt 15 pend
-#define NVIC_PEND0_INT14        0x00004000  // Interrupt 14 pend
-#define NVIC_PEND0_INT13        0x00002000  // Interrupt 13 pend
-#define NVIC_PEND0_INT12        0x00001000  // Interrupt 12 pend
-#define NVIC_PEND0_INT11        0x00000800  // Interrupt 11 pend
-#define NVIC_PEND0_INT10        0x00000400  // Interrupt 10 pend
-#define NVIC_PEND0_INT9         0x00000200  // Interrupt 9 pend
-#define NVIC_PEND0_INT8         0x00000100  // Interrupt 8 pend
-#define NVIC_PEND0_INT7         0x00000080  // Interrupt 7 pend
-#define NVIC_PEND0_INT6         0x00000040  // Interrupt 6 pend
-#define NVIC_PEND0_INT5         0x00000020  // Interrupt 5 pend
-#define NVIC_PEND0_INT4         0x00000010  // Interrupt 4 pend
-#define NVIC_PEND0_INT3         0x00000008  // Interrupt 3 pend
-#define NVIC_PEND0_INT2         0x00000004  // Interrupt 2 pend
-#define NVIC_PEND0_INT1         0x00000002  // Interrupt 1 pend
+#define NVIC_PEND0_INT_M        0xFFFFFFFF  // Interrupt Set Pending
 #define NVIC_PEND0_INT0         0x00000001  // Interrupt 0 pend
+#define NVIC_PEND0_INT1         0x00000002  // Interrupt 1 pend
+#define NVIC_PEND0_INT2         0x00000004  // Interrupt 2 pend
+#define NVIC_PEND0_INT3         0x00000008  // Interrupt 3 pend
+#define NVIC_PEND0_INT4         0x00000010  // Interrupt 4 pend
+#define NVIC_PEND0_INT5         0x00000020  // Interrupt 5 pend
+#define NVIC_PEND0_INT6         0x00000040  // Interrupt 6 pend
+#define NVIC_PEND0_INT7         0x00000080  // Interrupt 7 pend
+#define NVIC_PEND0_INT8         0x00000100  // Interrupt 8 pend
+#define NVIC_PEND0_INT9         0x00000200  // Interrupt 9 pend
+#define NVIC_PEND0_INT10        0x00000400  // Interrupt 10 pend
+#define NVIC_PEND0_INT11        0x00000800  // Interrupt 11 pend
+#define NVIC_PEND0_INT12        0x00001000  // Interrupt 12 pend
+#define NVIC_PEND0_INT13        0x00002000  // Interrupt 13 pend
+#define NVIC_PEND0_INT14        0x00004000  // Interrupt 14 pend
+#define NVIC_PEND0_INT15        0x00008000  // Interrupt 15 pend
+#define NVIC_PEND0_INT16        0x00010000  // Interrupt 16 pend
+#define NVIC_PEND0_INT17        0x00020000  // Interrupt 17 pend
+#define NVIC_PEND0_INT18        0x00040000  // Interrupt 18 pend
+#define NVIC_PEND0_INT19        0x00080000  // Interrupt 19 pend
+#define NVIC_PEND0_INT20        0x00100000  // Interrupt 20 pend
+#define NVIC_PEND0_INT21        0x00200000  // Interrupt 21 pend
+#define NVIC_PEND0_INT22        0x00400000  // Interrupt 22 pend
+#define NVIC_PEND0_INT23        0x00800000  // Interrupt 23 pend
+#define NVIC_PEND0_INT24        0x01000000  // Interrupt 24 pend
+#define NVIC_PEND0_INT25        0x02000000  // Interrupt 25 pend
+#define NVIC_PEND0_INT26        0x04000000  // Interrupt 26 pend
+#define NVIC_PEND0_INT27        0x08000000  // Interrupt 27 pend
+#define NVIC_PEND0_INT28        0x10000000  // Interrupt 28 pend
+#define NVIC_PEND0_INT29        0x20000000  // Interrupt 29 pend
+#define NVIC_PEND0_INT30        0x40000000  // Interrupt 30 pend
+#define NVIC_PEND0_INT31        0x80000000  // Interrupt 31 pend
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_PEND1 register.
 //
 //*****************************************************************************
-#define NVIC_PEND1_INT59        0x08000000  // Interrupt 59 pend
-#define NVIC_PEND1_INT58        0x04000000  // Interrupt 58 pend
-#define NVIC_PEND1_INT57        0x02000000  // Interrupt 57 pend
-#define NVIC_PEND1_INT56        0x01000000  // Interrupt 56 pend
-#define NVIC_PEND1_INT55        0x00800000  // Interrupt 55 pend
-#define NVIC_PEND1_INT54        0x00400000  // Interrupt 54 pend
-#define NVIC_PEND1_INT53        0x00200000  // Interrupt 53 pend
-#define NVIC_PEND1_INT52        0x00100000  // Interrupt 52 pend
-#define NVIC_PEND1_INT51        0x00080000  // Interrupt 51 pend
-#define NVIC_PEND1_INT50        0x00040000  // Interrupt 50 pend
-#define NVIC_PEND1_INT49        0x00020000  // Interrupt 49 pend
-#define NVIC_PEND1_INT48        0x00010000  // Interrupt 48 pend
-#define NVIC_PEND1_INT47        0x00008000  // Interrupt 47 pend
-#define NVIC_PEND1_INT46        0x00004000  // Interrupt 46 pend
-#define NVIC_PEND1_INT45        0x00002000  // Interrupt 45 pend
-#define NVIC_PEND1_INT44        0x00001000  // Interrupt 44 pend
-#define NVIC_PEND1_INT43        0x00000800  // Interrupt 43 pend
-#define NVIC_PEND1_INT42        0x00000400  // Interrupt 42 pend
-#define NVIC_PEND1_INT41        0x00000200  // Interrupt 41 pend
-#define NVIC_PEND1_INT40        0x00000100  // Interrupt 40 pend
-#define NVIC_PEND1_INT39        0x00000080  // Interrupt 39 pend
-#define NVIC_PEND1_INT38        0x00000040  // Interrupt 38 pend
-#define NVIC_PEND1_INT37        0x00000020  // Interrupt 37 pend
-#define NVIC_PEND1_INT36        0x00000010  // Interrupt 36 pend
-#define NVIC_PEND1_INT35        0x00000008  // Interrupt 35 pend
-#define NVIC_PEND1_INT34        0x00000004  // Interrupt 34 pend
-#define NVIC_PEND1_INT33        0x00000002  // Interrupt 33 pend
+#define NVIC_PEND1_INT_M        0x00FFFFFF  // Interrupt Set Pending
 #define NVIC_PEND1_INT32        0x00000001  // Interrupt 32 pend
+#define NVIC_PEND1_INT33        0x00000002  // Interrupt 33 pend
+#define NVIC_PEND1_INT34        0x00000004  // Interrupt 34 pend
+#define NVIC_PEND1_INT35        0x00000008  // Interrupt 35 pend
+#define NVIC_PEND1_INT36        0x00000010  // Interrupt 36 pend
+#define NVIC_PEND1_INT37        0x00000020  // Interrupt 37 pend
+#define NVIC_PEND1_INT38        0x00000040  // Interrupt 38 pend
+#define NVIC_PEND1_INT39        0x00000080  // Interrupt 39 pend
+#define NVIC_PEND1_INT40        0x00000100  // Interrupt 40 pend
+#define NVIC_PEND1_INT41        0x00000200  // Interrupt 41 pend
+#define NVIC_PEND1_INT42        0x00000400  // Interrupt 42 pend
+#define NVIC_PEND1_INT43        0x00000800  // Interrupt 43 pend
+#define NVIC_PEND1_INT44        0x00001000  // Interrupt 44 pend
+#define NVIC_PEND1_INT45        0x00002000  // Interrupt 45 pend
+#define NVIC_PEND1_INT46        0x00004000  // Interrupt 46 pend
+#define NVIC_PEND1_INT47        0x00008000  // Interrupt 47 pend
+#define NVIC_PEND1_INT48        0x00010000  // Interrupt 48 pend
+#define NVIC_PEND1_INT49        0x00020000  // Interrupt 49 pend
+#define NVIC_PEND1_INT50        0x00040000  // Interrupt 50 pend
+#define NVIC_PEND1_INT51        0x00080000  // Interrupt 51 pend
+#define NVIC_PEND1_INT52        0x00100000  // Interrupt 52 pend
+#define NVIC_PEND1_INT53        0x00200000  // Interrupt 53 pend
+#define NVIC_PEND1_INT54        0x00400000  // Interrupt 54 pend
+#define NVIC_PEND1_INT55        0x00800000  // Interrupt 55 pend
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_UNPEND0 register.
 //
 //*****************************************************************************
-#define NVIC_UNPEND0_INT31      0x80000000  // Interrupt 31 unpend
-#define NVIC_UNPEND0_INT30      0x40000000  // Interrupt 30 unpend
-#define NVIC_UNPEND0_INT29      0x20000000  // Interrupt 29 unpend
-#define NVIC_UNPEND0_INT28      0x10000000  // Interrupt 28 unpend
-#define NVIC_UNPEND0_INT27      0x08000000  // Interrupt 27 unpend
-#define NVIC_UNPEND0_INT26      0x04000000  // Interrupt 26 unpend
-#define NVIC_UNPEND0_INT25      0x02000000  // Interrupt 25 unpend
-#define NVIC_UNPEND0_INT24      0x01000000  // Interrupt 24 unpend
-#define NVIC_UNPEND0_INT23      0x00800000  // Interrupt 23 unpend
-#define NVIC_UNPEND0_INT22      0x00400000  // Interrupt 22 unpend
-#define NVIC_UNPEND0_INT21      0x00200000  // Interrupt 21 unpend
-#define NVIC_UNPEND0_INT20      0x00100000  // Interrupt 20 unpend
-#define NVIC_UNPEND0_INT19      0x00080000  // Interrupt 19 unpend
-#define NVIC_UNPEND0_INT18      0x00040000  // Interrupt 18 unpend
-#define NVIC_UNPEND0_INT17      0x00020000  // Interrupt 17 unpend
-#define NVIC_UNPEND0_INT16      0x00010000  // Interrupt 16 unpend
-#define NVIC_UNPEND0_INT15      0x00008000  // Interrupt 15 unpend
-#define NVIC_UNPEND0_INT14      0x00004000  // Interrupt 14 unpend
-#define NVIC_UNPEND0_INT13      0x00002000  // Interrupt 13 unpend
-#define NVIC_UNPEND0_INT12      0x00001000  // Interrupt 12 unpend
-#define NVIC_UNPEND0_INT11      0x00000800  // Interrupt 11 unpend
-#define NVIC_UNPEND0_INT10      0x00000400  // Interrupt 10 unpend
-#define NVIC_UNPEND0_INT9       0x00000200  // Interrupt 9 unpend
-#define NVIC_UNPEND0_INT8       0x00000100  // Interrupt 8 unpend
-#define NVIC_UNPEND0_INT7       0x00000080  // Interrupt 7 unpend
-#define NVIC_UNPEND0_INT6       0x00000040  // Interrupt 6 unpend
-#define NVIC_UNPEND0_INT5       0x00000020  // Interrupt 5 unpend
-#define NVIC_UNPEND0_INT4       0x00000010  // Interrupt 4 unpend
-#define NVIC_UNPEND0_INT3       0x00000008  // Interrupt 3 unpend
-#define NVIC_UNPEND0_INT2       0x00000004  // Interrupt 2 unpend
-#define NVIC_UNPEND0_INT1       0x00000002  // Interrupt 1 unpend
+#define NVIC_UNPEND0_INT_M      0xFFFFFFFF  // Interrupt Clear Pending
 #define NVIC_UNPEND0_INT0       0x00000001  // Interrupt 0 unpend
+#define NVIC_UNPEND0_INT1       0x00000002  // Interrupt 1 unpend
+#define NVIC_UNPEND0_INT2       0x00000004  // Interrupt 2 unpend
+#define NVIC_UNPEND0_INT3       0x00000008  // Interrupt 3 unpend
+#define NVIC_UNPEND0_INT4       0x00000010  // Interrupt 4 unpend
+#define NVIC_UNPEND0_INT5       0x00000020  // Interrupt 5 unpend
+#define NVIC_UNPEND0_INT6       0x00000040  // Interrupt 6 unpend
+#define NVIC_UNPEND0_INT7       0x00000080  // Interrupt 7 unpend
+#define NVIC_UNPEND0_INT8       0x00000100  // Interrupt 8 unpend
+#define NVIC_UNPEND0_INT9       0x00000200  // Interrupt 9 unpend
+#define NVIC_UNPEND0_INT10      0x00000400  // Interrupt 10 unpend
+#define NVIC_UNPEND0_INT11      0x00000800  // Interrupt 11 unpend
+#define NVIC_UNPEND0_INT12      0x00001000  // Interrupt 12 unpend
+#define NVIC_UNPEND0_INT13      0x00002000  // Interrupt 13 unpend
+#define NVIC_UNPEND0_INT14      0x00004000  // Interrupt 14 unpend
+#define NVIC_UNPEND0_INT15      0x00008000  // Interrupt 15 unpend
+#define NVIC_UNPEND0_INT16      0x00010000  // Interrupt 16 unpend
+#define NVIC_UNPEND0_INT17      0x00020000  // Interrupt 17 unpend
+#define NVIC_UNPEND0_INT18      0x00040000  // Interrupt 18 unpend
+#define NVIC_UNPEND0_INT19      0x00080000  // Interrupt 19 unpend
+#define NVIC_UNPEND0_INT20      0x00100000  // Interrupt 20 unpend
+#define NVIC_UNPEND0_INT21      0x00200000  // Interrupt 21 unpend
+#define NVIC_UNPEND0_INT22      0x00400000  // Interrupt 22 unpend
+#define NVIC_UNPEND0_INT23      0x00800000  // Interrupt 23 unpend
+#define NVIC_UNPEND0_INT24      0x01000000  // Interrupt 24 unpend
+#define NVIC_UNPEND0_INT25      0x02000000  // Interrupt 25 unpend
+#define NVIC_UNPEND0_INT26      0x04000000  // Interrupt 26 unpend
+#define NVIC_UNPEND0_INT27      0x08000000  // Interrupt 27 unpend
+#define NVIC_UNPEND0_INT28      0x10000000  // Interrupt 28 unpend
+#define NVIC_UNPEND0_INT29      0x20000000  // Interrupt 29 unpend
+#define NVIC_UNPEND0_INT30      0x40000000  // Interrupt 30 unpend
+#define NVIC_UNPEND0_INT31      0x80000000  // Interrupt 31 unpend
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_UNPEND1 register.
 //
 //*****************************************************************************
-#define NVIC_UNPEND1_INT59      0x08000000  // Interrupt 59 unpend
-#define NVIC_UNPEND1_INT58      0x04000000  // Interrupt 58 unpend
-#define NVIC_UNPEND1_INT57      0x02000000  // Interrupt 57 unpend
-#define NVIC_UNPEND1_INT56      0x01000000  // Interrupt 56 unpend
-#define NVIC_UNPEND1_INT55      0x00800000  // Interrupt 55 unpend
-#define NVIC_UNPEND1_INT54      0x00400000  // Interrupt 54 unpend
-#define NVIC_UNPEND1_INT53      0x00200000  // Interrupt 53 unpend
-#define NVIC_UNPEND1_INT52      0x00100000  // Interrupt 52 unpend
-#define NVIC_UNPEND1_INT51      0x00080000  // Interrupt 51 unpend
-#define NVIC_UNPEND1_INT50      0x00040000  // Interrupt 50 unpend
-#define NVIC_UNPEND1_INT49      0x00020000  // Interrupt 49 unpend
-#define NVIC_UNPEND1_INT48      0x00010000  // Interrupt 48 unpend
-#define NVIC_UNPEND1_INT47      0x00008000  // Interrupt 47 unpend
-#define NVIC_UNPEND1_INT46      0x00004000  // Interrupt 46 unpend
-#define NVIC_UNPEND1_INT45      0x00002000  // Interrupt 45 unpend
-#define NVIC_UNPEND1_INT44      0x00001000  // Interrupt 44 unpend
-#define NVIC_UNPEND1_INT43      0x00000800  // Interrupt 43 unpend
-#define NVIC_UNPEND1_INT42      0x00000400  // Interrupt 42 unpend
-#define NVIC_UNPEND1_INT41      0x00000200  // Interrupt 41 unpend
-#define NVIC_UNPEND1_INT40      0x00000100  // Interrupt 40 unpend
-#define NVIC_UNPEND1_INT39      0x00000080  // Interrupt 39 unpend
-#define NVIC_UNPEND1_INT38      0x00000040  // Interrupt 38 unpend
-#define NVIC_UNPEND1_INT37      0x00000020  // Interrupt 37 unpend
-#define NVIC_UNPEND1_INT36      0x00000010  // Interrupt 36 unpend
-#define NVIC_UNPEND1_INT35      0x00000008  // Interrupt 35 unpend
-#define NVIC_UNPEND1_INT34      0x00000004  // Interrupt 34 unpend
-#define NVIC_UNPEND1_INT33      0x00000002  // Interrupt 33 unpend
+#define NVIC_UNPEND1_INT_M      0x00FFFFFF  // Interrupt Clear Pending
 #define NVIC_UNPEND1_INT32      0x00000001  // Interrupt 32 unpend
+#define NVIC_UNPEND1_INT33      0x00000002  // Interrupt 33 unpend
+#define NVIC_UNPEND1_INT34      0x00000004  // Interrupt 34 unpend
+#define NVIC_UNPEND1_INT35      0x00000008  // Interrupt 35 unpend
+#define NVIC_UNPEND1_INT36      0x00000010  // Interrupt 36 unpend
+#define NVIC_UNPEND1_INT37      0x00000020  // Interrupt 37 unpend
+#define NVIC_UNPEND1_INT38      0x00000040  // Interrupt 38 unpend
+#define NVIC_UNPEND1_INT39      0x00000080  // Interrupt 39 unpend
+#define NVIC_UNPEND1_INT40      0x00000100  // Interrupt 40 unpend
+#define NVIC_UNPEND1_INT41      0x00000200  // Interrupt 41 unpend
+#define NVIC_UNPEND1_INT42      0x00000400  // Interrupt 42 unpend
+#define NVIC_UNPEND1_INT43      0x00000800  // Interrupt 43 unpend
+#define NVIC_UNPEND1_INT44      0x00001000  // Interrupt 44 unpend
+#define NVIC_UNPEND1_INT45      0x00002000  // Interrupt 45 unpend
+#define NVIC_UNPEND1_INT46      0x00004000  // Interrupt 46 unpend
+#define NVIC_UNPEND1_INT47      0x00008000  // Interrupt 47 unpend
+#define NVIC_UNPEND1_INT48      0x00010000  // Interrupt 48 unpend
+#define NVIC_UNPEND1_INT49      0x00020000  // Interrupt 49 unpend
+#define NVIC_UNPEND1_INT50      0x00040000  // Interrupt 50 unpend
+#define NVIC_UNPEND1_INT51      0x00080000  // Interrupt 51 unpend
+#define NVIC_UNPEND1_INT52      0x00100000  // Interrupt 52 unpend
+#define NVIC_UNPEND1_INT53      0x00200000  // Interrupt 53 unpend
+#define NVIC_UNPEND1_INT54      0x00400000  // Interrupt 54 unpend
+#define NVIC_UNPEND1_INT55      0x00800000  // Interrupt 55 unpend
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_ACTIVE0 register.
 //
 //*****************************************************************************
-#define NVIC_ACTIVE0_INT31      0x80000000  // Interrupt 31 active
-#define NVIC_ACTIVE0_INT30      0x40000000  // Interrupt 30 active
-#define NVIC_ACTIVE0_INT29      0x20000000  // Interrupt 29 active
-#define NVIC_ACTIVE0_INT28      0x10000000  // Interrupt 28 active
-#define NVIC_ACTIVE0_INT27      0x08000000  // Interrupt 27 active
-#define NVIC_ACTIVE0_INT26      0x04000000  // Interrupt 26 active
-#define NVIC_ACTIVE0_INT25      0x02000000  // Interrupt 25 active
-#define NVIC_ACTIVE0_INT24      0x01000000  // Interrupt 24 active
-#define NVIC_ACTIVE0_INT23      0x00800000  // Interrupt 23 active
-#define NVIC_ACTIVE0_INT22      0x00400000  // Interrupt 22 active
-#define NVIC_ACTIVE0_INT21      0x00200000  // Interrupt 21 active
-#define NVIC_ACTIVE0_INT20      0x00100000  // Interrupt 20 active
-#define NVIC_ACTIVE0_INT19      0x00080000  // Interrupt 19 active
-#define NVIC_ACTIVE0_INT18      0x00040000  // Interrupt 18 active
-#define NVIC_ACTIVE0_INT17      0x00020000  // Interrupt 17 active
-#define NVIC_ACTIVE0_INT16      0x00010000  // Interrupt 16 active
-#define NVIC_ACTIVE0_INT15      0x00008000  // Interrupt 15 active
-#define NVIC_ACTIVE0_INT14      0x00004000  // Interrupt 14 active
-#define NVIC_ACTIVE0_INT13      0x00002000  // Interrupt 13 active
-#define NVIC_ACTIVE0_INT12      0x00001000  // Interrupt 12 active
-#define NVIC_ACTIVE0_INT11      0x00000800  // Interrupt 11 active
-#define NVIC_ACTIVE0_INT10      0x00000400  // Interrupt 10 active
-#define NVIC_ACTIVE0_INT9       0x00000200  // Interrupt 9 active
-#define NVIC_ACTIVE0_INT8       0x00000100  // Interrupt 8 active
-#define NVIC_ACTIVE0_INT7       0x00000080  // Interrupt 7 active
-#define NVIC_ACTIVE0_INT6       0x00000040  // Interrupt 6 active
-#define NVIC_ACTIVE0_INT5       0x00000020  // Interrupt 5 active
-#define NVIC_ACTIVE0_INT4       0x00000010  // Interrupt 4 active
-#define NVIC_ACTIVE0_INT3       0x00000008  // Interrupt 3 active
-#define NVIC_ACTIVE0_INT2       0x00000004  // Interrupt 2 active
-#define NVIC_ACTIVE0_INT1       0x00000002  // Interrupt 1 active
+#define NVIC_ACTIVE0_INT_M      0xFFFFFFFF  // Interrupt Active
 #define NVIC_ACTIVE0_INT0       0x00000001  // Interrupt 0 active
+#define NVIC_ACTIVE0_INT1       0x00000002  // Interrupt 1 active
+#define NVIC_ACTIVE0_INT2       0x00000004  // Interrupt 2 active
+#define NVIC_ACTIVE0_INT3       0x00000008  // Interrupt 3 active
+#define NVIC_ACTIVE0_INT4       0x00000010  // Interrupt 4 active
+#define NVIC_ACTIVE0_INT5       0x00000020  // Interrupt 5 active
+#define NVIC_ACTIVE0_INT6       0x00000040  // Interrupt 6 active
+#define NVIC_ACTIVE0_INT7       0x00000080  // Interrupt 7 active
+#define NVIC_ACTIVE0_INT8       0x00000100  // Interrupt 8 active
+#define NVIC_ACTIVE0_INT9       0x00000200  // Interrupt 9 active
+#define NVIC_ACTIVE0_INT10      0x00000400  // Interrupt 10 active
+#define NVIC_ACTIVE0_INT11      0x00000800  // Interrupt 11 active
+#define NVIC_ACTIVE0_INT12      0x00001000  // Interrupt 12 active
+#define NVIC_ACTIVE0_INT13      0x00002000  // Interrupt 13 active
+#define NVIC_ACTIVE0_INT14      0x00004000  // Interrupt 14 active
+#define NVIC_ACTIVE0_INT15      0x00008000  // Interrupt 15 active
+#define NVIC_ACTIVE0_INT16      0x00010000  // Interrupt 16 active
+#define NVIC_ACTIVE0_INT17      0x00020000  // Interrupt 17 active
+#define NVIC_ACTIVE0_INT18      0x00040000  // Interrupt 18 active
+#define NVIC_ACTIVE0_INT19      0x00080000  // Interrupt 19 active
+#define NVIC_ACTIVE0_INT20      0x00100000  // Interrupt 20 active
+#define NVIC_ACTIVE0_INT21      0x00200000  // Interrupt 21 active
+#define NVIC_ACTIVE0_INT22      0x00400000  // Interrupt 22 active
+#define NVIC_ACTIVE0_INT23      0x00800000  // Interrupt 23 active
+#define NVIC_ACTIVE0_INT24      0x01000000  // Interrupt 24 active
+#define NVIC_ACTIVE0_INT25      0x02000000  // Interrupt 25 active
+#define NVIC_ACTIVE0_INT26      0x04000000  // Interrupt 26 active
+#define NVIC_ACTIVE0_INT27      0x08000000  // Interrupt 27 active
+#define NVIC_ACTIVE0_INT28      0x10000000  // Interrupt 28 active
+#define NVIC_ACTIVE0_INT29      0x20000000  // Interrupt 29 active
+#define NVIC_ACTIVE0_INT30      0x40000000  // Interrupt 30 active
+#define NVIC_ACTIVE0_INT31      0x80000000  // Interrupt 31 active
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_ACTIVE1 register.
 //
 //*****************************************************************************
-#define NVIC_ACTIVE1_INT59      0x08000000  // Interrupt 59 active
-#define NVIC_ACTIVE1_INT58      0x04000000  // Interrupt 58 active
-#define NVIC_ACTIVE1_INT57      0x02000000  // Interrupt 57 active
-#define NVIC_ACTIVE1_INT56      0x01000000  // Interrupt 56 active
-#define NVIC_ACTIVE1_INT55      0x00800000  // Interrupt 55 active
-#define NVIC_ACTIVE1_INT54      0x00400000  // Interrupt 54 active
-#define NVIC_ACTIVE1_INT53      0x00200000  // Interrupt 53 active
-#define NVIC_ACTIVE1_INT52      0x00100000  // Interrupt 52 active
-#define NVIC_ACTIVE1_INT51      0x00080000  // Interrupt 51 active
-#define NVIC_ACTIVE1_INT50      0x00040000  // Interrupt 50 active
-#define NVIC_ACTIVE1_INT49      0x00020000  // Interrupt 49 active
-#define NVIC_ACTIVE1_INT48      0x00010000  // Interrupt 48 active
-#define NVIC_ACTIVE1_INT47      0x00008000  // Interrupt 47 active
-#define NVIC_ACTIVE1_INT46      0x00004000  // Interrupt 46 active
-#define NVIC_ACTIVE1_INT45      0x00002000  // Interrupt 45 active
-#define NVIC_ACTIVE1_INT44      0x00001000  // Interrupt 44 active
-#define NVIC_ACTIVE1_INT43      0x00000800  // Interrupt 43 active
-#define NVIC_ACTIVE1_INT42      0x00000400  // Interrupt 42 active
-#define NVIC_ACTIVE1_INT41      0x00000200  // Interrupt 41 active
-#define NVIC_ACTIVE1_INT40      0x00000100  // Interrupt 40 active
-#define NVIC_ACTIVE1_INT39      0x00000080  // Interrupt 39 active
-#define NVIC_ACTIVE1_INT38      0x00000040  // Interrupt 38 active
-#define NVIC_ACTIVE1_INT37      0x00000020  // Interrupt 37 active
-#define NVIC_ACTIVE1_INT36      0x00000010  // Interrupt 36 active
-#define NVIC_ACTIVE1_INT35      0x00000008  // Interrupt 35 active
-#define NVIC_ACTIVE1_INT34      0x00000004  // Interrupt 34 active
-#define NVIC_ACTIVE1_INT33      0x00000002  // Interrupt 33 active
+#define NVIC_ACTIVE1_INT_M      0x00FFFFFF  // Interrupt Active
 #define NVIC_ACTIVE1_INT32      0x00000001  // Interrupt 32 active
+#define NVIC_ACTIVE1_INT33      0x00000002  // Interrupt 33 active
+#define NVIC_ACTIVE1_INT34      0x00000004  // Interrupt 34 active
+#define NVIC_ACTIVE1_INT35      0x00000008  // Interrupt 35 active
+#define NVIC_ACTIVE1_INT36      0x00000010  // Interrupt 36 active
+#define NVIC_ACTIVE1_INT37      0x00000020  // Interrupt 37 active
+#define NVIC_ACTIVE1_INT38      0x00000040  // Interrupt 38 active
+#define NVIC_ACTIVE1_INT39      0x00000080  // Interrupt 39 active
+#define NVIC_ACTIVE1_INT40      0x00000100  // Interrupt 40 active
+#define NVIC_ACTIVE1_INT41      0x00000200  // Interrupt 41 active
+#define NVIC_ACTIVE1_INT42      0x00000400  // Interrupt 42 active
+#define NVIC_ACTIVE1_INT43      0x00000800  // Interrupt 43 active
+#define NVIC_ACTIVE1_INT44      0x00001000  // Interrupt 44 active
+#define NVIC_ACTIVE1_INT45      0x00002000  // Interrupt 45 active
+#define NVIC_ACTIVE1_INT46      0x00004000  // Interrupt 46 active
+#define NVIC_ACTIVE1_INT47      0x00008000  // Interrupt 47 active
+#define NVIC_ACTIVE1_INT48      0x00010000  // Interrupt 48 active
+#define NVIC_ACTIVE1_INT49      0x00020000  // Interrupt 49 active
+#define NVIC_ACTIVE1_INT50      0x00040000  // Interrupt 50 active
+#define NVIC_ACTIVE1_INT51      0x00080000  // Interrupt 51 active
+#define NVIC_ACTIVE1_INT52      0x00100000  // Interrupt 52 active
+#define NVIC_ACTIVE1_INT53      0x00200000  // Interrupt 53 active
+#define NVIC_ACTIVE1_INT54      0x00400000  // Interrupt 54 active
+#define NVIC_ACTIVE1_INT55      0x00800000  // Interrupt 55 active
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_PRI0 register.
 //
 //*****************************************************************************
-#define NVIC_PRI0_INT3_M        0xFF000000  // Interrupt 3 priority mask
-#define NVIC_PRI0_INT2_M        0x00FF0000  // Interrupt 2 priority mask
-#define NVIC_PRI0_INT1_M        0x0000FF00  // Interrupt 1 priority mask
-#define NVIC_PRI0_INT0_M        0x000000FF  // Interrupt 0 priority mask
-#define NVIC_PRI0_INT3_S        24
-#define NVIC_PRI0_INT2_S        16
-#define NVIC_PRI0_INT1_S        8
-#define NVIC_PRI0_INT0_S        0
+#define NVIC_PRI0_INT3_M        0xE0000000  // Interrupt 3 Priority Mask
+#define NVIC_PRI0_INT2_M        0x00E00000  // Interrupt 2 Priority Mask
+#define NVIC_PRI0_INT1_M        0x0000E000  // Interrupt 1 Priority Mask
+#define NVIC_PRI0_INT0_M        0x000000E0  // Interrupt 0 Priority Mask
+#define NVIC_PRI0_INT3_S        29
+#define NVIC_PRI0_INT2_S        21
+#define NVIC_PRI0_INT1_S        13
+#define NVIC_PRI0_INT0_S        5
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_PRI1 register.
 //
 //*****************************************************************************
-#define NVIC_PRI1_INT7_M        0xFF000000  // Interrupt 7 priority mask
-#define NVIC_PRI1_INT6_M        0x00FF0000  // Interrupt 6 priority mask
-#define NVIC_PRI1_INT5_M        0x0000FF00  // Interrupt 5 priority mask
-#define NVIC_PRI1_INT4_M        0x000000FF  // Interrupt 4 priority mask
-#define NVIC_PRI1_INT7_S        24
-#define NVIC_PRI1_INT6_S        16
-#define NVIC_PRI1_INT5_S        8
-#define NVIC_PRI1_INT4_S        0
+#define NVIC_PRI1_INT7_M        0xE0000000  // Interrupt 7 Priority Mask
+#define NVIC_PRI1_INT6_M        0x00E00000  // Interrupt 6 Priority Mask
+#define NVIC_PRI1_INT5_M        0x0000E000  // Interrupt 5 Priority Mask
+#define NVIC_PRI1_INT4_M        0x000000E0  // Interrupt 4 Priority Mask
+#define NVIC_PRI1_INT7_S        29
+#define NVIC_PRI1_INT6_S        21
+#define NVIC_PRI1_INT5_S        13
+#define NVIC_PRI1_INT4_S        5
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_PRI2 register.
 //
 //*****************************************************************************
-#define NVIC_PRI2_INT11_M       0xFF000000  // Interrupt 11 priority mask
-#define NVIC_PRI2_INT10_M       0x00FF0000  // Interrupt 10 priority mask
-#define NVIC_PRI2_INT9_M        0x0000FF00  // Interrupt 9 priority mask
-#define NVIC_PRI2_INT8_M        0x000000FF  // Interrupt 8 priority mask
-#define NVIC_PRI2_INT11_S       24
-#define NVIC_PRI2_INT10_S       16
-#define NVIC_PRI2_INT9_S        8
-#define NVIC_PRI2_INT8_S        0
+#define NVIC_PRI2_INT11_M       0xE0000000  // Interrupt 11 Priority Mask
+#define NVIC_PRI2_INT10_M       0x00E00000  // Interrupt 10 Priority Mask
+#define NVIC_PRI2_INT9_M        0x0000E000  // Interrupt 9 Priority Mask
+#define NVIC_PRI2_INT8_M        0x000000E0  // Interrupt 8 Priority Mask
+#define NVIC_PRI2_INT11_S       29
+#define NVIC_PRI2_INT10_S       21
+#define NVIC_PRI2_INT9_S        13
+#define NVIC_PRI2_INT8_S        5
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_PRI3 register.
 //
 //*****************************************************************************
-#define NVIC_PRI3_INT15_M       0xFF000000  // Interrupt 15 priority mask
-#define NVIC_PRI3_INT14_M       0x00FF0000  // Interrupt 14 priority mask
-#define NVIC_PRI3_INT13_M       0x0000FF00  // Interrupt 13 priority mask
-#define NVIC_PRI3_INT12_M       0x000000FF  // Interrupt 12 priority mask
-#define NVIC_PRI3_INT15_S       24
-#define NVIC_PRI3_INT14_S       16
-#define NVIC_PRI3_INT13_S       8
-#define NVIC_PRI3_INT12_S       0
+#define NVIC_PRI3_INT15_M       0xE0000000  // Interrupt 15 Priority Mask
+#define NVIC_PRI3_INT14_M       0x00E00000  // Interrupt 14 Priority Mask
+#define NVIC_PRI3_INT13_M       0x0000E000  // Interrupt 13 Priority Mask
+#define NVIC_PRI3_INT12_M       0x000000E0  // Interrupt 12 Priority Mask
+#define NVIC_PRI3_INT15_S       29
+#define NVIC_PRI3_INT14_S       21
+#define NVIC_PRI3_INT13_S       13
+#define NVIC_PRI3_INT12_S       5
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_PRI4 register.
 //
 //*****************************************************************************
-#define NVIC_PRI4_INT19_M       0xFF000000  // Interrupt 19 priority mask
-#define NVIC_PRI4_INT18_M       0x00FF0000  // Interrupt 18 priority mask
-#define NVIC_PRI4_INT17_M       0x0000FF00  // Interrupt 17 priority mask
-#define NVIC_PRI4_INT16_M       0x000000FF  // Interrupt 16 priority mask
-#define NVIC_PRI4_INT19_S       24
-#define NVIC_PRI4_INT18_S       16
-#define NVIC_PRI4_INT17_S       8
-#define NVIC_PRI4_INT16_S       0
+#define NVIC_PRI4_INT19_M       0xE0000000  // Interrupt 19 Priority Mask
+#define NVIC_PRI4_INT18_M       0x00E00000  // Interrupt 18 Priority Mask
+#define NVIC_PRI4_INT17_M       0x0000E000  // Interrupt 17 Priority Mask
+#define NVIC_PRI4_INT16_M       0x000000E0  // Interrupt 16 Priority Mask
+#define NVIC_PRI4_INT19_S       29
+#define NVIC_PRI4_INT18_S       21
+#define NVIC_PRI4_INT17_S       13
+#define NVIC_PRI4_INT16_S       5
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_PRI5 register.
 //
 //*****************************************************************************
-#define NVIC_PRI5_INT23_M       0xFF000000  // Interrupt 23 priority mask
-#define NVIC_PRI5_INT22_M       0x00FF0000  // Interrupt 22 priority mask
-#define NVIC_PRI5_INT21_M       0x0000FF00  // Interrupt 21 priority mask
-#define NVIC_PRI5_INT20_M       0x000000FF  // Interrupt 20 priority mask
-#define NVIC_PRI5_INT23_S       24
-#define NVIC_PRI5_INT22_S       16
-#define NVIC_PRI5_INT21_S       8
-#define NVIC_PRI5_INT20_S       0
+#define NVIC_PRI5_INT23_M       0xE0000000  // Interrupt 23 Priority Mask
+#define NVIC_PRI5_INT22_M       0x00E00000  // Interrupt 22 Priority Mask
+#define NVIC_PRI5_INT21_M       0x0000E000  // Interrupt 21 Priority Mask
+#define NVIC_PRI5_INT20_M       0x000000E0  // Interrupt 20 Priority Mask
+#define NVIC_PRI5_INT23_S       29
+#define NVIC_PRI5_INT22_S       21
+#define NVIC_PRI5_INT21_S       13
+#define NVIC_PRI5_INT20_S       5
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_PRI6 register.
 //
 //*****************************************************************************
-#define NVIC_PRI6_INT27_M       0xFF000000  // Interrupt 27 priority mask
-#define NVIC_PRI6_INT26_M       0x00FF0000  // Interrupt 26 priority mask
-#define NVIC_PRI6_INT25_M       0x0000FF00  // Interrupt 25 priority mask
-#define NVIC_PRI6_INT24_M       0x000000FF  // Interrupt 24 priority mask
-#define NVIC_PRI6_INT27_S       24
-#define NVIC_PRI6_INT26_S       16
-#define NVIC_PRI6_INT25_S       8
-#define NVIC_PRI6_INT24_S       0
+#define NVIC_PRI6_INT27_M       0xE0000000  // Interrupt 27 Priority Mask
+#define NVIC_PRI6_INT26_M       0x00E00000  // Interrupt 26 Priority Mask
+#define NVIC_PRI6_INT25_M       0x0000E000  // Interrupt 25 Priority Mask
+#define NVIC_PRI6_INT24_M       0x000000E0  // Interrupt 24 Priority Mask
+#define NVIC_PRI6_INT27_S       29
+#define NVIC_PRI6_INT26_S       21
+#define NVIC_PRI6_INT25_S       13
+#define NVIC_PRI6_INT24_S       5
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_PRI7 register.
 //
 //*****************************************************************************
-#define NVIC_PRI7_INT31_M       0xFF000000  // Interrupt 31 priority mask
-#define NVIC_PRI7_INT30_M       0x00FF0000  // Interrupt 30 priority mask
-#define NVIC_PRI7_INT29_M       0x0000FF00  // Interrupt 29 priority mask
-#define NVIC_PRI7_INT28_M       0x000000FF  // Interrupt 28 priority mask
-#define NVIC_PRI7_INT31_S       24
-#define NVIC_PRI7_INT30_S       16
-#define NVIC_PRI7_INT29_S       8
-#define NVIC_PRI7_INT28_S       0
+#define NVIC_PRI7_INT31_M       0xE0000000  // Interrupt 31 Priority Mask
+#define NVIC_PRI7_INT30_M       0x00E00000  // Interrupt 30 Priority Mask
+#define NVIC_PRI7_INT29_M       0x0000E000  // Interrupt 29 Priority Mask
+#define NVIC_PRI7_INT28_M       0x000000E0  // Interrupt 28 Priority Mask
+#define NVIC_PRI7_INT31_S       29
+#define NVIC_PRI7_INT30_S       21
+#define NVIC_PRI7_INT29_S       13
+#define NVIC_PRI7_INT28_S       5
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_PRI8 register.
 //
 //*****************************************************************************
-#define NVIC_PRI8_INT35_M       0xFF000000  // Interrupt 35 priority mask
-#define NVIC_PRI8_INT34_M       0x00FF0000  // Interrupt 34 priority mask
-#define NVIC_PRI8_INT33_M       0x0000FF00  // Interrupt 33 priority mask
-#define NVIC_PRI8_INT32_M       0x000000FF  // Interrupt 32 priority mask
-#define NVIC_PRI8_INT35_S       24
-#define NVIC_PRI8_INT34_S       16
-#define NVIC_PRI8_INT33_S       8
-#define NVIC_PRI8_INT32_S       0
+#define NVIC_PRI8_INT35_M       0xE0000000  // Interrupt 35 Priority Mask
+#define NVIC_PRI8_INT34_M       0x00E00000  // Interrupt 34 Priority Mask
+#define NVIC_PRI8_INT33_M       0x0000E000  // Interrupt 33 Priority Mask
+#define NVIC_PRI8_INT32_M       0x000000E0  // Interrupt 32 Priority Mask
+#define NVIC_PRI8_INT35_S       29
+#define NVIC_PRI8_INT34_S       21
+#define NVIC_PRI8_INT33_S       13
+#define NVIC_PRI8_INT32_S       5
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_PRI9 register.
 //
 //*****************************************************************************
-#define NVIC_PRI9_INT39_M       0xFF000000  // Interrupt 39 priority mask
-#define NVIC_PRI9_INT38_M       0x00FF0000  // Interrupt 38 priority mask
-#define NVIC_PRI9_INT37_M       0x0000FF00  // Interrupt 37 priority mask
-#define NVIC_PRI9_INT36_M       0x000000FF  // Interrupt 36 priority mask
-#define NVIC_PRI9_INT39_S       24
-#define NVIC_PRI9_INT38_S       16
-#define NVIC_PRI9_INT37_S       8
-#define NVIC_PRI9_INT36_S       0
+#define NVIC_PRI9_INT39_M       0xE0000000  // Interrupt 39 Priority Mask
+#define NVIC_PRI9_INT38_M       0x00E00000  // Interrupt 38 Priority Mask
+#define NVIC_PRI9_INT37_M       0x0000E000  // Interrupt 37 Priority Mask
+#define NVIC_PRI9_INT36_M       0x000000E0  // Interrupt 36 Priority Mask
+#define NVIC_PRI9_INT39_S       29
+#define NVIC_PRI9_INT38_S       21
+#define NVIC_PRI9_INT37_S       13
+#define NVIC_PRI9_INT36_S       5
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_PRI10 register.
 //
 //*****************************************************************************
-#define NVIC_PRI10_INT43_M      0xFF000000  // Interrupt 43 priority mask
-#define NVIC_PRI10_INT42_M      0x00FF0000  // Interrupt 42 priority mask
-#define NVIC_PRI10_INT41_M      0x0000FF00  // Interrupt 41 priority mask
-#define NVIC_PRI10_INT40_M      0x000000FF  // Interrupt 40 priority mask
-#define NVIC_PRI10_INT43_S      24
-#define NVIC_PRI10_INT42_S      16
-#define NVIC_PRI10_INT41_S      8
-#define NVIC_PRI10_INT40_S      0
+#define NVIC_PRI10_INT43_M      0xE0000000  // Interrupt 43 Priority Mask
+#define NVIC_PRI10_INT42_M      0x00E00000  // Interrupt 42 Priority Mask
+#define NVIC_PRI10_INT41_M      0x0000E000  // Interrupt 41 Priority Mask
+#define NVIC_PRI10_INT40_M      0x000000E0  // Interrupt 40 Priority Mask
+#define NVIC_PRI10_INT43_S      29
+#define NVIC_PRI10_INT42_S      21
+#define NVIC_PRI10_INT41_S      13
+#define NVIC_PRI10_INT40_S      5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI11 register.
+//
+//*****************************************************************************
+#define NVIC_PRI11_INT47_M      0xE0000000  // Interrupt 47 Priority Mask
+#define NVIC_PRI11_INT46_M      0x00E00000  // Interrupt 46 Priority Mask
+#define NVIC_PRI11_INT45_M      0x0000E000  // Interrupt 45 Priority Mask
+#define NVIC_PRI11_INT44_M      0x000000E0  // Interrupt 44 Priority Mask
+#define NVIC_PRI11_INT47_S      29
+#define NVIC_PRI11_INT46_S      21
+#define NVIC_PRI11_INT45_S      13
+#define NVIC_PRI11_INT44_S      5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI12 register.
+//
+//*****************************************************************************
+#define NVIC_PRI12_INT51_M      0xE0000000  // Interrupt 51 Priority Mask
+#define NVIC_PRI12_INT50_M      0x00E00000  // Interrupt 50 Priority Mask
+#define NVIC_PRI12_INT49_M      0x0000E000  // Interrupt 49 Priority Mask
+#define NVIC_PRI12_INT48_M      0x000000E0  // Interrupt 48 Priority Mask
+#define NVIC_PRI12_INT51_S      29
+#define NVIC_PRI12_INT50_S      21
+#define NVIC_PRI12_INT49_S      13
+#define NVIC_PRI12_INT48_S      5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI13 register.
+//
+//*****************************************************************************
+#define NVIC_PRI13_INT55_M      0xE0000000  // Interrupt 55 Priority Mask
+#define NVIC_PRI13_INT54_M      0x00E00000  // Interrupt 54 Priority Mask
+#define NVIC_PRI13_INT53_M      0x0000E000  // Interrupt 53 Priority Mask
+#define NVIC_PRI13_INT52_M      0x000000E0  // Interrupt 52 Priority Mask
+#define NVIC_PRI13_INT55_S      29
+#define NVIC_PRI13_INT54_S      21
+#define NVIC_PRI13_INT53_S      13
+#define NVIC_PRI13_INT52_S      5
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_CPUID register.
 //
 //*****************************************************************************
-#define NVIC_CPUID_IMP_M        0xFF000000  // Implementer
-#define NVIC_CPUID_VAR_M        0x00F00000  // Variant
-#define NVIC_CPUID_PARTNO_M     0x0000FFF0  // Processor part number
-#define NVIC_CPUID_REV_M        0x0000000F  // Revision
+#define NVIC_CPUID_IMP_M        0xFF000000  // Implementer Code
+#define NVIC_CPUID_IMP_ARM      0x41000000  // ARM
+#define NVIC_CPUID_VAR_M        0x00F00000  // Variant Number
+#define NVIC_CPUID_CON_M        0x000F0000  // Constant
+#define NVIC_CPUID_PARTNO_M     0x0000FFF0  // Part Number
+#define NVIC_CPUID_PARTNO_CM3   0x0000C230  // Cortex-M3 processor
+#define NVIC_CPUID_REV_M        0x0000000F  // Revision Number
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_INT_CTRL register.
 //
 //*****************************************************************************
-#define NVIC_INT_CTRL_NMI_SET   0x80000000  // Pend a NMI
-#define NVIC_INT_CTRL_PEND_SV   0x10000000  // Pend a PendSV
-#define NVIC_INT_CTRL_UNPEND_SV 0x08000000  // Unpend a PendSV
-#define NVIC_INT_CTRL_ISR_PRE   0x00800000  // Debug interrupt handling
-#define NVIC_INT_CTRL_ISR_PEND  0x00400000  // Debug interrupt pending
-#define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000  // Highest pending exception
-#define NVIC_INT_CTRL_RET_BASE  0x00000800  // Return to base
-#define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF  // Current active exception
+#define NVIC_INT_CTRL_NMI_SET   0x80000000  // NMI Set Pending
+#define NVIC_INT_CTRL_PEND_SV   0x10000000  // PendSV Set Pending
+#define NVIC_INT_CTRL_UNPEND_SV 0x08000000  // PendSV Clear Pending
+#define NVIC_INT_CTRL_PENDSTSET 0x04000000  // SysTick Set Pending
+#define NVIC_INT_CTRL_PENDSTCLR 0x02000000  // SysTick Clear Pending
+#define NVIC_INT_CTRL_ISR_PRE   0x00800000  // Debug Interrupt Handling
+#define NVIC_INT_CTRL_ISR_PEND  0x00400000  // Interrupt Pending
+#define NVIC_INT_CTRL_VEC_PEN_M 0x0007F000  // Interrupt Pending Vector Number
+#define NVIC_INT_CTRL_VEC_PEN_NMI \
+                                0x00002000  // NMI
+#define NVIC_INT_CTRL_VEC_PEN_HARD \
+                                0x00003000  // Hard fault
+#define NVIC_INT_CTRL_VEC_PEN_MEM \
+                                0x00004000  // Memory management fault
+#define NVIC_INT_CTRL_VEC_PEN_BUS \
+                                0x00005000  // Bus fault
+#define NVIC_INT_CTRL_VEC_PEN_USG \
+                                0x00006000  // Usage fault
+#define NVIC_INT_CTRL_VEC_PEN_SVC \
+                                0x0000B000  // SVCall
+#define NVIC_INT_CTRL_VEC_PEN_PNDSV \
+                                0x0000E000  // PendSV
+#define NVIC_INT_CTRL_VEC_PEN_TICK \
+                                0x0000F000  // SysTick
+#define NVIC_INT_CTRL_RET_BASE  0x00000800  // Return to Base
+#define NVIC_INT_CTRL_VEC_ACT_M 0x0000007F  // Interrupt Pending Vector Number
 #define NVIC_INT_CTRL_VEC_PEN_S 12
 #define NVIC_INT_CTRL_VEC_ACT_S 0
 
@@ -678,86 +749,85 @@
 // The following are defines for the bit fields in the NVIC_VTABLE register.
 //
 //*****************************************************************************
-#define NVIC_VTABLE_BASE        0x20000000  // Vector table base
-#define NVIC_VTABLE_OFFSET_M    0x1FFFFF00  // Vector table offset
-#define NVIC_VTABLE_OFFSET_S    8
+#define NVIC_VTABLE_BASE        0x20000000  // Vector Table Base
+#define NVIC_VTABLE_OFFSET_M    0x1FFFFE00  // Vector Table Offset
+#define NVIC_VTABLE_OFFSET_S    9
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_APINT register.
 //
 //*****************************************************************************
-#define NVIC_APINT_VECTKEY_M    0xFFFF0000  // Vector key mask
+#define NVIC_APINT_VECTKEY_M    0xFFFF0000  // Register Key
 #define NVIC_APINT_VECTKEY      0x05FA0000  // Vector key
-#define NVIC_APINT_ENDIANESS    0x00008000  // Data endianess
-#define NVIC_APINT_PRIGROUP_M   0x00000700  // Priority group
-#define NVIC_APINT_PRIGROUP_0_8 0x00000700  // Priority group 0.8 split
-#define NVIC_APINT_PRIGROUP_1_7 0x00000600  // Priority group 1.7 split
-#define NVIC_APINT_PRIGROUP_2_6 0x00000500  // Priority group 2.6 split
-#define NVIC_APINT_PRIGROUP_3_5 0x00000400  // Priority group 3.5 split
-#define NVIC_APINT_PRIGROUP_4_4 0x00000300  // Priority group 4.4 split
-#define NVIC_APINT_PRIGROUP_5_3 0x00000200  // Priority group 5.3 split
-#define NVIC_APINT_PRIGROUP_6_2 0x00000100  // Priority group 6.2 split
-#define NVIC_APINT_SYSRESETREQ  0x00000004  // System reset request
-#define NVIC_APINT_VECT_CLR_ACT 0x00000002  // Clear active NMI/fault info
-#define NVIC_APINT_VECT_RESET   0x00000001  // System reset
+#define NVIC_APINT_ENDIANESS    0x00008000  // Data Endianess
+#define NVIC_APINT_PRIGROUP_M   0x00000700  // Interrupt Priority Grouping
 #define NVIC_APINT_PRIGROUP_7_1 0x00000000  // Priority group 7.1 split
+#define NVIC_APINT_PRIGROUP_6_2 0x00000100  // Priority group 6.2 split
+#define NVIC_APINT_PRIGROUP_5_3 0x00000200  // Priority group 5.3 split
+#define NVIC_APINT_PRIGROUP_4_4 0x00000300  // Priority group 4.4 split
+#define NVIC_APINT_PRIGROUP_3_5 0x00000400  // Priority group 3.5 split
+#define NVIC_APINT_PRIGROUP_2_6 0x00000500  // Priority group 2.6 split
+#define NVIC_APINT_PRIGROUP_1_7 0x00000600  // Priority group 1.7 split
+#define NVIC_APINT_PRIGROUP_0_8 0x00000700  // Priority group 0.8 split
+#define NVIC_APINT_SYSRESETREQ  0x00000004  // System Reset Request
+#define NVIC_APINT_VECT_CLR_ACT 0x00000002  // Clear Active NMI / Fault
+#define NVIC_APINT_VECT_RESET   0x00000001  // System Reset
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_SYS_CTRL register.
 //
 //*****************************************************************************
-#define NVIC_SYS_CTRL_SEVONPEND 0x00000010  // Wakeup on pend
-#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004  // Deep sleep enable
-#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002  // Sleep on ISR exit
+#define NVIC_SYS_CTRL_SEVONPEND 0x00000010  // Wake Up on Pending
+#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004  // Deep Sleep Enable
+#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002  // Sleep on ISR Exit
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_CFG_CTRL register.
 //
 //*****************************************************************************
-#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100  // Ignore bus fault in NMI/fault
-#define NVIC_CFG_CTRL_DIV0      0x00000010  // Trap on divide by 0
-#define NVIC_CFG_CTRL_UNALIGNED 0x00000008  // Trap on unaligned access
-#define NVIC_CFG_CTRL_DEEP_PEND 0x00000004  // Allow deep interrupt trigger
-#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002  // Allow main interrupt trigger
-#define NVIC_CFG_CTRL_BASE_THR  0x00000001  // Thread state control
+#define NVIC_CFG_CTRL_STKALIGN  0x00000200  // Stack Alignment on Exception
+                                            // Entry
+#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100  // Ignore Bus Fault in NMI and
+                                            // Fault
+#define NVIC_CFG_CTRL_DIV0      0x00000010  // Trap on Divide by 0
+#define NVIC_CFG_CTRL_UNALIGNED 0x00000008  // Trap on Unaligned Access
+#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002  // Allow Main Interrupt Trigger
+#define NVIC_CFG_CTRL_BASE_THR  0x00000001  // Thread State Control
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_SYS_PRI1 register.
 //
 //*****************************************************************************
-#define NVIC_SYS_PRI1_RES_M     0xFF000000  // Priority of reserved handler
-#define NVIC_SYS_PRI1_USAGE_M   0x00FF0000  // Priority of usage fault handler
-#define NVIC_SYS_PRI1_BUS_M     0x0000FF00  // Priority of bus fault handler
-#define NVIC_SYS_PRI1_MEM_M     0x000000FF  // Priority of mem manage handler
-#define NVIC_SYS_PRI1_USAGE_S   16
-#define NVIC_SYS_PRI1_BUS_S     8
-#define NVIC_SYS_PRI1_MEM_S     0
+#define NVIC_SYS_PRI1_USAGE_M   0x00E00000  // Usage Fault Priority
+#define NVIC_SYS_PRI1_BUS_M     0x0000E000  // Bus Fault Priority
+#define NVIC_SYS_PRI1_MEM_M     0x000000E0  // Memory Management Fault Priority
+#define NVIC_SYS_PRI1_USAGE_S   21
+#define NVIC_SYS_PRI1_BUS_S     13
+#define NVIC_SYS_PRI1_MEM_S     5
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_SYS_PRI2 register.
 //
 //*****************************************************************************
-#define NVIC_SYS_PRI2_SVC_M     0xFF000000  // Priority of SVCall handler
-#define NVIC_SYS_PRI2_RES_M     0x00FFFFFF  // Priority of reserved handlers
-#define NVIC_SYS_PRI2_SVC_S     24
+#define NVIC_SYS_PRI2_SVC_M     0xE0000000  // SVCall Priority
+#define NVIC_SYS_PRI2_SVC_S     29
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_SYS_PRI3 register.
 //
 //*****************************************************************************
-#define NVIC_SYS_PRI3_TICK_M    0xFF000000  // Priority of Sys Tick handler
-#define NVIC_SYS_PRI3_PENDSV_M  0x00FF0000  // Priority of PendSV handler
-#define NVIC_SYS_PRI3_RES_M     0x0000FF00  // Priority of reserved handler
-#define NVIC_SYS_PRI3_DEBUG_M   0x000000FF  // Priority of debug handler
-#define NVIC_SYS_PRI3_TICK_S    24
-#define NVIC_SYS_PRI3_PENDSV_S  16
-#define NVIC_SYS_PRI3_DEBUG_S   0
+#define NVIC_SYS_PRI3_TICK_M    0xE0000000  // SysTick Exception Priority
+#define NVIC_SYS_PRI3_PENDSV_M  0x00E00000  // PendSV Priority
+#define NVIC_SYS_PRI3_DEBUG_M   0x000000E0  // Debug Priority
+#define NVIC_SYS_PRI3_TICK_S    29
+#define NVIC_SYS_PRI3_PENDSV_S  21
+#define NVIC_SYS_PRI3_DEBUG_S   5
 
 //*****************************************************************************
 //
@@ -765,18 +835,21 @@
 // register.
 //
 //*****************************************************************************
-#define NVIC_SYS_HND_CTRL_USAGE 0x00040000  // Usage fault enable
-#define NVIC_SYS_HND_CTRL_BUS   0x00020000  // Bus fault enable
-#define NVIC_SYS_HND_CTRL_MEM   0x00010000  // Mem manage fault enable
-#define NVIC_SYS_HND_CTRL_SVC   0x00008000  // SVCall is pended
-#define NVIC_SYS_HND_CTRL_BUSP  0x00004000  // Bus fault is pended
-#define NVIC_SYS_HND_CTRL_TICK  0x00000800  // Sys tick is active
-#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400  // PendSV is active
-#define NVIC_SYS_HND_CTRL_MON   0x00000100  // Monitor is active
-#define NVIC_SYS_HND_CTRL_SVCA  0x00000080  // SVCall is active
-#define NVIC_SYS_HND_CTRL_USGA  0x00000008  // Usage fault is active
-#define NVIC_SYS_HND_CTRL_BUSA  0x00000002  // Bus fault is active
-#define NVIC_SYS_HND_CTRL_MEMA  0x00000001  // Mem manage is active
+#define NVIC_SYS_HND_CTRL_USAGE 0x00040000  // Usage Fault Enable
+#define NVIC_SYS_HND_CTRL_BUS   0x00020000  // Bus Fault Enable
+#define NVIC_SYS_HND_CTRL_MEM   0x00010000  // Memory Management Fault Enable
+#define NVIC_SYS_HND_CTRL_SVC   0x00008000  // SVC Call Pending
+#define NVIC_SYS_HND_CTRL_BUSP  0x00004000  // Bus Fault Pending
+#define NVIC_SYS_HND_CTRL_MEMP  0x00002000  // Memory Management Fault Pending
+#define NVIC_SYS_HND_CTRL_USAGEP \
+                                0x00001000  // Usage Fault Pending
+#define NVIC_SYS_HND_CTRL_TICK  0x00000800  // SysTick Exception Active
+#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400  // PendSV Exception Active
+#define NVIC_SYS_HND_CTRL_MON   0x00000100  // Debug Monitor Active
+#define NVIC_SYS_HND_CTRL_SVCA  0x00000080  // SVC Call Active
+#define NVIC_SYS_HND_CTRL_USGA  0x00000008  // Usage Fault Active
+#define NVIC_SYS_HND_CTRL_BUSA  0x00000002  // Bus Fault Active
+#define NVIC_SYS_HND_CTRL_MEMA  0x00000001  // Memory Management Fault Active
 
 //*****************************************************************************
 //
@@ -784,23 +857,25 @@
 // register.
 //
 //*****************************************************************************
-#define NVIC_FAULT_STAT_DIV0    0x02000000  // Divide by zero fault
-#define NVIC_FAULT_STAT_UNALIGN 0x01000000  // Unaligned access fault
-#define NVIC_FAULT_STAT_NOCP    0x00080000  // No coprocessor fault
-#define NVIC_FAULT_STAT_INVPC   0x00040000  // Invalid PC fault
-#define NVIC_FAULT_STAT_INVSTAT 0x00020000  // Invalid state fault
-#define NVIC_FAULT_STAT_UNDEF   0x00010000  // Undefined instruction fault
-#define NVIC_FAULT_STAT_BFARV   0x00008000  // BFAR is valid
-#define NVIC_FAULT_STAT_BSTKE   0x00001000  // Stack bus fault
-#define NVIC_FAULT_STAT_BUSTKE  0x00000800  // Unstack bus fault
-#define NVIC_FAULT_STAT_IMPRE   0x00000400  // Imprecise data bus error
-#define NVIC_FAULT_STAT_PRECISE 0x00000200  // Precise data bus error
-#define NVIC_FAULT_STAT_IBUS    0x00000100  // Instruction bus fault
-#define NVIC_FAULT_STAT_MMARV   0x00000080  // MMAR is valid
-#define NVIC_FAULT_STAT_MSTKE   0x00000010  // Stack access violation
-#define NVIC_FAULT_STAT_MUSTKE  0x00000008  // Unstack access violation
-#define NVIC_FAULT_STAT_DERR    0x00000002  // Data access violation
-#define NVIC_FAULT_STAT_IERR    0x00000001  // Instruction access violation
+#define NVIC_FAULT_STAT_DIV0    0x02000000  // Divide-by-Zero Usage Fault
+#define NVIC_FAULT_STAT_UNALIGN 0x01000000  // Unaligned Access Usage Fault
+#define NVIC_FAULT_STAT_NOCP    0x00080000  // No Coprocessor Usage Fault
+#define NVIC_FAULT_STAT_INVPC   0x00040000  // Invalid PC Load Usage Fault
+#define NVIC_FAULT_STAT_INVSTAT 0x00020000  // Invalid State Usage Fault
+#define NVIC_FAULT_STAT_UNDEF   0x00010000  // Undefined Instruction Usage
+                                            // Fault
+#define NVIC_FAULT_STAT_BFARV   0x00008000  // Bus Fault Address Register Valid
+#define NVIC_FAULT_STAT_BSTKE   0x00001000  // Stack Bus Fault
+#define NVIC_FAULT_STAT_BUSTKE  0x00000800  // Unstack Bus Fault
+#define NVIC_FAULT_STAT_IMPRE   0x00000400  // Imprecise Data Bus Error
+#define NVIC_FAULT_STAT_PRECISE 0x00000200  // Precise Data Bus Error
+#define NVIC_FAULT_STAT_IBUS    0x00000100  // Instruction Bus Error
+#define NVIC_FAULT_STAT_MMARV   0x00000080  // Memory Management Fault Address
+                                            // Register Valid
+#define NVIC_FAULT_STAT_MSTKE   0x00000010  // Stack Access Violation
+#define NVIC_FAULT_STAT_MUSTKE  0x00000008  // Unstack Access Violation
+#define NVIC_FAULT_STAT_DERR    0x00000002  // Data Access Violation
+#define NVIC_FAULT_STAT_IERR    0x00000001  // Instruction Access Violation
 
 //*****************************************************************************
 //
@@ -808,9 +883,9 @@
 // register.
 //
 //*****************************************************************************
-#define NVIC_HFAULT_STAT_DBG    0x80000000  // Debug event
-#define NVIC_HFAULT_STAT_FORCED 0x40000000  // Cannot execute fault handler
-#define NVIC_HFAULT_STAT_VECT   0x00000002  // Vector table read fault
+#define NVIC_HFAULT_STAT_DBG    0x80000000  // Debug Event
+#define NVIC_HFAULT_STAT_FORCED 0x40000000  // Forced Hard Fault
+#define NVIC_HFAULT_STAT_VECT   0x00000002  // Vector Table Read Fault
 
 //*****************************************************************************
 //
@@ -829,7 +904,7 @@
 // The following are defines for the bit fields in the NVIC_MM_ADDR register.
 //
 //*****************************************************************************
-#define NVIC_MM_ADDR_M          0xFFFFFFFF  // Data fault address
+#define NVIC_MM_ADDR_M          0xFFFFFFFF  // Fault Address
 #define NVIC_MM_ADDR_S          0
 
 //*****************************************************************************
@@ -838,7 +913,7 @@
 // register.
 //
 //*****************************************************************************
-#define NVIC_FAULT_ADDR_M       0xFFFFFFFF  // Data bus fault address
+#define NVIC_FAULT_ADDR_M       0xFFFFFFFF  // Fault Address
 #define NVIC_FAULT_ADDR_S       0
 
 //*****************************************************************************
@@ -846,9 +921,9 @@
 // The following are defines for the bit fields in the NVIC_MPU_TYPE register.
 //
 //*****************************************************************************
-#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000  // Number of I regions
-#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00  // Number of D regions
-#define NVIC_MPU_TYPE_SEPARATE  0x00000001  // Separate or unified MPU
+#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000  // Number of I Regions
+#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00  // Number of D Regions
+#define NVIC_MPU_TYPE_SEPARATE  0x00000001  // Separate or Unified MPU
 #define NVIC_MPU_TYPE_IREGION_S 16
 #define NVIC_MPU_TYPE_DREGION_S 8
 
@@ -857,9 +932,9 @@
 // The following are defines for the bit fields in the NVIC_MPU_CTRL register.
 //
 //*****************************************************************************
-#define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004  // MPU default region in priv mode
-#define NVIC_MPU_CTRL_HFNMIENA  0x00000002  // MPU enabled during faults
-#define NVIC_MPU_CTRL_ENABLE    0x00000001  // MPU enable
+#define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004  // MPU Default Region
+#define NVIC_MPU_CTRL_HFNMIENA  0x00000002  // MPU Enabled During Faults
+#define NVIC_MPU_CTRL_ENABLE    0x00000001  // MPU Enable
 
 //*****************************************************************************
 //
@@ -867,7 +942,7 @@
 // register.
 //
 //*****************************************************************************
-#define NVIC_MPU_NUMBER_M       0x000000FF  // MPU region to access
+#define NVIC_MPU_NUMBER_M       0x00000007  // MPU Region to Access
 #define NVIC_MPU_NUMBER_S       0
 
 //*****************************************************************************
@@ -875,10 +950,10 @@
 // The following are defines for the bit fields in the NVIC_MPU_BASE register.
 //
 //*****************************************************************************
-#define NVIC_MPU_BASE_ADDR_M    0xFFFFFFE0  // Base address mask
-#define NVIC_MPU_BASE_VALID     0x00000010  // Region number valid
-#define NVIC_MPU_BASE_REGION_M  0x0000000F  // Region number
-#define NVIC_MPU_BASE_ADDR_S    8
+#define NVIC_MPU_BASE_ADDR_M    0xFFFFFFE0  // Base Address Mask
+#define NVIC_MPU_BASE_VALID     0x00000010  // Region Number Valid
+#define NVIC_MPU_BASE_REGION_M  0x00000007  // Region Number
+#define NVIC_MPU_BASE_ADDR_S    5
 #define NVIC_MPU_BASE_REGION_S  0
 
 //*****************************************************************************
@@ -887,19 +962,19 @@
 //
 //*****************************************************************************
 #define NVIC_MPU_ATTR_M         0xFFFF0000  // Attributes
+#define NVIC_MPU_ATTR_XN        0x10000000  // Instruction Access Disable
+#define NVIC_MPU_ATTR_AP_M      0x07000000  // Access Privilege
 #define NVIC_MPU_ATTR_AP_NO_NO  0x00000000  // prv: no access, usr: no access
-#define NVIC_MPU_ATTR_BUFFRABLE 0x00010000  // Bufferable
-#define NVIC_MPU_ATTR_CACHEABLE 0x00020000  // Cacheable
-#define NVIC_MPU_ATTR_SHAREABLE 0x00040000  // Shareable
-#define NVIC_MPU_ATTR_TEX_M     0x00380000  // Type extension mask
 #define NVIC_MPU_ATTR_AP_RW_NO  0x01000000  // prv: rw, usr: none
 #define NVIC_MPU_ATTR_AP_RW_RO  0x02000000  // prv: rw, usr: read-only
 #define NVIC_MPU_ATTR_AP_RW_RW  0x03000000  // prv: rw, usr: rw
 #define NVIC_MPU_ATTR_AP_RO_NO  0x05000000  // prv: ro, usr: none
 #define NVIC_MPU_ATTR_AP_RO_RO  0x06000000  // prv: ro, usr: ro
-#define NVIC_MPU_ATTR_AP_M      0x07000000  // Access permissions mask
-#define NVIC_MPU_ATTR_XN        0x10000000  // Execute disable
-#define NVIC_MPU_ATTR_SRD_M     0x0000FF00  // Sub-region disable mask
+#define NVIC_MPU_ATTR_TEX_M     0x00380000  // Type Extension Mask
+#define NVIC_MPU_ATTR_SHAREABLE 0x00040000  // Shareable
+#define NVIC_MPU_ATTR_CACHEABLE 0x00020000  // Cacheable
+#define NVIC_MPU_ATTR_BUFFRABLE 0x00010000  // Bufferable
+#define NVIC_MPU_ATTR_SRD_M     0x0000FF00  // Subregion Disable Bits
 #define NVIC_MPU_ATTR_SRD_0     0x00000100  // Sub-region 0 disable
 #define NVIC_MPU_ATTR_SRD_1     0x00000200  // Sub-region 1 disable
 #define NVIC_MPU_ATTR_SRD_2     0x00000400  // Sub-region 2 disable
@@ -908,7 +983,7 @@
 #define NVIC_MPU_ATTR_SRD_5     0x00002000  // Sub-region 5 disable
 #define NVIC_MPU_ATTR_SRD_6     0x00004000  // Sub-region 6 disable
 #define NVIC_MPU_ATTR_SRD_7     0x00008000  // Sub-region 7 disable
-#define NVIC_MPU_ATTR_SIZE_M    0x0000003E  // Region size mask
+#define NVIC_MPU_ATTR_SIZE_M    0x0000003E  // Region Size Mask
 #define NVIC_MPU_ATTR_SIZE_32B  0x00000008  // Region size 32 bytes
 #define NVIC_MPU_ATTR_SIZE_64B  0x0000000A  // Region size 64 bytes
 #define NVIC_MPU_ATTR_SIZE_128B 0x0000000C  // Region size 128 bytes
@@ -937,7 +1012,94 @@
 #define NVIC_MPU_ATTR_SIZE_1G   0x0000003A  // Region size 1 Gbytes
 #define NVIC_MPU_ATTR_SIZE_2G   0x0000003C  // Region size 2 Gbytes
 #define NVIC_MPU_ATTR_SIZE_4G   0x0000003E  // Region size 4 Gbytes
-#define NVIC_MPU_ATTR_ENABLE    0x00000001  // Region enable
+#define NVIC_MPU_ATTR_ENABLE    0x00000001  // Region Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE1 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE1_ADDR_M   0xFFFFFFE0  // Base Address Mask
+#define NVIC_MPU_BASE1_VALID    0x00000010  // Region Number Valid
+#define NVIC_MPU_BASE1_REGION_M 0x00000007  // Region Number
+#define NVIC_MPU_BASE1_ADDR_S   5
+#define NVIC_MPU_BASE1_REGION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR1 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR1_XN       0x10000000  // Instruction Access Disable
+#define NVIC_MPU_ATTR1_AP_M     0x07000000  // Access Privilege
+#define NVIC_MPU_ATTR1_TEX_M    0x00380000  // Type Extension Mask
+#define NVIC_MPU_ATTR1_SHAREABLE \
+                                0x00040000  // Shareable
+#define NVIC_MPU_ATTR1_CACHEABLE \
+                                0x00020000  // Cacheable
+#define NVIC_MPU_ATTR1_BUFFRABLE \
+                                0x00010000  // Bufferable
+#define NVIC_MPU_ATTR1_SRD_M    0x0000FF00  // Subregion Disable Bits
+#define NVIC_MPU_ATTR1_SIZE_M   0x0000003E  // Region Size Mask
+#define NVIC_MPU_ATTR1_ENABLE   0x00000001  // Region Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE2 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE2_ADDR_M   0xFFFFFFE0  // Base Address Mask
+#define NVIC_MPU_BASE2_VALID    0x00000010  // Region Number Valid
+#define NVIC_MPU_BASE2_REGION_M 0x00000007  // Region Number
+#define NVIC_MPU_BASE2_ADDR_S   5
+#define NVIC_MPU_BASE2_REGION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR2 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR2_XN       0x10000000  // Instruction Access Disable
+#define NVIC_MPU_ATTR2_AP_M     0x07000000  // Access Privilege
+#define NVIC_MPU_ATTR2_TEX_M    0x00380000  // Type Extension Mask
+#define NVIC_MPU_ATTR2_SHAREABLE \
+                                0x00040000  // Shareable
+#define NVIC_MPU_ATTR2_CACHEABLE \
+                                0x00020000  // Cacheable
+#define NVIC_MPU_ATTR2_BUFFRABLE \
+                                0x00010000  // Bufferable
+#define NVIC_MPU_ATTR2_SRD_M    0x0000FF00  // Subregion Disable Bits
+#define NVIC_MPU_ATTR2_SIZE_M   0x0000003E  // Region Size Mask
+#define NVIC_MPU_ATTR2_ENABLE   0x00000001  // Region Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE3 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE3_ADDR_M   0xFFFFFFE0  // Base Address Mask
+#define NVIC_MPU_BASE3_VALID    0x00000010  // Region Number Valid
+#define NVIC_MPU_BASE3_REGION_M 0x00000007  // Region Number
+#define NVIC_MPU_BASE3_ADDR_S   5
+#define NVIC_MPU_BASE3_REGION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR3 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR3_XN       0x10000000  // Instruction Access Disable
+#define NVIC_MPU_ATTR3_AP_M     0x07000000  // Access Privilege
+#define NVIC_MPU_ATTR3_TEX_M    0x00380000  // Type Extension Mask
+#define NVIC_MPU_ATTR3_SHAREABLE \
+                                0x00040000  // Shareable
+#define NVIC_MPU_ATTR3_CACHEABLE \
+                                0x00020000  // Cacheable
+#define NVIC_MPU_ATTR3_BUFFRABLE \
+                                0x00010000  // Bufferable
+#define NVIC_MPU_ATTR3_SRD_M    0x0000FF00  // Subregion Disable Bits
+#define NVIC_MPU_ATTR3_SIZE_M   0x0000003E  // Region Size Mask
+#define NVIC_MPU_ATTR3_ENABLE   0x00000001  // Region Enable
 
 //*****************************************************************************
 //
@@ -969,27 +1131,27 @@
 //*****************************************************************************
 #define NVIC_DBG_XFER_REG_WNR   0x00010000  // Write or not read
 #define NVIC_DBG_XFER_REG_SEL_M 0x0000001F  // Register
-#define NVIC_DBG_XFER_REG_CFBP  0x00000014  // Control/Fault/BasePri/PriMask
-#define NVIC_DBG_XFER_REG_DSP   0x00000013  // Deep SP
-#define NVIC_DBG_XFER_REG_PSP   0x00000012  // Process SP
-#define NVIC_DBG_XFER_REG_MSP   0x00000011  // Main SP
-#define NVIC_DBG_XFER_REG_FLAGS 0x00000010  // xPSR/Flags register
-#define NVIC_DBG_XFER_REG_R15   0x0000000F  // Register R15
-#define NVIC_DBG_XFER_REG_R14   0x0000000E  // Register R14
-#define NVIC_DBG_XFER_REG_R13   0x0000000D  // Register R13
-#define NVIC_DBG_XFER_REG_R12   0x0000000C  // Register R12
-#define NVIC_DBG_XFER_REG_R11   0x0000000B  // Register R11
-#define NVIC_DBG_XFER_REG_R10   0x0000000A  // Register R10
-#define NVIC_DBG_XFER_REG_R9    0x00000009  // Register R9
-#define NVIC_DBG_XFER_REG_R8    0x00000008  // Register R8
-#define NVIC_DBG_XFER_REG_R7    0x00000007  // Register R7
-#define NVIC_DBG_XFER_REG_R6    0x00000006  // Register R6
-#define NVIC_DBG_XFER_REG_R5    0x00000005  // Register R5
-#define NVIC_DBG_XFER_REG_R4    0x00000004  // Register R4
-#define NVIC_DBG_XFER_REG_R3    0x00000003  // Register R3
-#define NVIC_DBG_XFER_REG_R2    0x00000002  // Register R2
-#define NVIC_DBG_XFER_REG_R1    0x00000001  // Register R1
 #define NVIC_DBG_XFER_REG_R0    0x00000000  // Register R0
+#define NVIC_DBG_XFER_REG_R1    0x00000001  // Register R1
+#define NVIC_DBG_XFER_REG_R2    0x00000002  // Register R2
+#define NVIC_DBG_XFER_REG_R3    0x00000003  // Register R3
+#define NVIC_DBG_XFER_REG_R4    0x00000004  // Register R4
+#define NVIC_DBG_XFER_REG_R5    0x00000005  // Register R5
+#define NVIC_DBG_XFER_REG_R6    0x00000006  // Register R6
+#define NVIC_DBG_XFER_REG_R7    0x00000007  // Register R7
+#define NVIC_DBG_XFER_REG_R8    0x00000008  // Register R8
+#define NVIC_DBG_XFER_REG_R9    0x00000009  // Register R9
+#define NVIC_DBG_XFER_REG_R10   0x0000000A  // Register R10
+#define NVIC_DBG_XFER_REG_R11   0x0000000B  // Register R11
+#define NVIC_DBG_XFER_REG_R12   0x0000000C  // Register R12
+#define NVIC_DBG_XFER_REG_R13   0x0000000D  // Register R13
+#define NVIC_DBG_XFER_REG_R14   0x0000000E  // Register R14
+#define NVIC_DBG_XFER_REG_R15   0x0000000F  // Register R15
+#define NVIC_DBG_XFER_REG_FLAGS 0x00000010  // xPSR/Flags register
+#define NVIC_DBG_XFER_REG_MSP   0x00000011  // Main SP
+#define NVIC_DBG_XFER_REG_PSP   0x00000012  // Process SP
+#define NVIC_DBG_XFER_REG_DSP   0x00000013  // Deep SP
+#define NVIC_DBG_XFER_REG_CFBP  0x00000014  // Control/Fault/BasePri/PriMask
 
 //*****************************************************************************
 //
@@ -1021,7 +1183,7 @@
 // The following are defines for the bit fields in the NVIC_SW_TRIG register.
 //
 //*****************************************************************************
-#define NVIC_SW_TRIG_INTID_M    0x000003FF  // Interrupt to trigger
+#define NVIC_SW_TRIG_INTID_M    0x0000003F  // Interrupt ID
 #define NVIC_SW_TRIG_INTID_S    0
 
 #endif // __HW_NVIC_H__
diff --git a/src/platform/lm3s/hw_pwm.h b/src/platform/lm3s/inc/hw_pwm.h
similarity index 67%
rename from src/platform/lm3s/hw_pwm.h
rename to src/platform/lm3s/inc/hw_pwm.h
index fcfc4adc..b9064f01 100755
--- a/src/platform/lm3s/hw_pwm.h
+++ b/src/platform/lm3s/inc/hw_pwm.h
@@ -1,27 +1,24 @@
 //*****************************************************************************
 //
-// hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports
+// hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports.
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2011 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4781 of the Stellaris Firmware Development Package.
+// This is part of revision 7611 of the Stellaris Firmware Development Package.
 //
 //*****************************************************************************
 
@@ -30,19 +27,20 @@
 
 //*****************************************************************************
 //
-// The following are defines for the PWM Module Register offsets.
+// The following are defines for the PWM register offsets.
 //
 //*****************************************************************************
-#define PWM_O_CTL               0x00000000  // PWM Master Control register
-#define PWM_O_SYNC              0x00000004  // PWM Time Base Sync register
-#define PWM_O_ENABLE            0x00000008  // PWM Output Enable register
-#define PWM_O_INVERT            0x0000000C  // PWM Output Inversion register
-#define PWM_O_FAULT             0x00000010  // PWM Output Fault register
-#define PWM_O_INTEN             0x00000014  // PWM Interrupt Enable register
-#define PWM_O_RIS               0x00000018  // PWM Interrupt Raw Status reg.
-#define PWM_O_ISC               0x0000001C  // PWM Interrupt Status register
-#define PWM_O_STATUS            0x00000020  // PWM Status register
+#define PWM_O_CTL               0x00000000  // PWM Master Control
+#define PWM_O_SYNC              0x00000004  // PWM Time Base Sync
+#define PWM_O_ENABLE            0x00000008  // PWM Output Enable
+#define PWM_O_INVERT            0x0000000C  // PWM Output Inversion
+#define PWM_O_FAULT             0x00000010  // PWM Output Fault
+#define PWM_O_INTEN             0x00000014  // PWM Interrupt Enable
+#define PWM_O_RIS               0x00000018  // PWM Raw Interrupt Status
+#define PWM_O_ISC               0x0000001C  // PWM Interrupt Status and Clear
+#define PWM_O_STATUS            0x00000020  // PWM Status
 #define PWM_O_FAULTVAL          0x00000024  // PWM Fault Condition Value
+#define PWM_O_ENUPD             0x00000028  // PWM Enable Update
 #define PWM_O_0_CTL             0x00000040  // PWM0 Control
 #define PWM_O_0_INTEN           0x00000044  // PWM0 Interrupt and Trigger
                                             // Enable
@@ -62,7 +60,8 @@
 #define PWM_O_0_FLTSRC1         0x00000078  // PWM0 Fault Source 1
 #define PWM_O_0_MINFLTPER       0x0000007C  // PWM0 Minimum Fault Period
 #define PWM_O_1_CTL             0x00000080  // PWM1 Control
-#define PWM_O_1_INTEN           0x00000084  // PWM1 Interrupt Enable
+#define PWM_O_1_INTEN           0x00000084  // PWM1 Interrupt and Trigger
+                                            // Enable
 #define PWM_O_1_RIS             0x00000088  // PWM1 Raw Interrupt Status
 #define PWM_O_1_ISC             0x0000008C  // PWM1 Interrupt Status and Clear
 #define PWM_O_1_LOAD            0x00000090  // PWM1 Load
@@ -79,7 +78,8 @@
 #define PWM_O_1_FLTSRC1         0x000000B8  // PWM1 Fault Source 1
 #define PWM_O_1_MINFLTPER       0x000000BC  // PWM1 Minimum Fault Period
 #define PWM_O_2_CTL             0x000000C0  // PWM2 Control
-#define PWM_O_2_INTEN           0x000000C4  // PWM2 InterruptEnable
+#define PWM_O_2_INTEN           0x000000C4  // PWM2 Interrupt and Trigger
+                                            // Enable
 #define PWM_O_2_RIS             0x000000C8  // PWM2 Raw Interrupt Status
 #define PWM_O_2_ISC             0x000000CC  // PWM2 Interrupt Status and Clear
 #define PWM_O_2_LOAD            0x000000D0  // PWM2 Load
@@ -128,78 +128,471 @@
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the PWM Master Control
+// The following are defines for the bit fields in the PWM_O_CTL register.
+//
+//*****************************************************************************
+#define PWM_CTL_GLOBALSYNC3     0x00000008  // Update PWM Generator 3
+#define PWM_CTL_GLOBALSYNC2     0x00000004  // Update PWM Generator 2
+#define PWM_CTL_GLOBALSYNC1     0x00000002  // Update PWM Generator 1
+#define PWM_CTL_GLOBALSYNC0     0x00000001  // Update PWM Generator 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_SYNC register.
+//
+//*****************************************************************************
+#define PWM_SYNC_SYNC3          0x00000008  // Reset Generator 3 Counter
+#define PWM_SYNC_SYNC2          0x00000004  // Reset Generator 2 Counter
+#define PWM_SYNC_SYNC1          0x00000002  // Reset Generator 1 Counter
+#define PWM_SYNC_SYNC0          0x00000001  // Reset Generator 0 Counter
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_ENABLE register.
+//
+//*****************************************************************************
+#define PWM_ENABLE_PWM7EN       0x00000080  // PWM7 Output Enable
+#define PWM_ENABLE_PWM6EN       0x00000040  // PWM6 Output Enable
+#define PWM_ENABLE_PWM5EN       0x00000020  // PWM5 Output Enable
+#define PWM_ENABLE_PWM4EN       0x00000010  // PWM4 Output Enable
+#define PWM_ENABLE_PWM3EN       0x00000008  // PWM3 Output Enable
+#define PWM_ENABLE_PWM2EN       0x00000004  // PWM2 Output Enable
+#define PWM_ENABLE_PWM1EN       0x00000002  // PWM1 Output Enable
+#define PWM_ENABLE_PWM0EN       0x00000001  // PWM0 Output Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_INVERT register.
+//
+//*****************************************************************************
+#define PWM_INVERT_PWM7INV      0x00000080  // Invert PWM7 Signal
+#define PWM_INVERT_PWM6INV      0x00000040  // Invert PWM6 Signal
+#define PWM_INVERT_PWM5INV      0x00000020  // Invert PWM5 Signal
+#define PWM_INVERT_PWM4INV      0x00000010  // Invert PWM4 Signal
+#define PWM_INVERT_PWM3INV      0x00000008  // Invert PWM3 Signal
+#define PWM_INVERT_PWM2INV      0x00000004  // Invert PWM2 Signal
+#define PWM_INVERT_PWM1INV      0x00000002  // Invert PWM1 Signal
+#define PWM_INVERT_PWM0INV      0x00000001  // Invert PWM0 Signal
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_FAULT register.
+//
+//*****************************************************************************
+#define PWM_FAULT_FAULT7        0x00000080  // PWM7 Fault
+#define PWM_FAULT_FAULT6        0x00000040  // PWM6 Fault
+#define PWM_FAULT_FAULT5        0x00000020  // PWM5 Fault
+#define PWM_FAULT_FAULT4        0x00000010  // PWM4 Fault
+#define PWM_FAULT_FAULT3        0x00000008  // PWM3 Fault
+#define PWM_FAULT_FAULT2        0x00000004  // PWM2 Fault
+#define PWM_FAULT_FAULT1        0x00000002  // PWM1 Fault
+#define PWM_FAULT_FAULT0        0x00000001  // PWM0 Fault
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_INTEN register.
+//
+//*****************************************************************************
+#define PWM_INTEN_INTFAULT3     0x00080000  // Interrupt Fault 3
+#define PWM_INTEN_INTFAULT2     0x00040000  // Interrupt Fault 2
+#define PWM_INTEN_INTFAULT1     0x00020000  // Interrupt Fault 1
+#define PWM_INTEN_INTFAULT      0x00010000  // Fault Interrupt Enable
+#define PWM_INTEN_INTFAULT0     0x00010000  // Interrupt Fault 0
+#define PWM_INTEN_INTPWM3       0x00000008  // PWM3 Interrupt Enable
+#define PWM_INTEN_INTPWM2       0x00000004  // PWM2 Interrupt Enable
+#define PWM_INTEN_INTPWM1       0x00000002  // PWM1 Interrupt Enable
+#define PWM_INTEN_INTPWM0       0x00000001  // PWM0 Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_RIS register.
+//
+//*****************************************************************************
+#define PWM_RIS_INTFAULT3       0x00080000  // Interrupt Fault PWM 3
+#define PWM_RIS_INTFAULT2       0x00040000  // Interrupt Fault PWM 2
+#define PWM_RIS_INTFAULT1       0x00020000  // Interrupt Fault PWM 1
+#define PWM_RIS_INTFAULT0       0x00010000  // Interrupt Fault PWM 0
+#define PWM_RIS_INTFAULT        0x00010000  // Fault Interrupt Asserted
+#define PWM_RIS_INTPWM3         0x00000008  // PWM3 Interrupt Asserted
+#define PWM_RIS_INTPWM2         0x00000004  // PWM2 Interrupt Asserted
+#define PWM_RIS_INTPWM1         0x00000002  // PWM1 Interrupt Asserted
+#define PWM_RIS_INTPWM0         0x00000001  // PWM0 Interrupt Asserted
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_ISC register.
+//
+//*****************************************************************************
+#define PWM_ISC_INTFAULT3       0x00080000  // FAULT3 Interrupt Asserted
+#define PWM_ISC_INTFAULT2       0x00040000  // FAULT2 Interrupt Asserted
+#define PWM_ISC_INTFAULT1       0x00020000  // FAULT1 Interrupt Asserted
+#define PWM_ISC_INTFAULT        0x00010000  // Fault Interrupt Asserted
+#define PWM_ISC_INTFAULT0       0x00010000  // FAULT0 Interrupt Asserted
+#define PWM_ISC_INTPWM3         0x00000008  // PWM3 Interrupt Status
+#define PWM_ISC_INTPWM2         0x00000004  // PWM2 Interrupt Status
+#define PWM_ISC_INTPWM1         0x00000002  // PWM1 Interrupt Status
+#define PWM_ISC_INTPWM0         0x00000001  // PWM0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_STATUS register.
+//
+//*****************************************************************************
+#define PWM_STATUS_FAULT3       0x00000008  // Generator 3 Fault Status
+#define PWM_STATUS_FAULT2       0x00000004  // Generator 2 Fault Status
+#define PWM_STATUS_FAULT1       0x00000002  // Generator 1 Fault Status
+#define PWM_STATUS_FAULT0       0x00000001  // Generator 0 Fault Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_FAULTVAL register.
+//
+//*****************************************************************************
+#define PWM_FAULTVAL_PWM7       0x00000080  // PWM7 Fault Value
+#define PWM_FAULTVAL_PWM6       0x00000040  // PWM6 Fault Value
+#define PWM_FAULTVAL_PWM5       0x00000020  // PWM5 Fault Value
+#define PWM_FAULTVAL_PWM4       0x00000010  // PWM4 Fault Value
+#define PWM_FAULTVAL_PWM3       0x00000008  // PWM3 Fault Value
+#define PWM_FAULTVAL_PWM2       0x00000004  // PWM2 Fault Value
+#define PWM_FAULTVAL_PWM1       0x00000002  // PWM1 Fault Value
+#define PWM_FAULTVAL_PWM0       0x00000001  // PWM0 Fault Value
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_ENUPD register.
+//
+//*****************************************************************************
+#define PWM_ENUPD_ENUPD7_M      0x0000C000  // PWM7 Enable Update Mode
+#define PWM_ENUPD_ENUPD7_IMM    0x00000000  // Immediate
+#define PWM_ENUPD_ENUPD7_LSYNC  0x00008000  // Locally Synchronized
+#define PWM_ENUPD_ENUPD7_GSYNC  0x0000C000  // Globally Synchronized
+#define PWM_ENUPD_ENUPD6_M      0x00003000  // PWM6 Enable Update Mode
+#define PWM_ENUPD_ENUPD6_IMM    0x00000000  // Immediate
+#define PWM_ENUPD_ENUPD6_LSYNC  0x00002000  // Locally Synchronized
+#define PWM_ENUPD_ENUPD6_GSYNC  0x00003000  // Globally Synchronized
+#define PWM_ENUPD_ENUPD5_M      0x00000C00  // PWM5 Enable Update Mode
+#define PWM_ENUPD_ENUPD5_IMM    0x00000000  // Immediate
+#define PWM_ENUPD_ENUPD5_LSYNC  0x00000800  // Locally Synchronized
+#define PWM_ENUPD_ENUPD5_GSYNC  0x00000C00  // Globally Synchronized
+#define PWM_ENUPD_ENUPD4_M      0x00000300  // PWM4 Enable Update Mode
+#define PWM_ENUPD_ENUPD4_IMM    0x00000000  // Immediate
+#define PWM_ENUPD_ENUPD4_LSYNC  0x00000200  // Locally Synchronized
+#define PWM_ENUPD_ENUPD4_GSYNC  0x00000300  // Globally Synchronized
+#define PWM_ENUPD_ENUPD3_M      0x000000C0  // PWM3 Enable Update Mode
+#define PWM_ENUPD_ENUPD3_IMM    0x00000000  // Immediate
+#define PWM_ENUPD_ENUPD3_LSYNC  0x00000080  // Locally Synchronized
+#define PWM_ENUPD_ENUPD3_GSYNC  0x000000C0  // Globally Synchronized
+#define PWM_ENUPD_ENUPD2_M      0x00000030  // PWM2 Enable Update Mode
+#define PWM_ENUPD_ENUPD2_IMM    0x00000000  // Immediate
+#define PWM_ENUPD_ENUPD2_LSYNC  0x00000020  // Locally Synchronized
+#define PWM_ENUPD_ENUPD2_GSYNC  0x00000030  // Globally Synchronized
+#define PWM_ENUPD_ENUPD1_M      0x0000000C  // PWM1 Enable Update Mode
+#define PWM_ENUPD_ENUPD1_IMM    0x00000000  // Immediate
+#define PWM_ENUPD_ENUPD1_LSYNC  0x00000008  // Locally Synchronized
+#define PWM_ENUPD_ENUPD1_GSYNC  0x0000000C  // Globally Synchronized
+#define PWM_ENUPD_ENUPD0_M      0x00000003  // PWM0 Enable Update Mode
+#define PWM_ENUPD_ENUPD0_IMM    0x00000000  // Immediate
+#define PWM_ENUPD_ENUPD0_LSYNC  0x00000002  // Locally Synchronized
+#define PWM_ENUPD_ENUPD0_GSYNC  0x00000003  // Globally Synchronized
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_CTL register.
+//
+//*****************************************************************************
+#define PWM_X_CTL_LATCH         0x00040000  // Latch Fault Input
+#define PWM_X_CTL_MINFLTPER     0x00020000  // Minimum Fault Period
+#define PWM_X_CTL_FLTSRC        0x00010000  // Fault Condition Source
+#define PWM_X_CTL_DBFALLUPD_M   0x0000C000  // PWMnDBFALL Update Mode
+#define PWM_X_CTL_DBFALLUPD_I   0x00000000  // Immediate
+#define PWM_X_CTL_DBFALLUPD_LS  0x00008000  // Locally Synchronized
+#define PWM_X_CTL_DBFALLUPD_GS  0x0000C000  // Globally Synchronized
+#define PWM_X_CTL_DBRISEUPD_M   0x00003000  // PWMnDBRISE Update Mode
+#define PWM_X_CTL_DBRISEUPD_I   0x00000000  // Immediate
+#define PWM_X_CTL_DBRISEUPD_LS  0x00002000  // Locally Synchronized
+#define PWM_X_CTL_DBRISEUPD_GS  0x00003000  // Globally Synchronized
+#define PWM_X_CTL_DBCTLUPD_M    0x00000C00  // PWMnDBCTL Update Mode
+#define PWM_X_CTL_DBCTLUPD_I    0x00000000  // Immediate
+#define PWM_X_CTL_DBCTLUPD_LS   0x00000800  // Locally Synchronized
+#define PWM_X_CTL_DBCTLUPD_GS   0x00000C00  // Globally Synchronized
+#define PWM_X_CTL_GENBUPD_M     0x00000300  // PWMnGENB Update Mode
+#define PWM_X_CTL_GENBUPD_I     0x00000000  // Immediate
+#define PWM_X_CTL_GENBUPD_LS    0x00000200  // Locally Synchronized
+#define PWM_X_CTL_GENBUPD_GS    0x00000300  // Globally Synchronized
+#define PWM_X_CTL_GENAUPD_M     0x000000C0  // PWMnGENA Update Mode
+#define PWM_X_CTL_GENAUPD_I     0x00000000  // Immediate
+#define PWM_X_CTL_GENAUPD_LS    0x00000080  // Locally Synchronized
+#define PWM_X_CTL_GENAUPD_GS    0x000000C0  // Globally Synchronized
+#define PWM_X_CTL_CMPBUPD       0x00000020  // Comparator B Update Mode
+#define PWM_X_CTL_CMPAUPD       0x00000010  // Comparator A Update Mode
+#define PWM_X_CTL_LOADUPD       0x00000008  // Load Register Update Mode
+#define PWM_X_CTL_DEBUG         0x00000004  // Debug Mode
+#define PWM_X_CTL_MODE          0x00000002  // Counter Mode
+#define PWM_X_CTL_ENABLE        0x00000001  // PWM Block Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_INTEN register.
+//
+//*****************************************************************************
+#define PWM_X_INTEN_TRCMPBD     0x00002000  // Trigger for Counter=PWMnCMPB
+                                            // Down
+#define PWM_X_INTEN_TRCMPBU     0x00001000  // Trigger for Counter=PWMnCMPB Up
+#define PWM_X_INTEN_TRCMPAD     0x00000800  // Trigger for Counter=PWMnCMPA
+                                            // Down
+#define PWM_X_INTEN_TRCMPAU     0x00000400  // Trigger for Counter=PWMnCMPA Up
+#define PWM_X_INTEN_TRCNTLOAD   0x00000200  // Trigger for Counter=PWMnLOAD
+#define PWM_X_INTEN_TRCNTZERO   0x00000100  // Trigger for Counter=0
+#define PWM_X_INTEN_INTCMPBD    0x00000020  // Interrupt for Counter=PWMnCMPB
+                                            // Down
+#define PWM_X_INTEN_INTCMPBU    0x00000010  // Interrupt for Counter=PWMnCMPB
+                                            // Up
+#define PWM_X_INTEN_INTCMPAD    0x00000008  // Interrupt for Counter=PWMnCMPA
+                                            // Down
+#define PWM_X_INTEN_INTCMPAU    0x00000004  // Interrupt for Counter=PWMnCMPA
+                                            // Up
+#define PWM_X_INTEN_INTCNTLOAD  0x00000002  // Interrupt for Counter=PWMnLOAD
+#define PWM_X_INTEN_INTCNTZERO  0x00000001  // Interrupt for Counter=0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_RIS register.
+//
+//*****************************************************************************
+#define PWM_X_RIS_INTCMPBD      0x00000020  // Comparator B Down Interrupt
+                                            // Status
+#define PWM_X_RIS_INTCMPBU      0x00000010  // Comparator B Up Interrupt Status
+#define PWM_X_RIS_INTCMPAD      0x00000008  // Comparator A Down Interrupt
+                                            // Status
+#define PWM_X_RIS_INTCMPAU      0x00000004  // Comparator A Up Interrupt Status
+#define PWM_X_RIS_INTCNTLOAD    0x00000002  // Counter=Load Interrupt Status
+#define PWM_X_RIS_INTCNTZERO    0x00000001  // Counter=0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_ISC register.
+//
+//*****************************************************************************
+#define PWM_X_ISC_INTCMPBD      0x00000020  // Comparator B Down Interrupt
+#define PWM_X_ISC_INTCMPBU      0x00000010  // Comparator B Up Interrupt
+#define PWM_X_ISC_INTCMPAD      0x00000008  // Comparator A Down Interrupt
+#define PWM_X_ISC_INTCMPAU      0x00000004  // Comparator A Up Interrupt
+#define PWM_X_ISC_INTCNTLOAD    0x00000002  // Counter=Load Interrupt
+#define PWM_X_ISC_INTCNTZERO    0x00000001  // Counter=0 Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_LOAD register.
+//
+//*****************************************************************************
+#define PWM_X_LOAD_M            0x0000FFFF  // Counter Load Value
+#define PWM_X_LOAD_S            0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_COUNT register.
+//
+//*****************************************************************************
+#define PWM_X_COUNT_M           0x0000FFFF  // Counter Value
+#define PWM_X_COUNT_S           0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_CMPA register.
+//
+//*****************************************************************************
+#define PWM_X_CMPA_M            0x0000FFFF  // Comparator A Value
+#define PWM_X_CMPA_S            0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_CMPB register.
+//
+//*****************************************************************************
+#define PWM_X_CMPB_M            0x0000FFFF  // Comparator B Value
+#define PWM_X_CMPB_S            0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_GENA register.
+//
+//*****************************************************************************
+#define PWM_X_GENA_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down
+#define PWM_X_GENA_ACTCMPBD_NONE \
+                                0x00000000  // Do nothing
+#define PWM_X_GENA_ACTCMPBD_INV 0x00000400  // Invert pwmA
+#define PWM_X_GENA_ACTCMPBD_ZERO \
+                                0x00000800  // Drive pwmA Low
+#define PWM_X_GENA_ACTCMPBD_ONE 0x00000C00  // Drive pwmA High
+#define PWM_X_GENA_ACTCMPBU_M   0x00000300  // Action for Comparator B Up
+#define PWM_X_GENA_ACTCMPBU_NONE \
+                                0x00000000  // Do nothing
+#define PWM_X_GENA_ACTCMPBU_INV 0x00000100  // Invert pwmA
+#define PWM_X_GENA_ACTCMPBU_ZERO \
+                                0x00000200  // Drive pwmA Low
+#define PWM_X_GENA_ACTCMPBU_ONE 0x00000300  // Drive pwmA High
+#define PWM_X_GENA_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down
+#define PWM_X_GENA_ACTCMPAD_NONE \
+                                0x00000000  // Do nothing
+#define PWM_X_GENA_ACTCMPAD_INV 0x00000040  // Invert pwmA
+#define PWM_X_GENA_ACTCMPAD_ZERO \
+                                0x00000080  // Drive pwmA Low
+#define PWM_X_GENA_ACTCMPAD_ONE 0x000000C0  // Drive pwmA High
+#define PWM_X_GENA_ACTCMPAU_M   0x00000030  // Action for Comparator A Up
+#define PWM_X_GENA_ACTCMPAU_NONE \
+                                0x00000000  // Do nothing
+#define PWM_X_GENA_ACTCMPAU_INV 0x00000010  // Invert pwmA
+#define PWM_X_GENA_ACTCMPAU_ZERO \
+                                0x00000020  // Drive pwmA Low
+#define PWM_X_GENA_ACTCMPAU_ONE 0x00000030  // Drive pwmA High
+#define PWM_X_GENA_ACTLOAD_M    0x0000000C  // Action for Counter=LOAD
+#define PWM_X_GENA_ACTLOAD_NONE 0x00000000  // Do nothing
+#define PWM_X_GENA_ACTLOAD_INV  0x00000004  // Invert pwmA
+#define PWM_X_GENA_ACTLOAD_ZERO 0x00000008  // Drive pwmA Low
+#define PWM_X_GENA_ACTLOAD_ONE  0x0000000C  // Drive pwmA High
+#define PWM_X_GENA_ACTZERO_M    0x00000003  // Action for Counter=0
+#define PWM_X_GENA_ACTZERO_NONE 0x00000000  // Do nothing
+#define PWM_X_GENA_ACTZERO_INV  0x00000001  // Invert pwmA
+#define PWM_X_GENA_ACTZERO_ZERO 0x00000002  // Drive pwmA Low
+#define PWM_X_GENA_ACTZERO_ONE  0x00000003  // Drive pwmA High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_GENB register.
+//
+//*****************************************************************************
+#define PWM_X_GENB_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down
+#define PWM_X_GENB_ACTCMPBD_NONE \
+                                0x00000000  // Do nothing
+#define PWM_X_GENB_ACTCMPBD_INV 0x00000400  // Invert pwmB
+#define PWM_X_GENB_ACTCMPBD_ZERO \
+                                0x00000800  // Drive pwmB Low
+#define PWM_X_GENB_ACTCMPBD_ONE 0x00000C00  // Drive pwmB High
+#define PWM_X_GENB_ACTCMPBU_M   0x00000300  // Action for Comparator B Up
+#define PWM_X_GENB_ACTCMPBU_NONE \
+                                0x00000000  // Do nothing
+#define PWM_X_GENB_ACTCMPBU_INV 0x00000100  // Invert pwmB
+#define PWM_X_GENB_ACTCMPBU_ZERO \
+                                0x00000200  // Drive pwmB Low
+#define PWM_X_GENB_ACTCMPBU_ONE 0x00000300  // Drive pwmB High
+#define PWM_X_GENB_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down
+#define PWM_X_GENB_ACTCMPAD_NONE \
+                                0x00000000  // Do nothing
+#define PWM_X_GENB_ACTCMPAD_INV 0x00000040  // Invert pwmB
+#define PWM_X_GENB_ACTCMPAD_ZERO \
+                                0x00000080  // Drive pwmB Low
+#define PWM_X_GENB_ACTCMPAD_ONE 0x000000C0  // Drive pwmB High
+#define PWM_X_GENB_ACTCMPAU_M   0x00000030  // Action for Comparator A Up
+#define PWM_X_GENB_ACTCMPAU_NONE \
+                                0x00000000  // Do nothing
+#define PWM_X_GENB_ACTCMPAU_INV 0x00000010  // Invert pwmB
+#define PWM_X_GENB_ACTCMPAU_ZERO \
+                                0x00000020  // Drive pwmB Low
+#define PWM_X_GENB_ACTCMPAU_ONE 0x00000030  // Drive pwmB High
+#define PWM_X_GENB_ACTLOAD_M    0x0000000C  // Action for Counter=LOAD
+#define PWM_X_GENB_ACTLOAD_NONE 0x00000000  // Do nothing
+#define PWM_X_GENB_ACTLOAD_INV  0x00000004  // Invert pwmB
+#define PWM_X_GENB_ACTLOAD_ZERO 0x00000008  // Drive pwmB Low
+#define PWM_X_GENB_ACTLOAD_ONE  0x0000000C  // Drive pwmB High
+#define PWM_X_GENB_ACTZERO_M    0x00000003  // Action for Counter=0
+#define PWM_X_GENB_ACTZERO_NONE 0x00000000  // Do nothing
+#define PWM_X_GENB_ACTZERO_INV  0x00000001  // Invert pwmB
+#define PWM_X_GENB_ACTZERO_ZERO 0x00000002  // Drive pwmB Low
+#define PWM_X_GENB_ACTZERO_ONE  0x00000003  // Drive pwmB High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_DBCTL register.
+//
+//*****************************************************************************
+#define PWM_X_DBCTL_ENABLE      0x00000001  // Dead-Band Generator Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_DBRISE register.
+//
+//*****************************************************************************
+#define PWM_X_DBRISE_DELAY_M    0x00000FFF  // Dead-Band Rise Delay
+#define PWM_X_DBRISE_DELAY_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_DBFALL register.
+//
+//*****************************************************************************
+#define PWM_X_DBFALL_DELAY_M    0x00000FFF  // Dead-Band Fall Delay
+#define PWM_X_DBFALL_DELAY_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_FLTSRC0
 // register.
 //
 //*****************************************************************************
-#define PWM_CTL_GLOBALSYNC3     0x00000008  // Update PWM Generator 3.
-#define PWM_CTL_GLOBALSYNC2     0x00000004  // Update PWM Generator 2.
-#define PWM_CTL_GLOBALSYNC1     0x00000002  // Update PWM Generator 1.
-#define PWM_CTL_GLOBALSYNC0     0x00000001  // Update PWM Generator 0.
+#define PWM_X_FLTSRC0_FAULT3    0x00000008  // Fault3 Input
+#define PWM_X_FLTSRC0_FAULT2    0x00000004  // Fault2 Input
+#define PWM_X_FLTSRC0_FAULT1    0x00000002  // Fault1 Input
+#define PWM_X_FLTSRC0_FAULT0    0x00000001  // Fault0 Input
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the PWM Time Base Sync
+// The following are defines for the bit fields in the PWM_O_X_FLTSRC1
 // register.
 //
 //*****************************************************************************
-#define PWM_SYNC_SYNC3          0x00000008  // Reset generator 3 counter
-#define PWM_SYNC_SYNC2          0x00000004  // Reset generator 2 counter
-#define PWM_SYNC_SYNC1          0x00000002  // Reset generator 1 counter
-#define PWM_SYNC_SYNC0          0x00000001  // Reset generator 0 counter
+#define PWM_X_FLTSRC1_DCMP7     0x00000080  // Digital Comparator 7
+#define PWM_X_FLTSRC1_DCMP6     0x00000040  // Digital Comparator 6
+#define PWM_X_FLTSRC1_DCMP5     0x00000020  // Digital Comparator 5
+#define PWM_X_FLTSRC1_DCMP4     0x00000010  // Digital Comparator 4
+#define PWM_X_FLTSRC1_DCMP3     0x00000008  // Digital Comparator 3
+#define PWM_X_FLTSRC1_DCMP2     0x00000004  // Digital Comparator 2
+#define PWM_X_FLTSRC1_DCMP1     0x00000002  // Digital Comparator 1
+#define PWM_X_FLTSRC1_DCMP0     0x00000001  // Digital Comparator 0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the PWM Output Enable
+// The following are defines for the bit fields in the PWM_O_X_MINFLTPER
 // register.
 //
 //*****************************************************************************
-#define PWM_ENABLE_PWM7EN       0x00000080  // PWM7 pin enable
-#define PWM_ENABLE_PWM6EN       0x00000040  // PWM6 pin enable
-#define PWM_ENABLE_PWM5EN       0x00000020  // PWM5 pin enable
-#define PWM_ENABLE_PWM4EN       0x00000010  // PWM4 pin enable
-#define PWM_ENABLE_PWM3EN       0x00000008  // PWM3 pin enable
-#define PWM_ENABLE_PWM2EN       0x00000004  // PWM2 pin enable
-#define PWM_ENABLE_PWM1EN       0x00000002  // PWM1 pin enable
-#define PWM_ENABLE_PWM0EN       0x00000001  // PWM0 pin enable
+#define PWM_X_MINFLTPER_M       0x0000FFFF  // Minimum Fault Period
+#define PWM_X_MINFLTPER_S       0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the PWM Inversion register.
+// The following are defines for the bit fields in the PWM_O_X_FLTSEN register.
 //
 //*****************************************************************************
-#define PWM_INVERT_PWM7INV      0x00000080  // PWM7 pin invert
-#define PWM_INVERT_PWM6INV      0x00000040  // PWM6 pin invert
-#define PWM_INVERT_PWM5INV      0x00000020  // PWM5 pin invert
-#define PWM_INVERT_PWM4INV      0x00000010  // PWM4 pin invert
-#define PWM_INVERT_PWM3INV      0x00000008  // PWM3 pin invert
-#define PWM_INVERT_PWM2INV      0x00000004  // PWM2 pin invert
-#define PWM_INVERT_PWM1INV      0x00000002  // PWM1 pin invert
-#define PWM_INVERT_PWM0INV      0x00000001  // PWM0 pin invert
+#define PWM_X_FLTSEN_FAULT3     0x00000008  // Fault3 Sense
+#define PWM_X_FLTSEN_FAULT2     0x00000004  // Fault2 Sense
+#define PWM_X_FLTSEN_FAULT1     0x00000002  // Fault1 Sense
+#define PWM_X_FLTSEN_FAULT0     0x00000001  // Fault0 Sense
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the PWM Fault register.
+// The following are defines for the bit fields in the PWM_O_X_FLTSTAT0
+// register.
 //
 //*****************************************************************************
-#define PWM_FAULT_FAULT7        0x00000080  // PWM7 pin fault
-#define PWM_FAULT_FAULT6        0x00000040  // PWM6 pin fault
-#define PWM_FAULT_FAULT5        0x00000020  // PWM5 pin fault
-#define PWM_FAULT_FAULT4        0x00000010  // PWM4 pin fault
-#define PWM_FAULT_FAULT3        0x00000008  // PWM3 pin fault
-#define PWM_FAULT_FAULT2        0x00000004  // PWM2 pin fault
-#define PWM_FAULT_FAULT1        0x00000002  // PWM1 pin fault
-#define PWM_FAULT_FAULT0        0x00000001  // PWM0 pin fault
+#define PWM_X_FLTSTAT0_FAULT3   0x00000008  // Fault Input 3
+#define PWM_X_FLTSTAT0_FAULT2   0x00000004  // Fault Input 2
+#define PWM_X_FLTSTAT0_FAULT1   0x00000002  // Fault Input 1
+#define PWM_X_FLTSTAT0_FAULT0   0x00000001  // Fault Input 0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the PWM Status register.
+// The following are defines for the bit fields in the PWM_O_X_FLTSTAT1
+// register.
 //
 //*****************************************************************************
-#define PWM_STATUS_FAULT3       0x00000008  // Fault3 Interrupt Status.
-#define PWM_STATUS_FAULT2       0x00000004  // Fault2 Interrupt Status.
-#define PWM_STATUS_FAULT1       0x00000002  // Fault1 Interrupt Status.
-#define PWM_STATUS_FAULT0       0x00000001  // Fault0 Interrupt Status.
+#define PWM_X_FLTSTAT1_DCMP7    0x00000080  // Digital Comparator 7 Trigger
+#define PWM_X_FLTSTAT1_DCMP6    0x00000040  // Digital Comparator 6 Trigger
+#define PWM_X_FLTSTAT1_DCMP5    0x00000020  // Digital Comparator 5 Trigger
+#define PWM_X_FLTSTAT1_DCMP4    0x00000010  // Digital Comparator 4 Trigger
+#define PWM_X_FLTSTAT1_DCMP3    0x00000008  // Digital Comparator 3 Trigger
+#define PWM_X_FLTSTAT1_DCMP2    0x00000004  // Digital Comparator 2 Trigger
+#define PWM_X_FLTSTAT1_DCMP1    0x00000002  // Digital Comparator 1 Trigger
+#define PWM_X_FLTSTAT1_DCMP0    0x00000001  // Digital Comparator 0 Trigger
 
 //*****************************************************************************
 //
@@ -227,42 +620,6 @@
 #define PWM_GEN_2_OFFSET        0x000000C0  // PWM2 base
 #define PWM_GEN_3_OFFSET        0x00000100  // PWM3 base
 
-//*****************************************************************************
-//
-// The following are defines for the PWM_X Control Register bit definitions.
-//
-//*****************************************************************************
-#define PWM_X_CTL_LATCH         0x00040000  // Latch Fault Input.
-#define PWM_X_CTL_MINFLTPER     0x00020000  // Minimum fault period enabled
-#define PWM_X_CTL_FLTSRC        0x00010000  // Fault Condition Source.
-#define PWM_X_CTL_DBFALLUPD_M   0x0000C000  // Specifies the update mode for
-                                            // the PWMnDBFALL register.
-#define PWM_X_CTL_DBFALLUPD_I   0x00000000  // Immediate
-#define PWM_X_CTL_DBFALLUPD_LS  0x00008000  // Locally Synchronized
-#define PWM_X_CTL_DBFALLUPD_GS  0x0000C000  // Globally Synchronized
-#define PWM_X_CTL_DBRISEUPD_M   0x00003000  // PWMnDBRISE Update Mode.
-#define PWM_X_CTL_DBRISEUPD_I   0x00000000  // Immediate
-#define PWM_X_CTL_DBRISEUPD_LS  0x00002000  // Locally Synchronized
-#define PWM_X_CTL_DBRISEUPD_GS  0x00003000  // Globally Synchronized
-#define PWM_X_CTL_DBCTLUPD_M    0x00000C00  // PWMnDBCTL Update Mode.
-#define PWM_X_CTL_DBCTLUPD_I    0x00000000  // Immediate
-#define PWM_X_CTL_DBCTLUPD_LS   0x00000800  // Locally Synchronized
-#define PWM_X_CTL_DBCTLUPD_GS   0x00000C00  // Globally Synchronized
-#define PWM_X_CTL_GENBUPD_M     0x00000300  // PWMnGENB Update Mode.
-#define PWM_X_CTL_GENBUPD_I     0x00000000  // Immediate
-#define PWM_X_CTL_GENBUPD_LS    0x00000200  // Locally Synchronized
-#define PWM_X_CTL_GENBUPD_GS    0x00000300  // Globally Synchronized
-#define PWM_X_CTL_GENAUPD_M     0x000000C0  // PWMnGENA Update Mode.
-#define PWM_X_CTL_GENAUPD_I     0x00000000  // Immediate
-#define PWM_X_CTL_GENAUPD_LS    0x00000080  // Locally Synchronized
-#define PWM_X_CTL_GENAUPD_GS    0x000000C0  // Globally Synchronized
-#define PWM_X_CTL_CMPBUPD       0x00000020  // Update mode for comp B reg
-#define PWM_X_CTL_CMPAUPD       0x00000010  // Update mode for comp A reg
-#define PWM_X_CTL_LOADUPD       0x00000008  // Update mode for the load reg
-#define PWM_X_CTL_DEBUG         0x00000004  // Debug mode
-#define PWM_X_CTL_MODE          0x00000002  // Counter mode, down or up/down
-#define PWM_X_CTL_ENABLE        0x00000001  // Master enable for gen block
-
 //*****************************************************************************
 //
 // The following are defines for the PWM Generator extended offsets.
@@ -276,323 +633,6 @@
 #define PWM_EXT_2_OFFSET        0x00000900  // PWM2 extended base
 #define PWM_EXT_3_OFFSET        0x00000980  // PWM3 extended base
 
-//*****************************************************************************
-//
-// The following are defines for the PWM_X Interrupt/Trigger Enable Register
-// bit definitions.
-//
-//*****************************************************************************
-#define PWM_X_INTEN_TRCMPBD     0x00002000  // Trig if COUNT = CMPB D
-#define PWM_X_INTEN_TRCMPBU     0x00001000  // Trig if COUNT = CMPB U
-#define PWM_X_INTEN_TRCMPAD     0x00000800  // Trig if COUNT = CMPA D
-#define PWM_X_INTEN_TRCMPAU     0x00000400  // Trig if COUNT = CMPA U
-#define PWM_X_INTEN_TRCNTLOAD   0x00000200  // Trig if COUNT = LOAD
-#define PWM_X_INTEN_TRCNTZERO   0x00000100  // Trig if COUNT = 0
-#define PWM_X_INTEN_INTCMPBD    0x00000020  // Int if COUNT = CMPA D
-#define PWM_X_INTEN_INTCMPBU    0x00000010  // Int if COUNT = CMPA U
-#define PWM_X_INTEN_INTCMPAD    0x00000008  // Int if COUNT = CMPA D
-#define PWM_X_INTEN_INTCMPAU    0x00000004  // Int if COUNT = CMPA U
-#define PWM_X_INTEN_INTCNTLOAD  0x00000002  // Int if COUNT = LOAD
-#define PWM_X_INTEN_INTCNTZERO  0x00000001  // Int if COUNT = 0
-
-//*****************************************************************************
-//
-// The following are defines for the PWM_X Raw Interrupt Status Register bit
-// definitions.
-//
-//*****************************************************************************
-#define PWM_X_RIS_INTCMPBD      0x00000020  // PWM_X_COUNT = PWM_X_CMPB D int
-#define PWM_X_RIS_INTCMPBU      0x00000010  // PWM_X_COUNT = PWM_X_CMPB U int
-#define PWM_X_RIS_INTCMPAD      0x00000008  // PWM_X_COUNT = PWM_X_CMPA D int
-#define PWM_X_RIS_INTCMPAU      0x00000004  // PWM_X_COUNT = PWM_X_CMPA U int
-#define PWM_X_RIS_INTCNTLOAD    0x00000002  // PWM_X_COUNT = PWM_X_LOAD int
-#define PWM_X_RIS_INTCNTZERO    0x00000001  // PWM_X_COUNT = 0 int
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the PWM_O_INTEN register.
-//
-//*****************************************************************************
-#define PWM_INTEN_INTFAULT3     0x00080000  // Interrupt Fault 3.
-#define PWM_INTEN_INTFAULT2     0x00040000  // Interrupt Fault 2.
-#define PWM_INTEN_INTFAULT1     0x00020000  // Interrupt Fault 1.
-#define PWM_INTEN_INTFAULT      0x00010000  // Fault Interrupt Enable.
-#define PWM_INTEN_INTFAULT0     0x00010000  // Interrupt Fault 0.
-#define PWM_INTEN_INTPWM3       0x00000008  // PWM3 Interrupt Enable.
-#define PWM_INTEN_INTPWM2       0x00000004  // PWM2 Interrupt Enable.
-#define PWM_INTEN_INTPWM1       0x00000002  // PWM1 Interrupt Enable.
-#define PWM_INTEN_INTPWM0       0x00000001  // PWM0 Interrupt Enable.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the PWM_O_RIS register.
-//
-//*****************************************************************************
-#define PWM_RIS_INTFAULT3       0x00080000  // Interrupt Fault PWM 3.
-#define PWM_RIS_INTFAULT2       0x00040000  // Interrupt Fault PWM 2.
-#define PWM_RIS_INTFAULT1       0x00020000  // Interrupt Fault PWM 1.
-#define PWM_RIS_INTFAULT0       0x00010000  // Interrupt Fault PWM 0.
-#define PWM_RIS_INTFAULT        0x00010000  // Fault Interrupt Asserted.
-#define PWM_RIS_INTPWM3         0x00000008  // PWM3 Interrupt Asserted.
-#define PWM_RIS_INTPWM2         0x00000004  // PWM2 Interrupt Asserted.
-#define PWM_RIS_INTPWM1         0x00000002  // PWM1 Interrupt Asserted.
-#define PWM_RIS_INTPWM0         0x00000001  // PWM0 Interrupt Asserted.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the PWM_O_ISC register.
-//
-//*****************************************************************************
-#define PWM_ISC_INTFAULT3       0x00080000  // FAULT3 Interrupt Asserted.
-#define PWM_ISC_INTFAULT2       0x00040000  // FAULT2 Interrupt Asserted.
-#define PWM_ISC_INTFAULT1       0x00020000  // FAULT1 Interrupt Asserted.
-#define PWM_ISC_INTFAULT        0x00010000  // Fault Interrupt Asserted.
-#define PWM_ISC_INTFAULT0       0x00010000  // FAULT0 Interrupt Asserted.
-#define PWM_ISC_INTPWM3         0x00000008  // PWM3 Interrupt Status.
-#define PWM_ISC_INTPWM2         0x00000004  // PWM2 Interrupt Status.
-#define PWM_ISC_INTPWM1         0x00000002  // PWM1 Interrupt Status.
-#define PWM_ISC_INTPWM0         0x00000001  // PWM0 Interrupt Status.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the PWM_O_X_ISC register.
-//
-//*****************************************************************************
-#define PWM_X_ISC_INTCMPBD      0x00000020  // Comparator B Down Interrupt.
-#define PWM_X_ISC_INTCMPBU      0x00000010  // Comparator B Up Interrupt.
-#define PWM_X_ISC_INTCMPAD      0x00000008  // Comparator A Down Interrupt.
-#define PWM_X_ISC_INTCMPAU      0x00000004  // Comparator A Up Interrupt.
-#define PWM_X_ISC_INTCNTLOAD    0x00000002  // Counter=Load Interrupt.
-#define PWM_X_ISC_INTCNTZERO    0x00000001  // Counter=0 Interrupt.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the PWM_O_X_LOAD register.
-//
-//*****************************************************************************
-#define PWM_X_LOAD_M            0x0000FFFF  // Counter Load Value.
-#define PWM_X_LOAD_S            0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the PWM_O_X_COUNT register.
-//
-//*****************************************************************************
-#define PWM_X_COUNT_M           0x0000FFFF  // Counter Value.
-#define PWM_X_COUNT_S           0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the PWM_O_X_CMPA register.
-//
-//*****************************************************************************
-#define PWM_X_CMPA_M            0x0000FFFF  // Comparator A Value.
-#define PWM_X_CMPA_S            0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the PWM_O_X_CMPB register.
-//
-//*****************************************************************************
-#define PWM_X_CMPB_M            0x0000FFFF  // Comparator B Value.
-#define PWM_X_CMPB_S            0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the PWM_O_X_GENA register.
-//
-//*****************************************************************************
-#define PWM_X_GENA_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down.
-#define PWM_X_GENA_ACTCMPBD_NONE \
-                                0x00000000  // Do nothing.
-#define PWM_X_GENA_ACTCMPBD_INV 0x00000400  // Invert the output signal.
-#define PWM_X_GENA_ACTCMPBD_ZERO \
-                                0x00000800  // Set the output signal to 0.
-#define PWM_X_GENA_ACTCMPBD_ONE 0x00000C00  // Set the output signal to 1.
-#define PWM_X_GENA_ACTCMPBU_M   0x00000300  // Action for Comparator B Up.
-#define PWM_X_GENA_ACTCMPBU_NONE \
-                                0x00000000  // Do nothing.
-#define PWM_X_GENA_ACTCMPBU_INV 0x00000100  // Invert the output signal.
-#define PWM_X_GENA_ACTCMPBU_ZERO \
-                                0x00000200  // Set the output signal to 0.
-#define PWM_X_GENA_ACTCMPBU_ONE 0x00000300  // Set the output signal to 1.
-#define PWM_X_GENA_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down.
-#define PWM_X_GENA_ACTCMPAD_NONE \
-                                0x00000000  // Do nothing.
-#define PWM_X_GENA_ACTCMPAD_INV 0x00000040  // Invert the output signal.
-#define PWM_X_GENA_ACTCMPAD_ZERO \
-                                0x00000080  // Set the output signal to 0.
-#define PWM_X_GENA_ACTCMPAD_ONE 0x000000C0  // Set the output signal to 1.
-#define PWM_X_GENA_ACTCMPAU_M   0x00000030  // Action for Comparator A Up.
-#define PWM_X_GENA_ACTCMPAU_NONE \
-                                0x00000000  // Do nothing.
-#define PWM_X_GENA_ACTCMPAU_INV 0x00000010  // Invert the output signal.
-#define PWM_X_GENA_ACTCMPAU_ZERO \
-                                0x00000020  // Set the output signal to 0.
-#define PWM_X_GENA_ACTCMPAU_ONE 0x00000030  // Set the output signal to 1.
-#define PWM_X_GENA_ACTLOAD_M    0x0000000C  // Action for Counter=Load.
-#define PWM_X_GENA_ACTLOAD_NONE 0x00000000  // Do nothing.
-#define PWM_X_GENA_ACTLOAD_INV  0x00000004  // Invert the output signal.
-#define PWM_X_GENA_ACTLOAD_ZERO 0x00000008  // Set the output signal to 0.
-#define PWM_X_GENA_ACTLOAD_ONE  0x0000000C  // Set the output signal to 1.
-#define PWM_X_GENA_ACTZERO_M    0x00000003  // Action for Counter=0.
-#define PWM_X_GENA_ACTZERO_NONE 0x00000000  // Do nothing.
-#define PWM_X_GENA_ACTZERO_INV  0x00000001  // Invert the output signal.
-#define PWM_X_GENA_ACTZERO_ZERO 0x00000002  // Set the output signal to 0.
-#define PWM_X_GENA_ACTZERO_ONE  0x00000003  // Set the output signal to 1.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the PWM_O_X_GENB register.
-//
-//*****************************************************************************
-#define PWM_X_GENB_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down.
-#define PWM_X_GENB_ACTCMPBD_NONE \
-                                0x00000000  // Do nothing.
-#define PWM_X_GENB_ACTCMPBD_INV 0x00000400  // Invert the output signal.
-#define PWM_X_GENB_ACTCMPBD_ZERO \
-                                0x00000800  // Set the output signal to 0.
-#define PWM_X_GENB_ACTCMPBD_ONE 0x00000C00  // Set the output signal to 1.
-#define PWM_X_GENB_ACTCMPBU_M   0x00000300  // Action for Comparator B Up.
-#define PWM_X_GENB_ACTCMPBU_NONE \
-                                0x00000000  // Do nothing.
-#define PWM_X_GENB_ACTCMPBU_INV 0x00000100  // Invert the output signal.
-#define PWM_X_GENB_ACTCMPBU_ZERO \
-                                0x00000200  // Set the output signal to 0.
-#define PWM_X_GENB_ACTCMPBU_ONE 0x00000300  // Set the output signal to 1.
-#define PWM_X_GENB_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down.
-#define PWM_X_GENB_ACTCMPAD_NONE \
-                                0x00000000  // Do nothing.
-#define PWM_X_GENB_ACTCMPAD_INV 0x00000040  // Invert the output signal.
-#define PWM_X_GENB_ACTCMPAD_ZERO \
-                                0x00000080  // Set the output signal to 0.
-#define PWM_X_GENB_ACTCMPAD_ONE 0x000000C0  // Set the output signal to 1.
-#define PWM_X_GENB_ACTCMPAU_M   0x00000030  // Action for Comparator A Up.
-#define PWM_X_GENB_ACTCMPAU_NONE \
-                                0x00000000  // Do nothing.
-#define PWM_X_GENB_ACTCMPAU_INV 0x00000010  // Invert the output signal.
-#define PWM_X_GENB_ACTCMPAU_ZERO \
-                                0x00000020  // Set the output signal to 0.
-#define PWM_X_GENB_ACTCMPAU_ONE 0x00000030  // Set the output signal to 1.
-#define PWM_X_GENB_ACTLOAD_M    0x0000000C  // Action for Counter=Load.
-#define PWM_X_GENB_ACTLOAD_NONE 0x00000000  // Do nothing.
-#define PWM_X_GENB_ACTLOAD_INV  0x00000004  // Invert the output signal.
-#define PWM_X_GENB_ACTLOAD_ZERO 0x00000008  // Set the output signal to 0.
-#define PWM_X_GENB_ACTLOAD_ONE  0x0000000C  // Set the output signal to 1.
-#define PWM_X_GENB_ACTZERO_M    0x00000003  // Action for Counter=0.
-#define PWM_X_GENB_ACTZERO_NONE 0x00000000  // Do nothing.
-#define PWM_X_GENB_ACTZERO_INV  0x00000001  // Invert the output signal.
-#define PWM_X_GENB_ACTZERO_ZERO 0x00000002  // Set the output signal to 0.
-#define PWM_X_GENB_ACTZERO_ONE  0x00000003  // Set the output signal to 1.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the PWM_O_X_DBCTL register.
-//
-//*****************************************************************************
-#define PWM_X_DBCTL_ENABLE      0x00000001  // Dead-Band Generator Enable.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the PWM_O_X_DBRISE register.
-//
-//*****************************************************************************
-#define PWM_X_DBRISE_DELAY_M    0x00000FFF  // Dead-Band Rise Delay.
-#define PWM_X_DBRISE_DELAY_S    0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the PWM_O_X_DBFALL register.
-//
-//*****************************************************************************
-#define PWM_X_DBFALL_DELAY_M    0x00000FFF  // Dead-Band Fall Delay.
-#define PWM_X_DBFALL_DELAY_S    0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the PWM_O_FAULTVAL register.
-//
-//*****************************************************************************
-#define PWM_FAULTVAL_PWM7       0x00000080  // PWM7 Fault Value.
-#define PWM_FAULTVAL_PWM6       0x00000040  // PWM6 Fault Value.
-#define PWM_FAULTVAL_PWM5       0x00000020  // PWM5 Fault Value.
-#define PWM_FAULTVAL_PWM4       0x00000010  // PWM4 Fault Value.
-#define PWM_FAULTVAL_PWM3       0x00000008  // PWM3 Fault Value.
-#define PWM_FAULTVAL_PWM2       0x00000004  // PWM2 Fault Value.
-#define PWM_FAULTVAL_PWM1       0x00000002  // PWM1 Fault Value.
-#define PWM_FAULTVAL_PWM0       0x00000001  // PWM0 Fault Value.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the PWM_O_X_MINFLTPER
-// register.
-//
-//*****************************************************************************
-#define PWM_X_MINFLTPER_M       0x0000FFFF  // Minimum Fault Period.
-#define PWM_X_MINFLTPER_S       0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the PWM_O_X_FLTSEN register.
-//
-//*****************************************************************************
-#define PWM_X_FLTSEN_FAULT3     0x00000008  // Fault3 Sense.
-#define PWM_X_FLTSEN_FAULT2     0x00000004  // Fault2 Sense.
-#define PWM_X_FLTSEN_FAULT1     0x00000002  // Fault1 Sense.
-#define PWM_X_FLTSEN_FAULT0     0x00000001  // Fault0 Sense.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the PWM_O_X_FLTSRC0
-// register.
-//
-//*****************************************************************************
-#define PWM_X_FLTSRC0_FAULT3    0x00000008  // Fault3.
-#define PWM_X_FLTSRC0_FAULT2    0x00000004  // Fault2.
-#define PWM_X_FLTSRC0_FAULT1    0x00000002  // Fault1.
-#define PWM_X_FLTSRC0_FAULT0    0x00000001  // Fault0.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the PWM_O_X_FLTSTAT0
-// register.
-//
-//*****************************************************************************
-#define PWM_X_FLTSTAT0_FAULT3   0x00000008  // Fault Input 3.
-#define PWM_X_FLTSTAT0_FAULT2   0x00000004  // Fault Input 2.
-#define PWM_X_FLTSTAT0_FAULT1   0x00000002  // Fault Input 1.
-#define PWM_X_FLTSTAT0_FAULT0   0x00000001  // Fault Input 0.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the PWM_O_X_FLTSRC1
-// register.
-//
-//*****************************************************************************
-#define PWM_X_FLTSRC1_DCMP7     0x00000080  // Digital Comparator 7.
-#define PWM_X_FLTSRC1_DCMP6     0x00000040  // Digital Comparator 6.
-#define PWM_X_FLTSRC1_DCMP5     0x00000020  // Digital Comparator 5.
-#define PWM_X_FLTSRC1_DCMP4     0x00000010  // Digital Comparator 4.
-#define PWM_X_FLTSRC1_DCMP3     0x00000008  // Digital Comparator 3.
-#define PWM_X_FLTSRC1_DCMP2     0x00000004  // Digital Comparator 2.
-#define PWM_X_FLTSRC1_DCMP1     0x00000002  // Digital Comparator 1.
-#define PWM_X_FLTSRC1_DCMP0     0x00000001  // Digital Comparator 0.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the PWM_O_X_FLTSTAT1
-// register.
-//
-//*****************************************************************************
-#define PWM_X_FLTSTAT1_DCMP7    0x00000080  // Digital Comparator 7 Trigger.
-#define PWM_X_FLTSTAT1_DCMP6    0x00000040  // Digital Comparator 6 Trigger.
-#define PWM_X_FLTSTAT1_DCMP5    0x00000020  // Digital Comparator 5 Trigger.
-#define PWM_X_FLTSTAT1_DCMP4    0x00000010  // Digital Comparator 4 Trigger.
-#define PWM_X_FLTSTAT1_DCMP3    0x00000008  // Digital Comparator 3 Trigger.
-#define PWM_X_FLTSTAT1_DCMP2    0x00000004  // Digital Comparator 2 Trigger.
-#define PWM_X_FLTSTAT1_DCMP1    0x00000002  // Digital Comparator 1 Trigger.
-#define PWM_X_FLTSTAT1_DCMP0    0x00000001  // Digital Comparator 0 Trigger.
-
 //*****************************************************************************
 //
 // The following definitions are deprecated.
@@ -602,14 +642,22 @@
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the bit fields in the PWM Master
-// Control register.
+// The following are deprecated defines for the bit fields in the PWM_O_CTL
+// register.
 //
 //*****************************************************************************
 #define PWM_CTL_GLOBAL_SYNC2    0x00000004  // Global sync generator 2
 #define PWM_CTL_GLOBAL_SYNC1    0x00000002  // Global sync generator 1
 #define PWM_CTL_GLOBAL_SYNC0    0x00000001  // Global sync generator 0
 
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the PWM_O_STATUS
+// register.
+//
+//*****************************************************************************
+#define PWM_STATUS_FAULT        0x00000001  // Fault Interrupt Status
+
 //*****************************************************************************
 //
 // The following are deprecated defines for the PWM Interrupt Register bit
@@ -618,14 +666,6 @@
 //*****************************************************************************
 #define PWM_INT_INTFAULT        0x00010000  // Fault interrupt pending
 
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the PWM Status
-// register.
-//
-//*****************************************************************************
-#define PWM_STATUS_FAULT        0x00000001  // Fault status
-
 //*****************************************************************************
 //
 // The following are deprecated defines for the PWM_X Interrupt Status Register
diff --git a/src/platform/lm3s/inc/hw_qei.h b/src/platform/lm3s/inc/hw_qei.h
new file mode 100755
index 00000000..3325d536
--- /dev/null
+++ b/src/platform/lm3s/inc/hw_qei.h
@@ -0,0 +1,201 @@
+//*****************************************************************************
+//
+// hw_qei.h - Macros used when accessing the QEI hardware.
+//
+// Copyright (c) 2005-2011 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 7611 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_QEI_H__
+#define __HW_QEI_H__
+
+//*****************************************************************************
+//
+// The following are defines for the QEI register offsets.
+//
+//*****************************************************************************
+#define QEI_O_CTL               0x00000000  // QEI Control
+#define QEI_O_STAT              0x00000004  // QEI Status
+#define QEI_O_POS               0x00000008  // QEI Position
+#define QEI_O_MAXPOS            0x0000000C  // QEI Maximum Position
+#define QEI_O_LOAD              0x00000010  // QEI Timer Load
+#define QEI_O_TIME              0x00000014  // QEI Timer
+#define QEI_O_COUNT             0x00000018  // QEI Velocity Counter
+#define QEI_O_SPEED             0x0000001C  // QEI Velocity
+#define QEI_O_INTEN             0x00000020  // QEI Interrupt Enable
+#define QEI_O_RIS               0x00000024  // QEI Raw Interrupt Status
+#define QEI_O_ISC               0x00000028  // QEI Interrupt Status and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_CTL register.
+//
+//*****************************************************************************
+#define QEI_CTL_FILTCNT_M       0x000F0000  // Input Filter Prescale Count
+#define QEI_CTL_FILTEN          0x00002000  // Enable Input Filter
+#define QEI_CTL_STALLEN         0x00001000  // Stall QEI
+#define QEI_CTL_INVI            0x00000800  // Invert Index Pulse
+#define QEI_CTL_INVB            0x00000400  // Invert PhB
+#define QEI_CTL_INVA            0x00000200  // Invert PhA
+#define QEI_CTL_VELDIV_M        0x000001C0  // Predivide Velocity
+#define QEI_CTL_VELDIV_1        0x00000000  // QEI clock /1
+#define QEI_CTL_VELDIV_2        0x00000040  // QEI clock /2
+#define QEI_CTL_VELDIV_4        0x00000080  // QEI clock /4
+#define QEI_CTL_VELDIV_8        0x000000C0  // QEI clock /8
+#define QEI_CTL_VELDIV_16       0x00000100  // QEI clock /16
+#define QEI_CTL_VELDIV_32       0x00000140  // QEI clock /32
+#define QEI_CTL_VELDIV_64       0x00000180  // QEI clock /64
+#define QEI_CTL_VELDIV_128      0x000001C0  // QEI clock /128
+#define QEI_CTL_VELEN           0x00000020  // Capture Velocity
+#define QEI_CTL_RESMODE         0x00000010  // Reset Mode
+#define QEI_CTL_CAPMODE         0x00000008  // Capture Mode
+#define QEI_CTL_SIGMODE         0x00000004  // Signal Mode
+#define QEI_CTL_SWAP            0x00000002  // Swap Signals
+#define QEI_CTL_ENABLE          0x00000001  // Enable QEI
+#define QEI_CTL_FILTCNT_S       16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_STAT register.
+//
+//*****************************************************************************
+#define QEI_STAT_DIRECTION      0x00000002  // Direction of Rotation
+#define QEI_STAT_ERROR          0x00000001  // Error Detected
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_POS register.
+//
+//*****************************************************************************
+#define QEI_POS_M               0xFFFFFFFF  // Current Position Integrator
+                                            // Value
+#define QEI_POS_S               0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_MAXPOS register.
+//
+//*****************************************************************************
+#define QEI_MAXPOS_M            0xFFFFFFFF  // Maximum Position Integrator
+                                            // Value
+#define QEI_MAXPOS_S            0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_LOAD register.
+//
+//*****************************************************************************
+#define QEI_LOAD_M              0xFFFFFFFF  // Velocity Timer Load Value
+#define QEI_LOAD_S              0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_TIME register.
+//
+//*****************************************************************************
+#define QEI_TIME_M              0xFFFFFFFF  // Velocity Timer Current Value
+#define QEI_TIME_S              0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_COUNT register.
+//
+//*****************************************************************************
+#define QEI_COUNT_M             0xFFFFFFFF  // Velocity Pulse Count
+#define QEI_COUNT_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_SPEED register.
+//
+//*****************************************************************************
+#define QEI_SPEED_M             0xFFFFFFFF  // Velocity
+#define QEI_SPEED_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_INTEN register.
+//
+//*****************************************************************************
+#define QEI_INTEN_ERROR         0x00000008  // Phase Error Interrupt Enable
+#define QEI_INTEN_DIR           0x00000004  // Direction Change Interrupt
+                                            // Enable
+#define QEI_INTEN_TIMER         0x00000002  // Timer Expires Interrupt Enable
+#define QEI_INTEN_INDEX         0x00000001  // Index Pulse Detected Interrupt
+                                            // Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_RIS register.
+//
+//*****************************************************************************
+#define QEI_RIS_ERROR           0x00000008  // Phase Error Detected
+#define QEI_RIS_DIR             0x00000004  // Direction Change Detected
+#define QEI_RIS_TIMER           0x00000002  // Velocity Timer Expired
+#define QEI_RIS_INDEX           0x00000001  // Index Pulse Asserted
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_ISC register.
+//
+//*****************************************************************************
+#define QEI_ISC_ERROR           0x00000008  // Phase Error Interrupt
+#define QEI_ISC_DIR             0x00000004  // Direction Change Interrupt
+#define QEI_ISC_TIMER           0x00000002  // Velocity Timer Expired Interrupt
+#define QEI_ISC_INDEX           0x00000001  // Index Pulse Interrupt
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the QEI_ISC
+// register.
+//
+//*****************************************************************************
+#define QEI_INT_ERROR           0x00000008  // Phase error detected
+#define QEI_INT_DIR             0x00000004  // Direction change
+#define QEI_INT_TIMER           0x00000002  // Velocity timer expired
+#define QEI_INT_INDEX           0x00000001  // Index pulse detected
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the reset values for the QEI
+// registers.
+//
+//*****************************************************************************
+#define QEI_RV_POS              0x00000000  // Current position register
+#define QEI_RV_LOAD             0x00000000  // Velocity timer load register
+#define QEI_RV_CTL              0x00000000  // Configuration and control reg
+#define QEI_RV_RIS              0x00000000  // Raw interrupt status register
+#define QEI_RV_ISC              0x00000000  // Interrupt status register
+#define QEI_RV_SPEED            0x00000000  // Velocity speed register
+#define QEI_RV_INTEN            0x00000000  // Interrupt enable register
+#define QEI_RV_STAT             0x00000000  // Status register
+#define QEI_RV_COUNT            0x00000000  // Velocity pulse count register
+#define QEI_RV_MAXPOS           0x00000000  // Maximum position register
+#define QEI_RV_TIME             0x00000000  // Velocity timer register
+
+#endif
+
+#endif // __HW_QEI_H__
diff --git a/src/platform/lm3s/hw_ssi.h b/src/platform/lm3s/inc/hw_ssi.h
similarity index 57%
rename from src/platform/lm3s/hw_ssi.h
rename to src/platform/lm3s/inc/hw_ssi.h
index 59c3bb9f..81414f6c 100755
--- a/src/platform/lm3s/hw_ssi.h
+++ b/src/platform/lm3s/inc/hw_ssi.h
@@ -2,26 +2,23 @@
 //
 // hw_ssi.h - Macros used when accessing the SSI hardware.
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2011 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4781 of the Stellaris Firmware Development Package.
+// This is part of revision 7611 of the Stellaris Firmware Development Package.
 //
 //*****************************************************************************
 
@@ -33,96 +30,96 @@
 // The following are defines for the SSI register offsets.
 //
 //*****************************************************************************
-#define SSI_O_CR0               0x00000000  // Control register 0
-#define SSI_O_CR1               0x00000004  // Control register 1
-#define SSI_O_DR                0x00000008  // Data register
-#define SSI_O_SR                0x0000000C  // Status register
-#define SSI_O_CPSR              0x00000010  // Clock prescale register
-#define SSI_O_IM                0x00000014  // Int mask set and clear register
-#define SSI_O_RIS               0x00000018  // Raw interrupt register
-#define SSI_O_MIS               0x0000001C  // Masked interrupt register
-#define SSI_O_ICR               0x00000020  // Interrupt clear register
+#define SSI_O_CR0               0x00000000  // SSI Control 0
+#define SSI_O_CR1               0x00000004  // SSI Control 1
+#define SSI_O_DR                0x00000008  // SSI Data
+#define SSI_O_SR                0x0000000C  // SSI Status
+#define SSI_O_CPSR              0x00000010  // SSI Clock Prescale
+#define SSI_O_IM                0x00000014  // SSI Interrupt Mask
+#define SSI_O_RIS               0x00000018  // SSI Raw Interrupt Status
+#define SSI_O_MIS               0x0000001C  // SSI Masked Interrupt Status
+#define SSI_O_ICR               0x00000020  // SSI Interrupt Clear
 #define SSI_O_DMACTL            0x00000024  // SSI DMA Control
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the SSI Control register 0.
+// The following are defines for the bit fields in the SSI_O_CR0 register.
 //
 //*****************************************************************************
-#define SSI_CR0_SCR_M           0x0000FF00  // SSI Serial Clock Rate.
-#define SSI_CR0_SPH             0x00000080  // SSPCLKOUT phase
-#define SSI_CR0_SPO             0x00000040  // SSPCLKOUT polarity
-#define SSI_CR0_FRF_M           0x00000030  // Frame format mask
-#define SSI_CR0_FRF_MOTO        0x00000000  // Motorola SPI frame format
-#define SSI_CR0_FRF_TI          0x00000010  // TI sync serial frame format
-#define SSI_CR0_FRF_NMW         0x00000020  // National Microwire frame format
-#define SSI_CR0_DSS_M           0x0000000F  // SSI Data Size Select.
-#define SSI_CR0_DSS_4           0x00000003  // 4 bit data
-#define SSI_CR0_DSS_5           0x00000004  // 5 bit data
-#define SSI_CR0_DSS_6           0x00000005  // 6 bit data
-#define SSI_CR0_DSS_7           0x00000006  // 7 bit data
-#define SSI_CR0_DSS_8           0x00000007  // 8 bit data
-#define SSI_CR0_DSS_9           0x00000008  // 9 bit data
-#define SSI_CR0_DSS_10          0x00000009  // 10 bit data
-#define SSI_CR0_DSS_11          0x0000000A  // 11 bit data
-#define SSI_CR0_DSS_12          0x0000000B  // 12 bit data
-#define SSI_CR0_DSS_13          0x0000000C  // 13 bit data
-#define SSI_CR0_DSS_14          0x0000000D  // 14 bit data
-#define SSI_CR0_DSS_15          0x0000000E  // 15 bit data
-#define SSI_CR0_DSS_16          0x0000000F  // 16 bit data
+#define SSI_CR0_SCR_M           0x0000FF00  // SSI Serial Clock Rate
+#define SSI_CR0_SPH             0x00000080  // SSI Serial Clock Phase
+#define SSI_CR0_SPO             0x00000040  // SSI Serial Clock Polarity
+#define SSI_CR0_FRF_M           0x00000030  // SSI Frame Format Select
+#define SSI_CR0_FRF_MOTO        0x00000000  // Freescale SPI Frame Format
+#define SSI_CR0_FRF_TI          0x00000010  // Texas Instruments Synchronous
+                                            // Serial Frame Format
+#define SSI_CR0_FRF_NMW         0x00000020  // MICROWIRE Frame Format
+#define SSI_CR0_DSS_M           0x0000000F  // SSI Data Size Select
+#define SSI_CR0_DSS_4           0x00000003  // 4-bit data
+#define SSI_CR0_DSS_5           0x00000004  // 5-bit data
+#define SSI_CR0_DSS_6           0x00000005  // 6-bit data
+#define SSI_CR0_DSS_7           0x00000006  // 7-bit data
+#define SSI_CR0_DSS_8           0x00000007  // 8-bit data
+#define SSI_CR0_DSS_9           0x00000008  // 9-bit data
+#define SSI_CR0_DSS_10          0x00000009  // 10-bit data
+#define SSI_CR0_DSS_11          0x0000000A  // 11-bit data
+#define SSI_CR0_DSS_12          0x0000000B  // 12-bit data
+#define SSI_CR0_DSS_13          0x0000000C  // 13-bit data
+#define SSI_CR0_DSS_14          0x0000000D  // 14-bit data
+#define SSI_CR0_DSS_15          0x0000000E  // 15-bit data
+#define SSI_CR0_DSS_16          0x0000000F  // 16-bit data
 #define SSI_CR0_SCR_S           8
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the SSI Control register 1.
+// The following are defines for the bit fields in the SSI_O_CR1 register.
 //
 //*****************************************************************************
-#define SSI_CR1_EOT             0x00000010  // End of Transmission.
-#define SSI_CR1_SOD             0x00000008  // Slave mode output disable
-#define SSI_CR1_MS              0x00000004  // Master or slave mode select
-#define SSI_CR1_SSE             0x00000002  // Sync serial port enable
-#define SSI_CR1_LBM             0x00000001  // Loopback mode
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SSI Status register.
-//
-//*****************************************************************************
-#define SSI_SR_BSY              0x00000010  // SSI busy
-#define SSI_SR_RFF              0x00000008  // RX FIFO full
-#define SSI_SR_RNE              0x00000004  // RX FIFO not empty
-#define SSI_SR_TNF              0x00000002  // TX FIFO not full
-#define SSI_SR_TFE              0x00000001  // TX FIFO empty
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SSI clock prescale
-// register.
-//
-//*****************************************************************************
-#define SSI_CPSR_CPSDVSR_M      0x000000FF  // SSI Clock Prescale Divisor.
-#define SSI_CPSR_CPSDVSR_S      0
+#define SSI_CR1_EOT             0x00000010  // End of Transmission
+#define SSI_CR1_SOD             0x00000008  // SSI Slave Mode Output Disable
+#define SSI_CR1_MS              0x00000004  // SSI Master/Slave Select
+#define SSI_CR1_SSE             0x00000002  // SSI Synchronous Serial Port
+                                            // Enable
+#define SSI_CR1_LBM             0x00000001  // SSI Loopback Mode
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SSI_O_DR register.
 //
 //*****************************************************************************
-#define SSI_DR_DATA_M           0x0000FFFF  // SSI Receive/Transmit Data.
+#define SSI_DR_DATA_M           0x0000FFFF  // SSI Receive/Transmit Data
 #define SSI_DR_DATA_S           0
 
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_SR register.
+//
+//*****************************************************************************
+#define SSI_SR_BSY              0x00000010  // SSI Busy Bit
+#define SSI_SR_RFF              0x00000008  // SSI Receive FIFO Full
+#define SSI_SR_RNE              0x00000004  // SSI Receive FIFO Not Empty
+#define SSI_SR_TNF              0x00000002  // SSI Transmit FIFO Not Full
+#define SSI_SR_TFE              0x00000001  // SSI Transmit FIFO Empty
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_CPSR register.
+//
+//*****************************************************************************
+#define SSI_CPSR_CPSDVSR_M      0x000000FF  // SSI Clock Prescale Divisor
+#define SSI_CPSR_CPSDVSR_S      0
+
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SSI_O_IM register.
 //
 //*****************************************************************************
-#define SSI_IM_TXIM             0x00000008  // SSI Transmit FIFO Interrupt
-                                            // Mask.
-#define SSI_IM_RXIM             0x00000004  // SSI Receive FIFO Interrupt Mask.
+#define SSI_IM_TXIM             0x00000008  // SSI Transmit FIFO Interrupt Mask
+#define SSI_IM_RXIM             0x00000004  // SSI Receive FIFO Interrupt Mask
 #define SSI_IM_RTIM             0x00000002  // SSI Receive Time-Out Interrupt
-                                            // Mask.
+                                            // Mask
 #define SSI_IM_RORIM            0x00000001  // SSI Receive Overrun Interrupt
-                                            // Mask.
+                                            // Mask
 
 //*****************************************************************************
 //
@@ -130,13 +127,13 @@
 //
 //*****************************************************************************
 #define SSI_RIS_TXRIS           0x00000008  // SSI Transmit FIFO Raw Interrupt
-                                            // Status.
+                                            // Status
 #define SSI_RIS_RXRIS           0x00000004  // SSI Receive FIFO Raw Interrupt
-                                            // Status.
+                                            // Status
 #define SSI_RIS_RTRIS           0x00000002  // SSI Receive Time-Out Raw
-                                            // Interrupt Status.
+                                            // Interrupt Status
 #define SSI_RIS_RORRIS          0x00000001  // SSI Receive Overrun Raw
-                                            // Interrupt Status.
+                                            // Interrupt Status
 
 //*****************************************************************************
 //
@@ -144,13 +141,13 @@
 //
 //*****************************************************************************
 #define SSI_MIS_TXMIS           0x00000008  // SSI Transmit FIFO Masked
-                                            // Interrupt Status.
+                                            // Interrupt Status
 #define SSI_MIS_RXMIS           0x00000004  // SSI Receive FIFO Masked
-                                            // Interrupt Status.
+                                            // Interrupt Status
 #define SSI_MIS_RTMIS           0x00000002  // SSI Receive Time-Out Masked
-                                            // Interrupt Status.
+                                            // Interrupt Status
 #define SSI_MIS_RORMIS          0x00000001  // SSI Receive Overrun Masked
-                                            // Interrupt Status.
+                                            // Interrupt Status
 
 //*****************************************************************************
 //
@@ -158,17 +155,17 @@
 //
 //*****************************************************************************
 #define SSI_ICR_RTIC            0x00000002  // SSI Receive Time-Out Interrupt
-                                            // Clear.
+                                            // Clear
 #define SSI_ICR_RORIC           0x00000001  // SSI Receive Overrun Interrupt
-                                            // Clear.
+                                            // Clear
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SSI_O_DMACTL register.
 //
 //*****************************************************************************
-#define SSI_DMACTL_TXDMAE       0x00000002  // Transmit DMA Enable.
-#define SSI_DMACTL_RXDMAE       0x00000001  // Receive DMA Enable.
+#define SSI_DMACTL_TXDMAE       0x00000002  // Transmit DMA Enable
+#define SSI_DMACTL_RXDMAE       0x00000001  // Receive DMA Enable
 
 //*****************************************************************************
 //
@@ -179,8 +176,8 @@
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the bit fields in the SSI Control
-// register 0.
+// The following are deprecated defines for the bit fields in the SSI_O_CR0
+// register.
 //
 //*****************************************************************************
 #define SSI_CR0_SCR             0x0000FF00  // Serial clock rate
@@ -189,8 +186,8 @@
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the bit fields in the SSI clock
-// prescale register.
+// The following are deprecated defines for the bit fields in the SSI_O_CPSR
+// register.
 //
 //*****************************************************************************
 #define SSI_CPSR_CPSDVSR_MASK   0x000000FF  // Clock prescale
diff --git a/src/platform/lm3s/hw_sysctl.h b/src/platform/lm3s/inc/hw_sysctl.h
similarity index 64%
rename from src/platform/lm3s/hw_sysctl.h
rename to src/platform/lm3s/inc/hw_sysctl.h
index 736ba588..28aabd4b 100755
--- a/src/platform/lm3s/hw_sysctl.h
+++ b/src/platform/lm3s/inc/hw_sysctl.h
@@ -2,26 +2,23 @@
 //
 // hw_sysctl.h - Macros used when accessing the system control hardware.
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2011 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4781 of the Stellaris Firmware Development Package.
+// This is part of revision 7611 of the Stellaris Firmware Development Package.
 //
 //*****************************************************************************
 
@@ -30,84 +27,103 @@
 
 //*****************************************************************************
 //
-// The following are defines for the system control register addresses.
+// The following are defines for the System Control register addresses.
 //
 //*****************************************************************************
-#define SYSCTL_DID0             0x400FE000  // Device identification register 0
-#define SYSCTL_DID1             0x400FE004  // Device identification register 1
-#define SYSCTL_DC0              0x400FE008  // Device capabilities register 0
-#define SYSCTL_DC1              0x400FE010  // Device capabilities register 1
-#define SYSCTL_DC2              0x400FE014  // Device capabilities register 2
-#define SYSCTL_DC3              0x400FE018  // Device capabilities register 3
-#define SYSCTL_DC4              0x400FE01C  // Device capabilities register 4
-#define SYSCTL_DC5              0x400FE020  // Device capabilities register 5
-#define SYSCTL_DC6              0x400FE024  // Device capabilities register 6
-#define SYSCTL_DC7              0x400FE028  // Device capabilities register 7
-#define SYSCTL_DC8              0x400FE02C  // Device capabilities register 8
-#define SYSCTL_PBORCTL          0x400FE030  // POR/BOR reset control register
-#define SYSCTL_LDOPCTL          0x400FE034  // LDO power control register
-#define SYSCTL_SRCR0            0x400FE040  // Software reset control reg 0
-#define SYSCTL_SRCR1            0x400FE044  // Software reset control reg 1
-#define SYSCTL_SRCR2            0x400FE048  // Software reset control reg 2
-#define SYSCTL_RIS              0x400FE050  // Raw interrupt status register
-#define SYSCTL_IMC              0x400FE054  // Interrupt mask/control register
-#define SYSCTL_MISC             0x400FE058  // Interrupt status register
-#define SYSCTL_RESC             0x400FE05C  // Reset cause register
-#define SYSCTL_RCC              0x400FE060  // Run-mode clock config register
-#define SYSCTL_PLLCFG           0x400FE064  // PLL configuration register
-#define SYSCTL_GPIOHSCTL        0x400FE06C  // GPIO High Speed Control
-#define SYSCTL_GPIOHBCTL        0x400FE06C  // GPIO Host-Bus Control
-#define SYSCTL_RCC2             0x400FE070  // Run-mode clock config register 2
+#define SYSCTL_DID0             0x400FE000  // Device Identification 0
+#define SYSCTL_DID1             0x400FE004  // Device Identification 1
+#define SYSCTL_DC0              0x400FE008  // Device Capabilities 0
+#define SYSCTL_DC1              0x400FE010  // Device Capabilities 1
+#define SYSCTL_DC2              0x400FE014  // Device Capabilities 2
+#define SYSCTL_DC3              0x400FE018  // Device Capabilities 3
+#define SYSCTL_DC4              0x400FE01C  // Device Capabilities 4
+#define SYSCTL_DC5              0x400FE020  // Device Capabilities 5
+#define SYSCTL_DC6              0x400FE024  // Device Capabilities 6
+#define SYSCTL_DC7              0x400FE028  // Device Capabilities 7
+#define SYSCTL_DC8              0x400FE02C  // Device Capabilities 8 ADC
+                                            // Channels
+#define SYSCTL_PBORCTL          0x400FE030  // Brown-Out Reset Control
+#define SYSCTL_LDOPCTL          0x400FE034  // LDO Power Control
+#define SYSCTL_SRCR0            0x400FE040  // Software Reset Control 0
+#define SYSCTL_SRCR1            0x400FE044  // Software Reset Control 1
+#define SYSCTL_SRCR2            0x400FE048  // Software Reset Control 2
+#define SYSCTL_RIS              0x400FE050  // Raw Interrupt Status
+#define SYSCTL_IMC              0x400FE054  // Interrupt Mask Control
+#define SYSCTL_MISC             0x400FE058  // Masked Interrupt Status and
+                                            // Clear
+#define SYSCTL_RESC             0x400FE05C  // Reset Cause
+#define SYSCTL_RCC              0x400FE060  // Run-Mode Clock Configuration
+#define SYSCTL_PLLCFG           0x400FE064  // XTAL to PLL Translation
+#define SYSCTL_GPIOHBCTL        0x400FE06C  // GPIO High-Performance Bus
+                                            // Control
+#define SYSCTL_RCC2             0x400FE070  // Run-Mode Clock Configuration 2
 #define SYSCTL_MOSCCTL          0x400FE07C  // Main Oscillator Control
-#define SYSCTL_PIOSCCTL         0x400FE088  // Precision internal oscillator
-                                            // control register
-#define SYSCTL_RCGC0            0x400FE100  // Run-mode clock gating register 0
-#define SYSCTL_RCGC1            0x400FE104  // Run-mode clock gating register 1
-#define SYSCTL_RCGC2            0x400FE108  // Run-mode clock gating register 2
-#define SYSCTL_SCGC0            0x400FE110  // Sleep-mode clock gating reg 0
-#define SYSCTL_SCGC1            0x400FE114  // Sleep-mode clock gating reg 1
-#define SYSCTL_SCGC2            0x400FE118  // Sleep-mode clock gating reg 2
-#define SYSCTL_DCGC0            0x400FE120  // Deep Sleep-mode clock gate reg 0
-#define SYSCTL_DCGC1            0x400FE124  // Deep Sleep-mode clock gate reg 1
-#define SYSCTL_DCGC2            0x400FE128  // Deep Sleep-mode clock gate reg 2
-#define SYSCTL_DSLPCLKCFG       0x400FE144  // Deep Sleep-mode clock config reg
-#define SYSCTL_DSFLASHCFG       0x400FE14C  // Deep Sleep Flash Configuration
-#define SYSCTL_CLKVCLR          0x400FE150  // Clock verifcation clear register
+#define SYSCTL_RCGC0            0x400FE100  // Run Mode Clock Gating Control
+                                            // Register 0
+#define SYSCTL_RCGC1            0x400FE104  // Run Mode Clock Gating Control
+                                            // Register 1
+#define SYSCTL_RCGC2            0x400FE108  // Run Mode Clock Gating Control
+                                            // Register 2
+#define SYSCTL_SCGC0            0x400FE110  // Sleep Mode Clock Gating Control
+                                            // Register 0
+#define SYSCTL_SCGC1            0x400FE114  // Sleep Mode Clock Gating Control
+                                            // Register 1
+#define SYSCTL_SCGC2            0x400FE118  // Sleep Mode Clock Gating Control
+                                            // Register 2
+#define SYSCTL_DCGC0            0x400FE120  // Deep Sleep Mode Clock Gating
+                                            // Control Register 0
+#define SYSCTL_DCGC1            0x400FE124  // Deep-Sleep Mode Clock Gating
+                                            // Control Register 1
+#define SYSCTL_DCGC2            0x400FE128  // Deep Sleep Mode Clock Gating
+                                            // Control Register 2
+#define SYSCTL_DSLPCLKCFG       0x400FE144  // Deep Sleep Clock Configuration
 #define SYSCTL_PIOSCCAL         0x400FE150  // Precision Internal Oscillator
                                             // Calibration
+#define SYSCTL_CLKVCLR          0x400FE150  // Clock Verification Clear
 #define SYSCTL_PIOSCSTAT        0x400FE154  // Precision Internal Oscillator
                                             // Statistics
-#define SYSCTL_LDOARST          0x400FE160  // LDO reset control register
+#define SYSCTL_LDOARST          0x400FE160  // Allow Unregulated LDO to Reset
+                                            // the Part
 #define SYSCTL_I2SMCLKCFG       0x400FE170  // I2S MCLK Configuration
-#define SYSCTL_DC9              0x400FE190  // Device capabilities register 9
-#define SYSCTL_NVMSTAT          0x400FE1A0  // Non-Volitile Memory Information
+#define SYSCTL_DC9              0x400FE190  // Device Capabilities 9 ADC
+                                            // Digital Comparators
+#define SYSCTL_NVMSTAT          0x400FE1A0  // Non-Volatile Memory Information
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_DID0 register.
 //
 //*****************************************************************************
-#define SYSCTL_DID0_VER_M       0x70000000  // DID0 version mask
-#define SYSCTL_DID0_VER_0       0x00000000  // DID0 version 0
-#define SYSCTL_DID0_VER_1       0x10000000  // DID0 version 1
+#define SYSCTL_DID0_VER_M       0x70000000  // DID0 Version
+#define SYSCTL_DID0_VER_0       0x00000000  // Initial DID0 register format
+                                            // definition for Stellaris(R)
+                                            // Sandstorm-class devices
+#define SYSCTL_DID0_VER_1       0x10000000  // Second version of the DID0
+                                            // register format
 #define SYSCTL_DID0_CLASS_M     0x00FF0000  // Device Class
 #define SYSCTL_DID0_CLASS_SANDSTORM \
                                 0x00000000  // Sandstorm-class Device
-#define SYSCTL_DID0_CLASS_FURY  0x00010000  // Fury-class Device
+#define SYSCTL_DID0_CLASS_FURY  0x00010000  // Stellaris(R) Fury-class devices
 #define SYSCTL_DID0_CLASS_DUSTDEVIL \
-                                0x00030000  // DustDevil-class Device
+                                0x00030000  // Stellaris(R) DustDevil-class
+                                            // devices
 #define SYSCTL_DID0_CLASS_TEMPEST \
-                                0x00040000  // Tempest-class Device
-#define SYSCTL_DID0_MAJ_M       0x0000FF00  // Major revision mask
+                                0x00040000  // Stellaris(R) Tempest-class
+                                            // microcontrollers
+#define SYSCTL_DID0_CLASS_FIRESTORM \
+                                0x00060000  // Stellaris(R) Firestorm-class
+                                            // microcontrollers
+#define SYSCTL_DID0_MAJ_M       0x0000FF00  // Major Revision
 #define SYSCTL_DID0_MAJ_REVA    0x00000000  // Revision A (initial device)
 #define SYSCTL_DID0_MAJ_REVB    0x00000100  // Revision B (first base layer
                                             // revision)
 #define SYSCTL_DID0_MAJ_REVC    0x00000200  // Revision C (second base layer
                                             // revision)
-#define SYSCTL_DID0_MIN_M       0x000000FF  // Minor revision mask
-#define SYSCTL_DID0_MIN_0       0x00000000  // Minor revision 0
-#define SYSCTL_DID0_MIN_1       0x00000001  // Minor revision 1
-#define SYSCTL_DID0_MIN_2       0x00000002  // Minor revision 2
+#define SYSCTL_DID0_MIN_M       0x000000FF  // Minor Revision
+#define SYSCTL_DID0_MIN_0       0x00000000  // Initial device, or a major
+                                            // revision update
+#define SYSCTL_DID0_MIN_1       0x00000001  // First metal layer change
+#define SYSCTL_DID0_MIN_2       0x00000002  // Second metal layer change
 #define SYSCTL_DID0_MIN_3       0x00000003  // Minor revision 3
 #define SYSCTL_DID0_MIN_4       0x00000004  // Minor revision 4
 #define SYSCTL_DID0_MIN_5       0x00000005  // Minor revision 5
@@ -117,26 +133,19 @@
 // The following are defines for the bit fields in the SYSCTL_DID1 register.
 //
 //*****************************************************************************
-#define SYSCTL_DID1_VER_M       0xF0000000  // DID1 Version.
+#define SYSCTL_DID1_VER_M       0xF0000000  // DID1 Version
 #define SYSCTL_DID1_VER_0       0x00000000  // Initial DID1 register format
                                             // definition, indicating a
-                                            // Stellaris LM3Snnn device.
-#define SYSCTL_DID1_VER_1       0x10000000  // First revision of the DID1
-                                            // register format, indicating a
-                                            // Stellaris Fury-class device.
-#define SYSCTL_DID1_FAM_M       0x0F000000  // Family.
+                                            // Stellaris LM3Snnn device
+#define SYSCTL_DID1_VER_1       0x10000000  // Second version of the DID1
+                                            // register format
+#define SYSCTL_DID1_FAM_M       0x0F000000  // Family
 #define SYSCTL_DID1_FAM_STELLARIS \
                                 0x00000000  // Stellaris family of
                                             // microcontollers, that is, all
                                             // devices with external part
-                                            // numbers starting with LM3S.
-#define SYSCTL_DID1_PRTNO_M     0x00FF0000  // Part number mask
-#define SYSCTL_DID1_PRTNO_2B93  0x006C0000  // LM3S2B93
-#define SYSCTL_DID1_PRTNO_5B91  0x00680000  // LM3S5B91
-#define SYSCTL_DID1_PRTNO_9B95  0x006E0000  // LM3S9B95
-#define SYSCTL_DID1_PRTNO_9B92  0x006A0000  // LM3S9B92
-#define SYSCTL_DID1_PRTNO_9B96  0x006F0000  // LM3S9B96
-#define SYSCTL_DID1_PRTNO_9B90  0x00660000  // LM3S9B90
+                                            // numbers starting with LM3S
+#define SYSCTL_DID1_PRTNO_M     0x00FF0000  // Part Number
 #define SYSCTL_DID1_PRTNO_101   0x00010000  // LM3S101
 #define SYSCTL_DID1_PRTNO_102   0x00020000  // LM3S102
 #define SYSCTL_DID1_PRTNO_300   0x00190000  // LM3S300
@@ -173,6 +182,7 @@
 #define SYSCTL_DID1_PRTNO_1150  0x00C10000  // LM3S1150
 #define SYSCTL_DID1_PRTNO_1162  0x00C40000  // LM3S1162
 #define SYSCTL_DID1_PRTNO_1165  0x00C20000  // LM3S1165
+#define SYSCTL_DID1_PRTNO_1166  0x00EC0000  // LM3S1166
 #define SYSCTL_DID1_PRTNO_1332  0x00C60000  // LM3S1332
 #define SYSCTL_DID1_PRTNO_1435  0x00BC0000  // LM3S1435
 #define SYSCTL_DID1_PRTNO_1439  0x00BA0000  // LM3S1439
@@ -182,13 +192,18 @@
 #define SYSCTL_DID1_PRTNO_1607  0x00060000  // LM3S1607
 #define SYSCTL_DID1_PRTNO_1608  0x00DA0000  // LM3S1608
 #define SYSCTL_DID1_PRTNO_1620  0x00C00000  // LM3S1620
+#define SYSCTL_DID1_PRTNO_1621  0x00CD0000  // LM3S1621
 #define SYSCTL_DID1_PRTNO_1625  0x00030000  // LM3S1625
 #define SYSCTL_DID1_PRTNO_1626  0x00040000  // LM3S1626
 #define SYSCTL_DID1_PRTNO_1627  0x00050000  // LM3S1627
 #define SYSCTL_DID1_PRTNO_1635  0x00B30000  // LM3S1635
+#define SYSCTL_DID1_PRTNO_1636  0x00EB0000  // LM3S1636
 #define SYSCTL_DID1_PRTNO_1637  0x00BD0000  // LM3S1637
+#define SYSCTL_DID1_PRTNO_1651  0x00B10000  // LM3S1651
 #define SYSCTL_DID1_PRTNO_1751  0x00B90000  // LM3S1751
 #define SYSCTL_DID1_PRTNO_1776  0x00100000  // LM3S1776
+#define SYSCTL_DID1_PRTNO_1811  0x00160000  // LM3S1811
+#define SYSCTL_DID1_PRTNO_1816  0x003D0000  // LM3S1816
 #define SYSCTL_DID1_PRTNO_1850  0x00B40000  // LM3S1850
 #define SYSCTL_DID1_PRTNO_1911  0x00DD0000  // LM3S1911
 #define SYSCTL_DID1_PRTNO_1918  0x00DC0000  // LM3S1918
@@ -196,6 +211,25 @@
 #define SYSCTL_DID1_PRTNO_1958  0x00BE0000  // LM3S1958
 #define SYSCTL_DID1_PRTNO_1960  0x00B50000  // LM3S1960
 #define SYSCTL_DID1_PRTNO_1968  0x00B80000  // LM3S1968
+#define SYSCTL_DID1_PRTNO_1969  0x00EA0000  // LM3S1969
+#define SYSCTL_DID1_PRTNO_1B21  0x00CE0000  // LM3S1B21
+#define SYSCTL_DID1_PRTNO_1C58  0x00980000  // LM3S1C58
+#define SYSCTL_DID1_PRTNO_1D21  0x00B00000  // LM3S1D21
+#define SYSCTL_DID1_PRTNO_1F11  0x001D0000  // LM3S1F11
+#define SYSCTL_DID1_PRTNO_1F16  0x001B0000  // LM3S1F16
+#define SYSCTL_DID1_PRTNO_1G21  0x00AF0000  // LM3S1G21
+#define SYSCTL_DID1_PRTNO_1G58  0x00950000  // LM3S1G58
+#define SYSCTL_DID1_PRTNO_1H11  0x001E0000  // LM3S1H11
+#define SYSCTL_DID1_PRTNO_1H16  0x001C0000  // LM3S1H16
+#define SYSCTL_DID1_PRTNO_1J11  0x000F0000  // LM3S1J11
+#define SYSCTL_DID1_PRTNO_1J16  0x003C0000  // LM3S1J16
+#define SYSCTL_DID1_PRTNO_1N11  0x000E0000  // LM3S1N11
+#define SYSCTL_DID1_PRTNO_1N16  0x003B0000  // LM3S1N16
+#define SYSCTL_DID1_PRTNO_1P51  0x00B20000  // LM3S1P51
+#define SYSCTL_DID1_PRTNO_1R21  0x009E0000  // LM3S1R21
+#define SYSCTL_DID1_PRTNO_1R26  0x00C90000  // LM3S1R26
+#define SYSCTL_DID1_PRTNO_1W16  0x00300000  // LM3S1W16
+#define SYSCTL_DID1_PRTNO_1Z16  0x002F0000  // LM3S1Z16
 #define SYSCTL_DID1_PRTNO_2110  0x00510000  // LM3S2110
 #define SYSCTL_DID1_PRTNO_2139  0x00840000  // LM3S2139
 #define SYSCTL_DID1_PRTNO_2276  0x00390000  // LM3S2276
@@ -217,16 +251,29 @@
 #define SYSCTL_DID1_PRTNO_2793  0x006D0000  // LM3S2793
 #define SYSCTL_DID1_PRTNO_2911  0x00E30000  // LM3S2911
 #define SYSCTL_DID1_PRTNO_2918  0x00E20000  // LM3S2918
+#define SYSCTL_DID1_PRTNO_2919  0x00ED0000  // LM3S2919
 #define SYSCTL_DID1_PRTNO_2939  0x00540000  // LM3S2939
 #define SYSCTL_DID1_PRTNO_2948  0x008F0000  // LM3S2948
 #define SYSCTL_DID1_PRTNO_2950  0x00580000  // LM3S2950
 #define SYSCTL_DID1_PRTNO_2965  0x00550000  // LM3S2965
+#define SYSCTL_DID1_PRTNO_2B93  0x006C0000  // LM3S2B93
+#define SYSCTL_DID1_PRTNO_2D93  0x00940000  // LM3S2D93
+#define SYSCTL_DID1_PRTNO_2U93  0x00930000  // LM3S2U93
+#define SYSCTL_DID1_PRTNO_3634  0x00080000  // LM3S3634
 #define SYSCTL_DID1_PRTNO_3651  0x00430000  // LM3S3651
+#define SYSCTL_DID1_PRTNO_3654  0x00C80000  // LM3S3654
 #define SYSCTL_DID1_PRTNO_3739  0x00440000  // LM3S3739
 #define SYSCTL_DID1_PRTNO_3748  0x00490000  // LM3S3748
 #define SYSCTL_DID1_PRTNO_3749  0x00450000  // LM3S3749
+#define SYSCTL_DID1_PRTNO_3826  0x00420000  // LM3S3826
+#define SYSCTL_DID1_PRTNO_3J26  0x00410000  // LM3S3J26
+#define SYSCTL_DID1_PRTNO_3N26  0x00400000  // LM3S3N26
+#define SYSCTL_DID1_PRTNO_3W26  0x003F0000  // LM3S3W26
+#define SYSCTL_DID1_PRTNO_3Z26  0x003E0000  // LM3S3Z26
 #define SYSCTL_DID1_PRTNO_5632  0x00810000  // LM3S5632
+#define SYSCTL_DID1_PRTNO_5651  0x000C0000  // LM3S5651
 #define SYSCTL_DID1_PRTNO_5652  0x008A0000  // LM3S5652
+#define SYSCTL_DID1_PRTNO_5656  0x004D0000  // LM3S5656
 #define SYSCTL_DID1_PRTNO_5662  0x00910000  // LM3S5662
 #define SYSCTL_DID1_PRTNO_5732  0x00960000  // LM3S5732
 #define SYSCTL_DID1_PRTNO_5737  0x00970000  // LM3S5737
@@ -236,6 +283,32 @@
 #define SYSCTL_DID1_PRTNO_5752  0x009A0000  // LM3S5752
 #define SYSCTL_DID1_PRTNO_5762  0x009C0000  // LM3S5762
 #define SYSCTL_DID1_PRTNO_5791  0x00690000  // LM3S5791
+#define SYSCTL_DID1_PRTNO_5951  0x000B0000  // LM3S5951
+#define SYSCTL_DID1_PRTNO_5956  0x004E0000  // LM3S5956
+#define SYSCTL_DID1_PRTNO_5B91  0x00680000  // LM3S5B91
+#define SYSCTL_DID1_PRTNO_5C31  0x002E0000  // LM3S5C31
+#define SYSCTL_DID1_PRTNO_5C36  0x002C0000  // LM3S5C36
+#define SYSCTL_DID1_PRTNO_5C51  0x005E0000  // LM3S5C51
+#define SYSCTL_DID1_PRTNO_5C56  0x005B0000  // LM3S5C56
+#define SYSCTL_DID1_PRTNO_5D51  0x005F0000  // LM3S5D51
+#define SYSCTL_DID1_PRTNO_5D56  0x005C0000  // LM3S5D56
+#define SYSCTL_DID1_PRTNO_5D91  0x00870000  // LM3S5D91
+#define SYSCTL_DID1_PRTNO_5G31  0x002D0000  // LM3S5G31
+#define SYSCTL_DID1_PRTNO_5G36  0x001F0000  // LM3S5G36
+#define SYSCTL_DID1_PRTNO_5G51  0x005D0000  // LM3S5G51
+#define SYSCTL_DID1_PRTNO_5G56  0x004F0000  // LM3S5G56
+#define SYSCTL_DID1_PRTNO_5K31  0x00090000  // LM3S5K31
+#define SYSCTL_DID1_PRTNO_5K36  0x004A0000  // LM3S5K36
+#define SYSCTL_DID1_PRTNO_5P31  0x000A0000  // LM3S5P31
+#define SYSCTL_DID1_PRTNO_5P36  0x00480000  // LM3S5P36
+#define SYSCTL_DID1_PRTNO_5P3B  0x00B60000  // LM3S5P3B
+#define SYSCTL_DID1_PRTNO_5P51  0x000D0000  // LM3S5P51
+#define SYSCTL_DID1_PRTNO_5P56  0x004C0000  // LM3S5P56
+#define SYSCTL_DID1_PRTNO_5R31  0x00070000  // LM3S5R31
+#define SYSCTL_DID1_PRTNO_5R36  0x004B0000  // LM3S5R36
+#define SYSCTL_DID1_PRTNO_5T36  0x00470000  // LM3S5T36
+#define SYSCTL_DID1_PRTNO_5U91  0x007F0000  // LM3S5U91
+#define SYSCTL_DID1_PRTNO_5Y36  0x00460000  // LM3S5Y36
 #define SYSCTL_DID1_PRTNO_6100  0x00A10000  // LM3S6100
 #define SYSCTL_DID1_PRTNO_6110  0x00740000  // LM3S6110
 #define SYSCTL_DID1_PRTNO_6420  0x00A50000  // LM3S6420
@@ -255,6 +328,10 @@
 #define SYSCTL_DID1_PRTNO_6950  0x00720000  // LM3S6950
 #define SYSCTL_DID1_PRTNO_6952  0x00780000  // LM3S6952
 #define SYSCTL_DID1_PRTNO_6965  0x00730000  // LM3S6965
+#define SYSCTL_DID1_PRTNO_6C11  0x00AA0000  // LM3S6C11
+#define SYSCTL_DID1_PRTNO_6C65  0x00AC0000  // LM3S6C65
+#define SYSCTL_DID1_PRTNO_6G11  0x009F0000  // LM3S6G11
+#define SYSCTL_DID1_PRTNO_6G65  0x00AB0000  // LM3S6G65
 #define SYSCTL_DID1_PRTNO_8530  0x00640000  // LM3S8530
 #define SYSCTL_DID1_PRTNO_8538  0x008E0000  // LM3S8538
 #define SYSCTL_DID1_PRTNO_8630  0x00610000  // LM3S8630
@@ -267,27 +344,61 @@
 #define SYSCTL_DID1_PRTNO_8962  0x00A60000  // LM3S8962
 #define SYSCTL_DID1_PRTNO_8970  0x00620000  // LM3S8970
 #define SYSCTL_DID1_PRTNO_8971  0x00D70000  // LM3S8971
+#define SYSCTL_DID1_PRTNO_8C62  0x00AE0000  // LM3S8C62
+#define SYSCTL_DID1_PRTNO_8G62  0x00AD0000  // LM3S8G62
+#define SYSCTL_DID1_PRTNO_9781  0x00CF0000  // LM3S9781
 #define SYSCTL_DID1_PRTNO_9790  0x00670000  // LM3S9790
 #define SYSCTL_DID1_PRTNO_9792  0x006B0000  // LM3S9792
-#define SYSCTL_DID1_PINCNT_M    0x0000E000  // Package Pin Count.
+#define SYSCTL_DID1_PRTNO_9971  0x002D0000  // LM3S9971
+#define SYSCTL_DID1_PRTNO_9997  0x00200000  // LM3S9997
+#define SYSCTL_DID1_PRTNO_9B81  0x00D00000  // LM3S9B81
+#define SYSCTL_DID1_PRTNO_9B90  0x00660000  // LM3S9B90
+#define SYSCTL_DID1_PRTNO_9B92  0x006A0000  // LM3S9B92
+#define SYSCTL_DID1_PRTNO_9B95  0x006E0000  // LM3S9B95
+#define SYSCTL_DID1_PRTNO_9B96  0x006F0000  // LM3S9B96
+#define SYSCTL_DID1_PRTNO_9BN2  0x001D0000  // LM3S9BN2
+#define SYSCTL_DID1_PRTNO_9BN5  0x001E0000  // LM3S9BN5
+#define SYSCTL_DID1_PRTNO_9BN6  0x001F0000  // LM3S9BN6
+#define SYSCTL_DID1_PRTNO_9C97  0x00700000  // LM3S9C97
+#define SYSCTL_DID1_PRTNO_9CN5  0x007A0000  // LM3S9CN5
+#define SYSCTL_DID1_PRTNO_9D81  0x00A90000  // LM3S9D81
+#define SYSCTL_DID1_PRTNO_9D90  0x007E0000  // LM3S9D90
+#define SYSCTL_DID1_PRTNO_9D92  0x00920000  // LM3S9D92
+#define SYSCTL_DID1_PRTNO_9D95  0x00C80000  // LM3S9D95
+#define SYSCTL_DID1_PRTNO_9D96  0x009D0000  // LM3S9D96
+#define SYSCTL_DID1_PRTNO_9DN5  0x007B0000  // LM3S9DN5
+#define SYSCTL_DID1_PRTNO_9DN6  0x007C0000  // LM3S9DN6
+#define SYSCTL_DID1_PRTNO_9G97  0x00600000  // LM3S9G97
+#define SYSCTL_DID1_PRTNO_9GN5  0x00790000  // LM3S9GN5
+#define SYSCTL_DID1_PRTNO_9L71  0x001B0000  // LM3S9L71
+#define SYSCTL_DID1_PRTNO_9L97  0x00180000  // LM3S9L97
+#define SYSCTL_DID1_PRTNO_9U81  0x00A80000  // LM3S9U81
+#define SYSCTL_DID1_PRTNO_9U90  0x007D0000  // LM3S9U90
+#define SYSCTL_DID1_PRTNO_9U92  0x00900000  // LM3S9U92
+#define SYSCTL_DID1_PRTNO_9U95  0x00B70000  // LM3S9U95
+#define SYSCTL_DID1_PRTNO_9U96  0x009B0000  // LM3S9U96
+#define SYSCTL_DID1_PINCNT_M    0x0000E000  // Package Pin Count
 #define SYSCTL_DID1_PINCNT_28   0x00000000  // 28 pin package
-#define SYSCTL_DID1_PINCNT_48   0x00002000  // 48 pin package
-#define SYSCTL_DID1_PINCNT_100  0x00004000  // 100 pin package
-#define SYSCTL_DID1_PINCNT_64   0x00006000  // 64 pin package
-#define SYSCTL_DID1_TEMP_M      0x000000E0  // Temperature range mask
-#define SYSCTL_DID1_TEMP_C      0x00000000  // Commercial temp range (0..70C)
-#define SYSCTL_DID1_TEMP_I      0x00000020  // Industrial temp range (-40..85C)
+#define SYSCTL_DID1_PINCNT_48   0x00002000  // 48-pin package
+#define SYSCTL_DID1_PINCNT_100  0x00004000  // 100-pin package
+#define SYSCTL_DID1_PINCNT_64   0x00006000  // 64-pin package
+#define SYSCTL_DID1_TEMP_M      0x000000E0  // Temperature Range
+#define SYSCTL_DID1_TEMP_C      0x00000000  // Commercial temperature range (0C
+                                            // to 70C)
+#define SYSCTL_DID1_TEMP_I      0x00000020  // Industrial temperature range
+                                            // (-40C to 85C)
 #define SYSCTL_DID1_TEMP_E      0x00000040  // Extended temperature range (-40C
                                             // to 105C)
-#define SYSCTL_DID1_PKG_M       0x00000018  // Package Type.
-#define SYSCTL_DID1_PKG_28SOIC  0x00000000  // 28-pin SOIC
-#define SYSCTL_DID1_PKG_48QFP   0x00000008  // 48-pin QFP
+#define SYSCTL_DID1_PKG_M       0x00000018  // Package Type
+#define SYSCTL_DID1_PKG_SOIC    0x00000000  // SOIC package
+#define SYSCTL_DID1_PKG_QFP     0x00000008  // LQFP package
 #define SYSCTL_DID1_PKG_BGA     0x00000010  // BGA package
-#define SYSCTL_DID1_ROHS        0x00000004  // Part is RoHS compliant
-#define SYSCTL_DID1_QUAL_M      0x00000003  // Qualification status mask
-#define SYSCTL_DID1_QUAL_ES     0x00000000  // Engineering sample (unqualified)
-#define SYSCTL_DID1_QUAL_PP     0x00000001  // Pilot production (unqualified)
-#define SYSCTL_DID1_QUAL_FQ     0x00000002  // Fully qualified
+#define SYSCTL_DID1_PKG_QFN     0x00000018  // QFN package
+#define SYSCTL_DID1_ROHS        0x00000004  // RoHS-Compliance
+#define SYSCTL_DID1_QUAL_M      0x00000003  // Qualification Status
+#define SYSCTL_DID1_QUAL_ES     0x00000000  // Engineering Sample (unqualified)
+#define SYSCTL_DID1_QUAL_PP     0x00000001  // Pilot Production (unqualified)
+#define SYSCTL_DID1_QUAL_FQ     0x00000002  // Fully Qualified
 #define SYSCTL_DID1_PRTNO_S     16          // Part number shift
 
 //*****************************************************************************
@@ -295,22 +406,29 @@
 // The following are defines for the bit fields in the SYSCTL_DC0 register.
 //
 //*****************************************************************************
-#define SYSCTL_DC0_SRAMSZ_M     0xFFFF0000  // SRAM size mask
+#define SYSCTL_DC0_SRAMSZ_M     0xFFFF0000  // SRAM Size
 #define SYSCTL_DC0_SRAMSZ_2KB   0x00070000  // 2 KB of SRAM
 #define SYSCTL_DC0_SRAMSZ_4KB   0x000F0000  // 4 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_6KB   0x00170000  // 6 KB of SRAM
 #define SYSCTL_DC0_SRAMSZ_8KB   0x001F0000  // 8 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_12KB  0x002F0000  // 12 KB of SRAM
 #define SYSCTL_DC0_SRAMSZ_16KB  0x003F0000  // 16 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_20KB  0x004F0000  // 20 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_24KB  0x005F0000  // 24 KB of SRAM
 #define SYSCTL_DC0_SRAMSZ_32KB  0x007F0000  // 32 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_48KB  0x00BF0000  // 48 KB of SRAM
 #define SYSCTL_DC0_SRAMSZ_64KB  0x00FF0000  // 64 KB of SRAM
 #define SYSCTL_DC0_SRAMSZ_96KB  0x017F0000  // 96 KB of SRAM
-#define SYSCTL_DC0_FLASHSZ_M    0x0000FFFF  // Flash size mask
-#define SYSCTL_DC0_FLASHSZ_8KB  0x00000003  // 8 KB of flash
-#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007  // 16 KB of flash
-#define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F  // 32 KB of flash
-#define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F  // 64 KB of flash
-#define SYSCTL_DC0_FLASHSZ_96KB 0x0000002F  // 96 KB of flash
-#define SYSCTL_DC0_FLASHSZ_128K 0x0000003F  // 128 KB of flash
-#define SYSCTL_DC0_FLASHSZ_256K 0x0000007F  // 256 KB of flash
+#define SYSCTL_DC0_FLASHSZ_M    0x0000FFFF  // Flash Size
+#define SYSCTL_DC0_FLASHSZ_8KB  0x00000003  // 8 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007  // 16 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F  // 32 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F  // 64 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_96KB 0x0000002F  // 96 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_128K 0x0000003F  // 128 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_256K 0x0000007F  // 256 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_384K 0x000000BF  // 384 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_512K 0x000000FF  // 512 KB of Flash
 #define SYSCTL_DC0_SRAMSZ_S     16          // SRAM size shift
 #define SYSCTL_DC0_FLASHSZ_S    0           // Flash size shift
 
@@ -319,103 +437,102 @@
 // The following are defines for the bit fields in the SYSCTL_DC1 register.
 //
 //*****************************************************************************
-#define SYSCTL_DC1_WDT1         0x10000000  // Watchdog Timer1 Present.
-#define SYSCTL_DC1_CAN2         0x04000000  // CAN2 module present
-#define SYSCTL_DC1_CAN1         0x02000000  // CAN1 module present
-#define SYSCTL_DC1_CAN0         0x01000000  // CAN0 module present
-#define SYSCTL_DC1_PWM          0x00100000  // PWM module present
-#define SYSCTL_DC1_ADC1         0x00020000  // ADC Module 1 Present.
-#define SYSCTL_DC1_ADC0         0x00010000  // ADC Module 0 Present.
-#define SYSCTL_DC1_MINSYSDIV_M  0x0000F000  // System Clock Divider.
+#define SYSCTL_DC1_WDT1         0x10000000  // Watchdog Timer1 Present
+#define SYSCTL_DC1_CAN2         0x04000000  // CAN Module 2 Present
+#define SYSCTL_DC1_CAN1         0x02000000  // CAN Module 1 Present
+#define SYSCTL_DC1_CAN0         0x01000000  // CAN Module 0 Present
+#define SYSCTL_DC1_PWM          0x00100000  // PWM Module Present
+#define SYSCTL_DC1_ADC1         0x00020000  // ADC Module 1 Present
+#define SYSCTL_DC1_ADC0         0x00010000  // ADC Module 0 Present
+#define SYSCTL_DC1_MINSYSDIV_M  0x0000F000  // System Clock Divider
 #define SYSCTL_DC1_MINSYSDIV_100 \
-                                0x00001000  // Specifies a 100-MHz clock with a
-                                            // PLL divider of 2.
-#define SYSCTL_DC1_MINSYSDIV_66 0x00002000  // Specifies a 66-MHz clock with a
-                                            // PLL divider of 3.
-#define SYSCTL_DC1_MINSYSDIV_50 0x00003000  // Specifies a 50-MHz clock with a
-                                            // PLL divider of 4.
+                                0x00001000  // Divide VCO (400MHZ) by 5 minimum
+#define SYSCTL_DC1_MINSYSDIV_66 0x00002000  // Divide VCO (400MHZ) by 2*2 + 2 =
+                                            // 6 minimum
+#define SYSCTL_DC1_MINSYSDIV_50 0x00003000  // Specifies a 50-MHz CPU clock
+                                            // with a PLL divider of 4
 #define SYSCTL_DC1_MINSYSDIV_25 0x00007000  // Specifies a 25-MHz clock with a
-                                            // PLL divider of 8.
+                                            // PLL divider of 8
 #define SYSCTL_DC1_MINSYSDIV_20 0x00009000  // Specifies a 20-MHz clock with a
-                                            // PLL divider of 10.
-#define SYSCTL_DC1_ADCSPD_M     0x00000F00  // ADC speed mask
+                                            // PLL divider of 10
+#define SYSCTL_DC1_ADCSPD_M     0x00000F00  // Max ADC Speed
 #define SYSCTL_DC1_ADCSPD_125K  0x00000000  // 125Ksps ADC
-#define SYSCTL_DC1_ADCSPD_250K  0x00000100  // 250Ksps ADC
-#define SYSCTL_DC1_ADCSPD_500K  0x00000200  // 500Ksps ADC
-#define SYSCTL_DC1_ADCSPD_1M    0x00000300  // 1Msps ADC
-#define SYSCTL_DC1_ADC1SPD_M    0x00000C00  // Max ADC1 Speed.
+#define SYSCTL_DC1_ADCSPD_250K  0x00000100  // 250K samples/second
+#define SYSCTL_DC1_ADCSPD_500K  0x00000200  // 500K samples/second
+#define SYSCTL_DC1_ADCSPD_1M    0x00000300  // 1M samples/second
+#define SYSCTL_DC1_ADC1SPD_M    0x00000C00  // Max ADC1 Speed
 #define SYSCTL_DC1_ADC1SPD_1M   0x00000C00  // 1M samples/second
-#define SYSCTL_DC1_ADC0SPD_M    0x00000300  // Max ADC0 Speed.
+#define SYSCTL_DC1_ADC0SPD_M    0x00000300  // Max ADC0 Speed
 #define SYSCTL_DC1_ADC0SPD_1M   0x00000300  // 1M samples/second
-#define SYSCTL_DC1_MPU          0x00000080  // Cortex M3 MPU present
-#define SYSCTL_DC1_HIB          0x00000040  // Hibernation module present
-#define SYSCTL_DC1_TEMP         0x00000020  // Temperature sensor present
-#define SYSCTL_DC1_PLL          0x00000010  // PLL present
-#define SYSCTL_DC1_WDT0         0x00000008  // Watchdog Timer 0 Present.
-#define SYSCTL_DC1_SWO          0x00000004  // Serial wire output present
-#define SYSCTL_DC1_SWD          0x00000002  // Serial wire debug present
-#define SYSCTL_DC1_JTAG         0x00000001  // JTAG debug present
+#define SYSCTL_DC1_MPU          0x00000080  // MPU Present
+#define SYSCTL_DC1_HIB          0x00000040  // Hibernation Module Present
+#define SYSCTL_DC1_TEMP         0x00000020  // Temp Sensor Present
+#define SYSCTL_DC1_PLL          0x00000010  // PLL Present
+#define SYSCTL_DC1_WDT0         0x00000008  // Watchdog Timer 0 Present
+#define SYSCTL_DC1_SWO          0x00000004  // SWO Trace Port Present
+#define SYSCTL_DC1_SWD          0x00000002  // SWD Present
+#define SYSCTL_DC1_JTAG         0x00000001  // JTAG Present
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_DC2 register.
 //
 //*****************************************************************************
-#define SYSCTL_DC2_EPI0         0x40000000  // EPI0 Present.
-#define SYSCTL_DC2_I2S0         0x10000000  // I2S 0 Present.
-#define SYSCTL_DC2_COMP2        0x04000000  // Analog comparator 2 present
-#define SYSCTL_DC2_COMP1        0x02000000  // Analog comparator 1 present
-#define SYSCTL_DC2_COMP0        0x01000000  // Analog comparator 0 present
-#define SYSCTL_DC2_TIMER3       0x00080000  // Timer 3 present
-#define SYSCTL_DC2_TIMER2       0x00040000  // Timer 2 present
-#define SYSCTL_DC2_TIMER1       0x00020000  // Timer 1 present
-#define SYSCTL_DC2_TIMER0       0x00010000  // Timer 0 present
-#define SYSCTL_DC2_I2C1         0x00004000  // I2C 1 present
-#define SYSCTL_DC2_I2C0         0x00001000  // I2C 0 present
-#define SYSCTL_DC2_QEI1         0x00000200  // QEI 1 present
-#define SYSCTL_DC2_QEI0         0x00000100  // QEI 0 present
-#define SYSCTL_DC2_SSI1         0x00000020  // SSI 1 present
-#define SYSCTL_DC2_SSI0         0x00000010  // SSI 0 present
-#define SYSCTL_DC2_UART2        0x00000004  // UART 2 present
-#define SYSCTL_DC2_UART1        0x00000002  // UART 1 present
-#define SYSCTL_DC2_UART0        0x00000001  // UART 0 present
+#define SYSCTL_DC2_EPI0         0x40000000  // EPI Module 0 Present
+#define SYSCTL_DC2_I2S0         0x10000000  // I2S Module 0 Present
+#define SYSCTL_DC2_COMP2        0x04000000  // Analog Comparator 2 Present
+#define SYSCTL_DC2_COMP1        0x02000000  // Analog Comparator 1 Present
+#define SYSCTL_DC2_COMP0        0x01000000  // Analog Comparator 0 Present
+#define SYSCTL_DC2_TIMER3       0x00080000  // Timer Module 3 Present
+#define SYSCTL_DC2_TIMER2       0x00040000  // Timer Module 2 Present
+#define SYSCTL_DC2_TIMER1       0x00020000  // Timer Module 1 Present
+#define SYSCTL_DC2_TIMER0       0x00010000  // Timer Module 0 Present
+#define SYSCTL_DC2_I2C1         0x00004000  // I2C Module 1 Present
+#define SYSCTL_DC2_I2C0         0x00001000  // I2C Module 0 Present
+#define SYSCTL_DC2_QEI1         0x00000200  // QEI Module 1 Present
+#define SYSCTL_DC2_QEI0         0x00000100  // QEI Module 0 Present
+#define SYSCTL_DC2_SSI1         0x00000020  // SSI Module 1 Present
+#define SYSCTL_DC2_SSI0         0x00000010  // SSI Module 0 Present
+#define SYSCTL_DC2_UART2        0x00000004  // UART Module 2 Present
+#define SYSCTL_DC2_UART1        0x00000002  // UART Module 1 Present
+#define SYSCTL_DC2_UART0        0x00000001  // UART Module 0 Present
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_DC3 register.
 //
 //*****************************************************************************
-#define SYSCTL_DC3_32KHZ        0x80000000  // 32KHz Pin Present.
-#define SYSCTL_DC3_CCP5         0x20000000  // CCP5 pin present
-#define SYSCTL_DC3_CCP4         0x10000000  // CCP4 pin present
-#define SYSCTL_DC3_CCP3         0x08000000  // CCP3 pin present
-#define SYSCTL_DC3_CCP2         0x04000000  // CCP2 pin present
-#define SYSCTL_DC3_CCP1         0x02000000  // CCP1 pin present
-#define SYSCTL_DC3_CCP0         0x01000000  // CCP0 pin present
-#define SYSCTL_DC3_ADC0AIN7     0x00800000  // AIN7 Pin Present.
-#define SYSCTL_DC3_ADC0AIN6     0x00400000  // AIN6 Pin Present.
-#define SYSCTL_DC3_ADC0AIN5     0x00200000  // AIN5 Pin Present.
-#define SYSCTL_DC3_ADC0AIN4     0x00100000  // AIN4 Pin Present.
-#define SYSCTL_DC3_ADC0AIN3     0x00080000  // AIN3 Pin Present.
-#define SYSCTL_DC3_ADC0AIN2     0x00040000  // AIN2 Pin Present.
-#define SYSCTL_DC3_ADC0AIN1     0x00020000  // AIN1 Pin Present.
-#define SYSCTL_DC3_ADC0AIN0     0x00010000  // AIN0 Pin Present.
-#define SYSCTL_DC3_PWMFAULT     0x00008000  // PWM Fault Pin Present.
-#define SYSCTL_DC3_C2O          0x00004000  // C2o pin present
-#define SYSCTL_DC3_C2PLUS       0x00002000  // C2+ pin present
-#define SYSCTL_DC3_C2MINUS      0x00001000  // C2- pin present
-#define SYSCTL_DC3_C1O          0x00000800  // C1o pin present
-#define SYSCTL_DC3_C1PLUS       0x00000400  // C1+ pin present
-#define SYSCTL_DC3_C1MINUS      0x00000200  // C1- pin present
-#define SYSCTL_DC3_C0O          0x00000100  // C0o pin present
-#define SYSCTL_DC3_C0PLUS       0x00000080  // C0+ pin present
-#define SYSCTL_DC3_C0MINUS      0x00000040  // C0- pin present
-#define SYSCTL_DC3_PWM5         0x00000020  // PWM5 pin present
-#define SYSCTL_DC3_PWM4         0x00000010  // PWM4 pin present
-#define SYSCTL_DC3_PWM3         0x00000008  // PWM3 pin present
-#define SYSCTL_DC3_PWM2         0x00000004  // PWM2 pin present
-#define SYSCTL_DC3_PWM1         0x00000002  // PWM1 pin present
-#define SYSCTL_DC3_PWM0         0x00000001  // PWM0 pin present
+#define SYSCTL_DC3_32KHZ        0x80000000  // 32KHz Input Clock Available
+#define SYSCTL_DC3_CCP5         0x20000000  // CCP5 Pin Present
+#define SYSCTL_DC3_CCP4         0x10000000  // CCP4 Pin Present
+#define SYSCTL_DC3_CCP3         0x08000000  // CCP3 Pin Present
+#define SYSCTL_DC3_CCP2         0x04000000  // CCP2 Pin Present
+#define SYSCTL_DC3_CCP1         0x02000000  // CCP1 Pin Present
+#define SYSCTL_DC3_CCP0         0x01000000  // CCP0 Pin Present
+#define SYSCTL_DC3_ADC0AIN7     0x00800000  // ADC Module 0 AIN7 Pin Present
+#define SYSCTL_DC3_ADC0AIN6     0x00400000  // ADC Module 0 AIN6 Pin Present
+#define SYSCTL_DC3_ADC0AIN5     0x00200000  // ADC Module 0 AIN5 Pin Present
+#define SYSCTL_DC3_ADC0AIN4     0x00100000  // ADC Module 0 AIN4 Pin Present
+#define SYSCTL_DC3_ADC0AIN3     0x00080000  // ADC Module 0 AIN3 Pin Present
+#define SYSCTL_DC3_ADC0AIN2     0x00040000  // ADC Module 0 AIN2 Pin Present
+#define SYSCTL_DC3_ADC0AIN1     0x00020000  // ADC Module 0 AIN1 Pin Present
+#define SYSCTL_DC3_ADC0AIN0     0x00010000  // ADC Module 0 AIN0 Pin Present
+#define SYSCTL_DC3_PWMFAULT     0x00008000  // PWM Fault Pin Present
+#define SYSCTL_DC3_C2O          0x00004000  // C2o Pin Present
+#define SYSCTL_DC3_C2PLUS       0x00002000  // C2+ Pin Present
+#define SYSCTL_DC3_C2MINUS      0x00001000  // C2- Pin Present
+#define SYSCTL_DC3_C1O          0x00000800  // C1o Pin Present
+#define SYSCTL_DC3_C1PLUS       0x00000400  // C1+ Pin Present
+#define SYSCTL_DC3_C1MINUS      0x00000200  // C1- Pin Present
+#define SYSCTL_DC3_C0O          0x00000100  // C0o Pin Present
+#define SYSCTL_DC3_C0PLUS       0x00000080  // C0+ Pin Present
+#define SYSCTL_DC3_C0MINUS      0x00000040  // C0- Pin Present
+#define SYSCTL_DC3_PWM5         0x00000020  // PWM5 Pin Present
+#define SYSCTL_DC3_PWM4         0x00000010  // PWM4 Pin Present
+#define SYSCTL_DC3_PWM3         0x00000008  // PWM3 Pin Present
+#define SYSCTL_DC3_PWM2         0x00000004  // PWM2 Pin Present
+#define SYSCTL_DC3_PWM1         0x00000002  // PWM1 Pin Present
+#define SYSCTL_DC3_PWM0         0x00000001  // PWM0 Pin Present
 
 //*****************************************************************************
 //
@@ -423,33 +540,153 @@
 //
 //*****************************************************************************
 #define SYSCTL_DC4_ETH          0x50000000  // Ethernet present
-#define SYSCTL_DC4_EPHY0        0x40000000  // Ethernet PHY0 Present.
-#define SYSCTL_DC4_EMAC0        0x10000000  // Ethernet MAC0 Present.
-#define SYSCTL_DC4_E1588        0x01000000  // 1588 Capable.
-#define SYSCTL_DC4_PICAL        0x00040000  // When set, indicates that the
-                                            // USER can calibrate the PIOSC
-#define SYSCTL_DC4_CCP7         0x00008000  // CCP7 Pin Present.
-#define SYSCTL_DC4_CCP6         0x00004000  // CCP6 Pin Present.
-#define SYSCTL_DC4_UDMA         0x00002000  // Micro-DMA is present.
-#define SYSCTL_DC4_ROM          0x00001000  // Internal Code ROM is present.
-#define SYSCTL_DC4_GPIOJ        0x00000100  // GPIO Port J Present.
-#define SYSCTL_DC4_GPIOH        0x00000080  // GPIO port H present
-#define SYSCTL_DC4_GPIOG        0x00000040  // GPIO port G present
-#define SYSCTL_DC4_GPIOF        0x00000020  // GPIO port F present
-#define SYSCTL_DC4_GPIOE        0x00000010  // GPIO port E present
-#define SYSCTL_DC4_GPIOD        0x00000008  // GPIO port D present
-#define SYSCTL_DC4_GPIOC        0x00000004  // GPIO port C present
-#define SYSCTL_DC4_GPIOB        0x00000002  // GPIO port B present
-#define SYSCTL_DC4_GPIOA        0x00000001  // GPIO port A present
+#define SYSCTL_DC4_EPHY0        0x40000000  // Ethernet PHY Layer 0 Present
+#define SYSCTL_DC4_EMAC0        0x10000000  // Ethernet MAC Layer 0 Present
+#define SYSCTL_DC4_E1588        0x01000000  // 1588 Capable
+#define SYSCTL_DC4_PICAL        0x00040000  // PIOSC Calibrate
+#define SYSCTL_DC4_CCP7         0x00008000  // CCP7 Pin Present
+#define SYSCTL_DC4_CCP6         0x00004000  // CCP6 Pin Present
+#define SYSCTL_DC4_UDMA         0x00002000  // Micro-DMA Module Present
+#define SYSCTL_DC4_ROM          0x00001000  // Internal Code ROM Present
+#define SYSCTL_DC4_GPIOJ        0x00000100  // GPIO Port J Present
+#define SYSCTL_DC4_GPIOH        0x00000080  // GPIO Port H Present
+#define SYSCTL_DC4_GPIOG        0x00000040  // GPIO Port G Present
+#define SYSCTL_DC4_GPIOF        0x00000020  // GPIO Port F Present
+#define SYSCTL_DC4_GPIOE        0x00000010  // GPIO Port E Present
+#define SYSCTL_DC4_GPIOD        0x00000008  // GPIO Port D Present
+#define SYSCTL_DC4_GPIOC        0x00000004  // GPIO Port C Present
+#define SYSCTL_DC4_GPIOB        0x00000002  // GPIO Port B Present
+#define SYSCTL_DC4_GPIOA        0x00000001  // GPIO Port A Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC5 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC5_PWMFAULT3    0x08000000  // PWM Fault 3 Pin Present
+#define SYSCTL_DC5_PWMFAULT2    0x04000000  // PWM Fault 2 Pin Present
+#define SYSCTL_DC5_PWMFAULT1    0x02000000  // PWM Fault 1 Pin Present
+#define SYSCTL_DC5_PWMFAULT0    0x01000000  // PWM Fault 0 Pin Present
+#define SYSCTL_DC5_PWMEFLT      0x00200000  // PWM Extended Fault Active
+#define SYSCTL_DC5_PWMESYNC     0x00100000  // PWM Extended SYNC Active
+#define SYSCTL_DC5_PWM7         0x00000080  // PWM7 Pin Present
+#define SYSCTL_DC5_PWM6         0x00000040  // PWM6 Pin Present
+#define SYSCTL_DC5_PWM5         0x00000020  // PWM5 Pin Present
+#define SYSCTL_DC5_PWM4         0x00000010  // PWM4 Pin Present
+#define SYSCTL_DC5_PWM3         0x00000008  // PWM3 Pin Present
+#define SYSCTL_DC5_PWM2         0x00000004  // PWM2 Pin Present
+#define SYSCTL_DC5_PWM1         0x00000002  // PWM1 Pin Present
+#define SYSCTL_DC5_PWM0         0x00000001  // PWM0 Pin Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC6 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC6_USB0PHY      0x00000010  // USB Module 0 PHY Present
+#define SYSCTL_DC6_USB0_M       0x00000003  // USB Module 0 Present
+#define SYSCTL_DC6_USB0_DEV     0x00000001  // USB0 is Device Only
+#define SYSCTL_DC6_USB0_HOSTDEV 0x00000002  // USB is Device or Host
+#define SYSCTL_DC6_USB0_OTG     0x00000003  // USB0 is OTG
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC7 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC7_SW           0x40000000  // Software transfer on uDMA Ch30
+#define SYSCTL_DC7_DMACH30      0x40000000  // SW
+#define SYSCTL_DC7_DMACH29      0x20000000  // I2S0_TX / CAN1_TX
+#define SYSCTL_DC7_DMACH28      0x10000000  // I2S0_RX / CAN1_RX
+#define SYSCTL_DC7_DMACH27      0x08000000  // CAN1_TX / ADC1_SS3
+#define SYSCTL_DC7_DMACH26      0x04000000  // CAN1_RX / ADC1_SS2
+#define SYSCTL_DC7_DMACH25      0x02000000  // SSI1_TX / ADC1_SS1
+#define SYSCTL_DC7_SSI1_TX      0x02000000  // SSI1 TX on uDMA Ch25
+#define SYSCTL_DC7_SSI1_RX      0x01000000  // SSI1 RX on uDMA Ch24
+#define SYSCTL_DC7_DMACH24      0x01000000  // SSI1_RX / ADC1_SS0
+#define SYSCTL_DC7_UART1_TX     0x00800000  // UART1 TX on uDMA Ch23
+#define SYSCTL_DC7_DMACH23      0x00800000  // UART1_TX / CAN2_TX
+#define SYSCTL_DC7_DMACH22      0x00400000  // UART1_RX / CAN2_RX
+#define SYSCTL_DC7_UART1_RX     0x00400000  // UART1 RX on uDMA Ch22
+#define SYSCTL_DC7_DMACH21      0x00200000  // Timer1B / EPI0_WFIFO
+#define SYSCTL_DC7_DMACH20      0x00100000  // Timer1A / EPI0_NBRFIFO
+#define SYSCTL_DC7_DMACH19      0x00080000  // Timer0B / Timer1B
+#define SYSCTL_DC7_DMACH18      0x00040000  // Timer0A / Timer1A
+#define SYSCTL_DC7_DMACH17      0x00020000  // ADC0_SS3
+#define SYSCTL_DC7_DMACH16      0x00010000  // ADC0_SS2
+#define SYSCTL_DC7_DMACH15      0x00008000  // ADC0_SS1 / Timer2B
+#define SYSCTL_DC7_DMACH14      0x00004000  // ADC0_SS0 / Timer2A
+#define SYSCTL_DC7_DMACH13      0x00002000  // CAN0_TX / UART2_TX
+#define SYSCTL_DC7_DMACH12      0x00001000  // CAN0_RX / UART2_RX
+#define SYSCTL_DC7_SSI0_TX      0x00000800  // SSI0 TX on uDMA Ch11
+#define SYSCTL_DC7_DMACH11      0x00000800  // SSI0_TX / SSI1_TX
+#define SYSCTL_DC7_SSI0_RX      0x00000400  // SSI0 RX on uDMA Ch10
+#define SYSCTL_DC7_DMACH10      0x00000400  // SSI0_RX / SSI1_RX
+#define SYSCTL_DC7_UART0_TX     0x00000200  // UART0 TX on uDMA Ch9
+#define SYSCTL_DC7_DMACH9       0x00000200  // UART0_TX / UART1_TX
+#define SYSCTL_DC7_DMACH8       0x00000100  // UART0_RX / UART1_RX
+#define SYSCTL_DC7_UART0_RX     0x00000100  // UART0 RX on uDMA Ch8
+#define SYSCTL_DC7_DMACH7       0x00000080  // ETH_TX / Timer2B
+#define SYSCTL_DC7_DMACH6       0x00000040  // ETH_RX / Timer2A
+#define SYSCTL_DC7_DMACH5       0x00000020  // USB_EP3_TX / Timer2B
+#define SYSCTL_DC7_USB_EP3_TX   0x00000020  // USB EP3 TX on uDMA Ch5
+#define SYSCTL_DC7_USB_EP3_RX   0x00000010  // USB EP3 RX on uDMA Ch4
+#define SYSCTL_DC7_DMACH4       0x00000010  // USB_EP3_RX / Timer2A
+#define SYSCTL_DC7_USB_EP2_TX   0x00000008  // USB EP2 TX on uDMA Ch3
+#define SYSCTL_DC7_DMACH3       0x00000008  // USB_EP2_TX / Timer3B
+#define SYSCTL_DC7_USB_EP2_RX   0x00000004  // USB EP2 RX on uDMA Ch2
+#define SYSCTL_DC7_DMACH2       0x00000004  // USB_EP2_RX / Timer3A
+#define SYSCTL_DC7_USB_EP1_TX   0x00000002  // USB EP1 TX on uDMA Ch1
+#define SYSCTL_DC7_DMACH1       0x00000002  // USB_EP1_TX / UART2_TX
+#define SYSCTL_DC7_DMACH0       0x00000001  // USB_EP1_RX / UART2_RX
+#define SYSCTL_DC7_USB_EP1_RX   0x00000001  // USB EP1 RX on uDMA Ch0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC8 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC8_ADC1AIN15    0x80000000  // ADC Module 1 AIN15 Pin Present
+#define SYSCTL_DC8_ADC1AIN14    0x40000000  // ADC Module 1 AIN14 Pin Present
+#define SYSCTL_DC8_ADC1AIN13    0x20000000  // ADC Module 1 AIN13 Pin Present
+#define SYSCTL_DC8_ADC1AIN12    0x10000000  // ADC Module 1 AIN12 Pin Present
+#define SYSCTL_DC8_ADC1AIN11    0x08000000  // ADC Module 1 AIN11 Pin Present
+#define SYSCTL_DC8_ADC1AIN10    0x04000000  // ADC Module 1 AIN10 Pin Present
+#define SYSCTL_DC8_ADC1AIN9     0x02000000  // ADC Module 1 AIN9 Pin Present
+#define SYSCTL_DC8_ADC1AIN8     0x01000000  // ADC Module 1 AIN8 Pin Present
+#define SYSCTL_DC8_ADC1AIN7     0x00800000  // ADC Module 1 AIN7 Pin Present
+#define SYSCTL_DC8_ADC1AIN6     0x00400000  // ADC Module 1 AIN6 Pin Present
+#define SYSCTL_DC8_ADC1AIN5     0x00200000  // ADC Module 1 AIN5 Pin Present
+#define SYSCTL_DC8_ADC1AIN4     0x00100000  // ADC Module 1 AIN4 Pin Present
+#define SYSCTL_DC8_ADC1AIN3     0x00080000  // ADC Module 1 AIN3 Pin Present
+#define SYSCTL_DC8_ADC1AIN2     0x00040000  // ADC Module 1 AIN2 Pin Present
+#define SYSCTL_DC8_ADC1AIN1     0x00020000  // ADC Module 1 AIN1 Pin Present
+#define SYSCTL_DC8_ADC1AIN0     0x00010000  // ADC Module 1 AIN0 Pin Present
+#define SYSCTL_DC8_ADC0AIN15    0x00008000  // ADC Module 0 AIN15 Pin Present
+#define SYSCTL_DC8_ADC0AIN14    0x00004000  // ADC Module 0 AIN14 Pin Present
+#define SYSCTL_DC8_ADC0AIN13    0x00002000  // ADC Module 0 AIN13 Pin Present
+#define SYSCTL_DC8_ADC0AIN12    0x00001000  // ADC Module 0 AIN12 Pin Present
+#define SYSCTL_DC8_ADC0AIN11    0x00000800  // ADC Module 0 AIN11 Pin Present
+#define SYSCTL_DC8_ADC0AIN10    0x00000400  // ADC Module 0 AIN10 Pin Present
+#define SYSCTL_DC8_ADC0AIN9     0x00000200  // ADC Module 0 AIN9 Pin Present
+#define SYSCTL_DC8_ADC0AIN8     0x00000100  // ADC Module 0 AIN8 Pin Present
+#define SYSCTL_DC8_ADC0AIN7     0x00000080  // ADC Module 0 AIN7 Pin Present
+#define SYSCTL_DC8_ADC0AIN6     0x00000040  // ADC Module 0 AIN6 Pin Present
+#define SYSCTL_DC8_ADC0AIN5     0x00000020  // ADC Module 0 AIN5 Pin Present
+#define SYSCTL_DC8_ADC0AIN4     0x00000010  // ADC Module 0 AIN4 Pin Present
+#define SYSCTL_DC8_ADC0AIN3     0x00000008  // ADC Module 0 AIN3 Pin Present
+#define SYSCTL_DC8_ADC0AIN2     0x00000004  // ADC Module 0 AIN2 Pin Present
+#define SYSCTL_DC8_ADC0AIN1     0x00000002  // ADC Module 0 AIN1 Pin Present
+#define SYSCTL_DC8_ADC0AIN0     0x00000001  // ADC Module 0 AIN0 Pin Present
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_PBORCTL register.
 //
 //*****************************************************************************
-#define SYSCTL_PBORCTL_BORTIM_M 0x0000FFFC  // BOR Time Delay.
-#define SYSCTL_PBORCTL_BORIOR   0x00000002  // BOR interrupt or reset
-#define SYSCTL_PBORCTL_BORWT    0x00000001  // BOR wait and check for noise
+#define SYSCTL_PBORCTL_BORTIM_M 0x0000FFFC  // BOR Time Delay
+#define SYSCTL_PBORCTL_BORIOR   0x00000002  // BOR Interrupt or Reset
+#define SYSCTL_PBORCTL_BORWT    0x00000001  // BOR Wait and Check for Noise
 #define SYSCTL_PBORCTL_BORTIM_S 2
 
 //*****************************************************************************
@@ -457,40 +694,158 @@
 // The following are defines for the bit fields in the SYSCTL_LDOPCTL register.
 //
 //*****************************************************************************
-#define SYSCTL_LDOPCTL_M        0x0000003F  // LDO Output Voltage.
-#define SYSCTL_LDOPCTL_2_55V    0x0000001F  // LDO output of 2.55V
-#define SYSCTL_LDOPCTL_2_60V    0x0000001E  // LDO output of 2.60V
-#define SYSCTL_LDOPCTL_2_65V    0x0000001D  // LDO output of 2.65V
-#define SYSCTL_LDOPCTL_2_70V    0x0000001C  // LDO output of 2.70V
-#define SYSCTL_LDOPCTL_2_75V    0x0000001B  // LDO output of 2.75V
-#define SYSCTL_LDOPCTL_2_25V    0x00000005  // LDO output of 2.25V
-#define SYSCTL_LDOPCTL_2_30V    0x00000004  // LDO output of 2.30V
-#define SYSCTL_LDOPCTL_2_35V    0x00000003  // LDO output of 2.35V
-#define SYSCTL_LDOPCTL_2_40V    0x00000002  // LDO output of 2.40V
-#define SYSCTL_LDOPCTL_2_45V    0x00000001  // LDO output of 2.45V
-#define SYSCTL_LDOPCTL_2_50V    0x00000000  // LDO output of 2.50V
+#define SYSCTL_LDOPCTL_M        0x0000003F  // LDO Output Voltage
+#define SYSCTL_LDOPCTL_2_50V    0x00000000  // 2.50
+#define SYSCTL_LDOPCTL_2_45V    0x00000001  // 2.45
+#define SYSCTL_LDOPCTL_2_40V    0x00000002  // 2.40
+#define SYSCTL_LDOPCTL_2_35V    0x00000003  // 2.35
+#define SYSCTL_LDOPCTL_2_30V    0x00000004  // 2.30
+#define SYSCTL_LDOPCTL_2_25V    0x00000005  // 2.25
+#define SYSCTL_LDOPCTL_2_75V    0x0000001B  // 2.75
+#define SYSCTL_LDOPCTL_2_70V    0x0000001C  // 2.70
+#define SYSCTL_LDOPCTL_2_65V    0x0000001D  // 2.65
+#define SYSCTL_LDOPCTL_2_60V    0x0000001E  // 2.60
+#define SYSCTL_LDOPCTL_2_55V    0x0000001F  // 2.55
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCR0 register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCR0_WDT1       0x10000000  // WDT1 Reset Control
+#define SYSCTL_SRCR0_CAN2       0x04000000  // CAN2 Reset Control
+#define SYSCTL_SRCR0_CAN1       0x02000000  // CAN1 Reset Control
+#define SYSCTL_SRCR0_CAN0       0x01000000  // CAN0 Reset Control
+#define SYSCTL_SRCR0_PWM        0x00100000  // PWM Reset Control
+#define SYSCTL_SRCR0_ADC1       0x00020000  // ADC1 Reset Control
+#define SYSCTL_SRCR0_ADC0       0x00010000  // ADC0 Reset Control
+#define SYSCTL_SRCR0_HIB        0x00000040  // HIB Reset Control
+#define SYSCTL_SRCR0_WDT0       0x00000008  // WDT0 Reset Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCR1 register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCR1_EPI0       0x40000000  // EPI0 Reset Control
+#define SYSCTL_SRCR1_I2S0       0x10000000  // I2S0 Reset Control
+#define SYSCTL_SRCR1_COMP2      0x04000000  // Analog Comp 2 Reset Control
+#define SYSCTL_SRCR1_COMP1      0x02000000  // Analog Comp 1 Reset Control
+#define SYSCTL_SRCR1_COMP0      0x01000000  // Analog Comp 0 Reset Control
+#define SYSCTL_SRCR1_TIMER3     0x00080000  // Timer 3 Reset Control
+#define SYSCTL_SRCR1_TIMER2     0x00040000  // Timer 2 Reset Control
+#define SYSCTL_SRCR1_TIMER1     0x00020000  // Timer 1 Reset Control
+#define SYSCTL_SRCR1_TIMER0     0x00010000  // Timer 0 Reset Control
+#define SYSCTL_SRCR1_I2C1       0x00004000  // I2C1 Reset Control
+#define SYSCTL_SRCR1_I2C0       0x00001000  // I2C0 Reset Control
+#define SYSCTL_SRCR1_QEI1       0x00000200  // QEI1 Reset Control
+#define SYSCTL_SRCR1_QEI0       0x00000100  // QEI0 Reset Control
+#define SYSCTL_SRCR1_SSI1       0x00000020  // SSI1 Reset Control
+#define SYSCTL_SRCR1_SSI0       0x00000010  // SSI0 Reset Control
+#define SYSCTL_SRCR1_UART2      0x00000004  // UART2 Reset Control
+#define SYSCTL_SRCR1_UART1      0x00000002  // UART1 Reset Control
+#define SYSCTL_SRCR1_UART0      0x00000001  // UART0 Reset Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCR2 register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCR2_EPHY0      0x40000000  // PHY0 Reset Control
+#define SYSCTL_SRCR2_EMAC0      0x10000000  // MAC0 Reset Control
+#define SYSCTL_SRCR2_USB0       0x00010000  // USB0 Reset Control
+#define SYSCTL_SRCR2_UDMA       0x00002000  // Micro-DMA Reset Control
+#define SYSCTL_SRCR2_GPIOJ      0x00000100  // Port J Reset Control
+#define SYSCTL_SRCR2_GPIOH      0x00000080  // Port H Reset Control
+#define SYSCTL_SRCR2_GPIOG      0x00000040  // Port G Reset Control
+#define SYSCTL_SRCR2_GPIOF      0x00000020  // Port F Reset Control
+#define SYSCTL_SRCR2_GPIOE      0x00000010  // Port E Reset Control
+#define SYSCTL_SRCR2_GPIOD      0x00000008  // Port D Reset Control
+#define SYSCTL_SRCR2_GPIOC      0x00000004  // Port C Reset Control
+#define SYSCTL_SRCR2_GPIOB      0x00000002  // Port B Reset Control
+#define SYSCTL_SRCR2_GPIOA      0x00000001  // Port A Reset Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RIS register.
+//
+//*****************************************************************************
+#define SYSCTL_RIS_MOSCPUPRIS   0x00000100  // MOSC Power Up Raw Interrupt
+                                            // Status
+#define SYSCTL_RIS_USBPLLLRIS   0x00000080  // USB PLL Lock Raw Interrupt
+                                            // Status
+#define SYSCTL_RIS_PLLLRIS      0x00000040  // PLL Lock Raw Interrupt Status
+#define SYSCTL_RIS_CLRIS        0x00000020  // Current Limit Raw Interrupt
+                                            // Status
+#define SYSCTL_RIS_IOFRIS       0x00000010  // Internal Oscillator Fault Raw
+                                            // Interrupt Status
+#define SYSCTL_RIS_MOFRIS       0x00000008  // Main Oscillator Fault Raw
+                                            // Interrupt Status
+#define SYSCTL_RIS_LDORIS       0x00000004  // LDO Power Unregulated Raw
+                                            // Interrupt Status
+#define SYSCTL_RIS_BORRIS       0x00000002  // Brown-Out Reset Raw Interrupt
+                                            // Status
+#define SYSCTL_RIS_PLLFRIS      0x00000001  // PLL Fault Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_IMC register.
+//
+//*****************************************************************************
+#define SYSCTL_IMC_MOSCPUPIM    0x00000100  // MOSC Power Up Interrupt Mask
+#define SYSCTL_IMC_USBPLLLIM    0x00000080  // USB PLL Lock Interrupt Mask
+#define SYSCTL_IMC_PLLLIM       0x00000040  // PLL Lock Interrupt Mask
+#define SYSCTL_IMC_CLIM         0x00000020  // Current Limit Interrupt Mask
+#define SYSCTL_IMC_IOFIM        0x00000010  // Internal Oscillator Fault
+                                            // Interrupt Mask
+#define SYSCTL_IMC_MOFIM        0x00000008  // Main Oscillator Fault Interrupt
+                                            // Mask
+#define SYSCTL_IMC_LDOIM        0x00000004  // LDO Power Unregulated Interrupt
+                                            // Mask
+#define SYSCTL_IMC_BORIM        0x00000002  // Brown-Out Reset Interrupt Mask
+#define SYSCTL_IMC_PLLFIM       0x00000001  // PLL Fault Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_MISC register.
+//
+//*****************************************************************************
+#define SYSCTL_MISC_MOSCPUPMIS  0x00000100  // MOSC Power Up Masked Interrupt
+                                            // Status
+#define SYSCTL_MISC_USBPLLLMIS  0x00000080  // USB PLL Lock Masked Interrupt
+                                            // Status
+#define SYSCTL_MISC_PLLLMIS     0x00000040  // PLL Lock Masked Interrupt Status
+#define SYSCTL_MISC_CLMIS       0x00000020  // Current Limit Masked Interrupt
+                                            // Status
+#define SYSCTL_MISC_IOFMIS      0x00000010  // Internal Oscillator Fault Masked
+                                            // Interrupt Status
+#define SYSCTL_MISC_MOFMIS      0x00000008  // Main Oscillator Fault Masked
+                                            // Interrupt Status
+#define SYSCTL_MISC_LDOMIS      0x00000004  // LDO Power Unregulated Masked
+                                            // Interrupt Status
+#define SYSCTL_MISC_BORMIS      0x00000002  // BOR Masked Interrupt Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_RESC register.
 //
 //*****************************************************************************
-#define SYSCTL_RESC_MOSCFAIL    0x00010000  // MOSC Failure Reset.
-#define SYSCTL_RESC_LDO         0x00000020  // LDO power OK lost reset
-#define SYSCTL_RESC_WDT1        0x00000020  // Watchdog Timer 1 Reset.
-#define SYSCTL_RESC_SW          0x00000010  // Software reset
-#define SYSCTL_RESC_WDT0        0x00000008  // Watchdog Timer 0 Reset.
-#define SYSCTL_RESC_BOR         0x00000004  // Brown-out reset
-#define SYSCTL_RESC_POR         0x00000002  // Power on reset
-#define SYSCTL_RESC_EXT         0x00000001  // External reset
+#define SYSCTL_RESC_MOSCFAIL    0x00010000  // MOSC Failure Reset
+#define SYSCTL_RESC_LDO         0x00000020  // LDO Reset
+#define SYSCTL_RESC_WDT1        0x00000020  // Watchdog Timer 1 Reset
+#define SYSCTL_RESC_SW          0x00000010  // Software Reset
+#define SYSCTL_RESC_WDT0        0x00000008  // Watchdog Timer 0 Reset
+#define SYSCTL_RESC_BOR         0x00000004  // Brown-Out Reset
+#define SYSCTL_RESC_POR         0x00000002  // Power-On Reset
+#define SYSCTL_RESC_EXT         0x00000001  // External Reset
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_RCC register.
 //
 //*****************************************************************************
-#define SYSCTL_RCC_ACG          0x08000000  // Automatic clock gating
-#define SYSCTL_RCC_SYSDIV_M     0x07800000  // System Clock Divisor.
+#define SYSCTL_RCC_ACG          0x08000000  // Auto Clock Gating
+#define SYSCTL_RCC_SYSDIV_M     0x07800000  // System Clock Divisor
 #define SYSCTL_RCC_SYSDIV_2     0x00800000  // System clock /2
 #define SYSCTL_RCC_SYSDIV_3     0x01000000  // System clock /3
 #define SYSCTL_RCC_SYSDIV_4     0x01800000  // System clock /4
@@ -506,53 +861,55 @@
 #define SYSCTL_RCC_SYSDIV_14    0x06800000  // System clock /14
 #define SYSCTL_RCC_SYSDIV_15    0x07000000  // System clock /15
 #define SYSCTL_RCC_SYSDIV_16    0x07800000  // System clock /16
-#define SYSCTL_RCC_USESYSDIV    0x00400000  // Enable System Clock Divider.
-#define SYSCTL_RCC_USEPWMDIV    0x00100000  // Enable PWM Clock Divisor.
-#define SYSCTL_RCC_PWMDIV_M     0x000E0000  // PWM clock divider
+#define SYSCTL_RCC_USESYSDIV    0x00400000  // Enable System Clock Divider
+#define SYSCTL_RCC_USEPWMDIV    0x00100000  // Enable PWM Clock Divisor
+#define SYSCTL_RCC_PWMDIV_M     0x000E0000  // PWM Unit Clock Divisor
 #define SYSCTL_RCC_PWMDIV_2     0x00000000  // PWM clock /2
 #define SYSCTL_RCC_PWMDIV_4     0x00020000  // PWM clock /4
 #define SYSCTL_RCC_PWMDIV_8     0x00040000  // PWM clock /8
 #define SYSCTL_RCC_PWMDIV_16    0x00060000  // PWM clock /16
 #define SYSCTL_RCC_PWMDIV_32    0x00080000  // PWM clock /32
 #define SYSCTL_RCC_PWMDIV_64    0x000A0000  // PWM clock /64
-#define SYSCTL_RCC_PWRDN        0x00002000  // PLL power down
-#define SYSCTL_RCC_OEN          0x00001000  // PLL Output Enable.
-#define SYSCTL_RCC_BYPASS       0x00000800  // PLL bypass
-#define SYSCTL_RCC_XTAL_M       0x000007C0  // Crystal attached to main osc
-#define SYSCTL_RCC_XTAL_1MHZ    0x00000000  // Using a 1MHz crystal
-#define SYSCTL_RCC_XTAL_1_84MHZ 0x00000040  // Using a 1.8432MHz crystal
-#define SYSCTL_RCC_XTAL_2MHZ    0x00000080  // Using a 2MHz crystal
-#define SYSCTL_RCC_XTAL_2_45MHZ 0x000000C0  // Using a 2.4576MHz crystal
-#define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100  // Using a 3.579545MHz crystal
-#define SYSCTL_RCC_XTAL_3_68MHZ 0x00000140  // Using a 3.6864MHz crystal
-#define SYSCTL_RCC_XTAL_4MHZ    0x00000180  // Using a 4MHz crystal
-#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0  // Using a 4.096MHz crystal
-#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200  // Using a 4.9152MHz crystal
-#define SYSCTL_RCC_XTAL_5MHZ    0x00000240  // Using a 5MHz crystal
-#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280  // Using a 5.12MHz crystal
-#define SYSCTL_RCC_XTAL_6MHZ    0x000002C0  // Using a 6MHz crystal
-#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300  // Using a 6.144MHz crystal
-#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340  // Using a 7.3728MHz crystal
-#define SYSCTL_RCC_XTAL_8MHZ    0x00000380  // Using a 8MHz crystal
-#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0  // Using a 8.192MHz crystal
-#define SYSCTL_RCC_XTAL_10MHZ   0x00000400  // 10.0 MHz (USB)
-#define SYSCTL_RCC_XTAL_12MHZ   0x00000440  // 12.0 MHz (USB)
+#define SYSCTL_RCC_PWRDN        0x00002000  // PLL Power Down
+#define SYSCTL_RCC_OEN          0x00001000  // PLL Output Enable
+#define SYSCTL_RCC_BYPASS       0x00000800  // PLL Bypass
+#define SYSCTL_RCC_XTAL_M       0x000007C0  // Crystal Value
+#define SYSCTL_RCC_XTAL_1MHZ    0x00000000  // 1 MHz
+#define SYSCTL_RCC_XTAL_1_84MHZ 0x00000040  // 1.8432 MHz
+#define SYSCTL_RCC_XTAL_2MHZ    0x00000080  // 2 MHz
+#define SYSCTL_RCC_XTAL_2_45MHZ 0x000000C0  // 2.4576 MHz
+#define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100  // 3.579545 MHz
+#define SYSCTL_RCC_XTAL_3_68MHZ 0x00000140  // 3.6864 MHz
+#define SYSCTL_RCC_XTAL_4MHZ    0x00000180  // 4 MHz
+#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0  // 4.096 MHz
+#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200  // 4.9152 MHz
+#define SYSCTL_RCC_XTAL_5MHZ    0x00000240  // 5 MHz
+#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280  // 5.12 MHz
+#define SYSCTL_RCC_XTAL_6MHZ    0x000002C0  // 6 MHz
+#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300  // 6.144 MHz
+#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340  // 7.3728 MHz
+#define SYSCTL_RCC_XTAL_8MHZ    0x00000380  // 8 MHz
+#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0  // 8.192 MHz
+#define SYSCTL_RCC_XTAL_10MHZ   0x00000400  // 10 MHz
+#define SYSCTL_RCC_XTAL_12MHZ   0x00000440  // 12 MHz
 #define SYSCTL_RCC_XTAL_12_2MHZ 0x00000480  // 12.288 MHz
 #define SYSCTL_RCC_XTAL_13_5MHZ 0x000004C0  // 13.56 MHz
 #define SYSCTL_RCC_XTAL_14_3MHZ 0x00000500  // 14.31818 MHz
-#define SYSCTL_RCC_XTAL_16MHZ   0x00000540  // 16.0 MHz (USB)
+#define SYSCTL_RCC_XTAL_16MHZ   0x00000540  // 16 MHz
 #define SYSCTL_RCC_XTAL_16_3MHZ 0x00000580  // 16.384 MHz
-#define SYSCTL_RCC_PLLVER       0x00000400  // PLL verification timer enable
-#define SYSCTL_RCC_OSCSRC_M     0x00000030  // Oscillator input select
-#define SYSCTL_RCC_OSCSRC_MAIN  0x00000000  // Use the main oscillator
-#define SYSCTL_RCC_OSCSRC_INT   0x00000010  // Use the internal oscillator
-#define SYSCTL_RCC_OSCSRC_INT4  0x00000020  // Use the internal oscillator / 4
-#define SYSCTL_RCC_OSCSRC_30    0x00000030  // 30 KHz internal oscillator
-#define SYSCTL_RCC_IOSCVER      0x00000008  // Int. osc. verification timer en
-#define SYSCTL_RCC_MOSCVER      0x00000004  // Main osc. verification timer en
-#define SYSCTL_RCC_IOSCDIS      0x00000002  // Internal oscillator disable
-#define SYSCTL_RCC_MOSCDIS      0x00000001  // Main oscillator disable
-#define SYSCTL_RCC_SYSDIV_S     23          // Shift to the SYSDIV field
+#define SYSCTL_RCC_PLLVER       0x00000400  // PLL Verification
+#define SYSCTL_RCC_OSCSRC_M     0x00000030  // Oscillator Source
+#define SYSCTL_RCC_OSCSRC_MAIN  0x00000000  // MOSC
+#define SYSCTL_RCC_OSCSRC_INT   0x00000010  // IOSC
+#define SYSCTL_RCC_OSCSRC_INT4  0x00000020  // IOSC/4
+#define SYSCTL_RCC_OSCSRC_30    0x00000030  // 30 kHz
+#define SYSCTL_RCC_IOSCVER      0x00000008  // Internal Oscillator Verification
+                                            // Timer
+#define SYSCTL_RCC_MOSCVER      0x00000004  // Main Oscillator Verification
+                                            // Timer
+#define SYSCTL_RCC_IOSCDIS      0x00000002  // Internal Oscillator Disable
+#define SYSCTL_RCC_MOSCDIS      0x00000001  // Main Oscillator Disable
+#define SYSCTL_RCC_SYSDIV_S     23
 #define SYSCTL_RCC_PWMDIV_S     17          // Shift to the PWMDIV field
 #define SYSCTL_RCC_XTAL_S       6           // Shift to the XTAL field
 #define SYSCTL_RCC_OSCSRC_S     4           // Shift to the OSCSRC field
@@ -562,23 +919,49 @@
 // The following are defines for the bit fields in the SYSCTL_PLLCFG register.
 //
 //*****************************************************************************
-#define SYSCTL_PLLCFG_OD_M      0x0000C000  // Output divider
-#define SYSCTL_PLLCFG_OD_1      0x00000000  // Output divider is 1
-#define SYSCTL_PLLCFG_OD_2      0x00004000  // Output divider is 2
-#define SYSCTL_PLLCFG_OD_4      0x00008000  // Output divider is 4
-#define SYSCTL_PLLCFG_F_M       0x00003FE0  // PLL F Value.
-#define SYSCTL_PLLCFG_R_M       0x0000001F  // PLL R Value.
+#define SYSCTL_PLLCFG_OD_M      0x0000C000  // PLL OD Value
+#define SYSCTL_PLLCFG_OD_1      0x00000000  // Divide by 1
+#define SYSCTL_PLLCFG_OD_2      0x00004000  // Divide by 2
+#define SYSCTL_PLLCFG_OD_4      0x00008000  // Divide by 4
+#define SYSCTL_PLLCFG_F_M       0x00003FE0  // PLL F Value
+#define SYSCTL_PLLCFG_R_M       0x0000001F  // PLL R Value
 #define SYSCTL_PLLCFG_F_S       5
 #define SYSCTL_PLLCFG_R_S       0
 
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_GPIOHBCTL
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_GPIOHBCTL_PORTJ  0x00000100  // Port J Advanced High-Performance
+                                            // Bus
+#define SYSCTL_GPIOHBCTL_PORTH  0x00000080  // Port H Advanced High-Performance
+                                            // Bus
+#define SYSCTL_GPIOHBCTL_PORTG  0x00000040  // Port G Advanced High-Performance
+                                            // Bus
+#define SYSCTL_GPIOHBCTL_PORTF  0x00000020  // Port F Advanced High-Performance
+                                            // Bus
+#define SYSCTL_GPIOHBCTL_PORTE  0x00000010  // Port E Advanced High-Performance
+                                            // Bus
+#define SYSCTL_GPIOHBCTL_PORTD  0x00000008  // Port D Advanced High-Performance
+                                            // Bus
+#define SYSCTL_GPIOHBCTL_PORTC  0x00000004  // Port C Advanced High-Performance
+                                            // Bus
+#define SYSCTL_GPIOHBCTL_PORTB  0x00000002  // Port B Advanced High-Performance
+                                            // Bus
+#define SYSCTL_GPIOHBCTL_PORTA  0x00000001  // Port A Advanced High-Performance
+                                            // Bus
+
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_RCC2 register.
 //
 //*****************************************************************************
 #define SYSCTL_RCC2_USERCC2     0x80000000  // Use RCC2
-#define SYSCTL_RCC2_USEFRACT    0x40000000  // Use fractional divider
-#define SYSCTL_RCC2_SYSDIV2_M   0x1F800000  // System clock divider
+#define SYSCTL_RCC2_DIV400      0x40000000  // Divide PLL as 400 MHz vs. 200
+                                            // MHz
+#define SYSCTL_RCC2_SYSDIV2_M   0x1F800000  // System Clock Divisor 2
 #define SYSCTL_RCC2_SYSDIV2_2   0x00800000  // System clock /2
 #define SYSCTL_RCC2_SYSDIV2_3   0x01000000  // System clock /3
 #define SYSCTL_RCC2_SYSDIV2_4   0x01800000  // System clock /4
@@ -642,18 +1025,241 @@
 #define SYSCTL_RCC2_SYSDIV2_62  0x1E800000  // System clock /62
 #define SYSCTL_RCC2_SYSDIV2_63  0x1F000000  // System clock /63
 #define SYSCTL_RCC2_SYSDIV2_64  0x1F800000  // System clock /64
-#define SYSCTL_RCC2_FRACT       0x00400000  // Fractional divide
-#define SYSCTL_RCC2_USBPWRDN    0x00004000  // Power-Down USB PLL.
-#define SYSCTL_RCC2_PWRDN2      0x00002000  // PLL power down
-#define SYSCTL_RCC2_BYPASS2     0x00000800  // PLL bypass
-#define SYSCTL_RCC2_OSCSRC2_M   0x00000070  // System Clock Source.
-#define SYSCTL_RCC2_OSCSRC2_MO  0x00000000  // Use the main oscillator
-#define SYSCTL_RCC2_OSCSRC2_IO  0x00000010  // Use the internal oscillator
-#define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020  // Use the internal oscillator / 4
-#define SYSCTL_RCC2_OSCSRC2_30  0x00000030  // Use the 30 KHz internal osc.
-#define SYSCTL_RCC2_OSCSRC2_419 0x00000060  // Use the 4.19 MHz external osc.
-#define SYSCTL_RCC2_OSCSRC2_32  0x00000070  // Use the 32 KHz external osc.
-#define SYSCTL_RCC2_SYSDIV2_S   23          // Shift to the SYSDIV2 field
+#define SYSCTL_RCC2_SYSDIV2LSB  0x00400000  // Additional LSB for SYSDIV2
+#define SYSCTL_RCC2_USBPWRDN    0x00004000  // Power-Down USB PLL
+#define SYSCTL_RCC2_PWRDN2      0x00002000  // Power-Down PLL 2
+#define SYSCTL_RCC2_BYPASS2     0x00000800  // PLL Bypass 2
+#define SYSCTL_RCC2_OSCSRC2_M   0x00000070  // Oscillator Source 2
+#define SYSCTL_RCC2_OSCSRC2_MO  0x00000000  // MOSC
+#define SYSCTL_RCC2_OSCSRC2_IO  0x00000010  // PIOSC
+#define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020  // PIOSC/4
+#define SYSCTL_RCC2_OSCSRC2_30  0x00000030  // 30 kHz
+#define SYSCTL_RCC2_OSCSRC2_419 0x00000060  // 4.194304 MHz
+#define SYSCTL_RCC2_OSCSRC2_32  0x00000070  // 32.768 kHz
+#define SYSCTL_RCC2_SYSDIV2_S   23
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_MOSCCTL register.
+//
+//*****************************************************************************
+#define SYSCTL_MOSCCTL_CVAL     0x00000001  // Clock Validation for MOSC
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGC0_WDT1       0x10000000  // WDT1 Clock Gating Control
+#define SYSCTL_RCGC0_CAN2       0x04000000  // CAN2 Clock Gating Control
+#define SYSCTL_RCGC0_CAN1       0x02000000  // CAN1 Clock Gating Control
+#define SYSCTL_RCGC0_CAN0       0x01000000  // CAN0 Clock Gating Control
+#define SYSCTL_RCGC0_PWM        0x00100000  // PWM Clock Gating Control
+#define SYSCTL_RCGC0_ADC1       0x00020000  // ADC1 Clock Gating Control
+#define SYSCTL_RCGC0_ADC0       0x00010000  // ADC0 Clock Gating Control
+#define SYSCTL_RCGC0_ADCSPD_M   0x00000F00  // ADC Sample Speed
+#define SYSCTL_RCGC0_ADCSPD125K 0x00000000  // 125K samples/second
+#define SYSCTL_RCGC0_ADCSPD250K 0x00000100  // 250K samples/second
+#define SYSCTL_RCGC0_ADCSPD500K 0x00000200  // 500K samples/second
+#define SYSCTL_RCGC0_ADCSPD1M   0x00000300  // 1M samples/second
+#define SYSCTL_RCGC0_ADC1SPD_M  0x00000C00  // ADC1 Sample Speed
+#define SYSCTL_RCGC0_ADC1SPD_125K \
+                                0x00000000  // 125K samples/second
+#define SYSCTL_RCGC0_ADC1SPD_250K \
+                                0x00000400  // 250K samples/second
+#define SYSCTL_RCGC0_ADC1SPD_500K \
+                                0x00000800  // 500K samples/second
+#define SYSCTL_RCGC0_ADC1SPD_1M 0x00000C00  // 1M samples/second
+#define SYSCTL_RCGC0_ADC0SPD_M  0x00000300  // ADC0 Sample Speed
+#define SYSCTL_RCGC0_ADC0SPD_125K \
+                                0x00000000  // 125K samples/second
+#define SYSCTL_RCGC0_ADC0SPD_250K \
+                                0x00000100  // 250K samples/second
+#define SYSCTL_RCGC0_ADC0SPD_500K \
+                                0x00000200  // 500K samples/second
+#define SYSCTL_RCGC0_ADC0SPD_1M 0x00000300  // 1M samples/second
+#define SYSCTL_RCGC0_HIB        0x00000040  // HIB Clock Gating Control
+#define SYSCTL_RCGC0_WDT0       0x00000008  // WDT0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGC1_EPI0       0x40000000  // EPI0 Clock Gating
+#define SYSCTL_RCGC1_I2S0       0x10000000  // I2S0 Clock Gating
+#define SYSCTL_RCGC1_COMP2      0x04000000  // Analog Comparator 2 Clock Gating
+#define SYSCTL_RCGC1_COMP1      0x02000000  // Analog Comparator 1 Clock Gating
+#define SYSCTL_RCGC1_COMP0      0x01000000  // Analog Comparator 0 Clock Gating
+#define SYSCTL_RCGC1_TIMER3     0x00080000  // Timer 3 Clock Gating Control
+#define SYSCTL_RCGC1_TIMER2     0x00040000  // Timer 2 Clock Gating Control
+#define SYSCTL_RCGC1_TIMER1     0x00020000  // Timer 1 Clock Gating Control
+#define SYSCTL_RCGC1_TIMER0     0x00010000  // Timer 0 Clock Gating Control
+#define SYSCTL_RCGC1_I2C1       0x00004000  // I2C1 Clock Gating Control
+#define SYSCTL_RCGC1_I2C0       0x00001000  // I2C0 Clock Gating Control
+#define SYSCTL_RCGC1_QEI1       0x00000200  // QEI1 Clock Gating Control
+#define SYSCTL_RCGC1_QEI0       0x00000100  // QEI0 Clock Gating Control
+#define SYSCTL_RCGC1_SSI1       0x00000020  // SSI1 Clock Gating Control
+#define SYSCTL_RCGC1_SSI0       0x00000010  // SSI0 Clock Gating Control
+#define SYSCTL_RCGC1_UART2      0x00000004  // UART2 Clock Gating Control
+#define SYSCTL_RCGC1_UART1      0x00000002  // UART1 Clock Gating Control
+#define SYSCTL_RCGC1_UART0      0x00000001  // UART0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGC2_EPHY0      0x40000000  // PHY0 Clock Gating Control
+#define SYSCTL_RCGC2_EMAC0      0x10000000  // MAC0 Clock Gating Control
+#define SYSCTL_RCGC2_USB0       0x00010000  // USB0 Clock Gating Control
+#define SYSCTL_RCGC2_UDMA       0x00002000  // Micro-DMA Clock Gating Control
+#define SYSCTL_RCGC2_GPIOJ      0x00000100  // Port J Clock Gating Control
+#define SYSCTL_RCGC2_GPIOH      0x00000080  // Port H Clock Gating Control
+#define SYSCTL_RCGC2_GPIOG      0x00000040  // Port G Clock Gating Control
+#define SYSCTL_RCGC2_GPIOF      0x00000020  // Port F Clock Gating Control
+#define SYSCTL_RCGC2_GPIOE      0x00000010  // Port E Clock Gating Control
+#define SYSCTL_RCGC2_GPIOD      0x00000008  // Port D Clock Gating Control
+#define SYSCTL_RCGC2_GPIOC      0x00000004  // Port C Clock Gating Control
+#define SYSCTL_RCGC2_GPIOB      0x00000002  // Port B Clock Gating Control
+#define SYSCTL_RCGC2_GPIOA      0x00000001  // Port A Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGC0_WDT1       0x10000000  // WDT1 Clock Gating Control
+#define SYSCTL_SCGC0_CAN2       0x04000000  // CAN2 Clock Gating Control
+#define SYSCTL_SCGC0_CAN1       0x02000000  // CAN1 Clock Gating Control
+#define SYSCTL_SCGC0_CAN0       0x01000000  // CAN0 Clock Gating Control
+#define SYSCTL_SCGC0_PWM        0x00100000  // PWM Clock Gating Control
+#define SYSCTL_SCGC0_ADC1       0x00020000  // ADC1 Clock Gating Control
+#define SYSCTL_SCGC0_ADC0       0x00010000  // ADC0 Clock Gating Control
+#define SYSCTL_SCGC0_ADCSPD_M   0x00000F00  // ADC Sample Speed
+#define SYSCTL_SCGC0_ADCSPD125K 0x00000000  // 125K samples/second
+#define SYSCTL_SCGC0_ADCSPD250K 0x00000100  // 250K samples/second
+#define SYSCTL_SCGC0_ADCSPD500K 0x00000200  // 500K samples/second
+#define SYSCTL_SCGC0_ADCSPD1M   0x00000300  // 1M samples/second
+#define SYSCTL_SCGC0_ADC1SPD_M  0x00000C00  // ADC1 Sample Speed
+#define SYSCTL_SCGC0_ADC1SPD_125K \
+                                0x00000000  // 125K samples/second
+#define SYSCTL_SCGC0_ADC1SPD_250K \
+                                0x00000400  // 250K samples/second
+#define SYSCTL_SCGC0_ADC1SPD_500K \
+                                0x00000800  // 500K samples/second
+#define SYSCTL_SCGC0_ADC1SPD_1M 0x00000C00  // 1M samples/second
+#define SYSCTL_SCGC0_ADC0SPD_M  0x00000300  // ADC0 Sample Speed
+#define SYSCTL_SCGC0_ADC0SPD_125K \
+                                0x00000000  // 125K samples/second
+#define SYSCTL_SCGC0_ADC0SPD_250K \
+                                0x00000100  // 250K samples/second
+#define SYSCTL_SCGC0_ADC0SPD_500K \
+                                0x00000200  // 500K samples/second
+#define SYSCTL_SCGC0_ADC0SPD_1M 0x00000300  // 1M samples/second
+#define SYSCTL_SCGC0_HIB        0x00000040  // HIB Clock Gating Control
+#define SYSCTL_SCGC0_WDT0       0x00000008  // WDT0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGC1_EPI0       0x40000000  // EPI0 Clock Gating
+#define SYSCTL_SCGC1_I2S0       0x10000000  // I2S0 Clock Gating
+#define SYSCTL_SCGC1_COMP2      0x04000000  // Analog Comparator 2 Clock Gating
+#define SYSCTL_SCGC1_COMP1      0x02000000  // Analog Comparator 1 Clock Gating
+#define SYSCTL_SCGC1_COMP0      0x01000000  // Analog Comparator 0 Clock Gating
+#define SYSCTL_SCGC1_TIMER3     0x00080000  // Timer 3 Clock Gating Control
+#define SYSCTL_SCGC1_TIMER2     0x00040000  // Timer 2 Clock Gating Control
+#define SYSCTL_SCGC1_TIMER1     0x00020000  // Timer 1 Clock Gating Control
+#define SYSCTL_SCGC1_TIMER0     0x00010000  // Timer 0 Clock Gating Control
+#define SYSCTL_SCGC1_I2C1       0x00004000  // I2C1 Clock Gating Control
+#define SYSCTL_SCGC1_I2C0       0x00001000  // I2C0 Clock Gating Control
+#define SYSCTL_SCGC1_QEI1       0x00000200  // QEI1 Clock Gating Control
+#define SYSCTL_SCGC1_QEI0       0x00000100  // QEI0 Clock Gating Control
+#define SYSCTL_SCGC1_SSI1       0x00000020  // SSI1 Clock Gating Control
+#define SYSCTL_SCGC1_SSI0       0x00000010  // SSI0 Clock Gating Control
+#define SYSCTL_SCGC1_UART2      0x00000004  // UART2 Clock Gating Control
+#define SYSCTL_SCGC1_UART1      0x00000002  // UART1 Clock Gating Control
+#define SYSCTL_SCGC1_UART0      0x00000001  // UART0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGC2_EPHY0      0x40000000  // PHY0 Clock Gating Control
+#define SYSCTL_SCGC2_EMAC0      0x10000000  // MAC0 Clock Gating Control
+#define SYSCTL_SCGC2_USB0       0x00010000  // USB0 Clock Gating Control
+#define SYSCTL_SCGC2_UDMA       0x00002000  // Micro-DMA Clock Gating Control
+#define SYSCTL_SCGC2_GPIOJ      0x00000100  // Port J Clock Gating Control
+#define SYSCTL_SCGC2_GPIOH      0x00000080  // Port H Clock Gating Control
+#define SYSCTL_SCGC2_GPIOG      0x00000040  // Port G Clock Gating Control
+#define SYSCTL_SCGC2_GPIOF      0x00000020  // Port F Clock Gating Control
+#define SYSCTL_SCGC2_GPIOE      0x00000010  // Port E Clock Gating Control
+#define SYSCTL_SCGC2_GPIOD      0x00000008  // Port D Clock Gating Control
+#define SYSCTL_SCGC2_GPIOC      0x00000004  // Port C Clock Gating Control
+#define SYSCTL_SCGC2_GPIOB      0x00000002  // Port B Clock Gating Control
+#define SYSCTL_SCGC2_GPIOA      0x00000001  // Port A Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGC0_WDT1       0x10000000  // WDT1 Clock Gating Control
+#define SYSCTL_DCGC0_CAN2       0x04000000  // CAN2 Clock Gating Control
+#define SYSCTL_DCGC0_CAN1       0x02000000  // CAN1 Clock Gating Control
+#define SYSCTL_DCGC0_CAN0       0x01000000  // CAN0 Clock Gating Control
+#define SYSCTL_DCGC0_PWM        0x00100000  // PWM Clock Gating Control
+#define SYSCTL_DCGC0_ADC1       0x00020000  // ADC1 Clock Gating Control
+#define SYSCTL_DCGC0_ADC0       0x00010000  // ADC0 Clock Gating Control
+#define SYSCTL_DCGC0_HIB        0x00000040  // HIB Clock Gating Control
+#define SYSCTL_DCGC0_WDT0       0x00000008  // WDT0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGC1_EPI0       0x40000000  // EPI0 Clock Gating
+#define SYSCTL_DCGC1_I2S0       0x10000000  // I2S0 Clock Gating
+#define SYSCTL_DCGC1_COMP2      0x04000000  // Analog Comparator 2 Clock Gating
+#define SYSCTL_DCGC1_COMP1      0x02000000  // Analog Comparator 1 Clock Gating
+#define SYSCTL_DCGC1_COMP0      0x01000000  // Analog Comparator 0 Clock Gating
+#define SYSCTL_DCGC1_TIMER3     0x00080000  // Timer 3 Clock Gating Control
+#define SYSCTL_DCGC1_TIMER2     0x00040000  // Timer 2 Clock Gating Control
+#define SYSCTL_DCGC1_TIMER1     0x00020000  // Timer 1 Clock Gating Control
+#define SYSCTL_DCGC1_TIMER0     0x00010000  // Timer 0 Clock Gating Control
+#define SYSCTL_DCGC1_I2C1       0x00004000  // I2C1 Clock Gating Control
+#define SYSCTL_DCGC1_I2C0       0x00001000  // I2C0 Clock Gating Control
+#define SYSCTL_DCGC1_QEI1       0x00000200  // QEI1 Clock Gating Control
+#define SYSCTL_DCGC1_QEI0       0x00000100  // QEI0 Clock Gating Control
+#define SYSCTL_DCGC1_SSI1       0x00000020  // SSI1 Clock Gating Control
+#define SYSCTL_DCGC1_SSI0       0x00000010  // SSI0 Clock Gating Control
+#define SYSCTL_DCGC1_UART2      0x00000004  // UART2 Clock Gating Control
+#define SYSCTL_DCGC1_UART1      0x00000002  // UART1 Clock Gating Control
+#define SYSCTL_DCGC1_UART0      0x00000001  // UART0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGC2_EPHY0      0x40000000  // PHY0 Clock Gating Control
+#define SYSCTL_DCGC2_EMAC0      0x10000000  // MAC0 Clock Gating Control
+#define SYSCTL_DCGC2_USB0       0x00010000  // USB0 Clock Gating Control
+#define SYSCTL_DCGC2_UDMA       0x00002000  // Micro-DMA Clock Gating Control
+#define SYSCTL_DCGC2_GPIOJ      0x00000100  // Port J Clock Gating Control
+#define SYSCTL_DCGC2_GPIOH      0x00000080  // Port H Clock Gating Control
+#define SYSCTL_DCGC2_GPIOG      0x00000040  // Port G Clock Gating Control
+#define SYSCTL_DCGC2_GPIOF      0x00000020  // Port F Clock Gating Control
+#define SYSCTL_DCGC2_GPIOE      0x00000010  // Port E Clock Gating Control
+#define SYSCTL_DCGC2_GPIOD      0x00000008  // Port D Clock Gating Control
+#define SYSCTL_DCGC2_GPIOC      0x00000004  // Port C Clock Gating Control
+#define SYSCTL_DCGC2_GPIOB      0x00000002  // Port B Clock Gating Control
+#define SYSCTL_DCGC2_GPIOA      0x00000001  // Port A Clock Gating Control
 
 //*****************************************************************************
 //
@@ -661,7 +1267,8 @@
 // register.
 //
 //*****************************************************************************
-#define SYSCTL_DSLPCLKCFG_D_M   0x1F800000  // Divider Field Override.
+#define SYSCTL_DSLPCLKCFG_D_M   0x1F800000  // Divider Field Override
+#define SYSCTL_DSLPCLKCFG_D_1   0x00000000  // System clock /1
 #define SYSCTL_DSLPCLKCFG_D_2   0x00800000  // System clock /2
 #define SYSCTL_DSLPCLKCFG_D_3   0x01000000  // System clock /3
 #define SYSCTL_DSLPCLKCFG_D_4   0x01800000  // System clock /4
@@ -725,544 +1332,70 @@
 #define SYSCTL_DSLPCLKCFG_D_62  0x1E800000  // System clock /62
 #define SYSCTL_DSLPCLKCFG_D_63  0x1F000000  // System clock /63
 #define SYSCTL_DSLPCLKCFG_D_64  0x1F800000  // System clock /64
-#define SYSCTL_DSLPCLKCFG_O_M   0x00000070  // Clock Source.
-#define SYSCTL_DSLPCLKCFG_O_IGN 0x00000000  // Do not override
-#define SYSCTL_DSLPCLKCFG_O_IO  0x00000010  // Use the internal oscillator
-#define SYSCTL_DSLPCLKCFG_O_30  0x00000030  // Use the 30 KHz internal osc.
-#define SYSCTL_DSLPCLKCFG_O_32  0x00000070  // Use the 32 KHz external osc.
-#define SYSCTL_DSLPCLKCFG_IOSC  0x00000001  // IOSC Clock Source.
+#define SYSCTL_DSLPCLKCFG_O_M   0x00000070  // Clock Source
+#define SYSCTL_DSLPCLKCFG_O_IGN 0x00000000  // MOSC
+#define SYSCTL_DSLPCLKCFG_O_IO  0x00000010  // PIOSC
+#define SYSCTL_DSLPCLKCFG_O_30  0x00000030  // 30 kHz
+#define SYSCTL_DSLPCLKCFG_O_32  0x00000070  // 32.768 kHz
+#define SYSCTL_DSLPCLKCFG_IOSC  0x00000001  // IOSC Clock Source
 #define SYSCTL_DSLPCLKCFG_D_S   23
 
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_CLKVCLR register.
-//
-//*****************************************************************************
-#define SYSCTL_CLKVCLR_VERCLR   0x00000001  // Clock Verification Clear.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_LDOARST register.
-//
-//*****************************************************************************
-#define SYSCTL_LDOARST_LDOARST  0x00000001  // LDO Reset.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_SRCR0 register.
-//
-//*****************************************************************************
-#define SYSCTL_SRCR0_WDT1       0x10000000  // WDT1 Reset Control.
-#define SYSCTL_SRCR0_CAN2       0x04000000  // CAN2 Reset Control.
-#define SYSCTL_SRCR0_CAN1       0x02000000  // CAN1 Reset Control.
-#define SYSCTL_SRCR0_CAN0       0x01000000  // CAN0 Reset Control.
-#define SYSCTL_SRCR0_PWM        0x00100000  // PWM Reset Control.
-#define SYSCTL_SRCR0_ADC1       0x00020000  // ADC1 Reset Control.
-#define SYSCTL_SRCR0_ADC0       0x00010000  // ADC0 Reset Control.
-#define SYSCTL_SRCR0_HIB        0x00000040  // HIB Reset Control.
-#define SYSCTL_SRCR0_WDT0       0x00000008  // WDT0 Reset Control.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_SRCR1 register.
-//
-//*****************************************************************************
-#define SYSCTL_SRCR1_EPI0       0x40000000  // EPI0 Reset Control.
-#define SYSCTL_SRCR1_I2S0       0x10000000  // I2S 0 Reset Control.
-#define SYSCTL_SRCR1_COMP2      0x04000000  // Analog Comp 2 Reset Control.
-#define SYSCTL_SRCR1_COMP1      0x02000000  // Analog Comp 1 Reset Control.
-#define SYSCTL_SRCR1_COMP0      0x01000000  // Analog Comp 0 Reset Control.
-#define SYSCTL_SRCR1_TIMER3     0x00080000  // Timer 3 Reset Control.
-#define SYSCTL_SRCR1_TIMER2     0x00040000  // Timer 2 Reset Control.
-#define SYSCTL_SRCR1_TIMER1     0x00020000  // Timer 1 Reset Control.
-#define SYSCTL_SRCR1_TIMER0     0x00010000  // Timer 0 Reset Control.
-#define SYSCTL_SRCR1_I2C1       0x00004000  // I2C1 Reset Control.
-#define SYSCTL_SRCR1_I2C0       0x00001000  // I2C0 Reset Control.
-#define SYSCTL_SRCR1_QEI1       0x00000200  // QEI1 Reset Control.
-#define SYSCTL_SRCR1_QEI0       0x00000100  // QEI0 Reset Control.
-#define SYSCTL_SRCR1_SSI1       0x00000020  // SSI1 Reset Control.
-#define SYSCTL_SRCR1_SSI0       0x00000010  // SSI0 Reset Control.
-#define SYSCTL_SRCR1_UART2      0x00000004  // UART2 Reset Control.
-#define SYSCTL_SRCR1_UART1      0x00000002  // UART1 Reset Control.
-#define SYSCTL_SRCR1_UART0      0x00000001  // UART0 Reset Control.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_SRCR2 register.
-//
-//*****************************************************************************
-#define SYSCTL_SRCR2_EPHY0      0x40000000  // PHY0 Reset Control.
-#define SYSCTL_SRCR2_EMAC0      0x10000000  // MAC0 Reset Control.
-#define SYSCTL_SRCR2_USB0       0x00010000  // USB0 Reset Control.
-#define SYSCTL_SRCR2_UDMA       0x00002000  // UDMA Reset Control.
-#define SYSCTL_SRCR2_GPIOJ      0x00000100  // Port J Reset Control.
-#define SYSCTL_SRCR2_GPIOH      0x00000080  // Port H Reset Control.
-#define SYSCTL_SRCR2_GPIOG      0x00000040  // Port G Reset Control.
-#define SYSCTL_SRCR2_GPIOF      0x00000020  // Port F Reset Control.
-#define SYSCTL_SRCR2_GPIOE      0x00000010  // Port E Reset Control.
-#define SYSCTL_SRCR2_GPIOD      0x00000008  // Port D Reset Control.
-#define SYSCTL_SRCR2_GPIOC      0x00000004  // Port C Reset Control.
-#define SYSCTL_SRCR2_GPIOB      0x00000002  // Port B Reset Control.
-#define SYSCTL_SRCR2_GPIOA      0x00000001  // Port A Reset Control.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_RIS register.
-//
-//*****************************************************************************
-#define SYSCTL_RIS_MOSCPUPRIS   0x00000100  // MOSC Power Up Raw Interrupt
-                                            // Status.
-#define SYSCTL_RIS_USBPLLLRIS   0x00000080  // USB PLL Lock Raw Interrupt
-                                            // Status.
-#define SYSCTL_RIS_PLLLRIS      0x00000040  // PLL Lock Raw Interrupt Status.
-#define SYSCTL_RIS_CLRIS        0x00000020  // Current Limit Raw Interrupt
-                                            // Status.
-#define SYSCTL_RIS_IOFRIS       0x00000010  // Internal Oscillator Fault Raw
-                                            // Interrupt Status.
-#define SYSCTL_RIS_MOFRIS       0x00000008  // Main Oscillator Fault Raw
-                                            // Interrupt Status.
-#define SYSCTL_RIS_LDORIS       0x00000004  // LDO Power Unregulated Raw
-                                            // Interrupt Status.
-#define SYSCTL_RIS_BORRIS       0x00000002  // Brown-Out Reset Raw Interrupt
-                                            // Status.
-#define SYSCTL_RIS_PLLFRIS      0x00000001  // PLL Fault Raw Interrupt Status.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_IMC register.
-//
-//*****************************************************************************
-#define SYSCTL_IMC_MOSCPUPIM    0x00000100  // MOSC Power Up Interrupt Mask.
-#define SYSCTL_IMC_USBPLLLIM    0x00000080  // USB PLL Lock Interrupt Mask.
-#define SYSCTL_IMC_PLLLIM       0x00000040  // PLL Lock Interrupt Mask.
-#define SYSCTL_IMC_CLIM         0x00000020  // Current Limit Interrupt Mask.
-#define SYSCTL_IMC_IOFIM        0x00000010  // Internal Oscillator Fault
-                                            // Interrupt Mask.
-#define SYSCTL_IMC_MOFIM        0x00000008  // Main Oscillator Fault Interrupt
-                                            // Mask.
-#define SYSCTL_IMC_LDOIM        0x00000004  // LDO Power Unregulated Interrupt
-                                            // Mask.
-#define SYSCTL_IMC_BORIM        0x00000002  // Brown-Out Reset Interrupt Mask.
-#define SYSCTL_IMC_PLLFIM       0x00000001  // PLL Fault Interrupt Mask.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_MISC register.
-//
-//*****************************************************************************
-#define SYSCTL_MISC_MOSCPUPMIS  0x00000100  // MOSC Power Up Masked Interrupt
-                                            // Status.
-#define SYSCTL_MISC_USBPLLLMIS  0x00000080  // USB PLL Lock Masked Interrupt
-                                            // Status.
-#define SYSCTL_MISC_PLLLMIS     0x00000040  // PLL Lock Masked Interrupt
-                                            // Status.
-#define SYSCTL_MISC_CLMIS       0x00000020  // Current Limit Masked Interrupt
-                                            // Status.
-#define SYSCTL_MISC_IOFMIS      0x00000010  // Internal Oscillator Fault Masked
-                                            // Interrupt Status.
-#define SYSCTL_MISC_MOFMIS      0x00000008  // Main Oscillator Fault Masked
-                                            // Interrupt Status.
-#define SYSCTL_MISC_LDOMIS      0x00000004  // LDO Power Unregulated Masked
-                                            // Interrupt Status.
-#define SYSCTL_MISC_BORMIS      0x00000002  // BOR Masked Interrupt Status.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_RCGC0 register.
-//
-//*****************************************************************************
-#define SYSCTL_RCGC0_WDT1       0x10000000  // WDT1 Clock Gating Control.
-#define SYSCTL_RCGC0_CAN2       0x04000000  // CAN2 Clock Gating Control.
-#define SYSCTL_RCGC0_CAN1       0x02000000  // CAN1 Clock Gating Control.
-#define SYSCTL_RCGC0_CAN0       0x01000000  // CAN0 Clock Gating Control.
-#define SYSCTL_RCGC0_PWM        0x00100000  // PWM Clock Gating Control.
-#define SYSCTL_RCGC0_ADC1       0x00020000  // ADC1 Clock Gating Control.
-#define SYSCTL_RCGC0_ADC0       0x00010000  // ADC0 Clock Gating Control.
-#define SYSCTL_RCGC0_ADCSPD_M   0x00000F00  // ADC Sample Speed.
-#define SYSCTL_RCGC0_ADCSPD125K 0x00000000  // 125K samples/second
-#define SYSCTL_RCGC0_ADCSPD250K 0x00000100  // 250K samples/second
-#define SYSCTL_RCGC0_ADCSPD500K 0x00000200  // 500K samples/second
-#define SYSCTL_RCGC0_ADCSPD1M   0x00000300  // 1M samples/second
-#define SYSCTL_RCGC0_ADC1SPD_M  0x00000C00  // ADC1 Sample Speed.
-#define SYSCTL_RCGC0_ADC1SPD_1M 0x00000C00  // 1M samples/second
-#define SYSCTL_RCGC0_ADC0SPD_M  0x00000300  // ADC0 Sample Speed.
-#define SYSCTL_RCGC0_ADC0SPD_1M 0x00000300  // 1M samples/second
-#define SYSCTL_RCGC0_HIB        0x00000040  // HIB Clock Gating Control.
-#define SYSCTL_RCGC0_WDT0       0x00000008  // WDT0 Clock Gating Control.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_RCGC1 register.
-//
-//*****************************************************************************
-#define SYSCTL_RCGC1_EPI0       0x40000000  // EPI0 Clock Gating.
-#define SYSCTL_RCGC1_I2S0       0x10000000  // I2S0 Clock Gating Control.
-#define SYSCTL_RCGC1_COMP2      0x04000000  // Analog Comparator 2 Clock
-                                            // Gating.
-#define SYSCTL_RCGC1_COMP1      0x02000000  // Analog Comparator 1 Clock
-                                            // Gating.
-#define SYSCTL_RCGC1_COMP0      0x01000000  // Analog Comparator 0 Clock
-                                            // Gating.
-#define SYSCTL_RCGC1_TIMER3     0x00080000  // Timer 3 Clock Gating Control.
-#define SYSCTL_RCGC1_TIMER2     0x00040000  // Timer 2 Clock Gating Control.
-#define SYSCTL_RCGC1_TIMER1     0x00020000  // Timer 1 Clock Gating Control.
-#define SYSCTL_RCGC1_TIMER0     0x00010000  // Timer 0 Clock Gating Control.
-#define SYSCTL_RCGC1_I2C1       0x00004000  // I2C1 Clock Gating Control.
-#define SYSCTL_RCGC1_I2C0       0x00001000  // I2C0 Clock Gating Control.
-#define SYSCTL_RCGC1_QEI1       0x00000200  // QEI1 Clock Gating Control.
-#define SYSCTL_RCGC1_QEI0       0x00000100  // QEI0 Clock Gating Control.
-#define SYSCTL_RCGC1_SSI1       0x00000020  // SSI1 Clock Gating Control.
-#define SYSCTL_RCGC1_SSI0       0x00000010  // SSI0 Clock Gating Control.
-#define SYSCTL_RCGC1_UART2      0x00000004  // UART2 Clock Gating Control.
-#define SYSCTL_RCGC1_UART1      0x00000002  // UART1 Clock Gating Control.
-#define SYSCTL_RCGC1_UART0      0x00000001  // UART0 Clock Gating Control.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_RCGC2 register.
-//
-//*****************************************************************************
-#define SYSCTL_RCGC2_EPHY0      0x40000000  // PHY0 Clock Gating Control.
-#define SYSCTL_RCGC2_EMAC0      0x10000000  // MAC0 Clock Gating Control.
-#define SYSCTL_RCGC2_USB0       0x00010000  // USB0 Clock Gating Control.
-#define SYSCTL_RCGC2_UDMA       0x00002000  // UDMA Clock Gating Control.
-#define SYSCTL_RCGC2_GPIOJ      0x00000100  // Port J Clock Gating Control.
-#define SYSCTL_RCGC2_GPIOH      0x00000080  // Port H Clock Gating Control.
-#define SYSCTL_RCGC2_GPIOG      0x00000040  // Port G Clock Gating Control.
-#define SYSCTL_RCGC2_GPIOF      0x00000020  // Port F Clock Gating Control.
-#define SYSCTL_RCGC2_GPIOE      0x00000010  // Port E Clock Gating Control.
-#define SYSCTL_RCGC2_GPIOD      0x00000008  // Port D Clock Gating Control.
-#define SYSCTL_RCGC2_GPIOC      0x00000004  // Port C Clock Gating Control.
-#define SYSCTL_RCGC2_GPIOB      0x00000002  // Port B Clock Gating Control.
-#define SYSCTL_RCGC2_GPIOA      0x00000001  // Port A Clock Gating Control.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_SCGC0 register.
-//
-//*****************************************************************************
-#define SYSCTL_SCGC0_WDT1       0x10000000  // WDT1 Clock Gating Control.
-#define SYSCTL_SCGC0_CAN2       0x04000000  // CAN2 Clock Gating Control.
-#define SYSCTL_SCGC0_CAN1       0x02000000  // CAN1 Clock Gating Control.
-#define SYSCTL_SCGC0_CAN0       0x01000000  // CAN0 Clock Gating Control.
-#define SYSCTL_SCGC0_PWM        0x00100000  // PWM Clock Gating Control.
-#define SYSCTL_SCGC0_ADC1       0x00020000  // ADC1 Clock Gating Control.
-#define SYSCTL_SCGC0_ADC0       0x00010000  // ADC0 Clock Gating Control.
-#define SYSCTL_SCGC0_ADCSPD_M   0x00000F00  // ADC Sample Speed.
-#define SYSCTL_SCGC0_ADCSPD125K 0x00000000  // 125K samples/second
-#define SYSCTL_SCGC0_ADCSPD250K 0x00000100  // 250K samples/second
-#define SYSCTL_SCGC0_ADCSPD500K 0x00000200  // 500K samples/second
-#define SYSCTL_SCGC0_ADCSPD1M   0x00000300  // 1M samples/second
-#define SYSCTL_SCGC0_ADC1SPD_M  0x00000C00  // ADC1 Sample Speed.
-#define SYSCTL_SCGC0_ADC1SPD_1M 0x00000C00  // 1M samples/second
-#define SYSCTL_SCGC0_ADC0SPD_M  0x00000300  // ADC0 Sample Speed.
-#define SYSCTL_SCGC0_ADC0SPD_1M 0x00000300  // 1M samples/second
-#define SYSCTL_SCGC0_HIB        0x00000040  // HIB Clock Gating Control.
-#define SYSCTL_SCGC0_WDT0       0x00000008  // WDT0 Clock Gating Control.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_SCGC1 register.
-//
-//*****************************************************************************
-#define SYSCTL_SCGC1_EPI0       0x40000000  // EPI0 Clock Gating.
-#define SYSCTL_SCGC1_I2S0       0x10000000  // I2S 0 Clock Gating.
-#define SYSCTL_SCGC1_COMP2      0x04000000  // Analog Comparator 2 Clock
-                                            // Gating.
-#define SYSCTL_SCGC1_COMP1      0x02000000  // Analog Comparator 1 Clock
-                                            // Gating.
-#define SYSCTL_SCGC1_COMP0      0x01000000  // Analog Comparator 0 Clock
-                                            // Gating.
-#define SYSCTL_SCGC1_TIMER3     0x00080000  // Timer 3 Clock Gating Control.
-#define SYSCTL_SCGC1_TIMER2     0x00040000  // Timer 2 Clock Gating Control.
-#define SYSCTL_SCGC1_TIMER1     0x00020000  // Timer 1 Clock Gating Control.
-#define SYSCTL_SCGC1_TIMER0     0x00010000  // Timer 0 Clock Gating Control.
-#define SYSCTL_SCGC1_I2C1       0x00004000  // I2C1 Clock Gating Control.
-#define SYSCTL_SCGC1_I2C0       0x00001000  // I2C0 Clock Gating Control.
-#define SYSCTL_SCGC1_QEI1       0x00000200  // QEI1 Clock Gating Control.
-#define SYSCTL_SCGC1_QEI0       0x00000100  // QEI0 Clock Gating Control.
-#define SYSCTL_SCGC1_SSI1       0x00000020  // SSI1 Clock Gating Control.
-#define SYSCTL_SCGC1_SSI0       0x00000010  // SSI0 Clock Gating Control.
-#define SYSCTL_SCGC1_UART2      0x00000004  // UART2 Clock Gating Control.
-#define SYSCTL_SCGC1_UART1      0x00000002  // UART1 Clock Gating Control.
-#define SYSCTL_SCGC1_UART0      0x00000001  // UART0 Clock Gating Control.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_SCGC2 register.
-//
-//*****************************************************************************
-#define SYSCTL_SCGC2_EPHY0      0x40000000  // PHY0 Clock Gating Control.
-#define SYSCTL_SCGC2_EMAC0      0x10000000  // MAC0 Clock Gating Control.
-#define SYSCTL_SCGC2_USB0       0x00010000  // USB0 Clock Gating Control.
-#define SYSCTL_SCGC2_UDMA       0x00002000  // UDMA Clock Gating Control.
-#define SYSCTL_SCGC2_GPIOJ      0x00000100  // GPIO Port J Present.
-#define SYSCTL_SCGC2_GPIOH      0x00000080  // Port H Clock Gating Control.
-#define SYSCTL_SCGC2_GPIOG      0x00000040  // Port G Clock Gating Control.
-#define SYSCTL_SCGC2_GPIOF      0x00000020  // Port F Clock Gating Control.
-#define SYSCTL_SCGC2_GPIOE      0x00000010  // Port E Clock Gating Control.
-#define SYSCTL_SCGC2_GPIOD      0x00000008  // Port D Clock Gating Control.
-#define SYSCTL_SCGC2_GPIOC      0x00000004  // Port C Clock Gating Control.
-#define SYSCTL_SCGC2_GPIOB      0x00000002  // Port B Clock Gating Control.
-#define SYSCTL_SCGC2_GPIOA      0x00000001  // Port A Clock Gating Control.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_DCGC0 register.
-//
-//*****************************************************************************
-#define SYSCTL_DCGC0_WDT1       0x10000000  // WDT1 Clock Gating Control.
-#define SYSCTL_DCGC0_CAN2       0x04000000  // CAN2 Clock Gating Control.
-#define SYSCTL_DCGC0_CAN1       0x02000000  // CAN1 Clock Gating Control.
-#define SYSCTL_DCGC0_CAN0       0x01000000  // CAN0 Clock Gating Control.
-#define SYSCTL_DCGC0_PWM        0x00100000  // PWM Clock Gating Control.
-#define SYSCTL_DCGC0_ADC1       0x00020000  // ADC1 Clock Gating Control.
-#define SYSCTL_DCGC0_ADC0       0x00010000  // ADC0 Clock Gating Control.
-#define SYSCTL_DCGC0_ADCSPD_M   0x00000F00  // ADC Sample Speed.
-#define SYSCTL_DCGC0_ADCSPD125K 0x00000000  // 125K samples/second
-#define SYSCTL_DCGC0_ADCSPD250K 0x00000100  // 250K samples/second
-#define SYSCTL_DCGC0_ADCSPD500K 0x00000200  // 500K samples/second
-#define SYSCTL_DCGC0_ADCSPD1M   0x00000300  // 1M samples/second
-#define SYSCTL_DCGC0_ADC1SPD_M  0x00000C00  // ADC1 Sample Speed.
-#define SYSCTL_DCGC0_ADC1SPD_1M 0x00000C00  // 1M samples/second
-#define SYSCTL_DCGC0_ADC0SPD_M  0x00000300  // ADC0 Sample Speed.
-#define SYSCTL_DCGC0_ADC0SPD_1M 0x00000300  // 1M samples/second
-#define SYSCTL_DCGC0_HIB        0x00000040  // HIB Clock Gating Control.
-#define SYSCTL_DCGC0_WDT0       0x00000008  // WDT0 Clock Gating Control.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_DCGC1 register.
-//
-//*****************************************************************************
-#define SYSCTL_DCGC1_EPI0       0x40000000  // EPI0 Clock Gating.
-#define SYSCTL_DCGC1_I2S0       0x10000000  // I2S 0 Clock Gating.
-#define SYSCTL_DCGC1_COMP2      0x04000000  // Analog Comparator 2 Clock
-                                            // Gating.
-#define SYSCTL_DCGC1_COMP1      0x02000000  // Analog Comparator 1 Clock
-                                            // Gating.
-#define SYSCTL_DCGC1_COMP0      0x01000000  // Analog Comparator 0 Clock
-                                            // Gating.
-#define SYSCTL_DCGC1_TIMER3     0x00080000  // Timer 3 Clock Gating Control.
-#define SYSCTL_DCGC1_TIMER2     0x00040000  // Timer 2 Clock Gating Control.
-#define SYSCTL_DCGC1_TIMER1     0x00020000  // Timer 1 Clock Gating Control.
-#define SYSCTL_DCGC1_TIMER0     0x00010000  // Timer 0 Clock Gating Control.
-#define SYSCTL_DCGC1_I2C1       0x00004000  // I2C1 Clock Gating Control.
-#define SYSCTL_DCGC1_I2C0       0x00001000  // I2C0 Clock Gating Control.
-#define SYSCTL_DCGC1_QEI1       0x00000200  // QEI1 Clock Gating Control.
-#define SYSCTL_DCGC1_QEI0       0x00000100  // QEI0 Clock Gating Control.
-#define SYSCTL_DCGC1_SSI1       0x00000020  // SSI1 Clock Gating Control.
-#define SYSCTL_DCGC1_SSI0       0x00000010  // SSI0 Clock Gating Control.
-#define SYSCTL_DCGC1_UART2      0x00000004  // UART2 Clock Gating Control.
-#define SYSCTL_DCGC1_UART1      0x00000002  // UART1 Clock Gating Control.
-#define SYSCTL_DCGC1_UART0      0x00000001  // UART0 Clock Gating Control.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_DCGC2 register.
-//
-//*****************************************************************************
-#define SYSCTL_DCGC2_EPHY0      0x40000000  // PHY0 Clock Gating Control.
-#define SYSCTL_DCGC2_EMAC0      0x10000000  // MAC0 Clock Gating Control.
-#define SYSCTL_DCGC2_USB0       0x00010000  // USB0 Clock Gating Control.
-#define SYSCTL_DCGC2_UDMA       0x00002000  // UDMA Clock Gating Control.
-#define SYSCTL_DCGC2_GPIOJ      0x00000100  // GPIO Port J Present.
-#define SYSCTL_DCGC2_GPIOH      0x00000080  // Port H Clock Gating Control.
-#define SYSCTL_DCGC2_GPIOG      0x00000040  // Port G Clock Gating Control.
-#define SYSCTL_DCGC2_GPIOF      0x00000020  // Port F Clock Gating Control.
-#define SYSCTL_DCGC2_GPIOE      0x00000010  // Port E Clock Gating Control.
-#define SYSCTL_DCGC2_GPIOD      0x00000008  // Port D Clock Gating Control.
-#define SYSCTL_DCGC2_GPIOC      0x00000004  // Port C Clock Gating Control.
-#define SYSCTL_DCGC2_GPIOB      0x00000002  // Port B Clock Gating Control.
-#define SYSCTL_DCGC2_GPIOA      0x00000001  // Port A Clock Gating Control.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_DC5 register.
-//
-//*****************************************************************************
-#define SYSCTL_DC5_PWMFAULT3    0x08000000  // PWM Fault 3 Pin Present.
-#define SYSCTL_DC5_PWMFAULT2    0x04000000  // PWM Fault 2 Pin Present.
-#define SYSCTL_DC5_PWMFAULT1    0x02000000  // PWM Fault 1 Pin Present.
-#define SYSCTL_DC5_PWMFAULT0    0x01000000  // PWM Fault 0 Pin Present.
-#define SYSCTL_DC5_PWMEFLT      0x00200000  // PWM Extended Fault feature is
-                                            // active.
-#define SYSCTL_DC5_PWMESYNC     0x00100000  // PWM Extended SYNC feature is
-                                            // active.
-#define SYSCTL_DC5_PWM7         0x00000080  // PWM7 Pin Present.
-#define SYSCTL_DC5_PWM6         0x00000040  // PWM6 Pin Present.
-#define SYSCTL_DC5_PWM5         0x00000020  // PWM5 Pin Present.
-#define SYSCTL_DC5_PWM4         0x00000010  // PWM4 Pin Present.
-#define SYSCTL_DC5_PWM3         0x00000008  // PWM3 Pin Present.
-#define SYSCTL_DC5_PWM2         0x00000004  // PWM2 Pin Present.
-#define SYSCTL_DC5_PWM1         0x00000002  // PWM1 Pin Present.
-#define SYSCTL_DC5_PWM0         0x00000001  // PWM0 Pin Present.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_DC6 register.
-//
-//*****************************************************************************
-#define SYSCTL_DC6_USB0PHY      0x00000010  // This specifies that USB0 PHY is
-                                            // present.
-#define SYSCTL_DC6_USB0_M       0x00000003  // This specifies that USB0 is
-                                            // present and its capability.
-#define SYSCTL_DC6_USB0_HOSTDEV 0x00000002  // USB is DEVICE or HOST
-#define SYSCTL_DC6_USB0_OTG     0x00000003  // USB is OTG
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_GPIOHSCTL
-// register.
-//
-//*****************************************************************************
-#define SYSCTL_GPIOHSCTL_PORTH  0x00000080  // Port H High-Speed.
-#define SYSCTL_GPIOHSCTL_PORTG  0x00000040  // Port G High-Speed.
-#define SYSCTL_GPIOHSCTL_PORTF  0x00000020  // Port F High-Speed.
-#define SYSCTL_GPIOHSCTL_PORTE  0x00000010  // Port E High-Speed.
-#define SYSCTL_GPIOHSCTL_PORTD  0x00000008  // Port D High-Speed.
-#define SYSCTL_GPIOHSCTL_PORTC  0x00000004  // Port C High-Speed.
-#define SYSCTL_GPIOHSCTL_PORTB  0x00000002  // Port B High-Speed.
-#define SYSCTL_GPIOHSCTL_PORTA  0x00000001  // Port A High-Speed.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_MOSCCTL register.
-//
-//*****************************************************************************
-#define SYSCTL_MOSCCTL_CVAL     0x00000001  // Clock Validation for MOSC.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_DC7 register.
-//
-//*****************************************************************************
-#define SYSCTL_DC7_DMACH30      0x40000000  // SW.
-#define SYSCTL_DC7_DMACH29      0x20000000  // I2S0_TX.
-#define SYSCTL_DC7_DMACH28      0x10000000  // I2S0_RX.
-#define SYSCTL_DC7_DMACH27      0x08000000  // ADC1_SS3.
-#define SYSCTL_DC7_DMACH26      0x04000000  // ADC1_SS2.
-#define SYSCTL_DC7_DMACH25      0x02000000  // SSI1_TX / ADC1_SS1.
-#define SYSCTL_DC7_SSI1_TX      0x02000000  // SSI1 TX on uDMA Ch25.
-#define SYSCTL_DC7_SSI1_RX      0x01000000  // SSI1 RX on uDMA Ch24.
-#define SYSCTL_DC7_DMACH24      0x01000000  // SSI1_RX / ADC1_SS0.
-#define SYSCTL_DC7_UART1_TX     0x00800000  // UART1 TX on uDMA Ch23.
-#define SYSCTL_DC7_DMACH23      0x00800000  // UART1_TX.
-#define SYSCTL_DC7_DMACH22      0x00400000  // UART1_RX.
-#define SYSCTL_DC7_UART1_RX     0x00400000  // UART1 RX on uDMA Ch22.
-#define SYSCTL_DC7_DMACH21      0x00200000  // Timer1B / EPI0_TX.
-#define SYSCTL_DC7_DMACH20      0x00100000  // Timer1A / EPI0_RX.
-#define SYSCTL_DC7_DMACH19      0x00080000  // Timer0B / Timer1B.
-#define SYSCTL_DC7_DMACH18      0x00040000  // Timer0A / Timer1A.
-#define SYSCTL_DC7_DMACH17      0x00020000  // ADC0_SS3.
-#define SYSCTL_DC7_DMACH16      0x00010000  // ADC0_SS2.
-#define SYSCTL_DC7_DMACH15      0x00008000  // ADC0_SS1 / Timer2B.
-#define SYSCTL_DC7_DMACH14      0x00004000  // ADC0_SS0 / Timer2A.
-#define SYSCTL_DC7_DMACH13      0x00002000  // UART2_TX.
-#define SYSCTL_DC7_DMACH12      0x00001000  // UART2_RX.
-#define SYSCTL_DC7_SSI0_TX      0x00000800  // SSI0 TX on uDMA Ch11.
-#define SYSCTL_DC7_DMACH11      0x00000800  // SSI0_TX / UART1_TX.
-#define SYSCTL_DC7_SSI0_RX      0x00000400  // SSI0 RX on uDMA Ch10.
-#define SYSCTL_DC7_DMACH10      0x00000400  // SSI0_RX / UART1_RX.
-#define SYSCTL_DC7_UART0_TX     0x00000200  // UART0 TX on uDMA Ch9.
-#define SYSCTL_DC7_DMACH9       0x00000200  // UART0_TX / SSI1_TX.
-#define SYSCTL_DC7_DMACH8       0x00000100  // UART0_RX / SSI1_RX.
-#define SYSCTL_DC7_UART0_RX     0x00000100  // UART0 RX on uDMA Ch8.
-#define SYSCTL_DC7_DMACH7       0x00000080  // ETH_TX / Timer2B.
-#define SYSCTL_DC7_DMACH6       0x00000040  // ETH_RX / Timer2A.
-#define SYSCTL_DC7_DMACH5       0x00000020  // USB_EP3_TX / Timer2B.
-#define SYSCTL_DC7_USB_EP3_TX   0x00000020  // USB EP3 TX on uDMA Ch5.
-#define SYSCTL_DC7_USB_EP3_RX   0x00000010  // USB EP3 RX on uDMA Ch4.
-#define SYSCTL_DC7_DMACH4       0x00000010  // USB_EP3_RX / Timer2A.
-#define SYSCTL_DC7_USB_EP2_TX   0x00000008  // USB EP2 TX on uDMA Ch3.
-#define SYSCTL_DC7_DMACH3       0x00000008  // USB_EP2_TX / Timer3B.
-#define SYSCTL_DC7_USB_EP2_RX   0x00000004  // USB EP2 RX on uDMA Ch2.
-#define SYSCTL_DC7_DMACH2       0x00000004  // USB_EP2_RX / Timer3A.
-#define SYSCTL_DC7_USB_EP1_TX   0x00000002  // USB EP1 TX on uDMA Ch1.
-#define SYSCTL_DC7_DMACH1       0x00000002  // USB_EP1_TX / UART2_TX.
-#define SYSCTL_DC7_DMACH0       0x00000001  // USB_EP1_RX / UART2_RX.
-#define SYSCTL_DC7_USB_EP1_RX   0x00000001  // USB EP1 RX on uDMA Ch0.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_DC8 register.
-//
-//*****************************************************************************
-#define SYSCTL_DC8_ADC1AIN15    0x80000000  // ADC Module 1 AIN15 Pin Present.
-#define SYSCTL_DC8_ADC1AIN14    0x40000000  // ADC Module 1 AIN14 Pin Present.
-#define SYSCTL_DC8_ADC1AIN13    0x20000000  // ADC Module 1 AIN13 Pin Present.
-#define SYSCTL_DC8_ADC1AIN12    0x10000000  // ADC Module 1 AIN12 Pin Present.
-#define SYSCTL_DC8_ADC1AIN11    0x08000000  // ADC1 11 Pin Present.
-#define SYSCTL_DC8_ADC1AIN10    0x04000000  // ADC1 10 Pin Present.
-#define SYSCTL_DC8_ADC1AIN9     0x02000000  // ADC1 9 Pin Present.
-#define SYSCTL_DC8_ADC1AIN8     0x01000000  // ADC1 8 Pin Present.
-#define SYSCTL_DC8_ADC1AIN7     0x00800000  // ADC1 7 Pin Present.
-#define SYSCTL_DC8_ADC1AIN6     0x00400000  // ADC1 6 Pin Present.
-#define SYSCTL_DC8_ADC1AIN5     0x00200000  // ADC1 5 Pin Present.
-#define SYSCTL_DC8_ADC1AIN4     0x00100000  // ADC1 4 Pin Present.
-#define SYSCTL_DC8_ADC1AIN3     0x00080000  // ADC1 3 Pin Present.
-#define SYSCTL_DC8_ADC1AIN2     0x00040000  // ADC1 2 Pin Present.
-#define SYSCTL_DC8_ADC1AIN1     0x00020000  // ADC1 1 Pin Present.
-#define SYSCTL_DC8_ADC1AIN0     0x00010000  // ADC1 0 Pin Present.
-#define SYSCTL_DC8_ADC0AIN15    0x00008000  // ADC Module 0 AIN15 Pin Present.
-#define SYSCTL_DC8_ADC0AIN14    0x00004000  // ADC Module 0 AIN14 Pin Present.
-#define SYSCTL_DC8_ADC0AIN13    0x00002000  // ADC Module 0 AIN13 Pin Present.
-#define SYSCTL_DC8_ADC0AIN12    0x00001000  // ADC Module 0 AIN12 Pin Present.
-#define SYSCTL_DC8_ADC0AIN11    0x00000800  // ADC0 11 Pin Present.
-#define SYSCTL_DC8_ADC0AIN10    0x00000400  // ADC0 10 Pin Present.
-#define SYSCTL_DC8_ADC0AIN9     0x00000200  // ADC0 9 Pin Present.
-#define SYSCTL_DC8_ADC0AIN8     0x00000100  // ADC0 8 Pin Present.
-#define SYSCTL_DC8_ADC0AIN7     0x00000080  // ADC0 7 Pin Present.
-#define SYSCTL_DC8_ADC0AIN6     0x00000040  // ADC0 6 Pin Present.
-#define SYSCTL_DC8_ADC0AIN5     0x00000020  // ADC0 5 Pin Present.
-#define SYSCTL_DC8_ADC0AIN4     0x00000010  // ADC0 4 Pin Present.
-#define SYSCTL_DC8_ADC0AIN3     0x00000008  // ADC0 3 Pin Present.
-#define SYSCTL_DC8_ADC0AIN2     0x00000004  // ADC0 2 Pin Present.
-#define SYSCTL_DC8_ADC0AIN1     0x00000002  // ADC0 1 Pin Present.
-#define SYSCTL_DC8_ADC0AIN0     0x00000001  // ADC0 0 Pin Present.
-
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_PIOSCCAL
 // register.
 //
 //*****************************************************************************
-#define SYSCTL_PIOSCCAL_UTEN    0x80000000  // Use User Trim Value.
-#define SYSCTL_PIOSCCAL_CAL     0x00000200  // Start Calibration.
-#define SYSCTL_PIOSCCAL_UPDATE  0x00000100  // Update Trim.
-#define SYSCTL_PIOSCCAL_UT_M    0x0000007F  // User Trim Value.
+#define SYSCTL_PIOSCCAL_UTEN    0x80000000  // Use User Trim Value
+#define SYSCTL_PIOSCCAL_CAL     0x00000200  // Start Calibration
+#define SYSCTL_PIOSCCAL_UPDATE  0x00000100  // Update Trim
+#define SYSCTL_PIOSCCAL_UT_M    0x0000007F  // User Trim Value
 #define SYSCTL_PIOSCCAL_UT_S    0
 
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_CLKVCLR register.
+//
+//*****************************************************************************
+#define SYSCTL_CLKVCLR_VERCLR   0x00000001  // Clock Verification Clear
+
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_PIOSCSTAT
 // register.
 //
 //*****************************************************************************
-#define SYSCTL_PIOSCSTAT_DT_M   0x007F0000  // Default Trim Value.
-#define SYSCTL_PIOSCSTAT_CR_M   0x00000300  // Calibration Result.
+#define SYSCTL_PIOSCSTAT_DT_M   0x007F0000  // Default Trim Value
+#define SYSCTL_PIOSCSTAT_CR_M   0x00000300  // Calibration Result
 #define SYSCTL_PIOSCSTAT_CRNONE 0x00000000  // Calibration has not been
-                                            // attempted.
+                                            // attempted
 #define SYSCTL_PIOSCSTAT_CRPASS 0x00000100  // The last calibration operation
-                                            // completed to meet 1% accuracy.
+                                            // completed to meet 1% accuracy
 #define SYSCTL_PIOSCSTAT_CRFAIL 0x00000200  // The last calibration operation
-                                            // failed to meet 1% accuracy.
-#define SYSCTL_PIOSCSTAT_CT_M   0x0000007F  // Calibration Trim Value.
+                                            // failed to meet 1% accuracy
+#define SYSCTL_PIOSCSTAT_CT_M   0x0000007F  // Calibration Trim Value
 #define SYSCTL_PIOSCSTAT_DT_S   16
 #define SYSCTL_PIOSCSTAT_CT_S   0
 
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_LDOARST register.
+//
+//*****************************************************************************
+#define SYSCTL_LDOARST_LDOARST  0x00000001  // LDO Reset
+
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_I2SMCLKCFG
 // register.
 //
 //*****************************************************************************
-#define SYSCTL_I2SMCLKCFG_RXEN  0x80000000  // RX Clock Enable.
-#define SYSCTL_I2SMCLKCFG_RXI_M 0x0FF00000  // RX Clock Integer Input.
-#define SYSCTL_I2SMCLKCFG_RXF_M 0x000F0000  // RX Clock Fractional Input.
-#define SYSCTL_I2SMCLKCFG_TXEN  0x00008000  // TX Clock Enable.
-#define SYSCTL_I2SMCLKCFG_TXI_M 0x00000FF0  // TX Clock Integer Input.
-#define SYSCTL_I2SMCLKCFG_TXF_M 0x0000000F  // TX Clock Fractional Input.
+#define SYSCTL_I2SMCLKCFG_RXEN  0x80000000  // RX Clock Enable
+#define SYSCTL_I2SMCLKCFG_RXI_M 0x3FF00000  // RX Clock Integer Input
+#define SYSCTL_I2SMCLKCFG_RXF_M 0x000F0000  // RX Clock Fractional Input
+#define SYSCTL_I2SMCLKCFG_TXEN  0x00008000  // TX Clock Enable
+#define SYSCTL_I2SMCLKCFG_TXI_M 0x00003FF0  // TX Clock Integer Input
+#define SYSCTL_I2SMCLKCFG_TXF_M 0x0000000F  // TX Clock Fractional Input
 #define SYSCTL_I2SMCLKCFG_RXI_S 20
 #define SYSCTL_I2SMCLKCFG_RXF_S 16
 #define SYSCTL_I2SMCLKCFG_TXI_S 4
@@ -1273,56 +1406,31 @@
 // The following are defines for the bit fields in the SYSCTL_DC9 register.
 //
 //*****************************************************************************
-#define SYSCTL_DC9_ADC1DC7      0x00800000  // ADC1 7 Dig Cmp Present.
-#define SYSCTL_DC9_ADC1DC6      0x00400000  // ADC1 6 Dig Cmp Present.
-#define SYSCTL_DC9_ADC1DC5      0x00200000  // ADC1 5 Dig Cmp Present.
-#define SYSCTL_DC9_ADC1DC4      0x00100000  // ADC1 4 Dig Cmp Present.
-#define SYSCTL_DC9_ADC1DC3      0x00080000  // ADC1 3 Dig Cmp Present.
-#define SYSCTL_DC9_ADC1DC2      0x00040000  // ADC1 2 Dig Cmp Present.
-#define SYSCTL_DC9_ADC1DC1      0x00020000  // ADC1 1 Dig Cmp Present.
-#define SYSCTL_DC9_ADC1DC0      0x00010000  // ADC1 0 Dig Cmp Present.
-#define SYSCTL_DC9_ADC0DC7      0x00000080  // ADC0 7 Dig Cmp Present.
-#define SYSCTL_DC9_ADC0DC6      0x00000040  // ADC0 6 Dig Cmp Present.
-#define SYSCTL_DC9_ADC0DC5      0x00000020  // ADC0 5 Dig Cmp Present.
-#define SYSCTL_DC9_ADC0DC4      0x00000010  // ADC0 4 Dig Cmp Present.
-#define SYSCTL_DC9_ADC0DC3      0x00000008  // ADC0 3 Dig Cmp Present.
-#define SYSCTL_DC9_ADC0DC2      0x00000004  // ADC0 2 Dig Cmp Present.
-#define SYSCTL_DC9_ADC0DC1      0x00000002  // ADC0 1 Dig Cmp Present.
-#define SYSCTL_DC9_ADC0DC0      0x00000001  // ADC0 0 Dig Cmp Present.
+#define SYSCTL_DC9_ADC1DC7      0x00800000  // ADC1 DC7 Present
+#define SYSCTL_DC9_ADC1DC6      0x00400000  // ADC1 DC6 Present
+#define SYSCTL_DC9_ADC1DC5      0x00200000  // ADC1 DC5 Present
+#define SYSCTL_DC9_ADC1DC4      0x00100000  // ADC1 DC4 Present
+#define SYSCTL_DC9_ADC1DC3      0x00080000  // ADC1 DC3 Present
+#define SYSCTL_DC9_ADC1DC2      0x00040000  // ADC1 DC2 Present
+#define SYSCTL_DC9_ADC1DC1      0x00020000  // ADC1 DC1 Present
+#define SYSCTL_DC9_ADC1DC0      0x00010000  // ADC1 DC0 Present
+#define SYSCTL_DC9_ADC0DC7      0x00000080  // ADC0 DC7 Present
+#define SYSCTL_DC9_ADC0DC6      0x00000040  // ADC0 DC6 Present
+#define SYSCTL_DC9_ADC0DC5      0x00000020  // ADC0 DC5 Present
+#define SYSCTL_DC9_ADC0DC4      0x00000010  // ADC0 DC4 Present
+#define SYSCTL_DC9_ADC0DC3      0x00000008  // ADC0 DC3 Present
+#define SYSCTL_DC9_ADC0DC2      0x00000004  // ADC0 DC2 Present
+#define SYSCTL_DC9_ADC0DC1      0x00000002  // ADC0 DC1 Present
+#define SYSCTL_DC9_ADC0DC0      0x00000001  // ADC0 DC0 Present
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_NVMSTAT register.
 //
 //*****************************************************************************
-#define SYSCTL_NVMSTAT_TPSW     0x00000010  // 1: Indicates 3rd party software
-                                            // in ROM.
-#define SYSCTL_NVMSTAT_FWB      0x00000001  // 32 Word flash write buffer
-                                            // function available.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_DSFLASHCFG
-// register.
-//
-//*****************************************************************************
-#define SYSCTL_DSFLASHCFG_SHDWN 0x00000001  // Flash Shutdown.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_GPIOHBCTL
-// register.
-//
-//*****************************************************************************
-#define SYSCTL_GPIOHBCTL_PORTJ  0x00000100  // Port J Advanced Host Bus.
-#define SYSCTL_GPIOHBCTL_PORTH  0x00000080  // Port H Advanced Host Bus.
-#define SYSCTL_GPIOHBCTL_PORTG  0x00000040  // Port G Advanced Host Bus.
-#define SYSCTL_GPIOHBCTL_PORTF  0x00000020  // Port F Advanced Host Bus.
-#define SYSCTL_GPIOHBCTL_PORTE  0x00000010  // Port E Advanced Host Bus.
-#define SYSCTL_GPIOHBCTL_PORTD  0x00000008  // Port D Advanced Host Bus.
-#define SYSCTL_GPIOHBCTL_PORTC  0x00000004  // Port C Advanced Host Bus.
-#define SYSCTL_GPIOHBCTL_PORTB  0x00000002  // Port B Advanced Host Bus.
-#define SYSCTL_GPIOHBCTL_PORTA  0x00000001  // Port A Advanced Host Bus.
+#define SYSCTL_NVMSTAT_TPSW     0x00000010  // Third Party Software Present
+#define SYSCTL_NVMSTAT_FWB      0x00000001  // 32 Word Flash Write Buffer
+                                            // Active
 
 //*****************************************************************************
 //
@@ -1333,10 +1441,11 @@
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the system control register
+// The following are deprecated defines for the System Control register
 // addresses.
 //
 //*****************************************************************************
+#define SYSCTL_GPIOHSCTL        0x400FE06C  // GPIO High-Speed Control
 #define SYSCTL_USER0            0x400FE1E0  // NV User Register 0
 #define SYSCTL_USER1            0x400FE1E4  // NV User Register 1
 
@@ -1367,7 +1476,9 @@
 #define SYSCTL_DID1_PINCNT_MASK 0x0000E000  // Pin count
 #define SYSCTL_DID1_TEMP_MASK   0x000000E0  // Temperature range mask
 #define SYSCTL_DID1_PKG_MASK    0x00000018  // Package mask
+#define SYSCTL_DID1_PKG_48QFP   0x00000008  // QFP package
 #define SYSCTL_DID1_QUAL_MASK   0x00000003  // Qualification status mask
+#define SYSCTL_DID1_PKG_28SOIC  0x00000000  // SOIC package
 #define SYSCTL_DID1_PRTNO_SHIFT 16
 
 //*****************************************************************************
@@ -1385,11 +1496,11 @@
 // register.
 //
 //*****************************************************************************
-#define SYSCTL_DC1_ADC          0x00010000  // ADC module present
+#define SYSCTL_DC1_ADC          0x00010000  // ADC Module Present
 #define SYSCTL_DC1_SYSDIV_MASK  0x0000F000  // Minimum system divider mask
 #define SYSCTL_DC1_ADCSPD_MASK  0x00000F00  // ADC speed mask
 #define SYSCTL_DC1_WDOG         0x00000008  // Watchdog present
-#define SYSCTL_DC1_WDT          0x00000008  // Watchdog Timer Present.
+#define SYSCTL_DC1_WDT          0x00000008  // Watchdog Timer Present
 
 //*****************************************************************************
 //
@@ -1407,14 +1518,14 @@
 // register.
 //
 //*****************************************************************************
-#define SYSCTL_DC3_ADC7         0x00800000  // ADC7 pin present
-#define SYSCTL_DC3_ADC6         0x00400000  // ADC6 pin present
-#define SYSCTL_DC3_ADC5         0x00200000  // ADC5 pin present
-#define SYSCTL_DC3_ADC4         0x00100000  // ADC4 pin present
-#define SYSCTL_DC3_ADC3         0x00080000  // ADC3 pin present
-#define SYSCTL_DC3_ADC2         0x00040000  // ADC2 pin present
-#define SYSCTL_DC3_ADC1         0x00020000  // ADC1 pin present
-#define SYSCTL_DC3_ADC0         0x00010000  // ADC0 pin present
+#define SYSCTL_DC3_ADC7         0x00800000  // ADC7 Pin Present
+#define SYSCTL_DC3_ADC6         0x00400000  // ADC6 Pin Present
+#define SYSCTL_DC3_ADC5         0x00200000  // ADC5 Pin Present
+#define SYSCTL_DC3_ADC4         0x00100000  // ADC4 Pin Present
+#define SYSCTL_DC3_ADC3         0x00080000  // ADC3 Pin Present
+#define SYSCTL_DC3_ADC2         0x00040000  // ADC2 Pin Present
+#define SYSCTL_DC3_ADC1         0x00020000  // ADC1 Pin Present
+#define SYSCTL_DC3_ADC0         0x00010000  // ADC0 Pin Present
 #define SYSCTL_DC3_MC_FAULT0    0x00008000  // MC0 fault pin present
 
 //*****************************************************************************
@@ -1434,6 +1545,134 @@
 //*****************************************************************************
 #define SYSCTL_LDOPCTL_MASK     0x0000003F  // Voltage adjust mask
 
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_SRCR0
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCR0_ADC        0x00010000  // ADC0 Reset Control
+#define SYSCTL_SRCR0_WDT        0x00000008  // WDT Reset Control
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_RESC
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RESC_WDOG        0x00000008  // Watchdog reset
+#define SYSCTL_RESC_WDT         0x00000008  // Watchdog Timer Reset
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_RCC
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCC_SYSDIV_MASK  0x07800000  // System clock divider
+#define SYSCTL_RCC_USE_SYSDIV   0x00400000  // Use sytem clock divider
+#define SYSCTL_RCC_USE_PWMDIV   0x00100000  // Use PWM clock divider
+#define SYSCTL_RCC_PWMDIV_MASK  0x000E0000  // PWM clock divider
+#define SYSCTL_RCC_OE           0x00001000  // PLL output enable
+#define SYSCTL_RCC_XTAL_3_68MHz 0x00000140  // Using a 3.6864 MHz crystal
+#define SYSCTL_RCC_XTAL_4MHz    0x00000180  // Using a 4 MHz crystal
+#define SYSCTL_RCC_XTAL_MASK    0x000003C0  // Crystal attached to main osc
+#define SYSCTL_RCC_OSCSRC_MASK  0x00000030  // Oscillator input select
+#define SYSCTL_RCC_SYSDIV_SHIFT 23          // Shift to the SYSDIV field
+#define SYSCTL_RCC_PWMDIV_SHIFT 17          // Shift to the PWMDIV field
+#define SYSCTL_RCC_XTAL_SHIFT   6           // Shift to the XTAL field
+#define SYSCTL_RCC_OSCSRC_SHIFT 4           // Shift to the OSCSRC field
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_PLLCFG
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PLLCFG_OD_MASK   0x0000C000  // Output divider
+#define SYSCTL_PLLCFG_F_MASK    0x00003FE0  // PLL multiplier
+#define SYSCTL_PLLCFG_R_MASK    0x0000001F  // Input predivider
+#define SYSCTL_PLLCFG_F_SHIFT   5
+#define SYSCTL_PLLCFG_R_SHIFT   0
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the
+// SYSCTL_GPIOHSCTL register.
+//
+//*****************************************************************************
+#define SYSCTL_GPIOHSCTL_PORTA  0x00000001  // Port A High-Speed
+#define SYSCTL_GPIOHSCTL_PORTB  0x00000002  // Port B High-Speed
+#define SYSCTL_GPIOHSCTL_PORTC  0x00000004  // Port C High-Speed
+#define SYSCTL_GPIOHSCTL_PORTD  0x00000008  // Port D High-Speed
+#define SYSCTL_GPIOHSCTL_PORTE  0x00000010  // Port E High-Speed
+#define SYSCTL_GPIOHSCTL_PORTF  0x00000020  // Port F High-Speed
+#define SYSCTL_GPIOHSCTL_PORTG  0x00000040  // Port G High-Speed
+#define SYSCTL_GPIOHSCTL_PORTH  0x00000080  // Port H High-Speed
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_RCC2
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCC2_USEFRACT    0x40000000  // Use fractional divider
+#define SYSCTL_RCC2_SYSDIV2_MSK 0x1F800000  // System clock divider
+#define SYSCTL_RCC2_FRACT       0x00400000  // Fractional divide
+#define SYSCTL_RCC2_OSCSRC2_MSK 0x00000070  // Oscillator input select
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_RCGC0
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGC0_ADC        0x00010000  // ADC0 Clock Gating Control
+#define SYSCTL_RCGC0_WDT        0x00000008  // WDT Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_SCGC0
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGC0_ADC        0x00010000  // ADC0 Clock Gating Control
+#define SYSCTL_SCGC0_WDT        0x00000008  // WDT Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_DCGC0
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGC0_ADC        0x00010000  // ADC0 Clock Gating Control
+#define SYSCTL_DCGC0_WDT        0x00000008  // WDT Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the
+// SYSCTL_DSLPCLKCFG register.
+//
+//*****************************************************************************
+#define SYSCTL_DSLPCLKCFG_D_MSK 0x1F800000  // Deep sleep system clock override
+#define SYSCTL_DSLPCLKCFG_O_MSK 0x00000070  // Deep sleep oscillator override
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the
+// SYSCTL_CLKVCLR register.
+//
+//*****************************************************************************
+#define SYSCTL_CLKVCLR_CLR      0x00000001  // Clear clock verification fault
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the
+// SYSCTL_LDOARST register.
+//
+//*****************************************************************************
+#define SYSCTL_LDOARST_ARST     0x00000001  // Allow LDO to reset device
+
 //*****************************************************************************
 //
 // The following are deprecated defines for the bit fields in the SYSCTL_SRCR0,
@@ -1509,117 +1748,6 @@
 #define SYSCTL_INT_BOR          0x00000002  // Brown out interrupt
 #define SYSCTL_INT_PLL_FAIL     0x00000001  // PLL failure interrupt
 
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the SYSCTL_RESC
-// register.
-//
-//*****************************************************************************
-#define SYSCTL_RESC_WDOG        0x00000008  // Watchdog reset
-#define SYSCTL_RESC_WDT         0x00000008  // Watchdog Timer Reset.
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the SYSCTL_RCC
-// register.
-//
-//*****************************************************************************
-#define SYSCTL_RCC_SYSDIV_MASK  0x07800000  // System clock divider
-#define SYSCTL_RCC_USE_SYSDIV   0x00400000  // Use sytem clock divider
-#define SYSCTL_RCC_USE_PWMDIV   0x00100000  // Use PWM clock divider
-#define SYSCTL_RCC_PWMDIV_MASK  0x000E0000  // PWM clock divider
-#define SYSCTL_RCC_OE           0x00001000  // PLL output enable
-#define SYSCTL_RCC_XTAL_3_68MHz 0x00000140  // Using a 3.6864 MHz crystal
-#define SYSCTL_RCC_XTAL_4MHz    0x00000180  // Using a 4 MHz crystal
-#define SYSCTL_RCC_XTAL_MASK    0x000003C0  // Crystal attached to main osc
-#define SYSCTL_RCC_OSCSRC_MASK  0x00000030  // Oscillator input select
-#define SYSCTL_RCC_SYSDIV_SHIFT 23          // Shift to the SYSDIV field
-#define SYSCTL_RCC_PWMDIV_SHIFT 17          // Shift to the PWMDIV field
-#define SYSCTL_RCC_XTAL_SHIFT   6           // Shift to the XTAL field
-#define SYSCTL_RCC_OSCSRC_SHIFT 4           // Shift to the OSCSRC field
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the SYSCTL_PLLCFG
-// register.
-//
-//*****************************************************************************
-#define SYSCTL_PLLCFG_OD_MASK   0x0000C000  // Output divider
-#define SYSCTL_PLLCFG_F_MASK    0x00003FE0  // PLL multiplier
-#define SYSCTL_PLLCFG_R_MASK    0x0000001F  // Input predivider
-#define SYSCTL_PLLCFG_F_SHIFT   5
-#define SYSCTL_PLLCFG_R_SHIFT   0
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the SYSCTL_RCC2
-// register.
-//
-//*****************************************************************************
-#define SYSCTL_RCC2_SYSDIV2_MSK 0x1F800000  // System clock divider
-#define SYSCTL_RCC2_OSCSRC2_MSK 0x00000070  // Oscillator input select
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the
-// SYSCTL_DSLPCLKCFG register.
-//
-//*****************************************************************************
-#define SYSCTL_DSLPCLKCFG_D_MSK 0x1F800000  // Deep sleep system clock override
-#define SYSCTL_DSLPCLKCFG_O_MSK 0x00000070  // Deep sleep oscillator override
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the
-// SYSCTL_CLKVCLR register.
-//
-//*****************************************************************************
-#define SYSCTL_CLKVCLR_CLR      0x00000001  // Clear clock verification fault
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the
-// SYSCTL_LDOARST register.
-//
-//*****************************************************************************
-#define SYSCTL_LDOARST_ARST     0x00000001  // Allow LDO to reset device
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the SYSCTL_SRCR0
-// register.
-//
-//*****************************************************************************
-#define SYSCTL_SRCR0_ADC        0x00010000  // ADC0 Reset Control.
-#define SYSCTL_SRCR0_WDT        0x00000008  // WDT Reset Control.
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the SYSCTL_RCGC0
-// register.
-//
-//*****************************************************************************
-#define SYSCTL_RCGC0_ADC        0x00010000  // ADC0 Clock Gating Control.
-#define SYSCTL_RCGC0_WDT        0x00000008  // WDT Clock Gating Control.
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the SYSCTL_SCGC0
-// register.
-//
-//*****************************************************************************
-#define SYSCTL_SCGC0_ADC        0x00010000  // ADC0 Clock Gating Control.
-#define SYSCTL_SCGC0_WDT        0x00000008  // WDT Clock Gating Control.
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the SYSCTL_DCGC0
-// register.
-//
-//*****************************************************************************
-#define SYSCTL_DCGC0_ADC        0x00010000  // ADC0 Clock Gating Control.
-#define SYSCTL_DCGC0_WDT        0x00000008  // WDT Clock Gating Control.
-
 #endif
 
 #endif // __HW_SYSCTL_H__
diff --git a/src/platform/lm3s/hw_timer.h b/src/platform/lm3s/inc/hw_timer.h
similarity index 56%
rename from src/platform/lm3s/hw_timer.h
rename to src/platform/lm3s/inc/hw_timer.h
index 3bbb5230..b656a7d5 100755
--- a/src/platform/lm3s/hw_timer.h
+++ b/src/platform/lm3s/inc/hw_timer.h
@@ -2,26 +2,23 @@
 //
 // hw_timer.h - Defines and macros used when accessing the timer.
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2011 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4781 of the Stellaris Firmware Development Package.
+// This is part of revision 7611 of the Stellaris Firmware Development Package.
 //
 //*****************************************************************************
 
@@ -30,206 +27,149 @@
 
 //*****************************************************************************
 //
-// The following are defines for the timer register offsets.
+// The following are defines for the Timer register offsets.
 //
 //*****************************************************************************
-#define TIMER_O_CFG             0x00000000  // Configuration register
-#define TIMER_O_TAMR            0x00000004  // TimerA mode register
-#define TIMER_O_TBMR            0x00000008  // TimerB mode register
-#define TIMER_O_CTL             0x0000000C  // Control register
-#define TIMER_O_IMR             0x00000018  // Interrupt mask register
-#define TIMER_O_RIS             0x0000001C  // Interrupt status register
-#define TIMER_O_MIS             0x00000020  // Masked interrupt status reg.
-#define TIMER_O_ICR             0x00000024  // Interrupt clear register
-#define TIMER_O_TAILR           0x00000028  // TimerA interval load register
-#define TIMER_O_TBILR           0x0000002C  // TimerB interval load register
-#define TIMER_O_TAMATCHR        0x00000030  // TimerA match register
-#define TIMER_O_TBMATCHR        0x00000034  // TimerB match register
-#define TIMER_O_TAPR            0x00000038  // TimerA prescale register
-#define TIMER_O_TBPR            0x0000003C  // TimerB prescale register
-#define TIMER_O_TAPMR           0x00000040  // TimerA prescale match register
-#define TIMER_O_TBPMR           0x00000044  // TimerB prescale match register
-#define TIMER_O_TAR             0x00000048  // TimerA register
-#define TIMER_O_TBR             0x0000004C  // TimerB register
+#define TIMER_O_CFG             0x00000000  // GPTM Configuration
+#define TIMER_O_TAMR            0x00000004  // GPTM Timer A Mode
+#define TIMER_O_TBMR            0x00000008  // GPTM Timer B Mode
+#define TIMER_O_CTL             0x0000000C  // GPTM Control
+#define TIMER_O_IMR             0x00000018  // GPTM Interrupt Mask
+#define TIMER_O_RIS             0x0000001C  // GPTM Raw Interrupt Status
+#define TIMER_O_MIS             0x00000020  // GPTM Masked Interrupt Status
+#define TIMER_O_ICR             0x00000024  // GPTM Interrupt Clear
+#define TIMER_O_TAILR           0x00000028  // GPTM Timer A Interval Load
+#define TIMER_O_TBILR           0x0000002C  // GPTM Timer B Interval Load
+#define TIMER_O_TAMATCHR        0x00000030  // GPTM Timer A Match
+#define TIMER_O_TBMATCHR        0x00000034  // GPTM Timer B Match
+#define TIMER_O_TAPR            0x00000038  // GPTM Timer A Prescale
+#define TIMER_O_TBPR            0x0000003C  // GPTM Timer B Prescale
+#define TIMER_O_TAPMR           0x00000040  // GPTM TimerA Prescale Match
+#define TIMER_O_TBPMR           0x00000044  // GPTM TimerB Prescale Match
+#define TIMER_O_TAR             0x00000048  // GPTM Timer A
+#define TIMER_O_TBR             0x0000004C  // GPTM Timer B
 #define TIMER_O_TAV             0x00000050  // GPTM Timer A Value
 #define TIMER_O_TBV             0x00000054  // GPTM Timer B Value
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the TIMER_CFG register.
+// The following are defines for the bit fields in the TIMER_O_CFG register.
 //
 //*****************************************************************************
-#define TIMER_CFG_M             0x00000007  // GPTM Configuration.
-#define TIMER_CFG_16_BIT        0x00000004  // Two 16 bit timers
-#define TIMER_CFG_32_BIT_RTC    0x00000001  // 32 bit RTC
-#define TIMER_CFG_32_BIT_TIMER  0x00000000  // 32 bit timer
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_CTL register.
-//
-//*****************************************************************************
-#define TIMER_CTL_TBPWML        0x00004000  // TimerB PWM output level invert
-#define TIMER_CTL_TBOTE         0x00002000  // TimerB output trigger enable
-#define TIMER_CTL_TBEVENT_POS   0x00000000  // TimerB event mode - pos edge
-#define TIMER_CTL_TBEVENT_NEG   0x00000400  // TimerB event mode - neg edge
-#define TIMER_CTL_TBEVENT_BOTH  0x00000C00  // TimerB event mode - both edges
-#define TIMER_CTL_TBEVENT_M     0x00000C00  // GPTM TimerB Event Mode.
-#define TIMER_CTL_TBSTALL       0x00000200  // TimerB stall enable
-#define TIMER_CTL_TBEN          0x00000100  // TimerB enable
-#define TIMER_CTL_TAPWML        0x00000040  // TimerA PWM output level invert
-#define TIMER_CTL_TAOTE         0x00000020  // TimerA output trigger enable
-#define TIMER_CTL_RTCEN         0x00000010  // RTC counter enable
-#define TIMER_CTL_TAEVENT_M     0x0000000C  // GPTM TimerA Event Mode.
-#define TIMER_CTL_TAEVENT_POS   0x00000000  // TimerA event mode - pos edge
-#define TIMER_CTL_TAEVENT_NEG   0x00000004  // TimerA event mode - neg edge
-#define TIMER_CTL_TAEVENT_BOTH  0x0000000C  // TimerA event mode - both edges
-#define TIMER_CTL_TASTALL       0x00000002  // TimerA stall enable
-#define TIMER_CTL_TAEN          0x00000001  // TimerA enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_IMR register.
-//
-//*****************************************************************************
-#define TIMER_IMR_TBMIM         0x00000800  // GPTM Timer B Mode Match
-                                            // Interrupt Mask.
-#define TIMER_IMR_CBEIM         0x00000400  // CaptureB event interrupt mask
-#define TIMER_IMR_CBMIM         0x00000200  // CaptureB match interrupt mask
-#define TIMER_IMR_TBTOIM        0x00000100  // TimerB time out interrupt mask
-#define TIMER_IMR_TAMIM         0x00000010  // GPTM Timer A Mode Match
-                                            // Interrupt Mask.
-#define TIMER_IMR_RTCIM         0x00000008  // RTC interrupt mask
-#define TIMER_IMR_CAEIM         0x00000004  // CaptureA event interrupt mask
-#define TIMER_IMR_CAMIM         0x00000002  // CaptureA match interrupt mask
-#define TIMER_IMR_TATOIM        0x00000001  // TimerA time out interrupt mask
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_RIS register.
-//
-//*****************************************************************************
-#define TIMER_RIS_TBMRIS        0x00000800  // GPTM Timer B Mode Match Raw
-                                            // Interrupt.
-#define TIMER_RIS_CBERIS        0x00000400  // CaptureB event raw int status
-#define TIMER_RIS_CBMRIS        0x00000200  // CaptureB match raw int status
-#define TIMER_RIS_TBTORIS       0x00000100  // TimerB time out raw int status
-#define TIMER_RIS_TAMRIS        0x00000010  // GPTM Timer A Mode Match Raw
-                                            // Interrupt.
-#define TIMER_RIS_RTCRIS        0x00000008  // RTC raw int status
-#define TIMER_RIS_CAERIS        0x00000004  // CaptureA event raw int status
-#define TIMER_RIS_CAMRIS        0x00000002  // CaptureA match raw int status
-#define TIMER_RIS_TATORIS       0x00000001  // TimerA time out raw int status
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_ICR register.
-//
-//*****************************************************************************
-#define TIMER_ICR_TBMCINT       0x00000800  // GPTM Timer B Mode Match
-                                            // Interrupt Clear.
-#define TIMER_ICR_CBECINT       0x00000400  // CaptureB event interrupt clear
-#define TIMER_ICR_CBMCINT       0x00000200  // CaptureB match interrupt clear
-#define TIMER_ICR_TBTOCINT      0x00000100  // TimerB time out interrupt clear
-#define TIMER_ICR_TAMCINT       0x00000010  // GPTM Timer A Mode Match
-                                            // Interrupt Clear.
-#define TIMER_ICR_RTCCINT       0x00000008  // RTC interrupt clear
-#define TIMER_ICR_CAECINT       0x00000004  // CaptureA event interrupt clear
-#define TIMER_ICR_CAMCINT       0x00000002  // CaptureA match interrupt clear
-#define TIMER_ICR_TATOCINT      0x00000001  // TimerA time out interrupt clear
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_TAILR register.
-//
-//*****************************************************************************
-#define TIMER_TAILR_TAILRH_M    0xFFFF0000  // GPTM TimerA Interval Load
-                                            // Register High.
-#define TIMER_TAILR_TAILRL_M    0x0000FFFF  // GPTM TimerA Interval Load
-                                            // Register Low.
-#define TIMER_TAILR_TAILRH_S    16
-#define TIMER_TAILR_TAILRL_S    0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_TBILR register.
-//
-//*****************************************************************************
-#define TIMER_TBILR_TBILRL_M    0x0000FFFF  // GPTM TimerB Interval Load
-                                            // Register.
-#define TIMER_TBILR_TBILRL_S    0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_TAMATCHR register.
-//
-//*****************************************************************************
-#define TIMER_TAMATCHR_TAMRH_M  0xFFFF0000  // GPTM TimerA Match Register High.
-#define TIMER_TAMATCHR_TAMRL_M  0x0000FFFF  // GPTM TimerA Match Register Low.
-#define TIMER_TAMATCHR_TAMRH_S  16
-#define TIMER_TAMATCHR_TAMRL_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_TBMATCHR register.
-//
-//*****************************************************************************
-#define TIMER_TBMATCHR_TBMRL_M  0x0000FFFF  // GPTM TimerB Match Register Low.
-#define TIMER_TBMATCHR_TBMRL_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_TAR register.
-//
-//*****************************************************************************
-#define TIMER_TAR_TARH_M        0xFFFF0000  // GPTM TimerA Register High.
-#define TIMER_TAR_TARL_M        0x0000FFFF  // GPTM TimerA Register Low.
-#define TIMER_TAR_TARH_S        16
-#define TIMER_TAR_TARL_S        0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_TBR register.
-//
-//*****************************************************************************
-#define TIMER_TBR_TBRL_M        0x0000FFFF  // GPTM TimerB.
-#define TIMER_TBR_TBRL_S        0
+#define TIMER_CFG_M             0x00000007  // GPTM Configuration
+#define TIMER_CFG_32_BIT_TIMER  0x00000000  // 32-bit timer configuration
+#define TIMER_CFG_32_BIT_RTC    0x00000001  // 32-bit real-time clock (RTC)
+                                            // counter configuration
+#define TIMER_CFG_16_BIT        0x00000004  // 16-bit timer configuration. The
+                                            // function is controlled by bits
+                                            // 1:0 of GPTMTAMR and GPTMTBMR
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the TIMER_O_TAMR register.
 //
 //*****************************************************************************
-#define TIMER_TAMR_TASNAPS      0x00000080  // GPTM Timer A Snap-Shot Mode.
-#define TIMER_TAMR_TAWOT        0x00000040  // GPTM Timer A Wait-on-Trigger.
+#define TIMER_TAMR_TASNAPS      0x00000080  // GPTM Timer A Snap-Shot Mode
+#define TIMER_TAMR_TAWOT        0x00000040  // GPTM Timer A Wait-on-Trigger
 #define TIMER_TAMR_TAMIE        0x00000020  // GPTM Timer A Match Interrupt
-                                            // Enable.
-#define TIMER_TAMR_TACDIR       0x00000010  // GPTM Timer A Count Direction.
-#define TIMER_TAMR_TAAMS        0x00000008  // GPTM TimerA Alternate Mode
-                                            // Select.
-#define TIMER_TAMR_TACMR        0x00000004  // GPTM TimerA Capture Mode.
-#define TIMER_TAMR_TAMR_M       0x00000003  // GPTM TimerA Mode.
-#define TIMER_TAMR_TAMR_1_SHOT  0x00000001  // One-Shot Timer mode.
-#define TIMER_TAMR_TAMR_PERIOD  0x00000002  // Periodic Timer mode.
-#define TIMER_TAMR_TAMR_CAP     0x00000003  // Capture mode.
+                                            // Enable
+#define TIMER_TAMR_TACDIR       0x00000010  // GPTM Timer A Count Direction
+#define TIMER_TAMR_TAAMS        0x00000008  // GPTM Timer A Alternate Mode
+                                            // Select
+#define TIMER_TAMR_TACMR        0x00000004  // GPTM Timer A Capture Mode
+#define TIMER_TAMR_TAMR_M       0x00000003  // GPTM Timer A Mode
+#define TIMER_TAMR_TAMR_1_SHOT  0x00000001  // One-Shot Timer mode
+#define TIMER_TAMR_TAMR_PERIOD  0x00000002  // Periodic Timer mode
+#define TIMER_TAMR_TAMR_CAP     0x00000003  // Capture mode
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the TIMER_O_TBMR register.
 //
 //*****************************************************************************
-#define TIMER_TBMR_TBSNAPS      0x00000080  // GPTM Timer B Snap-Shot Mode.
-#define TIMER_TBMR_TBWOT        0x00000040  // GPTM Timer B Wait-on-Trigger.
+#define TIMER_TBMR_TBSNAPS      0x00000080  // GPTM Timer B Snap-Shot Mode
+#define TIMER_TBMR_TBWOT        0x00000040  // GPTM Timer B Wait-on-Trigger
 #define TIMER_TBMR_TBMIE        0x00000020  // GPTM Timer B Match Interrupt
-                                            // Enable.
-#define TIMER_TBMR_TBCDIR       0x00000010  // GPTM Timer B Count Direction.
-#define TIMER_TBMR_TBAMS        0x00000008  // GPTM TimerB Alternate Mode
-                                            // Select.
-#define TIMER_TBMR_TBCMR        0x00000004  // GPTM TimerB Capture Mode.
-#define TIMER_TBMR_TBMR_M       0x00000003  // GPTM TimerB Mode.
-#define TIMER_TBMR_TBMR_1_SHOT  0x00000001  // One-Shot Timer mode.
-#define TIMER_TBMR_TBMR_PERIOD  0x00000002  // Periodic Timer mode.
-#define TIMER_TBMR_TBMR_CAP     0x00000003  // Capture mode.
+                                            // Enable
+#define TIMER_TBMR_TBCDIR       0x00000010  // GPTM Timer B Count Direction
+#define TIMER_TBMR_TBAMS        0x00000008  // GPTM Timer B Alternate Mode
+                                            // Select
+#define TIMER_TBMR_TBCMR        0x00000004  // GPTM Timer B Capture Mode
+#define TIMER_TBMR_TBMR_M       0x00000003  // GPTM Timer B Mode
+#define TIMER_TBMR_TBMR_1_SHOT  0x00000001  // One-Shot Timer mode
+#define TIMER_TBMR_TBMR_PERIOD  0x00000002  // Periodic Timer mode
+#define TIMER_TBMR_TBMR_CAP     0x00000003  // Capture mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_CTL register.
+//
+//*****************************************************************************
+#define TIMER_CTL_TBPWML        0x00004000  // GPTM Timer B PWM Output Level
+#define TIMER_CTL_TBOTE         0x00002000  // GPTM Timer B Output Trigger
+                                            // Enable
+#define TIMER_CTL_TBEVENT_M     0x00000C00  // GPTM Timer B Event Mode
+#define TIMER_CTL_TBEVENT_POS   0x00000000  // Positive edge
+#define TIMER_CTL_TBEVENT_NEG   0x00000400  // Negative edge
+#define TIMER_CTL_TBEVENT_BOTH  0x00000C00  // Both edges
+#define TIMER_CTL_TBSTALL       0x00000200  // GPTM Timer B Stall Enable
+#define TIMER_CTL_TBEN          0x00000100  // GPTM Timer B Enable
+#define TIMER_CTL_TAPWML        0x00000040  // GPTM Timer A PWM Output Level
+#define TIMER_CTL_TAOTE         0x00000020  // GPTM Timer A Output Trigger
+                                            // Enable
+#define TIMER_CTL_RTCEN         0x00000010  // GPTM RTC Enable
+#define TIMER_CTL_TAEVENT_M     0x0000000C  // GPTM Timer A Event Mode
+#define TIMER_CTL_TAEVENT_POS   0x00000000  // Positive edge
+#define TIMER_CTL_TAEVENT_NEG   0x00000004  // Negative edge
+#define TIMER_CTL_TAEVENT_BOTH  0x0000000C  // Both edges
+#define TIMER_CTL_TASTALL       0x00000002  // GPTM Timer A Stall Enable
+#define TIMER_CTL_TAEN          0x00000001  // GPTM Timer A Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_IMR register.
+//
+//*****************************************************************************
+#define TIMER_IMR_TBMIM         0x00000800  // GPTM Timer B Mode Match
+                                            // Interrupt Mask
+#define TIMER_IMR_CBEIM         0x00000400  // GPTM Capture B Event Interrupt
+                                            // Mask
+#define TIMER_IMR_CBMIM         0x00000200  // GPTM Capture B Match Interrupt
+                                            // Mask
+#define TIMER_IMR_TBTOIM        0x00000100  // GPTM Timer B Time-Out Interrupt
+                                            // Mask
+#define TIMER_IMR_TAMIM         0x00000010  // GPTM Timer A Mode Match
+                                            // Interrupt Mask
+#define TIMER_IMR_RTCIM         0x00000008  // GPTM RTC Interrupt Mask
+#define TIMER_IMR_CAEIM         0x00000004  // GPTM Capture A Event Interrupt
+                                            // Mask
+#define TIMER_IMR_CAMIM         0x00000002  // GPTM Capture A Match Interrupt
+                                            // Mask
+#define TIMER_IMR_TATOIM        0x00000001  // GPTM Timer A Time-Out Interrupt
+                                            // Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_RIS register.
+//
+//*****************************************************************************
+#define TIMER_RIS_TBMRIS        0x00000800  // GPTM Timer B Mode Match Raw
+                                            // Interrupt
+#define TIMER_RIS_CBERIS        0x00000400  // GPTM Capture B Event Raw
+                                            // Interrupt
+#define TIMER_RIS_CBMRIS        0x00000200  // GPTM Capture B Match Raw
+                                            // Interrupt
+#define TIMER_RIS_TBTORIS       0x00000100  // GPTM Timer B Time-Out Raw
+                                            // Interrupt
+#define TIMER_RIS_TAMRIS        0x00000010  // GPTM Timer A Mode Match Raw
+                                            // Interrupt
+#define TIMER_RIS_RTCRIS        0x00000008  // GPTM RTC Raw Interrupt
+#define TIMER_RIS_CAERIS        0x00000004  // GPTM Capture A Event Raw
+                                            // Interrupt
+#define TIMER_RIS_CAMRIS        0x00000002  // GPTM Capture A Match Raw
+                                            // Interrupt
+#define TIMER_RIS_TATORIS       0x00000001  // GPTM Timer A Time-Out Raw
+                                            // Interrupt
 
 //*****************************************************************************
 //
@@ -237,29 +177,93 @@
 //
 //*****************************************************************************
 #define TIMER_MIS_TBMMIS        0x00000800  // GPTM Timer B Mode Match Masked
-                                            // Interrupt.
-#define TIMER_MIS_CBEMIS        0x00000400  // GPTM CaptureB Event Masked
-                                            // Interrupt.
-#define TIMER_MIS_CBMMIS        0x00000200  // GPTM CaptureB Match Masked
-                                            // Interrupt.
-#define TIMER_MIS_TBTOMIS       0x00000100  // GPTM TimerB Time-Out Masked
-                                            // Interrupt.
+                                            // Interrupt
+#define TIMER_MIS_CBEMIS        0x00000400  // GPTM Capture B Event Masked
+                                            // Interrupt
+#define TIMER_MIS_CBMMIS        0x00000200  // GPTM Capture B Match Masked
+                                            // Interrupt
+#define TIMER_MIS_TBTOMIS       0x00000100  // GPTM Timer B Time-Out Masked
+                                            // Interrupt
 #define TIMER_MIS_TAMMIS        0x00000010  // GPTM Timer A Mode Match Masked
-                                            // Interrupt.
-#define TIMER_MIS_RTCMIS        0x00000008  // GPTM RTC Masked Interrupt.
-#define TIMER_MIS_CAEMIS        0x00000004  // GPTM CaptureA Event Masked
-                                            // Interrupt.
-#define TIMER_MIS_CAMMIS        0x00000002  // GPTM CaptureA Match Masked
-                                            // Interrupt.
-#define TIMER_MIS_TATOMIS       0x00000001  // GPTM TimerA Time-Out Masked
-                                            // Interrupt.
+                                            // Interrupt
+#define TIMER_MIS_RTCMIS        0x00000008  // GPTM RTC Masked Interrupt
+#define TIMER_MIS_CAEMIS        0x00000004  // GPTM Capture A Event Masked
+                                            // Interrupt
+#define TIMER_MIS_CAMMIS        0x00000002  // GPTM Capture A Match Masked
+                                            // Interrupt
+#define TIMER_MIS_TATOMIS       0x00000001  // GPTM Timer A Time-Out Masked
+                                            // Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_ICR register.
+//
+//*****************************************************************************
+#define TIMER_ICR_TBMCINT       0x00000800  // GPTM Timer B Mode Match
+                                            // Interrupt Clear
+#define TIMER_ICR_CBECINT       0x00000400  // GPTM Capture B Event Interrupt
+                                            // Clear
+#define TIMER_ICR_CBMCINT       0x00000200  // GPTM Capture B Match Interrupt
+                                            // Clear
+#define TIMER_ICR_TBTOCINT      0x00000100  // GPTM Timer B Time-Out Interrupt
+                                            // Clear
+#define TIMER_ICR_TAMCINT       0x00000010  // GPTM Timer A Mode Match
+                                            // Interrupt Clear
+#define TIMER_ICR_RTCCINT       0x00000008  // GPTM RTC Interrupt Clear
+#define TIMER_ICR_CAECINT       0x00000004  // GPTM Capture A Event Interrupt
+                                            // Clear
+#define TIMER_ICR_CAMCINT       0x00000002  // GPTM Capture A Match Interrupt
+                                            // Clear
+#define TIMER_ICR_TATOCINT      0x00000001  // GPTM Timer A Time-Out Raw
+                                            // Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAILR register.
+//
+//*****************************************************************************
+#define TIMER_TAILR_TAILRH_M    0xFFFF0000  // GPTM Timer A Interval Load
+                                            // Register High
+#define TIMER_TAILR_TAILRL_M    0x0000FFFF  // GPTM Timer A Interval Load
+                                            // Register Low
+#define TIMER_TAILR_TAILRH_S    16
+#define TIMER_TAILR_TAILRL_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBILR register.
+//
+//*****************************************************************************
+#define TIMER_TBILR_TBILRL_M    0x0000FFFF  // GPTM Timer B Interval Load
+                                            // Register
+#define TIMER_TBILR_TBILRL_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAMATCHR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TAMATCHR_TAMRH_M  0xFFFF0000  // GPTM Timer A Match Register High
+#define TIMER_TAMATCHR_TAMRL_M  0x0000FFFF  // GPTM Timer A Match Register Low
+#define TIMER_TAMATCHR_TAMRH_S  16
+#define TIMER_TAMATCHR_TAMRL_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBMATCHR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TBMATCHR_TBMRL_M  0x0000FFFF  // GPTM Timer B Match Register Low
+#define TIMER_TBMATCHR_TBMRL_S  0
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the TIMER_O_TAPR register.
 //
 //*****************************************************************************
-#define TIMER_TAPR_TAPSR_M      0x000000FF  // GPTM TimerA Prescale.
+#define TIMER_TAPR_TAPSR_M      0x000000FF  // GPTM Timer A Prescale
 #define TIMER_TAPR_TAPSR_S      0
 
 //*****************************************************************************
@@ -267,7 +271,7 @@
 // The following are defines for the bit fields in the TIMER_O_TBPR register.
 //
 //*****************************************************************************
-#define TIMER_TBPR_TBPSR_M      0x000000FF  // GPTM TimerB Prescale.
+#define TIMER_TBPR_TBPSR_M      0x000000FF  // GPTM Timer B Prescale
 #define TIMER_TBPR_TBPSR_S      0
 
 //*****************************************************************************
@@ -275,7 +279,7 @@
 // The following are defines for the bit fields in the TIMER_O_TAPMR register.
 //
 //*****************************************************************************
-#define TIMER_TAPMR_TAPSMR_M    0x000000FF  // GPTM TimerA Prescale Match.
+#define TIMER_TAPMR_TAPSMR_M    0x000000FF  // GPTM TimerA Prescale Match
 #define TIMER_TAPMR_TAPSMR_S    0
 
 //*****************************************************************************
@@ -283,16 +287,34 @@
 // The following are defines for the bit fields in the TIMER_O_TBPMR register.
 //
 //*****************************************************************************
-#define TIMER_TBPMR_TBPSMR_M    0x000000FF  // GPTM TimerB Prescale Match.
+#define TIMER_TBPMR_TBPSMR_M    0x000000FF  // GPTM TimerB Prescale Match
 #define TIMER_TBPMR_TBPSMR_S    0
 
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAR register.
+//
+//*****************************************************************************
+#define TIMER_TAR_TARH_M        0xFFFF0000  // GPTM Timer A Register High
+#define TIMER_TAR_TARL_M        0x0000FFFF  // GPTM Timer A Register Low
+#define TIMER_TAR_TARH_S        16
+#define TIMER_TAR_TARL_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBR register.
+//
+//*****************************************************************************
+#define TIMER_TBR_TBRL_M        0x00FFFFFF  // GPTM Timer B
+#define TIMER_TBR_TBRL_S        0
+
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the TIMER_O_TAV register.
 //
 //*****************************************************************************
-#define TIMER_TAV_TAVH_M        0xFFFF0000  // GPTM Timer A Value High.
-#define TIMER_TAV_TAVL_M        0x0000FFFF  // GPTM Timer A Register Low.
+#define TIMER_TAV_TAVH_M        0xFFFF0000  // GPTM Timer A Value High
+#define TIMER_TAV_TAVL_M        0x0000FFFF  // GPTM Timer A Register Low
 #define TIMER_TAV_TAVH_S        16
 #define TIMER_TAV_TAVL_S        0
 
@@ -301,7 +323,7 @@
 // The following are defines for the bit fields in the TIMER_O_TBV register.
 //
 //*****************************************************************************
-#define TIMER_TBV_TBVL_M        0x0000FFFF  // GPTM Timer B Register.
+#define TIMER_TBV_TBVL_M        0x0000FFFF  // GPTM Timer B Register
 #define TIMER_TBV_TBVL_S        0
 
 //*****************************************************************************
@@ -311,6 +333,88 @@
 //*****************************************************************************
 #ifndef DEPRECATED
 
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the TIMER_O_CFG
+// register.
+//
+//*****************************************************************************
+#define TIMER_CFG_CFG_MSK       0x00000007  // Configuration options mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the TIMER_O_CTL
+// register.
+//
+//*****************************************************************************
+#define TIMER_CTL_TBEVENT_MSK   0x00000C00  // TimerB event mode mask
+#define TIMER_CTL_TAEVENT_MSK   0x0000000C  // TimerA event mode mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the TIMER_O_RIS
+// register.
+//
+//*****************************************************************************
+#define TIMER_RIS_CBEMIS        0x00000400  // CaptureB event masked int status
+#define TIMER_RIS_CBMMIS        0x00000200  // CaptureB match masked int status
+#define TIMER_RIS_TBTOMIS       0x00000100  // TimerB time out masked int stat
+#define TIMER_RIS_RTCMIS        0x00000008  // RTC masked int status
+#define TIMER_RIS_CAEMIS        0x00000004  // CaptureA event masked int status
+#define TIMER_RIS_CAMMIS        0x00000002  // CaptureA match masked int status
+#define TIMER_RIS_TATOMIS       0x00000001  // TimerA time out masked int stat
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the TIMER_O_TAILR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TAILR_TAILRH      0xFFFF0000  // TimerB load val in 32 bit mode
+#define TIMER_TAILR_TAILRL      0x0000FFFF  // TimerA interval load value
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the TIMER_O_TBILR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TBILR_TBILRL      0x0000FFFF  // TimerB interval load value
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the
+// TIMER_O_TAMATCHR register.
+//
+//*****************************************************************************
+#define TIMER_TAMATCHR_TAMRH    0xFFFF0000  // TimerB match val in 32 bit mode
+#define TIMER_TAMATCHR_TAMRL    0x0000FFFF  // TimerA match value
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the
+// TIMER_O_TBMATCHR register.
+//
+//*****************************************************************************
+#define TIMER_TBMATCHR_TBMRL    0x0000FFFF  // TimerB match load value
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the TIMER_O_TAR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TAR_TARH          0xFFFF0000  // TimerB val in 32 bit mode
+#define TIMER_TAR_TARL          0x0000FFFF  // TimerA value
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the TIMER_O_TBR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TBR_TBRL          0x0000FFFF  // TimerB value
+
 //*****************************************************************************
 //
 // The following are deprecated defines for the reset values of the timer
@@ -336,14 +440,6 @@
 #define TIMER_RV_IMR            0x00000000  // Interrupt mask register RV
 #define TIMER_RV_TAMR           0x00000000  // TimerA mode register RV
 
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the TIMER_CFG
-// register.
-//
-//*****************************************************************************
-#define TIMER_CFG_CFG_MSK       0x00000007  // Configuration options mask
-
 //*****************************************************************************
 //
 // The following are deprecated defines for the bit fields in the TIMER_TnMR
@@ -357,63 +453,6 @@
 #define TIMER_TNMR_TNTMR_PERIOD 0x00000002  // Mode - periodic
 #define TIMER_TNMR_TNTMR_CAP    0x00000003  // Mode - capture
 
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the TIMER_CTL
-// register.
-//
-//*****************************************************************************
-#define TIMER_CTL_TBEVENT_MSK   0x00000C00  // TimerB event mode mask
-#define TIMER_CTL_TAEVENT_MSK   0x0000000C  // TimerA event mode mask
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the TIMER_MIS
-// register.
-//
-//*****************************************************************************
-#define TIMER_RIS_CBEMIS        0x00000400  // CaptureB event masked int status
-#define TIMER_RIS_CBMMIS        0x00000200  // CaptureB match masked int status
-#define TIMER_RIS_TBTOMIS       0x00000100  // TimerB time out masked int stat
-#define TIMER_RIS_RTCMIS        0x00000008  // RTC masked int status
-#define TIMER_RIS_CAEMIS        0x00000004  // CaptureA event masked int status
-#define TIMER_RIS_CAMMIS        0x00000002  // CaptureA match masked int status
-#define TIMER_RIS_TATOMIS       0x00000001  // TimerA time out masked int stat
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the TIMER_TAILR
-// register.
-//
-//*****************************************************************************
-#define TIMER_TAILR_TAILRH      0xFFFF0000  // TimerB load val in 32 bit mode
-#define TIMER_TAILR_TAILRL      0x0000FFFF  // TimerA interval load value
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the TIMER_TBILR
-// register.
-//
-//*****************************************************************************
-#define TIMER_TBILR_TBILRL      0x0000FFFF  // TimerB interval load value
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the
-// TIMER_TAMATCHR register.
-//
-//*****************************************************************************
-#define TIMER_TAMATCHR_TAMRH    0xFFFF0000  // TimerB match val in 32 bit mode
-#define TIMER_TAMATCHR_TAMRL    0x0000FFFF  // TimerA match value
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the
-// TIMER_TBMATCHR register.
-//
-//*****************************************************************************
-#define TIMER_TBMATCHR_TBMRL    0x0000FFFF  // TimerB match load value
-
 //*****************************************************************************
 //
 // The following are deprecated defines for the bit fields in the TIMER_TnPR
@@ -430,23 +469,6 @@
 //*****************************************************************************
 #define TIMER_TNPMR_TNPSMR      0x000000FF  // TimerN prescale match value
 
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the TIMER_TAR
-// register.
-//
-//*****************************************************************************
-#define TIMER_TAR_TARH          0xFFFF0000  // TimerB val in 32 bit mode
-#define TIMER_TAR_TARL          0x0000FFFF  // TimerA value
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the TIMER_TBR
-// register.
-//
-//*****************************************************************************
-#define TIMER_TBR_TBRL          0x0000FFFF  // TimerB value
-
 #endif
 
 #endif // __HW_TIMER_H__
diff --git a/src/platform/lm3s/hw_types.h b/src/platform/lm3s/inc/hw_types.h
similarity index 80%
rename from src/platform/lm3s/hw_types.h
rename to src/platform/lm3s/inc/hw_types.h
index ddea77e9..5e0be000 100755
--- a/src/platform/lm3s/hw_types.h
+++ b/src/platform/lm3s/inc/hw_types.h
@@ -2,26 +2,23 @@
 //
 // hw_types.h - Common types and macros.
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2011 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4781 of the Stellaris Firmware Development Package.
+// This is part of revision 7611 of the Stellaris Firmware Development Package.
 //
 //*****************************************************************************
 
@@ -118,6 +115,12 @@ typedef unsigned char tBoolean;
          (SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_TEMPEST))
 #endif
 
+#ifndef CLASS_IS_FIRESTORM
+#define CLASS_IS_FIRESTORM                                                   \
+        ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
+         (SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_FIRESTORM))
+#endif
+
 #ifndef REVISION_IS_A0
 #define REVISION_IS_A0                                                     \
         ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
@@ -148,6 +151,12 @@ typedef unsigned char tBoolean;
          (SYSCTL_DID0_MAJ_REVB | SYSCTL_DID0_MIN_1))
 #endif
 
+#ifndef REVISION_IS_C0
+#define REVISION_IS_C0                                                     \
+        ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
+         (SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_0))
+#endif
+
 #ifndef REVISION_IS_C1
 #define REVISION_IS_C1                                                     \
         ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
@@ -160,6 +169,12 @@ typedef unsigned char tBoolean;
          (SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_2))
 #endif
 
+#ifndef REVISION_IS_C3
+#define REVISION_IS_C3                                                     \
+        ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
+         (SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_3))
+#endif
+
 //*****************************************************************************
 //
 // Deprecated silicon class and revision detection macros.
diff --git a/src/platform/lm3s/hw_uart.h b/src/platform/lm3s/inc/hw_uart.h
similarity index 56%
rename from src/platform/lm3s/hw_uart.h
rename to src/platform/lm3s/inc/hw_uart.h
index 84691b71..bebf8328 100755
--- a/src/platform/lm3s/hw_uart.h
+++ b/src/platform/lm3s/inc/hw_uart.h
@@ -1,27 +1,24 @@
 //*****************************************************************************
 //
-// hw_uart.h - Macros and defines used when accessing the UART hardware
+// hw_uart.h - Macros and defines used when accessing the UART hardware.
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2011 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4781 of the Stellaris Firmware Development Package.
+// This is part of revision 7611 of the Stellaris Firmware Development Package.
 //
 //*****************************************************************************
 
@@ -30,23 +27,24 @@
 
 //*****************************************************************************
 //
-// The following are defines for the UART Register offsets.
+// The following are defines for the UART register offsets.
 //
 //*****************************************************************************
-#define UART_O_DR               0x00000000  // Data Register
-#define UART_O_RSR              0x00000004  // Receive Status Register (read)
-#define UART_O_ECR              0x00000004  // Error Clear Register (write)
-#define UART_O_FR               0x00000018  // Flag Register (read only)
+#define UART_O_DR               0x00000000  // UART Data
+#define UART_O_RSR              0x00000004  // UART Receive Status/Error Clear
+#define UART_O_ECR              0x00000004  // UART Receive Status/Error Clear
+#define UART_O_FR               0x00000018  // UART Flag
 #define UART_O_ILPR             0x00000020  // UART IrDA Low-Power Register
-#define UART_O_IBRD             0x00000024  // Integer Baud Rate Divisor Reg
-#define UART_O_FBRD             0x00000028  // Fractional Baud Rate Divisor Reg
+#define UART_O_IBRD             0x00000024  // UART Integer Baud-Rate Divisor
+#define UART_O_FBRD             0x00000028  // UART Fractional Baud-Rate
+                                            // Divisor
 #define UART_O_LCRH             0x0000002C  // UART Line Control
-#define UART_O_CTL              0x00000030  // Control Register
-#define UART_O_IFLS             0x00000034  // Interrupt FIFO Level Select Reg
-#define UART_O_IM               0x00000038  // Interrupt Mask Set/Clear Reg
-#define UART_O_RIS              0x0000003C  // Raw Interrupt Status Register
-#define UART_O_MIS              0x00000040  // Masked Interrupt Status Register
-#define UART_O_ICR              0x00000044  // Interrupt Clear Register
+#define UART_O_CTL              0x00000030  // UART Control
+#define UART_O_IFLS             0x00000034  // UART Interrupt FIFO Level Select
+#define UART_O_IM               0x00000038  // UART Interrupt Mask
+#define UART_O_RIS              0x0000003C  // UART Raw Interrupt Status
+#define UART_O_MIS              0x00000040  // UART Masked Interrupt Status
+#define UART_O_ICR              0x00000044  // UART Interrupt Clear
 #define UART_O_DMACTL           0x00000048  // UART DMA Control
 #define UART_O_LCTL             0x00000090  // UART LIN Control
 #define UART_O_LSS              0x00000094  // UART LIN Snap Shot
@@ -54,260 +52,279 @@
 
 //*****************************************************************************
 //
-// The following are defines for the Data Register bits
+// The following are defines for the bit fields in the UART_O_DR register.
 //
 //*****************************************************************************
-#define UART_DR_OE              0x00000800  // Overrun Error
-#define UART_DR_BE              0x00000400  // Break Error
-#define UART_DR_PE              0x00000200  // Parity Error
-#define UART_DR_FE              0x00000100  // Framing Error
-#define UART_DR_DATA_M          0x000000FF  // Data Transmitted or Received.
+#define UART_DR_OE              0x00000800  // UART Overrun Error
+#define UART_DR_BE              0x00000400  // UART Break Error
+#define UART_DR_PE              0x00000200  // UART Parity Error
+#define UART_DR_FE              0x00000100  // UART Framing Error
+#define UART_DR_DATA_M          0x000000FF  // Data Transmitted or Received
 #define UART_DR_DATA_S          0
 
 //*****************************************************************************
 //
-// The following are defines for the Receive Status Register bits
+// The following are defines for the bit fields in the UART_O_RSR register.
 //
 //*****************************************************************************
-#define UART_RSR_OE             0x00000008  // Overrun Error
-#define UART_RSR_BE             0x00000004  // Break Error
-#define UART_RSR_PE             0x00000002  // Parity Error
-#define UART_RSR_FE             0x00000001  // Framing Error
-
-//*****************************************************************************
-//
-// The following are defines for the Flag Register bits
-//
-//*****************************************************************************
-#define UART_FR_RI              0x00000100  // Ring Indicator.
-#define UART_FR_TXFE            0x00000080  // TX FIFO Empty
-#define UART_FR_RXFF            0x00000040  // RX FIFO Full
-#define UART_FR_TXFF            0x00000020  // TX FIFO Full
-#define UART_FR_RXFE            0x00000010  // RX FIFO Empty
-#define UART_FR_BUSY            0x00000008  // UART Busy
-#define UART_FR_DCD             0x00000004  // Data Carrier Detect.
-#define UART_FR_DSR             0x00000002  // Data Set Ready.
-#define UART_FR_CTS             0x00000001  // Clear To Send.
-
-//*****************************************************************************
-//
-// The following are defines for the Integer baud-rate divisor
-//
-//*****************************************************************************
-#define UART_IBRD_DIVINT_M      0x0000FFFF  // Integer Baud-Rate Divisor.
-#define UART_IBRD_DIVINT_S      0
-
-//*****************************************************************************
-//
-// The following are defines for the Fractional baud-rate divisor
-//
-//*****************************************************************************
-#define UART_FBRD_DIVFRAC_M     0x0000003F  // Fractional Baud-Rate Divisor.
-#define UART_FBRD_DIVFRAC_S     0
-
-//*****************************************************************************
-//
-// The following are defines for the Control Register bits
-//
-//*****************************************************************************
-#define UART_CTL_CTSEN          0x00008000  // Enable Clear To Send.
-#define UART_CTL_RTSEN          0x00004000  // Enable Request to Send.
-#define UART_CTL_RTS            0x00000800  // Request to Send.
-#define UART_CTL_DTR            0x00000400  // Data Terminal Ready.
-#define UART_CTL_RXE            0x00000200  // Receive Enable
-#define UART_CTL_TXE            0x00000100  // Transmit Enable
-#define UART_CTL_LBE            0x00000080  // Loopback Enable
-#define UART_CTL_LIN            0x00000040  // LIN Mode Enable.
-#define UART_CTL_HSE            0x00000020  // High-Speed Enable.
-#define UART_CTL_EOT            0x00000010  // End of Transmission.
-#define UART_CTL_SMART          0x00000008  // ISO 7816 Smart Card Support.
-#define UART_CTL_SIRLP          0x00000004  // SIR (IrDA) Low Power Enable
-#define UART_CTL_SIREN          0x00000002  // SIR (IrDA) Enable
-#define UART_CTL_UARTEN         0x00000001  // UART Enable
-
-//*****************************************************************************
-//
-// The following are defines for the Interrupt FIFO Level Select Register bits
-//
-//*****************************************************************************
-#define UART_IFLS_RX_M          0x00000038  // RX FIFO Level Interrupt Mask
-#define UART_IFLS_RX1_8         0x00000000  // 1/8 Full
-#define UART_IFLS_RX2_8         0x00000008  // 1/4 Full
-#define UART_IFLS_RX4_8         0x00000010  // 1/2 Full
-#define UART_IFLS_RX6_8         0x00000018  // 3/4 Full
-#define UART_IFLS_RX7_8         0x00000020  // 7/8 Full
-#define UART_IFLS_TX_M          0x00000007  // TX FIFO Level Interrupt Mask
-#define UART_IFLS_TX1_8         0x00000000  // 1/8 Full
-#define UART_IFLS_TX2_8         0x00000001  // 1/4 Full
-#define UART_IFLS_TX4_8         0x00000002  // 1/2 Full
-#define UART_IFLS_TX6_8         0x00000003  // 3/4 Full
-#define UART_IFLS_TX7_8         0x00000004  // 7/8 Full
-
-//*****************************************************************************
-//
-// The following are defines for the Interrupt Mask Set/Clear Register bits
-//
-//*****************************************************************************
-#define UART_IM_LME5IM          0x00008000  // LIN Mode Edge 5 Interrupt Mask.
-#define UART_IM_LME1IM          0x00004000  // LIN Mode Edge 1 Interrupt Mask.
-#define UART_IM_LMSBIM          0x00002000  // LIN Mode Sync Break Interrupt
-                                            // Mask.
-#define UART_IM_OEIM            0x00000400  // Overrun Error Interrupt Mask
-#define UART_IM_BEIM            0x00000200  // Break Error Interrupt Mask
-#define UART_IM_PEIM            0x00000100  // Parity Error Interrupt Mask
-#define UART_IM_FEIM            0x00000080  // Framing Error Interrupt Mask
-#define UART_IM_RTIM            0x00000040  // Receive Timeout Interrupt Mask
-#define UART_IM_TXIM            0x00000020  // Transmit Interrupt Mask
-#define UART_IM_RXIM            0x00000010  // Receive Interrupt Mask
-#define UART_IM_DSRMIM          0x00000008  // UART Data Set Ready Modem
-                                            // Interrupt Mask.
-#define UART_IM_DCDMIM          0x00000004  // UART Data Carrier Detect Modem
-                                            // Interrupt Mask.
-#define UART_IM_CTSMIM          0x00000002  // UART Clear to Send Modem
-                                            // Interrupt Mask.
-#define UART_IM_RIMIM           0x00000001  // UART Ring Indicator Modem
-                                            // Interrupt Mask.
-
-//*****************************************************************************
-//
-// The following are defines for the Raw Interrupt Status Register
-//
-//*****************************************************************************
-#define UART_RIS_LME5RIS        0x00008000  // LIN Mode Edge 5 Raw Interrupt
-                                            // Status.
-#define UART_RIS_LME1RIS        0x00004000  // LIN Mode Edge 1 Raw Interrupt
-                                            // Status.
-#define UART_RIS_LMSBRIS        0x00002000  // LIN Mode Sync Break Raw
-                                            // Interrupt Status.
-#define UART_RIS_OERIS          0x00000400  // Overrun Error Interrupt Status
-#define UART_RIS_BERIS          0x00000200  // Break Error Interrupt Status
-#define UART_RIS_PERIS          0x00000100  // Parity Error Interrupt Status
-#define UART_RIS_FERIS          0x00000080  // Framing Error Interrupt Status
-#define UART_RIS_RTRIS          0x00000040  // Receive Timeout Interrupt Status
-#define UART_RIS_TXRIS          0x00000020  // Transmit Interrupt Status
-#define UART_RIS_RXRIS          0x00000010  // Receive Interrupt Status
-#define UART_RIS_DSRRIS         0x00000008  // UART Data Set Ready Modem Raw
-                                            // Interrupt Status.
-#define UART_RIS_DCDRIS         0x00000004  // UART Data Carrier Detect odem
-                                            // Raw Interrupt Status.
-#define UART_RIS_CTSRIS         0x00000002  // UART Clear to Send Modem Raw
-                                            // Interrupt Status.
-#define UART_RIS_RIRIS          0x00000001  // UART Ring Indicator Modem Raw
-                                            // Interrupt Status.
-
-//*****************************************************************************
-//
-// The following are defines for the Masked Interrupt Status Register
-//
-//*****************************************************************************
-#define UART_MIS_LME5MIS        0x00008000  // LIN Mode Edge 5 Masked Interrupt
-                                            // Status.
-#define UART_MIS_LME1MIS        0x00004000  // LIN Mode Edge 1 Masked Interrupt
-                                            // Status.
-#define UART_MIS_LMSBMIS        0x00002000  // LIN Mode Sync Break Masked
-                                            // Interrupt Status.
-#define UART_MIS_OEMIS          0x00000400  // Overrun Error Interrupt Status
-#define UART_MIS_BEMIS          0x00000200  // Break Error Interrupt Status
-#define UART_MIS_PEMIS          0x00000100  // Parity Error Interrupt Status
-#define UART_MIS_FEMIS          0x00000080  // Framing Error Interrupt Status
-#define UART_MIS_RTMIS          0x00000040  // Receive Timeout Interrupt Status
-#define UART_MIS_TXMIS          0x00000020  // Transmit Interrupt Status
-#define UART_MIS_RXMIS          0x00000010  // Receive Interrupt Status
-#define UART_MIS_DSRMIS         0x00000008  // UART Data Set Ready Modem Masked
-                                            // Interrupt Status.
-#define UART_MIS_DCDMIS         0x00000004  // UART Data Carrier Detect odem
-                                            // Masked Interrupt Status.
-#define UART_MIS_CTSMIS         0x00000002  // UART Clear to Send Modem Masked
-                                            // Interrupt Status.
-#define UART_MIS_RIMIS          0x00000001  // UART Ring Indicator Modem Masked
-                                            // Interrupt Status.
-
-//*****************************************************************************
-//
-// The following are defines for the Interrupt Clear Register bits
-//
-//*****************************************************************************
-#define UART_ICR_LME5MIC        0x00008000  // LIN Mode Edge 5 Interrupt Clear.
-#define UART_ICR_LME1MIC        0x00004000  // LIN Mode Edge 1 Interrupt Clear.
-#define UART_ICR_LMSBMIC        0x00002000  // LIN Mode Sync Break Interrupt
-                                            // Clear.
-#define UART_ICR_OEIC           0x00000400  // Overrun Error Interrupt Clear
-#define UART_ICR_BEIC           0x00000200  // Break Error Interrupt Clear
-#define UART_ICR_PEIC           0x00000100  // Parity Error Interrupt Clear
-#define UART_ICR_FEIC           0x00000080  // Framing Error Interrupt Clear
-#define UART_ICR_RTIC           0x00000040  // Receive Timeout Interrupt Clear
-#define UART_ICR_TXIC           0x00000020  // Transmit Interrupt Clear
-#define UART_ICR_RXIC           0x00000010  // Receive Interrupt Clear
-#define UART_ICR_DSRMIC         0x00000008  // UART Data Set Ready Modem
-                                            // Interrupt Clear.
-#define UART_ICR_DCDMIC         0x00000004  // UART Data Carrier Detect odem
-                                            // Interrupt Clear.
-#define UART_ICR_CTSMIC         0x00000002  // UART Clear to Send Modem
-                                            // Interrupt Clear.
-#define UART_ICR_RIMIC          0x00000001  // UART Ring Indicator Modem
-                                            // Interrupt Clear.
+#define UART_RSR_OE             0x00000008  // UART Overrun Error
+#define UART_RSR_BE             0x00000004  // UART Break Error
+#define UART_RSR_PE             0x00000002  // UART Parity Error
+#define UART_RSR_FE             0x00000001  // UART Framing Error
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the UART_O_ECR register.
 //
 //*****************************************************************************
-#define UART_ECR_DATA_M         0x000000FF  // Error Clear.
+#define UART_ECR_DATA_M         0x000000FF  // Error Clear
 #define UART_ECR_DATA_S         0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the UART_O_LCRH register.
+// The following are defines for the bit fields in the UART_O_FR register.
 //
 //*****************************************************************************
-#define UART_LCRH_SPS           0x00000080  // UART Stick Parity Select.
-#define UART_LCRH_WLEN_M        0x00000060  // UART Word Length.
-#define UART_LCRH_WLEN_5        0x00000000  // 5 bits (default)
-#define UART_LCRH_WLEN_6        0x00000020  // 6 bits
-#define UART_LCRH_WLEN_7        0x00000040  // 7 bits
-#define UART_LCRH_WLEN_8        0x00000060  // 8 bits
-#define UART_LCRH_FEN           0x00000010  // UART Enable FIFOs.
-#define UART_LCRH_STP2          0x00000008  // UART Two Stop Bits Select.
-#define UART_LCRH_EPS           0x00000004  // UART Even Parity Select.
-#define UART_LCRH_PEN           0x00000002  // UART Parity Enable.
-#define UART_LCRH_BRK           0x00000001  // UART Send Break.
+#define UART_FR_RI              0x00000100  // Ring Indicator
+#define UART_FR_TXFE            0x00000080  // UART Transmit FIFO Empty
+#define UART_FR_RXFF            0x00000040  // UART Receive FIFO Full
+#define UART_FR_TXFF            0x00000020  // UART Transmit FIFO Full
+#define UART_FR_RXFE            0x00000010  // UART Receive FIFO Empty
+#define UART_FR_BUSY            0x00000008  // UART Busy
+#define UART_FR_DCD             0x00000004  // Data Carrier Detect
+#define UART_FR_DSR             0x00000002  // Data Set Ready
+#define UART_FR_CTS             0x00000001  // Clear To Send
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the UART_O_ILPR register.
 //
 //*****************************************************************************
-#define UART_ILPR_ILPDVSR_M     0x000000FF  // IrDA Low-Power Divisor.
+#define UART_ILPR_ILPDVSR_M     0x000000FF  // IrDA Low-Power Divisor
 #define UART_ILPR_ILPDVSR_S     0
 
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_IBRD register.
+//
+//*****************************************************************************
+#define UART_IBRD_DIVINT_M      0x0000FFFF  // Integer Baud-Rate Divisor
+#define UART_IBRD_DIVINT_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_FBRD register.
+//
+//*****************************************************************************
+#define UART_FBRD_DIVFRAC_M     0x0000003F  // Fractional Baud-Rate Divisor
+#define UART_FBRD_DIVFRAC_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_LCRH register.
+//
+//*****************************************************************************
+#define UART_LCRH_SPS           0x00000080  // UART Stick Parity Select
+#define UART_LCRH_WLEN_M        0x00000060  // UART Word Length
+#define UART_LCRH_WLEN_5        0x00000000  // 5 bits (default)
+#define UART_LCRH_WLEN_6        0x00000020  // 6 bits
+#define UART_LCRH_WLEN_7        0x00000040  // 7 bits
+#define UART_LCRH_WLEN_8        0x00000060  // 8 bits
+#define UART_LCRH_FEN           0x00000010  // UART Enable FIFOs
+#define UART_LCRH_STP2          0x00000008  // UART Two Stop Bits Select
+#define UART_LCRH_EPS           0x00000004  // UART Even Parity Select
+#define UART_LCRH_PEN           0x00000002  // UART Parity Enable
+#define UART_LCRH_BRK           0x00000001  // UART Send Break
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_CTL register.
+//
+//*****************************************************************************
+#define UART_CTL_CTSEN          0x00008000  // Enable Clear To Send
+#define UART_CTL_RTSEN          0x00004000  // Enable Request to Send
+#define UART_CTL_RTS            0x00000800  // Request to Send
+#define UART_CTL_DTR            0x00000400  // Data Terminal Ready
+#define UART_CTL_RXE            0x00000200  // UART Receive Enable
+#define UART_CTL_TXE            0x00000100  // UART Transmit Enable
+#define UART_CTL_LBE            0x00000080  // UART Loop Back Enable
+#define UART_CTL_LIN            0x00000040  // LIN Mode Enable
+#define UART_CTL_HSE            0x00000020  // High-Speed Enable
+#define UART_CTL_EOT            0x00000010  // End of Transmission
+#define UART_CTL_SMART          0x00000008  // ISO 7816 Smart Card Support
+#define UART_CTL_SIRLP          0x00000004  // UART SIR Low-Power Mode
+#define UART_CTL_SIREN          0x00000002  // UART SIR Enable
+#define UART_CTL_UARTEN         0x00000001  // UART Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_IFLS register.
+//
+//*****************************************************************************
+#define UART_IFLS_RX_M          0x00000038  // UART Receive Interrupt FIFO
+                                            // Level Select
+#define UART_IFLS_RX1_8         0x00000000  // RX FIFO >= 1/8 full
+#define UART_IFLS_RX2_8         0x00000008  // RX FIFO >= 1/4 full
+#define UART_IFLS_RX4_8         0x00000010  // RX FIFO >= 1/2 full (default)
+#define UART_IFLS_RX6_8         0x00000018  // RX FIFO >= 3/4 full
+#define UART_IFLS_RX7_8         0x00000020  // RX FIFO >= 7/8 full
+#define UART_IFLS_TX_M          0x00000007  // UART Transmit Interrupt FIFO
+                                            // Level Select
+#define UART_IFLS_TX1_8         0x00000000  // TX FIFO <= 1/8 full
+#define UART_IFLS_TX2_8         0x00000001  // TX FIFO <= 1/4 full
+#define UART_IFLS_TX4_8         0x00000002  // TX FIFO <= 1/2 full (default)
+#define UART_IFLS_TX6_8         0x00000003  // TX FIFO <= 3/4 full
+#define UART_IFLS_TX7_8         0x00000004  // TX FIFO <= 7/8 full
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_IM register.
+//
+//*****************************************************************************
+#define UART_IM_LME5IM          0x00008000  // LIN Mode Edge 5 Interrupt Mask
+#define UART_IM_LME1IM          0x00004000  // LIN Mode Edge 1 Interrupt Mask
+#define UART_IM_LMSBIM          0x00002000  // LIN Mode Sync Break Interrupt
+                                            // Mask
+#define UART_IM_OEIM            0x00000400  // UART Overrun Error Interrupt
+                                            // Mask
+#define UART_IM_BEIM            0x00000200  // UART Break Error Interrupt Mask
+#define UART_IM_PEIM            0x00000100  // UART Parity Error Interrupt Mask
+#define UART_IM_FEIM            0x00000080  // UART Framing Error Interrupt
+                                            // Mask
+#define UART_IM_RTIM            0x00000040  // UART Receive Time-Out Interrupt
+                                            // Mask
+#define UART_IM_TXIM            0x00000020  // UART Transmit Interrupt Mask
+#define UART_IM_RXIM            0x00000010  // UART Receive Interrupt Mask
+#define UART_IM_DSRMIM          0x00000008  // UART Data Set Ready Modem
+                                            // Interrupt Mask
+#define UART_IM_DCDMIM          0x00000004  // UART Data Carrier Detect Modem
+                                            // Interrupt Mask
+#define UART_IM_CTSMIM          0x00000002  // UART Clear to Send Modem
+                                            // Interrupt Mask
+#define UART_IM_RIMIM           0x00000001  // UART Ring Indicator Modem
+                                            // Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_RIS register.
+//
+//*****************************************************************************
+#define UART_RIS_LME5RIS        0x00008000  // LIN Mode Edge 5 Raw Interrupt
+                                            // Status
+#define UART_RIS_LME1RIS        0x00004000  // LIN Mode Edge 1 Raw Interrupt
+                                            // Status
+#define UART_RIS_LMSBRIS        0x00002000  // LIN Mode Sync Break Raw
+                                            // Interrupt Status
+#define UART_RIS_OERIS          0x00000400  // UART Overrun Error Raw Interrupt
+                                            // Status
+#define UART_RIS_BERIS          0x00000200  // UART Break Error Raw Interrupt
+                                            // Status
+#define UART_RIS_PERIS          0x00000100  // UART Parity Error Raw Interrupt
+                                            // Status
+#define UART_RIS_FERIS          0x00000080  // UART Framing Error Raw Interrupt
+                                            // Status
+#define UART_RIS_RTRIS          0x00000040  // UART Receive Time-Out Raw
+                                            // Interrupt Status
+#define UART_RIS_TXRIS          0x00000020  // UART Transmit Raw Interrupt
+                                            // Status
+#define UART_RIS_RXRIS          0x00000010  // UART Receive Raw Interrupt
+                                            // Status
+#define UART_RIS_DSRRIS         0x00000008  // UART Data Set Ready Modem Raw
+                                            // Interrupt Status
+#define UART_RIS_DCDRIS         0x00000004  // UART Data Carrier Detect Modem
+                                            // Raw Interrupt Status
+#define UART_RIS_CTSRIS         0x00000002  // UART Clear to Send Modem Raw
+                                            // Interrupt Status
+#define UART_RIS_RIRIS          0x00000001  // UART Ring Indicator Modem Raw
+                                            // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_MIS register.
+//
+//*****************************************************************************
+#define UART_MIS_LME5MIS        0x00008000  // LIN Mode Edge 5 Masked Interrupt
+                                            // Status
+#define UART_MIS_LME1MIS        0x00004000  // LIN Mode Edge 1 Masked Interrupt
+                                            // Status
+#define UART_MIS_LMSBMIS        0x00002000  // LIN Mode Sync Break Masked
+                                            // Interrupt Status
+#define UART_MIS_OEMIS          0x00000400  // UART Overrun Error Masked
+                                            // Interrupt Status
+#define UART_MIS_BEMIS          0x00000200  // UART Break Error Masked
+                                            // Interrupt Status
+#define UART_MIS_PEMIS          0x00000100  // UART Parity Error Masked
+                                            // Interrupt Status
+#define UART_MIS_FEMIS          0x00000080  // UART Framing Error Masked
+                                            // Interrupt Status
+#define UART_MIS_RTMIS          0x00000040  // UART Receive Time-Out Masked
+                                            // Interrupt Status
+#define UART_MIS_TXMIS          0x00000020  // UART Transmit Masked Interrupt
+                                            // Status
+#define UART_MIS_RXMIS          0x00000010  // UART Receive Masked Interrupt
+                                            // Status
+#define UART_MIS_DSRMIS         0x00000008  // UART Data Set Ready Modem Masked
+                                            // Interrupt Status
+#define UART_MIS_DCDMIS         0x00000004  // UART Data Carrier Detect Modem
+                                            // Masked Interrupt Status
+#define UART_MIS_CTSMIS         0x00000002  // UART Clear to Send Modem Masked
+                                            // Interrupt Status
+#define UART_MIS_RIMIS          0x00000001  // UART Ring Indicator Modem Masked
+                                            // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_ICR register.
+//
+//*****************************************************************************
+#define UART_ICR_LME5IC         0x00008000  // LIN Mode Edge 5 Interrupt Clear
+#define UART_ICR_LME1IC         0x00004000  // LIN Mode Edge 1 Interrupt Clear
+#define UART_ICR_LMSBIC         0x00002000  // LIN Mode Sync Break Interrupt
+                                            // Clear
+#define UART_ICR_OEIC           0x00000400  // Overrun Error Interrupt Clear
+#define UART_ICR_BEIC           0x00000200  // Break Error Interrupt Clear
+#define UART_ICR_PEIC           0x00000100  // Parity Error Interrupt Clear
+#define UART_ICR_FEIC           0x00000080  // Framing Error Interrupt Clear
+#define UART_ICR_RTIC           0x00000040  // Receive Time-Out Interrupt Clear
+#define UART_ICR_TXIC           0x00000020  // Transmit Interrupt Clear
+#define UART_ICR_RXIC           0x00000010  // Receive Interrupt Clear
+#define UART_ICR_DSRMIC         0x00000008  // UART Data Set Ready Modem
+                                            // Interrupt Clear
+#define UART_ICR_DCDMIC         0x00000004  // UART Data Carrier Detect Modem
+                                            // Interrupt Clear
+#define UART_ICR_CTSMIC         0x00000002  // UART Clear to Send Modem
+                                            // Interrupt Clear
+#define UART_ICR_RIMIC          0x00000001  // UART Ring Indicator Modem
+                                            // Interrupt Clear
+
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the UART_O_DMACTL register.
 //
 //*****************************************************************************
-#define UART_DMACTL_DMAERR      0x00000004  // DMA on Error.
-#define UART_DMACTL_TXDMAE      0x00000002  // Transmit DMA Enable.
-#define UART_DMACTL_RXDMAE      0x00000001  // Receive DMA Enable.
+#define UART_DMACTL_DMAERR      0x00000004  // DMA on Error
+#define UART_DMACTL_TXDMAE      0x00000002  // Transmit DMA Enable
+#define UART_DMACTL_RXDMAE      0x00000001  // Receive DMA Enable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the UART_O_LCTL register.
 //
 //*****************************************************************************
-#define UART_LCTL_BLEN_M        0x00000030  // Sync Break Length.
+#define UART_LCTL_BLEN_M        0x00000030  // Sync Break Length
 #define UART_LCTL_BLEN_13T      0x00000000  // Sync break length is 13T bits
                                             // (default)
 #define UART_LCTL_BLEN_14T      0x00000010  // Sync break length is 14T bits
 #define UART_LCTL_BLEN_15T      0x00000020  // Sync break length is 15T bits
 #define UART_LCTL_BLEN_16T      0x00000030  // Sync break length is 16T bits
-#define UART_LCTL_MASTER        0x00000001  // LIN Master Enable.
+#define UART_LCTL_MASTER        0x00000001  // LIN Master Enable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the UART_O_LSS register.
 //
 //*****************************************************************************
-#define UART_LSS_TSS_M          0x0000FFFF  // Timer Snap Shot.
+#define UART_LSS_TSS_M          0x0000FFFF  // Timer Snap Shot
 #define UART_LSS_TSS_S          0
 
 //*****************************************************************************
@@ -315,7 +332,7 @@
 // The following are defines for the bit fields in the UART_O_LTIM register.
 //
 //*****************************************************************************
-#define UART_LTIM_TIMER_M       0x0000FFFF  // Timer Value.
+#define UART_LTIM_TIMER_M       0x0000FFFF  // Timer Value
 #define UART_LTIM_TIMER_S       0
 
 //*****************************************************************************
@@ -327,7 +344,7 @@
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the UART Register offsets.
+// The following are deprecated defines for the UART register offsets.
 //
 //*****************************************************************************
 #define UART_O_LCR_H            0x0000002C  // Line Control Register, HIGH byte
@@ -346,28 +363,32 @@
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the Data Register bits
+// The following are deprecated defines for the bit fields in the UART_O_DR
+// register.
 //
 //*****************************************************************************
 #define UART_DR_DATA_MASK       0x000000FF  // UART data
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the Integer baud-rate divisor
+// The following are deprecated defines for the bit fields in the UART_O_IBRD
+// register.
 //
 //*****************************************************************************
 #define UART_IBRD_DIVINT_MASK   0x0000FFFF  // Integer baud-rate divisor
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the Fractional baud-rate divisor
+// The following are deprecated defines for the bit fields in the UART_O_FBRD
+// register.
 //
 //*****************************************************************************
 #define UART_FBRD_DIVFRAC_MASK  0x0000003F  // Fractional baud-rate divisor
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the Line Control Register High bits
+// The following are deprecated defines for the bit fields in the UART_O_LCR_H
+// register.
 //
 //*****************************************************************************
 #define UART_LCR_H_SPS          0x00000080  // Stick Parity Select
@@ -384,8 +405,8 @@
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the Interrupt FIFO Level Select
-// Register bits
+// The following are deprecated defines for the bit fields in the UART_O_IFLS
+// register.
 //
 //*****************************************************************************
 #define UART_IFLS_RX_MASK       0x00000038  // RX FIFO level mask
@@ -393,9 +414,14 @@
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the Interrupt Clear Register bits
+// The following are deprecated defines for the bit fields in the UART_O_ICR
+// register.
 //
 //*****************************************************************************
+#define UART_ICR_LME5MIC        0x00008000  // LIN Mode Edge 5 Interrupt Clear
+#define UART_ICR_LME1MIC        0x00004000  // LIN Mode Edge 1 Interrupt Clear
+#define UART_ICR_LMSBMIC        0x00002000  // LIN Mode Sync Break Interrupt
+                                            // Clear
 #define UART_RSR_ANY            (UART_RSR_OE | UART_RSR_BE | UART_RSR_PE | \
                                  UART_RSR_FE)
 
diff --git a/src/platform/lm3s/hw_udma.h b/src/platform/lm3s/inc/hw_udma.h
similarity index 81%
rename from src/platform/lm3s/hw_udma.h
rename to src/platform/lm3s/inc/hw_udma.h
index 62b297dd..4a1b4fee 100755
--- a/src/platform/lm3s/hw_udma.h
+++ b/src/platform/lm3s/inc/hw_udma.h
@@ -2,26 +2,23 @@
 //
 // hw_udma.h - Macros for use in accessing the UDMA registers.
 //
-// Copyright (c) 2007-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2007-2011 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4781 of the Stellaris Firmware Development Package.
+// This is part of revision 7611 of the Stellaris Firmware Development Package.
 //
 //*****************************************************************************
 
@@ -30,7 +27,8 @@
 
 //*****************************************************************************
 //
-// The following are defines for the Micro Direct Memory Access (uDMA) offsets.
+// The following are defines for the Micro Direct Memory Access register
+// addresses.
 //
 //*****************************************************************************
 #define UDMA_STAT               0x400FF000  // DMA Status
@@ -38,7 +36,7 @@
 #define UDMA_CTLBASE            0x400FF008  // DMA Channel Control Base Pointer
 #define UDMA_ALTBASE            0x400FF00C  // DMA Alternate Channel Control
                                             // Base Pointer
-#define UDMA_WAITSTAT           0x400FF010  // DMA Channel Wait on Request
+#define UDMA_WAITSTAT           0x400FF010  // DMA Channel Wait-on-Request
                                             // Status
 #define UDMA_SWREQ              0x400FF014  // DMA Channel Software Request
 #define UDMA_USEBURSTSET        0x400FF018  // DMA Channel Useburst Set
@@ -54,12 +52,175 @@
 #define UDMA_PRIOSET            0x400FF038  // DMA Channel Priority Set
 #define UDMA_PRIOCLR            0x400FF03C  // DMA Channel Priority Clear
 #define UDMA_ERRCLR             0x400FF04C  // DMA Bus Error Clear
-#define UDMA_CHALT              0x400FF500  // DMA Channel Alternate Select
+#define UDMA_CHASGN             0x400FF500  // DMA Channel Assignment
 #define UDMA_CHIS               0x400FF504  // DMA Channel Interrupt Status
 
 //*****************************************************************************
 //
-// Micro Direct Memory Access (uDMA) offsets.
+// The following are defines for the bit fields in the UDMA_STAT register.
+//
+//*****************************************************************************
+#define UDMA_STAT_DMACHANS_M    0x001F0000  // Available uDMA Channels Minus 1
+#define UDMA_STAT_STATE_M       0x000000F0  // Control State Machine Status
+#define UDMA_STAT_STATE_IDLE    0x00000000  // Idle
+#define UDMA_STAT_STATE_RD_CTRL 0x00000010  // Reading channel controller data
+#define UDMA_STAT_STATE_RD_SRCENDP \
+                                0x00000020  // Reading source end pointer
+#define UDMA_STAT_STATE_RD_DSTENDP \
+                                0x00000030  // Reading destination end pointer
+#define UDMA_STAT_STATE_RD_SRCDAT \
+                                0x00000040  // Reading source data
+#define UDMA_STAT_STATE_WR_DSTDAT \
+                                0x00000050  // Writing destination data
+#define UDMA_STAT_STATE_WAIT    0x00000060  // Waiting for uDMA request to
+                                            // clear
+#define UDMA_STAT_STATE_WR_CTRL 0x00000070  // Writing channel controller data
+#define UDMA_STAT_STATE_STALL   0x00000080  // Stalled
+#define UDMA_STAT_STATE_DONE    0x00000090  // Done
+#define UDMA_STAT_STATE_UNDEF   0x000000A0  // Undefined
+#define UDMA_STAT_MASTEN        0x00000001  // Master Enable Status
+#define UDMA_STAT_DMACHANS_S    16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CFG register.
+//
+//*****************************************************************************
+#define UDMA_CFG_MASTEN         0x00000001  // Controller Master Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CTLBASE register.
+//
+//*****************************************************************************
+#define UDMA_CTLBASE_ADDR_M     0xFFFFFC00  // Channel Control Base Address
+#define UDMA_CTLBASE_ADDR_S     10
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ALTBASE register.
+//
+//*****************************************************************************
+#define UDMA_ALTBASE_ADDR_M     0xFFFFFFFF  // Alternate Channel Address
+                                            // Pointer
+#define UDMA_ALTBASE_ADDR_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_WAITSTAT register.
+//
+//*****************************************************************************
+#define UDMA_WAITSTAT_WAITREQ_M 0xFFFFFFFF  // Channel [n] Wait Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_SWREQ register.
+//
+//*****************************************************************************
+#define UDMA_SWREQ_M            0xFFFFFFFF  // Channel [n] Software Request
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_USEBURSTSET
+// register.
+//
+//*****************************************************************************
+#define UDMA_USEBURSTSET_SET_M  0xFFFFFFFF  // Channel [n] Useburst Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_USEBURSTCLR
+// register.
+//
+//*****************************************************************************
+#define UDMA_USEBURSTCLR_CLR_M  0xFFFFFFFF  // Channel [n] Useburst Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_REQMASKSET
+// register.
+//
+//*****************************************************************************
+#define UDMA_REQMASKSET_SET_M   0xFFFFFFFF  // Channel [n] Request Mask Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_REQMASKCLR
+// register.
+//
+//*****************************************************************************
+#define UDMA_REQMASKCLR_CLR_M   0xFFFFFFFF  // Channel [n] Request Mask Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ENASET register.
+//
+//*****************************************************************************
+#define UDMA_ENASET_SET_M       0xFFFFFFFF  // Channel [n] Enable Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ENACLR register.
+//
+//*****************************************************************************
+#define UDMA_ENACLR_CLR_M       0xFFFFFFFF  // Clear Channel [n] Enable Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ALTSET register.
+//
+//*****************************************************************************
+#define UDMA_ALTSET_SET_M       0xFFFFFFFF  // Channel [n] Alternate Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ALTCLR register.
+//
+//*****************************************************************************
+#define UDMA_ALTCLR_CLR_M       0xFFFFFFFF  // Channel [n] Alternate Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_PRIOSET register.
+//
+//*****************************************************************************
+#define UDMA_PRIOSET_SET_M      0xFFFFFFFF  // Channel [n] Priority Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_PRIOCLR register.
+//
+//*****************************************************************************
+#define UDMA_PRIOCLR_CLR_M      0xFFFFFFFF  // Channel [n] Priority Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ERRCLR register.
+//
+//*****************************************************************************
+#define UDMA_ERRCLR_ERRCLR      0x00000001  // uDMA Bus Error Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CHASGN register.
+//
+//*****************************************************************************
+#define UDMA_CHASGN_M           0xFFFFFFFF  // Channel [n] Assignment Select
+#define UDMA_CHASGN_PRIMARY     0x00000000  // Use the primary channel
+                                            // assignment
+#define UDMA_CHASGN_SECONDARY   0x00000001  // Use the secondary channel
+                                            // assignment
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CHIS register.
+//
+//*****************************************************************************
+#define UDMA_CHIS_M             0xFFFFFFFF  // Channel [n] Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the Micro Direct Memory Access (uDMA) offsets.
 //
 //*****************************************************************************
 #define UDMA_O_SRCENDP          0x00000000  // DMA Channel Source Address End
@@ -73,81 +234,41 @@
 // The following are defines for the bit fields in the UDMA_O_SRCENDP register.
 //
 //*****************************************************************************
-#define UDMA_SRCENDP_ADDR_M     0xFFFFFFFF  // Source Address End Pointer.
+#define UDMA_SRCENDP_ADDR_M     0xFFFFFFFF  // Source Address End Pointer
 #define UDMA_SRCENDP_ADDR_S     0
 
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_STAT register.
-//
-//*****************************************************************************
-#define UDMA_STAT_DMACHANS_M    0x001F0000  // Available DMA Channels Minus 1.
-#define UDMA_STAT_STATE_M       0x000000F0  // Control State Machine State.
-#define UDMA_STAT_STATE_IDLE    0x00000000  // Idle
-#define UDMA_STAT_STATE_RD_CTRL 0x00000010  // Reading channel controller data
-#define UDMA_STAT_STATE_RD_SRCENDP \
-                                0x00000020  // Reading source end pointer
-#define UDMA_STAT_STATE_RD_DSTENDP \
-                                0x00000030  // Reading destination end pointer
-#define UDMA_STAT_STATE_RD_SRCDAT \
-                                0x00000040  // Reading source data
-#define UDMA_STAT_STATE_WR_DSTDAT \
-                                0x00000050  // Writing destination data
-#define UDMA_STAT_STATE_WAIT    0x00000060  // Waiting for DMA request to clear
-#define UDMA_STAT_STATE_WR_CTRL 0x00000070  // Writing channel controller data
-#define UDMA_STAT_STATE_STALL   0x00000080  // Stalled
-#define UDMA_STAT_STATE_DONE    0x00000090  // Done
-#define UDMA_STAT_STATE_UNDEF   0x000000A0  // Undefined
-#define UDMA_STAT_MASTEN        0x00000001  // Master Enable.
-#define UDMA_STAT_DMACHANS_S    16
-
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the UDMA_O_DSTENDP register.
 //
 //*****************************************************************************
-#define UDMA_DSTENDP_ADDR_M     0xFFFFFFFF  // Destination Address End Pointer.
+#define UDMA_DSTENDP_ADDR_M     0xFFFFFFFF  // Destination Address End Pointer
 #define UDMA_DSTENDP_ADDR_S     0
 
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_CFG register.
-//
-//*****************************************************************************
-#define UDMA_CFG_MASTEN         0x00000001  // Controller Master Enable.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_CTLBASE register.
-//
-//*****************************************************************************
-#define UDMA_CTLBASE_ADDR_M     0xFFFFFC00  // Channel Control Base Address.
-#define UDMA_CTLBASE_ADDR_S     10
-
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the UDMA_O_CHCTL register.
 //
 //*****************************************************************************
-#define UDMA_CHCTL_DSTINC_M     0xC0000000  // Destination Address Increment.
+#define UDMA_CHCTL_DSTINC_M     0xC0000000  // Destination Address Increment
 #define UDMA_CHCTL_DSTINC_8     0x00000000  // Byte
 #define UDMA_CHCTL_DSTINC_16    0x40000000  // Half-word
 #define UDMA_CHCTL_DSTINC_32    0x80000000  // Word
 #define UDMA_CHCTL_DSTINC_NONE  0xC0000000  // No increment
-#define UDMA_CHCTL_DSTSIZE_M    0x30000000  // Destination Data Size.
+#define UDMA_CHCTL_DSTSIZE_M    0x30000000  // Destination Data Size
 #define UDMA_CHCTL_DSTSIZE_8    0x00000000  // Byte
 #define UDMA_CHCTL_DSTSIZE_16   0x10000000  // Half-word
 #define UDMA_CHCTL_DSTSIZE_32   0x20000000  // Word
-#define UDMA_CHCTL_SRCINC_M     0x0C000000  // Source Address Increment.
+#define UDMA_CHCTL_SRCINC_M     0x0C000000  // Source Address Increment
 #define UDMA_CHCTL_SRCINC_8     0x00000000  // Byte
 #define UDMA_CHCTL_SRCINC_16    0x04000000  // Half-word
 #define UDMA_CHCTL_SRCINC_32    0x08000000  // Word
 #define UDMA_CHCTL_SRCINC_NONE  0x0C000000  // No increment
-#define UDMA_CHCTL_SRCSIZE_M    0x03000000  // Source Data Size.
+#define UDMA_CHCTL_SRCSIZE_M    0x03000000  // Source Data Size
 #define UDMA_CHCTL_SRCSIZE_8    0x00000000  // Byte
 #define UDMA_CHCTL_SRCSIZE_16   0x01000000  // Half-word
 #define UDMA_CHCTL_SRCSIZE_32   0x02000000  // Word
-#define UDMA_CHCTL_ARBSIZE_M    0x0003C000  // Arbitration Size.
+#define UDMA_CHCTL_ARBSIZE_M    0x0003C000  // Arbitration Size
 #define UDMA_CHCTL_ARBSIZE_1    0x00000000  // 1 Transfer
 #define UDMA_CHCTL_ARBSIZE_2    0x00004000  // 2 Transfers
 #define UDMA_CHCTL_ARBSIZE_4    0x00008000  // 4 Transfers
@@ -159,9 +280,9 @@
 #define UDMA_CHCTL_ARBSIZE_256  0x00020000  // 256 Transfers
 #define UDMA_CHCTL_ARBSIZE_512  0x00024000  // 512 Transfers
 #define UDMA_CHCTL_ARBSIZE_1024 0x00028000  // 1024 Transfers
-#define UDMA_CHCTL_XFERSIZE_M   0x00003FF0  // Transfer Size (minus 1).
-#define UDMA_CHCTL_NXTUSEBURST  0x00000008  // Next Useburst.
-#define UDMA_CHCTL_XFERMODE_M   0x00000007  // DMA Transfer Mode.
+#define UDMA_CHCTL_XFERSIZE_M   0x00003FF0  // Transfer Size (minus 1)
+#define UDMA_CHCTL_NXTUSEBURST  0x00000008  // Next Useburst
+#define UDMA_CHCTL_XFERMODE_M   0x00000007  // uDMA Transfer Mode
 #define UDMA_CHCTL_XFERMODE_STOP \
                                 0x00000000  // Stop
 #define UDMA_CHCTL_XFERMODE_BASIC \
@@ -181,125 +302,6 @@
                                             // Scatter-Gather
 #define UDMA_CHCTL_XFERSIZE_S   4
 
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_ALTBASE register.
-//
-//*****************************************************************************
-#define UDMA_ALTBASE_ADDR_M     0xFFFFFFFF  // Alternate Channel Address
-                                            // Pointer.
-#define UDMA_ALTBASE_ADDR_S     0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_WAITSTAT register.
-//
-//*****************************************************************************
-#define UDMA_WAITSTAT_WAITREQ_M 0xFFFFFFFF  // Channel [n] Wait Status.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_SWREQ register.
-//
-//*****************************************************************************
-#define UDMA_SWREQ_M            0xFFFFFFFF  // Channel [n] Software Request.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_USEBURSTSET
-// register.
-//
-//*****************************************************************************
-#define UDMA_USEBURSTSET_SET_M  0xFFFFFFFF  // Channel [n] Useburst Set.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_USEBURSTCLR
-// register.
-//
-//*****************************************************************************
-#define UDMA_USEBURSTCLR_CLR_M  0xFFFFFFFF  // Channel [n] Useburst Clear.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_REQMASKSET
-// register.
-//
-//*****************************************************************************
-#define UDMA_REQMASKSET_SET_M   0xFFFFFFFF  // Channel [n] Request Mask Set.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_REQMASKCLR
-// register.
-//
-//*****************************************************************************
-#define UDMA_REQMASKCLR_CLR_M   0xFFFFFFFF  // Channel [n] Request Mask Clear.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_ENASET register.
-//
-//*****************************************************************************
-#define UDMA_ENASET_SET_M       0xFFFFFFFF  // Channel [n] Enable Set.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_ENACLR register.
-//
-//*****************************************************************************
-#define UDMA_ENACLR_CLR_M       0xFFFFFFFF  // Clear Channel [n] Enable.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_ALTSET register.
-//
-//*****************************************************************************
-#define UDMA_ALTSET_SET_M       0xFFFFFFFF  // Channel [n] Alternate Set.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_ALTCLR register.
-//
-//*****************************************************************************
-#define UDMA_ALTCLR_CLR_M       0xFFFFFFFF  // Channel [n] Alternate Clear.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_PRIOSET register.
-//
-//*****************************************************************************
-#define UDMA_PRIOSET_SET_M      0xFFFFFFFF  // Channel [n] Priority Set.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_PRIOCLR register.
-//
-//*****************************************************************************
-#define UDMA_PRIOCLR_CLR_M      0xFFFFFFFF  // Channel [n] Priority Clear.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_ERRCLR register.
-//
-//*****************************************************************************
-#define UDMA_ERRCLR_ERRCLR      0x00000001  // DMA Bus Error Status.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_CHALT register.
-//
-//*****************************************************************************
-#define UDMA_CHALT_M            0xFFFFFFFF  // Channel [n] Alternate Assignment
-                                            // Select.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_CHIS register.
-//
-//*****************************************************************************
-#define UDMA_CHIS_M             0xFFFFFFFF  // Channel [n] Interrupt Status.
-
 //*****************************************************************************
 //
 // The following definitions are deprecated.
@@ -307,13 +309,30 @@
 //*****************************************************************************
 #ifndef DEPRECATED
 
+//*****************************************************************************
+//
+// The following are deprecated defines for the Micro Direct Memory Access
+// register addresses.
+//
+//*****************************************************************************
+#define UDMA_CHALT              0x400FF500  // DMA Channel Alternate Select
+
 //*****************************************************************************
 //
 // The following are deprecated defines for the bit fields in the UDMA_ENASET
 // register.
 //
 //*****************************************************************************
-#define UDMA_ENASET_CHENSET_M   0xFFFFFFFF  // Channel [n] Enable Set.
+#define UDMA_ENASET_CHENSET_M   0xFFFFFFFF  // Channel [n] Enable Set
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the UDMA_CHALT
+// register.
+//
+//*****************************************************************************
+#define UDMA_CHALT_M            0xFFFFFFFF  // Channel [n] Alternate Assignment
+                                            // Select
 
 #endif
 
diff --git a/src/platform/lm3s/hw_usb.h b/src/platform/lm3s/inc/hw_usb.h
similarity index 78%
rename from src/platform/lm3s/hw_usb.h
rename to src/platform/lm3s/inc/hw_usb.h
index 549a768b..46fd601a 100755
--- a/src/platform/lm3s/hw_usb.h
+++ b/src/platform/lm3s/inc/hw_usb.h
@@ -2,26 +2,23 @@
 //
 // hw_usb.h - Macros for use in accessing the USB registers.
 //
-// Copyright (c) 2007-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2007-2011 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4781 of the Stellaris Firmware Development Package.
+// This is part of revision 7611 of the Stellaris Firmware Development Package.
 //
 //*****************************************************************************
 
@@ -30,8 +27,7 @@
 
 //*****************************************************************************
 //
-// The following are defines for the Univeral Serial Bus (USB) Controller
-// offsets.
+// The following are defines for the Univeral Serial Bus register offsets.
 //
 //*****************************************************************************
 #define USB_O_FADDR             0x00000000  // USB Device Functional Address
@@ -67,7 +63,7 @@
 #define USB_O_TXFIFOADD         0x00000064  // USB Transmit FIFO Start Address
 #define USB_O_RXFIFOADD         0x00000066  // USB Receive FIFO Start Address
 #define USB_O_CONTIM            0x0000007A  // USB Connect Timing
-#define USB_O_VPLEN             0x0000007B  // USB OTG VBus Pulse Timing
+#define USB_O_VPLEN             0x0000007B  // USB OTG VBUS Pulse Timing
 #define USB_O_FSEOF             0x0000007D  // USB Full-Speed Last Transaction
                                             // to End of Frame Timing
 #define USB_O_LSEOF             0x0000007E  // USB Low-Speed Last Transaction
@@ -612,10 +608,10 @@
                                             // Interrupt Mask
 #define USB_O_EPCISC            0x0000040C  // USB External Power Control
                                             // Interrupt Status and Clear
-#define USB_O_DRRIS             0x00000410  // USB Device Resume Raw Interrupt
+#define USB_O_DRRIS             0x00000410  // USB Device RESUME Raw Interrupt
                                             // Status
-#define USB_O_DRIM              0x00000414  // USB Device Resume Interrupt Mask
-#define USB_O_DRISC             0x00000418  // USB Device Resume Interrupt
+#define USB_O_DRIM              0x00000414  // USB Device RESUME Interrupt Mask
+#define USB_O_DRISC             0x00000418  // USB Device RESUME Interrupt
                                             // Status and Clear
 #define USB_O_GPCS              0x0000041C  // USB General-Purpose Control and
                                             // Status
@@ -632,14 +628,14 @@
                                             // Mask
 #define USB_O_IDVISC            0x0000044C  // USB ID Valid Detect Interrupt
                                             // Status and Clear
-#define USB_O_EPS               0x00000450  // USB End-Point Select
+#define USB_O_DMASEL            0x00000450  // USB DMA Select
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_FADDR register.
 //
 //*****************************************************************************
-#define USB_FADDR_M             0x0000007F  // Function Address.
+#define USB_FADDR_M             0x0000007F  // Function Address
 #define USB_FADDR_S             0
 
 //*****************************************************************************
@@ -647,137 +643,136 @@
 // The following are defines for the bit fields in the USB_O_POWER register.
 //
 //*****************************************************************************
-#define USB_POWER_ISOUP         0x00000080  // ISO Update.
-#define USB_POWER_SOFTCONN      0x00000040  // Soft Connect/Disconnect.
-#define USB_POWER_RESET         0x00000008  // Reset.
-#define USB_POWER_RESUME        0x00000004  // Resume Signaling.
-#define USB_POWER_SUSPEND       0x00000002  // Suspend Mode.
-#define USB_POWER_PWRDNPHY      0x00000001  // Power Down PHY.
+#define USB_POWER_ISOUP         0x00000080  // Isochronous Update
+#define USB_POWER_SOFTCONN      0x00000040  // Soft Connect/Disconnect
+#define USB_POWER_RESET         0x00000008  // RESET Signaling
+#define USB_POWER_RESUME        0x00000004  // RESUME Signaling
+#define USB_POWER_SUSPEND       0x00000002  // SUSPEND Mode
+#define USB_POWER_PWRDNPHY      0x00000001  // Power Down PHY
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_TXIS register.
 //
 //*****************************************************************************
-#define USB_TXIS_EP15           0x00008000  // TX Endpoint 15 Interrupt.
-#define USB_TXIS_EP14           0x00004000  // TX Endpoint 14 Interrupt.
-#define USB_TXIS_EP13           0x00002000  // TX Endpoint 13 Interrupt.
-#define USB_TXIS_EP12           0x00001000  // TX Endpoint 12 Interrupt.
-#define USB_TXIS_EP11           0x00000800  // TX Endpoint 11 Interrupt.
-#define USB_TXIS_EP10           0x00000400  // TX Endpoint 10 Interrupt.
-#define USB_TXIS_EP9            0x00000200  // TX Endpoint 9 Interrupt.
-#define USB_TXIS_EP8            0x00000100  // TX Endpoint 8 Interrupt.
-#define USB_TXIS_EP7            0x00000080  // TX Endpoint 7 Interrupt.
-#define USB_TXIS_EP6            0x00000040  // TX Endpoint 6 Interrupt.
-#define USB_TXIS_EP5            0x00000020  // TX Endpoint 5 Interrupt.
-#define USB_TXIS_EP4            0x00000010  // TX Endpoint 4 Interrupt.
-#define USB_TXIS_EP3            0x00000008  // TX Endpoint 3 Interrupt.
-#define USB_TXIS_EP2            0x00000004  // TX Endpoint 2 Interrupt.
-#define USB_TXIS_EP1            0x00000002  // TX Endpoint 1 Interrupt.
-#define USB_TXIS_EP0            0x00000001  // TX and RX Endpoint 0 Interrupt.
+#define USB_TXIS_EP15           0x00008000  // TX Endpoint 15 Interrupt
+#define USB_TXIS_EP14           0x00004000  // TX Endpoint 14 Interrupt
+#define USB_TXIS_EP13           0x00002000  // TX Endpoint 13 Interrupt
+#define USB_TXIS_EP12           0x00001000  // TX Endpoint 12 Interrupt
+#define USB_TXIS_EP11           0x00000800  // TX Endpoint 11 Interrupt
+#define USB_TXIS_EP10           0x00000400  // TX Endpoint 10 Interrupt
+#define USB_TXIS_EP9            0x00000200  // TX Endpoint 9 Interrupt
+#define USB_TXIS_EP8            0x00000100  // TX Endpoint 8 Interrupt
+#define USB_TXIS_EP7            0x00000080  // TX Endpoint 7 Interrupt
+#define USB_TXIS_EP6            0x00000040  // TX Endpoint 6 Interrupt
+#define USB_TXIS_EP5            0x00000020  // TX Endpoint 5 Interrupt
+#define USB_TXIS_EP4            0x00000010  // TX Endpoint 4 Interrupt
+#define USB_TXIS_EP3            0x00000008  // TX Endpoint 3 Interrupt
+#define USB_TXIS_EP2            0x00000004  // TX Endpoint 2 Interrupt
+#define USB_TXIS_EP1            0x00000002  // TX Endpoint 1 Interrupt
+#define USB_TXIS_EP0            0x00000001  // TX and RX Endpoint 0 Interrupt
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXIS register.
 //
 //*****************************************************************************
-#define USB_RXIS_EP15           0x00008000  // RX Endpoint 15 Interrupt.
-#define USB_RXIS_EP14           0x00004000  // RX Endpoint 14 Interrupt.
-#define USB_RXIS_EP13           0x00002000  // RX Endpoint 13 Interrupt.
-#define USB_RXIS_EP12           0x00001000  // RX Endpoint 12 Interrupt.
-#define USB_RXIS_EP11           0x00000800  // RX Endpoint 11 Interrupt.
-#define USB_RXIS_EP10           0x00000400  // RX Endpoint 10 Interrupt.
-#define USB_RXIS_EP9            0x00000200  // RX Endpoint 9 Interrupt.
-#define USB_RXIS_EP8            0x00000100  // RX Endpoint 8 Interrupt.
-#define USB_RXIS_EP7            0x00000080  // RX Endpoint 7 Interrupt.
-#define USB_RXIS_EP6            0x00000040  // RX Endpoint 6 Interrupt.
-#define USB_RXIS_EP5            0x00000020  // RX Endpoint 5 Interrupt.
-#define USB_RXIS_EP4            0x00000010  // RX Endpoint 4 Interrupt.
-#define USB_RXIS_EP3            0x00000008  // RX Endpoint 3 Interrupt.
-#define USB_RXIS_EP2            0x00000004  // RX Endpoint 2 Interrupt.
-#define USB_RXIS_EP1            0x00000002  // RX Endpoint 1 Interrupt.
+#define USB_RXIS_EP15           0x00008000  // RX Endpoint 15 Interrupt
+#define USB_RXIS_EP14           0x00004000  // RX Endpoint 14 Interrupt
+#define USB_RXIS_EP13           0x00002000  // RX Endpoint 13 Interrupt
+#define USB_RXIS_EP12           0x00001000  // RX Endpoint 12 Interrupt
+#define USB_RXIS_EP11           0x00000800  // RX Endpoint 11 Interrupt
+#define USB_RXIS_EP10           0x00000400  // RX Endpoint 10 Interrupt
+#define USB_RXIS_EP9            0x00000200  // RX Endpoint 9 Interrupt
+#define USB_RXIS_EP8            0x00000100  // RX Endpoint 8 Interrupt
+#define USB_RXIS_EP7            0x00000080  // RX Endpoint 7 Interrupt
+#define USB_RXIS_EP6            0x00000040  // RX Endpoint 6 Interrupt
+#define USB_RXIS_EP5            0x00000020  // RX Endpoint 5 Interrupt
+#define USB_RXIS_EP4            0x00000010  // RX Endpoint 4 Interrupt
+#define USB_RXIS_EP3            0x00000008  // RX Endpoint 3 Interrupt
+#define USB_RXIS_EP2            0x00000004  // RX Endpoint 2 Interrupt
+#define USB_RXIS_EP1            0x00000002  // RX Endpoint 1 Interrupt
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_TXIE register.
 //
 //*****************************************************************************
-#define USB_TXIE_EP15           0x00008000  // TX Endpoint 15 Interrupt Enable.
-#define USB_TXIE_EP14           0x00004000  // TX Endpoint 14 Interrupt Enable.
-#define USB_TXIE_EP13           0x00002000  // TX Endpoint 13 Interrupt Enable.
-#define USB_TXIE_EP12           0x00001000  // TX Endpoint 12 Interrupt Enable.
-#define USB_TXIE_EP11           0x00000800  // TX Endpoint 11 Interrupt Enable.
-#define USB_TXIE_EP10           0x00000400  // TX Endpoint 10 Interrupt Enable.
-#define USB_TXIE_EP9            0x00000200  // TX Endpoint 9 Interrupt Enable.
-#define USB_TXIE_EP8            0x00000100  // TX Endpoint 8 Interrupt Enable.
-#define USB_TXIE_EP7            0x00000080  // TX Endpoint 7 Interrupt Enable.
-#define USB_TXIE_EP6            0x00000040  // TX Endpoint 6 Interrupt Enable.
-#define USB_TXIE_EP5            0x00000020  // TX Endpoint 5 Interrupt Enable.
-#define USB_TXIE_EP4            0x00000010  // TX Endpoint 4 Interrupt Enable.
-#define USB_TXIE_EP3            0x00000008  // TX Endpoint 3 Interrupt Enable.
-#define USB_TXIE_EP2            0x00000004  // TX Endpoint 2 Interrupt Enable.
-#define USB_TXIE_EP1            0x00000002  // TX Endpoint 1 Interrupt Enable.
+#define USB_TXIE_EP15           0x00008000  // TX Endpoint 15 Interrupt Enable
+#define USB_TXIE_EP14           0x00004000  // TX Endpoint 14 Interrupt Enable
+#define USB_TXIE_EP13           0x00002000  // TX Endpoint 13 Interrupt Enable
+#define USB_TXIE_EP12           0x00001000  // TX Endpoint 12 Interrupt Enable
+#define USB_TXIE_EP11           0x00000800  // TX Endpoint 11 Interrupt Enable
+#define USB_TXIE_EP10           0x00000400  // TX Endpoint 10 Interrupt Enable
+#define USB_TXIE_EP9            0x00000200  // TX Endpoint 9 Interrupt Enable
+#define USB_TXIE_EP8            0x00000100  // TX Endpoint 8 Interrupt Enable
+#define USB_TXIE_EP7            0x00000080  // TX Endpoint 7 Interrupt Enable
+#define USB_TXIE_EP6            0x00000040  // TX Endpoint 6 Interrupt Enable
+#define USB_TXIE_EP5            0x00000020  // TX Endpoint 5 Interrupt Enable
+#define USB_TXIE_EP4            0x00000010  // TX Endpoint 4 Interrupt Enable
+#define USB_TXIE_EP3            0x00000008  // TX Endpoint 3 Interrupt Enable
+#define USB_TXIE_EP2            0x00000004  // TX Endpoint 2 Interrupt Enable
+#define USB_TXIE_EP1            0x00000002  // TX Endpoint 1 Interrupt Enable
 #define USB_TXIE_EP0            0x00000001  // TX and RX Endpoint 0 Interrupt
-                                            // Enable.
+                                            // Enable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXIE register.
 //
 //*****************************************************************************
-#define USB_RXIE_EP15           0x00008000  // RX Endpoint 15 Interrupt Enable.
-#define USB_RXIE_EP14           0x00004000  // RX Endpoint 14 Interrupt Enable.
-#define USB_RXIE_EP13           0x00002000  // RX Endpoint 13 Interrupt Enable.
-#define USB_RXIE_EP12           0x00001000  // RX Endpoint 12 Interrupt Enable.
-#define USB_RXIE_EP11           0x00000800  // RX Endpoint 11 Interrupt Enable.
-#define USB_RXIE_EP10           0x00000400  // RX Endpoint 10 Interrupt Enable.
-#define USB_RXIE_EP9            0x00000200  // RX Endpoint 9 Interrupt Enable.
-#define USB_RXIE_EP8            0x00000100  // RX Endpoint 8 Interrupt Enable.
-#define USB_RXIE_EP7            0x00000080  // RX Endpoint 7 Interrupt Enable.
-#define USB_RXIE_EP6            0x00000040  // RX Endpoint 6 Interrupt Enable.
-#define USB_RXIE_EP5            0x00000020  // RX Endpoint 5 Interrupt Enable.
-#define USB_RXIE_EP4            0x00000010  // RX Endpoint 4 Interrupt Enable.
-#define USB_RXIE_EP3            0x00000008  // RX Endpoint 3 Interrupt Enable.
-#define USB_RXIE_EP2            0x00000004  // RX Endpoint 2 Interrupt Enable.
-#define USB_RXIE_EP1            0x00000002  // RX Endpoint 1 Interrupt Enable.
+#define USB_RXIE_EP15           0x00008000  // RX Endpoint 15 Interrupt Enable
+#define USB_RXIE_EP14           0x00004000  // RX Endpoint 14 Interrupt Enable
+#define USB_RXIE_EP13           0x00002000  // RX Endpoint 13 Interrupt Enable
+#define USB_RXIE_EP12           0x00001000  // RX Endpoint 12 Interrupt Enable
+#define USB_RXIE_EP11           0x00000800  // RX Endpoint 11 Interrupt Enable
+#define USB_RXIE_EP10           0x00000400  // RX Endpoint 10 Interrupt Enable
+#define USB_RXIE_EP9            0x00000200  // RX Endpoint 9 Interrupt Enable
+#define USB_RXIE_EP8            0x00000100  // RX Endpoint 8 Interrupt Enable
+#define USB_RXIE_EP7            0x00000080  // RX Endpoint 7 Interrupt Enable
+#define USB_RXIE_EP6            0x00000040  // RX Endpoint 6 Interrupt Enable
+#define USB_RXIE_EP5            0x00000020  // RX Endpoint 5 Interrupt Enable
+#define USB_RXIE_EP4            0x00000010  // RX Endpoint 4 Interrupt Enable
+#define USB_RXIE_EP3            0x00000008  // RX Endpoint 3 Interrupt Enable
+#define USB_RXIE_EP2            0x00000004  // RX Endpoint 2 Interrupt Enable
+#define USB_RXIE_EP1            0x00000002  // RX Endpoint 1 Interrupt Enable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_IS register.
 //
 //*****************************************************************************
-#define USB_IS_VBUSERR          0x00000080  // VBus Error.
-#define USB_IS_SESREQ           0x00000040  // Session Request.
-#define USB_IS_DISCON           0x00000020  // Session Disconnect.
-#define USB_IS_CONN             0x00000010  // Session Connect.
-#define USB_IS_SOF              0x00000008  // Start of Frame.
-#define USB_IS_BABBLE           0x00000004  // Babble Detected.
-#define USB_IS_RESET            0x00000004  // Reset Signal Detected.
-#define USB_IS_RESUME           0x00000002  // Resume Signal Detected.
-#define USB_IS_SUSPEND          0x00000001  // Suspend Signal Detected.
+#define USB_IS_VBUSERR          0x00000080  // VBUS Error
+#define USB_IS_SESREQ           0x00000040  // SESSION REQUEST
+#define USB_IS_DISCON           0x00000020  // Session Disconnect
+#define USB_IS_CONN             0x00000010  // Session Connect
+#define USB_IS_SOF              0x00000008  // Start of Frame
+#define USB_IS_BABBLE           0x00000004  // Babble Detected
+#define USB_IS_RESET            0x00000004  // RESET Signaling Detected
+#define USB_IS_RESUME           0x00000002  // RESUME Signaling Detected
+#define USB_IS_SUSPEND          0x00000001  // SUSPEND Signaling Detected
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_IE register.
 //
 //*****************************************************************************
-#define USB_IE_VBUSERR          0x00000080  // Enable VBUS Error Interrupt.
+#define USB_IE_VBUSERR          0x00000080  // Enable VBUS Error Interrupt
 #define USB_IE_SESREQ           0x00000040  // Enable Session Request
-                                            // Interrupt.
-#define USB_IE_DISCON           0x00000020  // Enable Disconnect Interrupt.
-#define USB_IE_CONN             0x00000010  // Enable Connect Interrupt.
-#define USB_IE_SOF              0x00000008  // Enable Start-of-Frame Interrupt.
-#define USB_IE_BABBLE           0x00000004  // Enable Babble Interrupt.
-#define USB_IE_RESET            0x00000004  // Enable Reset Interrupt.
-#define USB_IE_RESUME           0x00000002  // Enable Resume Interrupt.
-#define USB_IE_SUSPND           0x00000001  // Enable Suspend Interrupt.
+#define USB_IE_DISCON           0x00000020  // Enable Disconnect Interrupt
+#define USB_IE_CONN             0x00000010  // Enable Connect Interrupt
+#define USB_IE_SOF              0x00000008  // Enable Start-of-Frame Interrupt
+#define USB_IE_BABBLE           0x00000004  // Enable Babble Interrupt
+#define USB_IE_RESET            0x00000004  // Enable RESET Interrupt
+#define USB_IE_RESUME           0x00000002  // Enable RESUME Interrupt
+#define USB_IE_SUSPND           0x00000001  // Enable SUSPEND Interrupt
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_FRAME register.
 //
 //*****************************************************************************
-#define USB_FRAME_M             0x000007FF  // Frame Number.
+#define USB_FRAME_M             0x000007FF  // Frame Number
 #define USB_FRAME_S             0
 
 //*****************************************************************************
@@ -785,7 +780,7 @@
 // The following are defines for the bit fields in the USB_O_EPIDX register.
 //
 //*****************************************************************************
-#define USB_EPIDX_EPIDX_M       0x0000000F  // Endpoint Index.
+#define USB_EPIDX_EPIDX_M       0x0000000F  // Endpoint Index
 #define USB_EPIDX_EPIDX_S       0
 
 //*****************************************************************************
@@ -793,16 +788,16 @@
 // The following are defines for the bit fields in the USB_O_TEST register.
 //
 //*****************************************************************************
-#define USB_TEST_FORCEH         0x00000080  // Force Host Mode.
-#define USB_TEST_FIFOACC        0x00000040  // FIFO Access.
-#define USB_TEST_FORCEFS        0x00000020  // Force Full Speed.
+#define USB_TEST_FORCEH         0x00000080  // Force Host Mode
+#define USB_TEST_FIFOACC        0x00000040  // FIFO Access
+#define USB_TEST_FORCEFS        0x00000020  // Force Full-Speed Mode
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_FIFO0 register.
 //
 //*****************************************************************************
-#define USB_FIFO0_EPDATA_M      0xFFFFFFFF  // Endpoint Data.
+#define USB_FIFO0_EPDATA_M      0xFFFFFFFF  // Endpoint Data
 #define USB_FIFO0_EPDATA_S      0
 
 //*****************************************************************************
@@ -810,7 +805,7 @@
 // The following are defines for the bit fields in the USB_O_FIFO1 register.
 //
 //*****************************************************************************
-#define USB_FIFO1_EPDATA_M      0xFFFFFFFF  // Endpoint Data.
+#define USB_FIFO1_EPDATA_M      0xFFFFFFFF  // Endpoint Data
 #define USB_FIFO1_EPDATA_S      0
 
 //*****************************************************************************
@@ -818,7 +813,7 @@
 // The following are defines for the bit fields in the USB_O_FIFO2 register.
 //
 //*****************************************************************************
-#define USB_FIFO2_EPDATA_M      0xFFFFFFFF  // Endpoint Data.
+#define USB_FIFO2_EPDATA_M      0xFFFFFFFF  // Endpoint Data
 #define USB_FIFO2_EPDATA_S      0
 
 //*****************************************************************************
@@ -826,33 +821,129 @@
 // The following are defines for the bit fields in the USB_O_FIFO3 register.
 //
 //*****************************************************************************
-#define USB_FIFO3_EPDATA_M      0xFFFFFFFF  // Endpoint Data.
+#define USB_FIFO3_EPDATA_M      0xFFFFFFFF  // Endpoint Data
 #define USB_FIFO3_EPDATA_S      0
 
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO4 register.
+//
+//*****************************************************************************
+#define USB_FIFO4_EPDATA_M      0xFFFFFFFF  // Endpoint Data
+#define USB_FIFO4_EPDATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO5 register.
+//
+//*****************************************************************************
+#define USB_FIFO5_EPDATA_M      0xFFFFFFFF  // Endpoint Data
+#define USB_FIFO5_EPDATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO6 register.
+//
+//*****************************************************************************
+#define USB_FIFO6_EPDATA_M      0xFFFFFFFF  // Endpoint Data
+#define USB_FIFO6_EPDATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO7 register.
+//
+//*****************************************************************************
+#define USB_FIFO7_EPDATA_M      0xFFFFFFFF  // Endpoint Data
+#define USB_FIFO7_EPDATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO8 register.
+//
+//*****************************************************************************
+#define USB_FIFO8_EPDATA_M      0xFFFFFFFF  // Endpoint Data
+#define USB_FIFO8_EPDATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO9 register.
+//
+//*****************************************************************************
+#define USB_FIFO9_EPDATA_M      0xFFFFFFFF  // Endpoint Data
+#define USB_FIFO9_EPDATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO10 register.
+//
+//*****************************************************************************
+#define USB_FIFO10_EPDATA_M     0xFFFFFFFF  // Endpoint Data
+#define USB_FIFO10_EPDATA_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO11 register.
+//
+//*****************************************************************************
+#define USB_FIFO11_EPDATA_M     0xFFFFFFFF  // Endpoint Data
+#define USB_FIFO11_EPDATA_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO12 register.
+//
+//*****************************************************************************
+#define USB_FIFO12_EPDATA_M     0xFFFFFFFF  // Endpoint Data
+#define USB_FIFO12_EPDATA_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO13 register.
+//
+//*****************************************************************************
+#define USB_FIFO13_EPDATA_M     0xFFFFFFFF  // Endpoint Data
+#define USB_FIFO13_EPDATA_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO14 register.
+//
+//*****************************************************************************
+#define USB_FIFO14_EPDATA_M     0xFFFFFFFF  // Endpoint Data
+#define USB_FIFO14_EPDATA_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO15 register.
+//
+//*****************************************************************************
+#define USB_FIFO15_EPDATA_M     0xFFFFFFFF  // Endpoint Data
+#define USB_FIFO15_EPDATA_S     0
+
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_DEVCTL register.
 //
 //*****************************************************************************
-#define USB_DEVCTL_DEV          0x00000080  // Device Mode.
-#define USB_DEVCTL_FSDEV        0x00000040  // Full-Speed Device Detected.
-#define USB_DEVCTL_LSDEV        0x00000020  // Low-Speed Device Detected.
-#define USB_DEVCTL_VBUS_M       0x00000018  // VBus Level.
+#define USB_DEVCTL_DEV          0x00000080  // Device Mode
+#define USB_DEVCTL_FSDEV        0x00000040  // Full-Speed Device Detected
+#define USB_DEVCTL_LSDEV        0x00000020  // Low-Speed Device Detected
+#define USB_DEVCTL_VBUS_M       0x00000018  // VBUS Level
 #define USB_DEVCTL_VBUS_NONE    0x00000000  // Below SessionEnd
 #define USB_DEVCTL_VBUS_SEND    0x00000008  // Above SessionEnd, below AValid
-#define USB_DEVCTL_VBUS_AVALID  0x00000010  // Above AValid, below VBusValid
-#define USB_DEVCTL_VBUS_VALID   0x00000018  // Above VBusValid
-#define USB_DEVCTL_HOST         0x00000004  // Host Mode.
-#define USB_DEVCTL_HOSTREQ      0x00000002  // Host Request.
-#define USB_DEVCTL_SESSION      0x00000001  // Session Start/End.
+#define USB_DEVCTL_VBUS_AVALID  0x00000010  // Above AValid, below VBUSValid
+#define USB_DEVCTL_VBUS_VALID   0x00000018  // Above VBUSValid
+#define USB_DEVCTL_HOST         0x00000004  // Host Mode
+#define USB_DEVCTL_HOSTREQ      0x00000002  // Host Request
+#define USB_DEVCTL_SESSION      0x00000001  // Session Start/End
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_TXFIFOSZ register.
 //
 //*****************************************************************************
-#define USB_TXFIFOSZ_DPB        0x00000010  // Double Packet Buffer Support.
-#define USB_TXFIFOSZ_SIZE_M     0x0000000F  // Max Packet Size.
+#define USB_TXFIFOSZ_DPB        0x00000010  // Double Packet Buffer Support
+#define USB_TXFIFOSZ_SIZE_M     0x0000000F  // Max Packet Size
 #define USB_TXFIFOSZ_SIZE_8     0x00000000  // 8
 #define USB_TXFIFOSZ_SIZE_16    0x00000001  // 16
 #define USB_TXFIFOSZ_SIZE_32    0x00000002  // 32
@@ -868,8 +959,8 @@
 // The following are defines for the bit fields in the USB_O_RXFIFOSZ register.
 //
 //*****************************************************************************
-#define USB_RXFIFOSZ_DPB        0x00000010  // Double Packet Buffer Support.
-#define USB_RXFIFOSZ_SIZE_M     0x0000000F  // Max Packet Size.
+#define USB_RXFIFOSZ_DPB        0x00000010  // Double Packet Buffer Support
+#define USB_RXFIFOSZ_SIZE_M     0x0000000F  // Max Packet Size
 #define USB_RXFIFOSZ_SIZE_8     0x00000000  // 8
 #define USB_RXFIFOSZ_SIZE_16    0x00000001  // 16
 #define USB_RXFIFOSZ_SIZE_32    0x00000002  // 32
@@ -886,17 +977,8 @@
 // register.
 //
 //*****************************************************************************
-#define USB_TXFIFOADD_ADDR_M    0x00001FFF  // Transmit/Receive Start Address.
-#define USB_TXFIFOADD_ADDR_0    0x00000000  // 0
-#define USB_TXFIFOADD_ADDR_8    0x00000001  // 8
-#define USB_TXFIFOADD_ADDR_16   0x00000002  // 16
-#define USB_TXFIFOADD_ADDR_32   0x00000003  // 32
-#define USB_TXFIFOADD_ADDR_64   0x00000004  // 64
-#define USB_TXFIFOADD_ADDR_128  0x00000005  // 128
-#define USB_TXFIFOADD_ADDR_256  0x00000006  // 256
-#define USB_TXFIFOADD_ADDR_512  0x00000007  // 512
-#define USB_TXFIFOADD_ADDR_1024 0x00000008  // 1024
-#define USB_TXFIFOADD_ADDR_2048 0x00000009  // 2048
+#define USB_TXFIFOADD_ADDR_M    0x000001FF  // Transmit/Receive Start Address
+#define USB_TXFIFOADD_ADDR_S    0
 
 //*****************************************************************************
 //
@@ -904,34 +986,33 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RXFIFOADD_ADDR_M    0x00001FFF  // Transmit/Receive Start Address.
-#define USB_RXFIFOADD_ADDR_0    0x00000000  // 0
-#define USB_RXFIFOADD_ADDR_8    0x00000001  // 8
-#define USB_RXFIFOADD_ADDR_16   0x00000002  // 16
-#define USB_RXFIFOADD_ADDR_32   0x00000003  // 32
-#define USB_RXFIFOADD_ADDR_64   0x00000004  // 64
-#define USB_RXFIFOADD_ADDR_128  0x00000005  // 128
-#define USB_RXFIFOADD_ADDR_256  0x00000006  // 256
-#define USB_RXFIFOADD_ADDR_512  0x00000007  // 512
-#define USB_RXFIFOADD_ADDR_1024 0x00000008  // 1024
-#define USB_RXFIFOADD_ADDR_2048 0x00000009  // 2048
+#define USB_RXFIFOADD_ADDR_M    0x000001FF  // Transmit/Receive Start Address
+#define USB_RXFIFOADD_ADDR_S    0
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_CONTIM register.
 //
 //*****************************************************************************
-#define USB_CONTIM_WTCON_M      0x000000F0  // Connect Wait.
-#define USB_CONTIM_WTID_M       0x0000000F  // Wait ID.
+#define USB_CONTIM_WTCON_M      0x000000F0  // Connect Wait
+#define USB_CONTIM_WTID_M       0x0000000F  // Wait ID
 #define USB_CONTIM_WTCON_S      4
 #define USB_CONTIM_WTID_S       0
 
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VPLEN register.
+//
+//*****************************************************************************
+#define USB_VPLEN_VPLEN_M       0x000000FF  // VBUS Pulse Length
+#define USB_VPLEN_VPLEN_S       0
+
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_FSEOF register.
 //
 //*****************************************************************************
-#define USB_FSEOF_FSEOFG_M      0x000000FF  // Full-Speed End-of-Frame Gap.
+#define USB_FSEOF_FSEOFG_M      0x000000FF  // Full-Speed End-of-Frame Gap
 #define USB_FSEOF_FSEOFG_S      0
 
 //*****************************************************************************
@@ -939,7 +1020,7 @@
 // The following are defines for the bit fields in the USB_O_LSEOF register.
 //
 //*****************************************************************************
-#define USB_LSEOF_LSEOFG_M      0x000000FF  // Low-Speed End-of-Frame Gap.
+#define USB_LSEOF_LSEOFG_M      0x000000FF  // Low-Speed End-of-Frame Gap
 #define USB_LSEOF_LSEOFG_S      0
 
 //*****************************************************************************
@@ -948,7 +1029,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_TXFUNCADDR0_ADDR_M  0x0000007F  // Device Address.
+#define USB_TXFUNCADDR0_ADDR_M  0x0000007F  // Device Address
 #define USB_TXFUNCADDR0_ADDR_S  0
 
 //*****************************************************************************
@@ -957,8 +1038,8 @@
 // register.
 //
 //*****************************************************************************
-#define USB_TXHUBADDR0_MULTTRAN 0x00000080  // Multiple Translators.
-#define USB_TXHUBADDR0_ADDR_M   0x0000007F  // Hub Address.
+#define USB_TXHUBADDR0_MULTTRAN 0x00000080  // Multiple Translators
+#define USB_TXHUBADDR0_ADDR_M   0x0000007F  // Hub Address
 #define USB_TXHUBADDR0_ADDR_S   0
 
 //*****************************************************************************
@@ -967,7 +1048,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_TXHUBPORT0_PORT_M   0x0000007F  // Hub Port.
+#define USB_TXHUBPORT0_PORT_M   0x0000007F  // Hub Port
 #define USB_TXHUBPORT0_PORT_S   0
 
 //*****************************************************************************
@@ -976,7 +1057,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_TXFUNCADDR1_ADDR_M  0x0000007F  // Device Address.
+#define USB_TXFUNCADDR1_ADDR_M  0x0000007F  // Device Address
 #define USB_TXFUNCADDR1_ADDR_S  0
 
 //*****************************************************************************
@@ -985,8 +1066,8 @@
 // register.
 //
 //*****************************************************************************
-#define USB_TXHUBADDR1_MULTTRAN 0x00000080  // Multiple Translators.
-#define USB_TXHUBADDR1_ADDR_M   0x0000007F  // Hub Address.
+#define USB_TXHUBADDR1_MULTTRAN 0x00000080  // Multiple Translators
+#define USB_TXHUBADDR1_ADDR_M   0x0000007F  // Hub Address
 #define USB_TXHUBADDR1_ADDR_S   0
 
 //*****************************************************************************
@@ -995,7 +1076,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_TXHUBPORT1_PORT_M   0x0000007F  // Hub Port.
+#define USB_TXHUBPORT1_PORT_M   0x0000007F  // Hub Port
 #define USB_TXHUBPORT1_PORT_S   0
 
 //*****************************************************************************
@@ -1004,7 +1085,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RXFUNCADDR1_ADDR_M  0x0000007F  // Device Address.
+#define USB_RXFUNCADDR1_ADDR_M  0x0000007F  // Device Address
 #define USB_RXFUNCADDR1_ADDR_S  0
 
 //*****************************************************************************
@@ -1013,8 +1094,8 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RXHUBADDR1_MULTTRAN 0x00000080  // Multiple Translators.
-#define USB_RXHUBADDR1_ADDR_M   0x0000007F  // Hub Address.
+#define USB_RXHUBADDR1_MULTTRAN 0x00000080  // Multiple Translators
+#define USB_RXHUBADDR1_ADDR_M   0x0000007F  // Hub Address
 #define USB_RXHUBADDR1_ADDR_S   0
 
 //*****************************************************************************
@@ -1023,7 +1104,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RXHUBPORT1_PORT_M   0x0000007F  // Hub Port.
+#define USB_RXHUBPORT1_PORT_M   0x0000007F  // Hub Port
 #define USB_RXHUBPORT1_PORT_S   0
 
 //*****************************************************************************
@@ -1032,7 +1113,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_TXFUNCADDR2_ADDR_M  0x0000007F  // Device Address.
+#define USB_TXFUNCADDR2_ADDR_M  0x0000007F  // Device Address
 #define USB_TXFUNCADDR2_ADDR_S  0
 
 //*****************************************************************************
@@ -1041,8 +1122,8 @@
 // register.
 //
 //*****************************************************************************
-#define USB_TXHUBADDR2_MULTTRAN 0x00000080  // Multiple Translators.
-#define USB_TXHUBADDR2_ADDR_M   0x0000007F  // Hub Address.
+#define USB_TXHUBADDR2_MULTTRAN 0x00000080  // Multiple Translators
+#define USB_TXHUBADDR2_ADDR_M   0x0000007F  // Hub Address
 #define USB_TXHUBADDR2_ADDR_S   0
 
 //*****************************************************************************
@@ -1051,7 +1132,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_TXHUBPORT2_PORT_M   0x0000007F  // Hub Port.
+#define USB_TXHUBPORT2_PORT_M   0x0000007F  // Hub Port
 #define USB_TXHUBPORT2_PORT_S   0
 
 //*****************************************************************************
@@ -1060,7 +1141,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RXFUNCADDR2_ADDR_M  0x0000007F  // Device Address.
+#define USB_RXFUNCADDR2_ADDR_M  0x0000007F  // Device Address
 #define USB_RXFUNCADDR2_ADDR_S  0
 
 //*****************************************************************************
@@ -1069,8 +1150,8 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RXHUBADDR2_MULTTRAN 0x00000080  // Multiple Translators.
-#define USB_RXHUBADDR2_ADDR_M   0x0000007F  // Hub Address.
+#define USB_RXHUBADDR2_MULTTRAN 0x00000080  // Multiple Translators
+#define USB_RXHUBADDR2_ADDR_M   0x0000007F  // Hub Address
 #define USB_RXHUBADDR2_ADDR_S   0
 
 //*****************************************************************************
@@ -1079,7 +1160,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RXHUBPORT2_PORT_M   0x0000007F  // Hub Port.
+#define USB_RXHUBPORT2_PORT_M   0x0000007F  // Hub Port
 #define USB_RXHUBPORT2_PORT_S   0
 
 //*****************************************************************************
@@ -1088,7 +1169,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_TXFUNCADDR3_ADDR_M  0x0000007F  // Device Address.
+#define USB_TXFUNCADDR3_ADDR_M  0x0000007F  // Device Address
 #define USB_TXFUNCADDR3_ADDR_S  0
 
 //*****************************************************************************
@@ -1097,8 +1178,8 @@
 // register.
 //
 //*****************************************************************************
-#define USB_TXHUBADDR3_MULTTRAN 0x00000080  // Multiple Translators.
-#define USB_TXHUBADDR3_ADDR_M   0x0000007F  // Hub Address.
+#define USB_TXHUBADDR3_MULTTRAN 0x00000080  // Multiple Translators
+#define USB_TXHUBADDR3_ADDR_M   0x0000007F  // Hub Address
 #define USB_TXHUBADDR3_ADDR_S   0
 
 //*****************************************************************************
@@ -1107,7 +1188,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_TXHUBPORT3_PORT_M   0x0000007F  // Hub Port.
+#define USB_TXHUBPORT3_PORT_M   0x0000007F  // Hub Port
 #define USB_TXHUBPORT3_PORT_S   0
 
 //*****************************************************************************
@@ -1116,7 +1197,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RXFUNCADDR3_ADDR_M  0x0000007F  // Device Address.
+#define USB_RXFUNCADDR3_ADDR_M  0x0000007F  // Device Address
 #define USB_RXFUNCADDR3_ADDR_S  0
 
 //*****************************************************************************
@@ -1125,8 +1206,8 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RXHUBADDR3_MULTTRAN 0x00000080  // Multiple Translators.
-#define USB_RXHUBADDR3_ADDR_M   0x0000007F  // Hub Address.
+#define USB_RXHUBADDR3_MULTTRAN 0x00000080  // Multiple Translators
+#define USB_RXHUBADDR3_ADDR_M   0x0000007F  // Hub Address
 #define USB_RXHUBADDR3_ADDR_S   0
 
 //*****************************************************************************
@@ -1135,43 +1216,727 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RXHUBPORT3_PORT_M   0x0000007F  // Hub Port.
+#define USB_RXHUBPORT3_PORT_M   0x0000007F  // Hub Port
 #define USB_RXHUBPORT3_PORT_S   0
 
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR4
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR4_ADDR_M  0x0000007F  // Device Address
+#define USB_TXFUNCADDR4_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR4
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR4_MULTTRAN 0x00000080  // Multiple Translators
+#define USB_TXHUBADDR4_ADDR_M   0x0000007F  // Hub Address
+#define USB_TXHUBADDR4_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT4
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT4_PORT_M   0x0000007F  // Hub Port
+#define USB_TXHUBPORT4_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR4
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR4_ADDR_M  0x0000007F  // Device Address
+#define USB_RXFUNCADDR4_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR4
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR4_MULTTRAN 0x00000080  // Multiple Translators
+#define USB_RXHUBADDR4_ADDR_M   0x0000007F  // Hub Address
+#define USB_RXHUBADDR4_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT4
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT4_PORT_M   0x0000007F  // Hub Port
+#define USB_RXHUBPORT4_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR5
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR5_ADDR_M  0x0000007F  // Device Address
+#define USB_TXFUNCADDR5_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR5
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR5_MULTTRAN 0x00000080  // Multiple Translators
+#define USB_TXHUBADDR5_ADDR_M   0x0000007F  // Hub Address
+#define USB_TXHUBADDR5_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT5
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT5_PORT_M   0x0000007F  // Hub Port
+#define USB_TXHUBPORT5_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR5
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR5_ADDR_M  0x0000007F  // Device Address
+#define USB_RXFUNCADDR5_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR5
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR5_MULTTRAN 0x00000080  // Multiple Translators
+#define USB_RXHUBADDR5_ADDR_M   0x0000007F  // Hub Address
+#define USB_RXHUBADDR5_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT5
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT5_PORT_M   0x0000007F  // Hub Port
+#define USB_RXHUBPORT5_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR6
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR6_ADDR_M  0x0000007F  // Device Address
+#define USB_TXFUNCADDR6_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR6
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR6_MULTTRAN 0x00000080  // Multiple Translators
+#define USB_TXHUBADDR6_ADDR_M   0x0000007F  // Hub Address
+#define USB_TXHUBADDR6_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT6
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT6_PORT_M   0x0000007F  // Hub Port
+#define USB_TXHUBPORT6_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR6
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR6_ADDR_M  0x0000007F  // Device Address
+#define USB_RXFUNCADDR6_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR6
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR6_MULTTRAN 0x00000080  // Multiple Translators
+#define USB_RXHUBADDR6_ADDR_M   0x0000007F  // Hub Address
+#define USB_RXHUBADDR6_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT6
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT6_PORT_M   0x0000007F  // Hub Port
+#define USB_RXHUBPORT6_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR7
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR7_ADDR_M  0x0000007F  // Device Address
+#define USB_TXFUNCADDR7_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR7
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR7_MULTTRAN 0x00000080  // Multiple Translators
+#define USB_TXHUBADDR7_ADDR_M   0x0000007F  // Hub Address
+#define USB_TXHUBADDR7_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT7
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT7_PORT_M   0x0000007F  // Hub Port
+#define USB_TXHUBPORT7_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR7
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR7_ADDR_M  0x0000007F  // Device Address
+#define USB_RXFUNCADDR7_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR7
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR7_MULTTRAN 0x00000080  // Multiple Translators
+#define USB_RXHUBADDR7_ADDR_M   0x0000007F  // Hub Address
+#define USB_RXHUBADDR7_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT7
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT7_PORT_M   0x0000007F  // Hub Port
+#define USB_RXHUBPORT7_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR8
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR8_ADDR_M  0x0000007F  // Device Address
+#define USB_TXFUNCADDR8_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR8
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR8_MULTTRAN 0x00000080  // Multiple Translators
+#define USB_TXHUBADDR8_ADDR_M   0x0000007F  // Hub Address
+#define USB_TXHUBADDR8_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT8
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT8_PORT_M   0x0000007F  // Hub Port
+#define USB_TXHUBPORT8_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR8
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR8_ADDR_M  0x0000007F  // Device Address
+#define USB_RXFUNCADDR8_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR8
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR8_MULTTRAN 0x00000080  // Multiple Translators
+#define USB_RXHUBADDR8_ADDR_M   0x0000007F  // Hub Address
+#define USB_RXHUBADDR8_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT8
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT8_PORT_M   0x0000007F  // Hub Port
+#define USB_RXHUBPORT8_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR9
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR9_ADDR_M  0x0000007F  // Device Address
+#define USB_TXFUNCADDR9_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR9
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR9_MULTTRAN 0x00000080  // Multiple Translators
+#define USB_TXHUBADDR9_ADDR_M   0x0000007F  // Hub Address
+#define USB_TXHUBADDR9_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT9
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT9_PORT_M   0x0000007F  // Hub Port
+#define USB_TXHUBPORT9_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR9
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR9_ADDR_M  0x0000007F  // Device Address
+#define USB_RXFUNCADDR9_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR9
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR9_MULTTRAN 0x00000080  // Multiple Translators
+#define USB_RXHUBADDR9_ADDR_M   0x0000007F  // Hub Address
+#define USB_RXHUBADDR9_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT9
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT9_PORT_M   0x0000007F  // Hub Port
+#define USB_RXHUBPORT9_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR10
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR10_ADDR_M 0x0000007F  // Device Address
+#define USB_TXFUNCADDR10_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR10
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR10_MULTTRAN \
+                                0x00000080  // Multiple Translators
+#define USB_TXHUBADDR10_ADDR_M  0x0000007F  // Hub Address
+#define USB_TXHUBADDR10_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT10
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT10_PORT_M  0x0000007F  // Hub Port
+#define USB_TXHUBPORT10_PORT_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR10
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR10_ADDR_M 0x0000007F  // Device Address
+#define USB_RXFUNCADDR10_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR10
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR10_MULTTRAN \
+                                0x00000080  // Multiple Translators
+#define USB_RXHUBADDR10_ADDR_M  0x0000007F  // Hub Address
+#define USB_RXHUBADDR10_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT10
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT10_PORT_M  0x0000007F  // Hub Port
+#define USB_RXHUBPORT10_PORT_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR11
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR11_ADDR_M 0x0000007F  // Device Address
+#define USB_TXFUNCADDR11_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR11
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR11_MULTTRAN \
+                                0x00000080  // Multiple Translators
+#define USB_TXHUBADDR11_ADDR_M  0x0000007F  // Hub Address
+#define USB_TXHUBADDR11_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT11
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT11_PORT_M  0x0000007F  // Hub Port
+#define USB_TXHUBPORT11_PORT_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR11
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR11_ADDR_M 0x0000007F  // Device Address
+#define USB_RXFUNCADDR11_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR11
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR11_MULTTRAN \
+                                0x00000080  // Multiple Translators
+#define USB_RXHUBADDR11_ADDR_M  0x0000007F  // Hub Address
+#define USB_RXHUBADDR11_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT11
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT11_PORT_M  0x0000007F  // Hub Port
+#define USB_RXHUBPORT11_PORT_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR12
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR12_ADDR_M 0x0000007F  // Device Address
+#define USB_TXFUNCADDR12_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR12
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR12_MULTTRAN \
+                                0x00000080  // Multiple Translators
+#define USB_TXHUBADDR12_ADDR_M  0x0000007F  // Hub Address
+#define USB_TXHUBADDR12_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT12
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT12_PORT_M  0x0000007F  // Hub Port
+#define USB_TXHUBPORT12_PORT_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR12
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR12_ADDR_M 0x0000007F  // Device Address
+#define USB_RXFUNCADDR12_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR12
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR12_MULTTRAN \
+                                0x00000080  // Multiple Translators
+#define USB_RXHUBADDR12_ADDR_M  0x0000007F  // Hub Address
+#define USB_RXHUBADDR12_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT12
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT12_PORT_M  0x0000007F  // Hub Port
+#define USB_RXHUBPORT12_PORT_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR13
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR13_ADDR_M 0x0000007F  // Device Address
+#define USB_TXFUNCADDR13_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR13
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR13_MULTTRAN \
+                                0x00000080  // Multiple Translators
+#define USB_TXHUBADDR13_ADDR_M  0x0000007F  // Hub Address
+#define USB_TXHUBADDR13_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT13
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT13_PORT_M  0x0000007F  // Hub Port
+#define USB_TXHUBPORT13_PORT_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR13
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR13_ADDR_M 0x0000007F  // Device Address
+#define USB_RXFUNCADDR13_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR13
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR13_MULTTRAN \
+                                0x00000080  // Multiple Translators
+#define USB_RXHUBADDR13_ADDR_M  0x0000007F  // Hub Address
+#define USB_RXHUBADDR13_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT13
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT13_PORT_M  0x0000007F  // Hub Port
+#define USB_RXHUBPORT13_PORT_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR14
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR14_ADDR_M 0x0000007F  // Device Address
+#define USB_TXFUNCADDR14_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR14
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR14_MULTTRAN \
+                                0x00000080  // Multiple Translators
+#define USB_TXHUBADDR14_ADDR_M  0x0000007F  // Hub Address
+#define USB_TXHUBADDR14_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT14
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT14_PORT_M  0x0000007F  // Hub Port
+#define USB_TXHUBPORT14_PORT_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR14
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR14_ADDR_M 0x0000007F  // Device Address
+#define USB_RXFUNCADDR14_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR14
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR14_MULTTRAN \
+                                0x00000080  // Multiple Translators
+#define USB_RXHUBADDR14_ADDR_M  0x0000007F  // Hub Address
+#define USB_RXHUBADDR14_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT14
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT14_PORT_M  0x0000007F  // Hub Port
+#define USB_RXHUBPORT14_PORT_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR15
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR15_ADDR_M 0x0000007F  // Device Address
+#define USB_TXFUNCADDR15_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR15
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR15_MULTTRAN \
+                                0x00000080  // Multiple Translators
+#define USB_TXHUBADDR15_ADDR_M  0x0000007F  // Hub Address
+#define USB_TXHUBADDR15_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT15
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT15_PORT_M  0x0000007F  // Hub Port
+#define USB_TXHUBPORT15_PORT_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR15
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR15_ADDR_M 0x0000007F  // Device Address
+#define USB_RXFUNCADDR15_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR15
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR15_MULTTRAN \
+                                0x00000080  // Multiple Translators
+#define USB_RXHUBADDR15_ADDR_M  0x0000007F  // Hub Address
+#define USB_RXHUBADDR15_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT15
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT15_PORT_M  0x0000007F  // Hub Port
+#define USB_RXHUBPORT15_PORT_S  0
+
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_CSRL0 register.
 //
 //*****************************************************************************
-#define USB_CSRL0_NAKTO         0x00000080  // NAK Timeout.
-#define USB_CSRL0_SETENDC       0x00000080  // Setup End Clear.
-#define USB_CSRL0_STATUS        0x00000040  // Status Packet.
-#define USB_CSRL0_RXRDYC        0x00000040  // RXRDY Clear.
-#define USB_CSRL0_REQPKT        0x00000020  // Request Packet.
-#define USB_CSRL0_STALL         0x00000020  // Send Stall.
-#define USB_CSRL0_SETEND        0x00000010  // Setup End.
-#define USB_CSRL0_ERROR         0x00000010  // Error.
-#define USB_CSRL0_DATAEND       0x00000008  // Data End.
-#define USB_CSRL0_SETUP         0x00000008  // Setup Packet.
-#define USB_CSRL0_STALLED       0x00000004  // Endpoint Stalled.
-#define USB_CSRL0_TXRDY         0x00000002  // Transmit Packet Ready.
-#define USB_CSRL0_RXRDY         0x00000001  // Receive Packet Ready.
+#define USB_CSRL0_NAKTO         0x00000080  // NAK Timeout
+#define USB_CSRL0_SETENDC       0x00000080  // Setup End Clear
+#define USB_CSRL0_STATUS        0x00000040  // STATUS Packet
+#define USB_CSRL0_RXRDYC        0x00000040  // RXRDY Clear
+#define USB_CSRL0_REQPKT        0x00000020  // Request Packet
+#define USB_CSRL0_STALL         0x00000020  // Send Stall
+#define USB_CSRL0_SETEND        0x00000010  // Setup End
+#define USB_CSRL0_ERROR         0x00000010  // Error
+#define USB_CSRL0_DATAEND       0x00000008  // Data End
+#define USB_CSRL0_SETUP         0x00000008  // Setup Packet
+#define USB_CSRL0_STALLED       0x00000004  // Endpoint Stalled
+#define USB_CSRL0_TXRDY         0x00000002  // Transmit Packet Ready
+#define USB_CSRL0_RXRDY         0x00000001  // Receive Packet Ready
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_CSRH0 register.
 //
 //*****************************************************************************
-#define USB_CSRH0_DTWE          0x00000004  // Data Toggle Write Enable.
-#define USB_CSRH0_DT            0x00000002  // Data Toggle.
-#define USB_CSRH0_FLUSH         0x00000001  // Flush FIFO.
+#define USB_CSRH0_DTWE          0x00000004  // Data Toggle Write Enable
+#define USB_CSRH0_DT            0x00000002  // Data Toggle
+#define USB_CSRH0_FLUSH         0x00000001  // Flush FIFO
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_COUNT0 register.
 //
 //*****************************************************************************
-#define USB_COUNT0_COUNT_M      0x0000007F  // Count.
+#define USB_COUNT0_COUNT_M      0x0000007F  // FIFO Count
 #define USB_COUNT0_COUNT_S      0
 
 //*****************************************************************************
@@ -1179,7 +1944,7 @@
 // The following are defines for the bit fields in the USB_O_TYPE0 register.
 //
 //*****************************************************************************
-#define USB_TYPE0_SPEED_M       0x000000C0  // Operating Speed.
+#define USB_TYPE0_SPEED_M       0x000000C0  // Operating Speed
 #define USB_TYPE0_SPEED_FULL    0x00000080  // Full
 #define USB_TYPE0_SPEED_LOW     0x000000C0  // Low
 
@@ -1188,7 +1953,7 @@
 // The following are defines for the bit fields in the USB_O_NAKLMT register.
 //
 //*****************************************************************************
-#define USB_NAKLMT_NAKLMT_M     0x0000001F  // EP0 NAK Limit.
+#define USB_NAKLMT_NAKLMT_M     0x0000001F  // EP0 NAK Limit
 #define USB_NAKLMT_NAKLMT_S     0
 
 //*****************************************************************************
@@ -1196,9 +1961,7 @@
 // The following are defines for the bit fields in the USB_O_TXMAXP1 register.
 //
 //*****************************************************************************
-#define USB_TXMAXP1_MULT_M      0x0000F800  // Multiplier.
-#define USB_TXMAXP1_MAXLOAD_M   0x000007FF  // Maximum Payload.
-#define USB_TXMAXP1_MULT_S      11
+#define USB_TXMAXP1_MAXLOAD_M   0x000007FF  // Maximum Payload
 #define USB_TXMAXP1_MAXLOAD_S   0
 
 //*****************************************************************************
@@ -1207,39 +1970,36 @@
 //
 //*****************************************************************************
 #define USB_TXCSRL1_NAKTO       0x00000080  // NAK Timeout
-#define USB_TXCSRL1_INCTX       0x00000080  // Incomplete Transmit.
-#define USB_TXCSRL1_CLRDT       0x00000040  // Clear Data Toggle.
-#define USB_TXCSRL1_STALLED     0x00000020  // Endpoint Stalled.
-#define USB_TXCSRL1_STALL       0x00000010  // Send Stall.
-#define USB_TXCSRL1_SETUP       0x00000010  // Setup Packet.
-#define USB_TXCSRL1_FLUSH       0x00000008  // Flush FIFO.
-#define USB_TXCSRL1_ERROR       0x00000004  // Error.
-#define USB_TXCSRL1_UNDRN       0x00000004  // Underrun.
-#define USB_TXCSRL1_FIFONE      0x00000002  // FIFO Not Empty.
-#define USB_TXCSRL1_TXRDY       0x00000001  // Transmit Packet Ready.
+#define USB_TXCSRL1_CLRDT       0x00000040  // Clear Data Toggle
+#define USB_TXCSRL1_STALLED     0x00000020  // Endpoint Stalled
+#define USB_TXCSRL1_STALL       0x00000010  // Send STALL
+#define USB_TXCSRL1_SETUP       0x00000010  // Setup Packet
+#define USB_TXCSRL1_FLUSH       0x00000008  // Flush FIFO
+#define USB_TXCSRL1_ERROR       0x00000004  // Error
+#define USB_TXCSRL1_UNDRN       0x00000004  // Underrun
+#define USB_TXCSRL1_FIFONE      0x00000002  // FIFO Not Empty
+#define USB_TXCSRL1_TXRDY       0x00000001  // Transmit Packet Ready
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_TXCSRH1 register.
 //
 //*****************************************************************************
-#define USB_TXCSRH1_AUTOSET     0x00000080  // Auto Set.
-#define USB_TXCSRH1_ISO         0x00000040  // ISO.
-#define USB_TXCSRH1_MODE        0x00000020  // Mode.
-#define USB_TXCSRH1_DMAEN       0x00000010  // DMA Request Enable.
-#define USB_TXCSRH1_FDT         0x00000008  // Force Data Toggle.
-#define USB_TXCSRH1_DMAMOD      0x00000004  // DMA Request Mode.
-#define USB_TXCSRH1_DTWE        0x00000002  // Data Toggle Write Enable.
-#define USB_TXCSRH1_DT          0x00000001  // Data Toggle.
+#define USB_TXCSRH1_AUTOSET     0x00000080  // Auto Set
+#define USB_TXCSRH1_ISO         0x00000040  // Isochronous Transfers
+#define USB_TXCSRH1_MODE        0x00000020  // Mode
+#define USB_TXCSRH1_DMAEN       0x00000010  // DMA Request Enable
+#define USB_TXCSRH1_FDT         0x00000008  // Force Data Toggle
+#define USB_TXCSRH1_DMAMOD      0x00000004  // DMA Request Mode
+#define USB_TXCSRH1_DTWE        0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH1_DT          0x00000001  // Data Toggle
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXMAXP1 register.
 //
 //*****************************************************************************
-#define USB_RXMAXP1_MULT_M      0x0000F800  // Multiplier.
-#define USB_RXMAXP1_MAXLOAD_M   0x000007FF  // Maximum Payload.
-#define USB_RXMAXP1_MULT_S      11
+#define USB_RXMAXP1_MAXLOAD_M   0x000007FF  // Maximum Payload
 #define USB_RXMAXP1_MAXLOAD_S   0
 
 //*****************************************************************************
@@ -1247,40 +2007,39 @@
 // The following are defines for the bit fields in the USB_O_RXCSRL1 register.
 //
 //*****************************************************************************
-#define USB_RXCSRL1_CLRDT       0x00000080  // Clear Data Toggle.
-#define USB_RXCSRL1_STALLED     0x00000040  // Endpoint Stalled.
-#define USB_RXCSRL1_STALL       0x00000020  // Send Stall.
-#define USB_RXCSRL1_REQPKT      0x00000020  // Request Packet.
-#define USB_RXCSRL1_FLUSH       0x00000010  // Flush FIFO.
-#define USB_RXCSRL1_DATAERR     0x00000008  // Data Error.
-#define USB_RXCSRL1_NAKTO       0x00000008  // NAK Timeout.
-#define USB_RXCSRL1_OVER        0x00000004  // Overrun.
-#define USB_RXCSRL1_ERROR       0x00000004  // Error.
-#define USB_RXCSRL1_FULL        0x00000002  // FIFO Full.
-#define USB_RXCSRL1_RXRDY       0x00000001  // Receive Packet Ready.
+#define USB_RXCSRL1_CLRDT       0x00000080  // Clear Data Toggle
+#define USB_RXCSRL1_STALLED     0x00000040  // Endpoint Stalled
+#define USB_RXCSRL1_STALL       0x00000020  // Send STALL
+#define USB_RXCSRL1_REQPKT      0x00000020  // Request Packet
+#define USB_RXCSRL1_FLUSH       0x00000010  // Flush FIFO
+#define USB_RXCSRL1_DATAERR     0x00000008  // Data Error
+#define USB_RXCSRL1_NAKTO       0x00000008  // NAK Timeout
+#define USB_RXCSRL1_OVER        0x00000004  // Overrun
+#define USB_RXCSRL1_ERROR       0x00000004  // Error
+#define USB_RXCSRL1_FULL        0x00000002  // FIFO Full
+#define USB_RXCSRL1_RXRDY       0x00000001  // Receive Packet Ready
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXCSRH1 register.
 //
 //*****************************************************************************
-#define USB_RXCSRH1_AUTOCL      0x00000080  // Auto Clear.
-#define USB_RXCSRH1_AUTORQ      0x00000040  // Auto Request.
-#define USB_RXCSRH1_ISO         0x00000040  // ISO.
-#define USB_RXCSRH1_DMAEN       0x00000020  // DMA Request Enable.
+#define USB_RXCSRH1_AUTOCL      0x00000080  // Auto Clear
+#define USB_RXCSRH1_AUTORQ      0x00000040  // Auto Request
+#define USB_RXCSRH1_ISO         0x00000040  // Isochronous Transfers
+#define USB_RXCSRH1_DMAEN       0x00000020  // DMA Request Enable
 #define USB_RXCSRH1_DISNYET     0x00000010  // Disable NYET
-#define USB_RXCSRH1_PIDERR      0x00000010  // PID Error.
-#define USB_RXCSRH1_DMAMOD      0x00000008  // DMA Request Mode.
-#define USB_RXCSRH1_DTWE        0x00000004  // Data Toggle Write Enable.
-#define USB_RXCSRH1_DT          0x00000002  // Data Toggle.
-#define USB_RXCSRH1_INCRX       0x00000001  // Incomplete Receive.
+#define USB_RXCSRH1_PIDERR      0x00000010  // PID Error
+#define USB_RXCSRH1_DMAMOD      0x00000008  // DMA Request Mode
+#define USB_RXCSRH1_DTWE        0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH1_DT          0x00000002  // Data Toggle
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXCOUNT1 register.
 //
 //*****************************************************************************
-#define USB_RXCOUNT1_COUNT_M    0x00001FFF  // Receive Packet Count.
+#define USB_RXCOUNT1_COUNT_M    0x00001FFF  // Receive Packet Count
 #define USB_RXCOUNT1_COUNT_S    0
 
 //*****************************************************************************
@@ -1288,16 +2047,16 @@
 // The following are defines for the bit fields in the USB_O_TXTYPE1 register.
 //
 //*****************************************************************************
-#define USB_TXTYPE1_SPEED_M     0x000000C0  // Operating Speed.
+#define USB_TXTYPE1_SPEED_M     0x000000C0  // Operating Speed
 #define USB_TXTYPE1_SPEED_DFLT  0x00000000  // Default
 #define USB_TXTYPE1_SPEED_FULL  0x00000080  // Full
 #define USB_TXTYPE1_SPEED_LOW   0x000000C0  // Low
-#define USB_TXTYPE1_PROTO_M     0x00000030  // Protocol.
+#define USB_TXTYPE1_PROTO_M     0x00000030  // Protocol
 #define USB_TXTYPE1_PROTO_CTRL  0x00000000  // Control
 #define USB_TXTYPE1_PROTO_ISOC  0x00000010  // Isochronous
 #define USB_TXTYPE1_PROTO_BULK  0x00000020  // Bulk
 #define USB_TXTYPE1_PROTO_INT   0x00000030  // Interrupt
-#define USB_TXTYPE1_TEP_M       0x0000000F  // Target Endpoint Number.
+#define USB_TXTYPE1_TEP_M       0x0000000F  // Target Endpoint Number
 #define USB_TXTYPE1_TEP_S       0
 
 //*****************************************************************************
@@ -1307,7 +2066,7 @@
 //
 //*****************************************************************************
 #define USB_TXINTERVAL1_NAKLMT_M \
-                                0x000000FF  // NAK Limit.
+                                0x000000FF  // NAK Limit
 #define USB_TXINTERVAL1_TXPOLL_M \
                                 0x000000FF  // TX Polling
 #define USB_TXINTERVAL1_TXPOLL_S \
@@ -1320,16 +2079,16 @@
 // The following are defines for the bit fields in the USB_O_RXTYPE1 register.
 //
 //*****************************************************************************
-#define USB_RXTYPE1_SPEED_M     0x000000C0  // Operating Speed.
+#define USB_RXTYPE1_SPEED_M     0x000000C0  // Operating Speed
 #define USB_RXTYPE1_SPEED_DFLT  0x00000000  // Default
 #define USB_RXTYPE1_SPEED_FULL  0x00000080  // Full
 #define USB_RXTYPE1_SPEED_LOW   0x000000C0  // Low
-#define USB_RXTYPE1_PROTO_M     0x00000030  // Protocol.
+#define USB_RXTYPE1_PROTO_M     0x00000030  // Protocol
 #define USB_RXTYPE1_PROTO_CTRL  0x00000000  // Control
 #define USB_RXTYPE1_PROTO_ISOC  0x00000010  // Isochronous
 #define USB_RXTYPE1_PROTO_BULK  0x00000020  // Bulk
 #define USB_RXTYPE1_PROTO_INT   0x00000030  // Interrupt
-#define USB_RXTYPE1_TEP_M       0x0000000F  // Target Endpoint Number.
+#define USB_RXTYPE1_TEP_M       0x0000000F  // Target Endpoint Number
 #define USB_RXTYPE1_TEP_S       0
 
 //*****************************************************************************
@@ -1341,7 +2100,7 @@
 #define USB_RXINTERVAL1_TXPOLL_M \
                                 0x000000FF  // RX Polling
 #define USB_RXINTERVAL1_NAKLMT_M \
-                                0x000000FF  // NAK Limit.
+                                0x000000FF  // NAK Limit
 #define USB_RXINTERVAL1_TXPOLL_S \
                                 0
 #define USB_RXINTERVAL1_NAKLMT_S \
@@ -1352,9 +2111,7 @@
 // The following are defines for the bit fields in the USB_O_TXMAXP2 register.
 //
 //*****************************************************************************
-#define USB_TXMAXP2_MULT_M      0x0000F800  // Multiplier.
-#define USB_TXMAXP2_MAXLOAD_M   0x000007FF  // Maximum Payload.
-#define USB_TXMAXP2_MULT_S      11
+#define USB_TXMAXP2_MAXLOAD_M   0x000007FF  // Maximum Payload
 #define USB_TXMAXP2_MAXLOAD_S   0
 
 //*****************************************************************************
@@ -1362,40 +2119,37 @@
 // The following are defines for the bit fields in the USB_O_TXCSRL2 register.
 //
 //*****************************************************************************
-#define USB_TXCSRL2_INCTX       0x00000080  // Incomplete Transmit.
 #define USB_TXCSRL2_NAKTO       0x00000080  // NAK Timeout
-#define USB_TXCSRL2_CLRDT       0x00000040  // Clear Data Toggle.
-#define USB_TXCSRL2_STALLED     0x00000020  // Endpoint Stalled.
-#define USB_TXCSRL2_SETUP       0x00000010  // Setup Packet.
-#define USB_TXCSRL2_STALL       0x00000010  // Send Stall.
-#define USB_TXCSRL2_FLUSH       0x00000008  // Flush FIFO.
-#define USB_TXCSRL2_ERROR       0x00000004  // Error.
-#define USB_TXCSRL2_UNDRN       0x00000004  // Underrun.
-#define USB_TXCSRL2_FIFONE      0x00000002  // FIFO Not Empty.
-#define USB_TXCSRL2_TXRDY       0x00000001  // Transmit Packet Ready.
+#define USB_TXCSRL2_CLRDT       0x00000040  // Clear Data Toggle
+#define USB_TXCSRL2_STALLED     0x00000020  // Endpoint Stalled
+#define USB_TXCSRL2_SETUP       0x00000010  // Setup Packet
+#define USB_TXCSRL2_STALL       0x00000010  // Send STALL
+#define USB_TXCSRL2_FLUSH       0x00000008  // Flush FIFO
+#define USB_TXCSRL2_ERROR       0x00000004  // Error
+#define USB_TXCSRL2_UNDRN       0x00000004  // Underrun
+#define USB_TXCSRL2_FIFONE      0x00000002  // FIFO Not Empty
+#define USB_TXCSRL2_TXRDY       0x00000001  // Transmit Packet Ready
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_TXCSRH2 register.
 //
 //*****************************************************************************
-#define USB_TXCSRH2_AUTOSET     0x00000080  // Auto Set.
-#define USB_TXCSRH2_ISO         0x00000040  // ISO.
-#define USB_TXCSRH2_MODE        0x00000020  // Mode.
-#define USB_TXCSRH2_DMAEN       0x00000010  // DMA Request Enable.
-#define USB_TXCSRH2_FDT         0x00000008  // Force Data Toggle.
-#define USB_TXCSRH2_DMAMOD      0x00000004  // DMA Request Mode.
-#define USB_TXCSRH2_DTWE        0x00000002  // Data Toggle Write Enable.
-#define USB_TXCSRH2_DT          0x00000001  // Data Toggle.
+#define USB_TXCSRH2_AUTOSET     0x00000080  // Auto Set
+#define USB_TXCSRH2_ISO         0x00000040  // Isochronous Transfers
+#define USB_TXCSRH2_MODE        0x00000020  // Mode
+#define USB_TXCSRH2_DMAEN       0x00000010  // DMA Request Enable
+#define USB_TXCSRH2_FDT         0x00000008  // Force Data Toggle
+#define USB_TXCSRH2_DMAMOD      0x00000004  // DMA Request Mode
+#define USB_TXCSRH2_DTWE        0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH2_DT          0x00000001  // Data Toggle
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXMAXP2 register.
 //
 //*****************************************************************************
-#define USB_RXMAXP2_MULT_M      0x0000F800  // Multiplier.
-#define USB_RXMAXP2_MAXLOAD_M   0x000007FF  // Maximum Payload.
-#define USB_RXMAXP2_MULT_S      11
+#define USB_RXMAXP2_MAXLOAD_M   0x000007FF  // Maximum Payload
 #define USB_RXMAXP2_MAXLOAD_S   0
 
 //*****************************************************************************
@@ -1403,40 +2157,39 @@
 // The following are defines for the bit fields in the USB_O_RXCSRL2 register.
 //
 //*****************************************************************************
-#define USB_RXCSRL2_CLRDT       0x00000080  // Clear Data Toggle.
-#define USB_RXCSRL2_STALLED     0x00000040  // Endpoint Stalled.
-#define USB_RXCSRL2_REQPKT      0x00000020  // Request Packet.
-#define USB_RXCSRL2_STALL       0x00000020  // Send Stall.
-#define USB_RXCSRL2_FLUSH       0x00000010  // Flush FIFO.
-#define USB_RXCSRL2_DATAERR     0x00000008  // Data Error.
-#define USB_RXCSRL2_NAKTO       0x00000008  // NAK Timeout.
-#define USB_RXCSRL2_ERROR       0x00000004  // Error.
-#define USB_RXCSRL2_OVER        0x00000004  // Overrun.
-#define USB_RXCSRL2_FULL        0x00000002  // FIFO Full.
-#define USB_RXCSRL2_RXRDY       0x00000001  // Receive Packet Ready.
+#define USB_RXCSRL2_CLRDT       0x00000080  // Clear Data Toggle
+#define USB_RXCSRL2_STALLED     0x00000040  // Endpoint Stalled
+#define USB_RXCSRL2_REQPKT      0x00000020  // Request Packet
+#define USB_RXCSRL2_STALL       0x00000020  // Send STALL
+#define USB_RXCSRL2_FLUSH       0x00000010  // Flush FIFO
+#define USB_RXCSRL2_DATAERR     0x00000008  // Data Error
+#define USB_RXCSRL2_NAKTO       0x00000008  // NAK Timeout
+#define USB_RXCSRL2_ERROR       0x00000004  // Error
+#define USB_RXCSRL2_OVER        0x00000004  // Overrun
+#define USB_RXCSRL2_FULL        0x00000002  // FIFO Full
+#define USB_RXCSRL2_RXRDY       0x00000001  // Receive Packet Ready
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXCSRH2 register.
 //
 //*****************************************************************************
-#define USB_RXCSRH2_AUTOCL      0x00000080  // Auto Clear.
-#define USB_RXCSRH2_AUTORQ      0x00000040  // Auto Request.
-#define USB_RXCSRH2_ISO         0x00000040  // ISO.
-#define USB_RXCSRH2_DMAEN       0x00000020  // DMA Request Enable.
+#define USB_RXCSRH2_AUTOCL      0x00000080  // Auto Clear
+#define USB_RXCSRH2_AUTORQ      0x00000040  // Auto Request
+#define USB_RXCSRH2_ISO         0x00000040  // Isochronous Transfers
+#define USB_RXCSRH2_DMAEN       0x00000020  // DMA Request Enable
 #define USB_RXCSRH2_DISNYET     0x00000010  // Disable NYET
-#define USB_RXCSRH2_PIDERR      0x00000010  // PID Error.
-#define USB_RXCSRH2_DMAMOD      0x00000008  // DMA Request Mode.
-#define USB_RXCSRH2_DTWE        0x00000004  // Data Toggle Write Enable.
-#define USB_RXCSRH2_DT          0x00000002  // Data Toggle.
-#define USB_RXCSRH2_INCRX       0x00000001  // Incomplete Receive.
+#define USB_RXCSRH2_PIDERR      0x00000010  // PID Error
+#define USB_RXCSRH2_DMAMOD      0x00000008  // DMA Request Mode
+#define USB_RXCSRH2_DTWE        0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH2_DT          0x00000002  // Data Toggle
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXCOUNT2 register.
 //
 //*****************************************************************************
-#define USB_RXCOUNT2_COUNT_M    0x00001FFF  // Receive Packet Count.
+#define USB_RXCOUNT2_COUNT_M    0x00001FFF  // Receive Packet Count
 #define USB_RXCOUNT2_COUNT_S    0
 
 //*****************************************************************************
@@ -1444,16 +2197,16 @@
 // The following are defines for the bit fields in the USB_O_TXTYPE2 register.
 //
 //*****************************************************************************
-#define USB_TXTYPE2_SPEED_M     0x000000C0  // Operating Speed.
+#define USB_TXTYPE2_SPEED_M     0x000000C0  // Operating Speed
 #define USB_TXTYPE2_SPEED_DFLT  0x00000000  // Default
 #define USB_TXTYPE2_SPEED_FULL  0x00000080  // Full
 #define USB_TXTYPE2_SPEED_LOW   0x000000C0  // Low
-#define USB_TXTYPE2_PROTO_M     0x00000030  // Protocol.
+#define USB_TXTYPE2_PROTO_M     0x00000030  // Protocol
 #define USB_TXTYPE2_PROTO_CTRL  0x00000000  // Control
 #define USB_TXTYPE2_PROTO_ISOC  0x00000010  // Isochronous
 #define USB_TXTYPE2_PROTO_BULK  0x00000020  // Bulk
 #define USB_TXTYPE2_PROTO_INT   0x00000030  // Interrupt
-#define USB_TXTYPE2_TEP_M       0x0000000F  // Target Endpoint Number.
+#define USB_TXTYPE2_TEP_M       0x0000000F  // Target Endpoint Number
 #define USB_TXTYPE2_TEP_S       0
 
 //*****************************************************************************
@@ -1465,7 +2218,7 @@
 #define USB_TXINTERVAL2_TXPOLL_M \
                                 0x000000FF  // TX Polling
 #define USB_TXINTERVAL2_NAKLMT_M \
-                                0x000000FF  // NAK Limit.
+                                0x000000FF  // NAK Limit
 #define USB_TXINTERVAL2_NAKLMT_S \
                                 0
 #define USB_TXINTERVAL2_TXPOLL_S \
@@ -1476,16 +2229,16 @@
 // The following are defines for the bit fields in the USB_O_RXTYPE2 register.
 //
 //*****************************************************************************
-#define USB_RXTYPE2_SPEED_M     0x000000C0  // Operating Speed.
+#define USB_RXTYPE2_SPEED_M     0x000000C0  // Operating Speed
 #define USB_RXTYPE2_SPEED_DFLT  0x00000000  // Default
 #define USB_RXTYPE2_SPEED_FULL  0x00000080  // Full
 #define USB_RXTYPE2_SPEED_LOW   0x000000C0  // Low
-#define USB_RXTYPE2_PROTO_M     0x00000030  // Protocol.
+#define USB_RXTYPE2_PROTO_M     0x00000030  // Protocol
 #define USB_RXTYPE2_PROTO_CTRL  0x00000000  // Control
 #define USB_RXTYPE2_PROTO_ISOC  0x00000010  // Isochronous
 #define USB_RXTYPE2_PROTO_BULK  0x00000020  // Bulk
 #define USB_RXTYPE2_PROTO_INT   0x00000030  // Interrupt
-#define USB_RXTYPE2_TEP_M       0x0000000F  // Target Endpoint Number.
+#define USB_RXTYPE2_TEP_M       0x0000000F  // Target Endpoint Number
 #define USB_RXTYPE2_TEP_S       0
 
 //*****************************************************************************
@@ -1497,7 +2250,7 @@
 #define USB_RXINTERVAL2_TXPOLL_M \
                                 0x000000FF  // RX Polling
 #define USB_RXINTERVAL2_NAKLMT_M \
-                                0x000000FF  // NAK Limit.
+                                0x000000FF  // NAK Limit
 #define USB_RXINTERVAL2_TXPOLL_S \
                                 0
 #define USB_RXINTERVAL2_NAKLMT_S \
@@ -1508,9 +2261,7 @@
 // The following are defines for the bit fields in the USB_O_TXMAXP3 register.
 //
 //*****************************************************************************
-#define USB_TXMAXP3_MULT_M      0x0000F800  // Multiplier.
-#define USB_TXMAXP3_MAXLOAD_M   0x000007FF  // Maximum Payload.
-#define USB_TXMAXP3_MULT_S      11
+#define USB_TXMAXP3_MAXLOAD_M   0x000007FF  // Maximum Payload
 #define USB_TXMAXP3_MAXLOAD_S   0
 
 //*****************************************************************************
@@ -1518,40 +2269,37 @@
 // The following are defines for the bit fields in the USB_O_TXCSRL3 register.
 //
 //*****************************************************************************
-#define USB_TXCSRL3_INCTX       0x00000080  // Incomplete Transmit.
 #define USB_TXCSRL3_NAKTO       0x00000080  // NAK Timeout
-#define USB_TXCSRL3_CLRDT       0x00000040  // Clear Data Toggle.
-#define USB_TXCSRL3_STALLED     0x00000020  // Endpoint Stalled.
-#define USB_TXCSRL3_SETUP       0x00000010  // Setup Packet.
-#define USB_TXCSRL3_STALL       0x00000010  // Send Stall.
-#define USB_TXCSRL3_FLUSH       0x00000008  // Flush FIFO.
-#define USB_TXCSRL3_ERROR       0x00000004  // Error.
-#define USB_TXCSRL3_UNDRN       0x00000004  // Underrun.
-#define USB_TXCSRL3_FIFONE      0x00000002  // FIFO Not Empty.
-#define USB_TXCSRL3_TXRDY       0x00000001  // Transmit Packet Ready.
+#define USB_TXCSRL3_CLRDT       0x00000040  // Clear Data Toggle
+#define USB_TXCSRL3_STALLED     0x00000020  // Endpoint Stalled
+#define USB_TXCSRL3_SETUP       0x00000010  // Setup Packet
+#define USB_TXCSRL3_STALL       0x00000010  // Send STALL
+#define USB_TXCSRL3_FLUSH       0x00000008  // Flush FIFO
+#define USB_TXCSRL3_ERROR       0x00000004  // Error
+#define USB_TXCSRL3_UNDRN       0x00000004  // Underrun
+#define USB_TXCSRL3_FIFONE      0x00000002  // FIFO Not Empty
+#define USB_TXCSRL3_TXRDY       0x00000001  // Transmit Packet Ready
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_TXCSRH3 register.
 //
 //*****************************************************************************
-#define USB_TXCSRH3_AUTOSET     0x00000080  // Auto Set.
-#define USB_TXCSRH3_ISO         0x00000040  // ISO.
-#define USB_TXCSRH3_MODE        0x00000020  // Mode.
-#define USB_TXCSRH3_DMAEN       0x00000010  // DMA Request Enable.
-#define USB_TXCSRH3_FDT         0x00000008  // Force Data Toggle.
-#define USB_TXCSRH3_DMAMOD      0x00000004  // DMA Request Mode.
-#define USB_TXCSRH3_DTWE        0x00000002  // Data Toggle Write Enable.
-#define USB_TXCSRH3_DT          0x00000001  // Data Toggle.
+#define USB_TXCSRH3_AUTOSET     0x00000080  // Auto Set
+#define USB_TXCSRH3_ISO         0x00000040  // Isochronous Transfers
+#define USB_TXCSRH3_MODE        0x00000020  // Mode
+#define USB_TXCSRH3_DMAEN       0x00000010  // DMA Request Enable
+#define USB_TXCSRH3_FDT         0x00000008  // Force Data Toggle
+#define USB_TXCSRH3_DMAMOD      0x00000004  // DMA Request Mode
+#define USB_TXCSRH3_DTWE        0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH3_DT          0x00000001  // Data Toggle
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXMAXP3 register.
 //
 //*****************************************************************************
-#define USB_RXMAXP3_MULT_M      0x0000F800  // Multiplier.
-#define USB_RXMAXP3_MAXLOAD_M   0x000007FF  // Maximum Payload.
-#define USB_RXMAXP3_MULT_S      11
+#define USB_RXMAXP3_MAXLOAD_M   0x000007FF  // Maximum Payload
 #define USB_RXMAXP3_MAXLOAD_S   0
 
 //*****************************************************************************
@@ -1559,40 +2307,39 @@
 // The following are defines for the bit fields in the USB_O_RXCSRL3 register.
 //
 //*****************************************************************************
-#define USB_RXCSRL3_CLRDT       0x00000080  // Clear Data Toggle.
-#define USB_RXCSRL3_STALLED     0x00000040  // Endpoint Stalled.
-#define USB_RXCSRL3_STALL       0x00000020  // Send Stall.
-#define USB_RXCSRL3_REQPKT      0x00000020  // Request Packet.
-#define USB_RXCSRL3_FLUSH       0x00000010  // Flush FIFO.
-#define USB_RXCSRL3_DATAERR     0x00000008  // Data Error.
-#define USB_RXCSRL3_NAKTO       0x00000008  // NAK Timeout.
-#define USB_RXCSRL3_ERROR       0x00000004  // Error.
-#define USB_RXCSRL3_OVER        0x00000004  // Overrun.
-#define USB_RXCSRL3_FULL        0x00000002  // FIFO Full.
-#define USB_RXCSRL3_RXRDY       0x00000001  // Receive Packet Ready.
+#define USB_RXCSRL3_CLRDT       0x00000080  // Clear Data Toggle
+#define USB_RXCSRL3_STALLED     0x00000040  // Endpoint Stalled
+#define USB_RXCSRL3_STALL       0x00000020  // Send STALL
+#define USB_RXCSRL3_REQPKT      0x00000020  // Request Packet
+#define USB_RXCSRL3_FLUSH       0x00000010  // Flush FIFO
+#define USB_RXCSRL3_DATAERR     0x00000008  // Data Error
+#define USB_RXCSRL3_NAKTO       0x00000008  // NAK Timeout
+#define USB_RXCSRL3_ERROR       0x00000004  // Error
+#define USB_RXCSRL3_OVER        0x00000004  // Overrun
+#define USB_RXCSRL3_FULL        0x00000002  // FIFO Full
+#define USB_RXCSRL3_RXRDY       0x00000001  // Receive Packet Ready
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXCSRH3 register.
 //
 //*****************************************************************************
-#define USB_RXCSRH3_AUTOCL      0x00000080  // Auto Clear.
-#define USB_RXCSRH3_AUTORQ      0x00000040  // Auto Request.
-#define USB_RXCSRH3_ISO         0x00000040  // ISO.
-#define USB_RXCSRH3_DMAEN       0x00000020  // DMA Request Enable.
+#define USB_RXCSRH3_AUTOCL      0x00000080  // Auto Clear
+#define USB_RXCSRH3_AUTORQ      0x00000040  // Auto Request
+#define USB_RXCSRH3_ISO         0x00000040  // Isochronous Transfers
+#define USB_RXCSRH3_DMAEN       0x00000020  // DMA Request Enable
 #define USB_RXCSRH3_DISNYET     0x00000010  // Disable NYET
-#define USB_RXCSRH3_PIDERR      0x00000010  // PID Error.
-#define USB_RXCSRH3_DMAMOD      0x00000008  // DMA Request Mode.
-#define USB_RXCSRH3_DTWE        0x00000004  // Data Toggle Write Enable.
-#define USB_RXCSRH3_DT          0x00000002  // Data Toggle.
-#define USB_RXCSRH3_INCRX       0x00000001  // Incomplete Receive.
+#define USB_RXCSRH3_PIDERR      0x00000010  // PID Error
+#define USB_RXCSRH3_DMAMOD      0x00000008  // DMA Request Mode
+#define USB_RXCSRH3_DTWE        0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH3_DT          0x00000002  // Data Toggle
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXCOUNT3 register.
 //
 //*****************************************************************************
-#define USB_RXCOUNT3_COUNT_M    0x00001FFF  // Receive Packet Count.
+#define USB_RXCOUNT3_COUNT_M    0x00001FFF  // Receive Packet Count
 #define USB_RXCOUNT3_COUNT_S    0
 
 //*****************************************************************************
@@ -1600,16 +2347,16 @@
 // The following are defines for the bit fields in the USB_O_TXTYPE3 register.
 //
 //*****************************************************************************
-#define USB_TXTYPE3_SPEED_M     0x000000C0  // Operating Speed.
+#define USB_TXTYPE3_SPEED_M     0x000000C0  // Operating Speed
 #define USB_TXTYPE3_SPEED_DFLT  0x00000000  // Default
 #define USB_TXTYPE3_SPEED_FULL  0x00000080  // Full
 #define USB_TXTYPE3_SPEED_LOW   0x000000C0  // Low
-#define USB_TXTYPE3_PROTO_M     0x00000030  // Protocol.
+#define USB_TXTYPE3_PROTO_M     0x00000030  // Protocol
 #define USB_TXTYPE3_PROTO_CTRL  0x00000000  // Control
 #define USB_TXTYPE3_PROTO_ISOC  0x00000010  // Isochronous
 #define USB_TXTYPE3_PROTO_BULK  0x00000020  // Bulk
 #define USB_TXTYPE3_PROTO_INT   0x00000030  // Interrupt
-#define USB_TXTYPE3_TEP_M       0x0000000F  // Target Endpoint Number.
+#define USB_TXTYPE3_TEP_M       0x0000000F  // Target Endpoint Number
 #define USB_TXTYPE3_TEP_S       0
 
 //*****************************************************************************
@@ -1621,7 +2368,7 @@
 #define USB_TXINTERVAL3_TXPOLL_M \
                                 0x000000FF  // TX Polling
 #define USB_TXINTERVAL3_NAKLMT_M \
-                                0x000000FF  // NAK Limit.
+                                0x000000FF  // NAK Limit
 #define USB_TXINTERVAL3_TXPOLL_S \
                                 0
 #define USB_TXINTERVAL3_NAKLMT_S \
@@ -1632,16 +2379,16 @@
 // The following are defines for the bit fields in the USB_O_RXTYPE3 register.
 //
 //*****************************************************************************
-#define USB_RXTYPE3_SPEED_M     0x000000C0  // Operating Speed.
+#define USB_RXTYPE3_SPEED_M     0x000000C0  // Operating Speed
 #define USB_RXTYPE3_SPEED_DFLT  0x00000000  // Default
 #define USB_RXTYPE3_SPEED_FULL  0x00000080  // Full
 #define USB_RXTYPE3_SPEED_LOW   0x000000C0  // Low
-#define USB_RXTYPE3_PROTO_M     0x00000030  // Protocol.
+#define USB_RXTYPE3_PROTO_M     0x00000030  // Protocol
 #define USB_RXTYPE3_PROTO_CTRL  0x00000000  // Control
 #define USB_RXTYPE3_PROTO_ISOC  0x00000010  // Isochronous
 #define USB_RXTYPE3_PROTO_BULK  0x00000020  // Bulk
 #define USB_RXTYPE3_PROTO_INT   0x00000030  // Interrupt
-#define USB_RXTYPE3_TEP_M       0x0000000F  // Target Endpoint Number.
+#define USB_RXTYPE3_TEP_M       0x0000000F  // Target Endpoint Number
 #define USB_RXTYPE3_TEP_S       0
 
 //*****************************************************************************
@@ -1653,1032 +2400,18 @@
 #define USB_RXINTERVAL3_TXPOLL_M \
                                 0x000000FF  // RX Polling
 #define USB_RXINTERVAL3_NAKLMT_M \
-                                0x000000FF  // NAK Limit.
+                                0x000000FF  // NAK Limit
 #define USB_RXINTERVAL3_TXPOLL_S \
                                 0
 #define USB_RXINTERVAL3_NAKLMT_S \
                                 0
 
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RQPKTCOUNT1
-// register.
-//
-//*****************************************************************************
-#define USB_RQPKTCOUNT1_M       0x0000FFFF  // Block Transfer Packet Count.
-#define USB_RQPKTCOUNT1_S       0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RQPKTCOUNT2
-// register.
-//
-//*****************************************************************************
-#define USB_RQPKTCOUNT2_M       0x0000FFFF  // Block Transfer Packet Count.
-#define USB_RQPKTCOUNT2_S       0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RQPKTCOUNT3
-// register.
-//
-//*****************************************************************************
-#define USB_RQPKTCOUNT3_M       0x0000FFFF  // Block Transfer Packet Count.
-#define USB_RQPKTCOUNT3_S       0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXDPKTBUFDIS
-// register.
-//
-//*****************************************************************************
-#define USB_RXDPKTBUFDIS_EP15   0x00008000  // EP15 RX Double-Packet Buffer
-                                            // Disable.
-#define USB_RXDPKTBUFDIS_EP14   0x00004000  // EP14 RX Double-Packet Buffer
-                                            // Disable.
-#define USB_RXDPKTBUFDIS_EP13   0x00002000  // EP13 RX Double-Packet Buffer
-                                            // Disable.
-#define USB_RXDPKTBUFDIS_EP12   0x00001000  // EP12 RX Double-Packet Buffer
-                                            // Disable.
-#define USB_RXDPKTBUFDIS_EP11   0x00000800  // EP11 RX Double-Packet Buffer
-                                            // Disable.
-#define USB_RXDPKTBUFDIS_EP10   0x00000400  // EP10 RX Double-Packet Buffer
-                                            // Disable.
-#define USB_RXDPKTBUFDIS_EP9    0x00000200  // EP9 RX Double-Packet Buffer
-                                            // Disable.
-#define USB_RXDPKTBUFDIS_EP8    0x00000100  // EP8 RX Double-Packet Buffer
-                                            // Disable.
-#define USB_RXDPKTBUFDIS_EP7    0x00000080  // EP7 RX Double-Packet Buffer
-                                            // Disable.
-#define USB_RXDPKTBUFDIS_EP6    0x00000040  // EP6 RX Double-Packet Buffer
-                                            // Disable.
-#define USB_RXDPKTBUFDIS_EP5    0x00000020  // EP5 RX Double-Packet Buffer
-                                            // Disable.
-#define USB_RXDPKTBUFDIS_EP4    0x00000010  // EP4 RX Double-Packet Buffer
-                                            // Disable.
-#define USB_RXDPKTBUFDIS_EP3    0x00000008  // EP3 RX Double-Packet Buffer
-                                            // Disable.
-#define USB_RXDPKTBUFDIS_EP2    0x00000004  // EP2 RX Double-Packet Buffer
-                                            // Disable.
-#define USB_RXDPKTBUFDIS_EP1    0x00000002  // EP1 RX Double-Packet Buffer
-                                            // Disable.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXDPKTBUFDIS
-// register.
-//
-//*****************************************************************************
-#define USB_TXDPKTBUFDIS_EP15   0x00008000  // EP15 TX Double-Packet Buffer
-                                            // Disable.
-#define USB_TXDPKTBUFDIS_EP14   0x00004000  // EP14 TX Double-Packet Buffer
-                                            // Disable.
-#define USB_TXDPKTBUFDIS_EP13   0x00002000  // EP13 TX Double-Packet Buffer
-                                            // Disable.
-#define USB_TXDPKTBUFDIS_EP12   0x00001000  // EP12 TX Double-Packet Buffer
-                                            // Disable.
-#define USB_TXDPKTBUFDIS_EP11   0x00000800  // EP11 TX Double-Packet Buffer
-                                            // Disable.
-#define USB_TXDPKTBUFDIS_EP10   0x00000400  // EP10 TX Double-Packet Buffer
-                                            // Disable.
-#define USB_TXDPKTBUFDIS_EP9    0x00000200  // EP9 TX Double-Packet Buffer
-                                            // Disable.
-#define USB_TXDPKTBUFDIS_EP8    0x00000100  // EP8 TX Double-Packet Buffer
-                                            // Disable.
-#define USB_TXDPKTBUFDIS_EP7    0x00000080  // EP7 TX Double-Packet Buffer
-                                            // Disable.
-#define USB_TXDPKTBUFDIS_EP6    0x00000040  // EP6 TX Double-Packet Buffer
-                                            // Disable.
-#define USB_TXDPKTBUFDIS_EP5    0x00000020  // EP5 TX Double-Packet Buffer
-                                            // Disable.
-#define USB_TXDPKTBUFDIS_EP4    0x00000010  // EP4 TX Double-Packet Buffer
-                                            // Disable.
-#define USB_TXDPKTBUFDIS_EP3    0x00000008  // EP3 TX Double-Packet Buffer
-                                            // Disable.
-#define USB_TXDPKTBUFDIS_EP2    0x00000004  // EP2 TX Double-Packet Buffer
-                                            // Disable.
-#define USB_TXDPKTBUFDIS_EP1    0x00000002  // EP1 TX Double-Packet Buffer
-                                            // Disable.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_EPC register.
-//
-//*****************************************************************************
-#define USB_EPC_PFLTACT_M       0x00000300  // Power Fault Action.
-#define USB_EPC_PFLTACT_UNCHG   0x00000000  // Unchanged
-#define USB_EPC_PFLTACT_TRIS    0x00000100  // Tristate
-#define USB_EPC_PFLTACT_LOW     0x00000200  // Low
-#define USB_EPC_PFLTACT_HIGH    0x00000300  // High
-#define USB_EPC_PFLTAEN         0x00000040  // Power Fault Action Enable.
-#define USB_EPC_PFLTSEN_HIGH    0x00000020  // Power Fault Sense.
-#define USB_EPC_PFLTEN          0x00000010  // Power Fault Input Enable.
-#define USB_EPC_EPENDE          0x00000004  // EPEN Drive Enable.
-#define USB_EPC_EPEN_M          0x00000003  // External Power Supply Enable
-                                            // Configuration.
-#define USB_EPC_EPEN_LOW        0x00000000  // Power Enable Active Low
-#define USB_EPC_EPEN_HIGH       0x00000001  // Power Enable Active High
-#define USB_EPC_EPEN_VBLOW      0x00000002  // Power Enable High if VBUS Low
-#define USB_EPC_EPEN_VBHIGH     0x00000003  // Power Enable High if VBUS High
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_EPCRIS register.
-//
-//*****************************************************************************
-#define USB_EPCRIS_PF           0x00000001  // USB Power Fault Interrupt
-                                            // Status.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_EPCIM register.
-//
-//*****************************************************************************
-#define USB_EPCIM_PF            0x00000001  // USB Power Fault Interrupt Mask.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_EPCISC register.
-//
-//*****************************************************************************
-#define USB_EPCISC_PF           0x00000001  // USB Power Fault Interrupt Status
-                                            // and Clear.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_DRRIS register.
-//
-//*****************************************************************************
-#define USB_DRRIS_RESUME        0x00000001  // Resume Interrupt Status.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_DRIM register.
-//
-//*****************************************************************************
-#define USB_DRIM_RESUME         0x00000001  // Resume Interrupt Mask.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_DRISC register.
-//
-//*****************************************************************************
-#define USB_DRISC_RESUME        0x00000001  // Resume Interrupt Status and
-                                            // Clear.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_GPCS register.
-//
-//*****************************************************************************
-#define USB_GPCS_DEVMOD         0x00000001  // Device Mode.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_VPLEN register.
-//
-//*****************************************************************************
-#define USB_VPLEN_VPLEN_M       0x000000FF  // VBus Pulse Length.
-#define USB_VPLEN_VPLEN_S       0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_VDC register.
-//
-//*****************************************************************************
-#define USB_VDC_VBDEN           0x00000001  // VBUS Droop Enable.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_VDCRIS register.
-//
-//*****************************************************************************
-#define USB_VDCRIS_VD           0x00000001  // VBUS Droop Raw Interrupt Status.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_VDCIM register.
-//
-//*****************************************************************************
-#define USB_VDCIM_VD            0x00000001  // VBUS Droop Interrupt Mask.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_VDCISC register.
-//
-//*****************************************************************************
-#define USB_VDCISC_VD           0x00000001  // VBUS Droop Interrupt Status and
-                                            // Clear.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_IDVRIS register.
-//
-//*****************************************************************************
-#define USB_IDVRIS_ID           0x00000001  // ID Valid Detect Raw Interrupt
-                                            // Status.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_IDVIM register.
-//
-//*****************************************************************************
-#define USB_IDVIM_ID            0x00000001  // ID Valid Detect Interrupt Mask.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_IDVISC register.
-//
-//*****************************************************************************
-#define USB_IDVISC_ID           0x00000001  // ID Valid Detect Interrupt Status
-                                            // and Clear.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_FIFO4 register.
-//
-//*****************************************************************************
-#define USB_FIFO4_EPDATA_M      0xFFFFFFFF  // Endpoint Data.
-#define USB_FIFO4_EPDATA_S      0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_FIFO5 register.
-//
-//*****************************************************************************
-#define USB_FIFO5_EPDATA_M      0xFFFFFFFF  // Endpoint Data.
-#define USB_FIFO5_EPDATA_S      0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_FIFO6 register.
-//
-//*****************************************************************************
-#define USB_FIFO6_EPDATA_M      0xFFFFFFFF  // Endpoint Data.
-#define USB_FIFO6_EPDATA_S      0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_FIFO7 register.
-//
-//*****************************************************************************
-#define USB_FIFO7_EPDATA_M      0xFFFFFFFF  // Endpoint Data.
-#define USB_FIFO7_EPDATA_S      0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_FIFO8 register.
-//
-//*****************************************************************************
-#define USB_FIFO8_EPDATA_M      0xFFFFFFFF  // Endpoint Data.
-#define USB_FIFO8_EPDATA_S      0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_FIFO9 register.
-//
-//*****************************************************************************
-#define USB_FIFO9_EPDATA_M      0xFFFFFFFF  // Endpoint Data.
-#define USB_FIFO9_EPDATA_S      0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_FIFO10 register.
-//
-//*****************************************************************************
-#define USB_FIFO10_EPDATA_M     0xFFFFFFFF  // Endpoint Data.
-#define USB_FIFO10_EPDATA_S     0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_FIFO11 register.
-//
-//*****************************************************************************
-#define USB_FIFO11_EPDATA_M     0xFFFFFFFF  // Endpoint Data.
-#define USB_FIFO11_EPDATA_S     0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_FIFO12 register.
-//
-//*****************************************************************************
-#define USB_FIFO12_EPDATA_M     0xFFFFFFFF  // Endpoint Data.
-#define USB_FIFO12_EPDATA_S     0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_FIFO13 register.
-//
-//*****************************************************************************
-#define USB_FIFO13_EPDATA_M     0xFFFFFFFF  // Endpoint Data.
-#define USB_FIFO13_EPDATA_S     0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_FIFO14 register.
-//
-//*****************************************************************************
-#define USB_FIFO14_EPDATA_M     0xFFFFFFFF  // Endpoint Data.
-#define USB_FIFO14_EPDATA_S     0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_FIFO15 register.
-//
-//*****************************************************************************
-#define USB_FIFO15_EPDATA_M     0xFFFFFFFF  // Endpoint Data.
-#define USB_FIFO15_EPDATA_S     0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXFUNCADDR4
-// register.
-//
-//*****************************************************************************
-#define USB_TXFUNCADDR4_ADDR_M  0x0000007F  // Device Address.
-#define USB_TXFUNCADDR4_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBADDR4
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBADDR4_MULTTRAN 0x00000080  // Multiple Translators.
-#define USB_TXHUBADDR4_ADDR_M   0x0000007F  // Hub Address.
-#define USB_TXHUBADDR4_ADDR_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBPORT4
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBPORT4_PORT_M   0x0000007F  // Hub Port.
-#define USB_TXHUBPORT4_PORT_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXFUNCADDR4
-// register.
-//
-//*****************************************************************************
-#define USB_RXFUNCADDR4_ADDR_M  0x0000007F  // Device Address.
-#define USB_RXFUNCADDR4_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBADDR4
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBADDR4_MULTTRAN 0x00000080  // Multiple Translators.
-#define USB_RXHUBADDR4_ADDR_M   0x0000007F  // Hub Address.
-#define USB_RXHUBADDR4_ADDR_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBPORT4
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBPORT4_PORT_M   0x0000007F  // Hub Port.
-#define USB_RXHUBPORT4_PORT_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXFUNCADDR5
-// register.
-//
-//*****************************************************************************
-#define USB_TXFUNCADDR5_ADDR_M  0x0000007F  // Device Address.
-#define USB_TXFUNCADDR5_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBADDR5
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBADDR5_MULTTRAN 0x00000080  // Multiple Translators.
-#define USB_TXHUBADDR5_ADDR_M   0x0000007F  // Hub Address.
-#define USB_TXHUBADDR5_ADDR_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBPORT5
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBPORT5_PORT_M   0x0000007F  // Hub Port.
-#define USB_TXHUBPORT5_PORT_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXFUNCADDR5
-// register.
-//
-//*****************************************************************************
-#define USB_RXFUNCADDR5_ADDR_M  0x0000007F  // Device Address.
-#define USB_RXFUNCADDR5_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBADDR5
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBADDR5_MULTTRAN 0x00000080  // Multiple Translators.
-#define USB_RXHUBADDR5_ADDR_M   0x0000007F  // Hub Address.
-#define USB_RXHUBADDR5_ADDR_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBPORT5
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBPORT5_PORT_M   0x0000007F  // Hub Port.
-#define USB_RXHUBPORT5_PORT_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXFUNCADDR6
-// register.
-//
-//*****************************************************************************
-#define USB_TXFUNCADDR6_ADDR_M  0x0000007F  // Device Address.
-#define USB_TXFUNCADDR6_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBADDR6
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBADDR6_MULTTRAN 0x00000080  // Multiple Translators.
-#define USB_TXHUBADDR6_ADDR_M   0x0000007F  // Hub Address.
-#define USB_TXHUBADDR6_ADDR_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBPORT6
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBPORT6_PORT_M   0x0000007F  // Hub Port.
-#define USB_TXHUBPORT6_PORT_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXFUNCADDR6
-// register.
-//
-//*****************************************************************************
-#define USB_RXFUNCADDR6_ADDR_M  0x0000007F  // Device Address.
-#define USB_RXFUNCADDR6_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBADDR6
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBADDR6_MULTTRAN 0x00000080  // Multiple Translators.
-#define USB_RXHUBADDR6_ADDR_M   0x0000007F  // Hub Address.
-#define USB_RXHUBADDR6_ADDR_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBPORT6
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBPORT6_PORT_M   0x0000007F  // Hub Port.
-#define USB_RXHUBPORT6_PORT_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXFUNCADDR7
-// register.
-//
-//*****************************************************************************
-#define USB_TXFUNCADDR7_ADDR_M  0x0000007F  // Device Address.
-#define USB_TXFUNCADDR7_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBADDR7
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBADDR7_MULTTRAN 0x00000080  // Multiple Translators.
-#define USB_TXHUBADDR7_ADDR_M   0x0000007F  // Hub Address.
-#define USB_TXHUBADDR7_ADDR_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBPORT7
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBPORT7_PORT_M   0x0000007F  // Hub Port.
-#define USB_TXHUBPORT7_PORT_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXFUNCADDR7
-// register.
-//
-//*****************************************************************************
-#define USB_RXFUNCADDR7_ADDR_M  0x0000007F  // Device Address.
-#define USB_RXFUNCADDR7_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBADDR7
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBADDR7_MULTTRAN 0x00000080  // Multiple Translators.
-#define USB_RXHUBADDR7_ADDR_M   0x0000007F  // Hub Address.
-#define USB_RXHUBADDR7_ADDR_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBPORT7
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBPORT7_PORT_M   0x0000007F  // Hub Port.
-#define USB_RXHUBPORT7_PORT_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXFUNCADDR8
-// register.
-//
-//*****************************************************************************
-#define USB_TXFUNCADDR8_ADDR_M  0x0000007F  // Device Address.
-#define USB_TXFUNCADDR8_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBADDR8
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBADDR8_MULTTRAN 0x00000080  // Multiple Translators.
-#define USB_TXHUBADDR8_ADDR_M   0x0000007F  // Hub Address.
-#define USB_TXHUBADDR8_ADDR_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBPORT8
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBPORT8_PORT_M   0x0000007F  // Hub Port.
-#define USB_TXHUBPORT8_PORT_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXFUNCADDR8
-// register.
-//
-//*****************************************************************************
-#define USB_RXFUNCADDR8_ADDR_M  0x0000007F  // Device Address.
-#define USB_RXFUNCADDR8_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBADDR8
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBADDR8_MULTTRAN 0x00000080  // Multiple Translators.
-#define USB_RXHUBADDR8_ADDR_M   0x0000007F  // Hub Address.
-#define USB_RXHUBADDR8_ADDR_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBPORT8
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBPORT8_PORT_M   0x0000007F  // Hub Port.
-#define USB_RXHUBPORT8_PORT_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXFUNCADDR9
-// register.
-//
-//*****************************************************************************
-#define USB_TXFUNCADDR9_ADDR_M  0x0000007F  // Device Address.
-#define USB_TXFUNCADDR9_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBADDR9
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBADDR9_MULTTRAN 0x00000080  // Multiple Translators.
-#define USB_TXHUBADDR9_ADDR_M   0x0000007F  // Hub Address.
-#define USB_TXHUBADDR9_ADDR_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBPORT9
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBPORT9_PORT_M   0x0000007F  // Hub Port.
-#define USB_TXHUBPORT9_PORT_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXFUNCADDR9
-// register.
-//
-//*****************************************************************************
-#define USB_RXFUNCADDR9_ADDR_M  0x0000007F  // Device Address.
-#define USB_RXFUNCADDR9_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBADDR9
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBADDR9_MULTTRAN 0x00000080  // Multiple Translators.
-#define USB_RXHUBADDR9_ADDR_M   0x0000007F  // Hub Address.
-#define USB_RXHUBADDR9_ADDR_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBPORT9
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBPORT9_PORT_M   0x0000007F  // Hub Port.
-#define USB_RXHUBPORT9_PORT_S   0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXFUNCADDR10
-// register.
-//
-//*****************************************************************************
-#define USB_TXFUNCADDR10_ADDR_M 0x0000007F  // Device Address.
-#define USB_TXFUNCADDR10_ADDR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBADDR10
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBADDR10_MULTTRAN \
-                                0x00000080  // Multiple Translators.
-#define USB_TXHUBADDR10_ADDR_M  0x0000007F  // Hub Address.
-#define USB_TXHUBADDR10_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBPORT10
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBPORT10_PORT_M  0x0000007F  // Hub Port.
-#define USB_TXHUBPORT10_PORT_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXFUNCADDR10
-// register.
-//
-//*****************************************************************************
-#define USB_RXFUNCADDR10_ADDR_M 0x0000007F  // Device Address.
-#define USB_RXFUNCADDR10_ADDR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBADDR10
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBADDR10_MULTTRAN \
-                                0x00000080  // Multiple Translators.
-#define USB_RXHUBADDR10_ADDR_M  0x0000007F  // Hub Address.
-#define USB_RXHUBADDR10_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBPORT10
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBPORT10_PORT_M  0x0000007F  // Hub Port.
-#define USB_RXHUBPORT10_PORT_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXFUNCADDR11
-// register.
-//
-//*****************************************************************************
-#define USB_TXFUNCADDR11_ADDR_M 0x0000007F  // Device Address.
-#define USB_TXFUNCADDR11_ADDR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBADDR11
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBADDR11_MULTTRAN \
-                                0x00000080  // Multiple Translators.
-#define USB_TXHUBADDR11_ADDR_M  0x0000007F  // Hub Address.
-#define USB_TXHUBADDR11_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBPORT11
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBPORT11_PORT_M  0x0000007F  // Hub Port.
-#define USB_TXHUBPORT11_PORT_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXFUNCADDR11
-// register.
-//
-//*****************************************************************************
-#define USB_RXFUNCADDR11_ADDR_M 0x0000007F  // Device Address.
-#define USB_RXFUNCADDR11_ADDR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBADDR11
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBADDR11_MULTTRAN \
-                                0x00000080  // Multiple Translators.
-#define USB_RXHUBADDR11_ADDR_M  0x0000007F  // Hub Address.
-#define USB_RXHUBADDR11_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBPORT11
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBPORT11_PORT_M  0x0000007F  // Hub Port.
-#define USB_RXHUBPORT11_PORT_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXFUNCADDR12
-// register.
-//
-//*****************************************************************************
-#define USB_TXFUNCADDR12_ADDR_M 0x0000007F  // Device Address.
-#define USB_TXFUNCADDR12_ADDR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBADDR12
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBADDR12_MULTTRAN \
-                                0x00000080  // Multiple Translators.
-#define USB_TXHUBADDR12_ADDR_M  0x0000007F  // Hub Address.
-#define USB_TXHUBADDR12_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBPORT12
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBPORT12_PORT_M  0x0000007F  // Hub Port.
-#define USB_TXHUBPORT12_PORT_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXFUNCADDR12
-// register.
-//
-//*****************************************************************************
-#define USB_RXFUNCADDR12_ADDR_M 0x0000007F  // Device Address.
-#define USB_RXFUNCADDR12_ADDR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBADDR12
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBADDR12_MULTTRAN \
-                                0x00000080  // Multiple Translators.
-#define USB_RXHUBADDR12_ADDR_M  0x0000007F  // Hub Address.
-#define USB_RXHUBADDR12_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBPORT12
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBPORT12_PORT_M  0x0000007F  // Hub Port.
-#define USB_RXHUBPORT12_PORT_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXFUNCADDR13
-// register.
-//
-//*****************************************************************************
-#define USB_TXFUNCADDR13_ADDR_M 0x0000007F  // Device Address.
-#define USB_TXFUNCADDR13_ADDR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBADDR13
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBADDR13_MULTTRAN \
-                                0x00000080  // Multiple Translators.
-#define USB_TXHUBADDR13_ADDR_M  0x0000007F  // Hub Address.
-#define USB_TXHUBADDR13_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBPORT13
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBPORT13_PORT_M  0x0000007F  // Hub Port.
-#define USB_TXHUBPORT13_PORT_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXFUNCADDR13
-// register.
-//
-//*****************************************************************************
-#define USB_RXFUNCADDR13_ADDR_M 0x0000007F  // Device Address.
-#define USB_RXFUNCADDR13_ADDR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBADDR13
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBADDR13_MULTTRAN \
-                                0x00000080  // Multiple Translators.
-#define USB_RXHUBADDR13_ADDR_M  0x0000007F  // Hub Address.
-#define USB_RXHUBADDR13_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBPORT13
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBPORT13_PORT_M  0x0000007F  // Hub Port.
-#define USB_RXHUBPORT13_PORT_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXFUNCADDR14
-// register.
-//
-//*****************************************************************************
-#define USB_TXFUNCADDR14_ADDR_M 0x0000007F  // Device Address.
-#define USB_TXFUNCADDR14_ADDR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBADDR14
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBADDR14_MULTTRAN \
-                                0x00000080  // Multiple Translators.
-#define USB_TXHUBADDR14_ADDR_M  0x0000007F  // Hub Address.
-#define USB_TXHUBADDR14_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBPORT14
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBPORT14_PORT_M  0x0000007F  // Hub Port.
-#define USB_TXHUBPORT14_PORT_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXFUNCADDR14
-// register.
-//
-//*****************************************************************************
-#define USB_RXFUNCADDR14_ADDR_M 0x0000007F  // Device Address.
-#define USB_RXFUNCADDR14_ADDR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBADDR14
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBADDR14_MULTTRAN \
-                                0x00000080  // Multiple Translators.
-#define USB_RXHUBADDR14_ADDR_M  0x0000007F  // Hub Address.
-#define USB_RXHUBADDR14_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBPORT14
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBPORT14_PORT_M  0x0000007F  // Hub Port.
-#define USB_RXHUBPORT14_PORT_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXFUNCADDR15
-// register.
-//
-//*****************************************************************************
-#define USB_TXFUNCADDR15_ADDR_M 0x0000007F  // Device Address.
-#define USB_TXFUNCADDR15_ADDR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBADDR15
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBADDR15_MULTTRAN \
-                                0x00000080  // Multiple Translators.
-#define USB_TXHUBADDR15_ADDR_M  0x0000007F  // Hub Address.
-#define USB_TXHUBADDR15_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXHUBPORT15
-// register.
-//
-//*****************************************************************************
-#define USB_TXHUBPORT15_PORT_M  0x0000007F  // Hub Port.
-#define USB_TXHUBPORT15_PORT_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXFUNCADDR15
-// register.
-//
-//*****************************************************************************
-#define USB_RXFUNCADDR15_ADDR_M 0x0000007F  // Device Address.
-#define USB_RXFUNCADDR15_ADDR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBADDR15
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBADDR15_MULTTRAN \
-                                0x00000080  // Multiple Translators.
-#define USB_RXHUBADDR15_ADDR_M  0x0000007F  // Hub Address.
-#define USB_RXHUBADDR15_ADDR_S  0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXHUBPORT15
-// register.
-//
-//*****************************************************************************
-#define USB_RXHUBPORT15_PORT_M  0x0000007F  // Hub Port.
-#define USB_RXHUBPORT15_PORT_S  0
-
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_TXMAXP4 register.
 //
 //*****************************************************************************
-#define USB_TXMAXP4_MAXLOAD_M   0x000007FF  // Maximum Payload.
+#define USB_TXMAXP4_MAXLOAD_M   0x000007FF  // Maximum Payload
 #define USB_TXMAXP4_MAXLOAD_S   0
 
 //*****************************************************************************
@@ -2686,38 +2419,37 @@
 // The following are defines for the bit fields in the USB_O_TXCSRL4 register.
 //
 //*****************************************************************************
-#define USB_TXCSRL4_INCTX       0x00000080  // Incomplete Transmit.
 #define USB_TXCSRL4_NAKTO       0x00000080  // NAK Timeout
-#define USB_TXCSRL4_CLRDT       0x00000040  // Clear Data Toggle.
-#define USB_TXCSRL4_STALLED     0x00000020  // Endpoint Stalled.
-#define USB_TXCSRL4_SETUP       0x00000010  // Setup Packet.
-#define USB_TXCSRL4_STALL       0x00000010  // Send Stall.
-#define USB_TXCSRL4_FLUSH       0x00000008  // Flush FIFO.
-#define USB_TXCSRL4_ERROR       0x00000004  // Error.
-#define USB_TXCSRL4_UNDRN       0x00000004  // Underrun.
-#define USB_TXCSRL4_FIFONE      0x00000002  // FIFO Not Empty.
-#define USB_TXCSRL4_TXRDY       0x00000001  // Transmit Packet Ready.
+#define USB_TXCSRL4_CLRDT       0x00000040  // Clear Data Toggle
+#define USB_TXCSRL4_STALLED     0x00000020  // Endpoint Stalled
+#define USB_TXCSRL4_SETUP       0x00000010  // Setup Packet
+#define USB_TXCSRL4_STALL       0x00000010  // Send STALL
+#define USB_TXCSRL4_FLUSH       0x00000008  // Flush FIFO
+#define USB_TXCSRL4_ERROR       0x00000004  // Error
+#define USB_TXCSRL4_UNDRN       0x00000004  // Underrun
+#define USB_TXCSRL4_FIFONE      0x00000002  // FIFO Not Empty
+#define USB_TXCSRL4_TXRDY       0x00000001  // Transmit Packet Ready
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_TXCSRH4 register.
 //
 //*****************************************************************************
-#define USB_TXCSRH4_AUTOSET     0x00000080  // Auto Set.
-#define USB_TXCSRH4_ISO         0x00000040  // ISO.
-#define USB_TXCSRH4_MODE        0x00000020  // Mode.
-#define USB_TXCSRH4_DMAEN       0x00000010  // DMA Request Enable.
-#define USB_TXCSRH4_FDT         0x00000008  // Force Data Toggle.
-#define USB_TXCSRH4_DMAMOD      0x00000004  // DMA Request Mode.
-#define USB_TXCSRH4_DTWE        0x00000002  // Data Toggle Write Enable.
-#define USB_TXCSRH4_DT          0x00000001  // Data Toggle.
+#define USB_TXCSRH4_AUTOSET     0x00000080  // Auto Set
+#define USB_TXCSRH4_ISO         0x00000040  // Isochronous Transfers
+#define USB_TXCSRH4_MODE        0x00000020  // Mode
+#define USB_TXCSRH4_DMAEN       0x00000010  // DMA Request Enable
+#define USB_TXCSRH4_FDT         0x00000008  // Force Data Toggle
+#define USB_TXCSRH4_DMAMOD      0x00000004  // DMA Request Mode
+#define USB_TXCSRH4_DTWE        0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH4_DT          0x00000001  // Data Toggle
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXMAXP4 register.
 //
 //*****************************************************************************
-#define USB_RXMAXP4_MAXLOAD_M   0x000007FF  // Maximum Payload.
+#define USB_RXMAXP4_MAXLOAD_M   0x000007FF  // Maximum Payload
 #define USB_RXMAXP4_MAXLOAD_S   0
 
 //*****************************************************************************
@@ -2725,40 +2457,39 @@
 // The following are defines for the bit fields in the USB_O_RXCSRL4 register.
 //
 //*****************************************************************************
-#define USB_RXCSRL4_CLRDT       0x00000080  // Clear Data Toggle.
-#define USB_RXCSRL4_STALLED     0x00000040  // Endpoint Stalled.
-#define USB_RXCSRL4_STALL       0x00000020  // Send Stall.
-#define USB_RXCSRL4_REQPKT      0x00000020  // Request Packet.
-#define USB_RXCSRL4_FLUSH       0x00000010  // Flush FIFO.
-#define USB_RXCSRL4_NAKTO       0x00000008  // NAK Timeout.
-#define USB_RXCSRL4_DATAERR     0x00000008  // Data Error.
-#define USB_RXCSRL4_OVER        0x00000004  // Overrun.
-#define USB_RXCSRL4_ERROR       0x00000004  // Error.
-#define USB_RXCSRL4_FULL        0x00000002  // FIFO Full.
-#define USB_RXCSRL4_RXRDY       0x00000001  // Receive Packet Ready.
+#define USB_RXCSRL4_CLRDT       0x00000080  // Clear Data Toggle
+#define USB_RXCSRL4_STALLED     0x00000040  // Endpoint Stalled
+#define USB_RXCSRL4_STALL       0x00000020  // Send STALL
+#define USB_RXCSRL4_REQPKT      0x00000020  // Request Packet
+#define USB_RXCSRL4_FLUSH       0x00000010  // Flush FIFO
+#define USB_RXCSRL4_NAKTO       0x00000008  // NAK Timeout
+#define USB_RXCSRL4_DATAERR     0x00000008  // Data Error
+#define USB_RXCSRL4_OVER        0x00000004  // Overrun
+#define USB_RXCSRL4_ERROR       0x00000004  // Error
+#define USB_RXCSRL4_FULL        0x00000002  // FIFO Full
+#define USB_RXCSRL4_RXRDY       0x00000001  // Receive Packet Ready
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXCSRH4 register.
 //
 //*****************************************************************************
-#define USB_RXCSRH4_AUTOCL      0x00000080  // Auto Clear.
-#define USB_RXCSRH4_AUTORQ      0x00000040  // Auto Request.
-#define USB_RXCSRH4_ISO         0x00000040  // ISO.
-#define USB_RXCSRH4_DMAEN       0x00000020  // DMA Request Enable.
+#define USB_RXCSRH4_AUTOCL      0x00000080  // Auto Clear
+#define USB_RXCSRH4_AUTORQ      0x00000040  // Auto Request
+#define USB_RXCSRH4_ISO         0x00000040  // Isochronous Transfers
+#define USB_RXCSRH4_DMAEN       0x00000020  // DMA Request Enable
 #define USB_RXCSRH4_DISNYET     0x00000010  // Disable NYET
-#define USB_RXCSRH4_PIDERR      0x00000010  // PID Error.
-#define USB_RXCSRH4_DMAMOD      0x00000008  // DMA Request Mode.
-#define USB_RXCSRH4_DTWE        0x00000004  // Data Toggle Write Enable.
-#define USB_RXCSRH4_DT          0x00000002  // Data Toggle.
-#define USB_RXCSRH4_INCRX       0x00000001  // Incomplete Receive.
+#define USB_RXCSRH4_PIDERR      0x00000010  // PID Error
+#define USB_RXCSRH4_DMAMOD      0x00000008  // DMA Request Mode
+#define USB_RXCSRH4_DTWE        0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH4_DT          0x00000002  // Data Toggle
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXCOUNT4 register.
 //
 //*****************************************************************************
-#define USB_RXCOUNT4_COUNT_M    0x00001FFF  // Receive Packet Count.
+#define USB_RXCOUNT4_COUNT_M    0x00001FFF  // Receive Packet Count
 #define USB_RXCOUNT4_COUNT_S    0
 
 //*****************************************************************************
@@ -2766,16 +2497,16 @@
 // The following are defines for the bit fields in the USB_O_TXTYPE4 register.
 //
 //*****************************************************************************
-#define USB_TXTYPE4_SPEED_M     0x000000C0  // Operating Speed.
+#define USB_TXTYPE4_SPEED_M     0x000000C0  // Operating Speed
 #define USB_TXTYPE4_SPEED_DFLT  0x00000000  // Default
 #define USB_TXTYPE4_SPEED_FULL  0x00000080  // Full
 #define USB_TXTYPE4_SPEED_LOW   0x000000C0  // Low
-#define USB_TXTYPE4_PROTO_M     0x00000030  // Protocol.
+#define USB_TXTYPE4_PROTO_M     0x00000030  // Protocol
 #define USB_TXTYPE4_PROTO_CTRL  0x00000000  // Control
 #define USB_TXTYPE4_PROTO_ISOC  0x00000010  // Isochronous
 #define USB_TXTYPE4_PROTO_BULK  0x00000020  // Bulk
 #define USB_TXTYPE4_PROTO_INT   0x00000030  // Interrupt
-#define USB_TXTYPE4_TEP_M       0x0000000F  // Target Endpoint Number.
+#define USB_TXTYPE4_TEP_M       0x0000000F  // Target Endpoint Number
 #define USB_TXTYPE4_TEP_S       0
 
 //*****************************************************************************
@@ -2787,7 +2518,7 @@
 #define USB_TXINTERVAL4_TXPOLL_M \
                                 0x000000FF  // TX Polling
 #define USB_TXINTERVAL4_NAKLMT_M \
-                                0x000000FF  // NAK Limit.
+                                0x000000FF  // NAK Limit
 #define USB_TXINTERVAL4_NAKLMT_S \
                                 0
 #define USB_TXINTERVAL4_TXPOLL_S \
@@ -2798,16 +2529,16 @@
 // The following are defines for the bit fields in the USB_O_RXTYPE4 register.
 //
 //*****************************************************************************
-#define USB_RXTYPE4_SPEED_M     0x000000C0  // Operating Speed.
+#define USB_RXTYPE4_SPEED_M     0x000000C0  // Operating Speed
 #define USB_RXTYPE4_SPEED_DFLT  0x00000000  // Default
 #define USB_RXTYPE4_SPEED_FULL  0x00000080  // Full
 #define USB_RXTYPE4_SPEED_LOW   0x000000C0  // Low
-#define USB_RXTYPE4_PROTO_M     0x00000030  // Protocol.
+#define USB_RXTYPE4_PROTO_M     0x00000030  // Protocol
 #define USB_RXTYPE4_PROTO_CTRL  0x00000000  // Control
 #define USB_RXTYPE4_PROTO_ISOC  0x00000010  // Isochronous
 #define USB_RXTYPE4_PROTO_BULK  0x00000020  // Bulk
 #define USB_RXTYPE4_PROTO_INT   0x00000030  // Interrupt
-#define USB_RXTYPE4_TEP_M       0x0000000F  // Target Endpoint Number.
+#define USB_RXTYPE4_TEP_M       0x0000000F  // Target Endpoint Number
 #define USB_RXTYPE4_TEP_S       0
 
 //*****************************************************************************
@@ -2819,7 +2550,7 @@
 #define USB_RXINTERVAL4_TXPOLL_M \
                                 0x000000FF  // RX Polling
 #define USB_RXINTERVAL4_NAKLMT_M \
-                                0x000000FF  // NAK Limit.
+                                0x000000FF  // NAK Limit
 #define USB_RXINTERVAL4_NAKLMT_S \
                                 0
 #define USB_RXINTERVAL4_TXPOLL_S \
@@ -2830,7 +2561,7 @@
 // The following are defines for the bit fields in the USB_O_TXMAXP5 register.
 //
 //*****************************************************************************
-#define USB_TXMAXP5_MAXLOAD_M   0x000007FF  // Maximum Payload.
+#define USB_TXMAXP5_MAXLOAD_M   0x000007FF  // Maximum Payload
 #define USB_TXMAXP5_MAXLOAD_S   0
 
 //*****************************************************************************
@@ -2839,37 +2570,36 @@
 //
 //*****************************************************************************
 #define USB_TXCSRL5_NAKTO       0x00000080  // NAK Timeout
-#define USB_TXCSRL5_INCTX       0x00000080  // Incomplete Transmit.
-#define USB_TXCSRL5_CLRDT       0x00000040  // Clear Data Toggle.
-#define USB_TXCSRL5_STALLED     0x00000020  // Endpoint Stalled.
-#define USB_TXCSRL5_SETUP       0x00000010  // Setup Packet.
-#define USB_TXCSRL5_STALL       0x00000010  // Send Stall.
-#define USB_TXCSRL5_FLUSH       0x00000008  // Flush FIFO.
-#define USB_TXCSRL5_ERROR       0x00000004  // Error.
-#define USB_TXCSRL5_UNDRN       0x00000004  // Underrun.
-#define USB_TXCSRL5_FIFONE      0x00000002  // FIFO Not Empty.
-#define USB_TXCSRL5_TXRDY       0x00000001  // Transmit Packet Ready.
+#define USB_TXCSRL5_CLRDT       0x00000040  // Clear Data Toggle
+#define USB_TXCSRL5_STALLED     0x00000020  // Endpoint Stalled
+#define USB_TXCSRL5_SETUP       0x00000010  // Setup Packet
+#define USB_TXCSRL5_STALL       0x00000010  // Send STALL
+#define USB_TXCSRL5_FLUSH       0x00000008  // Flush FIFO
+#define USB_TXCSRL5_ERROR       0x00000004  // Error
+#define USB_TXCSRL5_UNDRN       0x00000004  // Underrun
+#define USB_TXCSRL5_FIFONE      0x00000002  // FIFO Not Empty
+#define USB_TXCSRL5_TXRDY       0x00000001  // Transmit Packet Ready
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_TXCSRH5 register.
 //
 //*****************************************************************************
-#define USB_TXCSRH5_AUTOSET     0x00000080  // Auto Set.
-#define USB_TXCSRH5_ISO         0x00000040  // ISO.
-#define USB_TXCSRH5_MODE        0x00000020  // Mode.
-#define USB_TXCSRH5_DMAEN       0x00000010  // DMA Request Enable.
-#define USB_TXCSRH5_FDT         0x00000008  // Force Data Toggle.
-#define USB_TXCSRH5_DMAMOD      0x00000004  // DMA Request Mode.
-#define USB_TXCSRH5_DTWE        0x00000002  // Data Toggle Write Enable.
-#define USB_TXCSRH5_DT          0x00000001  // Data Toggle.
+#define USB_TXCSRH5_AUTOSET     0x00000080  // Auto Set
+#define USB_TXCSRH5_ISO         0x00000040  // Isochronous Transfers
+#define USB_TXCSRH5_MODE        0x00000020  // Mode
+#define USB_TXCSRH5_DMAEN       0x00000010  // DMA Request Enable
+#define USB_TXCSRH5_FDT         0x00000008  // Force Data Toggle
+#define USB_TXCSRH5_DMAMOD      0x00000004  // DMA Request Mode
+#define USB_TXCSRH5_DTWE        0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH5_DT          0x00000001  // Data Toggle
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXMAXP5 register.
 //
 //*****************************************************************************
-#define USB_RXMAXP5_MAXLOAD_M   0x000007FF  // Maximum Payload.
+#define USB_RXMAXP5_MAXLOAD_M   0x000007FF  // Maximum Payload
 #define USB_RXMAXP5_MAXLOAD_S   0
 
 //*****************************************************************************
@@ -2877,40 +2607,39 @@
 // The following are defines for the bit fields in the USB_O_RXCSRL5 register.
 //
 //*****************************************************************************
-#define USB_RXCSRL5_CLRDT       0x00000080  // Clear Data Toggle.
-#define USB_RXCSRL5_STALLED     0x00000040  // Endpoint Stalled.
-#define USB_RXCSRL5_STALL       0x00000020  // Send Stall.
-#define USB_RXCSRL5_REQPKT      0x00000020  // Request Packet.
-#define USB_RXCSRL5_FLUSH       0x00000010  // Flush FIFO.
-#define USB_RXCSRL5_NAKTO       0x00000008  // NAK Timeout.
-#define USB_RXCSRL5_DATAERR     0x00000008  // Data Error.
-#define USB_RXCSRL5_ERROR       0x00000004  // Error.
-#define USB_RXCSRL5_OVER        0x00000004  // Overrun.
-#define USB_RXCSRL5_FULL        0x00000002  // FIFO Full.
-#define USB_RXCSRL5_RXRDY       0x00000001  // Receive Packet Ready.
+#define USB_RXCSRL5_CLRDT       0x00000080  // Clear Data Toggle
+#define USB_RXCSRL5_STALLED     0x00000040  // Endpoint Stalled
+#define USB_RXCSRL5_STALL       0x00000020  // Send STALL
+#define USB_RXCSRL5_REQPKT      0x00000020  // Request Packet
+#define USB_RXCSRL5_FLUSH       0x00000010  // Flush FIFO
+#define USB_RXCSRL5_NAKTO       0x00000008  // NAK Timeout
+#define USB_RXCSRL5_DATAERR     0x00000008  // Data Error
+#define USB_RXCSRL5_ERROR       0x00000004  // Error
+#define USB_RXCSRL5_OVER        0x00000004  // Overrun
+#define USB_RXCSRL5_FULL        0x00000002  // FIFO Full
+#define USB_RXCSRL5_RXRDY       0x00000001  // Receive Packet Ready
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXCSRH5 register.
 //
 //*****************************************************************************
-#define USB_RXCSRH5_AUTOCL      0x00000080  // Auto Clear.
-#define USB_RXCSRH5_AUTORQ      0x00000040  // Auto Request.
-#define USB_RXCSRH5_ISO         0x00000040  // ISO.
-#define USB_RXCSRH5_DMAEN       0x00000020  // DMA Request Enable.
+#define USB_RXCSRH5_AUTOCL      0x00000080  // Auto Clear
+#define USB_RXCSRH5_AUTORQ      0x00000040  // Auto Request
+#define USB_RXCSRH5_ISO         0x00000040  // Isochronous Transfers
+#define USB_RXCSRH5_DMAEN       0x00000020  // DMA Request Enable
 #define USB_RXCSRH5_DISNYET     0x00000010  // Disable NYET
-#define USB_RXCSRH5_PIDERR      0x00000010  // PID Error.
-#define USB_RXCSRH5_DMAMOD      0x00000008  // DMA Request Mode.
-#define USB_RXCSRH5_DTWE        0x00000004  // Data Toggle Write Enable.
-#define USB_RXCSRH5_DT          0x00000002  // Data Toggle.
-#define USB_RXCSRH5_INCRX       0x00000001  // Incomplete Receive.
+#define USB_RXCSRH5_PIDERR      0x00000010  // PID Error
+#define USB_RXCSRH5_DMAMOD      0x00000008  // DMA Request Mode
+#define USB_RXCSRH5_DTWE        0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH5_DT          0x00000002  // Data Toggle
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXCOUNT5 register.
 //
 //*****************************************************************************
-#define USB_RXCOUNT5_COUNT_M    0x00001FFF  // Receive Packet Count.
+#define USB_RXCOUNT5_COUNT_M    0x00001FFF  // Receive Packet Count
 #define USB_RXCOUNT5_COUNT_S    0
 
 //*****************************************************************************
@@ -2918,16 +2647,16 @@
 // The following are defines for the bit fields in the USB_O_TXTYPE5 register.
 //
 //*****************************************************************************
-#define USB_TXTYPE5_SPEED_M     0x000000C0  // Operating Speed.
+#define USB_TXTYPE5_SPEED_M     0x000000C0  // Operating Speed
 #define USB_TXTYPE5_SPEED_DFLT  0x00000000  // Default
 #define USB_TXTYPE5_SPEED_FULL  0x00000080  // Full
 #define USB_TXTYPE5_SPEED_LOW   0x000000C0  // Low
-#define USB_TXTYPE5_PROTO_M     0x00000030  // Protocol.
+#define USB_TXTYPE5_PROTO_M     0x00000030  // Protocol
 #define USB_TXTYPE5_PROTO_CTRL  0x00000000  // Control
 #define USB_TXTYPE5_PROTO_ISOC  0x00000010  // Isochronous
 #define USB_TXTYPE5_PROTO_BULK  0x00000020  // Bulk
 #define USB_TXTYPE5_PROTO_INT   0x00000030  // Interrupt
-#define USB_TXTYPE5_TEP_M       0x0000000F  // Target Endpoint Number.
+#define USB_TXTYPE5_TEP_M       0x0000000F  // Target Endpoint Number
 #define USB_TXTYPE5_TEP_S       0
 
 //*****************************************************************************
@@ -2939,7 +2668,7 @@
 #define USB_TXINTERVAL5_TXPOLL_M \
                                 0x000000FF  // TX Polling
 #define USB_TXINTERVAL5_NAKLMT_M \
-                                0x000000FF  // NAK Limit.
+                                0x000000FF  // NAK Limit
 #define USB_TXINTERVAL5_NAKLMT_S \
                                 0
 #define USB_TXINTERVAL5_TXPOLL_S \
@@ -2950,16 +2679,16 @@
 // The following are defines for the bit fields in the USB_O_RXTYPE5 register.
 //
 //*****************************************************************************
-#define USB_RXTYPE5_SPEED_M     0x000000C0  // Operating Speed.
+#define USB_RXTYPE5_SPEED_M     0x000000C0  // Operating Speed
 #define USB_RXTYPE5_SPEED_DFLT  0x00000000  // Default
 #define USB_RXTYPE5_SPEED_FULL  0x00000080  // Full
 #define USB_RXTYPE5_SPEED_LOW   0x000000C0  // Low
-#define USB_RXTYPE5_PROTO_M     0x00000030  // Protocol.
+#define USB_RXTYPE5_PROTO_M     0x00000030  // Protocol
 #define USB_RXTYPE5_PROTO_CTRL  0x00000000  // Control
 #define USB_RXTYPE5_PROTO_ISOC  0x00000010  // Isochronous
 #define USB_RXTYPE5_PROTO_BULK  0x00000020  // Bulk
 #define USB_RXTYPE5_PROTO_INT   0x00000030  // Interrupt
-#define USB_RXTYPE5_TEP_M       0x0000000F  // Target Endpoint Number.
+#define USB_RXTYPE5_TEP_M       0x0000000F  // Target Endpoint Number
 #define USB_RXTYPE5_TEP_S       0
 
 //*****************************************************************************
@@ -2971,7 +2700,7 @@
 #define USB_RXINTERVAL5_TXPOLL_M \
                                 0x000000FF  // RX Polling
 #define USB_RXINTERVAL5_NAKLMT_M \
-                                0x000000FF  // NAK Limit.
+                                0x000000FF  // NAK Limit
 #define USB_RXINTERVAL5_TXPOLL_S \
                                 0
 #define USB_RXINTERVAL5_NAKLMT_S \
@@ -2982,7 +2711,7 @@
 // The following are defines for the bit fields in the USB_O_TXMAXP6 register.
 //
 //*****************************************************************************
-#define USB_TXMAXP6_MAXLOAD_M   0x000007FF  // Maximum Payload.
+#define USB_TXMAXP6_MAXLOAD_M   0x000007FF  // Maximum Payload
 #define USB_TXMAXP6_MAXLOAD_S   0
 
 //*****************************************************************************
@@ -2990,38 +2719,37 @@
 // The following are defines for the bit fields in the USB_O_TXCSRL6 register.
 //
 //*****************************************************************************
-#define USB_TXCSRL6_INCTX       0x00000080  // Incomplete Transmit.
 #define USB_TXCSRL6_NAKTO       0x00000080  // NAK Timeout
-#define USB_TXCSRL6_CLRDT       0x00000040  // Clear Data Toggle.
-#define USB_TXCSRL6_STALLED     0x00000020  // Endpoint Stalled.
-#define USB_TXCSRL6_STALL       0x00000010  // Send Stall.
-#define USB_TXCSRL6_SETUP       0x00000010  // Setup Packet.
-#define USB_TXCSRL6_FLUSH       0x00000008  // Flush FIFO.
-#define USB_TXCSRL6_ERROR       0x00000004  // Error.
-#define USB_TXCSRL6_UNDRN       0x00000004  // Underrun.
-#define USB_TXCSRL6_FIFONE      0x00000002  // FIFO Not Empty.
-#define USB_TXCSRL6_TXRDY       0x00000001  // Transmit Packet Ready.
+#define USB_TXCSRL6_CLRDT       0x00000040  // Clear Data Toggle
+#define USB_TXCSRL6_STALLED     0x00000020  // Endpoint Stalled
+#define USB_TXCSRL6_STALL       0x00000010  // Send STALL
+#define USB_TXCSRL6_SETUP       0x00000010  // Setup Packet
+#define USB_TXCSRL6_FLUSH       0x00000008  // Flush FIFO
+#define USB_TXCSRL6_ERROR       0x00000004  // Error
+#define USB_TXCSRL6_UNDRN       0x00000004  // Underrun
+#define USB_TXCSRL6_FIFONE      0x00000002  // FIFO Not Empty
+#define USB_TXCSRL6_TXRDY       0x00000001  // Transmit Packet Ready
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_TXCSRH6 register.
 //
 //*****************************************************************************
-#define USB_TXCSRH6_AUTOSET     0x00000080  // Auto Set.
-#define USB_TXCSRH6_ISO         0x00000040  // ISO.
-#define USB_TXCSRH6_MODE        0x00000020  // Mode.
-#define USB_TXCSRH6_DMAEN       0x00000010  // DMA Request Enable.
-#define USB_TXCSRH6_FDT         0x00000008  // Force Data Toggle.
-#define USB_TXCSRH6_DMAMOD      0x00000004  // DMA Request Mode.
-#define USB_TXCSRH6_DTWE        0x00000002  // Data Toggle Write Enable.
-#define USB_TXCSRH6_DT          0x00000001  // Data Toggle.
+#define USB_TXCSRH6_AUTOSET     0x00000080  // Auto Set
+#define USB_TXCSRH6_ISO         0x00000040  // Isochronous Transfers
+#define USB_TXCSRH6_MODE        0x00000020  // Mode
+#define USB_TXCSRH6_DMAEN       0x00000010  // DMA Request Enable
+#define USB_TXCSRH6_FDT         0x00000008  // Force Data Toggle
+#define USB_TXCSRH6_DMAMOD      0x00000004  // DMA Request Mode
+#define USB_TXCSRH6_DTWE        0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH6_DT          0x00000001  // Data Toggle
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXMAXP6 register.
 //
 //*****************************************************************************
-#define USB_RXMAXP6_MAXLOAD_M   0x000007FF  // Maximum Payload.
+#define USB_RXMAXP6_MAXLOAD_M   0x000007FF  // Maximum Payload
 #define USB_RXMAXP6_MAXLOAD_S   0
 
 //*****************************************************************************
@@ -3029,40 +2757,39 @@
 // The following are defines for the bit fields in the USB_O_RXCSRL6 register.
 //
 //*****************************************************************************
-#define USB_RXCSRL6_CLRDT       0x00000080  // Clear Data Toggle.
-#define USB_RXCSRL6_STALLED     0x00000040  // Endpoint Stalled.
-#define USB_RXCSRL6_REQPKT      0x00000020  // Request Packet.
-#define USB_RXCSRL6_STALL       0x00000020  // Send Stall.
-#define USB_RXCSRL6_FLUSH       0x00000010  // Flush FIFO.
-#define USB_RXCSRL6_NAKTO       0x00000008  // NAK Timeout.
-#define USB_RXCSRL6_DATAERR     0x00000008  // Data Error.
-#define USB_RXCSRL6_ERROR       0x00000004  // Error.
-#define USB_RXCSRL6_OVER        0x00000004  // Overrun.
-#define USB_RXCSRL6_FULL        0x00000002  // FIFO Full.
-#define USB_RXCSRL6_RXRDY       0x00000001  // Receive Packet Ready.
+#define USB_RXCSRL6_CLRDT       0x00000080  // Clear Data Toggle
+#define USB_RXCSRL6_STALLED     0x00000040  // Endpoint Stalled
+#define USB_RXCSRL6_REQPKT      0x00000020  // Request Packet
+#define USB_RXCSRL6_STALL       0x00000020  // Send STALL
+#define USB_RXCSRL6_FLUSH       0x00000010  // Flush FIFO
+#define USB_RXCSRL6_NAKTO       0x00000008  // NAK Timeout
+#define USB_RXCSRL6_DATAERR     0x00000008  // Data Error
+#define USB_RXCSRL6_ERROR       0x00000004  // Error
+#define USB_RXCSRL6_OVER        0x00000004  // Overrun
+#define USB_RXCSRL6_FULL        0x00000002  // FIFO Full
+#define USB_RXCSRL6_RXRDY       0x00000001  // Receive Packet Ready
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXCSRH6 register.
 //
 //*****************************************************************************
-#define USB_RXCSRH6_AUTOCL      0x00000080  // Auto Clear.
-#define USB_RXCSRH6_AUTORQ      0x00000040  // Auto Request.
-#define USB_RXCSRH6_ISO         0x00000040  // ISO.
-#define USB_RXCSRH6_DMAEN       0x00000020  // DMA Request Enable.
+#define USB_RXCSRH6_AUTOCL      0x00000080  // Auto Clear
+#define USB_RXCSRH6_AUTORQ      0x00000040  // Auto Request
+#define USB_RXCSRH6_ISO         0x00000040  // Isochronous Transfers
+#define USB_RXCSRH6_DMAEN       0x00000020  // DMA Request Enable
 #define USB_RXCSRH6_DISNYET     0x00000010  // Disable NYET
-#define USB_RXCSRH6_PIDERR      0x00000010  // PID Error.
-#define USB_RXCSRH6_DMAMOD      0x00000008  // DMA Request Mode.
-#define USB_RXCSRH6_DTWE        0x00000004  // Data Toggle Write Enable.
-#define USB_RXCSRH6_DT          0x00000002  // Data Toggle.
-#define USB_RXCSRH6_INCRX       0x00000001  // Incomplete Receive.
+#define USB_RXCSRH6_PIDERR      0x00000010  // PID Error
+#define USB_RXCSRH6_DMAMOD      0x00000008  // DMA Request Mode
+#define USB_RXCSRH6_DTWE        0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH6_DT          0x00000002  // Data Toggle
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXCOUNT6 register.
 //
 //*****************************************************************************
-#define USB_RXCOUNT6_COUNT_M    0x00001FFF  // Receive Packet Count.
+#define USB_RXCOUNT6_COUNT_M    0x00001FFF  // Receive Packet Count
 #define USB_RXCOUNT6_COUNT_S    0
 
 //*****************************************************************************
@@ -3070,16 +2797,16 @@
 // The following are defines for the bit fields in the USB_O_TXTYPE6 register.
 //
 //*****************************************************************************
-#define USB_TXTYPE6_SPEED_M     0x000000C0  // Operating Speed.
+#define USB_TXTYPE6_SPEED_M     0x000000C0  // Operating Speed
 #define USB_TXTYPE6_SPEED_DFLT  0x00000000  // Default
 #define USB_TXTYPE6_SPEED_FULL  0x00000080  // Full
 #define USB_TXTYPE6_SPEED_LOW   0x000000C0  // Low
-#define USB_TXTYPE6_PROTO_M     0x00000030  // Protocol.
+#define USB_TXTYPE6_PROTO_M     0x00000030  // Protocol
 #define USB_TXTYPE6_PROTO_CTRL  0x00000000  // Control
 #define USB_TXTYPE6_PROTO_ISOC  0x00000010  // Isochronous
 #define USB_TXTYPE6_PROTO_BULK  0x00000020  // Bulk
 #define USB_TXTYPE6_PROTO_INT   0x00000030  // Interrupt
-#define USB_TXTYPE6_TEP_M       0x0000000F  // Target Endpoint Number.
+#define USB_TXTYPE6_TEP_M       0x0000000F  // Target Endpoint Number
 #define USB_TXTYPE6_TEP_S       0
 
 //*****************************************************************************
@@ -3091,7 +2818,7 @@
 #define USB_TXINTERVAL6_TXPOLL_M \
                                 0x000000FF  // TX Polling
 #define USB_TXINTERVAL6_NAKLMT_M \
-                                0x000000FF  // NAK Limit.
+                                0x000000FF  // NAK Limit
 #define USB_TXINTERVAL6_TXPOLL_S \
                                 0
 #define USB_TXINTERVAL6_NAKLMT_S \
@@ -3102,16 +2829,16 @@
 // The following are defines for the bit fields in the USB_O_RXTYPE6 register.
 //
 //*****************************************************************************
-#define USB_RXTYPE6_SPEED_M     0x000000C0  // Operating Speed.
+#define USB_RXTYPE6_SPEED_M     0x000000C0  // Operating Speed
 #define USB_RXTYPE6_SPEED_DFLT  0x00000000  // Default
 #define USB_RXTYPE6_SPEED_FULL  0x00000080  // Full
 #define USB_RXTYPE6_SPEED_LOW   0x000000C0  // Low
-#define USB_RXTYPE6_PROTO_M     0x00000030  // Protocol.
+#define USB_RXTYPE6_PROTO_M     0x00000030  // Protocol
 #define USB_RXTYPE6_PROTO_CTRL  0x00000000  // Control
 #define USB_RXTYPE6_PROTO_ISOC  0x00000010  // Isochronous
 #define USB_RXTYPE6_PROTO_BULK  0x00000020  // Bulk
 #define USB_RXTYPE6_PROTO_INT   0x00000030  // Interrupt
-#define USB_RXTYPE6_TEP_M       0x0000000F  // Target Endpoint Number.
+#define USB_RXTYPE6_TEP_M       0x0000000F  // Target Endpoint Number
 #define USB_RXTYPE6_TEP_S       0
 
 //*****************************************************************************
@@ -3123,7 +2850,7 @@
 #define USB_RXINTERVAL6_TXPOLL_M \
                                 0x000000FF  // RX Polling
 #define USB_RXINTERVAL6_NAKLMT_M \
-                                0x000000FF  // NAK Limit.
+                                0x000000FF  // NAK Limit
 #define USB_RXINTERVAL6_NAKLMT_S \
                                 0
 #define USB_RXINTERVAL6_TXPOLL_S \
@@ -3134,7 +2861,7 @@
 // The following are defines for the bit fields in the USB_O_TXMAXP7 register.
 //
 //*****************************************************************************
-#define USB_TXMAXP7_MAXLOAD_M   0x000007FF  // Maximum Payload.
+#define USB_TXMAXP7_MAXLOAD_M   0x000007FF  // Maximum Payload
 #define USB_TXMAXP7_MAXLOAD_S   0
 
 //*****************************************************************************
@@ -3142,38 +2869,37 @@
 // The following are defines for the bit fields in the USB_O_TXCSRL7 register.
 //
 //*****************************************************************************
-#define USB_TXCSRL7_INCTX       0x00000080  // Incomplete Transmit.
 #define USB_TXCSRL7_NAKTO       0x00000080  // NAK Timeout
-#define USB_TXCSRL7_CLRDT       0x00000040  // Clear Data Toggle.
-#define USB_TXCSRL7_STALLED     0x00000020  // Endpoint Stalled.
-#define USB_TXCSRL7_STALL       0x00000010  // Send Stall.
-#define USB_TXCSRL7_SETUP       0x00000010  // Setup Packet.
-#define USB_TXCSRL7_FLUSH       0x00000008  // Flush FIFO.
-#define USB_TXCSRL7_ERROR       0x00000004  // Error.
-#define USB_TXCSRL7_UNDRN       0x00000004  // Underrun.
-#define USB_TXCSRL7_FIFONE      0x00000002  // FIFO Not Empty.
-#define USB_TXCSRL7_TXRDY       0x00000001  // Transmit Packet Ready.
+#define USB_TXCSRL7_CLRDT       0x00000040  // Clear Data Toggle
+#define USB_TXCSRL7_STALLED     0x00000020  // Endpoint Stalled
+#define USB_TXCSRL7_STALL       0x00000010  // Send STALL
+#define USB_TXCSRL7_SETUP       0x00000010  // Setup Packet
+#define USB_TXCSRL7_FLUSH       0x00000008  // Flush FIFO
+#define USB_TXCSRL7_ERROR       0x00000004  // Error
+#define USB_TXCSRL7_UNDRN       0x00000004  // Underrun
+#define USB_TXCSRL7_FIFONE      0x00000002  // FIFO Not Empty
+#define USB_TXCSRL7_TXRDY       0x00000001  // Transmit Packet Ready
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_TXCSRH7 register.
 //
 //*****************************************************************************
-#define USB_TXCSRH7_AUTOSET     0x00000080  // Auto Set.
-#define USB_TXCSRH7_ISO         0x00000040  // ISO.
-#define USB_TXCSRH7_MODE        0x00000020  // Mode.
-#define USB_TXCSRH7_DMAEN       0x00000010  // DMA Request Enable.
-#define USB_TXCSRH7_FDT         0x00000008  // Force Data Toggle.
-#define USB_TXCSRH7_DMAMOD      0x00000004  // DMA Request Mode.
-#define USB_TXCSRH7_DTWE        0x00000002  // Data Toggle Write Enable.
-#define USB_TXCSRH7_DT          0x00000001  // Data Toggle.
+#define USB_TXCSRH7_AUTOSET     0x00000080  // Auto Set
+#define USB_TXCSRH7_ISO         0x00000040  // Isochronous Transfers
+#define USB_TXCSRH7_MODE        0x00000020  // Mode
+#define USB_TXCSRH7_DMAEN       0x00000010  // DMA Request Enable
+#define USB_TXCSRH7_FDT         0x00000008  // Force Data Toggle
+#define USB_TXCSRH7_DMAMOD      0x00000004  // DMA Request Mode
+#define USB_TXCSRH7_DTWE        0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH7_DT          0x00000001  // Data Toggle
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXMAXP7 register.
 //
 //*****************************************************************************
-#define USB_RXMAXP7_MAXLOAD_M   0x000007FF  // Maximum Payload.
+#define USB_RXMAXP7_MAXLOAD_M   0x000007FF  // Maximum Payload
 #define USB_RXMAXP7_MAXLOAD_S   0
 
 //*****************************************************************************
@@ -3181,40 +2907,39 @@
 // The following are defines for the bit fields in the USB_O_RXCSRL7 register.
 //
 //*****************************************************************************
-#define USB_RXCSRL7_CLRDT       0x00000080  // Clear Data Toggle.
-#define USB_RXCSRL7_STALLED     0x00000040  // Endpoint Stalled.
-#define USB_RXCSRL7_REQPKT      0x00000020  // Request Packet.
-#define USB_RXCSRL7_STALL       0x00000020  // Send Stall.
-#define USB_RXCSRL7_FLUSH       0x00000010  // Flush FIFO.
-#define USB_RXCSRL7_DATAERR     0x00000008  // Data Error.
-#define USB_RXCSRL7_NAKTO       0x00000008  // NAK Timeout.
-#define USB_RXCSRL7_ERROR       0x00000004  // Error.
-#define USB_RXCSRL7_OVER        0x00000004  // Overrun.
-#define USB_RXCSRL7_FULL        0x00000002  // FIFO Full.
-#define USB_RXCSRL7_RXRDY       0x00000001  // Receive Packet Ready.
+#define USB_RXCSRL7_CLRDT       0x00000080  // Clear Data Toggle
+#define USB_RXCSRL7_STALLED     0x00000040  // Endpoint Stalled
+#define USB_RXCSRL7_REQPKT      0x00000020  // Request Packet
+#define USB_RXCSRL7_STALL       0x00000020  // Send STALL
+#define USB_RXCSRL7_FLUSH       0x00000010  // Flush FIFO
+#define USB_RXCSRL7_DATAERR     0x00000008  // Data Error
+#define USB_RXCSRL7_NAKTO       0x00000008  // NAK Timeout
+#define USB_RXCSRL7_ERROR       0x00000004  // Error
+#define USB_RXCSRL7_OVER        0x00000004  // Overrun
+#define USB_RXCSRL7_FULL        0x00000002  // FIFO Full
+#define USB_RXCSRL7_RXRDY       0x00000001  // Receive Packet Ready
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXCSRH7 register.
 //
 //*****************************************************************************
-#define USB_RXCSRH7_AUTOCL      0x00000080  // Auto Clear.
-#define USB_RXCSRH7_ISO         0x00000040  // ISO.
-#define USB_RXCSRH7_AUTORQ      0x00000040  // Auto Request.
-#define USB_RXCSRH7_DMAEN       0x00000020  // DMA Request Enable.
-#define USB_RXCSRH7_PIDERR      0x00000010  // PID Error.
+#define USB_RXCSRH7_AUTOCL      0x00000080  // Auto Clear
+#define USB_RXCSRH7_ISO         0x00000040  // Isochronous Transfers
+#define USB_RXCSRH7_AUTORQ      0x00000040  // Auto Request
+#define USB_RXCSRH7_DMAEN       0x00000020  // DMA Request Enable
+#define USB_RXCSRH7_PIDERR      0x00000010  // PID Error
 #define USB_RXCSRH7_DISNYET     0x00000010  // Disable NYET
-#define USB_RXCSRH7_DMAMOD      0x00000008  // DMA Request Mode.
-#define USB_RXCSRH7_DTWE        0x00000004  // Data Toggle Write Enable.
-#define USB_RXCSRH7_DT          0x00000002  // Data Toggle.
-#define USB_RXCSRH7_INCRX       0x00000001  // Incomplete Receive.
+#define USB_RXCSRH7_DMAMOD      0x00000008  // DMA Request Mode
+#define USB_RXCSRH7_DTWE        0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH7_DT          0x00000002  // Data Toggle
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXCOUNT7 register.
 //
 //*****************************************************************************
-#define USB_RXCOUNT7_COUNT_M    0x00001FFF  // Receive Packet Count.
+#define USB_RXCOUNT7_COUNT_M    0x00001FFF  // Receive Packet Count
 #define USB_RXCOUNT7_COUNT_S    0
 
 //*****************************************************************************
@@ -3222,16 +2947,16 @@
 // The following are defines for the bit fields in the USB_O_TXTYPE7 register.
 //
 //*****************************************************************************
-#define USB_TXTYPE7_SPEED_M     0x000000C0  // Operating Speed.
+#define USB_TXTYPE7_SPEED_M     0x000000C0  // Operating Speed
 #define USB_TXTYPE7_SPEED_DFLT  0x00000000  // Default
 #define USB_TXTYPE7_SPEED_FULL  0x00000080  // Full
 #define USB_TXTYPE7_SPEED_LOW   0x000000C0  // Low
-#define USB_TXTYPE7_PROTO_M     0x00000030  // Protocol.
+#define USB_TXTYPE7_PROTO_M     0x00000030  // Protocol
 #define USB_TXTYPE7_PROTO_CTRL  0x00000000  // Control
 #define USB_TXTYPE7_PROTO_ISOC  0x00000010  // Isochronous
 #define USB_TXTYPE7_PROTO_BULK  0x00000020  // Bulk
 #define USB_TXTYPE7_PROTO_INT   0x00000030  // Interrupt
-#define USB_TXTYPE7_TEP_M       0x0000000F  // Target Endpoint Number.
+#define USB_TXTYPE7_TEP_M       0x0000000F  // Target Endpoint Number
 #define USB_TXTYPE7_TEP_S       0
 
 //*****************************************************************************
@@ -3243,7 +2968,7 @@
 #define USB_TXINTERVAL7_TXPOLL_M \
                                 0x000000FF  // TX Polling
 #define USB_TXINTERVAL7_NAKLMT_M \
-                                0x000000FF  // NAK Limit.
+                                0x000000FF  // NAK Limit
 #define USB_TXINTERVAL7_NAKLMT_S \
                                 0
 #define USB_TXINTERVAL7_TXPOLL_S \
@@ -3254,16 +2979,16 @@
 // The following are defines for the bit fields in the USB_O_RXTYPE7 register.
 //
 //*****************************************************************************
-#define USB_RXTYPE7_SPEED_M     0x000000C0  // Operating Speed.
+#define USB_RXTYPE7_SPEED_M     0x000000C0  // Operating Speed
 #define USB_RXTYPE7_SPEED_DFLT  0x00000000  // Default
 #define USB_RXTYPE7_SPEED_FULL  0x00000080  // Full
 #define USB_RXTYPE7_SPEED_LOW   0x000000C0  // Low
-#define USB_RXTYPE7_PROTO_M     0x00000030  // Protocol.
+#define USB_RXTYPE7_PROTO_M     0x00000030  // Protocol
 #define USB_RXTYPE7_PROTO_CTRL  0x00000000  // Control
 #define USB_RXTYPE7_PROTO_ISOC  0x00000010  // Isochronous
 #define USB_RXTYPE7_PROTO_BULK  0x00000020  // Bulk
 #define USB_RXTYPE7_PROTO_INT   0x00000030  // Interrupt
-#define USB_RXTYPE7_TEP_M       0x0000000F  // Target Endpoint Number.
+#define USB_RXTYPE7_TEP_M       0x0000000F  // Target Endpoint Number
 #define USB_RXTYPE7_TEP_S       0
 
 //*****************************************************************************
@@ -3275,7 +3000,7 @@
 #define USB_RXINTERVAL7_TXPOLL_M \
                                 0x000000FF  // RX Polling
 #define USB_RXINTERVAL7_NAKLMT_M \
-                                0x000000FF  // NAK Limit.
+                                0x000000FF  // NAK Limit
 #define USB_RXINTERVAL7_NAKLMT_S \
                                 0
 #define USB_RXINTERVAL7_TXPOLL_S \
@@ -3286,7 +3011,7 @@
 // The following are defines for the bit fields in the USB_O_TXMAXP8 register.
 //
 //*****************************************************************************
-#define USB_TXMAXP8_MAXLOAD_M   0x000007FF  // Maximum Payload.
+#define USB_TXMAXP8_MAXLOAD_M   0x000007FF  // Maximum Payload
 #define USB_TXMAXP8_MAXLOAD_S   0
 
 //*****************************************************************************
@@ -3294,38 +3019,37 @@
 // The following are defines for the bit fields in the USB_O_TXCSRL8 register.
 //
 //*****************************************************************************
-#define USB_TXCSRL8_INCTX       0x00000080  // Incomplete Transmit.
 #define USB_TXCSRL8_NAKTO       0x00000080  // NAK Timeout
-#define USB_TXCSRL8_CLRDT       0x00000040  // Clear Data Toggle.
-#define USB_TXCSRL8_STALLED     0x00000020  // Endpoint Stalled.
-#define USB_TXCSRL8_STALL       0x00000010  // Send Stall.
-#define USB_TXCSRL8_SETUP       0x00000010  // Setup Packet.
-#define USB_TXCSRL8_FLUSH       0x00000008  // Flush FIFO.
-#define USB_TXCSRL8_ERROR       0x00000004  // Error.
-#define USB_TXCSRL8_UNDRN       0x00000004  // Underrun.
-#define USB_TXCSRL8_FIFONE      0x00000002  // FIFO Not Empty.
-#define USB_TXCSRL8_TXRDY       0x00000001  // Transmit Packet Ready.
+#define USB_TXCSRL8_CLRDT       0x00000040  // Clear Data Toggle
+#define USB_TXCSRL8_STALLED     0x00000020  // Endpoint Stalled
+#define USB_TXCSRL8_STALL       0x00000010  // Send STALL
+#define USB_TXCSRL8_SETUP       0x00000010  // Setup Packet
+#define USB_TXCSRL8_FLUSH       0x00000008  // Flush FIFO
+#define USB_TXCSRL8_ERROR       0x00000004  // Error
+#define USB_TXCSRL8_UNDRN       0x00000004  // Underrun
+#define USB_TXCSRL8_FIFONE      0x00000002  // FIFO Not Empty
+#define USB_TXCSRL8_TXRDY       0x00000001  // Transmit Packet Ready
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_TXCSRH8 register.
 //
 //*****************************************************************************
-#define USB_TXCSRH8_AUTOSET     0x00000080  // Auto Set.
-#define USB_TXCSRH8_ISO         0x00000040  // ISO.
-#define USB_TXCSRH8_MODE        0x00000020  // Mode.
-#define USB_TXCSRH8_DMAEN       0x00000010  // DMA Request Enable.
-#define USB_TXCSRH8_FDT         0x00000008  // Force Data Toggle.
-#define USB_TXCSRH8_DMAMOD      0x00000004  // DMA Request Mode.
-#define USB_TXCSRH8_DTWE        0x00000002  // Data Toggle Write Enable.
-#define USB_TXCSRH8_DT          0x00000001  // Data Toggle.
+#define USB_TXCSRH8_AUTOSET     0x00000080  // Auto Set
+#define USB_TXCSRH8_ISO         0x00000040  // Isochronous Transfers
+#define USB_TXCSRH8_MODE        0x00000020  // Mode
+#define USB_TXCSRH8_DMAEN       0x00000010  // DMA Request Enable
+#define USB_TXCSRH8_FDT         0x00000008  // Force Data Toggle
+#define USB_TXCSRH8_DMAMOD      0x00000004  // DMA Request Mode
+#define USB_TXCSRH8_DTWE        0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH8_DT          0x00000001  // Data Toggle
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXMAXP8 register.
 //
 //*****************************************************************************
-#define USB_RXMAXP8_MAXLOAD_M   0x000007FF  // Maximum Payload.
+#define USB_RXMAXP8_MAXLOAD_M   0x000007FF  // Maximum Payload
 #define USB_RXMAXP8_MAXLOAD_S   0
 
 //*****************************************************************************
@@ -3333,40 +3057,39 @@
 // The following are defines for the bit fields in the USB_O_RXCSRL8 register.
 //
 //*****************************************************************************
-#define USB_RXCSRL8_CLRDT       0x00000080  // Clear Data Toggle.
-#define USB_RXCSRL8_STALLED     0x00000040  // Endpoint Stalled.
-#define USB_RXCSRL8_STALL       0x00000020  // Send Stall.
-#define USB_RXCSRL8_REQPKT      0x00000020  // Request Packet.
-#define USB_RXCSRL8_FLUSH       0x00000010  // Flush FIFO.
-#define USB_RXCSRL8_NAKTO       0x00000008  // NAK Timeout.
-#define USB_RXCSRL8_DATAERR     0x00000008  // Data Error.
-#define USB_RXCSRL8_OVER        0x00000004  // Overrun.
-#define USB_RXCSRL8_ERROR       0x00000004  // Error.
-#define USB_RXCSRL8_FULL        0x00000002  // FIFO Full.
-#define USB_RXCSRL8_RXRDY       0x00000001  // Receive Packet Ready.
+#define USB_RXCSRL8_CLRDT       0x00000080  // Clear Data Toggle
+#define USB_RXCSRL8_STALLED     0x00000040  // Endpoint Stalled
+#define USB_RXCSRL8_STALL       0x00000020  // Send STALL
+#define USB_RXCSRL8_REQPKT      0x00000020  // Request Packet
+#define USB_RXCSRL8_FLUSH       0x00000010  // Flush FIFO
+#define USB_RXCSRL8_NAKTO       0x00000008  // NAK Timeout
+#define USB_RXCSRL8_DATAERR     0x00000008  // Data Error
+#define USB_RXCSRL8_OVER        0x00000004  // Overrun
+#define USB_RXCSRL8_ERROR       0x00000004  // Error
+#define USB_RXCSRL8_FULL        0x00000002  // FIFO Full
+#define USB_RXCSRL8_RXRDY       0x00000001  // Receive Packet Ready
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXCSRH8 register.
 //
 //*****************************************************************************
-#define USB_RXCSRH8_AUTOCL      0x00000080  // Auto Clear.
-#define USB_RXCSRH8_AUTORQ      0x00000040  // Auto Request.
-#define USB_RXCSRH8_ISO         0x00000040  // ISO.
-#define USB_RXCSRH8_DMAEN       0x00000020  // DMA Request Enable.
+#define USB_RXCSRH8_AUTOCL      0x00000080  // Auto Clear
+#define USB_RXCSRH8_AUTORQ      0x00000040  // Auto Request
+#define USB_RXCSRH8_ISO         0x00000040  // Isochronous Transfers
+#define USB_RXCSRH8_DMAEN       0x00000020  // DMA Request Enable
 #define USB_RXCSRH8_DISNYET     0x00000010  // Disable NYET
-#define USB_RXCSRH8_PIDERR      0x00000010  // PID Error.
-#define USB_RXCSRH8_DMAMOD      0x00000008  // DMA Request Mode.
-#define USB_RXCSRH8_DTWE        0x00000004  // Data Toggle Write Enable.
-#define USB_RXCSRH8_DT          0x00000002  // Data Toggle.
-#define USB_RXCSRH8_INCRX       0x00000001  // Incomplete Receive.
+#define USB_RXCSRH8_PIDERR      0x00000010  // PID Error
+#define USB_RXCSRH8_DMAMOD      0x00000008  // DMA Request Mode
+#define USB_RXCSRH8_DTWE        0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH8_DT          0x00000002  // Data Toggle
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXCOUNT8 register.
 //
 //*****************************************************************************
-#define USB_RXCOUNT8_COUNT_M    0x00001FFF  // Receive Packet Count.
+#define USB_RXCOUNT8_COUNT_M    0x00001FFF  // Receive Packet Count
 #define USB_RXCOUNT8_COUNT_S    0
 
 //*****************************************************************************
@@ -3374,16 +3097,16 @@
 // The following are defines for the bit fields in the USB_O_TXTYPE8 register.
 //
 //*****************************************************************************
-#define USB_TXTYPE8_SPEED_M     0x000000C0  // Operating Speed.
+#define USB_TXTYPE8_SPEED_M     0x000000C0  // Operating Speed
 #define USB_TXTYPE8_SPEED_DFLT  0x00000000  // Default
 #define USB_TXTYPE8_SPEED_FULL  0x00000080  // Full
 #define USB_TXTYPE8_SPEED_LOW   0x000000C0  // Low
-#define USB_TXTYPE8_PROTO_M     0x00000030  // Protocol.
+#define USB_TXTYPE8_PROTO_M     0x00000030  // Protocol
 #define USB_TXTYPE8_PROTO_CTRL  0x00000000  // Control
 #define USB_TXTYPE8_PROTO_ISOC  0x00000010  // Isochronous
 #define USB_TXTYPE8_PROTO_BULK  0x00000020  // Bulk
 #define USB_TXTYPE8_PROTO_INT   0x00000030  // Interrupt
-#define USB_TXTYPE8_TEP_M       0x0000000F  // Target Endpoint Number.
+#define USB_TXTYPE8_TEP_M       0x0000000F  // Target Endpoint Number
 #define USB_TXTYPE8_TEP_S       0
 
 //*****************************************************************************
@@ -3395,7 +3118,7 @@
 #define USB_TXINTERVAL8_TXPOLL_M \
                                 0x000000FF  // TX Polling
 #define USB_TXINTERVAL8_NAKLMT_M \
-                                0x000000FF  // NAK Limit.
+                                0x000000FF  // NAK Limit
 #define USB_TXINTERVAL8_NAKLMT_S \
                                 0
 #define USB_TXINTERVAL8_TXPOLL_S \
@@ -3406,16 +3129,16 @@
 // The following are defines for the bit fields in the USB_O_RXTYPE8 register.
 //
 //*****************************************************************************
-#define USB_RXTYPE8_SPEED_M     0x000000C0  // Operating Speed.
+#define USB_RXTYPE8_SPEED_M     0x000000C0  // Operating Speed
 #define USB_RXTYPE8_SPEED_DFLT  0x00000000  // Default
 #define USB_RXTYPE8_SPEED_FULL  0x00000080  // Full
 #define USB_RXTYPE8_SPEED_LOW   0x000000C0  // Low
-#define USB_RXTYPE8_PROTO_M     0x00000030  // Protocol.
+#define USB_RXTYPE8_PROTO_M     0x00000030  // Protocol
 #define USB_RXTYPE8_PROTO_CTRL  0x00000000  // Control
 #define USB_RXTYPE8_PROTO_ISOC  0x00000010  // Isochronous
 #define USB_RXTYPE8_PROTO_BULK  0x00000020  // Bulk
 #define USB_RXTYPE8_PROTO_INT   0x00000030  // Interrupt
-#define USB_RXTYPE8_TEP_M       0x0000000F  // Target Endpoint Number.
+#define USB_RXTYPE8_TEP_M       0x0000000F  // Target Endpoint Number
 #define USB_RXTYPE8_TEP_S       0
 
 //*****************************************************************************
@@ -3425,7 +3148,7 @@
 //
 //*****************************************************************************
 #define USB_RXINTERVAL8_NAKLMT_M \
-                                0x000000FF  // NAK Limit.
+                                0x000000FF  // NAK Limit
 #define USB_RXINTERVAL8_TXPOLL_M \
                                 0x000000FF  // RX Polling
 #define USB_RXINTERVAL8_NAKLMT_S \
@@ -3438,7 +3161,7 @@
 // The following are defines for the bit fields in the USB_O_TXMAXP9 register.
 //
 //*****************************************************************************
-#define USB_TXMAXP9_MAXLOAD_M   0x000007FF  // Maximum Payload.
+#define USB_TXMAXP9_MAXLOAD_M   0x000007FF  // Maximum Payload
 #define USB_TXMAXP9_MAXLOAD_S   0
 
 //*****************************************************************************
@@ -3446,38 +3169,37 @@
 // The following are defines for the bit fields in the USB_O_TXCSRL9 register.
 //
 //*****************************************************************************
-#define USB_TXCSRL9_INCTX       0x00000080  // Incomplete Transmit.
 #define USB_TXCSRL9_NAKTO       0x00000080  // NAK Timeout
-#define USB_TXCSRL9_CLRDT       0x00000040  // Clear Data Toggle.
-#define USB_TXCSRL9_STALLED     0x00000020  // Endpoint Stalled.
-#define USB_TXCSRL9_SETUP       0x00000010  // Setup Packet.
-#define USB_TXCSRL9_STALL       0x00000010  // Send Stall.
-#define USB_TXCSRL9_FLUSH       0x00000008  // Flush FIFO.
-#define USB_TXCSRL9_ERROR       0x00000004  // Error.
-#define USB_TXCSRL9_UNDRN       0x00000004  // Underrun.
-#define USB_TXCSRL9_FIFONE      0x00000002  // FIFO Not Empty.
-#define USB_TXCSRL9_TXRDY       0x00000001  // Transmit Packet Ready.
+#define USB_TXCSRL9_CLRDT       0x00000040  // Clear Data Toggle
+#define USB_TXCSRL9_STALLED     0x00000020  // Endpoint Stalled
+#define USB_TXCSRL9_SETUP       0x00000010  // Setup Packet
+#define USB_TXCSRL9_STALL       0x00000010  // Send STALL
+#define USB_TXCSRL9_FLUSH       0x00000008  // Flush FIFO
+#define USB_TXCSRL9_ERROR       0x00000004  // Error
+#define USB_TXCSRL9_UNDRN       0x00000004  // Underrun
+#define USB_TXCSRL9_FIFONE      0x00000002  // FIFO Not Empty
+#define USB_TXCSRL9_TXRDY       0x00000001  // Transmit Packet Ready
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_TXCSRH9 register.
 //
 //*****************************************************************************
-#define USB_TXCSRH9_AUTOSET     0x00000080  // Auto Set.
-#define USB_TXCSRH9_ISO         0x00000040  // ISO.
-#define USB_TXCSRH9_MODE        0x00000020  // Mode.
-#define USB_TXCSRH9_DMAEN       0x00000010  // DMA Request Enable.
-#define USB_TXCSRH9_FDT         0x00000008  // Force Data Toggle.
-#define USB_TXCSRH9_DMAMOD      0x00000004  // DMA Request Mode.
-#define USB_TXCSRH9_DTWE        0x00000002  // Data Toggle Write Enable.
-#define USB_TXCSRH9_DT          0x00000001  // Data Toggle.
+#define USB_TXCSRH9_AUTOSET     0x00000080  // Auto Set
+#define USB_TXCSRH9_ISO         0x00000040  // Isochronous Transfers
+#define USB_TXCSRH9_MODE        0x00000020  // Mode
+#define USB_TXCSRH9_DMAEN       0x00000010  // DMA Request Enable
+#define USB_TXCSRH9_FDT         0x00000008  // Force Data Toggle
+#define USB_TXCSRH9_DMAMOD      0x00000004  // DMA Request Mode
+#define USB_TXCSRH9_DTWE        0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH9_DT          0x00000001  // Data Toggle
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXMAXP9 register.
 //
 //*****************************************************************************
-#define USB_RXMAXP9_MAXLOAD_M   0x000007FF  // Maximum Payload.
+#define USB_RXMAXP9_MAXLOAD_M   0x000007FF  // Maximum Payload
 #define USB_RXMAXP9_MAXLOAD_S   0
 
 //*****************************************************************************
@@ -3485,40 +3207,39 @@
 // The following are defines for the bit fields in the USB_O_RXCSRL9 register.
 //
 //*****************************************************************************
-#define USB_RXCSRL9_CLRDT       0x00000080  // Clear Data Toggle.
-#define USB_RXCSRL9_STALLED     0x00000040  // Endpoint Stalled.
-#define USB_RXCSRL9_STALL       0x00000020  // Send Stall.
-#define USB_RXCSRL9_REQPKT      0x00000020  // Request Packet.
-#define USB_RXCSRL9_FLUSH       0x00000010  // Flush FIFO.
-#define USB_RXCSRL9_DATAERR     0x00000008  // Data Error.
-#define USB_RXCSRL9_NAKTO       0x00000008  // NAK Timeout.
-#define USB_RXCSRL9_ERROR       0x00000004  // Error.
-#define USB_RXCSRL9_OVER        0x00000004  // Overrun.
-#define USB_RXCSRL9_FULL        0x00000002  // FIFO Full.
-#define USB_RXCSRL9_RXRDY       0x00000001  // Receive Packet Ready.
+#define USB_RXCSRL9_CLRDT       0x00000080  // Clear Data Toggle
+#define USB_RXCSRL9_STALLED     0x00000040  // Endpoint Stalled
+#define USB_RXCSRL9_STALL       0x00000020  // Send STALL
+#define USB_RXCSRL9_REQPKT      0x00000020  // Request Packet
+#define USB_RXCSRL9_FLUSH       0x00000010  // Flush FIFO
+#define USB_RXCSRL9_DATAERR     0x00000008  // Data Error
+#define USB_RXCSRL9_NAKTO       0x00000008  // NAK Timeout
+#define USB_RXCSRL9_ERROR       0x00000004  // Error
+#define USB_RXCSRL9_OVER        0x00000004  // Overrun
+#define USB_RXCSRL9_FULL        0x00000002  // FIFO Full
+#define USB_RXCSRL9_RXRDY       0x00000001  // Receive Packet Ready
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXCSRH9 register.
 //
 //*****************************************************************************
-#define USB_RXCSRH9_AUTOCL      0x00000080  // Auto Clear.
-#define USB_RXCSRH9_ISO         0x00000040  // ISO.
-#define USB_RXCSRH9_AUTORQ      0x00000040  // Auto Request.
-#define USB_RXCSRH9_DMAEN       0x00000020  // DMA Request Enable.
-#define USB_RXCSRH9_PIDERR      0x00000010  // PID Error.
+#define USB_RXCSRH9_AUTOCL      0x00000080  // Auto Clear
+#define USB_RXCSRH9_ISO         0x00000040  // Isochronous Transfers
+#define USB_RXCSRH9_AUTORQ      0x00000040  // Auto Request
+#define USB_RXCSRH9_DMAEN       0x00000020  // DMA Request Enable
+#define USB_RXCSRH9_PIDERR      0x00000010  // PID Error
 #define USB_RXCSRH9_DISNYET     0x00000010  // Disable NYET
-#define USB_RXCSRH9_DMAMOD      0x00000008  // DMA Request Mode.
-#define USB_RXCSRH9_DTWE        0x00000004  // Data Toggle Write Enable.
-#define USB_RXCSRH9_DT          0x00000002  // Data Toggle.
-#define USB_RXCSRH9_INCRX       0x00000001  // Incomplete Receive.
+#define USB_RXCSRH9_DMAMOD      0x00000008  // DMA Request Mode
+#define USB_RXCSRH9_DTWE        0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH9_DT          0x00000002  // Data Toggle
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXCOUNT9 register.
 //
 //*****************************************************************************
-#define USB_RXCOUNT9_COUNT_M    0x00001FFF  // Receive Packet Count.
+#define USB_RXCOUNT9_COUNT_M    0x00001FFF  // Receive Packet Count
 #define USB_RXCOUNT9_COUNT_S    0
 
 //*****************************************************************************
@@ -3526,16 +3247,16 @@
 // The following are defines for the bit fields in the USB_O_TXTYPE9 register.
 //
 //*****************************************************************************
-#define USB_TXTYPE9_SPEED_M     0x000000C0  // Operating Speed.
+#define USB_TXTYPE9_SPEED_M     0x000000C0  // Operating Speed
 #define USB_TXTYPE9_SPEED_DFLT  0x00000000  // Default
 #define USB_TXTYPE9_SPEED_FULL  0x00000080  // Full
 #define USB_TXTYPE9_SPEED_LOW   0x000000C0  // Low
-#define USB_TXTYPE9_PROTO_M     0x00000030  // Protocol.
+#define USB_TXTYPE9_PROTO_M     0x00000030  // Protocol
 #define USB_TXTYPE9_PROTO_CTRL  0x00000000  // Control
 #define USB_TXTYPE9_PROTO_ISOC  0x00000010  // Isochronous
 #define USB_TXTYPE9_PROTO_BULK  0x00000020  // Bulk
 #define USB_TXTYPE9_PROTO_INT   0x00000030  // Interrupt
-#define USB_TXTYPE9_TEP_M       0x0000000F  // Target Endpoint Number.
+#define USB_TXTYPE9_TEP_M       0x0000000F  // Target Endpoint Number
 #define USB_TXTYPE9_TEP_S       0
 
 //*****************************************************************************
@@ -3547,7 +3268,7 @@
 #define USB_TXINTERVAL9_TXPOLL_M \
                                 0x000000FF  // TX Polling
 #define USB_TXINTERVAL9_NAKLMT_M \
-                                0x000000FF  // NAK Limit.
+                                0x000000FF  // NAK Limit
 #define USB_TXINTERVAL9_TXPOLL_S \
                                 0
 #define USB_TXINTERVAL9_NAKLMT_S \
@@ -3558,16 +3279,16 @@
 // The following are defines for the bit fields in the USB_O_RXTYPE9 register.
 //
 //*****************************************************************************
-#define USB_RXTYPE9_SPEED_M     0x000000C0  // Operating Speed.
+#define USB_RXTYPE9_SPEED_M     0x000000C0  // Operating Speed
 #define USB_RXTYPE9_SPEED_DFLT  0x00000000  // Default
 #define USB_RXTYPE9_SPEED_FULL  0x00000080  // Full
 #define USB_RXTYPE9_SPEED_LOW   0x000000C0  // Low
-#define USB_RXTYPE9_PROTO_M     0x00000030  // Protocol.
+#define USB_RXTYPE9_PROTO_M     0x00000030  // Protocol
 #define USB_RXTYPE9_PROTO_CTRL  0x00000000  // Control
 #define USB_RXTYPE9_PROTO_ISOC  0x00000010  // Isochronous
 #define USB_RXTYPE9_PROTO_BULK  0x00000020  // Bulk
 #define USB_RXTYPE9_PROTO_INT   0x00000030  // Interrupt
-#define USB_RXTYPE9_TEP_M       0x0000000F  // Target Endpoint Number.
+#define USB_RXTYPE9_TEP_M       0x0000000F  // Target Endpoint Number
 #define USB_RXTYPE9_TEP_S       0
 
 //*****************************************************************************
@@ -3579,7 +3300,7 @@
 #define USB_RXINTERVAL9_TXPOLL_M \
                                 0x000000FF  // RX Polling
 #define USB_RXINTERVAL9_NAKLMT_M \
-                                0x000000FF  // NAK Limit.
+                                0x000000FF  // NAK Limit
 #define USB_RXINTERVAL9_NAKLMT_S \
                                 0
 #define USB_RXINTERVAL9_TXPOLL_S \
@@ -3590,7 +3311,7 @@
 // The following are defines for the bit fields in the USB_O_TXMAXP10 register.
 //
 //*****************************************************************************
-#define USB_TXMAXP10_MAXLOAD_M  0x000007FF  // Maximum Payload.
+#define USB_TXMAXP10_MAXLOAD_M  0x000007FF  // Maximum Payload
 #define USB_TXMAXP10_MAXLOAD_S  0
 
 //*****************************************************************************
@@ -3599,37 +3320,36 @@
 //
 //*****************************************************************************
 #define USB_TXCSRL10_NAKTO      0x00000080  // NAK Timeout
-#define USB_TXCSRL10_INCTX      0x00000080  // Incomplete Transmit.
-#define USB_TXCSRL10_CLRDT      0x00000040  // Clear Data Toggle.
-#define USB_TXCSRL10_STALLED    0x00000020  // Endpoint Stalled.
-#define USB_TXCSRL10_SETUP      0x00000010  // Setup Packet.
-#define USB_TXCSRL10_STALL      0x00000010  // Send Stall.
-#define USB_TXCSRL10_FLUSH      0x00000008  // Flush FIFO.
-#define USB_TXCSRL10_UNDRN      0x00000004  // Underrun.
-#define USB_TXCSRL10_ERROR      0x00000004  // Error.
-#define USB_TXCSRL10_FIFONE     0x00000002  // FIFO Not Empty.
-#define USB_TXCSRL10_TXRDY      0x00000001  // Transmit Packet Ready.
+#define USB_TXCSRL10_CLRDT      0x00000040  // Clear Data Toggle
+#define USB_TXCSRL10_STALLED    0x00000020  // Endpoint Stalled
+#define USB_TXCSRL10_SETUP      0x00000010  // Setup Packet
+#define USB_TXCSRL10_STALL      0x00000010  // Send STALL
+#define USB_TXCSRL10_FLUSH      0x00000008  // Flush FIFO
+#define USB_TXCSRL10_UNDRN      0x00000004  // Underrun
+#define USB_TXCSRL10_ERROR      0x00000004  // Error
+#define USB_TXCSRL10_FIFONE     0x00000002  // FIFO Not Empty
+#define USB_TXCSRL10_TXRDY      0x00000001  // Transmit Packet Ready
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_TXCSRH10 register.
 //
 //*****************************************************************************
-#define USB_TXCSRH10_AUTOSET    0x00000080  // Auto Set.
-#define USB_TXCSRH10_ISO        0x00000040  // ISO.
-#define USB_TXCSRH10_MODE       0x00000020  // Mode.
-#define USB_TXCSRH10_DMAEN      0x00000010  // DMA Request Enable.
-#define USB_TXCSRH10_FDT        0x00000008  // Force Data Toggle.
-#define USB_TXCSRH10_DMAMOD     0x00000004  // DMA Request Mode.
-#define USB_TXCSRH10_DTWE       0x00000002  // Data Toggle Write Enable.
-#define USB_TXCSRH10_DT         0x00000001  // Data Toggle.
+#define USB_TXCSRH10_AUTOSET    0x00000080  // Auto Set
+#define USB_TXCSRH10_ISO        0x00000040  // Isochronous Transfers
+#define USB_TXCSRH10_MODE       0x00000020  // Mode
+#define USB_TXCSRH10_DMAEN      0x00000010  // DMA Request Enable
+#define USB_TXCSRH10_FDT        0x00000008  // Force Data Toggle
+#define USB_TXCSRH10_DMAMOD     0x00000004  // DMA Request Mode
+#define USB_TXCSRH10_DTWE       0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH10_DT         0x00000001  // Data Toggle
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXMAXP10 register.
 //
 //*****************************************************************************
-#define USB_RXMAXP10_MAXLOAD_M  0x000007FF  // Maximum Payload.
+#define USB_RXMAXP10_MAXLOAD_M  0x000007FF  // Maximum Payload
 #define USB_RXMAXP10_MAXLOAD_S  0
 
 //*****************************************************************************
@@ -3637,33 +3357,32 @@
 // The following are defines for the bit fields in the USB_O_RXCSRL10 register.
 //
 //*****************************************************************************
-#define USB_RXCSRL10_CLRDT      0x00000080  // Clear Data Toggle.
-#define USB_RXCSRL10_STALLED    0x00000040  // Endpoint Stalled.
-#define USB_RXCSRL10_STALL      0x00000020  // Send Stall.
-#define USB_RXCSRL10_REQPKT     0x00000020  // Request Packet.
-#define USB_RXCSRL10_FLUSH      0x00000010  // Flush FIFO.
-#define USB_RXCSRL10_NAKTO      0x00000008  // NAK Timeout.
-#define USB_RXCSRL10_DATAERR    0x00000008  // Data Error.
-#define USB_RXCSRL10_OVER       0x00000004  // Overrun.
-#define USB_RXCSRL10_ERROR      0x00000004  // Error.
-#define USB_RXCSRL10_FULL       0x00000002  // FIFO Full.
-#define USB_RXCSRL10_RXRDY      0x00000001  // Receive Packet Ready.
+#define USB_RXCSRL10_CLRDT      0x00000080  // Clear Data Toggle
+#define USB_RXCSRL10_STALLED    0x00000040  // Endpoint Stalled
+#define USB_RXCSRL10_STALL      0x00000020  // Send STALL
+#define USB_RXCSRL10_REQPKT     0x00000020  // Request Packet
+#define USB_RXCSRL10_FLUSH      0x00000010  // Flush FIFO
+#define USB_RXCSRL10_NAKTO      0x00000008  // NAK Timeout
+#define USB_RXCSRL10_DATAERR    0x00000008  // Data Error
+#define USB_RXCSRL10_OVER       0x00000004  // Overrun
+#define USB_RXCSRL10_ERROR      0x00000004  // Error
+#define USB_RXCSRL10_FULL       0x00000002  // FIFO Full
+#define USB_RXCSRL10_RXRDY      0x00000001  // Receive Packet Ready
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXCSRH10 register.
 //
 //*****************************************************************************
-#define USB_RXCSRH10_AUTOCL     0x00000080  // Auto Clear.
-#define USB_RXCSRH10_AUTORQ     0x00000040  // Auto Request.
-#define USB_RXCSRH10_ISO        0x00000040  // ISO.
-#define USB_RXCSRH10_DMAEN      0x00000020  // DMA Request Enable.
-#define USB_RXCSRH10_PIDERR     0x00000010  // PID Error.
+#define USB_RXCSRH10_AUTOCL     0x00000080  // Auto Clear
+#define USB_RXCSRH10_AUTORQ     0x00000040  // Auto Request
+#define USB_RXCSRH10_ISO        0x00000040  // Isochronous Transfers
+#define USB_RXCSRH10_DMAEN      0x00000020  // DMA Request Enable
+#define USB_RXCSRH10_PIDERR     0x00000010  // PID Error
 #define USB_RXCSRH10_DISNYET    0x00000010  // Disable NYET
-#define USB_RXCSRH10_DMAMOD     0x00000008  // DMA Request Mode.
-#define USB_RXCSRH10_DTWE       0x00000004  // Data Toggle Write Enable.
-#define USB_RXCSRH10_DT         0x00000002  // Data Toggle.
-#define USB_RXCSRH10_INCRX      0x00000001  // Incomplete Receive.
+#define USB_RXCSRH10_DMAMOD     0x00000008  // DMA Request Mode
+#define USB_RXCSRH10_DTWE       0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH10_DT         0x00000002  // Data Toggle
 
 //*****************************************************************************
 //
@@ -3671,7 +3390,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RXCOUNT10_COUNT_M   0x00001FFF  // Receive Packet Count.
+#define USB_RXCOUNT10_COUNT_M   0x00001FFF  // Receive Packet Count
 #define USB_RXCOUNT10_COUNT_S   0
 
 //*****************************************************************************
@@ -3679,16 +3398,16 @@
 // The following are defines for the bit fields in the USB_O_TXTYPE10 register.
 //
 //*****************************************************************************
-#define USB_TXTYPE10_SPEED_M    0x000000C0  // Operating Speed.
+#define USB_TXTYPE10_SPEED_M    0x000000C0  // Operating Speed
 #define USB_TXTYPE10_SPEED_DFLT 0x00000000  // Default
 #define USB_TXTYPE10_SPEED_FULL 0x00000080  // Full
 #define USB_TXTYPE10_SPEED_LOW  0x000000C0  // Low
-#define USB_TXTYPE10_PROTO_M    0x00000030  // Protocol.
+#define USB_TXTYPE10_PROTO_M    0x00000030  // Protocol
 #define USB_TXTYPE10_PROTO_CTRL 0x00000000  // Control
 #define USB_TXTYPE10_PROTO_ISOC 0x00000010  // Isochronous
 #define USB_TXTYPE10_PROTO_BULK 0x00000020  // Bulk
 #define USB_TXTYPE10_PROTO_INT  0x00000030  // Interrupt
-#define USB_TXTYPE10_TEP_M      0x0000000F  // Target Endpoint Number.
+#define USB_TXTYPE10_TEP_M      0x0000000F  // Target Endpoint Number
 #define USB_TXTYPE10_TEP_S      0
 
 //*****************************************************************************
@@ -3698,7 +3417,7 @@
 //
 //*****************************************************************************
 #define USB_TXINTERVAL10_NAKLMT_M \
-                                0x000000FF  // NAK Limit.
+                                0x000000FF  // NAK Limit
 #define USB_TXINTERVAL10_TXPOLL_M \
                                 0x000000FF  // TX Polling
 #define USB_TXINTERVAL10_TXPOLL_S \
@@ -3711,16 +3430,16 @@
 // The following are defines for the bit fields in the USB_O_RXTYPE10 register.
 //
 //*****************************************************************************
-#define USB_RXTYPE10_SPEED_M    0x000000C0  // Operating Speed.
+#define USB_RXTYPE10_SPEED_M    0x000000C0  // Operating Speed
 #define USB_RXTYPE10_SPEED_DFLT 0x00000000  // Default
 #define USB_RXTYPE10_SPEED_FULL 0x00000080  // Full
 #define USB_RXTYPE10_SPEED_LOW  0x000000C0  // Low
-#define USB_RXTYPE10_PROTO_M    0x00000030  // Protocol.
+#define USB_RXTYPE10_PROTO_M    0x00000030  // Protocol
 #define USB_RXTYPE10_PROTO_CTRL 0x00000000  // Control
 #define USB_RXTYPE10_PROTO_ISOC 0x00000010  // Isochronous
 #define USB_RXTYPE10_PROTO_BULK 0x00000020  // Bulk
 #define USB_RXTYPE10_PROTO_INT  0x00000030  // Interrupt
-#define USB_RXTYPE10_TEP_M      0x0000000F  // Target Endpoint Number.
+#define USB_RXTYPE10_TEP_M      0x0000000F  // Target Endpoint Number
 #define USB_RXTYPE10_TEP_S      0
 
 //*****************************************************************************
@@ -3730,7 +3449,7 @@
 //
 //*****************************************************************************
 #define USB_RXINTERVAL10_NAKLMT_M \
-                                0x000000FF  // NAK Limit.
+                                0x000000FF  // NAK Limit
 #define USB_RXINTERVAL10_TXPOLL_M \
                                 0x000000FF  // RX Polling
 #define USB_RXINTERVAL10_TXPOLL_S \
@@ -3743,7 +3462,7 @@
 // The following are defines for the bit fields in the USB_O_TXMAXP11 register.
 //
 //*****************************************************************************
-#define USB_TXMAXP11_MAXLOAD_M  0x000007FF  // Maximum Payload.
+#define USB_TXMAXP11_MAXLOAD_M  0x000007FF  // Maximum Payload
 #define USB_TXMAXP11_MAXLOAD_S  0
 
 //*****************************************************************************
@@ -3752,37 +3471,36 @@
 //
 //*****************************************************************************
 #define USB_TXCSRL11_NAKTO      0x00000080  // NAK Timeout
-#define USB_TXCSRL11_INCTX      0x00000080  // Incomplete Transmit.
-#define USB_TXCSRL11_CLRDT      0x00000040  // Clear Data Toggle.
-#define USB_TXCSRL11_STALLED    0x00000020  // Endpoint Stalled.
-#define USB_TXCSRL11_STALL      0x00000010  // Send Stall.
-#define USB_TXCSRL11_SETUP      0x00000010  // Setup Packet.
-#define USB_TXCSRL11_FLUSH      0x00000008  // Flush FIFO.
-#define USB_TXCSRL11_ERROR      0x00000004  // Error.
-#define USB_TXCSRL11_UNDRN      0x00000004  // Underrun.
-#define USB_TXCSRL11_FIFONE     0x00000002  // FIFO Not Empty.
-#define USB_TXCSRL11_TXRDY      0x00000001  // Transmit Packet Ready.
+#define USB_TXCSRL11_CLRDT      0x00000040  // Clear Data Toggle
+#define USB_TXCSRL11_STALLED    0x00000020  // Endpoint Stalled
+#define USB_TXCSRL11_STALL      0x00000010  // Send STALL
+#define USB_TXCSRL11_SETUP      0x00000010  // Setup Packet
+#define USB_TXCSRL11_FLUSH      0x00000008  // Flush FIFO
+#define USB_TXCSRL11_ERROR      0x00000004  // Error
+#define USB_TXCSRL11_UNDRN      0x00000004  // Underrun
+#define USB_TXCSRL11_FIFONE     0x00000002  // FIFO Not Empty
+#define USB_TXCSRL11_TXRDY      0x00000001  // Transmit Packet Ready
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_TXCSRH11 register.
 //
 //*****************************************************************************
-#define USB_TXCSRH11_AUTOSET    0x00000080  // Auto Set.
-#define USB_TXCSRH11_ISO        0x00000040  // ISO.
-#define USB_TXCSRH11_MODE       0x00000020  // Mode.
-#define USB_TXCSRH11_DMAEN      0x00000010  // DMA Request Enable.
-#define USB_TXCSRH11_FDT        0x00000008  // Force Data Toggle.
-#define USB_TXCSRH11_DMAMOD     0x00000004  // DMA Request Mode.
-#define USB_TXCSRH11_DTWE       0x00000002  // Data Toggle Write Enable.
-#define USB_TXCSRH11_DT         0x00000001  // Data Toggle.
+#define USB_TXCSRH11_AUTOSET    0x00000080  // Auto Set
+#define USB_TXCSRH11_ISO        0x00000040  // Isochronous Transfers
+#define USB_TXCSRH11_MODE       0x00000020  // Mode
+#define USB_TXCSRH11_DMAEN      0x00000010  // DMA Request Enable
+#define USB_TXCSRH11_FDT        0x00000008  // Force Data Toggle
+#define USB_TXCSRH11_DMAMOD     0x00000004  // DMA Request Mode
+#define USB_TXCSRH11_DTWE       0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH11_DT         0x00000001  // Data Toggle
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXMAXP11 register.
 //
 //*****************************************************************************
-#define USB_RXMAXP11_MAXLOAD_M  0x000007FF  // Maximum Payload.
+#define USB_RXMAXP11_MAXLOAD_M  0x000007FF  // Maximum Payload
 #define USB_RXMAXP11_MAXLOAD_S  0
 
 //*****************************************************************************
@@ -3790,33 +3508,32 @@
 // The following are defines for the bit fields in the USB_O_RXCSRL11 register.
 //
 //*****************************************************************************
-#define USB_RXCSRL11_CLRDT      0x00000080  // Clear Data Toggle.
-#define USB_RXCSRL11_STALLED    0x00000040  // Endpoint Stalled.
-#define USB_RXCSRL11_STALL      0x00000020  // Send Stall.
-#define USB_RXCSRL11_REQPKT     0x00000020  // Request Packet.
-#define USB_RXCSRL11_FLUSH      0x00000010  // Flush FIFO.
-#define USB_RXCSRL11_DATAERR    0x00000008  // Data Error.
-#define USB_RXCSRL11_NAKTO      0x00000008  // NAK Timeout.
-#define USB_RXCSRL11_OVER       0x00000004  // Overrun.
-#define USB_RXCSRL11_ERROR      0x00000004  // Error.
-#define USB_RXCSRL11_FULL       0x00000002  // FIFO Full.
-#define USB_RXCSRL11_RXRDY      0x00000001  // Receive Packet Ready.
+#define USB_RXCSRL11_CLRDT      0x00000080  // Clear Data Toggle
+#define USB_RXCSRL11_STALLED    0x00000040  // Endpoint Stalled
+#define USB_RXCSRL11_STALL      0x00000020  // Send STALL
+#define USB_RXCSRL11_REQPKT     0x00000020  // Request Packet
+#define USB_RXCSRL11_FLUSH      0x00000010  // Flush FIFO
+#define USB_RXCSRL11_DATAERR    0x00000008  // Data Error
+#define USB_RXCSRL11_NAKTO      0x00000008  // NAK Timeout
+#define USB_RXCSRL11_OVER       0x00000004  // Overrun
+#define USB_RXCSRL11_ERROR      0x00000004  // Error
+#define USB_RXCSRL11_FULL       0x00000002  // FIFO Full
+#define USB_RXCSRL11_RXRDY      0x00000001  // Receive Packet Ready
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXCSRH11 register.
 //
 //*****************************************************************************
-#define USB_RXCSRH11_AUTOCL     0x00000080  // Auto Clear.
-#define USB_RXCSRH11_ISO        0x00000040  // ISO.
-#define USB_RXCSRH11_AUTORQ     0x00000040  // Auto Request.
-#define USB_RXCSRH11_DMAEN      0x00000020  // DMA Request Enable.
+#define USB_RXCSRH11_AUTOCL     0x00000080  // Auto Clear
+#define USB_RXCSRH11_ISO        0x00000040  // Isochronous Transfers
+#define USB_RXCSRH11_AUTORQ     0x00000040  // Auto Request
+#define USB_RXCSRH11_DMAEN      0x00000020  // DMA Request Enable
 #define USB_RXCSRH11_DISNYET    0x00000010  // Disable NYET
-#define USB_RXCSRH11_PIDERR     0x00000010  // PID Error.
-#define USB_RXCSRH11_DMAMOD     0x00000008  // DMA Request Mode.
-#define USB_RXCSRH11_DTWE       0x00000004  // Data Toggle Write Enable.
-#define USB_RXCSRH11_DT         0x00000002  // Data Toggle.
-#define USB_RXCSRH11_INCRX      0x00000001  // Incomplete Receive.
+#define USB_RXCSRH11_PIDERR     0x00000010  // PID Error
+#define USB_RXCSRH11_DMAMOD     0x00000008  // DMA Request Mode
+#define USB_RXCSRH11_DTWE       0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH11_DT         0x00000002  // Data Toggle
 
 //*****************************************************************************
 //
@@ -3824,7 +3541,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RXCOUNT11_COUNT_M   0x00001FFF  // Receive Packet Count.
+#define USB_RXCOUNT11_COUNT_M   0x00001FFF  // Receive Packet Count
 #define USB_RXCOUNT11_COUNT_S   0
 
 //*****************************************************************************
@@ -3832,16 +3549,16 @@
 // The following are defines for the bit fields in the USB_O_TXTYPE11 register.
 //
 //*****************************************************************************
-#define USB_TXTYPE11_SPEED_M    0x000000C0  // Operating Speed.
+#define USB_TXTYPE11_SPEED_M    0x000000C0  // Operating Speed
 #define USB_TXTYPE11_SPEED_DFLT 0x00000000  // Default
 #define USB_TXTYPE11_SPEED_FULL 0x00000080  // Full
 #define USB_TXTYPE11_SPEED_LOW  0x000000C0  // Low
-#define USB_TXTYPE11_PROTO_M    0x00000030  // Protocol.
+#define USB_TXTYPE11_PROTO_M    0x00000030  // Protocol
 #define USB_TXTYPE11_PROTO_CTRL 0x00000000  // Control
 #define USB_TXTYPE11_PROTO_ISOC 0x00000010  // Isochronous
 #define USB_TXTYPE11_PROTO_BULK 0x00000020  // Bulk
 #define USB_TXTYPE11_PROTO_INT  0x00000030  // Interrupt
-#define USB_TXTYPE11_TEP_M      0x0000000F  // Target Endpoint Number.
+#define USB_TXTYPE11_TEP_M      0x0000000F  // Target Endpoint Number
 #define USB_TXTYPE11_TEP_S      0
 
 //*****************************************************************************
@@ -3853,7 +3570,7 @@
 #define USB_TXINTERVAL11_TXPOLL_M \
                                 0x000000FF  // TX Polling
 #define USB_TXINTERVAL11_NAKLMT_M \
-                                0x000000FF  // NAK Limit.
+                                0x000000FF  // NAK Limit
 #define USB_TXINTERVAL11_NAKLMT_S \
                                 0
 #define USB_TXINTERVAL11_TXPOLL_S \
@@ -3864,16 +3581,16 @@
 // The following are defines for the bit fields in the USB_O_RXTYPE11 register.
 //
 //*****************************************************************************
-#define USB_RXTYPE11_SPEED_M    0x000000C0  // Operating Speed.
+#define USB_RXTYPE11_SPEED_M    0x000000C0  // Operating Speed
 #define USB_RXTYPE11_SPEED_DFLT 0x00000000  // Default
 #define USB_RXTYPE11_SPEED_FULL 0x00000080  // Full
 #define USB_RXTYPE11_SPEED_LOW  0x000000C0  // Low
-#define USB_RXTYPE11_PROTO_M    0x00000030  // Protocol.
+#define USB_RXTYPE11_PROTO_M    0x00000030  // Protocol
 #define USB_RXTYPE11_PROTO_CTRL 0x00000000  // Control
 #define USB_RXTYPE11_PROTO_ISOC 0x00000010  // Isochronous
 #define USB_RXTYPE11_PROTO_BULK 0x00000020  // Bulk
 #define USB_RXTYPE11_PROTO_INT  0x00000030  // Interrupt
-#define USB_RXTYPE11_TEP_M      0x0000000F  // Target Endpoint Number.
+#define USB_RXTYPE11_TEP_M      0x0000000F  // Target Endpoint Number
 #define USB_RXTYPE11_TEP_S      0
 
 //*****************************************************************************
@@ -3883,7 +3600,7 @@
 //
 //*****************************************************************************
 #define USB_RXINTERVAL11_NAKLMT_M \
-                                0x000000FF  // NAK Limit.
+                                0x000000FF  // NAK Limit
 #define USB_RXINTERVAL11_TXPOLL_M \
                                 0x000000FF  // RX Polling
 #define USB_RXINTERVAL11_TXPOLL_S \
@@ -3896,7 +3613,7 @@
 // The following are defines for the bit fields in the USB_O_TXMAXP12 register.
 //
 //*****************************************************************************
-#define USB_TXMAXP12_MAXLOAD_M  0x000007FF  // Maximum Payload.
+#define USB_TXMAXP12_MAXLOAD_M  0x000007FF  // Maximum Payload
 #define USB_TXMAXP12_MAXLOAD_S  0
 
 //*****************************************************************************
@@ -3904,38 +3621,37 @@
 // The following are defines for the bit fields in the USB_O_TXCSRL12 register.
 //
 //*****************************************************************************
-#define USB_TXCSRL12_INCTX      0x00000080  // Incomplete Transmit.
 #define USB_TXCSRL12_NAKTO      0x00000080  // NAK Timeout
-#define USB_TXCSRL12_CLRDT      0x00000040  // Clear Data Toggle.
-#define USB_TXCSRL12_STALLED    0x00000020  // Endpoint Stalled.
-#define USB_TXCSRL12_SETUP      0x00000010  // Setup Packet.
-#define USB_TXCSRL12_STALL      0x00000010  // Send Stall.
-#define USB_TXCSRL12_FLUSH      0x00000008  // Flush FIFO.
-#define USB_TXCSRL12_UNDRN      0x00000004  // Underrun.
-#define USB_TXCSRL12_ERROR      0x00000004  // Error.
-#define USB_TXCSRL12_FIFONE     0x00000002  // FIFO Not Empty.
-#define USB_TXCSRL12_TXRDY      0x00000001  // Transmit Packet Ready.
+#define USB_TXCSRL12_CLRDT      0x00000040  // Clear Data Toggle
+#define USB_TXCSRL12_STALLED    0x00000020  // Endpoint Stalled
+#define USB_TXCSRL12_SETUP      0x00000010  // Setup Packet
+#define USB_TXCSRL12_STALL      0x00000010  // Send STALL
+#define USB_TXCSRL12_FLUSH      0x00000008  // Flush FIFO
+#define USB_TXCSRL12_UNDRN      0x00000004  // Underrun
+#define USB_TXCSRL12_ERROR      0x00000004  // Error
+#define USB_TXCSRL12_FIFONE     0x00000002  // FIFO Not Empty
+#define USB_TXCSRL12_TXRDY      0x00000001  // Transmit Packet Ready
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_TXCSRH12 register.
 //
 //*****************************************************************************
-#define USB_TXCSRH12_AUTOSET    0x00000080  // Auto Set.
-#define USB_TXCSRH12_ISO        0x00000040  // ISO.
-#define USB_TXCSRH12_MODE       0x00000020  // Mode.
-#define USB_TXCSRH12_DMAEN      0x00000010  // DMA Request Enable.
-#define USB_TXCSRH12_FDT        0x00000008  // Force Data Toggle.
-#define USB_TXCSRH12_DMAMOD     0x00000004  // DMA Request Mode.
-#define USB_TXCSRH12_DTWE       0x00000002  // Data Toggle Write Enable.
-#define USB_TXCSRH12_DT         0x00000001  // Data Toggle.
+#define USB_TXCSRH12_AUTOSET    0x00000080  // Auto Set
+#define USB_TXCSRH12_ISO        0x00000040  // Isochronous Transfers
+#define USB_TXCSRH12_MODE       0x00000020  // Mode
+#define USB_TXCSRH12_DMAEN      0x00000010  // DMA Request Enable
+#define USB_TXCSRH12_FDT        0x00000008  // Force Data Toggle
+#define USB_TXCSRH12_DMAMOD     0x00000004  // DMA Request Mode
+#define USB_TXCSRH12_DTWE       0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH12_DT         0x00000001  // Data Toggle
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXMAXP12 register.
 //
 //*****************************************************************************
-#define USB_RXMAXP12_MAXLOAD_M  0x000007FF  // Maximum Payload.
+#define USB_RXMAXP12_MAXLOAD_M  0x000007FF  // Maximum Payload
 #define USB_RXMAXP12_MAXLOAD_S  0
 
 //*****************************************************************************
@@ -3943,33 +3659,32 @@
 // The following are defines for the bit fields in the USB_O_RXCSRL12 register.
 //
 //*****************************************************************************
-#define USB_RXCSRL12_CLRDT      0x00000080  // Clear Data Toggle.
-#define USB_RXCSRL12_STALLED    0x00000040  // Endpoint Stalled.
-#define USB_RXCSRL12_STALL      0x00000020  // Send Stall.
-#define USB_RXCSRL12_REQPKT     0x00000020  // Request Packet.
-#define USB_RXCSRL12_FLUSH      0x00000010  // Flush FIFO.
-#define USB_RXCSRL12_NAKTO      0x00000008  // NAK Timeout.
-#define USB_RXCSRL12_DATAERR    0x00000008  // Data Error.
-#define USB_RXCSRL12_ERROR      0x00000004  // Error.
-#define USB_RXCSRL12_OVER       0x00000004  // Overrun.
-#define USB_RXCSRL12_FULL       0x00000002  // FIFO Full.
-#define USB_RXCSRL12_RXRDY      0x00000001  // Receive Packet Ready.
+#define USB_RXCSRL12_CLRDT      0x00000080  // Clear Data Toggle
+#define USB_RXCSRL12_STALLED    0x00000040  // Endpoint Stalled
+#define USB_RXCSRL12_STALL      0x00000020  // Send STALL
+#define USB_RXCSRL12_REQPKT     0x00000020  // Request Packet
+#define USB_RXCSRL12_FLUSH      0x00000010  // Flush FIFO
+#define USB_RXCSRL12_NAKTO      0x00000008  // NAK Timeout
+#define USB_RXCSRL12_DATAERR    0x00000008  // Data Error
+#define USB_RXCSRL12_ERROR      0x00000004  // Error
+#define USB_RXCSRL12_OVER       0x00000004  // Overrun
+#define USB_RXCSRL12_FULL       0x00000002  // FIFO Full
+#define USB_RXCSRL12_RXRDY      0x00000001  // Receive Packet Ready
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXCSRH12 register.
 //
 //*****************************************************************************
-#define USB_RXCSRH12_AUTOCL     0x00000080  // Auto Clear.
-#define USB_RXCSRH12_ISO        0x00000040  // ISO.
-#define USB_RXCSRH12_AUTORQ     0x00000040  // Auto Request.
-#define USB_RXCSRH12_DMAEN      0x00000020  // DMA Request Enable.
-#define USB_RXCSRH12_PIDERR     0x00000010  // PID Error.
+#define USB_RXCSRH12_AUTOCL     0x00000080  // Auto Clear
+#define USB_RXCSRH12_ISO        0x00000040  // Isochronous Transfers
+#define USB_RXCSRH12_AUTORQ     0x00000040  // Auto Request
+#define USB_RXCSRH12_DMAEN      0x00000020  // DMA Request Enable
+#define USB_RXCSRH12_PIDERR     0x00000010  // PID Error
 #define USB_RXCSRH12_DISNYET    0x00000010  // Disable NYET
-#define USB_RXCSRH12_DMAMOD     0x00000008  // DMA Request Mode.
-#define USB_RXCSRH12_DTWE       0x00000004  // Data Toggle Write Enable.
-#define USB_RXCSRH12_DT         0x00000002  // Data Toggle.
-#define USB_RXCSRH12_INCRX      0x00000001  // Incomplete Receive.
+#define USB_RXCSRH12_DMAMOD     0x00000008  // DMA Request Mode
+#define USB_RXCSRH12_DTWE       0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH12_DT         0x00000002  // Data Toggle
 
 //*****************************************************************************
 //
@@ -3977,7 +3692,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RXCOUNT12_COUNT_M   0x00001FFF  // Receive Packet Count.
+#define USB_RXCOUNT12_COUNT_M   0x00001FFF  // Receive Packet Count
 #define USB_RXCOUNT12_COUNT_S   0
 
 //*****************************************************************************
@@ -3985,16 +3700,16 @@
 // The following are defines for the bit fields in the USB_O_TXTYPE12 register.
 //
 //*****************************************************************************
-#define USB_TXTYPE12_SPEED_M    0x000000C0  // Operating Speed.
+#define USB_TXTYPE12_SPEED_M    0x000000C0  // Operating Speed
 #define USB_TXTYPE12_SPEED_DFLT 0x00000000  // Default
 #define USB_TXTYPE12_SPEED_FULL 0x00000080  // Full
 #define USB_TXTYPE12_SPEED_LOW  0x000000C0  // Low
-#define USB_TXTYPE12_PROTO_M    0x00000030  // Protocol.
+#define USB_TXTYPE12_PROTO_M    0x00000030  // Protocol
 #define USB_TXTYPE12_PROTO_CTRL 0x00000000  // Control
 #define USB_TXTYPE12_PROTO_ISOC 0x00000010  // Isochronous
 #define USB_TXTYPE12_PROTO_BULK 0x00000020  // Bulk
 #define USB_TXTYPE12_PROTO_INT  0x00000030  // Interrupt
-#define USB_TXTYPE12_TEP_M      0x0000000F  // Target Endpoint Number.
+#define USB_TXTYPE12_TEP_M      0x0000000F  // Target Endpoint Number
 #define USB_TXTYPE12_TEP_S      0
 
 //*****************************************************************************
@@ -4006,7 +3721,7 @@
 #define USB_TXINTERVAL12_TXPOLL_M \
                                 0x000000FF  // TX Polling
 #define USB_TXINTERVAL12_NAKLMT_M \
-                                0x000000FF  // NAK Limit.
+                                0x000000FF  // NAK Limit
 #define USB_TXINTERVAL12_TXPOLL_S \
                                 0
 #define USB_TXINTERVAL12_NAKLMT_S \
@@ -4017,16 +3732,16 @@
 // The following are defines for the bit fields in the USB_O_RXTYPE12 register.
 //
 //*****************************************************************************
-#define USB_RXTYPE12_SPEED_M    0x000000C0  // Operating Speed.
+#define USB_RXTYPE12_SPEED_M    0x000000C0  // Operating Speed
 #define USB_RXTYPE12_SPEED_DFLT 0x00000000  // Default
 #define USB_RXTYPE12_SPEED_FULL 0x00000080  // Full
 #define USB_RXTYPE12_SPEED_LOW  0x000000C0  // Low
-#define USB_RXTYPE12_PROTO_M    0x00000030  // Protocol.
+#define USB_RXTYPE12_PROTO_M    0x00000030  // Protocol
 #define USB_RXTYPE12_PROTO_CTRL 0x00000000  // Control
 #define USB_RXTYPE12_PROTO_ISOC 0x00000010  // Isochronous
 #define USB_RXTYPE12_PROTO_BULK 0x00000020  // Bulk
 #define USB_RXTYPE12_PROTO_INT  0x00000030  // Interrupt
-#define USB_RXTYPE12_TEP_M      0x0000000F  // Target Endpoint Number.
+#define USB_RXTYPE12_TEP_M      0x0000000F  // Target Endpoint Number
 #define USB_RXTYPE12_TEP_S      0
 
 //*****************************************************************************
@@ -4036,7 +3751,7 @@
 //
 //*****************************************************************************
 #define USB_RXINTERVAL12_NAKLMT_M \
-                                0x000000FF  // NAK Limit.
+                                0x000000FF  // NAK Limit
 #define USB_RXINTERVAL12_TXPOLL_M \
                                 0x000000FF  // RX Polling
 #define USB_RXINTERVAL12_NAKLMT_S \
@@ -4049,7 +3764,7 @@
 // The following are defines for the bit fields in the USB_O_TXMAXP13 register.
 //
 //*****************************************************************************
-#define USB_TXMAXP13_MAXLOAD_M  0x000007FF  // Maximum Payload.
+#define USB_TXMAXP13_MAXLOAD_M  0x000007FF  // Maximum Payload
 #define USB_TXMAXP13_MAXLOAD_S  0
 
 //*****************************************************************************
@@ -4058,37 +3773,36 @@
 //
 //*****************************************************************************
 #define USB_TXCSRL13_NAKTO      0x00000080  // NAK Timeout
-#define USB_TXCSRL13_INCTX      0x00000080  // Incomplete Transmit.
-#define USB_TXCSRL13_CLRDT      0x00000040  // Clear Data Toggle.
-#define USB_TXCSRL13_STALLED    0x00000020  // Endpoint Stalled.
-#define USB_TXCSRL13_SETUP      0x00000010  // Setup Packet.
-#define USB_TXCSRL13_STALL      0x00000010  // Send Stall.
-#define USB_TXCSRL13_FLUSH      0x00000008  // Flush FIFO.
-#define USB_TXCSRL13_UNDRN      0x00000004  // Underrun.
-#define USB_TXCSRL13_ERROR      0x00000004  // Error.
-#define USB_TXCSRL13_FIFONE     0x00000002  // FIFO Not Empty.
-#define USB_TXCSRL13_TXRDY      0x00000001  // Transmit Packet Ready.
+#define USB_TXCSRL13_CLRDT      0x00000040  // Clear Data Toggle
+#define USB_TXCSRL13_STALLED    0x00000020  // Endpoint Stalled
+#define USB_TXCSRL13_SETUP      0x00000010  // Setup Packet
+#define USB_TXCSRL13_STALL      0x00000010  // Send STALL
+#define USB_TXCSRL13_FLUSH      0x00000008  // Flush FIFO
+#define USB_TXCSRL13_UNDRN      0x00000004  // Underrun
+#define USB_TXCSRL13_ERROR      0x00000004  // Error
+#define USB_TXCSRL13_FIFONE     0x00000002  // FIFO Not Empty
+#define USB_TXCSRL13_TXRDY      0x00000001  // Transmit Packet Ready
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_TXCSRH13 register.
 //
 //*****************************************************************************
-#define USB_TXCSRH13_AUTOSET    0x00000080  // Auto Set.
-#define USB_TXCSRH13_ISO        0x00000040  // ISO.
-#define USB_TXCSRH13_MODE       0x00000020  // Mode.
-#define USB_TXCSRH13_DMAEN      0x00000010  // DMA Request Enable.
-#define USB_TXCSRH13_FDT        0x00000008  // Force Data Toggle.
-#define USB_TXCSRH13_DMAMOD     0x00000004  // DMA Request Mode.
-#define USB_TXCSRH13_DTWE       0x00000002  // Data Toggle Write Enable.
-#define USB_TXCSRH13_DT         0x00000001  // Data Toggle.
+#define USB_TXCSRH13_AUTOSET    0x00000080  // Auto Set
+#define USB_TXCSRH13_ISO        0x00000040  // Isochronous Transfers
+#define USB_TXCSRH13_MODE       0x00000020  // Mode
+#define USB_TXCSRH13_DMAEN      0x00000010  // DMA Request Enable
+#define USB_TXCSRH13_FDT        0x00000008  // Force Data Toggle
+#define USB_TXCSRH13_DMAMOD     0x00000004  // DMA Request Mode
+#define USB_TXCSRH13_DTWE       0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH13_DT         0x00000001  // Data Toggle
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXMAXP13 register.
 //
 //*****************************************************************************
-#define USB_RXMAXP13_MAXLOAD_M  0x000007FF  // Maximum Payload.
+#define USB_RXMAXP13_MAXLOAD_M  0x000007FF  // Maximum Payload
 #define USB_RXMAXP13_MAXLOAD_S  0
 
 //*****************************************************************************
@@ -4096,33 +3810,32 @@
 // The following are defines for the bit fields in the USB_O_RXCSRL13 register.
 //
 //*****************************************************************************
-#define USB_RXCSRL13_CLRDT      0x00000080  // Clear Data Toggle.
-#define USB_RXCSRL13_STALLED    0x00000040  // Endpoint Stalled.
-#define USB_RXCSRL13_REQPKT     0x00000020  // Request Packet.
-#define USB_RXCSRL13_STALL      0x00000020  // Send Stall.
-#define USB_RXCSRL13_FLUSH      0x00000010  // Flush FIFO.
-#define USB_RXCSRL13_NAKTO      0x00000008  // NAK Timeout.
-#define USB_RXCSRL13_DATAERR    0x00000008  // Data Error.
-#define USB_RXCSRL13_OVER       0x00000004  // Overrun.
-#define USB_RXCSRL13_ERROR      0x00000004  // Error.
-#define USB_RXCSRL13_FULL       0x00000002  // FIFO Full.
-#define USB_RXCSRL13_RXRDY      0x00000001  // Receive Packet Ready.
+#define USB_RXCSRL13_CLRDT      0x00000080  // Clear Data Toggle
+#define USB_RXCSRL13_STALLED    0x00000040  // Endpoint Stalled
+#define USB_RXCSRL13_REQPKT     0x00000020  // Request Packet
+#define USB_RXCSRL13_STALL      0x00000020  // Send STALL
+#define USB_RXCSRL13_FLUSH      0x00000010  // Flush FIFO
+#define USB_RXCSRL13_NAKTO      0x00000008  // NAK Timeout
+#define USB_RXCSRL13_DATAERR    0x00000008  // Data Error
+#define USB_RXCSRL13_OVER       0x00000004  // Overrun
+#define USB_RXCSRL13_ERROR      0x00000004  // Error
+#define USB_RXCSRL13_FULL       0x00000002  // FIFO Full
+#define USB_RXCSRL13_RXRDY      0x00000001  // Receive Packet Ready
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXCSRH13 register.
 //
 //*****************************************************************************
-#define USB_RXCSRH13_AUTOCL     0x00000080  // Auto Clear.
-#define USB_RXCSRH13_ISO        0x00000040  // ISO.
-#define USB_RXCSRH13_AUTORQ     0x00000040  // Auto Request.
-#define USB_RXCSRH13_DMAEN      0x00000020  // DMA Request Enable.
+#define USB_RXCSRH13_AUTOCL     0x00000080  // Auto Clear
+#define USB_RXCSRH13_ISO        0x00000040  // Isochronous Transfers
+#define USB_RXCSRH13_AUTORQ     0x00000040  // Auto Request
+#define USB_RXCSRH13_DMAEN      0x00000020  // DMA Request Enable
 #define USB_RXCSRH13_DISNYET    0x00000010  // Disable NYET
-#define USB_RXCSRH13_PIDERR     0x00000010  // PID Error.
-#define USB_RXCSRH13_DMAMOD     0x00000008  // DMA Request Mode.
-#define USB_RXCSRH13_DTWE       0x00000004  // Data Toggle Write Enable.
-#define USB_RXCSRH13_DT         0x00000002  // Data Toggle.
-#define USB_RXCSRH13_INCRX      0x00000001  // Incomplete Receive.
+#define USB_RXCSRH13_PIDERR     0x00000010  // PID Error
+#define USB_RXCSRH13_DMAMOD     0x00000008  // DMA Request Mode
+#define USB_RXCSRH13_DTWE       0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH13_DT         0x00000002  // Data Toggle
 
 //*****************************************************************************
 //
@@ -4130,7 +3843,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RXCOUNT13_COUNT_M   0x00001FFF  // Receive Packet Count.
+#define USB_RXCOUNT13_COUNT_M   0x00001FFF  // Receive Packet Count
 #define USB_RXCOUNT13_COUNT_S   0
 
 //*****************************************************************************
@@ -4138,16 +3851,16 @@
 // The following are defines for the bit fields in the USB_O_TXTYPE13 register.
 //
 //*****************************************************************************
-#define USB_TXTYPE13_SPEED_M    0x000000C0  // Operating Speed.
+#define USB_TXTYPE13_SPEED_M    0x000000C0  // Operating Speed
 #define USB_TXTYPE13_SPEED_DFLT 0x00000000  // Default
 #define USB_TXTYPE13_SPEED_FULL 0x00000080  // Full
 #define USB_TXTYPE13_SPEED_LOW  0x000000C0  // Low
-#define USB_TXTYPE13_PROTO_M    0x00000030  // Protocol.
+#define USB_TXTYPE13_PROTO_M    0x00000030  // Protocol
 #define USB_TXTYPE13_PROTO_CTRL 0x00000000  // Control
 #define USB_TXTYPE13_PROTO_ISOC 0x00000010  // Isochronous
 #define USB_TXTYPE13_PROTO_BULK 0x00000020  // Bulk
 #define USB_TXTYPE13_PROTO_INT  0x00000030  // Interrupt
-#define USB_TXTYPE13_TEP_M      0x0000000F  // Target Endpoint Number.
+#define USB_TXTYPE13_TEP_M      0x0000000F  // Target Endpoint Number
 #define USB_TXTYPE13_TEP_S      0
 
 //*****************************************************************************
@@ -4157,7 +3870,7 @@
 //
 //*****************************************************************************
 #define USB_TXINTERVAL13_NAKLMT_M \
-                                0x000000FF  // NAK Limit.
+                                0x000000FF  // NAK Limit
 #define USB_TXINTERVAL13_TXPOLL_M \
                                 0x000000FF  // TX Polling
 #define USB_TXINTERVAL13_TXPOLL_S \
@@ -4170,16 +3883,16 @@
 // The following are defines for the bit fields in the USB_O_RXTYPE13 register.
 //
 //*****************************************************************************
-#define USB_RXTYPE13_SPEED_M    0x000000C0  // Operating Speed.
+#define USB_RXTYPE13_SPEED_M    0x000000C0  // Operating Speed
 #define USB_RXTYPE13_SPEED_DFLT 0x00000000  // Default
 #define USB_RXTYPE13_SPEED_FULL 0x00000080  // Full
 #define USB_RXTYPE13_SPEED_LOW  0x000000C0  // Low
-#define USB_RXTYPE13_PROTO_M    0x00000030  // Protocol.
+#define USB_RXTYPE13_PROTO_M    0x00000030  // Protocol
 #define USB_RXTYPE13_PROTO_CTRL 0x00000000  // Control
 #define USB_RXTYPE13_PROTO_ISOC 0x00000010  // Isochronous
 #define USB_RXTYPE13_PROTO_BULK 0x00000020  // Bulk
 #define USB_RXTYPE13_PROTO_INT  0x00000030  // Interrupt
-#define USB_RXTYPE13_TEP_M      0x0000000F  // Target Endpoint Number.
+#define USB_RXTYPE13_TEP_M      0x0000000F  // Target Endpoint Number
 #define USB_RXTYPE13_TEP_S      0
 
 //*****************************************************************************
@@ -4191,7 +3904,7 @@
 #define USB_RXINTERVAL13_TXPOLL_M \
                                 0x000000FF  // RX Polling
 #define USB_RXINTERVAL13_NAKLMT_M \
-                                0x000000FF  // NAK Limit.
+                                0x000000FF  // NAK Limit
 #define USB_RXINTERVAL13_TXPOLL_S \
                                 0
 #define USB_RXINTERVAL13_NAKLMT_S \
@@ -4202,7 +3915,7 @@
 // The following are defines for the bit fields in the USB_O_TXMAXP14 register.
 //
 //*****************************************************************************
-#define USB_TXMAXP14_MAXLOAD_M  0x000007FF  // Maximum Payload.
+#define USB_TXMAXP14_MAXLOAD_M  0x000007FF  // Maximum Payload
 #define USB_TXMAXP14_MAXLOAD_S  0
 
 //*****************************************************************************
@@ -4211,37 +3924,36 @@
 //
 //*****************************************************************************
 #define USB_TXCSRL14_NAKTO      0x00000080  // NAK Timeout
-#define USB_TXCSRL14_INCTX      0x00000080  // Incomplete Transmit.
-#define USB_TXCSRL14_CLRDT      0x00000040  // Clear Data Toggle.
-#define USB_TXCSRL14_STALLED    0x00000020  // Endpoint Stalled.
-#define USB_TXCSRL14_STALL      0x00000010  // Send Stall.
-#define USB_TXCSRL14_SETUP      0x00000010  // Setup Packet.
-#define USB_TXCSRL14_FLUSH      0x00000008  // Flush FIFO.
-#define USB_TXCSRL14_ERROR      0x00000004  // Error.
-#define USB_TXCSRL14_UNDRN      0x00000004  // Underrun.
-#define USB_TXCSRL14_FIFONE     0x00000002  // FIFO Not Empty.
-#define USB_TXCSRL14_TXRDY      0x00000001  // Transmit Packet Ready.
+#define USB_TXCSRL14_CLRDT      0x00000040  // Clear Data Toggle
+#define USB_TXCSRL14_STALLED    0x00000020  // Endpoint Stalled
+#define USB_TXCSRL14_STALL      0x00000010  // Send STALL
+#define USB_TXCSRL14_SETUP      0x00000010  // Setup Packet
+#define USB_TXCSRL14_FLUSH      0x00000008  // Flush FIFO
+#define USB_TXCSRL14_ERROR      0x00000004  // Error
+#define USB_TXCSRL14_UNDRN      0x00000004  // Underrun
+#define USB_TXCSRL14_FIFONE     0x00000002  // FIFO Not Empty
+#define USB_TXCSRL14_TXRDY      0x00000001  // Transmit Packet Ready
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_TXCSRH14 register.
 //
 //*****************************************************************************
-#define USB_TXCSRH14_AUTOSET    0x00000080  // Auto Set.
-#define USB_TXCSRH14_ISO        0x00000040  // ISO.
-#define USB_TXCSRH14_MODE       0x00000020  // Mode.
-#define USB_TXCSRH14_DMAEN      0x00000010  // DMA Request Enable.
-#define USB_TXCSRH14_FDT        0x00000008  // Force Data Toggle.
-#define USB_TXCSRH14_DMAMOD     0x00000004  // DMA Request Mode.
-#define USB_TXCSRH14_DTWE       0x00000002  // Data Toggle Write Enable.
-#define USB_TXCSRH14_DT         0x00000001  // Data Toggle.
+#define USB_TXCSRH14_AUTOSET    0x00000080  // Auto Set
+#define USB_TXCSRH14_ISO        0x00000040  // Isochronous Transfers
+#define USB_TXCSRH14_MODE       0x00000020  // Mode
+#define USB_TXCSRH14_DMAEN      0x00000010  // DMA Request Enable
+#define USB_TXCSRH14_FDT        0x00000008  // Force Data Toggle
+#define USB_TXCSRH14_DMAMOD     0x00000004  // DMA Request Mode
+#define USB_TXCSRH14_DTWE       0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH14_DT         0x00000001  // Data Toggle
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXMAXP14 register.
 //
 //*****************************************************************************
-#define USB_RXMAXP14_MAXLOAD_M  0x000007FF  // Maximum Payload.
+#define USB_RXMAXP14_MAXLOAD_M  0x000007FF  // Maximum Payload
 #define USB_RXMAXP14_MAXLOAD_S  0
 
 //*****************************************************************************
@@ -4249,33 +3961,32 @@
 // The following are defines for the bit fields in the USB_O_RXCSRL14 register.
 //
 //*****************************************************************************
-#define USB_RXCSRL14_CLRDT      0x00000080  // Clear Data Toggle.
-#define USB_RXCSRL14_STALLED    0x00000040  // Endpoint Stalled.
-#define USB_RXCSRL14_REQPKT     0x00000020  // Request Packet.
-#define USB_RXCSRL14_STALL      0x00000020  // Send Stall.
-#define USB_RXCSRL14_FLUSH      0x00000010  // Flush FIFO.
-#define USB_RXCSRL14_DATAERR    0x00000008  // Data Error.
-#define USB_RXCSRL14_NAKTO      0x00000008  // NAK Timeout.
-#define USB_RXCSRL14_OVER       0x00000004  // Overrun.
-#define USB_RXCSRL14_ERROR      0x00000004  // Error.
-#define USB_RXCSRL14_FULL       0x00000002  // FIFO Full.
-#define USB_RXCSRL14_RXRDY      0x00000001  // Receive Packet Ready.
+#define USB_RXCSRL14_CLRDT      0x00000080  // Clear Data Toggle
+#define USB_RXCSRL14_STALLED    0x00000040  // Endpoint Stalled
+#define USB_RXCSRL14_REQPKT     0x00000020  // Request Packet
+#define USB_RXCSRL14_STALL      0x00000020  // Send STALL
+#define USB_RXCSRL14_FLUSH      0x00000010  // Flush FIFO
+#define USB_RXCSRL14_DATAERR    0x00000008  // Data Error
+#define USB_RXCSRL14_NAKTO      0x00000008  // NAK Timeout
+#define USB_RXCSRL14_OVER       0x00000004  // Overrun
+#define USB_RXCSRL14_ERROR      0x00000004  // Error
+#define USB_RXCSRL14_FULL       0x00000002  // FIFO Full
+#define USB_RXCSRL14_RXRDY      0x00000001  // Receive Packet Ready
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXCSRH14 register.
 //
 //*****************************************************************************
-#define USB_RXCSRH14_AUTOCL     0x00000080  // Auto Clear.
-#define USB_RXCSRH14_AUTORQ     0x00000040  // Auto Request.
-#define USB_RXCSRH14_ISO        0x00000040  // ISO.
-#define USB_RXCSRH14_DMAEN      0x00000020  // DMA Request Enable.
-#define USB_RXCSRH14_PIDERR     0x00000010  // PID Error.
+#define USB_RXCSRH14_AUTOCL     0x00000080  // Auto Clear
+#define USB_RXCSRH14_AUTORQ     0x00000040  // Auto Request
+#define USB_RXCSRH14_ISO        0x00000040  // Isochronous Transfers
+#define USB_RXCSRH14_DMAEN      0x00000020  // DMA Request Enable
+#define USB_RXCSRH14_PIDERR     0x00000010  // PID Error
 #define USB_RXCSRH14_DISNYET    0x00000010  // Disable NYET
-#define USB_RXCSRH14_DMAMOD     0x00000008  // DMA Request Mode.
-#define USB_RXCSRH14_DTWE       0x00000004  // Data Toggle Write Enable.
-#define USB_RXCSRH14_DT         0x00000002  // Data Toggle.
-#define USB_RXCSRH14_INCRX      0x00000001  // Incomplete Receive.
+#define USB_RXCSRH14_DMAMOD     0x00000008  // DMA Request Mode
+#define USB_RXCSRH14_DTWE       0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH14_DT         0x00000002  // Data Toggle
 
 //*****************************************************************************
 //
@@ -4283,7 +3994,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RXCOUNT14_COUNT_M   0x00001FFF  // Receive Packet Count.
+#define USB_RXCOUNT14_COUNT_M   0x00001FFF  // Receive Packet Count
 #define USB_RXCOUNT14_COUNT_S   0
 
 //*****************************************************************************
@@ -4291,16 +4002,16 @@
 // The following are defines for the bit fields in the USB_O_TXTYPE14 register.
 //
 //*****************************************************************************
-#define USB_TXTYPE14_SPEED_M    0x000000C0  // Operating Speed.
+#define USB_TXTYPE14_SPEED_M    0x000000C0  // Operating Speed
 #define USB_TXTYPE14_SPEED_DFLT 0x00000000  // Default
 #define USB_TXTYPE14_SPEED_FULL 0x00000080  // Full
 #define USB_TXTYPE14_SPEED_LOW  0x000000C0  // Low
-#define USB_TXTYPE14_PROTO_M    0x00000030  // Protocol.
+#define USB_TXTYPE14_PROTO_M    0x00000030  // Protocol
 #define USB_TXTYPE14_PROTO_CTRL 0x00000000  // Control
 #define USB_TXTYPE14_PROTO_ISOC 0x00000010  // Isochronous
 #define USB_TXTYPE14_PROTO_BULK 0x00000020  // Bulk
 #define USB_TXTYPE14_PROTO_INT  0x00000030  // Interrupt
-#define USB_TXTYPE14_TEP_M      0x0000000F  // Target Endpoint Number.
+#define USB_TXTYPE14_TEP_M      0x0000000F  // Target Endpoint Number
 #define USB_TXTYPE14_TEP_S      0
 
 //*****************************************************************************
@@ -4312,7 +4023,7 @@
 #define USB_TXINTERVAL14_TXPOLL_M \
                                 0x000000FF  // TX Polling
 #define USB_TXINTERVAL14_NAKLMT_M \
-                                0x000000FF  // NAK Limit.
+                                0x000000FF  // NAK Limit
 #define USB_TXINTERVAL14_TXPOLL_S \
                                 0
 #define USB_TXINTERVAL14_NAKLMT_S \
@@ -4323,16 +4034,16 @@
 // The following are defines for the bit fields in the USB_O_RXTYPE14 register.
 //
 //*****************************************************************************
-#define USB_RXTYPE14_SPEED_M    0x000000C0  // Operating Speed.
+#define USB_RXTYPE14_SPEED_M    0x000000C0  // Operating Speed
 #define USB_RXTYPE14_SPEED_DFLT 0x00000000  // Default
 #define USB_RXTYPE14_SPEED_FULL 0x00000080  // Full
 #define USB_RXTYPE14_SPEED_LOW  0x000000C0  // Low
-#define USB_RXTYPE14_PROTO_M    0x00000030  // Protocol.
+#define USB_RXTYPE14_PROTO_M    0x00000030  // Protocol
 #define USB_RXTYPE14_PROTO_CTRL 0x00000000  // Control
 #define USB_RXTYPE14_PROTO_ISOC 0x00000010  // Isochronous
 #define USB_RXTYPE14_PROTO_BULK 0x00000020  // Bulk
 #define USB_RXTYPE14_PROTO_INT  0x00000030  // Interrupt
-#define USB_RXTYPE14_TEP_M      0x0000000F  // Target Endpoint Number.
+#define USB_RXTYPE14_TEP_M      0x0000000F  // Target Endpoint Number
 #define USB_RXTYPE14_TEP_S      0
 
 //*****************************************************************************
@@ -4344,7 +4055,7 @@
 #define USB_RXINTERVAL14_TXPOLL_M \
                                 0x000000FF  // RX Polling
 #define USB_RXINTERVAL14_NAKLMT_M \
-                                0x000000FF  // NAK Limit.
+                                0x000000FF  // NAK Limit
 #define USB_RXINTERVAL14_TXPOLL_S \
                                 0
 #define USB_RXINTERVAL14_NAKLMT_S \
@@ -4355,7 +4066,7 @@
 // The following are defines for the bit fields in the USB_O_TXMAXP15 register.
 //
 //*****************************************************************************
-#define USB_TXMAXP15_MAXLOAD_M  0x000007FF  // Maximum Payload.
+#define USB_TXMAXP15_MAXLOAD_M  0x000007FF  // Maximum Payload
 #define USB_TXMAXP15_MAXLOAD_S  0
 
 //*****************************************************************************
@@ -4364,37 +4075,36 @@
 //
 //*****************************************************************************
 #define USB_TXCSRL15_NAKTO      0x00000080  // NAK Timeout
-#define USB_TXCSRL15_INCTX      0x00000080  // Incomplete Transmit.
-#define USB_TXCSRL15_CLRDT      0x00000040  // Clear Data Toggle.
-#define USB_TXCSRL15_STALLED    0x00000020  // Endpoint Stalled.
-#define USB_TXCSRL15_SETUP      0x00000010  // Setup Packet.
-#define USB_TXCSRL15_STALL      0x00000010  // Send Stall.
-#define USB_TXCSRL15_FLUSH      0x00000008  // Flush FIFO.
-#define USB_TXCSRL15_UNDRN      0x00000004  // Underrun.
-#define USB_TXCSRL15_ERROR      0x00000004  // Error.
-#define USB_TXCSRL15_FIFONE     0x00000002  // FIFO Not Empty.
-#define USB_TXCSRL15_TXRDY      0x00000001  // Transmit Packet Ready.
+#define USB_TXCSRL15_CLRDT      0x00000040  // Clear Data Toggle
+#define USB_TXCSRL15_STALLED    0x00000020  // Endpoint Stalled
+#define USB_TXCSRL15_SETUP      0x00000010  // Setup Packet
+#define USB_TXCSRL15_STALL      0x00000010  // Send STALL
+#define USB_TXCSRL15_FLUSH      0x00000008  // Flush FIFO
+#define USB_TXCSRL15_UNDRN      0x00000004  // Underrun
+#define USB_TXCSRL15_ERROR      0x00000004  // Error
+#define USB_TXCSRL15_FIFONE     0x00000002  // FIFO Not Empty
+#define USB_TXCSRL15_TXRDY      0x00000001  // Transmit Packet Ready
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_TXCSRH15 register.
 //
 //*****************************************************************************
-#define USB_TXCSRH15_AUTOSET    0x00000080  // Auto Set.
-#define USB_TXCSRH15_ISO        0x00000040  // ISO.
-#define USB_TXCSRH15_MODE       0x00000020  // Mode.
-#define USB_TXCSRH15_DMAEN      0x00000010  // DMA Request Enable.
-#define USB_TXCSRH15_FDT        0x00000008  // Force Data Toggle.
-#define USB_TXCSRH15_DMAMOD     0x00000004  // DMA Request Mode.
-#define USB_TXCSRH15_DTWE       0x00000002  // Data Toggle Write Enable.
-#define USB_TXCSRH15_DT         0x00000001  // Data Toggle.
+#define USB_TXCSRH15_AUTOSET    0x00000080  // Auto Set
+#define USB_TXCSRH15_ISO        0x00000040  // Isochronous Transfers
+#define USB_TXCSRH15_MODE       0x00000020  // Mode
+#define USB_TXCSRH15_DMAEN      0x00000010  // DMA Request Enable
+#define USB_TXCSRH15_FDT        0x00000008  // Force Data Toggle
+#define USB_TXCSRH15_DMAMOD     0x00000004  // DMA Request Mode
+#define USB_TXCSRH15_DTWE       0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH15_DT         0x00000001  // Data Toggle
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXMAXP15 register.
 //
 //*****************************************************************************
-#define USB_RXMAXP15_MAXLOAD_M  0x000007FF  // Maximum Payload.
+#define USB_RXMAXP15_MAXLOAD_M  0x000007FF  // Maximum Payload
 #define USB_RXMAXP15_MAXLOAD_S  0
 
 //*****************************************************************************
@@ -4402,33 +4112,32 @@
 // The following are defines for the bit fields in the USB_O_RXCSRL15 register.
 //
 //*****************************************************************************
-#define USB_RXCSRL15_CLRDT      0x00000080  // Clear Data Toggle.
-#define USB_RXCSRL15_STALLED    0x00000040  // Endpoint Stalled.
-#define USB_RXCSRL15_STALL      0x00000020  // Send Stall.
-#define USB_RXCSRL15_REQPKT     0x00000020  // Request Packet.
-#define USB_RXCSRL15_FLUSH      0x00000010  // Flush FIFO.
-#define USB_RXCSRL15_DATAERR    0x00000008  // Data Error.
-#define USB_RXCSRL15_NAKTO      0x00000008  // NAK Timeout.
-#define USB_RXCSRL15_ERROR      0x00000004  // Error.
-#define USB_RXCSRL15_OVER       0x00000004  // Overrun.
-#define USB_RXCSRL15_FULL       0x00000002  // FIFO Full.
-#define USB_RXCSRL15_RXRDY      0x00000001  // Receive Packet Ready.
+#define USB_RXCSRL15_CLRDT      0x00000080  // Clear Data Toggle
+#define USB_RXCSRL15_STALLED    0x00000040  // Endpoint Stalled
+#define USB_RXCSRL15_STALL      0x00000020  // Send STALL
+#define USB_RXCSRL15_REQPKT     0x00000020  // Request Packet
+#define USB_RXCSRL15_FLUSH      0x00000010  // Flush FIFO
+#define USB_RXCSRL15_DATAERR    0x00000008  // Data Error
+#define USB_RXCSRL15_NAKTO      0x00000008  // NAK Timeout
+#define USB_RXCSRL15_ERROR      0x00000004  // Error
+#define USB_RXCSRL15_OVER       0x00000004  // Overrun
+#define USB_RXCSRL15_FULL       0x00000002  // FIFO Full
+#define USB_RXCSRL15_RXRDY      0x00000001  // Receive Packet Ready
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXCSRH15 register.
 //
 //*****************************************************************************
-#define USB_RXCSRH15_AUTOCL     0x00000080  // Auto Clear.
-#define USB_RXCSRH15_AUTORQ     0x00000040  // Auto Request.
-#define USB_RXCSRH15_ISO        0x00000040  // ISO.
-#define USB_RXCSRH15_DMAEN      0x00000020  // DMA Request Enable.
-#define USB_RXCSRH15_PIDERR     0x00000010  // PID Error.
+#define USB_RXCSRH15_AUTOCL     0x00000080  // Auto Clear
+#define USB_RXCSRH15_AUTORQ     0x00000040  // Auto Request
+#define USB_RXCSRH15_ISO        0x00000040  // Isochronous Transfers
+#define USB_RXCSRH15_DMAEN      0x00000020  // DMA Request Enable
+#define USB_RXCSRH15_PIDERR     0x00000010  // PID Error
 #define USB_RXCSRH15_DISNYET    0x00000010  // Disable NYET
-#define USB_RXCSRH15_DMAMOD     0x00000008  // DMA Request Mode.
-#define USB_RXCSRH15_DTWE       0x00000004  // Data Toggle Write Enable.
-#define USB_RXCSRH15_DT         0x00000002  // Data Toggle.
-#define USB_RXCSRH15_INCRX      0x00000001  // Incomplete Receive.
+#define USB_RXCSRH15_DMAMOD     0x00000008  // DMA Request Mode
+#define USB_RXCSRH15_DTWE       0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH15_DT         0x00000002  // Data Toggle
 
 //*****************************************************************************
 //
@@ -4436,7 +4145,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RXCOUNT15_COUNT_M   0x00001FFF  // Receive Packet Count.
+#define USB_RXCOUNT15_COUNT_M   0x00001FFF  // Receive Packet Count
 #define USB_RXCOUNT15_COUNT_S   0
 
 //*****************************************************************************
@@ -4444,16 +4153,16 @@
 // The following are defines for the bit fields in the USB_O_TXTYPE15 register.
 //
 //*****************************************************************************
-#define USB_TXTYPE15_SPEED_M    0x000000C0  // Operating Speed.
+#define USB_TXTYPE15_SPEED_M    0x000000C0  // Operating Speed
 #define USB_TXTYPE15_SPEED_DFLT 0x00000000  // Default
 #define USB_TXTYPE15_SPEED_FULL 0x00000080  // Full
 #define USB_TXTYPE15_SPEED_LOW  0x000000C0  // Low
-#define USB_TXTYPE15_PROTO_M    0x00000030  // Protocol.
+#define USB_TXTYPE15_PROTO_M    0x00000030  // Protocol
 #define USB_TXTYPE15_PROTO_CTRL 0x00000000  // Control
 #define USB_TXTYPE15_PROTO_ISOC 0x00000010  // Isochronous
 #define USB_TXTYPE15_PROTO_BULK 0x00000020  // Bulk
 #define USB_TXTYPE15_PROTO_INT  0x00000030  // Interrupt
-#define USB_TXTYPE15_TEP_M      0x0000000F  // Target Endpoint Number.
+#define USB_TXTYPE15_TEP_M      0x0000000F  // Target Endpoint Number
 #define USB_TXTYPE15_TEP_S      0
 
 //*****************************************************************************
@@ -4465,7 +4174,7 @@
 #define USB_TXINTERVAL15_TXPOLL_M \
                                 0x000000FF  // TX Polling
 #define USB_TXINTERVAL15_NAKLMT_M \
-                                0x000000FF  // NAK Limit.
+                                0x000000FF  // NAK Limit
 #define USB_TXINTERVAL15_NAKLMT_S \
                                 0
 #define USB_TXINTERVAL15_TXPOLL_S \
@@ -4476,16 +4185,16 @@
 // The following are defines for the bit fields in the USB_O_RXTYPE15 register.
 //
 //*****************************************************************************
-#define USB_RXTYPE15_SPEED_M    0x000000C0  // Operating Speed.
+#define USB_RXTYPE15_SPEED_M    0x000000C0  // Operating Speed
 #define USB_RXTYPE15_SPEED_DFLT 0x00000000  // Default
 #define USB_RXTYPE15_SPEED_FULL 0x00000080  // Full
 #define USB_RXTYPE15_SPEED_LOW  0x000000C0  // Low
-#define USB_RXTYPE15_PROTO_M    0x00000030  // Protocol.
+#define USB_RXTYPE15_PROTO_M    0x00000030  // Protocol
 #define USB_RXTYPE15_PROTO_CTRL 0x00000000  // Control
 #define USB_RXTYPE15_PROTO_ISOC 0x00000010  // Isochronous
 #define USB_RXTYPE15_PROTO_BULK 0x00000020  // Bulk
 #define USB_RXTYPE15_PROTO_INT  0x00000030  // Interrupt
-#define USB_RXTYPE15_TEP_M      0x0000000F  // Target Endpoint Number.
+#define USB_RXTYPE15_TEP_M      0x0000000F  // Target Endpoint Number
 #define USB_RXTYPE15_TEP_S      0
 
 //*****************************************************************************
@@ -4497,19 +4206,46 @@
 #define USB_RXINTERVAL15_TXPOLL_M \
                                 0x000000FF  // RX Polling
 #define USB_RXINTERVAL15_NAKLMT_M \
-                                0x000000FF  // NAK Limit.
+                                0x000000FF  // NAK Limit
 #define USB_RXINTERVAL15_TXPOLL_S \
                                 0
 #define USB_RXINTERVAL15_NAKLMT_S \
                                 0
 
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT1
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT1_M       0x0000FFFF  // Block Transfer Packet Count
+#define USB_RQPKTCOUNT1_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT2
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT2_M       0x0000FFFF  // Block Transfer Packet Count
+#define USB_RQPKTCOUNT2_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT3
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT3_M       0x0000FFFF  // Block Transfer Packet Count
+#define USB_RQPKTCOUNT3_S       0
+
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RQPKTCOUNT4
 // register.
 //
 //*****************************************************************************
-#define USB_RQPKTCOUNT4_COUNT_M 0x0000FFFF  // Block Transfer Packet Count.
+#define USB_RQPKTCOUNT4_COUNT_M 0x0000FFFF  // Block Transfer Packet Count
 #define USB_RQPKTCOUNT4_COUNT_S 0
 
 //*****************************************************************************
@@ -4518,7 +4254,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RQPKTCOUNT5_COUNT_M 0x0000FFFF  // Block Transfer Packet Count.
+#define USB_RQPKTCOUNT5_COUNT_M 0x0000FFFF  // Block Transfer Packet Count
 #define USB_RQPKTCOUNT5_COUNT_S 0
 
 //*****************************************************************************
@@ -4527,7 +4263,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RQPKTCOUNT6_COUNT_M 0x0000FFFF  // Block Transfer Packet Count.
+#define USB_RQPKTCOUNT6_COUNT_M 0x0000FFFF  // Block Transfer Packet Count
 #define USB_RQPKTCOUNT6_COUNT_S 0
 
 //*****************************************************************************
@@ -4536,7 +4272,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RQPKTCOUNT7_COUNT_M 0x0000FFFF  // Block Transfer Packet Count.
+#define USB_RQPKTCOUNT7_COUNT_M 0x0000FFFF  // Block Transfer Packet Count
 #define USB_RQPKTCOUNT7_COUNT_S 0
 
 //*****************************************************************************
@@ -4545,7 +4281,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RQPKTCOUNT8_COUNT_M 0x0000FFFF  // Block Transfer Packet Count.
+#define USB_RQPKTCOUNT8_COUNT_M 0x0000FFFF  // Block Transfer Packet Count
 #define USB_RQPKTCOUNT8_COUNT_S 0
 
 //*****************************************************************************
@@ -4554,7 +4290,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RQPKTCOUNT9_COUNT_M 0x0000FFFF  // Block Transfer Packet Count.
+#define USB_RQPKTCOUNT9_COUNT_M 0x0000FFFF  // Block Transfer Packet Count
 #define USB_RQPKTCOUNT9_COUNT_S 0
 
 //*****************************************************************************
@@ -4564,7 +4300,7 @@
 //
 //*****************************************************************************
 #define USB_RQPKTCOUNT10_COUNT_M \
-                                0x0000FFFF  // Block Transfer Packet Count.
+                                0x0000FFFF  // Block Transfer Packet Count
 #define USB_RQPKTCOUNT10_COUNT_S \
                                 0
 
@@ -4575,7 +4311,7 @@
 //
 //*****************************************************************************
 #define USB_RQPKTCOUNT11_COUNT_M \
-                                0x0000FFFF  // Block Transfer Packet Count.
+                                0x0000FFFF  // Block Transfer Packet Count
 #define USB_RQPKTCOUNT11_COUNT_S \
                                 0
 
@@ -4586,7 +4322,7 @@
 //
 //*****************************************************************************
 #define USB_RQPKTCOUNT12_COUNT_M \
-                                0x0000FFFF  // Block Transfer Packet Count.
+                                0x0000FFFF  // Block Transfer Packet Count
 #define USB_RQPKTCOUNT12_COUNT_S \
                                 0
 
@@ -4597,7 +4333,7 @@
 //
 //*****************************************************************************
 #define USB_RQPKTCOUNT13_COUNT_M \
-                                0x0000FFFF  // Block Transfer Packet Count.
+                                0x0000FFFF  // Block Transfer Packet Count
 #define USB_RQPKTCOUNT13_COUNT_S \
                                 0
 
@@ -4608,7 +4344,7 @@
 //
 //*****************************************************************************
 #define USB_RQPKTCOUNT14_COUNT_M \
-                                0x0000FFFF  // Block Transfer Packet Count.
+                                0x0000FFFF  // Block Transfer Packet Count
 #define USB_RQPKTCOUNT14_COUNT_S \
                                 0
 
@@ -4619,20 +4355,268 @@
 //
 //*****************************************************************************
 #define USB_RQPKTCOUNT15_COUNT_M \
-                                0x0000FFFF  // Block Transfer Packet Count.
+                                0x0000FFFF  // Block Transfer Packet Count
 #define USB_RQPKTCOUNT15_COUNT_S \
                                 0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_EPS register.
+// The following are defines for the bit fields in the USB_O_RXDPKTBUFDIS
+// register.
 //
 //*****************************************************************************
-#define USB_EPS_DMAC_M          0x00000F00  // DMA C Select.
-#define USB_EPS_DMAB_M          0x000000F0  // DMA B Select.
-#define USB_EPS_DMAA_M          0x0000000F  // DMA A Select.
-#define USB_EPS_DMAC_S          8
-#define USB_EPS_DMAB_S          4
-#define USB_EPS_DMAA_S          0
+#define USB_RXDPKTBUFDIS_EP15   0x00008000  // EP15 RX Double-Packet Buffer
+                                            // Disable
+#define USB_RXDPKTBUFDIS_EP14   0x00004000  // EP14 RX Double-Packet Buffer
+                                            // Disable
+#define USB_RXDPKTBUFDIS_EP13   0x00002000  // EP13 RX Double-Packet Buffer
+                                            // Disable
+#define USB_RXDPKTBUFDIS_EP12   0x00001000  // EP12 RX Double-Packet Buffer
+                                            // Disable
+#define USB_RXDPKTBUFDIS_EP11   0x00000800  // EP11 RX Double-Packet Buffer
+                                            // Disable
+#define USB_RXDPKTBUFDIS_EP10   0x00000400  // EP10 RX Double-Packet Buffer
+                                            // Disable
+#define USB_RXDPKTBUFDIS_EP9    0x00000200  // EP9 RX Double-Packet Buffer
+                                            // Disable
+#define USB_RXDPKTBUFDIS_EP8    0x00000100  // EP8 RX Double-Packet Buffer
+                                            // Disable
+#define USB_RXDPKTBUFDIS_EP7    0x00000080  // EP7 RX Double-Packet Buffer
+                                            // Disable
+#define USB_RXDPKTBUFDIS_EP6    0x00000040  // EP6 RX Double-Packet Buffer
+                                            // Disable
+#define USB_RXDPKTBUFDIS_EP5    0x00000020  // EP5 RX Double-Packet Buffer
+                                            // Disable
+#define USB_RXDPKTBUFDIS_EP4    0x00000010  // EP4 RX Double-Packet Buffer
+                                            // Disable
+#define USB_RXDPKTBUFDIS_EP3    0x00000008  // EP3 RX Double-Packet Buffer
+                                            // Disable
+#define USB_RXDPKTBUFDIS_EP2    0x00000004  // EP2 RX Double-Packet Buffer
+                                            // Disable
+#define USB_RXDPKTBUFDIS_EP1    0x00000002  // EP1 RX Double-Packet Buffer
+                                            // Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXDPKTBUFDIS
+// register.
+//
+//*****************************************************************************
+#define USB_TXDPKTBUFDIS_EP15   0x00008000  // EP15 TX Double-Packet Buffer
+                                            // Disable
+#define USB_TXDPKTBUFDIS_EP14   0x00004000  // EP14 TX Double-Packet Buffer
+                                            // Disable
+#define USB_TXDPKTBUFDIS_EP13   0x00002000  // EP13 TX Double-Packet Buffer
+                                            // Disable
+#define USB_TXDPKTBUFDIS_EP12   0x00001000  // EP12 TX Double-Packet Buffer
+                                            // Disable
+#define USB_TXDPKTBUFDIS_EP11   0x00000800  // EP11 TX Double-Packet Buffer
+                                            // Disable
+#define USB_TXDPKTBUFDIS_EP10   0x00000400  // EP10 TX Double-Packet Buffer
+                                            // Disable
+#define USB_TXDPKTBUFDIS_EP9    0x00000200  // EP9 TX Double-Packet Buffer
+                                            // Disable
+#define USB_TXDPKTBUFDIS_EP8    0x00000100  // EP8 TX Double-Packet Buffer
+                                            // Disable
+#define USB_TXDPKTBUFDIS_EP7    0x00000080  // EP7 TX Double-Packet Buffer
+                                            // Disable
+#define USB_TXDPKTBUFDIS_EP6    0x00000040  // EP6 TX Double-Packet Buffer
+                                            // Disable
+#define USB_TXDPKTBUFDIS_EP5    0x00000020  // EP5 TX Double-Packet Buffer
+                                            // Disable
+#define USB_TXDPKTBUFDIS_EP4    0x00000010  // EP4 TX Double-Packet Buffer
+                                            // Disable
+#define USB_TXDPKTBUFDIS_EP3    0x00000008  // EP3 TX Double-Packet Buffer
+                                            // Disable
+#define USB_TXDPKTBUFDIS_EP2    0x00000004  // EP2 TX Double-Packet Buffer
+                                            // Disable
+#define USB_TXDPKTBUFDIS_EP1    0x00000002  // EP1 TX Double-Packet Buffer
+                                            // Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPC register.
+//
+//*****************************************************************************
+#define USB_EPC_PFLTACT_M       0x00000300  // Power Fault Action
+#define USB_EPC_PFLTACT_UNCHG   0x00000000  // Unchanged
+#define USB_EPC_PFLTACT_TRIS    0x00000100  // Tristate
+#define USB_EPC_PFLTACT_LOW     0x00000200  // Low
+#define USB_EPC_PFLTACT_HIGH    0x00000300  // High
+#define USB_EPC_PFLTAEN         0x00000040  // Power Fault Action Enable
+#define USB_EPC_PFLTSEN_HIGH    0x00000020  // Power Fault Sense
+#define USB_EPC_PFLTEN          0x00000010  // Power Fault Input Enable
+#define USB_EPC_EPENDE          0x00000004  // EPEN Drive Enable
+#define USB_EPC_EPEN_M          0x00000003  // External Power Supply Enable
+                                            // Configuration
+#define USB_EPC_EPEN_LOW        0x00000000  // Power Enable Active Low
+#define USB_EPC_EPEN_HIGH       0x00000001  // Power Enable Active High
+#define USB_EPC_EPEN_VBLOW      0x00000002  // Power Enable High if VBUS Low
+#define USB_EPC_EPEN_VBHIGH     0x00000003  // Power Enable High if VBUS High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPCRIS register.
+//
+//*****************************************************************************
+#define USB_EPCRIS_PF           0x00000001  // USB Power Fault Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPCIM register.
+//
+//*****************************************************************************
+#define USB_EPCIM_PF            0x00000001  // USB Power Fault Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPCISC register.
+//
+//*****************************************************************************
+#define USB_EPCISC_PF           0x00000001  // USB Power Fault Interrupt Status
+                                            // and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DRRIS register.
+//
+//*****************************************************************************
+#define USB_DRRIS_RESUME        0x00000001  // RESUME Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DRIM register.
+//
+//*****************************************************************************
+#define USB_DRIM_RESUME         0x00000001  // RESUME Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DRISC register.
+//
+//*****************************************************************************
+#define USB_DRISC_RESUME        0x00000001  // RESUME Interrupt Status and
+                                            // Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_GPCS register.
+//
+//*****************************************************************************
+#define USB_GPCS_DEVMODOTG      0x00000002  // Enable Device Mode
+#define USB_GPCS_DEVMOD         0x00000001  // Device Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VDC register.
+//
+//*****************************************************************************
+#define USB_VDC_VBDEN           0x00000001  // VBUS Droop Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VDCRIS register.
+//
+//*****************************************************************************
+#define USB_VDCRIS_VD           0x00000001  // VBUS Droop Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VDCIM register.
+//
+//*****************************************************************************
+#define USB_VDCIM_VD            0x00000001  // VBUS Droop Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VDCISC register.
+//
+//*****************************************************************************
+#define USB_VDCISC_VD           0x00000001  // VBUS Droop Interrupt Status and
+                                            // Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_IDVRIS register.
+//
+//*****************************************************************************
+#define USB_IDVRIS_ID           0x00000001  // ID Valid Detect Raw Interrupt
+                                            // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_IDVIM register.
+//
+//*****************************************************************************
+#define USB_IDVIM_ID            0x00000001  // ID Valid Detect Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_IDVISC register.
+//
+//*****************************************************************************
+#define USB_IDVISC_ID           0x00000001  // ID Valid Detect Interrupt Status
+                                            // and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMASEL register.
+//
+//*****************************************************************************
+#define USB_DMASEL_DMACTX_M     0x00F00000  // DMA C TX Select
+#define USB_DMASEL_DMACRX_M     0x000F0000  // DMA C RX Select
+#define USB_DMASEL_DMABTX_M     0x0000F000  // DMA B TX Select
+#define USB_DMASEL_DMABRX_M     0x00000F00  // DMA B RX Select
+#define USB_DMASEL_DMAATX_M     0x000000F0  // DMA A TX Select
+#define USB_DMASEL_DMAARX_M     0x0000000F  // DMA A RX Select
+#define USB_DMASEL_DMACTX_S     20
+#define USB_DMASEL_DMACRX_S     16
+#define USB_DMASEL_DMABTX_S     12
+#define USB_DMASEL_DMABRX_S     8
+#define USB_DMASEL_DMAATX_S     4
+#define USB_DMASEL_DMAARX_S     0
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the
+// USB_O_TXFIFOADD register.
+//
+//*****************************************************************************
+#define USB_TXFIFOADD_ADDR_2048 0x00000009  // 2048
+#define USB_TXFIFOADD_ADDR_1024 0x00000008  // 1024
+#define USB_TXFIFOADD_ADDR_512  0x00000007  // 512
+#define USB_TXFIFOADD_ADDR_256  0x00000006  // 256
+#define USB_TXFIFOADD_ADDR_128  0x00000005  // 128
+#define USB_TXFIFOADD_ADDR_64   0x00000004  // 64
+#define USB_TXFIFOADD_ADDR_32   0x00000003  // 32
+#define USB_TXFIFOADD_ADDR_16   0x00000002  // 16
+#define USB_TXFIFOADD_ADDR_8    0x00000001  // 8
+#define USB_TXFIFOADD_ADDR_0    0x00000000  // 0
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the
+// USB_O_RXFIFOADD register.
+//
+//*****************************************************************************
+#define USB_RXFIFOADD_ADDR_2048 0x00000009  // 2048
+#define USB_RXFIFOADD_ADDR_1024 0x00000008  // 1024
+#define USB_RXFIFOADD_ADDR_512  0x00000007  // 512
+#define USB_RXFIFOADD_ADDR_256  0x00000006  // 256
+#define USB_RXFIFOADD_ADDR_128  0x00000005  // 128
+#define USB_RXFIFOADD_ADDR_64   0x00000004  // 64
+#define USB_RXFIFOADD_ADDR_32   0x00000003  // 32
+#define USB_RXFIFOADD_ADDR_16   0x00000002  // 16
+#define USB_RXFIFOADD_ADDR_8    0x00000001  // 8
+#define USB_RXFIFOADD_ADDR_0    0x00000000  // 0
+
+#endif
 
 #endif // __HW_USB_H__
diff --git a/src/platform/lm3s/hw_watchdog.h b/src/platform/lm3s/inc/hw_watchdog.h
similarity index 69%
rename from src/platform/lm3s/hw_watchdog.h
rename to src/platform/lm3s/inc/hw_watchdog.h
index 33885cb6..5a0fa85d 100755
--- a/src/platform/lm3s/hw_watchdog.h
+++ b/src/platform/lm3s/inc/hw_watchdog.h
@@ -2,26 +2,23 @@
 //
 // hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware.
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2011 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4781 of the Stellaris Firmware Development Package.
+// This is part of revision 7611 of the Stellaris Firmware Development Package.
 //
 //*****************************************************************************
 
@@ -33,22 +30,78 @@
 // The following are defines for the Watchdog Timer register offsets.
 //
 //*****************************************************************************
-#define WDT_O_LOAD              0x00000000  // Load register
-#define WDT_O_VALUE             0x00000004  // Current value register
-#define WDT_O_CTL               0x00000008  // Control register
-#define WDT_O_ICR               0x0000000C  // Interrupt clear register
-#define WDT_O_RIS               0x00000010  // Raw interrupt status register
-#define WDT_O_MIS               0x00000014  // Masked interrupt status register
-#define WDT_O_TEST              0x00000418  // Test register
-#define WDT_O_LOCK              0x00000C00  // Lock register
+#define WDT_O_LOAD              0x00000000  // Watchdog Load
+#define WDT_O_VALUE             0x00000004  // Watchdog Value
+#define WDT_O_CTL               0x00000008  // Watchdog Control
+#define WDT_O_ICR               0x0000000C  // Watchdog Interrupt Clear
+#define WDT_O_RIS               0x00000010  // Watchdog Raw Interrupt Status
+#define WDT_O_MIS               0x00000014  // Watchdog Masked Interrupt Status
+#define WDT_O_TEST              0x00000418  // Watchdog Test
+#define WDT_O_LOCK              0x00000C00  // Watchdog Lock
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the WDT_CTL register.
+// The following are defines for the bit fields in the WDT_O_LOAD register.
 //
 //*****************************************************************************
-#define WDT_CTL_RESEN           0x00000002  // Enable reset output
-#define WDT_CTL_INTEN           0x00000001  // Enable the WDT counter and int
+#define WDT_LOAD_M              0xFFFFFFFF  // Watchdog Load Value
+#define WDT_LOAD_S              0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_VALUE register.
+//
+//*****************************************************************************
+#define WDT_VALUE_M             0xFFFFFFFF  // Watchdog Value
+#define WDT_VALUE_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_CTL register.
+//
+//*****************************************************************************
+#define WDT_CTL_WRC             0x80000000  // Write Complete
+#define WDT_CTL_RESEN           0x00000002  // Watchdog Reset Enable
+#define WDT_CTL_INTEN           0x00000001  // Watchdog Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_ICR register.
+//
+//*****************************************************************************
+#define WDT_ICR_M               0xFFFFFFFF  // Watchdog Interrupt Clear
+#define WDT_ICR_S               0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_RIS register.
+//
+//*****************************************************************************
+#define WDT_RIS_WDTRIS          0x00000001  // Watchdog Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_MIS register.
+//
+//*****************************************************************************
+#define WDT_MIS_WDTMIS          0x00000001  // Watchdog Masked Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_TEST register.
+//
+//*****************************************************************************
+#define WDT_TEST_STALL          0x00000100  // Watchdog Stall Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_LOCK register.
+//
+//*****************************************************************************
+#define WDT_LOCK_M              0xFFFFFFFF  // Watchdog Lock
+#define WDT_LOCK_UNLOCKED       0x00000000  // Unlocked
+#define WDT_LOCK_LOCKED         0x00000001  // Locked
+#define WDT_LOCK_UNLOCK         0x1ACCE551  // Unlocks the watchdog timer
 
 //*****************************************************************************
 //
@@ -58,62 +111,6 @@
 //*****************************************************************************
 #define WDT_INT_TIMEOUT         0x00000001  // Watchdog timer expired
 
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the WDT_TEST register.
-//
-//*****************************************************************************
-#define WDT_TEST_STALL          0x00000100  // Watchdog stall enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the WDT_LOCK register.
-//
-//*****************************************************************************
-#define WDT_LOCK_M              0xFFFFFFFF  // Watchdog Lock.
-#define WDT_LOCK_UNLOCK         0x1ACCE551  // Unlocks the watchdog timer
-#define WDT_LOCK_LOCKED         0x00000001  // Watchdog timer is locked
-#define WDT_LOCK_UNLOCKED       0x00000000  // Watchdog timer is unlocked
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the WDT_O_LOAD register.
-//
-//*****************************************************************************
-#define WDT_LOAD_M              0xFFFFFFFF  // Watchdog Load Value.
-#define WDT_LOAD_S              0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the WDT_O_VALUE register.
-//
-//*****************************************************************************
-#define WDT_VALUE_M             0xFFFFFFFF  // Watchdog Value.
-#define WDT_VALUE_S             0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the WDT_O_ICR register.
-//
-//*****************************************************************************
-#define WDT_ICR_M               0xFFFFFFFF  // Watchdog Interrupt Clear.
-#define WDT_ICR_S               0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the WDT_O_RIS register.
-//
-//*****************************************************************************
-#define WDT_RIS_WDTRIS          0x00000001  // Watchdog Raw Interrupt Status.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the WDT_O_MIS register.
-//
-//*****************************************************************************
-#define WDT_MIS_WDTMIS          0x00000001  // Watchdog Masked Interrupt
-                                            // Status.
-
 //*****************************************************************************
 //
 // The following definitions are deprecated.
@@ -142,7 +139,7 @@
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the bit fields in the WDT_TEST
+// The following are deprecated defines for the bit fields in the WDT_O_TEST
 // register.
 //
 //*****************************************************************************
diff --git a/src/platform/lm3s/lm3s-9d92.ld b/src/platform/lm3s/lm3s-9d92.ld
new file mode 100644
index 00000000..a9023dc1
--- /dev/null
+++ b/src/platform/lm3s/lm3s-9d92.ld
@@ -0,0 +1,64 @@
+MEMORY
+{
+    sram (W!RX) : ORIGIN = 0x20000000, LENGTH = 0x00018000
+    flash (RX) : ORIGIN = 0x00000000, LENGTH = 0x00080000
+}
+
+SECTIONS
+{  
+    .text :
+    {
+        . = ALIGN(4);
+        _text = .;
+        PROVIDE(stext = .);
+        KEEP(*(.isr_vector))
+        KEEP(*(.init))
+        *(.text .text.*)        
+        *(.rodata .rodata.*)        
+        *(.gnu.linkonce.t.*)
+        *(.glue_7)
+        *(.glue_7t)
+        *(.gcc_except_table)
+        *(.gnu.linkonce.r.*)
+        . = ALIGN(4);
+        _etext = .;
+        PROVIDE(etext = .);   
+     		_fini = . ;
+				*(.fini)
+
+    } >flash
+
+    .data : AT (_etext)
+    {
+        . = ALIGN(4);
+        _data = .;
+        *(.ramfunc .ramfunc.* .fastrun .fastrun.*)
+        *(.data .data.*)
+        *(.gnu.linkonce.d.*)
+        . = ALIGN(4);
+        _edata = .;
+    } >sram
+		
+		.ARM.extab :
+		{
+		    *(.ARM.extab*)
+		} >sram
+		
+		__exidx_start = .;
+		.ARM.exidx :
+		{
+		    *(.ARM.exidx*)
+		} >sram
+		__exidx_end = .;
+		
+    .bss (NOLOAD) : {
+        _bss = .;
+        *(.bss .bss.*)
+        *(.gnu.linkonce.b.*)
+        *(COMMON)
+        . = ALIGN(4);        
+        _ebss = .;
+    } >sram
+    
+    end = .;
+}
diff --git a/src/platform/lm3s/lm3s6918.h b/src/platform/lm3s/lm3s6918.h
index dabcd4b8..56e0d72f 100755
--- a/src/platform/lm3s/lm3s6918.h
+++ b/src/platform/lm3s/lm3s6918.h
@@ -2,26 +2,23 @@
 //
 // lm3s6918.h - LM3S6918 Register Definitions
 //
-// Copyright (c) 2007-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2007-2011 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4781 of the Stellaris Firmware Development Package.
+// This is part of revision 7611 of the Stellaris Firmware Development Package.
 //
 //*****************************************************************************
 
@@ -30,21 +27,21 @@
 
 //*****************************************************************************
 //
-// Watchdog Timer (WATCHDOG)
+// Watchdog Timer registers (WATCHDOG0)
 //
 //*****************************************************************************
-#define WATCHDOG_LOAD_R         (*((volatile unsigned long *)0x40000000))
-#define WATCHDOG_VALUE_R        (*((volatile unsigned long *)0x40000004))
-#define WATCHDOG_CTL_R          (*((volatile unsigned long *)0x40000008))
-#define WATCHDOG_ICR_R          (*((volatile unsigned long *)0x4000000C))
-#define WATCHDOG_RIS_R          (*((volatile unsigned long *)0x40000010))
-#define WATCHDOG_MIS_R          (*((volatile unsigned long *)0x40000014))
-#define WATCHDOG_TEST_R         (*((volatile unsigned long *)0x40000418))
-#define WATCHDOG_LOCK_R         (*((volatile unsigned long *)0x40000C00))
+#define WATCHDOG0_LOAD_R        (*((volatile unsigned long *)0x40000000))
+#define WATCHDOG0_VALUE_R       (*((volatile unsigned long *)0x40000004))
+#define WATCHDOG0_CTL_R         (*((volatile unsigned long *)0x40000008))
+#define WATCHDOG0_ICR_R         (*((volatile unsigned long *)0x4000000C))
+#define WATCHDOG0_RIS_R         (*((volatile unsigned long *)0x40000010))
+#define WATCHDOG0_MIS_R         (*((volatile unsigned long *)0x40000014))
+#define WATCHDOG0_TEST_R        (*((volatile unsigned long *)0x40000418))
+#define WATCHDOG0_LOCK_R        (*((volatile unsigned long *)0x40000C00))
 
 //*****************************************************************************
 //
-// General-Purpose Input/Outputs (PORTA)
+// GPIO registers (PORTA)
 //
 //*****************************************************************************
 #define GPIO_PORTA_DATA_BITS_R  ((volatile unsigned long *)0x40004000)
@@ -71,7 +68,7 @@
 
 //*****************************************************************************
 //
-// General-Purpose Input/Outputs (PORTB)
+// GPIO registers (PORTB)
 //
 //*****************************************************************************
 #define GPIO_PORTB_DATA_BITS_R  ((volatile unsigned long *)0x40005000)
@@ -98,7 +95,7 @@
 
 //*****************************************************************************
 //
-// General-Purpose Input/Outputs (PORTC)
+// GPIO registers (PORTC)
 //
 //*****************************************************************************
 #define GPIO_PORTC_DATA_BITS_R  ((volatile unsigned long *)0x40006000)
@@ -125,7 +122,7 @@
 
 //*****************************************************************************
 //
-// General-Purpose Input/Outputs (PORTD)
+// GPIO registers (PORTD)
 //
 //*****************************************************************************
 #define GPIO_PORTD_DATA_BITS_R  ((volatile unsigned long *)0x40007000)
@@ -152,7 +149,7 @@
 
 //*****************************************************************************
 //
-// Synchronous Serial Interface (SSI0)
+// SSI registers (SSI0)
 //
 //*****************************************************************************
 #define SSI0_CR0_R              (*((volatile unsigned long *)0x40008000))
@@ -167,7 +164,7 @@
 
 //*****************************************************************************
 //
-// Synchronous Serial Interface (SSI1)
+// SSI registers (SSI1)
 //
 //*****************************************************************************
 #define SSI1_CR0_R              (*((volatile unsigned long *)0x40009000))
@@ -182,7 +179,7 @@
 
 //*****************************************************************************
 //
-// Universal Asynchronous Receivers/Transmitters (UART0)
+// UART registers (UART0)
 //
 //*****************************************************************************
 #define UART0_DR_R              (*((volatile unsigned long *)0x4000C000))
@@ -202,7 +199,7 @@
 
 //*****************************************************************************
 //
-// Universal Asynchronous Receivers/Transmitters (UART1)
+// UART registers (UART1)
 //
 //*****************************************************************************
 #define UART1_DR_R              (*((volatile unsigned long *)0x4000D000))
@@ -222,95 +219,63 @@
 
 //*****************************************************************************
 //
-// Inter-Integrated Circuit (MASTER) Interface
+// I2C registers (I2C0 MASTER)
 //
 //*****************************************************************************
 #define I2C0_MASTER_MSA_R       (*((volatile unsigned long *)0x40020000))
-#define I2C0_MASTER_SOAR_R      (*((volatile unsigned long *)0x40020000))
-#define I2C0_MASTER_SCSR_R      (*((volatile unsigned long *)0x40020004))
 #define I2C0_MASTER_MCS_R       (*((volatile unsigned long *)0x40020004))
-#define I2C0_MASTER_SDR_R       (*((volatile unsigned long *)0x40020008))
 #define I2C0_MASTER_MDR_R       (*((volatile unsigned long *)0x40020008))
 #define I2C0_MASTER_MTPR_R      (*((volatile unsigned long *)0x4002000C))
-#define I2C0_MASTER_SIMR_R      (*((volatile unsigned long *)0x4002000C))
-#define I2C0_MASTER_SRIS_R      (*((volatile unsigned long *)0x40020010))
 #define I2C0_MASTER_MIMR_R      (*((volatile unsigned long *)0x40020010))
 #define I2C0_MASTER_MRIS_R      (*((volatile unsigned long *)0x40020014))
-#define I2C0_MASTER_SMIS_R      (*((volatile unsigned long *)0x40020014))
-#define I2C0_MASTER_SICR_R      (*((volatile unsigned long *)0x40020018))
 #define I2C0_MASTER_MMIS_R      (*((volatile unsigned long *)0x40020018))
 #define I2C0_MASTER_MICR_R      (*((volatile unsigned long *)0x4002001C))
 #define I2C0_MASTER_MCR_R       (*((volatile unsigned long *)0x40020020))
 
 //*****************************************************************************
 //
-// Inter-Integrated Circuit (SLAVE) Interface
+// I2C registers (I2C0 SLAVE)
 //
 //*****************************************************************************
-#define I2C0_SLAVE_MSA_R        (*((volatile unsigned long *)0x40020800))
 #define I2C0_SLAVE_SOAR_R       (*((volatile unsigned long *)0x40020800))
 #define I2C0_SLAVE_SCSR_R       (*((volatile unsigned long *)0x40020804))
-#define I2C0_SLAVE_MCS_R        (*((volatile unsigned long *)0x40020804))
 #define I2C0_SLAVE_SDR_R        (*((volatile unsigned long *)0x40020808))
-#define I2C0_SLAVE_MDR_R        (*((volatile unsigned long *)0x40020808))
-#define I2C0_SLAVE_MTPR_R       (*((volatile unsigned long *)0x4002080C))
 #define I2C0_SLAVE_SIMR_R       (*((volatile unsigned long *)0x4002080C))
 #define I2C0_SLAVE_SRIS_R       (*((volatile unsigned long *)0x40020810))
-#define I2C0_SLAVE_MIMR_R       (*((volatile unsigned long *)0x40020810))
-#define I2C0_SLAVE_MRIS_R       (*((volatile unsigned long *)0x40020814))
 #define I2C0_SLAVE_SMIS_R       (*((volatile unsigned long *)0x40020814))
 #define I2C0_SLAVE_SICR_R       (*((volatile unsigned long *)0x40020818))
-#define I2C0_SLAVE_MMIS_R       (*((volatile unsigned long *)0x40020818))
-#define I2C0_SLAVE_MICR_R       (*((volatile unsigned long *)0x4002081C))
-#define I2C0_SLAVE_MCR_R        (*((volatile unsigned long *)0x40020820))
 
 //*****************************************************************************
 //
-// Inter-Integrated Circuit (MASTER) Interface
+// I2C registers (I2C1 MASTER)
 //
 //*****************************************************************************
 #define I2C1_MASTER_MSA_R       (*((volatile unsigned long *)0x40021000))
-#define I2C1_MASTER_SOAR_R      (*((volatile unsigned long *)0x40021000))
-#define I2C1_MASTER_SCSR_R      (*((volatile unsigned long *)0x40021004))
 #define I2C1_MASTER_MCS_R       (*((volatile unsigned long *)0x40021004))
-#define I2C1_MASTER_SDR_R       (*((volatile unsigned long *)0x40021008))
 #define I2C1_MASTER_MDR_R       (*((volatile unsigned long *)0x40021008))
 #define I2C1_MASTER_MTPR_R      (*((volatile unsigned long *)0x4002100C))
-#define I2C1_MASTER_SIMR_R      (*((volatile unsigned long *)0x4002100C))
-#define I2C1_MASTER_SRIS_R      (*((volatile unsigned long *)0x40021010))
 #define I2C1_MASTER_MIMR_R      (*((volatile unsigned long *)0x40021010))
 #define I2C1_MASTER_MRIS_R      (*((volatile unsigned long *)0x40021014))
-#define I2C1_MASTER_SMIS_R      (*((volatile unsigned long *)0x40021014))
-#define I2C1_MASTER_SICR_R      (*((volatile unsigned long *)0x40021018))
 #define I2C1_MASTER_MMIS_R      (*((volatile unsigned long *)0x40021018))
 #define I2C1_MASTER_MICR_R      (*((volatile unsigned long *)0x4002101C))
 #define I2C1_MASTER_MCR_R       (*((volatile unsigned long *)0x40021020))
 
 //*****************************************************************************
 //
-// Inter-Integrated Circuit (SLAVE) Interface
+// I2C registers (I2C1 SLAVE)
 //
 //*****************************************************************************
-#define I2C1_SLAVE_MSA_R        (*((volatile unsigned long *)0x40021800))
 #define I2C1_SLAVE_SOAR_R       (*((volatile unsigned long *)0x40021800))
 #define I2C1_SLAVE_SCSR_R       (*((volatile unsigned long *)0x40021804))
-#define I2C1_SLAVE_MCS_R        (*((volatile unsigned long *)0x40021804))
 #define I2C1_SLAVE_SDR_R        (*((volatile unsigned long *)0x40021808))
-#define I2C1_SLAVE_MDR_R        (*((volatile unsigned long *)0x40021808))
-#define I2C1_SLAVE_MTPR_R       (*((volatile unsigned long *)0x4002180C))
 #define I2C1_SLAVE_SIMR_R       (*((volatile unsigned long *)0x4002180C))
 #define I2C1_SLAVE_SRIS_R       (*((volatile unsigned long *)0x40021810))
-#define I2C1_SLAVE_MIMR_R       (*((volatile unsigned long *)0x40021810))
-#define I2C1_SLAVE_MRIS_R       (*((volatile unsigned long *)0x40021814))
 #define I2C1_SLAVE_SMIS_R       (*((volatile unsigned long *)0x40021814))
 #define I2C1_SLAVE_SICR_R       (*((volatile unsigned long *)0x40021818))
-#define I2C1_SLAVE_MMIS_R       (*((volatile unsigned long *)0x40021818))
-#define I2C1_SLAVE_MICR_R       (*((volatile unsigned long *)0x4002181C))
-#define I2C1_SLAVE_MCR_R        (*((volatile unsigned long *)0x40021820))
 
 //*****************************************************************************
 //
-// General-Purpose Input/Outputs (PORTE)
+// GPIO registers (PORTE)
 //
 //*****************************************************************************
 #define GPIO_PORTE_DATA_BITS_R  ((volatile unsigned long *)0x40024000)
@@ -337,7 +302,7 @@
 
 //*****************************************************************************
 //
-// General-Purpose Input/Outputs (PORTF)
+// GPIO registers (PORTF)
 //
 //*****************************************************************************
 #define GPIO_PORTF_DATA_BITS_R  ((volatile unsigned long *)0x40025000)
@@ -364,7 +329,7 @@
 
 //*****************************************************************************
 //
-// General-Purpose Input/Outputs (PORTG)
+// GPIO registers (PORTG)
 //
 //*****************************************************************************
 #define GPIO_PORTG_DATA_BITS_R  ((volatile unsigned long *)0x40026000)
@@ -391,7 +356,7 @@
 
 //*****************************************************************************
 //
-// General-Purpose Input/Outputs (PORTH)
+// GPIO registers (PORTH)
 //
 //*****************************************************************************
 #define GPIO_PORTH_DATA_BITS_R  ((volatile unsigned long *)0x40027000)
@@ -418,7 +383,7 @@
 
 //*****************************************************************************
 //
-// General-Purpose Timers (TIMER0)
+// Timer registers (TIMER0)
 //
 //*****************************************************************************
 #define TIMER0_CFG_R            (*((volatile unsigned long *)0x40030000))
@@ -442,7 +407,7 @@
 
 //*****************************************************************************
 //
-// General-Purpose Timers (TIMER1)
+// Timer registers (TIMER1)
 //
 //*****************************************************************************
 #define TIMER1_CFG_R            (*((volatile unsigned long *)0x40031000))
@@ -466,7 +431,7 @@
 
 //*****************************************************************************
 //
-// General-Purpose Timers (TIMER2)
+// Timer registers (TIMER2)
 //
 //*****************************************************************************
 #define TIMER2_CFG_R            (*((volatile unsigned long *)0x40032000))
@@ -490,7 +455,7 @@
 
 //*****************************************************************************
 //
-// General-Purpose Timers (TIMER3)
+// Timer registers (TIMER3)
 //
 //*****************************************************************************
 #define TIMER3_CFG_R            (*((volatile unsigned long *)0x40033000))
@@ -514,40 +479,40 @@
 
 //*****************************************************************************
 //
-// Analog-to-Digital Converter (ADC)
+// ADC registers (ADC0)
 //
 //*****************************************************************************
-#define ADC_ACTSS_R             (*((volatile unsigned long *)0x40038000))
-#define ADC_RIS_R               (*((volatile unsigned long *)0x40038004))
-#define ADC_IM_R                (*((volatile unsigned long *)0x40038008))
-#define ADC_ISC_R               (*((volatile unsigned long *)0x4003800C))
-#define ADC_OSTAT_R             (*((volatile unsigned long *)0x40038010))
-#define ADC_EMUX_R              (*((volatile unsigned long *)0x40038014))
-#define ADC_USTAT_R             (*((volatile unsigned long *)0x40038018))
-#define ADC_SSPRI_R             (*((volatile unsigned long *)0x40038020))
-#define ADC_PSSI_R              (*((volatile unsigned long *)0x40038028))
-#define ADC_SAC_R               (*((volatile unsigned long *)0x40038030))
-#define ADC_SSMUX0_R            (*((volatile unsigned long *)0x40038040))
-#define ADC_SSCTL0_R            (*((volatile unsigned long *)0x40038044))
-#define ADC_SSFIFO0_R           (*((volatile unsigned long *)0x40038048))
-#define ADC_SSFSTAT0_R          (*((volatile unsigned long *)0x4003804C))
-#define ADC_SSMUX1_R            (*((volatile unsigned long *)0x40038060))
-#define ADC_SSCTL1_R            (*((volatile unsigned long *)0x40038064))
-#define ADC_SSFIFO1_R           (*((volatile unsigned long *)0x40038068))
-#define ADC_SSFSTAT1_R          (*((volatile unsigned long *)0x4003806C))
-#define ADC_SSMUX2_R            (*((volatile unsigned long *)0x40038080))
-#define ADC_SSCTL2_R            (*((volatile unsigned long *)0x40038084))
-#define ADC_SSFIFO2_R           (*((volatile unsigned long *)0x40038088))
-#define ADC_SSFSTAT2_R          (*((volatile unsigned long *)0x4003808C))
-#define ADC_SSMUX3_R            (*((volatile unsigned long *)0x400380A0))
-#define ADC_SSCTL3_R            (*((volatile unsigned long *)0x400380A4))
-#define ADC_SSFIFO3_R           (*((volatile unsigned long *)0x400380A8))
-#define ADC_SSFSTAT3_R          (*((volatile unsigned long *)0x400380AC))
-#define ADC_TMLB_R              (*((volatile unsigned long *)0x40038100))
+#define ADC0_ACTSS_R            (*((volatile unsigned long *)0x40038000))
+#define ADC0_RIS_R              (*((volatile unsigned long *)0x40038004))
+#define ADC0_IM_R               (*((volatile unsigned long *)0x40038008))
+#define ADC0_ISC_R              (*((volatile unsigned long *)0x4003800C))
+#define ADC0_OSTAT_R            (*((volatile unsigned long *)0x40038010))
+#define ADC0_EMUX_R             (*((volatile unsigned long *)0x40038014))
+#define ADC0_USTAT_R            (*((volatile unsigned long *)0x40038018))
+#define ADC0_SSPRI_R            (*((volatile unsigned long *)0x40038020))
+#define ADC0_PSSI_R             (*((volatile unsigned long *)0x40038028))
+#define ADC0_SAC_R              (*((volatile unsigned long *)0x40038030))
+#define ADC0_SSMUX0_R           (*((volatile unsigned long *)0x40038040))
+#define ADC0_SSCTL0_R           (*((volatile unsigned long *)0x40038044))
+#define ADC0_SSFIFO0_R          (*((volatile unsigned long *)0x40038048))
+#define ADC0_SSFSTAT0_R         (*((volatile unsigned long *)0x4003804C))
+#define ADC0_SSMUX1_R           (*((volatile unsigned long *)0x40038060))
+#define ADC0_SSCTL1_R           (*((volatile unsigned long *)0x40038064))
+#define ADC0_SSFIFO1_R          (*((volatile unsigned long *)0x40038068))
+#define ADC0_SSFSTAT1_R         (*((volatile unsigned long *)0x4003806C))
+#define ADC0_SSMUX2_R           (*((volatile unsigned long *)0x40038080))
+#define ADC0_SSCTL2_R           (*((volatile unsigned long *)0x40038084))
+#define ADC0_SSFIFO2_R          (*((volatile unsigned long *)0x40038088))
+#define ADC0_SSFSTAT2_R         (*((volatile unsigned long *)0x4003808C))
+#define ADC0_SSMUX3_R           (*((volatile unsigned long *)0x400380A0))
+#define ADC0_SSCTL3_R           (*((volatile unsigned long *)0x400380A4))
+#define ADC0_SSFIFO3_R          (*((volatile unsigned long *)0x400380A8))
+#define ADC0_SSFSTAT3_R         (*((volatile unsigned long *)0x400380AC))
+#define ADC0_TMLB_R             (*((volatile unsigned long *)0x40038100))
 
 //*****************************************************************************
 //
-// Analog Comparators (COMP)
+// Comparator registers (COMP)
 //
 //*****************************************************************************
 #define COMP_ACMIS_R            (*((volatile unsigned long *)0x4003C000))
@@ -561,30 +526,17 @@
 
 //*****************************************************************************
 //
-// Ethernet Controller (MAC)
+// Ethernet MAC registers (MAC)
 //
 //*****************************************************************************
-#define MAC_MR0_R               (*((volatile unsigned long *)0x40048000))
 #define MAC_RIS_R               (*((volatile unsigned long *)0x40048000))
 #define MAC_IACK_R              (*((volatile unsigned long *)0x40048000))
-#define MAC_MR1_R               (*((volatile unsigned long *)0x40048001))
-#define MAC_MR2_R               (*((volatile unsigned long *)0x40048002))
-#define MAC_MR3_R               (*((volatile unsigned long *)0x40048003))
 #define MAC_IM_R                (*((volatile unsigned long *)0x40048004))
-#define MAC_MR4_R               (*((volatile unsigned long *)0x40048004))
-#define MAC_MR5_R               (*((volatile unsigned long *)0x40048005))
-#define MAC_MR6_R               (*((volatile unsigned long *)0x40048006))
 #define MAC_RCTL_R              (*((volatile unsigned long *)0x40048008))
 #define MAC_TCTL_R              (*((volatile unsigned long *)0x4004800C))
 #define MAC_DATA_R              (*((volatile unsigned long *)0x40048010))
-#define MAC_MR16_R              (*((volatile unsigned long *)0x40048010))
-#define MAC_MR17_R              (*((volatile unsigned long *)0x40048011))
-#define MAC_MR18_R              (*((volatile unsigned long *)0x40048012))
-#define MAC_MR19_R              (*((volatile unsigned long *)0x40048013))
 #define MAC_IA0_R               (*((volatile unsigned long *)0x40048014))
-#define MAC_MR23_R              (*((volatile unsigned long *)0x40048017))
 #define MAC_IA1_R               (*((volatile unsigned long *)0x40048018))
-#define MAC_MR24_R              (*((volatile unsigned long *)0x40048018))
 #define MAC_THR_R               (*((volatile unsigned long *)0x4004801C))
 #define MAC_MCTL_R              (*((volatile unsigned long *)0x40048020))
 #define MAC_MDV_R               (*((volatile unsigned long *)0x40048024))
@@ -595,7 +547,41 @@
 
 //*****************************************************************************
 //
-// Hibernation Module (HIB)
+// Ethernet Controller PHY registers (MAC)
+//
+//*****************************************************************************
+#define PHY_MR0                 0x00000000  // Ethernet PHY Management Register
+                                            // 0 - Control
+#define PHY_MR1                 0x00000001  // Ethernet PHY Management Register
+                                            // 1 - Status
+#define PHY_MR2                 0x00000002  // Ethernet PHY Management Register
+                                            // 2 - PHY Identifier 1
+#define PHY_MR3                 0x00000003  // Ethernet PHY Management Register
+                                            // 3 - PHY Identifier 2
+#define PHY_MR4                 0x00000004  // Ethernet PHY Management Register
+                                            // 4 - Auto-Negotiation
+                                            // Advertisement
+#define PHY_MR5                 0x00000005  // Ethernet PHY Management Register
+                                            // 5 - Auto-Negotiation Link
+                                            // Partner Base Page Ability
+#define PHY_MR6                 0x00000006  // Ethernet PHY Management Register
+                                            // 6 - Auto-Negotiation Expansion
+#define PHY_MR16                0x00000010  // Ethernet PHY Management Register
+                                            // 16 - Vendor-Specific
+#define PHY_MR17                0x00000011  // Ethernet PHY Management Register
+                                            // 17 - Mode Control/Status
+#define PHY_MR18                0x00000012  // Ethernet PHY Management Register
+                                            // 18 - Diagnostic
+#define PHY_MR19                0x00000013  // Ethernet PHY Management Register
+                                            // 19 - Transceiver Control
+#define PHY_MR23                0x00000017  // Ethernet PHY Management Register
+                                            // 23 - LED Configuration
+#define PHY_MR24                0x00000018  // Ethernet PHY Management Register
+                                            // 24 -MDI/MDIX Control
+
+//*****************************************************************************
+//
+// Hibernation module registers (HIB)
 //
 //*****************************************************************************
 #define HIB_RTCC_R              (*((volatile unsigned long *)0x400FC000))
@@ -612,7 +598,7 @@
 
 //*****************************************************************************
 //
-// Internal Memory (FLASH)
+// FLASH registers (FLASH CTRL)
 //
 //*****************************************************************************
 #define FLASH_FMA_R             (*((volatile unsigned long *)0x400FD000))
@@ -636,7 +622,7 @@
 
 //*****************************************************************************
 //
-// System Control (SYSCTL)
+// System Control registers (SYSCTL)
 //
 //*****************************************************************************
 #define SYSCTL_DID0_R           (*((volatile unsigned long *)0x400FE000))
@@ -671,7 +657,7 @@
 
 //*****************************************************************************
 //
-// Nested Vectored Interrupt Ctrl (NVIC)
+// NVIC registers (NVIC)
 //
 //*****************************************************************************
 #define NVIC_INT_TYPE_R         (*((volatile unsigned long *)0xE000E004))
@@ -718,8 +704,14 @@
 #define NVIC_MPU_TYPE_R         (*((volatile unsigned long *)0xE000ED90))
 #define NVIC_MPU_CTRL_R         (*((volatile unsigned long *)0xE000ED94))
 #define NVIC_MPU_NUMBER_R       (*((volatile unsigned long *)0xE000ED98))
-#define NVIC_MPU_R              (*((volatile unsigned long *)0xE000ED9C))
+#define NVIC_MPU_BASE_R         (*((volatile unsigned long *)0xE000ED9C))
 #define NVIC_MPU_ATTR_R         (*((volatile unsigned long *)0xE000EDA0))
+#define NVIC_MPU_BASE1_R        (*((volatile unsigned long *)0xE000EDA4))
+#define NVIC_MPU_ATTR1_R        (*((volatile unsigned long *)0xE000EDA8))
+#define NVIC_MPU_BASE2_R        (*((volatile unsigned long *)0xE000EDAC))
+#define NVIC_MPU_ATTR2_R        (*((volatile unsigned long *)0xE000EDB0))
+#define NVIC_MPU_BASE3_R        (*((volatile unsigned long *)0xE000EDB4))
+#define NVIC_MPU_ATTR3_R        (*((volatile unsigned long *)0xE000EDB8))
 #define NVIC_DBG_CTRL_R         (*((volatile unsigned long *)0xE000EDF0))
 #define NVIC_DBG_XFER_R         (*((volatile unsigned long *)0xE000EDF4))
 #define NVIC_DBG_DATA_R         (*((volatile unsigned long *)0xE000EDF8))
@@ -731,7 +723,7 @@
 // The following are defines for the bit fields in the WDT_O_LOAD register.
 //
 //*****************************************************************************
-#define WDT_LOAD_M              0xFFFFFFFF  // Watchdog Load Value.
+#define WDT_LOAD_M              0xFFFFFFFF  // Watchdog Load Value
 #define WDT_LOAD_S              0
 
 //*****************************************************************************
@@ -739,7 +731,7 @@
 // The following are defines for the bit fields in the WDT_O_VALUE register.
 //
 //*****************************************************************************
-#define WDT_VALUE_M             0xFFFFFFFF  // Watchdog Value.
+#define WDT_VALUE_M             0xFFFFFFFF  // Watchdog Value
 #define WDT_VALUE_S             0
 
 //*****************************************************************************
@@ -747,15 +739,15 @@
 // The following are defines for the bit fields in the WDT_O_CTL register.
 //
 //*****************************************************************************
-#define WDT_CTL_RESEN           0x00000002  // Watchdog Reset Enable.
-#define WDT_CTL_INTEN           0x00000001  // Watchdog Interrupt Enable.
+#define WDT_CTL_RESEN           0x00000002  // Watchdog Reset Enable
+#define WDT_CTL_INTEN           0x00000001  // Watchdog Interrupt Enable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the WDT_O_ICR register.
 //
 //*****************************************************************************
-#define WDT_ICR_M               0xFFFFFFFF  // Watchdog Interrupt Clear.
+#define WDT_ICR_M               0xFFFFFFFF  // Watchdog Interrupt Clear
 #define WDT_ICR_S               0
 
 //*****************************************************************************
@@ -763,40 +755,42 @@
 // The following are defines for the bit fields in the WDT_O_RIS register.
 //
 //*****************************************************************************
-#define WDT_RIS_WDTRIS          0x00000001  // Watchdog Raw Interrupt Status.
+#define WDT_RIS_WDTRIS          0x00000001  // Watchdog Raw Interrupt Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the WDT_O_MIS register.
 //
 //*****************************************************************************
-#define WDT_MIS_WDTMIS          0x00000001  // Watchdog Masked Interrupt
-                                            // Status.
+#define WDT_MIS_WDTMIS          0x00000001  // Watchdog Masked Interrupt Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the WDT_O_TEST register.
 //
 //*****************************************************************************
-#define WDT_TEST_STALL          0x00000100  // Watchdog Stall Enable.
+#define WDT_TEST_STALL          0x00000100  // Watchdog Stall Enable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the WDT_O_LOCK register.
 //
 //*****************************************************************************
-#define WDT_LOCK_M              0xFFFFFFFF  // Watchdog Lock.
+#define WDT_LOCK_M              0xFFFFFFFF  // Watchdog Lock
 #define WDT_LOCK_UNLOCKED       0x00000000  // Unlocked
 #define WDT_LOCK_LOCKED         0x00000001  // Locked
+#define WDT_LOCK_UNLOCK         0x1ACCE551  // Unlocks the watchdog timer
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the GPIO_O_LOCK register.
 //
 //*****************************************************************************
-#define GPIO_LOCK_M             0xFFFFFFFF  // GPIO Lock.
-#define GPIO_LOCK_UNLOCKED      0x00000000  // unlocked
-#define GPIO_LOCK_LOCKED        0x00000001  // locked
+#define GPIO_LOCK_M             0xFFFFFFFF  // GPIO Lock
+#define GPIO_LOCK_UNLOCKED      0x00000000  // The GPIOCR register is unlocked
+                                            // and may be modified
+#define GPIO_LOCK_LOCKED        0x00000001  // The GPIOCR register is locked
+                                            // and may not be modified
 #define GPIO_LOCK_KEY           0x1ACCE551  // Unlocks the GPIO_CR register
 
 //*****************************************************************************
@@ -804,15 +798,15 @@
 // The following are defines for the bit fields in the SSI_O_CR0 register.
 //
 //*****************************************************************************
-#define SSI_CR0_SCR_M           0x0000FF00  // SSI Serial Clock Rate.
-#define SSI_CR0_SPH             0x00000080  // SSI Serial Clock Phase.
-#define SSI_CR0_SPO             0x00000040  // SSI Serial Clock Polarity.
-#define SSI_CR0_FRF_M           0x00000030  // SSI Frame Format Select.
+#define SSI_CR0_SCR_M           0x0000FF00  // SSI Serial Clock Rate
+#define SSI_CR0_SPH             0x00000080  // SSI Serial Clock Phase
+#define SSI_CR0_SPO             0x00000040  // SSI Serial Clock Polarity
+#define SSI_CR0_FRF_M           0x00000030  // SSI Frame Format Select
 #define SSI_CR0_FRF_MOTO        0x00000000  // Freescale SPI Frame Format
 #define SSI_CR0_FRF_TI          0x00000010  // Texas Instruments Synchronous
                                             // Serial Frame Format
 #define SSI_CR0_FRF_NMW         0x00000020  // MICROWIRE Frame Format
-#define SSI_CR0_DSS_M           0x0000000F  // SSI Data Size Select.
+#define SSI_CR0_DSS_M           0x0000000F  // SSI Data Size Select
 #define SSI_CR0_DSS_4           0x00000003  // 4-bit data
 #define SSI_CR0_DSS_5           0x00000004  // 5-bit data
 #define SSI_CR0_DSS_6           0x00000005  // 6-bit data
@@ -833,18 +827,18 @@
 // The following are defines for the bit fields in the SSI_O_CR1 register.
 //
 //*****************************************************************************
-#define SSI_CR1_SOD             0x00000008  // SSI Slave Mode Output Disable.
-#define SSI_CR1_MS              0x00000004  // SSI Master/Slave Select.
+#define SSI_CR1_SOD             0x00000008  // SSI Slave Mode Output Disable
+#define SSI_CR1_MS              0x00000004  // SSI Master/Slave Select
 #define SSI_CR1_SSE             0x00000002  // SSI Synchronous Serial Port
-                                            // Enable.
-#define SSI_CR1_LBM             0x00000001  // SSI Loopback Mode.
+                                            // Enable
+#define SSI_CR1_LBM             0x00000001  // SSI Loopback Mode
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SSI_O_DR register.
 //
 //*****************************************************************************
-#define SSI_DR_DATA_M           0x0000FFFF  // SSI Receive/Transmit Data.
+#define SSI_DR_DATA_M           0x0000FFFF  // SSI Receive/Transmit Data
 #define SSI_DR_DATA_S           0
 
 //*****************************************************************************
@@ -852,18 +846,18 @@
 // The following are defines for the bit fields in the SSI_O_SR register.
 //
 //*****************************************************************************
-#define SSI_SR_BSY              0x00000010  // SSI Busy Bit.
-#define SSI_SR_RFF              0x00000008  // SSI Receive FIFO Full.
-#define SSI_SR_RNE              0x00000004  // SSI Receive FIFO Not Empty.
-#define SSI_SR_TNF              0x00000002  // SSI Transmit FIFO Not Full.
-#define SSI_SR_TFE              0x00000001  // SSI Transmit FIFO Empty.
+#define SSI_SR_BSY              0x00000010  // SSI Busy Bit
+#define SSI_SR_RFF              0x00000008  // SSI Receive FIFO Full
+#define SSI_SR_RNE              0x00000004  // SSI Receive FIFO Not Empty
+#define SSI_SR_TNF              0x00000002  // SSI Transmit FIFO Not Full
+#define SSI_SR_TFE              0x00000001  // SSI Transmit FIFO Empty
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SSI_O_CPSR register.
 //
 //*****************************************************************************
-#define SSI_CPSR_CPSDVSR_M      0x000000FF  // SSI Clock Prescale Divisor.
+#define SSI_CPSR_CPSDVSR_M      0x000000FF  // SSI Clock Prescale Divisor
 #define SSI_CPSR_CPSDVSR_S      0
 
 //*****************************************************************************
@@ -871,13 +865,12 @@
 // The following are defines for the bit fields in the SSI_O_IM register.
 //
 //*****************************************************************************
-#define SSI_IM_TXIM             0x00000008  // SSI Transmit FIFO Interrupt
-                                            // Mask.
-#define SSI_IM_RXIM             0x00000004  // SSI Receive FIFO Interrupt Mask.
+#define SSI_IM_TXIM             0x00000008  // SSI Transmit FIFO Interrupt Mask
+#define SSI_IM_RXIM             0x00000004  // SSI Receive FIFO Interrupt Mask
 #define SSI_IM_RTIM             0x00000002  // SSI Receive Time-Out Interrupt
-                                            // Mask.
+                                            // Mask
 #define SSI_IM_RORIM            0x00000001  // SSI Receive Overrun Interrupt
-                                            // Mask.
+                                            // Mask
 
 //*****************************************************************************
 //
@@ -885,13 +878,13 @@
 //
 //*****************************************************************************
 #define SSI_RIS_TXRIS           0x00000008  // SSI Transmit FIFO Raw Interrupt
-                                            // Status.
+                                            // Status
 #define SSI_RIS_RXRIS           0x00000004  // SSI Receive FIFO Raw Interrupt
-                                            // Status.
+                                            // Status
 #define SSI_RIS_RTRIS           0x00000002  // SSI Receive Time-Out Raw
-                                            // Interrupt Status.
+                                            // Interrupt Status
 #define SSI_RIS_RORRIS          0x00000001  // SSI Receive Overrun Raw
-                                            // Interrupt Status.
+                                            // Interrupt Status
 
 //*****************************************************************************
 //
@@ -899,13 +892,13 @@
 //
 //*****************************************************************************
 #define SSI_MIS_TXMIS           0x00000008  // SSI Transmit FIFO Masked
-                                            // Interrupt Status.
+                                            // Interrupt Status
 #define SSI_MIS_RXMIS           0x00000004  // SSI Receive FIFO Masked
-                                            // Interrupt Status.
+                                            // Interrupt Status
 #define SSI_MIS_RTMIS           0x00000002  // SSI Receive Time-Out Masked
-                                            // Interrupt Status.
+                                            // Interrupt Status
 #define SSI_MIS_RORMIS          0x00000001  // SSI Receive Overrun Masked
-                                            // Interrupt Status.
+                                            // Interrupt Status
 
 //*****************************************************************************
 //
@@ -913,20 +906,20 @@
 //
 //*****************************************************************************
 #define SSI_ICR_RTIC            0x00000002  // SSI Receive Time-Out Interrupt
-                                            // Clear.
+                                            // Clear
 #define SSI_ICR_RORIC           0x00000001  // SSI Receive Overrun Interrupt
-                                            // Clear.
+                                            // Clear
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the UART_O_DR register.
 //
 //*****************************************************************************
-#define UART_DR_OE              0x00000800  // UART Overrun Error.
-#define UART_DR_BE              0x00000400  // UART Break Error.
-#define UART_DR_PE              0x00000200  // UART Parity Error.
-#define UART_DR_FE              0x00000100  // UART Framing Error.
-#define UART_DR_DATA_M          0x000000FF  // Data Transmitted or Received.
+#define UART_DR_OE              0x00000800  // UART Overrun Error
+#define UART_DR_BE              0x00000400  // UART Break Error
+#define UART_DR_PE              0x00000200  // UART Parity Error
+#define UART_DR_FE              0x00000100  // UART Framing Error
+#define UART_DR_DATA_M          0x000000FF  // Data Transmitted or Received
 #define UART_DR_DATA_S          0
 
 //*****************************************************************************
@@ -934,17 +927,17 @@
 // The following are defines for the bit fields in the UART_O_RSR register.
 //
 //*****************************************************************************
-#define UART_RSR_OE             0x00000008  // UART Overrun Error.
-#define UART_RSR_BE             0x00000004  // UART Break Error.
-#define UART_RSR_PE             0x00000002  // UART Parity Error.
-#define UART_RSR_FE             0x00000001  // UART Framing Error.
+#define UART_RSR_OE             0x00000008  // UART Overrun Error
+#define UART_RSR_BE             0x00000004  // UART Break Error
+#define UART_RSR_PE             0x00000002  // UART Parity Error
+#define UART_RSR_FE             0x00000001  // UART Framing Error
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the UART_O_ECR register.
 //
 //*****************************************************************************
-#define UART_ECR_DATA_M         0x000000FF  // Error Clear.
+#define UART_ECR_DATA_M         0x000000FF  // Error Clear
 #define UART_ECR_DATA_S         0
 
 //*****************************************************************************
@@ -952,18 +945,18 @@
 // The following are defines for the bit fields in the UART_O_FR register.
 //
 //*****************************************************************************
-#define UART_FR_TXFE            0x00000080  // UART Transmit FIFO Empty.
-#define UART_FR_RXFF            0x00000040  // UART Receive FIFO Full.
-#define UART_FR_TXFF            0x00000020  // UART Transmit FIFO Full.
-#define UART_FR_RXFE            0x00000010  // UART Receive FIFO Empty.
-#define UART_FR_BUSY            0x00000008  // UART Busy.
+#define UART_FR_TXFE            0x00000080  // UART Transmit FIFO Empty
+#define UART_FR_RXFF            0x00000040  // UART Receive FIFO Full
+#define UART_FR_TXFF            0x00000020  // UART Transmit FIFO Full
+#define UART_FR_RXFE            0x00000010  // UART Receive FIFO Empty
+#define UART_FR_BUSY            0x00000008  // UART Busy
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the UART_O_ILPR register.
 //
 //*****************************************************************************
-#define UART_ILPR_ILPDVSR_M     0x000000FF  // IrDA Low-Power Divisor.
+#define UART_ILPR_ILPDVSR_M     0x000000FF  // IrDA Low-Power Divisor
 #define UART_ILPR_ILPDVSR_S     0
 
 //*****************************************************************************
@@ -971,7 +964,7 @@
 // The following are defines for the bit fields in the UART_O_IBRD register.
 //
 //*****************************************************************************
-#define UART_IBRD_DIVINT_M      0x0000FFFF  // Integer Baud-Rate Divisor.
+#define UART_IBRD_DIVINT_M      0x0000FFFF  // Integer Baud-Rate Divisor
 #define UART_IBRD_DIVINT_S      0
 
 //*****************************************************************************
@@ -979,7 +972,7 @@
 // The following are defines for the bit fields in the UART_O_FBRD register.
 //
 //*****************************************************************************
-#define UART_FBRD_DIVFRAC_M     0x0000003F  // Fractional Baud-Rate Divisor.
+#define UART_FBRD_DIVFRAC_M     0x0000003F  // Fractional Baud-Rate Divisor
 #define UART_FBRD_DIVFRAC_S     0
 
 //*****************************************************************************
@@ -987,29 +980,29 @@
 // The following are defines for the bit fields in the UART_O_LCRH register.
 //
 //*****************************************************************************
-#define UART_LCRH_SPS           0x00000080  // UART Stick Parity Select.
-#define UART_LCRH_WLEN_M        0x00000060  // UART Word Length.
+#define UART_LCRH_SPS           0x00000080  // UART Stick Parity Select
+#define UART_LCRH_WLEN_M        0x00000060  // UART Word Length
 #define UART_LCRH_WLEN_5        0x00000000  // 5 bits (default)
 #define UART_LCRH_WLEN_6        0x00000020  // 6 bits
 #define UART_LCRH_WLEN_7        0x00000040  // 7 bits
 #define UART_LCRH_WLEN_8        0x00000060  // 8 bits
-#define UART_LCRH_FEN           0x00000010  // UART Enable FIFOs.
-#define UART_LCRH_STP2          0x00000008  // UART Two Stop Bits Select.
-#define UART_LCRH_EPS           0x00000004  // UART Even Parity Select.
-#define UART_LCRH_PEN           0x00000002  // UART Parity Enable.
-#define UART_LCRH_BRK           0x00000001  // UART Send Break.
+#define UART_LCRH_FEN           0x00000010  // UART Enable FIFOs
+#define UART_LCRH_STP2          0x00000008  // UART Two Stop Bits Select
+#define UART_LCRH_EPS           0x00000004  // UART Even Parity Select
+#define UART_LCRH_PEN           0x00000002  // UART Parity Enable
+#define UART_LCRH_BRK           0x00000001  // UART Send Break
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the UART_O_CTL register.
 //
 //*****************************************************************************
-#define UART_CTL_RXE            0x00000200  // UART Receive Enable.
-#define UART_CTL_TXE            0x00000100  // UART Transmit Enable.
-#define UART_CTL_LBE            0x00000080  // UART Loop Back Enable.
-#define UART_CTL_SIRLP          0x00000004  // UART SIR Low Power Mode.
-#define UART_CTL_SIREN          0x00000002  // UART SIR Enable.
-#define UART_CTL_UARTEN         0x00000001  // UART Enable.
+#define UART_CTL_RXE            0x00000200  // UART Receive Enable
+#define UART_CTL_TXE            0x00000100  // UART Transmit Enable
+#define UART_CTL_LBE            0x00000080  // UART Loop Back Enable
+#define UART_CTL_SIRLP          0x00000004  // UART SIR Low-Power Mode
+#define UART_CTL_SIREN          0x00000002  // UART SIR Enable
+#define UART_CTL_UARTEN         0x00000001  // UART Enable
 
 //*****************************************************************************
 //
@@ -1017,19 +1010,19 @@
 //
 //*****************************************************************************
 #define UART_IFLS_RX_M          0x00000038  // UART Receive Interrupt FIFO
-                                            // Level Select.
-#define UART_IFLS_RX1_8         0x00000000  // RX FIFO <= 1/8 full
-#define UART_IFLS_RX2_8         0x00000008  // RX FIFO <= 1/4 full
-#define UART_IFLS_RX4_8         0x00000010  // RX FIFO <= 1/2 full (default)
-#define UART_IFLS_RX6_8         0x00000018  // RX FIFO <= 3/4 full
-#define UART_IFLS_RX7_8         0x00000020  // RX FIFO <= 7/8 full
+                                            // Level Select
+#define UART_IFLS_RX1_8         0x00000000  // RX FIFO >= 1/8 full
+#define UART_IFLS_RX2_8         0x00000008  // RX FIFO >= 1/4 full
+#define UART_IFLS_RX4_8         0x00000010  // RX FIFO >= 1/2 full (default)
+#define UART_IFLS_RX6_8         0x00000018  // RX FIFO >= 3/4 full
+#define UART_IFLS_RX7_8         0x00000020  // RX FIFO >= 7/8 full
 #define UART_IFLS_TX_M          0x00000007  // UART Transmit Interrupt FIFO
-                                            // Level Select.
-#define UART_IFLS_TX1_8         0x00000000  // TX FIFO >= 1/8 full
-#define UART_IFLS_TX2_8         0x00000001  // TX FIFO >= 1/4 full
-#define UART_IFLS_TX4_8         0x00000002  // TX FIFO >= 1/2 full (default)
-#define UART_IFLS_TX6_8         0x00000003  // TX FIFO >= 3/4 full
-#define UART_IFLS_TX7_8         0x00000004  // TX FIFO >= 7/8 full
+                                            // Level Select
+#define UART_IFLS_TX1_8         0x00000000  // TX FIFO <= 1/8 full
+#define UART_IFLS_TX2_8         0x00000001  // TX FIFO <= 1/4 full
+#define UART_IFLS_TX4_8         0x00000002  // TX FIFO <= 1/2 full (default)
+#define UART_IFLS_TX6_8         0x00000003  // TX FIFO <= 3/4 full
+#define UART_IFLS_TX7_8         0x00000004  // TX FIFO <= 7/8 full
 
 //*****************************************************************************
 //
@@ -1037,16 +1030,15 @@
 //
 //*****************************************************************************
 #define UART_IM_OEIM            0x00000400  // UART Overrun Error Interrupt
-                                            // Mask.
-#define UART_IM_BEIM            0x00000200  // UART Break Error Interrupt Mask.
-#define UART_IM_PEIM            0x00000100  // UART Parity Error Interrupt
-                                            // Mask.
+                                            // Mask
+#define UART_IM_BEIM            0x00000200  // UART Break Error Interrupt Mask
+#define UART_IM_PEIM            0x00000100  // UART Parity Error Interrupt Mask
 #define UART_IM_FEIM            0x00000080  // UART Framing Error Interrupt
-                                            // Mask.
+                                            // Mask
 #define UART_IM_RTIM            0x00000040  // UART Receive Time-Out Interrupt
-                                            // Mask.
-#define UART_IM_TXIM            0x00000020  // UART Transmit Interrupt Mask.
-#define UART_IM_RXIM            0x00000010  // UART Receive Interrupt Mask.
+                                            // Mask
+#define UART_IM_TXIM            0x00000020  // UART Transmit Interrupt Mask
+#define UART_IM_RXIM            0x00000010  // UART Receive Interrupt Mask
 
 //*****************************************************************************
 //
@@ -1054,19 +1046,19 @@
 //
 //*****************************************************************************
 #define UART_RIS_OERIS          0x00000400  // UART Overrun Error Raw Interrupt
-                                            // Status.
+                                            // Status
 #define UART_RIS_BERIS          0x00000200  // UART Break Error Raw Interrupt
-                                            // Status.
+                                            // Status
 #define UART_RIS_PERIS          0x00000100  // UART Parity Error Raw Interrupt
-                                            // Status.
+                                            // Status
 #define UART_RIS_FERIS          0x00000080  // UART Framing Error Raw Interrupt
-                                            // Status.
+                                            // Status
 #define UART_RIS_RTRIS          0x00000040  // UART Receive Time-Out Raw
-                                            // Interrupt Status.
+                                            // Interrupt Status
 #define UART_RIS_TXRIS          0x00000020  // UART Transmit Raw Interrupt
-                                            // Status.
+                                            // Status
 #define UART_RIS_RXRIS          0x00000010  // UART Receive Raw Interrupt
-                                            // Status.
+                                            // Status
 
 //*****************************************************************************
 //
@@ -1074,41 +1066,40 @@
 //
 //*****************************************************************************
 #define UART_MIS_OEMIS          0x00000400  // UART Overrun Error Masked
-                                            // Interrupt Status.
+                                            // Interrupt Status
 #define UART_MIS_BEMIS          0x00000200  // UART Break Error Masked
-                                            // Interrupt Status.
+                                            // Interrupt Status
 #define UART_MIS_PEMIS          0x00000100  // UART Parity Error Masked
-                                            // Interrupt Status.
+                                            // Interrupt Status
 #define UART_MIS_FEMIS          0x00000080  // UART Framing Error Masked
-                                            // Interrupt Status.
+                                            // Interrupt Status
 #define UART_MIS_RTMIS          0x00000040  // UART Receive Time-Out Masked
-                                            // Interrupt Status.
+                                            // Interrupt Status
 #define UART_MIS_TXMIS          0x00000020  // UART Transmit Masked Interrupt
-                                            // Status.
+                                            // Status
 #define UART_MIS_RXMIS          0x00000010  // UART Receive Masked Interrupt
-                                            // Status.
+                                            // Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the UART_O_ICR register.
 //
 //*****************************************************************************
-#define UART_ICR_OEIC           0x00000400  // Overrun Error Interrupt Clear.
-#define UART_ICR_BEIC           0x00000200  // Break Error Interrupt Clear.
-#define UART_ICR_PEIC           0x00000100  // Parity Error Interrupt Clear.
-#define UART_ICR_FEIC           0x00000080  // Framing Error Interrupt Clear.
-#define UART_ICR_RTIC           0x00000040  // Receive Time-Out Interrupt
-                                            // Clear.
-#define UART_ICR_TXIC           0x00000020  // Transmit Interrupt Clear.
-#define UART_ICR_RXIC           0x00000010  // Receive Interrupt Clear.
+#define UART_ICR_OEIC           0x00000400  // Overrun Error Interrupt Clear
+#define UART_ICR_BEIC           0x00000200  // Break Error Interrupt Clear
+#define UART_ICR_PEIC           0x00000100  // Parity Error Interrupt Clear
+#define UART_ICR_FEIC           0x00000080  // Framing Error Interrupt Clear
+#define UART_ICR_RTIC           0x00000040  // Receive Time-Out Interrupt Clear
+#define UART_ICR_TXIC           0x00000020  // Transmit Interrupt Clear
+#define UART_ICR_RXIC           0x00000010  // Receive Interrupt Clear
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2C_O_MSA register.
 //
 //*****************************************************************************
-#define I2C_MSA_SA_M            0x000000FE  // I2C Slave Address.
-#define I2C_MSA_RS              0x00000001  // Receive not send.
+#define I2C_MSA_SA_M            0x000000FE  // I2C Slave Address
+#define I2C_MSA_RS              0x00000001  // Receive not send
 #define I2C_MSA_SA_S            1
 
 //*****************************************************************************
@@ -1116,7 +1107,7 @@
 // The following are defines for the bit fields in the I2C_O_SOAR register.
 //
 //*****************************************************************************
-#define I2C_SOAR_OAR_M          0x0000007F  // I2C Slave Own Address.
+#define I2C_SOAR_OAR_M          0x0000007F  // I2C Slave Own Address
 #define I2C_SOAR_OAR_S          0
 
 //*****************************************************************************
@@ -1124,34 +1115,34 @@
 // The following are defines for the bit fields in the I2C_O_SCSR register.
 //
 //*****************************************************************************
-#define I2C_SCSR_FBR            0x00000004  // First Byte Received.
-#define I2C_SCSR_TREQ           0x00000002  // Transmit Request.
-#define I2C_SCSR_DA             0x00000001  // Device Active.
-#define I2C_SCSR_RREQ           0x00000001  // Receive Request.
+#define I2C_SCSR_FBR            0x00000004  // First Byte Received
+#define I2C_SCSR_TREQ           0x00000002  // Transmit Request
+#define I2C_SCSR_DA             0x00000001  // Device Active
+#define I2C_SCSR_RREQ           0x00000001  // Receive Request
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2C_O_MCS register.
 //
 //*****************************************************************************
-#define I2C_MCS_BUSBSY          0x00000040  // Bus Busy.
-#define I2C_MCS_IDLE            0x00000020  // I2C Idle.
-#define I2C_MCS_ARBLST          0x00000010  // Arbitration Lost.
-#define I2C_MCS_ACK             0x00000008  // Data Acknowledge Enable.
-#define I2C_MCS_DATACK          0x00000008  // Acknowledge Data.
-#define I2C_MCS_ADRACK          0x00000004  // Acknowledge Address.
-#define I2C_MCS_STOP            0x00000004  // Generate STOP.
-#define I2C_MCS_START           0x00000002  // Generate START.
-#define I2C_MCS_ERROR           0x00000002  // Error.
-#define I2C_MCS_RUN             0x00000001  // I2C Master Enable.
-#define I2C_MCS_BUSY            0x00000001  // I2C Busy.
+#define I2C_MCS_BUSBSY          0x00000040  // Bus Busy
+#define I2C_MCS_IDLE            0x00000020  // I2C Idle
+#define I2C_MCS_ARBLST          0x00000010  // Arbitration Lost
+#define I2C_MCS_ACK             0x00000008  // Data Acknowledge Enable
+#define I2C_MCS_DATACK          0x00000008  // Acknowledge Data
+#define I2C_MCS_ADRACK          0x00000004  // Acknowledge Address
+#define I2C_MCS_STOP            0x00000004  // Generate STOP
+#define I2C_MCS_START           0x00000002  // Generate START
+#define I2C_MCS_ERROR           0x00000002  // Error
+#define I2C_MCS_RUN             0x00000001  // I2C Master Enable
+#define I2C_MCS_BUSY            0x00000001  // I2C Busy
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2C_O_SDR register.
 //
 //*****************************************************************************
-#define I2C_SDR_DATA_M          0x000000FF  // Data for Transfer.
+#define I2C_SDR_DATA_M          0x000000FF  // Data for Transfer
 #define I2C_SDR_DATA_S          0
 
 //*****************************************************************************
@@ -1159,7 +1150,7 @@
 // The following are defines for the bit fields in the I2C_O_MDR register.
 //
 //*****************************************************************************
-#define I2C_MDR_DATA_M          0x000000FF  // Data Transferred.
+#define I2C_MDR_DATA_M          0x000000FF  // Data Transferred
 #define I2C_MDR_DATA_S          0
 
 //*****************************************************************************
@@ -1167,7 +1158,7 @@
 // The following are defines for the bit fields in the I2C_O_MTPR register.
 //
 //*****************************************************************************
-#define I2C_MTPR_TPR_M          0x000000FF  // SCL Clock Period.
+#define I2C_MTPR_TPR_M          0x0000007F  // SCL Clock Period
 #define I2C_MTPR_TPR_S          0
 
 //*****************************************************************************
@@ -1175,88 +1166,88 @@
 // The following are defines for the bit fields in the I2C_O_SIMR register.
 //
 //*****************************************************************************
-#define I2C_SIMR_IM             0x00000001  // Data Interrupt Mask.
+#define I2C_SIMR_DATAIM         0x00000001  // Data Interrupt Mask
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2C_O_SRIS register.
 //
 //*****************************************************************************
-#define I2C_SRIS_RIS            0x00000001  // Data Raw Interrupt Status.
+#define I2C_SRIS_DATARIS        0x00000001  // Data Raw Interrupt Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2C_O_MIMR register.
 //
 //*****************************************************************************
-#define I2C_MIMR_IM             0x00000001  // Interrupt Mask.
+#define I2C_MIMR_IM             0x00000001  // Interrupt Mask
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2C_O_MRIS register.
 //
 //*****************************************************************************
-#define I2C_MRIS_RIS            0x00000001  // Raw Interrupt Status.
+#define I2C_MRIS_RIS            0x00000001  // Raw Interrupt Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2C_O_SMIS register.
 //
 //*****************************************************************************
-#define I2C_SMIS_MIS            0x00000001  // Data Masked Interrupt Status.
+#define I2C_SMIS_DATAMIS        0x00000001  // Data Masked Interrupt Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2C_O_SICR register.
 //
 //*****************************************************************************
-#define I2C_SICR_IC             0x00000001  // Data Interrupt Clear.
+#define I2C_SICR_DATAIC         0x00000001  // Data Interrupt Clear
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2C_O_MMIS register.
 //
 //*****************************************************************************
-#define I2C_MMIS_MIS            0x00000001  // Masked Interrupt Status.
+#define I2C_MMIS_MIS            0x00000001  // Masked Interrupt Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2C_O_MICR register.
 //
 //*****************************************************************************
-#define I2C_MICR_IC             0x00000001  // Interrupt Clear.
+#define I2C_MICR_IC             0x00000001  // Interrupt Clear
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2C_O_MCR register.
 //
 //*****************************************************************************
-#define I2C_MCR_SFE             0x00000020  // I2C Slave Function Enable.
-#define I2C_MCR_MFE             0x00000010  // I2C Master Function Enable.
-#define I2C_MCR_LPBK            0x00000001  // I2C Loopback.
+#define I2C_MCR_SFE             0x00000020  // I2C Slave Function Enable
+#define I2C_MCR_MFE             0x00000010  // I2C Master Function Enable
+#define I2C_MCR_LPBK            0x00000001  // I2C Loopback
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the TIMER_O_CFG register.
 //
 //*****************************************************************************
-#define TIMER_CFG_M             0x00000007  // GPTM Configuration.
-#define TIMER_CFG_32_BIT_TIMER  0x00000000  // 32-bit timer configuration.
+#define TIMER_CFG_M             0x00000007  // GPTM Configuration
+#define TIMER_CFG_32_BIT_TIMER  0x00000000  // 32-bit timer configuration
 #define TIMER_CFG_32_BIT_RTC    0x00000001  // 32-bit real-time clock (RTC)
-                                            // counter configuration.
-#define TIMER_CFG_16_BIT        0x00000004  // 16-bit timer configuration,
+                                            // counter configuration
+#define TIMER_CFG_16_BIT        0x00000004  // 16-bit timer configuration. The
                                             // function is controlled by bits
-                                            // 1:0 of GPTMTAMR and GPTMTBMR.
+                                            // 1:0 of GPTMTAMR and GPTMTBMR
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the TIMER_O_TAMR register.
 //
 //*****************************************************************************
-#define TIMER_TAMR_TAAMS        0x00000008  // GPTM TimerA Alternate Mode
-                                            // Select.
-#define TIMER_TAMR_TACMR        0x00000004  // GPTM TimerA Capture Mode.
-#define TIMER_TAMR_TAMR_M       0x00000003  // GPTM TimerA Mode.
+#define TIMER_TAMR_TAAMS        0x00000008  // GPTM Timer A Alternate Mode
+                                            // Select
+#define TIMER_TAMR_TACMR        0x00000004  // GPTM Timer A Capture Mode
+#define TIMER_TAMR_TAMR_M       0x00000003  // GPTM Timer A Mode
 #define TIMER_TAMR_TAMR_1_SHOT  0x00000001  // One-Shot Timer mode
 #define TIMER_TAMR_TAMR_PERIOD  0x00000002  // Periodic Timer mode
 #define TIMER_TAMR_TAMR_CAP     0x00000003  // Capture mode
@@ -1266,10 +1257,10 @@
 // The following are defines for the bit fields in the TIMER_O_TBMR register.
 //
 //*****************************************************************************
-#define TIMER_TBMR_TBAMS        0x00000008  // GPTM TimerB Alternate Mode
-                                            // Select.
-#define TIMER_TBMR_TBCMR        0x00000004  // GPTM TimerB Capture Mode.
-#define TIMER_TBMR_TBMR_M       0x00000003  // GPTM TimerB Mode.
+#define TIMER_TBMR_TBAMS        0x00000008  // GPTM Timer B Alternate Mode
+                                            // Select
+#define TIMER_TBMR_TBCMR        0x00000004  // GPTM Timer B Capture Mode
+#define TIMER_TBMR_TBMR_M       0x00000003  // GPTM Timer B Mode
 #define TIMER_TBMR_TBMR_1_SHOT  0x00000001  // One-Shot Timer mode
 #define TIMER_TBMR_TBMR_PERIOD  0x00000002  // Periodic Timer mode
 #define TIMER_TBMR_TBMR_CAP     0x00000003  // Capture mode
@@ -1279,111 +1270,111 @@
 // The following are defines for the bit fields in the TIMER_O_CTL register.
 //
 //*****************************************************************************
-#define TIMER_CTL_TBPWML        0x00004000  // GPTM TimerB PWM Output Level.
-#define TIMER_CTL_TBOTE         0x00002000  // GPTM TimerB Output Trigger
-                                            // Enable.
-#define TIMER_CTL_TBEVENT_M     0x00000C00  // GPTM TimerB Event Mode.
+#define TIMER_CTL_TBPWML        0x00004000  // GPTM Timer B PWM Output Level
+#define TIMER_CTL_TBOTE         0x00002000  // GPTM Timer B Output Trigger
+                                            // Enable
+#define TIMER_CTL_TBEVENT_M     0x00000C00  // GPTM Timer B Event Mode
 #define TIMER_CTL_TBEVENT_POS   0x00000000  // Positive edge
 #define TIMER_CTL_TBEVENT_NEG   0x00000400  // Negative edge
 #define TIMER_CTL_TBEVENT_BOTH  0x00000C00  // Both edges
-#define TIMER_CTL_TBSTALL       0x00000200  // GPTM TimerB Stall Enable.
-#define TIMER_CTL_TBEN          0x00000100  // GPTM TimerB Enable.
-#define TIMER_CTL_TAPWML        0x00000040  // GPTM TimerA PWM Output Level.
-#define TIMER_CTL_TAOTE         0x00000020  // GPTM TimerA Output Trigger
-                                            // Enable.
-#define TIMER_CTL_RTCEN         0x00000010  // GPTM RTC Enable.
-#define TIMER_CTL_TAEVENT_M     0x0000000C  // GPTM TimerA Event Mode.
+#define TIMER_CTL_TBSTALL       0x00000200  // GPTM Timer B Stall Enable
+#define TIMER_CTL_TBEN          0x00000100  // GPTM Timer B Enable
+#define TIMER_CTL_TAPWML        0x00000040  // GPTM Timer A PWM Output Level
+#define TIMER_CTL_TAOTE         0x00000020  // GPTM Timer A Output Trigger
+                                            // Enable
+#define TIMER_CTL_RTCEN         0x00000010  // GPTM RTC Enable
+#define TIMER_CTL_TAEVENT_M     0x0000000C  // GPTM Timer A Event Mode
 #define TIMER_CTL_TAEVENT_POS   0x00000000  // Positive edge
 #define TIMER_CTL_TAEVENT_NEG   0x00000004  // Negative edge
 #define TIMER_CTL_TAEVENT_BOTH  0x0000000C  // Both edges
-#define TIMER_CTL_TASTALL       0x00000002  // GPTM TimerA Stall Enable.
-#define TIMER_CTL_TAEN          0x00000001  // GPTM TimerA Enable.
+#define TIMER_CTL_TASTALL       0x00000002  // GPTM Timer A Stall Enable
+#define TIMER_CTL_TAEN          0x00000001  // GPTM Timer A Enable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the TIMER_O_IMR register.
 //
 //*****************************************************************************
-#define TIMER_IMR_CBEIM         0x00000400  // GPTM CaptureB Event Interrupt
-                                            // Mask.
-#define TIMER_IMR_CBMIM         0x00000200  // GPTM CaptureB Match Interrupt
-                                            // Mask.
-#define TIMER_IMR_TBTOIM        0x00000100  // GPTM TimerB Time-Out Interrupt
-                                            // Mask.
-#define TIMER_IMR_RTCIM         0x00000008  // GPTM RTC Interrupt Mask.
-#define TIMER_IMR_CAEIM         0x00000004  // GPTM CaptureA Event Interrupt
-                                            // Mask.
-#define TIMER_IMR_CAMIM         0x00000002  // GPTM CaptureA Match Interrupt
-                                            // Mask.
-#define TIMER_IMR_TATOIM        0x00000001  // GPTM TimerA Time-Out Interrupt
-                                            // Mask.
+#define TIMER_IMR_CBEIM         0x00000400  // GPTM Capture B Event Interrupt
+                                            // Mask
+#define TIMER_IMR_CBMIM         0x00000200  // GPTM Capture B Match Interrupt
+                                            // Mask
+#define TIMER_IMR_TBTOIM        0x00000100  // GPTM Timer B Time-Out Interrupt
+                                            // Mask
+#define TIMER_IMR_RTCIM         0x00000008  // GPTM RTC Interrupt Mask
+#define TIMER_IMR_CAEIM         0x00000004  // GPTM Capture A Event Interrupt
+                                            // Mask
+#define TIMER_IMR_CAMIM         0x00000002  // GPTM Capture A Match Interrupt
+                                            // Mask
+#define TIMER_IMR_TATOIM        0x00000001  // GPTM Timer A Time-Out Interrupt
+                                            // Mask
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the TIMER_O_RIS register.
 //
 //*****************************************************************************
-#define TIMER_RIS_CBERIS        0x00000400  // GPTM CaptureB Event Raw
-                                            // Interrupt.
-#define TIMER_RIS_CBMRIS        0x00000200  // GPTM CaptureB Match Raw
-                                            // Interrupt.
-#define TIMER_RIS_TBTORIS       0x00000100  // GPTM TimerB Time-Out Raw
-                                            // Interrupt.
-#define TIMER_RIS_RTCRIS        0x00000008  // GPTM RTC Raw Interrupt.
-#define TIMER_RIS_CAERIS        0x00000004  // GPTM CaptureA Event Raw
-                                            // Interrupt.
-#define TIMER_RIS_CAMRIS        0x00000002  // GPTM CaptureA Match Raw
-                                            // Interrupt.
-#define TIMER_RIS_TATORIS       0x00000001  // GPTM TimerA Time-Out Raw
-                                            // Interrupt.
+#define TIMER_RIS_CBERIS        0x00000400  // GPTM Capture B Event Raw
+                                            // Interrupt
+#define TIMER_RIS_CBMRIS        0x00000200  // GPTM Capture B Match Raw
+                                            // Interrupt
+#define TIMER_RIS_TBTORIS       0x00000100  // GPTM Timer B Time-Out Raw
+                                            // Interrupt
+#define TIMER_RIS_RTCRIS        0x00000008  // GPTM RTC Raw Interrupt
+#define TIMER_RIS_CAERIS        0x00000004  // GPTM Capture A Event Raw
+                                            // Interrupt
+#define TIMER_RIS_CAMRIS        0x00000002  // GPTM Capture A Match Raw
+                                            // Interrupt
+#define TIMER_RIS_TATORIS       0x00000001  // GPTM Timer A Time-Out Raw
+                                            // Interrupt
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the TIMER_O_MIS register.
 //
 //*****************************************************************************
-#define TIMER_MIS_CBEMIS        0x00000400  // GPTM CaptureB Event Masked
-                                            // Interrupt.
-#define TIMER_MIS_CBMMIS        0x00000200  // GPTM CaptureB Match Masked
-                                            // Interrupt.
-#define TIMER_MIS_TBTOMIS       0x00000100  // GPTM TimerB Time-Out Masked
-                                            // Interrupt.
-#define TIMER_MIS_RTCMIS        0x00000008  // GPTM RTC Masked Interrupt.
-#define TIMER_MIS_CAEMIS        0x00000004  // GPTM CaptureA Event Masked
-                                            // Interrupt.
-#define TIMER_MIS_CAMMIS        0x00000002  // GPTM CaptureA Match Masked
-                                            // Interrupt.
-#define TIMER_MIS_TATOMIS       0x00000001  // GPTM TimerA Time-Out Masked
-                                            // Interrupt.
+#define TIMER_MIS_CBEMIS        0x00000400  // GPTM Capture B Event Masked
+                                            // Interrupt
+#define TIMER_MIS_CBMMIS        0x00000200  // GPTM Capture B Match Masked
+                                            // Interrupt
+#define TIMER_MIS_TBTOMIS       0x00000100  // GPTM Timer B Time-Out Masked
+                                            // Interrupt
+#define TIMER_MIS_RTCMIS        0x00000008  // GPTM RTC Masked Interrupt
+#define TIMER_MIS_CAEMIS        0x00000004  // GPTM Capture A Event Masked
+                                            // Interrupt
+#define TIMER_MIS_CAMMIS        0x00000002  // GPTM Capture A Match Masked
+                                            // Interrupt
+#define TIMER_MIS_TATOMIS       0x00000001  // GPTM Timer A Time-Out Masked
+                                            // Interrupt
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the TIMER_O_ICR register.
 //
 //*****************************************************************************
-#define TIMER_ICR_CBECINT       0x00000400  // GPTM CaptureB Event Interrupt
-                                            // Clear.
-#define TIMER_ICR_CBMCINT       0x00000200  // GPTM CaptureB Match Interrupt
-                                            // Clear.
-#define TIMER_ICR_TBTOCINT      0x00000100  // GPTM TimerB Time-Out Interrupt
-                                            // Clear.
-#define TIMER_ICR_RTCCINT       0x00000008  // GPTM RTC Interrupt Clear.
-#define TIMER_ICR_CAECINT       0x00000004  // GPTM CaptureA Event Interrupt
-                                            // Clear.
-#define TIMER_ICR_CAMCINT       0x00000002  // GPTM CaptureA Match Raw
-                                            // Interrupt.
-#define TIMER_ICR_TATOCINT      0x00000001  // GPTM TimerA Time-Out Raw
-                                            // Interrupt.
+#define TIMER_ICR_CBECINT       0x00000400  // GPTM Capture B Event Interrupt
+                                            // Clear
+#define TIMER_ICR_CBMCINT       0x00000200  // GPTM Capture B Match Interrupt
+                                            // Clear
+#define TIMER_ICR_TBTOCINT      0x00000100  // GPTM Timer B Time-Out Interrupt
+                                            // Clear
+#define TIMER_ICR_RTCCINT       0x00000008  // GPTM RTC Interrupt Clear
+#define TIMER_ICR_CAECINT       0x00000004  // GPTM Capture A Event Interrupt
+                                            // Clear
+#define TIMER_ICR_CAMCINT       0x00000002  // GPTM Capture A Match Interrupt
+                                            // Clear
+#define TIMER_ICR_TATOCINT      0x00000001  // GPTM Timer A Time-Out Raw
+                                            // Interrupt
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the TIMER_O_TAILR register.
 //
 //*****************************************************************************
-#define TIMER_TAILR_TAILRH_M    0xFFFF0000  // GPTM TimerA Interval Load
-                                            // Register High.
-#define TIMER_TAILR_TAILRL_M    0x0000FFFF  // GPTM TimerA Interval Load
-                                            // Register Low.
+#define TIMER_TAILR_TAILRH_M    0xFFFF0000  // GPTM Timer A Interval Load
+                                            // Register High
+#define TIMER_TAILR_TAILRL_M    0x0000FFFF  // GPTM Timer A Interval Load
+                                            // Register Low
 #define TIMER_TAILR_TAILRH_S    16
 #define TIMER_TAILR_TAILRL_S    0
 
@@ -1392,8 +1383,8 @@
 // The following are defines for the bit fields in the TIMER_O_TBILR register.
 //
 //*****************************************************************************
-#define TIMER_TBILR_TBILRL_M    0x0000FFFF  // GPTM TimerB Interval Load
-                                            // Register.
+#define TIMER_TBILR_TBILRL_M    0x0000FFFF  // GPTM Timer B Interval Load
+                                            // Register
 #define TIMER_TBILR_TBILRL_S    0
 
 //*****************************************************************************
@@ -1402,8 +1393,8 @@
 // register.
 //
 //*****************************************************************************
-#define TIMER_TAMATCHR_TAMRH_M  0xFFFF0000  // GPTM TimerA Match Register High.
-#define TIMER_TAMATCHR_TAMRL_M  0x0000FFFF  // GPTM TimerA Match Register Low.
+#define TIMER_TAMATCHR_TAMRH_M  0xFFFF0000  // GPTM Timer A Match Register High
+#define TIMER_TAMATCHR_TAMRL_M  0x0000FFFF  // GPTM Timer A Match Register Low
 #define TIMER_TAMATCHR_TAMRH_S  16
 #define TIMER_TAMATCHR_TAMRL_S  0
 
@@ -1413,7 +1404,7 @@
 // register.
 //
 //*****************************************************************************
-#define TIMER_TBMATCHR_TBMRL_M  0x0000FFFF  // GPTM TimerB Match Register Low.
+#define TIMER_TBMATCHR_TBMRL_M  0x0000FFFF  // GPTM Timer B Match Register Low
 #define TIMER_TBMATCHR_TBMRL_S  0
 
 //*****************************************************************************
@@ -1421,7 +1412,7 @@
 // The following are defines for the bit fields in the TIMER_O_TAPR register.
 //
 //*****************************************************************************
-#define TIMER_TAPR_TAPSR_M      0x000000FF  // GPTM TimerA Prescale.
+#define TIMER_TAPR_TAPSR_M      0x000000FF  // GPTM Timer A Prescale
 #define TIMER_TAPR_TAPSR_S      0
 
 //*****************************************************************************
@@ -1429,7 +1420,7 @@
 // The following are defines for the bit fields in the TIMER_O_TBPR register.
 //
 //*****************************************************************************
-#define TIMER_TBPR_TBPSR_M      0x000000FF  // GPTM TimerB Prescale.
+#define TIMER_TBPR_TBPSR_M      0x000000FF  // GPTM Timer B Prescale
 #define TIMER_TBPR_TBPSR_S      0
 
 //*****************************************************************************
@@ -1437,7 +1428,7 @@
 // The following are defines for the bit fields in the TIMER_O_TAPMR register.
 //
 //*****************************************************************************
-#define TIMER_TAPMR_TAPSMR_M    0x000000FF  // GPTM TimerA Prescale Match.
+#define TIMER_TAPMR_TAPSMR_M    0x000000FF  // GPTM TimerA Prescale Match
 #define TIMER_TAPMR_TAPSMR_S    0
 
 //*****************************************************************************
@@ -1445,7 +1436,7 @@
 // The following are defines for the bit fields in the TIMER_O_TBPMR register.
 //
 //*****************************************************************************
-#define TIMER_TBPMR_TBPSMR_M    0x000000FF  // GPTM TimerB Prescale Match.
+#define TIMER_TBPMR_TBPSMR_M    0x000000FF  // GPTM TimerB Prescale Match
 #define TIMER_TBPMR_TBPSMR_S    0
 
 //*****************************************************************************
@@ -1453,8 +1444,8 @@
 // The following are defines for the bit fields in the TIMER_O_TAR register.
 //
 //*****************************************************************************
-#define TIMER_TAR_TARH_M        0xFFFF0000  // GPTM TimerA Register High.
-#define TIMER_TAR_TARL_M        0x0000FFFF  // GPTM TimerA Register Low.
+#define TIMER_TAR_TARH_M        0xFFFF0000  // GPTM Timer A Register High
+#define TIMER_TAR_TARL_M        0x0000FFFF  // GPTM Timer A Register Low
 #define TIMER_TAR_TARH_S        16
 #define TIMER_TAR_TARL_S        0
 
@@ -1463,7 +1454,7 @@
 // The following are defines for the bit fields in the TIMER_O_TBR register.
 //
 //*****************************************************************************
-#define TIMER_TBR_TBRL_M        0x0000FFFF  // GPTM TimerB.
+#define TIMER_TBR_TBRL_M        0x0000FFFF  // GPTM Timer B
 #define TIMER_TBR_TBRL_S        0
 
 //*****************************************************************************
@@ -1471,79 +1462,79 @@
 // The following are defines for the bit fields in the ADC_O_ACTSS register.
 //
 //*****************************************************************************
-#define ADC_ACTSS_ASEN3         0x00000008  // ADC SS3 Enable.
-#define ADC_ACTSS_ASEN2         0x00000004  // ADC SS2 Enable.
-#define ADC_ACTSS_ASEN1         0x00000002  // ADC SS1 Enable.
-#define ADC_ACTSS_ASEN0         0x00000001  // ADC SS0 Enable.
+#define ADC_ACTSS_ASEN3         0x00000008  // ADC SS3 Enable
+#define ADC_ACTSS_ASEN2         0x00000004  // ADC SS2 Enable
+#define ADC_ACTSS_ASEN1         0x00000002  // ADC SS1 Enable
+#define ADC_ACTSS_ASEN0         0x00000001  // ADC SS0 Enable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the ADC_O_RIS register.
 //
 //*****************************************************************************
-#define ADC_RIS_INR3            0x00000008  // SS3 Raw Interrupt Status.
-#define ADC_RIS_INR2            0x00000004  // SS2 Raw Interrupt Status.
-#define ADC_RIS_INR1            0x00000002  // SS1 Raw Interrupt Status.
-#define ADC_RIS_INR0            0x00000001  // SS0 Raw Interrupt Status.
+#define ADC_RIS_INR3            0x00000008  // SS3 Raw Interrupt Status
+#define ADC_RIS_INR2            0x00000004  // SS2 Raw Interrupt Status
+#define ADC_RIS_INR1            0x00000002  // SS1 Raw Interrupt Status
+#define ADC_RIS_INR0            0x00000001  // SS0 Raw Interrupt Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the ADC_O_IM register.
 //
 //*****************************************************************************
-#define ADC_IM_MASK3            0x00000008  // SS3 Interrupt Mask.
-#define ADC_IM_MASK2            0x00000004  // SS2 Interrupt Mask.
-#define ADC_IM_MASK1            0x00000002  // SS1 Interrupt Mask.
-#define ADC_IM_MASK0            0x00000001  // SS0 Interrupt Mask.
+#define ADC_IM_MASK3            0x00000008  // SS3 Interrupt Mask
+#define ADC_IM_MASK2            0x00000004  // SS2 Interrupt Mask
+#define ADC_IM_MASK1            0x00000002  // SS1 Interrupt Mask
+#define ADC_IM_MASK0            0x00000001  // SS0 Interrupt Mask
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the ADC_O_ISC register.
 //
 //*****************************************************************************
-#define ADC_ISC_IN3             0x00000008  // SS3 Interrupt Status and Clear.
-#define ADC_ISC_IN2             0x00000004  // SS2 Interrupt Status and Clear.
-#define ADC_ISC_IN1             0x00000002  // SS1 Interrupt Status and Clear.
-#define ADC_ISC_IN0             0x00000001  // SS0 Interrupt Status and Clear.
+#define ADC_ISC_IN3             0x00000008  // SS3 Interrupt Status and Clear
+#define ADC_ISC_IN2             0x00000004  // SS2 Interrupt Status and Clear
+#define ADC_ISC_IN1             0x00000002  // SS1 Interrupt Status and Clear
+#define ADC_ISC_IN0             0x00000001  // SS0 Interrupt Status and Clear
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the ADC_O_OSTAT register.
 //
 //*****************************************************************************
-#define ADC_OSTAT_OV3           0x00000008  // SS3 FIFO Overflow.
-#define ADC_OSTAT_OV2           0x00000004  // SS2 FIFO Overflow.
-#define ADC_OSTAT_OV1           0x00000002  // SS1 FIFO Overflow.
-#define ADC_OSTAT_OV0           0x00000001  // SS0 FIFO Overflow.
+#define ADC_OSTAT_OV3           0x00000008  // SS3 FIFO Overflow
+#define ADC_OSTAT_OV2           0x00000004  // SS2 FIFO Overflow
+#define ADC_OSTAT_OV1           0x00000002  // SS1 FIFO Overflow
+#define ADC_OSTAT_OV0           0x00000001  // SS0 FIFO Overflow
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the ADC_O_EMUX register.
 //
 //*****************************************************************************
-#define ADC_EMUX_EM3_M          0x0000F000  // SS3 Trigger Select.
-#define ADC_EMUX_EM3_PROCESSOR  0x00000000  // Controller (default)
+#define ADC_EMUX_EM3_M          0x0000F000  // SS3 Trigger Select
+#define ADC_EMUX_EM3_PROCESSOR  0x00000000  // Processor (default)
 #define ADC_EMUX_EM3_COMP0      0x00001000  // Analog Comparator 0
 #define ADC_EMUX_EM3_COMP1      0x00002000  // Analog Comparator 1
 #define ADC_EMUX_EM3_EXTERNAL   0x00004000  // External (GPIO PB4)
 #define ADC_EMUX_EM3_TIMER      0x00005000  // Timer
 #define ADC_EMUX_EM3_ALWAYS     0x0000F000  // Always (continuously sample)
-#define ADC_EMUX_EM2_M          0x00000F00  // SS2 Trigger Select.
-#define ADC_EMUX_EM2_PROCESSOR  0x00000000  // Controller (default)
+#define ADC_EMUX_EM2_M          0x00000F00  // SS2 Trigger Select
+#define ADC_EMUX_EM2_PROCESSOR  0x00000000  // Processor (default)
 #define ADC_EMUX_EM2_COMP0      0x00000100  // Analog Comparator 0
 #define ADC_EMUX_EM2_COMP1      0x00000200  // Analog Comparator 1
 #define ADC_EMUX_EM2_EXTERNAL   0x00000400  // External (GPIO PB4)
 #define ADC_EMUX_EM2_TIMER      0x00000500  // Timer
 #define ADC_EMUX_EM2_ALWAYS     0x00000F00  // Always (continuously sample)
-#define ADC_EMUX_EM1_M          0x000000F0  // SS1 Trigger Select.
-#define ADC_EMUX_EM1_PROCESSOR  0x00000000  // Controller (default)
+#define ADC_EMUX_EM1_M          0x000000F0  // SS1 Trigger Select
+#define ADC_EMUX_EM1_PROCESSOR  0x00000000  // Processor (default)
 #define ADC_EMUX_EM1_COMP0      0x00000010  // Analog Comparator 0
 #define ADC_EMUX_EM1_COMP1      0x00000020  // Analog Comparator 1
 #define ADC_EMUX_EM1_EXTERNAL   0x00000040  // External (GPIO PB4)
 #define ADC_EMUX_EM1_TIMER      0x00000050  // Timer
 #define ADC_EMUX_EM1_ALWAYS     0x000000F0  // Always (continuously sample)
-#define ADC_EMUX_EM0_M          0x0000000F  // SS0 Trigger Select.
-#define ADC_EMUX_EM0_PROCESSOR  0x00000000  // Controller (default)
+#define ADC_EMUX_EM0_M          0x0000000F  // SS0 Trigger Select
+#define ADC_EMUX_EM0_PROCESSOR  0x00000000  // Processor (default)
 #define ADC_EMUX_EM0_COMP0      0x00000001  // Analog Comparator 0
 #define ADC_EMUX_EM0_COMP1      0x00000002  // Analog Comparator 1
 #define ADC_EMUX_EM0_EXTERNAL   0x00000004  // External (GPIO PB4)
@@ -1555,32 +1546,32 @@
 // The following are defines for the bit fields in the ADC_O_USTAT register.
 //
 //*****************************************************************************
-#define ADC_USTAT_UV3           0x00000008  // SS3 FIFO Underflow.
-#define ADC_USTAT_UV2           0x00000004  // SS2 FIFO Underflow.
-#define ADC_USTAT_UV1           0x00000002  // SS1 FIFO Underflow.
-#define ADC_USTAT_UV0           0x00000001  // SS0 FIFO Underflow.
+#define ADC_USTAT_UV3           0x00000008  // SS3 FIFO Underflow
+#define ADC_USTAT_UV2           0x00000004  // SS2 FIFO Underflow
+#define ADC_USTAT_UV1           0x00000002  // SS1 FIFO Underflow
+#define ADC_USTAT_UV0           0x00000001  // SS0 FIFO Underflow
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the ADC_O_SSPRI register.
 //
 //*****************************************************************************
-#define ADC_SSPRI_SS3_M         0x00003000  // SS3 Priority.
+#define ADC_SSPRI_SS3_M         0x00003000  // SS3 Priority
 #define ADC_SSPRI_SS3_1ST       0x00000000  // First priority
 #define ADC_SSPRI_SS3_2ND       0x00001000  // Second priority
 #define ADC_SSPRI_SS3_3RD       0x00002000  // Third priority
 #define ADC_SSPRI_SS3_4TH       0x00003000  // Fourth priority
-#define ADC_SSPRI_SS2_M         0x00000300  // SS2 Priority.
+#define ADC_SSPRI_SS2_M         0x00000300  // SS2 Priority
 #define ADC_SSPRI_SS2_1ST       0x00000000  // First priority
 #define ADC_SSPRI_SS2_2ND       0x00000100  // Second priority
 #define ADC_SSPRI_SS2_3RD       0x00000200  // Third priority
 #define ADC_SSPRI_SS2_4TH       0x00000300  // Fourth priority
-#define ADC_SSPRI_SS1_M         0x00000030  // SS1 Priority.
+#define ADC_SSPRI_SS1_M         0x00000030  // SS1 Priority
 #define ADC_SSPRI_SS1_1ST       0x00000000  // First priority
 #define ADC_SSPRI_SS1_2ND       0x00000010  // Second priority
 #define ADC_SSPRI_SS1_3RD       0x00000020  // Third priority
 #define ADC_SSPRI_SS1_4TH       0x00000030  // Fourth priority
-#define ADC_SSPRI_SS0_M         0x00000003  // SS0 Priority.
+#define ADC_SSPRI_SS0_M         0x00000003  // SS0 Priority
 #define ADC_SSPRI_SS0_1ST       0x00000000  // First priority
 #define ADC_SSPRI_SS0_2ND       0x00000001  // Second priority
 #define ADC_SSPRI_SS0_3RD       0x00000002  // Third priority
@@ -1591,17 +1582,17 @@
 // The following are defines for the bit fields in the ADC_O_PSSI register.
 //
 //*****************************************************************************
-#define ADC_PSSI_SS3            0x00000008  // SS3 Initiate.
-#define ADC_PSSI_SS2            0x00000004  // SS2 Initiate.
-#define ADC_PSSI_SS1            0x00000002  // SS1 Initiate.
-#define ADC_PSSI_SS0            0x00000001  // SS0 Initiate.
+#define ADC_PSSI_SS3            0x00000008  // SS3 Initiate
+#define ADC_PSSI_SS2            0x00000004  // SS2 Initiate
+#define ADC_PSSI_SS1            0x00000002  // SS1 Initiate
+#define ADC_PSSI_SS0            0x00000001  // SS0 Initiate
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the ADC_O_SAC register.
 //
 //*****************************************************************************
-#define ADC_SAC_AVG_M           0x00000007  // Hardware Averaging Control.
+#define ADC_SAC_AVG_M           0x00000007  // Hardware Averaging Control
 #define ADC_SAC_AVG_OFF         0x00000000  // No hardware oversampling
 #define ADC_SAC_AVG_2X          0x00000001  // 2x hardware oversampling
 #define ADC_SAC_AVG_4X          0x00000002  // 4x hardware oversampling
@@ -1615,14 +1606,14 @@
 // The following are defines for the bit fields in the ADC_O_SSMUX0 register.
 //
 //*****************************************************************************
-#define ADC_SSMUX0_MUX7_M       0x70000000  // 8th Sample Input Select.
-#define ADC_SSMUX0_MUX6_M       0x07000000  // 7th Sample Input Select.
-#define ADC_SSMUX0_MUX5_M       0x00700000  // 6th Sample Input Select.
-#define ADC_SSMUX0_MUX4_M       0x00070000  // 5th Sample Input Select.
-#define ADC_SSMUX0_MUX3_M       0x00007000  // 4th Sample Input Select.
-#define ADC_SSMUX0_MUX2_M       0x00000700  // 3rd Sample Input Select.
-#define ADC_SSMUX0_MUX1_M       0x00000070  // 2nd Sample Input Select.
-#define ADC_SSMUX0_MUX0_M       0x00000007  // 1st Sample Input Select.
+#define ADC_SSMUX0_MUX7_M       0x70000000  // 8th Sample Input Select
+#define ADC_SSMUX0_MUX6_M       0x07000000  // 7th Sample Input Select
+#define ADC_SSMUX0_MUX5_M       0x00700000  // 6th Sample Input Select
+#define ADC_SSMUX0_MUX4_M       0x00070000  // 5th Sample Input Select
+#define ADC_SSMUX0_MUX3_M       0x00007000  // 4th Sample Input Select
+#define ADC_SSMUX0_MUX2_M       0x00000700  // 3rd Sample Input Select
+#define ADC_SSMUX0_MUX1_M       0x00000070  // 2nd Sample Input Select
+#define ADC_SSMUX0_MUX0_M       0x00000007  // 1st Sample Input Select
 #define ADC_SSMUX0_MUX7_S       28
 #define ADC_SSMUX0_MUX6_S       24
 #define ADC_SSMUX0_MUX5_S       20
@@ -1637,45 +1628,45 @@
 // The following are defines for the bit fields in the ADC_O_SSCTL0 register.
 //
 //*****************************************************************************
-#define ADC_SSCTL0_TS7          0x80000000  // 8th Sample Temp Sensor Select.
-#define ADC_SSCTL0_IE7          0x40000000  // 8th Sample Interrupt Enable.
-#define ADC_SSCTL0_END7         0x20000000  // 8th Sample is End of Sequence.
-#define ADC_SSCTL0_D7           0x10000000  // 8th Sample Diff Input Select.
-#define ADC_SSCTL0_TS6          0x08000000  // 7th Sample Temp Sensor Select.
-#define ADC_SSCTL0_IE6          0x04000000  // 7th Sample Interrupt Enable.
-#define ADC_SSCTL0_END6         0x02000000  // 7th Sample is End of Sequence.
-#define ADC_SSCTL0_D6           0x01000000  // 7th Sample Diff Input Select.
-#define ADC_SSCTL0_TS5          0x00800000  // 6th Sample Temp Sensor Select.
-#define ADC_SSCTL0_IE5          0x00400000  // 6th Sample Interrupt Enable.
-#define ADC_SSCTL0_END5         0x00200000  // 6th Sample is End of Sequence.
-#define ADC_SSCTL0_D5           0x00100000  // 6th Sample Diff Input Select.
-#define ADC_SSCTL0_TS4          0x00080000  // 5th Sample Temp Sensor Select.
-#define ADC_SSCTL0_IE4          0x00040000  // 5th Sample Interrupt Enable.
-#define ADC_SSCTL0_END4         0x00020000  // 5th Sample is End of Sequence.
-#define ADC_SSCTL0_D4           0x00010000  // 5th Sample Diff Input Select.
-#define ADC_SSCTL0_TS3          0x00008000  // 4th Sample Temp Sensor Select.
-#define ADC_SSCTL0_IE3          0x00004000  // 4th Sample Interrupt Enable.
-#define ADC_SSCTL0_END3         0x00002000  // 4th Sample is End of Sequence.
-#define ADC_SSCTL0_D3           0x00001000  // 4th Sample Diff Input Select.
-#define ADC_SSCTL0_TS2          0x00000800  // 3rd Sample Temp Sensor Select.
-#define ADC_SSCTL0_IE2          0x00000400  // 3rd Sample Interrupt Enable.
-#define ADC_SSCTL0_END2         0x00000200  // 3rd Sample is End of Sequence.
-#define ADC_SSCTL0_D2           0x00000100  // 3rd Sample Diff Input Select.
-#define ADC_SSCTL0_TS1          0x00000080  // 2nd Sample Temp Sensor Select.
-#define ADC_SSCTL0_IE1          0x00000040  // 2nd Sample Interrupt Enable.
-#define ADC_SSCTL0_END1         0x00000020  // 2nd Sample is End of Sequence.
-#define ADC_SSCTL0_D1           0x00000010  // 2nd Sample Diff Input Select.
-#define ADC_SSCTL0_TS0          0x00000008  // 1st Sample Temp Sensor Select.
-#define ADC_SSCTL0_IE0          0x00000004  // 1st Sample Interrupt Enable.
-#define ADC_SSCTL0_END0         0x00000002  // 1st Sample is End of Sequence.
-#define ADC_SSCTL0_D0           0x00000001  // 1st Sample Diff Input Select.
+#define ADC_SSCTL0_TS7          0x80000000  // 8th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE7          0x40000000  // 8th Sample Interrupt Enable
+#define ADC_SSCTL0_END7         0x20000000  // 8th Sample is End of Sequence
+#define ADC_SSCTL0_D7           0x10000000  // 8th Sample Diff Input Select
+#define ADC_SSCTL0_TS6          0x08000000  // 7th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE6          0x04000000  // 7th Sample Interrupt Enable
+#define ADC_SSCTL0_END6         0x02000000  // 7th Sample is End of Sequence
+#define ADC_SSCTL0_D6           0x01000000  // 7th Sample Diff Input Select
+#define ADC_SSCTL0_TS5          0x00800000  // 6th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE5          0x00400000  // 6th Sample Interrupt Enable
+#define ADC_SSCTL0_END5         0x00200000  // 6th Sample is End of Sequence
+#define ADC_SSCTL0_D5           0x00100000  // 6th Sample Diff Input Select
+#define ADC_SSCTL0_TS4          0x00080000  // 5th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE4          0x00040000  // 5th Sample Interrupt Enable
+#define ADC_SSCTL0_END4         0x00020000  // 5th Sample is End of Sequence
+#define ADC_SSCTL0_D4           0x00010000  // 5th Sample Diff Input Select
+#define ADC_SSCTL0_TS3          0x00008000  // 4th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE3          0x00004000  // 4th Sample Interrupt Enable
+#define ADC_SSCTL0_END3         0x00002000  // 4th Sample is End of Sequence
+#define ADC_SSCTL0_D3           0x00001000  // 4th Sample Diff Input Select
+#define ADC_SSCTL0_TS2          0x00000800  // 3rd Sample Temp Sensor Select
+#define ADC_SSCTL0_IE2          0x00000400  // 3rd Sample Interrupt Enable
+#define ADC_SSCTL0_END2         0x00000200  // 3rd Sample is End of Sequence
+#define ADC_SSCTL0_D2           0x00000100  // 3rd Sample Diff Input Select
+#define ADC_SSCTL0_TS1          0x00000080  // 2nd Sample Temp Sensor Select
+#define ADC_SSCTL0_IE1          0x00000040  // 2nd Sample Interrupt Enable
+#define ADC_SSCTL0_END1         0x00000020  // 2nd Sample is End of Sequence
+#define ADC_SSCTL0_D1           0x00000010  // 2nd Sample Diff Input Select
+#define ADC_SSCTL0_TS0          0x00000008  // 1st Sample Temp Sensor Select
+#define ADC_SSCTL0_IE0          0x00000004  // 1st Sample Interrupt Enable
+#define ADC_SSCTL0_END0         0x00000002  // 1st Sample is End of Sequence
+#define ADC_SSCTL0_D0           0x00000001  // 1st Sample Diff Input Select
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the ADC_O_SSFIFO0 register.
 //
 //*****************************************************************************
-#define ADC_SSFIFO0_DATA_M      0x000003FF  // Conversion Result Data.
+#define ADC_SSFIFO0_DATA_M      0x000003FF  // Conversion Result Data
 #define ADC_SSFIFO0_DATA_S      0
 
 //*****************************************************************************
@@ -1683,10 +1674,10 @@
 // The following are defines for the bit fields in the ADC_O_SSFSTAT0 register.
 //
 //*****************************************************************************
-#define ADC_SSFSTAT0_FULL       0x00001000  // FIFO Full.
-#define ADC_SSFSTAT0_EMPTY      0x00000100  // FIFO Empty.
-#define ADC_SSFSTAT0_HPTR_M     0x000000F0  // FIFO Head Pointer.
-#define ADC_SSFSTAT0_TPTR_M     0x0000000F  // FIFO Tail Pointer.
+#define ADC_SSFSTAT0_FULL       0x00001000  // FIFO Full
+#define ADC_SSFSTAT0_EMPTY      0x00000100  // FIFO Empty
+#define ADC_SSFSTAT0_HPTR_M     0x000000F0  // FIFO Head Pointer
+#define ADC_SSFSTAT0_TPTR_M     0x0000000F  // FIFO Tail Pointer
 #define ADC_SSFSTAT0_HPTR_S     4
 #define ADC_SSFSTAT0_TPTR_S     0
 
@@ -1695,10 +1686,10 @@
 // The following are defines for the bit fields in the ADC_O_SSMUX1 register.
 //
 //*****************************************************************************
-#define ADC_SSMUX1_MUX3_M       0x00007000  // 4th Sample Input Select.
-#define ADC_SSMUX1_MUX2_M       0x00000700  // 3rd Sample Input Select.
-#define ADC_SSMUX1_MUX1_M       0x00000070  // 2nd Sample Input Select.
-#define ADC_SSMUX1_MUX0_M       0x00000007  // 1st Sample Input Select.
+#define ADC_SSMUX1_MUX3_M       0x00007000  // 4th Sample Input Select
+#define ADC_SSMUX1_MUX2_M       0x00000700  // 3rd Sample Input Select
+#define ADC_SSMUX1_MUX1_M       0x00000070  // 2nd Sample Input Select
+#define ADC_SSMUX1_MUX0_M       0x00000007  // 1st Sample Input Select
 #define ADC_SSMUX1_MUX3_S       12
 #define ADC_SSMUX1_MUX2_S       8
 #define ADC_SSMUX1_MUX1_S       4
@@ -1709,29 +1700,29 @@
 // The following are defines for the bit fields in the ADC_O_SSCTL1 register.
 //
 //*****************************************************************************
-#define ADC_SSCTL1_TS3          0x00008000  // 4th Sample Temp Sensor Select.
-#define ADC_SSCTL1_IE3          0x00004000  // 4th Sample Interrupt Enable.
-#define ADC_SSCTL1_END3         0x00002000  // 4th Sample is End of Sequence.
-#define ADC_SSCTL1_D3           0x00001000  // 4th Sample Diff Input Select.
-#define ADC_SSCTL1_TS2          0x00000800  // 3rd Sample Temp Sensor Select.
-#define ADC_SSCTL1_IE2          0x00000400  // 3rd Sample Interrupt Enable.
-#define ADC_SSCTL1_END2         0x00000200  // 3rd Sample is End of Sequence.
-#define ADC_SSCTL1_D2           0x00000100  // 3rd Sample Diff Input Select.
-#define ADC_SSCTL1_TS1          0x00000080  // 2nd Sample Temp Sensor Select.
-#define ADC_SSCTL1_IE1          0x00000040  // 2nd Sample Interrupt Enable.
-#define ADC_SSCTL1_END1         0x00000020  // 2nd Sample is End of Sequence.
-#define ADC_SSCTL1_D1           0x00000010  // 2nd Sample Diff Input Select.
-#define ADC_SSCTL1_TS0          0x00000008  // 1st Sample Temp Sensor Select.
-#define ADC_SSCTL1_IE0          0x00000004  // 1st Sample Interrupt Enable.
-#define ADC_SSCTL1_END0         0x00000002  // 1st Sample is End of Sequence.
-#define ADC_SSCTL1_D0           0x00000001  // 1st Sample Diff Input Select.
+#define ADC_SSCTL1_TS3          0x00008000  // 4th Sample Temp Sensor Select
+#define ADC_SSCTL1_IE3          0x00004000  // 4th Sample Interrupt Enable
+#define ADC_SSCTL1_END3         0x00002000  // 4th Sample is End of Sequence
+#define ADC_SSCTL1_D3           0x00001000  // 4th Sample Diff Input Select
+#define ADC_SSCTL1_TS2          0x00000800  // 3rd Sample Temp Sensor Select
+#define ADC_SSCTL1_IE2          0x00000400  // 3rd Sample Interrupt Enable
+#define ADC_SSCTL1_END2         0x00000200  // 3rd Sample is End of Sequence
+#define ADC_SSCTL1_D2           0x00000100  // 3rd Sample Diff Input Select
+#define ADC_SSCTL1_TS1          0x00000080  // 2nd Sample Temp Sensor Select
+#define ADC_SSCTL1_IE1          0x00000040  // 2nd Sample Interrupt Enable
+#define ADC_SSCTL1_END1         0x00000020  // 2nd Sample is End of Sequence
+#define ADC_SSCTL1_D1           0x00000010  // 2nd Sample Diff Input Select
+#define ADC_SSCTL1_TS0          0x00000008  // 1st Sample Temp Sensor Select
+#define ADC_SSCTL1_IE0          0x00000004  // 1st Sample Interrupt Enable
+#define ADC_SSCTL1_END0         0x00000002  // 1st Sample is End of Sequence
+#define ADC_SSCTL1_D0           0x00000001  // 1st Sample Diff Input Select
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the ADC_O_SSFIFO1 register.
 //
 //*****************************************************************************
-#define ADC_SSFIFO1_DATA_M      0x000003FF  // Conversion Result Data.
+#define ADC_SSFIFO1_DATA_M      0x000003FF  // Conversion Result Data
 #define ADC_SSFIFO1_DATA_S      0
 
 //*****************************************************************************
@@ -1739,10 +1730,10 @@
 // The following are defines for the bit fields in the ADC_O_SSFSTAT1 register.
 //
 //*****************************************************************************
-#define ADC_SSFSTAT1_FULL       0x00001000  // FIFO Full.
-#define ADC_SSFSTAT1_EMPTY      0x00000100  // FIFO Empty.
-#define ADC_SSFSTAT1_HPTR_M     0x000000F0  // FIFO Head Pointer.
-#define ADC_SSFSTAT1_TPTR_M     0x0000000F  // FIFO Tail Pointer.
+#define ADC_SSFSTAT1_FULL       0x00001000  // FIFO Full
+#define ADC_SSFSTAT1_EMPTY      0x00000100  // FIFO Empty
+#define ADC_SSFSTAT1_HPTR_M     0x000000F0  // FIFO Head Pointer
+#define ADC_SSFSTAT1_TPTR_M     0x0000000F  // FIFO Tail Pointer
 #define ADC_SSFSTAT1_HPTR_S     4
 #define ADC_SSFSTAT1_TPTR_S     0
 
@@ -1751,10 +1742,10 @@
 // The following are defines for the bit fields in the ADC_O_SSMUX2 register.
 //
 //*****************************************************************************
-#define ADC_SSMUX2_MUX3_M       0x00007000  // 4th Sample Input Select.
-#define ADC_SSMUX2_MUX2_M       0x00000700  // 3rd Sample Input Select.
-#define ADC_SSMUX2_MUX1_M       0x00000070  // 2nd Sample Input Select.
-#define ADC_SSMUX2_MUX0_M       0x00000007  // 1st Sample Input Select.
+#define ADC_SSMUX2_MUX3_M       0x00007000  // 4th Sample Input Select
+#define ADC_SSMUX2_MUX2_M       0x00000700  // 3rd Sample Input Select
+#define ADC_SSMUX2_MUX1_M       0x00000070  // 2nd Sample Input Select
+#define ADC_SSMUX2_MUX0_M       0x00000007  // 1st Sample Input Select
 #define ADC_SSMUX2_MUX3_S       12
 #define ADC_SSMUX2_MUX2_S       8
 #define ADC_SSMUX2_MUX1_S       4
@@ -1765,29 +1756,29 @@
 // The following are defines for the bit fields in the ADC_O_SSCTL2 register.
 //
 //*****************************************************************************
-#define ADC_SSCTL2_TS3          0x00008000  // 4th Sample Temp Sensor Select.
-#define ADC_SSCTL2_IE3          0x00004000  // 4th Sample Interrupt Enable.
-#define ADC_SSCTL2_END3         0x00002000  // 4th Sample is End of Sequence.
-#define ADC_SSCTL2_D3           0x00001000  // 4th Sample Diff Input Select.
-#define ADC_SSCTL2_TS2          0x00000800  // 3rd Sample Temp Sensor Select.
-#define ADC_SSCTL2_IE2          0x00000400  // 3rd Sample Interrupt Enable.
-#define ADC_SSCTL2_END2         0x00000200  // 3rd Sample is End of Sequence.
-#define ADC_SSCTL2_D2           0x00000100  // 3rd Sample Diff Input Select.
-#define ADC_SSCTL2_TS1          0x00000080  // 2nd Sample Temp Sensor Select.
-#define ADC_SSCTL2_IE1          0x00000040  // 2nd Sample Interrupt Enable.
-#define ADC_SSCTL2_END1         0x00000020  // 2nd Sample is End of Sequence.
-#define ADC_SSCTL2_D1           0x00000010  // 2nd Sample Diff Input Select.
-#define ADC_SSCTL2_TS0          0x00000008  // 1st Sample Temp Sensor Select.
-#define ADC_SSCTL2_IE0          0x00000004  // 1st Sample Interrupt Enable.
-#define ADC_SSCTL2_END0         0x00000002  // 1st Sample is End of Sequence.
-#define ADC_SSCTL2_D0           0x00000001  // 1st Sample Diff Input Select.
+#define ADC_SSCTL2_TS3          0x00008000  // 4th Sample Temp Sensor Select
+#define ADC_SSCTL2_IE3          0x00004000  // 4th Sample Interrupt Enable
+#define ADC_SSCTL2_END3         0x00002000  // 4th Sample is End of Sequence
+#define ADC_SSCTL2_D3           0x00001000  // 4th Sample Diff Input Select
+#define ADC_SSCTL2_TS2          0x00000800  // 3rd Sample Temp Sensor Select
+#define ADC_SSCTL2_IE2          0x00000400  // 3rd Sample Interrupt Enable
+#define ADC_SSCTL2_END2         0x00000200  // 3rd Sample is End of Sequence
+#define ADC_SSCTL2_D2           0x00000100  // 3rd Sample Diff Input Select
+#define ADC_SSCTL2_TS1          0x00000080  // 2nd Sample Temp Sensor Select
+#define ADC_SSCTL2_IE1          0x00000040  // 2nd Sample Interrupt Enable
+#define ADC_SSCTL2_END1         0x00000020  // 2nd Sample is End of Sequence
+#define ADC_SSCTL2_D1           0x00000010  // 2nd Sample Diff Input Select
+#define ADC_SSCTL2_TS0          0x00000008  // 1st Sample Temp Sensor Select
+#define ADC_SSCTL2_IE0          0x00000004  // 1st Sample Interrupt Enable
+#define ADC_SSCTL2_END0         0x00000002  // 1st Sample is End of Sequence
+#define ADC_SSCTL2_D0           0x00000001  // 1st Sample Diff Input Select
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the ADC_O_SSFIFO2 register.
 //
 //*****************************************************************************
-#define ADC_SSFIFO2_DATA_M      0x000003FF  // Conversion Result Data.
+#define ADC_SSFIFO2_DATA_M      0x000003FF  // Conversion Result Data
 #define ADC_SSFIFO2_DATA_S      0
 
 //*****************************************************************************
@@ -1795,10 +1786,10 @@
 // The following are defines for the bit fields in the ADC_O_SSFSTAT2 register.
 //
 //*****************************************************************************
-#define ADC_SSFSTAT2_FULL       0x00001000  // FIFO Full.
-#define ADC_SSFSTAT2_EMPTY      0x00000100  // FIFO Empty.
-#define ADC_SSFSTAT2_HPTR_M     0x000000F0  // FIFO Head Pointer.
-#define ADC_SSFSTAT2_TPTR_M     0x0000000F  // FIFO Tail Pointer.
+#define ADC_SSFSTAT2_FULL       0x00001000  // FIFO Full
+#define ADC_SSFSTAT2_EMPTY      0x00000100  // FIFO Empty
+#define ADC_SSFSTAT2_HPTR_M     0x000000F0  // FIFO Head Pointer
+#define ADC_SSFSTAT2_TPTR_M     0x0000000F  // FIFO Tail Pointer
 #define ADC_SSFSTAT2_HPTR_S     4
 #define ADC_SSFSTAT2_TPTR_S     0
 
@@ -1807,7 +1798,7 @@
 // The following are defines for the bit fields in the ADC_O_SSMUX3 register.
 //
 //*****************************************************************************
-#define ADC_SSMUX3_MUX0_M       0x00000007  // 1st Sample Input Select.
+#define ADC_SSMUX3_MUX0_M       0x00000007  // 1st Sample Input Select
 #define ADC_SSMUX3_MUX0_S       0
 
 //*****************************************************************************
@@ -1815,17 +1806,17 @@
 // The following are defines for the bit fields in the ADC_O_SSCTL3 register.
 //
 //*****************************************************************************
-#define ADC_SSCTL3_TS0          0x00000008  // 1st Sample Temp Sensor Select.
-#define ADC_SSCTL3_IE0          0x00000004  // 1st Sample Interrupt Enable.
-#define ADC_SSCTL3_END0         0x00000002  // 1st Sample is End of Sequence.
-#define ADC_SSCTL3_D0           0x00000001  // 1st Sample Diff Input Select.
+#define ADC_SSCTL3_TS0          0x00000008  // 1st Sample Temp Sensor Select
+#define ADC_SSCTL3_IE0          0x00000004  // 1st Sample Interrupt Enable
+#define ADC_SSCTL3_END0         0x00000002  // 1st Sample is End of Sequence
+#define ADC_SSCTL3_D0           0x00000001  // 1st Sample Diff Input Select
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the ADC_O_SSFIFO3 register.
 //
 //*****************************************************************************
-#define ADC_SSFIFO3_DATA_M      0x000003FF  // Conversion Result Data.
+#define ADC_SSFIFO3_DATA_M      0x000003FF  // Conversion Result Data
 #define ADC_SSFIFO3_DATA_S      0
 
 //*****************************************************************************
@@ -1833,10 +1824,10 @@
 // The following are defines for the bit fields in the ADC_O_SSFSTAT3 register.
 //
 //*****************************************************************************
-#define ADC_SSFSTAT3_FULL       0x00001000  // FIFO Full.
-#define ADC_SSFSTAT3_EMPTY      0x00000100  // FIFO Empty.
-#define ADC_SSFSTAT3_HPTR_M     0x000000F0  // FIFO Head Pointer.
-#define ADC_SSFSTAT3_TPTR_M     0x0000000F  // FIFO Tail Pointer.
+#define ADC_SSFSTAT3_FULL       0x00001000  // FIFO Full
+#define ADC_SSFSTAT3_EMPTY      0x00000100  // FIFO Empty
+#define ADC_SSFSTAT3_HPTR_M     0x000000F0  // FIFO Head Pointer
+#define ADC_SSFSTAT3_TPTR_M     0x0000000F  // FIFO Tail Pointer
 #define ADC_SSFSTAT3_HPTR_S     4
 #define ADC_SSFSTAT3_TPTR_S     0
 
@@ -1845,7 +1836,7 @@
 // The following are defines for the bit fields in the ADC_O_TMLB register.
 //
 //*****************************************************************************
-#define ADC_TMLB_LB             0x00000001  // Loopback Mode Enable.
+#define ADC_TMLB_LB             0x00000001  // Loopback Mode Enable
 
 //*****************************************************************************
 //
@@ -1853,53 +1844,39 @@
 // SSFIFOx when the ADC TMLB is enabled.
 //
 //*****************************************************************************
-#define ADC_SSFIFO_TMLB_CNT_M   0x000003C0  // Continuous Sample Counter.
-#define ADC_SSFIFO_TMLB_CONT    0x00000020  // Continuation Sample Indicator.
-#define ADC_SSFIFO_TMLB_DIFF    0x00000010  // Differential Sample Indicator.
-#define ADC_SSFIFO_TMLB_TS      0x00000008  // Temp Sensor Sample Indicator.
-#define ADC_SSFIFO_TMLB_MUX_M   0x00000007  // Analog Input Indicator.
+#define ADC_SSFIFO_TMLB_CNT_M   0x000003C0  // Continuous Sample Counter
+#define ADC_SSFIFO_TMLB_CONT    0x00000020  // Continuation Sample Indicator
+#define ADC_SSFIFO_TMLB_DIFF    0x00000010  // Differential Sample Indicator
+#define ADC_SSFIFO_TMLB_TS      0x00000008  // Temp Sensor Sample Indicator
+#define ADC_SSFIFO_TMLB_MUX_M   0x00000007  // Analog Input Indicator
 #define ADC_SSFIFO_TMLB_CNT_S   6           // Sample counter shift
 #define ADC_SSFIFO_TMLB_MUX_S   0           // Input channel number shift
 
-//*****************************************************************************
-//
-// The following are defines for the the interpretation of the data in the
-// SSFIFOx when the ADC TMLB is enabled.
-//
-//*****************************************************************************
-#define ADC_TMLB_CNT_M          0x000003C0  // Continuous Sample Counter.
-#define ADC_TMLB_CONT           0x00000020  // Continuation Sample Indicator.
-#define ADC_TMLB_DIFF           0x00000010  // Differential Sample Indicator.
-#define ADC_TMLB_TS             0x00000008  // Temp Sensor Sample Indicator.
-#define ADC_TMLB_MUX_M          0x00000007  // Analog Input Indicator.
-#define ADC_TMLB_CNT_S          6           // Sample counter shift
-#define ADC_TMLB_MUX_S          0           // Input channel number shift
-
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the COMP_O_ACMIS register.
 //
 //*****************************************************************************
 #define COMP_ACMIS_IN1          0x00000002  // Comparator 1 Masked Interrupt
-                                            // Status.
+                                            // Status
 #define COMP_ACMIS_IN0          0x00000001  // Comparator 0 Masked Interrupt
-                                            // Status.
+                                            // Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the COMP_O_ACRIS register.
 //
 //*****************************************************************************
-#define COMP_ACRIS_IN1          0x00000002  // Comparator 1 Interrupt Status.
-#define COMP_ACRIS_IN0          0x00000001  // Comparator 0 Interrupt Status.
+#define COMP_ACRIS_IN1          0x00000002  // Comparator 1 Interrupt Status
+#define COMP_ACRIS_IN0          0x00000001  // Comparator 0 Interrupt Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the COMP_O_ACINTEN register.
 //
 //*****************************************************************************
-#define COMP_ACINTEN_IN1        0x00000002  // Comparator 1 Interrupt Enable.
-#define COMP_ACINTEN_IN0        0x00000001  // Comparator 0 Interrupt Enable.
+#define COMP_ACINTEN_IN1        0x00000002  // Comparator 1 Interrupt Enable
+#define COMP_ACINTEN_IN0        0x00000001  // Comparator 0 Interrupt Enable
 
 //*****************************************************************************
 //
@@ -1907,9 +1884,9 @@
 // register.
 //
 //*****************************************************************************
-#define COMP_ACREFCTL_EN        0x00000200  // Resistor Ladder Enable.
-#define COMP_ACREFCTL_RNG       0x00000100  // Resistor Ladder Range.
-#define COMP_ACREFCTL_VREF_M    0x0000000F  // Resistor Ladder Voltage Ref.
+#define COMP_ACREFCTL_EN        0x00000200  // Resistor Ladder Enable
+#define COMP_ACREFCTL_RNG       0x00000100  // Resistor Ladder Range
+#define COMP_ACREFCTL_VREF_M    0x0000000F  // Resistor Ladder Voltage Ref
 #define COMP_ACREFCTL_VREF_S    0
 
 //*****************************************************************************
@@ -1917,181 +1894,296 @@
 // The following are defines for the bit fields in the COMP_O_ACSTAT0 register.
 //
 //*****************************************************************************
-#define COMP_ACSTAT0_OVAL       0x00000002  // Comparator Output Value.
+#define COMP_ACSTAT0_OVAL       0x00000002  // Comparator Output Value
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the COMP_O_ACCTL0 register.
 //
 //*****************************************************************************
-#define COMP_ACCTL0_TOEN        0x00000800  // Trigger Output Enable.
-#define COMP_ACCTL0_ASRCP_M     0x00000600  // Analog Source Positive.
-#define COMP_ACCTL0_ASRCP_PIN   0x00000000  // Pin value
+#define COMP_ACCTL0_TOEN        0x00000800  // Trigger Output Enable
+#define COMP_ACCTL0_ASRCP_M     0x00000600  // Analog Source Positive
+#define COMP_ACCTL0_ASRCP_PIN   0x00000000  // Pin value of Cn+
 #define COMP_ACCTL0_ASRCP_PIN0  0x00000200  // Pin value of C0+
 #define COMP_ACCTL0_ASRCP_REF   0x00000400  // Internal voltage reference
-#define COMP_ACCTL0_TSLVAL      0x00000080  // Trigger Sense Level Value.
-#define COMP_ACCTL0_TSEN_M      0x00000060  // Trigger Sense.
+                                            // (VIREF)
+#define COMP_ACCTL0_TSLVAL      0x00000080  // Trigger Sense Level Value
+#define COMP_ACCTL0_TSEN_M      0x00000060  // Trigger Sense
 #define COMP_ACCTL0_TSEN_LEVEL  0x00000000  // Level sense, see TSLVAL
 #define COMP_ACCTL0_TSEN_FALL   0x00000020  // Falling edge
 #define COMP_ACCTL0_TSEN_RISE   0x00000040  // Rising edge
 #define COMP_ACCTL0_TSEN_BOTH   0x00000060  // Either edge
-#define COMP_ACCTL0_ISLVAL      0x00000010  // Interrupt Sense Level Value.
-#define COMP_ACCTL0_ISEN_M      0x0000000C  // Interrupt Sense.
+#define COMP_ACCTL0_ISLVAL      0x00000010  // Interrupt Sense Level Value
+#define COMP_ACCTL0_ISEN_M      0x0000000C  // Interrupt Sense
 #define COMP_ACCTL0_ISEN_LEVEL  0x00000000  // Level sense, see ISLVAL
 #define COMP_ACCTL0_ISEN_FALL   0x00000004  // Falling edge
 #define COMP_ACCTL0_ISEN_RISE   0x00000008  // Rising edge
 #define COMP_ACCTL0_ISEN_BOTH   0x0000000C  // Either edge
-#define COMP_ACCTL0_CINV        0x00000002  // Comparator Output Invert.
+#define COMP_ACCTL0_CINV        0x00000002  // Comparator Output Invert
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the COMP_O_ACSTAT1 register.
 //
 //*****************************************************************************
-#define COMP_ACSTAT1_OVAL       0x00000002  // Comparator Output Value.
+#define COMP_ACSTAT1_OVAL       0x00000002  // Comparator Output Value
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the COMP_O_ACCTL1 register.
 //
 //*****************************************************************************
-#define COMP_ACCTL1_TOEN        0x00000800  // Trigger Output Enable.
-#define COMP_ACCTL1_ASRCP_M     0x00000600  // Analog Source Positive.
-#define COMP_ACCTL1_ASRCP_PIN   0x00000000  // Pin value
+#define COMP_ACCTL1_TOEN        0x00000800  // Trigger Output Enable
+#define COMP_ACCTL1_ASRCP_M     0x00000600  // Analog Source Positive
+#define COMP_ACCTL1_ASRCP_PIN   0x00000000  // Pin value of Cn+
 #define COMP_ACCTL1_ASRCP_PIN0  0x00000200  // Pin value of C0+
 #define COMP_ACCTL1_ASRCP_REF   0x00000400  // Internal voltage reference
-#define COMP_ACCTL1_TSLVAL      0x00000080  // Trigger Sense Level Value.
-#define COMP_ACCTL1_TSEN_M      0x00000060  // Trigger Sense.
+                                            // (VIREF)
+#define COMP_ACCTL1_TSLVAL      0x00000080  // Trigger Sense Level Value
+#define COMP_ACCTL1_TSEN_M      0x00000060  // Trigger Sense
 #define COMP_ACCTL1_TSEN_LEVEL  0x00000000  // Level sense, see TSLVAL
 #define COMP_ACCTL1_TSEN_FALL   0x00000020  // Falling edge
 #define COMP_ACCTL1_TSEN_RISE   0x00000040  // Rising edge
 #define COMP_ACCTL1_TSEN_BOTH   0x00000060  // Either edge
-#define COMP_ACCTL1_ISLVAL      0x00000010  // Interrupt Sense Level Value.
-#define COMP_ACCTL1_ISEN_M      0x0000000C  // Interrupt Sense.
+#define COMP_ACCTL1_ISLVAL      0x00000010  // Interrupt Sense Level Value
+#define COMP_ACCTL1_ISEN_M      0x0000000C  // Interrupt Sense
 #define COMP_ACCTL1_ISEN_LEVEL  0x00000000  // Level sense, see ISLVAL
 #define COMP_ACCTL1_ISEN_FALL   0x00000004  // Falling edge
 #define COMP_ACCTL1_ISEN_RISE   0x00000008  // Rising edge
 #define COMP_ACCTL1_ISEN_BOTH   0x0000000C  // Either edge
-#define COMP_ACCTL1_CINV        0x00000002  // Comparator Output Invert.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_MR0 register.
-//
-//*****************************************************************************
-#define PHY_MR0_RESET           0x00008000  // Reset Registers.
-#define PHY_MR0_LOOPBK          0x00004000  // Loopback Mode.
-#define PHY_MR0_SPEEDSL         0x00002000  // Speed Select.
-#define PHY_MR0_ANEGEN          0x00001000  // Auto-Negotiation Enable.
-#define PHY_MR0_PWRDN           0x00000800  // Power Down.
-#define PHY_MR0_ISO             0x00000400  // Isolate.
-#define PHY_MR0_RANEG           0x00000200  // Restart Auto-Negotiation.
-#define PHY_MR0_DUPLEX          0x00000100  // Set Duplex Mode.
-#define PHY_MR0_COLT            0x00000080  // Collision Test.
+#define COMP_ACCTL1_CINV        0x00000002  // Comparator Output Invert
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the MAC_O_RIS register.
 //
 //*****************************************************************************
-#define MAC_RIS_PHYINT          0x00000040  // PHY Interrupt.
-#define MAC_RIS_MDINT           0x00000020  // MII Transaction Complete.
-#define MAC_RIS_RXER            0x00000010  // Receive Error.
-#define MAC_RIS_FOV             0x00000008  // FIFO Overrun.
-#define MAC_RIS_TXEMP           0x00000004  // Transmit FIFO Empty.
-#define MAC_RIS_TXER            0x00000002  // Transmit Error.
-#define MAC_RIS_RXINT           0x00000001  // Packet Received.
+#define MAC_RIS_PHYINT          0x00000040  // PHY Interrupt
+#define MAC_RIS_MDINT           0x00000020  // MII Transaction Complete
+#define MAC_RIS_RXER            0x00000010  // Receive Error
+#define MAC_RIS_FOV             0x00000008  // FIFO Overrun
+#define MAC_RIS_TXEMP           0x00000004  // Transmit FIFO Empty
+#define MAC_RIS_TXER            0x00000002  // Transmit Error
+#define MAC_RIS_RXINT           0x00000001  // Packet Received
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the MAC_O_IACK register.
 //
 //*****************************************************************************
-#define MAC_IACK_PHYINT         0x00000040  // Clear PHY Interrupt.
-#define MAC_IACK_MDINT          0x00000020  // Clear MII Transaction Complete.
-#define MAC_IACK_RXER           0x00000010  // Clear Receive Error.
-#define MAC_IACK_FOV            0x00000008  // Clear FIFO Overrun.
-#define MAC_IACK_TXEMP          0x00000004  // Clear Transmit FIFO Empty.
-#define MAC_IACK_TXER           0x00000002  // Clear Transmit Error.
-#define MAC_IACK_RXINT          0x00000001  // Clear Packet Received.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_MR1 register.
-//
-//*****************************************************************************
-#define PHY_MR1_100X_F          0x00004000  // 100BASE-TX Full-Duplex Mode.
-#define PHY_MR1_100X_H          0x00002000  // 100BASE-TX Half-Duplex Mode.
-#define PHY_MR1_10T_F           0x00001000  // 10BASE-T Full-Duplex Mode.
-#define PHY_MR1_10T_H           0x00000800  // 10BASE-T Half-Duplex Mode.
-#define PHY_MR1_MFPS            0x00000040  // Management Frames with Preamble
-                                            // Suppressed.
-#define PHY_MR1_ANEGC           0x00000020  // Auto-Negotiation Complete.
-#define PHY_MR1_RFAULT          0x00000010  // Remote Fault.
-#define PHY_MR1_ANEGA           0x00000008  // Auto-Negotiation.
-#define PHY_MR1_LINK            0x00000004  // Link Made.
-#define PHY_MR1_JAB             0x00000002  // Jabber Condition.
-#define PHY_MR1_EXTD            0x00000001  // Extended Capabilities.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_MR2 register.
-//
-//*****************************************************************************
-#define PHY_MR2_OUI_M           0x0000FFFF  // Organizationally Unique
-                                            // Identifier[21:6].
-#define PHY_MR2_OUI_S           0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_MR3 register.
-//
-//*****************************************************************************
-#define PHY_MR3_OUI_M           0x0000FC00  // Organizationally Unique
-                                            // Identifier[5:0].
-#define PHY_MR3_MN_M            0x000003F0  // Model Number.
-#define PHY_MR3_RN_M            0x0000000F  // Revision Number.
-#define PHY_MR3_OUI_S           10
-#define PHY_MR3_MN_S            4
-#define PHY_MR3_RN_S            0
+#define MAC_IACK_PHYINT         0x00000040  // Clear PHY Interrupt
+#define MAC_IACK_MDINT          0x00000020  // Clear MII Transaction Complete
+#define MAC_IACK_RXER           0x00000010  // Clear Receive Error
+#define MAC_IACK_FOV            0x00000008  // Clear FIFO Overrun
+#define MAC_IACK_TXEMP          0x00000004  // Clear Transmit FIFO Empty
+#define MAC_IACK_TXER           0x00000002  // Clear Transmit Error
+#define MAC_IACK_RXINT          0x00000001  // Clear Packet Received
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the MAC_O_IM register.
 //
 //*****************************************************************************
-#define MAC_IM_PHYINTM          0x00000040  // Mask PHY Interrupt.
-#define MAC_IM_MDINTM           0x00000020  // Mask MII Transaction Complete.
-#define MAC_IM_RXERM            0x00000010  // Mask Receive Error.
-#define MAC_IM_FOVM             0x00000008  // Mask FIFO Overrun.
-#define MAC_IM_TXEMPM           0x00000004  // Mask Transmit FIFO Empty.
-#define MAC_IM_TXERM            0x00000002  // Mask Transmit Error.
-#define MAC_IM_RXINTM           0x00000001  // Mask Packet Received.
+#define MAC_IM_PHYINTM          0x00000040  // Mask PHY Interrupt
+#define MAC_IM_MDINTM           0x00000020  // Mask MII Transaction Complete
+#define MAC_IM_RXERM            0x00000010  // Mask Receive Error
+#define MAC_IM_FOVM             0x00000008  // Mask FIFO Overrun
+#define MAC_IM_TXEMPM           0x00000004  // Mask Transmit FIFO Empty
+#define MAC_IM_TXERM            0x00000002  // Mask Transmit Error
+#define MAC_IM_RXINTM           0x00000001  // Mask Packet Received
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the MAC_O_MR4 register.
+// The following are defines for the bit fields in the MAC_O_RCTL register.
 //
 //*****************************************************************************
-#define PHY_MR4_NP              0x00008000  // Next Page.
-#define PHY_MR4_RF              0x00002000  // Remote Fault.
-#define PHY_MR4_A3              0x00000100  // Technology Ability Field[3].
-#define PHY_MR4_A2              0x00000080  // Technology Ability Field[2].
-#define PHY_MR4_A1              0x00000040  // Technology Ability Field[1].
-#define PHY_MR4_A0              0x00000020  // Technology Ability Field[0].
-#define PHY_MR4_S_M             0x0000001F  // Selector Field.
+#define MAC_RCTL_RSTFIFO        0x00000010  // Clear Receive FIFO
+#define MAC_RCTL_BADCRC         0x00000008  // Enable Reject Bad CRC
+#define MAC_RCTL_PRMS           0x00000004  // Enable Promiscuous Mode
+#define MAC_RCTL_AMUL           0x00000002  // Enable Multicast Frames
+#define MAC_RCTL_RXEN           0x00000001  // Enable Receiver
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_TCTL register.
+//
+//*****************************************************************************
+#define MAC_TCTL_DUPLEX         0x00000010  // Enable Duplex Mode
+#define MAC_TCTL_CRC            0x00000004  // Enable CRC Generation
+#define MAC_TCTL_PADEN          0x00000002  // Enable Packet Padding
+#define MAC_TCTL_TXEN           0x00000001  // Enable Transmitter
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_DATA register.
+//
+//*****************************************************************************
+#define MAC_DATA_TXDATA_M       0xFFFFFFFF  // Transmit FIFO Data
+#define MAC_DATA_RXDATA_M       0xFFFFFFFF  // Receive FIFO Data
+#define MAC_DATA_RXDATA_S       0
+#define MAC_DATA_TXDATA_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_IA0 register.
+//
+//*****************************************************************************
+#define MAC_IA0_MACOCT4_M       0xFF000000  // MAC Address Octet 4
+#define MAC_IA0_MACOCT3_M       0x00FF0000  // MAC Address Octet 3
+#define MAC_IA0_MACOCT2_M       0x0000FF00  // MAC Address Octet 2
+#define MAC_IA0_MACOCT1_M       0x000000FF  // MAC Address Octet 1
+#define MAC_IA0_MACOCT4_S       24
+#define MAC_IA0_MACOCT3_S       16
+#define MAC_IA0_MACOCT2_S       8
+#define MAC_IA0_MACOCT1_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_IA1 register.
+//
+//*****************************************************************************
+#define MAC_IA1_MACOCT6_M       0x0000FF00  // MAC Address Octet 6
+#define MAC_IA1_MACOCT5_M       0x000000FF  // MAC Address Octet 5
+#define MAC_IA1_MACOCT6_S       8
+#define MAC_IA1_MACOCT5_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_THR register.
+//
+//*****************************************************************************
+#define MAC_THR_THRESH_M        0x0000003F  // Threshold Value
+#define MAC_THR_THRESH_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MCTL register.
+//
+//*****************************************************************************
+#define MAC_MCTL_REGADR_M       0x000000F8  // MII Register Address
+#define MAC_MCTL_WRITE          0x00000002  // MII Register Transaction Type
+#define MAC_MCTL_START          0x00000001  // MII Register Transaction Enable
+#define MAC_MCTL_REGADR_S       3
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MDV register.
+//
+//*****************************************************************************
+#define MAC_MDV_DIV_M           0x000000FF  // Clock Divider
+#define MAC_MDV_DIV_S           0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MTXD register.
+//
+//*****************************************************************************
+#define MAC_MTXD_MDTX_M         0x0000FFFF  // MII Register Transmit Data
+#define MAC_MTXD_MDTX_S         0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MRXD register.
+//
+//*****************************************************************************
+#define MAC_MRXD_MDRX_M         0x0000FFFF  // MII Register Receive Data
+#define MAC_MRXD_MDRX_S         0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_NP register.
+//
+//*****************************************************************************
+#define MAC_NP_NPR_M            0x0000003F  // Number of Packets in Receive
+                                            // FIFO
+#define MAC_NP_NPR_S            0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_TR register.
+//
+//*****************************************************************************
+#define MAC_TR_NEWTX            0x00000001  // New Transmission
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR0 register.
+//
+//*****************************************************************************
+#define PHY_MR0_RESET           0x00008000  // Reset Registers
+#define PHY_MR0_LOOPBK          0x00004000  // Loopback Mode
+#define PHY_MR0_SPEEDSL         0x00002000  // Speed Select
+#define PHY_MR0_ANEGEN          0x00001000  // Auto-Negotiation Enable
+#define PHY_MR0_PWRDN           0x00000800  // Power Down
+#define PHY_MR0_ISO             0x00000400  // Isolate
+#define PHY_MR0_RANEG           0x00000200  // Restart Auto-Negotiation
+#define PHY_MR0_DUPLEX          0x00000100  // Set Duplex Mode
+#define PHY_MR0_COLT            0x00000080  // Collision Test
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR1 register.
+//
+//*****************************************************************************
+#define PHY_MR1_100X_F          0x00004000  // 100BASE-TX Full-Duplex Mode
+#define PHY_MR1_100X_H          0x00002000  // 100BASE-TX Half-Duplex Mode
+#define PHY_MR1_10T_F           0x00001000  // 10BASE-T Full-Duplex Mode
+#define PHY_MR1_10T_H           0x00000800  // 10BASE-T Half-Duplex Mode
+#define PHY_MR1_MFPS            0x00000040  // Management Frames with Preamble
+                                            // Suppressed
+#define PHY_MR1_ANEGC           0x00000020  // Auto-Negotiation Complete
+#define PHY_MR1_RFAULT          0x00000010  // Remote Fault
+#define PHY_MR1_ANEGA           0x00000008  // Auto-Negotiation
+#define PHY_MR1_LINK            0x00000004  // Link Made
+#define PHY_MR1_JAB             0x00000002  // Jabber Condition
+#define PHY_MR1_EXTD            0x00000001  // Extended Capabilities
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR2 register.
+//
+//*****************************************************************************
+#define PHY_MR2_OUI_M           0x0000FFFF  // Organizationally Unique
+                                            // Identifier[21:6]
+#define PHY_MR2_OUI_S           0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR3 register.
+//
+//*****************************************************************************
+#define PHY_MR3_OUI_M           0x0000FC00  // Organizationally Unique
+                                            // Identifier[5:0]
+#define PHY_MR3_MN_M            0x000003F0  // Model Number
+#define PHY_MR3_RN_M            0x0000000F  // Revision Number
+#define PHY_MR3_OUI_S           10
+#define PHY_MR3_MN_S            4
+#define PHY_MR3_RN_S            0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR4 register.
+//
+//*****************************************************************************
+#define PHY_MR4_NP              0x00008000  // Next Page
+#define PHY_MR4_RF              0x00002000  // Remote Fault
+#define PHY_MR4_A3              0x00000100  // Technology Ability Field [3]
+#define PHY_MR4_A2              0x00000080  // Technology Ability Field [2]
+#define PHY_MR4_A1              0x00000040  // Technology Ability Field [1]
+#define PHY_MR4_A0              0x00000020  // Technology Ability Field [0]
+#define PHY_MR4_S_M             0x0000001F  // Selector Field
 #define PHY_MR4_S_S             0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the MAC_O_MR5 register.
+// The following are defines for the bit fields in the PHY_MR5 register.
 //
 //*****************************************************************************
-#define PHY_MR5_NP              0x00008000  // Next Page.
-#define PHY_MR5_ACK             0x00004000  // Acknowledge.
-#define PHY_MR5_RF              0x00002000  // Remote Fault.
-#define PHY_MR5_A_M             0x00001FE0  // Technology Ability Field.
-#define PHY_MR5_S_M             0x0000001F  // Selector Field.
+#define PHY_MR5_NP              0x00008000  // Next Page
+#define PHY_MR5_ACK             0x00004000  // Acknowledge
+#define PHY_MR5_RF              0x00002000  // Remote Fault
+#define PHY_MR5_A_M             0x00001FE0  // Technology Ability Field
+#define PHY_MR5_S_M             0x0000001F  // Selector Field
 #define PHY_MR5_S_8023          0x00000001  // IEEE Std 802.3
 #define PHY_MR5_S_8029          0x00000002  // IEEE Std 802.9 ISLAN-16T
 #define PHY_MR5_S_8025          0x00000003  // IEEE Std 802.5
@@ -2100,105 +2192,74 @@
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the MAC_O_MR6 register.
+// The following are defines for the bit fields in the PHY_MR6 register.
 //
 //*****************************************************************************
-#define PHY_MR6_PDF             0x00000010  // Parallel Detection Fault.
-#define PHY_MR6_LPNPA           0x00000008  // Link Partner is Next Page Able.
-#define PHY_MR6_PRX             0x00000002  // New Page Received.
+#define PHY_MR6_PDF             0x00000010  // Parallel Detection Fault
+#define PHY_MR6_LPNPA           0x00000008  // Link Partner is Next Page Able
+#define PHY_MR6_PRX             0x00000002  // New Page Received
 #define PHY_MR6_LPANEGA         0x00000001  // Link Partner is Auto-Negotiation
-                                            // Able.
+                                            // Able
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the MAC_O_RCTL register.
+// The following are defines for the bit fields in the PHY_MR16 register.
 //
 //*****************************************************************************
-#define MAC_RCTL_RSTFIFO        0x00000010  // Clear Receive FIFO.
-#define MAC_RCTL_BADCRC         0x00000008  // Enable Reject Bad CRC.
-#define MAC_RCTL_PRMS           0x00000004  // Enable Promiscuous Mode.
-#define MAC_RCTL_AMUL           0x00000002  // Enable Multicast Frames.
-#define MAC_RCTL_RXEN           0x00000001  // Enable Receiver.
+#define PHY_MR16_RPTR           0x00008000  // Repeater Mode
+#define PHY_MR16_INPOL          0x00004000  // Interrupt Polarity
+#define PHY_MR16_TXHIM          0x00001000  // Transmit High Impedance Mode
+#define PHY_MR16_SQEI           0x00000800  // SQE Inhibit Testing
+#define PHY_MR16_NL10           0x00000400  // Natural Loopback Mode
+#define PHY_MR16_APOL           0x00000020  // Auto-Polarity Disable
+#define PHY_MR16_RVSPOL         0x00000010  // Receive Data Polarity
+#define PHY_MR16_PCSBP          0x00000002  // PCS Bypass
+#define PHY_MR16_RXCC           0x00000001  // Receive Clock Control
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the MAC_O_TCTL register.
+// The following are defines for the bit fields in the PHY_MR17 register.
 //
 //*****************************************************************************
-#define MAC_TCTL_DUPLEX         0x00000010  // Enable Duplex Mode.
-#define MAC_TCTL_CRC            0x00000004  // Enable CRC Generation.
-#define MAC_TCTL_PADEN          0x00000002  // Enable Packet Padding.
-#define MAC_TCTL_TXEN           0x00000001  // Enable Transmitter.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_DATA register.
-//
-//*****************************************************************************
-#define MAC_DATA_TXDATA_M       0xFFFFFFFF  // Transmit FIFO Data.
-#define MAC_DATA_RXDATA_M       0xFFFFFFFF  // Receive FIFO Data.
-#define MAC_DATA_RXDATA_S       0
-#define MAC_DATA_TXDATA_S       0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_MR16 register.
-//
-//*****************************************************************************
-#define PHY_MR16_RPTR           0x00008000  // Repeater Mode.
-#define PHY_MR16_INPOL          0x00004000  // Interrupt Polarity.
-#define PHY_MR16_TXHIM          0x00001000  // Transmit High Impedance Mode.
-#define PHY_MR16_SQEI           0x00000800  // SQE Inhibit Testing.
-#define PHY_MR16_NL10           0x00000400  // Natural Loopback Mode.
-#define PHY_MR16_APOL           0x00000020  // Auto-Polarity Disable.
-#define PHY_MR16_RVSPOL         0x00000010  // Receive Data Polarity.
-#define PHY_MR16_PCSBP          0x00000002  // PCS Bypass.
-#define PHY_MR16_RXCC           0x00000001  // Receive Clock Control.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_MR17 register.
-//
-//*****************************************************************************
-#define PHY_MR17_JABBER_IE      0x00008000  // Jabber Interrupt Enable.
-#define PHY_MR17_RXER_IE        0x00004000  // Receive Error Interrupt Enable.
-#define PHY_MR17_PRX_IE         0x00002000  // Page Received Interrupt Enable.
+#define PHY_MR17_JABBER_IE      0x00008000  // Jabber Interrupt Enable
+#define PHY_MR17_RXER_IE        0x00004000  // Receive Error Interrupt Enable
+#define PHY_MR17_PRX_IE         0x00002000  // Page Received Interrupt Enable
 #define PHY_MR17_PDF_IE         0x00001000  // Parallel Detection Fault
-                                            // Interrupt Enable.
-#define PHY_MR17_LPACK_IE       0x00000800  // LP Acknowledge Interrupt Enable.
+                                            // Interrupt Enable
+#define PHY_MR17_LPACK_IE       0x00000800  // LP Acknowledge Interrupt Enable
 #define PHY_MR17_LSCHG_IE       0x00000400  // Link Status Change Interrupt
-                                            // Enable.
-#define PHY_MR17_RFAULT_IE      0x00000200  // Remote Fault Interrupt Enable.
+                                            // Enable
+#define PHY_MR17_RFAULT_IE      0x00000200  // Remote Fault Interrupt Enable
 #define PHY_MR17_ANEGCOMP_IE    0x00000100  // Auto-Negotiation Complete
-                                            // Interrupt Enable.
-#define PHY_MR17_JABBER_INT     0x00000080  // Jabber Event Interrupt.
-#define PHY_MR17_RXER_INT       0x00000040  // Receive Error Interrupt.
-#define PHY_MR17_PRX_INT        0x00000020  // Page Receive Interrupt.
+                                            // Interrupt Enable
+#define PHY_MR17_JABBER_INT     0x00000080  // Jabber Event Interrupt
+#define PHY_MR17_RXER_INT       0x00000040  // Receive Error Interrupt
+#define PHY_MR17_PRX_INT        0x00000020  // Page Receive Interrupt
 #define PHY_MR17_PDF_INT        0x00000010  // Parallel Detection Fault
-                                            // Interrupt.
-#define PHY_MR17_LPACK_INT      0x00000008  // LP Acknowledge Interrupt.
-#define PHY_MR17_LSCHG_INT      0x00000004  // Link Status Change Interrupt.
-#define PHY_MR17_RFAULT_INT     0x00000002  // Remote Fault Interrupt.
+                                            // Interrupt
+#define PHY_MR17_LPACK_INT      0x00000008  // LP Acknowledge Interrupt
+#define PHY_MR17_LSCHG_INT      0x00000004  // Link Status Change Interrupt
+#define PHY_MR17_RFAULT_INT     0x00000002  // Remote Fault Interrupt
 #define PHY_MR17_ANEGCOMP_INT   0x00000001  // Auto-Negotiation Complete
-                                            // Interrupt.
+                                            // Interrupt
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the MAC_O_MR18 register.
+// The following are defines for the bit fields in the PHY_MR18 register.
 //
 //*****************************************************************************
-#define PHY_MR18_ANEGF          0x00001000  // Auto-Negotiation Failure.
-#define PHY_MR18_DPLX           0x00000800  // Duplex Mode.
-#define PHY_MR18_RATE           0x00000400  // Rate.
-#define PHY_MR18_RXSD           0x00000200  // Receive Detection.
-#define PHY_MR18_RX_LOCK        0x00000100  // Receive PLL Lock.
+#define PHY_MR18_ANEGF          0x00001000  // Auto-Negotiation Failure
+#define PHY_MR18_DPLX           0x00000800  // Duplex Mode
+#define PHY_MR18_RATE           0x00000400  // Rate
+#define PHY_MR18_RXSD           0x00000200  // Receive Detection
+#define PHY_MR18_RX_LOCK        0x00000100  // Receive PLL Lock
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the MAC_O_MR19 register.
+// The following are defines for the bit fields in the PHY_MR19 register.
 //
 //*****************************************************************************
-#define PHY_MR19_TXO_M          0x0000C000  // Transmit Amplitude Selection.
+#define PHY_MR19_TXO_M          0x0000C000  // Transmit Amplitude Selection
 #define PHY_MR19_TXO_00DB       0x00000000  // Gain set for 0.0dB of insertion
                                             // loss
 #define PHY_MR19_TXO_04DB       0x00004000  // Gain set for 0.4dB of insertion
@@ -2210,24 +2271,10 @@
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the MAC_O_IA0 register.
+// The following are defines for the bit fields in the PHY_MR23 register.
 //
 //*****************************************************************************
-#define MAC_IA0_MACOCT4_M       0xFF000000  // MAC Address Octet 4.
-#define MAC_IA0_MACOCT3_M       0x00FF0000  // MAC Address Octet 3.
-#define MAC_IA0_MACOCT2_M       0x0000FF00  // MAC Address Octet 2.
-#define MAC_IA0_MACOCT1_M       0x000000FF  // MAC Address Octet 1.
-#define MAC_IA0_MACOCT4_S       24
-#define MAC_IA0_MACOCT3_S       16
-#define MAC_IA0_MACOCT2_S       8
-#define MAC_IA0_MACOCT1_S       0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_MR23 register.
-//
-//*****************************************************************************
-#define PHY_MR23_LED1_M         0x000000F0  // LED1 Source.
+#define PHY_MR23_LED1_M         0x000000F0  // LED1 Source
 #define PHY_MR23_LED1_LINK      0x00000000  // Link OK
 #define PHY_MR23_LED1_RXTX      0x00000010  // RX or TX Activity (Default LED1)
 #define PHY_MR23_LED1_100       0x00000050  // 100BASE-TX mode
@@ -2235,7 +2282,7 @@
 #define PHY_MR23_LED1_DUPLEX    0x00000070  // Full-Duplex
 #define PHY_MR23_LED1_LINKACT   0x00000080  // Link OK & Blink=RX or TX
                                             // Activity
-#define PHY_MR23_LED0_M         0x0000000F  // LED0 Source.
+#define PHY_MR23_LED0_M         0x0000000F  // LED0 Source
 #define PHY_MR23_LED0_LINK      0x00000000  // Link OK (Default LED0)
 #define PHY_MR23_LED0_RXTX      0x00000001  // RX or TX Activity
 #define PHY_MR23_LED0_100       0x00000005  // 100BASE-TX mode
@@ -2246,90 +2293,22 @@
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the MAC_O_IA1 register.
+// The following are defines for the bit fields in the PHY_MR24 register.
 //
 //*****************************************************************************
-#define MAC_IA1_MACOCT6_M       0x0000FF00  // MAC Address Octet 6.
-#define MAC_IA1_MACOCT5_M       0x000000FF  // MAC Address Octet 5.
-#define MAC_IA1_MACOCT6_S       8
-#define MAC_IA1_MACOCT5_S       0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_MR24 register.
-//
-//*****************************************************************************
-#define PHY_MR24_PD_MODE        0x00000080  // Parallel Detection Mode.
-#define PHY_MR24_AUTO_SW        0x00000040  // Auto-Switching Enable.
-#define PHY_MR24_MDIX           0x00000020  // Auto-Switching Configuration.
-#define PHY_MR24_MDIX_CM        0x00000010  // Auto-Switching Complete.
-#define PHY_MR24_MDIX_SD_M      0x0000000F  // Auto-Switching Seed.
+#define PHY_MR24_PD_MODE        0x00000080  // Parallel Detection Mode
+#define PHY_MR24_AUTO_SW        0x00000040  // Auto-Switching Enable
+#define PHY_MR24_MDIX           0x00000020  // Auto-Switching Configuration
+#define PHY_MR24_MDIX_CM        0x00000010  // Auto-Switching Complete
+#define PHY_MR24_MDIX_SD_M      0x0000000F  // Auto-Switching Seed
 #define PHY_MR24_MDIX_SD_S      0
 
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_THR register.
-//
-//*****************************************************************************
-#define MAC_THR_THRESH_M        0x0000003F  // Threshold Value.
-#define MAC_THR_THRESH_S        0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_MCTL register.
-//
-//*****************************************************************************
-#define MAC_MCTL_REGADR_M       0x000000F8  // MII Register Address.
-#define MAC_MCTL_WRITE          0x00000002  // MII Register Transaction Type.
-#define MAC_MCTL_START          0x00000001  // MII Register Transaction Enable.
-#define MAC_MCTL_REGADR_S       3
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_MDV register.
-//
-//*****************************************************************************
-#define MAC_MDV_DIV_M           0x000000FF  // Clock Divider.
-#define MAC_MDV_DIV_S           0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_MTXD register.
-//
-//*****************************************************************************
-#define MAC_MTXD_MDTX_M         0x0000FFFF  // MII Register Transmit Data.
-#define MAC_MTXD_MDTX_S         0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_MRXD register.
-//
-//*****************************************************************************
-#define MAC_MRXD_MDRX_M         0x0000FFFF  // MII Register Receive Data.
-#define MAC_MRXD_MDRX_S         0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_NP register.
-//
-//*****************************************************************************
-#define MAC_NP_NPR_M            0x0000003F  // Number of Packets in Receive
-                                            // FIFO.
-#define MAC_NP_NPR_S            0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_TR register.
-//
-//*****************************************************************************
-#define MAC_TR_NEWTX            0x00000001  // New Transmission.
-
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the HIB_RTCC register.
 //
 //*****************************************************************************
-#define HIB_RTCC_M              0xFFFFFFFF  // RTC Counter.
+#define HIB_RTCC_M              0xFFFFFFFF  // RTC Counter
 #define HIB_RTCC_S              0
 
 //*****************************************************************************
@@ -2337,7 +2316,7 @@
 // The following are defines for the bit fields in the HIB_RTCM0 register.
 //
 //*****************************************************************************
-#define HIB_RTCM0_M             0xFFFFFFFF  // RTC Match 0.
+#define HIB_RTCM0_M             0xFFFFFFFF  // RTC Match 0
 #define HIB_RTCM0_S             0
 
 //*****************************************************************************
@@ -2345,7 +2324,7 @@
 // The following are defines for the bit fields in the HIB_RTCM1 register.
 //
 //*****************************************************************************
-#define HIB_RTCM1_M             0xFFFFFFFF  // RTC Match 1.
+#define HIB_RTCM1_M             0xFFFFFFFF  // RTC Match 1
 #define HIB_RTCM1_S             0
 
 //*****************************************************************************
@@ -2353,7 +2332,7 @@
 // The following are defines for the bit fields in the HIB_RTCLD register.
 //
 //*****************************************************************************
-#define HIB_RTCLD_M             0xFFFFFFFF  // RTC Load.
+#define HIB_RTCLD_M             0xFFFFFFFF  // RTC Load
 #define HIB_RTCLD_S             0
 
 //*****************************************************************************
@@ -2361,25 +2340,25 @@
 // The following are defines for the bit fields in the HIB_CTL register.
 //
 //*****************************************************************************
-#define HIB_CTL_VABORT          0x00000080  // Power Cut Abort Enable.
-#define HIB_CTL_CLK32EN         0x00000040  // Clocking Enable.
-#define HIB_CTL_LOWBATEN        0x00000020  // Low Battery Monitoring Enable.
-#define HIB_CTL_PINWEN          0x00000010  // External WAKE Pin Enable.
-#define HIB_CTL_RTCWEN          0x00000008  // RTC Wake-up Enable.
-#define HIB_CTL_CLKSEL          0x00000004  // Hibernation Module Clock Select.
-#define HIB_CTL_HIBREQ          0x00000002  // Hibernation Request.
-#define HIB_CTL_RTCEN           0x00000001  // RTC Timer Enable.
+#define HIB_CTL_VABORT          0x00000080  // Power Cut Abort Enable
+#define HIB_CTL_CLK32EN         0x00000040  // Clocking Enable
+#define HIB_CTL_LOWBATEN        0x00000020  // Low Battery Monitoring Enable
+#define HIB_CTL_PINWEN          0x00000010  // External WAKE Pin Enable
+#define HIB_CTL_RTCWEN          0x00000008  // RTC Wake-up Enable
+#define HIB_CTL_CLKSEL          0x00000004  // Hibernation Module Clock Select
+#define HIB_CTL_HIBREQ          0x00000002  // Hibernation Request
+#define HIB_CTL_RTCEN           0x00000001  // RTC Timer Enable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the HIB_IM register.
 //
 //*****************************************************************************
-#define HIB_IM_EXTW             0x00000008  // External Wake-Up Interrupt Mask.
+#define HIB_IM_EXTW             0x00000008  // External Wake-Up Interrupt Mask
 #define HIB_IM_LOWBAT           0x00000004  // Low Battery Voltage Interrupt
-                                            // Mask.
-#define HIB_IM_RTCALT1          0x00000002  // RTC Alert1 Interrupt Mask.
-#define HIB_IM_RTCALT0          0x00000001  // RTC Alert0 Interrupt Mask.
+                                            // Mask
+#define HIB_IM_RTCALT1          0x00000002  // RTC Alert 1 Interrupt Mask
+#define HIB_IM_RTCALT0          0x00000001  // RTC Alert 0 Interrupt Mask
 
 //*****************************************************************************
 //
@@ -2387,11 +2366,11 @@
 //
 //*****************************************************************************
 #define HIB_RIS_EXTW            0x00000008  // External Wake-Up Raw Interrupt
-                                            // Status.
+                                            // Status
 #define HIB_RIS_LOWBAT          0x00000004  // Low Battery Voltage Raw
-                                            // Interrupt Status.
-#define HIB_RIS_RTCALT1         0x00000002  // RTC Alert1 Raw Interrupt Status.
-#define HIB_RIS_RTCALT0         0x00000001  // RTC Alert0 Raw Interrupt Status.
+                                            // Interrupt Status
+#define HIB_RIS_RTCALT1         0x00000002  // RTC Alert 1 Raw Interrupt Status
+#define HIB_RIS_RTCALT0         0x00000001  // RTC Alert 0 Raw Interrupt Status
 
 //*****************************************************************************
 //
@@ -2399,13 +2378,13 @@
 //
 //*****************************************************************************
 #define HIB_MIS_EXTW            0x00000008  // External Wake-Up Masked
-                                            // Interrupt Status.
+                                            // Interrupt Status
 #define HIB_MIS_LOWBAT          0x00000004  // Low Battery Voltage Masked
-                                            // Interrupt Status.
-#define HIB_MIS_RTCALT1         0x00000002  // RTC Alert1 Masked Interrupt
-                                            // Status.
-#define HIB_MIS_RTCALT0         0x00000001  // RTC Alert0 Masked Interrupt
-                                            // Status.
+                                            // Interrupt Status
+#define HIB_MIS_RTCALT1         0x00000002  // RTC Alert 1 Masked Interrupt
+                                            // Status
+#define HIB_MIS_RTCALT0         0x00000001  // RTC Alert 0 Masked Interrupt
+                                            // Status
 
 //*****************************************************************************
 //
@@ -2413,20 +2392,20 @@
 //
 //*****************************************************************************
 #define HIB_IC_EXTW             0x00000008  // External Wake-Up Masked
-                                            // Interrupt Clear.
+                                            // Interrupt Clear
 #define HIB_IC_LOWBAT           0x00000004  // Low Battery Voltage Masked
-                                            // Interrupt Clear.
+                                            // Interrupt Clear
 #define HIB_IC_RTCALT1          0x00000002  // RTC Alert1 Masked Interrupt
-                                            // Clear.
+                                            // Clear
 #define HIB_IC_RTCALT0          0x00000001  // RTC Alert0 Masked Interrupt
-                                            // Clear.
+                                            // Clear
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the HIB_RTCT register.
 //
 //*****************************************************************************
-#define HIB_RTCT_TRIM_M         0x0000FFFF  // RTC Trim Value.
+#define HIB_RTCT_TRIM_M         0x0000FFFF  // RTC Trim Value
 #define HIB_RTCT_TRIM_S         0
 
 //*****************************************************************************
@@ -2434,8 +2413,7 @@
 // The following are defines for the bit fields in the HIB_DATA register.
 //
 //*****************************************************************************
-#define HIB_DATA_RTD_M          0xFFFFFFFF  // Hibernation Module NV
-                                            // Registers[63:0].
+#define HIB_DATA_RTD_M          0xFFFFFFFF  // Hibernation Module NV Data
 #define HIB_DATA_RTD_S          0
 
 //*****************************************************************************
@@ -2443,7 +2421,7 @@
 // The following are defines for the bit fields in the FLASH_FMA register.
 //
 //*****************************************************************************
-#define FLASH_FMA_OFFSET_M      0x0003FFFF  // Address Offset.
+#define FLASH_FMA_OFFSET_M      0x0003FFFF  // Address Offset
 #define FLASH_FMA_OFFSET_S      0
 
 //*****************************************************************************
@@ -2451,7 +2429,7 @@
 // The following are defines for the bit fields in the FLASH_FMD register.
 //
 //*****************************************************************************
-#define FLASH_FMD_DATA_M        0xFFFFFFFF  // Data Value.
+#define FLASH_FMD_DATA_M        0xFFFFFFFF  // Data Value
 #define FLASH_FMD_DATA_S        0
 
 //*****************************************************************************
@@ -2459,30 +2437,27 @@
 // The following are defines for the bit fields in the FLASH_FMC register.
 //
 //*****************************************************************************
-#define FLASH_FMC_WRKEY_M       0xFFFF0000  // Flash Write Key.
 #define FLASH_FMC_WRKEY         0xA4420000  // FLASH write key
-#define FLASH_FMC_COMT          0x00000008  // Commit Register Value.
-#define FLASH_FMC_MERASE        0x00000004  // Mass Erase Flash Memory.
-#define FLASH_FMC_ERASE         0x00000002  // Erase a Page of Flash Memory.
-#define FLASH_FMC_WRITE         0x00000001  // Write a Word into Flash Memory.
-#define FLASH_FMC_WRKEY_S       16
+#define FLASH_FMC_COMT          0x00000008  // Commit Register Value
+#define FLASH_FMC_MERASE        0x00000004  // Mass Erase Flash Memory
+#define FLASH_FMC_ERASE         0x00000002  // Erase a Page of Flash Memory
+#define FLASH_FMC_WRITE         0x00000001  // Write a Word into Flash Memory
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the FLASH_FCRIS register.
 //
 //*****************************************************************************
-#define FLASH_FCRIS_PRIS        0x00000002  // Programming Raw Interrupt
-                                            // Status.
-#define FLASH_FCRIS_ARIS        0x00000001  // Access Raw Interrupt Status.
+#define FLASH_FCRIS_PRIS        0x00000002  // Programming Raw Interrupt Status
+#define FLASH_FCRIS_ARIS        0x00000001  // Access Raw Interrupt Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the FLASH_FCIM register.
 //
 //*****************************************************************************
-#define FLASH_FCIM_PMASK        0x00000002  // Programming Interrupt Mask.
-#define FLASH_FCIM_AMASK        0x00000001  // Access Interrupt Mask.
+#define FLASH_FCIM_PMASK        0x00000002  // Programming Interrupt Mask
+#define FLASH_FCIM_AMASK        0x00000001  // Access Interrupt Mask
 
 //*****************************************************************************
 //
@@ -2490,16 +2465,16 @@
 //
 //*****************************************************************************
 #define FLASH_FCMISC_PMISC      0x00000002  // Programming Masked Interrupt
-                                            // Status and Clear.
+                                            // Status and Clear
 #define FLASH_FCMISC_AMISC      0x00000001  // Access Masked Interrupt Status
-                                            // and Clear.
+                                            // and Clear
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the FLASH_USECRL register.
 //
 //*****************************************************************************
-#define FLASH_USECRL_M          0x000000FF  // Microsecond Reload Value.
+#define FLASH_USECRL_M          0x000000FF  // Microsecond Reload Value
 #define FLASH_USECRL_S          0
 
 //*****************************************************************************
@@ -2507,10 +2482,10 @@
 // The following are defines for the bit fields in the FLASH_USERDBG register.
 //
 //*****************************************************************************
-#define FLASH_USERDBG_NW        0x80000000  // User Debug Not Written.
-#define FLASH_USERDBG_DATA_M    0x7FFFFFFC  // User Data.
-#define FLASH_USERDBG_DBG1      0x00000002  // Debug Control 1.
-#define FLASH_USERDBG_DBG0      0x00000001  // Debug Control 0.
+#define FLASH_USERDBG_NW        0x80000000  // User Debug Not Written
+#define FLASH_USERDBG_DATA_M    0x7FFFFFFC  // User Data
+#define FLASH_USERDBG_DBG1      0x00000002  // Debug Control 1
+#define FLASH_USERDBG_DBG0      0x00000001  // Debug Control 0
 #define FLASH_USERDBG_DATA_S    2
 
 //*****************************************************************************
@@ -2518,8 +2493,8 @@
 // The following are defines for the bit fields in the FLASH_USERREG0 register.
 //
 //*****************************************************************************
-#define FLASH_USERREG0_NW       0x80000000  // Not Written.
-#define FLASH_USERREG0_DATA_M   0x7FFFFFFF  // User Data.
+#define FLASH_USERREG0_NW       0x80000000  // Not Written
+#define FLASH_USERREG0_DATA_M   0x7FFFFFFF  // User Data
 #define FLASH_USERREG0_DATA_S   0
 
 //*****************************************************************************
@@ -2527,8 +2502,8 @@
 // The following are defines for the bit fields in the FLASH_USERREG1 register.
 //
 //*****************************************************************************
-#define FLASH_USERREG1_NW       0x80000000  // Not Written.
-#define FLASH_USERREG1_DATA_M   0x7FFFFFFF  // User Data.
+#define FLASH_USERREG1_NW       0x80000000  // Not Written
+#define FLASH_USERREG1_DATA_M   0x7FFFFFFF  // User Data
 #define FLASH_USERREG1_DATA_S   0
 
 //*****************************************************************************
@@ -2546,54 +2521,54 @@
 // The following are defines for the bit fields in the SYSCTL_DID0 register.
 //
 //*****************************************************************************
-#define SYSCTL_DID0_VER_M       0x70000000  // DID0 Version.
+#define SYSCTL_DID0_VER_M       0x70000000  // DID0 Version
 #define SYSCTL_DID0_VER_1       0x10000000  // Second version of the DID0
-                                            // register format.
-#define SYSCTL_DID0_CLASS_M     0x00FF0000  // Device Class.
-#define SYSCTL_DID0_CLASS_FURY  0x00010000  // Stellaris(r) Fury-class devices.
-#define SYSCTL_DID0_MAJ_M       0x0000FF00  // Major Revision.
+                                            // register format
+#define SYSCTL_DID0_CLASS_M     0x00FF0000  // Device Class
+#define SYSCTL_DID0_CLASS_FURY  0x00010000  // Stellaris(R) Fury-class devices
+#define SYSCTL_DID0_MAJ_M       0x0000FF00  // Major Revision
 #define SYSCTL_DID0_MAJ_REVA    0x00000000  // Revision A (initial device)
 #define SYSCTL_DID0_MAJ_REVB    0x00000100  // Revision B (first base layer
                                             // revision)
 #define SYSCTL_DID0_MAJ_REVC    0x00000200  // Revision C (second base layer
                                             // revision)
-#define SYSCTL_DID0_MIN_M       0x000000FF  // Minor Revision.
+#define SYSCTL_DID0_MIN_M       0x000000FF  // Minor Revision
 #define SYSCTL_DID0_MIN_0       0x00000000  // Initial device, or a major
-                                            // revision update.
-#define SYSCTL_DID0_MIN_1       0x00000001  // First metal layer change.
-#define SYSCTL_DID0_MIN_2       0x00000002  // Second metal layer change.
+                                            // revision update
+#define SYSCTL_DID0_MIN_1       0x00000001  // First metal layer change
+#define SYSCTL_DID0_MIN_2       0x00000002  // Second metal layer change
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_DID1 register.
 //
 //*****************************************************************************
-#define SYSCTL_DID1_VER_M       0xF0000000  // DID1 Version.
+#define SYSCTL_DID1_VER_M       0xF0000000  // DID1 Version
 #define SYSCTL_DID1_VER_1       0x10000000  // Second version of the DID1
-                                            // register format.
-#define SYSCTL_DID1_FAM_M       0x0F000000  // Family.
+                                            // register format
+#define SYSCTL_DID1_FAM_M       0x0F000000  // Family
 #define SYSCTL_DID1_FAM_STELLARIS \
                                 0x00000000  // Stellaris family of
                                             // microcontollers, that is, all
                                             // devices with external part
-                                            // numbers starting with LM3S.
-#define SYSCTL_DID1_PRTNO_M     0x00FF0000  // Part Number.
+                                            // numbers starting with LM3S
+#define SYSCTL_DID1_PRTNO_M     0x00FF0000  // Part Number
 #define SYSCTL_DID1_PRTNO_6918  0x00E80000  // LM3S6918
-#define SYSCTL_DID1_PINCNT_M    0x0000E000  // Package Pin Count.
-#define SYSCTL_DID1_PINCNT_100  0x00004000  // 100-pin or 108-ball package
-#define SYSCTL_DID1_TEMP_M      0x000000E0  // Temperature Range.
+#define SYSCTL_DID1_PINCNT_M    0x0000E000  // Package Pin Count
+#define SYSCTL_DID1_PINCNT_100  0x00004000  // 100-pin package
+#define SYSCTL_DID1_TEMP_M      0x000000E0  // Temperature Range
 #define SYSCTL_DID1_TEMP_C      0x00000000  // Commercial temperature range (0C
                                             // to 70C)
 #define SYSCTL_DID1_TEMP_I      0x00000020  // Industrial temperature range
                                             // (-40C to 85C)
 #define SYSCTL_DID1_TEMP_E      0x00000040  // Extended temperature range (-40C
                                             // to 105C)
-#define SYSCTL_DID1_PKG_M       0x00000018  // Package Type.
-#define SYSCTL_DID1_PKG_28SOIC  0x00000000  // SOIC package
-#define SYSCTL_DID1_PKG_48QFP   0x00000008  // LQFP package
+#define SYSCTL_DID1_PKG_M       0x00000018  // Package Type
+#define SYSCTL_DID1_PKG_SOIC    0x00000000  // SOIC package
+#define SYSCTL_DID1_PKG_QFP     0x00000008  // LQFP package
 #define SYSCTL_DID1_PKG_BGA     0x00000010  // BGA package
-#define SYSCTL_DID1_ROHS        0x00000004  // RoHS-Compliance.
-#define SYSCTL_DID1_QUAL_M      0x00000003  // Qualification Status.
+#define SYSCTL_DID1_ROHS        0x00000004  // RoHS-Compliance
+#define SYSCTL_DID1_QUAL_M      0x00000003  // Qualification Status
 #define SYSCTL_DID1_QUAL_ES     0x00000000  // Engineering Sample (unqualified)
 #define SYSCTL_DID1_QUAL_PP     0x00000001  // Pilot Production (unqualified)
 #define SYSCTL_DID1_QUAL_FQ     0x00000002  // Fully Qualified
@@ -2603,9 +2578,9 @@
 // The following are defines for the bit fields in the SYSCTL_DC0 register.
 //
 //*****************************************************************************
-#define SYSCTL_DC0_SRAMSZ_M     0xFFFF0000  // SRAM Size.
+#define SYSCTL_DC0_SRAMSZ_M     0xFFFF0000  // SRAM Size
 #define SYSCTL_DC0_SRAMSZ_64KB  0x00FF0000  // 64 KB of SRAM
-#define SYSCTL_DC0_FLASHSZ_M    0x0000FFFF  // Flash Size.
+#define SYSCTL_DC0_FLASHSZ_M    0x0000FFFF  // Flash Size
 #define SYSCTL_DC0_FLASHSZ_256K 0x0000007F  // 256 KB of Flash
 #define SYSCTL_DC0_SRAMSZ_S     16          // SRAM size shift
 #define SYSCTL_DC0_FLASHSZ_S    0           // Flash size shift
@@ -2615,94 +2590,94 @@
 // The following are defines for the bit fields in the SYSCTL_DC1 register.
 //
 //*****************************************************************************
-#define SYSCTL_DC1_ADC          0x00010000  // ADC Module Present.
-#define SYSCTL_DC1_MINSYSDIV_M  0x0000F000  // System Clock Divider.
+#define SYSCTL_DC1_ADC          0x00010000  // ADC Module Present
+#define SYSCTL_DC1_MINSYSDIV_M  0x0000F000  // System Clock Divider
 #define SYSCTL_DC1_MINSYSDIV_50 0x00003000  // Specifies a 50-MHz CPU clock
-                                            // with a PLL divider of 4.
-#define SYSCTL_DC1_ADCSPD_M     0x00000300  // Max ADC Speed.
+                                            // with a PLL divider of 4
+#define SYSCTL_DC1_ADCSPD_M     0x00000300  // Max ADC Speed
 #define SYSCTL_DC1_ADCSPD_500K  0x00000200  // 500K samples/second
-#define SYSCTL_DC1_MPU          0x00000080  // MPU Present.
-#define SYSCTL_DC1_HIB          0x00000040  // Hibernation Module Present.
-#define SYSCTL_DC1_TEMP         0x00000020  // Temp Sensor Present.
-#define SYSCTL_DC1_PLL          0x00000010  // PLL Present.
-#define SYSCTL_DC1_WDT          0x00000008  // Watchdog Timer Present.
-#define SYSCTL_DC1_SWO          0x00000004  // SWO Trace Port Present.
-#define SYSCTL_DC1_SWD          0x00000002  // SWD Present.
-#define SYSCTL_DC1_JTAG         0x00000001  // JTAG Present.
+#define SYSCTL_DC1_MPU          0x00000080  // MPU Present
+#define SYSCTL_DC1_HIB          0x00000040  // Hibernation Module Present
+#define SYSCTL_DC1_TEMP         0x00000020  // Temp Sensor Present
+#define SYSCTL_DC1_PLL          0x00000010  // PLL Present
+#define SYSCTL_DC1_WDT0         0x00000008  // Watchdog Timer 0 Present
+#define SYSCTL_DC1_SWO          0x00000004  // SWO Trace Port Present
+#define SYSCTL_DC1_SWD          0x00000002  // SWD Present
+#define SYSCTL_DC1_JTAG         0x00000001  // JTAG Present
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_DC2 register.
 //
 //*****************************************************************************
-#define SYSCTL_DC2_COMP1        0x02000000  // Analog Comparator 1 Present.
-#define SYSCTL_DC2_COMP0        0x01000000  // Analog Comparator 0 Present.
-#define SYSCTL_DC2_TIMER3       0x00080000  // Timer 3 Present.
-#define SYSCTL_DC2_TIMER2       0x00040000  // Timer 2 Present.
-#define SYSCTL_DC2_TIMER1       0x00020000  // Timer 1 Present.
-#define SYSCTL_DC2_TIMER0       0x00010000  // Timer 0 Present.
-#define SYSCTL_DC2_I2C1         0x00004000  // I2C Module 1 Present.
-#define SYSCTL_DC2_I2C0         0x00001000  // I2C Module 0 Present.
-#define SYSCTL_DC2_SSI1         0x00000020  // SSI1 Present.
-#define SYSCTL_DC2_SSI0         0x00000010  // SSI0 Present.
-#define SYSCTL_DC2_UART1        0x00000002  // UART1 Present.
-#define SYSCTL_DC2_UART0        0x00000001  // UART0 Present.
+#define SYSCTL_DC2_COMP1        0x02000000  // Analog Comparator 1 Present
+#define SYSCTL_DC2_COMP0        0x01000000  // Analog Comparator 0 Present
+#define SYSCTL_DC2_TIMER3       0x00080000  // Timer Module 3 Present
+#define SYSCTL_DC2_TIMER2       0x00040000  // Timer Module 2 Present
+#define SYSCTL_DC2_TIMER1       0x00020000  // Timer Module 1 Present
+#define SYSCTL_DC2_TIMER0       0x00010000  // Timer Module 0 Present
+#define SYSCTL_DC2_I2C1         0x00004000  // I2C Module 1 Present
+#define SYSCTL_DC2_I2C0         0x00001000  // I2C Module 0 Present
+#define SYSCTL_DC2_SSI1         0x00000020  // SSI Module 1 Present
+#define SYSCTL_DC2_SSI0         0x00000010  // SSI Module 0 Present
+#define SYSCTL_DC2_UART1        0x00000002  // UART Module 1 Present
+#define SYSCTL_DC2_UART0        0x00000001  // UART Module 0 Present
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_DC3 register.
 //
 //*****************************************************************************
-#define SYSCTL_DC3_32KHZ        0x80000000  // 32KHz Input Clock Available.
-#define SYSCTL_DC3_CCP5         0x20000000  // CCP5 Pin Present.
-#define SYSCTL_DC3_CCP4         0x10000000  // CCP4 Pin Present.
-#define SYSCTL_DC3_CCP3         0x08000000  // CCP3 Pin Present.
-#define SYSCTL_DC3_CCP2         0x04000000  // CCP2 Pin Present.
-#define SYSCTL_DC3_CCP1         0x02000000  // CCP1 Pin Present.
-#define SYSCTL_DC3_CCP0         0x01000000  // CCP0 Pin Present.
-#define SYSCTL_DC3_ADC7         0x00800000  // ADC7 Pin Present.
-#define SYSCTL_DC3_ADC6         0x00400000  // ADC6 Pin Present.
-#define SYSCTL_DC3_ADC5         0x00200000  // ADC5 Pin Present.
-#define SYSCTL_DC3_ADC4         0x00100000  // ADC4 Pin Present.
-#define SYSCTL_DC3_ADC3         0x00080000  // ADC3 Pin Present.
-#define SYSCTL_DC3_ADC2         0x00040000  // ADC2 Pin Present.
-#define SYSCTL_DC3_ADC1         0x00020000  // ADC1 Pin Present.
-#define SYSCTL_DC3_ADC0         0x00010000  // ADC0 Pin Present.
-#define SYSCTL_DC3_C1PLUS       0x00000400  // C1+ Pin Present.
-#define SYSCTL_DC3_C1MINUS      0x00000200  // C1- Pin Present.
-#define SYSCTL_DC3_C0O          0x00000100  // C0o Pin Present.
-#define SYSCTL_DC3_C0PLUS       0x00000080  // C0+ Pin Present.
-#define SYSCTL_DC3_C0MINUS      0x00000040  // C0- Pin Present.
+#define SYSCTL_DC3_32KHZ        0x80000000  // 32KHz Input Clock Available
+#define SYSCTL_DC3_CCP5         0x20000000  // CCP5 Pin Present
+#define SYSCTL_DC3_CCP4         0x10000000  // CCP4 Pin Present
+#define SYSCTL_DC3_CCP3         0x08000000  // CCP3 Pin Present
+#define SYSCTL_DC3_CCP2         0x04000000  // CCP2 Pin Present
+#define SYSCTL_DC3_CCP1         0x02000000  // CCP1 Pin Present
+#define SYSCTL_DC3_CCP0         0x01000000  // CCP0 Pin Present
+#define SYSCTL_DC3_ADC7         0x00800000  // ADC7 Pin Present
+#define SYSCTL_DC3_ADC6         0x00400000  // ADC6 Pin Present
+#define SYSCTL_DC3_ADC5         0x00200000  // ADC5 Pin Present
+#define SYSCTL_DC3_ADC4         0x00100000  // ADC4 Pin Present
+#define SYSCTL_DC3_ADC3         0x00080000  // ADC3 Pin Present
+#define SYSCTL_DC3_ADC2         0x00040000  // ADC2 Pin Present
+#define SYSCTL_DC3_ADC1         0x00020000  // ADC1 Pin Present
+#define SYSCTL_DC3_ADC0         0x00010000  // ADC0 Pin Present
+#define SYSCTL_DC3_C1PLUS       0x00000400  // C1+ Pin Present
+#define SYSCTL_DC3_C1MINUS      0x00000200  // C1- Pin Present
+#define SYSCTL_DC3_C0O          0x00000100  // C0o Pin Present
+#define SYSCTL_DC3_C0PLUS       0x00000080  // C0+ Pin Present
+#define SYSCTL_DC3_C0MINUS      0x00000040  // C0- Pin Present
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_DC4 register.
 //
 //*****************************************************************************
-#define SYSCTL_DC4_EPHY0        0x40000000  // Ethernet PHY0 Present.
-#define SYSCTL_DC4_EMAC0        0x10000000  // Ethernet MAC0 Present.
-#define SYSCTL_DC4_GPIOH        0x00000080  // GPIO Port H Present.
-#define SYSCTL_DC4_GPIOG        0x00000040  // GPIO Port G Present.
-#define SYSCTL_DC4_GPIOF        0x00000020  // GPIO Port F Present.
-#define SYSCTL_DC4_GPIOE        0x00000010  // GPIO Port E Present.
-#define SYSCTL_DC4_GPIOD        0x00000008  // GPIO Port D Present.
-#define SYSCTL_DC4_GPIOC        0x00000004  // GPIO Port C Present.
-#define SYSCTL_DC4_GPIOB        0x00000002  // GPIO Port B Present.
-#define SYSCTL_DC4_GPIOA        0x00000001  // GPIO Port A Present.
+#define SYSCTL_DC4_EPHY0        0x40000000  // Ethernet PHY Layer 0 Present
+#define SYSCTL_DC4_EMAC0        0x10000000  // Ethernet MAC Layer 0 Present
+#define SYSCTL_DC4_GPIOH        0x00000080  // GPIO Port H Present
+#define SYSCTL_DC4_GPIOG        0x00000040  // GPIO Port G Present
+#define SYSCTL_DC4_GPIOF        0x00000020  // GPIO Port F Present
+#define SYSCTL_DC4_GPIOE        0x00000010  // GPIO Port E Present
+#define SYSCTL_DC4_GPIOD        0x00000008  // GPIO Port D Present
+#define SYSCTL_DC4_GPIOC        0x00000004  // GPIO Port C Present
+#define SYSCTL_DC4_GPIOB        0x00000002  // GPIO Port B Present
+#define SYSCTL_DC4_GPIOA        0x00000001  // GPIO Port A Present
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_PBORCTL register.
 //
 //*****************************************************************************
-#define SYSCTL_PBORCTL_BORIOR   0x00000002  // BOR Interrupt or Reset.
+#define SYSCTL_PBORCTL_BORIOR   0x00000002  // BOR Interrupt or Reset
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_LDOPCTL register.
 //
 //*****************************************************************************
-#define SYSCTL_LDOPCTL_M        0x0000003F  // LDO Output Voltage.
+#define SYSCTL_LDOPCTL_M        0x0000003F  // LDO Output Voltage
 #define SYSCTL_LDOPCTL_2_50V    0x00000000  // 2.50
 #define SYSCTL_LDOPCTL_2_45V    0x00000001  // 2.45
 #define SYSCTL_LDOPCTL_2_40V    0x00000002  // 2.40
@@ -2720,112 +2695,110 @@
 // The following are defines for the bit fields in the SYSCTL_SRCR0 register.
 //
 //*****************************************************************************
-#define SYSCTL_SRCR0_ADC        0x00010000  // ADC0 Reset Control.
-#define SYSCTL_SRCR0_HIB        0x00000040  // HIB Reset Control.
-#define SYSCTL_SRCR0_WDT        0x00000008  // WDT Reset Control.
+#define SYSCTL_SRCR0_ADC        0x00010000  // ADC0 Reset Control
+#define SYSCTL_SRCR0_HIB        0x00000040  // HIB Reset Control
+#define SYSCTL_SRCR0_WDT        0x00000008  // WDT Reset Control
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_SRCR1 register.
 //
 //*****************************************************************************
-#define SYSCTL_SRCR1_COMP1      0x02000000  // Analog Comp 1 Reset Control.
-#define SYSCTL_SRCR1_COMP0      0x01000000  // Analog Comp 0 Reset Control.
-#define SYSCTL_SRCR1_TIMER3     0x00080000  // Timer 3 Reset Control.
-#define SYSCTL_SRCR1_TIMER2     0x00040000  // Timer 2 Reset Control.
-#define SYSCTL_SRCR1_TIMER1     0x00020000  // Timer 1 Reset Control.
-#define SYSCTL_SRCR1_TIMER0     0x00010000  // Timer 0 Reset Control.
-#define SYSCTL_SRCR1_I2C1       0x00004000  // I2C1 Reset Control.
-#define SYSCTL_SRCR1_I2C0       0x00001000  // I2C0 Reset Control.
-#define SYSCTL_SRCR1_SSI1       0x00000020  // SSI1 Reset Control.
-#define SYSCTL_SRCR1_SSI0       0x00000010  // SSI0 Reset Control.
-#define SYSCTL_SRCR1_UART1      0x00000002  // UART1 Reset Control.
-#define SYSCTL_SRCR1_UART0      0x00000001  // UART0 Reset Control.
+#define SYSCTL_SRCR1_COMP1      0x02000000  // Analog Comp 1 Reset Control
+#define SYSCTL_SRCR1_COMP0      0x01000000  // Analog Comp 0 Reset Control
+#define SYSCTL_SRCR1_TIMER3     0x00080000  // Timer 3 Reset Control
+#define SYSCTL_SRCR1_TIMER2     0x00040000  // Timer 2 Reset Control
+#define SYSCTL_SRCR1_TIMER1     0x00020000  // Timer 1 Reset Control
+#define SYSCTL_SRCR1_TIMER0     0x00010000  // Timer 0 Reset Control
+#define SYSCTL_SRCR1_I2C1       0x00004000  // I2C1 Reset Control
+#define SYSCTL_SRCR1_I2C0       0x00001000  // I2C0 Reset Control
+#define SYSCTL_SRCR1_SSI1       0x00000020  // SSI1 Reset Control
+#define SYSCTL_SRCR1_SSI0       0x00000010  // SSI0 Reset Control
+#define SYSCTL_SRCR1_UART1      0x00000002  // UART1 Reset Control
+#define SYSCTL_SRCR1_UART0      0x00000001  // UART0 Reset Control
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_SRCR2 register.
 //
 //*****************************************************************************
-#define SYSCTL_SRCR2_EPHY0      0x40000000  // PHY0 Reset Control.
-#define SYSCTL_SRCR2_EMAC0      0x10000000  // MAC0 Reset Control.
-#define SYSCTL_SRCR2_GPIOH      0x00000080  // Port H Reset Control.
-#define SYSCTL_SRCR2_GPIOG      0x00000040  // Port G Reset Control.
-#define SYSCTL_SRCR2_GPIOF      0x00000020  // Port F Reset Control.
-#define SYSCTL_SRCR2_GPIOE      0x00000010  // Port E Reset Control.
-#define SYSCTL_SRCR2_GPIOD      0x00000008  // Port D Reset Control.
-#define SYSCTL_SRCR2_GPIOC      0x00000004  // Port C Reset Control.
-#define SYSCTL_SRCR2_GPIOB      0x00000002  // Port B Reset Control.
-#define SYSCTL_SRCR2_GPIOA      0x00000001  // Port A Reset Control.
+#define SYSCTL_SRCR2_EPHY0      0x40000000  // PHY0 Reset Control
+#define SYSCTL_SRCR2_EMAC0      0x10000000  // MAC0 Reset Control
+#define SYSCTL_SRCR2_GPIOH      0x00000080  // Port H Reset Control
+#define SYSCTL_SRCR2_GPIOG      0x00000040  // Port G Reset Control
+#define SYSCTL_SRCR2_GPIOF      0x00000020  // Port F Reset Control
+#define SYSCTL_SRCR2_GPIOE      0x00000010  // Port E Reset Control
+#define SYSCTL_SRCR2_GPIOD      0x00000008  // Port D Reset Control
+#define SYSCTL_SRCR2_GPIOC      0x00000004  // Port C Reset Control
+#define SYSCTL_SRCR2_GPIOB      0x00000002  // Port B Reset Control
+#define SYSCTL_SRCR2_GPIOA      0x00000001  // Port A Reset Control
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_RIS register.
 //
 //*****************************************************************************
-#define SYSCTL_RIS_PLLLRIS      0x00000040  // PLL Lock Raw Interrupt Status.
+#define SYSCTL_RIS_PLLLRIS      0x00000040  // PLL Lock Raw Interrupt Status
 #define SYSCTL_RIS_BORRIS       0x00000002  // Brown-Out Reset Raw Interrupt
-                                            // Status.
+                                            // Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_IMC register.
 //
 //*****************************************************************************
-#define SYSCTL_IMC_PLLLIM       0x00000040  // PLL Lock Interrupt Mask.
-#define SYSCTL_IMC_BORIM        0x00000002  // Brown-Out Reset Interrupt Mask.
+#define SYSCTL_IMC_PLLLIM       0x00000040  // PLL Lock Interrupt Mask
+#define SYSCTL_IMC_BORIM        0x00000002  // Brown-Out Reset Interrupt Mask
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_MISC register.
 //
 //*****************************************************************************
-#define SYSCTL_MISC_PLLLMIS     0x00000040  // PLL Lock Masked Interrupt
-                                            // Status.
-#define SYSCTL_MISC_BORMIS      0x00000002  // BOR Masked Interrupt Status.
+#define SYSCTL_MISC_PLLLMIS     0x00000040  // PLL Lock Masked Interrupt Status
+#define SYSCTL_MISC_BORMIS      0x00000002  // BOR Masked Interrupt Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_RESC register.
 //
 //*****************************************************************************
-#define SYSCTL_RESC_LDO         0x00000020  // LDO Reset.
-#define SYSCTL_RESC_SW          0x00000010  // Software Reset.
-#define SYSCTL_RESC_WDT         0x00000008  // Watchdog Timer Reset.
-#define SYSCTL_RESC_BOR         0x00000004  // Brown-Out Reset.
-#define SYSCTL_RESC_POR         0x00000002  // Power-On Reset.
-#define SYSCTL_RESC_EXT         0x00000001  // External Reset.
+#define SYSCTL_RESC_SW          0x00000010  // Software Reset
+#define SYSCTL_RESC_WDT         0x00000008  // Watchdog Timer Reset
+#define SYSCTL_RESC_BOR         0x00000004  // Brown-Out Reset
+#define SYSCTL_RESC_POR         0x00000002  // Power-On Reset
+#define SYSCTL_RESC_EXT         0x00000001  // External Reset
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_RCC register.
 //
 //*****************************************************************************
-#define SYSCTL_RCC_ACG          0x08000000  // Auto Clock Gating.
-#define SYSCTL_RCC_SYSDIV_M     0x07800000  // System Clock Divisor.
-#define SYSCTL_RCC_SYSDIV_2     0x00800000  // /2
-#define SYSCTL_RCC_SYSDIV_3     0x01000000  // /3
-#define SYSCTL_RCC_SYSDIV_4     0x01800000  // /4
-#define SYSCTL_RCC_SYSDIV_5     0x02000000  // /5
-#define SYSCTL_RCC_SYSDIV_6     0x02800000  // /6
-#define SYSCTL_RCC_SYSDIV_7     0x03000000  // /7
-#define SYSCTL_RCC_SYSDIV_8     0x03800000  // /8
-#define SYSCTL_RCC_SYSDIV_9     0x04000000  // /9
-#define SYSCTL_RCC_SYSDIV_10    0x04800000  // /10
-#define SYSCTL_RCC_SYSDIV_11    0x05000000  // /11
-#define SYSCTL_RCC_SYSDIV_12    0x05800000  // /12
-#define SYSCTL_RCC_SYSDIV_13    0x06000000  // /13
-#define SYSCTL_RCC_SYSDIV_14    0x06800000  // /14
-#define SYSCTL_RCC_SYSDIV_15    0x07000000  // /15
-#define SYSCTL_RCC_SYSDIV_16    0x07800000  // /16
-#define SYSCTL_RCC_USESYSDIV    0x00400000  // Enable System Clock Divider.
-#define SYSCTL_RCC_PWRDN        0x00002000  // PLL Power Down.
-#define SYSCTL_RCC_BYPASS       0x00000800  // PLL Bypass.
-#define SYSCTL_RCC_XTAL_M       0x000003C0  // Crystal Value.
-#define SYSCTL_RCC_XTAL_1MHZ    0x00000000  // 1.000
-#define SYSCTL_RCC_XTAL_1_84MHZ 0x00000040  // 1.8432
-#define SYSCTL_RCC_XTAL_2MHZ    0x00000080  // 2.000
-#define SYSCTL_RCC_XTAL_2_45MHZ 0x000000C0  // 2.4576
+#define SYSCTL_RCC_ACG          0x08000000  // Auto Clock Gating
+#define SYSCTL_RCC_SYSDIV_M     0x07800000  // System Clock Divisor
+#define SYSCTL_RCC_SYSDIV_2     0x00800000  // System clock /2
+#define SYSCTL_RCC_SYSDIV_3     0x01000000  // System clock /3
+#define SYSCTL_RCC_SYSDIV_4     0x01800000  // System clock /4
+#define SYSCTL_RCC_SYSDIV_5     0x02000000  // System clock /5
+#define SYSCTL_RCC_SYSDIV_6     0x02800000  // System clock /6
+#define SYSCTL_RCC_SYSDIV_7     0x03000000  // System clock /7
+#define SYSCTL_RCC_SYSDIV_8     0x03800000  // System clock /8
+#define SYSCTL_RCC_SYSDIV_9     0x04000000  // System clock /9
+#define SYSCTL_RCC_SYSDIV_10    0x04800000  // System clock /10
+#define SYSCTL_RCC_SYSDIV_11    0x05000000  // System clock /11
+#define SYSCTL_RCC_SYSDIV_12    0x05800000  // System clock /12
+#define SYSCTL_RCC_SYSDIV_13    0x06000000  // System clock /13
+#define SYSCTL_RCC_SYSDIV_14    0x06800000  // System clock /14
+#define SYSCTL_RCC_SYSDIV_15    0x07000000  // System clock /15
+#define SYSCTL_RCC_SYSDIV_16    0x07800000  // System clock /16
+#define SYSCTL_RCC_USESYSDIV    0x00400000  // Enable System Clock Divider
+#define SYSCTL_RCC_PWRDN        0x00002000  // PLL Power Down
+#define SYSCTL_RCC_BYPASS       0x00000800  // PLL Bypass
+#define SYSCTL_RCC_XTAL_M       0x000003C0  // Crystal Value
+#define SYSCTL_RCC_XTAL_1MHZ    0x00000000  // 1 MHz
+#define SYSCTL_RCC_XTAL_1_84MHZ 0x00000040  // 1.8432 MHz
+#define SYSCTL_RCC_XTAL_2MHZ    0x00000080  // 2 MHz
+#define SYSCTL_RCC_XTAL_2_45MHZ 0x000000C0  // 2.4576 MHz
 #define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100  // 3.579545 MHz
 #define SYSCTL_RCC_XTAL_3_68MHZ 0x00000140  // 3.6864 MHz
 #define SYSCTL_RCC_XTAL_4MHZ    0x00000180  // 4 MHz
@@ -2833,26 +2806,27 @@
 #define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200  // 4.9152 MHz
 #define SYSCTL_RCC_XTAL_5MHZ    0x00000240  // 5 MHz
 #define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280  // 5.12 MHz
-#define SYSCTL_RCC_XTAL_6MHZ    0x000002C0  // 6 MHz (reset value)
+#define SYSCTL_RCC_XTAL_6MHZ    0x000002C0  // 6 MHz
 #define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300  // 6.144 MHz
 #define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340  // 7.3728 MHz
 #define SYSCTL_RCC_XTAL_8MHZ    0x00000380  // 8 MHz
 #define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0  // 8.192 MHz
-#define SYSCTL_RCC_OSCSRC_M     0x00000030  // Oscillator Source.
+#define SYSCTL_RCC_OSCSRC_M     0x00000030  // Oscillator Source
 #define SYSCTL_RCC_OSCSRC_MAIN  0x00000000  // MOSC
 #define SYSCTL_RCC_OSCSRC_INT   0x00000010  // IOSC
 #define SYSCTL_RCC_OSCSRC_INT4  0x00000020  // IOSC/4
 #define SYSCTL_RCC_OSCSRC_30    0x00000030  // 30 kHz
-#define SYSCTL_RCC_IOSCDIS      0x00000002  // Internal Oscillator Disable.
-#define SYSCTL_RCC_MOSCDIS      0x00000001  // Main Oscillator Disable.
+#define SYSCTL_RCC_IOSCDIS      0x00000002  // Internal Oscillator Disable
+#define SYSCTL_RCC_MOSCDIS      0x00000001  // Main Oscillator Disable
+#define SYSCTL_RCC_SYSDIV_S     23
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_PLLCFG register.
 //
 //*****************************************************************************
-#define SYSCTL_PLLCFG_F_M       0x00003FE0  // PLL F Value.
-#define SYSCTL_PLLCFG_R_M       0x0000001F  // PLL R Value.
+#define SYSCTL_PLLCFG_F_M       0x00003FE0  // PLL F Value
+#define SYSCTL_PLLCFG_R_M       0x0000001F  // PLL R Value
 #define SYSCTL_PLLCFG_F_S       5
 #define SYSCTL_PLLCFG_R_S       0
 
@@ -2861,8 +2835,8 @@
 // The following are defines for the bit fields in the SYSCTL_RCC2 register.
 //
 //*****************************************************************************
-#define SYSCTL_RCC2_USERCC2     0x80000000  // Use RCC2.
-#define SYSCTL_RCC2_SYSDIV2_M   0x1F800000  // System Clock Divisor.
+#define SYSCTL_RCC2_USERCC2     0x80000000  // Use RCC2
+#define SYSCTL_RCC2_SYSDIV2_M   0x1F800000  // System Clock Divisor 2
 #define SYSCTL_RCC2_SYSDIV2_2   0x00800000  // System clock /2
 #define SYSCTL_RCC2_SYSDIV2_3   0x01000000  // System clock /3
 #define SYSCTL_RCC2_SYSDIV2_4   0x01800000  // System clock /4
@@ -2926,14 +2900,14 @@
 #define SYSCTL_RCC2_SYSDIV2_62  0x1E800000  // System clock /62
 #define SYSCTL_RCC2_SYSDIV2_63  0x1F000000  // System clock /63
 #define SYSCTL_RCC2_SYSDIV2_64  0x1F800000  // System clock /64
-#define SYSCTL_RCC2_PWRDN2      0x00002000  // Power-Down PLL.
-#define SYSCTL_RCC2_BYPASS2     0x00000800  // Bypass PLL.
-#define SYSCTL_RCC2_OSCSRC2_M   0x00000070  // Oscillator Source.
+#define SYSCTL_RCC2_PWRDN2      0x00002000  // Power-Down PLL 2
+#define SYSCTL_RCC2_BYPASS2     0x00000800  // PLL Bypass 2
+#define SYSCTL_RCC2_OSCSRC2_M   0x00000070  // Oscillator Source 2
 #define SYSCTL_RCC2_OSCSRC2_MO  0x00000000  // MOSC
-#define SYSCTL_RCC2_OSCSRC2_IO  0x00000010  // IOSC
-#define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020  // IOSC/4
+#define SYSCTL_RCC2_OSCSRC2_IO  0x00000010  // PIOSC
+#define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020  // PIOSC/4
 #define SYSCTL_RCC2_OSCSRC2_30  0x00000030  // 30 kHz
-#define SYSCTL_RCC2_OSCSRC2_32  0x00000070  // 32 kHz
+#define SYSCTL_RCC2_OSCSRC2_32  0x00000070  // 32.768 kHz
 #define SYSCTL_RCC2_SYSDIV2_S   23
 
 //*****************************************************************************
@@ -2941,147 +2915,137 @@
 // The following are defines for the bit fields in the SYSCTL_RCGC0 register.
 //
 //*****************************************************************************
-#define SYSCTL_RCGC0_ADC        0x00010000  // ADC0 Clock Gating Control.
-#define SYSCTL_RCGC0_ADCSPD_M   0x00000300  // ADC Sample Speed.
+#define SYSCTL_RCGC0_ADC        0x00010000  // ADC0 Clock Gating Control
+#define SYSCTL_RCGC0_ADCSPD_M   0x00000300  // ADC Sample Speed
 #define SYSCTL_RCGC0_ADCSPD125K 0x00000000  // 125K samples/second
 #define SYSCTL_RCGC0_ADCSPD250K 0x00000100  // 250K samples/second
 #define SYSCTL_RCGC0_ADCSPD500K 0x00000200  // 500K samples/second
-#define SYSCTL_RCGC0_HIB        0x00000040  // HIB Clock Gating Control.
-#define SYSCTL_RCGC0_WDT        0x00000008  // WDT Clock Gating Control.
+#define SYSCTL_RCGC0_HIB        0x00000040  // HIB Clock Gating Control
+#define SYSCTL_RCGC0_WDT        0x00000008  // WDT Clock Gating Control
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_RCGC1 register.
 //
 //*****************************************************************************
-#define SYSCTL_RCGC1_COMP1      0x02000000  // Analog Comparator 1 Clock
-                                            // Gating.
-#define SYSCTL_RCGC1_COMP0      0x01000000  // Analog Comparator 0 Clock
-                                            // Gating.
-#define SYSCTL_RCGC1_TIMER3     0x00080000  // Timer 3 Clock Gating Control.
-#define SYSCTL_RCGC1_TIMER2     0x00040000  // Timer 2 Clock Gating Control.
-#define SYSCTL_RCGC1_TIMER1     0x00020000  // Timer 1 Clock Gating Control.
-#define SYSCTL_RCGC1_TIMER0     0x00010000  // Timer 0 Clock Gating Control.
-#define SYSCTL_RCGC1_I2C1       0x00004000  // I2C1 Clock Gating Control.
-#define SYSCTL_RCGC1_I2C0       0x00001000  // I2C0 Clock Gating Control.
-#define SYSCTL_RCGC1_SSI1       0x00000020  // SSI1 Clock Gating Control.
-#define SYSCTL_RCGC1_SSI0       0x00000010  // SSI0 Clock Gating Control.
-#define SYSCTL_RCGC1_UART1      0x00000002  // UART1 Clock Gating Control.
-#define SYSCTL_RCGC1_UART0      0x00000001  // UART0 Clock Gating Control.
+#define SYSCTL_RCGC1_COMP1      0x02000000  // Analog Comparator 1 Clock Gating
+#define SYSCTL_RCGC1_COMP0      0x01000000  // Analog Comparator 0 Clock Gating
+#define SYSCTL_RCGC1_TIMER3     0x00080000  // Timer 3 Clock Gating Control
+#define SYSCTL_RCGC1_TIMER2     0x00040000  // Timer 2 Clock Gating Control
+#define SYSCTL_RCGC1_TIMER1     0x00020000  // Timer 1 Clock Gating Control
+#define SYSCTL_RCGC1_TIMER0     0x00010000  // Timer 0 Clock Gating Control
+#define SYSCTL_RCGC1_I2C1       0x00004000  // I2C1 Clock Gating Control
+#define SYSCTL_RCGC1_I2C0       0x00001000  // I2C0 Clock Gating Control
+#define SYSCTL_RCGC1_SSI1       0x00000020  // SSI1 Clock Gating Control
+#define SYSCTL_RCGC1_SSI0       0x00000010  // SSI0 Clock Gating Control
+#define SYSCTL_RCGC1_UART1      0x00000002  // UART1 Clock Gating Control
+#define SYSCTL_RCGC1_UART0      0x00000001  // UART0 Clock Gating Control
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_RCGC2 register.
 //
 //*****************************************************************************
-#define SYSCTL_RCGC2_EPHY0      0x40000000  // PHY0 Clock Gating Control.
-#define SYSCTL_RCGC2_EMAC0      0x10000000  // MAC0 Clock Gating Control.
-#define SYSCTL_RCGC2_GPIOH      0x00000080  // Port H Clock Gating Control.
-#define SYSCTL_RCGC2_GPIOG      0x00000040  // Port G Clock Gating Control.
-#define SYSCTL_RCGC2_GPIOF      0x00000020  // Port F Clock Gating Control.
-#define SYSCTL_RCGC2_GPIOE      0x00000010  // Port E Clock Gating Control.
-#define SYSCTL_RCGC2_GPIOD      0x00000008  // Port D Clock Gating Control.
-#define SYSCTL_RCGC2_GPIOC      0x00000004  // Port C Clock Gating Control.
-#define SYSCTL_RCGC2_GPIOB      0x00000002  // Port B Clock Gating Control.
-#define SYSCTL_RCGC2_GPIOA      0x00000001  // Port A Clock Gating Control.
+#define SYSCTL_RCGC2_EPHY0      0x40000000  // PHY0 Clock Gating Control
+#define SYSCTL_RCGC2_EMAC0      0x10000000  // MAC0 Clock Gating Control
+#define SYSCTL_RCGC2_GPIOH      0x00000080  // Port H Clock Gating Control
+#define SYSCTL_RCGC2_GPIOG      0x00000040  // Port G Clock Gating Control
+#define SYSCTL_RCGC2_GPIOF      0x00000020  // Port F Clock Gating Control
+#define SYSCTL_RCGC2_GPIOE      0x00000010  // Port E Clock Gating Control
+#define SYSCTL_RCGC2_GPIOD      0x00000008  // Port D Clock Gating Control
+#define SYSCTL_RCGC2_GPIOC      0x00000004  // Port C Clock Gating Control
+#define SYSCTL_RCGC2_GPIOB      0x00000002  // Port B Clock Gating Control
+#define SYSCTL_RCGC2_GPIOA      0x00000001  // Port A Clock Gating Control
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_SCGC0 register.
 //
 //*****************************************************************************
-#define SYSCTL_SCGC0_ADC        0x00010000  // ADC0 Clock Gating Control.
-#define SYSCTL_SCGC0_ADCSPD_M   0x00000300  // ADC Sample Speed.
+#define SYSCTL_SCGC0_ADC        0x00010000  // ADC0 Clock Gating Control
+#define SYSCTL_SCGC0_ADCSPD_M   0x00000300  // ADC Sample Speed
 #define SYSCTL_SCGC0_ADCSPD125K 0x00000000  // 125K samples/second
 #define SYSCTL_SCGC0_ADCSPD250K 0x00000100  // 250K samples/second
 #define SYSCTL_SCGC0_ADCSPD500K 0x00000200  // 500K samples/second
-#define SYSCTL_SCGC0_HIB        0x00000040  // HIB Clock Gating Control.
-#define SYSCTL_SCGC0_WDT        0x00000008  // WDT Clock Gating Control.
+#define SYSCTL_SCGC0_HIB        0x00000040  // HIB Clock Gating Control
+#define SYSCTL_SCGC0_WDT        0x00000008  // WDT Clock Gating Control
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_SCGC1 register.
 //
 //*****************************************************************************
-#define SYSCTL_SCGC1_COMP1      0x02000000  // Analog Comparator 1 Clock
-                                            // Gating.
-#define SYSCTL_SCGC1_COMP0      0x01000000  // Analog Comparator 0 Clock
-                                            // Gating.
-#define SYSCTL_SCGC1_TIMER3     0x00080000  // Timer 3 Clock Gating Control.
-#define SYSCTL_SCGC1_TIMER2     0x00040000  // Timer 2 Clock Gating Control.
-#define SYSCTL_SCGC1_TIMER1     0x00020000  // Timer 1 Clock Gating Control.
-#define SYSCTL_SCGC1_TIMER0     0x00010000  // Timer 0 Clock Gating Control.
-#define SYSCTL_SCGC1_I2C1       0x00004000  // I2C1 Clock Gating Control.
-#define SYSCTL_SCGC1_I2C0       0x00001000  // I2C0 Clock Gating Control.
-#define SYSCTL_SCGC1_SSI1       0x00000020  // SSI1 Clock Gating Control.
-#define SYSCTL_SCGC1_SSI0       0x00000010  // SSI0 Clock Gating Control.
-#define SYSCTL_SCGC1_UART1      0x00000002  // UART1 Clock Gating Control.
-#define SYSCTL_SCGC1_UART0      0x00000001  // UART0 Clock Gating Control.
+#define SYSCTL_SCGC1_COMP1      0x02000000  // Analog Comparator 1 Clock Gating
+#define SYSCTL_SCGC1_COMP0      0x01000000  // Analog Comparator 0 Clock Gating
+#define SYSCTL_SCGC1_TIMER3     0x00080000  // Timer 3 Clock Gating Control
+#define SYSCTL_SCGC1_TIMER2     0x00040000  // Timer 2 Clock Gating Control
+#define SYSCTL_SCGC1_TIMER1     0x00020000  // Timer 1 Clock Gating Control
+#define SYSCTL_SCGC1_TIMER0     0x00010000  // Timer 0 Clock Gating Control
+#define SYSCTL_SCGC1_I2C1       0x00004000  // I2C1 Clock Gating Control
+#define SYSCTL_SCGC1_I2C0       0x00001000  // I2C0 Clock Gating Control
+#define SYSCTL_SCGC1_SSI1       0x00000020  // SSI1 Clock Gating Control
+#define SYSCTL_SCGC1_SSI0       0x00000010  // SSI0 Clock Gating Control
+#define SYSCTL_SCGC1_UART1      0x00000002  // UART1 Clock Gating Control
+#define SYSCTL_SCGC1_UART0      0x00000001  // UART0 Clock Gating Control
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_SCGC2 register.
 //
 //*****************************************************************************
-#define SYSCTL_SCGC2_EPHY0      0x40000000  // PHY0 Clock Gating Control.
-#define SYSCTL_SCGC2_EMAC0      0x10000000  // MAC0 Clock Gating Control.
-#define SYSCTL_SCGC2_GPIOH      0x00000080  // Port H Clock Gating Control.
-#define SYSCTL_SCGC2_GPIOG      0x00000040  // Port G Clock Gating Control.
-#define SYSCTL_SCGC2_GPIOF      0x00000020  // Port F Clock Gating Control.
-#define SYSCTL_SCGC2_GPIOE      0x00000010  // Port E Clock Gating Control.
-#define SYSCTL_SCGC2_GPIOD      0x00000008  // Port D Clock Gating Control.
-#define SYSCTL_SCGC2_GPIOC      0x00000004  // Port C Clock Gating Control.
-#define SYSCTL_SCGC2_GPIOB      0x00000002  // Port B Clock Gating Control.
-#define SYSCTL_SCGC2_GPIOA      0x00000001  // Port A Clock Gating Control.
+#define SYSCTL_SCGC2_EPHY0      0x40000000  // PHY0 Clock Gating Control
+#define SYSCTL_SCGC2_EMAC0      0x10000000  // MAC0 Clock Gating Control
+#define SYSCTL_SCGC2_GPIOH      0x00000080  // Port H Clock Gating Control
+#define SYSCTL_SCGC2_GPIOG      0x00000040  // Port G Clock Gating Control
+#define SYSCTL_SCGC2_GPIOF      0x00000020  // Port F Clock Gating Control
+#define SYSCTL_SCGC2_GPIOE      0x00000010  // Port E Clock Gating Control
+#define SYSCTL_SCGC2_GPIOD      0x00000008  // Port D Clock Gating Control
+#define SYSCTL_SCGC2_GPIOC      0x00000004  // Port C Clock Gating Control
+#define SYSCTL_SCGC2_GPIOB      0x00000002  // Port B Clock Gating Control
+#define SYSCTL_SCGC2_GPIOA      0x00000001  // Port A Clock Gating Control
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_DCGC0 register.
 //
 //*****************************************************************************
-#define SYSCTL_DCGC0_ADC        0x00010000  // ADC0 Clock Gating Control.
-#define SYSCTL_DCGC0_ADCSPD_M   0x00000300  // ADC Sample Speed.
-#define SYSCTL_DCGC0_ADCSPD125K 0x00000000  // 125K samples/second
-#define SYSCTL_DCGC0_ADCSPD250K 0x00000100  // 250K samples/second
-#define SYSCTL_DCGC0_ADCSPD500K 0x00000200  // 500K samples/second
-#define SYSCTL_DCGC0_HIB        0x00000040  // HIB Clock Gating Control.
-#define SYSCTL_DCGC0_WDT        0x00000008  // WDT Clock Gating Control.
+#define SYSCTL_DCGC0_ADC        0x00010000  // ADC0 Clock Gating Control
+#define SYSCTL_DCGC0_HIB        0x00000040  // HIB Clock Gating Control
+#define SYSCTL_DCGC0_WDT        0x00000008  // WDT Clock Gating Control
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_DCGC1 register.
 //
 //*****************************************************************************
-#define SYSCTL_DCGC1_COMP1      0x02000000  // Analog Comparator 1 Clock
-                                            // Gating.
-#define SYSCTL_DCGC1_COMP0      0x01000000  // Analog Comparator 0 Clock
-                                            // Gating.
-#define SYSCTL_DCGC1_TIMER3     0x00080000  // Timer 3 Clock Gating Control.
-#define SYSCTL_DCGC1_TIMER2     0x00040000  // Timer 2 Clock Gating Control.
-#define SYSCTL_DCGC1_TIMER1     0x00020000  // Timer 1 Clock Gating Control.
-#define SYSCTL_DCGC1_TIMER0     0x00010000  // Timer 0 Clock Gating Control.
-#define SYSCTL_DCGC1_I2C1       0x00004000  // I2C1 Clock Gating Control.
-#define SYSCTL_DCGC1_I2C0       0x00001000  // I2C0 Clock Gating Control.
-#define SYSCTL_DCGC1_SSI1       0x00000020  // SSI1 Clock Gating Control.
-#define SYSCTL_DCGC1_SSI0       0x00000010  // SSI0 Clock Gating Control.
-#define SYSCTL_DCGC1_UART1      0x00000002  // UART1 Clock Gating Control.
-#define SYSCTL_DCGC1_UART0      0x00000001  // UART0 Clock Gating Control.
+#define SYSCTL_DCGC1_COMP1      0x02000000  // Analog Comparator 1 Clock Gating
+#define SYSCTL_DCGC1_COMP0      0x01000000  // Analog Comparator 0 Clock Gating
+#define SYSCTL_DCGC1_TIMER3     0x00080000  // Timer 3 Clock Gating Control
+#define SYSCTL_DCGC1_TIMER2     0x00040000  // Timer 2 Clock Gating Control
+#define SYSCTL_DCGC1_TIMER1     0x00020000  // Timer 1 Clock Gating Control
+#define SYSCTL_DCGC1_TIMER0     0x00010000  // Timer 0 Clock Gating Control
+#define SYSCTL_DCGC1_I2C1       0x00004000  // I2C1 Clock Gating Control
+#define SYSCTL_DCGC1_I2C0       0x00001000  // I2C0 Clock Gating Control
+#define SYSCTL_DCGC1_SSI1       0x00000020  // SSI1 Clock Gating Control
+#define SYSCTL_DCGC1_SSI0       0x00000010  // SSI0 Clock Gating Control
+#define SYSCTL_DCGC1_UART1      0x00000002  // UART1 Clock Gating Control
+#define SYSCTL_DCGC1_UART0      0x00000001  // UART0 Clock Gating Control
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_DCGC2 register.
 //
 //*****************************************************************************
-#define SYSCTL_DCGC2_EPHY0      0x40000000  // PHY0 Clock Gating Control.
-#define SYSCTL_DCGC2_EMAC0      0x10000000  // MAC0 Clock Gating Control.
-#define SYSCTL_DCGC2_GPIOH      0x00000080  // Port H Clock Gating Control.
-#define SYSCTL_DCGC2_GPIOG      0x00000040  // Port G Clock Gating Control.
-#define SYSCTL_DCGC2_GPIOF      0x00000020  // Port F Clock Gating Control.
-#define SYSCTL_DCGC2_GPIOE      0x00000010  // Port E Clock Gating Control.
-#define SYSCTL_DCGC2_GPIOD      0x00000008  // Port D Clock Gating Control.
-#define SYSCTL_DCGC2_GPIOC      0x00000004  // Port C Clock Gating Control.
-#define SYSCTL_DCGC2_GPIOB      0x00000002  // Port B Clock Gating Control.
-#define SYSCTL_DCGC2_GPIOA      0x00000001  // Port A Clock Gating Control.
+#define SYSCTL_DCGC2_EPHY0      0x40000000  // PHY0 Clock Gating Control
+#define SYSCTL_DCGC2_EMAC0      0x10000000  // MAC0 Clock Gating Control
+#define SYSCTL_DCGC2_GPIOH      0x00000080  // Port H Clock Gating Control
+#define SYSCTL_DCGC2_GPIOG      0x00000040  // Port G Clock Gating Control
+#define SYSCTL_DCGC2_GPIOF      0x00000020  // Port F Clock Gating Control
+#define SYSCTL_DCGC2_GPIOE      0x00000010  // Port E Clock Gating Control
+#define SYSCTL_DCGC2_GPIOD      0x00000008  // Port D Clock Gating Control
+#define SYSCTL_DCGC2_GPIOC      0x00000004  // Port C Clock Gating Control
+#define SYSCTL_DCGC2_GPIOB      0x00000002  // Port B Clock Gating Control
+#define SYSCTL_DCGC2_GPIOA      0x00000001  // Port A Clock Gating Control
 
 //*****************************************************************************
 //
@@ -3089,12 +3053,76 @@
 // register.
 //
 //*****************************************************************************
-#define SYSCTL_DSLPCLKCFG_D_M   0x1F800000  // Divider Field Override.
-#define SYSCTL_DSLPCLKCFG_O_M   0x00000070  // Clock Source.
+#define SYSCTL_DSLPCLKCFG_D_M   0x1F800000  // Divider Field Override
+#define SYSCTL_DSLPCLKCFG_D_1   0x00000000  // System clock /1
+#define SYSCTL_DSLPCLKCFG_D_2   0x00800000  // System clock /2
+#define SYSCTL_DSLPCLKCFG_D_3   0x01000000  // System clock /3
+#define SYSCTL_DSLPCLKCFG_D_4   0x01800000  // System clock /4
+#define SYSCTL_DSLPCLKCFG_D_5   0x02000000  // System clock /5
+#define SYSCTL_DSLPCLKCFG_D_6   0x02800000  // System clock /6
+#define SYSCTL_DSLPCLKCFG_D_7   0x03000000  // System clock /7
+#define SYSCTL_DSLPCLKCFG_D_8   0x03800000  // System clock /8
+#define SYSCTL_DSLPCLKCFG_D_9   0x04000000  // System clock /9
+#define SYSCTL_DSLPCLKCFG_D_10  0x04800000  // System clock /10
+#define SYSCTL_DSLPCLKCFG_D_11  0x05000000  // System clock /11
+#define SYSCTL_DSLPCLKCFG_D_12  0x05800000  // System clock /12
+#define SYSCTL_DSLPCLKCFG_D_13  0x06000000  // System clock /13
+#define SYSCTL_DSLPCLKCFG_D_14  0x06800000  // System clock /14
+#define SYSCTL_DSLPCLKCFG_D_15  0x07000000  // System clock /15
+#define SYSCTL_DSLPCLKCFG_D_16  0x07800000  // System clock /16
+#define SYSCTL_DSLPCLKCFG_D_17  0x08000000  // System clock /17
+#define SYSCTL_DSLPCLKCFG_D_18  0x08800000  // System clock /18
+#define SYSCTL_DSLPCLKCFG_D_19  0x09000000  // System clock /19
+#define SYSCTL_DSLPCLKCFG_D_20  0x09800000  // System clock /20
+#define SYSCTL_DSLPCLKCFG_D_21  0x0A000000  // System clock /21
+#define SYSCTL_DSLPCLKCFG_D_22  0x0A800000  // System clock /22
+#define SYSCTL_DSLPCLKCFG_D_23  0x0B000000  // System clock /23
+#define SYSCTL_DSLPCLKCFG_D_24  0x0B800000  // System clock /24
+#define SYSCTL_DSLPCLKCFG_D_25  0x0C000000  // System clock /25
+#define SYSCTL_DSLPCLKCFG_D_26  0x0C800000  // System clock /26
+#define SYSCTL_DSLPCLKCFG_D_27  0x0D000000  // System clock /27
+#define SYSCTL_DSLPCLKCFG_D_28  0x0D800000  // System clock /28
+#define SYSCTL_DSLPCLKCFG_D_29  0x0E000000  // System clock /29
+#define SYSCTL_DSLPCLKCFG_D_30  0x0E800000  // System clock /30
+#define SYSCTL_DSLPCLKCFG_D_31  0x0F000000  // System clock /31
+#define SYSCTL_DSLPCLKCFG_D_32  0x0F800000  // System clock /32
+#define SYSCTL_DSLPCLKCFG_D_33  0x10000000  // System clock /33
+#define SYSCTL_DSLPCLKCFG_D_34  0x10800000  // System clock /34
+#define SYSCTL_DSLPCLKCFG_D_35  0x11000000  // System clock /35
+#define SYSCTL_DSLPCLKCFG_D_36  0x11800000  // System clock /36
+#define SYSCTL_DSLPCLKCFG_D_37  0x12000000  // System clock /37
+#define SYSCTL_DSLPCLKCFG_D_38  0x12800000  // System clock /38
+#define SYSCTL_DSLPCLKCFG_D_39  0x13000000  // System clock /39
+#define SYSCTL_DSLPCLKCFG_D_40  0x13800000  // System clock /40
+#define SYSCTL_DSLPCLKCFG_D_41  0x14000000  // System clock /41
+#define SYSCTL_DSLPCLKCFG_D_42  0x14800000  // System clock /42
+#define SYSCTL_DSLPCLKCFG_D_43  0x15000000  // System clock /43
+#define SYSCTL_DSLPCLKCFG_D_44  0x15800000  // System clock /44
+#define SYSCTL_DSLPCLKCFG_D_45  0x16000000  // System clock /45
+#define SYSCTL_DSLPCLKCFG_D_46  0x16800000  // System clock /46
+#define SYSCTL_DSLPCLKCFG_D_47  0x17000000  // System clock /47
+#define SYSCTL_DSLPCLKCFG_D_48  0x17800000  // System clock /48
+#define SYSCTL_DSLPCLKCFG_D_49  0x18000000  // System clock /49
+#define SYSCTL_DSLPCLKCFG_D_50  0x18800000  // System clock /50
+#define SYSCTL_DSLPCLKCFG_D_51  0x19000000  // System clock /51
+#define SYSCTL_DSLPCLKCFG_D_52  0x19800000  // System clock /52
+#define SYSCTL_DSLPCLKCFG_D_53  0x1A000000  // System clock /53
+#define SYSCTL_DSLPCLKCFG_D_54  0x1A800000  // System clock /54
+#define SYSCTL_DSLPCLKCFG_D_55  0x1B000000  // System clock /55
+#define SYSCTL_DSLPCLKCFG_D_56  0x1B800000  // System clock /56
+#define SYSCTL_DSLPCLKCFG_D_57  0x1C000000  // System clock /57
+#define SYSCTL_DSLPCLKCFG_D_58  0x1C800000  // System clock /58
+#define SYSCTL_DSLPCLKCFG_D_59  0x1D000000  // System clock /59
+#define SYSCTL_DSLPCLKCFG_D_60  0x1D800000  // System clock /60
+#define SYSCTL_DSLPCLKCFG_D_61  0x1E000000  // System clock /61
+#define SYSCTL_DSLPCLKCFG_D_62  0x1E800000  // System clock /62
+#define SYSCTL_DSLPCLKCFG_D_63  0x1F000000  // System clock /63
+#define SYSCTL_DSLPCLKCFG_D_64  0x1F800000  // System clock /64
+#define SYSCTL_DSLPCLKCFG_O_M   0x00000070  // Clock Source
 #define SYSCTL_DSLPCLKCFG_O_IGN 0x00000000  // MOSC
-#define SYSCTL_DSLPCLKCFG_O_IO  0x00000010  // IOSC
+#define SYSCTL_DSLPCLKCFG_O_IO  0x00000010  // PIOSC
 #define SYSCTL_DSLPCLKCFG_O_30  0x00000030  // 30 kHz
-#define SYSCTL_DSLPCLKCFG_O_32  0x00000070  // 32 kHz
+#define SYSCTL_DSLPCLKCFG_O_32  0x00000070  // 32.768 kHz
 #define SYSCTL_DSLPCLKCFG_D_S   23
 
 //*****************************************************************************
@@ -3110,17 +3138,17 @@
 // The following are defines for the bit fields in the NVIC_ST_CTRL register.
 //
 //*****************************************************************************
-#define NVIC_ST_CTRL_COUNT      0x00010000  // Count flag
+#define NVIC_ST_CTRL_COUNT      0x00010000  // Count Flag
 #define NVIC_ST_CTRL_CLK_SRC    0x00000004  // Clock Source
-#define NVIC_ST_CTRL_INTEN      0x00000002  // Interrupt enable
-#define NVIC_ST_CTRL_ENABLE     0x00000001  // Counter mode
+#define NVIC_ST_CTRL_INTEN      0x00000002  // Interrupt Enable
+#define NVIC_ST_CTRL_ENABLE     0x00000001  // Enable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_ST_RELOAD register.
 //
 //*****************************************************************************
-#define NVIC_ST_RELOAD_M        0x00FFFFFF  // Counter load value
+#define NVIC_ST_RELOAD_M        0x00FFFFFF  // Reload Value
 #define NVIC_ST_RELOAD_S        0
 
 //*****************************************************************************
@@ -3129,7 +3157,7 @@
 // register.
 //
 //*****************************************************************************
-#define NVIC_ST_CURRENT_M       0x00FFFFFF  // Counter current value
+#define NVIC_ST_CURRENT_M       0x00FFFFFF  // Current Value
 #define NVIC_ST_CURRENT_S       0
 
 //*****************************************************************************
@@ -3147,539 +3175,541 @@
 // The following are defines for the bit fields in the NVIC_EN0 register.
 //
 //*****************************************************************************
-#define NVIC_EN0_INT31          0x80000000  // Interrupt 31 enable
-#define NVIC_EN0_INT30          0x40000000  // Interrupt 30 enable
-#define NVIC_EN0_INT29          0x20000000  // Interrupt 29 enable
-#define NVIC_EN0_INT28          0x10000000  // Interrupt 28 enable
-#define NVIC_EN0_INT27          0x08000000  // Interrupt 27 enable
-#define NVIC_EN0_INT26          0x04000000  // Interrupt 26 enable
-#define NVIC_EN0_INT25          0x02000000  // Interrupt 25 enable
-#define NVIC_EN0_INT24          0x01000000  // Interrupt 24 enable
-#define NVIC_EN0_INT23          0x00800000  // Interrupt 23 enable
-#define NVIC_EN0_INT22          0x00400000  // Interrupt 22 enable
-#define NVIC_EN0_INT21          0x00200000  // Interrupt 21 enable
-#define NVIC_EN0_INT20          0x00100000  // Interrupt 20 enable
-#define NVIC_EN0_INT19          0x00080000  // Interrupt 19 enable
-#define NVIC_EN0_INT18          0x00040000  // Interrupt 18 enable
-#define NVIC_EN0_INT17          0x00020000  // Interrupt 17 enable
-#define NVIC_EN0_INT16          0x00010000  // Interrupt 16 enable
-#define NVIC_EN0_INT15          0x00008000  // Interrupt 15 enable
-#define NVIC_EN0_INT14          0x00004000  // Interrupt 14 enable
-#define NVIC_EN0_INT13          0x00002000  // Interrupt 13 enable
-#define NVIC_EN0_INT12          0x00001000  // Interrupt 12 enable
-#define NVIC_EN0_INT11          0x00000800  // Interrupt 11 enable
-#define NVIC_EN0_INT10          0x00000400  // Interrupt 10 enable
-#define NVIC_EN0_INT9           0x00000200  // Interrupt 9 enable
-#define NVIC_EN0_INT8           0x00000100  // Interrupt 8 enable
-#define NVIC_EN0_INT7           0x00000080  // Interrupt 7 enable
-#define NVIC_EN0_INT6           0x00000040  // Interrupt 6 enable
-#define NVIC_EN0_INT5           0x00000020  // Interrupt 5 enable
-#define NVIC_EN0_INT4           0x00000010  // Interrupt 4 enable
-#define NVIC_EN0_INT3           0x00000008  // Interrupt 3 enable
-#define NVIC_EN0_INT2           0x00000004  // Interrupt 2 enable
-#define NVIC_EN0_INT1           0x00000002  // Interrupt 1 enable
+#define NVIC_EN0_INT_M          0xFFFFFFFF  // Interrupt Enable
 #define NVIC_EN0_INT0           0x00000001  // Interrupt 0 enable
+#define NVIC_EN0_INT1           0x00000002  // Interrupt 1 enable
+#define NVIC_EN0_INT2           0x00000004  // Interrupt 2 enable
+#define NVIC_EN0_INT3           0x00000008  // Interrupt 3 enable
+#define NVIC_EN0_INT4           0x00000010  // Interrupt 4 enable
+#define NVIC_EN0_INT5           0x00000020  // Interrupt 5 enable
+#define NVIC_EN0_INT6           0x00000040  // Interrupt 6 enable
+#define NVIC_EN0_INT7           0x00000080  // Interrupt 7 enable
+#define NVIC_EN0_INT8           0x00000100  // Interrupt 8 enable
+#define NVIC_EN0_INT9           0x00000200  // Interrupt 9 enable
+#define NVIC_EN0_INT10          0x00000400  // Interrupt 10 enable
+#define NVIC_EN0_INT11          0x00000800  // Interrupt 11 enable
+#define NVIC_EN0_INT12          0x00001000  // Interrupt 12 enable
+#define NVIC_EN0_INT13          0x00002000  // Interrupt 13 enable
+#define NVIC_EN0_INT14          0x00004000  // Interrupt 14 enable
+#define NVIC_EN0_INT15          0x00008000  // Interrupt 15 enable
+#define NVIC_EN0_INT16          0x00010000  // Interrupt 16 enable
+#define NVIC_EN0_INT17          0x00020000  // Interrupt 17 enable
+#define NVIC_EN0_INT18          0x00040000  // Interrupt 18 enable
+#define NVIC_EN0_INT19          0x00080000  // Interrupt 19 enable
+#define NVIC_EN0_INT20          0x00100000  // Interrupt 20 enable
+#define NVIC_EN0_INT21          0x00200000  // Interrupt 21 enable
+#define NVIC_EN0_INT22          0x00400000  // Interrupt 22 enable
+#define NVIC_EN0_INT23          0x00800000  // Interrupt 23 enable
+#define NVIC_EN0_INT24          0x01000000  // Interrupt 24 enable
+#define NVIC_EN0_INT25          0x02000000  // Interrupt 25 enable
+#define NVIC_EN0_INT26          0x04000000  // Interrupt 26 enable
+#define NVIC_EN0_INT27          0x08000000  // Interrupt 27 enable
+#define NVIC_EN0_INT28          0x10000000  // Interrupt 28 enable
+#define NVIC_EN0_INT29          0x20000000  // Interrupt 29 enable
+#define NVIC_EN0_INT30          0x40000000  // Interrupt 30 enable
+#define NVIC_EN0_INT31          0x80000000  // Interrupt 31 enable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_EN1 register.
 //
 //*****************************************************************************
-#define NVIC_EN1_INT59          0x08000000  // Interrupt 59 enable
-#define NVIC_EN1_INT58          0x04000000  // Interrupt 58 enable
-#define NVIC_EN1_INT57          0x02000000  // Interrupt 57 enable
-#define NVIC_EN1_INT56          0x01000000  // Interrupt 56 enable
-#define NVIC_EN1_INT55          0x00800000  // Interrupt 55 enable
-#define NVIC_EN1_INT54          0x00400000  // Interrupt 54 enable
-#define NVIC_EN1_INT53          0x00200000  // Interrupt 53 enable
-#define NVIC_EN1_INT52          0x00100000  // Interrupt 52 enable
-#define NVIC_EN1_INT51          0x00080000  // Interrupt 51 enable
-#define NVIC_EN1_INT50          0x00040000  // Interrupt 50 enable
-#define NVIC_EN1_INT49          0x00020000  // Interrupt 49 enable
-#define NVIC_EN1_INT48          0x00010000  // Interrupt 48 enable
-#define NVIC_EN1_INT47          0x00008000  // Interrupt 47 enable
-#define NVIC_EN1_INT46          0x00004000  // Interrupt 46 enable
-#define NVIC_EN1_INT45          0x00002000  // Interrupt 45 enable
-#define NVIC_EN1_INT44          0x00001000  // Interrupt 44 enable
-#define NVIC_EN1_INT43          0x00000800  // Interrupt 43 enable
-#define NVIC_EN1_INT42          0x00000400  // Interrupt 42 enable
-#define NVIC_EN1_INT41          0x00000200  // Interrupt 41 enable
-#define NVIC_EN1_INT40          0x00000100  // Interrupt 40 enable
-#define NVIC_EN1_INT39          0x00000080  // Interrupt 39 enable
-#define NVIC_EN1_INT38          0x00000040  // Interrupt 38 enable
-#define NVIC_EN1_INT37          0x00000020  // Interrupt 37 enable
-#define NVIC_EN1_INT36          0x00000010  // Interrupt 36 enable
-#define NVIC_EN1_INT35          0x00000008  // Interrupt 35 enable
-#define NVIC_EN1_INT34          0x00000004  // Interrupt 34 enable
-#define NVIC_EN1_INT33          0x00000002  // Interrupt 33 enable
+#define NVIC_EN1_INT_M          0x00000FFF  // Interrupt Enable
 #define NVIC_EN1_INT32          0x00000001  // Interrupt 32 enable
+#define NVIC_EN1_INT33          0x00000002  // Interrupt 33 enable
+#define NVIC_EN1_INT34          0x00000004  // Interrupt 34 enable
+#define NVIC_EN1_INT35          0x00000008  // Interrupt 35 enable
+#define NVIC_EN1_INT36          0x00000010  // Interrupt 36 enable
+#define NVIC_EN1_INT37          0x00000020  // Interrupt 37 enable
+#define NVIC_EN1_INT38          0x00000040  // Interrupt 38 enable
+#define NVIC_EN1_INT39          0x00000080  // Interrupt 39 enable
+#define NVIC_EN1_INT40          0x00000100  // Interrupt 40 enable
+#define NVIC_EN1_INT41          0x00000200  // Interrupt 41 enable
+#define NVIC_EN1_INT42          0x00000400  // Interrupt 42 enable
+#define NVIC_EN1_INT43          0x00000800  // Interrupt 43 enable
+#define NVIC_EN1_INT44          0x00001000  // Interrupt 44 enable
+#define NVIC_EN1_INT45          0x00002000  // Interrupt 45 enable
+#define NVIC_EN1_INT46          0x00004000  // Interrupt 46 enable
+#define NVIC_EN1_INT47          0x00008000  // Interrupt 47 enable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_DIS0 register.
 //
 //*****************************************************************************
-#define NVIC_DIS0_INT31         0x80000000  // Interrupt 31 disable
-#define NVIC_DIS0_INT30         0x40000000  // Interrupt 30 disable
-#define NVIC_DIS0_INT29         0x20000000  // Interrupt 29 disable
-#define NVIC_DIS0_INT28         0x10000000  // Interrupt 28 disable
-#define NVIC_DIS0_INT27         0x08000000  // Interrupt 27 disable
-#define NVIC_DIS0_INT26         0x04000000  // Interrupt 26 disable
-#define NVIC_DIS0_INT25         0x02000000  // Interrupt 25 disable
-#define NVIC_DIS0_INT24         0x01000000  // Interrupt 24 disable
-#define NVIC_DIS0_INT23         0x00800000  // Interrupt 23 disable
-#define NVIC_DIS0_INT22         0x00400000  // Interrupt 22 disable
-#define NVIC_DIS0_INT21         0x00200000  // Interrupt 21 disable
-#define NVIC_DIS0_INT20         0x00100000  // Interrupt 20 disable
-#define NVIC_DIS0_INT19         0x00080000  // Interrupt 19 disable
-#define NVIC_DIS0_INT18         0x00040000  // Interrupt 18 disable
-#define NVIC_DIS0_INT17         0x00020000  // Interrupt 17 disable
-#define NVIC_DIS0_INT16         0x00010000  // Interrupt 16 disable
-#define NVIC_DIS0_INT15         0x00008000  // Interrupt 15 disable
-#define NVIC_DIS0_INT14         0x00004000  // Interrupt 14 disable
-#define NVIC_DIS0_INT13         0x00002000  // Interrupt 13 disable
-#define NVIC_DIS0_INT12         0x00001000  // Interrupt 12 disable
-#define NVIC_DIS0_INT11         0x00000800  // Interrupt 11 disable
-#define NVIC_DIS0_INT10         0x00000400  // Interrupt 10 disable
-#define NVIC_DIS0_INT9          0x00000200  // Interrupt 9 disable
-#define NVIC_DIS0_INT8          0x00000100  // Interrupt 8 disable
-#define NVIC_DIS0_INT7          0x00000080  // Interrupt 7 disable
-#define NVIC_DIS0_INT6          0x00000040  // Interrupt 6 disable
-#define NVIC_DIS0_INT5          0x00000020  // Interrupt 5 disable
-#define NVIC_DIS0_INT4          0x00000010  // Interrupt 4 disable
-#define NVIC_DIS0_INT3          0x00000008  // Interrupt 3 disable
-#define NVIC_DIS0_INT2          0x00000004  // Interrupt 2 disable
-#define NVIC_DIS0_INT1          0x00000002  // Interrupt 1 disable
+#define NVIC_DIS0_INT_M         0xFFFFFFFF  // Interrupt Disable
 #define NVIC_DIS0_INT0          0x00000001  // Interrupt 0 disable
+#define NVIC_DIS0_INT1          0x00000002  // Interrupt 1 disable
+#define NVIC_DIS0_INT2          0x00000004  // Interrupt 2 disable
+#define NVIC_DIS0_INT3          0x00000008  // Interrupt 3 disable
+#define NVIC_DIS0_INT4          0x00000010  // Interrupt 4 disable
+#define NVIC_DIS0_INT5          0x00000020  // Interrupt 5 disable
+#define NVIC_DIS0_INT6          0x00000040  // Interrupt 6 disable
+#define NVIC_DIS0_INT7          0x00000080  // Interrupt 7 disable
+#define NVIC_DIS0_INT8          0x00000100  // Interrupt 8 disable
+#define NVIC_DIS0_INT9          0x00000200  // Interrupt 9 disable
+#define NVIC_DIS0_INT10         0x00000400  // Interrupt 10 disable
+#define NVIC_DIS0_INT11         0x00000800  // Interrupt 11 disable
+#define NVIC_DIS0_INT12         0x00001000  // Interrupt 12 disable
+#define NVIC_DIS0_INT13         0x00002000  // Interrupt 13 disable
+#define NVIC_DIS0_INT14         0x00004000  // Interrupt 14 disable
+#define NVIC_DIS0_INT15         0x00008000  // Interrupt 15 disable
+#define NVIC_DIS0_INT16         0x00010000  // Interrupt 16 disable
+#define NVIC_DIS0_INT17         0x00020000  // Interrupt 17 disable
+#define NVIC_DIS0_INT18         0x00040000  // Interrupt 18 disable
+#define NVIC_DIS0_INT19         0x00080000  // Interrupt 19 disable
+#define NVIC_DIS0_INT20         0x00100000  // Interrupt 20 disable
+#define NVIC_DIS0_INT21         0x00200000  // Interrupt 21 disable
+#define NVIC_DIS0_INT22         0x00400000  // Interrupt 22 disable
+#define NVIC_DIS0_INT23         0x00800000  // Interrupt 23 disable
+#define NVIC_DIS0_INT24         0x01000000  // Interrupt 24 disable
+#define NVIC_DIS0_INT25         0x02000000  // Interrupt 25 disable
+#define NVIC_DIS0_INT26         0x04000000  // Interrupt 26 disable
+#define NVIC_DIS0_INT27         0x08000000  // Interrupt 27 disable
+#define NVIC_DIS0_INT28         0x10000000  // Interrupt 28 disable
+#define NVIC_DIS0_INT29         0x20000000  // Interrupt 29 disable
+#define NVIC_DIS0_INT30         0x40000000  // Interrupt 30 disable
+#define NVIC_DIS0_INT31         0x80000000  // Interrupt 31 disable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_DIS1 register.
 //
 //*****************************************************************************
-#define NVIC_DIS1_INT59         0x08000000  // Interrupt 59 disable
-#define NVIC_DIS1_INT58         0x04000000  // Interrupt 58 disable
-#define NVIC_DIS1_INT57         0x02000000  // Interrupt 57 disable
-#define NVIC_DIS1_INT56         0x01000000  // Interrupt 56 disable
-#define NVIC_DIS1_INT55         0x00800000  // Interrupt 55 disable
-#define NVIC_DIS1_INT54         0x00400000  // Interrupt 54 disable
-#define NVIC_DIS1_INT53         0x00200000  // Interrupt 53 disable
-#define NVIC_DIS1_INT52         0x00100000  // Interrupt 52 disable
-#define NVIC_DIS1_INT51         0x00080000  // Interrupt 51 disable
-#define NVIC_DIS1_INT50         0x00040000  // Interrupt 50 disable
-#define NVIC_DIS1_INT49         0x00020000  // Interrupt 49 disable
-#define NVIC_DIS1_INT48         0x00010000  // Interrupt 48 disable
-#define NVIC_DIS1_INT47         0x00008000  // Interrupt 47 disable
-#define NVIC_DIS1_INT46         0x00004000  // Interrupt 46 disable
-#define NVIC_DIS1_INT45         0x00002000  // Interrupt 45 disable
-#define NVIC_DIS1_INT44         0x00001000  // Interrupt 44 disable
-#define NVIC_DIS1_INT43         0x00000800  // Interrupt 43 disable
-#define NVIC_DIS1_INT42         0x00000400  // Interrupt 42 disable
-#define NVIC_DIS1_INT41         0x00000200  // Interrupt 41 disable
-#define NVIC_DIS1_INT40         0x00000100  // Interrupt 40 disable
-#define NVIC_DIS1_INT39         0x00000080  // Interrupt 39 disable
-#define NVIC_DIS1_INT38         0x00000040  // Interrupt 38 disable
-#define NVIC_DIS1_INT37         0x00000020  // Interrupt 37 disable
-#define NVIC_DIS1_INT36         0x00000010  // Interrupt 36 disable
-#define NVIC_DIS1_INT35         0x00000008  // Interrupt 35 disable
-#define NVIC_DIS1_INT34         0x00000004  // Interrupt 34 disable
-#define NVIC_DIS1_INT33         0x00000002  // Interrupt 33 disable
+#define NVIC_DIS1_INT_M         0x00000FFF  // Interrupt Disable
 #define NVIC_DIS1_INT32         0x00000001  // Interrupt 32 disable
+#define NVIC_DIS1_INT33         0x00000002  // Interrupt 33 disable
+#define NVIC_DIS1_INT34         0x00000004  // Interrupt 34 disable
+#define NVIC_DIS1_INT35         0x00000008  // Interrupt 35 disable
+#define NVIC_DIS1_INT36         0x00000010  // Interrupt 36 disable
+#define NVIC_DIS1_INT37         0x00000020  // Interrupt 37 disable
+#define NVIC_DIS1_INT38         0x00000040  // Interrupt 38 disable
+#define NVIC_DIS1_INT39         0x00000080  // Interrupt 39 disable
+#define NVIC_DIS1_INT40         0x00000100  // Interrupt 40 disable
+#define NVIC_DIS1_INT41         0x00000200  // Interrupt 41 disable
+#define NVIC_DIS1_INT42         0x00000400  // Interrupt 42 disable
+#define NVIC_DIS1_INT43         0x00000800  // Interrupt 43 disable
+#define NVIC_DIS1_INT44         0x00001000  // Interrupt 44 disable
+#define NVIC_DIS1_INT45         0x00002000  // Interrupt 45 disable
+#define NVIC_DIS1_INT46         0x00004000  // Interrupt 46 disable
+#define NVIC_DIS1_INT47         0x00008000  // Interrupt 47 disable
+#define NVIC_DIS1_INT48         0x00010000  // Interrupt 48 disable
+#define NVIC_DIS1_INT49         0x00020000  // Interrupt 49 disable
+#define NVIC_DIS1_INT50         0x00040000  // Interrupt 50 disable
+#define NVIC_DIS1_INT51         0x00080000  // Interrupt 51 disable
+#define NVIC_DIS1_INT52         0x00100000  // Interrupt 52 disable
+#define NVIC_DIS1_INT53         0x00200000  // Interrupt 53 disable
+#define NVIC_DIS1_INT54         0x00400000  // Interrupt 54 disable
+#define NVIC_DIS1_INT55         0x00800000  // Interrupt 55 disable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_PEND0 register.
 //
 //*****************************************************************************
-#define NVIC_PEND0_INT31        0x80000000  // Interrupt 31 pend
-#define NVIC_PEND0_INT30        0x40000000  // Interrupt 30 pend
-#define NVIC_PEND0_INT29        0x20000000  // Interrupt 29 pend
-#define NVIC_PEND0_INT28        0x10000000  // Interrupt 28 pend
-#define NVIC_PEND0_INT27        0x08000000  // Interrupt 27 pend
-#define NVIC_PEND0_INT26        0x04000000  // Interrupt 26 pend
-#define NVIC_PEND0_INT25        0x02000000  // Interrupt 25 pend
-#define NVIC_PEND0_INT24        0x01000000  // Interrupt 24 pend
-#define NVIC_PEND0_INT23        0x00800000  // Interrupt 23 pend
-#define NVIC_PEND0_INT22        0x00400000  // Interrupt 22 pend
-#define NVIC_PEND0_INT21        0x00200000  // Interrupt 21 pend
-#define NVIC_PEND0_INT20        0x00100000  // Interrupt 20 pend
-#define NVIC_PEND0_INT19        0x00080000  // Interrupt 19 pend
-#define NVIC_PEND0_INT18        0x00040000  // Interrupt 18 pend
-#define NVIC_PEND0_INT17        0x00020000  // Interrupt 17 pend
-#define NVIC_PEND0_INT16        0x00010000  // Interrupt 16 pend
-#define NVIC_PEND0_INT15        0x00008000  // Interrupt 15 pend
-#define NVIC_PEND0_INT14        0x00004000  // Interrupt 14 pend
-#define NVIC_PEND0_INT13        0x00002000  // Interrupt 13 pend
-#define NVIC_PEND0_INT12        0x00001000  // Interrupt 12 pend
-#define NVIC_PEND0_INT11        0x00000800  // Interrupt 11 pend
-#define NVIC_PEND0_INT10        0x00000400  // Interrupt 10 pend
-#define NVIC_PEND0_INT9         0x00000200  // Interrupt 9 pend
-#define NVIC_PEND0_INT8         0x00000100  // Interrupt 8 pend
-#define NVIC_PEND0_INT7         0x00000080  // Interrupt 7 pend
-#define NVIC_PEND0_INT6         0x00000040  // Interrupt 6 pend
-#define NVIC_PEND0_INT5         0x00000020  // Interrupt 5 pend
-#define NVIC_PEND0_INT4         0x00000010  // Interrupt 4 pend
-#define NVIC_PEND0_INT3         0x00000008  // Interrupt 3 pend
-#define NVIC_PEND0_INT2         0x00000004  // Interrupt 2 pend
-#define NVIC_PEND0_INT1         0x00000002  // Interrupt 1 pend
+#define NVIC_PEND0_INT_M        0xFFFFFFFF  // Interrupt Set Pending
 #define NVIC_PEND0_INT0         0x00000001  // Interrupt 0 pend
+#define NVIC_PEND0_INT1         0x00000002  // Interrupt 1 pend
+#define NVIC_PEND0_INT2         0x00000004  // Interrupt 2 pend
+#define NVIC_PEND0_INT3         0x00000008  // Interrupt 3 pend
+#define NVIC_PEND0_INT4         0x00000010  // Interrupt 4 pend
+#define NVIC_PEND0_INT5         0x00000020  // Interrupt 5 pend
+#define NVIC_PEND0_INT6         0x00000040  // Interrupt 6 pend
+#define NVIC_PEND0_INT7         0x00000080  // Interrupt 7 pend
+#define NVIC_PEND0_INT8         0x00000100  // Interrupt 8 pend
+#define NVIC_PEND0_INT9         0x00000200  // Interrupt 9 pend
+#define NVIC_PEND0_INT10        0x00000400  // Interrupt 10 pend
+#define NVIC_PEND0_INT11        0x00000800  // Interrupt 11 pend
+#define NVIC_PEND0_INT12        0x00001000  // Interrupt 12 pend
+#define NVIC_PEND0_INT13        0x00002000  // Interrupt 13 pend
+#define NVIC_PEND0_INT14        0x00004000  // Interrupt 14 pend
+#define NVIC_PEND0_INT15        0x00008000  // Interrupt 15 pend
+#define NVIC_PEND0_INT16        0x00010000  // Interrupt 16 pend
+#define NVIC_PEND0_INT17        0x00020000  // Interrupt 17 pend
+#define NVIC_PEND0_INT18        0x00040000  // Interrupt 18 pend
+#define NVIC_PEND0_INT19        0x00080000  // Interrupt 19 pend
+#define NVIC_PEND0_INT20        0x00100000  // Interrupt 20 pend
+#define NVIC_PEND0_INT21        0x00200000  // Interrupt 21 pend
+#define NVIC_PEND0_INT22        0x00400000  // Interrupt 22 pend
+#define NVIC_PEND0_INT23        0x00800000  // Interrupt 23 pend
+#define NVIC_PEND0_INT24        0x01000000  // Interrupt 24 pend
+#define NVIC_PEND0_INT25        0x02000000  // Interrupt 25 pend
+#define NVIC_PEND0_INT26        0x04000000  // Interrupt 26 pend
+#define NVIC_PEND0_INT27        0x08000000  // Interrupt 27 pend
+#define NVIC_PEND0_INT28        0x10000000  // Interrupt 28 pend
+#define NVIC_PEND0_INT29        0x20000000  // Interrupt 29 pend
+#define NVIC_PEND0_INT30        0x40000000  // Interrupt 30 pend
+#define NVIC_PEND0_INT31        0x80000000  // Interrupt 31 pend
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_PEND1 register.
 //
 //*****************************************************************************
-#define NVIC_PEND1_INT59        0x08000000  // Interrupt 59 pend
-#define NVIC_PEND1_INT58        0x04000000  // Interrupt 58 pend
-#define NVIC_PEND1_INT57        0x02000000  // Interrupt 57 pend
-#define NVIC_PEND1_INT56        0x01000000  // Interrupt 56 pend
-#define NVIC_PEND1_INT55        0x00800000  // Interrupt 55 pend
-#define NVIC_PEND1_INT54        0x00400000  // Interrupt 54 pend
-#define NVIC_PEND1_INT53        0x00200000  // Interrupt 53 pend
-#define NVIC_PEND1_INT52        0x00100000  // Interrupt 52 pend
-#define NVIC_PEND1_INT51        0x00080000  // Interrupt 51 pend
-#define NVIC_PEND1_INT50        0x00040000  // Interrupt 50 pend
-#define NVIC_PEND1_INT49        0x00020000  // Interrupt 49 pend
-#define NVIC_PEND1_INT48        0x00010000  // Interrupt 48 pend
-#define NVIC_PEND1_INT47        0x00008000  // Interrupt 47 pend
-#define NVIC_PEND1_INT46        0x00004000  // Interrupt 46 pend
-#define NVIC_PEND1_INT45        0x00002000  // Interrupt 45 pend
-#define NVIC_PEND1_INT44        0x00001000  // Interrupt 44 pend
-#define NVIC_PEND1_INT43        0x00000800  // Interrupt 43 pend
-#define NVIC_PEND1_INT42        0x00000400  // Interrupt 42 pend
-#define NVIC_PEND1_INT41        0x00000200  // Interrupt 41 pend
-#define NVIC_PEND1_INT40        0x00000100  // Interrupt 40 pend
-#define NVIC_PEND1_INT39        0x00000080  // Interrupt 39 pend
-#define NVIC_PEND1_INT38        0x00000040  // Interrupt 38 pend
-#define NVIC_PEND1_INT37        0x00000020  // Interrupt 37 pend
-#define NVIC_PEND1_INT36        0x00000010  // Interrupt 36 pend
-#define NVIC_PEND1_INT35        0x00000008  // Interrupt 35 pend
-#define NVIC_PEND1_INT34        0x00000004  // Interrupt 34 pend
-#define NVIC_PEND1_INT33        0x00000002  // Interrupt 33 pend
+#define NVIC_PEND1_INT_M        0x00000FFF  // Interrupt Set Pending
 #define NVIC_PEND1_INT32        0x00000001  // Interrupt 32 pend
+#define NVIC_PEND1_INT33        0x00000002  // Interrupt 33 pend
+#define NVIC_PEND1_INT34        0x00000004  // Interrupt 34 pend
+#define NVIC_PEND1_INT35        0x00000008  // Interrupt 35 pend
+#define NVIC_PEND1_INT36        0x00000010  // Interrupt 36 pend
+#define NVIC_PEND1_INT37        0x00000020  // Interrupt 37 pend
+#define NVIC_PEND1_INT38        0x00000040  // Interrupt 38 pend
+#define NVIC_PEND1_INT39        0x00000080  // Interrupt 39 pend
+#define NVIC_PEND1_INT40        0x00000100  // Interrupt 40 pend
+#define NVIC_PEND1_INT41        0x00000200  // Interrupt 41 pend
+#define NVIC_PEND1_INT42        0x00000400  // Interrupt 42 pend
+#define NVIC_PEND1_INT43        0x00000800  // Interrupt 43 pend
+#define NVIC_PEND1_INT44        0x00001000  // Interrupt 44 pend
+#define NVIC_PEND1_INT45        0x00002000  // Interrupt 45 pend
+#define NVIC_PEND1_INT46        0x00004000  // Interrupt 46 pend
+#define NVIC_PEND1_INT47        0x00008000  // Interrupt 47 pend
+#define NVIC_PEND1_INT48        0x00010000  // Interrupt 48 pend
+#define NVIC_PEND1_INT49        0x00020000  // Interrupt 49 pend
+#define NVIC_PEND1_INT50        0x00040000  // Interrupt 50 pend
+#define NVIC_PEND1_INT51        0x00080000  // Interrupt 51 pend
+#define NVIC_PEND1_INT52        0x00100000  // Interrupt 52 pend
+#define NVIC_PEND1_INT53        0x00200000  // Interrupt 53 pend
+#define NVIC_PEND1_INT54        0x00400000  // Interrupt 54 pend
+#define NVIC_PEND1_INT55        0x00800000  // Interrupt 55 pend
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_UNPEND0 register.
 //
 //*****************************************************************************
-#define NVIC_UNPEND0_INT31      0x80000000  // Interrupt 31 unpend
-#define NVIC_UNPEND0_INT30      0x40000000  // Interrupt 30 unpend
-#define NVIC_UNPEND0_INT29      0x20000000  // Interrupt 29 unpend
-#define NVIC_UNPEND0_INT28      0x10000000  // Interrupt 28 unpend
-#define NVIC_UNPEND0_INT27      0x08000000  // Interrupt 27 unpend
-#define NVIC_UNPEND0_INT26      0x04000000  // Interrupt 26 unpend
-#define NVIC_UNPEND0_INT25      0x02000000  // Interrupt 25 unpend
-#define NVIC_UNPEND0_INT24      0x01000000  // Interrupt 24 unpend
-#define NVIC_UNPEND0_INT23      0x00800000  // Interrupt 23 unpend
-#define NVIC_UNPEND0_INT22      0x00400000  // Interrupt 22 unpend
-#define NVIC_UNPEND0_INT21      0x00200000  // Interrupt 21 unpend
-#define NVIC_UNPEND0_INT20      0x00100000  // Interrupt 20 unpend
-#define NVIC_UNPEND0_INT19      0x00080000  // Interrupt 19 unpend
-#define NVIC_UNPEND0_INT18      0x00040000  // Interrupt 18 unpend
-#define NVIC_UNPEND0_INT17      0x00020000  // Interrupt 17 unpend
-#define NVIC_UNPEND0_INT16      0x00010000  // Interrupt 16 unpend
-#define NVIC_UNPEND0_INT15      0x00008000  // Interrupt 15 unpend
-#define NVIC_UNPEND0_INT14      0x00004000  // Interrupt 14 unpend
-#define NVIC_UNPEND0_INT13      0x00002000  // Interrupt 13 unpend
-#define NVIC_UNPEND0_INT12      0x00001000  // Interrupt 12 unpend
-#define NVIC_UNPEND0_INT11      0x00000800  // Interrupt 11 unpend
-#define NVIC_UNPEND0_INT10      0x00000400  // Interrupt 10 unpend
-#define NVIC_UNPEND0_INT9       0x00000200  // Interrupt 9 unpend
-#define NVIC_UNPEND0_INT8       0x00000100  // Interrupt 8 unpend
-#define NVIC_UNPEND0_INT7       0x00000080  // Interrupt 7 unpend
-#define NVIC_UNPEND0_INT6       0x00000040  // Interrupt 6 unpend
-#define NVIC_UNPEND0_INT5       0x00000020  // Interrupt 5 unpend
-#define NVIC_UNPEND0_INT4       0x00000010  // Interrupt 4 unpend
-#define NVIC_UNPEND0_INT3       0x00000008  // Interrupt 3 unpend
-#define NVIC_UNPEND0_INT2       0x00000004  // Interrupt 2 unpend
-#define NVIC_UNPEND0_INT1       0x00000002  // Interrupt 1 unpend
+#define NVIC_UNPEND0_INT_M      0xFFFFFFFF  // Interrupt Clear Pending
 #define NVIC_UNPEND0_INT0       0x00000001  // Interrupt 0 unpend
+#define NVIC_UNPEND0_INT1       0x00000002  // Interrupt 1 unpend
+#define NVIC_UNPEND0_INT2       0x00000004  // Interrupt 2 unpend
+#define NVIC_UNPEND0_INT3       0x00000008  // Interrupt 3 unpend
+#define NVIC_UNPEND0_INT4       0x00000010  // Interrupt 4 unpend
+#define NVIC_UNPEND0_INT5       0x00000020  // Interrupt 5 unpend
+#define NVIC_UNPEND0_INT6       0x00000040  // Interrupt 6 unpend
+#define NVIC_UNPEND0_INT7       0x00000080  // Interrupt 7 unpend
+#define NVIC_UNPEND0_INT8       0x00000100  // Interrupt 8 unpend
+#define NVIC_UNPEND0_INT9       0x00000200  // Interrupt 9 unpend
+#define NVIC_UNPEND0_INT10      0x00000400  // Interrupt 10 unpend
+#define NVIC_UNPEND0_INT11      0x00000800  // Interrupt 11 unpend
+#define NVIC_UNPEND0_INT12      0x00001000  // Interrupt 12 unpend
+#define NVIC_UNPEND0_INT13      0x00002000  // Interrupt 13 unpend
+#define NVIC_UNPEND0_INT14      0x00004000  // Interrupt 14 unpend
+#define NVIC_UNPEND0_INT15      0x00008000  // Interrupt 15 unpend
+#define NVIC_UNPEND0_INT16      0x00010000  // Interrupt 16 unpend
+#define NVIC_UNPEND0_INT17      0x00020000  // Interrupt 17 unpend
+#define NVIC_UNPEND0_INT18      0x00040000  // Interrupt 18 unpend
+#define NVIC_UNPEND0_INT19      0x00080000  // Interrupt 19 unpend
+#define NVIC_UNPEND0_INT20      0x00100000  // Interrupt 20 unpend
+#define NVIC_UNPEND0_INT21      0x00200000  // Interrupt 21 unpend
+#define NVIC_UNPEND0_INT22      0x00400000  // Interrupt 22 unpend
+#define NVIC_UNPEND0_INT23      0x00800000  // Interrupt 23 unpend
+#define NVIC_UNPEND0_INT24      0x01000000  // Interrupt 24 unpend
+#define NVIC_UNPEND0_INT25      0x02000000  // Interrupt 25 unpend
+#define NVIC_UNPEND0_INT26      0x04000000  // Interrupt 26 unpend
+#define NVIC_UNPEND0_INT27      0x08000000  // Interrupt 27 unpend
+#define NVIC_UNPEND0_INT28      0x10000000  // Interrupt 28 unpend
+#define NVIC_UNPEND0_INT29      0x20000000  // Interrupt 29 unpend
+#define NVIC_UNPEND0_INT30      0x40000000  // Interrupt 30 unpend
+#define NVIC_UNPEND0_INT31      0x80000000  // Interrupt 31 unpend
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_UNPEND1 register.
 //
 //*****************************************************************************
-#define NVIC_UNPEND1_INT59      0x08000000  // Interrupt 59 unpend
-#define NVIC_UNPEND1_INT58      0x04000000  // Interrupt 58 unpend
-#define NVIC_UNPEND1_INT57      0x02000000  // Interrupt 57 unpend
-#define NVIC_UNPEND1_INT56      0x01000000  // Interrupt 56 unpend
-#define NVIC_UNPEND1_INT55      0x00800000  // Interrupt 55 unpend
-#define NVIC_UNPEND1_INT54      0x00400000  // Interrupt 54 unpend
-#define NVIC_UNPEND1_INT53      0x00200000  // Interrupt 53 unpend
-#define NVIC_UNPEND1_INT52      0x00100000  // Interrupt 52 unpend
-#define NVIC_UNPEND1_INT51      0x00080000  // Interrupt 51 unpend
-#define NVIC_UNPEND1_INT50      0x00040000  // Interrupt 50 unpend
-#define NVIC_UNPEND1_INT49      0x00020000  // Interrupt 49 unpend
-#define NVIC_UNPEND1_INT48      0x00010000  // Interrupt 48 unpend
-#define NVIC_UNPEND1_INT47      0x00008000  // Interrupt 47 unpend
-#define NVIC_UNPEND1_INT46      0x00004000  // Interrupt 46 unpend
-#define NVIC_UNPEND1_INT45      0x00002000  // Interrupt 45 unpend
-#define NVIC_UNPEND1_INT44      0x00001000  // Interrupt 44 unpend
-#define NVIC_UNPEND1_INT43      0x00000800  // Interrupt 43 unpend
-#define NVIC_UNPEND1_INT42      0x00000400  // Interrupt 42 unpend
-#define NVIC_UNPEND1_INT41      0x00000200  // Interrupt 41 unpend
-#define NVIC_UNPEND1_INT40      0x00000100  // Interrupt 40 unpend
-#define NVIC_UNPEND1_INT39      0x00000080  // Interrupt 39 unpend
-#define NVIC_UNPEND1_INT38      0x00000040  // Interrupt 38 unpend
-#define NVIC_UNPEND1_INT37      0x00000020  // Interrupt 37 unpend
-#define NVIC_UNPEND1_INT36      0x00000010  // Interrupt 36 unpend
-#define NVIC_UNPEND1_INT35      0x00000008  // Interrupt 35 unpend
-#define NVIC_UNPEND1_INT34      0x00000004  // Interrupt 34 unpend
-#define NVIC_UNPEND1_INT33      0x00000002  // Interrupt 33 unpend
+#define NVIC_UNPEND1_INT_M      0x00000FFF  // Interrupt Clear Pending
 #define NVIC_UNPEND1_INT32      0x00000001  // Interrupt 32 unpend
+#define NVIC_UNPEND1_INT33      0x00000002  // Interrupt 33 unpend
+#define NVIC_UNPEND1_INT34      0x00000004  // Interrupt 34 unpend
+#define NVIC_UNPEND1_INT35      0x00000008  // Interrupt 35 unpend
+#define NVIC_UNPEND1_INT36      0x00000010  // Interrupt 36 unpend
+#define NVIC_UNPEND1_INT37      0x00000020  // Interrupt 37 unpend
+#define NVIC_UNPEND1_INT38      0x00000040  // Interrupt 38 unpend
+#define NVIC_UNPEND1_INT39      0x00000080  // Interrupt 39 unpend
+#define NVIC_UNPEND1_INT40      0x00000100  // Interrupt 40 unpend
+#define NVIC_UNPEND1_INT41      0x00000200  // Interrupt 41 unpend
+#define NVIC_UNPEND1_INT42      0x00000400  // Interrupt 42 unpend
+#define NVIC_UNPEND1_INT43      0x00000800  // Interrupt 43 unpend
+#define NVIC_UNPEND1_INT44      0x00001000  // Interrupt 44 unpend
+#define NVIC_UNPEND1_INT45      0x00002000  // Interrupt 45 unpend
+#define NVIC_UNPEND1_INT46      0x00004000  // Interrupt 46 unpend
+#define NVIC_UNPEND1_INT47      0x00008000  // Interrupt 47 unpend
+#define NVIC_UNPEND1_INT48      0x00010000  // Interrupt 48 unpend
+#define NVIC_UNPEND1_INT49      0x00020000  // Interrupt 49 unpend
+#define NVIC_UNPEND1_INT50      0x00040000  // Interrupt 50 unpend
+#define NVIC_UNPEND1_INT51      0x00080000  // Interrupt 51 unpend
+#define NVIC_UNPEND1_INT52      0x00100000  // Interrupt 52 unpend
+#define NVIC_UNPEND1_INT53      0x00200000  // Interrupt 53 unpend
+#define NVIC_UNPEND1_INT54      0x00400000  // Interrupt 54 unpend
+#define NVIC_UNPEND1_INT55      0x00800000  // Interrupt 55 unpend
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_ACTIVE0 register.
 //
 //*****************************************************************************
-#define NVIC_ACTIVE0_INT31      0x80000000  // Interrupt 31 active
-#define NVIC_ACTIVE0_INT30      0x40000000  // Interrupt 30 active
-#define NVIC_ACTIVE0_INT29      0x20000000  // Interrupt 29 active
-#define NVIC_ACTIVE0_INT28      0x10000000  // Interrupt 28 active
-#define NVIC_ACTIVE0_INT27      0x08000000  // Interrupt 27 active
-#define NVIC_ACTIVE0_INT26      0x04000000  // Interrupt 26 active
-#define NVIC_ACTIVE0_INT25      0x02000000  // Interrupt 25 active
-#define NVIC_ACTIVE0_INT24      0x01000000  // Interrupt 24 active
-#define NVIC_ACTIVE0_INT23      0x00800000  // Interrupt 23 active
-#define NVIC_ACTIVE0_INT22      0x00400000  // Interrupt 22 active
-#define NVIC_ACTIVE0_INT21      0x00200000  // Interrupt 21 active
-#define NVIC_ACTIVE0_INT20      0x00100000  // Interrupt 20 active
-#define NVIC_ACTIVE0_INT19      0x00080000  // Interrupt 19 active
-#define NVIC_ACTIVE0_INT18      0x00040000  // Interrupt 18 active
-#define NVIC_ACTIVE0_INT17      0x00020000  // Interrupt 17 active
-#define NVIC_ACTIVE0_INT16      0x00010000  // Interrupt 16 active
-#define NVIC_ACTIVE0_INT15      0x00008000  // Interrupt 15 active
-#define NVIC_ACTIVE0_INT14      0x00004000  // Interrupt 14 active
-#define NVIC_ACTIVE0_INT13      0x00002000  // Interrupt 13 active
-#define NVIC_ACTIVE0_INT12      0x00001000  // Interrupt 12 active
-#define NVIC_ACTIVE0_INT11      0x00000800  // Interrupt 11 active
-#define NVIC_ACTIVE0_INT10      0x00000400  // Interrupt 10 active
-#define NVIC_ACTIVE0_INT9       0x00000200  // Interrupt 9 active
-#define NVIC_ACTIVE0_INT8       0x00000100  // Interrupt 8 active
-#define NVIC_ACTIVE0_INT7       0x00000080  // Interrupt 7 active
-#define NVIC_ACTIVE0_INT6       0x00000040  // Interrupt 6 active
-#define NVIC_ACTIVE0_INT5       0x00000020  // Interrupt 5 active
-#define NVIC_ACTIVE0_INT4       0x00000010  // Interrupt 4 active
-#define NVIC_ACTIVE0_INT3       0x00000008  // Interrupt 3 active
-#define NVIC_ACTIVE0_INT2       0x00000004  // Interrupt 2 active
-#define NVIC_ACTIVE0_INT1       0x00000002  // Interrupt 1 active
+#define NVIC_ACTIVE0_INT_M      0xFFFFFFFF  // Interrupt Active
 #define NVIC_ACTIVE0_INT0       0x00000001  // Interrupt 0 active
+#define NVIC_ACTIVE0_INT1       0x00000002  // Interrupt 1 active
+#define NVIC_ACTIVE0_INT2       0x00000004  // Interrupt 2 active
+#define NVIC_ACTIVE0_INT3       0x00000008  // Interrupt 3 active
+#define NVIC_ACTIVE0_INT4       0x00000010  // Interrupt 4 active
+#define NVIC_ACTIVE0_INT5       0x00000020  // Interrupt 5 active
+#define NVIC_ACTIVE0_INT6       0x00000040  // Interrupt 6 active
+#define NVIC_ACTIVE0_INT7       0x00000080  // Interrupt 7 active
+#define NVIC_ACTIVE0_INT8       0x00000100  // Interrupt 8 active
+#define NVIC_ACTIVE0_INT9       0x00000200  // Interrupt 9 active
+#define NVIC_ACTIVE0_INT10      0x00000400  // Interrupt 10 active
+#define NVIC_ACTIVE0_INT11      0x00000800  // Interrupt 11 active
+#define NVIC_ACTIVE0_INT12      0x00001000  // Interrupt 12 active
+#define NVIC_ACTIVE0_INT13      0x00002000  // Interrupt 13 active
+#define NVIC_ACTIVE0_INT14      0x00004000  // Interrupt 14 active
+#define NVIC_ACTIVE0_INT15      0x00008000  // Interrupt 15 active
+#define NVIC_ACTIVE0_INT16      0x00010000  // Interrupt 16 active
+#define NVIC_ACTIVE0_INT17      0x00020000  // Interrupt 17 active
+#define NVIC_ACTIVE0_INT18      0x00040000  // Interrupt 18 active
+#define NVIC_ACTIVE0_INT19      0x00080000  // Interrupt 19 active
+#define NVIC_ACTIVE0_INT20      0x00100000  // Interrupt 20 active
+#define NVIC_ACTIVE0_INT21      0x00200000  // Interrupt 21 active
+#define NVIC_ACTIVE0_INT22      0x00400000  // Interrupt 22 active
+#define NVIC_ACTIVE0_INT23      0x00800000  // Interrupt 23 active
+#define NVIC_ACTIVE0_INT24      0x01000000  // Interrupt 24 active
+#define NVIC_ACTIVE0_INT25      0x02000000  // Interrupt 25 active
+#define NVIC_ACTIVE0_INT26      0x04000000  // Interrupt 26 active
+#define NVIC_ACTIVE0_INT27      0x08000000  // Interrupt 27 active
+#define NVIC_ACTIVE0_INT28      0x10000000  // Interrupt 28 active
+#define NVIC_ACTIVE0_INT29      0x20000000  // Interrupt 29 active
+#define NVIC_ACTIVE0_INT30      0x40000000  // Interrupt 30 active
+#define NVIC_ACTIVE0_INT31      0x80000000  // Interrupt 31 active
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_ACTIVE1 register.
 //
 //*****************************************************************************
-#define NVIC_ACTIVE1_INT59      0x08000000  // Interrupt 59 active
-#define NVIC_ACTIVE1_INT58      0x04000000  // Interrupt 58 active
-#define NVIC_ACTIVE1_INT57      0x02000000  // Interrupt 57 active
-#define NVIC_ACTIVE1_INT56      0x01000000  // Interrupt 56 active
-#define NVIC_ACTIVE1_INT55      0x00800000  // Interrupt 55 active
-#define NVIC_ACTIVE1_INT54      0x00400000  // Interrupt 54 active
-#define NVIC_ACTIVE1_INT53      0x00200000  // Interrupt 53 active
-#define NVIC_ACTIVE1_INT52      0x00100000  // Interrupt 52 active
-#define NVIC_ACTIVE1_INT51      0x00080000  // Interrupt 51 active
-#define NVIC_ACTIVE1_INT50      0x00040000  // Interrupt 50 active
-#define NVIC_ACTIVE1_INT49      0x00020000  // Interrupt 49 active
-#define NVIC_ACTIVE1_INT48      0x00010000  // Interrupt 48 active
-#define NVIC_ACTIVE1_INT47      0x00008000  // Interrupt 47 active
-#define NVIC_ACTIVE1_INT46      0x00004000  // Interrupt 46 active
-#define NVIC_ACTIVE1_INT45      0x00002000  // Interrupt 45 active
-#define NVIC_ACTIVE1_INT44      0x00001000  // Interrupt 44 active
-#define NVIC_ACTIVE1_INT43      0x00000800  // Interrupt 43 active
-#define NVIC_ACTIVE1_INT42      0x00000400  // Interrupt 42 active
-#define NVIC_ACTIVE1_INT41      0x00000200  // Interrupt 41 active
-#define NVIC_ACTIVE1_INT40      0x00000100  // Interrupt 40 active
-#define NVIC_ACTIVE1_INT39      0x00000080  // Interrupt 39 active
-#define NVIC_ACTIVE1_INT38      0x00000040  // Interrupt 38 active
-#define NVIC_ACTIVE1_INT37      0x00000020  // Interrupt 37 active
-#define NVIC_ACTIVE1_INT36      0x00000010  // Interrupt 36 active
-#define NVIC_ACTIVE1_INT35      0x00000008  // Interrupt 35 active
-#define NVIC_ACTIVE1_INT34      0x00000004  // Interrupt 34 active
-#define NVIC_ACTIVE1_INT33      0x00000002  // Interrupt 33 active
+#define NVIC_ACTIVE1_INT_M      0x00000FFF  // Interrupt Active
 #define NVIC_ACTIVE1_INT32      0x00000001  // Interrupt 32 active
+#define NVIC_ACTIVE1_INT33      0x00000002  // Interrupt 33 active
+#define NVIC_ACTIVE1_INT34      0x00000004  // Interrupt 34 active
+#define NVIC_ACTIVE1_INT35      0x00000008  // Interrupt 35 active
+#define NVIC_ACTIVE1_INT36      0x00000010  // Interrupt 36 active
+#define NVIC_ACTIVE1_INT37      0x00000020  // Interrupt 37 active
+#define NVIC_ACTIVE1_INT38      0x00000040  // Interrupt 38 active
+#define NVIC_ACTIVE1_INT39      0x00000080  // Interrupt 39 active
+#define NVIC_ACTIVE1_INT40      0x00000100  // Interrupt 40 active
+#define NVIC_ACTIVE1_INT41      0x00000200  // Interrupt 41 active
+#define NVIC_ACTIVE1_INT42      0x00000400  // Interrupt 42 active
+#define NVIC_ACTIVE1_INT43      0x00000800  // Interrupt 43 active
+#define NVIC_ACTIVE1_INT44      0x00001000  // Interrupt 44 active
+#define NVIC_ACTIVE1_INT45      0x00002000  // Interrupt 45 active
+#define NVIC_ACTIVE1_INT46      0x00004000  // Interrupt 46 active
+#define NVIC_ACTIVE1_INT47      0x00008000  // Interrupt 47 active
+#define NVIC_ACTIVE1_INT48      0x00010000  // Interrupt 48 active
+#define NVIC_ACTIVE1_INT49      0x00020000  // Interrupt 49 active
+#define NVIC_ACTIVE1_INT50      0x00040000  // Interrupt 50 active
+#define NVIC_ACTIVE1_INT51      0x00080000  // Interrupt 51 active
+#define NVIC_ACTIVE1_INT52      0x00100000  // Interrupt 52 active
+#define NVIC_ACTIVE1_INT53      0x00200000  // Interrupt 53 active
+#define NVIC_ACTIVE1_INT54      0x00400000  // Interrupt 54 active
+#define NVIC_ACTIVE1_INT55      0x00800000  // Interrupt 55 active
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_PRI0 register.
 //
 //*****************************************************************************
-#define NVIC_PRI0_INT3_M        0xFF000000  // Interrupt 3 priority mask
-#define NVIC_PRI0_INT2_M        0x00FF0000  // Interrupt 2 priority mask
-#define NVIC_PRI0_INT1_M        0x0000FF00  // Interrupt 1 priority mask
-#define NVIC_PRI0_INT0_M        0x000000FF  // Interrupt 0 priority mask
-#define NVIC_PRI0_INT3_S        24
-#define NVIC_PRI0_INT2_S        16
-#define NVIC_PRI0_INT1_S        8
-#define NVIC_PRI0_INT0_S        0
+#define NVIC_PRI0_INT3_M        0xE0000000  // Interrupt 3 Priority Mask
+#define NVIC_PRI0_INT2_M        0x00E00000  // Interrupt 2 Priority Mask
+#define NVIC_PRI0_INT1_M        0x0000E000  // Interrupt 1 Priority Mask
+#define NVIC_PRI0_INT0_M        0x000000E0  // Interrupt 0 Priority Mask
+#define NVIC_PRI0_INT3_S        29
+#define NVIC_PRI0_INT2_S        21
+#define NVIC_PRI0_INT1_S        13
+#define NVIC_PRI0_INT0_S        5
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_PRI1 register.
 //
 //*****************************************************************************
-#define NVIC_PRI1_INT7_M        0xFF000000  // Interrupt 7 priority mask
-#define NVIC_PRI1_INT6_M        0x00FF0000  // Interrupt 6 priority mask
-#define NVIC_PRI1_INT5_M        0x0000FF00  // Interrupt 5 priority mask
-#define NVIC_PRI1_INT4_M        0x000000FF  // Interrupt 4 priority mask
-#define NVIC_PRI1_INT7_S        24
-#define NVIC_PRI1_INT6_S        16
-#define NVIC_PRI1_INT5_S        8
-#define NVIC_PRI1_INT4_S        0
+#define NVIC_PRI1_INT7_M        0xE0000000  // Interrupt 7 Priority Mask
+#define NVIC_PRI1_INT6_M        0x00E00000  // Interrupt 6 Priority Mask
+#define NVIC_PRI1_INT5_M        0x0000E000  // Interrupt 5 Priority Mask
+#define NVIC_PRI1_INT4_M        0x000000E0  // Interrupt 4 Priority Mask
+#define NVIC_PRI1_INT7_S        29
+#define NVIC_PRI1_INT6_S        21
+#define NVIC_PRI1_INT5_S        13
+#define NVIC_PRI1_INT4_S        5
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_PRI2 register.
 //
 //*****************************************************************************
-#define NVIC_PRI2_INT11_M       0xFF000000  // Interrupt 11 priority mask
-#define NVIC_PRI2_INT10_M       0x00FF0000  // Interrupt 10 priority mask
-#define NVIC_PRI2_INT9_M        0x0000FF00  // Interrupt 9 priority mask
-#define NVIC_PRI2_INT8_M        0x000000FF  // Interrupt 8 priority mask
-#define NVIC_PRI2_INT11_S       24
-#define NVIC_PRI2_INT10_S       16
-#define NVIC_PRI2_INT9_S        8
-#define NVIC_PRI2_INT8_S        0
+#define NVIC_PRI2_INT11_M       0xE0000000  // Interrupt 11 Priority Mask
+#define NVIC_PRI2_INT10_M       0x00E00000  // Interrupt 10 Priority Mask
+#define NVIC_PRI2_INT9_M        0x0000E000  // Interrupt 9 Priority Mask
+#define NVIC_PRI2_INT8_M        0x000000E0  // Interrupt 8 Priority Mask
+#define NVIC_PRI2_INT11_S       29
+#define NVIC_PRI2_INT10_S       21
+#define NVIC_PRI2_INT9_S        13
+#define NVIC_PRI2_INT8_S        5
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_PRI3 register.
 //
 //*****************************************************************************
-#define NVIC_PRI3_INT15_M       0xFF000000  // Interrupt 15 priority mask
-#define NVIC_PRI3_INT14_M       0x00FF0000  // Interrupt 14 priority mask
-#define NVIC_PRI3_INT13_M       0x0000FF00  // Interrupt 13 priority mask
-#define NVIC_PRI3_INT12_M       0x000000FF  // Interrupt 12 priority mask
-#define NVIC_PRI3_INT15_S       24
-#define NVIC_PRI3_INT14_S       16
-#define NVIC_PRI3_INT13_S       8
-#define NVIC_PRI3_INT12_S       0
+#define NVIC_PRI3_INT15_M       0xE0000000  // Interrupt 15 Priority Mask
+#define NVIC_PRI3_INT14_M       0x00E00000  // Interrupt 14 Priority Mask
+#define NVIC_PRI3_INT13_M       0x0000E000  // Interrupt 13 Priority Mask
+#define NVIC_PRI3_INT12_M       0x000000E0  // Interrupt 12 Priority Mask
+#define NVIC_PRI3_INT15_S       29
+#define NVIC_PRI3_INT14_S       21
+#define NVIC_PRI3_INT13_S       13
+#define NVIC_PRI3_INT12_S       5
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_PRI4 register.
 //
 //*****************************************************************************
-#define NVIC_PRI4_INT19_M       0xFF000000  // Interrupt 19 priority mask
-#define NVIC_PRI4_INT18_M       0x00FF0000  // Interrupt 18 priority mask
-#define NVIC_PRI4_INT17_M       0x0000FF00  // Interrupt 17 priority mask
-#define NVIC_PRI4_INT16_M       0x000000FF  // Interrupt 16 priority mask
-#define NVIC_PRI4_INT19_S       24
-#define NVIC_PRI4_INT18_S       16
-#define NVIC_PRI4_INT17_S       8
-#define NVIC_PRI4_INT16_S       0
+#define NVIC_PRI4_INT19_M       0xE0000000  // Interrupt 19 Priority Mask
+#define NVIC_PRI4_INT18_M       0x00E00000  // Interrupt 18 Priority Mask
+#define NVIC_PRI4_INT17_M       0x0000E000  // Interrupt 17 Priority Mask
+#define NVIC_PRI4_INT16_M       0x000000E0  // Interrupt 16 Priority Mask
+#define NVIC_PRI4_INT19_S       29
+#define NVIC_PRI4_INT18_S       21
+#define NVIC_PRI4_INT17_S       13
+#define NVIC_PRI4_INT16_S       5
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_PRI5 register.
 //
 //*****************************************************************************
-#define NVIC_PRI5_INT23_M       0xFF000000  // Interrupt 23 priority mask
-#define NVIC_PRI5_INT22_M       0x00FF0000  // Interrupt 22 priority mask
-#define NVIC_PRI5_INT21_M       0x0000FF00  // Interrupt 21 priority mask
-#define NVIC_PRI5_INT20_M       0x000000FF  // Interrupt 20 priority mask
-#define NVIC_PRI5_INT23_S       24
-#define NVIC_PRI5_INT22_S       16
-#define NVIC_PRI5_INT21_S       8
-#define NVIC_PRI5_INT20_S       0
+#define NVIC_PRI5_INT23_M       0xE0000000  // Interrupt 23 Priority Mask
+#define NVIC_PRI5_INT22_M       0x00E00000  // Interrupt 22 Priority Mask
+#define NVIC_PRI5_INT21_M       0x0000E000  // Interrupt 21 Priority Mask
+#define NVIC_PRI5_INT20_M       0x000000E0  // Interrupt 20 Priority Mask
+#define NVIC_PRI5_INT23_S       29
+#define NVIC_PRI5_INT22_S       21
+#define NVIC_PRI5_INT21_S       13
+#define NVIC_PRI5_INT20_S       5
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_PRI6 register.
 //
 //*****************************************************************************
-#define NVIC_PRI6_INT27_M       0xFF000000  // Interrupt 27 priority mask
-#define NVIC_PRI6_INT26_M       0x00FF0000  // Interrupt 26 priority mask
-#define NVIC_PRI6_INT25_M       0x0000FF00  // Interrupt 25 priority mask
-#define NVIC_PRI6_INT24_M       0x000000FF  // Interrupt 24 priority mask
-#define NVIC_PRI6_INT27_S       24
-#define NVIC_PRI6_INT26_S       16
-#define NVIC_PRI6_INT25_S       8
-#define NVIC_PRI6_INT24_S       0
+#define NVIC_PRI6_INT27_M       0xE0000000  // Interrupt 27 Priority Mask
+#define NVIC_PRI6_INT26_M       0x00E00000  // Interrupt 26 Priority Mask
+#define NVIC_PRI6_INT25_M       0x0000E000  // Interrupt 25 Priority Mask
+#define NVIC_PRI6_INT24_M       0x000000E0  // Interrupt 24 Priority Mask
+#define NVIC_PRI6_INT27_S       29
+#define NVIC_PRI6_INT26_S       21
+#define NVIC_PRI6_INT25_S       13
+#define NVIC_PRI6_INT24_S       5
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_PRI7 register.
 //
 //*****************************************************************************
-#define NVIC_PRI7_INT31_M       0xFF000000  // Interrupt 31 priority mask
-#define NVIC_PRI7_INT30_M       0x00FF0000  // Interrupt 30 priority mask
-#define NVIC_PRI7_INT29_M       0x0000FF00  // Interrupt 29 priority mask
-#define NVIC_PRI7_INT28_M       0x000000FF  // Interrupt 28 priority mask
-#define NVIC_PRI7_INT31_S       24
-#define NVIC_PRI7_INT30_S       16
-#define NVIC_PRI7_INT29_S       8
-#define NVIC_PRI7_INT28_S       0
+#define NVIC_PRI7_INT31_M       0xE0000000  // Interrupt 31 Priority Mask
+#define NVIC_PRI7_INT30_M       0x00E00000  // Interrupt 30 Priority Mask
+#define NVIC_PRI7_INT29_M       0x0000E000  // Interrupt 29 Priority Mask
+#define NVIC_PRI7_INT28_M       0x000000E0  // Interrupt 28 Priority Mask
+#define NVIC_PRI7_INT31_S       29
+#define NVIC_PRI7_INT30_S       21
+#define NVIC_PRI7_INT29_S       13
+#define NVIC_PRI7_INT28_S       5
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_PRI8 register.
 //
 //*****************************************************************************
-#define NVIC_PRI8_INT35_M       0xFF000000  // Interrupt 35 priority mask
-#define NVIC_PRI8_INT34_M       0x00FF0000  // Interrupt 34 priority mask
-#define NVIC_PRI8_INT33_M       0x0000FF00  // Interrupt 33 priority mask
-#define NVIC_PRI8_INT32_M       0x000000FF  // Interrupt 32 priority mask
-#define NVIC_PRI8_INT35_S       24
-#define NVIC_PRI8_INT34_S       16
-#define NVIC_PRI8_INT33_S       8
-#define NVIC_PRI8_INT32_S       0
+#define NVIC_PRI8_INT35_M       0xE0000000  // Interrupt 35 Priority Mask
+#define NVIC_PRI8_INT34_M       0x00E00000  // Interrupt 34 Priority Mask
+#define NVIC_PRI8_INT33_M       0x0000E000  // Interrupt 33 Priority Mask
+#define NVIC_PRI8_INT32_M       0x000000E0  // Interrupt 32 Priority Mask
+#define NVIC_PRI8_INT35_S       29
+#define NVIC_PRI8_INT34_S       21
+#define NVIC_PRI8_INT33_S       13
+#define NVIC_PRI8_INT32_S       5
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_PRI9 register.
 //
 //*****************************************************************************
-#define NVIC_PRI9_INT39_M       0xFF000000  // Interrupt 39 priority mask
-#define NVIC_PRI9_INT38_M       0x00FF0000  // Interrupt 38 priority mask
-#define NVIC_PRI9_INT37_M       0x0000FF00  // Interrupt 37 priority mask
-#define NVIC_PRI9_INT36_M       0x000000FF  // Interrupt 36 priority mask
-#define NVIC_PRI9_INT39_S       24
-#define NVIC_PRI9_INT38_S       16
-#define NVIC_PRI9_INT37_S       8
-#define NVIC_PRI9_INT36_S       0
+#define NVIC_PRI9_INT39_M       0xE0000000  // Interrupt 39 Priority Mask
+#define NVIC_PRI9_INT38_M       0x00E00000  // Interrupt 38 Priority Mask
+#define NVIC_PRI9_INT37_M       0x0000E000  // Interrupt 37 Priority Mask
+#define NVIC_PRI9_INT36_M       0x000000E0  // Interrupt 36 Priority Mask
+#define NVIC_PRI9_INT39_S       29
+#define NVIC_PRI9_INT38_S       21
+#define NVIC_PRI9_INT37_S       13
+#define NVIC_PRI9_INT36_S       5
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_PRI10 register.
 //
 //*****************************************************************************
-#define NVIC_PRI10_INT43_M      0xFF000000  // Interrupt 43 priority mask
-#define NVIC_PRI10_INT42_M      0x00FF0000  // Interrupt 42 priority mask
-#define NVIC_PRI10_INT41_M      0x0000FF00  // Interrupt 41 priority mask
-#define NVIC_PRI10_INT40_M      0x000000FF  // Interrupt 40 priority mask
-#define NVIC_PRI10_INT43_S      24
-#define NVIC_PRI10_INT42_S      16
-#define NVIC_PRI10_INT41_S      8
-#define NVIC_PRI10_INT40_S      0
+#define NVIC_PRI10_INT43_M      0xE0000000  // Interrupt 43 Priority Mask
+#define NVIC_PRI10_INT42_M      0x00E00000  // Interrupt 42 Priority Mask
+#define NVIC_PRI10_INT41_M      0x0000E000  // Interrupt 41 Priority Mask
+#define NVIC_PRI10_INT40_M      0x000000E0  // Interrupt 40 Priority Mask
+#define NVIC_PRI10_INT43_S      29
+#define NVIC_PRI10_INT42_S      21
+#define NVIC_PRI10_INT41_S      13
+#define NVIC_PRI10_INT40_S      5
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_CPUID register.
 //
 //*****************************************************************************
-#define NVIC_CPUID_IMP_M        0xFF000000  // Implementer
-#define NVIC_CPUID_VAR_M        0x00F00000  // Variant
-#define NVIC_CPUID_PARTNO_M     0x0000FFF0  // Processor part number
-#define NVIC_CPUID_REV_M        0x0000000F  // Revision
+#define NVIC_CPUID_IMP_M        0xFF000000  // Implementer Code
+#define NVIC_CPUID_IMP_ARM      0x41000000  // ARM
+#define NVIC_CPUID_VAR_M        0x00F00000  // Variant Number
+#define NVIC_CPUID_CON_M        0x000F0000  // Constant
+#define NVIC_CPUID_PARTNO_M     0x0000FFF0  // Part Number
+#define NVIC_CPUID_PARTNO_CM3   0x0000C230  // Cortex-M3 processor
+#define NVIC_CPUID_REV_M        0x0000000F  // Revision Number
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_INT_CTRL register.
 //
 //*****************************************************************************
-#define NVIC_INT_CTRL_NMI_SET   0x80000000  // Pend a NMI
-#define NVIC_INT_CTRL_PEND_SV   0x10000000  // Pend a PendSV
-#define NVIC_INT_CTRL_UNPEND_SV 0x08000000  // Unpend a PendSV
-#define NVIC_INT_CTRL_ISR_PRE   0x00800000  // Debug interrupt handling
-#define NVIC_INT_CTRL_ISR_PEND  0x00400000  // Debug interrupt pending
-#define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000  // Highest pending exception
-#define NVIC_INT_CTRL_RET_BASE  0x00000800  // Return to base
-#define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF  // Current active exception
-#define NVIC_INT_CTRL_VEC_PEN_S 12
+#define NVIC_INT_CTRL_NMI_SET   0x80000000  // NMI Set Pending
+#define NVIC_INT_CTRL_PEND_SV   0x10000000  // PendSV Set Pending
+#define NVIC_INT_CTRL_UNPEND_SV 0x08000000  // PendSV Clear Pending
+#define NVIC_INT_CTRL_PENDSTSET 0x04000000  // SysTick Set Pending
+#define NVIC_INT_CTRL_PENDSTCLR 0x02000000  // SysTick Clear Pending
+#define NVIC_INT_CTRL_ISR_PRE   0x00800000  // Debug Interrupt Handling
+#define NVIC_INT_CTRL_ISR_PEND  0x00400000  // Interrupt Pending
+#define NVIC_INT_CTRL_VEC_PEN_M 0x0003F000  // Interrupt Pending Vector Number
+#define NVIC_INT_CTRL_VEC_PEN_NMI \
+                                0x00002000  // NMI
+#define NVIC_INT_CTRL_VEC_PEN_HARD \
+                                0x00003000  // Hard fault
+#define NVIC_INT_CTRL_VEC_PEN_MEM \
+                                0x00004000  // Memory management fault
+#define NVIC_INT_CTRL_VEC_PEN_BUS \
+                                0x00005000  // Bus fault
+#define NVIC_INT_CTRL_VEC_PEN_USG \
+                                0x00006000  // Usage fault
+#define NVIC_INT_CTRL_VEC_PEN_SVC \
+                                0x0000B000  // SVCall
+#define NVIC_INT_CTRL_VEC_PEN_PNDSV \
+                                0x0000E000  // PendSV
+#define NVIC_INT_CTRL_VEC_PEN_TICK \
+                                0x0000F000  // SysTick
+#define NVIC_INT_CTRL_RET_BASE  0x00000800  // Return to Base
+#define NVIC_INT_CTRL_VEC_ACT_M 0x0000003F  // Interrupt Pending Vector Number
 #define NVIC_INT_CTRL_VEC_ACT_S 0
 
 //*****************************************************************************
@@ -3687,8 +3717,8 @@
 // The following are defines for the bit fields in the NVIC_VTABLE register.
 //
 //*****************************************************************************
-#define NVIC_VTABLE_BASE        0x20000000  // Vector table base
-#define NVIC_VTABLE_OFFSET_M    0x1FFFFF00  // Vector table offset
+#define NVIC_VTABLE_BASE        0x20000000  // Vector Table Base
+#define NVIC_VTABLE_OFFSET_M    0x1FFFFF00  // Vector Table Offset
 #define NVIC_VTABLE_OFFSET_S    8
 
 //*****************************************************************************
@@ -3696,77 +3726,76 @@
 // The following are defines for the bit fields in the NVIC_APINT register.
 //
 //*****************************************************************************
-#define NVIC_APINT_VECTKEY_M    0xFFFF0000  // Vector key mask
+#define NVIC_APINT_VECTKEY_M    0xFFFF0000  // Register Key
 #define NVIC_APINT_VECTKEY      0x05FA0000  // Vector key
-#define NVIC_APINT_ENDIANESS    0x00008000  // Data endianess
-#define NVIC_APINT_PRIGROUP_M   0x00000700  // Priority group
-#define NVIC_APINT_PRIGROUP_0_8 0x00000700  // Priority group 0.8 split
-#define NVIC_APINT_PRIGROUP_1_7 0x00000600  // Priority group 1.7 split
-#define NVIC_APINT_PRIGROUP_2_6 0x00000500  // Priority group 2.6 split
-#define NVIC_APINT_PRIGROUP_3_5 0x00000400  // Priority group 3.5 split
-#define NVIC_APINT_PRIGROUP_4_4 0x00000300  // Priority group 4.4 split
-#define NVIC_APINT_PRIGROUP_5_3 0x00000200  // Priority group 5.3 split
-#define NVIC_APINT_PRIGROUP_6_2 0x00000100  // Priority group 6.2 split
-#define NVIC_APINT_SYSRESETREQ  0x00000004  // System reset request
-#define NVIC_APINT_VECT_CLR_ACT 0x00000002  // Clear active NMI/fault info
-#define NVIC_APINT_VECT_RESET   0x00000001  // System reset
+#define NVIC_APINT_ENDIANESS    0x00008000  // Data Endianess
+#define NVIC_APINT_PRIGROUP_M   0x00000700  // Interrupt Priority Grouping
 #define NVIC_APINT_PRIGROUP_7_1 0x00000000  // Priority group 7.1 split
+#define NVIC_APINT_PRIGROUP_6_2 0x00000100  // Priority group 6.2 split
+#define NVIC_APINT_PRIGROUP_5_3 0x00000200  // Priority group 5.3 split
+#define NVIC_APINT_PRIGROUP_4_4 0x00000300  // Priority group 4.4 split
+#define NVIC_APINT_PRIGROUP_3_5 0x00000400  // Priority group 3.5 split
+#define NVIC_APINT_PRIGROUP_2_6 0x00000500  // Priority group 2.6 split
+#define NVIC_APINT_PRIGROUP_1_7 0x00000600  // Priority group 1.7 split
+#define NVIC_APINT_PRIGROUP_0_8 0x00000700  // Priority group 0.8 split
+#define NVIC_APINT_SYSRESETREQ  0x00000004  // System Reset Request
+#define NVIC_APINT_VECT_CLR_ACT 0x00000002  // Clear Active NMI / Fault
+#define NVIC_APINT_VECT_RESET   0x00000001  // System Reset
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_SYS_CTRL register.
 //
 //*****************************************************************************
-#define NVIC_SYS_CTRL_SEVONPEND 0x00000010  // Wakeup on pend
-#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004  // Deep sleep enable
-#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002  // Sleep on ISR exit
+#define NVIC_SYS_CTRL_SEVONPEND 0x00000010  // Wake Up on Pending
+#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004  // Deep Sleep Enable
+#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002  // Sleep on ISR Exit
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_CFG_CTRL register.
 //
 //*****************************************************************************
-#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100  // Ignore bus fault in NMI/fault
-#define NVIC_CFG_CTRL_DIV0      0x00000010  // Trap on divide by 0
-#define NVIC_CFG_CTRL_UNALIGNED 0x00000008  // Trap on unaligned access
-#define NVIC_CFG_CTRL_DEEP_PEND 0x00000004  // Allow deep interrupt trigger
-#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002  // Allow main interrupt trigger
-#define NVIC_CFG_CTRL_BASE_THR  0x00000001  // Thread state control
+#define NVIC_CFG_CTRL_STKALIGN  0x00000200  // Stack Alignment on Exception
+                                            // Entry
+#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100  // Ignore Bus Fault in NMI and
+                                            // Fault
+#define NVIC_CFG_CTRL_DIV0      0x00000010  // Trap on Divide by 0
+#define NVIC_CFG_CTRL_UNALIGNED 0x00000008  // Trap on Unaligned Access
+#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002  // Allow Main Interrupt Trigger
+#define NVIC_CFG_CTRL_BASE_THR  0x00000001  // Thread State Control
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_SYS_PRI1 register.
 //
 //*****************************************************************************
-#define NVIC_SYS_PRI1_RES_M     0xFF000000  // Priority of reserved handler
-#define NVIC_SYS_PRI1_USAGE_M   0x00FF0000  // Priority of usage fault handler
-#define NVIC_SYS_PRI1_BUS_M     0x0000FF00  // Priority of bus fault handler
-#define NVIC_SYS_PRI1_MEM_M     0x000000FF  // Priority of mem manage handler
-#define NVIC_SYS_PRI1_USAGE_S   16
-#define NVIC_SYS_PRI1_BUS_S     8
-#define NVIC_SYS_PRI1_MEM_S     0
+#define NVIC_SYS_PRI1_USAGE_M   0x00E00000  // Usage Fault Priority
+#define NVIC_SYS_PRI1_BUS_M     0x0000E000  // Bus Fault Priority
+#define NVIC_SYS_PRI1_MEM_M     0x000000E0  // Memory Management Fault Priority
+#define NVIC_SYS_PRI1_USAGE_S   21
+#define NVIC_SYS_PRI1_BUS_S     13
+#define NVIC_SYS_PRI1_MEM_S     5
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_SYS_PRI2 register.
 //
 //*****************************************************************************
-#define NVIC_SYS_PRI2_SVC_M     0xFF000000  // Priority of SVCall handler
-#define NVIC_SYS_PRI2_RES_M     0x00FFFFFF  // Priority of reserved handlers
-#define NVIC_SYS_PRI2_SVC_S     24
+#define NVIC_SYS_PRI2_SVC_M     0xE0000000  // SVCall Priority
+#define NVIC_SYS_PRI2_SVC_S     29
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_SYS_PRI3 register.
 //
 //*****************************************************************************
-#define NVIC_SYS_PRI3_TICK_M    0xFF000000  // Priority of Sys Tick handler
-#define NVIC_SYS_PRI3_PENDSV_M  0x00FF0000  // Priority of PendSV handler
-#define NVIC_SYS_PRI3_RES_M     0x0000FF00  // Priority of reserved handler
-#define NVIC_SYS_PRI3_DEBUG_M   0x000000FF  // Priority of debug handler
-#define NVIC_SYS_PRI3_TICK_S    24
-#define NVIC_SYS_PRI3_PENDSV_S  16
-#define NVIC_SYS_PRI3_DEBUG_S   0
+#define NVIC_SYS_PRI3_TICK_M    0xE0000000  // SysTick Exception Priority
+#define NVIC_SYS_PRI3_PENDSV_M  0x00E00000  // PendSV Priority
+#define NVIC_SYS_PRI3_DEBUG_M   0x000000E0  // Debug Priority
+#define NVIC_SYS_PRI3_TICK_S    29
+#define NVIC_SYS_PRI3_PENDSV_S  21
+#define NVIC_SYS_PRI3_DEBUG_S   5
 
 //*****************************************************************************
 //
@@ -3774,18 +3803,21 @@
 // register.
 //
 //*****************************************************************************
-#define NVIC_SYS_HND_CTRL_USAGE 0x00040000  // Usage fault enable
-#define NVIC_SYS_HND_CTRL_BUS   0x00020000  // Bus fault enable
-#define NVIC_SYS_HND_CTRL_MEM   0x00010000  // Mem manage fault enable
-#define NVIC_SYS_HND_CTRL_SVC   0x00008000  // SVCall is pended
-#define NVIC_SYS_HND_CTRL_BUSP  0x00004000  // Bus fault is pended
-#define NVIC_SYS_HND_CTRL_TICK  0x00000800  // Sys tick is active
-#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400  // PendSV is active
-#define NVIC_SYS_HND_CTRL_MON   0x00000100  // Monitor is active
-#define NVIC_SYS_HND_CTRL_SVCA  0x00000080  // SVCall is active
-#define NVIC_SYS_HND_CTRL_USGA  0x00000008  // Usage fault is active
-#define NVIC_SYS_HND_CTRL_BUSA  0x00000002  // Bus fault is active
-#define NVIC_SYS_HND_CTRL_MEMA  0x00000001  // Mem manage is active
+#define NVIC_SYS_HND_CTRL_USAGE 0x00040000  // Usage Fault Enable
+#define NVIC_SYS_HND_CTRL_BUS   0x00020000  // Bus Fault Enable
+#define NVIC_SYS_HND_CTRL_MEM   0x00010000  // Memory Management Fault Enable
+#define NVIC_SYS_HND_CTRL_SVC   0x00008000  // SVC Call Pending
+#define NVIC_SYS_HND_CTRL_BUSP  0x00004000  // Bus Fault Pending
+#define NVIC_SYS_HND_CTRL_MEMP  0x00002000  // Memory Management Fault Pending
+#define NVIC_SYS_HND_CTRL_USAGEP \
+                                0x00001000  // Usage Fault Pending
+#define NVIC_SYS_HND_CTRL_TICK  0x00000800  // SysTick Exception Active
+#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400  // PendSV Exception Active
+#define NVIC_SYS_HND_CTRL_MON   0x00000100  // Debug Monitor Active
+#define NVIC_SYS_HND_CTRL_SVCA  0x00000080  // SVC Call Active
+#define NVIC_SYS_HND_CTRL_USGA  0x00000008  // Usage Fault Active
+#define NVIC_SYS_HND_CTRL_BUSA  0x00000002  // Bus Fault Active
+#define NVIC_SYS_HND_CTRL_MEMA  0x00000001  // Memory Management Fault Active
 
 //*****************************************************************************
 //
@@ -3793,23 +3825,25 @@
 // register.
 //
 //*****************************************************************************
-#define NVIC_FAULT_STAT_DIV0    0x02000000  // Divide by zero fault
-#define NVIC_FAULT_STAT_UNALIGN 0x01000000  // Unaligned access fault
-#define NVIC_FAULT_STAT_NOCP    0x00080000  // No coprocessor fault
-#define NVIC_FAULT_STAT_INVPC   0x00040000  // Invalid PC fault
-#define NVIC_FAULT_STAT_INVSTAT 0x00020000  // Invalid state fault
-#define NVIC_FAULT_STAT_UNDEF   0x00010000  // Undefined instruction fault
-#define NVIC_FAULT_STAT_BFARV   0x00008000  // BFAR is valid
-#define NVIC_FAULT_STAT_BSTKE   0x00001000  // Stack bus fault
-#define NVIC_FAULT_STAT_BUSTKE  0x00000800  // Unstack bus fault
-#define NVIC_FAULT_STAT_IMPRE   0x00000400  // Imprecise data bus error
-#define NVIC_FAULT_STAT_PRECISE 0x00000200  // Precise data bus error
-#define NVIC_FAULT_STAT_IBUS    0x00000100  // Instruction bus fault
-#define NVIC_FAULT_STAT_MMARV   0x00000080  // MMAR is valid
-#define NVIC_FAULT_STAT_MSTKE   0x00000010  // Stack access violation
-#define NVIC_FAULT_STAT_MUSTKE  0x00000008  // Unstack access violation
-#define NVIC_FAULT_STAT_DERR    0x00000002  // Data access violation
-#define NVIC_FAULT_STAT_IERR    0x00000001  // Instruction access violation
+#define NVIC_FAULT_STAT_DIV0    0x02000000  // Divide-by-Zero Usage Fault
+#define NVIC_FAULT_STAT_UNALIGN 0x01000000  // Unaligned Access Usage Fault
+#define NVIC_FAULT_STAT_NOCP    0x00080000  // No Coprocessor Usage Fault
+#define NVIC_FAULT_STAT_INVPC   0x00040000  // Invalid PC Load Usage Fault
+#define NVIC_FAULT_STAT_INVSTAT 0x00020000  // Invalid State Usage Fault
+#define NVIC_FAULT_STAT_UNDEF   0x00010000  // Undefined Instruction Usage
+                                            // Fault
+#define NVIC_FAULT_STAT_BFARV   0x00008000  // Bus Fault Address Register Valid
+#define NVIC_FAULT_STAT_BSTKE   0x00001000  // Stack Bus Fault
+#define NVIC_FAULT_STAT_BUSTKE  0x00000800  // Unstack Bus Fault
+#define NVIC_FAULT_STAT_IMPRE   0x00000400  // Imprecise Data Bus Error
+#define NVIC_FAULT_STAT_PRECISE 0x00000200  // Precise Data Bus Error
+#define NVIC_FAULT_STAT_IBUS    0x00000100  // Instruction Bus Error
+#define NVIC_FAULT_STAT_MMARV   0x00000080  // Memory Management Fault Address
+                                            // Register Valid
+#define NVIC_FAULT_STAT_MSTKE   0x00000010  // Stack Access Violation
+#define NVIC_FAULT_STAT_MUSTKE  0x00000008  // Unstack Access Violation
+#define NVIC_FAULT_STAT_DERR    0x00000002  // Data Access Violation
+#define NVIC_FAULT_STAT_IERR    0x00000001  // Instruction Access Violation
 
 //*****************************************************************************
 //
@@ -3817,9 +3851,9 @@
 // register.
 //
 //*****************************************************************************
-#define NVIC_HFAULT_STAT_DBG    0x80000000  // Debug event
-#define NVIC_HFAULT_STAT_FORCED 0x40000000  // Cannot execute fault handler
-#define NVIC_HFAULT_STAT_VECT   0x00000002  // Vector table read fault
+#define NVIC_HFAULT_STAT_DBG    0x80000000  // Debug Event
+#define NVIC_HFAULT_STAT_FORCED 0x40000000  // Forced Hard Fault
+#define NVIC_HFAULT_STAT_VECT   0x00000002  // Vector Table Read Fault
 
 //*****************************************************************************
 //
@@ -3838,7 +3872,7 @@
 // The following are defines for the bit fields in the NVIC_MM_ADDR register.
 //
 //*****************************************************************************
-#define NVIC_MM_ADDR_M          0xFFFFFFFF  // Data fault address
+#define NVIC_MM_ADDR_M          0xFFFFFFFF  // Fault Address
 #define NVIC_MM_ADDR_S          0
 
 //*****************************************************************************
@@ -3847,7 +3881,7 @@
 // register.
 //
 //*****************************************************************************
-#define NVIC_FAULT_ADDR_M       0xFFFFFFFF  // Data bus fault address
+#define NVIC_FAULT_ADDR_M       0xFFFFFFFF  // Fault Address
 #define NVIC_FAULT_ADDR_S       0
 
 //*****************************************************************************
@@ -3855,9 +3889,9 @@
 // The following are defines for the bit fields in the NVIC_MPU_TYPE register.
 //
 //*****************************************************************************
-#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000  // Number of I regions
-#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00  // Number of D regions
-#define NVIC_MPU_TYPE_SEPARATE  0x00000001  // Separate or unified MPU
+#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000  // Number of I Regions
+#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00  // Number of D Regions
+#define NVIC_MPU_TYPE_SEPARATE  0x00000001  // Separate or Unified MPU
 #define NVIC_MPU_TYPE_IREGION_S 16
 #define NVIC_MPU_TYPE_DREGION_S 8
 
@@ -3866,9 +3900,9 @@
 // The following are defines for the bit fields in the NVIC_MPU_CTRL register.
 //
 //*****************************************************************************
-#define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004  // MPU default region in priv mode
-#define NVIC_MPU_CTRL_HFNMIENA  0x00000002  // MPU enabled during faults
-#define NVIC_MPU_CTRL_ENABLE    0x00000001  // MPU enable
+#define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004  // MPU Default Region
+#define NVIC_MPU_CTRL_HFNMIENA  0x00000002  // MPU Enabled During Faults
+#define NVIC_MPU_CTRL_ENABLE    0x00000001  // MPU Enable
 
 //*****************************************************************************
 //
@@ -3876,7 +3910,7 @@
 // register.
 //
 //*****************************************************************************
-#define NVIC_MPU_NUMBER_M       0x000000FF  // MPU region to access
+#define NVIC_MPU_NUMBER_M       0x00000007  // MPU Region to Access
 #define NVIC_MPU_NUMBER_S       0
 
 //*****************************************************************************
@@ -3884,10 +3918,10 @@
 // The following are defines for the bit fields in the NVIC_MPU_BASE register.
 //
 //*****************************************************************************
-#define NVIC_MPU_BASE_ADDR_M    0xFFFFFFE0  // Base address mask
-#define NVIC_MPU_BASE_VALID     0x00000010  // Region number valid
-#define NVIC_MPU_BASE_REGION_M  0x0000000F  // Region number
-#define NVIC_MPU_BASE_ADDR_S    8
+#define NVIC_MPU_BASE_ADDR_M    0xFFFFFFE0  // Base Address Mask
+#define NVIC_MPU_BASE_VALID     0x00000010  // Region Number Valid
+#define NVIC_MPU_BASE_REGION_M  0x00000007  // Region Number
+#define NVIC_MPU_BASE_ADDR_S    5
 #define NVIC_MPU_BASE_REGION_S  0
 
 //*****************************************************************************
@@ -3896,19 +3930,19 @@
 //
 //*****************************************************************************
 #define NVIC_MPU_ATTR_M         0xFFFF0000  // Attributes
+#define NVIC_MPU_ATTR_XN        0x10000000  // Instruction Access Disable
+#define NVIC_MPU_ATTR_AP_M      0x07000000  // Access Privilege
 #define NVIC_MPU_ATTR_AP_NO_NO  0x00000000  // prv: no access, usr: no access
-#define NVIC_MPU_ATTR_BUFFRABLE 0x00010000  // Bufferable
-#define NVIC_MPU_ATTR_CACHEABLE 0x00020000  // Cacheable
-#define NVIC_MPU_ATTR_SHAREABLE 0x00040000  // Shareable
-#define NVIC_MPU_ATTR_TEX_M     0x00380000  // Type extension mask
 #define NVIC_MPU_ATTR_AP_RW_NO  0x01000000  // prv: rw, usr: none
 #define NVIC_MPU_ATTR_AP_RW_RO  0x02000000  // prv: rw, usr: read-only
 #define NVIC_MPU_ATTR_AP_RW_RW  0x03000000  // prv: rw, usr: rw
 #define NVIC_MPU_ATTR_AP_RO_NO  0x05000000  // prv: ro, usr: none
 #define NVIC_MPU_ATTR_AP_RO_RO  0x06000000  // prv: ro, usr: ro
-#define NVIC_MPU_ATTR_AP_M      0x07000000  // Access permissions mask
-#define NVIC_MPU_ATTR_XN        0x10000000  // Execute disable
-#define NVIC_MPU_ATTR_SRD_M     0x0000FF00  // Sub-region disable mask
+#define NVIC_MPU_ATTR_TEX_M     0x00380000  // Type Extension Mask
+#define NVIC_MPU_ATTR_SHAREABLE 0x00040000  // Shareable
+#define NVIC_MPU_ATTR_CACHEABLE 0x00020000  // Cacheable
+#define NVIC_MPU_ATTR_BUFFRABLE 0x00010000  // Bufferable
+#define NVIC_MPU_ATTR_SRD_M     0x0000FF00  // Subregion Disable Bits
 #define NVIC_MPU_ATTR_SRD_0     0x00000100  // Sub-region 0 disable
 #define NVIC_MPU_ATTR_SRD_1     0x00000200  // Sub-region 1 disable
 #define NVIC_MPU_ATTR_SRD_2     0x00000400  // Sub-region 2 disable
@@ -3917,7 +3951,7 @@
 #define NVIC_MPU_ATTR_SRD_5     0x00002000  // Sub-region 5 disable
 #define NVIC_MPU_ATTR_SRD_6     0x00004000  // Sub-region 6 disable
 #define NVIC_MPU_ATTR_SRD_7     0x00008000  // Sub-region 7 disable
-#define NVIC_MPU_ATTR_SIZE_M    0x0000003E  // Region size mask
+#define NVIC_MPU_ATTR_SIZE_M    0x0000003E  // Region Size Mask
 #define NVIC_MPU_ATTR_SIZE_32B  0x00000008  // Region size 32 bytes
 #define NVIC_MPU_ATTR_SIZE_64B  0x0000000A  // Region size 64 bytes
 #define NVIC_MPU_ATTR_SIZE_128B 0x0000000C  // Region size 128 bytes
@@ -3946,7 +3980,94 @@
 #define NVIC_MPU_ATTR_SIZE_1G   0x0000003A  // Region size 1 Gbytes
 #define NVIC_MPU_ATTR_SIZE_2G   0x0000003C  // Region size 2 Gbytes
 #define NVIC_MPU_ATTR_SIZE_4G   0x0000003E  // Region size 4 Gbytes
-#define NVIC_MPU_ATTR_ENABLE    0x00000001  // Region enable
+#define NVIC_MPU_ATTR_ENABLE    0x00000001  // Region Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE1 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE1_ADDR_M   0xFFFFFFE0  // Base Address Mask
+#define NVIC_MPU_BASE1_VALID    0x00000010  // Region Number Valid
+#define NVIC_MPU_BASE1_REGION_M 0x00000007  // Region Number
+#define NVIC_MPU_BASE1_ADDR_S   5
+#define NVIC_MPU_BASE1_REGION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR1 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR1_XN       0x10000000  // Instruction Access Disable
+#define NVIC_MPU_ATTR1_AP_M     0x07000000  // Access Privilege
+#define NVIC_MPU_ATTR1_TEX_M    0x00380000  // Type Extension Mask
+#define NVIC_MPU_ATTR1_SHAREABLE \
+                                0x00040000  // Shareable
+#define NVIC_MPU_ATTR1_CACHEABLE \
+                                0x00020000  // Cacheable
+#define NVIC_MPU_ATTR1_BUFFRABLE \
+                                0x00010000  // Bufferable
+#define NVIC_MPU_ATTR1_SRD_M    0x0000FF00  // Subregion Disable Bits
+#define NVIC_MPU_ATTR1_SIZE_M   0x0000003E  // Region Size Mask
+#define NVIC_MPU_ATTR1_ENABLE   0x00000001  // Region Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE2 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE2_ADDR_M   0xFFFFFFE0  // Base Address Mask
+#define NVIC_MPU_BASE2_VALID    0x00000010  // Region Number Valid
+#define NVIC_MPU_BASE2_REGION_M 0x00000007  // Region Number
+#define NVIC_MPU_BASE2_ADDR_S   5
+#define NVIC_MPU_BASE2_REGION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR2 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR2_XN       0x10000000  // Instruction Access Disable
+#define NVIC_MPU_ATTR2_AP_M     0x07000000  // Access Privilege
+#define NVIC_MPU_ATTR2_TEX_M    0x00380000  // Type Extension Mask
+#define NVIC_MPU_ATTR2_SHAREABLE \
+                                0x00040000  // Shareable
+#define NVIC_MPU_ATTR2_CACHEABLE \
+                                0x00020000  // Cacheable
+#define NVIC_MPU_ATTR2_BUFFRABLE \
+                                0x00010000  // Bufferable
+#define NVIC_MPU_ATTR2_SRD_M    0x0000FF00  // Subregion Disable Bits
+#define NVIC_MPU_ATTR2_SIZE_M   0x0000003E  // Region Size Mask
+#define NVIC_MPU_ATTR2_ENABLE   0x00000001  // Region Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE3 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE3_ADDR_M   0xFFFFFFE0  // Base Address Mask
+#define NVIC_MPU_BASE3_VALID    0x00000010  // Region Number Valid
+#define NVIC_MPU_BASE3_REGION_M 0x00000007  // Region Number
+#define NVIC_MPU_BASE3_ADDR_S   5
+#define NVIC_MPU_BASE3_REGION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR3 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR3_XN       0x10000000  // Instruction Access Disable
+#define NVIC_MPU_ATTR3_AP_M     0x07000000  // Access Privilege
+#define NVIC_MPU_ATTR3_TEX_M    0x00380000  // Type Extension Mask
+#define NVIC_MPU_ATTR3_SHAREABLE \
+                                0x00040000  // Shareable
+#define NVIC_MPU_ATTR3_CACHEABLE \
+                                0x00020000  // Cacheable
+#define NVIC_MPU_ATTR3_BUFFRABLE \
+                                0x00010000  // Bufferable
+#define NVIC_MPU_ATTR3_SRD_M    0x0000FF00  // Subregion Disable Bits
+#define NVIC_MPU_ATTR3_SIZE_M   0x0000003E  // Region Size Mask
+#define NVIC_MPU_ATTR3_ENABLE   0x00000001  // Region Enable
 
 //*****************************************************************************
 //
@@ -3978,27 +4099,27 @@
 //*****************************************************************************
 #define NVIC_DBG_XFER_REG_WNR   0x00010000  // Write or not read
 #define NVIC_DBG_XFER_REG_SEL_M 0x0000001F  // Register
-#define NVIC_DBG_XFER_REG_CFBP  0x00000014  // Control/Fault/BasePri/PriMask
-#define NVIC_DBG_XFER_REG_DSP   0x00000013  // Deep SP
-#define NVIC_DBG_XFER_REG_PSP   0x00000012  // Process SP
-#define NVIC_DBG_XFER_REG_MSP   0x00000011  // Main SP
-#define NVIC_DBG_XFER_REG_FLAGS 0x00000010  // xPSR/Flags register
-#define NVIC_DBG_XFER_REG_R15   0x0000000F  // Register R15
-#define NVIC_DBG_XFER_REG_R14   0x0000000E  // Register R14
-#define NVIC_DBG_XFER_REG_R13   0x0000000D  // Register R13
-#define NVIC_DBG_XFER_REG_R12   0x0000000C  // Register R12
-#define NVIC_DBG_XFER_REG_R11   0x0000000B  // Register R11
-#define NVIC_DBG_XFER_REG_R10   0x0000000A  // Register R10
-#define NVIC_DBG_XFER_REG_R9    0x00000009  // Register R9
-#define NVIC_DBG_XFER_REG_R8    0x00000008  // Register R8
-#define NVIC_DBG_XFER_REG_R7    0x00000007  // Register R7
-#define NVIC_DBG_XFER_REG_R6    0x00000006  // Register R6
-#define NVIC_DBG_XFER_REG_R5    0x00000005  // Register R5
-#define NVIC_DBG_XFER_REG_R4    0x00000004  // Register R4
-#define NVIC_DBG_XFER_REG_R3    0x00000003  // Register R3
-#define NVIC_DBG_XFER_REG_R2    0x00000002  // Register R2
-#define NVIC_DBG_XFER_REG_R1    0x00000001  // Register R1
 #define NVIC_DBG_XFER_REG_R0    0x00000000  // Register R0
+#define NVIC_DBG_XFER_REG_R1    0x00000001  // Register R1
+#define NVIC_DBG_XFER_REG_R2    0x00000002  // Register R2
+#define NVIC_DBG_XFER_REG_R3    0x00000003  // Register R3
+#define NVIC_DBG_XFER_REG_R4    0x00000004  // Register R4
+#define NVIC_DBG_XFER_REG_R5    0x00000005  // Register R5
+#define NVIC_DBG_XFER_REG_R6    0x00000006  // Register R6
+#define NVIC_DBG_XFER_REG_R7    0x00000007  // Register R7
+#define NVIC_DBG_XFER_REG_R8    0x00000008  // Register R8
+#define NVIC_DBG_XFER_REG_R9    0x00000009  // Register R9
+#define NVIC_DBG_XFER_REG_R10   0x0000000A  // Register R10
+#define NVIC_DBG_XFER_REG_R11   0x0000000B  // Register R11
+#define NVIC_DBG_XFER_REG_R12   0x0000000C  // Register R12
+#define NVIC_DBG_XFER_REG_R13   0x0000000D  // Register R13
+#define NVIC_DBG_XFER_REG_R14   0x0000000E  // Register R14
+#define NVIC_DBG_XFER_REG_R15   0x0000000F  // Register R15
+#define NVIC_DBG_XFER_REG_FLAGS 0x00000010  // xPSR/Flags register
+#define NVIC_DBG_XFER_REG_MSP   0x00000011  // Main SP
+#define NVIC_DBG_XFER_REG_PSP   0x00000012  // Process SP
+#define NVIC_DBG_XFER_REG_DSP   0x00000013  // Deep SP
+#define NVIC_DBG_XFER_REG_CFBP  0x00000014  // Control/Fault/BasePri/PriMask
 
 //*****************************************************************************
 //
@@ -4030,7 +4151,135 @@
 // The following are defines for the bit fields in the NVIC_SW_TRIG register.
 //
 //*****************************************************************************
-#define NVIC_SW_TRIG_INTID_M    0x000003FF  // Interrupt to trigger
+#define NVIC_SW_TRIG_INTID_M    0x0000003F  // Interrupt ID
 #define NVIC_SW_TRIG_INTID_S    0
 
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// Deprecated defines for the Watchdog
+//
+//*****************************************************************************
+#define WATCHDOG_LOAD_R         (*((volatile unsigned long *)0x40000000))
+#define WATCHDOG_VALUE_R        (*((volatile unsigned long *)0x40000004))
+#define WATCHDOG_CTL_R          (*((volatile unsigned long *)0x40000008))
+#define WATCHDOG_ICR_R          (*((volatile unsigned long *)0x4000000C))
+#define WATCHDOG_RIS_R          (*((volatile unsigned long *)0x40000010))
+#define WATCHDOG_MIS_R          (*((volatile unsigned long *)0x40000014))
+#define WATCHDOG_TEST_R         (*((volatile unsigned long *)0x40000418))
+#define WATCHDOG_LOCK_R         (*((volatile unsigned long *)0x40000C00))
+
+//*****************************************************************************
+//
+// Deprecated defines for the bit fields in the I2C_O_SICR register.
+//
+//*****************************************************************************
+#define I2C_SICR_IC             0x00000001  // Clear Interrupt
+
+//*****************************************************************************
+//
+// Deprecated defines for the bit fields in the I2C_O_SMIS register.
+//
+//*****************************************************************************
+#define I2C_SMIS_MIS            0x00000001  // Masked Interrupt Status
+
+//*****************************************************************************
+//
+// Deprecated defines for the bit fields in the I2C_O_SRIS register.
+//
+//*****************************************************************************
+#define I2C_SRIS_RIS            0x00000001  // Raw Interrupt Status
+
+//*****************************************************************************
+//
+// Deprecated defines for the bit fields in the I2C_O_SIMR register.
+//
+//*****************************************************************************
+#define I2C_SIMR_IM             0x00000001  // Interrupt Mask
+
+//*****************************************************************************
+//
+// Deprecated defines for the bit fields in the the interpretation of the data
+// in the SSFIFOx when the ADC TMLB is enabled. register.
+//
+//*****************************************************************************
+#define ADC_TMLB_CNT_M          0x000003C0  // Continuous Sample Counter
+#define ADC_TMLB_CONT           0x00000020  // Continuation Sample Indicator
+#define ADC_TMLB_DIFF           0x00000010  // Differential Sample Indicator
+#define ADC_TMLB_TS             0x00000008  // Temp Sensor Sample Indicator
+#define ADC_TMLB_MUX_M          0x00000007  // Analog Input Indicator
+#define ADC_TMLB_CNT_S          6           // Sample counter shift
+#define ADC_TMLB_MUX_S          0           // Input channel number shift
+
+//*****************************************************************************
+//
+// Deprecated defines for the ADC register offsets.
+//
+//*****************************************************************************
+#define ADC_ACTSS_R             (*((volatile unsigned long *)0x40038000))
+#define ADC_RIS_R               (*((volatile unsigned long *)0x40038004))
+#define ADC_IM_R                (*((volatile unsigned long *)0x40038008))
+#define ADC_ISC_R               (*((volatile unsigned long *)0x4003800C))
+#define ADC_OSTAT_R             (*((volatile unsigned long *)0x40038010))
+#define ADC_EMUX_R              (*((volatile unsigned long *)0x40038014))
+#define ADC_USTAT_R             (*((volatile unsigned long *)0x40038018))
+#define ADC_SSPRI_R             (*((volatile unsigned long *)0x40038020))
+#define ADC_PSSI_R              (*((volatile unsigned long *)0x40038028))
+#define ADC_SAC_R               (*((volatile unsigned long *)0x40038030))
+#define ADC_SSMUX0_R            (*((volatile unsigned long *)0x40038040))
+#define ADC_SSCTL0_R            (*((volatile unsigned long *)0x40038044))
+#define ADC_SSFIFO0_R           (*((volatile unsigned long *)0x40038048))
+#define ADC_SSFSTAT0_R          (*((volatile unsigned long *)0x4003804C))
+#define ADC_SSMUX1_R            (*((volatile unsigned long *)0x40038060))
+#define ADC_SSCTL1_R            (*((volatile unsigned long *)0x40038064))
+#define ADC_SSFIFO1_R           (*((volatile unsigned long *)0x40038068))
+#define ADC_SSFSTAT1_R          (*((volatile unsigned long *)0x4003806C))
+#define ADC_SSMUX2_R            (*((volatile unsigned long *)0x40038080))
+#define ADC_SSCTL2_R            (*((volatile unsigned long *)0x40038084))
+#define ADC_SSFIFO2_R           (*((volatile unsigned long *)0x40038088))
+#define ADC_SSFSTAT2_R          (*((volatile unsigned long *)0x4003808C))
+#define ADC_SSMUX3_R            (*((volatile unsigned long *)0x400380A0))
+#define ADC_SSCTL3_R            (*((volatile unsigned long *)0x400380A4))
+#define ADC_SSFIFO3_R           (*((volatile unsigned long *)0x400380A8))
+#define ADC_SSFSTAT3_R          (*((volatile unsigned long *)0x400380AC))
+#define ADC_TMLB_R              (*((volatile unsigned long *)0x40038100))
+
+//*****************************************************************************
+//
+// Deprecated defines for the bit fields in the FLASH_FMC register.
+//
+//*****************************************************************************
+#define FLASH_FMC_WRKEY_M       0xFFFF0000  // Flash Memory Write Key
+#define FLASH_FMC_WRKEY_S       16
+
+//*****************************************************************************
+//
+// Deprecated defines for the bit fields in the SYSCTL_DC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC1_WDT          0x00000008  // Watchdog Timer Present
+
+//*****************************************************************************
+//
+// Deprecated defines for the bit fields in the SYSCTL_DID1 register.
+//
+//*****************************************************************************
+#define SYSCTL_DID1_PKG_28SOIC  0x00000000  // SOIC package
+#define SYSCTL_DID1_PKG_48QFP   0x00000008  // QFP package
+
+//*****************************************************************************
+//
+// Deprecated defines for the NVIC register addresses.
+//
+//*****************************************************************************
+#define NVIC_MPU_R              (*((volatile unsigned long *)0xE000ED9C))
+
+#endif
+
 #endif // __LM3S6918_H__
diff --git a/src/platform/lm3s/lm3s6965.h b/src/platform/lm3s/lm3s6965.h
index 008ff7bc..ba424fe9 100755
--- a/src/platform/lm3s/lm3s6965.h
+++ b/src/platform/lm3s/lm3s6965.h
@@ -2,26 +2,23 @@
 //
 // lm3s6965.h - LM3S6965 Register Definitions
 //
-// Copyright (c) 2007-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2007-2011 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4781 of the Stellaris Firmware Development Package.
+// This is part of revision 7611 of the Stellaris Firmware Development Package.
 //
 //*****************************************************************************
 
@@ -30,21 +27,21 @@
 
 //*****************************************************************************
 //
-// Watchdog Timer (WATCHDOG)
+// Watchdog Timer registers (WATCHDOG0)
 //
 //*****************************************************************************
-#define WATCHDOG_LOAD_R         (*((volatile unsigned long *)0x40000000))
-#define WATCHDOG_VALUE_R        (*((volatile unsigned long *)0x40000004))
-#define WATCHDOG_CTL_R          (*((volatile unsigned long *)0x40000008))
-#define WATCHDOG_ICR_R          (*((volatile unsigned long *)0x4000000C))
-#define WATCHDOG_RIS_R          (*((volatile unsigned long *)0x40000010))
-#define WATCHDOG_MIS_R          (*((volatile unsigned long *)0x40000014))
-#define WATCHDOG_TEST_R         (*((volatile unsigned long *)0x40000418))
-#define WATCHDOG_LOCK_R         (*((volatile unsigned long *)0x40000C00))
+#define WATCHDOG0_LOAD_R        (*((volatile unsigned long *)0x40000000))
+#define WATCHDOG0_VALUE_R       (*((volatile unsigned long *)0x40000004))
+#define WATCHDOG0_CTL_R         (*((volatile unsigned long *)0x40000008))
+#define WATCHDOG0_ICR_R         (*((volatile unsigned long *)0x4000000C))
+#define WATCHDOG0_RIS_R         (*((volatile unsigned long *)0x40000010))
+#define WATCHDOG0_MIS_R         (*((volatile unsigned long *)0x40000014))
+#define WATCHDOG0_TEST_R        (*((volatile unsigned long *)0x40000418))
+#define WATCHDOG0_LOCK_R        (*((volatile unsigned long *)0x40000C00))
 
 //*****************************************************************************
 //
-// General-Purpose Input/Outputs (PORTA)
+// GPIO registers (PORTA)
 //
 //*****************************************************************************
 #define GPIO_PORTA_DATA_BITS_R  ((volatile unsigned long *)0x40004000)
@@ -71,7 +68,7 @@
 
 //*****************************************************************************
 //
-// General-Purpose Input/Outputs (PORTB)
+// GPIO registers (PORTB)
 //
 //*****************************************************************************
 #define GPIO_PORTB_DATA_BITS_R  ((volatile unsigned long *)0x40005000)
@@ -98,7 +95,7 @@
 
 //*****************************************************************************
 //
-// General-Purpose Input/Outputs (PORTC)
+// GPIO registers (PORTC)
 //
 //*****************************************************************************
 #define GPIO_PORTC_DATA_BITS_R  ((volatile unsigned long *)0x40006000)
@@ -125,7 +122,7 @@
 
 //*****************************************************************************
 //
-// General-Purpose Input/Outputs (PORTD)
+// GPIO registers (PORTD)
 //
 //*****************************************************************************
 #define GPIO_PORTD_DATA_BITS_R  ((volatile unsigned long *)0x40007000)
@@ -152,7 +149,7 @@
 
 //*****************************************************************************
 //
-// Synchronous Serial Interface (SSI0)
+// SSI registers (SSI0)
 //
 //*****************************************************************************
 #define SSI0_CR0_R              (*((volatile unsigned long *)0x40008000))
@@ -167,7 +164,7 @@
 
 //*****************************************************************************
 //
-// Universal Asynchronous Receivers/Transmitters (UART0)
+// UART registers (UART0)
 //
 //*****************************************************************************
 #define UART0_DR_R              (*((volatile unsigned long *)0x4000C000))
@@ -187,7 +184,7 @@
 
 //*****************************************************************************
 //
-// Universal Asynchronous Receivers/Transmitters (UART1)
+// UART registers (UART1)
 //
 //*****************************************************************************
 #define UART1_DR_R              (*((volatile unsigned long *)0x4000D000))
@@ -207,7 +204,7 @@
 
 //*****************************************************************************
 //
-// Universal Asynchronous Receivers/Transmitters (UART2)
+// UART registers (UART2)
 //
 //*****************************************************************************
 #define UART2_DR_R              (*((volatile unsigned long *)0x4000E000))
@@ -227,95 +224,63 @@
 
 //*****************************************************************************
 //
-// Inter-Integrated Circuit (MASTER) Interface
+// I2C registers (I2C0 MASTER)
 //
 //*****************************************************************************
 #define I2C0_MASTER_MSA_R       (*((volatile unsigned long *)0x40020000))
-#define I2C0_MASTER_SOAR_R      (*((volatile unsigned long *)0x40020000))
-#define I2C0_MASTER_SCSR_R      (*((volatile unsigned long *)0x40020004))
 #define I2C0_MASTER_MCS_R       (*((volatile unsigned long *)0x40020004))
-#define I2C0_MASTER_SDR_R       (*((volatile unsigned long *)0x40020008))
 #define I2C0_MASTER_MDR_R       (*((volatile unsigned long *)0x40020008))
 #define I2C0_MASTER_MTPR_R      (*((volatile unsigned long *)0x4002000C))
-#define I2C0_MASTER_SIMR_R      (*((volatile unsigned long *)0x4002000C))
-#define I2C0_MASTER_SRIS_R      (*((volatile unsigned long *)0x40020010))
 #define I2C0_MASTER_MIMR_R      (*((volatile unsigned long *)0x40020010))
 #define I2C0_MASTER_MRIS_R      (*((volatile unsigned long *)0x40020014))
-#define I2C0_MASTER_SMIS_R      (*((volatile unsigned long *)0x40020014))
-#define I2C0_MASTER_SICR_R      (*((volatile unsigned long *)0x40020018))
 #define I2C0_MASTER_MMIS_R      (*((volatile unsigned long *)0x40020018))
 #define I2C0_MASTER_MICR_R      (*((volatile unsigned long *)0x4002001C))
 #define I2C0_MASTER_MCR_R       (*((volatile unsigned long *)0x40020020))
 
 //*****************************************************************************
 //
-// Inter-Integrated Circuit (SLAVE) Interface
+// I2C registers (I2C0 SLAVE)
 //
 //*****************************************************************************
-#define I2C0_SLAVE_MSA_R        (*((volatile unsigned long *)0x40020800))
 #define I2C0_SLAVE_SOAR_R       (*((volatile unsigned long *)0x40020800))
 #define I2C0_SLAVE_SCSR_R       (*((volatile unsigned long *)0x40020804))
-#define I2C0_SLAVE_MCS_R        (*((volatile unsigned long *)0x40020804))
 #define I2C0_SLAVE_SDR_R        (*((volatile unsigned long *)0x40020808))
-#define I2C0_SLAVE_MDR_R        (*((volatile unsigned long *)0x40020808))
-#define I2C0_SLAVE_MTPR_R       (*((volatile unsigned long *)0x4002080C))
 #define I2C0_SLAVE_SIMR_R       (*((volatile unsigned long *)0x4002080C))
 #define I2C0_SLAVE_SRIS_R       (*((volatile unsigned long *)0x40020810))
-#define I2C0_SLAVE_MIMR_R       (*((volatile unsigned long *)0x40020810))
-#define I2C0_SLAVE_MRIS_R       (*((volatile unsigned long *)0x40020814))
 #define I2C0_SLAVE_SMIS_R       (*((volatile unsigned long *)0x40020814))
 #define I2C0_SLAVE_SICR_R       (*((volatile unsigned long *)0x40020818))
-#define I2C0_SLAVE_MMIS_R       (*((volatile unsigned long *)0x40020818))
-#define I2C0_SLAVE_MICR_R       (*((volatile unsigned long *)0x4002081C))
-#define I2C0_SLAVE_MCR_R        (*((volatile unsigned long *)0x40020820))
 
 //*****************************************************************************
 //
-// Inter-Integrated Circuit (MASTER) Interface
+// I2C registers (I2C1 MASTER)
 //
 //*****************************************************************************
 #define I2C1_MASTER_MSA_R       (*((volatile unsigned long *)0x40021000))
-#define I2C1_MASTER_SOAR_R      (*((volatile unsigned long *)0x40021000))
-#define I2C1_MASTER_SCSR_R      (*((volatile unsigned long *)0x40021004))
 #define I2C1_MASTER_MCS_R       (*((volatile unsigned long *)0x40021004))
-#define I2C1_MASTER_SDR_R       (*((volatile unsigned long *)0x40021008))
 #define I2C1_MASTER_MDR_R       (*((volatile unsigned long *)0x40021008))
 #define I2C1_MASTER_MTPR_R      (*((volatile unsigned long *)0x4002100C))
-#define I2C1_MASTER_SIMR_R      (*((volatile unsigned long *)0x4002100C))
-#define I2C1_MASTER_SRIS_R      (*((volatile unsigned long *)0x40021010))
 #define I2C1_MASTER_MIMR_R      (*((volatile unsigned long *)0x40021010))
 #define I2C1_MASTER_MRIS_R      (*((volatile unsigned long *)0x40021014))
-#define I2C1_MASTER_SMIS_R      (*((volatile unsigned long *)0x40021014))
-#define I2C1_MASTER_SICR_R      (*((volatile unsigned long *)0x40021018))
 #define I2C1_MASTER_MMIS_R      (*((volatile unsigned long *)0x40021018))
 #define I2C1_MASTER_MICR_R      (*((volatile unsigned long *)0x4002101C))
 #define I2C1_MASTER_MCR_R       (*((volatile unsigned long *)0x40021020))
 
 //*****************************************************************************
 //
-// Inter-Integrated Circuit (SLAVE) Interface
+// I2C registers (I2C1 SLAVE)
 //
 //*****************************************************************************
-#define I2C1_SLAVE_MSA_R        (*((volatile unsigned long *)0x40021800))
 #define I2C1_SLAVE_SOAR_R       (*((volatile unsigned long *)0x40021800))
 #define I2C1_SLAVE_SCSR_R       (*((volatile unsigned long *)0x40021804))
-#define I2C1_SLAVE_MCS_R        (*((volatile unsigned long *)0x40021804))
 #define I2C1_SLAVE_SDR_R        (*((volatile unsigned long *)0x40021808))
-#define I2C1_SLAVE_MDR_R        (*((volatile unsigned long *)0x40021808))
-#define I2C1_SLAVE_MTPR_R       (*((volatile unsigned long *)0x4002180C))
 #define I2C1_SLAVE_SIMR_R       (*((volatile unsigned long *)0x4002180C))
 #define I2C1_SLAVE_SRIS_R       (*((volatile unsigned long *)0x40021810))
-#define I2C1_SLAVE_MIMR_R       (*((volatile unsigned long *)0x40021810))
-#define I2C1_SLAVE_MRIS_R       (*((volatile unsigned long *)0x40021814))
 #define I2C1_SLAVE_SMIS_R       (*((volatile unsigned long *)0x40021814))
 #define I2C1_SLAVE_SICR_R       (*((volatile unsigned long *)0x40021818))
-#define I2C1_SLAVE_MMIS_R       (*((volatile unsigned long *)0x40021818))
-#define I2C1_SLAVE_MICR_R       (*((volatile unsigned long *)0x4002181C))
-#define I2C1_SLAVE_MCR_R        (*((volatile unsigned long *)0x40021820))
 
 //*****************************************************************************
 //
-// General-Purpose Input/Outputs (PORTE)
+// GPIO registers (PORTE)
 //
 //*****************************************************************************
 #define GPIO_PORTE_DATA_BITS_R  ((volatile unsigned long *)0x40024000)
@@ -342,7 +307,7 @@
 
 //*****************************************************************************
 //
-// General-Purpose Input/Outputs (PORTF)
+// GPIO registers (PORTF)
 //
 //*****************************************************************************
 #define GPIO_PORTF_DATA_BITS_R  ((volatile unsigned long *)0x40025000)
@@ -369,7 +334,7 @@
 
 //*****************************************************************************
 //
-// General-Purpose Input/Outputs (PORTG)
+// GPIO registers (PORTG)
 //
 //*****************************************************************************
 #define GPIO_PORTG_DATA_BITS_R  ((volatile unsigned long *)0x40026000)
@@ -396,7 +361,7 @@
 
 //*****************************************************************************
 //
-// Pulse Width Modulator (PWM)
+// PWM registers (PWM)
 //
 //*****************************************************************************
 #define PWM_CTL_R               (*((volatile unsigned long *)0x40028000))
@@ -450,7 +415,7 @@
 
 //*****************************************************************************
 //
-// Quadrature Encoder Interface (QEI0)
+// QEI registers (QEI0)
 //
 //*****************************************************************************
 #define QEI0_CTL_R              (*((volatile unsigned long *)0x4002C000))
@@ -467,7 +432,7 @@
 
 //*****************************************************************************
 //
-// Quadrature Encoder Interface (QEI1)
+// QEI registers (QEI1)
 //
 //*****************************************************************************
 #define QEI1_CTL_R              (*((volatile unsigned long *)0x4002D000))
@@ -484,7 +449,7 @@
 
 //*****************************************************************************
 //
-// General-Purpose Timers (TIMER0)
+// Timer registers (TIMER0)
 //
 //*****************************************************************************
 #define TIMER0_CFG_R            (*((volatile unsigned long *)0x40030000))
@@ -508,7 +473,7 @@
 
 //*****************************************************************************
 //
-// General-Purpose Timers (TIMER1)
+// Timer registers (TIMER1)
 //
 //*****************************************************************************
 #define TIMER1_CFG_R            (*((volatile unsigned long *)0x40031000))
@@ -532,7 +497,7 @@
 
 //*****************************************************************************
 //
-// General-Purpose Timers (TIMER2)
+// Timer registers (TIMER2)
 //
 //*****************************************************************************
 #define TIMER2_CFG_R            (*((volatile unsigned long *)0x40032000))
@@ -556,7 +521,7 @@
 
 //*****************************************************************************
 //
-// General-Purpose Timers (TIMER3)
+// Timer registers (TIMER3)
 //
 //*****************************************************************************
 #define TIMER3_CFG_R            (*((volatile unsigned long *)0x40033000))
@@ -580,40 +545,40 @@
 
 //*****************************************************************************
 //
-// Analog-to-Digital Converter (ADC)
+// ADC registers (ADC0)
 //
 //*****************************************************************************
-#define ADC_ACTSS_R             (*((volatile unsigned long *)0x40038000))
-#define ADC_RIS_R               (*((volatile unsigned long *)0x40038004))
-#define ADC_IM_R                (*((volatile unsigned long *)0x40038008))
-#define ADC_ISC_R               (*((volatile unsigned long *)0x4003800C))
-#define ADC_OSTAT_R             (*((volatile unsigned long *)0x40038010))
-#define ADC_EMUX_R              (*((volatile unsigned long *)0x40038014))
-#define ADC_USTAT_R             (*((volatile unsigned long *)0x40038018))
-#define ADC_SSPRI_R             (*((volatile unsigned long *)0x40038020))
-#define ADC_PSSI_R              (*((volatile unsigned long *)0x40038028))
-#define ADC_SAC_R               (*((volatile unsigned long *)0x40038030))
-#define ADC_SSMUX0_R            (*((volatile unsigned long *)0x40038040))
-#define ADC_SSCTL0_R            (*((volatile unsigned long *)0x40038044))
-#define ADC_SSFIFO0_R           (*((volatile unsigned long *)0x40038048))
-#define ADC_SSFSTAT0_R          (*((volatile unsigned long *)0x4003804C))
-#define ADC_SSMUX1_R            (*((volatile unsigned long *)0x40038060))
-#define ADC_SSCTL1_R            (*((volatile unsigned long *)0x40038064))
-#define ADC_SSFIFO1_R           (*((volatile unsigned long *)0x40038068))
-#define ADC_SSFSTAT1_R          (*((volatile unsigned long *)0x4003806C))
-#define ADC_SSMUX2_R            (*((volatile unsigned long *)0x40038080))
-#define ADC_SSCTL2_R            (*((volatile unsigned long *)0x40038084))
-#define ADC_SSFIFO2_R           (*((volatile unsigned long *)0x40038088))
-#define ADC_SSFSTAT2_R          (*((volatile unsigned long *)0x4003808C))
-#define ADC_SSMUX3_R            (*((volatile unsigned long *)0x400380A0))
-#define ADC_SSCTL3_R            (*((volatile unsigned long *)0x400380A4))
-#define ADC_SSFIFO3_R           (*((volatile unsigned long *)0x400380A8))
-#define ADC_SSFSTAT3_R          (*((volatile unsigned long *)0x400380AC))
-#define ADC_TMLB_R              (*((volatile unsigned long *)0x40038100))
+#define ADC0_ACTSS_R            (*((volatile unsigned long *)0x40038000))
+#define ADC0_RIS_R              (*((volatile unsigned long *)0x40038004))
+#define ADC0_IM_R               (*((volatile unsigned long *)0x40038008))
+#define ADC0_ISC_R              (*((volatile unsigned long *)0x4003800C))
+#define ADC0_OSTAT_R            (*((volatile unsigned long *)0x40038010))
+#define ADC0_EMUX_R             (*((volatile unsigned long *)0x40038014))
+#define ADC0_USTAT_R            (*((volatile unsigned long *)0x40038018))
+#define ADC0_SSPRI_R            (*((volatile unsigned long *)0x40038020))
+#define ADC0_PSSI_R             (*((volatile unsigned long *)0x40038028))
+#define ADC0_SAC_R              (*((volatile unsigned long *)0x40038030))
+#define ADC0_SSMUX0_R           (*((volatile unsigned long *)0x40038040))
+#define ADC0_SSCTL0_R           (*((volatile unsigned long *)0x40038044))
+#define ADC0_SSFIFO0_R          (*((volatile unsigned long *)0x40038048))
+#define ADC0_SSFSTAT0_R         (*((volatile unsigned long *)0x4003804C))
+#define ADC0_SSMUX1_R           (*((volatile unsigned long *)0x40038060))
+#define ADC0_SSCTL1_R           (*((volatile unsigned long *)0x40038064))
+#define ADC0_SSFIFO1_R          (*((volatile unsigned long *)0x40038068))
+#define ADC0_SSFSTAT1_R         (*((volatile unsigned long *)0x4003806C))
+#define ADC0_SSMUX2_R           (*((volatile unsigned long *)0x40038080))
+#define ADC0_SSCTL2_R           (*((volatile unsigned long *)0x40038084))
+#define ADC0_SSFIFO2_R          (*((volatile unsigned long *)0x40038088))
+#define ADC0_SSFSTAT2_R         (*((volatile unsigned long *)0x4003808C))
+#define ADC0_SSMUX3_R           (*((volatile unsigned long *)0x400380A0))
+#define ADC0_SSCTL3_R           (*((volatile unsigned long *)0x400380A4))
+#define ADC0_SSFIFO3_R          (*((volatile unsigned long *)0x400380A8))
+#define ADC0_SSFSTAT3_R         (*((volatile unsigned long *)0x400380AC))
+#define ADC0_TMLB_R             (*((volatile unsigned long *)0x40038100))
 
 //*****************************************************************************
 //
-// Analog Comparators (COMP)
+// Comparator registers (COMP)
 //
 //*****************************************************************************
 #define COMP_ACMIS_R            (*((volatile unsigned long *)0x4003C000))
@@ -627,30 +592,17 @@
 
 //*****************************************************************************
 //
-// Ethernet Controller (MAC)
+// Ethernet MAC registers (MAC)
 //
 //*****************************************************************************
-#define MAC_MR0_R               (*((volatile unsigned long *)0x40048000))
 #define MAC_RIS_R               (*((volatile unsigned long *)0x40048000))
 #define MAC_IACK_R              (*((volatile unsigned long *)0x40048000))
-#define MAC_MR1_R               (*((volatile unsigned long *)0x40048001))
-#define MAC_MR2_R               (*((volatile unsigned long *)0x40048002))
-#define MAC_MR3_R               (*((volatile unsigned long *)0x40048003))
 #define MAC_IM_R                (*((volatile unsigned long *)0x40048004))
-#define MAC_MR4_R               (*((volatile unsigned long *)0x40048004))
-#define MAC_MR5_R               (*((volatile unsigned long *)0x40048005))
-#define MAC_MR6_R               (*((volatile unsigned long *)0x40048006))
 #define MAC_RCTL_R              (*((volatile unsigned long *)0x40048008))
 #define MAC_TCTL_R              (*((volatile unsigned long *)0x4004800C))
 #define MAC_DATA_R              (*((volatile unsigned long *)0x40048010))
-#define MAC_MR16_R              (*((volatile unsigned long *)0x40048010))
-#define MAC_MR17_R              (*((volatile unsigned long *)0x40048011))
-#define MAC_MR18_R              (*((volatile unsigned long *)0x40048012))
-#define MAC_MR19_R              (*((volatile unsigned long *)0x40048013))
 #define MAC_IA0_R               (*((volatile unsigned long *)0x40048014))
-#define MAC_MR23_R              (*((volatile unsigned long *)0x40048017))
 #define MAC_IA1_R               (*((volatile unsigned long *)0x40048018))
-#define MAC_MR24_R              (*((volatile unsigned long *)0x40048018))
 #define MAC_THR_R               (*((volatile unsigned long *)0x4004801C))
 #define MAC_MCTL_R              (*((volatile unsigned long *)0x40048020))
 #define MAC_MDV_R               (*((volatile unsigned long *)0x40048024))
@@ -661,7 +613,41 @@
 
 //*****************************************************************************
 //
-// Hibernation Module (HIB)
+// Ethernet Controller PHY registers (MAC)
+//
+//*****************************************************************************
+#define PHY_MR0                 0x00000000  // Ethernet PHY Management Register
+                                            // 0 - Control
+#define PHY_MR1                 0x00000001  // Ethernet PHY Management Register
+                                            // 1 - Status
+#define PHY_MR2                 0x00000002  // Ethernet PHY Management Register
+                                            // 2 - PHY Identifier 1
+#define PHY_MR3                 0x00000003  // Ethernet PHY Management Register
+                                            // 3 - PHY Identifier 2
+#define PHY_MR4                 0x00000004  // Ethernet PHY Management Register
+                                            // 4 - Auto-Negotiation
+                                            // Advertisement
+#define PHY_MR5                 0x00000005  // Ethernet PHY Management Register
+                                            // 5 - Auto-Negotiation Link
+                                            // Partner Base Page Ability
+#define PHY_MR6                 0x00000006  // Ethernet PHY Management Register
+                                            // 6 - Auto-Negotiation Expansion
+#define PHY_MR16                0x00000010  // Ethernet PHY Management Register
+                                            // 16 - Vendor-Specific
+#define PHY_MR17                0x00000011  // Ethernet PHY Management Register
+                                            // 17 - Mode Control/Status
+#define PHY_MR18                0x00000012  // Ethernet PHY Management Register
+                                            // 18 - Diagnostic
+#define PHY_MR19                0x00000013  // Ethernet PHY Management Register
+                                            // 19 - Transceiver Control
+#define PHY_MR23                0x00000017  // Ethernet PHY Management Register
+                                            // 23 - LED Configuration
+#define PHY_MR24                0x00000018  // Ethernet PHY Management Register
+                                            // 24 -MDI/MDIX Control
+
+//*****************************************************************************
+//
+// Hibernation module registers (HIB)
 //
 //*****************************************************************************
 #define HIB_RTCC_R              (*((volatile unsigned long *)0x400FC000))
@@ -678,7 +664,7 @@
 
 //*****************************************************************************
 //
-// Internal Memory (FLASH)
+// FLASH registers (FLASH CTRL)
 //
 //*****************************************************************************
 #define FLASH_FMA_R             (*((volatile unsigned long *)0x400FD000))
@@ -702,7 +688,7 @@
 
 //*****************************************************************************
 //
-// System Control (SYSCTL)
+// System Control registers (SYSCTL)
 //
 //*****************************************************************************
 #define SYSCTL_DID0_R           (*((volatile unsigned long *)0x400FE000))
@@ -737,7 +723,7 @@
 
 //*****************************************************************************
 //
-// Nested Vectored Interrupt Ctrl (NVIC)
+// NVIC registers (NVIC)
 //
 //*****************************************************************************
 #define NVIC_INT_TYPE_R         (*((volatile unsigned long *)0xE000E004))
@@ -784,8 +770,14 @@
 #define NVIC_MPU_TYPE_R         (*((volatile unsigned long *)0xE000ED90))
 #define NVIC_MPU_CTRL_R         (*((volatile unsigned long *)0xE000ED94))
 #define NVIC_MPU_NUMBER_R       (*((volatile unsigned long *)0xE000ED98))
-#define NVIC_MPU_R              (*((volatile unsigned long *)0xE000ED9C))
+#define NVIC_MPU_BASE_R         (*((volatile unsigned long *)0xE000ED9C))
 #define NVIC_MPU_ATTR_R         (*((volatile unsigned long *)0xE000EDA0))
+#define NVIC_MPU_BASE1_R        (*((volatile unsigned long *)0xE000EDA4))
+#define NVIC_MPU_ATTR1_R        (*((volatile unsigned long *)0xE000EDA8))
+#define NVIC_MPU_BASE2_R        (*((volatile unsigned long *)0xE000EDAC))
+#define NVIC_MPU_ATTR2_R        (*((volatile unsigned long *)0xE000EDB0))
+#define NVIC_MPU_BASE3_R        (*((volatile unsigned long *)0xE000EDB4))
+#define NVIC_MPU_ATTR3_R        (*((volatile unsigned long *)0xE000EDB8))
 #define NVIC_DBG_CTRL_R         (*((volatile unsigned long *)0xE000EDF0))
 #define NVIC_DBG_XFER_R         (*((volatile unsigned long *)0xE000EDF4))
 #define NVIC_DBG_DATA_R         (*((volatile unsigned long *)0xE000EDF8))
@@ -797,7 +789,7 @@
 // The following are defines for the bit fields in the WDT_O_LOAD register.
 //
 //*****************************************************************************
-#define WDT_LOAD_M              0xFFFFFFFF  // Watchdog Load Value.
+#define WDT_LOAD_M              0xFFFFFFFF  // Watchdog Load Value
 #define WDT_LOAD_S              0
 
 //*****************************************************************************
@@ -805,7 +797,7 @@
 // The following are defines for the bit fields in the WDT_O_VALUE register.
 //
 //*****************************************************************************
-#define WDT_VALUE_M             0xFFFFFFFF  // Watchdog Value.
+#define WDT_VALUE_M             0xFFFFFFFF  // Watchdog Value
 #define WDT_VALUE_S             0
 
 //*****************************************************************************
@@ -813,15 +805,15 @@
 // The following are defines for the bit fields in the WDT_O_CTL register.
 //
 //*****************************************************************************
-#define WDT_CTL_RESEN           0x00000002  // Watchdog Reset Enable.
-#define WDT_CTL_INTEN           0x00000001  // Watchdog Interrupt Enable.
+#define WDT_CTL_RESEN           0x00000002  // Watchdog Reset Enable
+#define WDT_CTL_INTEN           0x00000001  // Watchdog Interrupt Enable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the WDT_O_ICR register.
 //
 //*****************************************************************************
-#define WDT_ICR_M               0xFFFFFFFF  // Watchdog Interrupt Clear.
+#define WDT_ICR_M               0xFFFFFFFF  // Watchdog Interrupt Clear
 #define WDT_ICR_S               0
 
 //*****************************************************************************
@@ -829,40 +821,42 @@
 // The following are defines for the bit fields in the WDT_O_RIS register.
 //
 //*****************************************************************************
-#define WDT_RIS_WDTRIS          0x00000001  // Watchdog Raw Interrupt Status.
+#define WDT_RIS_WDTRIS          0x00000001  // Watchdog Raw Interrupt Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the WDT_O_MIS register.
 //
 //*****************************************************************************
-#define WDT_MIS_WDTMIS          0x00000001  // Watchdog Masked Interrupt
-                                            // Status.
+#define WDT_MIS_WDTMIS          0x00000001  // Watchdog Masked Interrupt Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the WDT_O_TEST register.
 //
 //*****************************************************************************
-#define WDT_TEST_STALL          0x00000100  // Watchdog Stall Enable.
+#define WDT_TEST_STALL          0x00000100  // Watchdog Stall Enable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the WDT_O_LOCK register.
 //
 //*****************************************************************************
-#define WDT_LOCK_M              0xFFFFFFFF  // Watchdog Lock.
+#define WDT_LOCK_M              0xFFFFFFFF  // Watchdog Lock
 #define WDT_LOCK_UNLOCKED       0x00000000  // Unlocked
 #define WDT_LOCK_LOCKED         0x00000001  // Locked
+#define WDT_LOCK_UNLOCK         0x1ACCE551  // Unlocks the watchdog timer
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the GPIO_O_LOCK register.
 //
 //*****************************************************************************
-#define GPIO_LOCK_M             0xFFFFFFFF  // GPIO Lock.
-#define GPIO_LOCK_UNLOCKED      0x00000000  // unlocked
-#define GPIO_LOCK_LOCKED        0x00000001  // locked
+#define GPIO_LOCK_M             0xFFFFFFFF  // GPIO Lock
+#define GPIO_LOCK_UNLOCKED      0x00000000  // The GPIOCR register is unlocked
+                                            // and may be modified
+#define GPIO_LOCK_LOCKED        0x00000001  // The GPIOCR register is locked
+                                            // and may not be modified
 #define GPIO_LOCK_KEY           0x1ACCE551  // Unlocks the GPIO_CR register
 
 //*****************************************************************************
@@ -870,15 +864,15 @@
 // The following are defines for the bit fields in the SSI_O_CR0 register.
 //
 //*****************************************************************************
-#define SSI_CR0_SCR_M           0x0000FF00  // SSI Serial Clock Rate.
-#define SSI_CR0_SPH             0x00000080  // SSI Serial Clock Phase.
-#define SSI_CR0_SPO             0x00000040  // SSI Serial Clock Polarity.
-#define SSI_CR0_FRF_M           0x00000030  // SSI Frame Format Select.
+#define SSI_CR0_SCR_M           0x0000FF00  // SSI Serial Clock Rate
+#define SSI_CR0_SPH             0x00000080  // SSI Serial Clock Phase
+#define SSI_CR0_SPO             0x00000040  // SSI Serial Clock Polarity
+#define SSI_CR0_FRF_M           0x00000030  // SSI Frame Format Select
 #define SSI_CR0_FRF_MOTO        0x00000000  // Freescale SPI Frame Format
 #define SSI_CR0_FRF_TI          0x00000010  // Texas Instruments Synchronous
                                             // Serial Frame Format
 #define SSI_CR0_FRF_NMW         0x00000020  // MICROWIRE Frame Format
-#define SSI_CR0_DSS_M           0x0000000F  // SSI Data Size Select.
+#define SSI_CR0_DSS_M           0x0000000F  // SSI Data Size Select
 #define SSI_CR0_DSS_4           0x00000003  // 4-bit data
 #define SSI_CR0_DSS_5           0x00000004  // 5-bit data
 #define SSI_CR0_DSS_6           0x00000005  // 6-bit data
@@ -899,18 +893,18 @@
 // The following are defines for the bit fields in the SSI_O_CR1 register.
 //
 //*****************************************************************************
-#define SSI_CR1_SOD             0x00000008  // SSI Slave Mode Output Disable.
-#define SSI_CR1_MS              0x00000004  // SSI Master/Slave Select.
+#define SSI_CR1_SOD             0x00000008  // SSI Slave Mode Output Disable
+#define SSI_CR1_MS              0x00000004  // SSI Master/Slave Select
 #define SSI_CR1_SSE             0x00000002  // SSI Synchronous Serial Port
-                                            // Enable.
-#define SSI_CR1_LBM             0x00000001  // SSI Loopback Mode.
+                                            // Enable
+#define SSI_CR1_LBM             0x00000001  // SSI Loopback Mode
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SSI_O_DR register.
 //
 //*****************************************************************************
-#define SSI_DR_DATA_M           0x0000FFFF  // SSI Receive/Transmit Data.
+#define SSI_DR_DATA_M           0x0000FFFF  // SSI Receive/Transmit Data
 #define SSI_DR_DATA_S           0
 
 //*****************************************************************************
@@ -918,18 +912,18 @@
 // The following are defines for the bit fields in the SSI_O_SR register.
 //
 //*****************************************************************************
-#define SSI_SR_BSY              0x00000010  // SSI Busy Bit.
-#define SSI_SR_RFF              0x00000008  // SSI Receive FIFO Full.
-#define SSI_SR_RNE              0x00000004  // SSI Receive FIFO Not Empty.
-#define SSI_SR_TNF              0x00000002  // SSI Transmit FIFO Not Full.
-#define SSI_SR_TFE              0x00000001  // SSI Transmit FIFO Empty.
+#define SSI_SR_BSY              0x00000010  // SSI Busy Bit
+#define SSI_SR_RFF              0x00000008  // SSI Receive FIFO Full
+#define SSI_SR_RNE              0x00000004  // SSI Receive FIFO Not Empty
+#define SSI_SR_TNF              0x00000002  // SSI Transmit FIFO Not Full
+#define SSI_SR_TFE              0x00000001  // SSI Transmit FIFO Empty
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SSI_O_CPSR register.
 //
 //*****************************************************************************
-#define SSI_CPSR_CPSDVSR_M      0x000000FF  // SSI Clock Prescale Divisor.
+#define SSI_CPSR_CPSDVSR_M      0x000000FF  // SSI Clock Prescale Divisor
 #define SSI_CPSR_CPSDVSR_S      0
 
 //*****************************************************************************
@@ -937,13 +931,12 @@
 // The following are defines for the bit fields in the SSI_O_IM register.
 //
 //*****************************************************************************
-#define SSI_IM_TXIM             0x00000008  // SSI Transmit FIFO Interrupt
-                                            // Mask.
-#define SSI_IM_RXIM             0x00000004  // SSI Receive FIFO Interrupt Mask.
+#define SSI_IM_TXIM             0x00000008  // SSI Transmit FIFO Interrupt Mask
+#define SSI_IM_RXIM             0x00000004  // SSI Receive FIFO Interrupt Mask
 #define SSI_IM_RTIM             0x00000002  // SSI Receive Time-Out Interrupt
-                                            // Mask.
+                                            // Mask
 #define SSI_IM_RORIM            0x00000001  // SSI Receive Overrun Interrupt
-                                            // Mask.
+                                            // Mask
 
 //*****************************************************************************
 //
@@ -951,13 +944,13 @@
 //
 //*****************************************************************************
 #define SSI_RIS_TXRIS           0x00000008  // SSI Transmit FIFO Raw Interrupt
-                                            // Status.
+                                            // Status
 #define SSI_RIS_RXRIS           0x00000004  // SSI Receive FIFO Raw Interrupt
-                                            // Status.
+                                            // Status
 #define SSI_RIS_RTRIS           0x00000002  // SSI Receive Time-Out Raw
-                                            // Interrupt Status.
+                                            // Interrupt Status
 #define SSI_RIS_RORRIS          0x00000001  // SSI Receive Overrun Raw
-                                            // Interrupt Status.
+                                            // Interrupt Status
 
 //*****************************************************************************
 //
@@ -965,13 +958,13 @@
 //
 //*****************************************************************************
 #define SSI_MIS_TXMIS           0x00000008  // SSI Transmit FIFO Masked
-                                            // Interrupt Status.
+                                            // Interrupt Status
 #define SSI_MIS_RXMIS           0x00000004  // SSI Receive FIFO Masked
-                                            // Interrupt Status.
+                                            // Interrupt Status
 #define SSI_MIS_RTMIS           0x00000002  // SSI Receive Time-Out Masked
-                                            // Interrupt Status.
+                                            // Interrupt Status
 #define SSI_MIS_RORMIS          0x00000001  // SSI Receive Overrun Masked
-                                            // Interrupt Status.
+                                            // Interrupt Status
 
 //*****************************************************************************
 //
@@ -979,20 +972,20 @@
 //
 //*****************************************************************************
 #define SSI_ICR_RTIC            0x00000002  // SSI Receive Time-Out Interrupt
-                                            // Clear.
+                                            // Clear
 #define SSI_ICR_RORIC           0x00000001  // SSI Receive Overrun Interrupt
-                                            // Clear.
+                                            // Clear
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the UART_O_DR register.
 //
 //*****************************************************************************
-#define UART_DR_OE              0x00000800  // UART Overrun Error.
-#define UART_DR_BE              0x00000400  // UART Break Error.
-#define UART_DR_PE              0x00000200  // UART Parity Error.
-#define UART_DR_FE              0x00000100  // UART Framing Error.
-#define UART_DR_DATA_M          0x000000FF  // Data Transmitted or Received.
+#define UART_DR_OE              0x00000800  // UART Overrun Error
+#define UART_DR_BE              0x00000400  // UART Break Error
+#define UART_DR_PE              0x00000200  // UART Parity Error
+#define UART_DR_FE              0x00000100  // UART Framing Error
+#define UART_DR_DATA_M          0x000000FF  // Data Transmitted or Received
 #define UART_DR_DATA_S          0
 
 //*****************************************************************************
@@ -1000,17 +993,17 @@
 // The following are defines for the bit fields in the UART_O_RSR register.
 //
 //*****************************************************************************
-#define UART_RSR_OE             0x00000008  // UART Overrun Error.
-#define UART_RSR_BE             0x00000004  // UART Break Error.
-#define UART_RSR_PE             0x00000002  // UART Parity Error.
-#define UART_RSR_FE             0x00000001  // UART Framing Error.
+#define UART_RSR_OE             0x00000008  // UART Overrun Error
+#define UART_RSR_BE             0x00000004  // UART Break Error
+#define UART_RSR_PE             0x00000002  // UART Parity Error
+#define UART_RSR_FE             0x00000001  // UART Framing Error
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the UART_O_ECR register.
 //
 //*****************************************************************************
-#define UART_ECR_DATA_M         0x000000FF  // Error Clear.
+#define UART_ECR_DATA_M         0x000000FF  // Error Clear
 #define UART_ECR_DATA_S         0
 
 //*****************************************************************************
@@ -1018,18 +1011,18 @@
 // The following are defines for the bit fields in the UART_O_FR register.
 //
 //*****************************************************************************
-#define UART_FR_TXFE            0x00000080  // UART Transmit FIFO Empty.
-#define UART_FR_RXFF            0x00000040  // UART Receive FIFO Full.
-#define UART_FR_TXFF            0x00000020  // UART Transmit FIFO Full.
-#define UART_FR_RXFE            0x00000010  // UART Receive FIFO Empty.
-#define UART_FR_BUSY            0x00000008  // UART Busy.
+#define UART_FR_TXFE            0x00000080  // UART Transmit FIFO Empty
+#define UART_FR_RXFF            0x00000040  // UART Receive FIFO Full
+#define UART_FR_TXFF            0x00000020  // UART Transmit FIFO Full
+#define UART_FR_RXFE            0x00000010  // UART Receive FIFO Empty
+#define UART_FR_BUSY            0x00000008  // UART Busy
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the UART_O_ILPR register.
 //
 //*****************************************************************************
-#define UART_ILPR_ILPDVSR_M     0x000000FF  // IrDA Low-Power Divisor.
+#define UART_ILPR_ILPDVSR_M     0x000000FF  // IrDA Low-Power Divisor
 #define UART_ILPR_ILPDVSR_S     0
 
 //*****************************************************************************
@@ -1037,7 +1030,7 @@
 // The following are defines for the bit fields in the UART_O_IBRD register.
 //
 //*****************************************************************************
-#define UART_IBRD_DIVINT_M      0x0000FFFF  // Integer Baud-Rate Divisor.
+#define UART_IBRD_DIVINT_M      0x0000FFFF  // Integer Baud-Rate Divisor
 #define UART_IBRD_DIVINT_S      0
 
 //*****************************************************************************
@@ -1045,7 +1038,7 @@
 // The following are defines for the bit fields in the UART_O_FBRD register.
 //
 //*****************************************************************************
-#define UART_FBRD_DIVFRAC_M     0x0000003F  // Fractional Baud-Rate Divisor.
+#define UART_FBRD_DIVFRAC_M     0x0000003F  // Fractional Baud-Rate Divisor
 #define UART_FBRD_DIVFRAC_S     0
 
 //*****************************************************************************
@@ -1053,29 +1046,29 @@
 // The following are defines for the bit fields in the UART_O_LCRH register.
 //
 //*****************************************************************************
-#define UART_LCRH_SPS           0x00000080  // UART Stick Parity Select.
-#define UART_LCRH_WLEN_M        0x00000060  // UART Word Length.
+#define UART_LCRH_SPS           0x00000080  // UART Stick Parity Select
+#define UART_LCRH_WLEN_M        0x00000060  // UART Word Length
 #define UART_LCRH_WLEN_5        0x00000000  // 5 bits (default)
 #define UART_LCRH_WLEN_6        0x00000020  // 6 bits
 #define UART_LCRH_WLEN_7        0x00000040  // 7 bits
 #define UART_LCRH_WLEN_8        0x00000060  // 8 bits
-#define UART_LCRH_FEN           0x00000010  // UART Enable FIFOs.
-#define UART_LCRH_STP2          0x00000008  // UART Two Stop Bits Select.
-#define UART_LCRH_EPS           0x00000004  // UART Even Parity Select.
-#define UART_LCRH_PEN           0x00000002  // UART Parity Enable.
-#define UART_LCRH_BRK           0x00000001  // UART Send Break.
+#define UART_LCRH_FEN           0x00000010  // UART Enable FIFOs
+#define UART_LCRH_STP2          0x00000008  // UART Two Stop Bits Select
+#define UART_LCRH_EPS           0x00000004  // UART Even Parity Select
+#define UART_LCRH_PEN           0x00000002  // UART Parity Enable
+#define UART_LCRH_BRK           0x00000001  // UART Send Break
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the UART_O_CTL register.
 //
 //*****************************************************************************
-#define UART_CTL_RXE            0x00000200  // UART Receive Enable.
-#define UART_CTL_TXE            0x00000100  // UART Transmit Enable.
-#define UART_CTL_LBE            0x00000080  // UART Loop Back Enable.
-#define UART_CTL_SIRLP          0x00000004  // UART SIR Low Power Mode.
-#define UART_CTL_SIREN          0x00000002  // UART SIR Enable.
-#define UART_CTL_UARTEN         0x00000001  // UART Enable.
+#define UART_CTL_RXE            0x00000200  // UART Receive Enable
+#define UART_CTL_TXE            0x00000100  // UART Transmit Enable
+#define UART_CTL_LBE            0x00000080  // UART Loop Back Enable
+#define UART_CTL_SIRLP          0x00000004  // UART SIR Low-Power Mode
+#define UART_CTL_SIREN          0x00000002  // UART SIR Enable
+#define UART_CTL_UARTEN         0x00000001  // UART Enable
 
 //*****************************************************************************
 //
@@ -1083,19 +1076,19 @@
 //
 //*****************************************************************************
 #define UART_IFLS_RX_M          0x00000038  // UART Receive Interrupt FIFO
-                                            // Level Select.
-#define UART_IFLS_RX1_8         0x00000000  // RX FIFO <= 1/8 full
-#define UART_IFLS_RX2_8         0x00000008  // RX FIFO <= 1/4 full
-#define UART_IFLS_RX4_8         0x00000010  // RX FIFO <= 1/2 full (default)
-#define UART_IFLS_RX6_8         0x00000018  // RX FIFO <= 3/4 full
-#define UART_IFLS_RX7_8         0x00000020  // RX FIFO <= 7/8 full
+                                            // Level Select
+#define UART_IFLS_RX1_8         0x00000000  // RX FIFO >= 1/8 full
+#define UART_IFLS_RX2_8         0x00000008  // RX FIFO >= 1/4 full
+#define UART_IFLS_RX4_8         0x00000010  // RX FIFO >= 1/2 full (default)
+#define UART_IFLS_RX6_8         0x00000018  // RX FIFO >= 3/4 full
+#define UART_IFLS_RX7_8         0x00000020  // RX FIFO >= 7/8 full
 #define UART_IFLS_TX_M          0x00000007  // UART Transmit Interrupt FIFO
-                                            // Level Select.
-#define UART_IFLS_TX1_8         0x00000000  // TX FIFO >= 1/8 full
-#define UART_IFLS_TX2_8         0x00000001  // TX FIFO >= 1/4 full
-#define UART_IFLS_TX4_8         0x00000002  // TX FIFO >= 1/2 full (default)
-#define UART_IFLS_TX6_8         0x00000003  // TX FIFO >= 3/4 full
-#define UART_IFLS_TX7_8         0x00000004  // TX FIFO >= 7/8 full
+                                            // Level Select
+#define UART_IFLS_TX1_8         0x00000000  // TX FIFO <= 1/8 full
+#define UART_IFLS_TX2_8         0x00000001  // TX FIFO <= 1/4 full
+#define UART_IFLS_TX4_8         0x00000002  // TX FIFO <= 1/2 full (default)
+#define UART_IFLS_TX6_8         0x00000003  // TX FIFO <= 3/4 full
+#define UART_IFLS_TX7_8         0x00000004  // TX FIFO <= 7/8 full
 
 //*****************************************************************************
 //
@@ -1103,16 +1096,15 @@
 //
 //*****************************************************************************
 #define UART_IM_OEIM            0x00000400  // UART Overrun Error Interrupt
-                                            // Mask.
-#define UART_IM_BEIM            0x00000200  // UART Break Error Interrupt Mask.
-#define UART_IM_PEIM            0x00000100  // UART Parity Error Interrupt
-                                            // Mask.
+                                            // Mask
+#define UART_IM_BEIM            0x00000200  // UART Break Error Interrupt Mask
+#define UART_IM_PEIM            0x00000100  // UART Parity Error Interrupt Mask
 #define UART_IM_FEIM            0x00000080  // UART Framing Error Interrupt
-                                            // Mask.
+                                            // Mask
 #define UART_IM_RTIM            0x00000040  // UART Receive Time-Out Interrupt
-                                            // Mask.
-#define UART_IM_TXIM            0x00000020  // UART Transmit Interrupt Mask.
-#define UART_IM_RXIM            0x00000010  // UART Receive Interrupt Mask.
+                                            // Mask
+#define UART_IM_TXIM            0x00000020  // UART Transmit Interrupt Mask
+#define UART_IM_RXIM            0x00000010  // UART Receive Interrupt Mask
 
 //*****************************************************************************
 //
@@ -1120,19 +1112,19 @@
 //
 //*****************************************************************************
 #define UART_RIS_OERIS          0x00000400  // UART Overrun Error Raw Interrupt
-                                            // Status.
+                                            // Status
 #define UART_RIS_BERIS          0x00000200  // UART Break Error Raw Interrupt
-                                            // Status.
+                                            // Status
 #define UART_RIS_PERIS          0x00000100  // UART Parity Error Raw Interrupt
-                                            // Status.
+                                            // Status
 #define UART_RIS_FERIS          0x00000080  // UART Framing Error Raw Interrupt
-                                            // Status.
+                                            // Status
 #define UART_RIS_RTRIS          0x00000040  // UART Receive Time-Out Raw
-                                            // Interrupt Status.
+                                            // Interrupt Status
 #define UART_RIS_TXRIS          0x00000020  // UART Transmit Raw Interrupt
-                                            // Status.
+                                            // Status
 #define UART_RIS_RXRIS          0x00000010  // UART Receive Raw Interrupt
-                                            // Status.
+                                            // Status
 
 //*****************************************************************************
 //
@@ -1140,41 +1132,40 @@
 //
 //*****************************************************************************
 #define UART_MIS_OEMIS          0x00000400  // UART Overrun Error Masked
-                                            // Interrupt Status.
+                                            // Interrupt Status
 #define UART_MIS_BEMIS          0x00000200  // UART Break Error Masked
-                                            // Interrupt Status.
+                                            // Interrupt Status
 #define UART_MIS_PEMIS          0x00000100  // UART Parity Error Masked
-                                            // Interrupt Status.
+                                            // Interrupt Status
 #define UART_MIS_FEMIS          0x00000080  // UART Framing Error Masked
-                                            // Interrupt Status.
+                                            // Interrupt Status
 #define UART_MIS_RTMIS          0x00000040  // UART Receive Time-Out Masked
-                                            // Interrupt Status.
+                                            // Interrupt Status
 #define UART_MIS_TXMIS          0x00000020  // UART Transmit Masked Interrupt
-                                            // Status.
+                                            // Status
 #define UART_MIS_RXMIS          0x00000010  // UART Receive Masked Interrupt
-                                            // Status.
+                                            // Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the UART_O_ICR register.
 //
 //*****************************************************************************
-#define UART_ICR_OEIC           0x00000400  // Overrun Error Interrupt Clear.
-#define UART_ICR_BEIC           0x00000200  // Break Error Interrupt Clear.
-#define UART_ICR_PEIC           0x00000100  // Parity Error Interrupt Clear.
-#define UART_ICR_FEIC           0x00000080  // Framing Error Interrupt Clear.
-#define UART_ICR_RTIC           0x00000040  // Receive Time-Out Interrupt
-                                            // Clear.
-#define UART_ICR_TXIC           0x00000020  // Transmit Interrupt Clear.
-#define UART_ICR_RXIC           0x00000010  // Receive Interrupt Clear.
+#define UART_ICR_OEIC           0x00000400  // Overrun Error Interrupt Clear
+#define UART_ICR_BEIC           0x00000200  // Break Error Interrupt Clear
+#define UART_ICR_PEIC           0x00000100  // Parity Error Interrupt Clear
+#define UART_ICR_FEIC           0x00000080  // Framing Error Interrupt Clear
+#define UART_ICR_RTIC           0x00000040  // Receive Time-Out Interrupt Clear
+#define UART_ICR_TXIC           0x00000020  // Transmit Interrupt Clear
+#define UART_ICR_RXIC           0x00000010  // Receive Interrupt Clear
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2C_O_MSA register.
 //
 //*****************************************************************************
-#define I2C_MSA_SA_M            0x000000FE  // I2C Slave Address.
-#define I2C_MSA_RS              0x00000001  // Receive not send.
+#define I2C_MSA_SA_M            0x000000FE  // I2C Slave Address
+#define I2C_MSA_RS              0x00000001  // Receive not send
 #define I2C_MSA_SA_S            1
 
 //*****************************************************************************
@@ -1182,7 +1173,7 @@
 // The following are defines for the bit fields in the I2C_O_SOAR register.
 //
 //*****************************************************************************
-#define I2C_SOAR_OAR_M          0x0000007F  // I2C Slave Own Address.
+#define I2C_SOAR_OAR_M          0x0000007F  // I2C Slave Own Address
 #define I2C_SOAR_OAR_S          0
 
 //*****************************************************************************
@@ -1190,34 +1181,34 @@
 // The following are defines for the bit fields in the I2C_O_SCSR register.
 //
 //*****************************************************************************
-#define I2C_SCSR_FBR            0x00000004  // First Byte Received.
-#define I2C_SCSR_TREQ           0x00000002  // Transmit Request.
-#define I2C_SCSR_DA             0x00000001  // Device Active.
-#define I2C_SCSR_RREQ           0x00000001  // Receive Request.
+#define I2C_SCSR_FBR            0x00000004  // First Byte Received
+#define I2C_SCSR_TREQ           0x00000002  // Transmit Request
+#define I2C_SCSR_DA             0x00000001  // Device Active
+#define I2C_SCSR_RREQ           0x00000001  // Receive Request
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2C_O_MCS register.
 //
 //*****************************************************************************
-#define I2C_MCS_BUSBSY          0x00000040  // Bus Busy.
-#define I2C_MCS_IDLE            0x00000020  // I2C Idle.
-#define I2C_MCS_ARBLST          0x00000010  // Arbitration Lost.
-#define I2C_MCS_ACK             0x00000008  // Data Acknowledge Enable.
-#define I2C_MCS_DATACK          0x00000008  // Acknowledge Data.
-#define I2C_MCS_ADRACK          0x00000004  // Acknowledge Address.
-#define I2C_MCS_STOP            0x00000004  // Generate STOP.
-#define I2C_MCS_START           0x00000002  // Generate START.
-#define I2C_MCS_ERROR           0x00000002  // Error.
-#define I2C_MCS_RUN             0x00000001  // I2C Master Enable.
-#define I2C_MCS_BUSY            0x00000001  // I2C Busy.
+#define I2C_MCS_BUSBSY          0x00000040  // Bus Busy
+#define I2C_MCS_IDLE            0x00000020  // I2C Idle
+#define I2C_MCS_ARBLST          0x00000010  // Arbitration Lost
+#define I2C_MCS_ACK             0x00000008  // Data Acknowledge Enable
+#define I2C_MCS_DATACK          0x00000008  // Acknowledge Data
+#define I2C_MCS_ADRACK          0x00000004  // Acknowledge Address
+#define I2C_MCS_STOP            0x00000004  // Generate STOP
+#define I2C_MCS_START           0x00000002  // Generate START
+#define I2C_MCS_ERROR           0x00000002  // Error
+#define I2C_MCS_RUN             0x00000001  // I2C Master Enable
+#define I2C_MCS_BUSY            0x00000001  // I2C Busy
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2C_O_SDR register.
 //
 //*****************************************************************************
-#define I2C_SDR_DATA_M          0x000000FF  // Data for Transfer.
+#define I2C_SDR_DATA_M          0x000000FF  // Data for Transfer
 #define I2C_SDR_DATA_S          0
 
 //*****************************************************************************
@@ -1225,7 +1216,7 @@
 // The following are defines for the bit fields in the I2C_O_MDR register.
 //
 //*****************************************************************************
-#define I2C_MDR_DATA_M          0x000000FF  // Data Transferred.
+#define I2C_MDR_DATA_M          0x000000FF  // Data Transferred
 #define I2C_MDR_DATA_S          0
 
 //*****************************************************************************
@@ -1233,7 +1224,7 @@
 // The following are defines for the bit fields in the I2C_O_MTPR register.
 //
 //*****************************************************************************
-#define I2C_MTPR_TPR_M          0x000000FF  // SCL Clock Period.
+#define I2C_MTPR_TPR_M          0x0000007F  // SCL Clock Period
 #define I2C_MTPR_TPR_S          0
 
 //*****************************************************************************
@@ -1241,377 +1232,360 @@
 // The following are defines for the bit fields in the I2C_O_SIMR register.
 //
 //*****************************************************************************
-#define I2C_SIMR_IM             0x00000001  // Data Interrupt Mask.
+#define I2C_SIMR_DATAIM         0x00000001  // Data Interrupt Mask
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2C_O_SRIS register.
 //
 //*****************************************************************************
-#define I2C_SRIS_RIS            0x00000001  // Data Raw Interrupt Status.
+#define I2C_SRIS_DATARIS        0x00000001  // Data Raw Interrupt Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2C_O_MIMR register.
 //
 //*****************************************************************************
-#define I2C_MIMR_IM             0x00000001  // Interrupt Mask.
+#define I2C_MIMR_IM             0x00000001  // Interrupt Mask
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2C_O_MRIS register.
 //
 //*****************************************************************************
-#define I2C_MRIS_RIS            0x00000001  // Raw Interrupt Status.
+#define I2C_MRIS_RIS            0x00000001  // Raw Interrupt Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2C_O_SMIS register.
 //
 //*****************************************************************************
-#define I2C_SMIS_MIS            0x00000001  // Data Masked Interrupt Status.
+#define I2C_SMIS_DATAMIS        0x00000001  // Data Masked Interrupt Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2C_O_SICR register.
 //
 //*****************************************************************************
-#define I2C_SICR_IC             0x00000001  // Data Interrupt Clear.
+#define I2C_SICR_DATAIC         0x00000001  // Data Interrupt Clear
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2C_O_MMIS register.
 //
 //*****************************************************************************
-#define I2C_MMIS_MIS            0x00000001  // Masked Interrupt Status.
+#define I2C_MMIS_MIS            0x00000001  // Masked Interrupt Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2C_O_MICR register.
 //
 //*****************************************************************************
-#define I2C_MICR_IC             0x00000001  // Interrupt Clear.
+#define I2C_MICR_IC             0x00000001  // Interrupt Clear
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2C_O_MCR register.
 //
 //*****************************************************************************
-#define I2C_MCR_SFE             0x00000020  // I2C Slave Function Enable.
-#define I2C_MCR_MFE             0x00000010  // I2C Master Function Enable.
-#define I2C_MCR_LPBK            0x00000001  // I2C Loopback.
+#define I2C_MCR_SFE             0x00000020  // I2C Slave Function Enable
+#define I2C_MCR_MFE             0x00000010  // I2C Master Function Enable
+#define I2C_MCR_LPBK            0x00000001  // I2C Loopback
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the PWM_O_CTL register.
 //
 //*****************************************************************************
-#define PWM_CTL_GLOBALSYNC2     0x00000004  // Update PWM Generator 2.
-#define PWM_CTL_GLOBALSYNC1     0x00000002  // Update PWM Generator 1.
-#define PWM_CTL_GLOBALSYNC0     0x00000001  // Update PWM Generator 0.
+#define PWM_CTL_GLOBALSYNC2     0x00000004  // Update PWM Generator 2
+#define PWM_CTL_GLOBALSYNC1     0x00000002  // Update PWM Generator 1
+#define PWM_CTL_GLOBALSYNC0     0x00000001  // Update PWM Generator 0
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the PWM_O_SYNC register.
 //
 //*****************************************************************************
-#define PWM_SYNC_SYNC2          0x00000004  // Reset Generator 2 Counter.
-#define PWM_SYNC_SYNC1          0x00000002  // Reset Generator 1 Counter.
-#define PWM_SYNC_SYNC0          0x00000001  // Reset Generator 0 Counter.
+#define PWM_SYNC_SYNC2          0x00000004  // Reset Generator 2 Counter
+#define PWM_SYNC_SYNC1          0x00000002  // Reset Generator 1 Counter
+#define PWM_SYNC_SYNC0          0x00000001  // Reset Generator 0 Counter
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the PWM_O_ENABLE register.
 //
 //*****************************************************************************
-#define PWM_ENABLE_PWM5EN       0x00000020  // PWM5 Output Enable.
-#define PWM_ENABLE_PWM4EN       0x00000010  // PWM4 Output Enable.
-#define PWM_ENABLE_PWM3EN       0x00000008  // PWM3 Output Enable.
-#define PWM_ENABLE_PWM2EN       0x00000004  // PWM2 Output Enable.
-#define PWM_ENABLE_PWM1EN       0x00000002  // PWM1 Output Enable.
-#define PWM_ENABLE_PWM0EN       0x00000001  // PWM0 Output Enable.
+#define PWM_ENABLE_PWM5EN       0x00000020  // PWM5 Output Enable
+#define PWM_ENABLE_PWM4EN       0x00000010  // PWM4 Output Enable
+#define PWM_ENABLE_PWM3EN       0x00000008  // PWM3 Output Enable
+#define PWM_ENABLE_PWM2EN       0x00000004  // PWM2 Output Enable
+#define PWM_ENABLE_PWM1EN       0x00000002  // PWM1 Output Enable
+#define PWM_ENABLE_PWM0EN       0x00000001  // PWM0 Output Enable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the PWM_O_INVERT register.
 //
 //*****************************************************************************
-#define PWM_INVERT_PWM5INV      0x00000020  // Invert PWM5 Signal.
-#define PWM_INVERT_PWM4INV      0x00000010  // Invert PWM4 Signal.
-#define PWM_INVERT_PWM3INV      0x00000008  // Invert PWM3 Signal.
-#define PWM_INVERT_PWM2INV      0x00000004  // Invert PWM2 Signal.
-#define PWM_INVERT_PWM1INV      0x00000002  // Invert PWM1 Signal.
-#define PWM_INVERT_PWM0INV      0x00000001  // Invert PWM0 Signal.
+#define PWM_INVERT_PWM5INV      0x00000020  // Invert PWM5 Signal
+#define PWM_INVERT_PWM4INV      0x00000010  // Invert PWM4 Signal
+#define PWM_INVERT_PWM3INV      0x00000008  // Invert PWM3 Signal
+#define PWM_INVERT_PWM2INV      0x00000004  // Invert PWM2 Signal
+#define PWM_INVERT_PWM1INV      0x00000002  // Invert PWM1 Signal
+#define PWM_INVERT_PWM0INV      0x00000001  // Invert PWM0 Signal
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the PWM_O_FAULT register.
 //
 //*****************************************************************************
-#define PWM_FAULT_FAULT5        0x00000020  // PWM5 Fault.
-#define PWM_FAULT_FAULT4        0x00000010  // PWM4 Fault.
-#define PWM_FAULT_FAULT3        0x00000008  // PWM3 Fault.
-#define PWM_FAULT_FAULT2        0x00000004  // PWM2 Fault.
-#define PWM_FAULT_FAULT1        0x00000002  // PWM1 Fault.
-#define PWM_FAULT_FAULT0        0x00000001  // PWM0 Fault.
+#define PWM_FAULT_FAULT5        0x00000020  // PWM5 Fault
+#define PWM_FAULT_FAULT4        0x00000010  // PWM4 Fault
+#define PWM_FAULT_FAULT3        0x00000008  // PWM3 Fault
+#define PWM_FAULT_FAULT2        0x00000004  // PWM2 Fault
+#define PWM_FAULT_FAULT1        0x00000002  // PWM1 Fault
+#define PWM_FAULT_FAULT0        0x00000001  // PWM0 Fault
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the PWM_O_INTEN register.
 //
 //*****************************************************************************
-#define PWM_INTEN_INTFAULT      0x00010000  // Fault Interrupt Enable.
-#define PWM_INTEN_INTPWM2       0x00000004  // PWM2 Interrupt Enable.
-#define PWM_INTEN_INTPWM1       0x00000002  // PWM1 Interrupt Enable.
-#define PWM_INTEN_INTPWM0       0x00000001  // PWM0 Interrupt Enable.
+#define PWM_INTEN_INTFAULT      0x00010000  // Fault Interrupt Enable
+#define PWM_INTEN_INTPWM2       0x00000004  // PWM2 Interrupt Enable
+#define PWM_INTEN_INTPWM1       0x00000002  // PWM1 Interrupt Enable
+#define PWM_INTEN_INTPWM0       0x00000001  // PWM0 Interrupt Enable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the PWM_O_RIS register.
 //
 //*****************************************************************************
-#define PWM_RIS_INTFAULT        0x00010000  // Fault Interrupt Asserted.
-#define PWM_RIS_INTPWM2         0x00000004  // PWM2 Interrupt Asserted.
-#define PWM_RIS_INTPWM1         0x00000002  // PWM1 Interrupt Asserted.
-#define PWM_RIS_INTPWM0         0x00000001  // PWM0 Interrupt Asserted.
+#define PWM_RIS_INTFAULT        0x00010000  // Fault Interrupt Asserted
+#define PWM_RIS_INTPWM2         0x00000004  // PWM2 Interrupt Asserted
+#define PWM_RIS_INTPWM1         0x00000002  // PWM1 Interrupt Asserted
+#define PWM_RIS_INTPWM0         0x00000001  // PWM0 Interrupt Asserted
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the PWM_O_ISC register.
 //
 //*****************************************************************************
-#define PWM_ISC_INTFAULT        0x00010000  // Fault Interrupt Asserted.
-#define PWM_ISC_INTPWM2         0x00000004  // PWM2 Interrupt Status.
-#define PWM_ISC_INTPWM1         0x00000002  // PWM1 Interrupt Status.
-#define PWM_ISC_INTPWM0         0x00000001  // PWM0 Interrupt Status.
+#define PWM_ISC_INTFAULT        0x00010000  // Fault Interrupt Asserted
+#define PWM_ISC_INTPWM2         0x00000004  // PWM2 Interrupt Status
+#define PWM_ISC_INTPWM1         0x00000002  // PWM1 Interrupt Status
+#define PWM_ISC_INTPWM0         0x00000001  // PWM0 Interrupt Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the PWM_O_STATUS register.
 //
 //*****************************************************************************
-#define PWM_STATUS_FAULT        0x00000001  // Fault Interrupt Status.
+#define PWM_STATUS_FAULT        0x00000001  // Fault Interrupt Status
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the PWM_O_0_CTL,
-// PWM_O_1_CTL, and PWM_O_2_CTL registers.
+// The following are defines for the bit fields in the PWM_O_X_CTL register.
 //
 //*****************************************************************************
-#define PWM_X_CTL_CMPBUPD       0x00000020  // Comparator B Update Mode.
-#define PWM_X_CTL_CMPAUPD       0x00000010  // Comparator A Update Mode.
-#define PWM_X_CTL_LOADUPD       0x00000008  // Load Register Update Mode.
-#define PWM_X_CTL_DEBUG         0x00000004  // Debug Mode.
-#define PWM_X_CTL_MODE          0x00000002  // Counter Mode.
-#define PWM_X_CTL_ENABLE        0x00000001  // PWM Block Enable.
+#define PWM_X_CTL_CMPBUPD       0x00000020  // Comparator B Update Mode
+#define PWM_X_CTL_CMPAUPD       0x00000010  // Comparator A Update Mode
+#define PWM_X_CTL_LOADUPD       0x00000008  // Load Register Update Mode
+#define PWM_X_CTL_DEBUG         0x00000004  // Debug Mode
+#define PWM_X_CTL_MODE          0x00000002  // Counter Mode
+#define PWM_X_CTL_ENABLE        0x00000001  // PWM Block Enable
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the PWM_O_0_INTEN,
-// PWM_O_1_INTEN, and PWM_O_2_INTEN registers.
+// The following are defines for the bit fields in the PWM_O_X_INTEN register.
 //
 //*****************************************************************************
-#define PWM_X_INTEN_TRCMPBD     0x00002000  // Trigger for Counter=Comparator B
-                                            // Down.
-#define PWM_X_INTEN_TRCMPBU     0x00001000  // Trigger for Counter=Comparator B
-                                            // Up.
-#define PWM_X_INTEN_TRCMPAD     0x00000800  // Trigger for Counter=Comparator A
-                                            // Down.
-#define PWM_X_INTEN_TRCMPAU     0x00000400  // Trigger for Counter=Comparator A
-                                            // Up.
-#define PWM_X_INTEN_TRCNTLOAD   0x00000200  // Trigger for Counter=Load.
-#define PWM_X_INTEN_TRCNTZERO   0x00000100  // Trigger for Counter=0.
-#define PWM_X_INTEN_INTCMPBD    0x00000020  // Interrupt for Counter=Comparator
-                                            // B Down.
-#define PWM_X_INTEN_INTCMPBU    0x00000010  // Interrupt for Counter=Comparator
-                                            // B Up.
-#define PWM_X_INTEN_INTCMPAD    0x00000008  // Interrupt for Counter=Comparator
-                                            // A Down.
-#define PWM_X_INTEN_INTCMPAU    0x00000004  // Interrupt for Counter=Comparator
-                                            // A Up.
-#define PWM_X_INTEN_INTCNTLOAD  0x00000002  // Interrupt for Counter=Load.
-#define PWM_X_INTEN_INTCNTZERO  0x00000001  // Interrupt for Counter=0.
+#define PWM_X_INTEN_TRCMPBD     0x00002000  // Trigger for Counter=PWMnCMPB
+                                            // Down
+#define PWM_X_INTEN_TRCMPBU     0x00001000  // Trigger for Counter=PWMnCMPB Up
+#define PWM_X_INTEN_TRCMPAD     0x00000800  // Trigger for Counter=PWMnCMPA
+                                            // Down
+#define PWM_X_INTEN_TRCMPAU     0x00000400  // Trigger for Counter=PWMnCMPA Up
+#define PWM_X_INTEN_TRCNTLOAD   0x00000200  // Trigger for Counter=PWMnLOAD
+#define PWM_X_INTEN_TRCNTZERO   0x00000100  // Trigger for Counter=0
+#define PWM_X_INTEN_INTCMPBD    0x00000020  // Interrupt for Counter=PWMnCMPB
+                                            // Down
+#define PWM_X_INTEN_INTCMPBU    0x00000010  // Interrupt for Counter=PWMnCMPB
+                                            // Up
+#define PWM_X_INTEN_INTCMPAD    0x00000008  // Interrupt for Counter=PWMnCMPA
+                                            // Down
+#define PWM_X_INTEN_INTCMPAU    0x00000004  // Interrupt for Counter=PWMnCMPA
+                                            // Up
+#define PWM_X_INTEN_INTCNTLOAD  0x00000002  // Interrupt for Counter=PWMnLOAD
+#define PWM_X_INTEN_INTCNTZERO  0x00000001  // Interrupt for Counter=0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the PWM_O_0_RIS,
-// PWM_O_1_RIS, and PWM_O_2_RIS registers.
+// The following are defines for the bit fields in the PWM_O_X_RIS register.
 //
 //*****************************************************************************
 #define PWM_X_RIS_INTCMPBD      0x00000020  // Comparator B Down Interrupt
-                                            // Status.
-#define PWM_X_RIS_INTCMPBU      0x00000010  // Comparator B Up Interrupt
-                                            // Status.
+                                            // Status
+#define PWM_X_RIS_INTCMPBU      0x00000010  // Comparator B Up Interrupt Status
 #define PWM_X_RIS_INTCMPAD      0x00000008  // Comparator A Down Interrupt
-                                            // Status.
-#define PWM_X_RIS_INTCMPAU      0x00000004  // Comparator A Up Interrupt
-                                            // Status.
-#define PWM_X_RIS_INTCNTLOAD    0x00000002  // Counter=Load Interrupt Status.
-#define PWM_X_RIS_INTCNTZERO    0x00000001  // Counter=0 Interrupt Status.
+                                            // Status
+#define PWM_X_RIS_INTCMPAU      0x00000004  // Comparator A Up Interrupt Status
+#define PWM_X_RIS_INTCNTLOAD    0x00000002  // Counter=Load Interrupt Status
+#define PWM_X_RIS_INTCNTZERO    0x00000001  // Counter=0 Interrupt Status
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the PWM_O_0_ISC,
-// PWM_O_1_ISC, and PWM_O_2_ISC registers.
+// The following are defines for the bit fields in the PWM_O_X_ISC register.
 //
 //*****************************************************************************
-#define PWM_X_ISC_INTCMPBD      0x00000020  // Comparator B Down Interrupt.
-#define PWM_X_ISC_INTCMPBU      0x00000010  // Comparator B Up Interrupt.
-#define PWM_X_ISC_INTCMPAD      0x00000008  // Comparator A Down Interrupt.
-#define PWM_X_ISC_INTCMPAU      0x00000004  // Comparator A Up Interrupt.
-#define PWM_X_ISC_INTCNTLOAD    0x00000002  // Counter=Load Interrupt.
-#define PWM_X_ISC_INTCNTZERO    0x00000001  // Counter=0 Interrupt.
+#define PWM_X_ISC_INTCMPBD      0x00000020  // Comparator B Down Interrupt
+#define PWM_X_ISC_INTCMPBU      0x00000010  // Comparator B Up Interrupt
+#define PWM_X_ISC_INTCMPAD      0x00000008  // Comparator A Down Interrupt
+#define PWM_X_ISC_INTCMPAU      0x00000004  // Comparator A Up Interrupt
+#define PWM_X_ISC_INTCNTLOAD    0x00000002  // Counter=Load Interrupt
+#define PWM_X_ISC_INTCNTZERO    0x00000001  // Counter=0 Interrupt
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the PWM_O_0_LOAD,
-// PWM_O_1_LOAD, and PWM_O_2_LOAD registers.
+// The following are defines for the bit fields in the PWM_O_X_LOAD register.
 //
 //*****************************************************************************
-#define PWM_X_LOAD_M            0x0000FFFF  // Counter Load Value.
+#define PWM_X_LOAD_M            0x0000FFFF  // Counter Load Value
 #define PWM_X_LOAD_S            0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the PWM_O_0_COUNT,
-// PWM_O_1_COUNT, and PWM_O_2_COUNT registers.
+// The following are defines for the bit fields in the PWM_O_X_COUNT register.
 //
 //*****************************************************************************
-#define PWM_X_COUNT_M           0x0000FFFF  // Counter Value.
+#define PWM_X_COUNT_M           0x0000FFFF  // Counter Value
 #define PWM_X_COUNT_S           0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the PWM_O_0_CMPA,
-// PWM_O_1_CMPA, and PWM_O_2_CMPA registers.
+// The following are defines for the bit fields in the PWM_O_X_CMPA register.
 //
 //*****************************************************************************
-#define PWM_X_CMPA_M            0x0000FFFF  // Comparator A Value.
+#define PWM_X_CMPA_M            0x0000FFFF  // Comparator A Value
 #define PWM_X_CMPA_S            0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the PWM_O_0_CMPB,
-// PWM_O_1_CMPB, and PWM_O_2_CMPB registers.
+// The following are defines for the bit fields in the PWM_O_X_CMPB register.
 //
 //*****************************************************************************
-#define PWM_X_CMPB_M            0x0000FFFF  // Comparator B Value.
+#define PWM_X_CMPB_M            0x0000FFFF  // Comparator B Value
 #define PWM_X_CMPB_S            0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the PWM_O_0_GENA,
-// PWM_O_1_GENA, and PWM_O_2_GENA registers.
+// The following are defines for the bit fields in the PWM_O_X_GENA register.
 //
 //*****************************************************************************
-#define PWM_X_GENA_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down.
+#define PWM_X_GENA_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down
 #define PWM_X_GENA_ACTCMPBD_NONE \
-                                0x00000000  // Do nothing.
-#define PWM_X_GENA_ACTCMPBD_INV 0x00000400  // Invert the output signal.
+                                0x00000000  // Do nothing
+#define PWM_X_GENA_ACTCMPBD_INV 0x00000400  // Invert pwmA
 #define PWM_X_GENA_ACTCMPBD_ZERO \
-                                0x00000800  // Set the output signal to 0.
-#define PWM_X_GENA_ACTCMPBD_ONE 0x00000C00  // Set the output signal to 1.
-#define PWM_X_GENA_ACTCMPBU_M   0x00000300  // Action for Comparator B Up.
+                                0x00000800  // Drive pwmA Low
+#define PWM_X_GENA_ACTCMPBD_ONE 0x00000C00  // Drive pwmA High
+#define PWM_X_GENA_ACTCMPBU_M   0x00000300  // Action for Comparator B Up
 #define PWM_X_GENA_ACTCMPBU_NONE \
-                                0x00000000  // Do nothing.
-#define PWM_X_GENA_ACTCMPBU_INV 0x00000100  // Invert the output signal.
+                                0x00000000  // Do nothing
+#define PWM_X_GENA_ACTCMPBU_INV 0x00000100  // Invert pwmA
 #define PWM_X_GENA_ACTCMPBU_ZERO \
-                                0x00000200  // Set the output signal to 0.
-#define PWM_X_GENA_ACTCMPBU_ONE 0x00000300  // Set the output signal to 1.
-#define PWM_X_GENA_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down.
+                                0x00000200  // Drive pwmA Low
+#define PWM_X_GENA_ACTCMPBU_ONE 0x00000300  // Drive pwmA High
+#define PWM_X_GENA_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down
 #define PWM_X_GENA_ACTCMPAD_NONE \
-                                0x00000000  // Do nothing.
-#define PWM_X_GENA_ACTCMPAD_INV 0x00000040  // Invert the output signal.
+                                0x00000000  // Do nothing
+#define PWM_X_GENA_ACTCMPAD_INV 0x00000040  // Invert pwmA
 #define PWM_X_GENA_ACTCMPAD_ZERO \
-                                0x00000080  // Set the output signal to 0.
-#define PWM_X_GENA_ACTCMPAD_ONE 0x000000C0  // Set the output signal to 1.
-#define PWM_X_GENA_ACTCMPAU_M   0x00000030  // Action for Comparator A Up.
+                                0x00000080  // Drive pwmA Low
+#define PWM_X_GENA_ACTCMPAD_ONE 0x000000C0  // Drive pwmA High
+#define PWM_X_GENA_ACTCMPAU_M   0x00000030  // Action for Comparator A Up
 #define PWM_X_GENA_ACTCMPAU_NONE \
-                                0x00000000  // Do nothing.
-#define PWM_X_GENA_ACTCMPAU_INV 0x00000010  // Invert the output signal.
+                                0x00000000  // Do nothing
+#define PWM_X_GENA_ACTCMPAU_INV 0x00000010  // Invert pwmA
 #define PWM_X_GENA_ACTCMPAU_ZERO \
-                                0x00000020  // Set the output signal to 0.
-#define PWM_X_GENA_ACTCMPAU_ONE 0x00000030  // Set the output signal to 1.
-#define PWM_X_GENA_ACTLOAD_M    0x0000000C  // Action for Counter=Load.
-#define PWM_X_GENA_ACTLOAD_NONE 0x00000000  // Do nothing.
-#define PWM_X_GENA_ACTLOAD_INV  0x00000004  // Invert the output signal.
-#define PWM_X_GENA_ACTLOAD_ZERO 0x00000008  // Set the output signal to 0.
-#define PWM_X_GENA_ACTLOAD_ONE  0x0000000C  // Set the output signal to 1.
-#define PWM_X_GENA_ACTZERO_M    0x00000003  // Action for Counter=0.
-#define PWM_X_GENA_ACTZERO_NONE 0x00000000  // Do nothing.
-#define PWM_X_GENA_ACTZERO_INV  0x00000001  // Invert the output signal.
-#define PWM_X_GENA_ACTZERO_ZERO 0x00000002  // Set the output signal to 0.
-#define PWM_X_GENA_ACTZERO_ONE  0x00000003  // Set the output signal to 1.
+                                0x00000020  // Drive pwmA Low
+#define PWM_X_GENA_ACTCMPAU_ONE 0x00000030  // Drive pwmA High
+#define PWM_X_GENA_ACTLOAD_M    0x0000000C  // Action for Counter=LOAD
+#define PWM_X_GENA_ACTLOAD_NONE 0x00000000  // Do nothing
+#define PWM_X_GENA_ACTLOAD_INV  0x00000004  // Invert pwmA
+#define PWM_X_GENA_ACTLOAD_ZERO 0x00000008  // Drive pwmA Low
+#define PWM_X_GENA_ACTLOAD_ONE  0x0000000C  // Drive pwmA High
+#define PWM_X_GENA_ACTZERO_M    0x00000003  // Action for Counter=0
+#define PWM_X_GENA_ACTZERO_NONE 0x00000000  // Do nothing
+#define PWM_X_GENA_ACTZERO_INV  0x00000001  // Invert pwmA
+#define PWM_X_GENA_ACTZERO_ZERO 0x00000002  // Drive pwmA Low
+#define PWM_X_GENA_ACTZERO_ONE  0x00000003  // Drive pwmA High
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the PWM_O_0_GENB,
-// PWM_O_1_GENB, and PWM_O_2_GENB registers.
+// The following are defines for the bit fields in the PWM_O_X_GENB register.
 //
 //*****************************************************************************
-#define PWM_X_GENB_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down.
+#define PWM_X_GENB_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down
 #define PWM_X_GENB_ACTCMPBD_NONE \
-                                0x00000000  // Do nothing.
-#define PWM_X_GENB_ACTCMPBD_INV 0x00000400  // Invert the output signal.
+                                0x00000000  // Do nothing
+#define PWM_X_GENB_ACTCMPBD_INV 0x00000400  // Invert pwmB
 #define PWM_X_GENB_ACTCMPBD_ZERO \
-                                0x00000800  // Set the output signal to 0.
-#define PWM_X_GENB_ACTCMPBD_ONE 0x00000C00  // Set the output signal to 1.
-#define PWM_X_GENB_ACTCMPBU_M   0x00000300  // Action for Comparator B Up.
+                                0x00000800  // Drive pwmB Low
+#define PWM_X_GENB_ACTCMPBD_ONE 0x00000C00  // Drive pwmB High
+#define PWM_X_GENB_ACTCMPBU_M   0x00000300  // Action for Comparator B Up
 #define PWM_X_GENB_ACTCMPBU_NONE \
-                                0x00000000  // Do nothing.
-#define PWM_X_GENB_ACTCMPBU_INV 0x00000100  // Invert the output signal.
+                                0x00000000  // Do nothing
+#define PWM_X_GENB_ACTCMPBU_INV 0x00000100  // Invert pwmB
 #define PWM_X_GENB_ACTCMPBU_ZERO \
-                                0x00000200  // Set the output signal to 0.
-#define PWM_X_GENB_ACTCMPBU_ONE 0x00000300  // Set the output signal to 1.
-#define PWM_X_GENB_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down.
+                                0x00000200  // Drive pwmB Low
+#define PWM_X_GENB_ACTCMPBU_ONE 0x00000300  // Drive pwmB High
+#define PWM_X_GENB_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down
 #define PWM_X_GENB_ACTCMPAD_NONE \
-                                0x00000000  // Do nothing.
-#define PWM_X_GENB_ACTCMPAD_INV 0x00000040  // Invert the output signal.
+                                0x00000000  // Do nothing
+#define PWM_X_GENB_ACTCMPAD_INV 0x00000040  // Invert pwmB
 #define PWM_X_GENB_ACTCMPAD_ZERO \
-                                0x00000080  // Set the output signal to 0.
-#define PWM_X_GENB_ACTCMPAD_ONE 0x000000C0  // Set the output signal to 1.
-#define PWM_X_GENB_ACTCMPAU_M   0x00000030  // Action for Comparator A Up.
+                                0x00000080  // Drive pwmB Low
+#define PWM_X_GENB_ACTCMPAD_ONE 0x000000C0  // Drive pwmB High
+#define PWM_X_GENB_ACTCMPAU_M   0x00000030  // Action for Comparator A Up
 #define PWM_X_GENB_ACTCMPAU_NONE \
-                                0x00000000  // Do nothing.
-#define PWM_X_GENB_ACTCMPAU_INV 0x00000010  // Invert the output signal.
+                                0x00000000  // Do nothing
+#define PWM_X_GENB_ACTCMPAU_INV 0x00000010  // Invert pwmB
 #define PWM_X_GENB_ACTCMPAU_ZERO \
-                                0x00000020  // Set the output signal to 0.
-#define PWM_X_GENB_ACTCMPAU_ONE 0x00000030  // Set the output signal to 1.
-#define PWM_X_GENB_ACTLOAD_M    0x0000000C  // Action for Counter=Load.
-#define PWM_X_GENB_ACTLOAD_NONE 0x00000000  // Do nothing.
-#define PWM_X_GENB_ACTLOAD_INV  0x00000004  // Invert the output signal.
-#define PWM_X_GENB_ACTLOAD_ZERO 0x00000008  // Set the output signal to 0.
-#define PWM_X_GENB_ACTLOAD_ONE  0x0000000C  // Set the output signal to 1.
-#define PWM_X_GENB_ACTZERO_M    0x00000003  // Action for Counter=0.
-#define PWM_X_GENB_ACTZERO_NONE 0x00000000  // Do nothing.
-#define PWM_X_GENB_ACTZERO_INV  0x00000001  // Invert the output signal.
-#define PWM_X_GENB_ACTZERO_ZERO 0x00000002  // Set the output signal to 0.
-#define PWM_X_GENB_ACTZERO_ONE  0x00000003  // Set the output signal to 1.
+                                0x00000020  // Drive pwmB Low
+#define PWM_X_GENB_ACTCMPAU_ONE 0x00000030  // Drive pwmB High
+#define PWM_X_GENB_ACTLOAD_M    0x0000000C  // Action for Counter=LOAD
+#define PWM_X_GENB_ACTLOAD_NONE 0x00000000  // Do nothing
+#define PWM_X_GENB_ACTLOAD_INV  0x00000004  // Invert pwmB
+#define PWM_X_GENB_ACTLOAD_ZERO 0x00000008  // Drive pwmB Low
+#define PWM_X_GENB_ACTLOAD_ONE  0x0000000C  // Drive pwmB High
+#define PWM_X_GENB_ACTZERO_M    0x00000003  // Action for Counter=0
+#define PWM_X_GENB_ACTZERO_NONE 0x00000000  // Do nothing
+#define PWM_X_GENB_ACTZERO_INV  0x00000001  // Invert pwmB
+#define PWM_X_GENB_ACTZERO_ZERO 0x00000002  // Drive pwmB Low
+#define PWM_X_GENB_ACTZERO_ONE  0x00000003  // Drive pwmB High
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the PWM_O_0_DBCTL,
-// PWM_O_1_DBCTL, and PWM_O_2_DBCTL registers.
+// The following are defines for the bit fields in the PWM_O_X_DBCTL register.
 //
 //*****************************************************************************
-#define PWM_X_DBCTL_ENABLE      0x00000001  // Dead-Band Generator Enable.
+#define PWM_X_DBCTL_ENABLE      0x00000001  // Dead-Band Generator Enable
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the PWM_O_0_DBRISE,
-// PWM_O_1_DBRISE, and PWM_O_2_DBRISE registers.
+// The following are defines for the bit fields in the PWM_O_X_DBRISE register.
 //
 //*****************************************************************************
-#define PWM_X_DBRISE_DELAY_M    0x00000FFF  // Dead-Band Rise Delay.
+#define PWM_X_DBRISE_DELAY_M    0x00000FFF  // Dead-Band Rise Delay
 #define PWM_X_DBRISE_DELAY_S    0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the PWM_O_0_DBFALL,
-// PWM_O_1_DBFALL, and PWM_O_2_DBFALL registers.
+// The following are defines for the bit fields in the PWM_O_X_DBFALL register.
 //
 //*****************************************************************************
-#define PWM_X_DBFALL_DELAY_M    0x00000FFF  // Dead-Band Fall Delay.
+#define PWM_X_DBFALL_DELAY_M    0x00000FFF  // Dead-Band Fall Delay
 #define PWM_X_DBFALL_DELAY_S    0
 
 //*****************************************************************************
@@ -1619,33 +1593,33 @@
 // The following are defines for the bit fields in the QEI_O_CTL register.
 //
 //*****************************************************************************
-#define QEI_CTL_STALLEN         0x00001000  // Stall QEI.
-#define QEI_CTL_INVI            0x00000800  // Invert Index Pulse.
-#define QEI_CTL_INVB            0x00000400  // Invert PhB.
-#define QEI_CTL_INVA            0x00000200  // Invert PhA.
-#define QEI_CTL_VELDIV_M        0x000001C0  // Predivide Velocity.
-#define QEI_CTL_VELDIV_1        0x00000000  // /1
-#define QEI_CTL_VELDIV_2        0x00000040  // /2
-#define QEI_CTL_VELDIV_4        0x00000080  // /4
-#define QEI_CTL_VELDIV_8        0x000000C0  // /8
-#define QEI_CTL_VELDIV_16       0x00000100  // /16
-#define QEI_CTL_VELDIV_32       0x00000140  // /32
-#define QEI_CTL_VELDIV_64       0x00000180  // /64
-#define QEI_CTL_VELDIV_128      0x000001C0  // /128
-#define QEI_CTL_VELEN           0x00000020  // Capture Velocity.
-#define QEI_CTL_RESMODE         0x00000010  // Reset Mode.
-#define QEI_CTL_CAPMODE         0x00000008  // Capture Mode.
-#define QEI_CTL_SIGMODE         0x00000004  // Signal Mode.
-#define QEI_CTL_SWAP            0x00000002  // Swap Signals.
-#define QEI_CTL_ENABLE          0x00000001  // Enable QEI.
+#define QEI_CTL_STALLEN         0x00001000  // Stall QEI
+#define QEI_CTL_INVI            0x00000800  // Invert Index Pulse
+#define QEI_CTL_INVB            0x00000400  // Invert PhB
+#define QEI_CTL_INVA            0x00000200  // Invert PhA
+#define QEI_CTL_VELDIV_M        0x000001C0  // Predivide Velocity
+#define QEI_CTL_VELDIV_1        0x00000000  // QEI clock /1
+#define QEI_CTL_VELDIV_2        0x00000040  // QEI clock /2
+#define QEI_CTL_VELDIV_4        0x00000080  // QEI clock /4
+#define QEI_CTL_VELDIV_8        0x000000C0  // QEI clock /8
+#define QEI_CTL_VELDIV_16       0x00000100  // QEI clock /16
+#define QEI_CTL_VELDIV_32       0x00000140  // QEI clock /32
+#define QEI_CTL_VELDIV_64       0x00000180  // QEI clock /64
+#define QEI_CTL_VELDIV_128      0x000001C0  // QEI clock /128
+#define QEI_CTL_VELEN           0x00000020  // Capture Velocity
+#define QEI_CTL_RESMODE         0x00000010  // Reset Mode
+#define QEI_CTL_CAPMODE         0x00000008  // Capture Mode
+#define QEI_CTL_SIGMODE         0x00000004  // Signal Mode
+#define QEI_CTL_SWAP            0x00000002  // Swap Signals
+#define QEI_CTL_ENABLE          0x00000001  // Enable QEI
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the QEI_O_STAT register.
 //
 //*****************************************************************************
-#define QEI_STAT_DIRECTION      0x00000002  // Direction of Rotation.
-#define QEI_STAT_ERROR          0x00000001  // Error Detected.
+#define QEI_STAT_DIRECTION      0x00000002  // Direction of Rotation
+#define QEI_STAT_ERROR          0x00000001  // Error Detected
 
 //*****************************************************************************
 //
@@ -1653,7 +1627,7 @@
 //
 //*****************************************************************************
 #define QEI_POS_M               0xFFFFFFFF  // Current Position Integrator
-                                            // Value.
+                                            // Value
 #define QEI_POS_S               0
 
 //*****************************************************************************
@@ -1662,7 +1636,7 @@
 //
 //*****************************************************************************
 #define QEI_MAXPOS_M            0xFFFFFFFF  // Maximum Position Integrator
-                                            // Value.
+                                            // Value
 #define QEI_MAXPOS_S            0
 
 //*****************************************************************************
@@ -1670,7 +1644,7 @@
 // The following are defines for the bit fields in the QEI_O_LOAD register.
 //
 //*****************************************************************************
-#define QEI_LOAD_M              0xFFFFFFFF  // Velocity Timer Load Value.
+#define QEI_LOAD_M              0xFFFFFFFF  // Velocity Timer Load Value
 #define QEI_LOAD_S              0
 
 //*****************************************************************************
@@ -1678,7 +1652,7 @@
 // The following are defines for the bit fields in the QEI_O_TIME register.
 //
 //*****************************************************************************
-#define QEI_TIME_M              0xFFFFFFFF  // Velocity Timer Current Value.
+#define QEI_TIME_M              0xFFFFFFFF  // Velocity Timer Current Value
 #define QEI_TIME_S              0
 
 //*****************************************************************************
@@ -1686,7 +1660,7 @@
 // The following are defines for the bit fields in the QEI_O_COUNT register.
 //
 //*****************************************************************************
-#define QEI_COUNT_M             0xFFFFFFFF  // Velocity Pulse Count.
+#define QEI_COUNT_M             0xFFFFFFFF  // Velocity Pulse Count
 #define QEI_COUNT_S             0
 
 //*****************************************************************************
@@ -1694,7 +1668,7 @@
 // The following are defines for the bit fields in the QEI_O_SPEED register.
 //
 //*****************************************************************************
-#define QEI_SPEED_M             0xFFFFFFFF  // Velocity.
+#define QEI_SPEED_M             0xFFFFFFFF  // Velocity
 #define QEI_SPEED_S             0
 
 //*****************************************************************************
@@ -1702,56 +1676,55 @@
 // The following are defines for the bit fields in the QEI_O_INTEN register.
 //
 //*****************************************************************************
-#define QEI_INTEN_ERROR         0x00000008  // Phase Error Interrupt Enable.
+#define QEI_INTEN_ERROR         0x00000008  // Phase Error Interrupt Enable
 #define QEI_INTEN_DIR           0x00000004  // Direction Change Interrupt
-                                            // Enable.
-#define QEI_INTEN_TIMER         0x00000002  // Timer Expires Interrupt Enable.
+                                            // Enable
+#define QEI_INTEN_TIMER         0x00000002  // Timer Expires Interrupt Enable
 #define QEI_INTEN_INDEX         0x00000001  // Index Pulse Detected Interrupt
-                                            // Enable.
+                                            // Enable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the QEI_O_RIS register.
 //
 //*****************************************************************************
-#define QEI_RIS_ERROR           0x00000008  // Phase Error Detected.
-#define QEI_RIS_DIR             0x00000004  // Direction Change Detected.
-#define QEI_RIS_TIMER           0x00000002  // Velocity Timer Expired.
-#define QEI_RIS_INDEX           0x00000001  // Index Pulse Asserted.
+#define QEI_RIS_ERROR           0x00000008  // Phase Error Detected
+#define QEI_RIS_DIR             0x00000004  // Direction Change Detected
+#define QEI_RIS_TIMER           0x00000002  // Velocity Timer Expired
+#define QEI_RIS_INDEX           0x00000001  // Index Pulse Asserted
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the QEI_O_ISC register.
 //
 //*****************************************************************************
-#define QEI_ISC_ERROR           0x00000008  // Phase Error Interrupt.
-#define QEI_ISC_DIR             0x00000004  // Direction Change Interrupt.
-#define QEI_ISC_TIMER           0x00000002  // Velocity Timer Expired
-                                            // Interrupt.
-#define QEI_ISC_INDEX           0x00000001  // Index Pulse Interrupt.
+#define QEI_ISC_ERROR           0x00000008  // Phase Error Interrupt
+#define QEI_ISC_DIR             0x00000004  // Direction Change Interrupt
+#define QEI_ISC_TIMER           0x00000002  // Velocity Timer Expired Interrupt
+#define QEI_ISC_INDEX           0x00000001  // Index Pulse Interrupt
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the TIMER_O_CFG register.
 //
 //*****************************************************************************
-#define TIMER_CFG_M             0x00000007  // GPTM Configuration.
-#define TIMER_CFG_32_BIT_TIMER  0x00000000  // 32-bit timer configuration.
+#define TIMER_CFG_M             0x00000007  // GPTM Configuration
+#define TIMER_CFG_32_BIT_TIMER  0x00000000  // 32-bit timer configuration
 #define TIMER_CFG_32_BIT_RTC    0x00000001  // 32-bit real-time clock (RTC)
-                                            // counter configuration.
-#define TIMER_CFG_16_BIT        0x00000004  // 16-bit timer configuration,
+                                            // counter configuration
+#define TIMER_CFG_16_BIT        0x00000004  // 16-bit timer configuration. The
                                             // function is controlled by bits
-                                            // 1:0 of GPTMTAMR and GPTMTBMR.
+                                            // 1:0 of GPTMTAMR and GPTMTBMR
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the TIMER_O_TAMR register.
 //
 //*****************************************************************************
-#define TIMER_TAMR_TAAMS        0x00000008  // GPTM TimerA Alternate Mode
-                                            // Select.
-#define TIMER_TAMR_TACMR        0x00000004  // GPTM TimerA Capture Mode.
-#define TIMER_TAMR_TAMR_M       0x00000003  // GPTM TimerA Mode.
+#define TIMER_TAMR_TAAMS        0x00000008  // GPTM Timer A Alternate Mode
+                                            // Select
+#define TIMER_TAMR_TACMR        0x00000004  // GPTM Timer A Capture Mode
+#define TIMER_TAMR_TAMR_M       0x00000003  // GPTM Timer A Mode
 #define TIMER_TAMR_TAMR_1_SHOT  0x00000001  // One-Shot Timer mode
 #define TIMER_TAMR_TAMR_PERIOD  0x00000002  // Periodic Timer mode
 #define TIMER_TAMR_TAMR_CAP     0x00000003  // Capture mode
@@ -1761,10 +1734,10 @@
 // The following are defines for the bit fields in the TIMER_O_TBMR register.
 //
 //*****************************************************************************
-#define TIMER_TBMR_TBAMS        0x00000008  // GPTM TimerB Alternate Mode
-                                            // Select.
-#define TIMER_TBMR_TBCMR        0x00000004  // GPTM TimerB Capture Mode.
-#define TIMER_TBMR_TBMR_M       0x00000003  // GPTM TimerB Mode.
+#define TIMER_TBMR_TBAMS        0x00000008  // GPTM Timer B Alternate Mode
+                                            // Select
+#define TIMER_TBMR_TBCMR        0x00000004  // GPTM Timer B Capture Mode
+#define TIMER_TBMR_TBMR_M       0x00000003  // GPTM Timer B Mode
 #define TIMER_TBMR_TBMR_1_SHOT  0x00000001  // One-Shot Timer mode
 #define TIMER_TBMR_TBMR_PERIOD  0x00000002  // Periodic Timer mode
 #define TIMER_TBMR_TBMR_CAP     0x00000003  // Capture mode
@@ -1774,111 +1747,111 @@
 // The following are defines for the bit fields in the TIMER_O_CTL register.
 //
 //*****************************************************************************
-#define TIMER_CTL_TBPWML        0x00004000  // GPTM TimerB PWM Output Level.
-#define TIMER_CTL_TBOTE         0x00002000  // GPTM TimerB Output Trigger
-                                            // Enable.
-#define TIMER_CTL_TBEVENT_M     0x00000C00  // GPTM TimerB Event Mode.
+#define TIMER_CTL_TBPWML        0x00004000  // GPTM Timer B PWM Output Level
+#define TIMER_CTL_TBOTE         0x00002000  // GPTM Timer B Output Trigger
+                                            // Enable
+#define TIMER_CTL_TBEVENT_M     0x00000C00  // GPTM Timer B Event Mode
 #define TIMER_CTL_TBEVENT_POS   0x00000000  // Positive edge
 #define TIMER_CTL_TBEVENT_NEG   0x00000400  // Negative edge
 #define TIMER_CTL_TBEVENT_BOTH  0x00000C00  // Both edges
-#define TIMER_CTL_TBSTALL       0x00000200  // GPTM TimerB Stall Enable.
-#define TIMER_CTL_TBEN          0x00000100  // GPTM TimerB Enable.
-#define TIMER_CTL_TAPWML        0x00000040  // GPTM TimerA PWM Output Level.
-#define TIMER_CTL_TAOTE         0x00000020  // GPTM TimerA Output Trigger
-                                            // Enable.
-#define TIMER_CTL_RTCEN         0x00000010  // GPTM RTC Enable.
-#define TIMER_CTL_TAEVENT_M     0x0000000C  // GPTM TimerA Event Mode.
+#define TIMER_CTL_TBSTALL       0x00000200  // GPTM Timer B Stall Enable
+#define TIMER_CTL_TBEN          0x00000100  // GPTM Timer B Enable
+#define TIMER_CTL_TAPWML        0x00000040  // GPTM Timer A PWM Output Level
+#define TIMER_CTL_TAOTE         0x00000020  // GPTM Timer A Output Trigger
+                                            // Enable
+#define TIMER_CTL_RTCEN         0x00000010  // GPTM RTC Enable
+#define TIMER_CTL_TAEVENT_M     0x0000000C  // GPTM Timer A Event Mode
 #define TIMER_CTL_TAEVENT_POS   0x00000000  // Positive edge
 #define TIMER_CTL_TAEVENT_NEG   0x00000004  // Negative edge
 #define TIMER_CTL_TAEVENT_BOTH  0x0000000C  // Both edges
-#define TIMER_CTL_TASTALL       0x00000002  // GPTM TimerA Stall Enable.
-#define TIMER_CTL_TAEN          0x00000001  // GPTM TimerA Enable.
+#define TIMER_CTL_TASTALL       0x00000002  // GPTM Timer A Stall Enable
+#define TIMER_CTL_TAEN          0x00000001  // GPTM Timer A Enable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the TIMER_O_IMR register.
 //
 //*****************************************************************************
-#define TIMER_IMR_CBEIM         0x00000400  // GPTM CaptureB Event Interrupt
-                                            // Mask.
-#define TIMER_IMR_CBMIM         0x00000200  // GPTM CaptureB Match Interrupt
-                                            // Mask.
-#define TIMER_IMR_TBTOIM        0x00000100  // GPTM TimerB Time-Out Interrupt
-                                            // Mask.
-#define TIMER_IMR_RTCIM         0x00000008  // GPTM RTC Interrupt Mask.
-#define TIMER_IMR_CAEIM         0x00000004  // GPTM CaptureA Event Interrupt
-                                            // Mask.
-#define TIMER_IMR_CAMIM         0x00000002  // GPTM CaptureA Match Interrupt
-                                            // Mask.
-#define TIMER_IMR_TATOIM        0x00000001  // GPTM TimerA Time-Out Interrupt
-                                            // Mask.
+#define TIMER_IMR_CBEIM         0x00000400  // GPTM Capture B Event Interrupt
+                                            // Mask
+#define TIMER_IMR_CBMIM         0x00000200  // GPTM Capture B Match Interrupt
+                                            // Mask
+#define TIMER_IMR_TBTOIM        0x00000100  // GPTM Timer B Time-Out Interrupt
+                                            // Mask
+#define TIMER_IMR_RTCIM         0x00000008  // GPTM RTC Interrupt Mask
+#define TIMER_IMR_CAEIM         0x00000004  // GPTM Capture A Event Interrupt
+                                            // Mask
+#define TIMER_IMR_CAMIM         0x00000002  // GPTM Capture A Match Interrupt
+                                            // Mask
+#define TIMER_IMR_TATOIM        0x00000001  // GPTM Timer A Time-Out Interrupt
+                                            // Mask
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the TIMER_O_RIS register.
 //
 //*****************************************************************************
-#define TIMER_RIS_CBERIS        0x00000400  // GPTM CaptureB Event Raw
-                                            // Interrupt.
-#define TIMER_RIS_CBMRIS        0x00000200  // GPTM CaptureB Match Raw
-                                            // Interrupt.
-#define TIMER_RIS_TBTORIS       0x00000100  // GPTM TimerB Time-Out Raw
-                                            // Interrupt.
-#define TIMER_RIS_RTCRIS        0x00000008  // GPTM RTC Raw Interrupt.
-#define TIMER_RIS_CAERIS        0x00000004  // GPTM CaptureA Event Raw
-                                            // Interrupt.
-#define TIMER_RIS_CAMRIS        0x00000002  // GPTM CaptureA Match Raw
-                                            // Interrupt.
-#define TIMER_RIS_TATORIS       0x00000001  // GPTM TimerA Time-Out Raw
-                                            // Interrupt.
+#define TIMER_RIS_CBERIS        0x00000400  // GPTM Capture B Event Raw
+                                            // Interrupt
+#define TIMER_RIS_CBMRIS        0x00000200  // GPTM Capture B Match Raw
+                                            // Interrupt
+#define TIMER_RIS_TBTORIS       0x00000100  // GPTM Timer B Time-Out Raw
+                                            // Interrupt
+#define TIMER_RIS_RTCRIS        0x00000008  // GPTM RTC Raw Interrupt
+#define TIMER_RIS_CAERIS        0x00000004  // GPTM Capture A Event Raw
+                                            // Interrupt
+#define TIMER_RIS_CAMRIS        0x00000002  // GPTM Capture A Match Raw
+                                            // Interrupt
+#define TIMER_RIS_TATORIS       0x00000001  // GPTM Timer A Time-Out Raw
+                                            // Interrupt
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the TIMER_O_MIS register.
 //
 //*****************************************************************************
-#define TIMER_MIS_CBEMIS        0x00000400  // GPTM CaptureB Event Masked
-                                            // Interrupt.
-#define TIMER_MIS_CBMMIS        0x00000200  // GPTM CaptureB Match Masked
-                                            // Interrupt.
-#define TIMER_MIS_TBTOMIS       0x00000100  // GPTM TimerB Time-Out Masked
-                                            // Interrupt.
-#define TIMER_MIS_RTCMIS        0x00000008  // GPTM RTC Masked Interrupt.
-#define TIMER_MIS_CAEMIS        0x00000004  // GPTM CaptureA Event Masked
-                                            // Interrupt.
-#define TIMER_MIS_CAMMIS        0x00000002  // GPTM CaptureA Match Masked
-                                            // Interrupt.
-#define TIMER_MIS_TATOMIS       0x00000001  // GPTM TimerA Time-Out Masked
-                                            // Interrupt.
+#define TIMER_MIS_CBEMIS        0x00000400  // GPTM Capture B Event Masked
+                                            // Interrupt
+#define TIMER_MIS_CBMMIS        0x00000200  // GPTM Capture B Match Masked
+                                            // Interrupt
+#define TIMER_MIS_TBTOMIS       0x00000100  // GPTM Timer B Time-Out Masked
+                                            // Interrupt
+#define TIMER_MIS_RTCMIS        0x00000008  // GPTM RTC Masked Interrupt
+#define TIMER_MIS_CAEMIS        0x00000004  // GPTM Capture A Event Masked
+                                            // Interrupt
+#define TIMER_MIS_CAMMIS        0x00000002  // GPTM Capture A Match Masked
+                                            // Interrupt
+#define TIMER_MIS_TATOMIS       0x00000001  // GPTM Timer A Time-Out Masked
+                                            // Interrupt
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the TIMER_O_ICR register.
 //
 //*****************************************************************************
-#define TIMER_ICR_CBECINT       0x00000400  // GPTM CaptureB Event Interrupt
-                                            // Clear.
-#define TIMER_ICR_CBMCINT       0x00000200  // GPTM CaptureB Match Interrupt
-                                            // Clear.
-#define TIMER_ICR_TBTOCINT      0x00000100  // GPTM TimerB Time-Out Interrupt
-                                            // Clear.
-#define TIMER_ICR_RTCCINT       0x00000008  // GPTM RTC Interrupt Clear.
-#define TIMER_ICR_CAECINT       0x00000004  // GPTM CaptureA Event Interrupt
-                                            // Clear.
-#define TIMER_ICR_CAMCINT       0x00000002  // GPTM CaptureA Match Raw
-                                            // Interrupt.
-#define TIMER_ICR_TATOCINT      0x00000001  // GPTM TimerA Time-Out Raw
-                                            // Interrupt.
+#define TIMER_ICR_CBECINT       0x00000400  // GPTM Capture B Event Interrupt
+                                            // Clear
+#define TIMER_ICR_CBMCINT       0x00000200  // GPTM Capture B Match Interrupt
+                                            // Clear
+#define TIMER_ICR_TBTOCINT      0x00000100  // GPTM Timer B Time-Out Interrupt
+                                            // Clear
+#define TIMER_ICR_RTCCINT       0x00000008  // GPTM RTC Interrupt Clear
+#define TIMER_ICR_CAECINT       0x00000004  // GPTM Capture A Event Interrupt
+                                            // Clear
+#define TIMER_ICR_CAMCINT       0x00000002  // GPTM Capture A Match Interrupt
+                                            // Clear
+#define TIMER_ICR_TATOCINT      0x00000001  // GPTM Timer A Time-Out Raw
+                                            // Interrupt
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the TIMER_O_TAILR register.
 //
 //*****************************************************************************
-#define TIMER_TAILR_TAILRH_M    0xFFFF0000  // GPTM TimerA Interval Load
-                                            // Register High.
-#define TIMER_TAILR_TAILRL_M    0x0000FFFF  // GPTM TimerA Interval Load
-                                            // Register Low.
+#define TIMER_TAILR_TAILRH_M    0xFFFF0000  // GPTM Timer A Interval Load
+                                            // Register High
+#define TIMER_TAILR_TAILRL_M    0x0000FFFF  // GPTM Timer A Interval Load
+                                            // Register Low
 #define TIMER_TAILR_TAILRH_S    16
 #define TIMER_TAILR_TAILRL_S    0
 
@@ -1887,8 +1860,8 @@
 // The following are defines for the bit fields in the TIMER_O_TBILR register.
 //
 //*****************************************************************************
-#define TIMER_TBILR_TBILRL_M    0x0000FFFF  // GPTM TimerB Interval Load
-                                            // Register.
+#define TIMER_TBILR_TBILRL_M    0x0000FFFF  // GPTM Timer B Interval Load
+                                            // Register
 #define TIMER_TBILR_TBILRL_S    0
 
 //*****************************************************************************
@@ -1897,8 +1870,8 @@
 // register.
 //
 //*****************************************************************************
-#define TIMER_TAMATCHR_TAMRH_M  0xFFFF0000  // GPTM TimerA Match Register High.
-#define TIMER_TAMATCHR_TAMRL_M  0x0000FFFF  // GPTM TimerA Match Register Low.
+#define TIMER_TAMATCHR_TAMRH_M  0xFFFF0000  // GPTM Timer A Match Register High
+#define TIMER_TAMATCHR_TAMRL_M  0x0000FFFF  // GPTM Timer A Match Register Low
 #define TIMER_TAMATCHR_TAMRH_S  16
 #define TIMER_TAMATCHR_TAMRL_S  0
 
@@ -1908,7 +1881,7 @@
 // register.
 //
 //*****************************************************************************
-#define TIMER_TBMATCHR_TBMRL_M  0x0000FFFF  // GPTM TimerB Match Register Low.
+#define TIMER_TBMATCHR_TBMRL_M  0x0000FFFF  // GPTM Timer B Match Register Low
 #define TIMER_TBMATCHR_TBMRL_S  0
 
 //*****************************************************************************
@@ -1916,7 +1889,7 @@
 // The following are defines for the bit fields in the TIMER_O_TAPR register.
 //
 //*****************************************************************************
-#define TIMER_TAPR_TAPSR_M      0x000000FF  // GPTM TimerA Prescale.
+#define TIMER_TAPR_TAPSR_M      0x000000FF  // GPTM Timer A Prescale
 #define TIMER_TAPR_TAPSR_S      0
 
 //*****************************************************************************
@@ -1924,7 +1897,7 @@
 // The following are defines for the bit fields in the TIMER_O_TBPR register.
 //
 //*****************************************************************************
-#define TIMER_TBPR_TBPSR_M      0x000000FF  // GPTM TimerB Prescale.
+#define TIMER_TBPR_TBPSR_M      0x000000FF  // GPTM Timer B Prescale
 #define TIMER_TBPR_TBPSR_S      0
 
 //*****************************************************************************
@@ -1932,7 +1905,7 @@
 // The following are defines for the bit fields in the TIMER_O_TAPMR register.
 //
 //*****************************************************************************
-#define TIMER_TAPMR_TAPSMR_M    0x000000FF  // GPTM TimerA Prescale Match.
+#define TIMER_TAPMR_TAPSMR_M    0x000000FF  // GPTM TimerA Prescale Match
 #define TIMER_TAPMR_TAPSMR_S    0
 
 //*****************************************************************************
@@ -1940,7 +1913,7 @@
 // The following are defines for the bit fields in the TIMER_O_TBPMR register.
 //
 //*****************************************************************************
-#define TIMER_TBPMR_TBPSMR_M    0x000000FF  // GPTM TimerB Prescale Match.
+#define TIMER_TBPMR_TBPSMR_M    0x000000FF  // GPTM TimerB Prescale Match
 #define TIMER_TBPMR_TBPSMR_S    0
 
 //*****************************************************************************
@@ -1948,8 +1921,8 @@
 // The following are defines for the bit fields in the TIMER_O_TAR register.
 //
 //*****************************************************************************
-#define TIMER_TAR_TARH_M        0xFFFF0000  // GPTM TimerA Register High.
-#define TIMER_TAR_TARL_M        0x0000FFFF  // GPTM TimerA Register Low.
+#define TIMER_TAR_TARH_M        0xFFFF0000  // GPTM Timer A Register High
+#define TIMER_TAR_TARL_M        0x0000FFFF  // GPTM Timer A Register Low
 #define TIMER_TAR_TARH_S        16
 #define TIMER_TAR_TARL_S        0
 
@@ -1958,7 +1931,7 @@
 // The following are defines for the bit fields in the TIMER_O_TBR register.
 //
 //*****************************************************************************
-#define TIMER_TBR_TBRL_M        0x0000FFFF  // GPTM TimerB.
+#define TIMER_TBR_TBRL_M        0x0000FFFF  // GPTM Timer B
 #define TIMER_TBR_TBRL_S        0
 
 //*****************************************************************************
@@ -1966,58 +1939,58 @@
 // The following are defines for the bit fields in the ADC_O_ACTSS register.
 //
 //*****************************************************************************
-#define ADC_ACTSS_ASEN3         0x00000008  // ADC SS3 Enable.
-#define ADC_ACTSS_ASEN2         0x00000004  // ADC SS2 Enable.
-#define ADC_ACTSS_ASEN1         0x00000002  // ADC SS1 Enable.
-#define ADC_ACTSS_ASEN0         0x00000001  // ADC SS0 Enable.
+#define ADC_ACTSS_ASEN3         0x00000008  // ADC SS3 Enable
+#define ADC_ACTSS_ASEN2         0x00000004  // ADC SS2 Enable
+#define ADC_ACTSS_ASEN1         0x00000002  // ADC SS1 Enable
+#define ADC_ACTSS_ASEN0         0x00000001  // ADC SS0 Enable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the ADC_O_RIS register.
 //
 //*****************************************************************************
-#define ADC_RIS_INR3            0x00000008  // SS3 Raw Interrupt Status.
-#define ADC_RIS_INR2            0x00000004  // SS2 Raw Interrupt Status.
-#define ADC_RIS_INR1            0x00000002  // SS1 Raw Interrupt Status.
-#define ADC_RIS_INR0            0x00000001  // SS0 Raw Interrupt Status.
+#define ADC_RIS_INR3            0x00000008  // SS3 Raw Interrupt Status
+#define ADC_RIS_INR2            0x00000004  // SS2 Raw Interrupt Status
+#define ADC_RIS_INR1            0x00000002  // SS1 Raw Interrupt Status
+#define ADC_RIS_INR0            0x00000001  // SS0 Raw Interrupt Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the ADC_O_IM register.
 //
 //*****************************************************************************
-#define ADC_IM_MASK3            0x00000008  // SS3 Interrupt Mask.
-#define ADC_IM_MASK2            0x00000004  // SS2 Interrupt Mask.
-#define ADC_IM_MASK1            0x00000002  // SS1 Interrupt Mask.
-#define ADC_IM_MASK0            0x00000001  // SS0 Interrupt Mask.
+#define ADC_IM_MASK3            0x00000008  // SS3 Interrupt Mask
+#define ADC_IM_MASK2            0x00000004  // SS2 Interrupt Mask
+#define ADC_IM_MASK1            0x00000002  // SS1 Interrupt Mask
+#define ADC_IM_MASK0            0x00000001  // SS0 Interrupt Mask
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the ADC_O_ISC register.
 //
 //*****************************************************************************
-#define ADC_ISC_IN3             0x00000008  // SS3 Interrupt Status and Clear.
-#define ADC_ISC_IN2             0x00000004  // SS2 Interrupt Status and Clear.
-#define ADC_ISC_IN1             0x00000002  // SS1 Interrupt Status and Clear.
-#define ADC_ISC_IN0             0x00000001  // SS0 Interrupt Status and Clear.
+#define ADC_ISC_IN3             0x00000008  // SS3 Interrupt Status and Clear
+#define ADC_ISC_IN2             0x00000004  // SS2 Interrupt Status and Clear
+#define ADC_ISC_IN1             0x00000002  // SS1 Interrupt Status and Clear
+#define ADC_ISC_IN0             0x00000001  // SS0 Interrupt Status and Clear
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the ADC_O_OSTAT register.
 //
 //*****************************************************************************
-#define ADC_OSTAT_OV3           0x00000008  // SS3 FIFO Overflow.
-#define ADC_OSTAT_OV2           0x00000004  // SS2 FIFO Overflow.
-#define ADC_OSTAT_OV1           0x00000002  // SS1 FIFO Overflow.
-#define ADC_OSTAT_OV0           0x00000001  // SS0 FIFO Overflow.
+#define ADC_OSTAT_OV3           0x00000008  // SS3 FIFO Overflow
+#define ADC_OSTAT_OV2           0x00000004  // SS2 FIFO Overflow
+#define ADC_OSTAT_OV1           0x00000002  // SS1 FIFO Overflow
+#define ADC_OSTAT_OV0           0x00000001  // SS0 FIFO Overflow
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the ADC_O_EMUX register.
 //
 //*****************************************************************************
-#define ADC_EMUX_EM3_M          0x0000F000  // SS3 Trigger Select.
-#define ADC_EMUX_EM3_PROCESSOR  0x00000000  // Controller (default)
+#define ADC_EMUX_EM3_M          0x0000F000  // SS3 Trigger Select
+#define ADC_EMUX_EM3_PROCESSOR  0x00000000  // Processor (default)
 #define ADC_EMUX_EM3_COMP0      0x00001000  // Analog Comparator 0
 #define ADC_EMUX_EM3_COMP1      0x00002000  // Analog Comparator 1
 #define ADC_EMUX_EM3_EXTERNAL   0x00004000  // External (GPIO PB4)
@@ -2026,8 +1999,8 @@
 #define ADC_EMUX_EM3_PWM1       0x00007000  // PWM1
 #define ADC_EMUX_EM3_PWM2       0x00008000  // PWM2
 #define ADC_EMUX_EM3_ALWAYS     0x0000F000  // Always (continuously sample)
-#define ADC_EMUX_EM2_M          0x00000F00  // SS2 Trigger Select.
-#define ADC_EMUX_EM2_PROCESSOR  0x00000000  // Controller (default)
+#define ADC_EMUX_EM2_M          0x00000F00  // SS2 Trigger Select
+#define ADC_EMUX_EM2_PROCESSOR  0x00000000  // Processor (default)
 #define ADC_EMUX_EM2_COMP0      0x00000100  // Analog Comparator 0
 #define ADC_EMUX_EM2_COMP1      0x00000200  // Analog Comparator 1
 #define ADC_EMUX_EM2_EXTERNAL   0x00000400  // External (GPIO PB4)
@@ -2036,8 +2009,8 @@
 #define ADC_EMUX_EM2_PWM1       0x00000700  // PWM1
 #define ADC_EMUX_EM2_PWM2       0x00000800  // PWM2
 #define ADC_EMUX_EM2_ALWAYS     0x00000F00  // Always (continuously sample)
-#define ADC_EMUX_EM1_M          0x000000F0  // SS1 Trigger Select.
-#define ADC_EMUX_EM1_PROCESSOR  0x00000000  // Controller (default)
+#define ADC_EMUX_EM1_M          0x000000F0  // SS1 Trigger Select
+#define ADC_EMUX_EM1_PROCESSOR  0x00000000  // Processor (default)
 #define ADC_EMUX_EM1_COMP0      0x00000010  // Analog Comparator 0
 #define ADC_EMUX_EM1_COMP1      0x00000020  // Analog Comparator 1
 #define ADC_EMUX_EM1_EXTERNAL   0x00000040  // External (GPIO PB4)
@@ -2046,8 +2019,8 @@
 #define ADC_EMUX_EM1_PWM1       0x00000070  // PWM1
 #define ADC_EMUX_EM1_PWM2       0x00000080  // PWM2
 #define ADC_EMUX_EM1_ALWAYS     0x000000F0  // Always (continuously sample)
-#define ADC_EMUX_EM0_M          0x0000000F  // SS0 Trigger Select.
-#define ADC_EMUX_EM0_PROCESSOR  0x00000000  // Controller (default)
+#define ADC_EMUX_EM0_M          0x0000000F  // SS0 Trigger Select
+#define ADC_EMUX_EM0_PROCESSOR  0x00000000  // Processor (default)
 #define ADC_EMUX_EM0_COMP0      0x00000001  // Analog Comparator 0
 #define ADC_EMUX_EM0_COMP1      0x00000002  // Analog Comparator 1
 #define ADC_EMUX_EM0_EXTERNAL   0x00000004  // External (GPIO PB4)
@@ -2062,32 +2035,32 @@
 // The following are defines for the bit fields in the ADC_O_USTAT register.
 //
 //*****************************************************************************
-#define ADC_USTAT_UV3           0x00000008  // SS3 FIFO Underflow.
-#define ADC_USTAT_UV2           0x00000004  // SS2 FIFO Underflow.
-#define ADC_USTAT_UV1           0x00000002  // SS1 FIFO Underflow.
-#define ADC_USTAT_UV0           0x00000001  // SS0 FIFO Underflow.
+#define ADC_USTAT_UV3           0x00000008  // SS3 FIFO Underflow
+#define ADC_USTAT_UV2           0x00000004  // SS2 FIFO Underflow
+#define ADC_USTAT_UV1           0x00000002  // SS1 FIFO Underflow
+#define ADC_USTAT_UV0           0x00000001  // SS0 FIFO Underflow
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the ADC_O_SSPRI register.
 //
 //*****************************************************************************
-#define ADC_SSPRI_SS3_M         0x00003000  // SS3 Priority.
+#define ADC_SSPRI_SS3_M         0x00003000  // SS3 Priority
 #define ADC_SSPRI_SS3_1ST       0x00000000  // First priority
 #define ADC_SSPRI_SS3_2ND       0x00001000  // Second priority
 #define ADC_SSPRI_SS3_3RD       0x00002000  // Third priority
 #define ADC_SSPRI_SS3_4TH       0x00003000  // Fourth priority
-#define ADC_SSPRI_SS2_M         0x00000300  // SS2 Priority.
+#define ADC_SSPRI_SS2_M         0x00000300  // SS2 Priority
 #define ADC_SSPRI_SS2_1ST       0x00000000  // First priority
 #define ADC_SSPRI_SS2_2ND       0x00000100  // Second priority
 #define ADC_SSPRI_SS2_3RD       0x00000200  // Third priority
 #define ADC_SSPRI_SS2_4TH       0x00000300  // Fourth priority
-#define ADC_SSPRI_SS1_M         0x00000030  // SS1 Priority.
+#define ADC_SSPRI_SS1_M         0x00000030  // SS1 Priority
 #define ADC_SSPRI_SS1_1ST       0x00000000  // First priority
 #define ADC_SSPRI_SS1_2ND       0x00000010  // Second priority
 #define ADC_SSPRI_SS1_3RD       0x00000020  // Third priority
 #define ADC_SSPRI_SS1_4TH       0x00000030  // Fourth priority
-#define ADC_SSPRI_SS0_M         0x00000003  // SS0 Priority.
+#define ADC_SSPRI_SS0_M         0x00000003  // SS0 Priority
 #define ADC_SSPRI_SS0_1ST       0x00000000  // First priority
 #define ADC_SSPRI_SS0_2ND       0x00000001  // Second priority
 #define ADC_SSPRI_SS0_3RD       0x00000002  // Third priority
@@ -2098,17 +2071,17 @@
 // The following are defines for the bit fields in the ADC_O_PSSI register.
 //
 //*****************************************************************************
-#define ADC_PSSI_SS3            0x00000008  // SS3 Initiate.
-#define ADC_PSSI_SS2            0x00000004  // SS2 Initiate.
-#define ADC_PSSI_SS1            0x00000002  // SS1 Initiate.
-#define ADC_PSSI_SS0            0x00000001  // SS0 Initiate.
+#define ADC_PSSI_SS3            0x00000008  // SS3 Initiate
+#define ADC_PSSI_SS2            0x00000004  // SS2 Initiate
+#define ADC_PSSI_SS1            0x00000002  // SS1 Initiate
+#define ADC_PSSI_SS0            0x00000001  // SS0 Initiate
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the ADC_O_SAC register.
 //
 //*****************************************************************************
-#define ADC_SAC_AVG_M           0x00000007  // Hardware Averaging Control.
+#define ADC_SAC_AVG_M           0x00000007  // Hardware Averaging Control
 #define ADC_SAC_AVG_OFF         0x00000000  // No hardware oversampling
 #define ADC_SAC_AVG_2X          0x00000001  // 2x hardware oversampling
 #define ADC_SAC_AVG_4X          0x00000002  // 4x hardware oversampling
@@ -2122,14 +2095,14 @@
 // The following are defines for the bit fields in the ADC_O_SSMUX0 register.
 //
 //*****************************************************************************
-#define ADC_SSMUX0_MUX7_M       0x30000000  // 8th Sample Input Select.
-#define ADC_SSMUX0_MUX6_M       0x03000000  // 7th Sample Input Select.
-#define ADC_SSMUX0_MUX5_M       0x00300000  // 6th Sample Input Select.
-#define ADC_SSMUX0_MUX4_M       0x00030000  // 5th Sample Input Select.
-#define ADC_SSMUX0_MUX3_M       0x00003000  // 4th Sample Input Select.
-#define ADC_SSMUX0_MUX2_M       0x00000300  // 3rd Sample Input Select.
-#define ADC_SSMUX0_MUX1_M       0x00000030  // 2nd Sample Input Select.
-#define ADC_SSMUX0_MUX0_M       0x00000003  // 1st Sample Input Select.
+#define ADC_SSMUX0_MUX7_M       0x30000000  // 8th Sample Input Select
+#define ADC_SSMUX0_MUX6_M       0x03000000  // 7th Sample Input Select
+#define ADC_SSMUX0_MUX5_M       0x00300000  // 6th Sample Input Select
+#define ADC_SSMUX0_MUX4_M       0x00030000  // 5th Sample Input Select
+#define ADC_SSMUX0_MUX3_M       0x00003000  // 4th Sample Input Select
+#define ADC_SSMUX0_MUX2_M       0x00000300  // 3rd Sample Input Select
+#define ADC_SSMUX0_MUX1_M       0x00000030  // 2nd Sample Input Select
+#define ADC_SSMUX0_MUX0_M       0x00000003  // 1st Sample Input Select
 #define ADC_SSMUX0_MUX7_S       28
 #define ADC_SSMUX0_MUX6_S       24
 #define ADC_SSMUX0_MUX5_S       20
@@ -2144,45 +2117,45 @@
 // The following are defines for the bit fields in the ADC_O_SSCTL0 register.
 //
 //*****************************************************************************
-#define ADC_SSCTL0_TS7          0x80000000  // 8th Sample Temp Sensor Select.
-#define ADC_SSCTL0_IE7          0x40000000  // 8th Sample Interrupt Enable.
-#define ADC_SSCTL0_END7         0x20000000  // 8th Sample is End of Sequence.
-#define ADC_SSCTL0_D7           0x10000000  // 8th Sample Diff Input Select.
-#define ADC_SSCTL0_TS6          0x08000000  // 7th Sample Temp Sensor Select.
-#define ADC_SSCTL0_IE6          0x04000000  // 7th Sample Interrupt Enable.
-#define ADC_SSCTL0_END6         0x02000000  // 7th Sample is End of Sequence.
-#define ADC_SSCTL0_D6           0x01000000  // 7th Sample Diff Input Select.
-#define ADC_SSCTL0_TS5          0x00800000  // 6th Sample Temp Sensor Select.
-#define ADC_SSCTL0_IE5          0x00400000  // 6th Sample Interrupt Enable.
-#define ADC_SSCTL0_END5         0x00200000  // 6th Sample is End of Sequence.
-#define ADC_SSCTL0_D5           0x00100000  // 6th Sample Diff Input Select.
-#define ADC_SSCTL0_TS4          0x00080000  // 5th Sample Temp Sensor Select.
-#define ADC_SSCTL0_IE4          0x00040000  // 5th Sample Interrupt Enable.
-#define ADC_SSCTL0_END4         0x00020000  // 5th Sample is End of Sequence.
-#define ADC_SSCTL0_D4           0x00010000  // 5th Sample Diff Input Select.
-#define ADC_SSCTL0_TS3          0x00008000  // 4th Sample Temp Sensor Select.
-#define ADC_SSCTL0_IE3          0x00004000  // 4th Sample Interrupt Enable.
-#define ADC_SSCTL0_END3         0x00002000  // 4th Sample is End of Sequence.
-#define ADC_SSCTL0_D3           0x00001000  // 4th Sample Diff Input Select.
-#define ADC_SSCTL0_TS2          0x00000800  // 3rd Sample Temp Sensor Select.
-#define ADC_SSCTL0_IE2          0x00000400  // 3rd Sample Interrupt Enable.
-#define ADC_SSCTL0_END2         0x00000200  // 3rd Sample is End of Sequence.
-#define ADC_SSCTL0_D2           0x00000100  // 3rd Sample Diff Input Select.
-#define ADC_SSCTL0_TS1          0x00000080  // 2nd Sample Temp Sensor Select.
-#define ADC_SSCTL0_IE1          0x00000040  // 2nd Sample Interrupt Enable.
-#define ADC_SSCTL0_END1         0x00000020  // 2nd Sample is End of Sequence.
-#define ADC_SSCTL0_D1           0x00000010  // 2nd Sample Diff Input Select.
-#define ADC_SSCTL0_TS0          0x00000008  // 1st Sample Temp Sensor Select.
-#define ADC_SSCTL0_IE0          0x00000004  // 1st Sample Interrupt Enable.
-#define ADC_SSCTL0_END0         0x00000002  // 1st Sample is End of Sequence.
-#define ADC_SSCTL0_D0           0x00000001  // 1st Sample Diff Input Select.
+#define ADC_SSCTL0_TS7          0x80000000  // 8th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE7          0x40000000  // 8th Sample Interrupt Enable
+#define ADC_SSCTL0_END7         0x20000000  // 8th Sample is End of Sequence
+#define ADC_SSCTL0_D7           0x10000000  // 8th Sample Diff Input Select
+#define ADC_SSCTL0_TS6          0x08000000  // 7th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE6          0x04000000  // 7th Sample Interrupt Enable
+#define ADC_SSCTL0_END6         0x02000000  // 7th Sample is End of Sequence
+#define ADC_SSCTL0_D6           0x01000000  // 7th Sample Diff Input Select
+#define ADC_SSCTL0_TS5          0x00800000  // 6th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE5          0x00400000  // 6th Sample Interrupt Enable
+#define ADC_SSCTL0_END5         0x00200000  // 6th Sample is End of Sequence
+#define ADC_SSCTL0_D5           0x00100000  // 6th Sample Diff Input Select
+#define ADC_SSCTL0_TS4          0x00080000  // 5th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE4          0x00040000  // 5th Sample Interrupt Enable
+#define ADC_SSCTL0_END4         0x00020000  // 5th Sample is End of Sequence
+#define ADC_SSCTL0_D4           0x00010000  // 5th Sample Diff Input Select
+#define ADC_SSCTL0_TS3          0x00008000  // 4th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE3          0x00004000  // 4th Sample Interrupt Enable
+#define ADC_SSCTL0_END3         0x00002000  // 4th Sample is End of Sequence
+#define ADC_SSCTL0_D3           0x00001000  // 4th Sample Diff Input Select
+#define ADC_SSCTL0_TS2          0x00000800  // 3rd Sample Temp Sensor Select
+#define ADC_SSCTL0_IE2          0x00000400  // 3rd Sample Interrupt Enable
+#define ADC_SSCTL0_END2         0x00000200  // 3rd Sample is End of Sequence
+#define ADC_SSCTL0_D2           0x00000100  // 3rd Sample Diff Input Select
+#define ADC_SSCTL0_TS1          0x00000080  // 2nd Sample Temp Sensor Select
+#define ADC_SSCTL0_IE1          0x00000040  // 2nd Sample Interrupt Enable
+#define ADC_SSCTL0_END1         0x00000020  // 2nd Sample is End of Sequence
+#define ADC_SSCTL0_D1           0x00000010  // 2nd Sample Diff Input Select
+#define ADC_SSCTL0_TS0          0x00000008  // 1st Sample Temp Sensor Select
+#define ADC_SSCTL0_IE0          0x00000004  // 1st Sample Interrupt Enable
+#define ADC_SSCTL0_END0         0x00000002  // 1st Sample is End of Sequence
+#define ADC_SSCTL0_D0           0x00000001  // 1st Sample Diff Input Select
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the ADC_O_SSFIFO0 register.
 //
 //*****************************************************************************
-#define ADC_SSFIFO0_DATA_M      0x000003FF  // Conversion Result Data.
+#define ADC_SSFIFO0_DATA_M      0x000003FF  // Conversion Result Data
 #define ADC_SSFIFO0_DATA_S      0
 
 //*****************************************************************************
@@ -2190,10 +2163,10 @@
 // The following are defines for the bit fields in the ADC_O_SSFSTAT0 register.
 //
 //*****************************************************************************
-#define ADC_SSFSTAT0_FULL       0x00001000  // FIFO Full.
-#define ADC_SSFSTAT0_EMPTY      0x00000100  // FIFO Empty.
-#define ADC_SSFSTAT0_HPTR_M     0x000000F0  // FIFO Head Pointer.
-#define ADC_SSFSTAT0_TPTR_M     0x0000000F  // FIFO Tail Pointer.
+#define ADC_SSFSTAT0_FULL       0x00001000  // FIFO Full
+#define ADC_SSFSTAT0_EMPTY      0x00000100  // FIFO Empty
+#define ADC_SSFSTAT0_HPTR_M     0x000000F0  // FIFO Head Pointer
+#define ADC_SSFSTAT0_TPTR_M     0x0000000F  // FIFO Tail Pointer
 #define ADC_SSFSTAT0_HPTR_S     4
 #define ADC_SSFSTAT0_TPTR_S     0
 
@@ -2202,10 +2175,10 @@
 // The following are defines for the bit fields in the ADC_O_SSMUX1 register.
 //
 //*****************************************************************************
-#define ADC_SSMUX1_MUX3_M       0x00003000  // 4th Sample Input Select.
-#define ADC_SSMUX1_MUX2_M       0x00000300  // 3rd Sample Input Select.
-#define ADC_SSMUX1_MUX1_M       0x00000030  // 2nd Sample Input Select.
-#define ADC_SSMUX1_MUX0_M       0x00000003  // 1st Sample Input Select.
+#define ADC_SSMUX1_MUX3_M       0x00003000  // 4th Sample Input Select
+#define ADC_SSMUX1_MUX2_M       0x00000300  // 3rd Sample Input Select
+#define ADC_SSMUX1_MUX1_M       0x00000030  // 2nd Sample Input Select
+#define ADC_SSMUX1_MUX0_M       0x00000003  // 1st Sample Input Select
 #define ADC_SSMUX1_MUX3_S       12
 #define ADC_SSMUX1_MUX2_S       8
 #define ADC_SSMUX1_MUX1_S       4
@@ -2216,29 +2189,29 @@
 // The following are defines for the bit fields in the ADC_O_SSCTL1 register.
 //
 //*****************************************************************************
-#define ADC_SSCTL1_TS3          0x00008000  // 4th Sample Temp Sensor Select.
-#define ADC_SSCTL1_IE3          0x00004000  // 4th Sample Interrupt Enable.
-#define ADC_SSCTL1_END3         0x00002000  // 4th Sample is End of Sequence.
-#define ADC_SSCTL1_D3           0x00001000  // 4th Sample Diff Input Select.
-#define ADC_SSCTL1_TS2          0x00000800  // 3rd Sample Temp Sensor Select.
-#define ADC_SSCTL1_IE2          0x00000400  // 3rd Sample Interrupt Enable.
-#define ADC_SSCTL1_END2         0x00000200  // 3rd Sample is End of Sequence.
-#define ADC_SSCTL1_D2           0x00000100  // 3rd Sample Diff Input Select.
-#define ADC_SSCTL1_TS1          0x00000080  // 2nd Sample Temp Sensor Select.
-#define ADC_SSCTL1_IE1          0x00000040  // 2nd Sample Interrupt Enable.
-#define ADC_SSCTL1_END1         0x00000020  // 2nd Sample is End of Sequence.
-#define ADC_SSCTL1_D1           0x00000010  // 2nd Sample Diff Input Select.
-#define ADC_SSCTL1_TS0          0x00000008  // 1st Sample Temp Sensor Select.
-#define ADC_SSCTL1_IE0          0x00000004  // 1st Sample Interrupt Enable.
-#define ADC_SSCTL1_END0         0x00000002  // 1st Sample is End of Sequence.
-#define ADC_SSCTL1_D0           0x00000001  // 1st Sample Diff Input Select.
+#define ADC_SSCTL1_TS3          0x00008000  // 4th Sample Temp Sensor Select
+#define ADC_SSCTL1_IE3          0x00004000  // 4th Sample Interrupt Enable
+#define ADC_SSCTL1_END3         0x00002000  // 4th Sample is End of Sequence
+#define ADC_SSCTL1_D3           0x00001000  // 4th Sample Diff Input Select
+#define ADC_SSCTL1_TS2          0x00000800  // 3rd Sample Temp Sensor Select
+#define ADC_SSCTL1_IE2          0x00000400  // 3rd Sample Interrupt Enable
+#define ADC_SSCTL1_END2         0x00000200  // 3rd Sample is End of Sequence
+#define ADC_SSCTL1_D2           0x00000100  // 3rd Sample Diff Input Select
+#define ADC_SSCTL1_TS1          0x00000080  // 2nd Sample Temp Sensor Select
+#define ADC_SSCTL1_IE1          0x00000040  // 2nd Sample Interrupt Enable
+#define ADC_SSCTL1_END1         0x00000020  // 2nd Sample is End of Sequence
+#define ADC_SSCTL1_D1           0x00000010  // 2nd Sample Diff Input Select
+#define ADC_SSCTL1_TS0          0x00000008  // 1st Sample Temp Sensor Select
+#define ADC_SSCTL1_IE0          0x00000004  // 1st Sample Interrupt Enable
+#define ADC_SSCTL1_END0         0x00000002  // 1st Sample is End of Sequence
+#define ADC_SSCTL1_D0           0x00000001  // 1st Sample Diff Input Select
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the ADC_O_SSFIFO1 register.
 //
 //*****************************************************************************
-#define ADC_SSFIFO1_DATA_M      0x000003FF  // Conversion Result Data.
+#define ADC_SSFIFO1_DATA_M      0x000003FF  // Conversion Result Data
 #define ADC_SSFIFO1_DATA_S      0
 
 //*****************************************************************************
@@ -2246,10 +2219,10 @@
 // The following are defines for the bit fields in the ADC_O_SSFSTAT1 register.
 //
 //*****************************************************************************
-#define ADC_SSFSTAT1_FULL       0x00001000  // FIFO Full.
-#define ADC_SSFSTAT1_EMPTY      0x00000100  // FIFO Empty.
-#define ADC_SSFSTAT1_HPTR_M     0x000000F0  // FIFO Head Pointer.
-#define ADC_SSFSTAT1_TPTR_M     0x0000000F  // FIFO Tail Pointer.
+#define ADC_SSFSTAT1_FULL       0x00001000  // FIFO Full
+#define ADC_SSFSTAT1_EMPTY      0x00000100  // FIFO Empty
+#define ADC_SSFSTAT1_HPTR_M     0x000000F0  // FIFO Head Pointer
+#define ADC_SSFSTAT1_TPTR_M     0x0000000F  // FIFO Tail Pointer
 #define ADC_SSFSTAT1_HPTR_S     4
 #define ADC_SSFSTAT1_TPTR_S     0
 
@@ -2258,10 +2231,10 @@
 // The following are defines for the bit fields in the ADC_O_SSMUX2 register.
 //
 //*****************************************************************************
-#define ADC_SSMUX2_MUX3_M       0x00003000  // 4th Sample Input Select.
-#define ADC_SSMUX2_MUX2_M       0x00000300  // 3rd Sample Input Select.
-#define ADC_SSMUX2_MUX1_M       0x00000030  // 2nd Sample Input Select.
-#define ADC_SSMUX2_MUX0_M       0x00000003  // 1st Sample Input Select.
+#define ADC_SSMUX2_MUX3_M       0x00003000  // 4th Sample Input Select
+#define ADC_SSMUX2_MUX2_M       0x00000300  // 3rd Sample Input Select
+#define ADC_SSMUX2_MUX1_M       0x00000030  // 2nd Sample Input Select
+#define ADC_SSMUX2_MUX0_M       0x00000003  // 1st Sample Input Select
 #define ADC_SSMUX2_MUX3_S       12
 #define ADC_SSMUX2_MUX2_S       8
 #define ADC_SSMUX2_MUX1_S       4
@@ -2272,29 +2245,29 @@
 // The following are defines for the bit fields in the ADC_O_SSCTL2 register.
 //
 //*****************************************************************************
-#define ADC_SSCTL2_TS3          0x00008000  // 4th Sample Temp Sensor Select.
-#define ADC_SSCTL2_IE3          0x00004000  // 4th Sample Interrupt Enable.
-#define ADC_SSCTL2_END3         0x00002000  // 4th Sample is End of Sequence.
-#define ADC_SSCTL2_D3           0x00001000  // 4th Sample Diff Input Select.
-#define ADC_SSCTL2_TS2          0x00000800  // 3rd Sample Temp Sensor Select.
-#define ADC_SSCTL2_IE2          0x00000400  // 3rd Sample Interrupt Enable.
-#define ADC_SSCTL2_END2         0x00000200  // 3rd Sample is End of Sequence.
-#define ADC_SSCTL2_D2           0x00000100  // 3rd Sample Diff Input Select.
-#define ADC_SSCTL2_TS1          0x00000080  // 2nd Sample Temp Sensor Select.
-#define ADC_SSCTL2_IE1          0x00000040  // 2nd Sample Interrupt Enable.
-#define ADC_SSCTL2_END1         0x00000020  // 2nd Sample is End of Sequence.
-#define ADC_SSCTL2_D1           0x00000010  // 2nd Sample Diff Input Select.
-#define ADC_SSCTL2_TS0          0x00000008  // 1st Sample Temp Sensor Select.
-#define ADC_SSCTL2_IE0          0x00000004  // 1st Sample Interrupt Enable.
-#define ADC_SSCTL2_END0         0x00000002  // 1st Sample is End of Sequence.
-#define ADC_SSCTL2_D0           0x00000001  // 1st Sample Diff Input Select.
+#define ADC_SSCTL2_TS3          0x00008000  // 4th Sample Temp Sensor Select
+#define ADC_SSCTL2_IE3          0x00004000  // 4th Sample Interrupt Enable
+#define ADC_SSCTL2_END3         0x00002000  // 4th Sample is End of Sequence
+#define ADC_SSCTL2_D3           0x00001000  // 4th Sample Diff Input Select
+#define ADC_SSCTL2_TS2          0x00000800  // 3rd Sample Temp Sensor Select
+#define ADC_SSCTL2_IE2          0x00000400  // 3rd Sample Interrupt Enable
+#define ADC_SSCTL2_END2         0x00000200  // 3rd Sample is End of Sequence
+#define ADC_SSCTL2_D2           0x00000100  // 3rd Sample Diff Input Select
+#define ADC_SSCTL2_TS1          0x00000080  // 2nd Sample Temp Sensor Select
+#define ADC_SSCTL2_IE1          0x00000040  // 2nd Sample Interrupt Enable
+#define ADC_SSCTL2_END1         0x00000020  // 2nd Sample is End of Sequence
+#define ADC_SSCTL2_D1           0x00000010  // 2nd Sample Diff Input Select
+#define ADC_SSCTL2_TS0          0x00000008  // 1st Sample Temp Sensor Select
+#define ADC_SSCTL2_IE0          0x00000004  // 1st Sample Interrupt Enable
+#define ADC_SSCTL2_END0         0x00000002  // 1st Sample is End of Sequence
+#define ADC_SSCTL2_D0           0x00000001  // 1st Sample Diff Input Select
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the ADC_O_SSFIFO2 register.
 //
 //*****************************************************************************
-#define ADC_SSFIFO2_DATA_M      0x000003FF  // Conversion Result Data.
+#define ADC_SSFIFO2_DATA_M      0x000003FF  // Conversion Result Data
 #define ADC_SSFIFO2_DATA_S      0
 
 //*****************************************************************************
@@ -2302,10 +2275,10 @@
 // The following are defines for the bit fields in the ADC_O_SSFSTAT2 register.
 //
 //*****************************************************************************
-#define ADC_SSFSTAT2_FULL       0x00001000  // FIFO Full.
-#define ADC_SSFSTAT2_EMPTY      0x00000100  // FIFO Empty.
-#define ADC_SSFSTAT2_HPTR_M     0x000000F0  // FIFO Head Pointer.
-#define ADC_SSFSTAT2_TPTR_M     0x0000000F  // FIFO Tail Pointer.
+#define ADC_SSFSTAT2_FULL       0x00001000  // FIFO Full
+#define ADC_SSFSTAT2_EMPTY      0x00000100  // FIFO Empty
+#define ADC_SSFSTAT2_HPTR_M     0x000000F0  // FIFO Head Pointer
+#define ADC_SSFSTAT2_TPTR_M     0x0000000F  // FIFO Tail Pointer
 #define ADC_SSFSTAT2_HPTR_S     4
 #define ADC_SSFSTAT2_TPTR_S     0
 
@@ -2314,7 +2287,7 @@
 // The following are defines for the bit fields in the ADC_O_SSMUX3 register.
 //
 //*****************************************************************************
-#define ADC_SSMUX3_MUX0_M       0x00000003  // 1st Sample Input Select.
+#define ADC_SSMUX3_MUX0_M       0x00000003  // 1st Sample Input Select
 #define ADC_SSMUX3_MUX0_S       0
 
 //*****************************************************************************
@@ -2322,17 +2295,17 @@
 // The following are defines for the bit fields in the ADC_O_SSCTL3 register.
 //
 //*****************************************************************************
-#define ADC_SSCTL3_TS0          0x00000008  // 1st Sample Temp Sensor Select.
-#define ADC_SSCTL3_IE0          0x00000004  // 1st Sample Interrupt Enable.
-#define ADC_SSCTL3_END0         0x00000002  // 1st Sample is End of Sequence.
-#define ADC_SSCTL3_D0           0x00000001  // 1st Sample Diff Input Select.
+#define ADC_SSCTL3_TS0          0x00000008  // 1st Sample Temp Sensor Select
+#define ADC_SSCTL3_IE0          0x00000004  // 1st Sample Interrupt Enable
+#define ADC_SSCTL3_END0         0x00000002  // 1st Sample is End of Sequence
+#define ADC_SSCTL3_D0           0x00000001  // 1st Sample Diff Input Select
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the ADC_O_SSFIFO3 register.
 //
 //*****************************************************************************
-#define ADC_SSFIFO3_DATA_M      0x000003FF  // Conversion Result Data.
+#define ADC_SSFIFO3_DATA_M      0x000003FF  // Conversion Result Data
 #define ADC_SSFIFO3_DATA_S      0
 
 //*****************************************************************************
@@ -2340,10 +2313,10 @@
 // The following are defines for the bit fields in the ADC_O_SSFSTAT3 register.
 //
 //*****************************************************************************
-#define ADC_SSFSTAT3_FULL       0x00001000  // FIFO Full.
-#define ADC_SSFSTAT3_EMPTY      0x00000100  // FIFO Empty.
-#define ADC_SSFSTAT3_HPTR_M     0x000000F0  // FIFO Head Pointer.
-#define ADC_SSFSTAT3_TPTR_M     0x0000000F  // FIFO Tail Pointer.
+#define ADC_SSFSTAT3_FULL       0x00001000  // FIFO Full
+#define ADC_SSFSTAT3_EMPTY      0x00000100  // FIFO Empty
+#define ADC_SSFSTAT3_HPTR_M     0x000000F0  // FIFO Head Pointer
+#define ADC_SSFSTAT3_TPTR_M     0x0000000F  // FIFO Tail Pointer
 #define ADC_SSFSTAT3_HPTR_S     4
 #define ADC_SSFSTAT3_TPTR_S     0
 
@@ -2352,7 +2325,7 @@
 // The following are defines for the bit fields in the ADC_O_TMLB register.
 //
 //*****************************************************************************
-#define ADC_TMLB_LB             0x00000001  // Loopback Mode Enable.
+#define ADC_TMLB_LB             0x00000001  // Loopback Mode Enable
 
 //*****************************************************************************
 //
@@ -2360,53 +2333,39 @@
 // SSFIFOx when the ADC TMLB is enabled.
 //
 //*****************************************************************************
-#define ADC_SSFIFO_TMLB_CNT_M   0x000003C0  // Continuous Sample Counter.
-#define ADC_SSFIFO_TMLB_CONT    0x00000020  // Continuation Sample Indicator.
-#define ADC_SSFIFO_TMLB_DIFF    0x00000010  // Differential Sample Indicator.
-#define ADC_SSFIFO_TMLB_TS      0x00000008  // Temp Sensor Sample Indicator.
-#define ADC_SSFIFO_TMLB_MUX_M   0x00000007  // Analog Input Indicator.
+#define ADC_SSFIFO_TMLB_CNT_M   0x000003C0  // Continuous Sample Counter
+#define ADC_SSFIFO_TMLB_CONT    0x00000020  // Continuation Sample Indicator
+#define ADC_SSFIFO_TMLB_DIFF    0x00000010  // Differential Sample Indicator
+#define ADC_SSFIFO_TMLB_TS      0x00000008  // Temp Sensor Sample Indicator
+#define ADC_SSFIFO_TMLB_MUX_M   0x00000007  // Analog Input Indicator
 #define ADC_SSFIFO_TMLB_CNT_S   6           // Sample counter shift
 #define ADC_SSFIFO_TMLB_MUX_S   0           // Input channel number shift
 
-//*****************************************************************************
-//
-// The following are defines for the the interpretation of the data in the
-// SSFIFOx when the ADC TMLB is enabled.
-//
-//*****************************************************************************
-#define ADC_TMLB_CNT_M          0x000003C0  // Continuous Sample Counter.
-#define ADC_TMLB_CONT           0x00000020  // Continuation Sample Indicator.
-#define ADC_TMLB_DIFF           0x00000010  // Differential Sample Indicator.
-#define ADC_TMLB_TS             0x00000008  // Temp Sensor Sample Indicator.
-#define ADC_TMLB_MUX_M          0x00000007  // Analog Input Indicator.
-#define ADC_TMLB_CNT_S          6           // Sample counter shift
-#define ADC_TMLB_MUX_S          0           // Input channel number shift
-
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the COMP_O_ACMIS register.
 //
 //*****************************************************************************
 #define COMP_ACMIS_IN1          0x00000002  // Comparator 1 Masked Interrupt
-                                            // Status.
+                                            // Status
 #define COMP_ACMIS_IN0          0x00000001  // Comparator 0 Masked Interrupt
-                                            // Status.
+                                            // Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the COMP_O_ACRIS register.
 //
 //*****************************************************************************
-#define COMP_ACRIS_IN1          0x00000002  // Comparator 1 Interrupt Status.
-#define COMP_ACRIS_IN0          0x00000001  // Comparator 0 Interrupt Status.
+#define COMP_ACRIS_IN1          0x00000002  // Comparator 1 Interrupt Status
+#define COMP_ACRIS_IN0          0x00000001  // Comparator 0 Interrupt Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the COMP_O_ACINTEN register.
 //
 //*****************************************************************************
-#define COMP_ACINTEN_IN1        0x00000002  // Comparator 1 Interrupt Enable.
-#define COMP_ACINTEN_IN0        0x00000001  // Comparator 0 Interrupt Enable.
+#define COMP_ACINTEN_IN1        0x00000002  // Comparator 1 Interrupt Enable
+#define COMP_ACINTEN_IN0        0x00000001  // Comparator 0 Interrupt Enable
 
 //*****************************************************************************
 //
@@ -2414,9 +2373,9 @@
 // register.
 //
 //*****************************************************************************
-#define COMP_ACREFCTL_EN        0x00000200  // Resistor Ladder Enable.
-#define COMP_ACREFCTL_RNG       0x00000100  // Resistor Ladder Range.
-#define COMP_ACREFCTL_VREF_M    0x0000000F  // Resistor Ladder Voltage Ref.
+#define COMP_ACREFCTL_EN        0x00000200  // Resistor Ladder Enable
+#define COMP_ACREFCTL_RNG       0x00000100  // Resistor Ladder Range
+#define COMP_ACREFCTL_VREF_M    0x0000000F  // Resistor Ladder Voltage Ref
 #define COMP_ACREFCTL_VREF_S    0
 
 //*****************************************************************************
@@ -2424,181 +2383,296 @@
 // The following are defines for the bit fields in the COMP_O_ACSTAT0 register.
 //
 //*****************************************************************************
-#define COMP_ACSTAT0_OVAL       0x00000002  // Comparator Output Value.
+#define COMP_ACSTAT0_OVAL       0x00000002  // Comparator Output Value
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the COMP_O_ACCTL0 register.
 //
 //*****************************************************************************
-#define COMP_ACCTL0_TOEN        0x00000800  // Trigger Output Enable.
-#define COMP_ACCTL0_ASRCP_M     0x00000600  // Analog Source Positive.
-#define COMP_ACCTL0_ASRCP_PIN   0x00000000  // Pin value
+#define COMP_ACCTL0_TOEN        0x00000800  // Trigger Output Enable
+#define COMP_ACCTL0_ASRCP_M     0x00000600  // Analog Source Positive
+#define COMP_ACCTL0_ASRCP_PIN   0x00000000  // Pin value of Cn+
 #define COMP_ACCTL0_ASRCP_PIN0  0x00000200  // Pin value of C0+
 #define COMP_ACCTL0_ASRCP_REF   0x00000400  // Internal voltage reference
-#define COMP_ACCTL0_TSLVAL      0x00000080  // Trigger Sense Level Value.
-#define COMP_ACCTL0_TSEN_M      0x00000060  // Trigger Sense.
+                                            // (VIREF)
+#define COMP_ACCTL0_TSLVAL      0x00000080  // Trigger Sense Level Value
+#define COMP_ACCTL0_TSEN_M      0x00000060  // Trigger Sense
 #define COMP_ACCTL0_TSEN_LEVEL  0x00000000  // Level sense, see TSLVAL
 #define COMP_ACCTL0_TSEN_FALL   0x00000020  // Falling edge
 #define COMP_ACCTL0_TSEN_RISE   0x00000040  // Rising edge
 #define COMP_ACCTL0_TSEN_BOTH   0x00000060  // Either edge
-#define COMP_ACCTL0_ISLVAL      0x00000010  // Interrupt Sense Level Value.
-#define COMP_ACCTL0_ISEN_M      0x0000000C  // Interrupt Sense.
+#define COMP_ACCTL0_ISLVAL      0x00000010  // Interrupt Sense Level Value
+#define COMP_ACCTL0_ISEN_M      0x0000000C  // Interrupt Sense
 #define COMP_ACCTL0_ISEN_LEVEL  0x00000000  // Level sense, see ISLVAL
 #define COMP_ACCTL0_ISEN_FALL   0x00000004  // Falling edge
 #define COMP_ACCTL0_ISEN_RISE   0x00000008  // Rising edge
 #define COMP_ACCTL0_ISEN_BOTH   0x0000000C  // Either edge
-#define COMP_ACCTL0_CINV        0x00000002  // Comparator Output Invert.
+#define COMP_ACCTL0_CINV        0x00000002  // Comparator Output Invert
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the COMP_O_ACSTAT1 register.
 //
 //*****************************************************************************
-#define COMP_ACSTAT1_OVAL       0x00000002  // Comparator Output Value.
+#define COMP_ACSTAT1_OVAL       0x00000002  // Comparator Output Value
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the COMP_O_ACCTL1 register.
 //
 //*****************************************************************************
-#define COMP_ACCTL1_TOEN        0x00000800  // Trigger Output Enable.
-#define COMP_ACCTL1_ASRCP_M     0x00000600  // Analog Source Positive.
-#define COMP_ACCTL1_ASRCP_PIN   0x00000000  // Pin value
+#define COMP_ACCTL1_TOEN        0x00000800  // Trigger Output Enable
+#define COMP_ACCTL1_ASRCP_M     0x00000600  // Analog Source Positive
+#define COMP_ACCTL1_ASRCP_PIN   0x00000000  // Pin value of Cn+
 #define COMP_ACCTL1_ASRCP_PIN0  0x00000200  // Pin value of C0+
 #define COMP_ACCTL1_ASRCP_REF   0x00000400  // Internal voltage reference
-#define COMP_ACCTL1_TSLVAL      0x00000080  // Trigger Sense Level Value.
-#define COMP_ACCTL1_TSEN_M      0x00000060  // Trigger Sense.
+                                            // (VIREF)
+#define COMP_ACCTL1_TSLVAL      0x00000080  // Trigger Sense Level Value
+#define COMP_ACCTL1_TSEN_M      0x00000060  // Trigger Sense
 #define COMP_ACCTL1_TSEN_LEVEL  0x00000000  // Level sense, see TSLVAL
 #define COMP_ACCTL1_TSEN_FALL   0x00000020  // Falling edge
 #define COMP_ACCTL1_TSEN_RISE   0x00000040  // Rising edge
 #define COMP_ACCTL1_TSEN_BOTH   0x00000060  // Either edge
-#define COMP_ACCTL1_ISLVAL      0x00000010  // Interrupt Sense Level Value.
-#define COMP_ACCTL1_ISEN_M      0x0000000C  // Interrupt Sense.
+#define COMP_ACCTL1_ISLVAL      0x00000010  // Interrupt Sense Level Value
+#define COMP_ACCTL1_ISEN_M      0x0000000C  // Interrupt Sense
 #define COMP_ACCTL1_ISEN_LEVEL  0x00000000  // Level sense, see ISLVAL
 #define COMP_ACCTL1_ISEN_FALL   0x00000004  // Falling edge
 #define COMP_ACCTL1_ISEN_RISE   0x00000008  // Rising edge
 #define COMP_ACCTL1_ISEN_BOTH   0x0000000C  // Either edge
-#define COMP_ACCTL1_CINV        0x00000002  // Comparator Output Invert.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_MR0 register.
-//
-//*****************************************************************************
-#define PHY_MR0_RESET           0x00008000  // Reset Registers.
-#define PHY_MR0_LOOPBK          0x00004000  // Loopback Mode.
-#define PHY_MR0_SPEEDSL         0x00002000  // Speed Select.
-#define PHY_MR0_ANEGEN          0x00001000  // Auto-Negotiation Enable.
-#define PHY_MR0_PWRDN           0x00000800  // Power Down.
-#define PHY_MR0_ISO             0x00000400  // Isolate.
-#define PHY_MR0_RANEG           0x00000200  // Restart Auto-Negotiation.
-#define PHY_MR0_DUPLEX          0x00000100  // Set Duplex Mode.
-#define PHY_MR0_COLT            0x00000080  // Collision Test.
+#define COMP_ACCTL1_CINV        0x00000002  // Comparator Output Invert
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the MAC_O_RIS register.
 //
 //*****************************************************************************
-#define MAC_RIS_PHYINT          0x00000040  // PHY Interrupt.
-#define MAC_RIS_MDINT           0x00000020  // MII Transaction Complete.
-#define MAC_RIS_RXER            0x00000010  // Receive Error.
-#define MAC_RIS_FOV             0x00000008  // FIFO Overrun.
-#define MAC_RIS_TXEMP           0x00000004  // Transmit FIFO Empty.
-#define MAC_RIS_TXER            0x00000002  // Transmit Error.
-#define MAC_RIS_RXINT           0x00000001  // Packet Received.
+#define MAC_RIS_PHYINT          0x00000040  // PHY Interrupt
+#define MAC_RIS_MDINT           0x00000020  // MII Transaction Complete
+#define MAC_RIS_RXER            0x00000010  // Receive Error
+#define MAC_RIS_FOV             0x00000008  // FIFO Overrun
+#define MAC_RIS_TXEMP           0x00000004  // Transmit FIFO Empty
+#define MAC_RIS_TXER            0x00000002  // Transmit Error
+#define MAC_RIS_RXINT           0x00000001  // Packet Received
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the MAC_O_IACK register.
 //
 //*****************************************************************************
-#define MAC_IACK_PHYINT         0x00000040  // Clear PHY Interrupt.
-#define MAC_IACK_MDINT          0x00000020  // Clear MII Transaction Complete.
-#define MAC_IACK_RXER           0x00000010  // Clear Receive Error.
-#define MAC_IACK_FOV            0x00000008  // Clear FIFO Overrun.
-#define MAC_IACK_TXEMP          0x00000004  // Clear Transmit FIFO Empty.
-#define MAC_IACK_TXER           0x00000002  // Clear Transmit Error.
-#define MAC_IACK_RXINT          0x00000001  // Clear Packet Received.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_MR1 register.
-//
-//*****************************************************************************
-#define PHY_MR1_100X_F          0x00004000  // 100BASE-TX Full-Duplex Mode.
-#define PHY_MR1_100X_H          0x00002000  // 100BASE-TX Half-Duplex Mode.
-#define PHY_MR1_10T_F           0x00001000  // 10BASE-T Full-Duplex Mode.
-#define PHY_MR1_10T_H           0x00000800  // 10BASE-T Half-Duplex Mode.
-#define PHY_MR1_MFPS            0x00000040  // Management Frames with Preamble
-                                            // Suppressed.
-#define PHY_MR1_ANEGC           0x00000020  // Auto-Negotiation Complete.
-#define PHY_MR1_RFAULT          0x00000010  // Remote Fault.
-#define PHY_MR1_ANEGA           0x00000008  // Auto-Negotiation.
-#define PHY_MR1_LINK            0x00000004  // Link Made.
-#define PHY_MR1_JAB             0x00000002  // Jabber Condition.
-#define PHY_MR1_EXTD            0x00000001  // Extended Capabilities.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_MR2 register.
-//
-//*****************************************************************************
-#define PHY_MR2_OUI_M           0x0000FFFF  // Organizationally Unique
-                                            // Identifier[21:6].
-#define PHY_MR2_OUI_S           0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_MR3 register.
-//
-//*****************************************************************************
-#define PHY_MR3_OUI_M           0x0000FC00  // Organizationally Unique
-                                            // Identifier[5:0].
-#define PHY_MR3_MN_M            0x000003F0  // Model Number.
-#define PHY_MR3_RN_M            0x0000000F  // Revision Number.
-#define PHY_MR3_OUI_S           10
-#define PHY_MR3_MN_S            4
-#define PHY_MR3_RN_S            0
+#define MAC_IACK_PHYINT         0x00000040  // Clear PHY Interrupt
+#define MAC_IACK_MDINT          0x00000020  // Clear MII Transaction Complete
+#define MAC_IACK_RXER           0x00000010  // Clear Receive Error
+#define MAC_IACK_FOV            0x00000008  // Clear FIFO Overrun
+#define MAC_IACK_TXEMP          0x00000004  // Clear Transmit FIFO Empty
+#define MAC_IACK_TXER           0x00000002  // Clear Transmit Error
+#define MAC_IACK_RXINT          0x00000001  // Clear Packet Received
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the MAC_O_IM register.
 //
 //*****************************************************************************
-#define MAC_IM_PHYINTM          0x00000040  // Mask PHY Interrupt.
-#define MAC_IM_MDINTM           0x00000020  // Mask MII Transaction Complete.
-#define MAC_IM_RXERM            0x00000010  // Mask Receive Error.
-#define MAC_IM_FOVM             0x00000008  // Mask FIFO Overrun.
-#define MAC_IM_TXEMPM           0x00000004  // Mask Transmit FIFO Empty.
-#define MAC_IM_TXERM            0x00000002  // Mask Transmit Error.
-#define MAC_IM_RXINTM           0x00000001  // Mask Packet Received.
+#define MAC_IM_PHYINTM          0x00000040  // Mask PHY Interrupt
+#define MAC_IM_MDINTM           0x00000020  // Mask MII Transaction Complete
+#define MAC_IM_RXERM            0x00000010  // Mask Receive Error
+#define MAC_IM_FOVM             0x00000008  // Mask FIFO Overrun
+#define MAC_IM_TXEMPM           0x00000004  // Mask Transmit FIFO Empty
+#define MAC_IM_TXERM            0x00000002  // Mask Transmit Error
+#define MAC_IM_RXINTM           0x00000001  // Mask Packet Received
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the MAC_O_MR4 register.
+// The following are defines for the bit fields in the MAC_O_RCTL register.
 //
 //*****************************************************************************
-#define PHY_MR4_NP              0x00008000  // Next Page.
-#define PHY_MR4_RF              0x00002000  // Remote Fault.
-#define PHY_MR4_A3              0x00000100  // Technology Ability Field[3].
-#define PHY_MR4_A2              0x00000080  // Technology Ability Field[2].
-#define PHY_MR4_A1              0x00000040  // Technology Ability Field[1].
-#define PHY_MR4_A0              0x00000020  // Technology Ability Field[0].
-#define PHY_MR4_S_M             0x0000001F  // Selector Field.
+#define MAC_RCTL_RSTFIFO        0x00000010  // Clear Receive FIFO
+#define MAC_RCTL_BADCRC         0x00000008  // Enable Reject Bad CRC
+#define MAC_RCTL_PRMS           0x00000004  // Enable Promiscuous Mode
+#define MAC_RCTL_AMUL           0x00000002  // Enable Multicast Frames
+#define MAC_RCTL_RXEN           0x00000001  // Enable Receiver
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_TCTL register.
+//
+//*****************************************************************************
+#define MAC_TCTL_DUPLEX         0x00000010  // Enable Duplex Mode
+#define MAC_TCTL_CRC            0x00000004  // Enable CRC Generation
+#define MAC_TCTL_PADEN          0x00000002  // Enable Packet Padding
+#define MAC_TCTL_TXEN           0x00000001  // Enable Transmitter
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_DATA register.
+//
+//*****************************************************************************
+#define MAC_DATA_TXDATA_M       0xFFFFFFFF  // Transmit FIFO Data
+#define MAC_DATA_RXDATA_M       0xFFFFFFFF  // Receive FIFO Data
+#define MAC_DATA_RXDATA_S       0
+#define MAC_DATA_TXDATA_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_IA0 register.
+//
+//*****************************************************************************
+#define MAC_IA0_MACOCT4_M       0xFF000000  // MAC Address Octet 4
+#define MAC_IA0_MACOCT3_M       0x00FF0000  // MAC Address Octet 3
+#define MAC_IA0_MACOCT2_M       0x0000FF00  // MAC Address Octet 2
+#define MAC_IA0_MACOCT1_M       0x000000FF  // MAC Address Octet 1
+#define MAC_IA0_MACOCT4_S       24
+#define MAC_IA0_MACOCT3_S       16
+#define MAC_IA0_MACOCT2_S       8
+#define MAC_IA0_MACOCT1_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_IA1 register.
+//
+//*****************************************************************************
+#define MAC_IA1_MACOCT6_M       0x0000FF00  // MAC Address Octet 6
+#define MAC_IA1_MACOCT5_M       0x000000FF  // MAC Address Octet 5
+#define MAC_IA1_MACOCT6_S       8
+#define MAC_IA1_MACOCT5_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_THR register.
+//
+//*****************************************************************************
+#define MAC_THR_THRESH_M        0x0000003F  // Threshold Value
+#define MAC_THR_THRESH_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MCTL register.
+//
+//*****************************************************************************
+#define MAC_MCTL_REGADR_M       0x000000F8  // MII Register Address
+#define MAC_MCTL_WRITE          0x00000002  // MII Register Transaction Type
+#define MAC_MCTL_START          0x00000001  // MII Register Transaction Enable
+#define MAC_MCTL_REGADR_S       3
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MDV register.
+//
+//*****************************************************************************
+#define MAC_MDV_DIV_M           0x000000FF  // Clock Divider
+#define MAC_MDV_DIV_S           0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MTXD register.
+//
+//*****************************************************************************
+#define MAC_MTXD_MDTX_M         0x0000FFFF  // MII Register Transmit Data
+#define MAC_MTXD_MDTX_S         0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MRXD register.
+//
+//*****************************************************************************
+#define MAC_MRXD_MDRX_M         0x0000FFFF  // MII Register Receive Data
+#define MAC_MRXD_MDRX_S         0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_NP register.
+//
+//*****************************************************************************
+#define MAC_NP_NPR_M            0x0000003F  // Number of Packets in Receive
+                                            // FIFO
+#define MAC_NP_NPR_S            0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_TR register.
+//
+//*****************************************************************************
+#define MAC_TR_NEWTX            0x00000001  // New Transmission
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR0 register.
+//
+//*****************************************************************************
+#define PHY_MR0_RESET           0x00008000  // Reset Registers
+#define PHY_MR0_LOOPBK          0x00004000  // Loopback Mode
+#define PHY_MR0_SPEEDSL         0x00002000  // Speed Select
+#define PHY_MR0_ANEGEN          0x00001000  // Auto-Negotiation Enable
+#define PHY_MR0_PWRDN           0x00000800  // Power Down
+#define PHY_MR0_ISO             0x00000400  // Isolate
+#define PHY_MR0_RANEG           0x00000200  // Restart Auto-Negotiation
+#define PHY_MR0_DUPLEX          0x00000100  // Set Duplex Mode
+#define PHY_MR0_COLT            0x00000080  // Collision Test
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR1 register.
+//
+//*****************************************************************************
+#define PHY_MR1_100X_F          0x00004000  // 100BASE-TX Full-Duplex Mode
+#define PHY_MR1_100X_H          0x00002000  // 100BASE-TX Half-Duplex Mode
+#define PHY_MR1_10T_F           0x00001000  // 10BASE-T Full-Duplex Mode
+#define PHY_MR1_10T_H           0x00000800  // 10BASE-T Half-Duplex Mode
+#define PHY_MR1_MFPS            0x00000040  // Management Frames with Preamble
+                                            // Suppressed
+#define PHY_MR1_ANEGC           0x00000020  // Auto-Negotiation Complete
+#define PHY_MR1_RFAULT          0x00000010  // Remote Fault
+#define PHY_MR1_ANEGA           0x00000008  // Auto-Negotiation
+#define PHY_MR1_LINK            0x00000004  // Link Made
+#define PHY_MR1_JAB             0x00000002  // Jabber Condition
+#define PHY_MR1_EXTD            0x00000001  // Extended Capabilities
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR2 register.
+//
+//*****************************************************************************
+#define PHY_MR2_OUI_M           0x0000FFFF  // Organizationally Unique
+                                            // Identifier[21:6]
+#define PHY_MR2_OUI_S           0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR3 register.
+//
+//*****************************************************************************
+#define PHY_MR3_OUI_M           0x0000FC00  // Organizationally Unique
+                                            // Identifier[5:0]
+#define PHY_MR3_MN_M            0x000003F0  // Model Number
+#define PHY_MR3_RN_M            0x0000000F  // Revision Number
+#define PHY_MR3_OUI_S           10
+#define PHY_MR3_MN_S            4
+#define PHY_MR3_RN_S            0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR4 register.
+//
+//*****************************************************************************
+#define PHY_MR4_NP              0x00008000  // Next Page
+#define PHY_MR4_RF              0x00002000  // Remote Fault
+#define PHY_MR4_A3              0x00000100  // Technology Ability Field [3]
+#define PHY_MR4_A2              0x00000080  // Technology Ability Field [2]
+#define PHY_MR4_A1              0x00000040  // Technology Ability Field [1]
+#define PHY_MR4_A0              0x00000020  // Technology Ability Field [0]
+#define PHY_MR4_S_M             0x0000001F  // Selector Field
 #define PHY_MR4_S_S             0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the MAC_O_MR5 register.
+// The following are defines for the bit fields in the PHY_MR5 register.
 //
 //*****************************************************************************
-#define PHY_MR5_NP              0x00008000  // Next Page.
-#define PHY_MR5_ACK             0x00004000  // Acknowledge.
-#define PHY_MR5_RF              0x00002000  // Remote Fault.
-#define PHY_MR5_A_M             0x00001FE0  // Technology Ability Field.
-#define PHY_MR5_S_M             0x0000001F  // Selector Field.
+#define PHY_MR5_NP              0x00008000  // Next Page
+#define PHY_MR5_ACK             0x00004000  // Acknowledge
+#define PHY_MR5_RF              0x00002000  // Remote Fault
+#define PHY_MR5_A_M             0x00001FE0  // Technology Ability Field
+#define PHY_MR5_S_M             0x0000001F  // Selector Field
 #define PHY_MR5_S_8023          0x00000001  // IEEE Std 802.3
 #define PHY_MR5_S_8029          0x00000002  // IEEE Std 802.9 ISLAN-16T
 #define PHY_MR5_S_8025          0x00000003  // IEEE Std 802.5
@@ -2607,105 +2681,74 @@
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the MAC_O_MR6 register.
+// The following are defines for the bit fields in the PHY_MR6 register.
 //
 //*****************************************************************************
-#define PHY_MR6_PDF             0x00000010  // Parallel Detection Fault.
-#define PHY_MR6_LPNPA           0x00000008  // Link Partner is Next Page Able.
-#define PHY_MR6_PRX             0x00000002  // New Page Received.
+#define PHY_MR6_PDF             0x00000010  // Parallel Detection Fault
+#define PHY_MR6_LPNPA           0x00000008  // Link Partner is Next Page Able
+#define PHY_MR6_PRX             0x00000002  // New Page Received
 #define PHY_MR6_LPANEGA         0x00000001  // Link Partner is Auto-Negotiation
-                                            // Able.
+                                            // Able
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the MAC_O_RCTL register.
+// The following are defines for the bit fields in the PHY_MR16 register.
 //
 //*****************************************************************************
-#define MAC_RCTL_RSTFIFO        0x00000010  // Clear Receive FIFO.
-#define MAC_RCTL_BADCRC         0x00000008  // Enable Reject Bad CRC.
-#define MAC_RCTL_PRMS           0x00000004  // Enable Promiscuous Mode.
-#define MAC_RCTL_AMUL           0x00000002  // Enable Multicast Frames.
-#define MAC_RCTL_RXEN           0x00000001  // Enable Receiver.
+#define PHY_MR16_RPTR           0x00008000  // Repeater Mode
+#define PHY_MR16_INPOL          0x00004000  // Interrupt Polarity
+#define PHY_MR16_TXHIM          0x00001000  // Transmit High Impedance Mode
+#define PHY_MR16_SQEI           0x00000800  // SQE Inhibit Testing
+#define PHY_MR16_NL10           0x00000400  // Natural Loopback Mode
+#define PHY_MR16_APOL           0x00000020  // Auto-Polarity Disable
+#define PHY_MR16_RVSPOL         0x00000010  // Receive Data Polarity
+#define PHY_MR16_PCSBP          0x00000002  // PCS Bypass
+#define PHY_MR16_RXCC           0x00000001  // Receive Clock Control
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the MAC_O_TCTL register.
+// The following are defines for the bit fields in the PHY_MR17 register.
 //
 //*****************************************************************************
-#define MAC_TCTL_DUPLEX         0x00000010  // Enable Duplex Mode.
-#define MAC_TCTL_CRC            0x00000004  // Enable CRC Generation.
-#define MAC_TCTL_PADEN          0x00000002  // Enable Packet Padding.
-#define MAC_TCTL_TXEN           0x00000001  // Enable Transmitter.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_DATA register.
-//
-//*****************************************************************************
-#define MAC_DATA_TXDATA_M       0xFFFFFFFF  // Transmit FIFO Data.
-#define MAC_DATA_RXDATA_M       0xFFFFFFFF  // Receive FIFO Data.
-#define MAC_DATA_RXDATA_S       0
-#define MAC_DATA_TXDATA_S       0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_MR16 register.
-//
-//*****************************************************************************
-#define PHY_MR16_RPTR           0x00008000  // Repeater Mode.
-#define PHY_MR16_INPOL          0x00004000  // Interrupt Polarity.
-#define PHY_MR16_TXHIM          0x00001000  // Transmit High Impedance Mode.
-#define PHY_MR16_SQEI           0x00000800  // SQE Inhibit Testing.
-#define PHY_MR16_NL10           0x00000400  // Natural Loopback Mode.
-#define PHY_MR16_APOL           0x00000020  // Auto-Polarity Disable.
-#define PHY_MR16_RVSPOL         0x00000010  // Receive Data Polarity.
-#define PHY_MR16_PCSBP          0x00000002  // PCS Bypass.
-#define PHY_MR16_RXCC           0x00000001  // Receive Clock Control.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_MR17 register.
-//
-//*****************************************************************************
-#define PHY_MR17_JABBER_IE      0x00008000  // Jabber Interrupt Enable.
-#define PHY_MR17_RXER_IE        0x00004000  // Receive Error Interrupt Enable.
-#define PHY_MR17_PRX_IE         0x00002000  // Page Received Interrupt Enable.
+#define PHY_MR17_JABBER_IE      0x00008000  // Jabber Interrupt Enable
+#define PHY_MR17_RXER_IE        0x00004000  // Receive Error Interrupt Enable
+#define PHY_MR17_PRX_IE         0x00002000  // Page Received Interrupt Enable
 #define PHY_MR17_PDF_IE         0x00001000  // Parallel Detection Fault
-                                            // Interrupt Enable.
-#define PHY_MR17_LPACK_IE       0x00000800  // LP Acknowledge Interrupt Enable.
+                                            // Interrupt Enable
+#define PHY_MR17_LPACK_IE       0x00000800  // LP Acknowledge Interrupt Enable
 #define PHY_MR17_LSCHG_IE       0x00000400  // Link Status Change Interrupt
-                                            // Enable.
-#define PHY_MR17_RFAULT_IE      0x00000200  // Remote Fault Interrupt Enable.
+                                            // Enable
+#define PHY_MR17_RFAULT_IE      0x00000200  // Remote Fault Interrupt Enable
 #define PHY_MR17_ANEGCOMP_IE    0x00000100  // Auto-Negotiation Complete
-                                            // Interrupt Enable.
-#define PHY_MR17_JABBER_INT     0x00000080  // Jabber Event Interrupt.
-#define PHY_MR17_RXER_INT       0x00000040  // Receive Error Interrupt.
-#define PHY_MR17_PRX_INT        0x00000020  // Page Receive Interrupt.
+                                            // Interrupt Enable
+#define PHY_MR17_JABBER_INT     0x00000080  // Jabber Event Interrupt
+#define PHY_MR17_RXER_INT       0x00000040  // Receive Error Interrupt
+#define PHY_MR17_PRX_INT        0x00000020  // Page Receive Interrupt
 #define PHY_MR17_PDF_INT        0x00000010  // Parallel Detection Fault
-                                            // Interrupt.
-#define PHY_MR17_LPACK_INT      0x00000008  // LP Acknowledge Interrupt.
-#define PHY_MR17_LSCHG_INT      0x00000004  // Link Status Change Interrupt.
-#define PHY_MR17_RFAULT_INT     0x00000002  // Remote Fault Interrupt.
+                                            // Interrupt
+#define PHY_MR17_LPACK_INT      0x00000008  // LP Acknowledge Interrupt
+#define PHY_MR17_LSCHG_INT      0x00000004  // Link Status Change Interrupt
+#define PHY_MR17_RFAULT_INT     0x00000002  // Remote Fault Interrupt
 #define PHY_MR17_ANEGCOMP_INT   0x00000001  // Auto-Negotiation Complete
-                                            // Interrupt.
+                                            // Interrupt
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the MAC_O_MR18 register.
+// The following are defines for the bit fields in the PHY_MR18 register.
 //
 //*****************************************************************************
-#define PHY_MR18_ANEGF          0x00001000  // Auto-Negotiation Failure.
-#define PHY_MR18_DPLX           0x00000800  // Duplex Mode.
-#define PHY_MR18_RATE           0x00000400  // Rate.
-#define PHY_MR18_RXSD           0x00000200  // Receive Detection.
-#define PHY_MR18_RX_LOCK        0x00000100  // Receive PLL Lock.
+#define PHY_MR18_ANEGF          0x00001000  // Auto-Negotiation Failure
+#define PHY_MR18_DPLX           0x00000800  // Duplex Mode
+#define PHY_MR18_RATE           0x00000400  // Rate
+#define PHY_MR18_RXSD           0x00000200  // Receive Detection
+#define PHY_MR18_RX_LOCK        0x00000100  // Receive PLL Lock
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the MAC_O_MR19 register.
+// The following are defines for the bit fields in the PHY_MR19 register.
 //
 //*****************************************************************************
-#define PHY_MR19_TXO_M          0x0000C000  // Transmit Amplitude Selection.
+#define PHY_MR19_TXO_M          0x0000C000  // Transmit Amplitude Selection
 #define PHY_MR19_TXO_00DB       0x00000000  // Gain set for 0.0dB of insertion
                                             // loss
 #define PHY_MR19_TXO_04DB       0x00004000  // Gain set for 0.4dB of insertion
@@ -2717,24 +2760,10 @@
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the MAC_O_IA0 register.
+// The following are defines for the bit fields in the PHY_MR23 register.
 //
 //*****************************************************************************
-#define MAC_IA0_MACOCT4_M       0xFF000000  // MAC Address Octet 4.
-#define MAC_IA0_MACOCT3_M       0x00FF0000  // MAC Address Octet 3.
-#define MAC_IA0_MACOCT2_M       0x0000FF00  // MAC Address Octet 2.
-#define MAC_IA0_MACOCT1_M       0x000000FF  // MAC Address Octet 1.
-#define MAC_IA0_MACOCT4_S       24
-#define MAC_IA0_MACOCT3_S       16
-#define MAC_IA0_MACOCT2_S       8
-#define MAC_IA0_MACOCT1_S       0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_MR23 register.
-//
-//*****************************************************************************
-#define PHY_MR23_LED1_M         0x000000F0  // LED1 Source.
+#define PHY_MR23_LED1_M         0x000000F0  // LED1 Source
 #define PHY_MR23_LED1_LINK      0x00000000  // Link OK
 #define PHY_MR23_LED1_RXTX      0x00000010  // RX or TX Activity (Default LED1)
 #define PHY_MR23_LED1_100       0x00000050  // 100BASE-TX mode
@@ -2742,7 +2771,7 @@
 #define PHY_MR23_LED1_DUPLEX    0x00000070  // Full-Duplex
 #define PHY_MR23_LED1_LINKACT   0x00000080  // Link OK & Blink=RX or TX
                                             // Activity
-#define PHY_MR23_LED0_M         0x0000000F  // LED0 Source.
+#define PHY_MR23_LED0_M         0x0000000F  // LED0 Source
 #define PHY_MR23_LED0_LINK      0x00000000  // Link OK (Default LED0)
 #define PHY_MR23_LED0_RXTX      0x00000001  // RX or TX Activity
 #define PHY_MR23_LED0_100       0x00000005  // 100BASE-TX mode
@@ -2753,90 +2782,22 @@
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the MAC_O_IA1 register.
+// The following are defines for the bit fields in the PHY_MR24 register.
 //
 //*****************************************************************************
-#define MAC_IA1_MACOCT6_M       0x0000FF00  // MAC Address Octet 6.
-#define MAC_IA1_MACOCT5_M       0x000000FF  // MAC Address Octet 5.
-#define MAC_IA1_MACOCT6_S       8
-#define MAC_IA1_MACOCT5_S       0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_MR24 register.
-//
-//*****************************************************************************
-#define PHY_MR24_PD_MODE        0x00000080  // Parallel Detection Mode.
-#define PHY_MR24_AUTO_SW        0x00000040  // Auto-Switching Enable.
-#define PHY_MR24_MDIX           0x00000020  // Auto-Switching Configuration.
-#define PHY_MR24_MDIX_CM        0x00000010  // Auto-Switching Complete.
-#define PHY_MR24_MDIX_SD_M      0x0000000F  // Auto-Switching Seed.
+#define PHY_MR24_PD_MODE        0x00000080  // Parallel Detection Mode
+#define PHY_MR24_AUTO_SW        0x00000040  // Auto-Switching Enable
+#define PHY_MR24_MDIX           0x00000020  // Auto-Switching Configuration
+#define PHY_MR24_MDIX_CM        0x00000010  // Auto-Switching Complete
+#define PHY_MR24_MDIX_SD_M      0x0000000F  // Auto-Switching Seed
 #define PHY_MR24_MDIX_SD_S      0
 
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_THR register.
-//
-//*****************************************************************************
-#define MAC_THR_THRESH_M        0x0000003F  // Threshold Value.
-#define MAC_THR_THRESH_S        0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_MCTL register.
-//
-//*****************************************************************************
-#define MAC_MCTL_REGADR_M       0x000000F8  // MII Register Address.
-#define MAC_MCTL_WRITE          0x00000002  // MII Register Transaction Type.
-#define MAC_MCTL_START          0x00000001  // MII Register Transaction Enable.
-#define MAC_MCTL_REGADR_S       3
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_MDV register.
-//
-//*****************************************************************************
-#define MAC_MDV_DIV_M           0x000000FF  // Clock Divider.
-#define MAC_MDV_DIV_S           0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_MTXD register.
-//
-//*****************************************************************************
-#define MAC_MTXD_MDTX_M         0x0000FFFF  // MII Register Transmit Data.
-#define MAC_MTXD_MDTX_S         0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_MRXD register.
-//
-//*****************************************************************************
-#define MAC_MRXD_MDRX_M         0x0000FFFF  // MII Register Receive Data.
-#define MAC_MRXD_MDRX_S         0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_NP register.
-//
-//*****************************************************************************
-#define MAC_NP_NPR_M            0x0000003F  // Number of Packets in Receive
-                                            // FIFO.
-#define MAC_NP_NPR_S            0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_TR register.
-//
-//*****************************************************************************
-#define MAC_TR_NEWTX            0x00000001  // New Transmission.
-
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the HIB_RTCC register.
 //
 //*****************************************************************************
-#define HIB_RTCC_M              0xFFFFFFFF  // RTC Counter.
+#define HIB_RTCC_M              0xFFFFFFFF  // RTC Counter
 #define HIB_RTCC_S              0
 
 //*****************************************************************************
@@ -2844,7 +2805,7 @@
 // The following are defines for the bit fields in the HIB_RTCM0 register.
 //
 //*****************************************************************************
-#define HIB_RTCM0_M             0xFFFFFFFF  // RTC Match 0.
+#define HIB_RTCM0_M             0xFFFFFFFF  // RTC Match 0
 #define HIB_RTCM0_S             0
 
 //*****************************************************************************
@@ -2852,7 +2813,7 @@
 // The following are defines for the bit fields in the HIB_RTCM1 register.
 //
 //*****************************************************************************
-#define HIB_RTCM1_M             0xFFFFFFFF  // RTC Match 1.
+#define HIB_RTCM1_M             0xFFFFFFFF  // RTC Match 1
 #define HIB_RTCM1_S             0
 
 //*****************************************************************************
@@ -2860,7 +2821,7 @@
 // The following are defines for the bit fields in the HIB_RTCLD register.
 //
 //*****************************************************************************
-#define HIB_RTCLD_M             0xFFFFFFFF  // RTC Load.
+#define HIB_RTCLD_M             0xFFFFFFFF  // RTC Load
 #define HIB_RTCLD_S             0
 
 //*****************************************************************************
@@ -2868,25 +2829,25 @@
 // The following are defines for the bit fields in the HIB_CTL register.
 //
 //*****************************************************************************
-#define HIB_CTL_VABORT          0x00000080  // Power Cut Abort Enable.
-#define HIB_CTL_CLK32EN         0x00000040  // Clocking Enable.
-#define HIB_CTL_LOWBATEN        0x00000020  // Low Battery Monitoring Enable.
-#define HIB_CTL_PINWEN          0x00000010  // External WAKE Pin Enable.
-#define HIB_CTL_RTCWEN          0x00000008  // RTC Wake-up Enable.
-#define HIB_CTL_CLKSEL          0x00000004  // Hibernation Module Clock Select.
-#define HIB_CTL_HIBREQ          0x00000002  // Hibernation Request.
-#define HIB_CTL_RTCEN           0x00000001  // RTC Timer Enable.
+#define HIB_CTL_VABORT          0x00000080  // Power Cut Abort Enable
+#define HIB_CTL_CLK32EN         0x00000040  // Clocking Enable
+#define HIB_CTL_LOWBATEN        0x00000020  // Low Battery Monitoring Enable
+#define HIB_CTL_PINWEN          0x00000010  // External WAKE Pin Enable
+#define HIB_CTL_RTCWEN          0x00000008  // RTC Wake-up Enable
+#define HIB_CTL_CLKSEL          0x00000004  // Hibernation Module Clock Select
+#define HIB_CTL_HIBREQ          0x00000002  // Hibernation Request
+#define HIB_CTL_RTCEN           0x00000001  // RTC Timer Enable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the HIB_IM register.
 //
 //*****************************************************************************
-#define HIB_IM_EXTW             0x00000008  // External Wake-Up Interrupt Mask.
+#define HIB_IM_EXTW             0x00000008  // External Wake-Up Interrupt Mask
 #define HIB_IM_LOWBAT           0x00000004  // Low Battery Voltage Interrupt
-                                            // Mask.
-#define HIB_IM_RTCALT1          0x00000002  // RTC Alert1 Interrupt Mask.
-#define HIB_IM_RTCALT0          0x00000001  // RTC Alert0 Interrupt Mask.
+                                            // Mask
+#define HIB_IM_RTCALT1          0x00000002  // RTC Alert 1 Interrupt Mask
+#define HIB_IM_RTCALT0          0x00000001  // RTC Alert 0 Interrupt Mask
 
 //*****************************************************************************
 //
@@ -2894,11 +2855,11 @@
 //
 //*****************************************************************************
 #define HIB_RIS_EXTW            0x00000008  // External Wake-Up Raw Interrupt
-                                            // Status.
+                                            // Status
 #define HIB_RIS_LOWBAT          0x00000004  // Low Battery Voltage Raw
-                                            // Interrupt Status.
-#define HIB_RIS_RTCALT1         0x00000002  // RTC Alert1 Raw Interrupt Status.
-#define HIB_RIS_RTCALT0         0x00000001  // RTC Alert0 Raw Interrupt Status.
+                                            // Interrupt Status
+#define HIB_RIS_RTCALT1         0x00000002  // RTC Alert 1 Raw Interrupt Status
+#define HIB_RIS_RTCALT0         0x00000001  // RTC Alert 0 Raw Interrupt Status
 
 //*****************************************************************************
 //
@@ -2906,13 +2867,13 @@
 //
 //*****************************************************************************
 #define HIB_MIS_EXTW            0x00000008  // External Wake-Up Masked
-                                            // Interrupt Status.
+                                            // Interrupt Status
 #define HIB_MIS_LOWBAT          0x00000004  // Low Battery Voltage Masked
-                                            // Interrupt Status.
-#define HIB_MIS_RTCALT1         0x00000002  // RTC Alert1 Masked Interrupt
-                                            // Status.
-#define HIB_MIS_RTCALT0         0x00000001  // RTC Alert0 Masked Interrupt
-                                            // Status.
+                                            // Interrupt Status
+#define HIB_MIS_RTCALT1         0x00000002  // RTC Alert 1 Masked Interrupt
+                                            // Status
+#define HIB_MIS_RTCALT0         0x00000001  // RTC Alert 0 Masked Interrupt
+                                            // Status
 
 //*****************************************************************************
 //
@@ -2920,20 +2881,20 @@
 //
 //*****************************************************************************
 #define HIB_IC_EXTW             0x00000008  // External Wake-Up Masked
-                                            // Interrupt Clear.
+                                            // Interrupt Clear
 #define HIB_IC_LOWBAT           0x00000004  // Low Battery Voltage Masked
-                                            // Interrupt Clear.
+                                            // Interrupt Clear
 #define HIB_IC_RTCALT1          0x00000002  // RTC Alert1 Masked Interrupt
-                                            // Clear.
+                                            // Clear
 #define HIB_IC_RTCALT0          0x00000001  // RTC Alert0 Masked Interrupt
-                                            // Clear.
+                                            // Clear
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the HIB_RTCT register.
 //
 //*****************************************************************************
-#define HIB_RTCT_TRIM_M         0x0000FFFF  // RTC Trim Value.
+#define HIB_RTCT_TRIM_M         0x0000FFFF  // RTC Trim Value
 #define HIB_RTCT_TRIM_S         0
 
 //*****************************************************************************
@@ -2941,8 +2902,7 @@
 // The following are defines for the bit fields in the HIB_DATA register.
 //
 //*****************************************************************************
-#define HIB_DATA_RTD_M          0xFFFFFFFF  // Hibernation Module NV
-                                            // Registers[63:0].
+#define HIB_DATA_RTD_M          0xFFFFFFFF  // Hibernation Module NV Data
 #define HIB_DATA_RTD_S          0
 
 //*****************************************************************************
@@ -2950,7 +2910,7 @@
 // The following are defines for the bit fields in the FLASH_FMA register.
 //
 //*****************************************************************************
-#define FLASH_FMA_OFFSET_M      0x0003FFFF  // Address Offset.
+#define FLASH_FMA_OFFSET_M      0x0003FFFF  // Address Offset
 #define FLASH_FMA_OFFSET_S      0
 
 //*****************************************************************************
@@ -2958,7 +2918,7 @@
 // The following are defines for the bit fields in the FLASH_FMD register.
 //
 //*****************************************************************************
-#define FLASH_FMD_DATA_M        0xFFFFFFFF  // Data Value.
+#define FLASH_FMD_DATA_M        0xFFFFFFFF  // Data Value
 #define FLASH_FMD_DATA_S        0
 
 //*****************************************************************************
@@ -2966,30 +2926,27 @@
 // The following are defines for the bit fields in the FLASH_FMC register.
 //
 //*****************************************************************************
-#define FLASH_FMC_WRKEY_M       0xFFFF0000  // Flash Write Key.
 #define FLASH_FMC_WRKEY         0xA4420000  // FLASH write key
-#define FLASH_FMC_COMT          0x00000008  // Commit Register Value.
-#define FLASH_FMC_MERASE        0x00000004  // Mass Erase Flash Memory.
-#define FLASH_FMC_ERASE         0x00000002  // Erase a Page of Flash Memory.
-#define FLASH_FMC_WRITE         0x00000001  // Write a Word into Flash Memory.
-#define FLASH_FMC_WRKEY_S       16
+#define FLASH_FMC_COMT          0x00000008  // Commit Register Value
+#define FLASH_FMC_MERASE        0x00000004  // Mass Erase Flash Memory
+#define FLASH_FMC_ERASE         0x00000002  // Erase a Page of Flash Memory
+#define FLASH_FMC_WRITE         0x00000001  // Write a Word into Flash Memory
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the FLASH_FCRIS register.
 //
 //*****************************************************************************
-#define FLASH_FCRIS_PRIS        0x00000002  // Programming Raw Interrupt
-                                            // Status.
-#define FLASH_FCRIS_ARIS        0x00000001  // Access Raw Interrupt Status.
+#define FLASH_FCRIS_PRIS        0x00000002  // Programming Raw Interrupt Status
+#define FLASH_FCRIS_ARIS        0x00000001  // Access Raw Interrupt Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the FLASH_FCIM register.
 //
 //*****************************************************************************
-#define FLASH_FCIM_PMASK        0x00000002  // Programming Interrupt Mask.
-#define FLASH_FCIM_AMASK        0x00000001  // Access Interrupt Mask.
+#define FLASH_FCIM_PMASK        0x00000002  // Programming Interrupt Mask
+#define FLASH_FCIM_AMASK        0x00000001  // Access Interrupt Mask
 
 //*****************************************************************************
 //
@@ -2997,16 +2954,16 @@
 //
 //*****************************************************************************
 #define FLASH_FCMISC_PMISC      0x00000002  // Programming Masked Interrupt
-                                            // Status and Clear.
+                                            // Status and Clear
 #define FLASH_FCMISC_AMISC      0x00000001  // Access Masked Interrupt Status
-                                            // and Clear.
+                                            // and Clear
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the FLASH_USECRL register.
 //
 //*****************************************************************************
-#define FLASH_USECRL_M          0x000000FF  // Microsecond Reload Value.
+#define FLASH_USECRL_M          0x000000FF  // Microsecond Reload Value
 #define FLASH_USECRL_S          0
 
 //*****************************************************************************
@@ -3014,10 +2971,10 @@
 // The following are defines for the bit fields in the FLASH_USERDBG register.
 //
 //*****************************************************************************
-#define FLASH_USERDBG_NW        0x80000000  // User Debug Not Written.
-#define FLASH_USERDBG_DATA_M    0x7FFFFFFC  // User Data.
-#define FLASH_USERDBG_DBG1      0x00000002  // Debug Control 1.
-#define FLASH_USERDBG_DBG0      0x00000001  // Debug Control 0.
+#define FLASH_USERDBG_NW        0x80000000  // User Debug Not Written
+#define FLASH_USERDBG_DATA_M    0x7FFFFFFC  // User Data
+#define FLASH_USERDBG_DBG1      0x00000002  // Debug Control 1
+#define FLASH_USERDBG_DBG0      0x00000001  // Debug Control 0
 #define FLASH_USERDBG_DATA_S    2
 
 //*****************************************************************************
@@ -3025,8 +2982,8 @@
 // The following are defines for the bit fields in the FLASH_USERREG0 register.
 //
 //*****************************************************************************
-#define FLASH_USERREG0_NW       0x80000000  // Not Written.
-#define FLASH_USERREG0_DATA_M   0x7FFFFFFF  // User Data.
+#define FLASH_USERREG0_NW       0x80000000  // Not Written
+#define FLASH_USERREG0_DATA_M   0x7FFFFFFF  // User Data
 #define FLASH_USERREG0_DATA_S   0
 
 //*****************************************************************************
@@ -3034,8 +2991,8 @@
 // The following are defines for the bit fields in the FLASH_USERREG1 register.
 //
 //*****************************************************************************
-#define FLASH_USERREG1_NW       0x80000000  // Not Written.
-#define FLASH_USERREG1_DATA_M   0x7FFFFFFF  // User Data.
+#define FLASH_USERREG1_NW       0x80000000  // Not Written
+#define FLASH_USERREG1_DATA_M   0x7FFFFFFF  // User Data
 #define FLASH_USERREG1_DATA_S   0
 
 //*****************************************************************************
@@ -3053,54 +3010,54 @@
 // The following are defines for the bit fields in the SYSCTL_DID0 register.
 //
 //*****************************************************************************
-#define SYSCTL_DID0_VER_M       0x70000000  // DID0 Version.
+#define SYSCTL_DID0_VER_M       0x70000000  // DID0 Version
 #define SYSCTL_DID0_VER_1       0x10000000  // Second version of the DID0
-                                            // register format.
-#define SYSCTL_DID0_CLASS_M     0x00FF0000  // Device Class.
-#define SYSCTL_DID0_CLASS_FURY  0x00010000  // Stellaris(r) Fury-class devices.
-#define SYSCTL_DID0_MAJ_M       0x0000FF00  // Major Revision.
+                                            // register format
+#define SYSCTL_DID0_CLASS_M     0x00FF0000  // Device Class
+#define SYSCTL_DID0_CLASS_FURY  0x00010000  // Stellaris(R) Fury-class devices
+#define SYSCTL_DID0_MAJ_M       0x0000FF00  // Major Revision
 #define SYSCTL_DID0_MAJ_REVA    0x00000000  // Revision A (initial device)
 #define SYSCTL_DID0_MAJ_REVB    0x00000100  // Revision B (first base layer
                                             // revision)
 #define SYSCTL_DID0_MAJ_REVC    0x00000200  // Revision C (second base layer
                                             // revision)
-#define SYSCTL_DID0_MIN_M       0x000000FF  // Minor Revision.
+#define SYSCTL_DID0_MIN_M       0x000000FF  // Minor Revision
 #define SYSCTL_DID0_MIN_0       0x00000000  // Initial device, or a major
-                                            // revision update.
-#define SYSCTL_DID0_MIN_1       0x00000001  // First metal layer change.
-#define SYSCTL_DID0_MIN_2       0x00000002  // Second metal layer change.
+                                            // revision update
+#define SYSCTL_DID0_MIN_1       0x00000001  // First metal layer change
+#define SYSCTL_DID0_MIN_2       0x00000002  // Second metal layer change
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_DID1 register.
 //
 //*****************************************************************************
-#define SYSCTL_DID1_VER_M       0xF0000000  // DID1 Version.
+#define SYSCTL_DID1_VER_M       0xF0000000  // DID1 Version
 #define SYSCTL_DID1_VER_1       0x10000000  // Second version of the DID1
-                                            // register format.
-#define SYSCTL_DID1_FAM_M       0x0F000000  // Family.
+                                            // register format
+#define SYSCTL_DID1_FAM_M       0x0F000000  // Family
 #define SYSCTL_DID1_FAM_STELLARIS \
                                 0x00000000  // Stellaris family of
                                             // microcontollers, that is, all
                                             // devices with external part
-                                            // numbers starting with LM3S.
-#define SYSCTL_DID1_PRTNO_M     0x00FF0000  // Part Number.
+                                            // numbers starting with LM3S
+#define SYSCTL_DID1_PRTNO_M     0x00FF0000  // Part Number
 #define SYSCTL_DID1_PRTNO_6965  0x00730000  // LM3S6965
-#define SYSCTL_DID1_PINCNT_M    0x0000E000  // Package Pin Count.
-#define SYSCTL_DID1_PINCNT_100  0x00004000  // 100-pin or 108-ball package
-#define SYSCTL_DID1_TEMP_M      0x000000E0  // Temperature Range.
+#define SYSCTL_DID1_PINCNT_M    0x0000E000  // Package Pin Count
+#define SYSCTL_DID1_PINCNT_100  0x00004000  // 100-pin package
+#define SYSCTL_DID1_TEMP_M      0x000000E0  // Temperature Range
 #define SYSCTL_DID1_TEMP_C      0x00000000  // Commercial temperature range (0C
                                             // to 70C)
 #define SYSCTL_DID1_TEMP_I      0x00000020  // Industrial temperature range
                                             // (-40C to 85C)
 #define SYSCTL_DID1_TEMP_E      0x00000040  // Extended temperature range (-40C
                                             // to 105C)
-#define SYSCTL_DID1_PKG_M       0x00000018  // Package Type.
-#define SYSCTL_DID1_PKG_28SOIC  0x00000000  // SOIC package
-#define SYSCTL_DID1_PKG_48QFP   0x00000008  // LQFP package
+#define SYSCTL_DID1_PKG_M       0x00000018  // Package Type
+#define SYSCTL_DID1_PKG_SOIC    0x00000000  // SOIC package
+#define SYSCTL_DID1_PKG_QFP     0x00000008  // LQFP package
 #define SYSCTL_DID1_PKG_BGA     0x00000010  // BGA package
-#define SYSCTL_DID1_ROHS        0x00000004  // RoHS-Compliance.
-#define SYSCTL_DID1_QUAL_M      0x00000003  // Qualification Status.
+#define SYSCTL_DID1_ROHS        0x00000004  // RoHS-Compliance
+#define SYSCTL_DID1_QUAL_M      0x00000003  // Qualification Status
 #define SYSCTL_DID1_QUAL_ES     0x00000000  // Engineering Sample (unqualified)
 #define SYSCTL_DID1_QUAL_PP     0x00000001  // Pilot Production (unqualified)
 #define SYSCTL_DID1_QUAL_FQ     0x00000002  // Fully Qualified
@@ -3110,9 +3067,9 @@
 // The following are defines for the bit fields in the SYSCTL_DC0 register.
 //
 //*****************************************************************************
-#define SYSCTL_DC0_SRAMSZ_M     0xFFFF0000  // SRAM Size.
+#define SYSCTL_DC0_SRAMSZ_M     0xFFFF0000  // SRAM Size
 #define SYSCTL_DC0_SRAMSZ_64KB  0x00FF0000  // 64 KB of SRAM
-#define SYSCTL_DC0_FLASHSZ_M    0x0000FFFF  // Flash Size.
+#define SYSCTL_DC0_FLASHSZ_M    0x0000FFFF  // Flash Size
 #define SYSCTL_DC0_FLASHSZ_256K 0x0000007F  // 256 KB of Flash
 #define SYSCTL_DC0_SRAMSZ_S     16          // SRAM size shift
 #define SYSCTL_DC0_FLASHSZ_S    0           // Flash size shift
@@ -3122,97 +3079,97 @@
 // The following are defines for the bit fields in the SYSCTL_DC1 register.
 //
 //*****************************************************************************
-#define SYSCTL_DC1_PWM          0x00100000  // PWM Module Present.
-#define SYSCTL_DC1_ADC          0x00010000  // ADC Module Present.
-#define SYSCTL_DC1_MINSYSDIV_M  0x0000F000  // System Clock Divider.
+#define SYSCTL_DC1_PWM          0x00100000  // PWM Module Present
+#define SYSCTL_DC1_ADC          0x00010000  // ADC Module Present
+#define SYSCTL_DC1_MINSYSDIV_M  0x0000F000  // System Clock Divider
 #define SYSCTL_DC1_MINSYSDIV_50 0x00003000  // Specifies a 50-MHz CPU clock
-                                            // with a PLL divider of 4.
-#define SYSCTL_DC1_ADCSPD_M     0x00000300  // Max ADC Speed.
+                                            // with a PLL divider of 4
+#define SYSCTL_DC1_ADCSPD_M     0x00000300  // Max ADC Speed
 #define SYSCTL_DC1_ADCSPD_1M    0x00000300  // 1M samples/second
-#define SYSCTL_DC1_MPU          0x00000080  // MPU Present.
-#define SYSCTL_DC1_HIB          0x00000040  // Hibernation Module Present.
-#define SYSCTL_DC1_TEMP         0x00000020  // Temp Sensor Present.
-#define SYSCTL_DC1_PLL          0x00000010  // PLL Present.
-#define SYSCTL_DC1_WDT          0x00000008  // Watchdog Timer Present.
-#define SYSCTL_DC1_SWO          0x00000004  // SWO Trace Port Present.
-#define SYSCTL_DC1_SWD          0x00000002  // SWD Present.
-#define SYSCTL_DC1_JTAG         0x00000001  // JTAG Present.
+#define SYSCTL_DC1_MPU          0x00000080  // MPU Present
+#define SYSCTL_DC1_HIB          0x00000040  // Hibernation Module Present
+#define SYSCTL_DC1_TEMP         0x00000020  // Temp Sensor Present
+#define SYSCTL_DC1_PLL          0x00000010  // PLL Present
+#define SYSCTL_DC1_WDT0         0x00000008  // Watchdog Timer 0 Present
+#define SYSCTL_DC1_SWO          0x00000004  // SWO Trace Port Present
+#define SYSCTL_DC1_SWD          0x00000002  // SWD Present
+#define SYSCTL_DC1_JTAG         0x00000001  // JTAG Present
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_DC2 register.
 //
 //*****************************************************************************
-#define SYSCTL_DC2_COMP1        0x02000000  // Analog Comparator 1 Present.
-#define SYSCTL_DC2_COMP0        0x01000000  // Analog Comparator 0 Present.
-#define SYSCTL_DC2_TIMER3       0x00080000  // Timer 3 Present.
-#define SYSCTL_DC2_TIMER2       0x00040000  // Timer 2 Present.
-#define SYSCTL_DC2_TIMER1       0x00020000  // Timer 1 Present.
-#define SYSCTL_DC2_TIMER0       0x00010000  // Timer 0 Present.
-#define SYSCTL_DC2_I2C1         0x00004000  // I2C Module 1 Present.
-#define SYSCTL_DC2_I2C0         0x00001000  // I2C Module 0 Present.
-#define SYSCTL_DC2_QEI1         0x00000200  // QEI1 Present.
-#define SYSCTL_DC2_QEI0         0x00000100  // QEI0 Present.
-#define SYSCTL_DC2_SSI0         0x00000010  // SSI0 Present.
-#define SYSCTL_DC2_UART2        0x00000004  // UART2 Present.
-#define SYSCTL_DC2_UART1        0x00000002  // UART1 Present.
-#define SYSCTL_DC2_UART0        0x00000001  // UART0 Present.
+#define SYSCTL_DC2_COMP1        0x02000000  // Analog Comparator 1 Present
+#define SYSCTL_DC2_COMP0        0x01000000  // Analog Comparator 0 Present
+#define SYSCTL_DC2_TIMER3       0x00080000  // Timer Module 3 Present
+#define SYSCTL_DC2_TIMER2       0x00040000  // Timer Module 2 Present
+#define SYSCTL_DC2_TIMER1       0x00020000  // Timer Module 1 Present
+#define SYSCTL_DC2_TIMER0       0x00010000  // Timer Module 0 Present
+#define SYSCTL_DC2_I2C1         0x00004000  // I2C Module 1 Present
+#define SYSCTL_DC2_I2C0         0x00001000  // I2C Module 0 Present
+#define SYSCTL_DC2_QEI1         0x00000200  // QEI Module 1 Present
+#define SYSCTL_DC2_QEI0         0x00000100  // QEI Module 0 Present
+#define SYSCTL_DC2_SSI0         0x00000010  // SSI Module 0 Present
+#define SYSCTL_DC2_UART2        0x00000004  // UART Module 2 Present
+#define SYSCTL_DC2_UART1        0x00000002  // UART Module 1 Present
+#define SYSCTL_DC2_UART0        0x00000001  // UART Module 0 Present
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_DC3 register.
 //
 //*****************************************************************************
-#define SYSCTL_DC3_32KHZ        0x80000000  // 32KHz Input Clock Available.
-#define SYSCTL_DC3_CCP3         0x08000000  // CCP3 Pin Present.
-#define SYSCTL_DC3_CCP2         0x04000000  // CCP2 Pin Present.
-#define SYSCTL_DC3_CCP1         0x02000000  // CCP1 Pin Present.
-#define SYSCTL_DC3_CCP0         0x01000000  // CCP0 Pin Present.
-#define SYSCTL_DC3_ADC3         0x00080000  // ADC3 Pin Present.
-#define SYSCTL_DC3_ADC2         0x00040000  // ADC2 Pin Present.
-#define SYSCTL_DC3_ADC1         0x00020000  // ADC1 Pin Present.
-#define SYSCTL_DC3_ADC0         0x00010000  // ADC0 Pin Present.
-#define SYSCTL_DC3_PWMFAULT     0x00008000  // PWM Fault Pin Present.
-#define SYSCTL_DC3_C1PLUS       0x00000400  // C1+ Pin Present.
-#define SYSCTL_DC3_C1MINUS      0x00000200  // C1- Pin Present.
-#define SYSCTL_DC3_C0O          0x00000100  // C0o Pin Present.
-#define SYSCTL_DC3_C0PLUS       0x00000080  // C0+ Pin Present.
-#define SYSCTL_DC3_C0MINUS      0x00000040  // C0- Pin Present.
-#define SYSCTL_DC3_PWM5         0x00000020  // PWM5 Pin Present.
-#define SYSCTL_DC3_PWM4         0x00000010  // PWM4 Pin Present.
-#define SYSCTL_DC3_PWM3         0x00000008  // PWM3 Pin Present.
-#define SYSCTL_DC3_PWM2         0x00000004  // PWM2 Pin Present.
-#define SYSCTL_DC3_PWM1         0x00000002  // PWM1 Pin Present.
-#define SYSCTL_DC3_PWM0         0x00000001  // PWM0 Pin Present.
+#define SYSCTL_DC3_32KHZ        0x80000000  // 32KHz Input Clock Available
+#define SYSCTL_DC3_CCP3         0x08000000  // CCP3 Pin Present
+#define SYSCTL_DC3_CCP2         0x04000000  // CCP2 Pin Present
+#define SYSCTL_DC3_CCP1         0x02000000  // CCP1 Pin Present
+#define SYSCTL_DC3_CCP0         0x01000000  // CCP0 Pin Present
+#define SYSCTL_DC3_ADC3         0x00080000  // ADC3 Pin Present
+#define SYSCTL_DC3_ADC2         0x00040000  // ADC2 Pin Present
+#define SYSCTL_DC3_ADC1         0x00020000  // ADC1 Pin Present
+#define SYSCTL_DC3_ADC0         0x00010000  // ADC0 Pin Present
+#define SYSCTL_DC3_PWMFAULT     0x00008000  // PWM Fault Pin Present
+#define SYSCTL_DC3_C1PLUS       0x00000400  // C1+ Pin Present
+#define SYSCTL_DC3_C1MINUS      0x00000200  // C1- Pin Present
+#define SYSCTL_DC3_C0O          0x00000100  // C0o Pin Present
+#define SYSCTL_DC3_C0PLUS       0x00000080  // C0+ Pin Present
+#define SYSCTL_DC3_C0MINUS      0x00000040  // C0- Pin Present
+#define SYSCTL_DC3_PWM5         0x00000020  // PWM5 Pin Present
+#define SYSCTL_DC3_PWM4         0x00000010  // PWM4 Pin Present
+#define SYSCTL_DC3_PWM3         0x00000008  // PWM3 Pin Present
+#define SYSCTL_DC3_PWM2         0x00000004  // PWM2 Pin Present
+#define SYSCTL_DC3_PWM1         0x00000002  // PWM1 Pin Present
+#define SYSCTL_DC3_PWM0         0x00000001  // PWM0 Pin Present
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_DC4 register.
 //
 //*****************************************************************************
-#define SYSCTL_DC4_EPHY0        0x40000000  // Ethernet PHY0 Present.
-#define SYSCTL_DC4_EMAC0        0x10000000  // Ethernet MAC0 Present.
-#define SYSCTL_DC4_GPIOG        0x00000040  // GPIO Port G Present.
-#define SYSCTL_DC4_GPIOF        0x00000020  // GPIO Port F Present.
-#define SYSCTL_DC4_GPIOE        0x00000010  // GPIO Port E Present.
-#define SYSCTL_DC4_GPIOD        0x00000008  // GPIO Port D Present.
-#define SYSCTL_DC4_GPIOC        0x00000004  // GPIO Port C Present.
-#define SYSCTL_DC4_GPIOB        0x00000002  // GPIO Port B Present.
-#define SYSCTL_DC4_GPIOA        0x00000001  // GPIO Port A Present.
+#define SYSCTL_DC4_EPHY0        0x40000000  // Ethernet PHY Layer 0 Present
+#define SYSCTL_DC4_EMAC0        0x10000000  // Ethernet MAC Layer 0 Present
+#define SYSCTL_DC4_GPIOG        0x00000040  // GPIO Port G Present
+#define SYSCTL_DC4_GPIOF        0x00000020  // GPIO Port F Present
+#define SYSCTL_DC4_GPIOE        0x00000010  // GPIO Port E Present
+#define SYSCTL_DC4_GPIOD        0x00000008  // GPIO Port D Present
+#define SYSCTL_DC4_GPIOC        0x00000004  // GPIO Port C Present
+#define SYSCTL_DC4_GPIOB        0x00000002  // GPIO Port B Present
+#define SYSCTL_DC4_GPIOA        0x00000001  // GPIO Port A Present
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_PBORCTL register.
 //
 //*****************************************************************************
-#define SYSCTL_PBORCTL_BORIOR   0x00000002  // BOR Interrupt or Reset.
+#define SYSCTL_PBORCTL_BORIOR   0x00000002  // BOR Interrupt or Reset
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_LDOPCTL register.
 //
 //*****************************************************************************
-#define SYSCTL_LDOPCTL_M        0x0000003F  // LDO Output Voltage.
+#define SYSCTL_LDOPCTL_M        0x0000003F  // LDO Output Voltage
 #define SYSCTL_LDOPCTL_2_50V    0x00000000  // 2.50
 #define SYSCTL_LDOPCTL_2_45V    0x00000001  // 2.45
 #define SYSCTL_LDOPCTL_2_40V    0x00000002  // 2.40
@@ -3230,122 +3187,120 @@
 // The following are defines for the bit fields in the SYSCTL_SRCR0 register.
 //
 //*****************************************************************************
-#define SYSCTL_SRCR0_PWM        0x00100000  // PWM Reset Control.
-#define SYSCTL_SRCR0_ADC        0x00010000  // ADC0 Reset Control.
-#define SYSCTL_SRCR0_HIB        0x00000040  // HIB Reset Control.
-#define SYSCTL_SRCR0_WDT        0x00000008  // WDT Reset Control.
+#define SYSCTL_SRCR0_PWM        0x00100000  // PWM Reset Control
+#define SYSCTL_SRCR0_ADC        0x00010000  // ADC0 Reset Control
+#define SYSCTL_SRCR0_HIB        0x00000040  // HIB Reset Control
+#define SYSCTL_SRCR0_WDT        0x00000008  // WDT Reset Control
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_SRCR1 register.
 //
 //*****************************************************************************
-#define SYSCTL_SRCR1_COMP1      0x02000000  // Analog Comp 1 Reset Control.
-#define SYSCTL_SRCR1_COMP0      0x01000000  // Analog Comp 0 Reset Control.
-#define SYSCTL_SRCR1_TIMER3     0x00080000  // Timer 3 Reset Control.
-#define SYSCTL_SRCR1_TIMER2     0x00040000  // Timer 2 Reset Control.
-#define SYSCTL_SRCR1_TIMER1     0x00020000  // Timer 1 Reset Control.
-#define SYSCTL_SRCR1_TIMER0     0x00010000  // Timer 0 Reset Control.
-#define SYSCTL_SRCR1_I2C1       0x00004000  // I2C1 Reset Control.
-#define SYSCTL_SRCR1_I2C0       0x00001000  // I2C0 Reset Control.
-#define SYSCTL_SRCR1_QEI1       0x00000200  // QEI1 Reset Control.
-#define SYSCTL_SRCR1_QEI0       0x00000100  // QEI0 Reset Control.
-#define SYSCTL_SRCR1_SSI0       0x00000010  // SSI0 Reset Control.
-#define SYSCTL_SRCR1_UART2      0x00000004  // UART2 Reset Control.
-#define SYSCTL_SRCR1_UART1      0x00000002  // UART1 Reset Control.
-#define SYSCTL_SRCR1_UART0      0x00000001  // UART0 Reset Control.
+#define SYSCTL_SRCR1_COMP1      0x02000000  // Analog Comp 1 Reset Control
+#define SYSCTL_SRCR1_COMP0      0x01000000  // Analog Comp 0 Reset Control
+#define SYSCTL_SRCR1_TIMER3     0x00080000  // Timer 3 Reset Control
+#define SYSCTL_SRCR1_TIMER2     0x00040000  // Timer 2 Reset Control
+#define SYSCTL_SRCR1_TIMER1     0x00020000  // Timer 1 Reset Control
+#define SYSCTL_SRCR1_TIMER0     0x00010000  // Timer 0 Reset Control
+#define SYSCTL_SRCR1_I2C1       0x00004000  // I2C1 Reset Control
+#define SYSCTL_SRCR1_I2C0       0x00001000  // I2C0 Reset Control
+#define SYSCTL_SRCR1_QEI1       0x00000200  // QEI1 Reset Control
+#define SYSCTL_SRCR1_QEI0       0x00000100  // QEI0 Reset Control
+#define SYSCTL_SRCR1_SSI0       0x00000010  // SSI0 Reset Control
+#define SYSCTL_SRCR1_UART2      0x00000004  // UART2 Reset Control
+#define SYSCTL_SRCR1_UART1      0x00000002  // UART1 Reset Control
+#define SYSCTL_SRCR1_UART0      0x00000001  // UART0 Reset Control
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_SRCR2 register.
 //
 //*****************************************************************************
-#define SYSCTL_SRCR2_EPHY0      0x40000000  // PHY0 Reset Control.
-#define SYSCTL_SRCR2_EMAC0      0x10000000  // MAC0 Reset Control.
-#define SYSCTL_SRCR2_GPIOG      0x00000040  // Port G Reset Control.
-#define SYSCTL_SRCR2_GPIOF      0x00000020  // Port F Reset Control.
-#define SYSCTL_SRCR2_GPIOE      0x00000010  // Port E Reset Control.
-#define SYSCTL_SRCR2_GPIOD      0x00000008  // Port D Reset Control.
-#define SYSCTL_SRCR2_GPIOC      0x00000004  // Port C Reset Control.
-#define SYSCTL_SRCR2_GPIOB      0x00000002  // Port B Reset Control.
-#define SYSCTL_SRCR2_GPIOA      0x00000001  // Port A Reset Control.
+#define SYSCTL_SRCR2_EPHY0      0x40000000  // PHY0 Reset Control
+#define SYSCTL_SRCR2_EMAC0      0x10000000  // MAC0 Reset Control
+#define SYSCTL_SRCR2_GPIOG      0x00000040  // Port G Reset Control
+#define SYSCTL_SRCR2_GPIOF      0x00000020  // Port F Reset Control
+#define SYSCTL_SRCR2_GPIOE      0x00000010  // Port E Reset Control
+#define SYSCTL_SRCR2_GPIOD      0x00000008  // Port D Reset Control
+#define SYSCTL_SRCR2_GPIOC      0x00000004  // Port C Reset Control
+#define SYSCTL_SRCR2_GPIOB      0x00000002  // Port B Reset Control
+#define SYSCTL_SRCR2_GPIOA      0x00000001  // Port A Reset Control
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_RIS register.
 //
 //*****************************************************************************
-#define SYSCTL_RIS_PLLLRIS      0x00000040  // PLL Lock Raw Interrupt Status.
+#define SYSCTL_RIS_PLLLRIS      0x00000040  // PLL Lock Raw Interrupt Status
 #define SYSCTL_RIS_BORRIS       0x00000002  // Brown-Out Reset Raw Interrupt
-                                            // Status.
+                                            // Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_IMC register.
 //
 //*****************************************************************************
-#define SYSCTL_IMC_PLLLIM       0x00000040  // PLL Lock Interrupt Mask.
-#define SYSCTL_IMC_BORIM        0x00000002  // Brown-Out Reset Interrupt Mask.
+#define SYSCTL_IMC_PLLLIM       0x00000040  // PLL Lock Interrupt Mask
+#define SYSCTL_IMC_BORIM        0x00000002  // Brown-Out Reset Interrupt Mask
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_MISC register.
 //
 //*****************************************************************************
-#define SYSCTL_MISC_PLLLMIS     0x00000040  // PLL Lock Masked Interrupt
-                                            // Status.
-#define SYSCTL_MISC_BORMIS      0x00000002  // BOR Masked Interrupt Status.
+#define SYSCTL_MISC_PLLLMIS     0x00000040  // PLL Lock Masked Interrupt Status
+#define SYSCTL_MISC_BORMIS      0x00000002  // BOR Masked Interrupt Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_RESC register.
 //
 //*****************************************************************************
-#define SYSCTL_RESC_LDO         0x00000020  // LDO Reset.
-#define SYSCTL_RESC_SW          0x00000010  // Software Reset.
-#define SYSCTL_RESC_WDT         0x00000008  // Watchdog Timer Reset.
-#define SYSCTL_RESC_BOR         0x00000004  // Brown-Out Reset.
-#define SYSCTL_RESC_POR         0x00000002  // Power-On Reset.
-#define SYSCTL_RESC_EXT         0x00000001  // External Reset.
+#define SYSCTL_RESC_SW          0x00000010  // Software Reset
+#define SYSCTL_RESC_WDT         0x00000008  // Watchdog Timer Reset
+#define SYSCTL_RESC_BOR         0x00000004  // Brown-Out Reset
+#define SYSCTL_RESC_POR         0x00000002  // Power-On Reset
+#define SYSCTL_RESC_EXT         0x00000001  // External Reset
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_RCC register.
 //
 //*****************************************************************************
-#define SYSCTL_RCC_ACG          0x08000000  // Auto Clock Gating.
-#define SYSCTL_RCC_SYSDIV_M     0x07800000  // System Clock Divisor.
-#define SYSCTL_RCC_SYSDIV_2     0x00800000  // /2
-#define SYSCTL_RCC_SYSDIV_3     0x01000000  // /3
-#define SYSCTL_RCC_SYSDIV_4     0x01800000  // /4
-#define SYSCTL_RCC_SYSDIV_5     0x02000000  // /5
-#define SYSCTL_RCC_SYSDIV_6     0x02800000  // /6
-#define SYSCTL_RCC_SYSDIV_7     0x03000000  // /7
-#define SYSCTL_RCC_SYSDIV_8     0x03800000  // /8
-#define SYSCTL_RCC_SYSDIV_9     0x04000000  // /9
-#define SYSCTL_RCC_SYSDIV_10    0x04800000  // /10
-#define SYSCTL_RCC_SYSDIV_11    0x05000000  // /11
-#define SYSCTL_RCC_SYSDIV_12    0x05800000  // /12
-#define SYSCTL_RCC_SYSDIV_13    0x06000000  // /13
-#define SYSCTL_RCC_SYSDIV_14    0x06800000  // /14
-#define SYSCTL_RCC_SYSDIV_15    0x07000000  // /15
-#define SYSCTL_RCC_SYSDIV_16    0x07800000  // /16
-#define SYSCTL_RCC_USESYSDIV    0x00400000  // Enable System Clock Divider.
-#define SYSCTL_RCC_USEPWMDIV    0x00100000  // Enable PWM Clock Divisor.
-#define SYSCTL_RCC_PWMDIV_M     0x000E0000  // PWM Unit Clock Divisor.
-#define SYSCTL_RCC_PWMDIV_2     0x00000000  // /2
-#define SYSCTL_RCC_PWMDIV_4     0x00020000  // /4
-#define SYSCTL_RCC_PWMDIV_8     0x00040000  // /8
-#define SYSCTL_RCC_PWMDIV_16    0x00060000  // /16
-#define SYSCTL_RCC_PWMDIV_32    0x00080000  // /32
-#define SYSCTL_RCC_PWMDIV_64    0x000A0000  // /64
-#define SYSCTL_RCC_PWRDN        0x00002000  // PLL Power Down.
-#define SYSCTL_RCC_BYPASS       0x00000800  // PLL Bypass.
-#define SYSCTL_RCC_XTAL_M       0x000003C0  // Crystal Value.
-#define SYSCTL_RCC_XTAL_1MHZ    0x00000000  // 1.000
-#define SYSCTL_RCC_XTAL_1_84MHZ 0x00000040  // 1.8432
-#define SYSCTL_RCC_XTAL_2MHZ    0x00000080  // 2.000
-#define SYSCTL_RCC_XTAL_2_45MHZ 0x000000C0  // 2.4576
+#define SYSCTL_RCC_ACG          0x08000000  // Auto Clock Gating
+#define SYSCTL_RCC_SYSDIV_M     0x07800000  // System Clock Divisor
+#define SYSCTL_RCC_SYSDIV_2     0x00800000  // System clock /2
+#define SYSCTL_RCC_SYSDIV_3     0x01000000  // System clock /3
+#define SYSCTL_RCC_SYSDIV_4     0x01800000  // System clock /4
+#define SYSCTL_RCC_SYSDIV_5     0x02000000  // System clock /5
+#define SYSCTL_RCC_SYSDIV_6     0x02800000  // System clock /6
+#define SYSCTL_RCC_SYSDIV_7     0x03000000  // System clock /7
+#define SYSCTL_RCC_SYSDIV_8     0x03800000  // System clock /8
+#define SYSCTL_RCC_SYSDIV_9     0x04000000  // System clock /9
+#define SYSCTL_RCC_SYSDIV_10    0x04800000  // System clock /10
+#define SYSCTL_RCC_SYSDIV_11    0x05000000  // System clock /11
+#define SYSCTL_RCC_SYSDIV_12    0x05800000  // System clock /12
+#define SYSCTL_RCC_SYSDIV_13    0x06000000  // System clock /13
+#define SYSCTL_RCC_SYSDIV_14    0x06800000  // System clock /14
+#define SYSCTL_RCC_SYSDIV_15    0x07000000  // System clock /15
+#define SYSCTL_RCC_SYSDIV_16    0x07800000  // System clock /16
+#define SYSCTL_RCC_USESYSDIV    0x00400000  // Enable System Clock Divider
+#define SYSCTL_RCC_USEPWMDIV    0x00100000  // Enable PWM Clock Divisor
+#define SYSCTL_RCC_PWMDIV_M     0x000E0000  // PWM Unit Clock Divisor
+#define SYSCTL_RCC_PWMDIV_2     0x00000000  // PWM clock /2
+#define SYSCTL_RCC_PWMDIV_4     0x00020000  // PWM clock /4
+#define SYSCTL_RCC_PWMDIV_8     0x00040000  // PWM clock /8
+#define SYSCTL_RCC_PWMDIV_16    0x00060000  // PWM clock /16
+#define SYSCTL_RCC_PWMDIV_32    0x00080000  // PWM clock /32
+#define SYSCTL_RCC_PWMDIV_64    0x000A0000  // PWM clock /64
+#define SYSCTL_RCC_PWRDN        0x00002000  // PLL Power Down
+#define SYSCTL_RCC_BYPASS       0x00000800  // PLL Bypass
+#define SYSCTL_RCC_XTAL_M       0x000003C0  // Crystal Value
+#define SYSCTL_RCC_XTAL_1MHZ    0x00000000  // 1 MHz
+#define SYSCTL_RCC_XTAL_1_84MHZ 0x00000040  // 1.8432 MHz
+#define SYSCTL_RCC_XTAL_2MHZ    0x00000080  // 2 MHz
+#define SYSCTL_RCC_XTAL_2_45MHZ 0x000000C0  // 2.4576 MHz
 #define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100  // 3.579545 MHz
 #define SYSCTL_RCC_XTAL_3_68MHZ 0x00000140  // 3.6864 MHz
 #define SYSCTL_RCC_XTAL_4MHZ    0x00000180  // 4 MHz
@@ -3353,26 +3308,27 @@
 #define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200  // 4.9152 MHz
 #define SYSCTL_RCC_XTAL_5MHZ    0x00000240  // 5 MHz
 #define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280  // 5.12 MHz
-#define SYSCTL_RCC_XTAL_6MHZ    0x000002C0  // 6 MHz (reset value)
+#define SYSCTL_RCC_XTAL_6MHZ    0x000002C0  // 6 MHz
 #define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300  // 6.144 MHz
 #define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340  // 7.3728 MHz
 #define SYSCTL_RCC_XTAL_8MHZ    0x00000380  // 8 MHz
 #define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0  // 8.192 MHz
-#define SYSCTL_RCC_OSCSRC_M     0x00000030  // Oscillator Source.
+#define SYSCTL_RCC_OSCSRC_M     0x00000030  // Oscillator Source
 #define SYSCTL_RCC_OSCSRC_MAIN  0x00000000  // MOSC
 #define SYSCTL_RCC_OSCSRC_INT   0x00000010  // IOSC
 #define SYSCTL_RCC_OSCSRC_INT4  0x00000020  // IOSC/4
 #define SYSCTL_RCC_OSCSRC_30    0x00000030  // 30 kHz
-#define SYSCTL_RCC_IOSCDIS      0x00000002  // Internal Oscillator Disable.
-#define SYSCTL_RCC_MOSCDIS      0x00000001  // Main Oscillator Disable.
+#define SYSCTL_RCC_IOSCDIS      0x00000002  // Internal Oscillator Disable
+#define SYSCTL_RCC_MOSCDIS      0x00000001  // Main Oscillator Disable
+#define SYSCTL_RCC_SYSDIV_S     23
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_PLLCFG register.
 //
 //*****************************************************************************
-#define SYSCTL_PLLCFG_F_M       0x00003FE0  // PLL F Value.
-#define SYSCTL_PLLCFG_R_M       0x0000001F  // PLL R Value.
+#define SYSCTL_PLLCFG_F_M       0x00003FE0  // PLL F Value
+#define SYSCTL_PLLCFG_R_M       0x0000001F  // PLL R Value
 #define SYSCTL_PLLCFG_F_S       5
 #define SYSCTL_PLLCFG_R_S       0
 
@@ -3381,8 +3337,8 @@
 // The following are defines for the bit fields in the SYSCTL_RCC2 register.
 //
 //*****************************************************************************
-#define SYSCTL_RCC2_USERCC2     0x80000000  // Use RCC2.
-#define SYSCTL_RCC2_SYSDIV2_M   0x1F800000  // System Clock Divisor.
+#define SYSCTL_RCC2_USERCC2     0x80000000  // Use RCC2
+#define SYSCTL_RCC2_SYSDIV2_M   0x1F800000  // System Clock Divisor 2
 #define SYSCTL_RCC2_SYSDIV2_2   0x00800000  // System clock /2
 #define SYSCTL_RCC2_SYSDIV2_3   0x01000000  // System clock /3
 #define SYSCTL_RCC2_SYSDIV2_4   0x01800000  // System clock /4
@@ -3446,14 +3402,14 @@
 #define SYSCTL_RCC2_SYSDIV2_62  0x1E800000  // System clock /62
 #define SYSCTL_RCC2_SYSDIV2_63  0x1F000000  // System clock /63
 #define SYSCTL_RCC2_SYSDIV2_64  0x1F800000  // System clock /64
-#define SYSCTL_RCC2_PWRDN2      0x00002000  // Power-Down PLL.
-#define SYSCTL_RCC2_BYPASS2     0x00000800  // Bypass PLL.
-#define SYSCTL_RCC2_OSCSRC2_M   0x00000070  // Oscillator Source.
+#define SYSCTL_RCC2_PWRDN2      0x00002000  // Power-Down PLL 2
+#define SYSCTL_RCC2_BYPASS2     0x00000800  // PLL Bypass 2
+#define SYSCTL_RCC2_OSCSRC2_M   0x00000070  // Oscillator Source 2
 #define SYSCTL_RCC2_OSCSRC2_MO  0x00000000  // MOSC
-#define SYSCTL_RCC2_OSCSRC2_IO  0x00000010  // IOSC
-#define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020  // IOSC/4
+#define SYSCTL_RCC2_OSCSRC2_IO  0x00000010  // PIOSC
+#define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020  // PIOSC/4
 #define SYSCTL_RCC2_OSCSRC2_30  0x00000030  // 30 kHz
-#define SYSCTL_RCC2_OSCSRC2_32  0x00000070  // 32 kHz
+#define SYSCTL_RCC2_OSCSRC2_32  0x00000070  // 32.768 kHz
 #define SYSCTL_RCC2_SYSDIV2_S   23
 
 //*****************************************************************************
@@ -3461,156 +3417,145 @@
 // The following are defines for the bit fields in the SYSCTL_RCGC0 register.
 //
 //*****************************************************************************
-#define SYSCTL_RCGC0_PWM        0x00100000  // PWM Clock Gating Control.
-#define SYSCTL_RCGC0_ADC        0x00010000  // ADC0 Clock Gating Control.
-#define SYSCTL_RCGC0_ADCSPD_M   0x00000300  // ADC Sample Speed.
+#define SYSCTL_RCGC0_PWM        0x00100000  // PWM Clock Gating Control
+#define SYSCTL_RCGC0_ADC        0x00010000  // ADC0 Clock Gating Control
+#define SYSCTL_RCGC0_ADCSPD_M   0x00000300  // ADC Sample Speed
 #define SYSCTL_RCGC0_ADCSPD125K 0x00000000  // 125K samples/second
 #define SYSCTL_RCGC0_ADCSPD250K 0x00000100  // 250K samples/second
 #define SYSCTL_RCGC0_ADCSPD500K 0x00000200  // 500K samples/second
 #define SYSCTL_RCGC0_ADCSPD1M   0x00000300  // 1M samples/second
-#define SYSCTL_RCGC0_HIB        0x00000040  // HIB Clock Gating Control.
-#define SYSCTL_RCGC0_WDT        0x00000008  // WDT Clock Gating Control.
+#define SYSCTL_RCGC0_HIB        0x00000040  // HIB Clock Gating Control
+#define SYSCTL_RCGC0_WDT        0x00000008  // WDT Clock Gating Control
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_RCGC1 register.
 //
 //*****************************************************************************
-#define SYSCTL_RCGC1_COMP1      0x02000000  // Analog Comparator 1 Clock
-                                            // Gating.
-#define SYSCTL_RCGC1_COMP0      0x01000000  // Analog Comparator 0 Clock
-                                            // Gating.
-#define SYSCTL_RCGC1_TIMER3     0x00080000  // Timer 3 Clock Gating Control.
-#define SYSCTL_RCGC1_TIMER2     0x00040000  // Timer 2 Clock Gating Control.
-#define SYSCTL_RCGC1_TIMER1     0x00020000  // Timer 1 Clock Gating Control.
-#define SYSCTL_RCGC1_TIMER0     0x00010000  // Timer 0 Clock Gating Control.
-#define SYSCTL_RCGC1_I2C1       0x00004000  // I2C1 Clock Gating Control.
-#define SYSCTL_RCGC1_I2C0       0x00001000  // I2C0 Clock Gating Control.
-#define SYSCTL_RCGC1_QEI1       0x00000200  // QEI1 Clock Gating Control.
-#define SYSCTL_RCGC1_QEI0       0x00000100  // QEI0 Clock Gating Control.
-#define SYSCTL_RCGC1_SSI0       0x00000010  // SSI0 Clock Gating Control.
-#define SYSCTL_RCGC1_UART2      0x00000004  // UART2 Clock Gating Control.
-#define SYSCTL_RCGC1_UART1      0x00000002  // UART1 Clock Gating Control.
-#define SYSCTL_RCGC1_UART0      0x00000001  // UART0 Clock Gating Control.
+#define SYSCTL_RCGC1_COMP1      0x02000000  // Analog Comparator 1 Clock Gating
+#define SYSCTL_RCGC1_COMP0      0x01000000  // Analog Comparator 0 Clock Gating
+#define SYSCTL_RCGC1_TIMER3     0x00080000  // Timer 3 Clock Gating Control
+#define SYSCTL_RCGC1_TIMER2     0x00040000  // Timer 2 Clock Gating Control
+#define SYSCTL_RCGC1_TIMER1     0x00020000  // Timer 1 Clock Gating Control
+#define SYSCTL_RCGC1_TIMER0     0x00010000  // Timer 0 Clock Gating Control
+#define SYSCTL_RCGC1_I2C1       0x00004000  // I2C1 Clock Gating Control
+#define SYSCTL_RCGC1_I2C0       0x00001000  // I2C0 Clock Gating Control
+#define SYSCTL_RCGC1_QEI1       0x00000200  // QEI1 Clock Gating Control
+#define SYSCTL_RCGC1_QEI0       0x00000100  // QEI0 Clock Gating Control
+#define SYSCTL_RCGC1_SSI0       0x00000010  // SSI0 Clock Gating Control
+#define SYSCTL_RCGC1_UART2      0x00000004  // UART2 Clock Gating Control
+#define SYSCTL_RCGC1_UART1      0x00000002  // UART1 Clock Gating Control
+#define SYSCTL_RCGC1_UART0      0x00000001  // UART0 Clock Gating Control
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_RCGC2 register.
 //
 //*****************************************************************************
-#define SYSCTL_RCGC2_EPHY0      0x40000000  // PHY0 Clock Gating Control.
-#define SYSCTL_RCGC2_EMAC0      0x10000000  // MAC0 Clock Gating Control.
-#define SYSCTL_RCGC2_GPIOG      0x00000040  // Port G Clock Gating Control.
-#define SYSCTL_RCGC2_GPIOF      0x00000020  // Port F Clock Gating Control.
-#define SYSCTL_RCGC2_GPIOE      0x00000010  // Port E Clock Gating Control.
-#define SYSCTL_RCGC2_GPIOD      0x00000008  // Port D Clock Gating Control.
-#define SYSCTL_RCGC2_GPIOC      0x00000004  // Port C Clock Gating Control.
-#define SYSCTL_RCGC2_GPIOB      0x00000002  // Port B Clock Gating Control.
-#define SYSCTL_RCGC2_GPIOA      0x00000001  // Port A Clock Gating Control.
+#define SYSCTL_RCGC2_EPHY0      0x40000000  // PHY0 Clock Gating Control
+#define SYSCTL_RCGC2_EMAC0      0x10000000  // MAC0 Clock Gating Control
+#define SYSCTL_RCGC2_GPIOG      0x00000040  // Port G Clock Gating Control
+#define SYSCTL_RCGC2_GPIOF      0x00000020  // Port F Clock Gating Control
+#define SYSCTL_RCGC2_GPIOE      0x00000010  // Port E Clock Gating Control
+#define SYSCTL_RCGC2_GPIOD      0x00000008  // Port D Clock Gating Control
+#define SYSCTL_RCGC2_GPIOC      0x00000004  // Port C Clock Gating Control
+#define SYSCTL_RCGC2_GPIOB      0x00000002  // Port B Clock Gating Control
+#define SYSCTL_RCGC2_GPIOA      0x00000001  // Port A Clock Gating Control
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_SCGC0 register.
 //
 //*****************************************************************************
-#define SYSCTL_SCGC0_PWM        0x00100000  // PWM Clock Gating Control.
-#define SYSCTL_SCGC0_ADC        0x00010000  // ADC0 Clock Gating Control.
-#define SYSCTL_SCGC0_ADCSPD_M   0x00000300  // ADC Sample Speed.
+#define SYSCTL_SCGC0_PWM        0x00100000  // PWM Clock Gating Control
+#define SYSCTL_SCGC0_ADC        0x00010000  // ADC0 Clock Gating Control
+#define SYSCTL_SCGC0_ADCSPD_M   0x00000300  // ADC Sample Speed
 #define SYSCTL_SCGC0_ADCSPD125K 0x00000000  // 125K samples/second
 #define SYSCTL_SCGC0_ADCSPD250K 0x00000100  // 250K samples/second
 #define SYSCTL_SCGC0_ADCSPD500K 0x00000200  // 500K samples/second
 #define SYSCTL_SCGC0_ADCSPD1M   0x00000300  // 1M samples/second
-#define SYSCTL_SCGC0_HIB        0x00000040  // HIB Clock Gating Control.
-#define SYSCTL_SCGC0_WDT        0x00000008  // WDT Clock Gating Control.
+#define SYSCTL_SCGC0_HIB        0x00000040  // HIB Clock Gating Control
+#define SYSCTL_SCGC0_WDT        0x00000008  // WDT Clock Gating Control
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_SCGC1 register.
 //
 //*****************************************************************************
-#define SYSCTL_SCGC1_COMP1      0x02000000  // Analog Comparator 1 Clock
-                                            // Gating.
-#define SYSCTL_SCGC1_COMP0      0x01000000  // Analog Comparator 0 Clock
-                                            // Gating.
-#define SYSCTL_SCGC1_TIMER3     0x00080000  // Timer 3 Clock Gating Control.
-#define SYSCTL_SCGC1_TIMER2     0x00040000  // Timer 2 Clock Gating Control.
-#define SYSCTL_SCGC1_TIMER1     0x00020000  // Timer 1 Clock Gating Control.
-#define SYSCTL_SCGC1_TIMER0     0x00010000  // Timer 0 Clock Gating Control.
-#define SYSCTL_SCGC1_I2C1       0x00004000  // I2C1 Clock Gating Control.
-#define SYSCTL_SCGC1_I2C0       0x00001000  // I2C0 Clock Gating Control.
-#define SYSCTL_SCGC1_QEI1       0x00000200  // QEI1 Clock Gating Control.
-#define SYSCTL_SCGC1_QEI0       0x00000100  // QEI0 Clock Gating Control.
-#define SYSCTL_SCGC1_SSI0       0x00000010  // SSI0 Clock Gating Control.
-#define SYSCTL_SCGC1_UART2      0x00000004  // UART2 Clock Gating Control.
-#define SYSCTL_SCGC1_UART1      0x00000002  // UART1 Clock Gating Control.
-#define SYSCTL_SCGC1_UART0      0x00000001  // UART0 Clock Gating Control.
+#define SYSCTL_SCGC1_COMP1      0x02000000  // Analog Comparator 1 Clock Gating
+#define SYSCTL_SCGC1_COMP0      0x01000000  // Analog Comparator 0 Clock Gating
+#define SYSCTL_SCGC1_TIMER3     0x00080000  // Timer 3 Clock Gating Control
+#define SYSCTL_SCGC1_TIMER2     0x00040000  // Timer 2 Clock Gating Control
+#define SYSCTL_SCGC1_TIMER1     0x00020000  // Timer 1 Clock Gating Control
+#define SYSCTL_SCGC1_TIMER0     0x00010000  // Timer 0 Clock Gating Control
+#define SYSCTL_SCGC1_I2C1       0x00004000  // I2C1 Clock Gating Control
+#define SYSCTL_SCGC1_I2C0       0x00001000  // I2C0 Clock Gating Control
+#define SYSCTL_SCGC1_QEI1       0x00000200  // QEI1 Clock Gating Control
+#define SYSCTL_SCGC1_QEI0       0x00000100  // QEI0 Clock Gating Control
+#define SYSCTL_SCGC1_SSI0       0x00000010  // SSI0 Clock Gating Control
+#define SYSCTL_SCGC1_UART2      0x00000004  // UART2 Clock Gating Control
+#define SYSCTL_SCGC1_UART1      0x00000002  // UART1 Clock Gating Control
+#define SYSCTL_SCGC1_UART0      0x00000001  // UART0 Clock Gating Control
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_SCGC2 register.
 //
 //*****************************************************************************
-#define SYSCTL_SCGC2_EPHY0      0x40000000  // PHY0 Clock Gating Control.
-#define SYSCTL_SCGC2_EMAC0      0x10000000  // MAC0 Clock Gating Control.
-#define SYSCTL_SCGC2_GPIOG      0x00000040  // Port G Clock Gating Control.
-#define SYSCTL_SCGC2_GPIOF      0x00000020  // Port F Clock Gating Control.
-#define SYSCTL_SCGC2_GPIOE      0x00000010  // Port E Clock Gating Control.
-#define SYSCTL_SCGC2_GPIOD      0x00000008  // Port D Clock Gating Control.
-#define SYSCTL_SCGC2_GPIOC      0x00000004  // Port C Clock Gating Control.
-#define SYSCTL_SCGC2_GPIOB      0x00000002  // Port B Clock Gating Control.
-#define SYSCTL_SCGC2_GPIOA      0x00000001  // Port A Clock Gating Control.
+#define SYSCTL_SCGC2_EPHY0      0x40000000  // PHY0 Clock Gating Control
+#define SYSCTL_SCGC2_EMAC0      0x10000000  // MAC0 Clock Gating Control
+#define SYSCTL_SCGC2_GPIOG      0x00000040  // Port G Clock Gating Control
+#define SYSCTL_SCGC2_GPIOF      0x00000020  // Port F Clock Gating Control
+#define SYSCTL_SCGC2_GPIOE      0x00000010  // Port E Clock Gating Control
+#define SYSCTL_SCGC2_GPIOD      0x00000008  // Port D Clock Gating Control
+#define SYSCTL_SCGC2_GPIOC      0x00000004  // Port C Clock Gating Control
+#define SYSCTL_SCGC2_GPIOB      0x00000002  // Port B Clock Gating Control
+#define SYSCTL_SCGC2_GPIOA      0x00000001  // Port A Clock Gating Control
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_DCGC0 register.
 //
 //*****************************************************************************
-#define SYSCTL_DCGC0_PWM        0x00100000  // PWM Clock Gating Control.
-#define SYSCTL_DCGC0_ADC        0x00010000  // ADC0 Clock Gating Control.
-#define SYSCTL_DCGC0_ADCSPD_M   0x00000300  // ADC Sample Speed.
-#define SYSCTL_DCGC0_ADCSPD125K 0x00000000  // 125K samples/second
-#define SYSCTL_DCGC0_ADCSPD250K 0x00000100  // 250K samples/second
-#define SYSCTL_DCGC0_ADCSPD500K 0x00000200  // 500K samples/second
-#define SYSCTL_DCGC0_ADCSPD1M   0x00000300  // 1M samples/second
-#define SYSCTL_DCGC0_HIB        0x00000040  // HIB Clock Gating Control.
-#define SYSCTL_DCGC0_WDT        0x00000008  // WDT Clock Gating Control.
+#define SYSCTL_DCGC0_PWM        0x00100000  // PWM Clock Gating Control
+#define SYSCTL_DCGC0_ADC        0x00010000  // ADC0 Clock Gating Control
+#define SYSCTL_DCGC0_HIB        0x00000040  // HIB Clock Gating Control
+#define SYSCTL_DCGC0_WDT        0x00000008  // WDT Clock Gating Control
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_DCGC1 register.
 //
 //*****************************************************************************
-#define SYSCTL_DCGC1_COMP1      0x02000000  // Analog Comparator 1 Clock
-                                            // Gating.
-#define SYSCTL_DCGC1_COMP0      0x01000000  // Analog Comparator 0 Clock
-                                            // Gating.
-#define SYSCTL_DCGC1_TIMER3     0x00080000  // Timer 3 Clock Gating Control.
-#define SYSCTL_DCGC1_TIMER2     0x00040000  // Timer 2 Clock Gating Control.
-#define SYSCTL_DCGC1_TIMER1     0x00020000  // Timer 1 Clock Gating Control.
-#define SYSCTL_DCGC1_TIMER0     0x00010000  // Timer 0 Clock Gating Control.
-#define SYSCTL_DCGC1_I2C1       0x00004000  // I2C1 Clock Gating Control.
-#define SYSCTL_DCGC1_I2C0       0x00001000  // I2C0 Clock Gating Control.
-#define SYSCTL_DCGC1_QEI1       0x00000200  // QEI1 Clock Gating Control.
-#define SYSCTL_DCGC1_QEI0       0x00000100  // QEI0 Clock Gating Control.
-#define SYSCTL_DCGC1_SSI0       0x00000010  // SSI0 Clock Gating Control.
-#define SYSCTL_DCGC1_UART2      0x00000004  // UART2 Clock Gating Control.
-#define SYSCTL_DCGC1_UART1      0x00000002  // UART1 Clock Gating Control.
-#define SYSCTL_DCGC1_UART0      0x00000001  // UART0 Clock Gating Control.
+#define SYSCTL_DCGC1_COMP1      0x02000000  // Analog Comparator 1 Clock Gating
+#define SYSCTL_DCGC1_COMP0      0x01000000  // Analog Comparator 0 Clock Gating
+#define SYSCTL_DCGC1_TIMER3     0x00080000  // Timer 3 Clock Gating Control
+#define SYSCTL_DCGC1_TIMER2     0x00040000  // Timer 2 Clock Gating Control
+#define SYSCTL_DCGC1_TIMER1     0x00020000  // Timer 1 Clock Gating Control
+#define SYSCTL_DCGC1_TIMER0     0x00010000  // Timer 0 Clock Gating Control
+#define SYSCTL_DCGC1_I2C1       0x00004000  // I2C1 Clock Gating Control
+#define SYSCTL_DCGC1_I2C0       0x00001000  // I2C0 Clock Gating Control
+#define SYSCTL_DCGC1_QEI1       0x00000200  // QEI1 Clock Gating Control
+#define SYSCTL_DCGC1_QEI0       0x00000100  // QEI0 Clock Gating Control
+#define SYSCTL_DCGC1_SSI0       0x00000010  // SSI0 Clock Gating Control
+#define SYSCTL_DCGC1_UART2      0x00000004  // UART2 Clock Gating Control
+#define SYSCTL_DCGC1_UART1      0x00000002  // UART1 Clock Gating Control
+#define SYSCTL_DCGC1_UART0      0x00000001  // UART0 Clock Gating Control
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_DCGC2 register.
 //
 //*****************************************************************************
-#define SYSCTL_DCGC2_EPHY0      0x40000000  // PHY0 Clock Gating Control.
-#define SYSCTL_DCGC2_EMAC0      0x10000000  // MAC0 Clock Gating Control.
-#define SYSCTL_DCGC2_GPIOG      0x00000040  // Port G Clock Gating Control.
-#define SYSCTL_DCGC2_GPIOF      0x00000020  // Port F Clock Gating Control.
-#define SYSCTL_DCGC2_GPIOE      0x00000010  // Port E Clock Gating Control.
-#define SYSCTL_DCGC2_GPIOD      0x00000008  // Port D Clock Gating Control.
-#define SYSCTL_DCGC2_GPIOC      0x00000004  // Port C Clock Gating Control.
-#define SYSCTL_DCGC2_GPIOB      0x00000002  // Port B Clock Gating Control.
-#define SYSCTL_DCGC2_GPIOA      0x00000001  // Port A Clock Gating Control.
+#define SYSCTL_DCGC2_EPHY0      0x40000000  // PHY0 Clock Gating Control
+#define SYSCTL_DCGC2_EMAC0      0x10000000  // MAC0 Clock Gating Control
+#define SYSCTL_DCGC2_GPIOG      0x00000040  // Port G Clock Gating Control
+#define SYSCTL_DCGC2_GPIOF      0x00000020  // Port F Clock Gating Control
+#define SYSCTL_DCGC2_GPIOE      0x00000010  // Port E Clock Gating Control
+#define SYSCTL_DCGC2_GPIOD      0x00000008  // Port D Clock Gating Control
+#define SYSCTL_DCGC2_GPIOC      0x00000004  // Port C Clock Gating Control
+#define SYSCTL_DCGC2_GPIOB      0x00000002  // Port B Clock Gating Control
+#define SYSCTL_DCGC2_GPIOA      0x00000001  // Port A Clock Gating Control
 
 //*****************************************************************************
 //
@@ -3618,12 +3563,76 @@
 // register.
 //
 //*****************************************************************************
-#define SYSCTL_DSLPCLKCFG_D_M   0x1F800000  // Divider Field Override.
-#define SYSCTL_DSLPCLKCFG_O_M   0x00000070  // Clock Source.
+#define SYSCTL_DSLPCLKCFG_D_M   0x1F800000  // Divider Field Override
+#define SYSCTL_DSLPCLKCFG_D_1   0x00000000  // System clock /1
+#define SYSCTL_DSLPCLKCFG_D_2   0x00800000  // System clock /2
+#define SYSCTL_DSLPCLKCFG_D_3   0x01000000  // System clock /3
+#define SYSCTL_DSLPCLKCFG_D_4   0x01800000  // System clock /4
+#define SYSCTL_DSLPCLKCFG_D_5   0x02000000  // System clock /5
+#define SYSCTL_DSLPCLKCFG_D_6   0x02800000  // System clock /6
+#define SYSCTL_DSLPCLKCFG_D_7   0x03000000  // System clock /7
+#define SYSCTL_DSLPCLKCFG_D_8   0x03800000  // System clock /8
+#define SYSCTL_DSLPCLKCFG_D_9   0x04000000  // System clock /9
+#define SYSCTL_DSLPCLKCFG_D_10  0x04800000  // System clock /10
+#define SYSCTL_DSLPCLKCFG_D_11  0x05000000  // System clock /11
+#define SYSCTL_DSLPCLKCFG_D_12  0x05800000  // System clock /12
+#define SYSCTL_DSLPCLKCFG_D_13  0x06000000  // System clock /13
+#define SYSCTL_DSLPCLKCFG_D_14  0x06800000  // System clock /14
+#define SYSCTL_DSLPCLKCFG_D_15  0x07000000  // System clock /15
+#define SYSCTL_DSLPCLKCFG_D_16  0x07800000  // System clock /16
+#define SYSCTL_DSLPCLKCFG_D_17  0x08000000  // System clock /17
+#define SYSCTL_DSLPCLKCFG_D_18  0x08800000  // System clock /18
+#define SYSCTL_DSLPCLKCFG_D_19  0x09000000  // System clock /19
+#define SYSCTL_DSLPCLKCFG_D_20  0x09800000  // System clock /20
+#define SYSCTL_DSLPCLKCFG_D_21  0x0A000000  // System clock /21
+#define SYSCTL_DSLPCLKCFG_D_22  0x0A800000  // System clock /22
+#define SYSCTL_DSLPCLKCFG_D_23  0x0B000000  // System clock /23
+#define SYSCTL_DSLPCLKCFG_D_24  0x0B800000  // System clock /24
+#define SYSCTL_DSLPCLKCFG_D_25  0x0C000000  // System clock /25
+#define SYSCTL_DSLPCLKCFG_D_26  0x0C800000  // System clock /26
+#define SYSCTL_DSLPCLKCFG_D_27  0x0D000000  // System clock /27
+#define SYSCTL_DSLPCLKCFG_D_28  0x0D800000  // System clock /28
+#define SYSCTL_DSLPCLKCFG_D_29  0x0E000000  // System clock /29
+#define SYSCTL_DSLPCLKCFG_D_30  0x0E800000  // System clock /30
+#define SYSCTL_DSLPCLKCFG_D_31  0x0F000000  // System clock /31
+#define SYSCTL_DSLPCLKCFG_D_32  0x0F800000  // System clock /32
+#define SYSCTL_DSLPCLKCFG_D_33  0x10000000  // System clock /33
+#define SYSCTL_DSLPCLKCFG_D_34  0x10800000  // System clock /34
+#define SYSCTL_DSLPCLKCFG_D_35  0x11000000  // System clock /35
+#define SYSCTL_DSLPCLKCFG_D_36  0x11800000  // System clock /36
+#define SYSCTL_DSLPCLKCFG_D_37  0x12000000  // System clock /37
+#define SYSCTL_DSLPCLKCFG_D_38  0x12800000  // System clock /38
+#define SYSCTL_DSLPCLKCFG_D_39  0x13000000  // System clock /39
+#define SYSCTL_DSLPCLKCFG_D_40  0x13800000  // System clock /40
+#define SYSCTL_DSLPCLKCFG_D_41  0x14000000  // System clock /41
+#define SYSCTL_DSLPCLKCFG_D_42  0x14800000  // System clock /42
+#define SYSCTL_DSLPCLKCFG_D_43  0x15000000  // System clock /43
+#define SYSCTL_DSLPCLKCFG_D_44  0x15800000  // System clock /44
+#define SYSCTL_DSLPCLKCFG_D_45  0x16000000  // System clock /45
+#define SYSCTL_DSLPCLKCFG_D_46  0x16800000  // System clock /46
+#define SYSCTL_DSLPCLKCFG_D_47  0x17000000  // System clock /47
+#define SYSCTL_DSLPCLKCFG_D_48  0x17800000  // System clock /48
+#define SYSCTL_DSLPCLKCFG_D_49  0x18000000  // System clock /49
+#define SYSCTL_DSLPCLKCFG_D_50  0x18800000  // System clock /50
+#define SYSCTL_DSLPCLKCFG_D_51  0x19000000  // System clock /51
+#define SYSCTL_DSLPCLKCFG_D_52  0x19800000  // System clock /52
+#define SYSCTL_DSLPCLKCFG_D_53  0x1A000000  // System clock /53
+#define SYSCTL_DSLPCLKCFG_D_54  0x1A800000  // System clock /54
+#define SYSCTL_DSLPCLKCFG_D_55  0x1B000000  // System clock /55
+#define SYSCTL_DSLPCLKCFG_D_56  0x1B800000  // System clock /56
+#define SYSCTL_DSLPCLKCFG_D_57  0x1C000000  // System clock /57
+#define SYSCTL_DSLPCLKCFG_D_58  0x1C800000  // System clock /58
+#define SYSCTL_DSLPCLKCFG_D_59  0x1D000000  // System clock /59
+#define SYSCTL_DSLPCLKCFG_D_60  0x1D800000  // System clock /60
+#define SYSCTL_DSLPCLKCFG_D_61  0x1E000000  // System clock /61
+#define SYSCTL_DSLPCLKCFG_D_62  0x1E800000  // System clock /62
+#define SYSCTL_DSLPCLKCFG_D_63  0x1F000000  // System clock /63
+#define SYSCTL_DSLPCLKCFG_D_64  0x1F800000  // System clock /64
+#define SYSCTL_DSLPCLKCFG_O_M   0x00000070  // Clock Source
 #define SYSCTL_DSLPCLKCFG_O_IGN 0x00000000  // MOSC
-#define SYSCTL_DSLPCLKCFG_O_IO  0x00000010  // IOSC
+#define SYSCTL_DSLPCLKCFG_O_IO  0x00000010  // PIOSC
 #define SYSCTL_DSLPCLKCFG_O_30  0x00000030  // 30 kHz
-#define SYSCTL_DSLPCLKCFG_O_32  0x00000070  // 32 kHz
+#define SYSCTL_DSLPCLKCFG_O_32  0x00000070  // 32.768 kHz
 #define SYSCTL_DSLPCLKCFG_D_S   23
 
 //*****************************************************************************
@@ -3639,17 +3648,17 @@
 // The following are defines for the bit fields in the NVIC_ST_CTRL register.
 //
 //*****************************************************************************
-#define NVIC_ST_CTRL_COUNT      0x00010000  // Count flag
+#define NVIC_ST_CTRL_COUNT      0x00010000  // Count Flag
 #define NVIC_ST_CTRL_CLK_SRC    0x00000004  // Clock Source
-#define NVIC_ST_CTRL_INTEN      0x00000002  // Interrupt enable
-#define NVIC_ST_CTRL_ENABLE     0x00000001  // Counter mode
+#define NVIC_ST_CTRL_INTEN      0x00000002  // Interrupt Enable
+#define NVIC_ST_CTRL_ENABLE     0x00000001  // Enable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_ST_RELOAD register.
 //
 //*****************************************************************************
-#define NVIC_ST_RELOAD_M        0x00FFFFFF  // Counter load value
+#define NVIC_ST_RELOAD_M        0x00FFFFFF  // Reload Value
 #define NVIC_ST_RELOAD_S        0
 
 //*****************************************************************************
@@ -3658,7 +3667,7 @@
 // register.
 //
 //*****************************************************************************
-#define NVIC_ST_CURRENT_M       0x00FFFFFF  // Counter current value
+#define NVIC_ST_CURRENT_M       0x00FFFFFF  // Current Value
 #define NVIC_ST_CURRENT_S       0
 
 //*****************************************************************************
@@ -3676,539 +3685,541 @@
 // The following are defines for the bit fields in the NVIC_EN0 register.
 //
 //*****************************************************************************
-#define NVIC_EN0_INT31          0x80000000  // Interrupt 31 enable
-#define NVIC_EN0_INT30          0x40000000  // Interrupt 30 enable
-#define NVIC_EN0_INT29          0x20000000  // Interrupt 29 enable
-#define NVIC_EN0_INT28          0x10000000  // Interrupt 28 enable
-#define NVIC_EN0_INT27          0x08000000  // Interrupt 27 enable
-#define NVIC_EN0_INT26          0x04000000  // Interrupt 26 enable
-#define NVIC_EN0_INT25          0x02000000  // Interrupt 25 enable
-#define NVIC_EN0_INT24          0x01000000  // Interrupt 24 enable
-#define NVIC_EN0_INT23          0x00800000  // Interrupt 23 enable
-#define NVIC_EN0_INT22          0x00400000  // Interrupt 22 enable
-#define NVIC_EN0_INT21          0x00200000  // Interrupt 21 enable
-#define NVIC_EN0_INT20          0x00100000  // Interrupt 20 enable
-#define NVIC_EN0_INT19          0x00080000  // Interrupt 19 enable
-#define NVIC_EN0_INT18          0x00040000  // Interrupt 18 enable
-#define NVIC_EN0_INT17          0x00020000  // Interrupt 17 enable
-#define NVIC_EN0_INT16          0x00010000  // Interrupt 16 enable
-#define NVIC_EN0_INT15          0x00008000  // Interrupt 15 enable
-#define NVIC_EN0_INT14          0x00004000  // Interrupt 14 enable
-#define NVIC_EN0_INT13          0x00002000  // Interrupt 13 enable
-#define NVIC_EN0_INT12          0x00001000  // Interrupt 12 enable
-#define NVIC_EN0_INT11          0x00000800  // Interrupt 11 enable
-#define NVIC_EN0_INT10          0x00000400  // Interrupt 10 enable
-#define NVIC_EN0_INT9           0x00000200  // Interrupt 9 enable
-#define NVIC_EN0_INT8           0x00000100  // Interrupt 8 enable
-#define NVIC_EN0_INT7           0x00000080  // Interrupt 7 enable
-#define NVIC_EN0_INT6           0x00000040  // Interrupt 6 enable
-#define NVIC_EN0_INT5           0x00000020  // Interrupt 5 enable
-#define NVIC_EN0_INT4           0x00000010  // Interrupt 4 enable
-#define NVIC_EN0_INT3           0x00000008  // Interrupt 3 enable
-#define NVIC_EN0_INT2           0x00000004  // Interrupt 2 enable
-#define NVIC_EN0_INT1           0x00000002  // Interrupt 1 enable
+#define NVIC_EN0_INT_M          0xFFFFFFFF  // Interrupt Enable
 #define NVIC_EN0_INT0           0x00000001  // Interrupt 0 enable
+#define NVIC_EN0_INT1           0x00000002  // Interrupt 1 enable
+#define NVIC_EN0_INT2           0x00000004  // Interrupt 2 enable
+#define NVIC_EN0_INT3           0x00000008  // Interrupt 3 enable
+#define NVIC_EN0_INT4           0x00000010  // Interrupt 4 enable
+#define NVIC_EN0_INT5           0x00000020  // Interrupt 5 enable
+#define NVIC_EN0_INT6           0x00000040  // Interrupt 6 enable
+#define NVIC_EN0_INT7           0x00000080  // Interrupt 7 enable
+#define NVIC_EN0_INT8           0x00000100  // Interrupt 8 enable
+#define NVIC_EN0_INT9           0x00000200  // Interrupt 9 enable
+#define NVIC_EN0_INT10          0x00000400  // Interrupt 10 enable
+#define NVIC_EN0_INT11          0x00000800  // Interrupt 11 enable
+#define NVIC_EN0_INT12          0x00001000  // Interrupt 12 enable
+#define NVIC_EN0_INT13          0x00002000  // Interrupt 13 enable
+#define NVIC_EN0_INT14          0x00004000  // Interrupt 14 enable
+#define NVIC_EN0_INT15          0x00008000  // Interrupt 15 enable
+#define NVIC_EN0_INT16          0x00010000  // Interrupt 16 enable
+#define NVIC_EN0_INT17          0x00020000  // Interrupt 17 enable
+#define NVIC_EN0_INT18          0x00040000  // Interrupt 18 enable
+#define NVIC_EN0_INT19          0x00080000  // Interrupt 19 enable
+#define NVIC_EN0_INT20          0x00100000  // Interrupt 20 enable
+#define NVIC_EN0_INT21          0x00200000  // Interrupt 21 enable
+#define NVIC_EN0_INT22          0x00400000  // Interrupt 22 enable
+#define NVIC_EN0_INT23          0x00800000  // Interrupt 23 enable
+#define NVIC_EN0_INT24          0x01000000  // Interrupt 24 enable
+#define NVIC_EN0_INT25          0x02000000  // Interrupt 25 enable
+#define NVIC_EN0_INT26          0x04000000  // Interrupt 26 enable
+#define NVIC_EN0_INT27          0x08000000  // Interrupt 27 enable
+#define NVIC_EN0_INT28          0x10000000  // Interrupt 28 enable
+#define NVIC_EN0_INT29          0x20000000  // Interrupt 29 enable
+#define NVIC_EN0_INT30          0x40000000  // Interrupt 30 enable
+#define NVIC_EN0_INT31          0x80000000  // Interrupt 31 enable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_EN1 register.
 //
 //*****************************************************************************
-#define NVIC_EN1_INT59          0x08000000  // Interrupt 59 enable
-#define NVIC_EN1_INT58          0x04000000  // Interrupt 58 enable
-#define NVIC_EN1_INT57          0x02000000  // Interrupt 57 enable
-#define NVIC_EN1_INT56          0x01000000  // Interrupt 56 enable
-#define NVIC_EN1_INT55          0x00800000  // Interrupt 55 enable
-#define NVIC_EN1_INT54          0x00400000  // Interrupt 54 enable
-#define NVIC_EN1_INT53          0x00200000  // Interrupt 53 enable
-#define NVIC_EN1_INT52          0x00100000  // Interrupt 52 enable
-#define NVIC_EN1_INT51          0x00080000  // Interrupt 51 enable
-#define NVIC_EN1_INT50          0x00040000  // Interrupt 50 enable
-#define NVIC_EN1_INT49          0x00020000  // Interrupt 49 enable
-#define NVIC_EN1_INT48          0x00010000  // Interrupt 48 enable
-#define NVIC_EN1_INT47          0x00008000  // Interrupt 47 enable
-#define NVIC_EN1_INT46          0x00004000  // Interrupt 46 enable
-#define NVIC_EN1_INT45          0x00002000  // Interrupt 45 enable
-#define NVIC_EN1_INT44          0x00001000  // Interrupt 44 enable
-#define NVIC_EN1_INT43          0x00000800  // Interrupt 43 enable
-#define NVIC_EN1_INT42          0x00000400  // Interrupt 42 enable
-#define NVIC_EN1_INT41          0x00000200  // Interrupt 41 enable
-#define NVIC_EN1_INT40          0x00000100  // Interrupt 40 enable
-#define NVIC_EN1_INT39          0x00000080  // Interrupt 39 enable
-#define NVIC_EN1_INT38          0x00000040  // Interrupt 38 enable
-#define NVIC_EN1_INT37          0x00000020  // Interrupt 37 enable
-#define NVIC_EN1_INT36          0x00000010  // Interrupt 36 enable
-#define NVIC_EN1_INT35          0x00000008  // Interrupt 35 enable
-#define NVIC_EN1_INT34          0x00000004  // Interrupt 34 enable
-#define NVIC_EN1_INT33          0x00000002  // Interrupt 33 enable
+#define NVIC_EN1_INT_M          0x00000FFF  // Interrupt Enable
 #define NVIC_EN1_INT32          0x00000001  // Interrupt 32 enable
+#define NVIC_EN1_INT33          0x00000002  // Interrupt 33 enable
+#define NVIC_EN1_INT34          0x00000004  // Interrupt 34 enable
+#define NVIC_EN1_INT35          0x00000008  // Interrupt 35 enable
+#define NVIC_EN1_INT36          0x00000010  // Interrupt 36 enable
+#define NVIC_EN1_INT37          0x00000020  // Interrupt 37 enable
+#define NVIC_EN1_INT38          0x00000040  // Interrupt 38 enable
+#define NVIC_EN1_INT39          0x00000080  // Interrupt 39 enable
+#define NVIC_EN1_INT40          0x00000100  // Interrupt 40 enable
+#define NVIC_EN1_INT41          0x00000200  // Interrupt 41 enable
+#define NVIC_EN1_INT42          0x00000400  // Interrupt 42 enable
+#define NVIC_EN1_INT43          0x00000800  // Interrupt 43 enable
+#define NVIC_EN1_INT44          0x00001000  // Interrupt 44 enable
+#define NVIC_EN1_INT45          0x00002000  // Interrupt 45 enable
+#define NVIC_EN1_INT46          0x00004000  // Interrupt 46 enable
+#define NVIC_EN1_INT47          0x00008000  // Interrupt 47 enable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_DIS0 register.
 //
 //*****************************************************************************
-#define NVIC_DIS0_INT31         0x80000000  // Interrupt 31 disable
-#define NVIC_DIS0_INT30         0x40000000  // Interrupt 30 disable
-#define NVIC_DIS0_INT29         0x20000000  // Interrupt 29 disable
-#define NVIC_DIS0_INT28         0x10000000  // Interrupt 28 disable
-#define NVIC_DIS0_INT27         0x08000000  // Interrupt 27 disable
-#define NVIC_DIS0_INT26         0x04000000  // Interrupt 26 disable
-#define NVIC_DIS0_INT25         0x02000000  // Interrupt 25 disable
-#define NVIC_DIS0_INT24         0x01000000  // Interrupt 24 disable
-#define NVIC_DIS0_INT23         0x00800000  // Interrupt 23 disable
-#define NVIC_DIS0_INT22         0x00400000  // Interrupt 22 disable
-#define NVIC_DIS0_INT21         0x00200000  // Interrupt 21 disable
-#define NVIC_DIS0_INT20         0x00100000  // Interrupt 20 disable
-#define NVIC_DIS0_INT19         0x00080000  // Interrupt 19 disable
-#define NVIC_DIS0_INT18         0x00040000  // Interrupt 18 disable
-#define NVIC_DIS0_INT17         0x00020000  // Interrupt 17 disable
-#define NVIC_DIS0_INT16         0x00010000  // Interrupt 16 disable
-#define NVIC_DIS0_INT15         0x00008000  // Interrupt 15 disable
-#define NVIC_DIS0_INT14         0x00004000  // Interrupt 14 disable
-#define NVIC_DIS0_INT13         0x00002000  // Interrupt 13 disable
-#define NVIC_DIS0_INT12         0x00001000  // Interrupt 12 disable
-#define NVIC_DIS0_INT11         0x00000800  // Interrupt 11 disable
-#define NVIC_DIS0_INT10         0x00000400  // Interrupt 10 disable
-#define NVIC_DIS0_INT9          0x00000200  // Interrupt 9 disable
-#define NVIC_DIS0_INT8          0x00000100  // Interrupt 8 disable
-#define NVIC_DIS0_INT7          0x00000080  // Interrupt 7 disable
-#define NVIC_DIS0_INT6          0x00000040  // Interrupt 6 disable
-#define NVIC_DIS0_INT5          0x00000020  // Interrupt 5 disable
-#define NVIC_DIS0_INT4          0x00000010  // Interrupt 4 disable
-#define NVIC_DIS0_INT3          0x00000008  // Interrupt 3 disable
-#define NVIC_DIS0_INT2          0x00000004  // Interrupt 2 disable
-#define NVIC_DIS0_INT1          0x00000002  // Interrupt 1 disable
+#define NVIC_DIS0_INT_M         0xFFFFFFFF  // Interrupt Disable
 #define NVIC_DIS0_INT0          0x00000001  // Interrupt 0 disable
+#define NVIC_DIS0_INT1          0x00000002  // Interrupt 1 disable
+#define NVIC_DIS0_INT2          0x00000004  // Interrupt 2 disable
+#define NVIC_DIS0_INT3          0x00000008  // Interrupt 3 disable
+#define NVIC_DIS0_INT4          0x00000010  // Interrupt 4 disable
+#define NVIC_DIS0_INT5          0x00000020  // Interrupt 5 disable
+#define NVIC_DIS0_INT6          0x00000040  // Interrupt 6 disable
+#define NVIC_DIS0_INT7          0x00000080  // Interrupt 7 disable
+#define NVIC_DIS0_INT8          0x00000100  // Interrupt 8 disable
+#define NVIC_DIS0_INT9          0x00000200  // Interrupt 9 disable
+#define NVIC_DIS0_INT10         0x00000400  // Interrupt 10 disable
+#define NVIC_DIS0_INT11         0x00000800  // Interrupt 11 disable
+#define NVIC_DIS0_INT12         0x00001000  // Interrupt 12 disable
+#define NVIC_DIS0_INT13         0x00002000  // Interrupt 13 disable
+#define NVIC_DIS0_INT14         0x00004000  // Interrupt 14 disable
+#define NVIC_DIS0_INT15         0x00008000  // Interrupt 15 disable
+#define NVIC_DIS0_INT16         0x00010000  // Interrupt 16 disable
+#define NVIC_DIS0_INT17         0x00020000  // Interrupt 17 disable
+#define NVIC_DIS0_INT18         0x00040000  // Interrupt 18 disable
+#define NVIC_DIS0_INT19         0x00080000  // Interrupt 19 disable
+#define NVIC_DIS0_INT20         0x00100000  // Interrupt 20 disable
+#define NVIC_DIS0_INT21         0x00200000  // Interrupt 21 disable
+#define NVIC_DIS0_INT22         0x00400000  // Interrupt 22 disable
+#define NVIC_DIS0_INT23         0x00800000  // Interrupt 23 disable
+#define NVIC_DIS0_INT24         0x01000000  // Interrupt 24 disable
+#define NVIC_DIS0_INT25         0x02000000  // Interrupt 25 disable
+#define NVIC_DIS0_INT26         0x04000000  // Interrupt 26 disable
+#define NVIC_DIS0_INT27         0x08000000  // Interrupt 27 disable
+#define NVIC_DIS0_INT28         0x10000000  // Interrupt 28 disable
+#define NVIC_DIS0_INT29         0x20000000  // Interrupt 29 disable
+#define NVIC_DIS0_INT30         0x40000000  // Interrupt 30 disable
+#define NVIC_DIS0_INT31         0x80000000  // Interrupt 31 disable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_DIS1 register.
 //
 //*****************************************************************************
-#define NVIC_DIS1_INT59         0x08000000  // Interrupt 59 disable
-#define NVIC_DIS1_INT58         0x04000000  // Interrupt 58 disable
-#define NVIC_DIS1_INT57         0x02000000  // Interrupt 57 disable
-#define NVIC_DIS1_INT56         0x01000000  // Interrupt 56 disable
-#define NVIC_DIS1_INT55         0x00800000  // Interrupt 55 disable
-#define NVIC_DIS1_INT54         0x00400000  // Interrupt 54 disable
-#define NVIC_DIS1_INT53         0x00200000  // Interrupt 53 disable
-#define NVIC_DIS1_INT52         0x00100000  // Interrupt 52 disable
-#define NVIC_DIS1_INT51         0x00080000  // Interrupt 51 disable
-#define NVIC_DIS1_INT50         0x00040000  // Interrupt 50 disable
-#define NVIC_DIS1_INT49         0x00020000  // Interrupt 49 disable
-#define NVIC_DIS1_INT48         0x00010000  // Interrupt 48 disable
-#define NVIC_DIS1_INT47         0x00008000  // Interrupt 47 disable
-#define NVIC_DIS1_INT46         0x00004000  // Interrupt 46 disable
-#define NVIC_DIS1_INT45         0x00002000  // Interrupt 45 disable
-#define NVIC_DIS1_INT44         0x00001000  // Interrupt 44 disable
-#define NVIC_DIS1_INT43         0x00000800  // Interrupt 43 disable
-#define NVIC_DIS1_INT42         0x00000400  // Interrupt 42 disable
-#define NVIC_DIS1_INT41         0x00000200  // Interrupt 41 disable
-#define NVIC_DIS1_INT40         0x00000100  // Interrupt 40 disable
-#define NVIC_DIS1_INT39         0x00000080  // Interrupt 39 disable
-#define NVIC_DIS1_INT38         0x00000040  // Interrupt 38 disable
-#define NVIC_DIS1_INT37         0x00000020  // Interrupt 37 disable
-#define NVIC_DIS1_INT36         0x00000010  // Interrupt 36 disable
-#define NVIC_DIS1_INT35         0x00000008  // Interrupt 35 disable
-#define NVIC_DIS1_INT34         0x00000004  // Interrupt 34 disable
-#define NVIC_DIS1_INT33         0x00000002  // Interrupt 33 disable
+#define NVIC_DIS1_INT_M         0x00000FFF  // Interrupt Disable
 #define NVIC_DIS1_INT32         0x00000001  // Interrupt 32 disable
+#define NVIC_DIS1_INT33         0x00000002  // Interrupt 33 disable
+#define NVIC_DIS1_INT34         0x00000004  // Interrupt 34 disable
+#define NVIC_DIS1_INT35         0x00000008  // Interrupt 35 disable
+#define NVIC_DIS1_INT36         0x00000010  // Interrupt 36 disable
+#define NVIC_DIS1_INT37         0x00000020  // Interrupt 37 disable
+#define NVIC_DIS1_INT38         0x00000040  // Interrupt 38 disable
+#define NVIC_DIS1_INT39         0x00000080  // Interrupt 39 disable
+#define NVIC_DIS1_INT40         0x00000100  // Interrupt 40 disable
+#define NVIC_DIS1_INT41         0x00000200  // Interrupt 41 disable
+#define NVIC_DIS1_INT42         0x00000400  // Interrupt 42 disable
+#define NVIC_DIS1_INT43         0x00000800  // Interrupt 43 disable
+#define NVIC_DIS1_INT44         0x00001000  // Interrupt 44 disable
+#define NVIC_DIS1_INT45         0x00002000  // Interrupt 45 disable
+#define NVIC_DIS1_INT46         0x00004000  // Interrupt 46 disable
+#define NVIC_DIS1_INT47         0x00008000  // Interrupt 47 disable
+#define NVIC_DIS1_INT48         0x00010000  // Interrupt 48 disable
+#define NVIC_DIS1_INT49         0x00020000  // Interrupt 49 disable
+#define NVIC_DIS1_INT50         0x00040000  // Interrupt 50 disable
+#define NVIC_DIS1_INT51         0x00080000  // Interrupt 51 disable
+#define NVIC_DIS1_INT52         0x00100000  // Interrupt 52 disable
+#define NVIC_DIS1_INT53         0x00200000  // Interrupt 53 disable
+#define NVIC_DIS1_INT54         0x00400000  // Interrupt 54 disable
+#define NVIC_DIS1_INT55         0x00800000  // Interrupt 55 disable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_PEND0 register.
 //
 //*****************************************************************************
-#define NVIC_PEND0_INT31        0x80000000  // Interrupt 31 pend
-#define NVIC_PEND0_INT30        0x40000000  // Interrupt 30 pend
-#define NVIC_PEND0_INT29        0x20000000  // Interrupt 29 pend
-#define NVIC_PEND0_INT28        0x10000000  // Interrupt 28 pend
-#define NVIC_PEND0_INT27        0x08000000  // Interrupt 27 pend
-#define NVIC_PEND0_INT26        0x04000000  // Interrupt 26 pend
-#define NVIC_PEND0_INT25        0x02000000  // Interrupt 25 pend
-#define NVIC_PEND0_INT24        0x01000000  // Interrupt 24 pend
-#define NVIC_PEND0_INT23        0x00800000  // Interrupt 23 pend
-#define NVIC_PEND0_INT22        0x00400000  // Interrupt 22 pend
-#define NVIC_PEND0_INT21        0x00200000  // Interrupt 21 pend
-#define NVIC_PEND0_INT20        0x00100000  // Interrupt 20 pend
-#define NVIC_PEND0_INT19        0x00080000  // Interrupt 19 pend
-#define NVIC_PEND0_INT18        0x00040000  // Interrupt 18 pend
-#define NVIC_PEND0_INT17        0x00020000  // Interrupt 17 pend
-#define NVIC_PEND0_INT16        0x00010000  // Interrupt 16 pend
-#define NVIC_PEND0_INT15        0x00008000  // Interrupt 15 pend
-#define NVIC_PEND0_INT14        0x00004000  // Interrupt 14 pend
-#define NVIC_PEND0_INT13        0x00002000  // Interrupt 13 pend
-#define NVIC_PEND0_INT12        0x00001000  // Interrupt 12 pend
-#define NVIC_PEND0_INT11        0x00000800  // Interrupt 11 pend
-#define NVIC_PEND0_INT10        0x00000400  // Interrupt 10 pend
-#define NVIC_PEND0_INT9         0x00000200  // Interrupt 9 pend
-#define NVIC_PEND0_INT8         0x00000100  // Interrupt 8 pend
-#define NVIC_PEND0_INT7         0x00000080  // Interrupt 7 pend
-#define NVIC_PEND0_INT6         0x00000040  // Interrupt 6 pend
-#define NVIC_PEND0_INT5         0x00000020  // Interrupt 5 pend
-#define NVIC_PEND0_INT4         0x00000010  // Interrupt 4 pend
-#define NVIC_PEND0_INT3         0x00000008  // Interrupt 3 pend
-#define NVIC_PEND0_INT2         0x00000004  // Interrupt 2 pend
-#define NVIC_PEND0_INT1         0x00000002  // Interrupt 1 pend
+#define NVIC_PEND0_INT_M        0xFFFFFFFF  // Interrupt Set Pending
 #define NVIC_PEND0_INT0         0x00000001  // Interrupt 0 pend
+#define NVIC_PEND0_INT1         0x00000002  // Interrupt 1 pend
+#define NVIC_PEND0_INT2         0x00000004  // Interrupt 2 pend
+#define NVIC_PEND0_INT3         0x00000008  // Interrupt 3 pend
+#define NVIC_PEND0_INT4         0x00000010  // Interrupt 4 pend
+#define NVIC_PEND0_INT5         0x00000020  // Interrupt 5 pend
+#define NVIC_PEND0_INT6         0x00000040  // Interrupt 6 pend
+#define NVIC_PEND0_INT7         0x00000080  // Interrupt 7 pend
+#define NVIC_PEND0_INT8         0x00000100  // Interrupt 8 pend
+#define NVIC_PEND0_INT9         0x00000200  // Interrupt 9 pend
+#define NVIC_PEND0_INT10        0x00000400  // Interrupt 10 pend
+#define NVIC_PEND0_INT11        0x00000800  // Interrupt 11 pend
+#define NVIC_PEND0_INT12        0x00001000  // Interrupt 12 pend
+#define NVIC_PEND0_INT13        0x00002000  // Interrupt 13 pend
+#define NVIC_PEND0_INT14        0x00004000  // Interrupt 14 pend
+#define NVIC_PEND0_INT15        0x00008000  // Interrupt 15 pend
+#define NVIC_PEND0_INT16        0x00010000  // Interrupt 16 pend
+#define NVIC_PEND0_INT17        0x00020000  // Interrupt 17 pend
+#define NVIC_PEND0_INT18        0x00040000  // Interrupt 18 pend
+#define NVIC_PEND0_INT19        0x00080000  // Interrupt 19 pend
+#define NVIC_PEND0_INT20        0x00100000  // Interrupt 20 pend
+#define NVIC_PEND0_INT21        0x00200000  // Interrupt 21 pend
+#define NVIC_PEND0_INT22        0x00400000  // Interrupt 22 pend
+#define NVIC_PEND0_INT23        0x00800000  // Interrupt 23 pend
+#define NVIC_PEND0_INT24        0x01000000  // Interrupt 24 pend
+#define NVIC_PEND0_INT25        0x02000000  // Interrupt 25 pend
+#define NVIC_PEND0_INT26        0x04000000  // Interrupt 26 pend
+#define NVIC_PEND0_INT27        0x08000000  // Interrupt 27 pend
+#define NVIC_PEND0_INT28        0x10000000  // Interrupt 28 pend
+#define NVIC_PEND0_INT29        0x20000000  // Interrupt 29 pend
+#define NVIC_PEND0_INT30        0x40000000  // Interrupt 30 pend
+#define NVIC_PEND0_INT31        0x80000000  // Interrupt 31 pend
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_PEND1 register.
 //
 //*****************************************************************************
-#define NVIC_PEND1_INT59        0x08000000  // Interrupt 59 pend
-#define NVIC_PEND1_INT58        0x04000000  // Interrupt 58 pend
-#define NVIC_PEND1_INT57        0x02000000  // Interrupt 57 pend
-#define NVIC_PEND1_INT56        0x01000000  // Interrupt 56 pend
-#define NVIC_PEND1_INT55        0x00800000  // Interrupt 55 pend
-#define NVIC_PEND1_INT54        0x00400000  // Interrupt 54 pend
-#define NVIC_PEND1_INT53        0x00200000  // Interrupt 53 pend
-#define NVIC_PEND1_INT52        0x00100000  // Interrupt 52 pend
-#define NVIC_PEND1_INT51        0x00080000  // Interrupt 51 pend
-#define NVIC_PEND1_INT50        0x00040000  // Interrupt 50 pend
-#define NVIC_PEND1_INT49        0x00020000  // Interrupt 49 pend
-#define NVIC_PEND1_INT48        0x00010000  // Interrupt 48 pend
-#define NVIC_PEND1_INT47        0x00008000  // Interrupt 47 pend
-#define NVIC_PEND1_INT46        0x00004000  // Interrupt 46 pend
-#define NVIC_PEND1_INT45        0x00002000  // Interrupt 45 pend
-#define NVIC_PEND1_INT44        0x00001000  // Interrupt 44 pend
-#define NVIC_PEND1_INT43        0x00000800  // Interrupt 43 pend
-#define NVIC_PEND1_INT42        0x00000400  // Interrupt 42 pend
-#define NVIC_PEND1_INT41        0x00000200  // Interrupt 41 pend
-#define NVIC_PEND1_INT40        0x00000100  // Interrupt 40 pend
-#define NVIC_PEND1_INT39        0x00000080  // Interrupt 39 pend
-#define NVIC_PEND1_INT38        0x00000040  // Interrupt 38 pend
-#define NVIC_PEND1_INT37        0x00000020  // Interrupt 37 pend
-#define NVIC_PEND1_INT36        0x00000010  // Interrupt 36 pend
-#define NVIC_PEND1_INT35        0x00000008  // Interrupt 35 pend
-#define NVIC_PEND1_INT34        0x00000004  // Interrupt 34 pend
-#define NVIC_PEND1_INT33        0x00000002  // Interrupt 33 pend
+#define NVIC_PEND1_INT_M        0x00000FFF  // Interrupt Set Pending
 #define NVIC_PEND1_INT32        0x00000001  // Interrupt 32 pend
+#define NVIC_PEND1_INT33        0x00000002  // Interrupt 33 pend
+#define NVIC_PEND1_INT34        0x00000004  // Interrupt 34 pend
+#define NVIC_PEND1_INT35        0x00000008  // Interrupt 35 pend
+#define NVIC_PEND1_INT36        0x00000010  // Interrupt 36 pend
+#define NVIC_PEND1_INT37        0x00000020  // Interrupt 37 pend
+#define NVIC_PEND1_INT38        0x00000040  // Interrupt 38 pend
+#define NVIC_PEND1_INT39        0x00000080  // Interrupt 39 pend
+#define NVIC_PEND1_INT40        0x00000100  // Interrupt 40 pend
+#define NVIC_PEND1_INT41        0x00000200  // Interrupt 41 pend
+#define NVIC_PEND1_INT42        0x00000400  // Interrupt 42 pend
+#define NVIC_PEND1_INT43        0x00000800  // Interrupt 43 pend
+#define NVIC_PEND1_INT44        0x00001000  // Interrupt 44 pend
+#define NVIC_PEND1_INT45        0x00002000  // Interrupt 45 pend
+#define NVIC_PEND1_INT46        0x00004000  // Interrupt 46 pend
+#define NVIC_PEND1_INT47        0x00008000  // Interrupt 47 pend
+#define NVIC_PEND1_INT48        0x00010000  // Interrupt 48 pend
+#define NVIC_PEND1_INT49        0x00020000  // Interrupt 49 pend
+#define NVIC_PEND1_INT50        0x00040000  // Interrupt 50 pend
+#define NVIC_PEND1_INT51        0x00080000  // Interrupt 51 pend
+#define NVIC_PEND1_INT52        0x00100000  // Interrupt 52 pend
+#define NVIC_PEND1_INT53        0x00200000  // Interrupt 53 pend
+#define NVIC_PEND1_INT54        0x00400000  // Interrupt 54 pend
+#define NVIC_PEND1_INT55        0x00800000  // Interrupt 55 pend
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_UNPEND0 register.
 //
 //*****************************************************************************
-#define NVIC_UNPEND0_INT31      0x80000000  // Interrupt 31 unpend
-#define NVIC_UNPEND0_INT30      0x40000000  // Interrupt 30 unpend
-#define NVIC_UNPEND0_INT29      0x20000000  // Interrupt 29 unpend
-#define NVIC_UNPEND0_INT28      0x10000000  // Interrupt 28 unpend
-#define NVIC_UNPEND0_INT27      0x08000000  // Interrupt 27 unpend
-#define NVIC_UNPEND0_INT26      0x04000000  // Interrupt 26 unpend
-#define NVIC_UNPEND0_INT25      0x02000000  // Interrupt 25 unpend
-#define NVIC_UNPEND0_INT24      0x01000000  // Interrupt 24 unpend
-#define NVIC_UNPEND0_INT23      0x00800000  // Interrupt 23 unpend
-#define NVIC_UNPEND0_INT22      0x00400000  // Interrupt 22 unpend
-#define NVIC_UNPEND0_INT21      0x00200000  // Interrupt 21 unpend
-#define NVIC_UNPEND0_INT20      0x00100000  // Interrupt 20 unpend
-#define NVIC_UNPEND0_INT19      0x00080000  // Interrupt 19 unpend
-#define NVIC_UNPEND0_INT18      0x00040000  // Interrupt 18 unpend
-#define NVIC_UNPEND0_INT17      0x00020000  // Interrupt 17 unpend
-#define NVIC_UNPEND0_INT16      0x00010000  // Interrupt 16 unpend
-#define NVIC_UNPEND0_INT15      0x00008000  // Interrupt 15 unpend
-#define NVIC_UNPEND0_INT14      0x00004000  // Interrupt 14 unpend
-#define NVIC_UNPEND0_INT13      0x00002000  // Interrupt 13 unpend
-#define NVIC_UNPEND0_INT12      0x00001000  // Interrupt 12 unpend
-#define NVIC_UNPEND0_INT11      0x00000800  // Interrupt 11 unpend
-#define NVIC_UNPEND0_INT10      0x00000400  // Interrupt 10 unpend
-#define NVIC_UNPEND0_INT9       0x00000200  // Interrupt 9 unpend
-#define NVIC_UNPEND0_INT8       0x00000100  // Interrupt 8 unpend
-#define NVIC_UNPEND0_INT7       0x00000080  // Interrupt 7 unpend
-#define NVIC_UNPEND0_INT6       0x00000040  // Interrupt 6 unpend
-#define NVIC_UNPEND0_INT5       0x00000020  // Interrupt 5 unpend
-#define NVIC_UNPEND0_INT4       0x00000010  // Interrupt 4 unpend
-#define NVIC_UNPEND0_INT3       0x00000008  // Interrupt 3 unpend
-#define NVIC_UNPEND0_INT2       0x00000004  // Interrupt 2 unpend
-#define NVIC_UNPEND0_INT1       0x00000002  // Interrupt 1 unpend
+#define NVIC_UNPEND0_INT_M      0xFFFFFFFF  // Interrupt Clear Pending
 #define NVIC_UNPEND0_INT0       0x00000001  // Interrupt 0 unpend
+#define NVIC_UNPEND0_INT1       0x00000002  // Interrupt 1 unpend
+#define NVIC_UNPEND0_INT2       0x00000004  // Interrupt 2 unpend
+#define NVIC_UNPEND0_INT3       0x00000008  // Interrupt 3 unpend
+#define NVIC_UNPEND0_INT4       0x00000010  // Interrupt 4 unpend
+#define NVIC_UNPEND0_INT5       0x00000020  // Interrupt 5 unpend
+#define NVIC_UNPEND0_INT6       0x00000040  // Interrupt 6 unpend
+#define NVIC_UNPEND0_INT7       0x00000080  // Interrupt 7 unpend
+#define NVIC_UNPEND0_INT8       0x00000100  // Interrupt 8 unpend
+#define NVIC_UNPEND0_INT9       0x00000200  // Interrupt 9 unpend
+#define NVIC_UNPEND0_INT10      0x00000400  // Interrupt 10 unpend
+#define NVIC_UNPEND0_INT11      0x00000800  // Interrupt 11 unpend
+#define NVIC_UNPEND0_INT12      0x00001000  // Interrupt 12 unpend
+#define NVIC_UNPEND0_INT13      0x00002000  // Interrupt 13 unpend
+#define NVIC_UNPEND0_INT14      0x00004000  // Interrupt 14 unpend
+#define NVIC_UNPEND0_INT15      0x00008000  // Interrupt 15 unpend
+#define NVIC_UNPEND0_INT16      0x00010000  // Interrupt 16 unpend
+#define NVIC_UNPEND0_INT17      0x00020000  // Interrupt 17 unpend
+#define NVIC_UNPEND0_INT18      0x00040000  // Interrupt 18 unpend
+#define NVIC_UNPEND0_INT19      0x00080000  // Interrupt 19 unpend
+#define NVIC_UNPEND0_INT20      0x00100000  // Interrupt 20 unpend
+#define NVIC_UNPEND0_INT21      0x00200000  // Interrupt 21 unpend
+#define NVIC_UNPEND0_INT22      0x00400000  // Interrupt 22 unpend
+#define NVIC_UNPEND0_INT23      0x00800000  // Interrupt 23 unpend
+#define NVIC_UNPEND0_INT24      0x01000000  // Interrupt 24 unpend
+#define NVIC_UNPEND0_INT25      0x02000000  // Interrupt 25 unpend
+#define NVIC_UNPEND0_INT26      0x04000000  // Interrupt 26 unpend
+#define NVIC_UNPEND0_INT27      0x08000000  // Interrupt 27 unpend
+#define NVIC_UNPEND0_INT28      0x10000000  // Interrupt 28 unpend
+#define NVIC_UNPEND0_INT29      0x20000000  // Interrupt 29 unpend
+#define NVIC_UNPEND0_INT30      0x40000000  // Interrupt 30 unpend
+#define NVIC_UNPEND0_INT31      0x80000000  // Interrupt 31 unpend
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_UNPEND1 register.
 //
 //*****************************************************************************
-#define NVIC_UNPEND1_INT59      0x08000000  // Interrupt 59 unpend
-#define NVIC_UNPEND1_INT58      0x04000000  // Interrupt 58 unpend
-#define NVIC_UNPEND1_INT57      0x02000000  // Interrupt 57 unpend
-#define NVIC_UNPEND1_INT56      0x01000000  // Interrupt 56 unpend
-#define NVIC_UNPEND1_INT55      0x00800000  // Interrupt 55 unpend
-#define NVIC_UNPEND1_INT54      0x00400000  // Interrupt 54 unpend
-#define NVIC_UNPEND1_INT53      0x00200000  // Interrupt 53 unpend
-#define NVIC_UNPEND1_INT52      0x00100000  // Interrupt 52 unpend
-#define NVIC_UNPEND1_INT51      0x00080000  // Interrupt 51 unpend
-#define NVIC_UNPEND1_INT50      0x00040000  // Interrupt 50 unpend
-#define NVIC_UNPEND1_INT49      0x00020000  // Interrupt 49 unpend
-#define NVIC_UNPEND1_INT48      0x00010000  // Interrupt 48 unpend
-#define NVIC_UNPEND1_INT47      0x00008000  // Interrupt 47 unpend
-#define NVIC_UNPEND1_INT46      0x00004000  // Interrupt 46 unpend
-#define NVIC_UNPEND1_INT45      0x00002000  // Interrupt 45 unpend
-#define NVIC_UNPEND1_INT44      0x00001000  // Interrupt 44 unpend
-#define NVIC_UNPEND1_INT43      0x00000800  // Interrupt 43 unpend
-#define NVIC_UNPEND1_INT42      0x00000400  // Interrupt 42 unpend
-#define NVIC_UNPEND1_INT41      0x00000200  // Interrupt 41 unpend
-#define NVIC_UNPEND1_INT40      0x00000100  // Interrupt 40 unpend
-#define NVIC_UNPEND1_INT39      0x00000080  // Interrupt 39 unpend
-#define NVIC_UNPEND1_INT38      0x00000040  // Interrupt 38 unpend
-#define NVIC_UNPEND1_INT37      0x00000020  // Interrupt 37 unpend
-#define NVIC_UNPEND1_INT36      0x00000010  // Interrupt 36 unpend
-#define NVIC_UNPEND1_INT35      0x00000008  // Interrupt 35 unpend
-#define NVIC_UNPEND1_INT34      0x00000004  // Interrupt 34 unpend
-#define NVIC_UNPEND1_INT33      0x00000002  // Interrupt 33 unpend
+#define NVIC_UNPEND1_INT_M      0x00000FFF  // Interrupt Clear Pending
 #define NVIC_UNPEND1_INT32      0x00000001  // Interrupt 32 unpend
+#define NVIC_UNPEND1_INT33      0x00000002  // Interrupt 33 unpend
+#define NVIC_UNPEND1_INT34      0x00000004  // Interrupt 34 unpend
+#define NVIC_UNPEND1_INT35      0x00000008  // Interrupt 35 unpend
+#define NVIC_UNPEND1_INT36      0x00000010  // Interrupt 36 unpend
+#define NVIC_UNPEND1_INT37      0x00000020  // Interrupt 37 unpend
+#define NVIC_UNPEND1_INT38      0x00000040  // Interrupt 38 unpend
+#define NVIC_UNPEND1_INT39      0x00000080  // Interrupt 39 unpend
+#define NVIC_UNPEND1_INT40      0x00000100  // Interrupt 40 unpend
+#define NVIC_UNPEND1_INT41      0x00000200  // Interrupt 41 unpend
+#define NVIC_UNPEND1_INT42      0x00000400  // Interrupt 42 unpend
+#define NVIC_UNPEND1_INT43      0x00000800  // Interrupt 43 unpend
+#define NVIC_UNPEND1_INT44      0x00001000  // Interrupt 44 unpend
+#define NVIC_UNPEND1_INT45      0x00002000  // Interrupt 45 unpend
+#define NVIC_UNPEND1_INT46      0x00004000  // Interrupt 46 unpend
+#define NVIC_UNPEND1_INT47      0x00008000  // Interrupt 47 unpend
+#define NVIC_UNPEND1_INT48      0x00010000  // Interrupt 48 unpend
+#define NVIC_UNPEND1_INT49      0x00020000  // Interrupt 49 unpend
+#define NVIC_UNPEND1_INT50      0x00040000  // Interrupt 50 unpend
+#define NVIC_UNPEND1_INT51      0x00080000  // Interrupt 51 unpend
+#define NVIC_UNPEND1_INT52      0x00100000  // Interrupt 52 unpend
+#define NVIC_UNPEND1_INT53      0x00200000  // Interrupt 53 unpend
+#define NVIC_UNPEND1_INT54      0x00400000  // Interrupt 54 unpend
+#define NVIC_UNPEND1_INT55      0x00800000  // Interrupt 55 unpend
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_ACTIVE0 register.
 //
 //*****************************************************************************
-#define NVIC_ACTIVE0_INT31      0x80000000  // Interrupt 31 active
-#define NVIC_ACTIVE0_INT30      0x40000000  // Interrupt 30 active
-#define NVIC_ACTIVE0_INT29      0x20000000  // Interrupt 29 active
-#define NVIC_ACTIVE0_INT28      0x10000000  // Interrupt 28 active
-#define NVIC_ACTIVE0_INT27      0x08000000  // Interrupt 27 active
-#define NVIC_ACTIVE0_INT26      0x04000000  // Interrupt 26 active
-#define NVIC_ACTIVE0_INT25      0x02000000  // Interrupt 25 active
-#define NVIC_ACTIVE0_INT24      0x01000000  // Interrupt 24 active
-#define NVIC_ACTIVE0_INT23      0x00800000  // Interrupt 23 active
-#define NVIC_ACTIVE0_INT22      0x00400000  // Interrupt 22 active
-#define NVIC_ACTIVE0_INT21      0x00200000  // Interrupt 21 active
-#define NVIC_ACTIVE0_INT20      0x00100000  // Interrupt 20 active
-#define NVIC_ACTIVE0_INT19      0x00080000  // Interrupt 19 active
-#define NVIC_ACTIVE0_INT18      0x00040000  // Interrupt 18 active
-#define NVIC_ACTIVE0_INT17      0x00020000  // Interrupt 17 active
-#define NVIC_ACTIVE0_INT16      0x00010000  // Interrupt 16 active
-#define NVIC_ACTIVE0_INT15      0x00008000  // Interrupt 15 active
-#define NVIC_ACTIVE0_INT14      0x00004000  // Interrupt 14 active
-#define NVIC_ACTIVE0_INT13      0x00002000  // Interrupt 13 active
-#define NVIC_ACTIVE0_INT12      0x00001000  // Interrupt 12 active
-#define NVIC_ACTIVE0_INT11      0x00000800  // Interrupt 11 active
-#define NVIC_ACTIVE0_INT10      0x00000400  // Interrupt 10 active
-#define NVIC_ACTIVE0_INT9       0x00000200  // Interrupt 9 active
-#define NVIC_ACTIVE0_INT8       0x00000100  // Interrupt 8 active
-#define NVIC_ACTIVE0_INT7       0x00000080  // Interrupt 7 active
-#define NVIC_ACTIVE0_INT6       0x00000040  // Interrupt 6 active
-#define NVIC_ACTIVE0_INT5       0x00000020  // Interrupt 5 active
-#define NVIC_ACTIVE0_INT4       0x00000010  // Interrupt 4 active
-#define NVIC_ACTIVE0_INT3       0x00000008  // Interrupt 3 active
-#define NVIC_ACTIVE0_INT2       0x00000004  // Interrupt 2 active
-#define NVIC_ACTIVE0_INT1       0x00000002  // Interrupt 1 active
+#define NVIC_ACTIVE0_INT_M      0xFFFFFFFF  // Interrupt Active
 #define NVIC_ACTIVE0_INT0       0x00000001  // Interrupt 0 active
+#define NVIC_ACTIVE0_INT1       0x00000002  // Interrupt 1 active
+#define NVIC_ACTIVE0_INT2       0x00000004  // Interrupt 2 active
+#define NVIC_ACTIVE0_INT3       0x00000008  // Interrupt 3 active
+#define NVIC_ACTIVE0_INT4       0x00000010  // Interrupt 4 active
+#define NVIC_ACTIVE0_INT5       0x00000020  // Interrupt 5 active
+#define NVIC_ACTIVE0_INT6       0x00000040  // Interrupt 6 active
+#define NVIC_ACTIVE0_INT7       0x00000080  // Interrupt 7 active
+#define NVIC_ACTIVE0_INT8       0x00000100  // Interrupt 8 active
+#define NVIC_ACTIVE0_INT9       0x00000200  // Interrupt 9 active
+#define NVIC_ACTIVE0_INT10      0x00000400  // Interrupt 10 active
+#define NVIC_ACTIVE0_INT11      0x00000800  // Interrupt 11 active
+#define NVIC_ACTIVE0_INT12      0x00001000  // Interrupt 12 active
+#define NVIC_ACTIVE0_INT13      0x00002000  // Interrupt 13 active
+#define NVIC_ACTIVE0_INT14      0x00004000  // Interrupt 14 active
+#define NVIC_ACTIVE0_INT15      0x00008000  // Interrupt 15 active
+#define NVIC_ACTIVE0_INT16      0x00010000  // Interrupt 16 active
+#define NVIC_ACTIVE0_INT17      0x00020000  // Interrupt 17 active
+#define NVIC_ACTIVE0_INT18      0x00040000  // Interrupt 18 active
+#define NVIC_ACTIVE0_INT19      0x00080000  // Interrupt 19 active
+#define NVIC_ACTIVE0_INT20      0x00100000  // Interrupt 20 active
+#define NVIC_ACTIVE0_INT21      0x00200000  // Interrupt 21 active
+#define NVIC_ACTIVE0_INT22      0x00400000  // Interrupt 22 active
+#define NVIC_ACTIVE0_INT23      0x00800000  // Interrupt 23 active
+#define NVIC_ACTIVE0_INT24      0x01000000  // Interrupt 24 active
+#define NVIC_ACTIVE0_INT25      0x02000000  // Interrupt 25 active
+#define NVIC_ACTIVE0_INT26      0x04000000  // Interrupt 26 active
+#define NVIC_ACTIVE0_INT27      0x08000000  // Interrupt 27 active
+#define NVIC_ACTIVE0_INT28      0x10000000  // Interrupt 28 active
+#define NVIC_ACTIVE0_INT29      0x20000000  // Interrupt 29 active
+#define NVIC_ACTIVE0_INT30      0x40000000  // Interrupt 30 active
+#define NVIC_ACTIVE0_INT31      0x80000000  // Interrupt 31 active
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_ACTIVE1 register.
 //
 //*****************************************************************************
-#define NVIC_ACTIVE1_INT59      0x08000000  // Interrupt 59 active
-#define NVIC_ACTIVE1_INT58      0x04000000  // Interrupt 58 active
-#define NVIC_ACTIVE1_INT57      0x02000000  // Interrupt 57 active
-#define NVIC_ACTIVE1_INT56      0x01000000  // Interrupt 56 active
-#define NVIC_ACTIVE1_INT55      0x00800000  // Interrupt 55 active
-#define NVIC_ACTIVE1_INT54      0x00400000  // Interrupt 54 active
-#define NVIC_ACTIVE1_INT53      0x00200000  // Interrupt 53 active
-#define NVIC_ACTIVE1_INT52      0x00100000  // Interrupt 52 active
-#define NVIC_ACTIVE1_INT51      0x00080000  // Interrupt 51 active
-#define NVIC_ACTIVE1_INT50      0x00040000  // Interrupt 50 active
-#define NVIC_ACTIVE1_INT49      0x00020000  // Interrupt 49 active
-#define NVIC_ACTIVE1_INT48      0x00010000  // Interrupt 48 active
-#define NVIC_ACTIVE1_INT47      0x00008000  // Interrupt 47 active
-#define NVIC_ACTIVE1_INT46      0x00004000  // Interrupt 46 active
-#define NVIC_ACTIVE1_INT45      0x00002000  // Interrupt 45 active
-#define NVIC_ACTIVE1_INT44      0x00001000  // Interrupt 44 active
-#define NVIC_ACTIVE1_INT43      0x00000800  // Interrupt 43 active
-#define NVIC_ACTIVE1_INT42      0x00000400  // Interrupt 42 active
-#define NVIC_ACTIVE1_INT41      0x00000200  // Interrupt 41 active
-#define NVIC_ACTIVE1_INT40      0x00000100  // Interrupt 40 active
-#define NVIC_ACTIVE1_INT39      0x00000080  // Interrupt 39 active
-#define NVIC_ACTIVE1_INT38      0x00000040  // Interrupt 38 active
-#define NVIC_ACTIVE1_INT37      0x00000020  // Interrupt 37 active
-#define NVIC_ACTIVE1_INT36      0x00000010  // Interrupt 36 active
-#define NVIC_ACTIVE1_INT35      0x00000008  // Interrupt 35 active
-#define NVIC_ACTIVE1_INT34      0x00000004  // Interrupt 34 active
-#define NVIC_ACTIVE1_INT33      0x00000002  // Interrupt 33 active
+#define NVIC_ACTIVE1_INT_M      0x00000FFF  // Interrupt Active
 #define NVIC_ACTIVE1_INT32      0x00000001  // Interrupt 32 active
+#define NVIC_ACTIVE1_INT33      0x00000002  // Interrupt 33 active
+#define NVIC_ACTIVE1_INT34      0x00000004  // Interrupt 34 active
+#define NVIC_ACTIVE1_INT35      0x00000008  // Interrupt 35 active
+#define NVIC_ACTIVE1_INT36      0x00000010  // Interrupt 36 active
+#define NVIC_ACTIVE1_INT37      0x00000020  // Interrupt 37 active
+#define NVIC_ACTIVE1_INT38      0x00000040  // Interrupt 38 active
+#define NVIC_ACTIVE1_INT39      0x00000080  // Interrupt 39 active
+#define NVIC_ACTIVE1_INT40      0x00000100  // Interrupt 40 active
+#define NVIC_ACTIVE1_INT41      0x00000200  // Interrupt 41 active
+#define NVIC_ACTIVE1_INT42      0x00000400  // Interrupt 42 active
+#define NVIC_ACTIVE1_INT43      0x00000800  // Interrupt 43 active
+#define NVIC_ACTIVE1_INT44      0x00001000  // Interrupt 44 active
+#define NVIC_ACTIVE1_INT45      0x00002000  // Interrupt 45 active
+#define NVIC_ACTIVE1_INT46      0x00004000  // Interrupt 46 active
+#define NVIC_ACTIVE1_INT47      0x00008000  // Interrupt 47 active
+#define NVIC_ACTIVE1_INT48      0x00010000  // Interrupt 48 active
+#define NVIC_ACTIVE1_INT49      0x00020000  // Interrupt 49 active
+#define NVIC_ACTIVE1_INT50      0x00040000  // Interrupt 50 active
+#define NVIC_ACTIVE1_INT51      0x00080000  // Interrupt 51 active
+#define NVIC_ACTIVE1_INT52      0x00100000  // Interrupt 52 active
+#define NVIC_ACTIVE1_INT53      0x00200000  // Interrupt 53 active
+#define NVIC_ACTIVE1_INT54      0x00400000  // Interrupt 54 active
+#define NVIC_ACTIVE1_INT55      0x00800000  // Interrupt 55 active
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_PRI0 register.
 //
 //*****************************************************************************
-#define NVIC_PRI0_INT3_M        0xFF000000  // Interrupt 3 priority mask
-#define NVIC_PRI0_INT2_M        0x00FF0000  // Interrupt 2 priority mask
-#define NVIC_PRI0_INT1_M        0x0000FF00  // Interrupt 1 priority mask
-#define NVIC_PRI0_INT0_M        0x000000FF  // Interrupt 0 priority mask
-#define NVIC_PRI0_INT3_S        24
-#define NVIC_PRI0_INT2_S        16
-#define NVIC_PRI0_INT1_S        8
-#define NVIC_PRI0_INT0_S        0
+#define NVIC_PRI0_INT3_M        0xE0000000  // Interrupt 3 Priority Mask
+#define NVIC_PRI0_INT2_M        0x00E00000  // Interrupt 2 Priority Mask
+#define NVIC_PRI0_INT1_M        0x0000E000  // Interrupt 1 Priority Mask
+#define NVIC_PRI0_INT0_M        0x000000E0  // Interrupt 0 Priority Mask
+#define NVIC_PRI0_INT3_S        29
+#define NVIC_PRI0_INT2_S        21
+#define NVIC_PRI0_INT1_S        13
+#define NVIC_PRI0_INT0_S        5
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_PRI1 register.
 //
 //*****************************************************************************
-#define NVIC_PRI1_INT7_M        0xFF000000  // Interrupt 7 priority mask
-#define NVIC_PRI1_INT6_M        0x00FF0000  // Interrupt 6 priority mask
-#define NVIC_PRI1_INT5_M        0x0000FF00  // Interrupt 5 priority mask
-#define NVIC_PRI1_INT4_M        0x000000FF  // Interrupt 4 priority mask
-#define NVIC_PRI1_INT7_S        24
-#define NVIC_PRI1_INT6_S        16
-#define NVIC_PRI1_INT5_S        8
-#define NVIC_PRI1_INT4_S        0
+#define NVIC_PRI1_INT7_M        0xE0000000  // Interrupt 7 Priority Mask
+#define NVIC_PRI1_INT6_M        0x00E00000  // Interrupt 6 Priority Mask
+#define NVIC_PRI1_INT5_M        0x0000E000  // Interrupt 5 Priority Mask
+#define NVIC_PRI1_INT4_M        0x000000E0  // Interrupt 4 Priority Mask
+#define NVIC_PRI1_INT7_S        29
+#define NVIC_PRI1_INT6_S        21
+#define NVIC_PRI1_INT5_S        13
+#define NVIC_PRI1_INT4_S        5
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_PRI2 register.
 //
 //*****************************************************************************
-#define NVIC_PRI2_INT11_M       0xFF000000  // Interrupt 11 priority mask
-#define NVIC_PRI2_INT10_M       0x00FF0000  // Interrupt 10 priority mask
-#define NVIC_PRI2_INT9_M        0x0000FF00  // Interrupt 9 priority mask
-#define NVIC_PRI2_INT8_M        0x000000FF  // Interrupt 8 priority mask
-#define NVIC_PRI2_INT11_S       24
-#define NVIC_PRI2_INT10_S       16
-#define NVIC_PRI2_INT9_S        8
-#define NVIC_PRI2_INT8_S        0
+#define NVIC_PRI2_INT11_M       0xE0000000  // Interrupt 11 Priority Mask
+#define NVIC_PRI2_INT10_M       0x00E00000  // Interrupt 10 Priority Mask
+#define NVIC_PRI2_INT9_M        0x0000E000  // Interrupt 9 Priority Mask
+#define NVIC_PRI2_INT8_M        0x000000E0  // Interrupt 8 Priority Mask
+#define NVIC_PRI2_INT11_S       29
+#define NVIC_PRI2_INT10_S       21
+#define NVIC_PRI2_INT9_S        13
+#define NVIC_PRI2_INT8_S        5
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_PRI3 register.
 //
 //*****************************************************************************
-#define NVIC_PRI3_INT15_M       0xFF000000  // Interrupt 15 priority mask
-#define NVIC_PRI3_INT14_M       0x00FF0000  // Interrupt 14 priority mask
-#define NVIC_PRI3_INT13_M       0x0000FF00  // Interrupt 13 priority mask
-#define NVIC_PRI3_INT12_M       0x000000FF  // Interrupt 12 priority mask
-#define NVIC_PRI3_INT15_S       24
-#define NVIC_PRI3_INT14_S       16
-#define NVIC_PRI3_INT13_S       8
-#define NVIC_PRI3_INT12_S       0
+#define NVIC_PRI3_INT15_M       0xE0000000  // Interrupt 15 Priority Mask
+#define NVIC_PRI3_INT14_M       0x00E00000  // Interrupt 14 Priority Mask
+#define NVIC_PRI3_INT13_M       0x0000E000  // Interrupt 13 Priority Mask
+#define NVIC_PRI3_INT12_M       0x000000E0  // Interrupt 12 Priority Mask
+#define NVIC_PRI3_INT15_S       29
+#define NVIC_PRI3_INT14_S       21
+#define NVIC_PRI3_INT13_S       13
+#define NVIC_PRI3_INT12_S       5
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_PRI4 register.
 //
 //*****************************************************************************
-#define NVIC_PRI4_INT19_M       0xFF000000  // Interrupt 19 priority mask
-#define NVIC_PRI4_INT18_M       0x00FF0000  // Interrupt 18 priority mask
-#define NVIC_PRI4_INT17_M       0x0000FF00  // Interrupt 17 priority mask
-#define NVIC_PRI4_INT16_M       0x000000FF  // Interrupt 16 priority mask
-#define NVIC_PRI4_INT19_S       24
-#define NVIC_PRI4_INT18_S       16
-#define NVIC_PRI4_INT17_S       8
-#define NVIC_PRI4_INT16_S       0
+#define NVIC_PRI4_INT19_M       0xE0000000  // Interrupt 19 Priority Mask
+#define NVIC_PRI4_INT18_M       0x00E00000  // Interrupt 18 Priority Mask
+#define NVIC_PRI4_INT17_M       0x0000E000  // Interrupt 17 Priority Mask
+#define NVIC_PRI4_INT16_M       0x000000E0  // Interrupt 16 Priority Mask
+#define NVIC_PRI4_INT19_S       29
+#define NVIC_PRI4_INT18_S       21
+#define NVIC_PRI4_INT17_S       13
+#define NVIC_PRI4_INT16_S       5
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_PRI5 register.
 //
 //*****************************************************************************
-#define NVIC_PRI5_INT23_M       0xFF000000  // Interrupt 23 priority mask
-#define NVIC_PRI5_INT22_M       0x00FF0000  // Interrupt 22 priority mask
-#define NVIC_PRI5_INT21_M       0x0000FF00  // Interrupt 21 priority mask
-#define NVIC_PRI5_INT20_M       0x000000FF  // Interrupt 20 priority mask
-#define NVIC_PRI5_INT23_S       24
-#define NVIC_PRI5_INT22_S       16
-#define NVIC_PRI5_INT21_S       8
-#define NVIC_PRI5_INT20_S       0
+#define NVIC_PRI5_INT23_M       0xE0000000  // Interrupt 23 Priority Mask
+#define NVIC_PRI5_INT22_M       0x00E00000  // Interrupt 22 Priority Mask
+#define NVIC_PRI5_INT21_M       0x0000E000  // Interrupt 21 Priority Mask
+#define NVIC_PRI5_INT20_M       0x000000E0  // Interrupt 20 Priority Mask
+#define NVIC_PRI5_INT23_S       29
+#define NVIC_PRI5_INT22_S       21
+#define NVIC_PRI5_INT21_S       13
+#define NVIC_PRI5_INT20_S       5
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_PRI6 register.
 //
 //*****************************************************************************
-#define NVIC_PRI6_INT27_M       0xFF000000  // Interrupt 27 priority mask
-#define NVIC_PRI6_INT26_M       0x00FF0000  // Interrupt 26 priority mask
-#define NVIC_PRI6_INT25_M       0x0000FF00  // Interrupt 25 priority mask
-#define NVIC_PRI6_INT24_M       0x000000FF  // Interrupt 24 priority mask
-#define NVIC_PRI6_INT27_S       24
-#define NVIC_PRI6_INT26_S       16
-#define NVIC_PRI6_INT25_S       8
-#define NVIC_PRI6_INT24_S       0
+#define NVIC_PRI6_INT27_M       0xE0000000  // Interrupt 27 Priority Mask
+#define NVIC_PRI6_INT26_M       0x00E00000  // Interrupt 26 Priority Mask
+#define NVIC_PRI6_INT25_M       0x0000E000  // Interrupt 25 Priority Mask
+#define NVIC_PRI6_INT24_M       0x000000E0  // Interrupt 24 Priority Mask
+#define NVIC_PRI6_INT27_S       29
+#define NVIC_PRI6_INT26_S       21
+#define NVIC_PRI6_INT25_S       13
+#define NVIC_PRI6_INT24_S       5
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_PRI7 register.
 //
 //*****************************************************************************
-#define NVIC_PRI7_INT31_M       0xFF000000  // Interrupt 31 priority mask
-#define NVIC_PRI7_INT30_M       0x00FF0000  // Interrupt 30 priority mask
-#define NVIC_PRI7_INT29_M       0x0000FF00  // Interrupt 29 priority mask
-#define NVIC_PRI7_INT28_M       0x000000FF  // Interrupt 28 priority mask
-#define NVIC_PRI7_INT31_S       24
-#define NVIC_PRI7_INT30_S       16
-#define NVIC_PRI7_INT29_S       8
-#define NVIC_PRI7_INT28_S       0
+#define NVIC_PRI7_INT31_M       0xE0000000  // Interrupt 31 Priority Mask
+#define NVIC_PRI7_INT30_M       0x00E00000  // Interrupt 30 Priority Mask
+#define NVIC_PRI7_INT29_M       0x0000E000  // Interrupt 29 Priority Mask
+#define NVIC_PRI7_INT28_M       0x000000E0  // Interrupt 28 Priority Mask
+#define NVIC_PRI7_INT31_S       29
+#define NVIC_PRI7_INT30_S       21
+#define NVIC_PRI7_INT29_S       13
+#define NVIC_PRI7_INT28_S       5
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_PRI8 register.
 //
 //*****************************************************************************
-#define NVIC_PRI8_INT35_M       0xFF000000  // Interrupt 35 priority mask
-#define NVIC_PRI8_INT34_M       0x00FF0000  // Interrupt 34 priority mask
-#define NVIC_PRI8_INT33_M       0x0000FF00  // Interrupt 33 priority mask
-#define NVIC_PRI8_INT32_M       0x000000FF  // Interrupt 32 priority mask
-#define NVIC_PRI8_INT35_S       24
-#define NVIC_PRI8_INT34_S       16
-#define NVIC_PRI8_INT33_S       8
-#define NVIC_PRI8_INT32_S       0
+#define NVIC_PRI8_INT35_M       0xE0000000  // Interrupt 35 Priority Mask
+#define NVIC_PRI8_INT34_M       0x00E00000  // Interrupt 34 Priority Mask
+#define NVIC_PRI8_INT33_M       0x0000E000  // Interrupt 33 Priority Mask
+#define NVIC_PRI8_INT32_M       0x000000E0  // Interrupt 32 Priority Mask
+#define NVIC_PRI8_INT35_S       29
+#define NVIC_PRI8_INT34_S       21
+#define NVIC_PRI8_INT33_S       13
+#define NVIC_PRI8_INT32_S       5
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_PRI9 register.
 //
 //*****************************************************************************
-#define NVIC_PRI9_INT39_M       0xFF000000  // Interrupt 39 priority mask
-#define NVIC_PRI9_INT38_M       0x00FF0000  // Interrupt 38 priority mask
-#define NVIC_PRI9_INT37_M       0x0000FF00  // Interrupt 37 priority mask
-#define NVIC_PRI9_INT36_M       0x000000FF  // Interrupt 36 priority mask
-#define NVIC_PRI9_INT39_S       24
-#define NVIC_PRI9_INT38_S       16
-#define NVIC_PRI9_INT37_S       8
-#define NVIC_PRI9_INT36_S       0
+#define NVIC_PRI9_INT39_M       0xE0000000  // Interrupt 39 Priority Mask
+#define NVIC_PRI9_INT38_M       0x00E00000  // Interrupt 38 Priority Mask
+#define NVIC_PRI9_INT37_M       0x0000E000  // Interrupt 37 Priority Mask
+#define NVIC_PRI9_INT36_M       0x000000E0  // Interrupt 36 Priority Mask
+#define NVIC_PRI9_INT39_S       29
+#define NVIC_PRI9_INT38_S       21
+#define NVIC_PRI9_INT37_S       13
+#define NVIC_PRI9_INT36_S       5
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_PRI10 register.
 //
 //*****************************************************************************
-#define NVIC_PRI10_INT43_M      0xFF000000  // Interrupt 43 priority mask
-#define NVIC_PRI10_INT42_M      0x00FF0000  // Interrupt 42 priority mask
-#define NVIC_PRI10_INT41_M      0x0000FF00  // Interrupt 41 priority mask
-#define NVIC_PRI10_INT40_M      0x000000FF  // Interrupt 40 priority mask
-#define NVIC_PRI10_INT43_S      24
-#define NVIC_PRI10_INT42_S      16
-#define NVIC_PRI10_INT41_S      8
-#define NVIC_PRI10_INT40_S      0
+#define NVIC_PRI10_INT43_M      0xE0000000  // Interrupt 43 Priority Mask
+#define NVIC_PRI10_INT42_M      0x00E00000  // Interrupt 42 Priority Mask
+#define NVIC_PRI10_INT41_M      0x0000E000  // Interrupt 41 Priority Mask
+#define NVIC_PRI10_INT40_M      0x000000E0  // Interrupt 40 Priority Mask
+#define NVIC_PRI10_INT43_S      29
+#define NVIC_PRI10_INT42_S      21
+#define NVIC_PRI10_INT41_S      13
+#define NVIC_PRI10_INT40_S      5
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_CPUID register.
 //
 //*****************************************************************************
-#define NVIC_CPUID_IMP_M        0xFF000000  // Implementer
-#define NVIC_CPUID_VAR_M        0x00F00000  // Variant
-#define NVIC_CPUID_PARTNO_M     0x0000FFF0  // Processor part number
-#define NVIC_CPUID_REV_M        0x0000000F  // Revision
+#define NVIC_CPUID_IMP_M        0xFF000000  // Implementer Code
+#define NVIC_CPUID_IMP_ARM      0x41000000  // ARM
+#define NVIC_CPUID_VAR_M        0x00F00000  // Variant Number
+#define NVIC_CPUID_CON_M        0x000F0000  // Constant
+#define NVIC_CPUID_PARTNO_M     0x0000FFF0  // Part Number
+#define NVIC_CPUID_PARTNO_CM3   0x0000C230  // Cortex-M3 processor
+#define NVIC_CPUID_REV_M        0x0000000F  // Revision Number
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_INT_CTRL register.
 //
 //*****************************************************************************
-#define NVIC_INT_CTRL_NMI_SET   0x80000000  // Pend a NMI
-#define NVIC_INT_CTRL_PEND_SV   0x10000000  // Pend a PendSV
-#define NVIC_INT_CTRL_UNPEND_SV 0x08000000  // Unpend a PendSV
-#define NVIC_INT_CTRL_ISR_PRE   0x00800000  // Debug interrupt handling
-#define NVIC_INT_CTRL_ISR_PEND  0x00400000  // Debug interrupt pending
-#define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000  // Highest pending exception
-#define NVIC_INT_CTRL_RET_BASE  0x00000800  // Return to base
-#define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF  // Current active exception
-#define NVIC_INT_CTRL_VEC_PEN_S 12
+#define NVIC_INT_CTRL_NMI_SET   0x80000000  // NMI Set Pending
+#define NVIC_INT_CTRL_PEND_SV   0x10000000  // PendSV Set Pending
+#define NVIC_INT_CTRL_UNPEND_SV 0x08000000  // PendSV Clear Pending
+#define NVIC_INT_CTRL_PENDSTSET 0x04000000  // SysTick Set Pending
+#define NVIC_INT_CTRL_PENDSTCLR 0x02000000  // SysTick Clear Pending
+#define NVIC_INT_CTRL_ISR_PRE   0x00800000  // Debug Interrupt Handling
+#define NVIC_INT_CTRL_ISR_PEND  0x00400000  // Interrupt Pending
+#define NVIC_INT_CTRL_VEC_PEN_M 0x0003F000  // Interrupt Pending Vector Number
+#define NVIC_INT_CTRL_VEC_PEN_NMI \
+                                0x00002000  // NMI
+#define NVIC_INT_CTRL_VEC_PEN_HARD \
+                                0x00003000  // Hard fault
+#define NVIC_INT_CTRL_VEC_PEN_MEM \
+                                0x00004000  // Memory management fault
+#define NVIC_INT_CTRL_VEC_PEN_BUS \
+                                0x00005000  // Bus fault
+#define NVIC_INT_CTRL_VEC_PEN_USG \
+                                0x00006000  // Usage fault
+#define NVIC_INT_CTRL_VEC_PEN_SVC \
+                                0x0000B000  // SVCall
+#define NVIC_INT_CTRL_VEC_PEN_PNDSV \
+                                0x0000E000  // PendSV
+#define NVIC_INT_CTRL_VEC_PEN_TICK \
+                                0x0000F000  // SysTick
+#define NVIC_INT_CTRL_RET_BASE  0x00000800  // Return to Base
+#define NVIC_INT_CTRL_VEC_ACT_M 0x0000003F  // Interrupt Pending Vector Number
 #define NVIC_INT_CTRL_VEC_ACT_S 0
 
 //*****************************************************************************
@@ -4216,8 +4227,8 @@
 // The following are defines for the bit fields in the NVIC_VTABLE register.
 //
 //*****************************************************************************
-#define NVIC_VTABLE_BASE        0x20000000  // Vector table base
-#define NVIC_VTABLE_OFFSET_M    0x1FFFFF00  // Vector table offset
+#define NVIC_VTABLE_BASE        0x20000000  // Vector Table Base
+#define NVIC_VTABLE_OFFSET_M    0x1FFFFF00  // Vector Table Offset
 #define NVIC_VTABLE_OFFSET_S    8
 
 //*****************************************************************************
@@ -4225,77 +4236,76 @@
 // The following are defines for the bit fields in the NVIC_APINT register.
 //
 //*****************************************************************************
-#define NVIC_APINT_VECTKEY_M    0xFFFF0000  // Vector key mask
+#define NVIC_APINT_VECTKEY_M    0xFFFF0000  // Register Key
 #define NVIC_APINT_VECTKEY      0x05FA0000  // Vector key
-#define NVIC_APINT_ENDIANESS    0x00008000  // Data endianess
-#define NVIC_APINT_PRIGROUP_M   0x00000700  // Priority group
-#define NVIC_APINT_PRIGROUP_0_8 0x00000700  // Priority group 0.8 split
-#define NVIC_APINT_PRIGROUP_1_7 0x00000600  // Priority group 1.7 split
-#define NVIC_APINT_PRIGROUP_2_6 0x00000500  // Priority group 2.6 split
-#define NVIC_APINT_PRIGROUP_3_5 0x00000400  // Priority group 3.5 split
-#define NVIC_APINT_PRIGROUP_4_4 0x00000300  // Priority group 4.4 split
-#define NVIC_APINT_PRIGROUP_5_3 0x00000200  // Priority group 5.3 split
-#define NVIC_APINT_PRIGROUP_6_2 0x00000100  // Priority group 6.2 split
-#define NVIC_APINT_SYSRESETREQ  0x00000004  // System reset request
-#define NVIC_APINT_VECT_CLR_ACT 0x00000002  // Clear active NMI/fault info
-#define NVIC_APINT_VECT_RESET   0x00000001  // System reset
+#define NVIC_APINT_ENDIANESS    0x00008000  // Data Endianess
+#define NVIC_APINT_PRIGROUP_M   0x00000700  // Interrupt Priority Grouping
 #define NVIC_APINT_PRIGROUP_7_1 0x00000000  // Priority group 7.1 split
+#define NVIC_APINT_PRIGROUP_6_2 0x00000100  // Priority group 6.2 split
+#define NVIC_APINT_PRIGROUP_5_3 0x00000200  // Priority group 5.3 split
+#define NVIC_APINT_PRIGROUP_4_4 0x00000300  // Priority group 4.4 split
+#define NVIC_APINT_PRIGROUP_3_5 0x00000400  // Priority group 3.5 split
+#define NVIC_APINT_PRIGROUP_2_6 0x00000500  // Priority group 2.6 split
+#define NVIC_APINT_PRIGROUP_1_7 0x00000600  // Priority group 1.7 split
+#define NVIC_APINT_PRIGROUP_0_8 0x00000700  // Priority group 0.8 split
+#define NVIC_APINT_SYSRESETREQ  0x00000004  // System Reset Request
+#define NVIC_APINT_VECT_CLR_ACT 0x00000002  // Clear Active NMI / Fault
+#define NVIC_APINT_VECT_RESET   0x00000001  // System Reset
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_SYS_CTRL register.
 //
 //*****************************************************************************
-#define NVIC_SYS_CTRL_SEVONPEND 0x00000010  // Wakeup on pend
-#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004  // Deep sleep enable
-#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002  // Sleep on ISR exit
+#define NVIC_SYS_CTRL_SEVONPEND 0x00000010  // Wake Up on Pending
+#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004  // Deep Sleep Enable
+#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002  // Sleep on ISR Exit
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_CFG_CTRL register.
 //
 //*****************************************************************************
-#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100  // Ignore bus fault in NMI/fault
-#define NVIC_CFG_CTRL_DIV0      0x00000010  // Trap on divide by 0
-#define NVIC_CFG_CTRL_UNALIGNED 0x00000008  // Trap on unaligned access
-#define NVIC_CFG_CTRL_DEEP_PEND 0x00000004  // Allow deep interrupt trigger
-#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002  // Allow main interrupt trigger
-#define NVIC_CFG_CTRL_BASE_THR  0x00000001  // Thread state control
+#define NVIC_CFG_CTRL_STKALIGN  0x00000200  // Stack Alignment on Exception
+                                            // Entry
+#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100  // Ignore Bus Fault in NMI and
+                                            // Fault
+#define NVIC_CFG_CTRL_DIV0      0x00000010  // Trap on Divide by 0
+#define NVIC_CFG_CTRL_UNALIGNED 0x00000008  // Trap on Unaligned Access
+#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002  // Allow Main Interrupt Trigger
+#define NVIC_CFG_CTRL_BASE_THR  0x00000001  // Thread State Control
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_SYS_PRI1 register.
 //
 //*****************************************************************************
-#define NVIC_SYS_PRI1_RES_M     0xFF000000  // Priority of reserved handler
-#define NVIC_SYS_PRI1_USAGE_M   0x00FF0000  // Priority of usage fault handler
-#define NVIC_SYS_PRI1_BUS_M     0x0000FF00  // Priority of bus fault handler
-#define NVIC_SYS_PRI1_MEM_M     0x000000FF  // Priority of mem manage handler
-#define NVIC_SYS_PRI1_USAGE_S   16
-#define NVIC_SYS_PRI1_BUS_S     8
-#define NVIC_SYS_PRI1_MEM_S     0
+#define NVIC_SYS_PRI1_USAGE_M   0x00E00000  // Usage Fault Priority
+#define NVIC_SYS_PRI1_BUS_M     0x0000E000  // Bus Fault Priority
+#define NVIC_SYS_PRI1_MEM_M     0x000000E0  // Memory Management Fault Priority
+#define NVIC_SYS_PRI1_USAGE_S   21
+#define NVIC_SYS_PRI1_BUS_S     13
+#define NVIC_SYS_PRI1_MEM_S     5
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_SYS_PRI2 register.
 //
 //*****************************************************************************
-#define NVIC_SYS_PRI2_SVC_M     0xFF000000  // Priority of SVCall handler
-#define NVIC_SYS_PRI2_RES_M     0x00FFFFFF  // Priority of reserved handlers
-#define NVIC_SYS_PRI2_SVC_S     24
+#define NVIC_SYS_PRI2_SVC_M     0xE0000000  // SVCall Priority
+#define NVIC_SYS_PRI2_SVC_S     29
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_SYS_PRI3 register.
 //
 //*****************************************************************************
-#define NVIC_SYS_PRI3_TICK_M    0xFF000000  // Priority of Sys Tick handler
-#define NVIC_SYS_PRI3_PENDSV_M  0x00FF0000  // Priority of PendSV handler
-#define NVIC_SYS_PRI3_RES_M     0x0000FF00  // Priority of reserved handler
-#define NVIC_SYS_PRI3_DEBUG_M   0x000000FF  // Priority of debug handler
-#define NVIC_SYS_PRI3_TICK_S    24
-#define NVIC_SYS_PRI3_PENDSV_S  16
-#define NVIC_SYS_PRI3_DEBUG_S   0
+#define NVIC_SYS_PRI3_TICK_M    0xE0000000  // SysTick Exception Priority
+#define NVIC_SYS_PRI3_PENDSV_M  0x00E00000  // PendSV Priority
+#define NVIC_SYS_PRI3_DEBUG_M   0x000000E0  // Debug Priority
+#define NVIC_SYS_PRI3_TICK_S    29
+#define NVIC_SYS_PRI3_PENDSV_S  21
+#define NVIC_SYS_PRI3_DEBUG_S   5
 
 //*****************************************************************************
 //
@@ -4303,18 +4313,21 @@
 // register.
 //
 //*****************************************************************************
-#define NVIC_SYS_HND_CTRL_USAGE 0x00040000  // Usage fault enable
-#define NVIC_SYS_HND_CTRL_BUS   0x00020000  // Bus fault enable
-#define NVIC_SYS_HND_CTRL_MEM   0x00010000  // Mem manage fault enable
-#define NVIC_SYS_HND_CTRL_SVC   0x00008000  // SVCall is pended
-#define NVIC_SYS_HND_CTRL_BUSP  0x00004000  // Bus fault is pended
-#define NVIC_SYS_HND_CTRL_TICK  0x00000800  // Sys tick is active
-#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400  // PendSV is active
-#define NVIC_SYS_HND_CTRL_MON   0x00000100  // Monitor is active
-#define NVIC_SYS_HND_CTRL_SVCA  0x00000080  // SVCall is active
-#define NVIC_SYS_HND_CTRL_USGA  0x00000008  // Usage fault is active
-#define NVIC_SYS_HND_CTRL_BUSA  0x00000002  // Bus fault is active
-#define NVIC_SYS_HND_CTRL_MEMA  0x00000001  // Mem manage is active
+#define NVIC_SYS_HND_CTRL_USAGE 0x00040000  // Usage Fault Enable
+#define NVIC_SYS_HND_CTRL_BUS   0x00020000  // Bus Fault Enable
+#define NVIC_SYS_HND_CTRL_MEM   0x00010000  // Memory Management Fault Enable
+#define NVIC_SYS_HND_CTRL_SVC   0x00008000  // SVC Call Pending
+#define NVIC_SYS_HND_CTRL_BUSP  0x00004000  // Bus Fault Pending
+#define NVIC_SYS_HND_CTRL_MEMP  0x00002000  // Memory Management Fault Pending
+#define NVIC_SYS_HND_CTRL_USAGEP \
+                                0x00001000  // Usage Fault Pending
+#define NVIC_SYS_HND_CTRL_TICK  0x00000800  // SysTick Exception Active
+#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400  // PendSV Exception Active
+#define NVIC_SYS_HND_CTRL_MON   0x00000100  // Debug Monitor Active
+#define NVIC_SYS_HND_CTRL_SVCA  0x00000080  // SVC Call Active
+#define NVIC_SYS_HND_CTRL_USGA  0x00000008  // Usage Fault Active
+#define NVIC_SYS_HND_CTRL_BUSA  0x00000002  // Bus Fault Active
+#define NVIC_SYS_HND_CTRL_MEMA  0x00000001  // Memory Management Fault Active
 
 //*****************************************************************************
 //
@@ -4322,23 +4335,25 @@
 // register.
 //
 //*****************************************************************************
-#define NVIC_FAULT_STAT_DIV0    0x02000000  // Divide by zero fault
-#define NVIC_FAULT_STAT_UNALIGN 0x01000000  // Unaligned access fault
-#define NVIC_FAULT_STAT_NOCP    0x00080000  // No coprocessor fault
-#define NVIC_FAULT_STAT_INVPC   0x00040000  // Invalid PC fault
-#define NVIC_FAULT_STAT_INVSTAT 0x00020000  // Invalid state fault
-#define NVIC_FAULT_STAT_UNDEF   0x00010000  // Undefined instruction fault
-#define NVIC_FAULT_STAT_BFARV   0x00008000  // BFAR is valid
-#define NVIC_FAULT_STAT_BSTKE   0x00001000  // Stack bus fault
-#define NVIC_FAULT_STAT_BUSTKE  0x00000800  // Unstack bus fault
-#define NVIC_FAULT_STAT_IMPRE   0x00000400  // Imprecise data bus error
-#define NVIC_FAULT_STAT_PRECISE 0x00000200  // Precise data bus error
-#define NVIC_FAULT_STAT_IBUS    0x00000100  // Instruction bus fault
-#define NVIC_FAULT_STAT_MMARV   0x00000080  // MMAR is valid
-#define NVIC_FAULT_STAT_MSTKE   0x00000010  // Stack access violation
-#define NVIC_FAULT_STAT_MUSTKE  0x00000008  // Unstack access violation
-#define NVIC_FAULT_STAT_DERR    0x00000002  // Data access violation
-#define NVIC_FAULT_STAT_IERR    0x00000001  // Instruction access violation
+#define NVIC_FAULT_STAT_DIV0    0x02000000  // Divide-by-Zero Usage Fault
+#define NVIC_FAULT_STAT_UNALIGN 0x01000000  // Unaligned Access Usage Fault
+#define NVIC_FAULT_STAT_NOCP    0x00080000  // No Coprocessor Usage Fault
+#define NVIC_FAULT_STAT_INVPC   0x00040000  // Invalid PC Load Usage Fault
+#define NVIC_FAULT_STAT_INVSTAT 0x00020000  // Invalid State Usage Fault
+#define NVIC_FAULT_STAT_UNDEF   0x00010000  // Undefined Instruction Usage
+                                            // Fault
+#define NVIC_FAULT_STAT_BFARV   0x00008000  // Bus Fault Address Register Valid
+#define NVIC_FAULT_STAT_BSTKE   0x00001000  // Stack Bus Fault
+#define NVIC_FAULT_STAT_BUSTKE  0x00000800  // Unstack Bus Fault
+#define NVIC_FAULT_STAT_IMPRE   0x00000400  // Imprecise Data Bus Error
+#define NVIC_FAULT_STAT_PRECISE 0x00000200  // Precise Data Bus Error
+#define NVIC_FAULT_STAT_IBUS    0x00000100  // Instruction Bus Error
+#define NVIC_FAULT_STAT_MMARV   0x00000080  // Memory Management Fault Address
+                                            // Register Valid
+#define NVIC_FAULT_STAT_MSTKE   0x00000010  // Stack Access Violation
+#define NVIC_FAULT_STAT_MUSTKE  0x00000008  // Unstack Access Violation
+#define NVIC_FAULT_STAT_DERR    0x00000002  // Data Access Violation
+#define NVIC_FAULT_STAT_IERR    0x00000001  // Instruction Access Violation
 
 //*****************************************************************************
 //
@@ -4346,9 +4361,9 @@
 // register.
 //
 //*****************************************************************************
-#define NVIC_HFAULT_STAT_DBG    0x80000000  // Debug event
-#define NVIC_HFAULT_STAT_FORCED 0x40000000  // Cannot execute fault handler
-#define NVIC_HFAULT_STAT_VECT   0x00000002  // Vector table read fault
+#define NVIC_HFAULT_STAT_DBG    0x80000000  // Debug Event
+#define NVIC_HFAULT_STAT_FORCED 0x40000000  // Forced Hard Fault
+#define NVIC_HFAULT_STAT_VECT   0x00000002  // Vector Table Read Fault
 
 //*****************************************************************************
 //
@@ -4367,7 +4382,7 @@
 // The following are defines for the bit fields in the NVIC_MM_ADDR register.
 //
 //*****************************************************************************
-#define NVIC_MM_ADDR_M          0xFFFFFFFF  // Data fault address
+#define NVIC_MM_ADDR_M          0xFFFFFFFF  // Fault Address
 #define NVIC_MM_ADDR_S          0
 
 //*****************************************************************************
@@ -4376,7 +4391,7 @@
 // register.
 //
 //*****************************************************************************
-#define NVIC_FAULT_ADDR_M       0xFFFFFFFF  // Data bus fault address
+#define NVIC_FAULT_ADDR_M       0xFFFFFFFF  // Fault Address
 #define NVIC_FAULT_ADDR_S       0
 
 //*****************************************************************************
@@ -4384,9 +4399,9 @@
 // The following are defines for the bit fields in the NVIC_MPU_TYPE register.
 //
 //*****************************************************************************
-#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000  // Number of I regions
-#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00  // Number of D regions
-#define NVIC_MPU_TYPE_SEPARATE  0x00000001  // Separate or unified MPU
+#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000  // Number of I Regions
+#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00  // Number of D Regions
+#define NVIC_MPU_TYPE_SEPARATE  0x00000001  // Separate or Unified MPU
 #define NVIC_MPU_TYPE_IREGION_S 16
 #define NVIC_MPU_TYPE_DREGION_S 8
 
@@ -4395,9 +4410,9 @@
 // The following are defines for the bit fields in the NVIC_MPU_CTRL register.
 //
 //*****************************************************************************
-#define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004  // MPU default region in priv mode
-#define NVIC_MPU_CTRL_HFNMIENA  0x00000002  // MPU enabled during faults
-#define NVIC_MPU_CTRL_ENABLE    0x00000001  // MPU enable
+#define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004  // MPU Default Region
+#define NVIC_MPU_CTRL_HFNMIENA  0x00000002  // MPU Enabled During Faults
+#define NVIC_MPU_CTRL_ENABLE    0x00000001  // MPU Enable
 
 //*****************************************************************************
 //
@@ -4405,7 +4420,7 @@
 // register.
 //
 //*****************************************************************************
-#define NVIC_MPU_NUMBER_M       0x000000FF  // MPU region to access
+#define NVIC_MPU_NUMBER_M       0x00000007  // MPU Region to Access
 #define NVIC_MPU_NUMBER_S       0
 
 //*****************************************************************************
@@ -4413,10 +4428,10 @@
 // The following are defines for the bit fields in the NVIC_MPU_BASE register.
 //
 //*****************************************************************************
-#define NVIC_MPU_BASE_ADDR_M    0xFFFFFFE0  // Base address mask
-#define NVIC_MPU_BASE_VALID     0x00000010  // Region number valid
-#define NVIC_MPU_BASE_REGION_M  0x0000000F  // Region number
-#define NVIC_MPU_BASE_ADDR_S    8
+#define NVIC_MPU_BASE_ADDR_M    0xFFFFFFE0  // Base Address Mask
+#define NVIC_MPU_BASE_VALID     0x00000010  // Region Number Valid
+#define NVIC_MPU_BASE_REGION_M  0x00000007  // Region Number
+#define NVIC_MPU_BASE_ADDR_S    5
 #define NVIC_MPU_BASE_REGION_S  0
 
 //*****************************************************************************
@@ -4425,19 +4440,19 @@
 //
 //*****************************************************************************
 #define NVIC_MPU_ATTR_M         0xFFFF0000  // Attributes
+#define NVIC_MPU_ATTR_XN        0x10000000  // Instruction Access Disable
+#define NVIC_MPU_ATTR_AP_M      0x07000000  // Access Privilege
 #define NVIC_MPU_ATTR_AP_NO_NO  0x00000000  // prv: no access, usr: no access
-#define NVIC_MPU_ATTR_BUFFRABLE 0x00010000  // Bufferable
-#define NVIC_MPU_ATTR_CACHEABLE 0x00020000  // Cacheable
-#define NVIC_MPU_ATTR_SHAREABLE 0x00040000  // Shareable
-#define NVIC_MPU_ATTR_TEX_M     0x00380000  // Type extension mask
 #define NVIC_MPU_ATTR_AP_RW_NO  0x01000000  // prv: rw, usr: none
 #define NVIC_MPU_ATTR_AP_RW_RO  0x02000000  // prv: rw, usr: read-only
 #define NVIC_MPU_ATTR_AP_RW_RW  0x03000000  // prv: rw, usr: rw
 #define NVIC_MPU_ATTR_AP_RO_NO  0x05000000  // prv: ro, usr: none
 #define NVIC_MPU_ATTR_AP_RO_RO  0x06000000  // prv: ro, usr: ro
-#define NVIC_MPU_ATTR_AP_M      0x07000000  // Access permissions mask
-#define NVIC_MPU_ATTR_XN        0x10000000  // Execute disable
-#define NVIC_MPU_ATTR_SRD_M     0x0000FF00  // Sub-region disable mask
+#define NVIC_MPU_ATTR_TEX_M     0x00380000  // Type Extension Mask
+#define NVIC_MPU_ATTR_SHAREABLE 0x00040000  // Shareable
+#define NVIC_MPU_ATTR_CACHEABLE 0x00020000  // Cacheable
+#define NVIC_MPU_ATTR_BUFFRABLE 0x00010000  // Bufferable
+#define NVIC_MPU_ATTR_SRD_M     0x0000FF00  // Subregion Disable Bits
 #define NVIC_MPU_ATTR_SRD_0     0x00000100  // Sub-region 0 disable
 #define NVIC_MPU_ATTR_SRD_1     0x00000200  // Sub-region 1 disable
 #define NVIC_MPU_ATTR_SRD_2     0x00000400  // Sub-region 2 disable
@@ -4446,7 +4461,7 @@
 #define NVIC_MPU_ATTR_SRD_5     0x00002000  // Sub-region 5 disable
 #define NVIC_MPU_ATTR_SRD_6     0x00004000  // Sub-region 6 disable
 #define NVIC_MPU_ATTR_SRD_7     0x00008000  // Sub-region 7 disable
-#define NVIC_MPU_ATTR_SIZE_M    0x0000003E  // Region size mask
+#define NVIC_MPU_ATTR_SIZE_M    0x0000003E  // Region Size Mask
 #define NVIC_MPU_ATTR_SIZE_32B  0x00000008  // Region size 32 bytes
 #define NVIC_MPU_ATTR_SIZE_64B  0x0000000A  // Region size 64 bytes
 #define NVIC_MPU_ATTR_SIZE_128B 0x0000000C  // Region size 128 bytes
@@ -4475,7 +4490,94 @@
 #define NVIC_MPU_ATTR_SIZE_1G   0x0000003A  // Region size 1 Gbytes
 #define NVIC_MPU_ATTR_SIZE_2G   0x0000003C  // Region size 2 Gbytes
 #define NVIC_MPU_ATTR_SIZE_4G   0x0000003E  // Region size 4 Gbytes
-#define NVIC_MPU_ATTR_ENABLE    0x00000001  // Region enable
+#define NVIC_MPU_ATTR_ENABLE    0x00000001  // Region Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE1 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE1_ADDR_M   0xFFFFFFE0  // Base Address Mask
+#define NVIC_MPU_BASE1_VALID    0x00000010  // Region Number Valid
+#define NVIC_MPU_BASE1_REGION_M 0x00000007  // Region Number
+#define NVIC_MPU_BASE1_ADDR_S   5
+#define NVIC_MPU_BASE1_REGION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR1 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR1_XN       0x10000000  // Instruction Access Disable
+#define NVIC_MPU_ATTR1_AP_M     0x07000000  // Access Privilege
+#define NVIC_MPU_ATTR1_TEX_M    0x00380000  // Type Extension Mask
+#define NVIC_MPU_ATTR1_SHAREABLE \
+                                0x00040000  // Shareable
+#define NVIC_MPU_ATTR1_CACHEABLE \
+                                0x00020000  // Cacheable
+#define NVIC_MPU_ATTR1_BUFFRABLE \
+                                0x00010000  // Bufferable
+#define NVIC_MPU_ATTR1_SRD_M    0x0000FF00  // Subregion Disable Bits
+#define NVIC_MPU_ATTR1_SIZE_M   0x0000003E  // Region Size Mask
+#define NVIC_MPU_ATTR1_ENABLE   0x00000001  // Region Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE2 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE2_ADDR_M   0xFFFFFFE0  // Base Address Mask
+#define NVIC_MPU_BASE2_VALID    0x00000010  // Region Number Valid
+#define NVIC_MPU_BASE2_REGION_M 0x00000007  // Region Number
+#define NVIC_MPU_BASE2_ADDR_S   5
+#define NVIC_MPU_BASE2_REGION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR2 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR2_XN       0x10000000  // Instruction Access Disable
+#define NVIC_MPU_ATTR2_AP_M     0x07000000  // Access Privilege
+#define NVIC_MPU_ATTR2_TEX_M    0x00380000  // Type Extension Mask
+#define NVIC_MPU_ATTR2_SHAREABLE \
+                                0x00040000  // Shareable
+#define NVIC_MPU_ATTR2_CACHEABLE \
+                                0x00020000  // Cacheable
+#define NVIC_MPU_ATTR2_BUFFRABLE \
+                                0x00010000  // Bufferable
+#define NVIC_MPU_ATTR2_SRD_M    0x0000FF00  // Subregion Disable Bits
+#define NVIC_MPU_ATTR2_SIZE_M   0x0000003E  // Region Size Mask
+#define NVIC_MPU_ATTR2_ENABLE   0x00000001  // Region Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE3 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE3_ADDR_M   0xFFFFFFE0  // Base Address Mask
+#define NVIC_MPU_BASE3_VALID    0x00000010  // Region Number Valid
+#define NVIC_MPU_BASE3_REGION_M 0x00000007  // Region Number
+#define NVIC_MPU_BASE3_ADDR_S   5
+#define NVIC_MPU_BASE3_REGION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR3 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR3_XN       0x10000000  // Instruction Access Disable
+#define NVIC_MPU_ATTR3_AP_M     0x07000000  // Access Privilege
+#define NVIC_MPU_ATTR3_TEX_M    0x00380000  // Type Extension Mask
+#define NVIC_MPU_ATTR3_SHAREABLE \
+                                0x00040000  // Shareable
+#define NVIC_MPU_ATTR3_CACHEABLE \
+                                0x00020000  // Cacheable
+#define NVIC_MPU_ATTR3_BUFFRABLE \
+                                0x00010000  // Bufferable
+#define NVIC_MPU_ATTR3_SRD_M    0x0000FF00  // Subregion Disable Bits
+#define NVIC_MPU_ATTR3_SIZE_M   0x0000003E  // Region Size Mask
+#define NVIC_MPU_ATTR3_ENABLE   0x00000001  // Region Enable
 
 //*****************************************************************************
 //
@@ -4507,27 +4609,27 @@
 //*****************************************************************************
 #define NVIC_DBG_XFER_REG_WNR   0x00010000  // Write or not read
 #define NVIC_DBG_XFER_REG_SEL_M 0x0000001F  // Register
-#define NVIC_DBG_XFER_REG_CFBP  0x00000014  // Control/Fault/BasePri/PriMask
-#define NVIC_DBG_XFER_REG_DSP   0x00000013  // Deep SP
-#define NVIC_DBG_XFER_REG_PSP   0x00000012  // Process SP
-#define NVIC_DBG_XFER_REG_MSP   0x00000011  // Main SP
-#define NVIC_DBG_XFER_REG_FLAGS 0x00000010  // xPSR/Flags register
-#define NVIC_DBG_XFER_REG_R15   0x0000000F  // Register R15
-#define NVIC_DBG_XFER_REG_R14   0x0000000E  // Register R14
-#define NVIC_DBG_XFER_REG_R13   0x0000000D  // Register R13
-#define NVIC_DBG_XFER_REG_R12   0x0000000C  // Register R12
-#define NVIC_DBG_XFER_REG_R11   0x0000000B  // Register R11
-#define NVIC_DBG_XFER_REG_R10   0x0000000A  // Register R10
-#define NVIC_DBG_XFER_REG_R9    0x00000009  // Register R9
-#define NVIC_DBG_XFER_REG_R8    0x00000008  // Register R8
-#define NVIC_DBG_XFER_REG_R7    0x00000007  // Register R7
-#define NVIC_DBG_XFER_REG_R6    0x00000006  // Register R6
-#define NVIC_DBG_XFER_REG_R5    0x00000005  // Register R5
-#define NVIC_DBG_XFER_REG_R4    0x00000004  // Register R4
-#define NVIC_DBG_XFER_REG_R3    0x00000003  // Register R3
-#define NVIC_DBG_XFER_REG_R2    0x00000002  // Register R2
-#define NVIC_DBG_XFER_REG_R1    0x00000001  // Register R1
 #define NVIC_DBG_XFER_REG_R0    0x00000000  // Register R0
+#define NVIC_DBG_XFER_REG_R1    0x00000001  // Register R1
+#define NVIC_DBG_XFER_REG_R2    0x00000002  // Register R2
+#define NVIC_DBG_XFER_REG_R3    0x00000003  // Register R3
+#define NVIC_DBG_XFER_REG_R4    0x00000004  // Register R4
+#define NVIC_DBG_XFER_REG_R5    0x00000005  // Register R5
+#define NVIC_DBG_XFER_REG_R6    0x00000006  // Register R6
+#define NVIC_DBG_XFER_REG_R7    0x00000007  // Register R7
+#define NVIC_DBG_XFER_REG_R8    0x00000008  // Register R8
+#define NVIC_DBG_XFER_REG_R9    0x00000009  // Register R9
+#define NVIC_DBG_XFER_REG_R10   0x0000000A  // Register R10
+#define NVIC_DBG_XFER_REG_R11   0x0000000B  // Register R11
+#define NVIC_DBG_XFER_REG_R12   0x0000000C  // Register R12
+#define NVIC_DBG_XFER_REG_R13   0x0000000D  // Register R13
+#define NVIC_DBG_XFER_REG_R14   0x0000000E  // Register R14
+#define NVIC_DBG_XFER_REG_R15   0x0000000F  // Register R15
+#define NVIC_DBG_XFER_REG_FLAGS 0x00000010  // xPSR/Flags register
+#define NVIC_DBG_XFER_REG_MSP   0x00000011  // Main SP
+#define NVIC_DBG_XFER_REG_PSP   0x00000012  // Process SP
+#define NVIC_DBG_XFER_REG_DSP   0x00000013  // Deep SP
+#define NVIC_DBG_XFER_REG_CFBP  0x00000014  // Control/Fault/BasePri/PriMask
 
 //*****************************************************************************
 //
@@ -4559,7 +4661,135 @@
 // The following are defines for the bit fields in the NVIC_SW_TRIG register.
 //
 //*****************************************************************************
-#define NVIC_SW_TRIG_INTID_M    0x000003FF  // Interrupt to trigger
+#define NVIC_SW_TRIG_INTID_M    0x0000003F  // Interrupt ID
 #define NVIC_SW_TRIG_INTID_S    0
 
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// Deprecated defines for the Watchdog
+//
+//*****************************************************************************
+#define WATCHDOG_LOAD_R         (*((volatile unsigned long *)0x40000000))
+#define WATCHDOG_VALUE_R        (*((volatile unsigned long *)0x40000004))
+#define WATCHDOG_CTL_R          (*((volatile unsigned long *)0x40000008))
+#define WATCHDOG_ICR_R          (*((volatile unsigned long *)0x4000000C))
+#define WATCHDOG_RIS_R          (*((volatile unsigned long *)0x40000010))
+#define WATCHDOG_MIS_R          (*((volatile unsigned long *)0x40000014))
+#define WATCHDOG_TEST_R         (*((volatile unsigned long *)0x40000418))
+#define WATCHDOG_LOCK_R         (*((volatile unsigned long *)0x40000C00))
+
+//*****************************************************************************
+//
+// Deprecated defines for the bit fields in the I2C_O_SICR register.
+//
+//*****************************************************************************
+#define I2C_SICR_IC             0x00000001  // Clear Interrupt
+
+//*****************************************************************************
+//
+// Deprecated defines for the bit fields in the I2C_O_SMIS register.
+//
+//*****************************************************************************
+#define I2C_SMIS_MIS            0x00000001  // Masked Interrupt Status
+
+//*****************************************************************************
+//
+// Deprecated defines for the bit fields in the I2C_O_SRIS register.
+//
+//*****************************************************************************
+#define I2C_SRIS_RIS            0x00000001  // Raw Interrupt Status
+
+//*****************************************************************************
+//
+// Deprecated defines for the bit fields in the I2C_O_SIMR register.
+//
+//*****************************************************************************
+#define I2C_SIMR_IM             0x00000001  // Interrupt Mask
+
+//*****************************************************************************
+//
+// Deprecated defines for the bit fields in the the interpretation of the data
+// in the SSFIFOx when the ADC TMLB is enabled. register.
+//
+//*****************************************************************************
+#define ADC_TMLB_CNT_M          0x000003C0  // Continuous Sample Counter
+#define ADC_TMLB_CONT           0x00000020  // Continuation Sample Indicator
+#define ADC_TMLB_DIFF           0x00000010  // Differential Sample Indicator
+#define ADC_TMLB_TS             0x00000008  // Temp Sensor Sample Indicator
+#define ADC_TMLB_MUX_M          0x00000007  // Analog Input Indicator
+#define ADC_TMLB_CNT_S          6           // Sample counter shift
+#define ADC_TMLB_MUX_S          0           // Input channel number shift
+
+//*****************************************************************************
+//
+// Deprecated defines for the ADC register offsets.
+//
+//*****************************************************************************
+#define ADC_ACTSS_R             (*((volatile unsigned long *)0x40038000))
+#define ADC_RIS_R               (*((volatile unsigned long *)0x40038004))
+#define ADC_IM_R                (*((volatile unsigned long *)0x40038008))
+#define ADC_ISC_R               (*((volatile unsigned long *)0x4003800C))
+#define ADC_OSTAT_R             (*((volatile unsigned long *)0x40038010))
+#define ADC_EMUX_R              (*((volatile unsigned long *)0x40038014))
+#define ADC_USTAT_R             (*((volatile unsigned long *)0x40038018))
+#define ADC_SSPRI_R             (*((volatile unsigned long *)0x40038020))
+#define ADC_PSSI_R              (*((volatile unsigned long *)0x40038028))
+#define ADC_SAC_R               (*((volatile unsigned long *)0x40038030))
+#define ADC_SSMUX0_R            (*((volatile unsigned long *)0x40038040))
+#define ADC_SSCTL0_R            (*((volatile unsigned long *)0x40038044))
+#define ADC_SSFIFO0_R           (*((volatile unsigned long *)0x40038048))
+#define ADC_SSFSTAT0_R          (*((volatile unsigned long *)0x4003804C))
+#define ADC_SSMUX1_R            (*((volatile unsigned long *)0x40038060))
+#define ADC_SSCTL1_R            (*((volatile unsigned long *)0x40038064))
+#define ADC_SSFIFO1_R           (*((volatile unsigned long *)0x40038068))
+#define ADC_SSFSTAT1_R          (*((volatile unsigned long *)0x4003806C))
+#define ADC_SSMUX2_R            (*((volatile unsigned long *)0x40038080))
+#define ADC_SSCTL2_R            (*((volatile unsigned long *)0x40038084))
+#define ADC_SSFIFO2_R           (*((volatile unsigned long *)0x40038088))
+#define ADC_SSFSTAT2_R          (*((volatile unsigned long *)0x4003808C))
+#define ADC_SSMUX3_R            (*((volatile unsigned long *)0x400380A0))
+#define ADC_SSCTL3_R            (*((volatile unsigned long *)0x400380A4))
+#define ADC_SSFIFO3_R           (*((volatile unsigned long *)0x400380A8))
+#define ADC_SSFSTAT3_R          (*((volatile unsigned long *)0x400380AC))
+#define ADC_TMLB_R              (*((volatile unsigned long *)0x40038100))
+
+//*****************************************************************************
+//
+// Deprecated defines for the bit fields in the FLASH_FMC register.
+//
+//*****************************************************************************
+#define FLASH_FMC_WRKEY_M       0xFFFF0000  // Flash Memory Write Key
+#define FLASH_FMC_WRKEY_S       16
+
+//*****************************************************************************
+//
+// Deprecated defines for the bit fields in the SYSCTL_DC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC1_WDT          0x00000008  // Watchdog Timer Present
+
+//*****************************************************************************
+//
+// Deprecated defines for the bit fields in the SYSCTL_DID1 register.
+//
+//*****************************************************************************
+#define SYSCTL_DID1_PKG_28SOIC  0x00000000  // SOIC package
+#define SYSCTL_DID1_PKG_48QFP   0x00000008  // QFP package
+
+//*****************************************************************************
+//
+// Deprecated defines for the NVIC register addresses.
+//
+//*****************************************************************************
+#define NVIC_MPU_R              (*((volatile unsigned long *)0xE000ED9C))
+
+#endif
+
 #endif // __LM3S6965_H__
diff --git a/src/platform/lm3s/lm3s8962.h b/src/platform/lm3s/lm3s8962.h
index 87cd5dde..91257d31 100755
--- a/src/platform/lm3s/lm3s8962.h
+++ b/src/platform/lm3s/lm3s8962.h
@@ -2,26 +2,23 @@
 //
 // lm3s8962.h - LM3S8962 Register Definitions
 //
-// Copyright (c) 2007-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2007-2011 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4781 of the Stellaris Firmware Development Package.
+// This is part of revision 7611 of the Stellaris Firmware Development Package.
 //
 //*****************************************************************************
 
@@ -30,21 +27,21 @@
 
 //*****************************************************************************
 //
-// Watchdog Timer (WATCHDOG)
+// Watchdog Timer registers (WATCHDOG0)
 //
 //*****************************************************************************
-#define WATCHDOG_LOAD_R         (*((volatile unsigned long *)0x40000000))
-#define WATCHDOG_VALUE_R        (*((volatile unsigned long *)0x40000004))
-#define WATCHDOG_CTL_R          (*((volatile unsigned long *)0x40000008))
-#define WATCHDOG_ICR_R          (*((volatile unsigned long *)0x4000000C))
-#define WATCHDOG_RIS_R          (*((volatile unsigned long *)0x40000010))
-#define WATCHDOG_MIS_R          (*((volatile unsigned long *)0x40000014))
-#define WATCHDOG_TEST_R         (*((volatile unsigned long *)0x40000418))
-#define WATCHDOG_LOCK_R         (*((volatile unsigned long *)0x40000C00))
+#define WATCHDOG0_LOAD_R        (*((volatile unsigned long *)0x40000000))
+#define WATCHDOG0_VALUE_R       (*((volatile unsigned long *)0x40000004))
+#define WATCHDOG0_CTL_R         (*((volatile unsigned long *)0x40000008))
+#define WATCHDOG0_ICR_R         (*((volatile unsigned long *)0x4000000C))
+#define WATCHDOG0_RIS_R         (*((volatile unsigned long *)0x40000010))
+#define WATCHDOG0_MIS_R         (*((volatile unsigned long *)0x40000014))
+#define WATCHDOG0_TEST_R        (*((volatile unsigned long *)0x40000418))
+#define WATCHDOG0_LOCK_R        (*((volatile unsigned long *)0x40000C00))
 
 //*****************************************************************************
 //
-// General-Purpose Input/Outputs (PORTA)
+// GPIO registers (PORTA)
 //
 //*****************************************************************************
 #define GPIO_PORTA_DATA_BITS_R  ((volatile unsigned long *)0x40004000)
@@ -71,7 +68,7 @@
 
 //*****************************************************************************
 //
-// General-Purpose Input/Outputs (PORTB)
+// GPIO registers (PORTB)
 //
 //*****************************************************************************
 #define GPIO_PORTB_DATA_BITS_R  ((volatile unsigned long *)0x40005000)
@@ -98,7 +95,7 @@
 
 //*****************************************************************************
 //
-// General-Purpose Input/Outputs (PORTC)
+// GPIO registers (PORTC)
 //
 //*****************************************************************************
 #define GPIO_PORTC_DATA_BITS_R  ((volatile unsigned long *)0x40006000)
@@ -125,7 +122,7 @@
 
 //*****************************************************************************
 //
-// General-Purpose Input/Outputs (PORTD)
+// GPIO registers (PORTD)
 //
 //*****************************************************************************
 #define GPIO_PORTD_DATA_BITS_R  ((volatile unsigned long *)0x40007000)
@@ -152,7 +149,7 @@
 
 //*****************************************************************************
 //
-// Synchronous Serial Interface (SSI0)
+// SSI registers (SSI0)
 //
 //*****************************************************************************
 #define SSI0_CR0_R              (*((volatile unsigned long *)0x40008000))
@@ -167,7 +164,7 @@
 
 //*****************************************************************************
 //
-// Universal Asynchronous Receivers/Transmitters (UART0)
+// UART registers (UART0)
 //
 //*****************************************************************************
 #define UART0_DR_R              (*((volatile unsigned long *)0x4000C000))
@@ -187,7 +184,7 @@
 
 //*****************************************************************************
 //
-// Universal Asynchronous Receivers/Transmitters (UART1)
+// UART registers (UART1)
 //
 //*****************************************************************************
 #define UART1_DR_R              (*((volatile unsigned long *)0x4000D000))
@@ -207,51 +204,35 @@
 
 //*****************************************************************************
 //
-// Inter-Integrated Circuit (MASTER) Interface
+// I2C registers (I2C0 MASTER)
 //
 //*****************************************************************************
 #define I2C0_MASTER_MSA_R       (*((volatile unsigned long *)0x40020000))
-#define I2C0_MASTER_SOAR_R      (*((volatile unsigned long *)0x40020000))
-#define I2C0_MASTER_SCSR_R      (*((volatile unsigned long *)0x40020004))
 #define I2C0_MASTER_MCS_R       (*((volatile unsigned long *)0x40020004))
-#define I2C0_MASTER_SDR_R       (*((volatile unsigned long *)0x40020008))
 #define I2C0_MASTER_MDR_R       (*((volatile unsigned long *)0x40020008))
 #define I2C0_MASTER_MTPR_R      (*((volatile unsigned long *)0x4002000C))
-#define I2C0_MASTER_SIMR_R      (*((volatile unsigned long *)0x4002000C))
-#define I2C0_MASTER_SRIS_R      (*((volatile unsigned long *)0x40020010))
 #define I2C0_MASTER_MIMR_R      (*((volatile unsigned long *)0x40020010))
 #define I2C0_MASTER_MRIS_R      (*((volatile unsigned long *)0x40020014))
-#define I2C0_MASTER_SMIS_R      (*((volatile unsigned long *)0x40020014))
-#define I2C0_MASTER_SICR_R      (*((volatile unsigned long *)0x40020018))
 #define I2C0_MASTER_MMIS_R      (*((volatile unsigned long *)0x40020018))
 #define I2C0_MASTER_MICR_R      (*((volatile unsigned long *)0x4002001C))
 #define I2C0_MASTER_MCR_R       (*((volatile unsigned long *)0x40020020))
 
 //*****************************************************************************
 //
-// Inter-Integrated Circuit (SLAVE) Interface
+// I2C registers (I2C0 SLAVE)
 //
 //*****************************************************************************
-#define I2C0_SLAVE_MSA_R        (*((volatile unsigned long *)0x40020800))
 #define I2C0_SLAVE_SOAR_R       (*((volatile unsigned long *)0x40020800))
 #define I2C0_SLAVE_SCSR_R       (*((volatile unsigned long *)0x40020804))
-#define I2C0_SLAVE_MCS_R        (*((volatile unsigned long *)0x40020804))
 #define I2C0_SLAVE_SDR_R        (*((volatile unsigned long *)0x40020808))
-#define I2C0_SLAVE_MDR_R        (*((volatile unsigned long *)0x40020808))
-#define I2C0_SLAVE_MTPR_R       (*((volatile unsigned long *)0x4002080C))
 #define I2C0_SLAVE_SIMR_R       (*((volatile unsigned long *)0x4002080C))
 #define I2C0_SLAVE_SRIS_R       (*((volatile unsigned long *)0x40020810))
-#define I2C0_SLAVE_MIMR_R       (*((volatile unsigned long *)0x40020810))
-#define I2C0_SLAVE_MRIS_R       (*((volatile unsigned long *)0x40020814))
 #define I2C0_SLAVE_SMIS_R       (*((volatile unsigned long *)0x40020814))
 #define I2C0_SLAVE_SICR_R       (*((volatile unsigned long *)0x40020818))
-#define I2C0_SLAVE_MMIS_R       (*((volatile unsigned long *)0x40020818))
-#define I2C0_SLAVE_MICR_R       (*((volatile unsigned long *)0x4002081C))
-#define I2C0_SLAVE_MCR_R        (*((volatile unsigned long *)0x40020820))
 
 //*****************************************************************************
 //
-// General-Purpose Input/Outputs (PORTE)
+// GPIO registers (PORTE)
 //
 //*****************************************************************************
 #define GPIO_PORTE_DATA_BITS_R  ((volatile unsigned long *)0x40024000)
@@ -278,7 +259,7 @@
 
 //*****************************************************************************
 //
-// General-Purpose Input/Outputs (PORTF)
+// GPIO registers (PORTF)
 //
 //*****************************************************************************
 #define GPIO_PORTF_DATA_BITS_R  ((volatile unsigned long *)0x40025000)
@@ -305,7 +286,7 @@
 
 //*****************************************************************************
 //
-// General-Purpose Input/Outputs (PORTG)
+// GPIO registers (PORTG)
 //
 //*****************************************************************************
 #define GPIO_PORTG_DATA_BITS_R  ((volatile unsigned long *)0x40026000)
@@ -332,7 +313,7 @@
 
 //*****************************************************************************
 //
-// Pulse Width Modulator (PWM)
+// PWM registers (PWM)
 //
 //*****************************************************************************
 #define PWM_CTL_R               (*((volatile unsigned long *)0x40028000))
@@ -386,7 +367,7 @@
 
 //*****************************************************************************
 //
-// Quadrature Encoder Interface (QEI0)
+// QEI registers (QEI0)
 //
 //*****************************************************************************
 #define QEI0_CTL_R              (*((volatile unsigned long *)0x4002C000))
@@ -403,7 +384,7 @@
 
 //*****************************************************************************
 //
-// Quadrature Encoder Interface (QEI1)
+// QEI registers (QEI1)
 //
 //*****************************************************************************
 #define QEI1_CTL_R              (*((volatile unsigned long *)0x4002D000))
@@ -420,7 +401,7 @@
 
 //*****************************************************************************
 //
-// General-Purpose Timers (TIMER0)
+// Timer registers (TIMER0)
 //
 //*****************************************************************************
 #define TIMER0_CFG_R            (*((volatile unsigned long *)0x40030000))
@@ -444,7 +425,7 @@
 
 //*****************************************************************************
 //
-// General-Purpose Timers (TIMER1)
+// Timer registers (TIMER1)
 //
 //*****************************************************************************
 #define TIMER1_CFG_R            (*((volatile unsigned long *)0x40031000))
@@ -468,7 +449,7 @@
 
 //*****************************************************************************
 //
-// General-Purpose Timers (TIMER2)
+// Timer registers (TIMER2)
 //
 //*****************************************************************************
 #define TIMER2_CFG_R            (*((volatile unsigned long *)0x40032000))
@@ -492,7 +473,7 @@
 
 //*****************************************************************************
 //
-// General-Purpose Timers (TIMER3)
+// Timer registers (TIMER3)
 //
 //*****************************************************************************
 #define TIMER3_CFG_R            (*((volatile unsigned long *)0x40033000))
@@ -516,40 +497,40 @@
 
 //*****************************************************************************
 //
-// Analog-to-Digital Converter (ADC)
+// ADC registers (ADC0)
 //
 //*****************************************************************************
-#define ADC_ACTSS_R             (*((volatile unsigned long *)0x40038000))
-#define ADC_RIS_R               (*((volatile unsigned long *)0x40038004))
-#define ADC_IM_R                (*((volatile unsigned long *)0x40038008))
-#define ADC_ISC_R               (*((volatile unsigned long *)0x4003800C))
-#define ADC_OSTAT_R             (*((volatile unsigned long *)0x40038010))
-#define ADC_EMUX_R              (*((volatile unsigned long *)0x40038014))
-#define ADC_USTAT_R             (*((volatile unsigned long *)0x40038018))
-#define ADC_SSPRI_R             (*((volatile unsigned long *)0x40038020))
-#define ADC_PSSI_R              (*((volatile unsigned long *)0x40038028))
-#define ADC_SAC_R               (*((volatile unsigned long *)0x40038030))
-#define ADC_SSMUX0_R            (*((volatile unsigned long *)0x40038040))
-#define ADC_SSCTL0_R            (*((volatile unsigned long *)0x40038044))
-#define ADC_SSFIFO0_R           (*((volatile unsigned long *)0x40038048))
-#define ADC_SSFSTAT0_R          (*((volatile unsigned long *)0x4003804C))
-#define ADC_SSMUX1_R            (*((volatile unsigned long *)0x40038060))
-#define ADC_SSCTL1_R            (*((volatile unsigned long *)0x40038064))
-#define ADC_SSFIFO1_R           (*((volatile unsigned long *)0x40038068))
-#define ADC_SSFSTAT1_R          (*((volatile unsigned long *)0x4003806C))
-#define ADC_SSMUX2_R            (*((volatile unsigned long *)0x40038080))
-#define ADC_SSCTL2_R            (*((volatile unsigned long *)0x40038084))
-#define ADC_SSFIFO2_R           (*((volatile unsigned long *)0x40038088))
-#define ADC_SSFSTAT2_R          (*((volatile unsigned long *)0x4003808C))
-#define ADC_SSMUX3_R            (*((volatile unsigned long *)0x400380A0))
-#define ADC_SSCTL3_R            (*((volatile unsigned long *)0x400380A4))
-#define ADC_SSFIFO3_R           (*((volatile unsigned long *)0x400380A8))
-#define ADC_SSFSTAT3_R          (*((volatile unsigned long *)0x400380AC))
-#define ADC_TMLB_R              (*((volatile unsigned long *)0x40038100))
+#define ADC0_ACTSS_R            (*((volatile unsigned long *)0x40038000))
+#define ADC0_RIS_R              (*((volatile unsigned long *)0x40038004))
+#define ADC0_IM_R               (*((volatile unsigned long *)0x40038008))
+#define ADC0_ISC_R              (*((volatile unsigned long *)0x4003800C))
+#define ADC0_OSTAT_R            (*((volatile unsigned long *)0x40038010))
+#define ADC0_EMUX_R             (*((volatile unsigned long *)0x40038014))
+#define ADC0_USTAT_R            (*((volatile unsigned long *)0x40038018))
+#define ADC0_SSPRI_R            (*((volatile unsigned long *)0x40038020))
+#define ADC0_PSSI_R             (*((volatile unsigned long *)0x40038028))
+#define ADC0_SAC_R              (*((volatile unsigned long *)0x40038030))
+#define ADC0_SSMUX0_R           (*((volatile unsigned long *)0x40038040))
+#define ADC0_SSCTL0_R           (*((volatile unsigned long *)0x40038044))
+#define ADC0_SSFIFO0_R          (*((volatile unsigned long *)0x40038048))
+#define ADC0_SSFSTAT0_R         (*((volatile unsigned long *)0x4003804C))
+#define ADC0_SSMUX1_R           (*((volatile unsigned long *)0x40038060))
+#define ADC0_SSCTL1_R           (*((volatile unsigned long *)0x40038064))
+#define ADC0_SSFIFO1_R          (*((volatile unsigned long *)0x40038068))
+#define ADC0_SSFSTAT1_R         (*((volatile unsigned long *)0x4003806C))
+#define ADC0_SSMUX2_R           (*((volatile unsigned long *)0x40038080))
+#define ADC0_SSCTL2_R           (*((volatile unsigned long *)0x40038084))
+#define ADC0_SSFIFO2_R          (*((volatile unsigned long *)0x40038088))
+#define ADC0_SSFSTAT2_R         (*((volatile unsigned long *)0x4003808C))
+#define ADC0_SSMUX3_R           (*((volatile unsigned long *)0x400380A0))
+#define ADC0_SSCTL3_R           (*((volatile unsigned long *)0x400380A4))
+#define ADC0_SSFIFO3_R          (*((volatile unsigned long *)0x400380A8))
+#define ADC0_SSFSTAT3_R         (*((volatile unsigned long *)0x400380AC))
+#define ADC0_TMLB_R             (*((volatile unsigned long *)0x40038100))
 
 //*****************************************************************************
 //
-// Analog Comparator (COMP)
+// Comparator registers (COMP)
 //
 //*****************************************************************************
 #define COMP_ACMIS_R            (*((volatile unsigned long *)0x4003C000))
@@ -561,7 +542,7 @@
 
 //*****************************************************************************
 //
-// Controller Area Network (CAN0) Module
+// CAN registers (CAN0)
 //
 //*****************************************************************************
 #define CAN0_CTL_R              (*((volatile unsigned long *)0x40040000))
@@ -604,30 +585,17 @@
 
 //*****************************************************************************
 //
-// Ethernet Controller (MAC)
+// Ethernet MAC registers (MAC)
 //
 //*****************************************************************************
-#define MAC_MR0_R               (*((volatile unsigned long *)0x40048000))
 #define MAC_RIS_R               (*((volatile unsigned long *)0x40048000))
 #define MAC_IACK_R              (*((volatile unsigned long *)0x40048000))
-#define MAC_MR1_R               (*((volatile unsigned long *)0x40048001))
-#define MAC_MR2_R               (*((volatile unsigned long *)0x40048002))
-#define MAC_MR3_R               (*((volatile unsigned long *)0x40048003))
 #define MAC_IM_R                (*((volatile unsigned long *)0x40048004))
-#define MAC_MR4_R               (*((volatile unsigned long *)0x40048004))
-#define MAC_MR5_R               (*((volatile unsigned long *)0x40048005))
-#define MAC_MR6_R               (*((volatile unsigned long *)0x40048006))
 #define MAC_RCTL_R              (*((volatile unsigned long *)0x40048008))
 #define MAC_TCTL_R              (*((volatile unsigned long *)0x4004800C))
 #define MAC_DATA_R              (*((volatile unsigned long *)0x40048010))
-#define MAC_MR16_R              (*((volatile unsigned long *)0x40048010))
-#define MAC_MR17_R              (*((volatile unsigned long *)0x40048011))
-#define MAC_MR18_R              (*((volatile unsigned long *)0x40048012))
-#define MAC_MR19_R              (*((volatile unsigned long *)0x40048013))
 #define MAC_IA0_R               (*((volatile unsigned long *)0x40048014))
-#define MAC_MR23_R              (*((volatile unsigned long *)0x40048017))
 #define MAC_IA1_R               (*((volatile unsigned long *)0x40048018))
-#define MAC_MR24_R              (*((volatile unsigned long *)0x40048018))
 #define MAC_THR_R               (*((volatile unsigned long *)0x4004801C))
 #define MAC_MCTL_R              (*((volatile unsigned long *)0x40048020))
 #define MAC_MDV_R               (*((volatile unsigned long *)0x40048024))
@@ -639,7 +607,41 @@
 
 //*****************************************************************************
 //
-// Hibernation Module (HIB)
+// Ethernet Controller PHY registers (MAC)
+//
+//*****************************************************************************
+#define PHY_MR0                 0x00000000  // Ethernet PHY Management Register
+                                            // 0 - Control
+#define PHY_MR1                 0x00000001  // Ethernet PHY Management Register
+                                            // 1 - Status
+#define PHY_MR2                 0x00000002  // Ethernet PHY Management Register
+                                            // 2 - PHY Identifier 1
+#define PHY_MR3                 0x00000003  // Ethernet PHY Management Register
+                                            // 3 - PHY Identifier 2
+#define PHY_MR4                 0x00000004  // Ethernet PHY Management Register
+                                            // 4 - Auto-Negotiation
+                                            // Advertisement
+#define PHY_MR5                 0x00000005  // Ethernet PHY Management Register
+                                            // 5 - Auto-Negotiation Link
+                                            // Partner Base Page Ability
+#define PHY_MR6                 0x00000006  // Ethernet PHY Management Register
+                                            // 6 - Auto-Negotiation Expansion
+#define PHY_MR16                0x00000010  // Ethernet PHY Management Register
+                                            // 16 - Vendor-Specific
+#define PHY_MR17                0x00000011  // Ethernet PHY Management Register
+                                            // 17 - Mode Control/Status
+#define PHY_MR18                0x00000012  // Ethernet PHY Management Register
+                                            // 18 - Diagnostic
+#define PHY_MR19                0x00000013  // Ethernet PHY Management Register
+                                            // 19 - Transceiver Control
+#define PHY_MR23                0x00000017  // Ethernet PHY Management Register
+                                            // 23 - LED Configuration
+#define PHY_MR24                0x00000018  // Ethernet PHY Management Register
+                                            // 24 -MDI/MDIX Control
+
+//*****************************************************************************
+//
+// Hibernation module registers (HIB)
 //
 //*****************************************************************************
 #define HIB_RTCC_R              (*((volatile unsigned long *)0x400FC000))
@@ -656,7 +658,7 @@
 
 //*****************************************************************************
 //
-// Internal Memory (FLASH)
+// FLASH registers (FLASH CTRL)
 //
 //*****************************************************************************
 #define FLASH_FMA_R             (*((volatile unsigned long *)0x400FD000))
@@ -680,7 +682,7 @@
 
 //*****************************************************************************
 //
-// System Control (SYSCTL)
+// System Control registers (SYSCTL)
 //
 //*****************************************************************************
 #define SYSCTL_DID0_R           (*((volatile unsigned long *)0x400FE000))
@@ -715,7 +717,7 @@
 
 //*****************************************************************************
 //
-// Nested Vectored Interrupt Ctrl (NVIC)
+// NVIC registers (NVIC)
 //
 //*****************************************************************************
 #define NVIC_INT_TYPE_R         (*((volatile unsigned long *)0xE000E004))
@@ -762,8 +764,14 @@
 #define NVIC_MPU_TYPE_R         (*((volatile unsigned long *)0xE000ED90))
 #define NVIC_MPU_CTRL_R         (*((volatile unsigned long *)0xE000ED94))
 #define NVIC_MPU_NUMBER_R       (*((volatile unsigned long *)0xE000ED98))
-#define NVIC_MPU_R              (*((volatile unsigned long *)0xE000ED9C))
+#define NVIC_MPU_BASE_R         (*((volatile unsigned long *)0xE000ED9C))
 #define NVIC_MPU_ATTR_R         (*((volatile unsigned long *)0xE000EDA0))
+#define NVIC_MPU_BASE1_R        (*((volatile unsigned long *)0xE000EDA4))
+#define NVIC_MPU_ATTR1_R        (*((volatile unsigned long *)0xE000EDA8))
+#define NVIC_MPU_BASE2_R        (*((volatile unsigned long *)0xE000EDAC))
+#define NVIC_MPU_ATTR2_R        (*((volatile unsigned long *)0xE000EDB0))
+#define NVIC_MPU_BASE3_R        (*((volatile unsigned long *)0xE000EDB4))
+#define NVIC_MPU_ATTR3_R        (*((volatile unsigned long *)0xE000EDB8))
 #define NVIC_DBG_CTRL_R         (*((volatile unsigned long *)0xE000EDF0))
 #define NVIC_DBG_XFER_R         (*((volatile unsigned long *)0xE000EDF4))
 #define NVIC_DBG_DATA_R         (*((volatile unsigned long *)0xE000EDF8))
@@ -775,7 +783,7 @@
 // The following are defines for the bit fields in the WDT_O_LOAD register.
 //
 //*****************************************************************************
-#define WDT_LOAD_M              0xFFFFFFFF  // Watchdog Load Value.
+#define WDT_LOAD_M              0xFFFFFFFF  // Watchdog Load Value
 #define WDT_LOAD_S              0
 
 //*****************************************************************************
@@ -783,7 +791,7 @@
 // The following are defines for the bit fields in the WDT_O_VALUE register.
 //
 //*****************************************************************************
-#define WDT_VALUE_M             0xFFFFFFFF  // Watchdog Value.
+#define WDT_VALUE_M             0xFFFFFFFF  // Watchdog Value
 #define WDT_VALUE_S             0
 
 //*****************************************************************************
@@ -791,15 +799,15 @@
 // The following are defines for the bit fields in the WDT_O_CTL register.
 //
 //*****************************************************************************
-#define WDT_CTL_RESEN           0x00000002  // Watchdog Reset Enable.
-#define WDT_CTL_INTEN           0x00000001  // Watchdog Interrupt Enable.
+#define WDT_CTL_RESEN           0x00000002  // Watchdog Reset Enable
+#define WDT_CTL_INTEN           0x00000001  // Watchdog Interrupt Enable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the WDT_O_ICR register.
 //
 //*****************************************************************************
-#define WDT_ICR_M               0xFFFFFFFF  // Watchdog Interrupt Clear.
+#define WDT_ICR_M               0xFFFFFFFF  // Watchdog Interrupt Clear
 #define WDT_ICR_S               0
 
 //*****************************************************************************
@@ -807,40 +815,42 @@
 // The following are defines for the bit fields in the WDT_O_RIS register.
 //
 //*****************************************************************************
-#define WDT_RIS_WDTRIS          0x00000001  // Watchdog Raw Interrupt Status.
+#define WDT_RIS_WDTRIS          0x00000001  // Watchdog Raw Interrupt Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the WDT_O_MIS register.
 //
 //*****************************************************************************
-#define WDT_MIS_WDTMIS          0x00000001  // Watchdog Masked Interrupt
-                                            // Status.
+#define WDT_MIS_WDTMIS          0x00000001  // Watchdog Masked Interrupt Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the WDT_O_TEST register.
 //
 //*****************************************************************************
-#define WDT_TEST_STALL          0x00000100  // Watchdog Stall Enable.
+#define WDT_TEST_STALL          0x00000100  // Watchdog Stall Enable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the WDT_O_LOCK register.
 //
 //*****************************************************************************
-#define WDT_LOCK_M              0xFFFFFFFF  // Watchdog Lock.
+#define WDT_LOCK_M              0xFFFFFFFF  // Watchdog Lock
 #define WDT_LOCK_UNLOCKED       0x00000000  // Unlocked
 #define WDT_LOCK_LOCKED         0x00000001  // Locked
+#define WDT_LOCK_UNLOCK         0x1ACCE551  // Unlocks the watchdog timer
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the GPIO_O_LOCK register.
 //
 //*****************************************************************************
-#define GPIO_LOCK_M             0xFFFFFFFF  // GPIO Lock.
-#define GPIO_LOCK_UNLOCKED      0x00000000  // unlocked
-#define GPIO_LOCK_LOCKED        0x00000001  // locked
+#define GPIO_LOCK_M             0xFFFFFFFF  // GPIO Lock
+#define GPIO_LOCK_UNLOCKED      0x00000000  // The GPIOCR register is unlocked
+                                            // and may be modified
+#define GPIO_LOCK_LOCKED        0x00000001  // The GPIOCR register is locked
+                                            // and may not be modified
 #define GPIO_LOCK_KEY           0x1ACCE551  // Unlocks the GPIO_CR register
 
 //*****************************************************************************
@@ -848,15 +858,15 @@
 // The following are defines for the bit fields in the SSI_O_CR0 register.
 //
 //*****************************************************************************
-#define SSI_CR0_SCR_M           0x0000FF00  // SSI Serial Clock Rate.
-#define SSI_CR0_SPH             0x00000080  // SSI Serial Clock Phase.
-#define SSI_CR0_SPO             0x00000040  // SSI Serial Clock Polarity.
-#define SSI_CR0_FRF_M           0x00000030  // SSI Frame Format Select.
+#define SSI_CR0_SCR_M           0x0000FF00  // SSI Serial Clock Rate
+#define SSI_CR0_SPH             0x00000080  // SSI Serial Clock Phase
+#define SSI_CR0_SPO             0x00000040  // SSI Serial Clock Polarity
+#define SSI_CR0_FRF_M           0x00000030  // SSI Frame Format Select
 #define SSI_CR0_FRF_MOTO        0x00000000  // Freescale SPI Frame Format
 #define SSI_CR0_FRF_TI          0x00000010  // Texas Instruments Synchronous
                                             // Serial Frame Format
 #define SSI_CR0_FRF_NMW         0x00000020  // MICROWIRE Frame Format
-#define SSI_CR0_DSS_M           0x0000000F  // SSI Data Size Select.
+#define SSI_CR0_DSS_M           0x0000000F  // SSI Data Size Select
 #define SSI_CR0_DSS_4           0x00000003  // 4-bit data
 #define SSI_CR0_DSS_5           0x00000004  // 5-bit data
 #define SSI_CR0_DSS_6           0x00000005  // 6-bit data
@@ -877,18 +887,18 @@
 // The following are defines for the bit fields in the SSI_O_CR1 register.
 //
 //*****************************************************************************
-#define SSI_CR1_SOD             0x00000008  // SSI Slave Mode Output Disable.
-#define SSI_CR1_MS              0x00000004  // SSI Master/Slave Select.
+#define SSI_CR1_SOD             0x00000008  // SSI Slave Mode Output Disable
+#define SSI_CR1_MS              0x00000004  // SSI Master/Slave Select
 #define SSI_CR1_SSE             0x00000002  // SSI Synchronous Serial Port
-                                            // Enable.
-#define SSI_CR1_LBM             0x00000001  // SSI Loopback Mode.
+                                            // Enable
+#define SSI_CR1_LBM             0x00000001  // SSI Loopback Mode
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SSI_O_DR register.
 //
 //*****************************************************************************
-#define SSI_DR_DATA_M           0x0000FFFF  // SSI Receive/Transmit Data.
+#define SSI_DR_DATA_M           0x0000FFFF  // SSI Receive/Transmit Data
 #define SSI_DR_DATA_S           0
 
 //*****************************************************************************
@@ -896,18 +906,18 @@
 // The following are defines for the bit fields in the SSI_O_SR register.
 //
 //*****************************************************************************
-#define SSI_SR_BSY              0x00000010  // SSI Busy Bit.
-#define SSI_SR_RFF              0x00000008  // SSI Receive FIFO Full.
-#define SSI_SR_RNE              0x00000004  // SSI Receive FIFO Not Empty.
-#define SSI_SR_TNF              0x00000002  // SSI Transmit FIFO Not Full.
-#define SSI_SR_TFE              0x00000001  // SSI Transmit FIFO Empty.
+#define SSI_SR_BSY              0x00000010  // SSI Busy Bit
+#define SSI_SR_RFF              0x00000008  // SSI Receive FIFO Full
+#define SSI_SR_RNE              0x00000004  // SSI Receive FIFO Not Empty
+#define SSI_SR_TNF              0x00000002  // SSI Transmit FIFO Not Full
+#define SSI_SR_TFE              0x00000001  // SSI Transmit FIFO Empty
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SSI_O_CPSR register.
 //
 //*****************************************************************************
-#define SSI_CPSR_CPSDVSR_M      0x000000FF  // SSI Clock Prescale Divisor.
+#define SSI_CPSR_CPSDVSR_M      0x000000FF  // SSI Clock Prescale Divisor
 #define SSI_CPSR_CPSDVSR_S      0
 
 //*****************************************************************************
@@ -915,13 +925,12 @@
 // The following are defines for the bit fields in the SSI_O_IM register.
 //
 //*****************************************************************************
-#define SSI_IM_TXIM             0x00000008  // SSI Transmit FIFO Interrupt
-                                            // Mask.
-#define SSI_IM_RXIM             0x00000004  // SSI Receive FIFO Interrupt Mask.
+#define SSI_IM_TXIM             0x00000008  // SSI Transmit FIFO Interrupt Mask
+#define SSI_IM_RXIM             0x00000004  // SSI Receive FIFO Interrupt Mask
 #define SSI_IM_RTIM             0x00000002  // SSI Receive Time-Out Interrupt
-                                            // Mask.
+                                            // Mask
 #define SSI_IM_RORIM            0x00000001  // SSI Receive Overrun Interrupt
-                                            // Mask.
+                                            // Mask
 
 //*****************************************************************************
 //
@@ -929,13 +938,13 @@
 //
 //*****************************************************************************
 #define SSI_RIS_TXRIS           0x00000008  // SSI Transmit FIFO Raw Interrupt
-                                            // Status.
+                                            // Status
 #define SSI_RIS_RXRIS           0x00000004  // SSI Receive FIFO Raw Interrupt
-                                            // Status.
+                                            // Status
 #define SSI_RIS_RTRIS           0x00000002  // SSI Receive Time-Out Raw
-                                            // Interrupt Status.
+                                            // Interrupt Status
 #define SSI_RIS_RORRIS          0x00000001  // SSI Receive Overrun Raw
-                                            // Interrupt Status.
+                                            // Interrupt Status
 
 //*****************************************************************************
 //
@@ -943,13 +952,13 @@
 //
 //*****************************************************************************
 #define SSI_MIS_TXMIS           0x00000008  // SSI Transmit FIFO Masked
-                                            // Interrupt Status.
+                                            // Interrupt Status
 #define SSI_MIS_RXMIS           0x00000004  // SSI Receive FIFO Masked
-                                            // Interrupt Status.
+                                            // Interrupt Status
 #define SSI_MIS_RTMIS           0x00000002  // SSI Receive Time-Out Masked
-                                            // Interrupt Status.
+                                            // Interrupt Status
 #define SSI_MIS_RORMIS          0x00000001  // SSI Receive Overrun Masked
-                                            // Interrupt Status.
+                                            // Interrupt Status
 
 //*****************************************************************************
 //
@@ -957,20 +966,20 @@
 //
 //*****************************************************************************
 #define SSI_ICR_RTIC            0x00000002  // SSI Receive Time-Out Interrupt
-                                            // Clear.
+                                            // Clear
 #define SSI_ICR_RORIC           0x00000001  // SSI Receive Overrun Interrupt
-                                            // Clear.
+                                            // Clear
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the UART_O_DR register.
 //
 //*****************************************************************************
-#define UART_DR_OE              0x00000800  // UART Overrun Error.
-#define UART_DR_BE              0x00000400  // UART Break Error.
-#define UART_DR_PE              0x00000200  // UART Parity Error.
-#define UART_DR_FE              0x00000100  // UART Framing Error.
-#define UART_DR_DATA_M          0x000000FF  // Data Transmitted or Received.
+#define UART_DR_OE              0x00000800  // UART Overrun Error
+#define UART_DR_BE              0x00000400  // UART Break Error
+#define UART_DR_PE              0x00000200  // UART Parity Error
+#define UART_DR_FE              0x00000100  // UART Framing Error
+#define UART_DR_DATA_M          0x000000FF  // Data Transmitted or Received
 #define UART_DR_DATA_S          0
 
 //*****************************************************************************
@@ -978,17 +987,17 @@
 // The following are defines for the bit fields in the UART_O_RSR register.
 //
 //*****************************************************************************
-#define UART_RSR_OE             0x00000008  // UART Overrun Error.
-#define UART_RSR_BE             0x00000004  // UART Break Error.
-#define UART_RSR_PE             0x00000002  // UART Parity Error.
-#define UART_RSR_FE             0x00000001  // UART Framing Error.
+#define UART_RSR_OE             0x00000008  // UART Overrun Error
+#define UART_RSR_BE             0x00000004  // UART Break Error
+#define UART_RSR_PE             0x00000002  // UART Parity Error
+#define UART_RSR_FE             0x00000001  // UART Framing Error
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the UART_O_ECR register.
 //
 //*****************************************************************************
-#define UART_ECR_DATA_M         0x000000FF  // Error Clear.
+#define UART_ECR_DATA_M         0x000000FF  // Error Clear
 #define UART_ECR_DATA_S         0
 
 //*****************************************************************************
@@ -996,18 +1005,18 @@
 // The following are defines for the bit fields in the UART_O_FR register.
 //
 //*****************************************************************************
-#define UART_FR_TXFE            0x00000080  // UART Transmit FIFO Empty.
-#define UART_FR_RXFF            0x00000040  // UART Receive FIFO Full.
-#define UART_FR_TXFF            0x00000020  // UART Transmit FIFO Full.
-#define UART_FR_RXFE            0x00000010  // UART Receive FIFO Empty.
-#define UART_FR_BUSY            0x00000008  // UART Busy.
+#define UART_FR_TXFE            0x00000080  // UART Transmit FIFO Empty
+#define UART_FR_RXFF            0x00000040  // UART Receive FIFO Full
+#define UART_FR_TXFF            0x00000020  // UART Transmit FIFO Full
+#define UART_FR_RXFE            0x00000010  // UART Receive FIFO Empty
+#define UART_FR_BUSY            0x00000008  // UART Busy
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the UART_O_ILPR register.
 //
 //*****************************************************************************
-#define UART_ILPR_ILPDVSR_M     0x000000FF  // IrDA Low-Power Divisor.
+#define UART_ILPR_ILPDVSR_M     0x000000FF  // IrDA Low-Power Divisor
 #define UART_ILPR_ILPDVSR_S     0
 
 //*****************************************************************************
@@ -1015,7 +1024,7 @@
 // The following are defines for the bit fields in the UART_O_IBRD register.
 //
 //*****************************************************************************
-#define UART_IBRD_DIVINT_M      0x0000FFFF  // Integer Baud-Rate Divisor.
+#define UART_IBRD_DIVINT_M      0x0000FFFF  // Integer Baud-Rate Divisor
 #define UART_IBRD_DIVINT_S      0
 
 //*****************************************************************************
@@ -1023,7 +1032,7 @@
 // The following are defines for the bit fields in the UART_O_FBRD register.
 //
 //*****************************************************************************
-#define UART_FBRD_DIVFRAC_M     0x0000003F  // Fractional Baud-Rate Divisor.
+#define UART_FBRD_DIVFRAC_M     0x0000003F  // Fractional Baud-Rate Divisor
 #define UART_FBRD_DIVFRAC_S     0
 
 //*****************************************************************************
@@ -1031,29 +1040,29 @@
 // The following are defines for the bit fields in the UART_O_LCRH register.
 //
 //*****************************************************************************
-#define UART_LCRH_SPS           0x00000080  // UART Stick Parity Select.
-#define UART_LCRH_WLEN_M        0x00000060  // UART Word Length.
+#define UART_LCRH_SPS           0x00000080  // UART Stick Parity Select
+#define UART_LCRH_WLEN_M        0x00000060  // UART Word Length
 #define UART_LCRH_WLEN_5        0x00000000  // 5 bits (default)
 #define UART_LCRH_WLEN_6        0x00000020  // 6 bits
 #define UART_LCRH_WLEN_7        0x00000040  // 7 bits
 #define UART_LCRH_WLEN_8        0x00000060  // 8 bits
-#define UART_LCRH_FEN           0x00000010  // UART Enable FIFOs.
-#define UART_LCRH_STP2          0x00000008  // UART Two Stop Bits Select.
-#define UART_LCRH_EPS           0x00000004  // UART Even Parity Select.
-#define UART_LCRH_PEN           0x00000002  // UART Parity Enable.
-#define UART_LCRH_BRK           0x00000001  // UART Send Break.
+#define UART_LCRH_FEN           0x00000010  // UART Enable FIFOs
+#define UART_LCRH_STP2          0x00000008  // UART Two Stop Bits Select
+#define UART_LCRH_EPS           0x00000004  // UART Even Parity Select
+#define UART_LCRH_PEN           0x00000002  // UART Parity Enable
+#define UART_LCRH_BRK           0x00000001  // UART Send Break
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the UART_O_CTL register.
 //
 //*****************************************************************************
-#define UART_CTL_RXE            0x00000200  // UART Receive Enable.
-#define UART_CTL_TXE            0x00000100  // UART Transmit Enable.
-#define UART_CTL_LBE            0x00000080  // UART Loop Back Enable.
-#define UART_CTL_SIRLP          0x00000004  // UART SIR Low Power Mode.
-#define UART_CTL_SIREN          0x00000002  // UART SIR Enable.
-#define UART_CTL_UARTEN         0x00000001  // UART Enable.
+#define UART_CTL_RXE            0x00000200  // UART Receive Enable
+#define UART_CTL_TXE            0x00000100  // UART Transmit Enable
+#define UART_CTL_LBE            0x00000080  // UART Loop Back Enable
+#define UART_CTL_SIRLP          0x00000004  // UART SIR Low-Power Mode
+#define UART_CTL_SIREN          0x00000002  // UART SIR Enable
+#define UART_CTL_UARTEN         0x00000001  // UART Enable
 
 //*****************************************************************************
 //
@@ -1061,19 +1070,19 @@
 //
 //*****************************************************************************
 #define UART_IFLS_RX_M          0x00000038  // UART Receive Interrupt FIFO
-                                            // Level Select.
-#define UART_IFLS_RX1_8         0x00000000  // RX FIFO <= 1/8 full
-#define UART_IFLS_RX2_8         0x00000008  // RX FIFO <= 1/4 full
-#define UART_IFLS_RX4_8         0x00000010  // RX FIFO <= 1/2 full (default)
-#define UART_IFLS_RX6_8         0x00000018  // RX FIFO <= 3/4 full
-#define UART_IFLS_RX7_8         0x00000020  // RX FIFO <= 7/8 full
+                                            // Level Select
+#define UART_IFLS_RX1_8         0x00000000  // RX FIFO >= 1/8 full
+#define UART_IFLS_RX2_8         0x00000008  // RX FIFO >= 1/4 full
+#define UART_IFLS_RX4_8         0x00000010  // RX FIFO >= 1/2 full (default)
+#define UART_IFLS_RX6_8         0x00000018  // RX FIFO >= 3/4 full
+#define UART_IFLS_RX7_8         0x00000020  // RX FIFO >= 7/8 full
 #define UART_IFLS_TX_M          0x00000007  // UART Transmit Interrupt FIFO
-                                            // Level Select.
-#define UART_IFLS_TX1_8         0x00000000  // TX FIFO >= 1/8 full
-#define UART_IFLS_TX2_8         0x00000001  // TX FIFO >= 1/4 full
-#define UART_IFLS_TX4_8         0x00000002  // TX FIFO >= 1/2 full (default)
-#define UART_IFLS_TX6_8         0x00000003  // TX FIFO >= 3/4 full
-#define UART_IFLS_TX7_8         0x00000004  // TX FIFO >= 7/8 full
+                                            // Level Select
+#define UART_IFLS_TX1_8         0x00000000  // TX FIFO <= 1/8 full
+#define UART_IFLS_TX2_8         0x00000001  // TX FIFO <= 1/4 full
+#define UART_IFLS_TX4_8         0x00000002  // TX FIFO <= 1/2 full (default)
+#define UART_IFLS_TX6_8         0x00000003  // TX FIFO <= 3/4 full
+#define UART_IFLS_TX7_8         0x00000004  // TX FIFO <= 7/8 full
 
 //*****************************************************************************
 //
@@ -1081,16 +1090,15 @@
 //
 //*****************************************************************************
 #define UART_IM_OEIM            0x00000400  // UART Overrun Error Interrupt
-                                            // Mask.
-#define UART_IM_BEIM            0x00000200  // UART Break Error Interrupt Mask.
-#define UART_IM_PEIM            0x00000100  // UART Parity Error Interrupt
-                                            // Mask.
+                                            // Mask
+#define UART_IM_BEIM            0x00000200  // UART Break Error Interrupt Mask
+#define UART_IM_PEIM            0x00000100  // UART Parity Error Interrupt Mask
 #define UART_IM_FEIM            0x00000080  // UART Framing Error Interrupt
-                                            // Mask.
+                                            // Mask
 #define UART_IM_RTIM            0x00000040  // UART Receive Time-Out Interrupt
-                                            // Mask.
-#define UART_IM_TXIM            0x00000020  // UART Transmit Interrupt Mask.
-#define UART_IM_RXIM            0x00000010  // UART Receive Interrupt Mask.
+                                            // Mask
+#define UART_IM_TXIM            0x00000020  // UART Transmit Interrupt Mask
+#define UART_IM_RXIM            0x00000010  // UART Receive Interrupt Mask
 
 //*****************************************************************************
 //
@@ -1098,19 +1106,19 @@
 //
 //*****************************************************************************
 #define UART_RIS_OERIS          0x00000400  // UART Overrun Error Raw Interrupt
-                                            // Status.
+                                            // Status
 #define UART_RIS_BERIS          0x00000200  // UART Break Error Raw Interrupt
-                                            // Status.
+                                            // Status
 #define UART_RIS_PERIS          0x00000100  // UART Parity Error Raw Interrupt
-                                            // Status.
+                                            // Status
 #define UART_RIS_FERIS          0x00000080  // UART Framing Error Raw Interrupt
-                                            // Status.
+                                            // Status
 #define UART_RIS_RTRIS          0x00000040  // UART Receive Time-Out Raw
-                                            // Interrupt Status.
+                                            // Interrupt Status
 #define UART_RIS_TXRIS          0x00000020  // UART Transmit Raw Interrupt
-                                            // Status.
+                                            // Status
 #define UART_RIS_RXRIS          0x00000010  // UART Receive Raw Interrupt
-                                            // Status.
+                                            // Status
 
 //*****************************************************************************
 //
@@ -1118,41 +1126,40 @@
 //
 //*****************************************************************************
 #define UART_MIS_OEMIS          0x00000400  // UART Overrun Error Masked
-                                            // Interrupt Status.
+                                            // Interrupt Status
 #define UART_MIS_BEMIS          0x00000200  // UART Break Error Masked
-                                            // Interrupt Status.
+                                            // Interrupt Status
 #define UART_MIS_PEMIS          0x00000100  // UART Parity Error Masked
-                                            // Interrupt Status.
+                                            // Interrupt Status
 #define UART_MIS_FEMIS          0x00000080  // UART Framing Error Masked
-                                            // Interrupt Status.
+                                            // Interrupt Status
 #define UART_MIS_RTMIS          0x00000040  // UART Receive Time-Out Masked
-                                            // Interrupt Status.
+                                            // Interrupt Status
 #define UART_MIS_TXMIS          0x00000020  // UART Transmit Masked Interrupt
-                                            // Status.
+                                            // Status
 #define UART_MIS_RXMIS          0x00000010  // UART Receive Masked Interrupt
-                                            // Status.
+                                            // Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the UART_O_ICR register.
 //
 //*****************************************************************************
-#define UART_ICR_OEIC           0x00000400  // Overrun Error Interrupt Clear.
-#define UART_ICR_BEIC           0x00000200  // Break Error Interrupt Clear.
-#define UART_ICR_PEIC           0x00000100  // Parity Error Interrupt Clear.
-#define UART_ICR_FEIC           0x00000080  // Framing Error Interrupt Clear.
-#define UART_ICR_RTIC           0x00000040  // Receive Time-Out Interrupt
-                                            // Clear.
-#define UART_ICR_TXIC           0x00000020  // Transmit Interrupt Clear.
-#define UART_ICR_RXIC           0x00000010  // Receive Interrupt Clear.
+#define UART_ICR_OEIC           0x00000400  // Overrun Error Interrupt Clear
+#define UART_ICR_BEIC           0x00000200  // Break Error Interrupt Clear
+#define UART_ICR_PEIC           0x00000100  // Parity Error Interrupt Clear
+#define UART_ICR_FEIC           0x00000080  // Framing Error Interrupt Clear
+#define UART_ICR_RTIC           0x00000040  // Receive Time-Out Interrupt Clear
+#define UART_ICR_TXIC           0x00000020  // Transmit Interrupt Clear
+#define UART_ICR_RXIC           0x00000010  // Receive Interrupt Clear
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2C_O_MSA register.
 //
 //*****************************************************************************
-#define I2C_MSA_SA_M            0x000000FE  // I2C Slave Address.
-#define I2C_MSA_RS              0x00000001  // Receive not send.
+#define I2C_MSA_SA_M            0x000000FE  // I2C Slave Address
+#define I2C_MSA_RS              0x00000001  // Receive not send
 #define I2C_MSA_SA_S            1
 
 //*****************************************************************************
@@ -1160,7 +1167,7 @@
 // The following are defines for the bit fields in the I2C_O_SOAR register.
 //
 //*****************************************************************************
-#define I2C_SOAR_OAR_M          0x0000007F  // I2C Slave Own Address.
+#define I2C_SOAR_OAR_M          0x0000007F  // I2C Slave Own Address
 #define I2C_SOAR_OAR_S          0
 
 //*****************************************************************************
@@ -1168,34 +1175,34 @@
 // The following are defines for the bit fields in the I2C_O_SCSR register.
 //
 //*****************************************************************************
-#define I2C_SCSR_FBR            0x00000004  // First Byte Received.
-#define I2C_SCSR_TREQ           0x00000002  // Transmit Request.
-#define I2C_SCSR_DA             0x00000001  // Device Active.
-#define I2C_SCSR_RREQ           0x00000001  // Receive Request.
+#define I2C_SCSR_FBR            0x00000004  // First Byte Received
+#define I2C_SCSR_TREQ           0x00000002  // Transmit Request
+#define I2C_SCSR_DA             0x00000001  // Device Active
+#define I2C_SCSR_RREQ           0x00000001  // Receive Request
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2C_O_MCS register.
 //
 //*****************************************************************************
-#define I2C_MCS_BUSBSY          0x00000040  // Bus Busy.
-#define I2C_MCS_IDLE            0x00000020  // I2C Idle.
-#define I2C_MCS_ARBLST          0x00000010  // Arbitration Lost.
-#define I2C_MCS_ACK             0x00000008  // Data Acknowledge Enable.
-#define I2C_MCS_DATACK          0x00000008  // Acknowledge Data.
-#define I2C_MCS_ADRACK          0x00000004  // Acknowledge Address.
-#define I2C_MCS_STOP            0x00000004  // Generate STOP.
-#define I2C_MCS_START           0x00000002  // Generate START.
-#define I2C_MCS_ERROR           0x00000002  // Error.
-#define I2C_MCS_RUN             0x00000001  // I2C Master Enable.
-#define I2C_MCS_BUSY            0x00000001  // I2C Busy.
+#define I2C_MCS_BUSBSY          0x00000040  // Bus Busy
+#define I2C_MCS_IDLE            0x00000020  // I2C Idle
+#define I2C_MCS_ARBLST          0x00000010  // Arbitration Lost
+#define I2C_MCS_ACK             0x00000008  // Data Acknowledge Enable
+#define I2C_MCS_DATACK          0x00000008  // Acknowledge Data
+#define I2C_MCS_ADRACK          0x00000004  // Acknowledge Address
+#define I2C_MCS_STOP            0x00000004  // Generate STOP
+#define I2C_MCS_START           0x00000002  // Generate START
+#define I2C_MCS_ERROR           0x00000002  // Error
+#define I2C_MCS_RUN             0x00000001  // I2C Master Enable
+#define I2C_MCS_BUSY            0x00000001  // I2C Busy
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2C_O_SDR register.
 //
 //*****************************************************************************
-#define I2C_SDR_DATA_M          0x000000FF  // Data for Transfer.
+#define I2C_SDR_DATA_M          0x000000FF  // Data for Transfer
 #define I2C_SDR_DATA_S          0
 
 //*****************************************************************************
@@ -1203,7 +1210,7 @@
 // The following are defines for the bit fields in the I2C_O_MDR register.
 //
 //*****************************************************************************
-#define I2C_MDR_DATA_M          0x000000FF  // Data Transferred.
+#define I2C_MDR_DATA_M          0x000000FF  // Data Transferred
 #define I2C_MDR_DATA_S          0
 
 //*****************************************************************************
@@ -1211,7 +1218,7 @@
 // The following are defines for the bit fields in the I2C_O_MTPR register.
 //
 //*****************************************************************************
-#define I2C_MTPR_TPR_M          0x000000FF  // SCL Clock Period.
+#define I2C_MTPR_TPR_M          0x0000007F  // SCL Clock Period
 #define I2C_MTPR_TPR_S          0
 
 //*****************************************************************************
@@ -1219,377 +1226,360 @@
 // The following are defines for the bit fields in the I2C_O_SIMR register.
 //
 //*****************************************************************************
-#define I2C_SIMR_IM             0x00000001  // Data Interrupt Mask.
+#define I2C_SIMR_DATAIM         0x00000001  // Data Interrupt Mask
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2C_O_SRIS register.
 //
 //*****************************************************************************
-#define I2C_SRIS_RIS            0x00000001  // Data Raw Interrupt Status.
+#define I2C_SRIS_DATARIS        0x00000001  // Data Raw Interrupt Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2C_O_MIMR register.
 //
 //*****************************************************************************
-#define I2C_MIMR_IM             0x00000001  // Interrupt Mask.
+#define I2C_MIMR_IM             0x00000001  // Interrupt Mask
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2C_O_MRIS register.
 //
 //*****************************************************************************
-#define I2C_MRIS_RIS            0x00000001  // Raw Interrupt Status.
+#define I2C_MRIS_RIS            0x00000001  // Raw Interrupt Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2C_O_SMIS register.
 //
 //*****************************************************************************
-#define I2C_SMIS_MIS            0x00000001  // Data Masked Interrupt Status.
+#define I2C_SMIS_DATAMIS        0x00000001  // Data Masked Interrupt Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2C_O_SICR register.
 //
 //*****************************************************************************
-#define I2C_SICR_IC             0x00000001  // Data Interrupt Clear.
+#define I2C_SICR_DATAIC         0x00000001  // Data Interrupt Clear
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2C_O_MMIS register.
 //
 //*****************************************************************************
-#define I2C_MMIS_MIS            0x00000001  // Masked Interrupt Status.
+#define I2C_MMIS_MIS            0x00000001  // Masked Interrupt Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2C_O_MICR register.
 //
 //*****************************************************************************
-#define I2C_MICR_IC             0x00000001  // Interrupt Clear.
+#define I2C_MICR_IC             0x00000001  // Interrupt Clear
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2C_O_MCR register.
 //
 //*****************************************************************************
-#define I2C_MCR_SFE             0x00000020  // I2C Slave Function Enable.
-#define I2C_MCR_MFE             0x00000010  // I2C Master Function Enable.
-#define I2C_MCR_LPBK            0x00000001  // I2C Loopback.
+#define I2C_MCR_SFE             0x00000020  // I2C Slave Function Enable
+#define I2C_MCR_MFE             0x00000010  // I2C Master Function Enable
+#define I2C_MCR_LPBK            0x00000001  // I2C Loopback
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the PWM_O_CTL register.
 //
 //*****************************************************************************
-#define PWM_CTL_GLOBALSYNC2     0x00000004  // Update PWM Generator 2.
-#define PWM_CTL_GLOBALSYNC1     0x00000002  // Update PWM Generator 1.
-#define PWM_CTL_GLOBALSYNC0     0x00000001  // Update PWM Generator 0.
+#define PWM_CTL_GLOBALSYNC2     0x00000004  // Update PWM Generator 2
+#define PWM_CTL_GLOBALSYNC1     0x00000002  // Update PWM Generator 1
+#define PWM_CTL_GLOBALSYNC0     0x00000001  // Update PWM Generator 0
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the PWM_O_SYNC register.
 //
 //*****************************************************************************
-#define PWM_SYNC_SYNC2          0x00000004  // Reset Generator 2 Counter.
-#define PWM_SYNC_SYNC1          0x00000002  // Reset Generator 1 Counter.
-#define PWM_SYNC_SYNC0          0x00000001  // Reset Generator 0 Counter.
+#define PWM_SYNC_SYNC2          0x00000004  // Reset Generator 2 Counter
+#define PWM_SYNC_SYNC1          0x00000002  // Reset Generator 1 Counter
+#define PWM_SYNC_SYNC0          0x00000001  // Reset Generator 0 Counter
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the PWM_O_ENABLE register.
 //
 //*****************************************************************************
-#define PWM_ENABLE_PWM5EN       0x00000020  // PWM5 Output Enable.
-#define PWM_ENABLE_PWM4EN       0x00000010  // PWM4 Output Enable.
-#define PWM_ENABLE_PWM3EN       0x00000008  // PWM3 Output Enable.
-#define PWM_ENABLE_PWM2EN       0x00000004  // PWM2 Output Enable.
-#define PWM_ENABLE_PWM1EN       0x00000002  // PWM1 Output Enable.
-#define PWM_ENABLE_PWM0EN       0x00000001  // PWM0 Output Enable.
+#define PWM_ENABLE_PWM5EN       0x00000020  // PWM5 Output Enable
+#define PWM_ENABLE_PWM4EN       0x00000010  // PWM4 Output Enable
+#define PWM_ENABLE_PWM3EN       0x00000008  // PWM3 Output Enable
+#define PWM_ENABLE_PWM2EN       0x00000004  // PWM2 Output Enable
+#define PWM_ENABLE_PWM1EN       0x00000002  // PWM1 Output Enable
+#define PWM_ENABLE_PWM0EN       0x00000001  // PWM0 Output Enable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the PWM_O_INVERT register.
 //
 //*****************************************************************************
-#define PWM_INVERT_PWM5INV      0x00000020  // Invert PWM5 Signal.
-#define PWM_INVERT_PWM4INV      0x00000010  // Invert PWM4 Signal.
-#define PWM_INVERT_PWM3INV      0x00000008  // Invert PWM3 Signal.
-#define PWM_INVERT_PWM2INV      0x00000004  // Invert PWM2 Signal.
-#define PWM_INVERT_PWM1INV      0x00000002  // Invert PWM1 Signal.
-#define PWM_INVERT_PWM0INV      0x00000001  // Invert PWM0 Signal.
+#define PWM_INVERT_PWM5INV      0x00000020  // Invert PWM5 Signal
+#define PWM_INVERT_PWM4INV      0x00000010  // Invert PWM4 Signal
+#define PWM_INVERT_PWM3INV      0x00000008  // Invert PWM3 Signal
+#define PWM_INVERT_PWM2INV      0x00000004  // Invert PWM2 Signal
+#define PWM_INVERT_PWM1INV      0x00000002  // Invert PWM1 Signal
+#define PWM_INVERT_PWM0INV      0x00000001  // Invert PWM0 Signal
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the PWM_O_FAULT register.
 //
 //*****************************************************************************
-#define PWM_FAULT_FAULT5        0x00000020  // PWM5 Fault.
-#define PWM_FAULT_FAULT4        0x00000010  // PWM4 Fault.
-#define PWM_FAULT_FAULT3        0x00000008  // PWM3 Fault.
-#define PWM_FAULT_FAULT2        0x00000004  // PWM2 Fault.
-#define PWM_FAULT_FAULT1        0x00000002  // PWM1 Fault.
-#define PWM_FAULT_FAULT0        0x00000001  // PWM0 Fault.
+#define PWM_FAULT_FAULT5        0x00000020  // PWM5 Fault
+#define PWM_FAULT_FAULT4        0x00000010  // PWM4 Fault
+#define PWM_FAULT_FAULT3        0x00000008  // PWM3 Fault
+#define PWM_FAULT_FAULT2        0x00000004  // PWM2 Fault
+#define PWM_FAULT_FAULT1        0x00000002  // PWM1 Fault
+#define PWM_FAULT_FAULT0        0x00000001  // PWM0 Fault
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the PWM_O_INTEN register.
 //
 //*****************************************************************************
-#define PWM_INTEN_INTFAULT      0x00010000  // Fault Interrupt Enable.
-#define PWM_INTEN_INTPWM2       0x00000004  // PWM2 Interrupt Enable.
-#define PWM_INTEN_INTPWM1       0x00000002  // PWM1 Interrupt Enable.
-#define PWM_INTEN_INTPWM0       0x00000001  // PWM0 Interrupt Enable.
+#define PWM_INTEN_INTFAULT      0x00010000  // Fault Interrupt Enable
+#define PWM_INTEN_INTPWM2       0x00000004  // PWM2 Interrupt Enable
+#define PWM_INTEN_INTPWM1       0x00000002  // PWM1 Interrupt Enable
+#define PWM_INTEN_INTPWM0       0x00000001  // PWM0 Interrupt Enable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the PWM_O_RIS register.
 //
 //*****************************************************************************
-#define PWM_RIS_INTFAULT        0x00010000  // Fault Interrupt Asserted.
-#define PWM_RIS_INTPWM2         0x00000004  // PWM2 Interrupt Asserted.
-#define PWM_RIS_INTPWM1         0x00000002  // PWM1 Interrupt Asserted.
-#define PWM_RIS_INTPWM0         0x00000001  // PWM0 Interrupt Asserted.
+#define PWM_RIS_INTFAULT        0x00010000  // Fault Interrupt Asserted
+#define PWM_RIS_INTPWM2         0x00000004  // PWM2 Interrupt Asserted
+#define PWM_RIS_INTPWM1         0x00000002  // PWM1 Interrupt Asserted
+#define PWM_RIS_INTPWM0         0x00000001  // PWM0 Interrupt Asserted
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the PWM_O_ISC register.
 //
 //*****************************************************************************
-#define PWM_ISC_INTFAULT        0x00010000  // Fault Interrupt Asserted.
-#define PWM_ISC_INTPWM2         0x00000004  // PWM2 Interrupt Status.
-#define PWM_ISC_INTPWM1         0x00000002  // PWM1 Interrupt Status.
-#define PWM_ISC_INTPWM0         0x00000001  // PWM0 Interrupt Status.
+#define PWM_ISC_INTFAULT        0x00010000  // Fault Interrupt Asserted
+#define PWM_ISC_INTPWM2         0x00000004  // PWM2 Interrupt Status
+#define PWM_ISC_INTPWM1         0x00000002  // PWM1 Interrupt Status
+#define PWM_ISC_INTPWM0         0x00000001  // PWM0 Interrupt Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the PWM_O_STATUS register.
 //
 //*****************************************************************************
-#define PWM_STATUS_FAULT        0x00000001  // Fault Interrupt Status.
+#define PWM_STATUS_FAULT        0x00000001  // Fault Interrupt Status
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the PWM_O_0_CTL,
-// PWM_O_1_CTL, and PWM_O_2_CTL registers.
+// The following are defines for the bit fields in the PWM_O_X_CTL register.
 //
 //*****************************************************************************
-#define PWM_X_CTL_CMPBUPD       0x00000020  // Comparator B Update Mode.
-#define PWM_X_CTL_CMPAUPD       0x00000010  // Comparator A Update Mode.
-#define PWM_X_CTL_LOADUPD       0x00000008  // Load Register Update Mode.
-#define PWM_X_CTL_DEBUG         0x00000004  // Debug Mode.
-#define PWM_X_CTL_MODE          0x00000002  // Counter Mode.
-#define PWM_X_CTL_ENABLE        0x00000001  // PWM Block Enable.
+#define PWM_X_CTL_CMPBUPD       0x00000020  // Comparator B Update Mode
+#define PWM_X_CTL_CMPAUPD       0x00000010  // Comparator A Update Mode
+#define PWM_X_CTL_LOADUPD       0x00000008  // Load Register Update Mode
+#define PWM_X_CTL_DEBUG         0x00000004  // Debug Mode
+#define PWM_X_CTL_MODE          0x00000002  // Counter Mode
+#define PWM_X_CTL_ENABLE        0x00000001  // PWM Block Enable
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the PWM_O_0_INTEN,
-// PWM_O_1_INTEN, and PWM_O_2_INTEN registers.
+// The following are defines for the bit fields in the PWM_O_X_INTEN register.
 //
 //*****************************************************************************
-#define PWM_X_INTEN_TRCMPBD     0x00002000  // Trigger for Counter=Comparator B
-                                            // Down.
-#define PWM_X_INTEN_TRCMPBU     0x00001000  // Trigger for Counter=Comparator B
-                                            // Up.
-#define PWM_X_INTEN_TRCMPAD     0x00000800  // Trigger for Counter=Comparator A
-                                            // Down.
-#define PWM_X_INTEN_TRCMPAU     0x00000400  // Trigger for Counter=Comparator A
-                                            // Up.
-#define PWM_X_INTEN_TRCNTLOAD   0x00000200  // Trigger for Counter=Load.
-#define PWM_X_INTEN_TRCNTZERO   0x00000100  // Trigger for Counter=0.
-#define PWM_X_INTEN_INTCMPBD    0x00000020  // Interrupt for Counter=Comparator
-                                            // B Down.
-#define PWM_X_INTEN_INTCMPBU    0x00000010  // Interrupt for Counter=Comparator
-                                            // B Up.
-#define PWM_X_INTEN_INTCMPAD    0x00000008  // Interrupt for Counter=Comparator
-                                            // A Down.
-#define PWM_X_INTEN_INTCMPAU    0x00000004  // Interrupt for Counter=Comparator
-                                            // A Up.
-#define PWM_X_INTEN_INTCNTLOAD  0x00000002  // Interrupt for Counter=Load.
-#define PWM_X_INTEN_INTCNTZERO  0x00000001  // Interrupt for Counter=0.
+#define PWM_X_INTEN_TRCMPBD     0x00002000  // Trigger for Counter=PWMnCMPB
+                                            // Down
+#define PWM_X_INTEN_TRCMPBU     0x00001000  // Trigger for Counter=PWMnCMPB Up
+#define PWM_X_INTEN_TRCMPAD     0x00000800  // Trigger for Counter=PWMnCMPA
+                                            // Down
+#define PWM_X_INTEN_TRCMPAU     0x00000400  // Trigger for Counter=PWMnCMPA Up
+#define PWM_X_INTEN_TRCNTLOAD   0x00000200  // Trigger for Counter=PWMnLOAD
+#define PWM_X_INTEN_TRCNTZERO   0x00000100  // Trigger for Counter=0
+#define PWM_X_INTEN_INTCMPBD    0x00000020  // Interrupt for Counter=PWMnCMPB
+                                            // Down
+#define PWM_X_INTEN_INTCMPBU    0x00000010  // Interrupt for Counter=PWMnCMPB
+                                            // Up
+#define PWM_X_INTEN_INTCMPAD    0x00000008  // Interrupt for Counter=PWMnCMPA
+                                            // Down
+#define PWM_X_INTEN_INTCMPAU    0x00000004  // Interrupt for Counter=PWMnCMPA
+                                            // Up
+#define PWM_X_INTEN_INTCNTLOAD  0x00000002  // Interrupt for Counter=PWMnLOAD
+#define PWM_X_INTEN_INTCNTZERO  0x00000001  // Interrupt for Counter=0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the PWM_O_0_RIS,
-// PWM_O_1_RIS, and PWM_O_2_RIS registers.
+// The following are defines for the bit fields in the PWM_O_X_RIS register.
 //
 //*****************************************************************************
 #define PWM_X_RIS_INTCMPBD      0x00000020  // Comparator B Down Interrupt
-                                            // Status.
-#define PWM_X_RIS_INTCMPBU      0x00000010  // Comparator B Up Interrupt
-                                            // Status.
+                                            // Status
+#define PWM_X_RIS_INTCMPBU      0x00000010  // Comparator B Up Interrupt Status
 #define PWM_X_RIS_INTCMPAD      0x00000008  // Comparator A Down Interrupt
-                                            // Status.
-#define PWM_X_RIS_INTCMPAU      0x00000004  // Comparator A Up Interrupt
-                                            // Status.
-#define PWM_X_RIS_INTCNTLOAD    0x00000002  // Counter=Load Interrupt Status.
-#define PWM_X_RIS_INTCNTZERO    0x00000001  // Counter=0 Interrupt Status.
+                                            // Status
+#define PWM_X_RIS_INTCMPAU      0x00000004  // Comparator A Up Interrupt Status
+#define PWM_X_RIS_INTCNTLOAD    0x00000002  // Counter=Load Interrupt Status
+#define PWM_X_RIS_INTCNTZERO    0x00000001  // Counter=0 Interrupt Status
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the PWM_O_0_ISC,
-// PWM_O_1_ISC, and PWM_O_2_ISC registers.
+// The following are defines for the bit fields in the PWM_O_X_ISC register.
 //
 //*****************************************************************************
-#define PWM_X_ISC_INTCMPBD      0x00000020  // Comparator B Down Interrupt.
-#define PWM_X_ISC_INTCMPBU      0x00000010  // Comparator B Up Interrupt.
-#define PWM_X_ISC_INTCMPAD      0x00000008  // Comparator A Down Interrupt.
-#define PWM_X_ISC_INTCMPAU      0x00000004  // Comparator A Up Interrupt.
-#define PWM_X_ISC_INTCNTLOAD    0x00000002  // Counter=Load Interrupt.
-#define PWM_X_ISC_INTCNTZERO    0x00000001  // Counter=0 Interrupt.
+#define PWM_X_ISC_INTCMPBD      0x00000020  // Comparator B Down Interrupt
+#define PWM_X_ISC_INTCMPBU      0x00000010  // Comparator B Up Interrupt
+#define PWM_X_ISC_INTCMPAD      0x00000008  // Comparator A Down Interrupt
+#define PWM_X_ISC_INTCMPAU      0x00000004  // Comparator A Up Interrupt
+#define PWM_X_ISC_INTCNTLOAD    0x00000002  // Counter=Load Interrupt
+#define PWM_X_ISC_INTCNTZERO    0x00000001  // Counter=0 Interrupt
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the PWM_O_0_LOAD,
-// PWM_O_1_LOAD, and PWM_O_2_LOAD registers.
+// The following are defines for the bit fields in the PWM_O_X_LOAD register.
 //
 //*****************************************************************************
-#define PWM_X_LOAD_M            0x0000FFFF  // Counter Load Value.
+#define PWM_X_LOAD_M            0x0000FFFF  // Counter Load Value
 #define PWM_X_LOAD_S            0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the PWM_O_0_COUNT,
-// PWM_O_1_COUNT, and PWM_O_2_COUNT registers.
+// The following are defines for the bit fields in the PWM_O_X_COUNT register.
 //
 //*****************************************************************************
-#define PWM_X_COUNT_M           0x0000FFFF  // Counter Value.
+#define PWM_X_COUNT_M           0x0000FFFF  // Counter Value
 #define PWM_X_COUNT_S           0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the PWM_O_0_CMPA,
-// PWM_O_1_CMPA, and PWM_O_2_CMPA registers.
+// The following are defines for the bit fields in the PWM_O_X_CMPA register.
 //
 //*****************************************************************************
-#define PWM_X_CMPA_M            0x0000FFFF  // Comparator A Value.
+#define PWM_X_CMPA_M            0x0000FFFF  // Comparator A Value
 #define PWM_X_CMPA_S            0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the PWM_O_0_CMPB,
-// PWM_O_1_CMPB, and PWM_O_2_CMPB registers.
+// The following are defines for the bit fields in the PWM_O_X_CMPB register.
 //
 //*****************************************************************************
-#define PWM_X_CMPB_M            0x0000FFFF  // Comparator B Value.
+#define PWM_X_CMPB_M            0x0000FFFF  // Comparator B Value
 #define PWM_X_CMPB_S            0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the PWM_O_0_GENA,
-// PWM_O_1_GENA, and PWM_O_2_GENA registers.
+// The following are defines for the bit fields in the PWM_O_X_GENA register.
 //
 //*****************************************************************************
-#define PWM_X_GENA_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down.
+#define PWM_X_GENA_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down
 #define PWM_X_GENA_ACTCMPBD_NONE \
-                                0x00000000  // Do nothing.
-#define PWM_X_GENA_ACTCMPBD_INV 0x00000400  // Invert the output signal.
+                                0x00000000  // Do nothing
+#define PWM_X_GENA_ACTCMPBD_INV 0x00000400  // Invert pwmA
 #define PWM_X_GENA_ACTCMPBD_ZERO \
-                                0x00000800  // Set the output signal to 0.
-#define PWM_X_GENA_ACTCMPBD_ONE 0x00000C00  // Set the output signal to 1.
-#define PWM_X_GENA_ACTCMPBU_M   0x00000300  // Action for Comparator B Up.
+                                0x00000800  // Drive pwmA Low
+#define PWM_X_GENA_ACTCMPBD_ONE 0x00000C00  // Drive pwmA High
+#define PWM_X_GENA_ACTCMPBU_M   0x00000300  // Action for Comparator B Up
 #define PWM_X_GENA_ACTCMPBU_NONE \
-                                0x00000000  // Do nothing.
-#define PWM_X_GENA_ACTCMPBU_INV 0x00000100  // Invert the output signal.
+                                0x00000000  // Do nothing
+#define PWM_X_GENA_ACTCMPBU_INV 0x00000100  // Invert pwmA
 #define PWM_X_GENA_ACTCMPBU_ZERO \
-                                0x00000200  // Set the output signal to 0.
-#define PWM_X_GENA_ACTCMPBU_ONE 0x00000300  // Set the output signal to 1.
-#define PWM_X_GENA_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down.
+                                0x00000200  // Drive pwmA Low
+#define PWM_X_GENA_ACTCMPBU_ONE 0x00000300  // Drive pwmA High
+#define PWM_X_GENA_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down
 #define PWM_X_GENA_ACTCMPAD_NONE \
-                                0x00000000  // Do nothing.
-#define PWM_X_GENA_ACTCMPAD_INV 0x00000040  // Invert the output signal.
+                                0x00000000  // Do nothing
+#define PWM_X_GENA_ACTCMPAD_INV 0x00000040  // Invert pwmA
 #define PWM_X_GENA_ACTCMPAD_ZERO \
-                                0x00000080  // Set the output signal to 0.
-#define PWM_X_GENA_ACTCMPAD_ONE 0x000000C0  // Set the output signal to 1.
-#define PWM_X_GENA_ACTCMPAU_M   0x00000030  // Action for Comparator A Up.
+                                0x00000080  // Drive pwmA Low
+#define PWM_X_GENA_ACTCMPAD_ONE 0x000000C0  // Drive pwmA High
+#define PWM_X_GENA_ACTCMPAU_M   0x00000030  // Action for Comparator A Up
 #define PWM_X_GENA_ACTCMPAU_NONE \
-                                0x00000000  // Do nothing.
-#define PWM_X_GENA_ACTCMPAU_INV 0x00000010  // Invert the output signal.
+                                0x00000000  // Do nothing
+#define PWM_X_GENA_ACTCMPAU_INV 0x00000010  // Invert pwmA
 #define PWM_X_GENA_ACTCMPAU_ZERO \
-                                0x00000020  // Set the output signal to 0.
-#define PWM_X_GENA_ACTCMPAU_ONE 0x00000030  // Set the output signal to 1.
-#define PWM_X_GENA_ACTLOAD_M    0x0000000C  // Action for Counter=Load.
-#define PWM_X_GENA_ACTLOAD_NONE 0x00000000  // Do nothing.
-#define PWM_X_GENA_ACTLOAD_INV  0x00000004  // Invert the output signal.
-#define PWM_X_GENA_ACTLOAD_ZERO 0x00000008  // Set the output signal to 0.
-#define PWM_X_GENA_ACTLOAD_ONE  0x0000000C  // Set the output signal to 1.
-#define PWM_X_GENA_ACTZERO_M    0x00000003  // Action for Counter=0.
-#define PWM_X_GENA_ACTZERO_NONE 0x00000000  // Do nothing.
-#define PWM_X_GENA_ACTZERO_INV  0x00000001  // Invert the output signal.
-#define PWM_X_GENA_ACTZERO_ZERO 0x00000002  // Set the output signal to 0.
-#define PWM_X_GENA_ACTZERO_ONE  0x00000003  // Set the output signal to 1.
+                                0x00000020  // Drive pwmA Low
+#define PWM_X_GENA_ACTCMPAU_ONE 0x00000030  // Drive pwmA High
+#define PWM_X_GENA_ACTLOAD_M    0x0000000C  // Action for Counter=LOAD
+#define PWM_X_GENA_ACTLOAD_NONE 0x00000000  // Do nothing
+#define PWM_X_GENA_ACTLOAD_INV  0x00000004  // Invert pwmA
+#define PWM_X_GENA_ACTLOAD_ZERO 0x00000008  // Drive pwmA Low
+#define PWM_X_GENA_ACTLOAD_ONE  0x0000000C  // Drive pwmA High
+#define PWM_X_GENA_ACTZERO_M    0x00000003  // Action for Counter=0
+#define PWM_X_GENA_ACTZERO_NONE 0x00000000  // Do nothing
+#define PWM_X_GENA_ACTZERO_INV  0x00000001  // Invert pwmA
+#define PWM_X_GENA_ACTZERO_ZERO 0x00000002  // Drive pwmA Low
+#define PWM_X_GENA_ACTZERO_ONE  0x00000003  // Drive pwmA High
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the PWM_O_0_GENB,
-// PWM_O_1_GENB, and PWM_O_2_GENB registers.
+// The following are defines for the bit fields in the PWM_O_X_GENB register.
 //
 //*****************************************************************************
-#define PWM_X_GENB_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down.
+#define PWM_X_GENB_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down
 #define PWM_X_GENB_ACTCMPBD_NONE \
-                                0x00000000  // Do nothing.
-#define PWM_X_GENB_ACTCMPBD_INV 0x00000400  // Invert the output signal.
+                                0x00000000  // Do nothing
+#define PWM_X_GENB_ACTCMPBD_INV 0x00000400  // Invert pwmB
 #define PWM_X_GENB_ACTCMPBD_ZERO \
-                                0x00000800  // Set the output signal to 0.
-#define PWM_X_GENB_ACTCMPBD_ONE 0x00000C00  // Set the output signal to 1.
-#define PWM_X_GENB_ACTCMPBU_M   0x00000300  // Action for Comparator B Up.
+                                0x00000800  // Drive pwmB Low
+#define PWM_X_GENB_ACTCMPBD_ONE 0x00000C00  // Drive pwmB High
+#define PWM_X_GENB_ACTCMPBU_M   0x00000300  // Action for Comparator B Up
 #define PWM_X_GENB_ACTCMPBU_NONE \
-                                0x00000000  // Do nothing.
-#define PWM_X_GENB_ACTCMPBU_INV 0x00000100  // Invert the output signal.
+                                0x00000000  // Do nothing
+#define PWM_X_GENB_ACTCMPBU_INV 0x00000100  // Invert pwmB
 #define PWM_X_GENB_ACTCMPBU_ZERO \
-                                0x00000200  // Set the output signal to 0.
-#define PWM_X_GENB_ACTCMPBU_ONE 0x00000300  // Set the output signal to 1.
-#define PWM_X_GENB_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down.
+                                0x00000200  // Drive pwmB Low
+#define PWM_X_GENB_ACTCMPBU_ONE 0x00000300  // Drive pwmB High
+#define PWM_X_GENB_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down
 #define PWM_X_GENB_ACTCMPAD_NONE \
-                                0x00000000  // Do nothing.
-#define PWM_X_GENB_ACTCMPAD_INV 0x00000040  // Invert the output signal.
+                                0x00000000  // Do nothing
+#define PWM_X_GENB_ACTCMPAD_INV 0x00000040  // Invert pwmB
 #define PWM_X_GENB_ACTCMPAD_ZERO \
-                                0x00000080  // Set the output signal to 0.
-#define PWM_X_GENB_ACTCMPAD_ONE 0x000000C0  // Set the output signal to 1.
-#define PWM_X_GENB_ACTCMPAU_M   0x00000030  // Action for Comparator A Up.
+                                0x00000080  // Drive pwmB Low
+#define PWM_X_GENB_ACTCMPAD_ONE 0x000000C0  // Drive pwmB High
+#define PWM_X_GENB_ACTCMPAU_M   0x00000030  // Action for Comparator A Up
 #define PWM_X_GENB_ACTCMPAU_NONE \
-                                0x00000000  // Do nothing.
-#define PWM_X_GENB_ACTCMPAU_INV 0x00000010  // Invert the output signal.
+                                0x00000000  // Do nothing
+#define PWM_X_GENB_ACTCMPAU_INV 0x00000010  // Invert pwmB
 #define PWM_X_GENB_ACTCMPAU_ZERO \
-                                0x00000020  // Set the output signal to 0.
-#define PWM_X_GENB_ACTCMPAU_ONE 0x00000030  // Set the output signal to 1.
-#define PWM_X_GENB_ACTLOAD_M    0x0000000C  // Action for Counter=Load.
-#define PWM_X_GENB_ACTLOAD_NONE 0x00000000  // Do nothing.
-#define PWM_X_GENB_ACTLOAD_INV  0x00000004  // Invert the output signal.
-#define PWM_X_GENB_ACTLOAD_ZERO 0x00000008  // Set the output signal to 0.
-#define PWM_X_GENB_ACTLOAD_ONE  0x0000000C  // Set the output signal to 1.
-#define PWM_X_GENB_ACTZERO_M    0x00000003  // Action for Counter=0.
-#define PWM_X_GENB_ACTZERO_NONE 0x00000000  // Do nothing.
-#define PWM_X_GENB_ACTZERO_INV  0x00000001  // Invert the output signal.
-#define PWM_X_GENB_ACTZERO_ZERO 0x00000002  // Set the output signal to 0.
-#define PWM_X_GENB_ACTZERO_ONE  0x00000003  // Set the output signal to 1.
+                                0x00000020  // Drive pwmB Low
+#define PWM_X_GENB_ACTCMPAU_ONE 0x00000030  // Drive pwmB High
+#define PWM_X_GENB_ACTLOAD_M    0x0000000C  // Action for Counter=LOAD
+#define PWM_X_GENB_ACTLOAD_NONE 0x00000000  // Do nothing
+#define PWM_X_GENB_ACTLOAD_INV  0x00000004  // Invert pwmB
+#define PWM_X_GENB_ACTLOAD_ZERO 0x00000008  // Drive pwmB Low
+#define PWM_X_GENB_ACTLOAD_ONE  0x0000000C  // Drive pwmB High
+#define PWM_X_GENB_ACTZERO_M    0x00000003  // Action for Counter=0
+#define PWM_X_GENB_ACTZERO_NONE 0x00000000  // Do nothing
+#define PWM_X_GENB_ACTZERO_INV  0x00000001  // Invert pwmB
+#define PWM_X_GENB_ACTZERO_ZERO 0x00000002  // Drive pwmB Low
+#define PWM_X_GENB_ACTZERO_ONE  0x00000003  // Drive pwmB High
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the PWM_O_0_DBCTL,
-// PWM_O_1_DBCTL, and PWM_O_2_DBCTL registers.
+// The following are defines for the bit fields in the PWM_O_X_DBCTL register.
 //
 //*****************************************************************************
-#define PWM_X_DBCTL_ENABLE      0x00000001  // Dead-Band Generator Enable.
+#define PWM_X_DBCTL_ENABLE      0x00000001  // Dead-Band Generator Enable
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the PWM_O_0_DBRISE,
-// PWM_O_1_DBRISE, and PWM_O_2_DBRISE registers.
+// The following are defines for the bit fields in the PWM_O_X_DBRISE register.
 //
 //*****************************************************************************
-#define PWM_X_DBRISE_DELAY_M    0x00000FFF  // Dead-Band Rise Delay.
+#define PWM_X_DBRISE_DELAY_M    0x00000FFF  // Dead-Band Rise Delay
 #define PWM_X_DBRISE_DELAY_S    0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the PWM_O_0_DBFALL,
-// PWM_O_1_DBFALL, and PWM_O_2_DBFALL registers.
+// The following are defines for the bit fields in the PWM_O_X_DBFALL register.
 //
 //*****************************************************************************
-#define PWM_X_DBFALL_DELAY_M    0x00000FFF  // Dead-Band Fall Delay.
+#define PWM_X_DBFALL_DELAY_M    0x00000FFF  // Dead-Band Fall Delay
 #define PWM_X_DBFALL_DELAY_S    0
 
 //*****************************************************************************
@@ -1597,33 +1587,33 @@
 // The following are defines for the bit fields in the QEI_O_CTL register.
 //
 //*****************************************************************************
-#define QEI_CTL_STALLEN         0x00001000  // Stall QEI.
-#define QEI_CTL_INVI            0x00000800  // Invert Index Pulse.
-#define QEI_CTL_INVB            0x00000400  // Invert PhB.
-#define QEI_CTL_INVA            0x00000200  // Invert PhA.
-#define QEI_CTL_VELDIV_M        0x000001C0  // Predivide Velocity.
-#define QEI_CTL_VELDIV_1        0x00000000  // /1
-#define QEI_CTL_VELDIV_2        0x00000040  // /2
-#define QEI_CTL_VELDIV_4        0x00000080  // /4
-#define QEI_CTL_VELDIV_8        0x000000C0  // /8
-#define QEI_CTL_VELDIV_16       0x00000100  // /16
-#define QEI_CTL_VELDIV_32       0x00000140  // /32
-#define QEI_CTL_VELDIV_64       0x00000180  // /64
-#define QEI_CTL_VELDIV_128      0x000001C0  // /128
-#define QEI_CTL_VELEN           0x00000020  // Capture Velocity.
-#define QEI_CTL_RESMODE         0x00000010  // Reset Mode.
-#define QEI_CTL_CAPMODE         0x00000008  // Capture Mode.
-#define QEI_CTL_SIGMODE         0x00000004  // Signal Mode.
-#define QEI_CTL_SWAP            0x00000002  // Swap Signals.
-#define QEI_CTL_ENABLE          0x00000001  // Enable QEI.
+#define QEI_CTL_STALLEN         0x00001000  // Stall QEI
+#define QEI_CTL_INVI            0x00000800  // Invert Index Pulse
+#define QEI_CTL_INVB            0x00000400  // Invert PhB
+#define QEI_CTL_INVA            0x00000200  // Invert PhA
+#define QEI_CTL_VELDIV_M        0x000001C0  // Predivide Velocity
+#define QEI_CTL_VELDIV_1        0x00000000  // QEI clock /1
+#define QEI_CTL_VELDIV_2        0x00000040  // QEI clock /2
+#define QEI_CTL_VELDIV_4        0x00000080  // QEI clock /4
+#define QEI_CTL_VELDIV_8        0x000000C0  // QEI clock /8
+#define QEI_CTL_VELDIV_16       0x00000100  // QEI clock /16
+#define QEI_CTL_VELDIV_32       0x00000140  // QEI clock /32
+#define QEI_CTL_VELDIV_64       0x00000180  // QEI clock /64
+#define QEI_CTL_VELDIV_128      0x000001C0  // QEI clock /128
+#define QEI_CTL_VELEN           0x00000020  // Capture Velocity
+#define QEI_CTL_RESMODE         0x00000010  // Reset Mode
+#define QEI_CTL_CAPMODE         0x00000008  // Capture Mode
+#define QEI_CTL_SIGMODE         0x00000004  // Signal Mode
+#define QEI_CTL_SWAP            0x00000002  // Swap Signals
+#define QEI_CTL_ENABLE          0x00000001  // Enable QEI
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the QEI_O_STAT register.
 //
 //*****************************************************************************
-#define QEI_STAT_DIRECTION      0x00000002  // Direction of Rotation.
-#define QEI_STAT_ERROR          0x00000001  // Error Detected.
+#define QEI_STAT_DIRECTION      0x00000002  // Direction of Rotation
+#define QEI_STAT_ERROR          0x00000001  // Error Detected
 
 //*****************************************************************************
 //
@@ -1631,7 +1621,7 @@
 //
 //*****************************************************************************
 #define QEI_POS_M               0xFFFFFFFF  // Current Position Integrator
-                                            // Value.
+                                            // Value
 #define QEI_POS_S               0
 
 //*****************************************************************************
@@ -1640,7 +1630,7 @@
 //
 //*****************************************************************************
 #define QEI_MAXPOS_M            0xFFFFFFFF  // Maximum Position Integrator
-                                            // Value.
+                                            // Value
 #define QEI_MAXPOS_S            0
 
 //*****************************************************************************
@@ -1648,7 +1638,7 @@
 // The following are defines for the bit fields in the QEI_O_LOAD register.
 //
 //*****************************************************************************
-#define QEI_LOAD_M              0xFFFFFFFF  // Velocity Timer Load Value.
+#define QEI_LOAD_M              0xFFFFFFFF  // Velocity Timer Load Value
 #define QEI_LOAD_S              0
 
 //*****************************************************************************
@@ -1656,7 +1646,7 @@
 // The following are defines for the bit fields in the QEI_O_TIME register.
 //
 //*****************************************************************************
-#define QEI_TIME_M              0xFFFFFFFF  // Velocity Timer Current Value.
+#define QEI_TIME_M              0xFFFFFFFF  // Velocity Timer Current Value
 #define QEI_TIME_S              0
 
 //*****************************************************************************
@@ -1664,7 +1654,7 @@
 // The following are defines for the bit fields in the QEI_O_COUNT register.
 //
 //*****************************************************************************
-#define QEI_COUNT_M             0xFFFFFFFF  // Velocity Pulse Count.
+#define QEI_COUNT_M             0xFFFFFFFF  // Velocity Pulse Count
 #define QEI_COUNT_S             0
 
 //*****************************************************************************
@@ -1672,7 +1662,7 @@
 // The following are defines for the bit fields in the QEI_O_SPEED register.
 //
 //*****************************************************************************
-#define QEI_SPEED_M             0xFFFFFFFF  // Velocity.
+#define QEI_SPEED_M             0xFFFFFFFF  // Velocity
 #define QEI_SPEED_S             0
 
 //*****************************************************************************
@@ -1680,56 +1670,55 @@
 // The following are defines for the bit fields in the QEI_O_INTEN register.
 //
 //*****************************************************************************
-#define QEI_INTEN_ERROR         0x00000008  // Phase Error Interrupt Enable.
+#define QEI_INTEN_ERROR         0x00000008  // Phase Error Interrupt Enable
 #define QEI_INTEN_DIR           0x00000004  // Direction Change Interrupt
-                                            // Enable.
-#define QEI_INTEN_TIMER         0x00000002  // Timer Expires Interrupt Enable.
+                                            // Enable
+#define QEI_INTEN_TIMER         0x00000002  // Timer Expires Interrupt Enable
 #define QEI_INTEN_INDEX         0x00000001  // Index Pulse Detected Interrupt
-                                            // Enable.
+                                            // Enable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the QEI_O_RIS register.
 //
 //*****************************************************************************
-#define QEI_RIS_ERROR           0x00000008  // Phase Error Detected.
-#define QEI_RIS_DIR             0x00000004  // Direction Change Detected.
-#define QEI_RIS_TIMER           0x00000002  // Velocity Timer Expired.
-#define QEI_RIS_INDEX           0x00000001  // Index Pulse Asserted.
+#define QEI_RIS_ERROR           0x00000008  // Phase Error Detected
+#define QEI_RIS_DIR             0x00000004  // Direction Change Detected
+#define QEI_RIS_TIMER           0x00000002  // Velocity Timer Expired
+#define QEI_RIS_INDEX           0x00000001  // Index Pulse Asserted
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the QEI_O_ISC register.
 //
 //*****************************************************************************
-#define QEI_ISC_ERROR           0x00000008  // Phase Error Interrupt.
-#define QEI_ISC_DIR             0x00000004  // Direction Change Interrupt.
-#define QEI_ISC_TIMER           0x00000002  // Velocity Timer Expired
-                                            // Interrupt.
-#define QEI_ISC_INDEX           0x00000001  // Index Pulse Interrupt.
+#define QEI_ISC_ERROR           0x00000008  // Phase Error Interrupt
+#define QEI_ISC_DIR             0x00000004  // Direction Change Interrupt
+#define QEI_ISC_TIMER           0x00000002  // Velocity Timer Expired Interrupt
+#define QEI_ISC_INDEX           0x00000001  // Index Pulse Interrupt
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the TIMER_O_CFG register.
 //
 //*****************************************************************************
-#define TIMER_CFG_M             0x00000007  // GPTM Configuration.
-#define TIMER_CFG_32_BIT_TIMER  0x00000000  // 32-bit timer configuration.
+#define TIMER_CFG_M             0x00000007  // GPTM Configuration
+#define TIMER_CFG_32_BIT_TIMER  0x00000000  // 32-bit timer configuration
 #define TIMER_CFG_32_BIT_RTC    0x00000001  // 32-bit real-time clock (RTC)
-                                            // counter configuration.
-#define TIMER_CFG_16_BIT        0x00000004  // 16-bit timer configuration,
+                                            // counter configuration
+#define TIMER_CFG_16_BIT        0x00000004  // 16-bit timer configuration. The
                                             // function is controlled by bits
-                                            // 1:0 of GPTMTAMR and GPTMTBMR.
+                                            // 1:0 of GPTMTAMR and GPTMTBMR
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the TIMER_O_TAMR register.
 //
 //*****************************************************************************
-#define TIMER_TAMR_TAAMS        0x00000008  // GPTM TimerA Alternate Mode
-                                            // Select.
-#define TIMER_TAMR_TACMR        0x00000004  // GPTM TimerA Capture Mode.
-#define TIMER_TAMR_TAMR_M       0x00000003  // GPTM TimerA Mode.
+#define TIMER_TAMR_TAAMS        0x00000008  // GPTM Timer A Alternate Mode
+                                            // Select
+#define TIMER_TAMR_TACMR        0x00000004  // GPTM Timer A Capture Mode
+#define TIMER_TAMR_TAMR_M       0x00000003  // GPTM Timer A Mode
 #define TIMER_TAMR_TAMR_1_SHOT  0x00000001  // One-Shot Timer mode
 #define TIMER_TAMR_TAMR_PERIOD  0x00000002  // Periodic Timer mode
 #define TIMER_TAMR_TAMR_CAP     0x00000003  // Capture mode
@@ -1739,10 +1728,10 @@
 // The following are defines for the bit fields in the TIMER_O_TBMR register.
 //
 //*****************************************************************************
-#define TIMER_TBMR_TBAMS        0x00000008  // GPTM TimerB Alternate Mode
-                                            // Select.
-#define TIMER_TBMR_TBCMR        0x00000004  // GPTM TimerB Capture Mode.
-#define TIMER_TBMR_TBMR_M       0x00000003  // GPTM TimerB Mode.
+#define TIMER_TBMR_TBAMS        0x00000008  // GPTM Timer B Alternate Mode
+                                            // Select
+#define TIMER_TBMR_TBCMR        0x00000004  // GPTM Timer B Capture Mode
+#define TIMER_TBMR_TBMR_M       0x00000003  // GPTM Timer B Mode
 #define TIMER_TBMR_TBMR_1_SHOT  0x00000001  // One-Shot Timer mode
 #define TIMER_TBMR_TBMR_PERIOD  0x00000002  // Periodic Timer mode
 #define TIMER_TBMR_TBMR_CAP     0x00000003  // Capture mode
@@ -1752,111 +1741,111 @@
 // The following are defines for the bit fields in the TIMER_O_CTL register.
 //
 //*****************************************************************************
-#define TIMER_CTL_TBPWML        0x00004000  // GPTM TimerB PWM Output Level.
-#define TIMER_CTL_TBOTE         0x00002000  // GPTM TimerB Output Trigger
-                                            // Enable.
-#define TIMER_CTL_TBEVENT_M     0x00000C00  // GPTM TimerB Event Mode.
+#define TIMER_CTL_TBPWML        0x00004000  // GPTM Timer B PWM Output Level
+#define TIMER_CTL_TBOTE         0x00002000  // GPTM Timer B Output Trigger
+                                            // Enable
+#define TIMER_CTL_TBEVENT_M     0x00000C00  // GPTM Timer B Event Mode
 #define TIMER_CTL_TBEVENT_POS   0x00000000  // Positive edge
 #define TIMER_CTL_TBEVENT_NEG   0x00000400  // Negative edge
 #define TIMER_CTL_TBEVENT_BOTH  0x00000C00  // Both edges
-#define TIMER_CTL_TBSTALL       0x00000200  // GPTM TimerB Stall Enable.
-#define TIMER_CTL_TBEN          0x00000100  // GPTM TimerB Enable.
-#define TIMER_CTL_TAPWML        0x00000040  // GPTM TimerA PWM Output Level.
-#define TIMER_CTL_TAOTE         0x00000020  // GPTM TimerA Output Trigger
-                                            // Enable.
-#define TIMER_CTL_RTCEN         0x00000010  // GPTM RTC Enable.
-#define TIMER_CTL_TAEVENT_M     0x0000000C  // GPTM TimerA Event Mode.
+#define TIMER_CTL_TBSTALL       0x00000200  // GPTM Timer B Stall Enable
+#define TIMER_CTL_TBEN          0x00000100  // GPTM Timer B Enable
+#define TIMER_CTL_TAPWML        0x00000040  // GPTM Timer A PWM Output Level
+#define TIMER_CTL_TAOTE         0x00000020  // GPTM Timer A Output Trigger
+                                            // Enable
+#define TIMER_CTL_RTCEN         0x00000010  // GPTM RTC Enable
+#define TIMER_CTL_TAEVENT_M     0x0000000C  // GPTM Timer A Event Mode
 #define TIMER_CTL_TAEVENT_POS   0x00000000  // Positive edge
 #define TIMER_CTL_TAEVENT_NEG   0x00000004  // Negative edge
 #define TIMER_CTL_TAEVENT_BOTH  0x0000000C  // Both edges
-#define TIMER_CTL_TASTALL       0x00000002  // GPTM TimerA Stall Enable.
-#define TIMER_CTL_TAEN          0x00000001  // GPTM TimerA Enable.
+#define TIMER_CTL_TASTALL       0x00000002  // GPTM Timer A Stall Enable
+#define TIMER_CTL_TAEN          0x00000001  // GPTM Timer A Enable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the TIMER_O_IMR register.
 //
 //*****************************************************************************
-#define TIMER_IMR_CBEIM         0x00000400  // GPTM CaptureB Event Interrupt
-                                            // Mask.
-#define TIMER_IMR_CBMIM         0x00000200  // GPTM CaptureB Match Interrupt
-                                            // Mask.
-#define TIMER_IMR_TBTOIM        0x00000100  // GPTM TimerB Time-Out Interrupt
-                                            // Mask.
-#define TIMER_IMR_RTCIM         0x00000008  // GPTM RTC Interrupt Mask.
-#define TIMER_IMR_CAEIM         0x00000004  // GPTM CaptureA Event Interrupt
-                                            // Mask.
-#define TIMER_IMR_CAMIM         0x00000002  // GPTM CaptureA Match Interrupt
-                                            // Mask.
-#define TIMER_IMR_TATOIM        0x00000001  // GPTM TimerA Time-Out Interrupt
-                                            // Mask.
+#define TIMER_IMR_CBEIM         0x00000400  // GPTM Capture B Event Interrupt
+                                            // Mask
+#define TIMER_IMR_CBMIM         0x00000200  // GPTM Capture B Match Interrupt
+                                            // Mask
+#define TIMER_IMR_TBTOIM        0x00000100  // GPTM Timer B Time-Out Interrupt
+                                            // Mask
+#define TIMER_IMR_RTCIM         0x00000008  // GPTM RTC Interrupt Mask
+#define TIMER_IMR_CAEIM         0x00000004  // GPTM Capture A Event Interrupt
+                                            // Mask
+#define TIMER_IMR_CAMIM         0x00000002  // GPTM Capture A Match Interrupt
+                                            // Mask
+#define TIMER_IMR_TATOIM        0x00000001  // GPTM Timer A Time-Out Interrupt
+                                            // Mask
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the TIMER_O_RIS register.
 //
 //*****************************************************************************
-#define TIMER_RIS_CBERIS        0x00000400  // GPTM CaptureB Event Raw
-                                            // Interrupt.
-#define TIMER_RIS_CBMRIS        0x00000200  // GPTM CaptureB Match Raw
-                                            // Interrupt.
-#define TIMER_RIS_TBTORIS       0x00000100  // GPTM TimerB Time-Out Raw
-                                            // Interrupt.
-#define TIMER_RIS_RTCRIS        0x00000008  // GPTM RTC Raw Interrupt.
-#define TIMER_RIS_CAERIS        0x00000004  // GPTM CaptureA Event Raw
-                                            // Interrupt.
-#define TIMER_RIS_CAMRIS        0x00000002  // GPTM CaptureA Match Raw
-                                            // Interrupt.
-#define TIMER_RIS_TATORIS       0x00000001  // GPTM TimerA Time-Out Raw
-                                            // Interrupt.
+#define TIMER_RIS_CBERIS        0x00000400  // GPTM Capture B Event Raw
+                                            // Interrupt
+#define TIMER_RIS_CBMRIS        0x00000200  // GPTM Capture B Match Raw
+                                            // Interrupt
+#define TIMER_RIS_TBTORIS       0x00000100  // GPTM Timer B Time-Out Raw
+                                            // Interrupt
+#define TIMER_RIS_RTCRIS        0x00000008  // GPTM RTC Raw Interrupt
+#define TIMER_RIS_CAERIS        0x00000004  // GPTM Capture A Event Raw
+                                            // Interrupt
+#define TIMER_RIS_CAMRIS        0x00000002  // GPTM Capture A Match Raw
+                                            // Interrupt
+#define TIMER_RIS_TATORIS       0x00000001  // GPTM Timer A Time-Out Raw
+                                            // Interrupt
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the TIMER_O_MIS register.
 //
 //*****************************************************************************
-#define TIMER_MIS_CBEMIS        0x00000400  // GPTM CaptureB Event Masked
-                                            // Interrupt.
-#define TIMER_MIS_CBMMIS        0x00000200  // GPTM CaptureB Match Masked
-                                            // Interrupt.
-#define TIMER_MIS_TBTOMIS       0x00000100  // GPTM TimerB Time-Out Masked
-                                            // Interrupt.
-#define TIMER_MIS_RTCMIS        0x00000008  // GPTM RTC Masked Interrupt.
-#define TIMER_MIS_CAEMIS        0x00000004  // GPTM CaptureA Event Masked
-                                            // Interrupt.
-#define TIMER_MIS_CAMMIS        0x00000002  // GPTM CaptureA Match Masked
-                                            // Interrupt.
-#define TIMER_MIS_TATOMIS       0x00000001  // GPTM TimerA Time-Out Masked
-                                            // Interrupt.
+#define TIMER_MIS_CBEMIS        0x00000400  // GPTM Capture B Event Masked
+                                            // Interrupt
+#define TIMER_MIS_CBMMIS        0x00000200  // GPTM Capture B Match Masked
+                                            // Interrupt
+#define TIMER_MIS_TBTOMIS       0x00000100  // GPTM Timer B Time-Out Masked
+                                            // Interrupt
+#define TIMER_MIS_RTCMIS        0x00000008  // GPTM RTC Masked Interrupt
+#define TIMER_MIS_CAEMIS        0x00000004  // GPTM Capture A Event Masked
+                                            // Interrupt
+#define TIMER_MIS_CAMMIS        0x00000002  // GPTM Capture A Match Masked
+                                            // Interrupt
+#define TIMER_MIS_TATOMIS       0x00000001  // GPTM Timer A Time-Out Masked
+                                            // Interrupt
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the TIMER_O_ICR register.
 //
 //*****************************************************************************
-#define TIMER_ICR_CBECINT       0x00000400  // GPTM CaptureB Event Interrupt
-                                            // Clear.
-#define TIMER_ICR_CBMCINT       0x00000200  // GPTM CaptureB Match Interrupt
-                                            // Clear.
-#define TIMER_ICR_TBTOCINT      0x00000100  // GPTM TimerB Time-Out Interrupt
-                                            // Clear.
-#define TIMER_ICR_RTCCINT       0x00000008  // GPTM RTC Interrupt Clear.
-#define TIMER_ICR_CAECINT       0x00000004  // GPTM CaptureA Event Interrupt
-                                            // Clear.
-#define TIMER_ICR_CAMCINT       0x00000002  // GPTM CaptureA Match Raw
-                                            // Interrupt.
-#define TIMER_ICR_TATOCINT      0x00000001  // GPTM TimerA Time-Out Raw
-                                            // Interrupt.
+#define TIMER_ICR_CBECINT       0x00000400  // GPTM Capture B Event Interrupt
+                                            // Clear
+#define TIMER_ICR_CBMCINT       0x00000200  // GPTM Capture B Match Interrupt
+                                            // Clear
+#define TIMER_ICR_TBTOCINT      0x00000100  // GPTM Timer B Time-Out Interrupt
+                                            // Clear
+#define TIMER_ICR_RTCCINT       0x00000008  // GPTM RTC Interrupt Clear
+#define TIMER_ICR_CAECINT       0x00000004  // GPTM Capture A Event Interrupt
+                                            // Clear
+#define TIMER_ICR_CAMCINT       0x00000002  // GPTM Capture A Match Interrupt
+                                            // Clear
+#define TIMER_ICR_TATOCINT      0x00000001  // GPTM Timer A Time-Out Raw
+                                            // Interrupt
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the TIMER_O_TAILR register.
 //
 //*****************************************************************************
-#define TIMER_TAILR_TAILRH_M    0xFFFF0000  // GPTM TimerA Interval Load
-                                            // Register High.
-#define TIMER_TAILR_TAILRL_M    0x0000FFFF  // GPTM TimerA Interval Load
-                                            // Register Low.
+#define TIMER_TAILR_TAILRH_M    0xFFFF0000  // GPTM Timer A Interval Load
+                                            // Register High
+#define TIMER_TAILR_TAILRL_M    0x0000FFFF  // GPTM Timer A Interval Load
+                                            // Register Low
 #define TIMER_TAILR_TAILRH_S    16
 #define TIMER_TAILR_TAILRL_S    0
 
@@ -1865,8 +1854,8 @@
 // The following are defines for the bit fields in the TIMER_O_TBILR register.
 //
 //*****************************************************************************
-#define TIMER_TBILR_TBILRL_M    0x0000FFFF  // GPTM TimerB Interval Load
-                                            // Register.
+#define TIMER_TBILR_TBILRL_M    0x0000FFFF  // GPTM Timer B Interval Load
+                                            // Register
 #define TIMER_TBILR_TBILRL_S    0
 
 //*****************************************************************************
@@ -1875,8 +1864,8 @@
 // register.
 //
 //*****************************************************************************
-#define TIMER_TAMATCHR_TAMRH_M  0xFFFF0000  // GPTM TimerA Match Register High.
-#define TIMER_TAMATCHR_TAMRL_M  0x0000FFFF  // GPTM TimerA Match Register Low.
+#define TIMER_TAMATCHR_TAMRH_M  0xFFFF0000  // GPTM Timer A Match Register High
+#define TIMER_TAMATCHR_TAMRL_M  0x0000FFFF  // GPTM Timer A Match Register Low
 #define TIMER_TAMATCHR_TAMRH_S  16
 #define TIMER_TAMATCHR_TAMRL_S  0
 
@@ -1886,7 +1875,7 @@
 // register.
 //
 //*****************************************************************************
-#define TIMER_TBMATCHR_TBMRL_M  0x0000FFFF  // GPTM TimerB Match Register Low.
+#define TIMER_TBMATCHR_TBMRL_M  0x0000FFFF  // GPTM Timer B Match Register Low
 #define TIMER_TBMATCHR_TBMRL_S  0
 
 //*****************************************************************************
@@ -1894,7 +1883,7 @@
 // The following are defines for the bit fields in the TIMER_O_TAPR register.
 //
 //*****************************************************************************
-#define TIMER_TAPR_TAPSR_M      0x000000FF  // GPTM TimerA Prescale.
+#define TIMER_TAPR_TAPSR_M      0x000000FF  // GPTM Timer A Prescale
 #define TIMER_TAPR_TAPSR_S      0
 
 //*****************************************************************************
@@ -1902,7 +1891,7 @@
 // The following are defines for the bit fields in the TIMER_O_TBPR register.
 //
 //*****************************************************************************
-#define TIMER_TBPR_TBPSR_M      0x000000FF  // GPTM TimerB Prescale.
+#define TIMER_TBPR_TBPSR_M      0x000000FF  // GPTM Timer B Prescale
 #define TIMER_TBPR_TBPSR_S      0
 
 //*****************************************************************************
@@ -1910,7 +1899,7 @@
 // The following are defines for the bit fields in the TIMER_O_TAPMR register.
 //
 //*****************************************************************************
-#define TIMER_TAPMR_TAPSMR_M    0x000000FF  // GPTM TimerA Prescale Match.
+#define TIMER_TAPMR_TAPSMR_M    0x000000FF  // GPTM TimerA Prescale Match
 #define TIMER_TAPMR_TAPSMR_S    0
 
 //*****************************************************************************
@@ -1918,7 +1907,7 @@
 // The following are defines for the bit fields in the TIMER_O_TBPMR register.
 //
 //*****************************************************************************
-#define TIMER_TBPMR_TBPSMR_M    0x000000FF  // GPTM TimerB Prescale Match.
+#define TIMER_TBPMR_TBPSMR_M    0x000000FF  // GPTM TimerB Prescale Match
 #define TIMER_TBPMR_TBPSMR_S    0
 
 //*****************************************************************************
@@ -1926,8 +1915,8 @@
 // The following are defines for the bit fields in the TIMER_O_TAR register.
 //
 //*****************************************************************************
-#define TIMER_TAR_TARH_M        0xFFFF0000  // GPTM TimerA Register High.
-#define TIMER_TAR_TARL_M        0x0000FFFF  // GPTM TimerA Register Low.
+#define TIMER_TAR_TARH_M        0xFFFF0000  // GPTM Timer A Register High
+#define TIMER_TAR_TARL_M        0x0000FFFF  // GPTM Timer A Register Low
 #define TIMER_TAR_TARH_S        16
 #define TIMER_TAR_TARL_S        0
 
@@ -1936,7 +1925,7 @@
 // The following are defines for the bit fields in the TIMER_O_TBR register.
 //
 //*****************************************************************************
-#define TIMER_TBR_TBRL_M        0x0000FFFF  // GPTM TimerB.
+#define TIMER_TBR_TBRL_M        0x0000FFFF  // GPTM Timer B
 #define TIMER_TBR_TBRL_S        0
 
 //*****************************************************************************
@@ -1944,58 +1933,58 @@
 // The following are defines for the bit fields in the ADC_O_ACTSS register.
 //
 //*****************************************************************************
-#define ADC_ACTSS_ASEN3         0x00000008  // ADC SS3 Enable.
-#define ADC_ACTSS_ASEN2         0x00000004  // ADC SS2 Enable.
-#define ADC_ACTSS_ASEN1         0x00000002  // ADC SS1 Enable.
-#define ADC_ACTSS_ASEN0         0x00000001  // ADC SS0 Enable.
+#define ADC_ACTSS_ASEN3         0x00000008  // ADC SS3 Enable
+#define ADC_ACTSS_ASEN2         0x00000004  // ADC SS2 Enable
+#define ADC_ACTSS_ASEN1         0x00000002  // ADC SS1 Enable
+#define ADC_ACTSS_ASEN0         0x00000001  // ADC SS0 Enable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the ADC_O_RIS register.
 //
 //*****************************************************************************
-#define ADC_RIS_INR3            0x00000008  // SS3 Raw Interrupt Status.
-#define ADC_RIS_INR2            0x00000004  // SS2 Raw Interrupt Status.
-#define ADC_RIS_INR1            0x00000002  // SS1 Raw Interrupt Status.
-#define ADC_RIS_INR0            0x00000001  // SS0 Raw Interrupt Status.
+#define ADC_RIS_INR3            0x00000008  // SS3 Raw Interrupt Status
+#define ADC_RIS_INR2            0x00000004  // SS2 Raw Interrupt Status
+#define ADC_RIS_INR1            0x00000002  // SS1 Raw Interrupt Status
+#define ADC_RIS_INR0            0x00000001  // SS0 Raw Interrupt Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the ADC_O_IM register.
 //
 //*****************************************************************************
-#define ADC_IM_MASK3            0x00000008  // SS3 Interrupt Mask.
-#define ADC_IM_MASK2            0x00000004  // SS2 Interrupt Mask.
-#define ADC_IM_MASK1            0x00000002  // SS1 Interrupt Mask.
-#define ADC_IM_MASK0            0x00000001  // SS0 Interrupt Mask.
+#define ADC_IM_MASK3            0x00000008  // SS3 Interrupt Mask
+#define ADC_IM_MASK2            0x00000004  // SS2 Interrupt Mask
+#define ADC_IM_MASK1            0x00000002  // SS1 Interrupt Mask
+#define ADC_IM_MASK0            0x00000001  // SS0 Interrupt Mask
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the ADC_O_ISC register.
 //
 //*****************************************************************************
-#define ADC_ISC_IN3             0x00000008  // SS3 Interrupt Status and Clear.
-#define ADC_ISC_IN2             0x00000004  // SS2 Interrupt Status and Clear.
-#define ADC_ISC_IN1             0x00000002  // SS1 Interrupt Status and Clear.
-#define ADC_ISC_IN0             0x00000001  // SS0 Interrupt Status and Clear.
+#define ADC_ISC_IN3             0x00000008  // SS3 Interrupt Status and Clear
+#define ADC_ISC_IN2             0x00000004  // SS2 Interrupt Status and Clear
+#define ADC_ISC_IN1             0x00000002  // SS1 Interrupt Status and Clear
+#define ADC_ISC_IN0             0x00000001  // SS0 Interrupt Status and Clear
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the ADC_O_OSTAT register.
 //
 //*****************************************************************************
-#define ADC_OSTAT_OV3           0x00000008  // SS3 FIFO Overflow.
-#define ADC_OSTAT_OV2           0x00000004  // SS2 FIFO Overflow.
-#define ADC_OSTAT_OV1           0x00000002  // SS1 FIFO Overflow.
-#define ADC_OSTAT_OV0           0x00000001  // SS0 FIFO Overflow.
+#define ADC_OSTAT_OV3           0x00000008  // SS3 FIFO Overflow
+#define ADC_OSTAT_OV2           0x00000004  // SS2 FIFO Overflow
+#define ADC_OSTAT_OV1           0x00000002  // SS1 FIFO Overflow
+#define ADC_OSTAT_OV0           0x00000001  // SS0 FIFO Overflow
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the ADC_O_EMUX register.
 //
 //*****************************************************************************
-#define ADC_EMUX_EM3_M          0x0000F000  // SS3 Trigger Select.
-#define ADC_EMUX_EM3_PROCESSOR  0x00000000  // Controller (default)
+#define ADC_EMUX_EM3_M          0x0000F000  // SS3 Trigger Select
+#define ADC_EMUX_EM3_PROCESSOR  0x00000000  // Processor (default)
 #define ADC_EMUX_EM3_COMP0      0x00001000  // Analog Comparator 0
 #define ADC_EMUX_EM3_EXTERNAL   0x00004000  // External (GPIO PB4)
 #define ADC_EMUX_EM3_TIMER      0x00005000  // Timer
@@ -2003,8 +1992,8 @@
 #define ADC_EMUX_EM3_PWM1       0x00007000  // PWM1
 #define ADC_EMUX_EM3_PWM2       0x00008000  // PWM2
 #define ADC_EMUX_EM3_ALWAYS     0x0000F000  // Always (continuously sample)
-#define ADC_EMUX_EM2_M          0x00000F00  // SS2 Trigger Select.
-#define ADC_EMUX_EM2_PROCESSOR  0x00000000  // Controller (default)
+#define ADC_EMUX_EM2_M          0x00000F00  // SS2 Trigger Select
+#define ADC_EMUX_EM2_PROCESSOR  0x00000000  // Processor (default)
 #define ADC_EMUX_EM2_COMP0      0x00000100  // Analog Comparator 0
 #define ADC_EMUX_EM2_EXTERNAL   0x00000400  // External (GPIO PB4)
 #define ADC_EMUX_EM2_TIMER      0x00000500  // Timer
@@ -2012,8 +2001,8 @@
 #define ADC_EMUX_EM2_PWM1       0x00000700  // PWM1
 #define ADC_EMUX_EM2_PWM2       0x00000800  // PWM2
 #define ADC_EMUX_EM2_ALWAYS     0x00000F00  // Always (continuously sample)
-#define ADC_EMUX_EM1_M          0x000000F0  // SS1 Trigger Select.
-#define ADC_EMUX_EM1_PROCESSOR  0x00000000  // Controller (default)
+#define ADC_EMUX_EM1_M          0x000000F0  // SS1 Trigger Select
+#define ADC_EMUX_EM1_PROCESSOR  0x00000000  // Processor (default)
 #define ADC_EMUX_EM1_COMP0      0x00000010  // Analog Comparator 0
 #define ADC_EMUX_EM1_EXTERNAL   0x00000040  // External (GPIO PB4)
 #define ADC_EMUX_EM1_TIMER      0x00000050  // Timer
@@ -2021,8 +2010,8 @@
 #define ADC_EMUX_EM1_PWM1       0x00000070  // PWM1
 #define ADC_EMUX_EM1_PWM2       0x00000080  // PWM2
 #define ADC_EMUX_EM1_ALWAYS     0x000000F0  // Always (continuously sample)
-#define ADC_EMUX_EM0_M          0x0000000F  // SS0 Trigger Select.
-#define ADC_EMUX_EM0_PROCESSOR  0x00000000  // Controller (default)
+#define ADC_EMUX_EM0_M          0x0000000F  // SS0 Trigger Select
+#define ADC_EMUX_EM0_PROCESSOR  0x00000000  // Processor (default)
 #define ADC_EMUX_EM0_COMP0      0x00000001  // Analog Comparator 0
 #define ADC_EMUX_EM0_EXTERNAL   0x00000004  // External (GPIO PB4)
 #define ADC_EMUX_EM0_TIMER      0x00000005  // Timer
@@ -2036,32 +2025,32 @@
 // The following are defines for the bit fields in the ADC_O_USTAT register.
 //
 //*****************************************************************************
-#define ADC_USTAT_UV3           0x00000008  // SS3 FIFO Underflow.
-#define ADC_USTAT_UV2           0x00000004  // SS2 FIFO Underflow.
-#define ADC_USTAT_UV1           0x00000002  // SS1 FIFO Underflow.
-#define ADC_USTAT_UV0           0x00000001  // SS0 FIFO Underflow.
+#define ADC_USTAT_UV3           0x00000008  // SS3 FIFO Underflow
+#define ADC_USTAT_UV2           0x00000004  // SS2 FIFO Underflow
+#define ADC_USTAT_UV1           0x00000002  // SS1 FIFO Underflow
+#define ADC_USTAT_UV0           0x00000001  // SS0 FIFO Underflow
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the ADC_O_SSPRI register.
 //
 //*****************************************************************************
-#define ADC_SSPRI_SS3_M         0x00003000  // SS3 Priority.
+#define ADC_SSPRI_SS3_M         0x00003000  // SS3 Priority
 #define ADC_SSPRI_SS3_1ST       0x00000000  // First priority
 #define ADC_SSPRI_SS3_2ND       0x00001000  // Second priority
 #define ADC_SSPRI_SS3_3RD       0x00002000  // Third priority
 #define ADC_SSPRI_SS3_4TH       0x00003000  // Fourth priority
-#define ADC_SSPRI_SS2_M         0x00000300  // SS2 Priority.
+#define ADC_SSPRI_SS2_M         0x00000300  // SS2 Priority
 #define ADC_SSPRI_SS2_1ST       0x00000000  // First priority
 #define ADC_SSPRI_SS2_2ND       0x00000100  // Second priority
 #define ADC_SSPRI_SS2_3RD       0x00000200  // Third priority
 #define ADC_SSPRI_SS2_4TH       0x00000300  // Fourth priority
-#define ADC_SSPRI_SS1_M         0x00000030  // SS1 Priority.
+#define ADC_SSPRI_SS1_M         0x00000030  // SS1 Priority
 #define ADC_SSPRI_SS1_1ST       0x00000000  // First priority
 #define ADC_SSPRI_SS1_2ND       0x00000010  // Second priority
 #define ADC_SSPRI_SS1_3RD       0x00000020  // Third priority
 #define ADC_SSPRI_SS1_4TH       0x00000030  // Fourth priority
-#define ADC_SSPRI_SS0_M         0x00000003  // SS0 Priority.
+#define ADC_SSPRI_SS0_M         0x00000003  // SS0 Priority
 #define ADC_SSPRI_SS0_1ST       0x00000000  // First priority
 #define ADC_SSPRI_SS0_2ND       0x00000001  // Second priority
 #define ADC_SSPRI_SS0_3RD       0x00000002  // Third priority
@@ -2072,17 +2061,17 @@
 // The following are defines for the bit fields in the ADC_O_PSSI register.
 //
 //*****************************************************************************
-#define ADC_PSSI_SS3            0x00000008  // SS3 Initiate.
-#define ADC_PSSI_SS2            0x00000004  // SS2 Initiate.
-#define ADC_PSSI_SS1            0x00000002  // SS1 Initiate.
-#define ADC_PSSI_SS0            0x00000001  // SS0 Initiate.
+#define ADC_PSSI_SS3            0x00000008  // SS3 Initiate
+#define ADC_PSSI_SS2            0x00000004  // SS2 Initiate
+#define ADC_PSSI_SS1            0x00000002  // SS1 Initiate
+#define ADC_PSSI_SS0            0x00000001  // SS0 Initiate
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the ADC_O_SAC register.
 //
 //*****************************************************************************
-#define ADC_SAC_AVG_M           0x00000007  // Hardware Averaging Control.
+#define ADC_SAC_AVG_M           0x00000007  // Hardware Averaging Control
 #define ADC_SAC_AVG_OFF         0x00000000  // No hardware oversampling
 #define ADC_SAC_AVG_2X          0x00000001  // 2x hardware oversampling
 #define ADC_SAC_AVG_4X          0x00000002  // 4x hardware oversampling
@@ -2096,14 +2085,14 @@
 // The following are defines for the bit fields in the ADC_O_SSMUX0 register.
 //
 //*****************************************************************************
-#define ADC_SSMUX0_MUX7_M       0x30000000  // 8th Sample Input Select.
-#define ADC_SSMUX0_MUX6_M       0x03000000  // 7th Sample Input Select.
-#define ADC_SSMUX0_MUX5_M       0x00300000  // 6th Sample Input Select.
-#define ADC_SSMUX0_MUX4_M       0x00030000  // 5th Sample Input Select.
-#define ADC_SSMUX0_MUX3_M       0x00003000  // 4th Sample Input Select.
-#define ADC_SSMUX0_MUX2_M       0x00000300  // 3rd Sample Input Select.
-#define ADC_SSMUX0_MUX1_M       0x00000030  // 2nd Sample Input Select.
-#define ADC_SSMUX0_MUX0_M       0x00000003  // 1st Sample Input Select.
+#define ADC_SSMUX0_MUX7_M       0x30000000  // 8th Sample Input Select
+#define ADC_SSMUX0_MUX6_M       0x03000000  // 7th Sample Input Select
+#define ADC_SSMUX0_MUX5_M       0x00300000  // 6th Sample Input Select
+#define ADC_SSMUX0_MUX4_M       0x00030000  // 5th Sample Input Select
+#define ADC_SSMUX0_MUX3_M       0x00003000  // 4th Sample Input Select
+#define ADC_SSMUX0_MUX2_M       0x00000300  // 3rd Sample Input Select
+#define ADC_SSMUX0_MUX1_M       0x00000030  // 2nd Sample Input Select
+#define ADC_SSMUX0_MUX0_M       0x00000003  // 1st Sample Input Select
 #define ADC_SSMUX0_MUX7_S       28
 #define ADC_SSMUX0_MUX6_S       24
 #define ADC_SSMUX0_MUX5_S       20
@@ -2118,45 +2107,45 @@
 // The following are defines for the bit fields in the ADC_O_SSCTL0 register.
 //
 //*****************************************************************************
-#define ADC_SSCTL0_TS7          0x80000000  // 8th Sample Temp Sensor Select.
-#define ADC_SSCTL0_IE7          0x40000000  // 8th Sample Interrupt Enable.
-#define ADC_SSCTL0_END7         0x20000000  // 8th Sample is End of Sequence.
-#define ADC_SSCTL0_D7           0x10000000  // 8th Sample Diff Input Select.
-#define ADC_SSCTL0_TS6          0x08000000  // 7th Sample Temp Sensor Select.
-#define ADC_SSCTL0_IE6          0x04000000  // 7th Sample Interrupt Enable.
-#define ADC_SSCTL0_END6         0x02000000  // 7th Sample is End of Sequence.
-#define ADC_SSCTL0_D6           0x01000000  // 7th Sample Diff Input Select.
-#define ADC_SSCTL0_TS5          0x00800000  // 6th Sample Temp Sensor Select.
-#define ADC_SSCTL0_IE5          0x00400000  // 6th Sample Interrupt Enable.
-#define ADC_SSCTL0_END5         0x00200000  // 6th Sample is End of Sequence.
-#define ADC_SSCTL0_D5           0x00100000  // 6th Sample Diff Input Select.
-#define ADC_SSCTL0_TS4          0x00080000  // 5th Sample Temp Sensor Select.
-#define ADC_SSCTL0_IE4          0x00040000  // 5th Sample Interrupt Enable.
-#define ADC_SSCTL0_END4         0x00020000  // 5th Sample is End of Sequence.
-#define ADC_SSCTL0_D4           0x00010000  // 5th Sample Diff Input Select.
-#define ADC_SSCTL0_TS3          0x00008000  // 4th Sample Temp Sensor Select.
-#define ADC_SSCTL0_IE3          0x00004000  // 4th Sample Interrupt Enable.
-#define ADC_SSCTL0_END3         0x00002000  // 4th Sample is End of Sequence.
-#define ADC_SSCTL0_D3           0x00001000  // 4th Sample Diff Input Select.
-#define ADC_SSCTL0_TS2          0x00000800  // 3rd Sample Temp Sensor Select.
-#define ADC_SSCTL0_IE2          0x00000400  // 3rd Sample Interrupt Enable.
-#define ADC_SSCTL0_END2         0x00000200  // 3rd Sample is End of Sequence.
-#define ADC_SSCTL0_D2           0x00000100  // 3rd Sample Diff Input Select.
-#define ADC_SSCTL0_TS1          0x00000080  // 2nd Sample Temp Sensor Select.
-#define ADC_SSCTL0_IE1          0x00000040  // 2nd Sample Interrupt Enable.
-#define ADC_SSCTL0_END1         0x00000020  // 2nd Sample is End of Sequence.
-#define ADC_SSCTL0_D1           0x00000010  // 2nd Sample Diff Input Select.
-#define ADC_SSCTL0_TS0          0x00000008  // 1st Sample Temp Sensor Select.
-#define ADC_SSCTL0_IE0          0x00000004  // 1st Sample Interrupt Enable.
-#define ADC_SSCTL0_END0         0x00000002  // 1st Sample is End of Sequence.
-#define ADC_SSCTL0_D0           0x00000001  // 1st Sample Diff Input Select.
+#define ADC_SSCTL0_TS7          0x80000000  // 8th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE7          0x40000000  // 8th Sample Interrupt Enable
+#define ADC_SSCTL0_END7         0x20000000  // 8th Sample is End of Sequence
+#define ADC_SSCTL0_D7           0x10000000  // 8th Sample Diff Input Select
+#define ADC_SSCTL0_TS6          0x08000000  // 7th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE6          0x04000000  // 7th Sample Interrupt Enable
+#define ADC_SSCTL0_END6         0x02000000  // 7th Sample is End of Sequence
+#define ADC_SSCTL0_D6           0x01000000  // 7th Sample Diff Input Select
+#define ADC_SSCTL0_TS5          0x00800000  // 6th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE5          0x00400000  // 6th Sample Interrupt Enable
+#define ADC_SSCTL0_END5         0x00200000  // 6th Sample is End of Sequence
+#define ADC_SSCTL0_D5           0x00100000  // 6th Sample Diff Input Select
+#define ADC_SSCTL0_TS4          0x00080000  // 5th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE4          0x00040000  // 5th Sample Interrupt Enable
+#define ADC_SSCTL0_END4         0x00020000  // 5th Sample is End of Sequence
+#define ADC_SSCTL0_D4           0x00010000  // 5th Sample Diff Input Select
+#define ADC_SSCTL0_TS3          0x00008000  // 4th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE3          0x00004000  // 4th Sample Interrupt Enable
+#define ADC_SSCTL0_END3         0x00002000  // 4th Sample is End of Sequence
+#define ADC_SSCTL0_D3           0x00001000  // 4th Sample Diff Input Select
+#define ADC_SSCTL0_TS2          0x00000800  // 3rd Sample Temp Sensor Select
+#define ADC_SSCTL0_IE2          0x00000400  // 3rd Sample Interrupt Enable
+#define ADC_SSCTL0_END2         0x00000200  // 3rd Sample is End of Sequence
+#define ADC_SSCTL0_D2           0x00000100  // 3rd Sample Diff Input Select
+#define ADC_SSCTL0_TS1          0x00000080  // 2nd Sample Temp Sensor Select
+#define ADC_SSCTL0_IE1          0x00000040  // 2nd Sample Interrupt Enable
+#define ADC_SSCTL0_END1         0x00000020  // 2nd Sample is End of Sequence
+#define ADC_SSCTL0_D1           0x00000010  // 2nd Sample Diff Input Select
+#define ADC_SSCTL0_TS0          0x00000008  // 1st Sample Temp Sensor Select
+#define ADC_SSCTL0_IE0          0x00000004  // 1st Sample Interrupt Enable
+#define ADC_SSCTL0_END0         0x00000002  // 1st Sample is End of Sequence
+#define ADC_SSCTL0_D0           0x00000001  // 1st Sample Diff Input Select
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the ADC_O_SSFIFO0 register.
 //
 //*****************************************************************************
-#define ADC_SSFIFO0_DATA_M      0x000003FF  // Conversion Result Data.
+#define ADC_SSFIFO0_DATA_M      0x000003FF  // Conversion Result Data
 #define ADC_SSFIFO0_DATA_S      0
 
 //*****************************************************************************
@@ -2164,10 +2153,10 @@
 // The following are defines for the bit fields in the ADC_O_SSFSTAT0 register.
 //
 //*****************************************************************************
-#define ADC_SSFSTAT0_FULL       0x00001000  // FIFO Full.
-#define ADC_SSFSTAT0_EMPTY      0x00000100  // FIFO Empty.
-#define ADC_SSFSTAT0_HPTR_M     0x000000F0  // FIFO Head Pointer.
-#define ADC_SSFSTAT0_TPTR_M     0x0000000F  // FIFO Tail Pointer.
+#define ADC_SSFSTAT0_FULL       0x00001000  // FIFO Full
+#define ADC_SSFSTAT0_EMPTY      0x00000100  // FIFO Empty
+#define ADC_SSFSTAT0_HPTR_M     0x000000F0  // FIFO Head Pointer
+#define ADC_SSFSTAT0_TPTR_M     0x0000000F  // FIFO Tail Pointer
 #define ADC_SSFSTAT0_HPTR_S     4
 #define ADC_SSFSTAT0_TPTR_S     0
 
@@ -2176,10 +2165,10 @@
 // The following are defines for the bit fields in the ADC_O_SSMUX1 register.
 //
 //*****************************************************************************
-#define ADC_SSMUX1_MUX3_M       0x00003000  // 4th Sample Input Select.
-#define ADC_SSMUX1_MUX2_M       0x00000300  // 3rd Sample Input Select.
-#define ADC_SSMUX1_MUX1_M       0x00000030  // 2nd Sample Input Select.
-#define ADC_SSMUX1_MUX0_M       0x00000003  // 1st Sample Input Select.
+#define ADC_SSMUX1_MUX3_M       0x00003000  // 4th Sample Input Select
+#define ADC_SSMUX1_MUX2_M       0x00000300  // 3rd Sample Input Select
+#define ADC_SSMUX1_MUX1_M       0x00000030  // 2nd Sample Input Select
+#define ADC_SSMUX1_MUX0_M       0x00000003  // 1st Sample Input Select
 #define ADC_SSMUX1_MUX3_S       12
 #define ADC_SSMUX1_MUX2_S       8
 #define ADC_SSMUX1_MUX1_S       4
@@ -2190,29 +2179,29 @@
 // The following are defines for the bit fields in the ADC_O_SSCTL1 register.
 //
 //*****************************************************************************
-#define ADC_SSCTL1_TS3          0x00008000  // 4th Sample Temp Sensor Select.
-#define ADC_SSCTL1_IE3          0x00004000  // 4th Sample Interrupt Enable.
-#define ADC_SSCTL1_END3         0x00002000  // 4th Sample is End of Sequence.
-#define ADC_SSCTL1_D3           0x00001000  // 4th Sample Diff Input Select.
-#define ADC_SSCTL1_TS2          0x00000800  // 3rd Sample Temp Sensor Select.
-#define ADC_SSCTL1_IE2          0x00000400  // 3rd Sample Interrupt Enable.
-#define ADC_SSCTL1_END2         0x00000200  // 3rd Sample is End of Sequence.
-#define ADC_SSCTL1_D2           0x00000100  // 3rd Sample Diff Input Select.
-#define ADC_SSCTL1_TS1          0x00000080  // 2nd Sample Temp Sensor Select.
-#define ADC_SSCTL1_IE1          0x00000040  // 2nd Sample Interrupt Enable.
-#define ADC_SSCTL1_END1         0x00000020  // 2nd Sample is End of Sequence.
-#define ADC_SSCTL1_D1           0x00000010  // 2nd Sample Diff Input Select.
-#define ADC_SSCTL1_TS0          0x00000008  // 1st Sample Temp Sensor Select.
-#define ADC_SSCTL1_IE0          0x00000004  // 1st Sample Interrupt Enable.
-#define ADC_SSCTL1_END0         0x00000002  // 1st Sample is End of Sequence.
-#define ADC_SSCTL1_D0           0x00000001  // 1st Sample Diff Input Select.
+#define ADC_SSCTL1_TS3          0x00008000  // 4th Sample Temp Sensor Select
+#define ADC_SSCTL1_IE3          0x00004000  // 4th Sample Interrupt Enable
+#define ADC_SSCTL1_END3         0x00002000  // 4th Sample is End of Sequence
+#define ADC_SSCTL1_D3           0x00001000  // 4th Sample Diff Input Select
+#define ADC_SSCTL1_TS2          0x00000800  // 3rd Sample Temp Sensor Select
+#define ADC_SSCTL1_IE2          0x00000400  // 3rd Sample Interrupt Enable
+#define ADC_SSCTL1_END2         0x00000200  // 3rd Sample is End of Sequence
+#define ADC_SSCTL1_D2           0x00000100  // 3rd Sample Diff Input Select
+#define ADC_SSCTL1_TS1          0x00000080  // 2nd Sample Temp Sensor Select
+#define ADC_SSCTL1_IE1          0x00000040  // 2nd Sample Interrupt Enable
+#define ADC_SSCTL1_END1         0x00000020  // 2nd Sample is End of Sequence
+#define ADC_SSCTL1_D1           0x00000010  // 2nd Sample Diff Input Select
+#define ADC_SSCTL1_TS0          0x00000008  // 1st Sample Temp Sensor Select
+#define ADC_SSCTL1_IE0          0x00000004  // 1st Sample Interrupt Enable
+#define ADC_SSCTL1_END0         0x00000002  // 1st Sample is End of Sequence
+#define ADC_SSCTL1_D0           0x00000001  // 1st Sample Diff Input Select
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the ADC_O_SSFIFO1 register.
 //
 //*****************************************************************************
-#define ADC_SSFIFO1_DATA_M      0x000003FF  // Conversion Result Data.
+#define ADC_SSFIFO1_DATA_M      0x000003FF  // Conversion Result Data
 #define ADC_SSFIFO1_DATA_S      0
 
 //*****************************************************************************
@@ -2220,10 +2209,10 @@
 // The following are defines for the bit fields in the ADC_O_SSFSTAT1 register.
 //
 //*****************************************************************************
-#define ADC_SSFSTAT1_FULL       0x00001000  // FIFO Full.
-#define ADC_SSFSTAT1_EMPTY      0x00000100  // FIFO Empty.
-#define ADC_SSFSTAT1_HPTR_M     0x000000F0  // FIFO Head Pointer.
-#define ADC_SSFSTAT1_TPTR_M     0x0000000F  // FIFO Tail Pointer.
+#define ADC_SSFSTAT1_FULL       0x00001000  // FIFO Full
+#define ADC_SSFSTAT1_EMPTY      0x00000100  // FIFO Empty
+#define ADC_SSFSTAT1_HPTR_M     0x000000F0  // FIFO Head Pointer
+#define ADC_SSFSTAT1_TPTR_M     0x0000000F  // FIFO Tail Pointer
 #define ADC_SSFSTAT1_HPTR_S     4
 #define ADC_SSFSTAT1_TPTR_S     0
 
@@ -2232,10 +2221,10 @@
 // The following are defines for the bit fields in the ADC_O_SSMUX2 register.
 //
 //*****************************************************************************
-#define ADC_SSMUX2_MUX3_M       0x00003000  // 4th Sample Input Select.
-#define ADC_SSMUX2_MUX2_M       0x00000300  // 3rd Sample Input Select.
-#define ADC_SSMUX2_MUX1_M       0x00000030  // 2nd Sample Input Select.
-#define ADC_SSMUX2_MUX0_M       0x00000003  // 1st Sample Input Select.
+#define ADC_SSMUX2_MUX3_M       0x00003000  // 4th Sample Input Select
+#define ADC_SSMUX2_MUX2_M       0x00000300  // 3rd Sample Input Select
+#define ADC_SSMUX2_MUX1_M       0x00000030  // 2nd Sample Input Select
+#define ADC_SSMUX2_MUX0_M       0x00000003  // 1st Sample Input Select
 #define ADC_SSMUX2_MUX3_S       12
 #define ADC_SSMUX2_MUX2_S       8
 #define ADC_SSMUX2_MUX1_S       4
@@ -2246,29 +2235,29 @@
 // The following are defines for the bit fields in the ADC_O_SSCTL2 register.
 //
 //*****************************************************************************
-#define ADC_SSCTL2_TS3          0x00008000  // 4th Sample Temp Sensor Select.
-#define ADC_SSCTL2_IE3          0x00004000  // 4th Sample Interrupt Enable.
-#define ADC_SSCTL2_END3         0x00002000  // 4th Sample is End of Sequence.
-#define ADC_SSCTL2_D3           0x00001000  // 4th Sample Diff Input Select.
-#define ADC_SSCTL2_TS2          0x00000800  // 3rd Sample Temp Sensor Select.
-#define ADC_SSCTL2_IE2          0x00000400  // 3rd Sample Interrupt Enable.
-#define ADC_SSCTL2_END2         0x00000200  // 3rd Sample is End of Sequence.
-#define ADC_SSCTL2_D2           0x00000100  // 3rd Sample Diff Input Select.
-#define ADC_SSCTL2_TS1          0x00000080  // 2nd Sample Temp Sensor Select.
-#define ADC_SSCTL2_IE1          0x00000040  // 2nd Sample Interrupt Enable.
-#define ADC_SSCTL2_END1         0x00000020  // 2nd Sample is End of Sequence.
-#define ADC_SSCTL2_D1           0x00000010  // 2nd Sample Diff Input Select.
-#define ADC_SSCTL2_TS0          0x00000008  // 1st Sample Temp Sensor Select.
-#define ADC_SSCTL2_IE0          0x00000004  // 1st Sample Interrupt Enable.
-#define ADC_SSCTL2_END0         0x00000002  // 1st Sample is End of Sequence.
-#define ADC_SSCTL2_D0           0x00000001  // 1st Sample Diff Input Select.
+#define ADC_SSCTL2_TS3          0x00008000  // 4th Sample Temp Sensor Select
+#define ADC_SSCTL2_IE3          0x00004000  // 4th Sample Interrupt Enable
+#define ADC_SSCTL2_END3         0x00002000  // 4th Sample is End of Sequence
+#define ADC_SSCTL2_D3           0x00001000  // 4th Sample Diff Input Select
+#define ADC_SSCTL2_TS2          0x00000800  // 3rd Sample Temp Sensor Select
+#define ADC_SSCTL2_IE2          0x00000400  // 3rd Sample Interrupt Enable
+#define ADC_SSCTL2_END2         0x00000200  // 3rd Sample is End of Sequence
+#define ADC_SSCTL2_D2           0x00000100  // 3rd Sample Diff Input Select
+#define ADC_SSCTL2_TS1          0x00000080  // 2nd Sample Temp Sensor Select
+#define ADC_SSCTL2_IE1          0x00000040  // 2nd Sample Interrupt Enable
+#define ADC_SSCTL2_END1         0x00000020  // 2nd Sample is End of Sequence
+#define ADC_SSCTL2_D1           0x00000010  // 2nd Sample Diff Input Select
+#define ADC_SSCTL2_TS0          0x00000008  // 1st Sample Temp Sensor Select
+#define ADC_SSCTL2_IE0          0x00000004  // 1st Sample Interrupt Enable
+#define ADC_SSCTL2_END0         0x00000002  // 1st Sample is End of Sequence
+#define ADC_SSCTL2_D0           0x00000001  // 1st Sample Diff Input Select
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the ADC_O_SSFIFO2 register.
 //
 //*****************************************************************************
-#define ADC_SSFIFO2_DATA_M      0x000003FF  // Conversion Result Data.
+#define ADC_SSFIFO2_DATA_M      0x000003FF  // Conversion Result Data
 #define ADC_SSFIFO2_DATA_S      0
 
 //*****************************************************************************
@@ -2276,10 +2265,10 @@
 // The following are defines for the bit fields in the ADC_O_SSFSTAT2 register.
 //
 //*****************************************************************************
-#define ADC_SSFSTAT2_FULL       0x00001000  // FIFO Full.
-#define ADC_SSFSTAT2_EMPTY      0x00000100  // FIFO Empty.
-#define ADC_SSFSTAT2_HPTR_M     0x000000F0  // FIFO Head Pointer.
-#define ADC_SSFSTAT2_TPTR_M     0x0000000F  // FIFO Tail Pointer.
+#define ADC_SSFSTAT2_FULL       0x00001000  // FIFO Full
+#define ADC_SSFSTAT2_EMPTY      0x00000100  // FIFO Empty
+#define ADC_SSFSTAT2_HPTR_M     0x000000F0  // FIFO Head Pointer
+#define ADC_SSFSTAT2_TPTR_M     0x0000000F  // FIFO Tail Pointer
 #define ADC_SSFSTAT2_HPTR_S     4
 #define ADC_SSFSTAT2_TPTR_S     0
 
@@ -2288,7 +2277,7 @@
 // The following are defines for the bit fields in the ADC_O_SSMUX3 register.
 //
 //*****************************************************************************
-#define ADC_SSMUX3_MUX0_M       0x00000003  // 1st Sample Input Select.
+#define ADC_SSMUX3_MUX0_M       0x00000003  // 1st Sample Input Select
 #define ADC_SSMUX3_MUX0_S       0
 
 //*****************************************************************************
@@ -2296,17 +2285,17 @@
 // The following are defines for the bit fields in the ADC_O_SSCTL3 register.
 //
 //*****************************************************************************
-#define ADC_SSCTL3_TS0          0x00000008  // 1st Sample Temp Sensor Select.
-#define ADC_SSCTL3_IE0          0x00000004  // 1st Sample Interrupt Enable.
-#define ADC_SSCTL3_END0         0x00000002  // 1st Sample is End of Sequence.
-#define ADC_SSCTL3_D0           0x00000001  // 1st Sample Diff Input Select.
+#define ADC_SSCTL3_TS0          0x00000008  // 1st Sample Temp Sensor Select
+#define ADC_SSCTL3_IE0          0x00000004  // 1st Sample Interrupt Enable
+#define ADC_SSCTL3_END0         0x00000002  // 1st Sample is End of Sequence
+#define ADC_SSCTL3_D0           0x00000001  // 1st Sample Diff Input Select
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the ADC_O_SSFIFO3 register.
 //
 //*****************************************************************************
-#define ADC_SSFIFO3_DATA_M      0x000003FF  // Conversion Result Data.
+#define ADC_SSFIFO3_DATA_M      0x000003FF  // Conversion Result Data
 #define ADC_SSFIFO3_DATA_S      0
 
 //*****************************************************************************
@@ -2314,10 +2303,10 @@
 // The following are defines for the bit fields in the ADC_O_SSFSTAT3 register.
 //
 //*****************************************************************************
-#define ADC_SSFSTAT3_FULL       0x00001000  // FIFO Full.
-#define ADC_SSFSTAT3_EMPTY      0x00000100  // FIFO Empty.
-#define ADC_SSFSTAT3_HPTR_M     0x000000F0  // FIFO Head Pointer.
-#define ADC_SSFSTAT3_TPTR_M     0x0000000F  // FIFO Tail Pointer.
+#define ADC_SSFSTAT3_FULL       0x00001000  // FIFO Full
+#define ADC_SSFSTAT3_EMPTY      0x00000100  // FIFO Empty
+#define ADC_SSFSTAT3_HPTR_M     0x000000F0  // FIFO Head Pointer
+#define ADC_SSFSTAT3_TPTR_M     0x0000000F  // FIFO Tail Pointer
 #define ADC_SSFSTAT3_HPTR_S     4
 #define ADC_SSFSTAT3_TPTR_S     0
 
@@ -2326,7 +2315,7 @@
 // The following are defines for the bit fields in the ADC_O_TMLB register.
 //
 //*****************************************************************************
-#define ADC_TMLB_LB             0x00000001  // Loopback Mode Enable.
+#define ADC_TMLB_LB             0x00000001  // Loopback Mode Enable
 
 //*****************************************************************************
 //
@@ -2334,49 +2323,35 @@
 // SSFIFOx when the ADC TMLB is enabled.
 //
 //*****************************************************************************
-#define ADC_SSFIFO_TMLB_CNT_M   0x000003C0  // Continuous Sample Counter.
-#define ADC_SSFIFO_TMLB_CONT    0x00000020  // Continuation Sample Indicator.
-#define ADC_SSFIFO_TMLB_DIFF    0x00000010  // Differential Sample Indicator.
-#define ADC_SSFIFO_TMLB_TS      0x00000008  // Temp Sensor Sample Indicator.
-#define ADC_SSFIFO_TMLB_MUX_M   0x00000007  // Analog Input Indicator.
+#define ADC_SSFIFO_TMLB_CNT_M   0x000003C0  // Continuous Sample Counter
+#define ADC_SSFIFO_TMLB_CONT    0x00000020  // Continuation Sample Indicator
+#define ADC_SSFIFO_TMLB_DIFF    0x00000010  // Differential Sample Indicator
+#define ADC_SSFIFO_TMLB_TS      0x00000008  // Temp Sensor Sample Indicator
+#define ADC_SSFIFO_TMLB_MUX_M   0x00000007  // Analog Input Indicator
 #define ADC_SSFIFO_TMLB_CNT_S   6           // Sample counter shift
 #define ADC_SSFIFO_TMLB_MUX_S   0           // Input channel number shift
 
-//*****************************************************************************
-//
-// The following are defines for the the interpretation of the data in the
-// SSFIFOx when the ADC TMLB is enabled.
-//
-//*****************************************************************************
-#define ADC_TMLB_CNT_M          0x000003C0  // Continuous Sample Counter.
-#define ADC_TMLB_CONT           0x00000020  // Continuation Sample Indicator.
-#define ADC_TMLB_DIFF           0x00000010  // Differential Sample Indicator.
-#define ADC_TMLB_TS             0x00000008  // Temp Sensor Sample Indicator.
-#define ADC_TMLB_MUX_M          0x00000007  // Analog Input Indicator.
-#define ADC_TMLB_CNT_S          6           // Sample counter shift
-#define ADC_TMLB_MUX_S          0           // Input channel number shift
-
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the COMP_O_ACMIS register.
 //
 //*****************************************************************************
 #define COMP_ACMIS_IN0          0x00000001  // Comparator 0 Masked Interrupt
-                                            // Status.
+                                            // Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the COMP_O_ACRIS register.
 //
 //*****************************************************************************
-#define COMP_ACRIS_IN0          0x00000001  // Comparator 0 Interrupt Status.
+#define COMP_ACRIS_IN0          0x00000001  // Comparator 0 Interrupt Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the COMP_O_ACINTEN register.
 //
 //*****************************************************************************
-#define COMP_ACINTEN_IN0        0x00000001  // Comparator 0 Interrupt Enable.
+#define COMP_ACINTEN_IN0        0x00000001  // Comparator 0 Interrupt Enable
 
 //*****************************************************************************
 //
@@ -2384,9 +2359,9 @@
 // register.
 //
 //*****************************************************************************
-#define COMP_ACREFCTL_EN        0x00000200  // Resistor Ladder Enable.
-#define COMP_ACREFCTL_RNG       0x00000100  // Resistor Ladder Range.
-#define COMP_ACREFCTL_VREF_M    0x0000000F  // Resistor Ladder Voltage Ref.
+#define COMP_ACREFCTL_EN        0x00000200  // Resistor Ladder Enable
+#define COMP_ACREFCTL_RNG       0x00000100  // Resistor Ladder Range
+#define COMP_ACREFCTL_VREF_M    0x0000000F  // Resistor Ladder Voltage Ref
 #define COMP_ACREFCTL_VREF_S    0
 
 //*****************************************************************************
@@ -2394,58 +2369,58 @@
 // The following are defines for the bit fields in the COMP_O_ACSTAT0 register.
 //
 //*****************************************************************************
-#define COMP_ACSTAT0_OVAL       0x00000002  // Comparator Output Value.
+#define COMP_ACSTAT0_OVAL       0x00000002  // Comparator Output Value
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the COMP_O_ACCTL0 register.
 //
 //*****************************************************************************
-#define COMP_ACCTL0_TOEN        0x00000800  // Trigger Output Enable.
-#define COMP_ACCTL0_ASRCP_M     0x00000600  // Analog Source Positive.
-#define COMP_ACCTL0_ASRCP_PIN   0x00000000  // Pin value
+#define COMP_ACCTL0_TOEN        0x00000800  // Trigger Output Enable
+#define COMP_ACCTL0_ASRCP_M     0x00000600  // Analog Source Positive
+#define COMP_ACCTL0_ASRCP_PIN   0x00000000  // Pin value of Cn+
 #define COMP_ACCTL0_ASRCP_PIN0  0x00000200  // Pin value of C0+
 #define COMP_ACCTL0_ASRCP_REF   0x00000400  // Internal voltage reference
-#define COMP_ACCTL0_TSLVAL      0x00000080  // Trigger Sense Level Value.
-#define COMP_ACCTL0_TSEN_M      0x00000060  // Trigger Sense.
+                                            // (VIREF)
+#define COMP_ACCTL0_TSLVAL      0x00000080  // Trigger Sense Level Value
+#define COMP_ACCTL0_TSEN_M      0x00000060  // Trigger Sense
 #define COMP_ACCTL0_TSEN_LEVEL  0x00000000  // Level sense, see TSLVAL
 #define COMP_ACCTL0_TSEN_FALL   0x00000020  // Falling edge
 #define COMP_ACCTL0_TSEN_RISE   0x00000040  // Rising edge
 #define COMP_ACCTL0_TSEN_BOTH   0x00000060  // Either edge
-#define COMP_ACCTL0_ISLVAL      0x00000010  // Interrupt Sense Level Value.
-#define COMP_ACCTL0_ISEN_M      0x0000000C  // Interrupt Sense.
+#define COMP_ACCTL0_ISLVAL      0x00000010  // Interrupt Sense Level Value
+#define COMP_ACCTL0_ISEN_M      0x0000000C  // Interrupt Sense
 #define COMP_ACCTL0_ISEN_LEVEL  0x00000000  // Level sense, see ISLVAL
 #define COMP_ACCTL0_ISEN_FALL   0x00000004  // Falling edge
 #define COMP_ACCTL0_ISEN_RISE   0x00000008  // Rising edge
 #define COMP_ACCTL0_ISEN_BOTH   0x0000000C  // Either edge
-#define COMP_ACCTL0_CINV        0x00000002  // Comparator Output Invert.
+#define COMP_ACCTL0_CINV        0x00000002  // Comparator Output Invert
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the CAN_O_CTL register.
 //
 //*****************************************************************************
-#define CAN_CTL_TEST            0x00000080  // Test Mode Enable.
-#define CAN_CTL_CCE             0x00000040  // Configuration Change Enable.
-#define CAN_CTL_DAR             0x00000020  // Disable
-                                            // Automatic-Retransmission.
-#define CAN_CTL_EIE             0x00000008  // Error Interrupt Enable.
-#define CAN_CTL_SIE             0x00000004  // Status Interrupt Enable.
-#define CAN_CTL_IE              0x00000002  // CAN Interrupt Enable.
-#define CAN_CTL_INIT            0x00000001  // Initialization.
+#define CAN_CTL_TEST            0x00000080  // Test Mode Enable
+#define CAN_CTL_CCE             0x00000040  // Configuration Change Enable
+#define CAN_CTL_DAR             0x00000020  // Disable Automatic-Retransmission
+#define CAN_CTL_EIE             0x00000008  // Error Interrupt Enable
+#define CAN_CTL_SIE             0x00000004  // Status Interrupt Enable
+#define CAN_CTL_IE              0x00000002  // CAN Interrupt Enable
+#define CAN_CTL_INIT            0x00000001  // Initialization
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the CAN_O_STS register.
 //
 //*****************************************************************************
-#define CAN_STS_BOFF            0x00000080  // Bus-Off Status.
-#define CAN_STS_EWARN           0x00000040  // Warning Status.
-#define CAN_STS_EPASS           0x00000020  // Error Passive.
-#define CAN_STS_RXOK            0x00000010  // Received a Message Successfully.
+#define CAN_STS_BOFF            0x00000080  // Bus-Off Status
+#define CAN_STS_EWARN           0x00000040  // Warning Status
+#define CAN_STS_EPASS           0x00000020  // Error Passive
+#define CAN_STS_RXOK            0x00000010  // Received a Message Successfully
 #define CAN_STS_TXOK            0x00000008  // Transmitted a Message
-                                            // Successfully.
-#define CAN_STS_LEC_M           0x00000007  // Last Error Code.
+                                            // Successfully
+#define CAN_STS_LEC_M           0x00000007  // Last Error Code
 #define CAN_STS_LEC_NONE        0x00000000  // No Error
 #define CAN_STS_LEC_STUFF       0x00000001  // Stuff Error
 #define CAN_STS_LEC_FORM        0x00000002  // Format Error
@@ -2453,16 +2428,16 @@
 #define CAN_STS_LEC_BIT1        0x00000004  // Bit 1 Error
 #define CAN_STS_LEC_BIT0        0x00000005  // Bit 0 Error
 #define CAN_STS_LEC_CRC         0x00000006  // CRC Error
-#define CAN_STS_LEC_NOEVENT     0x00000007  // Unused
+#define CAN_STS_LEC_NOEVENT     0x00000007  // No Event
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the CAN_O_ERR register.
 //
 //*****************************************************************************
-#define CAN_ERR_RP              0x00008000  // Received Error Passive.
-#define CAN_ERR_REC_M           0x00007F00  // Receive Error Counter.
-#define CAN_ERR_TEC_M           0x000000FF  // Transmit Error Counter.
+#define CAN_ERR_RP              0x00008000  // Received Error Passive
+#define CAN_ERR_REC_M           0x00007F00  // Receive Error Counter
+#define CAN_ERR_TEC_M           0x000000FF  // Transmit Error Counter
 #define CAN_ERR_REC_S           8
 #define CAN_ERR_TEC_S           0
 
@@ -2471,11 +2446,10 @@
 // The following are defines for the bit fields in the CAN_O_BIT register.
 //
 //*****************************************************************************
-#define CAN_BIT_TSEG2_M         0x00007000  // Time Segment after Sample Point.
-#define CAN_BIT_TSEG1_M         0x00000F00  // Time Segment Before Sample
-                                            // Point.
-#define CAN_BIT_SJW_M           0x000000C0  // (Re)Synchronization Jump Width.
-#define CAN_BIT_BRP_M           0x0000003F  // Baud Rate Prescaler.
+#define CAN_BIT_TSEG2_M         0x00007000  // Time Segment after Sample Point
+#define CAN_BIT_TSEG1_M         0x00000F00  // Time Segment Before Sample Point
+#define CAN_BIT_SJW_M           0x000000C0  // (Re)Synchronization Jump Width
+#define CAN_BIT_BRP_M           0x0000003F  // Baud Rate Prescaler
 #define CAN_BIT_TSEG2_S         12
 #define CAN_BIT_TSEG1_S         8
 #define CAN_BIT_SJW_S           6
@@ -2486,7 +2460,7 @@
 // The following are defines for the bit fields in the CAN_O_INT register.
 //
 //*****************************************************************************
-#define CAN_INT_INTID_M         0x0000FFFF  // Interrupt Identifier.
+#define CAN_INT_INTID_M         0x0000FFFF  // Interrupt Identifier
 #define CAN_INT_INTID_NONE      0x00000000  // No interrupt pending
 #define CAN_INT_INTID_STATUS    0x00008000  // Status Interrupt
 
@@ -2495,29 +2469,22 @@
 // The following are defines for the bit fields in the CAN_O_TST register.
 //
 //*****************************************************************************
-#define CAN_TST_RX              0x00000080  // Receive Observation.
-#define CAN_TST_TX_M            0x00000060  // Transmit Control.
-#define CAN_TST_TX_CANCTL       0x00000000  // CANnTx is controlled by the CAN
-                                            // module; default operation
-#define CAN_TST_TX_SAMPLE       0x00000020  // The sample point is driven on
-                                            // the CANnTx signal. This mode is
-                                            // useful to monitor bit timing.
-#define CAN_TST_TX_DOMINANT     0x00000040  // CANnTx drives a low value. This
-                                            // mode is useful for checking the
-                                            // physical layer of the CAN bus.
-#define CAN_TST_TX_RECESSIVE    0x00000060  // CANnTx drives a high value. This
-                                            // mode is useful for checking the
-                                            // physical layer of the CAN bus.
-#define CAN_TST_LBACK           0x00000010  // Loopback Mode.
-#define CAN_TST_SILENT          0x00000008  // Silent Mode.
-#define CAN_TST_BASIC           0x00000004  // Basic Mode.
+#define CAN_TST_RX              0x00000080  // Receive Observation
+#define CAN_TST_TX_M            0x00000060  // Transmit Control
+#define CAN_TST_TX_CANCTL       0x00000000  // CAN Module Control
+#define CAN_TST_TX_SAMPLE       0x00000020  // Sample Point
+#define CAN_TST_TX_DOMINANT     0x00000040  // Driven Low
+#define CAN_TST_TX_RECESSIVE    0x00000060  // Driven High
+#define CAN_TST_LBACK           0x00000010  // Loopback Mode
+#define CAN_TST_SILENT          0x00000008  // Silent Mode
+#define CAN_TST_BASIC           0x00000004  // Basic Mode
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the CAN_O_BRPE register.
 //
 //*****************************************************************************
-#define CAN_BRPE_BRPE_M         0x0000000F  // Baud Rate Prescaler Extension.
+#define CAN_BRPE_BRPE_M         0x0000000F  // Baud Rate Prescaler Extension
 #define CAN_BRPE_BRPE_S         0
 
 //*****************************************************************************
@@ -2525,33 +2492,34 @@
 // The following are defines for the bit fields in the CAN_O_IF1CRQ register.
 //
 //*****************************************************************************
-#define CAN_IF1CRQ_BUSY         0x00008000  // Busy Flag.
-#define CAN_IF1CRQ_MNUM_M       0x0000003F  // Message Number.
+#define CAN_IF1CRQ_BUSY         0x00008000  // Busy Flag
+#define CAN_IF1CRQ_MNUM_M       0x0000003F  // Message Number
 #define CAN_IF1CRQ_MNUM_RSVD    0x00000000  // 0 is not a valid message number;
                                             // it is interpreted as 0x20, or
-                                            // object 32.
+                                            // object 32
+#define CAN_IF1CRQ_MNUM_S       0
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the CAN_O_IF1CMSK register.
 //
 //*****************************************************************************
-#define CAN_IF1CMSK_WRNRD       0x00000080  // Write, Not Read.
-#define CAN_IF1CMSK_MASK        0x00000040  // Access Mask Bits.
-#define CAN_IF1CMSK_ARB         0x00000020  // Access Arbitration Bits.
-#define CAN_IF1CMSK_CONTROL     0x00000010  // Access Control Bits.
-#define CAN_IF1CMSK_CLRINTPND   0x00000008  // Clear Interrupt Pending Bit.
-#define CAN_IF1CMSK_NEWDAT      0x00000004  // NEWDAT 
-#define CAN_IF1CMSK_TXRQST      0x00000004  //  TXRQST Bit.
-#define CAN_IF1CMSK_DATAA       0x00000002  // Access Data Byte 0 to 3.
-#define CAN_IF1CMSK_DATAB       0x00000001  // Access Data Byte 4 to 7.
+#define CAN_IF1CMSK_WRNRD       0x00000080  // Write, Not Read
+#define CAN_IF1CMSK_MASK        0x00000040  // Access Mask Bits
+#define CAN_IF1CMSK_ARB         0x00000020  // Access Arbitration Bits
+#define CAN_IF1CMSK_CONTROL     0x00000010  // Access Control Bits
+#define CAN_IF1CMSK_CLRINTPND   0x00000008  // Clear Interrupt Pending Bit
+#define CAN_IF1CMSK_NEWDAT      0x00000004  // Access New Data
+#define CAN_IF1CMSK_TXRQST      0x00000004  // Access Transmission Request
+#define CAN_IF1CMSK_DATAA       0x00000002  // Access Data Byte 0 to 3
+#define CAN_IF1CMSK_DATAB       0x00000001  // Access Data Byte 4 to 7
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the CAN_O_IF1MSK1 register.
 //
 //*****************************************************************************
-#define CAN_IF1MSK1_IDMSK_M     0x0000FFFF  // Identifier Mask.
+#define CAN_IF1MSK1_IDMSK_M     0x0000FFFF  // Identifier Mask
 #define CAN_IF1MSK1_IDMSK_S     0
 
 //*****************************************************************************
@@ -2559,9 +2527,9 @@
 // The following are defines for the bit fields in the CAN_O_IF1MSK2 register.
 //
 //*****************************************************************************
-#define CAN_IF1MSK2_MXTD        0x00008000  // Mask Extended Identifier.
-#define CAN_IF1MSK2_MDIR        0x00004000  // Mask Message Direction.
-#define CAN_IF1MSK2_IDMSK_M     0x00001FFF  // Identifier Mask.
+#define CAN_IF1MSK2_MXTD        0x00008000  // Mask Extended Identifier
+#define CAN_IF1MSK2_MDIR        0x00004000  // Mask Message Direction
+#define CAN_IF1MSK2_IDMSK_M     0x00001FFF  // Identifier Mask
 #define CAN_IF1MSK2_IDMSK_S     0
 
 //*****************************************************************************
@@ -2569,7 +2537,7 @@
 // The following are defines for the bit fields in the CAN_O_IF1ARB1 register.
 //
 //*****************************************************************************
-#define CAN_IF1ARB1_ID_M        0x0000FFFF  // Message Identifier.
+#define CAN_IF1ARB1_ID_M        0x0000FFFF  // Message Identifier
 #define CAN_IF1ARB1_ID_S        0
 
 //*****************************************************************************
@@ -2577,10 +2545,10 @@
 // The following are defines for the bit fields in the CAN_O_IF1ARB2 register.
 //
 //*****************************************************************************
-#define CAN_IF1ARB2_MSGVAL      0x00008000  // Message Valid.
-#define CAN_IF1ARB2_XTD         0x00004000  // Extended Identifier.
-#define CAN_IF1ARB2_DIR         0x00002000  // Message Direction.
-#define CAN_IF1ARB2_ID_M        0x00001FFF  // Message Identifier.
+#define CAN_IF1ARB2_MSGVAL      0x00008000  // Message Valid
+#define CAN_IF1ARB2_XTD         0x00004000  // Extended Identifier
+#define CAN_IF1ARB2_DIR         0x00002000  // Message Direction
+#define CAN_IF1ARB2_ID_M        0x00001FFF  // Message Identifier
 #define CAN_IF1ARB2_ID_S        0
 
 //*****************************************************************************
@@ -2588,16 +2556,16 @@
 // The following are defines for the bit fields in the CAN_O_IF1MCTL register.
 //
 //*****************************************************************************
-#define CAN_IF1MCTL_NEWDAT      0x00008000  // New Data.
-#define CAN_IF1MCTL_MSGLST      0x00004000  // Message Lost.
-#define CAN_IF1MCTL_INTPND      0x00002000  // Interrupt Pending.
-#define CAN_IF1MCTL_UMASK       0x00001000  // Use Acceptance Mask.
-#define CAN_IF1MCTL_TXIE        0x00000800  // Transmit Interrupt Enable.
-#define CAN_IF1MCTL_RXIE        0x00000400  // Receive Interrupt Enable.
-#define CAN_IF1MCTL_RMTEN       0x00000200  // Remote Enable.
-#define CAN_IF1MCTL_TXRQST      0x00000100  // Transmit Request.
-#define CAN_IF1MCTL_EOB         0x00000080  // End of Buffer.
-#define CAN_IF1MCTL_DLC_M       0x0000000F  // Data Length Code.
+#define CAN_IF1MCTL_NEWDAT      0x00008000  // New Data
+#define CAN_IF1MCTL_MSGLST      0x00004000  // Message Lost
+#define CAN_IF1MCTL_INTPND      0x00002000  // Interrupt Pending
+#define CAN_IF1MCTL_UMASK       0x00001000  // Use Acceptance Mask
+#define CAN_IF1MCTL_TXIE        0x00000800  // Transmit Interrupt Enable
+#define CAN_IF1MCTL_RXIE        0x00000400  // Receive Interrupt Enable
+#define CAN_IF1MCTL_RMTEN       0x00000200  // Remote Enable
+#define CAN_IF1MCTL_TXRQST      0x00000100  // Transmit Request
+#define CAN_IF1MCTL_EOB         0x00000080  // End of Buffer
+#define CAN_IF1MCTL_DLC_M       0x0000000F  // Data Length Code
 #define CAN_IF1MCTL_DLC_S       0
 
 //*****************************************************************************
@@ -2605,7 +2573,7 @@
 // The following are defines for the bit fields in the CAN_O_IF1DA1 register.
 //
 //*****************************************************************************
-#define CAN_IF1DA1_DATA_M       0x0000FFFF  // Data.
+#define CAN_IF1DA1_DATA_M       0x0000FFFF  // Data
 #define CAN_IF1DA1_DATA_S       0
 
 //*****************************************************************************
@@ -2613,7 +2581,7 @@
 // The following are defines for the bit fields in the CAN_O_IF1DA2 register.
 //
 //*****************************************************************************
-#define CAN_IF1DA2_DATA_M       0x0000FFFF  // Data.
+#define CAN_IF1DA2_DATA_M       0x0000FFFF  // Data
 #define CAN_IF1DA2_DATA_S       0
 
 //*****************************************************************************
@@ -2621,7 +2589,7 @@
 // The following are defines for the bit fields in the CAN_O_IF1DB1 register.
 //
 //*****************************************************************************
-#define CAN_IF1DB1_DATA_M       0x0000FFFF  // Data.
+#define CAN_IF1DB1_DATA_M       0x0000FFFF  // Data
 #define CAN_IF1DB1_DATA_S       0
 
 //*****************************************************************************
@@ -2629,7 +2597,7 @@
 // The following are defines for the bit fields in the CAN_O_IF1DB2 register.
 //
 //*****************************************************************************
-#define CAN_IF1DB2_DATA_M       0x0000FFFF  // Data.
+#define CAN_IF1DB2_DATA_M       0x0000FFFF  // Data
 #define CAN_IF1DB2_DATA_S       0
 
 //*****************************************************************************
@@ -2637,33 +2605,34 @@
 // The following are defines for the bit fields in the CAN_O_IF2CRQ register.
 //
 //*****************************************************************************
-#define CAN_IF2CRQ_BUSY         0x00008000  // Busy Flag.
-#define CAN_IF2CRQ_MNUM_M       0x0000003F  // Message Number.
+#define CAN_IF2CRQ_BUSY         0x00008000  // Busy Flag
+#define CAN_IF2CRQ_MNUM_M       0x0000003F  // Message Number
 #define CAN_IF2CRQ_MNUM_RSVD    0x00000000  // 0 is not a valid message number;
                                             // it is interpreted as 0x20, or
-                                            // object 32.
+                                            // object 32
+#define CAN_IF2CRQ_MNUM_S       0
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the CAN_O_IF2CMSK register.
 //
 //*****************************************************************************
-#define CAN_IF2CMSK_WRNRD       0x00000080  // Write, Not Read.
-#define CAN_IF2CMSK_MASK        0x00000040  // Access Mask Bits.
-#define CAN_IF2CMSK_ARB         0x00000020  // Access Arbitration Bits.
-#define CAN_IF2CMSK_CONTROL     0x00000010  // Access Control Bits.
-#define CAN_IF2CMSK_CLRINTPND   0x00000008  // Clear Interrupt Pending Bit.
-#define CAN_IF2CMSK_NEWDAT      0x00000004  // NEWDAT 
-#define CAN_IF2CMSK_TXRQST      0x00000004  //  TXRQST Bit.
-#define CAN_IF2CMSK_DATAA       0x00000002  // Access Data Byte 0 to 3.
-#define CAN_IF2CMSK_DATAB       0x00000001  // Access Data Byte 4 to 7.
+#define CAN_IF2CMSK_WRNRD       0x00000080  // Write, Not Read
+#define CAN_IF2CMSK_MASK        0x00000040  // Access Mask Bits
+#define CAN_IF2CMSK_ARB         0x00000020  // Access Arbitration Bits
+#define CAN_IF2CMSK_CONTROL     0x00000010  // Access Control Bits
+#define CAN_IF2CMSK_CLRINTPND   0x00000008  // Clear Interrupt Pending Bit
+#define CAN_IF2CMSK_NEWDAT      0x00000004  // Access New Data
+#define CAN_IF2CMSK_TXRQST      0x00000004  // Access Transmission Request
+#define CAN_IF2CMSK_DATAA       0x00000002  // Access Data Byte 0 to 3
+#define CAN_IF2CMSK_DATAB       0x00000001  // Access Data Byte 4 to 7
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the CAN_O_IF2MSK1 register.
 //
 //*****************************************************************************
-#define CAN_IF2MSK1_IDMSK_M     0x0000FFFF  // Identifier Mask.
+#define CAN_IF2MSK1_IDMSK_M     0x0000FFFF  // Identifier Mask
 #define CAN_IF2MSK1_IDMSK_S     0
 
 //*****************************************************************************
@@ -2671,9 +2640,9 @@
 // The following are defines for the bit fields in the CAN_O_IF2MSK2 register.
 //
 //*****************************************************************************
-#define CAN_IF2MSK2_MXTD        0x00008000  // Mask Extended Identifier.
-#define CAN_IF2MSK2_MDIR        0x00004000  // Mask Message Direction.
-#define CAN_IF2MSK2_IDMSK_M     0x00001FFF  // Identifier Mask.
+#define CAN_IF2MSK2_MXTD        0x00008000  // Mask Extended Identifier
+#define CAN_IF2MSK2_MDIR        0x00004000  // Mask Message Direction
+#define CAN_IF2MSK2_IDMSK_M     0x00001FFF  // Identifier Mask
 #define CAN_IF2MSK2_IDMSK_S     0
 
 //*****************************************************************************
@@ -2681,7 +2650,7 @@
 // The following are defines for the bit fields in the CAN_O_IF2ARB1 register.
 //
 //*****************************************************************************
-#define CAN_IF2ARB1_ID_M        0x0000FFFF  // Message Identifier.
+#define CAN_IF2ARB1_ID_M        0x0000FFFF  // Message Identifier
 #define CAN_IF2ARB1_ID_S        0
 
 //*****************************************************************************
@@ -2689,10 +2658,10 @@
 // The following are defines for the bit fields in the CAN_O_IF2ARB2 register.
 //
 //*****************************************************************************
-#define CAN_IF2ARB2_MSGVAL      0x00008000  // Message Valid.
-#define CAN_IF2ARB2_XTD         0x00004000  // Extended Identifier.
-#define CAN_IF2ARB2_DIR         0x00002000  // Message Direction.
-#define CAN_IF2ARB2_ID_M        0x00001FFF  // Message Identifier.
+#define CAN_IF2ARB2_MSGVAL      0x00008000  // Message Valid
+#define CAN_IF2ARB2_XTD         0x00004000  // Extended Identifier
+#define CAN_IF2ARB2_DIR         0x00002000  // Message Direction
+#define CAN_IF2ARB2_ID_M        0x00001FFF  // Message Identifier
 #define CAN_IF2ARB2_ID_S        0
 
 //*****************************************************************************
@@ -2700,16 +2669,16 @@
 // The following are defines for the bit fields in the CAN_O_IF2MCTL register.
 //
 //*****************************************************************************
-#define CAN_IF2MCTL_NEWDAT      0x00008000  // New Data.
-#define CAN_IF2MCTL_MSGLST      0x00004000  // Message Lost.
-#define CAN_IF2MCTL_INTPND      0x00002000  // Interrupt Pending.
-#define CAN_IF2MCTL_UMASK       0x00001000  // Use Acceptance Mask.
-#define CAN_IF2MCTL_TXIE        0x00000800  // Transmit Interrupt Enable.
-#define CAN_IF2MCTL_RXIE        0x00000400  // Receive Interrupt Enable.
-#define CAN_IF2MCTL_RMTEN       0x00000200  // Remote Enable.
-#define CAN_IF2MCTL_TXRQST      0x00000100  // Transmit Request.
-#define CAN_IF2MCTL_EOB         0x00000080  // End of Buffer.
-#define CAN_IF2MCTL_DLC_M       0x0000000F  // Data Length Code.
+#define CAN_IF2MCTL_NEWDAT      0x00008000  // New Data
+#define CAN_IF2MCTL_MSGLST      0x00004000  // Message Lost
+#define CAN_IF2MCTL_INTPND      0x00002000  // Interrupt Pending
+#define CAN_IF2MCTL_UMASK       0x00001000  // Use Acceptance Mask
+#define CAN_IF2MCTL_TXIE        0x00000800  // Transmit Interrupt Enable
+#define CAN_IF2MCTL_RXIE        0x00000400  // Receive Interrupt Enable
+#define CAN_IF2MCTL_RMTEN       0x00000200  // Remote Enable
+#define CAN_IF2MCTL_TXRQST      0x00000100  // Transmit Request
+#define CAN_IF2MCTL_EOB         0x00000080  // End of Buffer
+#define CAN_IF2MCTL_DLC_M       0x0000000F  // Data Length Code
 #define CAN_IF2MCTL_DLC_S       0
 
 //*****************************************************************************
@@ -2717,7 +2686,7 @@
 // The following are defines for the bit fields in the CAN_O_IF2DA1 register.
 //
 //*****************************************************************************
-#define CAN_IF2DA1_DATA_M       0x0000FFFF  // Data.
+#define CAN_IF2DA1_DATA_M       0x0000FFFF  // Data
 #define CAN_IF2DA1_DATA_S       0
 
 //*****************************************************************************
@@ -2725,7 +2694,7 @@
 // The following are defines for the bit fields in the CAN_O_IF2DA2 register.
 //
 //*****************************************************************************
-#define CAN_IF2DA2_DATA_M       0x0000FFFF  // Data.
+#define CAN_IF2DA2_DATA_M       0x0000FFFF  // Data
 #define CAN_IF2DA2_DATA_S       0
 
 //*****************************************************************************
@@ -2733,7 +2702,7 @@
 // The following are defines for the bit fields in the CAN_O_IF2DB1 register.
 //
 //*****************************************************************************
-#define CAN_IF2DB1_DATA_M       0x0000FFFF  // Data.
+#define CAN_IF2DB1_DATA_M       0x0000FFFF  // Data
 #define CAN_IF2DB1_DATA_S       0
 
 //*****************************************************************************
@@ -2741,7 +2710,7 @@
 // The following are defines for the bit fields in the CAN_O_IF2DB2 register.
 //
 //*****************************************************************************
-#define CAN_IF2DB2_DATA_M       0x0000FFFF  // Data.
+#define CAN_IF2DB2_DATA_M       0x0000FFFF  // Data
 #define CAN_IF2DB2_DATA_S       0
 
 //*****************************************************************************
@@ -2749,7 +2718,7 @@
 // The following are defines for the bit fields in the CAN_O_TXRQ1 register.
 //
 //*****************************************************************************
-#define CAN_TXRQ1_TXRQST_M      0x0000FFFF  // Transmission Request Bits.
+#define CAN_TXRQ1_TXRQST_M      0x0000FFFF  // Transmission Request Bits
 #define CAN_TXRQ1_TXRQST_S      0
 
 //*****************************************************************************
@@ -2757,7 +2726,7 @@
 // The following are defines for the bit fields in the CAN_O_TXRQ2 register.
 //
 //*****************************************************************************
-#define CAN_TXRQ2_TXRQST_M      0x0000FFFF  // Transmission Request Bits.
+#define CAN_TXRQ2_TXRQST_M      0x0000FFFF  // Transmission Request Bits
 #define CAN_TXRQ2_TXRQST_S      0
 
 //*****************************************************************************
@@ -2765,7 +2734,7 @@
 // The following are defines for the bit fields in the CAN_O_NWDA1 register.
 //
 //*****************************************************************************
-#define CAN_NWDA1_NEWDAT_M      0x0000FFFF  // New Data Bits.
+#define CAN_NWDA1_NEWDAT_M      0x0000FFFF  // New Data Bits
 #define CAN_NWDA1_NEWDAT_S      0
 
 //*****************************************************************************
@@ -2773,7 +2742,7 @@
 // The following are defines for the bit fields in the CAN_O_NWDA2 register.
 //
 //*****************************************************************************
-#define CAN_NWDA2_NEWDAT_M      0x0000FFFF  // New Data Bits.
+#define CAN_NWDA2_NEWDAT_M      0x0000FFFF  // New Data Bits
 #define CAN_NWDA2_NEWDAT_S      0
 
 //*****************************************************************************
@@ -2781,7 +2750,7 @@
 // The following are defines for the bit fields in the CAN_O_MSG1INT register.
 //
 //*****************************************************************************
-#define CAN_MSG1INT_INTPND_M    0x0000FFFF  // Interrupt Pending Bits.
+#define CAN_MSG1INT_INTPND_M    0x0000FFFF  // Interrupt Pending Bits
 #define CAN_MSG1INT_INTPND_S    0
 
 //*****************************************************************************
@@ -2789,7 +2758,7 @@
 // The following are defines for the bit fields in the CAN_O_MSG2INT register.
 //
 //*****************************************************************************
-#define CAN_MSG2INT_INTPND_M    0x0000FFFF  // Interrupt Pending Bits.
+#define CAN_MSG2INT_INTPND_M    0x0000FFFF  // Interrupt Pending Bits
 #define CAN_MSG2INT_INTPND_S    0
 
 //*****************************************************************************
@@ -2797,7 +2766,7 @@
 // The following are defines for the bit fields in the CAN_O_MSG1VAL register.
 //
 //*****************************************************************************
-#define CAN_MSG1VAL_MSGVAL_M    0x0000FFFF  // Message Valid Bits.
+#define CAN_MSG1VAL_MSGVAL_M    0x0000FFFF  // Message Valid Bits
 #define CAN_MSG1VAL_MSGVAL_S    0
 
 //*****************************************************************************
@@ -2805,127 +2774,247 @@
 // The following are defines for the bit fields in the CAN_O_MSG2VAL register.
 //
 //*****************************************************************************
-#define CAN_MSG2VAL_MSGVAL_M    0x0000FFFF  // Message Valid Bits.
+#define CAN_MSG2VAL_MSGVAL_M    0x0000FFFF  // Message Valid Bits
 #define CAN_MSG2VAL_MSGVAL_S    0
 
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_MR0 register.
-//
-//*****************************************************************************
-#define PHY_MR0_RESET           0x00008000  // Reset Registers.
-#define PHY_MR0_LOOPBK          0x00004000  // Loopback Mode.
-#define PHY_MR0_SPEEDSL         0x00002000  // Speed Select.
-#define PHY_MR0_ANEGEN          0x00001000  // Auto-Negotiation Enable.
-#define PHY_MR0_PWRDN           0x00000800  // Power Down.
-#define PHY_MR0_ISO             0x00000400  // Isolate.
-#define PHY_MR0_RANEG           0x00000200  // Restart Auto-Negotiation.
-#define PHY_MR0_DUPLEX          0x00000100  // Set Duplex Mode.
-#define PHY_MR0_COLT            0x00000080  // Collision Test.
-
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the MAC_O_RIS register.
 //
 //*****************************************************************************
-#define MAC_RIS_PHYINT          0x00000040  // PHY Interrupt.
-#define MAC_RIS_MDINT           0x00000020  // MII Transaction Complete.
-#define MAC_RIS_RXER            0x00000010  // Receive Error.
-#define MAC_RIS_FOV             0x00000008  // FIFO Overrun.
-#define MAC_RIS_TXEMP           0x00000004  // Transmit FIFO Empty.
-#define MAC_RIS_TXER            0x00000002  // Transmit Error.
-#define MAC_RIS_RXINT           0x00000001  // Packet Received.
+#define MAC_RIS_PHYINT          0x00000040  // PHY Interrupt
+#define MAC_RIS_MDINT           0x00000020  // MII Transaction Complete
+#define MAC_RIS_RXER            0x00000010  // Receive Error
+#define MAC_RIS_FOV             0x00000008  // FIFO Overrun
+#define MAC_RIS_TXEMP           0x00000004  // Transmit FIFO Empty
+#define MAC_RIS_TXER            0x00000002  // Transmit Error
+#define MAC_RIS_RXINT           0x00000001  // Packet Received
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the MAC_O_IACK register.
 //
 //*****************************************************************************
-#define MAC_IACK_PHYINT         0x00000040  // Clear PHY Interrupt.
-#define MAC_IACK_MDINT          0x00000020  // Clear MII Transaction Complete.
-#define MAC_IACK_RXER           0x00000010  // Clear Receive Error.
-#define MAC_IACK_FOV            0x00000008  // Clear FIFO Overrun.
-#define MAC_IACK_TXEMP          0x00000004  // Clear Transmit FIFO Empty.
-#define MAC_IACK_TXER           0x00000002  // Clear Transmit Error.
-#define MAC_IACK_RXINT          0x00000001  // Clear Packet Received.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_MR1 register.
-//
-//*****************************************************************************
-#define PHY_MR1_100X_F          0x00004000  // 100BASE-TX Full-Duplex Mode.
-#define PHY_MR1_100X_H          0x00002000  // 100BASE-TX Half-Duplex Mode.
-#define PHY_MR1_10T_F           0x00001000  // 10BASE-T Full-Duplex Mode.
-#define PHY_MR1_10T_H           0x00000800  // 10BASE-T Half-Duplex Mode.
-#define PHY_MR1_MFPS            0x00000040  // Management Frames with Preamble
-                                            // Suppressed.
-#define PHY_MR1_ANEGC           0x00000020  // Auto-Negotiation Complete.
-#define PHY_MR1_RFAULT          0x00000010  // Remote Fault.
-#define PHY_MR1_ANEGA           0x00000008  // Auto-Negotiation.
-#define PHY_MR1_LINK            0x00000004  // Link Made.
-#define PHY_MR1_JAB             0x00000002  // Jabber Condition.
-#define PHY_MR1_EXTD            0x00000001  // Extended Capabilities.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_MR2 register.
-//
-//*****************************************************************************
-#define PHY_MR2_OUI_M           0x0000FFFF  // Organizationally Unique
-                                            // Identifier[21:6].
-#define PHY_MR2_OUI_S           0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_MR3 register.
-//
-//*****************************************************************************
-#define PHY_MR3_OUI_M           0x0000FC00  // Organizationally Unique
-                                            // Identifier[5:0].
-#define PHY_MR3_MN_M            0x000003F0  // Model Number.
-#define PHY_MR3_RN_M            0x0000000F  // Revision Number.
-#define PHY_MR3_OUI_S           10
-#define PHY_MR3_MN_S            4
-#define PHY_MR3_RN_S            0
+#define MAC_IACK_PHYINT         0x00000040  // Clear PHY Interrupt
+#define MAC_IACK_MDINT          0x00000020  // Clear MII Transaction Complete
+#define MAC_IACK_RXER           0x00000010  // Clear Receive Error
+#define MAC_IACK_FOV            0x00000008  // Clear FIFO Overrun
+#define MAC_IACK_TXEMP          0x00000004  // Clear Transmit FIFO Empty
+#define MAC_IACK_TXER           0x00000002  // Clear Transmit Error
+#define MAC_IACK_RXINT          0x00000001  // Clear Packet Received
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the MAC_O_IM register.
 //
 //*****************************************************************************
-#define MAC_IM_PHYINTM          0x00000040  // Mask PHY Interrupt.
-#define MAC_IM_MDINTM           0x00000020  // Mask MII Transaction Complete.
-#define MAC_IM_RXERM            0x00000010  // Mask Receive Error.
-#define MAC_IM_FOVM             0x00000008  // Mask FIFO Overrun.
-#define MAC_IM_TXEMPM           0x00000004  // Mask Transmit FIFO Empty.
-#define MAC_IM_TXERM            0x00000002  // Mask Transmit Error.
-#define MAC_IM_RXINTM           0x00000001  // Mask Packet Received.
+#define MAC_IM_PHYINTM          0x00000040  // Mask PHY Interrupt
+#define MAC_IM_MDINTM           0x00000020  // Mask MII Transaction Complete
+#define MAC_IM_RXERM            0x00000010  // Mask Receive Error
+#define MAC_IM_FOVM             0x00000008  // Mask FIFO Overrun
+#define MAC_IM_TXEMPM           0x00000004  // Mask Transmit FIFO Empty
+#define MAC_IM_TXERM            0x00000002  // Mask Transmit Error
+#define MAC_IM_RXINTM           0x00000001  // Mask Packet Received
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the MAC_O_MR4 register.
+// The following are defines for the bit fields in the MAC_O_RCTL register.
 //
 //*****************************************************************************
-#define PHY_MR4_NP              0x00008000  // Next Page.
-#define PHY_MR4_RF              0x00002000  // Remote Fault.
-#define PHY_MR4_A3              0x00000100  // Technology Ability Field[3].
-#define PHY_MR4_A2              0x00000080  // Technology Ability Field[2].
-#define PHY_MR4_A1              0x00000040  // Technology Ability Field[1].
-#define PHY_MR4_A0              0x00000020  // Technology Ability Field[0].
-#define PHY_MR4_S_M             0x0000001F  // Selector Field.
+#define MAC_RCTL_RSTFIFO        0x00000010  // Clear Receive FIFO
+#define MAC_RCTL_BADCRC         0x00000008  // Enable Reject Bad CRC
+#define MAC_RCTL_PRMS           0x00000004  // Enable Promiscuous Mode
+#define MAC_RCTL_AMUL           0x00000002  // Enable Multicast Frames
+#define MAC_RCTL_RXEN           0x00000001  // Enable Receiver
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_TCTL register.
+//
+//*****************************************************************************
+#define MAC_TCTL_DUPLEX         0x00000010  // Enable Duplex Mode
+#define MAC_TCTL_CRC            0x00000004  // Enable CRC Generation
+#define MAC_TCTL_PADEN          0x00000002  // Enable Packet Padding
+#define MAC_TCTL_TXEN           0x00000001  // Enable Transmitter
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_DATA register.
+//
+//*****************************************************************************
+#define MAC_DATA_TXDATA_M       0xFFFFFFFF  // Transmit FIFO Data
+#define MAC_DATA_RXDATA_M       0xFFFFFFFF  // Receive FIFO Data
+#define MAC_DATA_RXDATA_S       0
+#define MAC_DATA_TXDATA_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_IA0 register.
+//
+//*****************************************************************************
+#define MAC_IA0_MACOCT4_M       0xFF000000  // MAC Address Octet 4
+#define MAC_IA0_MACOCT3_M       0x00FF0000  // MAC Address Octet 3
+#define MAC_IA0_MACOCT2_M       0x0000FF00  // MAC Address Octet 2
+#define MAC_IA0_MACOCT1_M       0x000000FF  // MAC Address Octet 1
+#define MAC_IA0_MACOCT4_S       24
+#define MAC_IA0_MACOCT3_S       16
+#define MAC_IA0_MACOCT2_S       8
+#define MAC_IA0_MACOCT1_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_IA1 register.
+//
+//*****************************************************************************
+#define MAC_IA1_MACOCT6_M       0x0000FF00  // MAC Address Octet 6
+#define MAC_IA1_MACOCT5_M       0x000000FF  // MAC Address Octet 5
+#define MAC_IA1_MACOCT6_S       8
+#define MAC_IA1_MACOCT5_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_THR register.
+//
+//*****************************************************************************
+#define MAC_THR_THRESH_M        0x0000003F  // Threshold Value
+#define MAC_THR_THRESH_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MCTL register.
+//
+//*****************************************************************************
+#define MAC_MCTL_REGADR_M       0x000000F8  // MII Register Address
+#define MAC_MCTL_WRITE          0x00000002  // MII Register Transaction Type
+#define MAC_MCTL_START          0x00000001  // MII Register Transaction Enable
+#define MAC_MCTL_REGADR_S       3
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MDV register.
+//
+//*****************************************************************************
+#define MAC_MDV_DIV_M           0x000000FF  // Clock Divider
+#define MAC_MDV_DIV_S           0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MTXD register.
+//
+//*****************************************************************************
+#define MAC_MTXD_MDTX_M         0x0000FFFF  // MII Register Transmit Data
+#define MAC_MTXD_MDTX_S         0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MRXD register.
+//
+//*****************************************************************************
+#define MAC_MRXD_MDRX_M         0x0000FFFF  // MII Register Receive Data
+#define MAC_MRXD_MDRX_S         0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_NP register.
+//
+//*****************************************************************************
+#define MAC_NP_NPR_M            0x0000003F  // Number of Packets in Receive
+                                            // FIFO
+#define MAC_NP_NPR_S            0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_TR register.
+//
+//*****************************************************************************
+#define MAC_TR_NEWTX            0x00000001  // New Transmission
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_TS register.
+//
+//*****************************************************************************
+#define MAC_TS_TSEN             0x00000001  // Time Stamp Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR0 register.
+//
+//*****************************************************************************
+#define PHY_MR0_RESET           0x00008000  // Reset Registers
+#define PHY_MR0_LOOPBK          0x00004000  // Loopback Mode
+#define PHY_MR0_SPEEDSL         0x00002000  // Speed Select
+#define PHY_MR0_ANEGEN          0x00001000  // Auto-Negotiation Enable
+#define PHY_MR0_PWRDN           0x00000800  // Power Down
+#define PHY_MR0_ISO             0x00000400  // Isolate
+#define PHY_MR0_RANEG           0x00000200  // Restart Auto-Negotiation
+#define PHY_MR0_DUPLEX          0x00000100  // Set Duplex Mode
+#define PHY_MR0_COLT            0x00000080  // Collision Test
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR1 register.
+//
+//*****************************************************************************
+#define PHY_MR1_100X_F          0x00004000  // 100BASE-TX Full-Duplex Mode
+#define PHY_MR1_100X_H          0x00002000  // 100BASE-TX Half-Duplex Mode
+#define PHY_MR1_10T_F           0x00001000  // 10BASE-T Full-Duplex Mode
+#define PHY_MR1_10T_H           0x00000800  // 10BASE-T Half-Duplex Mode
+#define PHY_MR1_MFPS            0x00000040  // Management Frames with Preamble
+                                            // Suppressed
+#define PHY_MR1_ANEGC           0x00000020  // Auto-Negotiation Complete
+#define PHY_MR1_RFAULT          0x00000010  // Remote Fault
+#define PHY_MR1_ANEGA           0x00000008  // Auto-Negotiation
+#define PHY_MR1_LINK            0x00000004  // Link Made
+#define PHY_MR1_JAB             0x00000002  // Jabber Condition
+#define PHY_MR1_EXTD            0x00000001  // Extended Capabilities
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR2 register.
+//
+//*****************************************************************************
+#define PHY_MR2_OUI_M           0x0000FFFF  // Organizationally Unique
+                                            // Identifier[21:6]
+#define PHY_MR2_OUI_S           0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR3 register.
+//
+//*****************************************************************************
+#define PHY_MR3_OUI_M           0x0000FC00  // Organizationally Unique
+                                            // Identifier[5:0]
+#define PHY_MR3_MN_M            0x000003F0  // Model Number
+#define PHY_MR3_RN_M            0x0000000F  // Revision Number
+#define PHY_MR3_OUI_S           10
+#define PHY_MR3_MN_S            4
+#define PHY_MR3_RN_S            0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR4 register.
+//
+//*****************************************************************************
+#define PHY_MR4_NP              0x00008000  // Next Page
+#define PHY_MR4_RF              0x00002000  // Remote Fault
+#define PHY_MR4_A3              0x00000100  // Technology Ability Field [3]
+#define PHY_MR4_A2              0x00000080  // Technology Ability Field [2]
+#define PHY_MR4_A1              0x00000040  // Technology Ability Field [1]
+#define PHY_MR4_A0              0x00000020  // Technology Ability Field [0]
+#define PHY_MR4_S_M             0x0000001F  // Selector Field
 #define PHY_MR4_S_S             0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the MAC_O_MR5 register.
+// The following are defines for the bit fields in the PHY_MR5 register.
 //
 //*****************************************************************************
-#define PHY_MR5_NP              0x00008000  // Next Page.
-#define PHY_MR5_ACK             0x00004000  // Acknowledge.
-#define PHY_MR5_RF              0x00002000  // Remote Fault.
-#define PHY_MR5_A_M             0x00001FE0  // Technology Ability Field.
-#define PHY_MR5_S_M             0x0000001F  // Selector Field.
+#define PHY_MR5_NP              0x00008000  // Next Page
+#define PHY_MR5_ACK             0x00004000  // Acknowledge
+#define PHY_MR5_RF              0x00002000  // Remote Fault
+#define PHY_MR5_A_M             0x00001FE0  // Technology Ability Field
+#define PHY_MR5_S_M             0x0000001F  // Selector Field
 #define PHY_MR5_S_8023          0x00000001  // IEEE Std 802.3
 #define PHY_MR5_S_8029          0x00000002  // IEEE Std 802.9 ISLAN-16T
 #define PHY_MR5_S_8025          0x00000003  // IEEE Std 802.5
@@ -2934,105 +3023,74 @@
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the MAC_O_MR6 register.
+// The following are defines for the bit fields in the PHY_MR6 register.
 //
 //*****************************************************************************
-#define PHY_MR6_PDF             0x00000010  // Parallel Detection Fault.
-#define PHY_MR6_LPNPA           0x00000008  // Link Partner is Next Page Able.
-#define PHY_MR6_PRX             0x00000002  // New Page Received.
+#define PHY_MR6_PDF             0x00000010  // Parallel Detection Fault
+#define PHY_MR6_LPNPA           0x00000008  // Link Partner is Next Page Able
+#define PHY_MR6_PRX             0x00000002  // New Page Received
 #define PHY_MR6_LPANEGA         0x00000001  // Link Partner is Auto-Negotiation
-                                            // Able.
+                                            // Able
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the MAC_O_RCTL register.
+// The following are defines for the bit fields in the PHY_MR16 register.
 //
 //*****************************************************************************
-#define MAC_RCTL_RSTFIFO        0x00000010  // Clear Receive FIFO.
-#define MAC_RCTL_BADCRC         0x00000008  // Enable Reject Bad CRC.
-#define MAC_RCTL_PRMS           0x00000004  // Enable Promiscuous Mode.
-#define MAC_RCTL_AMUL           0x00000002  // Enable Multicast Frames.
-#define MAC_RCTL_RXEN           0x00000001  // Enable Receiver.
+#define PHY_MR16_RPTR           0x00008000  // Repeater Mode
+#define PHY_MR16_INPOL          0x00004000  // Interrupt Polarity
+#define PHY_MR16_TXHIM          0x00001000  // Transmit High Impedance Mode
+#define PHY_MR16_SQEI           0x00000800  // SQE Inhibit Testing
+#define PHY_MR16_NL10           0x00000400  // Natural Loopback Mode
+#define PHY_MR16_APOL           0x00000020  // Auto-Polarity Disable
+#define PHY_MR16_RVSPOL         0x00000010  // Receive Data Polarity
+#define PHY_MR16_PCSBP          0x00000002  // PCS Bypass
+#define PHY_MR16_RXCC           0x00000001  // Receive Clock Control
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the MAC_O_TCTL register.
+// The following are defines for the bit fields in the PHY_MR17 register.
 //
 //*****************************************************************************
-#define MAC_TCTL_DUPLEX         0x00000010  // Enable Duplex Mode.
-#define MAC_TCTL_CRC            0x00000004  // Enable CRC Generation.
-#define MAC_TCTL_PADEN          0x00000002  // Enable Packet Padding.
-#define MAC_TCTL_TXEN           0x00000001  // Enable Transmitter.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_DATA register.
-//
-//*****************************************************************************
-#define MAC_DATA_TXDATA_M       0xFFFFFFFF  // Transmit FIFO Data.
-#define MAC_DATA_RXDATA_M       0xFFFFFFFF  // Receive FIFO Data.
-#define MAC_DATA_RXDATA_S       0
-#define MAC_DATA_TXDATA_S       0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_MR16 register.
-//
-//*****************************************************************************
-#define PHY_MR16_RPTR           0x00008000  // Repeater Mode.
-#define PHY_MR16_INPOL          0x00004000  // Interrupt Polarity.
-#define PHY_MR16_TXHIM          0x00001000  // Transmit High Impedance Mode.
-#define PHY_MR16_SQEI           0x00000800  // SQE Inhibit Testing.
-#define PHY_MR16_NL10           0x00000400  // Natural Loopback Mode.
-#define PHY_MR16_APOL           0x00000020  // Auto-Polarity Disable.
-#define PHY_MR16_RVSPOL         0x00000010  // Receive Data Polarity.
-#define PHY_MR16_PCSBP          0x00000002  // PCS Bypass.
-#define PHY_MR16_RXCC           0x00000001  // Receive Clock Control.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_MR17 register.
-//
-//*****************************************************************************
-#define PHY_MR17_JABBER_IE      0x00008000  // Jabber Interrupt Enable.
-#define PHY_MR17_RXER_IE        0x00004000  // Receive Error Interrupt Enable.
-#define PHY_MR17_PRX_IE         0x00002000  // Page Received Interrupt Enable.
+#define PHY_MR17_JABBER_IE      0x00008000  // Jabber Interrupt Enable
+#define PHY_MR17_RXER_IE        0x00004000  // Receive Error Interrupt Enable
+#define PHY_MR17_PRX_IE         0x00002000  // Page Received Interrupt Enable
 #define PHY_MR17_PDF_IE         0x00001000  // Parallel Detection Fault
-                                            // Interrupt Enable.
-#define PHY_MR17_LPACK_IE       0x00000800  // LP Acknowledge Interrupt Enable.
+                                            // Interrupt Enable
+#define PHY_MR17_LPACK_IE       0x00000800  // LP Acknowledge Interrupt Enable
 #define PHY_MR17_LSCHG_IE       0x00000400  // Link Status Change Interrupt
-                                            // Enable.
-#define PHY_MR17_RFAULT_IE      0x00000200  // Remote Fault Interrupt Enable.
+                                            // Enable
+#define PHY_MR17_RFAULT_IE      0x00000200  // Remote Fault Interrupt Enable
 #define PHY_MR17_ANEGCOMP_IE    0x00000100  // Auto-Negotiation Complete
-                                            // Interrupt Enable.
-#define PHY_MR17_JABBER_INT     0x00000080  // Jabber Event Interrupt.
-#define PHY_MR17_RXER_INT       0x00000040  // Receive Error Interrupt.
-#define PHY_MR17_PRX_INT        0x00000020  // Page Receive Interrupt.
+                                            // Interrupt Enable
+#define PHY_MR17_JABBER_INT     0x00000080  // Jabber Event Interrupt
+#define PHY_MR17_RXER_INT       0x00000040  // Receive Error Interrupt
+#define PHY_MR17_PRX_INT        0x00000020  // Page Receive Interrupt
 #define PHY_MR17_PDF_INT        0x00000010  // Parallel Detection Fault
-                                            // Interrupt.
-#define PHY_MR17_LPACK_INT      0x00000008  // LP Acknowledge Interrupt.
-#define PHY_MR17_LSCHG_INT      0x00000004  // Link Status Change Interrupt.
-#define PHY_MR17_RFAULT_INT     0x00000002  // Remote Fault Interrupt.
+                                            // Interrupt
+#define PHY_MR17_LPACK_INT      0x00000008  // LP Acknowledge Interrupt
+#define PHY_MR17_LSCHG_INT      0x00000004  // Link Status Change Interrupt
+#define PHY_MR17_RFAULT_INT     0x00000002  // Remote Fault Interrupt
 #define PHY_MR17_ANEGCOMP_INT   0x00000001  // Auto-Negotiation Complete
-                                            // Interrupt.
+                                            // Interrupt
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the MAC_O_MR18 register.
+// The following are defines for the bit fields in the PHY_MR18 register.
 //
 //*****************************************************************************
-#define PHY_MR18_ANEGF          0x00001000  // Auto-Negotiation Failure.
-#define PHY_MR18_DPLX           0x00000800  // Duplex Mode.
-#define PHY_MR18_RATE           0x00000400  // Rate.
-#define PHY_MR18_RXSD           0x00000200  // Receive Detection.
-#define PHY_MR18_RX_LOCK        0x00000100  // Receive PLL Lock.
+#define PHY_MR18_ANEGF          0x00001000  // Auto-Negotiation Failure
+#define PHY_MR18_DPLX           0x00000800  // Duplex Mode
+#define PHY_MR18_RATE           0x00000400  // Rate
+#define PHY_MR18_RXSD           0x00000200  // Receive Detection
+#define PHY_MR18_RX_LOCK        0x00000100  // Receive PLL Lock
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the MAC_O_MR19 register.
+// The following are defines for the bit fields in the PHY_MR19 register.
 //
 //*****************************************************************************
-#define PHY_MR19_TXO_M          0x0000C000  // Transmit Amplitude Selection.
+#define PHY_MR19_TXO_M          0x0000C000  // Transmit Amplitude Selection
 #define PHY_MR19_TXO_00DB       0x00000000  // Gain set for 0.0dB of insertion
                                             // loss
 #define PHY_MR19_TXO_04DB       0x00004000  // Gain set for 0.4dB of insertion
@@ -3044,24 +3102,10 @@
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the MAC_O_IA0 register.
+// The following are defines for the bit fields in the PHY_MR23 register.
 //
 //*****************************************************************************
-#define MAC_IA0_MACOCT4_M       0xFF000000  // MAC Address Octet 4.
-#define MAC_IA0_MACOCT3_M       0x00FF0000  // MAC Address Octet 3.
-#define MAC_IA0_MACOCT2_M       0x0000FF00  // MAC Address Octet 2.
-#define MAC_IA0_MACOCT1_M       0x000000FF  // MAC Address Octet 1.
-#define MAC_IA0_MACOCT4_S       24
-#define MAC_IA0_MACOCT3_S       16
-#define MAC_IA0_MACOCT2_S       8
-#define MAC_IA0_MACOCT1_S       0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_MR23 register.
-//
-//*****************************************************************************
-#define PHY_MR23_LED1_M         0x000000F0  // LED1 Source.
+#define PHY_MR23_LED1_M         0x000000F0  // LED1 Source
 #define PHY_MR23_LED1_LINK      0x00000000  // Link OK
 #define PHY_MR23_LED1_RXTX      0x00000010  // RX or TX Activity (Default LED1)
 #define PHY_MR23_LED1_100       0x00000050  // 100BASE-TX mode
@@ -3069,7 +3113,7 @@
 #define PHY_MR23_LED1_DUPLEX    0x00000070  // Full-Duplex
 #define PHY_MR23_LED1_LINKACT   0x00000080  // Link OK & Blink=RX or TX
                                             // Activity
-#define PHY_MR23_LED0_M         0x0000000F  // LED0 Source.
+#define PHY_MR23_LED0_M         0x0000000F  // LED0 Source
 #define PHY_MR23_LED0_LINK      0x00000000  // Link OK (Default LED0)
 #define PHY_MR23_LED0_RXTX      0x00000001  // RX or TX Activity
 #define PHY_MR23_LED0_100       0x00000005  // 100BASE-TX mode
@@ -3080,97 +3124,22 @@
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the MAC_O_IA1 register.
+// The following are defines for the bit fields in the PHY_MR24 register.
 //
 //*****************************************************************************
-#define MAC_IA1_MACOCT6_M       0x0000FF00  // MAC Address Octet 6.
-#define MAC_IA1_MACOCT5_M       0x000000FF  // MAC Address Octet 5.
-#define MAC_IA1_MACOCT6_S       8
-#define MAC_IA1_MACOCT5_S       0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_MR24 register.
-//
-//*****************************************************************************
-#define PHY_MR24_PD_MODE        0x00000080  // Parallel Detection Mode.
-#define PHY_MR24_AUTO_SW        0x00000040  // Auto-Switching Enable.
-#define PHY_MR24_MDIX           0x00000020  // Auto-Switching Configuration.
-#define PHY_MR24_MDIX_CM        0x00000010  // Auto-Switching Complete.
-#define PHY_MR24_MDIX_SD_M      0x0000000F  // Auto-Switching Seed.
+#define PHY_MR24_PD_MODE        0x00000080  // Parallel Detection Mode
+#define PHY_MR24_AUTO_SW        0x00000040  // Auto-Switching Enable
+#define PHY_MR24_MDIX           0x00000020  // Auto-Switching Configuration
+#define PHY_MR24_MDIX_CM        0x00000010  // Auto-Switching Complete
+#define PHY_MR24_MDIX_SD_M      0x0000000F  // Auto-Switching Seed
 #define PHY_MR24_MDIX_SD_S      0
 
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_THR register.
-//
-//*****************************************************************************
-#define MAC_THR_THRESH_M        0x0000003F  // Threshold Value.
-#define MAC_THR_THRESH_S        0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_MCTL register.
-//
-//*****************************************************************************
-#define MAC_MCTL_REGADR_M       0x000000F8  // MII Register Address.
-#define MAC_MCTL_WRITE          0x00000002  // MII Register Transaction Type.
-#define MAC_MCTL_START          0x00000001  // MII Register Transaction Enable.
-#define MAC_MCTL_REGADR_S       3
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_MDV register.
-//
-//*****************************************************************************
-#define MAC_MDV_DIV_M           0x000000FF  // Clock Divider.
-#define MAC_MDV_DIV_S           0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_MTXD register.
-//
-//*****************************************************************************
-#define MAC_MTXD_MDTX_M         0x0000FFFF  // MII Register Transmit Data.
-#define MAC_MTXD_MDTX_S         0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_MRXD register.
-//
-//*****************************************************************************
-#define MAC_MRXD_MDRX_M         0x0000FFFF  // MII Register Receive Data.
-#define MAC_MRXD_MDRX_S         0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_NP register.
-//
-//*****************************************************************************
-#define MAC_NP_NPR_M            0x0000003F  // Number of Packets in Receive
-                                            // FIFO.
-#define MAC_NP_NPR_S            0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_TR register.
-//
-//*****************************************************************************
-#define MAC_TR_NEWTX            0x00000001  // New Transmission.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_TS register.
-//
-//*****************************************************************************
-#define MAC_TS_TSEN             0x00000001  // Time Stamp Enable.
-
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the HIB_RTCC register.
 //
 //*****************************************************************************
-#define HIB_RTCC_M              0xFFFFFFFF  // RTC Counter.
+#define HIB_RTCC_M              0xFFFFFFFF  // RTC Counter
 #define HIB_RTCC_S              0
 
 //*****************************************************************************
@@ -3178,7 +3147,7 @@
 // The following are defines for the bit fields in the HIB_RTCM0 register.
 //
 //*****************************************************************************
-#define HIB_RTCM0_M             0xFFFFFFFF  // RTC Match 0.
+#define HIB_RTCM0_M             0xFFFFFFFF  // RTC Match 0
 #define HIB_RTCM0_S             0
 
 //*****************************************************************************
@@ -3186,7 +3155,7 @@
 // The following are defines for the bit fields in the HIB_RTCM1 register.
 //
 //*****************************************************************************
-#define HIB_RTCM1_M             0xFFFFFFFF  // RTC Match 1.
+#define HIB_RTCM1_M             0xFFFFFFFF  // RTC Match 1
 #define HIB_RTCM1_S             0
 
 //*****************************************************************************
@@ -3194,7 +3163,7 @@
 // The following are defines for the bit fields in the HIB_RTCLD register.
 //
 //*****************************************************************************
-#define HIB_RTCLD_M             0xFFFFFFFF  // RTC Load.
+#define HIB_RTCLD_M             0xFFFFFFFF  // RTC Load
 #define HIB_RTCLD_S             0
 
 //*****************************************************************************
@@ -3202,25 +3171,25 @@
 // The following are defines for the bit fields in the HIB_CTL register.
 //
 //*****************************************************************************
-#define HIB_CTL_VABORT          0x00000080  // Power Cut Abort Enable.
-#define HIB_CTL_CLK32EN         0x00000040  // Clocking Enable.
-#define HIB_CTL_LOWBATEN        0x00000020  // Low Battery Monitoring Enable.
-#define HIB_CTL_PINWEN          0x00000010  // External WAKE Pin Enable.
-#define HIB_CTL_RTCWEN          0x00000008  // RTC Wake-up Enable.
-#define HIB_CTL_CLKSEL          0x00000004  // Hibernation Module Clock Select.
-#define HIB_CTL_HIBREQ          0x00000002  // Hibernation Request.
-#define HIB_CTL_RTCEN           0x00000001  // RTC Timer Enable.
+#define HIB_CTL_VABORT          0x00000080  // Power Cut Abort Enable
+#define HIB_CTL_CLK32EN         0x00000040  // Clocking Enable
+#define HIB_CTL_LOWBATEN        0x00000020  // Low Battery Monitoring Enable
+#define HIB_CTL_PINWEN          0x00000010  // External WAKE Pin Enable
+#define HIB_CTL_RTCWEN          0x00000008  // RTC Wake-up Enable
+#define HIB_CTL_CLKSEL          0x00000004  // Hibernation Module Clock Select
+#define HIB_CTL_HIBREQ          0x00000002  // Hibernation Request
+#define HIB_CTL_RTCEN           0x00000001  // RTC Timer Enable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the HIB_IM register.
 //
 //*****************************************************************************
-#define HIB_IM_EXTW             0x00000008  // External Wake-Up Interrupt Mask.
+#define HIB_IM_EXTW             0x00000008  // External Wake-Up Interrupt Mask
 #define HIB_IM_LOWBAT           0x00000004  // Low Battery Voltage Interrupt
-                                            // Mask.
-#define HIB_IM_RTCALT1          0x00000002  // RTC Alert1 Interrupt Mask.
-#define HIB_IM_RTCALT0          0x00000001  // RTC Alert0 Interrupt Mask.
+                                            // Mask
+#define HIB_IM_RTCALT1          0x00000002  // RTC Alert 1 Interrupt Mask
+#define HIB_IM_RTCALT0          0x00000001  // RTC Alert 0 Interrupt Mask
 
 //*****************************************************************************
 //
@@ -3228,11 +3197,11 @@
 //
 //*****************************************************************************
 #define HIB_RIS_EXTW            0x00000008  // External Wake-Up Raw Interrupt
-                                            // Status.
+                                            // Status
 #define HIB_RIS_LOWBAT          0x00000004  // Low Battery Voltage Raw
-                                            // Interrupt Status.
-#define HIB_RIS_RTCALT1         0x00000002  // RTC Alert1 Raw Interrupt Status.
-#define HIB_RIS_RTCALT0         0x00000001  // RTC Alert0 Raw Interrupt Status.
+                                            // Interrupt Status
+#define HIB_RIS_RTCALT1         0x00000002  // RTC Alert 1 Raw Interrupt Status
+#define HIB_RIS_RTCALT0         0x00000001  // RTC Alert 0 Raw Interrupt Status
 
 //*****************************************************************************
 //
@@ -3240,13 +3209,13 @@
 //
 //*****************************************************************************
 #define HIB_MIS_EXTW            0x00000008  // External Wake-Up Masked
-                                            // Interrupt Status.
+                                            // Interrupt Status
 #define HIB_MIS_LOWBAT          0x00000004  // Low Battery Voltage Masked
-                                            // Interrupt Status.
-#define HIB_MIS_RTCALT1         0x00000002  // RTC Alert1 Masked Interrupt
-                                            // Status.
-#define HIB_MIS_RTCALT0         0x00000001  // RTC Alert0 Masked Interrupt
-                                            // Status.
+                                            // Interrupt Status
+#define HIB_MIS_RTCALT1         0x00000002  // RTC Alert 1 Masked Interrupt
+                                            // Status
+#define HIB_MIS_RTCALT0         0x00000001  // RTC Alert 0 Masked Interrupt
+                                            // Status
 
 //*****************************************************************************
 //
@@ -3254,20 +3223,20 @@
 //
 //*****************************************************************************
 #define HIB_IC_EXTW             0x00000008  // External Wake-Up Masked
-                                            // Interrupt Clear.
+                                            // Interrupt Clear
 #define HIB_IC_LOWBAT           0x00000004  // Low Battery Voltage Masked
-                                            // Interrupt Clear.
+                                            // Interrupt Clear
 #define HIB_IC_RTCALT1          0x00000002  // RTC Alert1 Masked Interrupt
-                                            // Clear.
+                                            // Clear
 #define HIB_IC_RTCALT0          0x00000001  // RTC Alert0 Masked Interrupt
-                                            // Clear.
+                                            // Clear
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the HIB_RTCT register.
 //
 //*****************************************************************************
-#define HIB_RTCT_TRIM_M         0x0000FFFF  // RTC Trim Value.
+#define HIB_RTCT_TRIM_M         0x0000FFFF  // RTC Trim Value
 #define HIB_RTCT_TRIM_S         0
 
 //*****************************************************************************
@@ -3275,8 +3244,7 @@
 // The following are defines for the bit fields in the HIB_DATA register.
 //
 //*****************************************************************************
-#define HIB_DATA_RTD_M          0xFFFFFFFF  // Hibernation Module NV
-                                            // Registers[63:0].
+#define HIB_DATA_RTD_M          0xFFFFFFFF  // Hibernation Module NV Data
 #define HIB_DATA_RTD_S          0
 
 //*****************************************************************************
@@ -3284,7 +3252,7 @@
 // The following are defines for the bit fields in the FLASH_FMA register.
 //
 //*****************************************************************************
-#define FLASH_FMA_OFFSET_M      0x0003FFFF  // Address Offset.
+#define FLASH_FMA_OFFSET_M      0x0003FFFF  // Address Offset
 #define FLASH_FMA_OFFSET_S      0
 
 //*****************************************************************************
@@ -3292,7 +3260,7 @@
 // The following are defines for the bit fields in the FLASH_FMD register.
 //
 //*****************************************************************************
-#define FLASH_FMD_DATA_M        0xFFFFFFFF  // Data Value.
+#define FLASH_FMD_DATA_M        0xFFFFFFFF  // Data Value
 #define FLASH_FMD_DATA_S        0
 
 //*****************************************************************************
@@ -3300,30 +3268,27 @@
 // The following are defines for the bit fields in the FLASH_FMC register.
 //
 //*****************************************************************************
-#define FLASH_FMC_WRKEY_M       0xFFFF0000  // Flash Write Key.
 #define FLASH_FMC_WRKEY         0xA4420000  // FLASH write key
-#define FLASH_FMC_COMT          0x00000008  // Commit Register Value.
-#define FLASH_FMC_MERASE        0x00000004  // Mass Erase Flash Memory.
-#define FLASH_FMC_ERASE         0x00000002  // Erase a Page of Flash Memory.
-#define FLASH_FMC_WRITE         0x00000001  // Write a Word into Flash Memory.
-#define FLASH_FMC_WRKEY_S       16
+#define FLASH_FMC_COMT          0x00000008  // Commit Register Value
+#define FLASH_FMC_MERASE        0x00000004  // Mass Erase Flash Memory
+#define FLASH_FMC_ERASE         0x00000002  // Erase a Page of Flash Memory
+#define FLASH_FMC_WRITE         0x00000001  // Write a Word into Flash Memory
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the FLASH_FCRIS register.
 //
 //*****************************************************************************
-#define FLASH_FCRIS_PRIS        0x00000002  // Programming Raw Interrupt
-                                            // Status.
-#define FLASH_FCRIS_ARIS        0x00000001  // Access Raw Interrupt Status.
+#define FLASH_FCRIS_PRIS        0x00000002  // Programming Raw Interrupt Status
+#define FLASH_FCRIS_ARIS        0x00000001  // Access Raw Interrupt Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the FLASH_FCIM register.
 //
 //*****************************************************************************
-#define FLASH_FCIM_PMASK        0x00000002  // Programming Interrupt Mask.
-#define FLASH_FCIM_AMASK        0x00000001  // Access Interrupt Mask.
+#define FLASH_FCIM_PMASK        0x00000002  // Programming Interrupt Mask
+#define FLASH_FCIM_AMASK        0x00000001  // Access Interrupt Mask
 
 //*****************************************************************************
 //
@@ -3331,16 +3296,16 @@
 //
 //*****************************************************************************
 #define FLASH_FCMISC_PMISC      0x00000002  // Programming Masked Interrupt
-                                            // Status and Clear.
+                                            // Status and Clear
 #define FLASH_FCMISC_AMISC      0x00000001  // Access Masked Interrupt Status
-                                            // and Clear.
+                                            // and Clear
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the FLASH_USECRL register.
 //
 //*****************************************************************************
-#define FLASH_USECRL_M          0x000000FF  // Microsecond Reload Value.
+#define FLASH_USECRL_M          0x000000FF  // Microsecond Reload Value
 #define FLASH_USECRL_S          0
 
 //*****************************************************************************
@@ -3348,10 +3313,10 @@
 // The following are defines for the bit fields in the FLASH_USERDBG register.
 //
 //*****************************************************************************
-#define FLASH_USERDBG_NW        0x80000000  // User Debug Not Written.
-#define FLASH_USERDBG_DATA_M    0x7FFFFFFC  // User Data.
-#define FLASH_USERDBG_DBG1      0x00000002  // Debug Control 1.
-#define FLASH_USERDBG_DBG0      0x00000001  // Debug Control 0.
+#define FLASH_USERDBG_NW        0x80000000  // User Debug Not Written
+#define FLASH_USERDBG_DATA_M    0x7FFFFFFC  // User Data
+#define FLASH_USERDBG_DBG1      0x00000002  // Debug Control 1
+#define FLASH_USERDBG_DBG0      0x00000001  // Debug Control 0
 #define FLASH_USERDBG_DATA_S    2
 
 //*****************************************************************************
@@ -3359,8 +3324,8 @@
 // The following are defines for the bit fields in the FLASH_USERREG0 register.
 //
 //*****************************************************************************
-#define FLASH_USERREG0_NW       0x80000000  // Not Written.
-#define FLASH_USERREG0_DATA_M   0x7FFFFFFF  // User Data.
+#define FLASH_USERREG0_NW       0x80000000  // Not Written
+#define FLASH_USERREG0_DATA_M   0x7FFFFFFF  // User Data
 #define FLASH_USERREG0_DATA_S   0
 
 //*****************************************************************************
@@ -3368,8 +3333,8 @@
 // The following are defines for the bit fields in the FLASH_USERREG1 register.
 //
 //*****************************************************************************
-#define FLASH_USERREG1_NW       0x80000000  // Not Written.
-#define FLASH_USERREG1_DATA_M   0x7FFFFFFF  // User Data.
+#define FLASH_USERREG1_NW       0x80000000  // Not Written
+#define FLASH_USERREG1_DATA_M   0x7FFFFFFF  // User Data
 #define FLASH_USERREG1_DATA_S   0
 
 //*****************************************************************************
@@ -3387,54 +3352,54 @@
 // The following are defines for the bit fields in the SYSCTL_DID0 register.
 //
 //*****************************************************************************
-#define SYSCTL_DID0_VER_M       0x70000000  // DID0 Version.
+#define SYSCTL_DID0_VER_M       0x70000000  // DID0 Version
 #define SYSCTL_DID0_VER_1       0x10000000  // Second version of the DID0
-                                            // register format.
-#define SYSCTL_DID0_CLASS_M     0x00FF0000  // Device Class.
-#define SYSCTL_DID0_CLASS_FURY  0x00010000  // Stellaris(r) Fury-class devices.
-#define SYSCTL_DID0_MAJ_M       0x0000FF00  // Major Revision.
+                                            // register format
+#define SYSCTL_DID0_CLASS_M     0x00FF0000  // Device Class
+#define SYSCTL_DID0_CLASS_FURY  0x00010000  // Stellaris(R) Fury-class devices
+#define SYSCTL_DID0_MAJ_M       0x0000FF00  // Major Revision
 #define SYSCTL_DID0_MAJ_REVA    0x00000000  // Revision A (initial device)
 #define SYSCTL_DID0_MAJ_REVB    0x00000100  // Revision B (first base layer
                                             // revision)
 #define SYSCTL_DID0_MAJ_REVC    0x00000200  // Revision C (second base layer
                                             // revision)
-#define SYSCTL_DID0_MIN_M       0x000000FF  // Minor Revision.
+#define SYSCTL_DID0_MIN_M       0x000000FF  // Minor Revision
 #define SYSCTL_DID0_MIN_0       0x00000000  // Initial device, or a major
-                                            // revision update.
-#define SYSCTL_DID0_MIN_1       0x00000001  // First metal layer change.
-#define SYSCTL_DID0_MIN_2       0x00000002  // Second metal layer change.
+                                            // revision update
+#define SYSCTL_DID0_MIN_1       0x00000001  // First metal layer change
+#define SYSCTL_DID0_MIN_2       0x00000002  // Second metal layer change
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_DID1 register.
 //
 //*****************************************************************************
-#define SYSCTL_DID1_VER_M       0xF0000000  // DID1 Version.
+#define SYSCTL_DID1_VER_M       0xF0000000  // DID1 Version
 #define SYSCTL_DID1_VER_1       0x10000000  // Second version of the DID1
-                                            // register format.
-#define SYSCTL_DID1_FAM_M       0x0F000000  // Family.
+                                            // register format
+#define SYSCTL_DID1_FAM_M       0x0F000000  // Family
 #define SYSCTL_DID1_FAM_STELLARIS \
                                 0x00000000  // Stellaris family of
                                             // microcontollers, that is, all
                                             // devices with external part
-                                            // numbers starting with LM3S.
-#define SYSCTL_DID1_PRTNO_M     0x00FF0000  // Part Number.
+                                            // numbers starting with LM3S
+#define SYSCTL_DID1_PRTNO_M     0x00FF0000  // Part Number
 #define SYSCTL_DID1_PRTNO_8962  0x00A60000  // LM3S8962
-#define SYSCTL_DID1_PINCNT_M    0x0000E000  // Package Pin Count.
-#define SYSCTL_DID1_PINCNT_100  0x00004000  // 100-pin or 108-ball package
-#define SYSCTL_DID1_TEMP_M      0x000000E0  // Temperature Range.
+#define SYSCTL_DID1_PINCNT_M    0x0000E000  // Package Pin Count
+#define SYSCTL_DID1_PINCNT_100  0x00004000  // 100-pin package
+#define SYSCTL_DID1_TEMP_M      0x000000E0  // Temperature Range
 #define SYSCTL_DID1_TEMP_C      0x00000000  // Commercial temperature range (0C
                                             // to 70C)
 #define SYSCTL_DID1_TEMP_I      0x00000020  // Industrial temperature range
                                             // (-40C to 85C)
 #define SYSCTL_DID1_TEMP_E      0x00000040  // Extended temperature range (-40C
                                             // to 105C)
-#define SYSCTL_DID1_PKG_M       0x00000018  // Package Type.
-#define SYSCTL_DID1_PKG_28SOIC  0x00000000  // SOIC package
-#define SYSCTL_DID1_PKG_48QFP   0x00000008  // LQFP package
+#define SYSCTL_DID1_PKG_M       0x00000018  // Package Type
+#define SYSCTL_DID1_PKG_SOIC    0x00000000  // SOIC package
+#define SYSCTL_DID1_PKG_QFP     0x00000008  // LQFP package
 #define SYSCTL_DID1_PKG_BGA     0x00000010  // BGA package
-#define SYSCTL_DID1_ROHS        0x00000004  // RoHS-Compliance.
-#define SYSCTL_DID1_QUAL_M      0x00000003  // Qualification Status.
+#define SYSCTL_DID1_ROHS        0x00000004  // RoHS-Compliance
+#define SYSCTL_DID1_QUAL_M      0x00000003  // Qualification Status
 #define SYSCTL_DID1_QUAL_ES     0x00000000  // Engineering Sample (unqualified)
 #define SYSCTL_DID1_QUAL_PP     0x00000001  // Pilot Production (unqualified)
 #define SYSCTL_DID1_QUAL_FQ     0x00000002  // Fully Qualified
@@ -3444,9 +3409,9 @@
 // The following are defines for the bit fields in the SYSCTL_DC0 register.
 //
 //*****************************************************************************
-#define SYSCTL_DC0_SRAMSZ_M     0xFFFF0000  // SRAM Size.
+#define SYSCTL_DC0_SRAMSZ_M     0xFFFF0000  // SRAM Size
 #define SYSCTL_DC0_SRAMSZ_64KB  0x00FF0000  // 64 KB of SRAM
-#define SYSCTL_DC0_FLASHSZ_M    0x0000FFFF  // Flash Size.
+#define SYSCTL_DC0_FLASHSZ_M    0x0000FFFF  // Flash Size
 #define SYSCTL_DC0_FLASHSZ_256K 0x0000007F  // 256 KB of Flash
 #define SYSCTL_DC0_SRAMSZ_S     16          // SRAM size shift
 #define SYSCTL_DC0_FLASHSZ_S    0           // Flash size shift
@@ -3456,92 +3421,92 @@
 // The following are defines for the bit fields in the SYSCTL_DC1 register.
 //
 //*****************************************************************************
-#define SYSCTL_DC1_CAN0         0x01000000  // CAN Module 0 Present.
-#define SYSCTL_DC1_PWM          0x00100000  // PWM Module Present.
-#define SYSCTL_DC1_ADC          0x00010000  // ADC Module Present.
-#define SYSCTL_DC1_MINSYSDIV_M  0x0000F000  // System Clock Divider.
+#define SYSCTL_DC1_CAN0         0x01000000  // CAN Module 0 Present
+#define SYSCTL_DC1_PWM          0x00100000  // PWM Module Present
+#define SYSCTL_DC1_ADC          0x00010000  // ADC Module Present
+#define SYSCTL_DC1_MINSYSDIV_M  0x0000F000  // System Clock Divider
 #define SYSCTL_DC1_MINSYSDIV_50 0x00003000  // Specifies a 50-MHz CPU clock
-                                            // with a PLL divider of 4.
-#define SYSCTL_DC1_ADCSPD_M     0x00000300  // Max ADC Speed.
+                                            // with a PLL divider of 4
+#define SYSCTL_DC1_ADCSPD_M     0x00000300  // Max ADC Speed
 #define SYSCTL_DC1_ADCSPD_500K  0x00000200  // 500K samples/second
-#define SYSCTL_DC1_MPU          0x00000080  // MPU Present.
-#define SYSCTL_DC1_HIB          0x00000040  // Hibernation Module Present.
-#define SYSCTL_DC1_TEMP         0x00000020  // Temp Sensor Present.
-#define SYSCTL_DC1_PLL          0x00000010  // PLL Present.
-#define SYSCTL_DC1_WDT          0x00000008  // Watchdog Timer Present.
-#define SYSCTL_DC1_SWO          0x00000004  // SWO Trace Port Present.
-#define SYSCTL_DC1_SWD          0x00000002  // SWD Present.
-#define SYSCTL_DC1_JTAG         0x00000001  // JTAG Present.
+#define SYSCTL_DC1_MPU          0x00000080  // MPU Present
+#define SYSCTL_DC1_HIB          0x00000040  // Hibernation Module Present
+#define SYSCTL_DC1_TEMP         0x00000020  // Temp Sensor Present
+#define SYSCTL_DC1_PLL          0x00000010  // PLL Present
+#define SYSCTL_DC1_WDT0         0x00000008  // Watchdog Timer 0 Present
+#define SYSCTL_DC1_SWO          0x00000004  // SWO Trace Port Present
+#define SYSCTL_DC1_SWD          0x00000002  // SWD Present
+#define SYSCTL_DC1_JTAG         0x00000001  // JTAG Present
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_DC2 register.
 //
 //*****************************************************************************
-#define SYSCTL_DC2_COMP0        0x01000000  // Analog Comparator 0 Present.
-#define SYSCTL_DC2_TIMER3       0x00080000  // Timer 3 Present.
-#define SYSCTL_DC2_TIMER2       0x00040000  // Timer 2 Present.
-#define SYSCTL_DC2_TIMER1       0x00020000  // Timer 1 Present.
-#define SYSCTL_DC2_TIMER0       0x00010000  // Timer 0 Present.
-#define SYSCTL_DC2_I2C0         0x00001000  // I2C Module 0 Present.
-#define SYSCTL_DC2_QEI1         0x00000200  // QEI1 Present.
-#define SYSCTL_DC2_QEI0         0x00000100  // QEI0 Present.
-#define SYSCTL_DC2_SSI0         0x00000010  // SSI0 Present.
-#define SYSCTL_DC2_UART1        0x00000002  // UART1 Present.
-#define SYSCTL_DC2_UART0        0x00000001  // UART0 Present.
+#define SYSCTL_DC2_COMP0        0x01000000  // Analog Comparator 0 Present
+#define SYSCTL_DC2_TIMER3       0x00080000  // Timer Module 3 Present
+#define SYSCTL_DC2_TIMER2       0x00040000  // Timer Module 2 Present
+#define SYSCTL_DC2_TIMER1       0x00020000  // Timer Module 1 Present
+#define SYSCTL_DC2_TIMER0       0x00010000  // Timer Module 0 Present
+#define SYSCTL_DC2_I2C0         0x00001000  // I2C Module 0 Present
+#define SYSCTL_DC2_QEI1         0x00000200  // QEI Module 1 Present
+#define SYSCTL_DC2_QEI0         0x00000100  // QEI Module 0 Present
+#define SYSCTL_DC2_SSI0         0x00000010  // SSI Module 0 Present
+#define SYSCTL_DC2_UART1        0x00000002  // UART Module 1 Present
+#define SYSCTL_DC2_UART0        0x00000001  // UART Module 0 Present
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_DC3 register.
 //
 //*****************************************************************************
-#define SYSCTL_DC3_32KHZ        0x80000000  // 32KHz Input Clock Available.
-#define SYSCTL_DC3_CCP1         0x02000000  // CCP1 Pin Present.
-#define SYSCTL_DC3_CCP0         0x01000000  // CCP0 Pin Present.
-#define SYSCTL_DC3_ADC3         0x00080000  // ADC3 Pin Present.
-#define SYSCTL_DC3_ADC2         0x00040000  // ADC2 Pin Present.
-#define SYSCTL_DC3_ADC1         0x00020000  // ADC1 Pin Present.
-#define SYSCTL_DC3_ADC0         0x00010000  // ADC0 Pin Present.
-#define SYSCTL_DC3_PWMFAULT     0x00008000  // PWM Fault Pin Present.
-#define SYSCTL_DC3_C0O          0x00000100  // C0o Pin Present.
-#define SYSCTL_DC3_C0PLUS       0x00000080  // C0+ Pin Present.
-#define SYSCTL_DC3_C0MINUS      0x00000040  // C0- Pin Present.
-#define SYSCTL_DC3_PWM5         0x00000020  // PWM5 Pin Present.
-#define SYSCTL_DC3_PWM4         0x00000010  // PWM4 Pin Present.
-#define SYSCTL_DC3_PWM3         0x00000008  // PWM3 Pin Present.
-#define SYSCTL_DC3_PWM2         0x00000004  // PWM2 Pin Present.
-#define SYSCTL_DC3_PWM1         0x00000002  // PWM1 Pin Present.
-#define SYSCTL_DC3_PWM0         0x00000001  // PWM0 Pin Present.
+#define SYSCTL_DC3_32KHZ        0x80000000  // 32KHz Input Clock Available
+#define SYSCTL_DC3_CCP1         0x02000000  // CCP1 Pin Present
+#define SYSCTL_DC3_CCP0         0x01000000  // CCP0 Pin Present
+#define SYSCTL_DC3_ADC3         0x00080000  // ADC3 Pin Present
+#define SYSCTL_DC3_ADC2         0x00040000  // ADC2 Pin Present
+#define SYSCTL_DC3_ADC1         0x00020000  // ADC1 Pin Present
+#define SYSCTL_DC3_ADC0         0x00010000  // ADC0 Pin Present
+#define SYSCTL_DC3_PWMFAULT     0x00008000  // PWM Fault Pin Present
+#define SYSCTL_DC3_C0O          0x00000100  // C0o Pin Present
+#define SYSCTL_DC3_C0PLUS       0x00000080  // C0+ Pin Present
+#define SYSCTL_DC3_C0MINUS      0x00000040  // C0- Pin Present
+#define SYSCTL_DC3_PWM5         0x00000020  // PWM5 Pin Present
+#define SYSCTL_DC3_PWM4         0x00000010  // PWM4 Pin Present
+#define SYSCTL_DC3_PWM3         0x00000008  // PWM3 Pin Present
+#define SYSCTL_DC3_PWM2         0x00000004  // PWM2 Pin Present
+#define SYSCTL_DC3_PWM1         0x00000002  // PWM1 Pin Present
+#define SYSCTL_DC3_PWM0         0x00000001  // PWM0 Pin Present
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_DC4 register.
 //
 //*****************************************************************************
-#define SYSCTL_DC4_EPHY0        0x40000000  // Ethernet PHY0 Present.
-#define SYSCTL_DC4_EMAC0        0x10000000  // Ethernet MAC0 Present.
-#define SYSCTL_DC4_E1588        0x01000000  // 1588 Capable.
-#define SYSCTL_DC4_GPIOG        0x00000040  // GPIO Port G Present.
-#define SYSCTL_DC4_GPIOF        0x00000020  // GPIO Port F Present.
-#define SYSCTL_DC4_GPIOE        0x00000010  // GPIO Port E Present.
-#define SYSCTL_DC4_GPIOD        0x00000008  // GPIO Port D Present.
-#define SYSCTL_DC4_GPIOC        0x00000004  // GPIO Port C Present.
-#define SYSCTL_DC4_GPIOB        0x00000002  // GPIO Port B Present.
-#define SYSCTL_DC4_GPIOA        0x00000001  // GPIO Port A Present.
+#define SYSCTL_DC4_EPHY0        0x40000000  // Ethernet PHY Layer 0 Present
+#define SYSCTL_DC4_EMAC0        0x10000000  // Ethernet MAC Layer 0 Present
+#define SYSCTL_DC4_E1588        0x01000000  // 1588 Capable
+#define SYSCTL_DC4_GPIOG        0x00000040  // GPIO Port G Present
+#define SYSCTL_DC4_GPIOF        0x00000020  // GPIO Port F Present
+#define SYSCTL_DC4_GPIOE        0x00000010  // GPIO Port E Present
+#define SYSCTL_DC4_GPIOD        0x00000008  // GPIO Port D Present
+#define SYSCTL_DC4_GPIOC        0x00000004  // GPIO Port C Present
+#define SYSCTL_DC4_GPIOB        0x00000002  // GPIO Port B Present
+#define SYSCTL_DC4_GPIOA        0x00000001  // GPIO Port A Present
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_PBORCTL register.
 //
 //*****************************************************************************
-#define SYSCTL_PBORCTL_BORIOR   0x00000002  // BOR Interrupt or Reset.
+#define SYSCTL_PBORCTL_BORIOR   0x00000002  // BOR Interrupt or Reset
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_LDOPCTL register.
 //
 //*****************************************************************************
-#define SYSCTL_LDOPCTL_M        0x0000003F  // LDO Output Voltage.
+#define SYSCTL_LDOPCTL_M        0x0000003F  // LDO Output Voltage
 #define SYSCTL_LDOPCTL_2_50V    0x00000000  // 2.50
 #define SYSCTL_LDOPCTL_2_45V    0x00000001  // 2.45
 #define SYSCTL_LDOPCTL_2_40V    0x00000002  // 2.40
@@ -3559,120 +3524,118 @@
 // The following are defines for the bit fields in the SYSCTL_SRCR0 register.
 //
 //*****************************************************************************
-#define SYSCTL_SRCR0_CAN0       0x01000000  // CAN0 Reset Control.
-#define SYSCTL_SRCR0_PWM        0x00100000  // PWM Reset Control.
-#define SYSCTL_SRCR0_ADC        0x00010000  // ADC0 Reset Control.
-#define SYSCTL_SRCR0_HIB        0x00000040  // HIB Reset Control.
-#define SYSCTL_SRCR0_WDT        0x00000008  // WDT Reset Control.
+#define SYSCTL_SRCR0_CAN0       0x01000000  // CAN0 Reset Control
+#define SYSCTL_SRCR0_PWM        0x00100000  // PWM Reset Control
+#define SYSCTL_SRCR0_ADC        0x00010000  // ADC0 Reset Control
+#define SYSCTL_SRCR0_HIB        0x00000040  // HIB Reset Control
+#define SYSCTL_SRCR0_WDT        0x00000008  // WDT Reset Control
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_SRCR1 register.
 //
 //*****************************************************************************
-#define SYSCTL_SRCR1_COMP0      0x01000000  // Analog Comp 0 Reset Control.
-#define SYSCTL_SRCR1_TIMER3     0x00080000  // Timer 3 Reset Control.
-#define SYSCTL_SRCR1_TIMER2     0x00040000  // Timer 2 Reset Control.
-#define SYSCTL_SRCR1_TIMER1     0x00020000  // Timer 1 Reset Control.
-#define SYSCTL_SRCR1_TIMER0     0x00010000  // Timer 0 Reset Control.
-#define SYSCTL_SRCR1_I2C0       0x00001000  // I2C0 Reset Control.
-#define SYSCTL_SRCR1_QEI1       0x00000200  // QEI1 Reset Control.
-#define SYSCTL_SRCR1_QEI0       0x00000100  // QEI0 Reset Control.
-#define SYSCTL_SRCR1_SSI0       0x00000010  // SSI0 Reset Control.
-#define SYSCTL_SRCR1_UART1      0x00000002  // UART1 Reset Control.
-#define SYSCTL_SRCR1_UART0      0x00000001  // UART0 Reset Control.
+#define SYSCTL_SRCR1_COMP0      0x01000000  // Analog Comp 0 Reset Control
+#define SYSCTL_SRCR1_TIMER3     0x00080000  // Timer 3 Reset Control
+#define SYSCTL_SRCR1_TIMER2     0x00040000  // Timer 2 Reset Control
+#define SYSCTL_SRCR1_TIMER1     0x00020000  // Timer 1 Reset Control
+#define SYSCTL_SRCR1_TIMER0     0x00010000  // Timer 0 Reset Control
+#define SYSCTL_SRCR1_I2C0       0x00001000  // I2C0 Reset Control
+#define SYSCTL_SRCR1_QEI1       0x00000200  // QEI1 Reset Control
+#define SYSCTL_SRCR1_QEI0       0x00000100  // QEI0 Reset Control
+#define SYSCTL_SRCR1_SSI0       0x00000010  // SSI0 Reset Control
+#define SYSCTL_SRCR1_UART1      0x00000002  // UART1 Reset Control
+#define SYSCTL_SRCR1_UART0      0x00000001  // UART0 Reset Control
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_SRCR2 register.
 //
 //*****************************************************************************
-#define SYSCTL_SRCR2_EPHY0      0x40000000  // PHY0 Reset Control.
-#define SYSCTL_SRCR2_EMAC0      0x10000000  // MAC0 Reset Control.
-#define SYSCTL_SRCR2_GPIOG      0x00000040  // Port G Reset Control.
-#define SYSCTL_SRCR2_GPIOF      0x00000020  // Port F Reset Control.
-#define SYSCTL_SRCR2_GPIOE      0x00000010  // Port E Reset Control.
-#define SYSCTL_SRCR2_GPIOD      0x00000008  // Port D Reset Control.
-#define SYSCTL_SRCR2_GPIOC      0x00000004  // Port C Reset Control.
-#define SYSCTL_SRCR2_GPIOB      0x00000002  // Port B Reset Control.
-#define SYSCTL_SRCR2_GPIOA      0x00000001  // Port A Reset Control.
+#define SYSCTL_SRCR2_EPHY0      0x40000000  // PHY0 Reset Control
+#define SYSCTL_SRCR2_EMAC0      0x10000000  // MAC0 Reset Control
+#define SYSCTL_SRCR2_GPIOG      0x00000040  // Port G Reset Control
+#define SYSCTL_SRCR2_GPIOF      0x00000020  // Port F Reset Control
+#define SYSCTL_SRCR2_GPIOE      0x00000010  // Port E Reset Control
+#define SYSCTL_SRCR2_GPIOD      0x00000008  // Port D Reset Control
+#define SYSCTL_SRCR2_GPIOC      0x00000004  // Port C Reset Control
+#define SYSCTL_SRCR2_GPIOB      0x00000002  // Port B Reset Control
+#define SYSCTL_SRCR2_GPIOA      0x00000001  // Port A Reset Control
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_RIS register.
 //
 //*****************************************************************************
-#define SYSCTL_RIS_PLLLRIS      0x00000040  // PLL Lock Raw Interrupt Status.
+#define SYSCTL_RIS_PLLLRIS      0x00000040  // PLL Lock Raw Interrupt Status
 #define SYSCTL_RIS_BORRIS       0x00000002  // Brown-Out Reset Raw Interrupt
-                                            // Status.
+                                            // Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_IMC register.
 //
 //*****************************************************************************
-#define SYSCTL_IMC_PLLLIM       0x00000040  // PLL Lock Interrupt Mask.
-#define SYSCTL_IMC_BORIM        0x00000002  // Brown-Out Reset Interrupt Mask.
+#define SYSCTL_IMC_PLLLIM       0x00000040  // PLL Lock Interrupt Mask
+#define SYSCTL_IMC_BORIM        0x00000002  // Brown-Out Reset Interrupt Mask
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_MISC register.
 //
 //*****************************************************************************
-#define SYSCTL_MISC_PLLLMIS     0x00000040  // PLL Lock Masked Interrupt
-                                            // Status.
-#define SYSCTL_MISC_BORMIS      0x00000002  // BOR Masked Interrupt Status.
+#define SYSCTL_MISC_PLLLMIS     0x00000040  // PLL Lock Masked Interrupt Status
+#define SYSCTL_MISC_BORMIS      0x00000002  // BOR Masked Interrupt Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_RESC register.
 //
 //*****************************************************************************
-#define SYSCTL_RESC_LDO         0x00000020  // LDO Reset.
-#define SYSCTL_RESC_SW          0x00000010  // Software Reset.
-#define SYSCTL_RESC_WDT         0x00000008  // Watchdog Timer Reset.
-#define SYSCTL_RESC_BOR         0x00000004  // Brown-Out Reset.
-#define SYSCTL_RESC_POR         0x00000002  // Power-On Reset.
-#define SYSCTL_RESC_EXT         0x00000001  // External Reset.
+#define SYSCTL_RESC_SW          0x00000010  // Software Reset
+#define SYSCTL_RESC_WDT         0x00000008  // Watchdog Timer Reset
+#define SYSCTL_RESC_BOR         0x00000004  // Brown-Out Reset
+#define SYSCTL_RESC_POR         0x00000002  // Power-On Reset
+#define SYSCTL_RESC_EXT         0x00000001  // External Reset
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_RCC register.
 //
 //*****************************************************************************
-#define SYSCTL_RCC_ACG          0x08000000  // Auto Clock Gating.
-#define SYSCTL_RCC_SYSDIV_M     0x07800000  // System Clock Divisor.
-#define SYSCTL_RCC_SYSDIV_2     0x00800000  // /2
-#define SYSCTL_RCC_SYSDIV_3     0x01000000  // /3
-#define SYSCTL_RCC_SYSDIV_4     0x01800000  // /4
-#define SYSCTL_RCC_SYSDIV_5     0x02000000  // /5
-#define SYSCTL_RCC_SYSDIV_6     0x02800000  // /6
-#define SYSCTL_RCC_SYSDIV_7     0x03000000  // /7
-#define SYSCTL_RCC_SYSDIV_8     0x03800000  // /8
-#define SYSCTL_RCC_SYSDIV_9     0x04000000  // /9
-#define SYSCTL_RCC_SYSDIV_10    0x04800000  // /10
-#define SYSCTL_RCC_SYSDIV_11    0x05000000  // /11
-#define SYSCTL_RCC_SYSDIV_12    0x05800000  // /12
-#define SYSCTL_RCC_SYSDIV_13    0x06000000  // /13
-#define SYSCTL_RCC_SYSDIV_14    0x06800000  // /14
-#define SYSCTL_RCC_SYSDIV_15    0x07000000  // /15
-#define SYSCTL_RCC_SYSDIV_16    0x07800000  // /16
-#define SYSCTL_RCC_USESYSDIV    0x00400000  // Enable System Clock Divider.
-#define SYSCTL_RCC_USEPWMDIV    0x00100000  // Enable PWM Clock Divisor.
-#define SYSCTL_RCC_PWMDIV_M     0x000E0000  // PWM Unit Clock Divisor.
-#define SYSCTL_RCC_PWMDIV_2     0x00000000  // /2
-#define SYSCTL_RCC_PWMDIV_4     0x00020000  // /4
-#define SYSCTL_RCC_PWMDIV_8     0x00040000  // /8
-#define SYSCTL_RCC_PWMDIV_16    0x00060000  // /16
-#define SYSCTL_RCC_PWMDIV_32    0x00080000  // /32
-#define SYSCTL_RCC_PWMDIV_64    0x000A0000  // /64
-#define SYSCTL_RCC_PWRDN        0x00002000  // PLL Power Down.
-#define SYSCTL_RCC_BYPASS       0x00000800  // PLL Bypass.
-#define SYSCTL_RCC_XTAL_M       0x000003C0  // Crystal Value.
-#define SYSCTL_RCC_XTAL_1MHZ    0x00000000  // 1.000
-#define SYSCTL_RCC_XTAL_1_84MHZ 0x00000040  // 1.8432
-#define SYSCTL_RCC_XTAL_2MHZ    0x00000080  // 2.000
-#define SYSCTL_RCC_XTAL_2_45MHZ 0x000000C0  // 2.4576
+#define SYSCTL_RCC_ACG          0x08000000  // Auto Clock Gating
+#define SYSCTL_RCC_SYSDIV_M     0x07800000  // System Clock Divisor
+#define SYSCTL_RCC_SYSDIV_2     0x00800000  // System clock /2
+#define SYSCTL_RCC_SYSDIV_3     0x01000000  // System clock /3
+#define SYSCTL_RCC_SYSDIV_4     0x01800000  // System clock /4
+#define SYSCTL_RCC_SYSDIV_5     0x02000000  // System clock /5
+#define SYSCTL_RCC_SYSDIV_6     0x02800000  // System clock /6
+#define SYSCTL_RCC_SYSDIV_7     0x03000000  // System clock /7
+#define SYSCTL_RCC_SYSDIV_8     0x03800000  // System clock /8
+#define SYSCTL_RCC_SYSDIV_9     0x04000000  // System clock /9
+#define SYSCTL_RCC_SYSDIV_10    0x04800000  // System clock /10
+#define SYSCTL_RCC_SYSDIV_11    0x05000000  // System clock /11
+#define SYSCTL_RCC_SYSDIV_12    0x05800000  // System clock /12
+#define SYSCTL_RCC_SYSDIV_13    0x06000000  // System clock /13
+#define SYSCTL_RCC_SYSDIV_14    0x06800000  // System clock /14
+#define SYSCTL_RCC_SYSDIV_15    0x07000000  // System clock /15
+#define SYSCTL_RCC_SYSDIV_16    0x07800000  // System clock /16
+#define SYSCTL_RCC_USESYSDIV    0x00400000  // Enable System Clock Divider
+#define SYSCTL_RCC_USEPWMDIV    0x00100000  // Enable PWM Clock Divisor
+#define SYSCTL_RCC_PWMDIV_M     0x000E0000  // PWM Unit Clock Divisor
+#define SYSCTL_RCC_PWMDIV_2     0x00000000  // PWM clock /2
+#define SYSCTL_RCC_PWMDIV_4     0x00020000  // PWM clock /4
+#define SYSCTL_RCC_PWMDIV_8     0x00040000  // PWM clock /8
+#define SYSCTL_RCC_PWMDIV_16    0x00060000  // PWM clock /16
+#define SYSCTL_RCC_PWMDIV_32    0x00080000  // PWM clock /32
+#define SYSCTL_RCC_PWMDIV_64    0x000A0000  // PWM clock /64
+#define SYSCTL_RCC_PWRDN        0x00002000  // PLL Power Down
+#define SYSCTL_RCC_BYPASS       0x00000800  // PLL Bypass
+#define SYSCTL_RCC_XTAL_M       0x000003C0  // Crystal Value
+#define SYSCTL_RCC_XTAL_1MHZ    0x00000000  // 1 MHz
+#define SYSCTL_RCC_XTAL_1_84MHZ 0x00000040  // 1.8432 MHz
+#define SYSCTL_RCC_XTAL_2MHZ    0x00000080  // 2 MHz
+#define SYSCTL_RCC_XTAL_2_45MHZ 0x000000C0  // 2.4576 MHz
 #define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100  // 3.579545 MHz
 #define SYSCTL_RCC_XTAL_3_68MHZ 0x00000140  // 3.6864 MHz
 #define SYSCTL_RCC_XTAL_4MHZ    0x00000180  // 4 MHz
@@ -3680,26 +3643,27 @@
 #define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200  // 4.9152 MHz
 #define SYSCTL_RCC_XTAL_5MHZ    0x00000240  // 5 MHz
 #define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280  // 5.12 MHz
-#define SYSCTL_RCC_XTAL_6MHZ    0x000002C0  // 6 MHz (reset value)
+#define SYSCTL_RCC_XTAL_6MHZ    0x000002C0  // 6 MHz
 #define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300  // 6.144 MHz
 #define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340  // 7.3728 MHz
 #define SYSCTL_RCC_XTAL_8MHZ    0x00000380  // 8 MHz
 #define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0  // 8.192 MHz
-#define SYSCTL_RCC_OSCSRC_M     0x00000030  // Oscillator Source.
+#define SYSCTL_RCC_OSCSRC_M     0x00000030  // Oscillator Source
 #define SYSCTL_RCC_OSCSRC_MAIN  0x00000000  // MOSC
 #define SYSCTL_RCC_OSCSRC_INT   0x00000010  // IOSC
 #define SYSCTL_RCC_OSCSRC_INT4  0x00000020  // IOSC/4
 #define SYSCTL_RCC_OSCSRC_30    0x00000030  // 30 kHz
-#define SYSCTL_RCC_IOSCDIS      0x00000002  // Internal Oscillator Disable.
-#define SYSCTL_RCC_MOSCDIS      0x00000001  // Main Oscillator Disable.
+#define SYSCTL_RCC_IOSCDIS      0x00000002  // Internal Oscillator Disable
+#define SYSCTL_RCC_MOSCDIS      0x00000001  // Main Oscillator Disable
+#define SYSCTL_RCC_SYSDIV_S     23
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_PLLCFG register.
 //
 //*****************************************************************************
-#define SYSCTL_PLLCFG_F_M       0x00003FE0  // PLL F Value.
-#define SYSCTL_PLLCFG_R_M       0x0000001F  // PLL R Value.
+#define SYSCTL_PLLCFG_F_M       0x00003FE0  // PLL F Value
+#define SYSCTL_PLLCFG_R_M       0x0000001F  // PLL R Value
 #define SYSCTL_PLLCFG_F_S       5
 #define SYSCTL_PLLCFG_R_S       0
 
@@ -3708,8 +3672,8 @@
 // The following are defines for the bit fields in the SYSCTL_RCC2 register.
 //
 //*****************************************************************************
-#define SYSCTL_RCC2_USERCC2     0x80000000  // Use RCC2.
-#define SYSCTL_RCC2_SYSDIV2_M   0x1F800000  // System Clock Divisor.
+#define SYSCTL_RCC2_USERCC2     0x80000000  // Use RCC2
+#define SYSCTL_RCC2_SYSDIV2_M   0x1F800000  // System Clock Divisor 2
 #define SYSCTL_RCC2_SYSDIV2_2   0x00800000  // System clock /2
 #define SYSCTL_RCC2_SYSDIV2_3   0x01000000  // System clock /3
 #define SYSCTL_RCC2_SYSDIV2_4   0x01800000  // System clock /4
@@ -3773,14 +3737,14 @@
 #define SYSCTL_RCC2_SYSDIV2_62  0x1E800000  // System clock /62
 #define SYSCTL_RCC2_SYSDIV2_63  0x1F000000  // System clock /63
 #define SYSCTL_RCC2_SYSDIV2_64  0x1F800000  // System clock /64
-#define SYSCTL_RCC2_PWRDN2      0x00002000  // Power-Down PLL.
-#define SYSCTL_RCC2_BYPASS2     0x00000800  // Bypass PLL.
-#define SYSCTL_RCC2_OSCSRC2_M   0x00000070  // Oscillator Source.
+#define SYSCTL_RCC2_PWRDN2      0x00002000  // Power-Down PLL 2
+#define SYSCTL_RCC2_BYPASS2     0x00000800  // PLL Bypass 2
+#define SYSCTL_RCC2_OSCSRC2_M   0x00000070  // Oscillator Source 2
 #define SYSCTL_RCC2_OSCSRC2_MO  0x00000000  // MOSC
-#define SYSCTL_RCC2_OSCSRC2_IO  0x00000010  // IOSC
-#define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020  // IOSC/4
+#define SYSCTL_RCC2_OSCSRC2_IO  0x00000010  // PIOSC
+#define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020  // PIOSC/4
 #define SYSCTL_RCC2_OSCSRC2_30  0x00000030  // 30 kHz
-#define SYSCTL_RCC2_OSCSRC2_32  0x00000070  // 32 kHz
+#define SYSCTL_RCC2_OSCSRC2_32  0x00000070  // 32.768 kHz
 #define SYSCTL_RCC2_SYSDIV2_S   23
 
 //*****************************************************************************
@@ -3788,144 +3752,137 @@
 // The following are defines for the bit fields in the SYSCTL_RCGC0 register.
 //
 //*****************************************************************************
-#define SYSCTL_RCGC0_CAN0       0x01000000  // CAN0 Clock Gating Control.
-#define SYSCTL_RCGC0_PWM        0x00100000  // PWM Clock Gating Control.
-#define SYSCTL_RCGC0_ADC        0x00010000  // ADC0 Clock Gating Control.
-#define SYSCTL_RCGC0_ADCSPD_M   0x00000300  // ADC Sample Speed.
+#define SYSCTL_RCGC0_CAN0       0x01000000  // CAN0 Clock Gating Control
+#define SYSCTL_RCGC0_PWM        0x00100000  // PWM Clock Gating Control
+#define SYSCTL_RCGC0_ADC        0x00010000  // ADC0 Clock Gating Control
+#define SYSCTL_RCGC0_ADCSPD_M   0x00000300  // ADC Sample Speed
 #define SYSCTL_RCGC0_ADCSPD125K 0x00000000  // 125K samples/second
 #define SYSCTL_RCGC0_ADCSPD250K 0x00000100  // 250K samples/second
 #define SYSCTL_RCGC0_ADCSPD500K 0x00000200  // 500K samples/second
-#define SYSCTL_RCGC0_HIB        0x00000040  // HIB Clock Gating Control.
-#define SYSCTL_RCGC0_WDT        0x00000008  // WDT Clock Gating Control.
+#define SYSCTL_RCGC0_HIB        0x00000040  // HIB Clock Gating Control
+#define SYSCTL_RCGC0_WDT        0x00000008  // WDT Clock Gating Control
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_RCGC1 register.
 //
 //*****************************************************************************
-#define SYSCTL_RCGC1_COMP0      0x01000000  // Analog Comparator 0 Clock
-                                            // Gating.
-#define SYSCTL_RCGC1_TIMER3     0x00080000  // Timer 3 Clock Gating Control.
-#define SYSCTL_RCGC1_TIMER2     0x00040000  // Timer 2 Clock Gating Control.
-#define SYSCTL_RCGC1_TIMER1     0x00020000  // Timer 1 Clock Gating Control.
-#define SYSCTL_RCGC1_TIMER0     0x00010000  // Timer 0 Clock Gating Control.
-#define SYSCTL_RCGC1_I2C0       0x00001000  // I2C0 Clock Gating Control.
-#define SYSCTL_RCGC1_QEI1       0x00000200  // QEI1 Clock Gating Control.
-#define SYSCTL_RCGC1_QEI0       0x00000100  // QEI0 Clock Gating Control.
-#define SYSCTL_RCGC1_SSI0       0x00000010  // SSI0 Clock Gating Control.
-#define SYSCTL_RCGC1_UART1      0x00000002  // UART1 Clock Gating Control.
-#define SYSCTL_RCGC1_UART0      0x00000001  // UART0 Clock Gating Control.
+#define SYSCTL_RCGC1_COMP0      0x01000000  // Analog Comparator 0 Clock Gating
+#define SYSCTL_RCGC1_TIMER3     0x00080000  // Timer 3 Clock Gating Control
+#define SYSCTL_RCGC1_TIMER2     0x00040000  // Timer 2 Clock Gating Control
+#define SYSCTL_RCGC1_TIMER1     0x00020000  // Timer 1 Clock Gating Control
+#define SYSCTL_RCGC1_TIMER0     0x00010000  // Timer 0 Clock Gating Control
+#define SYSCTL_RCGC1_I2C0       0x00001000  // I2C0 Clock Gating Control
+#define SYSCTL_RCGC1_QEI1       0x00000200  // QEI1 Clock Gating Control
+#define SYSCTL_RCGC1_QEI0       0x00000100  // QEI0 Clock Gating Control
+#define SYSCTL_RCGC1_SSI0       0x00000010  // SSI0 Clock Gating Control
+#define SYSCTL_RCGC1_UART1      0x00000002  // UART1 Clock Gating Control
+#define SYSCTL_RCGC1_UART0      0x00000001  // UART0 Clock Gating Control
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_RCGC2 register.
 //
 //*****************************************************************************
-#define SYSCTL_RCGC2_EPHY0      0x40000000  // PHY0 Clock Gating Control.
-#define SYSCTL_RCGC2_EMAC0      0x10000000  // MAC0 Clock Gating Control.
-#define SYSCTL_RCGC2_GPIOG      0x00000040  // Port G Clock Gating Control.
-#define SYSCTL_RCGC2_GPIOF      0x00000020  // Port F Clock Gating Control.
-#define SYSCTL_RCGC2_GPIOE      0x00000010  // Port E Clock Gating Control.
-#define SYSCTL_RCGC2_GPIOD      0x00000008  // Port D Clock Gating Control.
-#define SYSCTL_RCGC2_GPIOC      0x00000004  // Port C Clock Gating Control.
-#define SYSCTL_RCGC2_GPIOB      0x00000002  // Port B Clock Gating Control.
-#define SYSCTL_RCGC2_GPIOA      0x00000001  // Port A Clock Gating Control.
+#define SYSCTL_RCGC2_EPHY0      0x40000000  // PHY0 Clock Gating Control
+#define SYSCTL_RCGC2_EMAC0      0x10000000  // MAC0 Clock Gating Control
+#define SYSCTL_RCGC2_GPIOG      0x00000040  // Port G Clock Gating Control
+#define SYSCTL_RCGC2_GPIOF      0x00000020  // Port F Clock Gating Control
+#define SYSCTL_RCGC2_GPIOE      0x00000010  // Port E Clock Gating Control
+#define SYSCTL_RCGC2_GPIOD      0x00000008  // Port D Clock Gating Control
+#define SYSCTL_RCGC2_GPIOC      0x00000004  // Port C Clock Gating Control
+#define SYSCTL_RCGC2_GPIOB      0x00000002  // Port B Clock Gating Control
+#define SYSCTL_RCGC2_GPIOA      0x00000001  // Port A Clock Gating Control
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_SCGC0 register.
 //
 //*****************************************************************************
-#define SYSCTL_SCGC0_CAN0       0x01000000  // CAN0 Clock Gating Control.
-#define SYSCTL_SCGC0_PWM        0x00100000  // PWM Clock Gating Control.
-#define SYSCTL_SCGC0_ADC        0x00010000  // ADC0 Clock Gating Control.
-#define SYSCTL_SCGC0_ADCSPD_M   0x00000300  // ADC Sample Speed.
+#define SYSCTL_SCGC0_CAN0       0x01000000  // CAN0 Clock Gating Control
+#define SYSCTL_SCGC0_PWM        0x00100000  // PWM Clock Gating Control
+#define SYSCTL_SCGC0_ADC        0x00010000  // ADC0 Clock Gating Control
+#define SYSCTL_SCGC0_ADCSPD_M   0x00000300  // ADC Sample Speed
 #define SYSCTL_SCGC0_ADCSPD125K 0x00000000  // 125K samples/second
 #define SYSCTL_SCGC0_ADCSPD250K 0x00000100  // 250K samples/second
 #define SYSCTL_SCGC0_ADCSPD500K 0x00000200  // 500K samples/second
-#define SYSCTL_SCGC0_HIB        0x00000040  // HIB Clock Gating Control.
-#define SYSCTL_SCGC0_WDT        0x00000008  // WDT Clock Gating Control.
+#define SYSCTL_SCGC0_HIB        0x00000040  // HIB Clock Gating Control
+#define SYSCTL_SCGC0_WDT        0x00000008  // WDT Clock Gating Control
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_SCGC1 register.
 //
 //*****************************************************************************
-#define SYSCTL_SCGC1_COMP0      0x01000000  // Analog Comparator 0 Clock
-                                            // Gating.
-#define SYSCTL_SCGC1_TIMER3     0x00080000  // Timer 3 Clock Gating Control.
-#define SYSCTL_SCGC1_TIMER2     0x00040000  // Timer 2 Clock Gating Control.
-#define SYSCTL_SCGC1_TIMER1     0x00020000  // Timer 1 Clock Gating Control.
-#define SYSCTL_SCGC1_TIMER0     0x00010000  // Timer 0 Clock Gating Control.
-#define SYSCTL_SCGC1_I2C0       0x00001000  // I2C0 Clock Gating Control.
-#define SYSCTL_SCGC1_QEI1       0x00000200  // QEI1 Clock Gating Control.
-#define SYSCTL_SCGC1_QEI0       0x00000100  // QEI0 Clock Gating Control.
-#define SYSCTL_SCGC1_SSI0       0x00000010  // SSI0 Clock Gating Control.
-#define SYSCTL_SCGC1_UART1      0x00000002  // UART1 Clock Gating Control.
-#define SYSCTL_SCGC1_UART0      0x00000001  // UART0 Clock Gating Control.
+#define SYSCTL_SCGC1_COMP0      0x01000000  // Analog Comparator 0 Clock Gating
+#define SYSCTL_SCGC1_TIMER3     0x00080000  // Timer 3 Clock Gating Control
+#define SYSCTL_SCGC1_TIMER2     0x00040000  // Timer 2 Clock Gating Control
+#define SYSCTL_SCGC1_TIMER1     0x00020000  // Timer 1 Clock Gating Control
+#define SYSCTL_SCGC1_TIMER0     0x00010000  // Timer 0 Clock Gating Control
+#define SYSCTL_SCGC1_I2C0       0x00001000  // I2C0 Clock Gating Control
+#define SYSCTL_SCGC1_QEI1       0x00000200  // QEI1 Clock Gating Control
+#define SYSCTL_SCGC1_QEI0       0x00000100  // QEI0 Clock Gating Control
+#define SYSCTL_SCGC1_SSI0       0x00000010  // SSI0 Clock Gating Control
+#define SYSCTL_SCGC1_UART1      0x00000002  // UART1 Clock Gating Control
+#define SYSCTL_SCGC1_UART0      0x00000001  // UART0 Clock Gating Control
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_SCGC2 register.
 //
 //*****************************************************************************
-#define SYSCTL_SCGC2_EPHY0      0x40000000  // PHY0 Clock Gating Control.
-#define SYSCTL_SCGC2_EMAC0      0x10000000  // MAC0 Clock Gating Control.
-#define SYSCTL_SCGC2_GPIOG      0x00000040  // Port G Clock Gating Control.
-#define SYSCTL_SCGC2_GPIOF      0x00000020  // Port F Clock Gating Control.
-#define SYSCTL_SCGC2_GPIOE      0x00000010  // Port E Clock Gating Control.
-#define SYSCTL_SCGC2_GPIOD      0x00000008  // Port D Clock Gating Control.
-#define SYSCTL_SCGC2_GPIOC      0x00000004  // Port C Clock Gating Control.
-#define SYSCTL_SCGC2_GPIOB      0x00000002  // Port B Clock Gating Control.
-#define SYSCTL_SCGC2_GPIOA      0x00000001  // Port A Clock Gating Control.
+#define SYSCTL_SCGC2_EPHY0      0x40000000  // PHY0 Clock Gating Control
+#define SYSCTL_SCGC2_EMAC0      0x10000000  // MAC0 Clock Gating Control
+#define SYSCTL_SCGC2_GPIOG      0x00000040  // Port G Clock Gating Control
+#define SYSCTL_SCGC2_GPIOF      0x00000020  // Port F Clock Gating Control
+#define SYSCTL_SCGC2_GPIOE      0x00000010  // Port E Clock Gating Control
+#define SYSCTL_SCGC2_GPIOD      0x00000008  // Port D Clock Gating Control
+#define SYSCTL_SCGC2_GPIOC      0x00000004  // Port C Clock Gating Control
+#define SYSCTL_SCGC2_GPIOB      0x00000002  // Port B Clock Gating Control
+#define SYSCTL_SCGC2_GPIOA      0x00000001  // Port A Clock Gating Control
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_DCGC0 register.
 //
 //*****************************************************************************
-#define SYSCTL_DCGC0_CAN0       0x01000000  // CAN0 Clock Gating Control.
-#define SYSCTL_DCGC0_PWM        0x00100000  // PWM Clock Gating Control.
-#define SYSCTL_DCGC0_ADC        0x00010000  // ADC0 Clock Gating Control.
-#define SYSCTL_DCGC0_ADCSPD_M   0x00000300  // ADC Sample Speed.
-#define SYSCTL_DCGC0_ADCSPD125K 0x00000000  // 125K samples/second
-#define SYSCTL_DCGC0_ADCSPD250K 0x00000100  // 250K samples/second
-#define SYSCTL_DCGC0_ADCSPD500K 0x00000200  // 500K samples/second
-#define SYSCTL_DCGC0_HIB        0x00000040  // HIB Clock Gating Control.
-#define SYSCTL_DCGC0_WDT        0x00000008  // WDT Clock Gating Control.
+#define SYSCTL_DCGC0_CAN0       0x01000000  // CAN0 Clock Gating Control
+#define SYSCTL_DCGC0_PWM        0x00100000  // PWM Clock Gating Control
+#define SYSCTL_DCGC0_ADC        0x00010000  // ADC0 Clock Gating Control
+#define SYSCTL_DCGC0_HIB        0x00000040  // HIB Clock Gating Control
+#define SYSCTL_DCGC0_WDT        0x00000008  // WDT Clock Gating Control
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_DCGC1 register.
 //
 //*****************************************************************************
-#define SYSCTL_DCGC1_COMP0      0x01000000  // Analog Comparator 0 Clock
-                                            // Gating.
-#define SYSCTL_DCGC1_TIMER3     0x00080000  // Timer 3 Clock Gating Control.
-#define SYSCTL_DCGC1_TIMER2     0x00040000  // Timer 2 Clock Gating Control.
-#define SYSCTL_DCGC1_TIMER1     0x00020000  // Timer 1 Clock Gating Control.
-#define SYSCTL_DCGC1_TIMER0     0x00010000  // Timer 0 Clock Gating Control.
-#define SYSCTL_DCGC1_I2C0       0x00001000  // I2C0 Clock Gating Control.
-#define SYSCTL_DCGC1_QEI1       0x00000200  // QEI1 Clock Gating Control.
-#define SYSCTL_DCGC1_QEI0       0x00000100  // QEI0 Clock Gating Control.
-#define SYSCTL_DCGC1_SSI0       0x00000010  // SSI0 Clock Gating Control.
-#define SYSCTL_DCGC1_UART1      0x00000002  // UART1 Clock Gating Control.
-#define SYSCTL_DCGC1_UART0      0x00000001  // UART0 Clock Gating Control.
+#define SYSCTL_DCGC1_COMP0      0x01000000  // Analog Comparator 0 Clock Gating
+#define SYSCTL_DCGC1_TIMER3     0x00080000  // Timer 3 Clock Gating Control
+#define SYSCTL_DCGC1_TIMER2     0x00040000  // Timer 2 Clock Gating Control
+#define SYSCTL_DCGC1_TIMER1     0x00020000  // Timer 1 Clock Gating Control
+#define SYSCTL_DCGC1_TIMER0     0x00010000  // Timer 0 Clock Gating Control
+#define SYSCTL_DCGC1_I2C0       0x00001000  // I2C0 Clock Gating Control
+#define SYSCTL_DCGC1_QEI1       0x00000200  // QEI1 Clock Gating Control
+#define SYSCTL_DCGC1_QEI0       0x00000100  // QEI0 Clock Gating Control
+#define SYSCTL_DCGC1_SSI0       0x00000010  // SSI0 Clock Gating Control
+#define SYSCTL_DCGC1_UART1      0x00000002  // UART1 Clock Gating Control
+#define SYSCTL_DCGC1_UART0      0x00000001  // UART0 Clock Gating Control
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_DCGC2 register.
 //
 //*****************************************************************************
-#define SYSCTL_DCGC2_EPHY0      0x40000000  // PHY0 Clock Gating Control.
-#define SYSCTL_DCGC2_EMAC0      0x10000000  // MAC0 Clock Gating Control.
-#define SYSCTL_DCGC2_GPIOG      0x00000040  // Port G Clock Gating Control.
-#define SYSCTL_DCGC2_GPIOF      0x00000020  // Port F Clock Gating Control.
-#define SYSCTL_DCGC2_GPIOE      0x00000010  // Port E Clock Gating Control.
-#define SYSCTL_DCGC2_GPIOD      0x00000008  // Port D Clock Gating Control.
-#define SYSCTL_DCGC2_GPIOC      0x00000004  // Port C Clock Gating Control.
-#define SYSCTL_DCGC2_GPIOB      0x00000002  // Port B Clock Gating Control.
-#define SYSCTL_DCGC2_GPIOA      0x00000001  // Port A Clock Gating Control.
+#define SYSCTL_DCGC2_EPHY0      0x40000000  // PHY0 Clock Gating Control
+#define SYSCTL_DCGC2_EMAC0      0x10000000  // MAC0 Clock Gating Control
+#define SYSCTL_DCGC2_GPIOG      0x00000040  // Port G Clock Gating Control
+#define SYSCTL_DCGC2_GPIOF      0x00000020  // Port F Clock Gating Control
+#define SYSCTL_DCGC2_GPIOE      0x00000010  // Port E Clock Gating Control
+#define SYSCTL_DCGC2_GPIOD      0x00000008  // Port D Clock Gating Control
+#define SYSCTL_DCGC2_GPIOC      0x00000004  // Port C Clock Gating Control
+#define SYSCTL_DCGC2_GPIOB      0x00000002  // Port B Clock Gating Control
+#define SYSCTL_DCGC2_GPIOA      0x00000001  // Port A Clock Gating Control
 
 //*****************************************************************************
 //
@@ -3933,12 +3890,76 @@
 // register.
 //
 //*****************************************************************************
-#define SYSCTL_DSLPCLKCFG_D_M   0x1F800000  // Divider Field Override.
-#define SYSCTL_DSLPCLKCFG_O_M   0x00000070  // Clock Source.
+#define SYSCTL_DSLPCLKCFG_D_M   0x1F800000  // Divider Field Override
+#define SYSCTL_DSLPCLKCFG_D_1   0x00000000  // System clock /1
+#define SYSCTL_DSLPCLKCFG_D_2   0x00800000  // System clock /2
+#define SYSCTL_DSLPCLKCFG_D_3   0x01000000  // System clock /3
+#define SYSCTL_DSLPCLKCFG_D_4   0x01800000  // System clock /4
+#define SYSCTL_DSLPCLKCFG_D_5   0x02000000  // System clock /5
+#define SYSCTL_DSLPCLKCFG_D_6   0x02800000  // System clock /6
+#define SYSCTL_DSLPCLKCFG_D_7   0x03000000  // System clock /7
+#define SYSCTL_DSLPCLKCFG_D_8   0x03800000  // System clock /8
+#define SYSCTL_DSLPCLKCFG_D_9   0x04000000  // System clock /9
+#define SYSCTL_DSLPCLKCFG_D_10  0x04800000  // System clock /10
+#define SYSCTL_DSLPCLKCFG_D_11  0x05000000  // System clock /11
+#define SYSCTL_DSLPCLKCFG_D_12  0x05800000  // System clock /12
+#define SYSCTL_DSLPCLKCFG_D_13  0x06000000  // System clock /13
+#define SYSCTL_DSLPCLKCFG_D_14  0x06800000  // System clock /14
+#define SYSCTL_DSLPCLKCFG_D_15  0x07000000  // System clock /15
+#define SYSCTL_DSLPCLKCFG_D_16  0x07800000  // System clock /16
+#define SYSCTL_DSLPCLKCFG_D_17  0x08000000  // System clock /17
+#define SYSCTL_DSLPCLKCFG_D_18  0x08800000  // System clock /18
+#define SYSCTL_DSLPCLKCFG_D_19  0x09000000  // System clock /19
+#define SYSCTL_DSLPCLKCFG_D_20  0x09800000  // System clock /20
+#define SYSCTL_DSLPCLKCFG_D_21  0x0A000000  // System clock /21
+#define SYSCTL_DSLPCLKCFG_D_22  0x0A800000  // System clock /22
+#define SYSCTL_DSLPCLKCFG_D_23  0x0B000000  // System clock /23
+#define SYSCTL_DSLPCLKCFG_D_24  0x0B800000  // System clock /24
+#define SYSCTL_DSLPCLKCFG_D_25  0x0C000000  // System clock /25
+#define SYSCTL_DSLPCLKCFG_D_26  0x0C800000  // System clock /26
+#define SYSCTL_DSLPCLKCFG_D_27  0x0D000000  // System clock /27
+#define SYSCTL_DSLPCLKCFG_D_28  0x0D800000  // System clock /28
+#define SYSCTL_DSLPCLKCFG_D_29  0x0E000000  // System clock /29
+#define SYSCTL_DSLPCLKCFG_D_30  0x0E800000  // System clock /30
+#define SYSCTL_DSLPCLKCFG_D_31  0x0F000000  // System clock /31
+#define SYSCTL_DSLPCLKCFG_D_32  0x0F800000  // System clock /32
+#define SYSCTL_DSLPCLKCFG_D_33  0x10000000  // System clock /33
+#define SYSCTL_DSLPCLKCFG_D_34  0x10800000  // System clock /34
+#define SYSCTL_DSLPCLKCFG_D_35  0x11000000  // System clock /35
+#define SYSCTL_DSLPCLKCFG_D_36  0x11800000  // System clock /36
+#define SYSCTL_DSLPCLKCFG_D_37  0x12000000  // System clock /37
+#define SYSCTL_DSLPCLKCFG_D_38  0x12800000  // System clock /38
+#define SYSCTL_DSLPCLKCFG_D_39  0x13000000  // System clock /39
+#define SYSCTL_DSLPCLKCFG_D_40  0x13800000  // System clock /40
+#define SYSCTL_DSLPCLKCFG_D_41  0x14000000  // System clock /41
+#define SYSCTL_DSLPCLKCFG_D_42  0x14800000  // System clock /42
+#define SYSCTL_DSLPCLKCFG_D_43  0x15000000  // System clock /43
+#define SYSCTL_DSLPCLKCFG_D_44  0x15800000  // System clock /44
+#define SYSCTL_DSLPCLKCFG_D_45  0x16000000  // System clock /45
+#define SYSCTL_DSLPCLKCFG_D_46  0x16800000  // System clock /46
+#define SYSCTL_DSLPCLKCFG_D_47  0x17000000  // System clock /47
+#define SYSCTL_DSLPCLKCFG_D_48  0x17800000  // System clock /48
+#define SYSCTL_DSLPCLKCFG_D_49  0x18000000  // System clock /49
+#define SYSCTL_DSLPCLKCFG_D_50  0x18800000  // System clock /50
+#define SYSCTL_DSLPCLKCFG_D_51  0x19000000  // System clock /51
+#define SYSCTL_DSLPCLKCFG_D_52  0x19800000  // System clock /52
+#define SYSCTL_DSLPCLKCFG_D_53  0x1A000000  // System clock /53
+#define SYSCTL_DSLPCLKCFG_D_54  0x1A800000  // System clock /54
+#define SYSCTL_DSLPCLKCFG_D_55  0x1B000000  // System clock /55
+#define SYSCTL_DSLPCLKCFG_D_56  0x1B800000  // System clock /56
+#define SYSCTL_DSLPCLKCFG_D_57  0x1C000000  // System clock /57
+#define SYSCTL_DSLPCLKCFG_D_58  0x1C800000  // System clock /58
+#define SYSCTL_DSLPCLKCFG_D_59  0x1D000000  // System clock /59
+#define SYSCTL_DSLPCLKCFG_D_60  0x1D800000  // System clock /60
+#define SYSCTL_DSLPCLKCFG_D_61  0x1E000000  // System clock /61
+#define SYSCTL_DSLPCLKCFG_D_62  0x1E800000  // System clock /62
+#define SYSCTL_DSLPCLKCFG_D_63  0x1F000000  // System clock /63
+#define SYSCTL_DSLPCLKCFG_D_64  0x1F800000  // System clock /64
+#define SYSCTL_DSLPCLKCFG_O_M   0x00000070  // Clock Source
 #define SYSCTL_DSLPCLKCFG_O_IGN 0x00000000  // MOSC
-#define SYSCTL_DSLPCLKCFG_O_IO  0x00000010  // IOSC
+#define SYSCTL_DSLPCLKCFG_O_IO  0x00000010  // PIOSC
 #define SYSCTL_DSLPCLKCFG_O_30  0x00000030  // 30 kHz
-#define SYSCTL_DSLPCLKCFG_O_32  0x00000070  // 32 kHz
+#define SYSCTL_DSLPCLKCFG_O_32  0x00000070  // 32.768 kHz
 #define SYSCTL_DSLPCLKCFG_D_S   23
 
 //*****************************************************************************
@@ -3954,17 +3975,17 @@
 // The following are defines for the bit fields in the NVIC_ST_CTRL register.
 //
 //*****************************************************************************
-#define NVIC_ST_CTRL_COUNT      0x00010000  // Count flag
+#define NVIC_ST_CTRL_COUNT      0x00010000  // Count Flag
 #define NVIC_ST_CTRL_CLK_SRC    0x00000004  // Clock Source
-#define NVIC_ST_CTRL_INTEN      0x00000002  // Interrupt enable
-#define NVIC_ST_CTRL_ENABLE     0x00000001  // Counter mode
+#define NVIC_ST_CTRL_INTEN      0x00000002  // Interrupt Enable
+#define NVIC_ST_CTRL_ENABLE     0x00000001  // Enable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_ST_RELOAD register.
 //
 //*****************************************************************************
-#define NVIC_ST_RELOAD_M        0x00FFFFFF  // Counter load value
+#define NVIC_ST_RELOAD_M        0x00FFFFFF  // Reload Value
 #define NVIC_ST_RELOAD_S        0
 
 //*****************************************************************************
@@ -3973,7 +3994,7 @@
 // register.
 //
 //*****************************************************************************
-#define NVIC_ST_CURRENT_M       0x00FFFFFF  // Counter current value
+#define NVIC_ST_CURRENT_M       0x00FFFFFF  // Current Value
 #define NVIC_ST_CURRENT_S       0
 
 //*****************************************************************************
@@ -3991,539 +4012,541 @@
 // The following are defines for the bit fields in the NVIC_EN0 register.
 //
 //*****************************************************************************
-#define NVIC_EN0_INT31          0x80000000  // Interrupt 31 enable
-#define NVIC_EN0_INT30          0x40000000  // Interrupt 30 enable
-#define NVIC_EN0_INT29          0x20000000  // Interrupt 29 enable
-#define NVIC_EN0_INT28          0x10000000  // Interrupt 28 enable
-#define NVIC_EN0_INT27          0x08000000  // Interrupt 27 enable
-#define NVIC_EN0_INT26          0x04000000  // Interrupt 26 enable
-#define NVIC_EN0_INT25          0x02000000  // Interrupt 25 enable
-#define NVIC_EN0_INT24          0x01000000  // Interrupt 24 enable
-#define NVIC_EN0_INT23          0x00800000  // Interrupt 23 enable
-#define NVIC_EN0_INT22          0x00400000  // Interrupt 22 enable
-#define NVIC_EN0_INT21          0x00200000  // Interrupt 21 enable
-#define NVIC_EN0_INT20          0x00100000  // Interrupt 20 enable
-#define NVIC_EN0_INT19          0x00080000  // Interrupt 19 enable
-#define NVIC_EN0_INT18          0x00040000  // Interrupt 18 enable
-#define NVIC_EN0_INT17          0x00020000  // Interrupt 17 enable
-#define NVIC_EN0_INT16          0x00010000  // Interrupt 16 enable
-#define NVIC_EN0_INT15          0x00008000  // Interrupt 15 enable
-#define NVIC_EN0_INT14          0x00004000  // Interrupt 14 enable
-#define NVIC_EN0_INT13          0x00002000  // Interrupt 13 enable
-#define NVIC_EN0_INT12          0x00001000  // Interrupt 12 enable
-#define NVIC_EN0_INT11          0x00000800  // Interrupt 11 enable
-#define NVIC_EN0_INT10          0x00000400  // Interrupt 10 enable
-#define NVIC_EN0_INT9           0x00000200  // Interrupt 9 enable
-#define NVIC_EN0_INT8           0x00000100  // Interrupt 8 enable
-#define NVIC_EN0_INT7           0x00000080  // Interrupt 7 enable
-#define NVIC_EN0_INT6           0x00000040  // Interrupt 6 enable
-#define NVIC_EN0_INT5           0x00000020  // Interrupt 5 enable
-#define NVIC_EN0_INT4           0x00000010  // Interrupt 4 enable
-#define NVIC_EN0_INT3           0x00000008  // Interrupt 3 enable
-#define NVIC_EN0_INT2           0x00000004  // Interrupt 2 enable
-#define NVIC_EN0_INT1           0x00000002  // Interrupt 1 enable
+#define NVIC_EN0_INT_M          0xFFFFFFFF  // Interrupt Enable
 #define NVIC_EN0_INT0           0x00000001  // Interrupt 0 enable
+#define NVIC_EN0_INT1           0x00000002  // Interrupt 1 enable
+#define NVIC_EN0_INT2           0x00000004  // Interrupt 2 enable
+#define NVIC_EN0_INT3           0x00000008  // Interrupt 3 enable
+#define NVIC_EN0_INT4           0x00000010  // Interrupt 4 enable
+#define NVIC_EN0_INT5           0x00000020  // Interrupt 5 enable
+#define NVIC_EN0_INT6           0x00000040  // Interrupt 6 enable
+#define NVIC_EN0_INT7           0x00000080  // Interrupt 7 enable
+#define NVIC_EN0_INT8           0x00000100  // Interrupt 8 enable
+#define NVIC_EN0_INT9           0x00000200  // Interrupt 9 enable
+#define NVIC_EN0_INT10          0x00000400  // Interrupt 10 enable
+#define NVIC_EN0_INT11          0x00000800  // Interrupt 11 enable
+#define NVIC_EN0_INT12          0x00001000  // Interrupt 12 enable
+#define NVIC_EN0_INT13          0x00002000  // Interrupt 13 enable
+#define NVIC_EN0_INT14          0x00004000  // Interrupt 14 enable
+#define NVIC_EN0_INT15          0x00008000  // Interrupt 15 enable
+#define NVIC_EN0_INT16          0x00010000  // Interrupt 16 enable
+#define NVIC_EN0_INT17          0x00020000  // Interrupt 17 enable
+#define NVIC_EN0_INT18          0x00040000  // Interrupt 18 enable
+#define NVIC_EN0_INT19          0x00080000  // Interrupt 19 enable
+#define NVIC_EN0_INT20          0x00100000  // Interrupt 20 enable
+#define NVIC_EN0_INT21          0x00200000  // Interrupt 21 enable
+#define NVIC_EN0_INT22          0x00400000  // Interrupt 22 enable
+#define NVIC_EN0_INT23          0x00800000  // Interrupt 23 enable
+#define NVIC_EN0_INT24          0x01000000  // Interrupt 24 enable
+#define NVIC_EN0_INT25          0x02000000  // Interrupt 25 enable
+#define NVIC_EN0_INT26          0x04000000  // Interrupt 26 enable
+#define NVIC_EN0_INT27          0x08000000  // Interrupt 27 enable
+#define NVIC_EN0_INT28          0x10000000  // Interrupt 28 enable
+#define NVIC_EN0_INT29          0x20000000  // Interrupt 29 enable
+#define NVIC_EN0_INT30          0x40000000  // Interrupt 30 enable
+#define NVIC_EN0_INT31          0x80000000  // Interrupt 31 enable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_EN1 register.
 //
 //*****************************************************************************
-#define NVIC_EN1_INT59          0x08000000  // Interrupt 59 enable
-#define NVIC_EN1_INT58          0x04000000  // Interrupt 58 enable
-#define NVIC_EN1_INT57          0x02000000  // Interrupt 57 enable
-#define NVIC_EN1_INT56          0x01000000  // Interrupt 56 enable
-#define NVIC_EN1_INT55          0x00800000  // Interrupt 55 enable
-#define NVIC_EN1_INT54          0x00400000  // Interrupt 54 enable
-#define NVIC_EN1_INT53          0x00200000  // Interrupt 53 enable
-#define NVIC_EN1_INT52          0x00100000  // Interrupt 52 enable
-#define NVIC_EN1_INT51          0x00080000  // Interrupt 51 enable
-#define NVIC_EN1_INT50          0x00040000  // Interrupt 50 enable
-#define NVIC_EN1_INT49          0x00020000  // Interrupt 49 enable
-#define NVIC_EN1_INT48          0x00010000  // Interrupt 48 enable
-#define NVIC_EN1_INT47          0x00008000  // Interrupt 47 enable
-#define NVIC_EN1_INT46          0x00004000  // Interrupt 46 enable
-#define NVIC_EN1_INT45          0x00002000  // Interrupt 45 enable
-#define NVIC_EN1_INT44          0x00001000  // Interrupt 44 enable
-#define NVIC_EN1_INT43          0x00000800  // Interrupt 43 enable
-#define NVIC_EN1_INT42          0x00000400  // Interrupt 42 enable
-#define NVIC_EN1_INT41          0x00000200  // Interrupt 41 enable
-#define NVIC_EN1_INT40          0x00000100  // Interrupt 40 enable
-#define NVIC_EN1_INT39          0x00000080  // Interrupt 39 enable
-#define NVIC_EN1_INT38          0x00000040  // Interrupt 38 enable
-#define NVIC_EN1_INT37          0x00000020  // Interrupt 37 enable
-#define NVIC_EN1_INT36          0x00000010  // Interrupt 36 enable
-#define NVIC_EN1_INT35          0x00000008  // Interrupt 35 enable
-#define NVIC_EN1_INT34          0x00000004  // Interrupt 34 enable
-#define NVIC_EN1_INT33          0x00000002  // Interrupt 33 enable
+#define NVIC_EN1_INT_M          0x00000FFF  // Interrupt Enable
 #define NVIC_EN1_INT32          0x00000001  // Interrupt 32 enable
+#define NVIC_EN1_INT33          0x00000002  // Interrupt 33 enable
+#define NVIC_EN1_INT34          0x00000004  // Interrupt 34 enable
+#define NVIC_EN1_INT35          0x00000008  // Interrupt 35 enable
+#define NVIC_EN1_INT36          0x00000010  // Interrupt 36 enable
+#define NVIC_EN1_INT37          0x00000020  // Interrupt 37 enable
+#define NVIC_EN1_INT38          0x00000040  // Interrupt 38 enable
+#define NVIC_EN1_INT39          0x00000080  // Interrupt 39 enable
+#define NVIC_EN1_INT40          0x00000100  // Interrupt 40 enable
+#define NVIC_EN1_INT41          0x00000200  // Interrupt 41 enable
+#define NVIC_EN1_INT42          0x00000400  // Interrupt 42 enable
+#define NVIC_EN1_INT43          0x00000800  // Interrupt 43 enable
+#define NVIC_EN1_INT44          0x00001000  // Interrupt 44 enable
+#define NVIC_EN1_INT45          0x00002000  // Interrupt 45 enable
+#define NVIC_EN1_INT46          0x00004000  // Interrupt 46 enable
+#define NVIC_EN1_INT47          0x00008000  // Interrupt 47 enable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_DIS0 register.
 //
 //*****************************************************************************
-#define NVIC_DIS0_INT31         0x80000000  // Interrupt 31 disable
-#define NVIC_DIS0_INT30         0x40000000  // Interrupt 30 disable
-#define NVIC_DIS0_INT29         0x20000000  // Interrupt 29 disable
-#define NVIC_DIS0_INT28         0x10000000  // Interrupt 28 disable
-#define NVIC_DIS0_INT27         0x08000000  // Interrupt 27 disable
-#define NVIC_DIS0_INT26         0x04000000  // Interrupt 26 disable
-#define NVIC_DIS0_INT25         0x02000000  // Interrupt 25 disable
-#define NVIC_DIS0_INT24         0x01000000  // Interrupt 24 disable
-#define NVIC_DIS0_INT23         0x00800000  // Interrupt 23 disable
-#define NVIC_DIS0_INT22         0x00400000  // Interrupt 22 disable
-#define NVIC_DIS0_INT21         0x00200000  // Interrupt 21 disable
-#define NVIC_DIS0_INT20         0x00100000  // Interrupt 20 disable
-#define NVIC_DIS0_INT19         0x00080000  // Interrupt 19 disable
-#define NVIC_DIS0_INT18         0x00040000  // Interrupt 18 disable
-#define NVIC_DIS0_INT17         0x00020000  // Interrupt 17 disable
-#define NVIC_DIS0_INT16         0x00010000  // Interrupt 16 disable
-#define NVIC_DIS0_INT15         0x00008000  // Interrupt 15 disable
-#define NVIC_DIS0_INT14         0x00004000  // Interrupt 14 disable
-#define NVIC_DIS0_INT13         0x00002000  // Interrupt 13 disable
-#define NVIC_DIS0_INT12         0x00001000  // Interrupt 12 disable
-#define NVIC_DIS0_INT11         0x00000800  // Interrupt 11 disable
-#define NVIC_DIS0_INT10         0x00000400  // Interrupt 10 disable
-#define NVIC_DIS0_INT9          0x00000200  // Interrupt 9 disable
-#define NVIC_DIS0_INT8          0x00000100  // Interrupt 8 disable
-#define NVIC_DIS0_INT7          0x00000080  // Interrupt 7 disable
-#define NVIC_DIS0_INT6          0x00000040  // Interrupt 6 disable
-#define NVIC_DIS0_INT5          0x00000020  // Interrupt 5 disable
-#define NVIC_DIS0_INT4          0x00000010  // Interrupt 4 disable
-#define NVIC_DIS0_INT3          0x00000008  // Interrupt 3 disable
-#define NVIC_DIS0_INT2          0x00000004  // Interrupt 2 disable
-#define NVIC_DIS0_INT1          0x00000002  // Interrupt 1 disable
+#define NVIC_DIS0_INT_M         0xFFFFFFFF  // Interrupt Disable
 #define NVIC_DIS0_INT0          0x00000001  // Interrupt 0 disable
+#define NVIC_DIS0_INT1          0x00000002  // Interrupt 1 disable
+#define NVIC_DIS0_INT2          0x00000004  // Interrupt 2 disable
+#define NVIC_DIS0_INT3          0x00000008  // Interrupt 3 disable
+#define NVIC_DIS0_INT4          0x00000010  // Interrupt 4 disable
+#define NVIC_DIS0_INT5          0x00000020  // Interrupt 5 disable
+#define NVIC_DIS0_INT6          0x00000040  // Interrupt 6 disable
+#define NVIC_DIS0_INT7          0x00000080  // Interrupt 7 disable
+#define NVIC_DIS0_INT8          0x00000100  // Interrupt 8 disable
+#define NVIC_DIS0_INT9          0x00000200  // Interrupt 9 disable
+#define NVIC_DIS0_INT10         0x00000400  // Interrupt 10 disable
+#define NVIC_DIS0_INT11         0x00000800  // Interrupt 11 disable
+#define NVIC_DIS0_INT12         0x00001000  // Interrupt 12 disable
+#define NVIC_DIS0_INT13         0x00002000  // Interrupt 13 disable
+#define NVIC_DIS0_INT14         0x00004000  // Interrupt 14 disable
+#define NVIC_DIS0_INT15         0x00008000  // Interrupt 15 disable
+#define NVIC_DIS0_INT16         0x00010000  // Interrupt 16 disable
+#define NVIC_DIS0_INT17         0x00020000  // Interrupt 17 disable
+#define NVIC_DIS0_INT18         0x00040000  // Interrupt 18 disable
+#define NVIC_DIS0_INT19         0x00080000  // Interrupt 19 disable
+#define NVIC_DIS0_INT20         0x00100000  // Interrupt 20 disable
+#define NVIC_DIS0_INT21         0x00200000  // Interrupt 21 disable
+#define NVIC_DIS0_INT22         0x00400000  // Interrupt 22 disable
+#define NVIC_DIS0_INT23         0x00800000  // Interrupt 23 disable
+#define NVIC_DIS0_INT24         0x01000000  // Interrupt 24 disable
+#define NVIC_DIS0_INT25         0x02000000  // Interrupt 25 disable
+#define NVIC_DIS0_INT26         0x04000000  // Interrupt 26 disable
+#define NVIC_DIS0_INT27         0x08000000  // Interrupt 27 disable
+#define NVIC_DIS0_INT28         0x10000000  // Interrupt 28 disable
+#define NVIC_DIS0_INT29         0x20000000  // Interrupt 29 disable
+#define NVIC_DIS0_INT30         0x40000000  // Interrupt 30 disable
+#define NVIC_DIS0_INT31         0x80000000  // Interrupt 31 disable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_DIS1 register.
 //
 //*****************************************************************************
-#define NVIC_DIS1_INT59         0x08000000  // Interrupt 59 disable
-#define NVIC_DIS1_INT58         0x04000000  // Interrupt 58 disable
-#define NVIC_DIS1_INT57         0x02000000  // Interrupt 57 disable
-#define NVIC_DIS1_INT56         0x01000000  // Interrupt 56 disable
-#define NVIC_DIS1_INT55         0x00800000  // Interrupt 55 disable
-#define NVIC_DIS1_INT54         0x00400000  // Interrupt 54 disable
-#define NVIC_DIS1_INT53         0x00200000  // Interrupt 53 disable
-#define NVIC_DIS1_INT52         0x00100000  // Interrupt 52 disable
-#define NVIC_DIS1_INT51         0x00080000  // Interrupt 51 disable
-#define NVIC_DIS1_INT50         0x00040000  // Interrupt 50 disable
-#define NVIC_DIS1_INT49         0x00020000  // Interrupt 49 disable
-#define NVIC_DIS1_INT48         0x00010000  // Interrupt 48 disable
-#define NVIC_DIS1_INT47         0x00008000  // Interrupt 47 disable
-#define NVIC_DIS1_INT46         0x00004000  // Interrupt 46 disable
-#define NVIC_DIS1_INT45         0x00002000  // Interrupt 45 disable
-#define NVIC_DIS1_INT44         0x00001000  // Interrupt 44 disable
-#define NVIC_DIS1_INT43         0x00000800  // Interrupt 43 disable
-#define NVIC_DIS1_INT42         0x00000400  // Interrupt 42 disable
-#define NVIC_DIS1_INT41         0x00000200  // Interrupt 41 disable
-#define NVIC_DIS1_INT40         0x00000100  // Interrupt 40 disable
-#define NVIC_DIS1_INT39         0x00000080  // Interrupt 39 disable
-#define NVIC_DIS1_INT38         0x00000040  // Interrupt 38 disable
-#define NVIC_DIS1_INT37         0x00000020  // Interrupt 37 disable
-#define NVIC_DIS1_INT36         0x00000010  // Interrupt 36 disable
-#define NVIC_DIS1_INT35         0x00000008  // Interrupt 35 disable
-#define NVIC_DIS1_INT34         0x00000004  // Interrupt 34 disable
-#define NVIC_DIS1_INT33         0x00000002  // Interrupt 33 disable
+#define NVIC_DIS1_INT_M         0x00000FFF  // Interrupt Disable
 #define NVIC_DIS1_INT32         0x00000001  // Interrupt 32 disable
+#define NVIC_DIS1_INT33         0x00000002  // Interrupt 33 disable
+#define NVIC_DIS1_INT34         0x00000004  // Interrupt 34 disable
+#define NVIC_DIS1_INT35         0x00000008  // Interrupt 35 disable
+#define NVIC_DIS1_INT36         0x00000010  // Interrupt 36 disable
+#define NVIC_DIS1_INT37         0x00000020  // Interrupt 37 disable
+#define NVIC_DIS1_INT38         0x00000040  // Interrupt 38 disable
+#define NVIC_DIS1_INT39         0x00000080  // Interrupt 39 disable
+#define NVIC_DIS1_INT40         0x00000100  // Interrupt 40 disable
+#define NVIC_DIS1_INT41         0x00000200  // Interrupt 41 disable
+#define NVIC_DIS1_INT42         0x00000400  // Interrupt 42 disable
+#define NVIC_DIS1_INT43         0x00000800  // Interrupt 43 disable
+#define NVIC_DIS1_INT44         0x00001000  // Interrupt 44 disable
+#define NVIC_DIS1_INT45         0x00002000  // Interrupt 45 disable
+#define NVIC_DIS1_INT46         0x00004000  // Interrupt 46 disable
+#define NVIC_DIS1_INT47         0x00008000  // Interrupt 47 disable
+#define NVIC_DIS1_INT48         0x00010000  // Interrupt 48 disable
+#define NVIC_DIS1_INT49         0x00020000  // Interrupt 49 disable
+#define NVIC_DIS1_INT50         0x00040000  // Interrupt 50 disable
+#define NVIC_DIS1_INT51         0x00080000  // Interrupt 51 disable
+#define NVIC_DIS1_INT52         0x00100000  // Interrupt 52 disable
+#define NVIC_DIS1_INT53         0x00200000  // Interrupt 53 disable
+#define NVIC_DIS1_INT54         0x00400000  // Interrupt 54 disable
+#define NVIC_DIS1_INT55         0x00800000  // Interrupt 55 disable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_PEND0 register.
 //
 //*****************************************************************************
-#define NVIC_PEND0_INT31        0x80000000  // Interrupt 31 pend
-#define NVIC_PEND0_INT30        0x40000000  // Interrupt 30 pend
-#define NVIC_PEND0_INT29        0x20000000  // Interrupt 29 pend
-#define NVIC_PEND0_INT28        0x10000000  // Interrupt 28 pend
-#define NVIC_PEND0_INT27        0x08000000  // Interrupt 27 pend
-#define NVIC_PEND0_INT26        0x04000000  // Interrupt 26 pend
-#define NVIC_PEND0_INT25        0x02000000  // Interrupt 25 pend
-#define NVIC_PEND0_INT24        0x01000000  // Interrupt 24 pend
-#define NVIC_PEND0_INT23        0x00800000  // Interrupt 23 pend
-#define NVIC_PEND0_INT22        0x00400000  // Interrupt 22 pend
-#define NVIC_PEND0_INT21        0x00200000  // Interrupt 21 pend
-#define NVIC_PEND0_INT20        0x00100000  // Interrupt 20 pend
-#define NVIC_PEND0_INT19        0x00080000  // Interrupt 19 pend
-#define NVIC_PEND0_INT18        0x00040000  // Interrupt 18 pend
-#define NVIC_PEND0_INT17        0x00020000  // Interrupt 17 pend
-#define NVIC_PEND0_INT16        0x00010000  // Interrupt 16 pend
-#define NVIC_PEND0_INT15        0x00008000  // Interrupt 15 pend
-#define NVIC_PEND0_INT14        0x00004000  // Interrupt 14 pend
-#define NVIC_PEND0_INT13        0x00002000  // Interrupt 13 pend
-#define NVIC_PEND0_INT12        0x00001000  // Interrupt 12 pend
-#define NVIC_PEND0_INT11        0x00000800  // Interrupt 11 pend
-#define NVIC_PEND0_INT10        0x00000400  // Interrupt 10 pend
-#define NVIC_PEND0_INT9         0x00000200  // Interrupt 9 pend
-#define NVIC_PEND0_INT8         0x00000100  // Interrupt 8 pend
-#define NVIC_PEND0_INT7         0x00000080  // Interrupt 7 pend
-#define NVIC_PEND0_INT6         0x00000040  // Interrupt 6 pend
-#define NVIC_PEND0_INT5         0x00000020  // Interrupt 5 pend
-#define NVIC_PEND0_INT4         0x00000010  // Interrupt 4 pend
-#define NVIC_PEND0_INT3         0x00000008  // Interrupt 3 pend
-#define NVIC_PEND0_INT2         0x00000004  // Interrupt 2 pend
-#define NVIC_PEND0_INT1         0x00000002  // Interrupt 1 pend
+#define NVIC_PEND0_INT_M        0xFFFFFFFF  // Interrupt Set Pending
 #define NVIC_PEND0_INT0         0x00000001  // Interrupt 0 pend
+#define NVIC_PEND0_INT1         0x00000002  // Interrupt 1 pend
+#define NVIC_PEND0_INT2         0x00000004  // Interrupt 2 pend
+#define NVIC_PEND0_INT3         0x00000008  // Interrupt 3 pend
+#define NVIC_PEND0_INT4         0x00000010  // Interrupt 4 pend
+#define NVIC_PEND0_INT5         0x00000020  // Interrupt 5 pend
+#define NVIC_PEND0_INT6         0x00000040  // Interrupt 6 pend
+#define NVIC_PEND0_INT7         0x00000080  // Interrupt 7 pend
+#define NVIC_PEND0_INT8         0x00000100  // Interrupt 8 pend
+#define NVIC_PEND0_INT9         0x00000200  // Interrupt 9 pend
+#define NVIC_PEND0_INT10        0x00000400  // Interrupt 10 pend
+#define NVIC_PEND0_INT11        0x00000800  // Interrupt 11 pend
+#define NVIC_PEND0_INT12        0x00001000  // Interrupt 12 pend
+#define NVIC_PEND0_INT13        0x00002000  // Interrupt 13 pend
+#define NVIC_PEND0_INT14        0x00004000  // Interrupt 14 pend
+#define NVIC_PEND0_INT15        0x00008000  // Interrupt 15 pend
+#define NVIC_PEND0_INT16        0x00010000  // Interrupt 16 pend
+#define NVIC_PEND0_INT17        0x00020000  // Interrupt 17 pend
+#define NVIC_PEND0_INT18        0x00040000  // Interrupt 18 pend
+#define NVIC_PEND0_INT19        0x00080000  // Interrupt 19 pend
+#define NVIC_PEND0_INT20        0x00100000  // Interrupt 20 pend
+#define NVIC_PEND0_INT21        0x00200000  // Interrupt 21 pend
+#define NVIC_PEND0_INT22        0x00400000  // Interrupt 22 pend
+#define NVIC_PEND0_INT23        0x00800000  // Interrupt 23 pend
+#define NVIC_PEND0_INT24        0x01000000  // Interrupt 24 pend
+#define NVIC_PEND0_INT25        0x02000000  // Interrupt 25 pend
+#define NVIC_PEND0_INT26        0x04000000  // Interrupt 26 pend
+#define NVIC_PEND0_INT27        0x08000000  // Interrupt 27 pend
+#define NVIC_PEND0_INT28        0x10000000  // Interrupt 28 pend
+#define NVIC_PEND0_INT29        0x20000000  // Interrupt 29 pend
+#define NVIC_PEND0_INT30        0x40000000  // Interrupt 30 pend
+#define NVIC_PEND0_INT31        0x80000000  // Interrupt 31 pend
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_PEND1 register.
 //
 //*****************************************************************************
-#define NVIC_PEND1_INT59        0x08000000  // Interrupt 59 pend
-#define NVIC_PEND1_INT58        0x04000000  // Interrupt 58 pend
-#define NVIC_PEND1_INT57        0x02000000  // Interrupt 57 pend
-#define NVIC_PEND1_INT56        0x01000000  // Interrupt 56 pend
-#define NVIC_PEND1_INT55        0x00800000  // Interrupt 55 pend
-#define NVIC_PEND1_INT54        0x00400000  // Interrupt 54 pend
-#define NVIC_PEND1_INT53        0x00200000  // Interrupt 53 pend
-#define NVIC_PEND1_INT52        0x00100000  // Interrupt 52 pend
-#define NVIC_PEND1_INT51        0x00080000  // Interrupt 51 pend
-#define NVIC_PEND1_INT50        0x00040000  // Interrupt 50 pend
-#define NVIC_PEND1_INT49        0x00020000  // Interrupt 49 pend
-#define NVIC_PEND1_INT48        0x00010000  // Interrupt 48 pend
-#define NVIC_PEND1_INT47        0x00008000  // Interrupt 47 pend
-#define NVIC_PEND1_INT46        0x00004000  // Interrupt 46 pend
-#define NVIC_PEND1_INT45        0x00002000  // Interrupt 45 pend
-#define NVIC_PEND1_INT44        0x00001000  // Interrupt 44 pend
-#define NVIC_PEND1_INT43        0x00000800  // Interrupt 43 pend
-#define NVIC_PEND1_INT42        0x00000400  // Interrupt 42 pend
-#define NVIC_PEND1_INT41        0x00000200  // Interrupt 41 pend
-#define NVIC_PEND1_INT40        0x00000100  // Interrupt 40 pend
-#define NVIC_PEND1_INT39        0x00000080  // Interrupt 39 pend
-#define NVIC_PEND1_INT38        0x00000040  // Interrupt 38 pend
-#define NVIC_PEND1_INT37        0x00000020  // Interrupt 37 pend
-#define NVIC_PEND1_INT36        0x00000010  // Interrupt 36 pend
-#define NVIC_PEND1_INT35        0x00000008  // Interrupt 35 pend
-#define NVIC_PEND1_INT34        0x00000004  // Interrupt 34 pend
-#define NVIC_PEND1_INT33        0x00000002  // Interrupt 33 pend
+#define NVIC_PEND1_INT_M        0x00000FFF  // Interrupt Set Pending
 #define NVIC_PEND1_INT32        0x00000001  // Interrupt 32 pend
+#define NVIC_PEND1_INT33        0x00000002  // Interrupt 33 pend
+#define NVIC_PEND1_INT34        0x00000004  // Interrupt 34 pend
+#define NVIC_PEND1_INT35        0x00000008  // Interrupt 35 pend
+#define NVIC_PEND1_INT36        0x00000010  // Interrupt 36 pend
+#define NVIC_PEND1_INT37        0x00000020  // Interrupt 37 pend
+#define NVIC_PEND1_INT38        0x00000040  // Interrupt 38 pend
+#define NVIC_PEND1_INT39        0x00000080  // Interrupt 39 pend
+#define NVIC_PEND1_INT40        0x00000100  // Interrupt 40 pend
+#define NVIC_PEND1_INT41        0x00000200  // Interrupt 41 pend
+#define NVIC_PEND1_INT42        0x00000400  // Interrupt 42 pend
+#define NVIC_PEND1_INT43        0x00000800  // Interrupt 43 pend
+#define NVIC_PEND1_INT44        0x00001000  // Interrupt 44 pend
+#define NVIC_PEND1_INT45        0x00002000  // Interrupt 45 pend
+#define NVIC_PEND1_INT46        0x00004000  // Interrupt 46 pend
+#define NVIC_PEND1_INT47        0x00008000  // Interrupt 47 pend
+#define NVIC_PEND1_INT48        0x00010000  // Interrupt 48 pend
+#define NVIC_PEND1_INT49        0x00020000  // Interrupt 49 pend
+#define NVIC_PEND1_INT50        0x00040000  // Interrupt 50 pend
+#define NVIC_PEND1_INT51        0x00080000  // Interrupt 51 pend
+#define NVIC_PEND1_INT52        0x00100000  // Interrupt 52 pend
+#define NVIC_PEND1_INT53        0x00200000  // Interrupt 53 pend
+#define NVIC_PEND1_INT54        0x00400000  // Interrupt 54 pend
+#define NVIC_PEND1_INT55        0x00800000  // Interrupt 55 pend
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_UNPEND0 register.
 //
 //*****************************************************************************
-#define NVIC_UNPEND0_INT31      0x80000000  // Interrupt 31 unpend
-#define NVIC_UNPEND0_INT30      0x40000000  // Interrupt 30 unpend
-#define NVIC_UNPEND0_INT29      0x20000000  // Interrupt 29 unpend
-#define NVIC_UNPEND0_INT28      0x10000000  // Interrupt 28 unpend
-#define NVIC_UNPEND0_INT27      0x08000000  // Interrupt 27 unpend
-#define NVIC_UNPEND0_INT26      0x04000000  // Interrupt 26 unpend
-#define NVIC_UNPEND0_INT25      0x02000000  // Interrupt 25 unpend
-#define NVIC_UNPEND0_INT24      0x01000000  // Interrupt 24 unpend
-#define NVIC_UNPEND0_INT23      0x00800000  // Interrupt 23 unpend
-#define NVIC_UNPEND0_INT22      0x00400000  // Interrupt 22 unpend
-#define NVIC_UNPEND0_INT21      0x00200000  // Interrupt 21 unpend
-#define NVIC_UNPEND0_INT20      0x00100000  // Interrupt 20 unpend
-#define NVIC_UNPEND0_INT19      0x00080000  // Interrupt 19 unpend
-#define NVIC_UNPEND0_INT18      0x00040000  // Interrupt 18 unpend
-#define NVIC_UNPEND0_INT17      0x00020000  // Interrupt 17 unpend
-#define NVIC_UNPEND0_INT16      0x00010000  // Interrupt 16 unpend
-#define NVIC_UNPEND0_INT15      0x00008000  // Interrupt 15 unpend
-#define NVIC_UNPEND0_INT14      0x00004000  // Interrupt 14 unpend
-#define NVIC_UNPEND0_INT13      0x00002000  // Interrupt 13 unpend
-#define NVIC_UNPEND0_INT12      0x00001000  // Interrupt 12 unpend
-#define NVIC_UNPEND0_INT11      0x00000800  // Interrupt 11 unpend
-#define NVIC_UNPEND0_INT10      0x00000400  // Interrupt 10 unpend
-#define NVIC_UNPEND0_INT9       0x00000200  // Interrupt 9 unpend
-#define NVIC_UNPEND0_INT8       0x00000100  // Interrupt 8 unpend
-#define NVIC_UNPEND0_INT7       0x00000080  // Interrupt 7 unpend
-#define NVIC_UNPEND0_INT6       0x00000040  // Interrupt 6 unpend
-#define NVIC_UNPEND0_INT5       0x00000020  // Interrupt 5 unpend
-#define NVIC_UNPEND0_INT4       0x00000010  // Interrupt 4 unpend
-#define NVIC_UNPEND0_INT3       0x00000008  // Interrupt 3 unpend
-#define NVIC_UNPEND0_INT2       0x00000004  // Interrupt 2 unpend
-#define NVIC_UNPEND0_INT1       0x00000002  // Interrupt 1 unpend
+#define NVIC_UNPEND0_INT_M      0xFFFFFFFF  // Interrupt Clear Pending
 #define NVIC_UNPEND0_INT0       0x00000001  // Interrupt 0 unpend
+#define NVIC_UNPEND0_INT1       0x00000002  // Interrupt 1 unpend
+#define NVIC_UNPEND0_INT2       0x00000004  // Interrupt 2 unpend
+#define NVIC_UNPEND0_INT3       0x00000008  // Interrupt 3 unpend
+#define NVIC_UNPEND0_INT4       0x00000010  // Interrupt 4 unpend
+#define NVIC_UNPEND0_INT5       0x00000020  // Interrupt 5 unpend
+#define NVIC_UNPEND0_INT6       0x00000040  // Interrupt 6 unpend
+#define NVIC_UNPEND0_INT7       0x00000080  // Interrupt 7 unpend
+#define NVIC_UNPEND0_INT8       0x00000100  // Interrupt 8 unpend
+#define NVIC_UNPEND0_INT9       0x00000200  // Interrupt 9 unpend
+#define NVIC_UNPEND0_INT10      0x00000400  // Interrupt 10 unpend
+#define NVIC_UNPEND0_INT11      0x00000800  // Interrupt 11 unpend
+#define NVIC_UNPEND0_INT12      0x00001000  // Interrupt 12 unpend
+#define NVIC_UNPEND0_INT13      0x00002000  // Interrupt 13 unpend
+#define NVIC_UNPEND0_INT14      0x00004000  // Interrupt 14 unpend
+#define NVIC_UNPEND0_INT15      0x00008000  // Interrupt 15 unpend
+#define NVIC_UNPEND0_INT16      0x00010000  // Interrupt 16 unpend
+#define NVIC_UNPEND0_INT17      0x00020000  // Interrupt 17 unpend
+#define NVIC_UNPEND0_INT18      0x00040000  // Interrupt 18 unpend
+#define NVIC_UNPEND0_INT19      0x00080000  // Interrupt 19 unpend
+#define NVIC_UNPEND0_INT20      0x00100000  // Interrupt 20 unpend
+#define NVIC_UNPEND0_INT21      0x00200000  // Interrupt 21 unpend
+#define NVIC_UNPEND0_INT22      0x00400000  // Interrupt 22 unpend
+#define NVIC_UNPEND0_INT23      0x00800000  // Interrupt 23 unpend
+#define NVIC_UNPEND0_INT24      0x01000000  // Interrupt 24 unpend
+#define NVIC_UNPEND0_INT25      0x02000000  // Interrupt 25 unpend
+#define NVIC_UNPEND0_INT26      0x04000000  // Interrupt 26 unpend
+#define NVIC_UNPEND0_INT27      0x08000000  // Interrupt 27 unpend
+#define NVIC_UNPEND0_INT28      0x10000000  // Interrupt 28 unpend
+#define NVIC_UNPEND0_INT29      0x20000000  // Interrupt 29 unpend
+#define NVIC_UNPEND0_INT30      0x40000000  // Interrupt 30 unpend
+#define NVIC_UNPEND0_INT31      0x80000000  // Interrupt 31 unpend
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_UNPEND1 register.
 //
 //*****************************************************************************
-#define NVIC_UNPEND1_INT59      0x08000000  // Interrupt 59 unpend
-#define NVIC_UNPEND1_INT58      0x04000000  // Interrupt 58 unpend
-#define NVIC_UNPEND1_INT57      0x02000000  // Interrupt 57 unpend
-#define NVIC_UNPEND1_INT56      0x01000000  // Interrupt 56 unpend
-#define NVIC_UNPEND1_INT55      0x00800000  // Interrupt 55 unpend
-#define NVIC_UNPEND1_INT54      0x00400000  // Interrupt 54 unpend
-#define NVIC_UNPEND1_INT53      0x00200000  // Interrupt 53 unpend
-#define NVIC_UNPEND1_INT52      0x00100000  // Interrupt 52 unpend
-#define NVIC_UNPEND1_INT51      0x00080000  // Interrupt 51 unpend
-#define NVIC_UNPEND1_INT50      0x00040000  // Interrupt 50 unpend
-#define NVIC_UNPEND1_INT49      0x00020000  // Interrupt 49 unpend
-#define NVIC_UNPEND1_INT48      0x00010000  // Interrupt 48 unpend
-#define NVIC_UNPEND1_INT47      0x00008000  // Interrupt 47 unpend
-#define NVIC_UNPEND1_INT46      0x00004000  // Interrupt 46 unpend
-#define NVIC_UNPEND1_INT45      0x00002000  // Interrupt 45 unpend
-#define NVIC_UNPEND1_INT44      0x00001000  // Interrupt 44 unpend
-#define NVIC_UNPEND1_INT43      0x00000800  // Interrupt 43 unpend
-#define NVIC_UNPEND1_INT42      0x00000400  // Interrupt 42 unpend
-#define NVIC_UNPEND1_INT41      0x00000200  // Interrupt 41 unpend
-#define NVIC_UNPEND1_INT40      0x00000100  // Interrupt 40 unpend
-#define NVIC_UNPEND1_INT39      0x00000080  // Interrupt 39 unpend
-#define NVIC_UNPEND1_INT38      0x00000040  // Interrupt 38 unpend
-#define NVIC_UNPEND1_INT37      0x00000020  // Interrupt 37 unpend
-#define NVIC_UNPEND1_INT36      0x00000010  // Interrupt 36 unpend
-#define NVIC_UNPEND1_INT35      0x00000008  // Interrupt 35 unpend
-#define NVIC_UNPEND1_INT34      0x00000004  // Interrupt 34 unpend
-#define NVIC_UNPEND1_INT33      0x00000002  // Interrupt 33 unpend
+#define NVIC_UNPEND1_INT_M      0x00000FFF  // Interrupt Clear Pending
 #define NVIC_UNPEND1_INT32      0x00000001  // Interrupt 32 unpend
+#define NVIC_UNPEND1_INT33      0x00000002  // Interrupt 33 unpend
+#define NVIC_UNPEND1_INT34      0x00000004  // Interrupt 34 unpend
+#define NVIC_UNPEND1_INT35      0x00000008  // Interrupt 35 unpend
+#define NVIC_UNPEND1_INT36      0x00000010  // Interrupt 36 unpend
+#define NVIC_UNPEND1_INT37      0x00000020  // Interrupt 37 unpend
+#define NVIC_UNPEND1_INT38      0x00000040  // Interrupt 38 unpend
+#define NVIC_UNPEND1_INT39      0x00000080  // Interrupt 39 unpend
+#define NVIC_UNPEND1_INT40      0x00000100  // Interrupt 40 unpend
+#define NVIC_UNPEND1_INT41      0x00000200  // Interrupt 41 unpend
+#define NVIC_UNPEND1_INT42      0x00000400  // Interrupt 42 unpend
+#define NVIC_UNPEND1_INT43      0x00000800  // Interrupt 43 unpend
+#define NVIC_UNPEND1_INT44      0x00001000  // Interrupt 44 unpend
+#define NVIC_UNPEND1_INT45      0x00002000  // Interrupt 45 unpend
+#define NVIC_UNPEND1_INT46      0x00004000  // Interrupt 46 unpend
+#define NVIC_UNPEND1_INT47      0x00008000  // Interrupt 47 unpend
+#define NVIC_UNPEND1_INT48      0x00010000  // Interrupt 48 unpend
+#define NVIC_UNPEND1_INT49      0x00020000  // Interrupt 49 unpend
+#define NVIC_UNPEND1_INT50      0x00040000  // Interrupt 50 unpend
+#define NVIC_UNPEND1_INT51      0x00080000  // Interrupt 51 unpend
+#define NVIC_UNPEND1_INT52      0x00100000  // Interrupt 52 unpend
+#define NVIC_UNPEND1_INT53      0x00200000  // Interrupt 53 unpend
+#define NVIC_UNPEND1_INT54      0x00400000  // Interrupt 54 unpend
+#define NVIC_UNPEND1_INT55      0x00800000  // Interrupt 55 unpend
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_ACTIVE0 register.
 //
 //*****************************************************************************
-#define NVIC_ACTIVE0_INT31      0x80000000  // Interrupt 31 active
-#define NVIC_ACTIVE0_INT30      0x40000000  // Interrupt 30 active
-#define NVIC_ACTIVE0_INT29      0x20000000  // Interrupt 29 active
-#define NVIC_ACTIVE0_INT28      0x10000000  // Interrupt 28 active
-#define NVIC_ACTIVE0_INT27      0x08000000  // Interrupt 27 active
-#define NVIC_ACTIVE0_INT26      0x04000000  // Interrupt 26 active
-#define NVIC_ACTIVE0_INT25      0x02000000  // Interrupt 25 active
-#define NVIC_ACTIVE0_INT24      0x01000000  // Interrupt 24 active
-#define NVIC_ACTIVE0_INT23      0x00800000  // Interrupt 23 active
-#define NVIC_ACTIVE0_INT22      0x00400000  // Interrupt 22 active
-#define NVIC_ACTIVE0_INT21      0x00200000  // Interrupt 21 active
-#define NVIC_ACTIVE0_INT20      0x00100000  // Interrupt 20 active
-#define NVIC_ACTIVE0_INT19      0x00080000  // Interrupt 19 active
-#define NVIC_ACTIVE0_INT18      0x00040000  // Interrupt 18 active
-#define NVIC_ACTIVE0_INT17      0x00020000  // Interrupt 17 active
-#define NVIC_ACTIVE0_INT16      0x00010000  // Interrupt 16 active
-#define NVIC_ACTIVE0_INT15      0x00008000  // Interrupt 15 active
-#define NVIC_ACTIVE0_INT14      0x00004000  // Interrupt 14 active
-#define NVIC_ACTIVE0_INT13      0x00002000  // Interrupt 13 active
-#define NVIC_ACTIVE0_INT12      0x00001000  // Interrupt 12 active
-#define NVIC_ACTIVE0_INT11      0x00000800  // Interrupt 11 active
-#define NVIC_ACTIVE0_INT10      0x00000400  // Interrupt 10 active
-#define NVIC_ACTIVE0_INT9       0x00000200  // Interrupt 9 active
-#define NVIC_ACTIVE0_INT8       0x00000100  // Interrupt 8 active
-#define NVIC_ACTIVE0_INT7       0x00000080  // Interrupt 7 active
-#define NVIC_ACTIVE0_INT6       0x00000040  // Interrupt 6 active
-#define NVIC_ACTIVE0_INT5       0x00000020  // Interrupt 5 active
-#define NVIC_ACTIVE0_INT4       0x00000010  // Interrupt 4 active
-#define NVIC_ACTIVE0_INT3       0x00000008  // Interrupt 3 active
-#define NVIC_ACTIVE0_INT2       0x00000004  // Interrupt 2 active
-#define NVIC_ACTIVE0_INT1       0x00000002  // Interrupt 1 active
+#define NVIC_ACTIVE0_INT_M      0xFFFFFFFF  // Interrupt Active
 #define NVIC_ACTIVE0_INT0       0x00000001  // Interrupt 0 active
+#define NVIC_ACTIVE0_INT1       0x00000002  // Interrupt 1 active
+#define NVIC_ACTIVE0_INT2       0x00000004  // Interrupt 2 active
+#define NVIC_ACTIVE0_INT3       0x00000008  // Interrupt 3 active
+#define NVIC_ACTIVE0_INT4       0x00000010  // Interrupt 4 active
+#define NVIC_ACTIVE0_INT5       0x00000020  // Interrupt 5 active
+#define NVIC_ACTIVE0_INT6       0x00000040  // Interrupt 6 active
+#define NVIC_ACTIVE0_INT7       0x00000080  // Interrupt 7 active
+#define NVIC_ACTIVE0_INT8       0x00000100  // Interrupt 8 active
+#define NVIC_ACTIVE0_INT9       0x00000200  // Interrupt 9 active
+#define NVIC_ACTIVE0_INT10      0x00000400  // Interrupt 10 active
+#define NVIC_ACTIVE0_INT11      0x00000800  // Interrupt 11 active
+#define NVIC_ACTIVE0_INT12      0x00001000  // Interrupt 12 active
+#define NVIC_ACTIVE0_INT13      0x00002000  // Interrupt 13 active
+#define NVIC_ACTIVE0_INT14      0x00004000  // Interrupt 14 active
+#define NVIC_ACTIVE0_INT15      0x00008000  // Interrupt 15 active
+#define NVIC_ACTIVE0_INT16      0x00010000  // Interrupt 16 active
+#define NVIC_ACTIVE0_INT17      0x00020000  // Interrupt 17 active
+#define NVIC_ACTIVE0_INT18      0x00040000  // Interrupt 18 active
+#define NVIC_ACTIVE0_INT19      0x00080000  // Interrupt 19 active
+#define NVIC_ACTIVE0_INT20      0x00100000  // Interrupt 20 active
+#define NVIC_ACTIVE0_INT21      0x00200000  // Interrupt 21 active
+#define NVIC_ACTIVE0_INT22      0x00400000  // Interrupt 22 active
+#define NVIC_ACTIVE0_INT23      0x00800000  // Interrupt 23 active
+#define NVIC_ACTIVE0_INT24      0x01000000  // Interrupt 24 active
+#define NVIC_ACTIVE0_INT25      0x02000000  // Interrupt 25 active
+#define NVIC_ACTIVE0_INT26      0x04000000  // Interrupt 26 active
+#define NVIC_ACTIVE0_INT27      0x08000000  // Interrupt 27 active
+#define NVIC_ACTIVE0_INT28      0x10000000  // Interrupt 28 active
+#define NVIC_ACTIVE0_INT29      0x20000000  // Interrupt 29 active
+#define NVIC_ACTIVE0_INT30      0x40000000  // Interrupt 30 active
+#define NVIC_ACTIVE0_INT31      0x80000000  // Interrupt 31 active
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_ACTIVE1 register.
 //
 //*****************************************************************************
-#define NVIC_ACTIVE1_INT59      0x08000000  // Interrupt 59 active
-#define NVIC_ACTIVE1_INT58      0x04000000  // Interrupt 58 active
-#define NVIC_ACTIVE1_INT57      0x02000000  // Interrupt 57 active
-#define NVIC_ACTIVE1_INT56      0x01000000  // Interrupt 56 active
-#define NVIC_ACTIVE1_INT55      0x00800000  // Interrupt 55 active
-#define NVIC_ACTIVE1_INT54      0x00400000  // Interrupt 54 active
-#define NVIC_ACTIVE1_INT53      0x00200000  // Interrupt 53 active
-#define NVIC_ACTIVE1_INT52      0x00100000  // Interrupt 52 active
-#define NVIC_ACTIVE1_INT51      0x00080000  // Interrupt 51 active
-#define NVIC_ACTIVE1_INT50      0x00040000  // Interrupt 50 active
-#define NVIC_ACTIVE1_INT49      0x00020000  // Interrupt 49 active
-#define NVIC_ACTIVE1_INT48      0x00010000  // Interrupt 48 active
-#define NVIC_ACTIVE1_INT47      0x00008000  // Interrupt 47 active
-#define NVIC_ACTIVE1_INT46      0x00004000  // Interrupt 46 active
-#define NVIC_ACTIVE1_INT45      0x00002000  // Interrupt 45 active
-#define NVIC_ACTIVE1_INT44      0x00001000  // Interrupt 44 active
-#define NVIC_ACTIVE1_INT43      0x00000800  // Interrupt 43 active
-#define NVIC_ACTIVE1_INT42      0x00000400  // Interrupt 42 active
-#define NVIC_ACTIVE1_INT41      0x00000200  // Interrupt 41 active
-#define NVIC_ACTIVE1_INT40      0x00000100  // Interrupt 40 active
-#define NVIC_ACTIVE1_INT39      0x00000080  // Interrupt 39 active
-#define NVIC_ACTIVE1_INT38      0x00000040  // Interrupt 38 active
-#define NVIC_ACTIVE1_INT37      0x00000020  // Interrupt 37 active
-#define NVIC_ACTIVE1_INT36      0x00000010  // Interrupt 36 active
-#define NVIC_ACTIVE1_INT35      0x00000008  // Interrupt 35 active
-#define NVIC_ACTIVE1_INT34      0x00000004  // Interrupt 34 active
-#define NVIC_ACTIVE1_INT33      0x00000002  // Interrupt 33 active
+#define NVIC_ACTIVE1_INT_M      0x00000FFF  // Interrupt Active
 #define NVIC_ACTIVE1_INT32      0x00000001  // Interrupt 32 active
+#define NVIC_ACTIVE1_INT33      0x00000002  // Interrupt 33 active
+#define NVIC_ACTIVE1_INT34      0x00000004  // Interrupt 34 active
+#define NVIC_ACTIVE1_INT35      0x00000008  // Interrupt 35 active
+#define NVIC_ACTIVE1_INT36      0x00000010  // Interrupt 36 active
+#define NVIC_ACTIVE1_INT37      0x00000020  // Interrupt 37 active
+#define NVIC_ACTIVE1_INT38      0x00000040  // Interrupt 38 active
+#define NVIC_ACTIVE1_INT39      0x00000080  // Interrupt 39 active
+#define NVIC_ACTIVE1_INT40      0x00000100  // Interrupt 40 active
+#define NVIC_ACTIVE1_INT41      0x00000200  // Interrupt 41 active
+#define NVIC_ACTIVE1_INT42      0x00000400  // Interrupt 42 active
+#define NVIC_ACTIVE1_INT43      0x00000800  // Interrupt 43 active
+#define NVIC_ACTIVE1_INT44      0x00001000  // Interrupt 44 active
+#define NVIC_ACTIVE1_INT45      0x00002000  // Interrupt 45 active
+#define NVIC_ACTIVE1_INT46      0x00004000  // Interrupt 46 active
+#define NVIC_ACTIVE1_INT47      0x00008000  // Interrupt 47 active
+#define NVIC_ACTIVE1_INT48      0x00010000  // Interrupt 48 active
+#define NVIC_ACTIVE1_INT49      0x00020000  // Interrupt 49 active
+#define NVIC_ACTIVE1_INT50      0x00040000  // Interrupt 50 active
+#define NVIC_ACTIVE1_INT51      0x00080000  // Interrupt 51 active
+#define NVIC_ACTIVE1_INT52      0x00100000  // Interrupt 52 active
+#define NVIC_ACTIVE1_INT53      0x00200000  // Interrupt 53 active
+#define NVIC_ACTIVE1_INT54      0x00400000  // Interrupt 54 active
+#define NVIC_ACTIVE1_INT55      0x00800000  // Interrupt 55 active
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_PRI0 register.
 //
 //*****************************************************************************
-#define NVIC_PRI0_INT3_M        0xFF000000  // Interrupt 3 priority mask
-#define NVIC_PRI0_INT2_M        0x00FF0000  // Interrupt 2 priority mask
-#define NVIC_PRI0_INT1_M        0x0000FF00  // Interrupt 1 priority mask
-#define NVIC_PRI0_INT0_M        0x000000FF  // Interrupt 0 priority mask
-#define NVIC_PRI0_INT3_S        24
-#define NVIC_PRI0_INT2_S        16
-#define NVIC_PRI0_INT1_S        8
-#define NVIC_PRI0_INT0_S        0
+#define NVIC_PRI0_INT3_M        0xE0000000  // Interrupt 3 Priority Mask
+#define NVIC_PRI0_INT2_M        0x00E00000  // Interrupt 2 Priority Mask
+#define NVIC_PRI0_INT1_M        0x0000E000  // Interrupt 1 Priority Mask
+#define NVIC_PRI0_INT0_M        0x000000E0  // Interrupt 0 Priority Mask
+#define NVIC_PRI0_INT3_S        29
+#define NVIC_PRI0_INT2_S        21
+#define NVIC_PRI0_INT1_S        13
+#define NVIC_PRI0_INT0_S        5
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_PRI1 register.
 //
 //*****************************************************************************
-#define NVIC_PRI1_INT7_M        0xFF000000  // Interrupt 7 priority mask
-#define NVIC_PRI1_INT6_M        0x00FF0000  // Interrupt 6 priority mask
-#define NVIC_PRI1_INT5_M        0x0000FF00  // Interrupt 5 priority mask
-#define NVIC_PRI1_INT4_M        0x000000FF  // Interrupt 4 priority mask
-#define NVIC_PRI1_INT7_S        24
-#define NVIC_PRI1_INT6_S        16
-#define NVIC_PRI1_INT5_S        8
-#define NVIC_PRI1_INT4_S        0
+#define NVIC_PRI1_INT7_M        0xE0000000  // Interrupt 7 Priority Mask
+#define NVIC_PRI1_INT6_M        0x00E00000  // Interrupt 6 Priority Mask
+#define NVIC_PRI1_INT5_M        0x0000E000  // Interrupt 5 Priority Mask
+#define NVIC_PRI1_INT4_M        0x000000E0  // Interrupt 4 Priority Mask
+#define NVIC_PRI1_INT7_S        29
+#define NVIC_PRI1_INT6_S        21
+#define NVIC_PRI1_INT5_S        13
+#define NVIC_PRI1_INT4_S        5
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_PRI2 register.
 //
 //*****************************************************************************
-#define NVIC_PRI2_INT11_M       0xFF000000  // Interrupt 11 priority mask
-#define NVIC_PRI2_INT10_M       0x00FF0000  // Interrupt 10 priority mask
-#define NVIC_PRI2_INT9_M        0x0000FF00  // Interrupt 9 priority mask
-#define NVIC_PRI2_INT8_M        0x000000FF  // Interrupt 8 priority mask
-#define NVIC_PRI2_INT11_S       24
-#define NVIC_PRI2_INT10_S       16
-#define NVIC_PRI2_INT9_S        8
-#define NVIC_PRI2_INT8_S        0
+#define NVIC_PRI2_INT11_M       0xE0000000  // Interrupt 11 Priority Mask
+#define NVIC_PRI2_INT10_M       0x00E00000  // Interrupt 10 Priority Mask
+#define NVIC_PRI2_INT9_M        0x0000E000  // Interrupt 9 Priority Mask
+#define NVIC_PRI2_INT8_M        0x000000E0  // Interrupt 8 Priority Mask
+#define NVIC_PRI2_INT11_S       29
+#define NVIC_PRI2_INT10_S       21
+#define NVIC_PRI2_INT9_S        13
+#define NVIC_PRI2_INT8_S        5
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_PRI3 register.
 //
 //*****************************************************************************
-#define NVIC_PRI3_INT15_M       0xFF000000  // Interrupt 15 priority mask
-#define NVIC_PRI3_INT14_M       0x00FF0000  // Interrupt 14 priority mask
-#define NVIC_PRI3_INT13_M       0x0000FF00  // Interrupt 13 priority mask
-#define NVIC_PRI3_INT12_M       0x000000FF  // Interrupt 12 priority mask
-#define NVIC_PRI3_INT15_S       24
-#define NVIC_PRI3_INT14_S       16
-#define NVIC_PRI3_INT13_S       8
-#define NVIC_PRI3_INT12_S       0
+#define NVIC_PRI3_INT15_M       0xE0000000  // Interrupt 15 Priority Mask
+#define NVIC_PRI3_INT14_M       0x00E00000  // Interrupt 14 Priority Mask
+#define NVIC_PRI3_INT13_M       0x0000E000  // Interrupt 13 Priority Mask
+#define NVIC_PRI3_INT12_M       0x000000E0  // Interrupt 12 Priority Mask
+#define NVIC_PRI3_INT15_S       29
+#define NVIC_PRI3_INT14_S       21
+#define NVIC_PRI3_INT13_S       13
+#define NVIC_PRI3_INT12_S       5
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_PRI4 register.
 //
 //*****************************************************************************
-#define NVIC_PRI4_INT19_M       0xFF000000  // Interrupt 19 priority mask
-#define NVIC_PRI4_INT18_M       0x00FF0000  // Interrupt 18 priority mask
-#define NVIC_PRI4_INT17_M       0x0000FF00  // Interrupt 17 priority mask
-#define NVIC_PRI4_INT16_M       0x000000FF  // Interrupt 16 priority mask
-#define NVIC_PRI4_INT19_S       24
-#define NVIC_PRI4_INT18_S       16
-#define NVIC_PRI4_INT17_S       8
-#define NVIC_PRI4_INT16_S       0
+#define NVIC_PRI4_INT19_M       0xE0000000  // Interrupt 19 Priority Mask
+#define NVIC_PRI4_INT18_M       0x00E00000  // Interrupt 18 Priority Mask
+#define NVIC_PRI4_INT17_M       0x0000E000  // Interrupt 17 Priority Mask
+#define NVIC_PRI4_INT16_M       0x000000E0  // Interrupt 16 Priority Mask
+#define NVIC_PRI4_INT19_S       29
+#define NVIC_PRI4_INT18_S       21
+#define NVIC_PRI4_INT17_S       13
+#define NVIC_PRI4_INT16_S       5
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_PRI5 register.
 //
 //*****************************************************************************
-#define NVIC_PRI5_INT23_M       0xFF000000  // Interrupt 23 priority mask
-#define NVIC_PRI5_INT22_M       0x00FF0000  // Interrupt 22 priority mask
-#define NVIC_PRI5_INT21_M       0x0000FF00  // Interrupt 21 priority mask
-#define NVIC_PRI5_INT20_M       0x000000FF  // Interrupt 20 priority mask
-#define NVIC_PRI5_INT23_S       24
-#define NVIC_PRI5_INT22_S       16
-#define NVIC_PRI5_INT21_S       8
-#define NVIC_PRI5_INT20_S       0
+#define NVIC_PRI5_INT23_M       0xE0000000  // Interrupt 23 Priority Mask
+#define NVIC_PRI5_INT22_M       0x00E00000  // Interrupt 22 Priority Mask
+#define NVIC_PRI5_INT21_M       0x0000E000  // Interrupt 21 Priority Mask
+#define NVIC_PRI5_INT20_M       0x000000E0  // Interrupt 20 Priority Mask
+#define NVIC_PRI5_INT23_S       29
+#define NVIC_PRI5_INT22_S       21
+#define NVIC_PRI5_INT21_S       13
+#define NVIC_PRI5_INT20_S       5
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_PRI6 register.
 //
 //*****************************************************************************
-#define NVIC_PRI6_INT27_M       0xFF000000  // Interrupt 27 priority mask
-#define NVIC_PRI6_INT26_M       0x00FF0000  // Interrupt 26 priority mask
-#define NVIC_PRI6_INT25_M       0x0000FF00  // Interrupt 25 priority mask
-#define NVIC_PRI6_INT24_M       0x000000FF  // Interrupt 24 priority mask
-#define NVIC_PRI6_INT27_S       24
-#define NVIC_PRI6_INT26_S       16
-#define NVIC_PRI6_INT25_S       8
-#define NVIC_PRI6_INT24_S       0
+#define NVIC_PRI6_INT27_M       0xE0000000  // Interrupt 27 Priority Mask
+#define NVIC_PRI6_INT26_M       0x00E00000  // Interrupt 26 Priority Mask
+#define NVIC_PRI6_INT25_M       0x0000E000  // Interrupt 25 Priority Mask
+#define NVIC_PRI6_INT24_M       0x000000E0  // Interrupt 24 Priority Mask
+#define NVIC_PRI6_INT27_S       29
+#define NVIC_PRI6_INT26_S       21
+#define NVIC_PRI6_INT25_S       13
+#define NVIC_PRI6_INT24_S       5
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_PRI7 register.
 //
 //*****************************************************************************
-#define NVIC_PRI7_INT31_M       0xFF000000  // Interrupt 31 priority mask
-#define NVIC_PRI7_INT30_M       0x00FF0000  // Interrupt 30 priority mask
-#define NVIC_PRI7_INT29_M       0x0000FF00  // Interrupt 29 priority mask
-#define NVIC_PRI7_INT28_M       0x000000FF  // Interrupt 28 priority mask
-#define NVIC_PRI7_INT31_S       24
-#define NVIC_PRI7_INT30_S       16
-#define NVIC_PRI7_INT29_S       8
-#define NVIC_PRI7_INT28_S       0
+#define NVIC_PRI7_INT31_M       0xE0000000  // Interrupt 31 Priority Mask
+#define NVIC_PRI7_INT30_M       0x00E00000  // Interrupt 30 Priority Mask
+#define NVIC_PRI7_INT29_M       0x0000E000  // Interrupt 29 Priority Mask
+#define NVIC_PRI7_INT28_M       0x000000E0  // Interrupt 28 Priority Mask
+#define NVIC_PRI7_INT31_S       29
+#define NVIC_PRI7_INT30_S       21
+#define NVIC_PRI7_INT29_S       13
+#define NVIC_PRI7_INT28_S       5
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_PRI8 register.
 //
 //*****************************************************************************
-#define NVIC_PRI8_INT35_M       0xFF000000  // Interrupt 35 priority mask
-#define NVIC_PRI8_INT34_M       0x00FF0000  // Interrupt 34 priority mask
-#define NVIC_PRI8_INT33_M       0x0000FF00  // Interrupt 33 priority mask
-#define NVIC_PRI8_INT32_M       0x000000FF  // Interrupt 32 priority mask
-#define NVIC_PRI8_INT35_S       24
-#define NVIC_PRI8_INT34_S       16
-#define NVIC_PRI8_INT33_S       8
-#define NVIC_PRI8_INT32_S       0
+#define NVIC_PRI8_INT35_M       0xE0000000  // Interrupt 35 Priority Mask
+#define NVIC_PRI8_INT34_M       0x00E00000  // Interrupt 34 Priority Mask
+#define NVIC_PRI8_INT33_M       0x0000E000  // Interrupt 33 Priority Mask
+#define NVIC_PRI8_INT32_M       0x000000E0  // Interrupt 32 Priority Mask
+#define NVIC_PRI8_INT35_S       29
+#define NVIC_PRI8_INT34_S       21
+#define NVIC_PRI8_INT33_S       13
+#define NVIC_PRI8_INT32_S       5
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_PRI9 register.
 //
 //*****************************************************************************
-#define NVIC_PRI9_INT39_M       0xFF000000  // Interrupt 39 priority mask
-#define NVIC_PRI9_INT38_M       0x00FF0000  // Interrupt 38 priority mask
-#define NVIC_PRI9_INT37_M       0x0000FF00  // Interrupt 37 priority mask
-#define NVIC_PRI9_INT36_M       0x000000FF  // Interrupt 36 priority mask
-#define NVIC_PRI9_INT39_S       24
-#define NVIC_PRI9_INT38_S       16
-#define NVIC_PRI9_INT37_S       8
-#define NVIC_PRI9_INT36_S       0
+#define NVIC_PRI9_INT39_M       0xE0000000  // Interrupt 39 Priority Mask
+#define NVIC_PRI9_INT38_M       0x00E00000  // Interrupt 38 Priority Mask
+#define NVIC_PRI9_INT37_M       0x0000E000  // Interrupt 37 Priority Mask
+#define NVIC_PRI9_INT36_M       0x000000E0  // Interrupt 36 Priority Mask
+#define NVIC_PRI9_INT39_S       29
+#define NVIC_PRI9_INT38_S       21
+#define NVIC_PRI9_INT37_S       13
+#define NVIC_PRI9_INT36_S       5
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_PRI10 register.
 //
 //*****************************************************************************
-#define NVIC_PRI10_INT43_M      0xFF000000  // Interrupt 43 priority mask
-#define NVIC_PRI10_INT42_M      0x00FF0000  // Interrupt 42 priority mask
-#define NVIC_PRI10_INT41_M      0x0000FF00  // Interrupt 41 priority mask
-#define NVIC_PRI10_INT40_M      0x000000FF  // Interrupt 40 priority mask
-#define NVIC_PRI10_INT43_S      24
-#define NVIC_PRI10_INT42_S      16
-#define NVIC_PRI10_INT41_S      8
-#define NVIC_PRI10_INT40_S      0
+#define NVIC_PRI10_INT43_M      0xE0000000  // Interrupt 43 Priority Mask
+#define NVIC_PRI10_INT42_M      0x00E00000  // Interrupt 42 Priority Mask
+#define NVIC_PRI10_INT41_M      0x0000E000  // Interrupt 41 Priority Mask
+#define NVIC_PRI10_INT40_M      0x000000E0  // Interrupt 40 Priority Mask
+#define NVIC_PRI10_INT43_S      29
+#define NVIC_PRI10_INT42_S      21
+#define NVIC_PRI10_INT41_S      13
+#define NVIC_PRI10_INT40_S      5
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_CPUID register.
 //
 //*****************************************************************************
-#define NVIC_CPUID_IMP_M        0xFF000000  // Implementer
-#define NVIC_CPUID_VAR_M        0x00F00000  // Variant
-#define NVIC_CPUID_PARTNO_M     0x0000FFF0  // Processor part number
-#define NVIC_CPUID_REV_M        0x0000000F  // Revision
+#define NVIC_CPUID_IMP_M        0xFF000000  // Implementer Code
+#define NVIC_CPUID_IMP_ARM      0x41000000  // ARM
+#define NVIC_CPUID_VAR_M        0x00F00000  // Variant Number
+#define NVIC_CPUID_CON_M        0x000F0000  // Constant
+#define NVIC_CPUID_PARTNO_M     0x0000FFF0  // Part Number
+#define NVIC_CPUID_PARTNO_CM3   0x0000C230  // Cortex-M3 processor
+#define NVIC_CPUID_REV_M        0x0000000F  // Revision Number
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_INT_CTRL register.
 //
 //*****************************************************************************
-#define NVIC_INT_CTRL_NMI_SET   0x80000000  // Pend a NMI
-#define NVIC_INT_CTRL_PEND_SV   0x10000000  // Pend a PendSV
-#define NVIC_INT_CTRL_UNPEND_SV 0x08000000  // Unpend a PendSV
-#define NVIC_INT_CTRL_ISR_PRE   0x00800000  // Debug interrupt handling
-#define NVIC_INT_CTRL_ISR_PEND  0x00400000  // Debug interrupt pending
-#define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000  // Highest pending exception
-#define NVIC_INT_CTRL_RET_BASE  0x00000800  // Return to base
-#define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF  // Current active exception
-#define NVIC_INT_CTRL_VEC_PEN_S 12
+#define NVIC_INT_CTRL_NMI_SET   0x80000000  // NMI Set Pending
+#define NVIC_INT_CTRL_PEND_SV   0x10000000  // PendSV Set Pending
+#define NVIC_INT_CTRL_UNPEND_SV 0x08000000  // PendSV Clear Pending
+#define NVIC_INT_CTRL_PENDSTSET 0x04000000  // SysTick Set Pending
+#define NVIC_INT_CTRL_PENDSTCLR 0x02000000  // SysTick Clear Pending
+#define NVIC_INT_CTRL_ISR_PRE   0x00800000  // Debug Interrupt Handling
+#define NVIC_INT_CTRL_ISR_PEND  0x00400000  // Interrupt Pending
+#define NVIC_INT_CTRL_VEC_PEN_M 0x0003F000  // Interrupt Pending Vector Number
+#define NVIC_INT_CTRL_VEC_PEN_NMI \
+                                0x00002000  // NMI
+#define NVIC_INT_CTRL_VEC_PEN_HARD \
+                                0x00003000  // Hard fault
+#define NVIC_INT_CTRL_VEC_PEN_MEM \
+                                0x00004000  // Memory management fault
+#define NVIC_INT_CTRL_VEC_PEN_BUS \
+                                0x00005000  // Bus fault
+#define NVIC_INT_CTRL_VEC_PEN_USG \
+                                0x00006000  // Usage fault
+#define NVIC_INT_CTRL_VEC_PEN_SVC \
+                                0x0000B000  // SVCall
+#define NVIC_INT_CTRL_VEC_PEN_PNDSV \
+                                0x0000E000  // PendSV
+#define NVIC_INT_CTRL_VEC_PEN_TICK \
+                                0x0000F000  // SysTick
+#define NVIC_INT_CTRL_RET_BASE  0x00000800  // Return to Base
+#define NVIC_INT_CTRL_VEC_ACT_M 0x0000003F  // Interrupt Pending Vector Number
 #define NVIC_INT_CTRL_VEC_ACT_S 0
 
 //*****************************************************************************
@@ -4531,8 +4554,8 @@
 // The following are defines for the bit fields in the NVIC_VTABLE register.
 //
 //*****************************************************************************
-#define NVIC_VTABLE_BASE        0x20000000  // Vector table base
-#define NVIC_VTABLE_OFFSET_M    0x1FFFFF00  // Vector table offset
+#define NVIC_VTABLE_BASE        0x20000000  // Vector Table Base
+#define NVIC_VTABLE_OFFSET_M    0x1FFFFF00  // Vector Table Offset
 #define NVIC_VTABLE_OFFSET_S    8
 
 //*****************************************************************************
@@ -4540,77 +4563,76 @@
 // The following are defines for the bit fields in the NVIC_APINT register.
 //
 //*****************************************************************************
-#define NVIC_APINT_VECTKEY_M    0xFFFF0000  // Vector key mask
+#define NVIC_APINT_VECTKEY_M    0xFFFF0000  // Register Key
 #define NVIC_APINT_VECTKEY      0x05FA0000  // Vector key
-#define NVIC_APINT_ENDIANESS    0x00008000  // Data endianess
-#define NVIC_APINT_PRIGROUP_M   0x00000700  // Priority group
-#define NVIC_APINT_PRIGROUP_0_8 0x00000700  // Priority group 0.8 split
-#define NVIC_APINT_PRIGROUP_1_7 0x00000600  // Priority group 1.7 split
-#define NVIC_APINT_PRIGROUP_2_6 0x00000500  // Priority group 2.6 split
-#define NVIC_APINT_PRIGROUP_3_5 0x00000400  // Priority group 3.5 split
-#define NVIC_APINT_PRIGROUP_4_4 0x00000300  // Priority group 4.4 split
-#define NVIC_APINT_PRIGROUP_5_3 0x00000200  // Priority group 5.3 split
-#define NVIC_APINT_PRIGROUP_6_2 0x00000100  // Priority group 6.2 split
-#define NVIC_APINT_SYSRESETREQ  0x00000004  // System reset request
-#define NVIC_APINT_VECT_CLR_ACT 0x00000002  // Clear active NMI/fault info
-#define NVIC_APINT_VECT_RESET   0x00000001  // System reset
+#define NVIC_APINT_ENDIANESS    0x00008000  // Data Endianess
+#define NVIC_APINT_PRIGROUP_M   0x00000700  // Interrupt Priority Grouping
 #define NVIC_APINT_PRIGROUP_7_1 0x00000000  // Priority group 7.1 split
+#define NVIC_APINT_PRIGROUP_6_2 0x00000100  // Priority group 6.2 split
+#define NVIC_APINT_PRIGROUP_5_3 0x00000200  // Priority group 5.3 split
+#define NVIC_APINT_PRIGROUP_4_4 0x00000300  // Priority group 4.4 split
+#define NVIC_APINT_PRIGROUP_3_5 0x00000400  // Priority group 3.5 split
+#define NVIC_APINT_PRIGROUP_2_6 0x00000500  // Priority group 2.6 split
+#define NVIC_APINT_PRIGROUP_1_7 0x00000600  // Priority group 1.7 split
+#define NVIC_APINT_PRIGROUP_0_8 0x00000700  // Priority group 0.8 split
+#define NVIC_APINT_SYSRESETREQ  0x00000004  // System Reset Request
+#define NVIC_APINT_VECT_CLR_ACT 0x00000002  // Clear Active NMI / Fault
+#define NVIC_APINT_VECT_RESET   0x00000001  // System Reset
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_SYS_CTRL register.
 //
 //*****************************************************************************
-#define NVIC_SYS_CTRL_SEVONPEND 0x00000010  // Wakeup on pend
-#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004  // Deep sleep enable
-#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002  // Sleep on ISR exit
+#define NVIC_SYS_CTRL_SEVONPEND 0x00000010  // Wake Up on Pending
+#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004  // Deep Sleep Enable
+#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002  // Sleep on ISR Exit
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_CFG_CTRL register.
 //
 //*****************************************************************************
-#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100  // Ignore bus fault in NMI/fault
-#define NVIC_CFG_CTRL_DIV0      0x00000010  // Trap on divide by 0
-#define NVIC_CFG_CTRL_UNALIGNED 0x00000008  // Trap on unaligned access
-#define NVIC_CFG_CTRL_DEEP_PEND 0x00000004  // Allow deep interrupt trigger
-#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002  // Allow main interrupt trigger
-#define NVIC_CFG_CTRL_BASE_THR  0x00000001  // Thread state control
+#define NVIC_CFG_CTRL_STKALIGN  0x00000200  // Stack Alignment on Exception
+                                            // Entry
+#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100  // Ignore Bus Fault in NMI and
+                                            // Fault
+#define NVIC_CFG_CTRL_DIV0      0x00000010  // Trap on Divide by 0
+#define NVIC_CFG_CTRL_UNALIGNED 0x00000008  // Trap on Unaligned Access
+#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002  // Allow Main Interrupt Trigger
+#define NVIC_CFG_CTRL_BASE_THR  0x00000001  // Thread State Control
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_SYS_PRI1 register.
 //
 //*****************************************************************************
-#define NVIC_SYS_PRI1_RES_M     0xFF000000  // Priority of reserved handler
-#define NVIC_SYS_PRI1_USAGE_M   0x00FF0000  // Priority of usage fault handler
-#define NVIC_SYS_PRI1_BUS_M     0x0000FF00  // Priority of bus fault handler
-#define NVIC_SYS_PRI1_MEM_M     0x000000FF  // Priority of mem manage handler
-#define NVIC_SYS_PRI1_USAGE_S   16
-#define NVIC_SYS_PRI1_BUS_S     8
-#define NVIC_SYS_PRI1_MEM_S     0
+#define NVIC_SYS_PRI1_USAGE_M   0x00E00000  // Usage Fault Priority
+#define NVIC_SYS_PRI1_BUS_M     0x0000E000  // Bus Fault Priority
+#define NVIC_SYS_PRI1_MEM_M     0x000000E0  // Memory Management Fault Priority
+#define NVIC_SYS_PRI1_USAGE_S   21
+#define NVIC_SYS_PRI1_BUS_S     13
+#define NVIC_SYS_PRI1_MEM_S     5
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_SYS_PRI2 register.
 //
 //*****************************************************************************
-#define NVIC_SYS_PRI2_SVC_M     0xFF000000  // Priority of SVCall handler
-#define NVIC_SYS_PRI2_RES_M     0x00FFFFFF  // Priority of reserved handlers
-#define NVIC_SYS_PRI2_SVC_S     24
+#define NVIC_SYS_PRI2_SVC_M     0xE0000000  // SVCall Priority
+#define NVIC_SYS_PRI2_SVC_S     29
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_SYS_PRI3 register.
 //
 //*****************************************************************************
-#define NVIC_SYS_PRI3_TICK_M    0xFF000000  // Priority of Sys Tick handler
-#define NVIC_SYS_PRI3_PENDSV_M  0x00FF0000  // Priority of PendSV handler
-#define NVIC_SYS_PRI3_RES_M     0x0000FF00  // Priority of reserved handler
-#define NVIC_SYS_PRI3_DEBUG_M   0x000000FF  // Priority of debug handler
-#define NVIC_SYS_PRI3_TICK_S    24
-#define NVIC_SYS_PRI3_PENDSV_S  16
-#define NVIC_SYS_PRI3_DEBUG_S   0
+#define NVIC_SYS_PRI3_TICK_M    0xE0000000  // SysTick Exception Priority
+#define NVIC_SYS_PRI3_PENDSV_M  0x00E00000  // PendSV Priority
+#define NVIC_SYS_PRI3_DEBUG_M   0x000000E0  // Debug Priority
+#define NVIC_SYS_PRI3_TICK_S    29
+#define NVIC_SYS_PRI3_PENDSV_S  21
+#define NVIC_SYS_PRI3_DEBUG_S   5
 
 //*****************************************************************************
 //
@@ -4618,18 +4640,21 @@
 // register.
 //
 //*****************************************************************************
-#define NVIC_SYS_HND_CTRL_USAGE 0x00040000  // Usage fault enable
-#define NVIC_SYS_HND_CTRL_BUS   0x00020000  // Bus fault enable
-#define NVIC_SYS_HND_CTRL_MEM   0x00010000  // Mem manage fault enable
-#define NVIC_SYS_HND_CTRL_SVC   0x00008000  // SVCall is pended
-#define NVIC_SYS_HND_CTRL_BUSP  0x00004000  // Bus fault is pended
-#define NVIC_SYS_HND_CTRL_TICK  0x00000800  // Sys tick is active
-#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400  // PendSV is active
-#define NVIC_SYS_HND_CTRL_MON   0x00000100  // Monitor is active
-#define NVIC_SYS_HND_CTRL_SVCA  0x00000080  // SVCall is active
-#define NVIC_SYS_HND_CTRL_USGA  0x00000008  // Usage fault is active
-#define NVIC_SYS_HND_CTRL_BUSA  0x00000002  // Bus fault is active
-#define NVIC_SYS_HND_CTRL_MEMA  0x00000001  // Mem manage is active
+#define NVIC_SYS_HND_CTRL_USAGE 0x00040000  // Usage Fault Enable
+#define NVIC_SYS_HND_CTRL_BUS   0x00020000  // Bus Fault Enable
+#define NVIC_SYS_HND_CTRL_MEM   0x00010000  // Memory Management Fault Enable
+#define NVIC_SYS_HND_CTRL_SVC   0x00008000  // SVC Call Pending
+#define NVIC_SYS_HND_CTRL_BUSP  0x00004000  // Bus Fault Pending
+#define NVIC_SYS_HND_CTRL_MEMP  0x00002000  // Memory Management Fault Pending
+#define NVIC_SYS_HND_CTRL_USAGEP \
+                                0x00001000  // Usage Fault Pending
+#define NVIC_SYS_HND_CTRL_TICK  0x00000800  // SysTick Exception Active
+#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400  // PendSV Exception Active
+#define NVIC_SYS_HND_CTRL_MON   0x00000100  // Debug Monitor Active
+#define NVIC_SYS_HND_CTRL_SVCA  0x00000080  // SVC Call Active
+#define NVIC_SYS_HND_CTRL_USGA  0x00000008  // Usage Fault Active
+#define NVIC_SYS_HND_CTRL_BUSA  0x00000002  // Bus Fault Active
+#define NVIC_SYS_HND_CTRL_MEMA  0x00000001  // Memory Management Fault Active
 
 //*****************************************************************************
 //
@@ -4637,23 +4662,25 @@
 // register.
 //
 //*****************************************************************************
-#define NVIC_FAULT_STAT_DIV0    0x02000000  // Divide by zero fault
-#define NVIC_FAULT_STAT_UNALIGN 0x01000000  // Unaligned access fault
-#define NVIC_FAULT_STAT_NOCP    0x00080000  // No coprocessor fault
-#define NVIC_FAULT_STAT_INVPC   0x00040000  // Invalid PC fault
-#define NVIC_FAULT_STAT_INVSTAT 0x00020000  // Invalid state fault
-#define NVIC_FAULT_STAT_UNDEF   0x00010000  // Undefined instruction fault
-#define NVIC_FAULT_STAT_BFARV   0x00008000  // BFAR is valid
-#define NVIC_FAULT_STAT_BSTKE   0x00001000  // Stack bus fault
-#define NVIC_FAULT_STAT_BUSTKE  0x00000800  // Unstack bus fault
-#define NVIC_FAULT_STAT_IMPRE   0x00000400  // Imprecise data bus error
-#define NVIC_FAULT_STAT_PRECISE 0x00000200  // Precise data bus error
-#define NVIC_FAULT_STAT_IBUS    0x00000100  // Instruction bus fault
-#define NVIC_FAULT_STAT_MMARV   0x00000080  // MMAR is valid
-#define NVIC_FAULT_STAT_MSTKE   0x00000010  // Stack access violation
-#define NVIC_FAULT_STAT_MUSTKE  0x00000008  // Unstack access violation
-#define NVIC_FAULT_STAT_DERR    0x00000002  // Data access violation
-#define NVIC_FAULT_STAT_IERR    0x00000001  // Instruction access violation
+#define NVIC_FAULT_STAT_DIV0    0x02000000  // Divide-by-Zero Usage Fault
+#define NVIC_FAULT_STAT_UNALIGN 0x01000000  // Unaligned Access Usage Fault
+#define NVIC_FAULT_STAT_NOCP    0x00080000  // No Coprocessor Usage Fault
+#define NVIC_FAULT_STAT_INVPC   0x00040000  // Invalid PC Load Usage Fault
+#define NVIC_FAULT_STAT_INVSTAT 0x00020000  // Invalid State Usage Fault
+#define NVIC_FAULT_STAT_UNDEF   0x00010000  // Undefined Instruction Usage
+                                            // Fault
+#define NVIC_FAULT_STAT_BFARV   0x00008000  // Bus Fault Address Register Valid
+#define NVIC_FAULT_STAT_BSTKE   0x00001000  // Stack Bus Fault
+#define NVIC_FAULT_STAT_BUSTKE  0x00000800  // Unstack Bus Fault
+#define NVIC_FAULT_STAT_IMPRE   0x00000400  // Imprecise Data Bus Error
+#define NVIC_FAULT_STAT_PRECISE 0x00000200  // Precise Data Bus Error
+#define NVIC_FAULT_STAT_IBUS    0x00000100  // Instruction Bus Error
+#define NVIC_FAULT_STAT_MMARV   0x00000080  // Memory Management Fault Address
+                                            // Register Valid
+#define NVIC_FAULT_STAT_MSTKE   0x00000010  // Stack Access Violation
+#define NVIC_FAULT_STAT_MUSTKE  0x00000008  // Unstack Access Violation
+#define NVIC_FAULT_STAT_DERR    0x00000002  // Data Access Violation
+#define NVIC_FAULT_STAT_IERR    0x00000001  // Instruction Access Violation
 
 //*****************************************************************************
 //
@@ -4661,9 +4688,9 @@
 // register.
 //
 //*****************************************************************************
-#define NVIC_HFAULT_STAT_DBG    0x80000000  // Debug event
-#define NVIC_HFAULT_STAT_FORCED 0x40000000  // Cannot execute fault handler
-#define NVIC_HFAULT_STAT_VECT   0x00000002  // Vector table read fault
+#define NVIC_HFAULT_STAT_DBG    0x80000000  // Debug Event
+#define NVIC_HFAULT_STAT_FORCED 0x40000000  // Forced Hard Fault
+#define NVIC_HFAULT_STAT_VECT   0x00000002  // Vector Table Read Fault
 
 //*****************************************************************************
 //
@@ -4682,7 +4709,7 @@
 // The following are defines for the bit fields in the NVIC_MM_ADDR register.
 //
 //*****************************************************************************
-#define NVIC_MM_ADDR_M          0xFFFFFFFF  // Data fault address
+#define NVIC_MM_ADDR_M          0xFFFFFFFF  // Fault Address
 #define NVIC_MM_ADDR_S          0
 
 //*****************************************************************************
@@ -4691,7 +4718,7 @@
 // register.
 //
 //*****************************************************************************
-#define NVIC_FAULT_ADDR_M       0xFFFFFFFF  // Data bus fault address
+#define NVIC_FAULT_ADDR_M       0xFFFFFFFF  // Fault Address
 #define NVIC_FAULT_ADDR_S       0
 
 //*****************************************************************************
@@ -4699,9 +4726,9 @@
 // The following are defines for the bit fields in the NVIC_MPU_TYPE register.
 //
 //*****************************************************************************
-#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000  // Number of I regions
-#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00  // Number of D regions
-#define NVIC_MPU_TYPE_SEPARATE  0x00000001  // Separate or unified MPU
+#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000  // Number of I Regions
+#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00  // Number of D Regions
+#define NVIC_MPU_TYPE_SEPARATE  0x00000001  // Separate or Unified MPU
 #define NVIC_MPU_TYPE_IREGION_S 16
 #define NVIC_MPU_TYPE_DREGION_S 8
 
@@ -4710,9 +4737,9 @@
 // The following are defines for the bit fields in the NVIC_MPU_CTRL register.
 //
 //*****************************************************************************
-#define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004  // MPU default region in priv mode
-#define NVIC_MPU_CTRL_HFNMIENA  0x00000002  // MPU enabled during faults
-#define NVIC_MPU_CTRL_ENABLE    0x00000001  // MPU enable
+#define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004  // MPU Default Region
+#define NVIC_MPU_CTRL_HFNMIENA  0x00000002  // MPU Enabled During Faults
+#define NVIC_MPU_CTRL_ENABLE    0x00000001  // MPU Enable
 
 //*****************************************************************************
 //
@@ -4720,7 +4747,7 @@
 // register.
 //
 //*****************************************************************************
-#define NVIC_MPU_NUMBER_M       0x000000FF  // MPU region to access
+#define NVIC_MPU_NUMBER_M       0x00000007  // MPU Region to Access
 #define NVIC_MPU_NUMBER_S       0
 
 //*****************************************************************************
@@ -4728,10 +4755,10 @@
 // The following are defines for the bit fields in the NVIC_MPU_BASE register.
 //
 //*****************************************************************************
-#define NVIC_MPU_BASE_ADDR_M    0xFFFFFFE0  // Base address mask
-#define NVIC_MPU_BASE_VALID     0x00000010  // Region number valid
-#define NVIC_MPU_BASE_REGION_M  0x0000000F  // Region number
-#define NVIC_MPU_BASE_ADDR_S    8
+#define NVIC_MPU_BASE_ADDR_M    0xFFFFFFE0  // Base Address Mask
+#define NVIC_MPU_BASE_VALID     0x00000010  // Region Number Valid
+#define NVIC_MPU_BASE_REGION_M  0x00000007  // Region Number
+#define NVIC_MPU_BASE_ADDR_S    5
 #define NVIC_MPU_BASE_REGION_S  0
 
 //*****************************************************************************
@@ -4740,19 +4767,19 @@
 //
 //*****************************************************************************
 #define NVIC_MPU_ATTR_M         0xFFFF0000  // Attributes
+#define NVIC_MPU_ATTR_XN        0x10000000  // Instruction Access Disable
+#define NVIC_MPU_ATTR_AP_M      0x07000000  // Access Privilege
 #define NVIC_MPU_ATTR_AP_NO_NO  0x00000000  // prv: no access, usr: no access
-#define NVIC_MPU_ATTR_BUFFRABLE 0x00010000  // Bufferable
-#define NVIC_MPU_ATTR_CACHEABLE 0x00020000  // Cacheable
-#define NVIC_MPU_ATTR_SHAREABLE 0x00040000  // Shareable
-#define NVIC_MPU_ATTR_TEX_M     0x00380000  // Type extension mask
 #define NVIC_MPU_ATTR_AP_RW_NO  0x01000000  // prv: rw, usr: none
 #define NVIC_MPU_ATTR_AP_RW_RO  0x02000000  // prv: rw, usr: read-only
 #define NVIC_MPU_ATTR_AP_RW_RW  0x03000000  // prv: rw, usr: rw
 #define NVIC_MPU_ATTR_AP_RO_NO  0x05000000  // prv: ro, usr: none
 #define NVIC_MPU_ATTR_AP_RO_RO  0x06000000  // prv: ro, usr: ro
-#define NVIC_MPU_ATTR_AP_M      0x07000000  // Access permissions mask
-#define NVIC_MPU_ATTR_XN        0x10000000  // Execute disable
-#define NVIC_MPU_ATTR_SRD_M     0x0000FF00  // Sub-region disable mask
+#define NVIC_MPU_ATTR_TEX_M     0x00380000  // Type Extension Mask
+#define NVIC_MPU_ATTR_SHAREABLE 0x00040000  // Shareable
+#define NVIC_MPU_ATTR_CACHEABLE 0x00020000  // Cacheable
+#define NVIC_MPU_ATTR_BUFFRABLE 0x00010000  // Bufferable
+#define NVIC_MPU_ATTR_SRD_M     0x0000FF00  // Subregion Disable Bits
 #define NVIC_MPU_ATTR_SRD_0     0x00000100  // Sub-region 0 disable
 #define NVIC_MPU_ATTR_SRD_1     0x00000200  // Sub-region 1 disable
 #define NVIC_MPU_ATTR_SRD_2     0x00000400  // Sub-region 2 disable
@@ -4761,7 +4788,7 @@
 #define NVIC_MPU_ATTR_SRD_5     0x00002000  // Sub-region 5 disable
 #define NVIC_MPU_ATTR_SRD_6     0x00004000  // Sub-region 6 disable
 #define NVIC_MPU_ATTR_SRD_7     0x00008000  // Sub-region 7 disable
-#define NVIC_MPU_ATTR_SIZE_M    0x0000003E  // Region size mask
+#define NVIC_MPU_ATTR_SIZE_M    0x0000003E  // Region Size Mask
 #define NVIC_MPU_ATTR_SIZE_32B  0x00000008  // Region size 32 bytes
 #define NVIC_MPU_ATTR_SIZE_64B  0x0000000A  // Region size 64 bytes
 #define NVIC_MPU_ATTR_SIZE_128B 0x0000000C  // Region size 128 bytes
@@ -4790,7 +4817,94 @@
 #define NVIC_MPU_ATTR_SIZE_1G   0x0000003A  // Region size 1 Gbytes
 #define NVIC_MPU_ATTR_SIZE_2G   0x0000003C  // Region size 2 Gbytes
 #define NVIC_MPU_ATTR_SIZE_4G   0x0000003E  // Region size 4 Gbytes
-#define NVIC_MPU_ATTR_ENABLE    0x00000001  // Region enable
+#define NVIC_MPU_ATTR_ENABLE    0x00000001  // Region Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE1 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE1_ADDR_M   0xFFFFFFE0  // Base Address Mask
+#define NVIC_MPU_BASE1_VALID    0x00000010  // Region Number Valid
+#define NVIC_MPU_BASE1_REGION_M 0x00000007  // Region Number
+#define NVIC_MPU_BASE1_ADDR_S   5
+#define NVIC_MPU_BASE1_REGION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR1 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR1_XN       0x10000000  // Instruction Access Disable
+#define NVIC_MPU_ATTR1_AP_M     0x07000000  // Access Privilege
+#define NVIC_MPU_ATTR1_TEX_M    0x00380000  // Type Extension Mask
+#define NVIC_MPU_ATTR1_SHAREABLE \
+                                0x00040000  // Shareable
+#define NVIC_MPU_ATTR1_CACHEABLE \
+                                0x00020000  // Cacheable
+#define NVIC_MPU_ATTR1_BUFFRABLE \
+                                0x00010000  // Bufferable
+#define NVIC_MPU_ATTR1_SRD_M    0x0000FF00  // Subregion Disable Bits
+#define NVIC_MPU_ATTR1_SIZE_M   0x0000003E  // Region Size Mask
+#define NVIC_MPU_ATTR1_ENABLE   0x00000001  // Region Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE2 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE2_ADDR_M   0xFFFFFFE0  // Base Address Mask
+#define NVIC_MPU_BASE2_VALID    0x00000010  // Region Number Valid
+#define NVIC_MPU_BASE2_REGION_M 0x00000007  // Region Number
+#define NVIC_MPU_BASE2_ADDR_S   5
+#define NVIC_MPU_BASE2_REGION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR2 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR2_XN       0x10000000  // Instruction Access Disable
+#define NVIC_MPU_ATTR2_AP_M     0x07000000  // Access Privilege
+#define NVIC_MPU_ATTR2_TEX_M    0x00380000  // Type Extension Mask
+#define NVIC_MPU_ATTR2_SHAREABLE \
+                                0x00040000  // Shareable
+#define NVIC_MPU_ATTR2_CACHEABLE \
+                                0x00020000  // Cacheable
+#define NVIC_MPU_ATTR2_BUFFRABLE \
+                                0x00010000  // Bufferable
+#define NVIC_MPU_ATTR2_SRD_M    0x0000FF00  // Subregion Disable Bits
+#define NVIC_MPU_ATTR2_SIZE_M   0x0000003E  // Region Size Mask
+#define NVIC_MPU_ATTR2_ENABLE   0x00000001  // Region Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE3 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE3_ADDR_M   0xFFFFFFE0  // Base Address Mask
+#define NVIC_MPU_BASE3_VALID    0x00000010  // Region Number Valid
+#define NVIC_MPU_BASE3_REGION_M 0x00000007  // Region Number
+#define NVIC_MPU_BASE3_ADDR_S   5
+#define NVIC_MPU_BASE3_REGION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR3 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR3_XN       0x10000000  // Instruction Access Disable
+#define NVIC_MPU_ATTR3_AP_M     0x07000000  // Access Privilege
+#define NVIC_MPU_ATTR3_TEX_M    0x00380000  // Type Extension Mask
+#define NVIC_MPU_ATTR3_SHAREABLE \
+                                0x00040000  // Shareable
+#define NVIC_MPU_ATTR3_CACHEABLE \
+                                0x00020000  // Cacheable
+#define NVIC_MPU_ATTR3_BUFFRABLE \
+                                0x00010000  // Bufferable
+#define NVIC_MPU_ATTR3_SRD_M    0x0000FF00  // Subregion Disable Bits
+#define NVIC_MPU_ATTR3_SIZE_M   0x0000003E  // Region Size Mask
+#define NVIC_MPU_ATTR3_ENABLE   0x00000001  // Region Enable
 
 //*****************************************************************************
 //
@@ -4822,27 +4936,27 @@
 //*****************************************************************************
 #define NVIC_DBG_XFER_REG_WNR   0x00010000  // Write or not read
 #define NVIC_DBG_XFER_REG_SEL_M 0x0000001F  // Register
-#define NVIC_DBG_XFER_REG_CFBP  0x00000014  // Control/Fault/BasePri/PriMask
-#define NVIC_DBG_XFER_REG_DSP   0x00000013  // Deep SP
-#define NVIC_DBG_XFER_REG_PSP   0x00000012  // Process SP
-#define NVIC_DBG_XFER_REG_MSP   0x00000011  // Main SP
-#define NVIC_DBG_XFER_REG_FLAGS 0x00000010  // xPSR/Flags register
-#define NVIC_DBG_XFER_REG_R15   0x0000000F  // Register R15
-#define NVIC_DBG_XFER_REG_R14   0x0000000E  // Register R14
-#define NVIC_DBG_XFER_REG_R13   0x0000000D  // Register R13
-#define NVIC_DBG_XFER_REG_R12   0x0000000C  // Register R12
-#define NVIC_DBG_XFER_REG_R11   0x0000000B  // Register R11
-#define NVIC_DBG_XFER_REG_R10   0x0000000A  // Register R10
-#define NVIC_DBG_XFER_REG_R9    0x00000009  // Register R9
-#define NVIC_DBG_XFER_REG_R8    0x00000008  // Register R8
-#define NVIC_DBG_XFER_REG_R7    0x00000007  // Register R7
-#define NVIC_DBG_XFER_REG_R6    0x00000006  // Register R6
-#define NVIC_DBG_XFER_REG_R5    0x00000005  // Register R5
-#define NVIC_DBG_XFER_REG_R4    0x00000004  // Register R4
-#define NVIC_DBG_XFER_REG_R3    0x00000003  // Register R3
-#define NVIC_DBG_XFER_REG_R2    0x00000002  // Register R2
-#define NVIC_DBG_XFER_REG_R1    0x00000001  // Register R1
 #define NVIC_DBG_XFER_REG_R0    0x00000000  // Register R0
+#define NVIC_DBG_XFER_REG_R1    0x00000001  // Register R1
+#define NVIC_DBG_XFER_REG_R2    0x00000002  // Register R2
+#define NVIC_DBG_XFER_REG_R3    0x00000003  // Register R3
+#define NVIC_DBG_XFER_REG_R4    0x00000004  // Register R4
+#define NVIC_DBG_XFER_REG_R5    0x00000005  // Register R5
+#define NVIC_DBG_XFER_REG_R6    0x00000006  // Register R6
+#define NVIC_DBG_XFER_REG_R7    0x00000007  // Register R7
+#define NVIC_DBG_XFER_REG_R8    0x00000008  // Register R8
+#define NVIC_DBG_XFER_REG_R9    0x00000009  // Register R9
+#define NVIC_DBG_XFER_REG_R10   0x0000000A  // Register R10
+#define NVIC_DBG_XFER_REG_R11   0x0000000B  // Register R11
+#define NVIC_DBG_XFER_REG_R12   0x0000000C  // Register R12
+#define NVIC_DBG_XFER_REG_R13   0x0000000D  // Register R13
+#define NVIC_DBG_XFER_REG_R14   0x0000000E  // Register R14
+#define NVIC_DBG_XFER_REG_R15   0x0000000F  // Register R15
+#define NVIC_DBG_XFER_REG_FLAGS 0x00000010  // xPSR/Flags register
+#define NVIC_DBG_XFER_REG_MSP   0x00000011  // Main SP
+#define NVIC_DBG_XFER_REG_PSP   0x00000012  // Process SP
+#define NVIC_DBG_XFER_REG_DSP   0x00000013  // Deep SP
+#define NVIC_DBG_XFER_REG_CFBP  0x00000014  // Control/Fault/BasePri/PriMask
 
 //*****************************************************************************
 //
@@ -4874,7 +4988,135 @@
 // The following are defines for the bit fields in the NVIC_SW_TRIG register.
 //
 //*****************************************************************************
-#define NVIC_SW_TRIG_INTID_M    0x000003FF  // Interrupt to trigger
+#define NVIC_SW_TRIG_INTID_M    0x0000003F  // Interrupt ID
 #define NVIC_SW_TRIG_INTID_S    0
 
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// Deprecated defines for the Watchdog
+//
+//*****************************************************************************
+#define WATCHDOG_LOAD_R         (*((volatile unsigned long *)0x40000000))
+#define WATCHDOG_VALUE_R        (*((volatile unsigned long *)0x40000004))
+#define WATCHDOG_CTL_R          (*((volatile unsigned long *)0x40000008))
+#define WATCHDOG_ICR_R          (*((volatile unsigned long *)0x4000000C))
+#define WATCHDOG_RIS_R          (*((volatile unsigned long *)0x40000010))
+#define WATCHDOG_MIS_R          (*((volatile unsigned long *)0x40000014))
+#define WATCHDOG_TEST_R         (*((volatile unsigned long *)0x40000418))
+#define WATCHDOG_LOCK_R         (*((volatile unsigned long *)0x40000C00))
+
+//*****************************************************************************
+//
+// Deprecated defines for the bit fields in the I2C_O_SICR register.
+//
+//*****************************************************************************
+#define I2C_SICR_IC             0x00000001  // Clear Interrupt
+
+//*****************************************************************************
+//
+// Deprecated defines for the bit fields in the I2C_O_SMIS register.
+//
+//*****************************************************************************
+#define I2C_SMIS_MIS            0x00000001  // Masked Interrupt Status
+
+//*****************************************************************************
+//
+// Deprecated defines for the bit fields in the I2C_O_SRIS register.
+//
+//*****************************************************************************
+#define I2C_SRIS_RIS            0x00000001  // Raw Interrupt Status
+
+//*****************************************************************************
+//
+// Deprecated defines for the bit fields in the I2C_O_SIMR register.
+//
+//*****************************************************************************
+#define I2C_SIMR_IM             0x00000001  // Interrupt Mask
+
+//*****************************************************************************
+//
+// Deprecated defines for the bit fields in the the interpretation of the data
+// in the SSFIFOx when the ADC TMLB is enabled. register.
+//
+//*****************************************************************************
+#define ADC_TMLB_CNT_M          0x000003C0  // Continuous Sample Counter
+#define ADC_TMLB_CONT           0x00000020  // Continuation Sample Indicator
+#define ADC_TMLB_DIFF           0x00000010  // Differential Sample Indicator
+#define ADC_TMLB_TS             0x00000008  // Temp Sensor Sample Indicator
+#define ADC_TMLB_MUX_M          0x00000007  // Analog Input Indicator
+#define ADC_TMLB_CNT_S          6           // Sample counter shift
+#define ADC_TMLB_MUX_S          0           // Input channel number shift
+
+//*****************************************************************************
+//
+// Deprecated defines for the ADC register offsets.
+//
+//*****************************************************************************
+#define ADC_ACTSS_R             (*((volatile unsigned long *)0x40038000))
+#define ADC_RIS_R               (*((volatile unsigned long *)0x40038004))
+#define ADC_IM_R                (*((volatile unsigned long *)0x40038008))
+#define ADC_ISC_R               (*((volatile unsigned long *)0x4003800C))
+#define ADC_OSTAT_R             (*((volatile unsigned long *)0x40038010))
+#define ADC_EMUX_R              (*((volatile unsigned long *)0x40038014))
+#define ADC_USTAT_R             (*((volatile unsigned long *)0x40038018))
+#define ADC_SSPRI_R             (*((volatile unsigned long *)0x40038020))
+#define ADC_PSSI_R              (*((volatile unsigned long *)0x40038028))
+#define ADC_SAC_R               (*((volatile unsigned long *)0x40038030))
+#define ADC_SSMUX0_R            (*((volatile unsigned long *)0x40038040))
+#define ADC_SSCTL0_R            (*((volatile unsigned long *)0x40038044))
+#define ADC_SSFIFO0_R           (*((volatile unsigned long *)0x40038048))
+#define ADC_SSFSTAT0_R          (*((volatile unsigned long *)0x4003804C))
+#define ADC_SSMUX1_R            (*((volatile unsigned long *)0x40038060))
+#define ADC_SSCTL1_R            (*((volatile unsigned long *)0x40038064))
+#define ADC_SSFIFO1_R           (*((volatile unsigned long *)0x40038068))
+#define ADC_SSFSTAT1_R          (*((volatile unsigned long *)0x4003806C))
+#define ADC_SSMUX2_R            (*((volatile unsigned long *)0x40038080))
+#define ADC_SSCTL2_R            (*((volatile unsigned long *)0x40038084))
+#define ADC_SSFIFO2_R           (*((volatile unsigned long *)0x40038088))
+#define ADC_SSFSTAT2_R          (*((volatile unsigned long *)0x4003808C))
+#define ADC_SSMUX3_R            (*((volatile unsigned long *)0x400380A0))
+#define ADC_SSCTL3_R            (*((volatile unsigned long *)0x400380A4))
+#define ADC_SSFIFO3_R           (*((volatile unsigned long *)0x400380A8))
+#define ADC_SSFSTAT3_R          (*((volatile unsigned long *)0x400380AC))
+#define ADC_TMLB_R              (*((volatile unsigned long *)0x40038100))
+
+//*****************************************************************************
+//
+// Deprecated defines for the bit fields in the FLASH_FMC register.
+//
+//*****************************************************************************
+#define FLASH_FMC_WRKEY_M       0xFFFF0000  // Flash Memory Write Key
+#define FLASH_FMC_WRKEY_S       16
+
+//*****************************************************************************
+//
+// Deprecated defines for the bit fields in the SYSCTL_DC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC1_WDT          0x00000008  // Watchdog Timer Present
+
+//*****************************************************************************
+//
+// Deprecated defines for the bit fields in the SYSCTL_DID1 register.
+//
+//*****************************************************************************
+#define SYSCTL_DID1_PKG_28SOIC  0x00000000  // SOIC package
+#define SYSCTL_DID1_PKG_48QFP   0x00000008  // QFP package
+
+//*****************************************************************************
+//
+// Deprecated defines for the NVIC register addresses.
+//
+//*****************************************************************************
+#define NVIC_MPU_R              (*((volatile unsigned long *)0xE000ED9C))
+
+#endif
+
 #endif // __LM3S8962_H__
diff --git a/src/platform/lm3s/lm3s9b92.h b/src/platform/lm3s/lm3s9b92.h
index df08a733..aa07189b 100755
--- a/src/platform/lm3s/lm3s9b92.h
+++ b/src/platform/lm3s/lm3s9b92.h
@@ -2,26 +2,23 @@
 //
 // lm3s9b92.h - LM3S9B92 Register Definitions
 //
-// Copyright (c) 2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2009-2011 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4781 of the Stellaris Firmware Development Package.
+// This is part of revision 7611 of the Stellaris Firmware Development Package.
 //
 //*****************************************************************************
 
@@ -30,7 +27,7 @@
 
 //*****************************************************************************
 //
-// Watchdog Timers (WATCHDOG0)
+// Watchdog Timer registers (WATCHDOG0)
 //
 //*****************************************************************************
 #define WATCHDOG0_LOAD_R        (*((volatile unsigned long *)0x40000000))
@@ -44,7 +41,7 @@
 
 //*****************************************************************************
 //
-// Watchdog Timers (WATCHDOG1)
+// Watchdog Timer registers (WATCHDOG1)
 //
 //*****************************************************************************
 #define WATCHDOG1_LOAD_R        (*((volatile unsigned long *)0x40001000))
@@ -58,7 +55,7 @@
 
 //*****************************************************************************
 //
-// General-Purpose Input/Outputs (PORTA)
+// GPIO registers (PORTA)
 //
 //*****************************************************************************
 #define GPIO_PORTA_DATA_BITS_R  ((volatile unsigned long *)0x40004000)
@@ -87,7 +84,7 @@
 
 //*****************************************************************************
 //
-// General-Purpose Input/Outputs (PORTB)
+// GPIO registers (PORTB)
 //
 //*****************************************************************************
 #define GPIO_PORTB_DATA_BITS_R  ((volatile unsigned long *)0x40005000)
@@ -116,7 +113,7 @@
 
 //*****************************************************************************
 //
-// General-Purpose Input/Outputs (PORTC)
+// GPIO registers (PORTC)
 //
 //*****************************************************************************
 #define GPIO_PORTC_DATA_BITS_R  ((volatile unsigned long *)0x40006000)
@@ -145,7 +142,7 @@
 
 //*****************************************************************************
 //
-// General-Purpose Input/Outputs (PORTD)
+// GPIO registers (PORTD)
 //
 //*****************************************************************************
 #define GPIO_PORTD_DATA_BITS_R  ((volatile unsigned long *)0x40007000)
@@ -174,7 +171,7 @@
 
 //*****************************************************************************
 //
-// Synchronous Serial Interface (SSI0)
+// SSI registers (SSI0)
 //
 //*****************************************************************************
 #define SSI0_CR0_R              (*((volatile unsigned long *)0x40008000))
@@ -190,7 +187,7 @@
 
 //*****************************************************************************
 //
-// Synchronous Serial Interface (SSI1)
+// SSI registers (SSI1)
 //
 //*****************************************************************************
 #define SSI1_CR0_R              (*((volatile unsigned long *)0x40009000))
@@ -206,7 +203,7 @@
 
 //*****************************************************************************
 //
-// Universal Asynchronous Receivers/Transmitters (UART0)
+// UART registers (UART0)
 //
 //*****************************************************************************
 #define UART0_DR_R              (*((volatile unsigned long *)0x4000C000))
@@ -230,7 +227,7 @@
 
 //*****************************************************************************
 //
-// Universal Asynchronous Receivers/Transmitters (UART1)
+// UART registers (UART1)
 //
 //*****************************************************************************
 #define UART1_DR_R              (*((volatile unsigned long *)0x4000D000))
@@ -254,7 +251,7 @@
 
 //*****************************************************************************
 //
-// Universal Asynchronous Receivers/Transmitters (UART2)
+// UART registers (UART2)
 //
 //*****************************************************************************
 #define UART2_DR_R              (*((volatile unsigned long *)0x4000E000))
@@ -278,95 +275,63 @@
 
 //*****************************************************************************
 //
-// Inter-Integrated Circuit (MASTER) Interface
+// I2C registers (I2C0 MASTER)
 //
 //*****************************************************************************
 #define I2C0_MASTER_MSA_R       (*((volatile unsigned long *)0x40020000))
-#define I2C0_MASTER_SOAR_R      (*((volatile unsigned long *)0x40020000))
-#define I2C0_MASTER_SCSR_R      (*((volatile unsigned long *)0x40020004))
 #define I2C0_MASTER_MCS_R       (*((volatile unsigned long *)0x40020004))
-#define I2C0_MASTER_SDR_R       (*((volatile unsigned long *)0x40020008))
 #define I2C0_MASTER_MDR_R       (*((volatile unsigned long *)0x40020008))
 #define I2C0_MASTER_MTPR_R      (*((volatile unsigned long *)0x4002000C))
-#define I2C0_MASTER_SIMR_R      (*((volatile unsigned long *)0x4002000C))
-#define I2C0_MASTER_SRIS_R      (*((volatile unsigned long *)0x40020010))
 #define I2C0_MASTER_MIMR_R      (*((volatile unsigned long *)0x40020010))
 #define I2C0_MASTER_MRIS_R      (*((volatile unsigned long *)0x40020014))
-#define I2C0_MASTER_SMIS_R      (*((volatile unsigned long *)0x40020014))
-#define I2C0_MASTER_SICR_R      (*((volatile unsigned long *)0x40020018))
 #define I2C0_MASTER_MMIS_R      (*((volatile unsigned long *)0x40020018))
 #define I2C0_MASTER_MICR_R      (*((volatile unsigned long *)0x4002001C))
 #define I2C0_MASTER_MCR_R       (*((volatile unsigned long *)0x40020020))
 
 //*****************************************************************************
 //
-// Inter-Integrated Circuit (SLAVE) Interface
+// I2C registers (I2C0 SLAVE)
 //
 //*****************************************************************************
-#define I2C0_SLAVE_MSA_R        (*((volatile unsigned long *)0x40020800))
 #define I2C0_SLAVE_SOAR_R       (*((volatile unsigned long *)0x40020800))
 #define I2C0_SLAVE_SCSR_R       (*((volatile unsigned long *)0x40020804))
-#define I2C0_SLAVE_MCS_R        (*((volatile unsigned long *)0x40020804))
 #define I2C0_SLAVE_SDR_R        (*((volatile unsigned long *)0x40020808))
-#define I2C0_SLAVE_MDR_R        (*((volatile unsigned long *)0x40020808))
-#define I2C0_SLAVE_MTPR_R       (*((volatile unsigned long *)0x4002080C))
 #define I2C0_SLAVE_SIMR_R       (*((volatile unsigned long *)0x4002080C))
 #define I2C0_SLAVE_SRIS_R       (*((volatile unsigned long *)0x40020810))
-#define I2C0_SLAVE_MIMR_R       (*((volatile unsigned long *)0x40020810))
-#define I2C0_SLAVE_MRIS_R       (*((volatile unsigned long *)0x40020814))
 #define I2C0_SLAVE_SMIS_R       (*((volatile unsigned long *)0x40020814))
 #define I2C0_SLAVE_SICR_R       (*((volatile unsigned long *)0x40020818))
-#define I2C0_SLAVE_MMIS_R       (*((volatile unsigned long *)0x40020818))
-#define I2C0_SLAVE_MICR_R       (*((volatile unsigned long *)0x4002081C))
-#define I2C0_SLAVE_MCR_R        (*((volatile unsigned long *)0x40020820))
 
 //*****************************************************************************
 //
-// Inter-Integrated Circuit (MASTER) Interface
+// I2C registers (I2C1 MASTER)
 //
 //*****************************************************************************
 #define I2C1_MASTER_MSA_R       (*((volatile unsigned long *)0x40021000))
-#define I2C1_MASTER_SOAR_R      (*((volatile unsigned long *)0x40021000))
-#define I2C1_MASTER_SCSR_R      (*((volatile unsigned long *)0x40021004))
 #define I2C1_MASTER_MCS_R       (*((volatile unsigned long *)0x40021004))
-#define I2C1_MASTER_SDR_R       (*((volatile unsigned long *)0x40021008))
 #define I2C1_MASTER_MDR_R       (*((volatile unsigned long *)0x40021008))
 #define I2C1_MASTER_MTPR_R      (*((volatile unsigned long *)0x4002100C))
-#define I2C1_MASTER_SIMR_R      (*((volatile unsigned long *)0x4002100C))
-#define I2C1_MASTER_SRIS_R      (*((volatile unsigned long *)0x40021010))
 #define I2C1_MASTER_MIMR_R      (*((volatile unsigned long *)0x40021010))
 #define I2C1_MASTER_MRIS_R      (*((volatile unsigned long *)0x40021014))
-#define I2C1_MASTER_SMIS_R      (*((volatile unsigned long *)0x40021014))
-#define I2C1_MASTER_SICR_R      (*((volatile unsigned long *)0x40021018))
 #define I2C1_MASTER_MMIS_R      (*((volatile unsigned long *)0x40021018))
 #define I2C1_MASTER_MICR_R      (*((volatile unsigned long *)0x4002101C))
 #define I2C1_MASTER_MCR_R       (*((volatile unsigned long *)0x40021020))
 
 //*****************************************************************************
 //
-// Inter-Integrated Circuit (SLAVE) Interface
+// I2C registers (I2C1 SLAVE)
 //
 //*****************************************************************************
-#define I2C1_SLAVE_MSA_R        (*((volatile unsigned long *)0x40021800))
 #define I2C1_SLAVE_SOAR_R       (*((volatile unsigned long *)0x40021800))
 #define I2C1_SLAVE_SCSR_R       (*((volatile unsigned long *)0x40021804))
-#define I2C1_SLAVE_MCS_R        (*((volatile unsigned long *)0x40021804))
 #define I2C1_SLAVE_SDR_R        (*((volatile unsigned long *)0x40021808))
-#define I2C1_SLAVE_MDR_R        (*((volatile unsigned long *)0x40021808))
-#define I2C1_SLAVE_MTPR_R       (*((volatile unsigned long *)0x4002180C))
 #define I2C1_SLAVE_SIMR_R       (*((volatile unsigned long *)0x4002180C))
 #define I2C1_SLAVE_SRIS_R       (*((volatile unsigned long *)0x40021810))
-#define I2C1_SLAVE_MIMR_R       (*((volatile unsigned long *)0x40021810))
-#define I2C1_SLAVE_MRIS_R       (*((volatile unsigned long *)0x40021814))
 #define I2C1_SLAVE_SMIS_R       (*((volatile unsigned long *)0x40021814))
 #define I2C1_SLAVE_SICR_R       (*((volatile unsigned long *)0x40021818))
-#define I2C1_SLAVE_MMIS_R       (*((volatile unsigned long *)0x40021818))
-#define I2C1_SLAVE_MICR_R       (*((volatile unsigned long *)0x4002181C))
-#define I2C1_SLAVE_MCR_R        (*((volatile unsigned long *)0x40021820))
 
 //*****************************************************************************
 //
-// General-Purpose Input/Outputs (PORTE)
+// GPIO registers (PORTE)
 //
 //*****************************************************************************
 #define GPIO_PORTE_DATA_BITS_R  ((volatile unsigned long *)0x40024000)
@@ -395,7 +360,7 @@
 
 //*****************************************************************************
 //
-// General-Purpose Input/Outputs (PORTF)
+// GPIO registers (PORTF)
 //
 //*****************************************************************************
 #define GPIO_PORTF_DATA_BITS_R  ((volatile unsigned long *)0x40025000)
@@ -424,7 +389,7 @@
 
 //*****************************************************************************
 //
-// General-Purpose Input/Outputs (PORTG)
+// GPIO registers (PORTG)
 //
 //*****************************************************************************
 #define GPIO_PORTG_DATA_BITS_R  ((volatile unsigned long *)0x40026000)
@@ -453,7 +418,7 @@
 
 //*****************************************************************************
 //
-// General-Purpose Input/Outputs (PORTH)
+// GPIO registers (PORTH)
 //
 //*****************************************************************************
 #define GPIO_PORTH_DATA_BITS_R  ((volatile unsigned long *)0x40027000)
@@ -482,7 +447,7 @@
 
 //*****************************************************************************
 //
-// Pulse Width Modulator (PWM)
+// PWM registers (PWM)
 //
 //*****************************************************************************
 #define PWM_CTL_R               (*((volatile unsigned long *)0x40028000))
@@ -495,6 +460,7 @@
 #define PWM_ISC_R               (*((volatile unsigned long *)0x4002801C))
 #define PWM_STATUS_R            (*((volatile unsigned long *)0x40028020))
 #define PWM_FAULTVAL_R          (*((volatile unsigned long *)0x40028024))
+#define PWM_ENUPD_R             (*((volatile unsigned long *)0x40028028))
 #define PWM_0_CTL_R             (*((volatile unsigned long *)0x40028040))
 #define PWM_0_INTEN_R           (*((volatile unsigned long *)0x40028044))
 #define PWM_0_RIS_R             (*((volatile unsigned long *)0x40028048))
@@ -574,7 +540,7 @@
 
 //*****************************************************************************
 //
-// Quadrature Encoder Interface (QEI0)
+// QEI registers (QEI0)
 //
 //*****************************************************************************
 #define QEI0_CTL_R              (*((volatile unsigned long *)0x4002C000))
@@ -591,7 +557,7 @@
 
 //*****************************************************************************
 //
-// Quadrature Encoder Interface (QEI1)
+// QEI registers (QEI1)
 //
 //*****************************************************************************
 #define QEI1_CTL_R              (*((volatile unsigned long *)0x4002D000))
@@ -608,7 +574,7 @@
 
 //*****************************************************************************
 //
-// General-Purpose Timers (TIMER0)
+// Timer registers (TIMER0)
 //
 //*****************************************************************************
 #define TIMER0_CFG_R            (*((volatile unsigned long *)0x40030000))
@@ -625,6 +591,8 @@
 #define TIMER0_TBMATCHR_R       (*((volatile unsigned long *)0x40030034))
 #define TIMER0_TAPR_R           (*((volatile unsigned long *)0x40030038))
 #define TIMER0_TBPR_R           (*((volatile unsigned long *)0x4003003C))
+#define TIMER0_TAPMR_R          (*((volatile unsigned long *)0x40030040))
+#define TIMER0_TBPMR_R          (*((volatile unsigned long *)0x40030044))
 #define TIMER0_TAR_R            (*((volatile unsigned long *)0x40030048))
 #define TIMER0_TBR_R            (*((volatile unsigned long *)0x4003004C))
 #define TIMER0_TAV_R            (*((volatile unsigned long *)0x40030050))
@@ -632,7 +600,7 @@
 
 //*****************************************************************************
 //
-// General-Purpose Timers (TIMER1)
+// Timer registers (TIMER1)
 //
 //*****************************************************************************
 #define TIMER1_CFG_R            (*((volatile unsigned long *)0x40031000))
@@ -649,6 +617,8 @@
 #define TIMER1_TBMATCHR_R       (*((volatile unsigned long *)0x40031034))
 #define TIMER1_TAPR_R           (*((volatile unsigned long *)0x40031038))
 #define TIMER1_TBPR_R           (*((volatile unsigned long *)0x4003103C))
+#define TIMER1_TAPMR_R          (*((volatile unsigned long *)0x40031040))
+#define TIMER1_TBPMR_R          (*((volatile unsigned long *)0x40031044))
 #define TIMER1_TAR_R            (*((volatile unsigned long *)0x40031048))
 #define TIMER1_TBR_R            (*((volatile unsigned long *)0x4003104C))
 #define TIMER1_TAV_R            (*((volatile unsigned long *)0x40031050))
@@ -656,7 +626,7 @@
 
 //*****************************************************************************
 //
-// General-Purpose Timers (TIMER2)
+// Timer registers (TIMER2)
 //
 //*****************************************************************************
 #define TIMER2_CFG_R            (*((volatile unsigned long *)0x40032000))
@@ -673,6 +643,8 @@
 #define TIMER2_TBMATCHR_R       (*((volatile unsigned long *)0x40032034))
 #define TIMER2_TAPR_R           (*((volatile unsigned long *)0x40032038))
 #define TIMER2_TBPR_R           (*((volatile unsigned long *)0x4003203C))
+#define TIMER2_TAPMR_R          (*((volatile unsigned long *)0x40032040))
+#define TIMER2_TBPMR_R          (*((volatile unsigned long *)0x40032044))
 #define TIMER2_TAR_R            (*((volatile unsigned long *)0x40032048))
 #define TIMER2_TBR_R            (*((volatile unsigned long *)0x4003204C))
 #define TIMER2_TAV_R            (*((volatile unsigned long *)0x40032050))
@@ -680,7 +652,7 @@
 
 //*****************************************************************************
 //
-// General-Purpose Timers (TIMER3)
+// Timer registers (TIMER3)
 //
 //*****************************************************************************
 #define TIMER3_CFG_R            (*((volatile unsigned long *)0x40033000))
@@ -697,6 +669,8 @@
 #define TIMER3_TBMATCHR_R       (*((volatile unsigned long *)0x40033034))
 #define TIMER3_TAPR_R           (*((volatile unsigned long *)0x40033038))
 #define TIMER3_TBPR_R           (*((volatile unsigned long *)0x4003303C))
+#define TIMER3_TAPMR_R          (*((volatile unsigned long *)0x40033040))
+#define TIMER3_TBPMR_R          (*((volatile unsigned long *)0x40033044))
 #define TIMER3_TAR_R            (*((volatile unsigned long *)0x40033048))
 #define TIMER3_TBR_R            (*((volatile unsigned long *)0x4003304C))
 #define TIMER3_TAV_R            (*((volatile unsigned long *)0x40033050))
@@ -704,7 +678,7 @@
 
 //*****************************************************************************
 //
-// Analog-to-Digital Converter (ADC0)
+// ADC registers (ADC0)
 //
 //*****************************************************************************
 #define ADC0_ACTSS_R            (*((volatile unsigned long *)0x40038000))
@@ -715,6 +689,7 @@
 #define ADC0_EMUX_R             (*((volatile unsigned long *)0x40038014))
 #define ADC0_USTAT_R            (*((volatile unsigned long *)0x40038018))
 #define ADC0_SSPRI_R            (*((volatile unsigned long *)0x40038020))
+#define ADC0_SPC_R              (*((volatile unsigned long *)0x40038024))
 #define ADC0_PSSI_R             (*((volatile unsigned long *)0x40038028))
 #define ADC0_SAC_R              (*((volatile unsigned long *)0x40038030))
 #define ADC0_DCISC_R            (*((volatile unsigned long *)0x40038034))
@@ -763,7 +738,7 @@
 
 //*****************************************************************************
 //
-// Analog-to-Digital Converter (ADC1)
+// ADC registers (ADC1)
 //
 //*****************************************************************************
 #define ADC1_ACTSS_R            (*((volatile unsigned long *)0x40039000))
@@ -774,6 +749,7 @@
 #define ADC1_EMUX_R             (*((volatile unsigned long *)0x40039014))
 #define ADC1_USTAT_R            (*((volatile unsigned long *)0x40039018))
 #define ADC1_SSPRI_R            (*((volatile unsigned long *)0x40039020))
+#define ADC1_SPC_R              (*((volatile unsigned long *)0x40039024))
 #define ADC1_PSSI_R             (*((volatile unsigned long *)0x40039028))
 #define ADC1_SAC_R              (*((volatile unsigned long *)0x40039030))
 #define ADC1_DCISC_R            (*((volatile unsigned long *)0x40039034))
@@ -822,7 +798,7 @@
 
 //*****************************************************************************
 //
-// Analog Comparators (COMP)
+// Comparator registers (COMP)
 //
 //*****************************************************************************
 #define COMP_ACMIS_R            (*((volatile unsigned long *)0x4003C000))
@@ -838,7 +814,7 @@
 
 //*****************************************************************************
 //
-// General-Purpose Input/Outputs (PORTJ)
+// GPIO registers (PORTJ)
 //
 //*****************************************************************************
 #define GPIO_PORTJ_DATA_BITS_R  ((volatile unsigned long *)0x4003D000)
@@ -867,7 +843,7 @@
 
 //*****************************************************************************
 //
-// Controller Area Network (CAN0) Module
+// CAN registers (CAN0)
 //
 //*****************************************************************************
 #define CAN0_CTL_R              (*((volatile unsigned long *)0x40040000))
@@ -910,7 +886,7 @@
 
 //*****************************************************************************
 //
-// Controller Area Network (CAN1) Module
+// CAN registers (CAN1)
 //
 //*****************************************************************************
 #define CAN1_CTL_R              (*((volatile unsigned long *)0x40041000))
@@ -953,31 +929,17 @@
 
 //*****************************************************************************
 //
-// Ethernet Controller (MAC)
+// Ethernet MAC registers (MAC)
 //
 //*****************************************************************************
-#define MAC_MR0_R               (*((volatile unsigned long *)0x40048000))
 #define MAC_RIS_R               (*((volatile unsigned long *)0x40048000))
-#define MAC_IACK_R              (*((volatile unsigned long *)0x40048000))
-#define MAC_MR1_R               (*((volatile unsigned long *)0x40048001))
-#define MAC_MR2_R               (*((volatile unsigned long *)0x40048002))
-#define MAC_MR3_R               (*((volatile unsigned long *)0x40048003))
 #define MAC_IM_R                (*((volatile unsigned long *)0x40048004))
-#define MAC_MR4_R               (*((volatile unsigned long *)0x40048004))
-#define MAC_MR5_R               (*((volatile unsigned long *)0x40048005))
-#define MAC_MR6_R               (*((volatile unsigned long *)0x40048006))
 #define MAC_RCTL_R              (*((volatile unsigned long *)0x40048008))
 #define MAC_TCTL_R              (*((volatile unsigned long *)0x4004800C))
 #define MAC_DATA_R              (*((volatile unsigned long *)0x40048010))
-#define MAC_MR16_R              (*((volatile unsigned long *)0x40048010))
-#define MAC_MR17_R              (*((volatile unsigned long *)0x40048011))
 #define MAC_IA0_R               (*((volatile unsigned long *)0x40048014))
 #define MAC_IA1_R               (*((volatile unsigned long *)0x40048018))
-#define MAC_MR27_R              (*((volatile unsigned long *)0x4004801B))
 #define MAC_THR_R               (*((volatile unsigned long *)0x4004801C))
-#define MAC_MR29_R              (*((volatile unsigned long *)0x4004801D))
-#define MAC_MR30_R              (*((volatile unsigned long *)0x4004801E))
-#define MAC_MR31_R              (*((volatile unsigned long *)0x4004801F))
 #define MAC_MCTL_R              (*((volatile unsigned long *)0x40048020))
 #define MAC_MDV_R               (*((volatile unsigned long *)0x40048024))
 #define MAC_MTXD_R              (*((volatile unsigned long *)0x4004802C))
@@ -989,20 +951,54 @@
 
 //*****************************************************************************
 //
-// Universal Serial Bus (USB0) Controller
+// Ethernet Controller PHY registers (MAC)
 //
 //*****************************************************************************
-#define USB0_FADDR_R            (*((volatile unsigned long *)0x40050000))
-#define USB0_POWER_R            (*((volatile unsigned long *)0x40050001))
-#define USB0_TXIS_R             (*((volatile unsigned long *)0x40050002))
-#define USB0_RXIS_R             (*((volatile unsigned long *)0x40050004))
-#define USB0_TXIE_R             (*((volatile unsigned long *)0x40050006))
-#define USB0_RXIE_R             (*((volatile unsigned long *)0x40050008))
-#define USB0_IS_R               (*((volatile unsigned long *)0x4005000A))
-#define USB0_IE_R               (*((volatile unsigned long *)0x4005000B))
-#define USB0_FRAME_R            (*((volatile unsigned long *)0x4005000C))
-#define USB0_EPIDX_R            (*((volatile unsigned long *)0x4005000E))
-#define USB0_TEST_R             (*((volatile unsigned long *)0x4005000F))
+#define PHY_MR0                 0x00000000  // Ethernet PHY Management Register
+                                            // 0 - Control
+#define PHY_MR1                 0x00000001  // Ethernet PHY Management Register
+                                            // 1 - Status
+#define PHY_MR2                 0x00000002  // Ethernet PHY Management Register
+                                            // 2 - PHY Identifier 1
+#define PHY_MR3                 0x00000003  // Ethernet PHY Management Register
+                                            // 3 - PHY Identifier 2
+#define PHY_MR4                 0x00000004  // Ethernet PHY Management Register
+                                            // 4 - Auto-Negotiation
+                                            // Advertisement
+#define PHY_MR5                 0x00000005  // Ethernet PHY Management Register
+                                            // 5 - Auto-Negotiation Link
+                                            // Partner Base Page Ability
+#define PHY_MR6                 0x00000006  // Ethernet PHY Management Register
+                                            // 6 - Auto-Negotiation Expansion
+#define PHY_MR16                0x00000010  // Ethernet PHY Management Register
+                                            // 16 - Vendor-Specific
+#define PHY_MR17                0x00000011  // Ethernet PHY Management Register
+                                            // 17 - Mode Control/Status
+#define PHY_MR27                0x0000001B  // Ethernet PHY Management Register
+                                            // 27 - Special Control/Status
+#define PHY_MR29                0x0000001D  // Ethernet PHY Management Register
+                                            // 29 - Interrupt Status
+#define PHY_MR30                0x0000001E  // Ethernet PHY Management Register
+                                            // 30 - Interrupt Mask
+#define PHY_MR31                0x0000001F  // Ethernet PHY Management Register
+                                            // 31 - PHY Special Control/Status
+
+//*****************************************************************************
+//
+// Univeral Serial Bus registers (USB0)
+//
+//*****************************************************************************
+#define USB0_FADDR_R            (*((volatile unsigned char *)0x40050000))
+#define USB0_POWER_R            (*((volatile unsigned char *)0x40050001))
+#define USB0_TXIS_R             (*((volatile unsigned short *)0x40050002))
+#define USB0_RXIS_R             (*((volatile unsigned short *)0x40050004))
+#define USB0_TXIE_R             (*((volatile unsigned short *)0x40050006))
+#define USB0_RXIE_R             (*((volatile unsigned short *)0x40050008))
+#define USB0_IS_R               (*((volatile unsigned char *)0x4005000A))
+#define USB0_IE_R               (*((volatile unsigned char *)0x4005000B))
+#define USB0_FRAME_R            (*((volatile unsigned short *)0x4005000C))
+#define USB0_EPIDX_R            (*((volatile unsigned char *)0x4005000E))
+#define USB0_TEST_R             (*((volatile unsigned char *)0x4005000F))
 #define USB0_FIFO0_R            (*((volatile unsigned long *)0x40050020))
 #define USB0_FIFO1_R            (*((volatile unsigned long *)0x40050024))
 #define USB0_FIFO2_R            (*((volatile unsigned long *)0x40050028))
@@ -1019,295 +1015,295 @@
 #define USB0_FIFO13_R           (*((volatile unsigned long *)0x40050054))
 #define USB0_FIFO14_R           (*((volatile unsigned long *)0x40050058))
 #define USB0_FIFO15_R           (*((volatile unsigned long *)0x4005005C))
-#define USB0_DEVCTL_R           (*((volatile unsigned long *)0x40050060))
-#define USB0_TXFIFOSZ_R         (*((volatile unsigned long *)0x40050062))
-#define USB0_RXFIFOSZ_R         (*((volatile unsigned long *)0x40050063))
-#define USB0_TXFIFOADD_R        (*((volatile unsigned long *)0x40050064))
-#define USB0_RXFIFOADD_R        (*((volatile unsigned long *)0x40050066))
-#define USB0_CONTIM_R           (*((volatile unsigned long *)0x4005007A))
-#define USB0_VPLEN_R            (*((volatile unsigned long *)0x4005007B))
-#define USB0_FSEOF_R            (*((volatile unsigned long *)0x4005007D))
-#define USB0_LSEOF_R            (*((volatile unsigned long *)0x4005007E))
-#define USB0_TXFUNCADDR0_R      (*((volatile unsigned long *)0x40050080))
-#define USB0_TXHUBADDR0_R       (*((volatile unsigned long *)0x40050082))
-#define USB0_TXHUBPORT0_R       (*((volatile unsigned long *)0x40050083))
-#define USB0_TXFUNCADDR1_R      (*((volatile unsigned long *)0x40050088))
-#define USB0_TXHUBADDR1_R       (*((volatile unsigned long *)0x4005008A))
-#define USB0_TXHUBPORT1_R       (*((volatile unsigned long *)0x4005008B))
-#define USB0_RXFUNCADDR1_R      (*((volatile unsigned long *)0x4005008C))
-#define USB0_RXHUBADDR1_R       (*((volatile unsigned long *)0x4005008E))
-#define USB0_RXHUBPORT1_R       (*((volatile unsigned long *)0x4005008F))
-#define USB0_TXFUNCADDR2_R      (*((volatile unsigned long *)0x40050090))
-#define USB0_TXHUBADDR2_R       (*((volatile unsigned long *)0x40050092))
-#define USB0_TXHUBPORT2_R       (*((volatile unsigned long *)0x40050093))
-#define USB0_RXFUNCADDR2_R      (*((volatile unsigned long *)0x40050094))
-#define USB0_RXHUBADDR2_R       (*((volatile unsigned long *)0x40050096))
-#define USB0_RXHUBPORT2_R       (*((volatile unsigned long *)0x40050097))
-#define USB0_TXFUNCADDR3_R      (*((volatile unsigned long *)0x40050098))
-#define USB0_TXHUBADDR3_R       (*((volatile unsigned long *)0x4005009A))
-#define USB0_TXHUBPORT3_R       (*((volatile unsigned long *)0x4005009B))
-#define USB0_RXFUNCADDR3_R      (*((volatile unsigned long *)0x4005009C))
-#define USB0_RXHUBADDR3_R       (*((volatile unsigned long *)0x4005009E))
-#define USB0_RXHUBPORT3_R       (*((volatile unsigned long *)0x4005009F))
-#define USB0_TXFUNCADDR4_R      (*((volatile unsigned long *)0x400500A0))
-#define USB0_TXHUBADDR4_R       (*((volatile unsigned long *)0x400500A2))
-#define USB0_TXHUBPORT4_R       (*((volatile unsigned long *)0x400500A3))
-#define USB0_RXFUNCADDR4_R      (*((volatile unsigned long *)0x400500A4))
-#define USB0_RXHUBADDR4_R       (*((volatile unsigned long *)0x400500A6))
-#define USB0_RXHUBPORT4_R       (*((volatile unsigned long *)0x400500A7))
-#define USB0_TXFUNCADDR5_R      (*((volatile unsigned long *)0x400500A8))
-#define USB0_TXHUBADDR5_R       (*((volatile unsigned long *)0x400500AA))
-#define USB0_TXHUBPORT5_R       (*((volatile unsigned long *)0x400500AB))
-#define USB0_RXFUNCADDR5_R      (*((volatile unsigned long *)0x400500AC))
-#define USB0_RXHUBADDR5_R       (*((volatile unsigned long *)0x400500AE))
-#define USB0_RXHUBPORT5_R       (*((volatile unsigned long *)0x400500AF))
-#define USB0_TXFUNCADDR6_R      (*((volatile unsigned long *)0x400500B0))
-#define USB0_TXHUBADDR6_R       (*((volatile unsigned long *)0x400500B2))
-#define USB0_TXHUBPORT6_R       (*((volatile unsigned long *)0x400500B3))
-#define USB0_RXFUNCADDR6_R      (*((volatile unsigned long *)0x400500B4))
-#define USB0_RXHUBADDR6_R       (*((volatile unsigned long *)0x400500B6))
-#define USB0_RXHUBPORT6_R       (*((volatile unsigned long *)0x400500B7))
-#define USB0_TXFUNCADDR7_R      (*((volatile unsigned long *)0x400500B8))
-#define USB0_TXHUBADDR7_R       (*((volatile unsigned long *)0x400500BA))
-#define USB0_TXHUBPORT7_R       (*((volatile unsigned long *)0x400500BB))
-#define USB0_RXFUNCADDR7_R      (*((volatile unsigned long *)0x400500BC))
-#define USB0_RXHUBADDR7_R       (*((volatile unsigned long *)0x400500BE))
-#define USB0_RXHUBPORT7_R       (*((volatile unsigned long *)0x400500BF))
-#define USB0_TXFUNCADDR8_R      (*((volatile unsigned long *)0x400500C0))
-#define USB0_TXHUBADDR8_R       (*((volatile unsigned long *)0x400500C2))
-#define USB0_TXHUBPORT8_R       (*((volatile unsigned long *)0x400500C3))
-#define USB0_RXFUNCADDR8_R      (*((volatile unsigned long *)0x400500C4))
-#define USB0_RXHUBADDR8_R       (*((volatile unsigned long *)0x400500C6))
-#define USB0_RXHUBPORT8_R       (*((volatile unsigned long *)0x400500C7))
-#define USB0_TXFUNCADDR9_R      (*((volatile unsigned long *)0x400500C8))
-#define USB0_TXHUBADDR9_R       (*((volatile unsigned long *)0x400500CA))
-#define USB0_TXHUBPORT9_R       (*((volatile unsigned long *)0x400500CB))
-#define USB0_RXFUNCADDR9_R      (*((volatile unsigned long *)0x400500CC))
-#define USB0_RXHUBADDR9_R       (*((volatile unsigned long *)0x400500CE))
-#define USB0_RXHUBPORT9_R       (*((volatile unsigned long *)0x400500CF))
-#define USB0_TXFUNCADDR10_R     (*((volatile unsigned long *)0x400500D0))
-#define USB0_TXHUBADDR10_R      (*((volatile unsigned long *)0x400500D2))
-#define USB0_TXHUBPORT10_R      (*((volatile unsigned long *)0x400500D3))
-#define USB0_RXFUNCADDR10_R     (*((volatile unsigned long *)0x400500D4))
-#define USB0_RXHUBADDR10_R      (*((volatile unsigned long *)0x400500D6))
-#define USB0_RXHUBPORT10_R      (*((volatile unsigned long *)0x400500D7))
-#define USB0_TXFUNCADDR11_R     (*((volatile unsigned long *)0x400500D8))
-#define USB0_TXHUBADDR11_R      (*((volatile unsigned long *)0x400500DA))
-#define USB0_TXHUBPORT11_R      (*((volatile unsigned long *)0x400500DB))
-#define USB0_RXFUNCADDR11_R     (*((volatile unsigned long *)0x400500DC))
-#define USB0_RXHUBADDR11_R      (*((volatile unsigned long *)0x400500DE))
-#define USB0_RXHUBPORT11_R      (*((volatile unsigned long *)0x400500DF))
-#define USB0_TXFUNCADDR12_R     (*((volatile unsigned long *)0x400500E0))
-#define USB0_TXHUBADDR12_R      (*((volatile unsigned long *)0x400500E2))
-#define USB0_TXHUBPORT12_R      (*((volatile unsigned long *)0x400500E3))
-#define USB0_RXFUNCADDR12_R     (*((volatile unsigned long *)0x400500E4))
-#define USB0_RXHUBADDR12_R      (*((volatile unsigned long *)0x400500E6))
-#define USB0_RXHUBPORT12_R      (*((volatile unsigned long *)0x400500E7))
-#define USB0_TXFUNCADDR13_R     (*((volatile unsigned long *)0x400500E8))
-#define USB0_TXHUBADDR13_R      (*((volatile unsigned long *)0x400500EA))
-#define USB0_TXHUBPORT13_R      (*((volatile unsigned long *)0x400500EB))
-#define USB0_RXFUNCADDR13_R     (*((volatile unsigned long *)0x400500EC))
-#define USB0_RXHUBADDR13_R      (*((volatile unsigned long *)0x400500EE))
-#define USB0_RXHUBPORT13_R      (*((volatile unsigned long *)0x400500EF))
-#define USB0_TXFUNCADDR14_R     (*((volatile unsigned long *)0x400500F0))
-#define USB0_TXHUBADDR14_R      (*((volatile unsigned long *)0x400500F2))
-#define USB0_TXHUBPORT14_R      (*((volatile unsigned long *)0x400500F3))
-#define USB0_RXFUNCADDR14_R     (*((volatile unsigned long *)0x400500F4))
-#define USB0_RXHUBADDR14_R      (*((volatile unsigned long *)0x400500F6))
-#define USB0_RXHUBPORT14_R      (*((volatile unsigned long *)0x400500F7))
-#define USB0_TXFUNCADDR15_R     (*((volatile unsigned long *)0x400500F8))
-#define USB0_TXHUBADDR15_R      (*((volatile unsigned long *)0x400500FA))
-#define USB0_TXHUBPORT15_R      (*((volatile unsigned long *)0x400500FB))
-#define USB0_RXFUNCADDR15_R     (*((volatile unsigned long *)0x400500FC))
-#define USB0_RXHUBADDR15_R      (*((volatile unsigned long *)0x400500FE))
-#define USB0_RXHUBPORT15_R      (*((volatile unsigned long *)0x400500FF))
-#define USB0_CSRL0_R            (*((volatile unsigned long *)0x40050102))
-#define USB0_CSRH0_R            (*((volatile unsigned long *)0x40050103))
-#define USB0_COUNT0_R           (*((volatile unsigned long *)0x40050108))
-#define USB0_TYPE0_R            (*((volatile unsigned long *)0x4005010A))
-#define USB0_NAKLMT_R           (*((volatile unsigned long *)0x4005010B))
-#define USB0_TXMAXP1_R          (*((volatile unsigned long *)0x40050110))
-#define USB0_TXCSRL1_R          (*((volatile unsigned long *)0x40050112))
-#define USB0_TXCSRH1_R          (*((volatile unsigned long *)0x40050113))
-#define USB0_RXMAXP1_R          (*((volatile unsigned long *)0x40050114))
-#define USB0_RXCSRL1_R          (*((volatile unsigned long *)0x40050116))
-#define USB0_RXCSRH1_R          (*((volatile unsigned long *)0x40050117))
-#define USB0_RXCOUNT1_R         (*((volatile unsigned long *)0x40050118))
-#define USB0_TXTYPE1_R          (*((volatile unsigned long *)0x4005011A))
-#define USB0_TXINTERVAL1_R      (*((volatile unsigned long *)0x4005011B))
-#define USB0_RXTYPE1_R          (*((volatile unsigned long *)0x4005011C))
-#define USB0_RXINTERVAL1_R      (*((volatile unsigned long *)0x4005011D))
-#define USB0_TXMAXP2_R          (*((volatile unsigned long *)0x40050120))
-#define USB0_TXCSRL2_R          (*((volatile unsigned long *)0x40050122))
-#define USB0_TXCSRH2_R          (*((volatile unsigned long *)0x40050123))
-#define USB0_RXMAXP2_R          (*((volatile unsigned long *)0x40050124))
-#define USB0_RXCSRL2_R          (*((volatile unsigned long *)0x40050126))
-#define USB0_RXCSRH2_R          (*((volatile unsigned long *)0x40050127))
-#define USB0_RXCOUNT2_R         (*((volatile unsigned long *)0x40050128))
-#define USB0_TXTYPE2_R          (*((volatile unsigned long *)0x4005012A))
-#define USB0_TXINTERVAL2_R      (*((volatile unsigned long *)0x4005012B))
-#define USB0_RXTYPE2_R          (*((volatile unsigned long *)0x4005012C))
-#define USB0_RXINTERVAL2_R      (*((volatile unsigned long *)0x4005012D))
-#define USB0_TXMAXP3_R          (*((volatile unsigned long *)0x40050130))
-#define USB0_TXCSRL3_R          (*((volatile unsigned long *)0x40050132))
-#define USB0_TXCSRH3_R          (*((volatile unsigned long *)0x40050133))
-#define USB0_RXMAXP3_R          (*((volatile unsigned long *)0x40050134))
-#define USB0_RXCSRL3_R          (*((volatile unsigned long *)0x40050136))
-#define USB0_RXCSRH3_R          (*((volatile unsigned long *)0x40050137))
-#define USB0_RXCOUNT3_R         (*((volatile unsigned long *)0x40050138))
-#define USB0_TXTYPE3_R          (*((volatile unsigned long *)0x4005013A))
-#define USB0_TXINTERVAL3_R      (*((volatile unsigned long *)0x4005013B))
-#define USB0_RXTYPE3_R          (*((volatile unsigned long *)0x4005013C))
-#define USB0_RXINTERVAL3_R      (*((volatile unsigned long *)0x4005013D))
-#define USB0_TXMAXP4_R          (*((volatile unsigned long *)0x40050140))
-#define USB0_TXCSRL4_R          (*((volatile unsigned long *)0x40050142))
-#define USB0_TXCSRH4_R          (*((volatile unsigned long *)0x40050143))
-#define USB0_RXMAXP4_R          (*((volatile unsigned long *)0x40050144))
-#define USB0_RXCSRL4_R          (*((volatile unsigned long *)0x40050146))
-#define USB0_RXCSRH4_R          (*((volatile unsigned long *)0x40050147))
-#define USB0_RXCOUNT4_R         (*((volatile unsigned long *)0x40050148))
-#define USB0_TXTYPE4_R          (*((volatile unsigned long *)0x4005014A))
-#define USB0_TXINTERVAL4_R      (*((volatile unsigned long *)0x4005014B))
-#define USB0_RXTYPE4_R          (*((volatile unsigned long *)0x4005014C))
-#define USB0_RXINTERVAL4_R      (*((volatile unsigned long *)0x4005014D))
-#define USB0_TXMAXP5_R          (*((volatile unsigned long *)0x40050150))
-#define USB0_TXCSRL5_R          (*((volatile unsigned long *)0x40050152))
-#define USB0_TXCSRH5_R          (*((volatile unsigned long *)0x40050153))
-#define USB0_RXMAXP5_R          (*((volatile unsigned long *)0x40050154))
-#define USB0_RXCSRL5_R          (*((volatile unsigned long *)0x40050156))
-#define USB0_RXCSRH5_R          (*((volatile unsigned long *)0x40050157))
-#define USB0_RXCOUNT5_R         (*((volatile unsigned long *)0x40050158))
-#define USB0_TXTYPE5_R          (*((volatile unsigned long *)0x4005015A))
-#define USB0_TXINTERVAL5_R      (*((volatile unsigned long *)0x4005015B))
-#define USB0_RXTYPE5_R          (*((volatile unsigned long *)0x4005015C))
-#define USB0_RXINTERVAL5_R      (*((volatile unsigned long *)0x4005015D))
-#define USB0_TXMAXP6_R          (*((volatile unsigned long *)0x40050160))
-#define USB0_TXCSRL6_R          (*((volatile unsigned long *)0x40050162))
-#define USB0_TXCSRH6_R          (*((volatile unsigned long *)0x40050163))
-#define USB0_RXMAXP6_R          (*((volatile unsigned long *)0x40050164))
-#define USB0_RXCSRL6_R          (*((volatile unsigned long *)0x40050166))
-#define USB0_RXCSRH6_R          (*((volatile unsigned long *)0x40050167))
-#define USB0_RXCOUNT6_R         (*((volatile unsigned long *)0x40050168))
-#define USB0_TXTYPE6_R          (*((volatile unsigned long *)0x4005016A))
-#define USB0_TXINTERVAL6_R      (*((volatile unsigned long *)0x4005016B))
-#define USB0_RXTYPE6_R          (*((volatile unsigned long *)0x4005016C))
-#define USB0_RXINTERVAL6_R      (*((volatile unsigned long *)0x4005016D))
-#define USB0_TXMAXP7_R          (*((volatile unsigned long *)0x40050170))
-#define USB0_TXCSRL7_R          (*((volatile unsigned long *)0x40050172))
-#define USB0_TXCSRH7_R          (*((volatile unsigned long *)0x40050173))
-#define USB0_RXMAXP7_R          (*((volatile unsigned long *)0x40050174))
-#define USB0_RXCSRL7_R          (*((volatile unsigned long *)0x40050176))
-#define USB0_RXCSRH7_R          (*((volatile unsigned long *)0x40050177))
-#define USB0_RXCOUNT7_R         (*((volatile unsigned long *)0x40050178))
-#define USB0_TXTYPE7_R          (*((volatile unsigned long *)0x4005017A))
-#define USB0_TXINTERVAL7_R      (*((volatile unsigned long *)0x4005017B))
-#define USB0_RXTYPE7_R          (*((volatile unsigned long *)0x4005017C))
-#define USB0_RXINTERVAL7_R      (*((volatile unsigned long *)0x4005017D))
-#define USB0_TXMAXP8_R          (*((volatile unsigned long *)0x40050180))
-#define USB0_TXCSRL8_R          (*((volatile unsigned long *)0x40050182))
-#define USB0_TXCSRH8_R          (*((volatile unsigned long *)0x40050183))
-#define USB0_RXMAXP8_R          (*((volatile unsigned long *)0x40050184))
-#define USB0_RXCSRL8_R          (*((volatile unsigned long *)0x40050186))
-#define USB0_RXCSRH8_R          (*((volatile unsigned long *)0x40050187))
-#define USB0_RXCOUNT8_R         (*((volatile unsigned long *)0x40050188))
-#define USB0_TXTYPE8_R          (*((volatile unsigned long *)0x4005018A))
-#define USB0_TXINTERVAL8_R      (*((volatile unsigned long *)0x4005018B))
-#define USB0_RXTYPE8_R          (*((volatile unsigned long *)0x4005018C))
-#define USB0_RXINTERVAL8_R      (*((volatile unsigned long *)0x4005018D))
-#define USB0_TXMAXP9_R          (*((volatile unsigned long *)0x40050190))
-#define USB0_TXCSRL9_R          (*((volatile unsigned long *)0x40050192))
-#define USB0_TXCSRH9_R          (*((volatile unsigned long *)0x40050193))
-#define USB0_RXMAXP9_R          (*((volatile unsigned long *)0x40050194))
-#define USB0_RXCSRL9_R          (*((volatile unsigned long *)0x40050196))
-#define USB0_RXCSRH9_R          (*((volatile unsigned long *)0x40050197))
-#define USB0_RXCOUNT9_R         (*((volatile unsigned long *)0x40050198))
-#define USB0_TXTYPE9_R          (*((volatile unsigned long *)0x4005019A))
-#define USB0_TXINTERVAL9_R      (*((volatile unsigned long *)0x4005019B))
-#define USB0_RXTYPE9_R          (*((volatile unsigned long *)0x4005019C))
-#define USB0_RXINTERVAL9_R      (*((volatile unsigned long *)0x4005019D))
-#define USB0_TXMAXP10_R         (*((volatile unsigned long *)0x400501A0))
-#define USB0_TXCSRL10_R         (*((volatile unsigned long *)0x400501A2))
-#define USB0_TXCSRH10_R         (*((volatile unsigned long *)0x400501A3))
-#define USB0_RXMAXP10_R         (*((volatile unsigned long *)0x400501A4))
-#define USB0_RXCSRL10_R         (*((volatile unsigned long *)0x400501A6))
-#define USB0_RXCSRH10_R         (*((volatile unsigned long *)0x400501A7))
-#define USB0_RXCOUNT10_R        (*((volatile unsigned long *)0x400501A8))
-#define USB0_TXTYPE10_R         (*((volatile unsigned long *)0x400501AA))
-#define USB0_TXINTERVAL10_R     (*((volatile unsigned long *)0x400501AB))
-#define USB0_RXTYPE10_R         (*((volatile unsigned long *)0x400501AC))
-#define USB0_RXINTERVAL10_R     (*((volatile unsigned long *)0x400501AD))
-#define USB0_TXMAXP11_R         (*((volatile unsigned long *)0x400501B0))
-#define USB0_TXCSRL11_R         (*((volatile unsigned long *)0x400501B2))
-#define USB0_TXCSRH11_R         (*((volatile unsigned long *)0x400501B3))
-#define USB0_RXMAXP11_R         (*((volatile unsigned long *)0x400501B4))
-#define USB0_RXCSRL11_R         (*((volatile unsigned long *)0x400501B6))
-#define USB0_RXCSRH11_R         (*((volatile unsigned long *)0x400501B7))
-#define USB0_RXCOUNT11_R        (*((volatile unsigned long *)0x400501B8))
-#define USB0_TXTYPE11_R         (*((volatile unsigned long *)0x400501BA))
-#define USB0_TXINTERVAL11_R     (*((volatile unsigned long *)0x400501BB))
-#define USB0_RXTYPE11_R         (*((volatile unsigned long *)0x400501BC))
-#define USB0_RXINTERVAL11_R     (*((volatile unsigned long *)0x400501BD))
-#define USB0_TXMAXP12_R         (*((volatile unsigned long *)0x400501C0))
-#define USB0_TXCSRL12_R         (*((volatile unsigned long *)0x400501C2))
-#define USB0_TXCSRH12_R         (*((volatile unsigned long *)0x400501C3))
-#define USB0_RXMAXP12_R         (*((volatile unsigned long *)0x400501C4))
-#define USB0_RXCSRL12_R         (*((volatile unsigned long *)0x400501C6))
-#define USB0_RXCSRH12_R         (*((volatile unsigned long *)0x400501C7))
-#define USB0_RXCOUNT12_R        (*((volatile unsigned long *)0x400501C8))
-#define USB0_TXTYPE12_R         (*((volatile unsigned long *)0x400501CA))
-#define USB0_TXINTERVAL12_R     (*((volatile unsigned long *)0x400501CB))
-#define USB0_RXTYPE12_R         (*((volatile unsigned long *)0x400501CC))
-#define USB0_RXINTERVAL12_R     (*((volatile unsigned long *)0x400501CD))
-#define USB0_TXMAXP13_R         (*((volatile unsigned long *)0x400501D0))
-#define USB0_TXCSRL13_R         (*((volatile unsigned long *)0x400501D2))
-#define USB0_TXCSRH13_R         (*((volatile unsigned long *)0x400501D3))
-#define USB0_RXMAXP13_R         (*((volatile unsigned long *)0x400501D4))
-#define USB0_RXCSRL13_R         (*((volatile unsigned long *)0x400501D6))
-#define USB0_RXCSRH13_R         (*((volatile unsigned long *)0x400501D7))
-#define USB0_RXCOUNT13_R        (*((volatile unsigned long *)0x400501D8))
-#define USB0_TXTYPE13_R         (*((volatile unsigned long *)0x400501DA))
-#define USB0_TXINTERVAL13_R     (*((volatile unsigned long *)0x400501DB))
-#define USB0_RXTYPE13_R         (*((volatile unsigned long *)0x400501DC))
-#define USB0_RXINTERVAL13_R     (*((volatile unsigned long *)0x400501DD))
-#define USB0_TXMAXP14_R         (*((volatile unsigned long *)0x400501E0))
-#define USB0_TXCSRL14_R         (*((volatile unsigned long *)0x400501E2))
-#define USB0_TXCSRH14_R         (*((volatile unsigned long *)0x400501E3))
-#define USB0_RXMAXP14_R         (*((volatile unsigned long *)0x400501E4))
-#define USB0_RXCSRL14_R         (*((volatile unsigned long *)0x400501E6))
-#define USB0_RXCSRH14_R         (*((volatile unsigned long *)0x400501E7))
-#define USB0_RXCOUNT14_R        (*((volatile unsigned long *)0x400501E8))
-#define USB0_TXTYPE14_R         (*((volatile unsigned long *)0x400501EA))
-#define USB0_TXINTERVAL14_R     (*((volatile unsigned long *)0x400501EB))
-#define USB0_RXTYPE14_R         (*((volatile unsigned long *)0x400501EC))
-#define USB0_RXINTERVAL14_R     (*((volatile unsigned long *)0x400501ED))
-#define USB0_TXMAXP15_R         (*((volatile unsigned long *)0x400501F0))
-#define USB0_TXCSRL15_R         (*((volatile unsigned long *)0x400501F2))
-#define USB0_TXCSRH15_R         (*((volatile unsigned long *)0x400501F3))
-#define USB0_RXMAXP15_R         (*((volatile unsigned long *)0x400501F4))
-#define USB0_RXCSRL15_R         (*((volatile unsigned long *)0x400501F6))
-#define USB0_RXCSRH15_R         (*((volatile unsigned long *)0x400501F7))
-#define USB0_RXCOUNT15_R        (*((volatile unsigned long *)0x400501F8))
-#define USB0_TXTYPE15_R         (*((volatile unsigned long *)0x400501FA))
-#define USB0_TXINTERVAL15_R     (*((volatile unsigned long *)0x400501FB))
-#define USB0_RXTYPE15_R         (*((volatile unsigned long *)0x400501FC))
-#define USB0_RXINTERVAL15_R     (*((volatile unsigned long *)0x400501FD))
-#define USB0_RQPKTCOUNT1_R      (*((volatile unsigned long *)0x40050304))
-#define USB0_RQPKTCOUNT2_R      (*((volatile unsigned long *)0x40050308))
-#define USB0_RQPKTCOUNT3_R      (*((volatile unsigned long *)0x4005030C))
-#define USB0_RQPKTCOUNT4_R      (*((volatile unsigned long *)0x40050310))
-#define USB0_RQPKTCOUNT5_R      (*((volatile unsigned long *)0x40050314))
-#define USB0_RQPKTCOUNT6_R      (*((volatile unsigned long *)0x40050318))
-#define USB0_RQPKTCOUNT7_R      (*((volatile unsigned long *)0x4005031C))
-#define USB0_RQPKTCOUNT8_R      (*((volatile unsigned long *)0x40050320))
-#define USB0_RQPKTCOUNT9_R      (*((volatile unsigned long *)0x40050324))
-#define USB0_RQPKTCOUNT10_R     (*((volatile unsigned long *)0x40050328))
-#define USB0_RQPKTCOUNT11_R     (*((volatile unsigned long *)0x4005032C))
-#define USB0_RQPKTCOUNT12_R     (*((volatile unsigned long *)0x40050330))
-#define USB0_RQPKTCOUNT13_R     (*((volatile unsigned long *)0x40050334))
-#define USB0_RQPKTCOUNT14_R     (*((volatile unsigned long *)0x40050338))
-#define USB0_RQPKTCOUNT15_R     (*((volatile unsigned long *)0x4005033C))
-#define USB0_RXDPKTBUFDIS_R     (*((volatile unsigned long *)0x40050340))
-#define USB0_TXDPKTBUFDIS_R     (*((volatile unsigned long *)0x40050342))
+#define USB0_DEVCTL_R           (*((volatile unsigned char *)0x40050060))
+#define USB0_TXFIFOSZ_R         (*((volatile unsigned char *)0x40050062))
+#define USB0_RXFIFOSZ_R         (*((volatile unsigned char *)0x40050063))
+#define USB0_TXFIFOADD_R        (*((volatile unsigned short *)0x40050064))
+#define USB0_RXFIFOADD_R        (*((volatile unsigned short *)0x40050066))
+#define USB0_CONTIM_R           (*((volatile unsigned char *)0x4005007A))
+#define USB0_VPLEN_R            (*((volatile unsigned char *)0x4005007B))
+#define USB0_FSEOF_R            (*((volatile unsigned char *)0x4005007D))
+#define USB0_LSEOF_R            (*((volatile unsigned char *)0x4005007E))
+#define USB0_TXFUNCADDR0_R      (*((volatile unsigned char *)0x40050080))
+#define USB0_TXHUBADDR0_R       (*((volatile unsigned char *)0x40050082))
+#define USB0_TXHUBPORT0_R       (*((volatile unsigned char *)0x40050083))
+#define USB0_TXFUNCADDR1_R      (*((volatile unsigned char *)0x40050088))
+#define USB0_TXHUBADDR1_R       (*((volatile unsigned char *)0x4005008A))
+#define USB0_TXHUBPORT1_R       (*((volatile unsigned char *)0x4005008B))
+#define USB0_RXFUNCADDR1_R      (*((volatile unsigned char *)0x4005008C))
+#define USB0_RXHUBADDR1_R       (*((volatile unsigned char *)0x4005008E))
+#define USB0_RXHUBPORT1_R       (*((volatile unsigned char *)0x4005008F))
+#define USB0_TXFUNCADDR2_R      (*((volatile unsigned char *)0x40050090))
+#define USB0_TXHUBADDR2_R       (*((volatile unsigned char *)0x40050092))
+#define USB0_TXHUBPORT2_R       (*((volatile unsigned char *)0x40050093))
+#define USB0_RXFUNCADDR2_R      (*((volatile unsigned char *)0x40050094))
+#define USB0_RXHUBADDR2_R       (*((volatile unsigned char *)0x40050096))
+#define USB0_RXHUBPORT2_R       (*((volatile unsigned char *)0x40050097))
+#define USB0_TXFUNCADDR3_R      (*((volatile unsigned char *)0x40050098))
+#define USB0_TXHUBADDR3_R       (*((volatile unsigned char *)0x4005009A))
+#define USB0_TXHUBPORT3_R       (*((volatile unsigned char *)0x4005009B))
+#define USB0_RXFUNCADDR3_R      (*((volatile unsigned char *)0x4005009C))
+#define USB0_RXHUBADDR3_R       (*((volatile unsigned char *)0x4005009E))
+#define USB0_RXHUBPORT3_R       (*((volatile unsigned char *)0x4005009F))
+#define USB0_TXFUNCADDR4_R      (*((volatile unsigned char *)0x400500A0))
+#define USB0_TXHUBADDR4_R       (*((volatile unsigned char *)0x400500A2))
+#define USB0_TXHUBPORT4_R       (*((volatile unsigned char *)0x400500A3))
+#define USB0_RXFUNCADDR4_R      (*((volatile unsigned char *)0x400500A4))
+#define USB0_RXHUBADDR4_R       (*((volatile unsigned char *)0x400500A6))
+#define USB0_RXHUBPORT4_R       (*((volatile unsigned char *)0x400500A7))
+#define USB0_TXFUNCADDR5_R      (*((volatile unsigned char *)0x400500A8))
+#define USB0_TXHUBADDR5_R       (*((volatile unsigned char *)0x400500AA))
+#define USB0_TXHUBPORT5_R       (*((volatile unsigned char *)0x400500AB))
+#define USB0_RXFUNCADDR5_R      (*((volatile unsigned char *)0x400500AC))
+#define USB0_RXHUBADDR5_R       (*((volatile unsigned char *)0x400500AE))
+#define USB0_RXHUBPORT5_R       (*((volatile unsigned char *)0x400500AF))
+#define USB0_TXFUNCADDR6_R      (*((volatile unsigned char *)0x400500B0))
+#define USB0_TXHUBADDR6_R       (*((volatile unsigned char *)0x400500B2))
+#define USB0_TXHUBPORT6_R       (*((volatile unsigned char *)0x400500B3))
+#define USB0_RXFUNCADDR6_R      (*((volatile unsigned char *)0x400500B4))
+#define USB0_RXHUBADDR6_R       (*((volatile unsigned char *)0x400500B6))
+#define USB0_RXHUBPORT6_R       (*((volatile unsigned char *)0x400500B7))
+#define USB0_TXFUNCADDR7_R      (*((volatile unsigned char *)0x400500B8))
+#define USB0_TXHUBADDR7_R       (*((volatile unsigned char *)0x400500BA))
+#define USB0_TXHUBPORT7_R       (*((volatile unsigned char *)0x400500BB))
+#define USB0_RXFUNCADDR7_R      (*((volatile unsigned char *)0x400500BC))
+#define USB0_RXHUBADDR7_R       (*((volatile unsigned char *)0x400500BE))
+#define USB0_RXHUBPORT7_R       (*((volatile unsigned char *)0x400500BF))
+#define USB0_TXFUNCADDR8_R      (*((volatile unsigned char *)0x400500C0))
+#define USB0_TXHUBADDR8_R       (*((volatile unsigned char *)0x400500C2))
+#define USB0_TXHUBPORT8_R       (*((volatile unsigned char *)0x400500C3))
+#define USB0_RXFUNCADDR8_R      (*((volatile unsigned char *)0x400500C4))
+#define USB0_RXHUBADDR8_R       (*((volatile unsigned char *)0x400500C6))
+#define USB0_RXHUBPORT8_R       (*((volatile unsigned char *)0x400500C7))
+#define USB0_TXFUNCADDR9_R      (*((volatile unsigned char *)0x400500C8))
+#define USB0_TXHUBADDR9_R       (*((volatile unsigned char *)0x400500CA))
+#define USB0_TXHUBPORT9_R       (*((volatile unsigned char *)0x400500CB))
+#define USB0_RXFUNCADDR9_R      (*((volatile unsigned char *)0x400500CC))
+#define USB0_RXHUBADDR9_R       (*((volatile unsigned char *)0x400500CE))
+#define USB0_RXHUBPORT9_R       (*((volatile unsigned char *)0x400500CF))
+#define USB0_TXFUNCADDR10_R     (*((volatile unsigned char *)0x400500D0))
+#define USB0_TXHUBADDR10_R      (*((volatile unsigned char *)0x400500D2))
+#define USB0_TXHUBPORT10_R      (*((volatile unsigned char *)0x400500D3))
+#define USB0_RXFUNCADDR10_R     (*((volatile unsigned char *)0x400500D4))
+#define USB0_RXHUBADDR10_R      (*((volatile unsigned char *)0x400500D6))
+#define USB0_RXHUBPORT10_R      (*((volatile unsigned char *)0x400500D7))
+#define USB0_TXFUNCADDR11_R     (*((volatile unsigned char *)0x400500D8))
+#define USB0_TXHUBADDR11_R      (*((volatile unsigned char *)0x400500DA))
+#define USB0_TXHUBPORT11_R      (*((volatile unsigned char *)0x400500DB))
+#define USB0_RXFUNCADDR11_R     (*((volatile unsigned char *)0x400500DC))
+#define USB0_RXHUBADDR11_R      (*((volatile unsigned char *)0x400500DE))
+#define USB0_RXHUBPORT11_R      (*((volatile unsigned char *)0x400500DF))
+#define USB0_TXFUNCADDR12_R     (*((volatile unsigned char *)0x400500E0))
+#define USB0_TXHUBADDR12_R      (*((volatile unsigned char *)0x400500E2))
+#define USB0_TXHUBPORT12_R      (*((volatile unsigned char *)0x400500E3))
+#define USB0_RXFUNCADDR12_R     (*((volatile unsigned char *)0x400500E4))
+#define USB0_RXHUBADDR12_R      (*((volatile unsigned char *)0x400500E6))
+#define USB0_RXHUBPORT12_R      (*((volatile unsigned char *)0x400500E7))
+#define USB0_TXFUNCADDR13_R     (*((volatile unsigned char *)0x400500E8))
+#define USB0_TXHUBADDR13_R      (*((volatile unsigned char *)0x400500EA))
+#define USB0_TXHUBPORT13_R      (*((volatile unsigned char *)0x400500EB))
+#define USB0_RXFUNCADDR13_R     (*((volatile unsigned char *)0x400500EC))
+#define USB0_RXHUBADDR13_R      (*((volatile unsigned char *)0x400500EE))
+#define USB0_RXHUBPORT13_R      (*((volatile unsigned char *)0x400500EF))
+#define USB0_TXFUNCADDR14_R     (*((volatile unsigned char *)0x400500F0))
+#define USB0_TXHUBADDR14_R      (*((volatile unsigned char *)0x400500F2))
+#define USB0_TXHUBPORT14_R      (*((volatile unsigned char *)0x400500F3))
+#define USB0_RXFUNCADDR14_R     (*((volatile unsigned char *)0x400500F4))
+#define USB0_RXHUBADDR14_R      (*((volatile unsigned char *)0x400500F6))
+#define USB0_RXHUBPORT14_R      (*((volatile unsigned char *)0x400500F7))
+#define USB0_TXFUNCADDR15_R     (*((volatile unsigned char *)0x400500F8))
+#define USB0_TXHUBADDR15_R      (*((volatile unsigned char *)0x400500FA))
+#define USB0_TXHUBPORT15_R      (*((volatile unsigned char *)0x400500FB))
+#define USB0_RXFUNCADDR15_R     (*((volatile unsigned char *)0x400500FC))
+#define USB0_RXHUBADDR15_R      (*((volatile unsigned char *)0x400500FE))
+#define USB0_RXHUBPORT15_R      (*((volatile unsigned char *)0x400500FF))
+#define USB0_CSRL0_R            (*((volatile unsigned char *)0x40050102))
+#define USB0_CSRH0_R            (*((volatile unsigned char *)0x40050103))
+#define USB0_COUNT0_R           (*((volatile unsigned char *)0x40050108))
+#define USB0_TYPE0_R            (*((volatile unsigned char *)0x4005010A))
+#define USB0_NAKLMT_R           (*((volatile unsigned char *)0x4005010B))
+#define USB0_TXMAXP1_R          (*((volatile unsigned short *)0x40050110))
+#define USB0_TXCSRL1_R          (*((volatile unsigned char *)0x40050112))
+#define USB0_TXCSRH1_R          (*((volatile unsigned char *)0x40050113))
+#define USB0_RXMAXP1_R          (*((volatile unsigned short *)0x40050114))
+#define USB0_RXCSRL1_R          (*((volatile unsigned char *)0x40050116))
+#define USB0_RXCSRH1_R          (*((volatile unsigned char *)0x40050117))
+#define USB0_RXCOUNT1_R         (*((volatile unsigned short *)0x40050118))
+#define USB0_TXTYPE1_R          (*((volatile unsigned char *)0x4005011A))
+#define USB0_TXINTERVAL1_R      (*((volatile unsigned char *)0x4005011B))
+#define USB0_RXTYPE1_R          (*((volatile unsigned char *)0x4005011C))
+#define USB0_RXINTERVAL1_R      (*((volatile unsigned char *)0x4005011D))
+#define USB0_TXMAXP2_R          (*((volatile unsigned short *)0x40050120))
+#define USB0_TXCSRL2_R          (*((volatile unsigned char *)0x40050122))
+#define USB0_TXCSRH2_R          (*((volatile unsigned char *)0x40050123))
+#define USB0_RXMAXP2_R          (*((volatile unsigned short *)0x40050124))
+#define USB0_RXCSRL2_R          (*((volatile unsigned char *)0x40050126))
+#define USB0_RXCSRH2_R          (*((volatile unsigned char *)0x40050127))
+#define USB0_RXCOUNT2_R         (*((volatile unsigned short *)0x40050128))
+#define USB0_TXTYPE2_R          (*((volatile unsigned char *)0x4005012A))
+#define USB0_TXINTERVAL2_R      (*((volatile unsigned char *)0x4005012B))
+#define USB0_RXTYPE2_R          (*((volatile unsigned char *)0x4005012C))
+#define USB0_RXINTERVAL2_R      (*((volatile unsigned char *)0x4005012D))
+#define USB0_TXMAXP3_R          (*((volatile unsigned short *)0x40050130))
+#define USB0_TXCSRL3_R          (*((volatile unsigned char *)0x40050132))
+#define USB0_TXCSRH3_R          (*((volatile unsigned char *)0x40050133))
+#define USB0_RXMAXP3_R          (*((volatile unsigned short *)0x40050134))
+#define USB0_RXCSRL3_R          (*((volatile unsigned char *)0x40050136))
+#define USB0_RXCSRH3_R          (*((volatile unsigned char *)0x40050137))
+#define USB0_RXCOUNT3_R         (*((volatile unsigned short *)0x40050138))
+#define USB0_TXTYPE3_R          (*((volatile unsigned char *)0x4005013A))
+#define USB0_TXINTERVAL3_R      (*((volatile unsigned char *)0x4005013B))
+#define USB0_RXTYPE3_R          (*((volatile unsigned char *)0x4005013C))
+#define USB0_RXINTERVAL3_R      (*((volatile unsigned char *)0x4005013D))
+#define USB0_TXMAXP4_R          (*((volatile unsigned short *)0x40050140))
+#define USB0_TXCSRL4_R          (*((volatile unsigned char *)0x40050142))
+#define USB0_TXCSRH4_R          (*((volatile unsigned char *)0x40050143))
+#define USB0_RXMAXP4_R          (*((volatile unsigned short *)0x40050144))
+#define USB0_RXCSRL4_R          (*((volatile unsigned char *)0x40050146))
+#define USB0_RXCSRH4_R          (*((volatile unsigned char *)0x40050147))
+#define USB0_RXCOUNT4_R         (*((volatile unsigned short *)0x40050148))
+#define USB0_TXTYPE4_R          (*((volatile unsigned char *)0x4005014A))
+#define USB0_TXINTERVAL4_R      (*((volatile unsigned char *)0x4005014B))
+#define USB0_RXTYPE4_R          (*((volatile unsigned char *)0x4005014C))
+#define USB0_RXINTERVAL4_R      (*((volatile unsigned char *)0x4005014D))
+#define USB0_TXMAXP5_R          (*((volatile unsigned short *)0x40050150))
+#define USB0_TXCSRL5_R          (*((volatile unsigned char *)0x40050152))
+#define USB0_TXCSRH5_R          (*((volatile unsigned char *)0x40050153))
+#define USB0_RXMAXP5_R          (*((volatile unsigned short *)0x40050154))
+#define USB0_RXCSRL5_R          (*((volatile unsigned char *)0x40050156))
+#define USB0_RXCSRH5_R          (*((volatile unsigned char *)0x40050157))
+#define USB0_RXCOUNT5_R         (*((volatile unsigned short *)0x40050158))
+#define USB0_TXTYPE5_R          (*((volatile unsigned char *)0x4005015A))
+#define USB0_TXINTERVAL5_R      (*((volatile unsigned char *)0x4005015B))
+#define USB0_RXTYPE5_R          (*((volatile unsigned char *)0x4005015C))
+#define USB0_RXINTERVAL5_R      (*((volatile unsigned char *)0x4005015D))
+#define USB0_TXMAXP6_R          (*((volatile unsigned short *)0x40050160))
+#define USB0_TXCSRL6_R          (*((volatile unsigned char *)0x40050162))
+#define USB0_TXCSRH6_R          (*((volatile unsigned char *)0x40050163))
+#define USB0_RXMAXP6_R          (*((volatile unsigned short *)0x40050164))
+#define USB0_RXCSRL6_R          (*((volatile unsigned char *)0x40050166))
+#define USB0_RXCSRH6_R          (*((volatile unsigned char *)0x40050167))
+#define USB0_RXCOUNT6_R         (*((volatile unsigned short *)0x40050168))
+#define USB0_TXTYPE6_R          (*((volatile unsigned char *)0x4005016A))
+#define USB0_TXINTERVAL6_R      (*((volatile unsigned char *)0x4005016B))
+#define USB0_RXTYPE6_R          (*((volatile unsigned char *)0x4005016C))
+#define USB0_RXINTERVAL6_R      (*((volatile unsigned char *)0x4005016D))
+#define USB0_TXMAXP7_R          (*((volatile unsigned short *)0x40050170))
+#define USB0_TXCSRL7_R          (*((volatile unsigned char *)0x40050172))
+#define USB0_TXCSRH7_R          (*((volatile unsigned char *)0x40050173))
+#define USB0_RXMAXP7_R          (*((volatile unsigned short *)0x40050174))
+#define USB0_RXCSRL7_R          (*((volatile unsigned char *)0x40050176))
+#define USB0_RXCSRH7_R          (*((volatile unsigned char *)0x40050177))
+#define USB0_RXCOUNT7_R         (*((volatile unsigned short *)0x40050178))
+#define USB0_TXTYPE7_R          (*((volatile unsigned char *)0x4005017A))
+#define USB0_TXINTERVAL7_R      (*((volatile unsigned char *)0x4005017B))
+#define USB0_RXTYPE7_R          (*((volatile unsigned char *)0x4005017C))
+#define USB0_RXINTERVAL7_R      (*((volatile unsigned char *)0x4005017D))
+#define USB0_TXMAXP8_R          (*((volatile unsigned short *)0x40050180))
+#define USB0_TXCSRL8_R          (*((volatile unsigned char *)0x40050182))
+#define USB0_TXCSRH8_R          (*((volatile unsigned char *)0x40050183))
+#define USB0_RXMAXP8_R          (*((volatile unsigned short *)0x40050184))
+#define USB0_RXCSRL8_R          (*((volatile unsigned char *)0x40050186))
+#define USB0_RXCSRH8_R          (*((volatile unsigned char *)0x40050187))
+#define USB0_RXCOUNT8_R         (*((volatile unsigned short *)0x40050188))
+#define USB0_TXTYPE8_R          (*((volatile unsigned char *)0x4005018A))
+#define USB0_TXINTERVAL8_R      (*((volatile unsigned char *)0x4005018B))
+#define USB0_RXTYPE8_R          (*((volatile unsigned char *)0x4005018C))
+#define USB0_RXINTERVAL8_R      (*((volatile unsigned char *)0x4005018D))
+#define USB0_TXMAXP9_R          (*((volatile unsigned short *)0x40050190))
+#define USB0_TXCSRL9_R          (*((volatile unsigned char *)0x40050192))
+#define USB0_TXCSRH9_R          (*((volatile unsigned char *)0x40050193))
+#define USB0_RXMAXP9_R          (*((volatile unsigned short *)0x40050194))
+#define USB0_RXCSRL9_R          (*((volatile unsigned char *)0x40050196))
+#define USB0_RXCSRH9_R          (*((volatile unsigned char *)0x40050197))
+#define USB0_RXCOUNT9_R         (*((volatile unsigned short *)0x40050198))
+#define USB0_TXTYPE9_R          (*((volatile unsigned char *)0x4005019A))
+#define USB0_TXINTERVAL9_R      (*((volatile unsigned char *)0x4005019B))
+#define USB0_RXTYPE9_R          (*((volatile unsigned char *)0x4005019C))
+#define USB0_RXINTERVAL9_R      (*((volatile unsigned char *)0x4005019D))
+#define USB0_TXMAXP10_R         (*((volatile unsigned short *)0x400501A0))
+#define USB0_TXCSRL10_R         (*((volatile unsigned char *)0x400501A2))
+#define USB0_TXCSRH10_R         (*((volatile unsigned char *)0x400501A3))
+#define USB0_RXMAXP10_R         (*((volatile unsigned short *)0x400501A4))
+#define USB0_RXCSRL10_R         (*((volatile unsigned char *)0x400501A6))
+#define USB0_RXCSRH10_R         (*((volatile unsigned char *)0x400501A7))
+#define USB0_RXCOUNT10_R        (*((volatile unsigned short *)0x400501A8))
+#define USB0_TXTYPE10_R         (*((volatile unsigned char *)0x400501AA))
+#define USB0_TXINTERVAL10_R     (*((volatile unsigned char *)0x400501AB))
+#define USB0_RXTYPE10_R         (*((volatile unsigned char *)0x400501AC))
+#define USB0_RXINTERVAL10_R     (*((volatile unsigned char *)0x400501AD))
+#define USB0_TXMAXP11_R         (*((volatile unsigned short *)0x400501B0))
+#define USB0_TXCSRL11_R         (*((volatile unsigned char *)0x400501B2))
+#define USB0_TXCSRH11_R         (*((volatile unsigned char *)0x400501B3))
+#define USB0_RXMAXP11_R         (*((volatile unsigned short *)0x400501B4))
+#define USB0_RXCSRL11_R         (*((volatile unsigned char *)0x400501B6))
+#define USB0_RXCSRH11_R         (*((volatile unsigned char *)0x400501B7))
+#define USB0_RXCOUNT11_R        (*((volatile unsigned short *)0x400501B8))
+#define USB0_TXTYPE11_R         (*((volatile unsigned char *)0x400501BA))
+#define USB0_TXINTERVAL11_R     (*((volatile unsigned char *)0x400501BB))
+#define USB0_RXTYPE11_R         (*((volatile unsigned char *)0x400501BC))
+#define USB0_RXINTERVAL11_R     (*((volatile unsigned char *)0x400501BD))
+#define USB0_TXMAXP12_R         (*((volatile unsigned short *)0x400501C0))
+#define USB0_TXCSRL12_R         (*((volatile unsigned char *)0x400501C2))
+#define USB0_TXCSRH12_R         (*((volatile unsigned char *)0x400501C3))
+#define USB0_RXMAXP12_R         (*((volatile unsigned short *)0x400501C4))
+#define USB0_RXCSRL12_R         (*((volatile unsigned char *)0x400501C6))
+#define USB0_RXCSRH12_R         (*((volatile unsigned char *)0x400501C7))
+#define USB0_RXCOUNT12_R        (*((volatile unsigned short *)0x400501C8))
+#define USB0_TXTYPE12_R         (*((volatile unsigned char *)0x400501CA))
+#define USB0_TXINTERVAL12_R     (*((volatile unsigned char *)0x400501CB))
+#define USB0_RXTYPE12_R         (*((volatile unsigned char *)0x400501CC))
+#define USB0_RXINTERVAL12_R     (*((volatile unsigned char *)0x400501CD))
+#define USB0_TXMAXP13_R         (*((volatile unsigned short *)0x400501D0))
+#define USB0_TXCSRL13_R         (*((volatile unsigned char *)0x400501D2))
+#define USB0_TXCSRH13_R         (*((volatile unsigned char *)0x400501D3))
+#define USB0_RXMAXP13_R         (*((volatile unsigned short *)0x400501D4))
+#define USB0_RXCSRL13_R         (*((volatile unsigned char *)0x400501D6))
+#define USB0_RXCSRH13_R         (*((volatile unsigned char *)0x400501D7))
+#define USB0_RXCOUNT13_R        (*((volatile unsigned short *)0x400501D8))
+#define USB0_TXTYPE13_R         (*((volatile unsigned char *)0x400501DA))
+#define USB0_TXINTERVAL13_R     (*((volatile unsigned char *)0x400501DB))
+#define USB0_RXTYPE13_R         (*((volatile unsigned char *)0x400501DC))
+#define USB0_RXINTERVAL13_R     (*((volatile unsigned char *)0x400501DD))
+#define USB0_TXMAXP14_R         (*((volatile unsigned short *)0x400501E0))
+#define USB0_TXCSRL14_R         (*((volatile unsigned char *)0x400501E2))
+#define USB0_TXCSRH14_R         (*((volatile unsigned char *)0x400501E3))
+#define USB0_RXMAXP14_R         (*((volatile unsigned short *)0x400501E4))
+#define USB0_RXCSRL14_R         (*((volatile unsigned char *)0x400501E6))
+#define USB0_RXCSRH14_R         (*((volatile unsigned char *)0x400501E7))
+#define USB0_RXCOUNT14_R        (*((volatile unsigned short *)0x400501E8))
+#define USB0_TXTYPE14_R         (*((volatile unsigned char *)0x400501EA))
+#define USB0_TXINTERVAL14_R     (*((volatile unsigned char *)0x400501EB))
+#define USB0_RXTYPE14_R         (*((volatile unsigned char *)0x400501EC))
+#define USB0_RXINTERVAL14_R     (*((volatile unsigned char *)0x400501ED))
+#define USB0_TXMAXP15_R         (*((volatile unsigned short *)0x400501F0))
+#define USB0_TXCSRL15_R         (*((volatile unsigned char *)0x400501F2))
+#define USB0_TXCSRH15_R         (*((volatile unsigned char *)0x400501F3))
+#define USB0_RXMAXP15_R         (*((volatile unsigned short *)0x400501F4))
+#define USB0_RXCSRL15_R         (*((volatile unsigned char *)0x400501F6))
+#define USB0_RXCSRH15_R         (*((volatile unsigned char *)0x400501F7))
+#define USB0_RXCOUNT15_R        (*((volatile unsigned short *)0x400501F8))
+#define USB0_TXTYPE15_R         (*((volatile unsigned char *)0x400501FA))
+#define USB0_TXINTERVAL15_R     (*((volatile unsigned char *)0x400501FB))
+#define USB0_RXTYPE15_R         (*((volatile unsigned char *)0x400501FC))
+#define USB0_RXINTERVAL15_R     (*((volatile unsigned char *)0x400501FD))
+#define USB0_RQPKTCOUNT1_R      (*((volatile unsigned short *)0x40050304))
+#define USB0_RQPKTCOUNT2_R      (*((volatile unsigned short *)0x40050308))
+#define USB0_RQPKTCOUNT3_R      (*((volatile unsigned short *)0x4005030C))
+#define USB0_RQPKTCOUNT4_R      (*((volatile unsigned short *)0x40050310))
+#define USB0_RQPKTCOUNT5_R      (*((volatile unsigned short *)0x40050314))
+#define USB0_RQPKTCOUNT6_R      (*((volatile unsigned short *)0x40050318))
+#define USB0_RQPKTCOUNT7_R      (*((volatile unsigned short *)0x4005031C))
+#define USB0_RQPKTCOUNT8_R      (*((volatile unsigned short *)0x40050320))
+#define USB0_RQPKTCOUNT9_R      (*((volatile unsigned short *)0x40050324))
+#define USB0_RQPKTCOUNT10_R     (*((volatile unsigned short *)0x40050328))
+#define USB0_RQPKTCOUNT11_R     (*((volatile unsigned short *)0x4005032C))
+#define USB0_RQPKTCOUNT12_R     (*((volatile unsigned short *)0x40050330))
+#define USB0_RQPKTCOUNT13_R     (*((volatile unsigned short *)0x40050334))
+#define USB0_RQPKTCOUNT14_R     (*((volatile unsigned short *)0x40050338))
+#define USB0_RQPKTCOUNT15_R     (*((volatile unsigned short *)0x4005033C))
+#define USB0_RXDPKTBUFDIS_R     (*((volatile unsigned short *)0x40050340))
+#define USB0_TXDPKTBUFDIS_R     (*((volatile unsigned short *)0x40050342))
 #define USB0_EPC_R              (*((volatile unsigned long *)0x40050400))
 #define USB0_EPCRIS_R           (*((volatile unsigned long *)0x40050404))
 #define USB0_EPCIM_R            (*((volatile unsigned long *)0x40050408))
@@ -1315,6 +1311,7 @@
 #define USB0_DRRIS_R            (*((volatile unsigned long *)0x40050410))
 #define USB0_DRIM_R             (*((volatile unsigned long *)0x40050414))
 #define USB0_DRISC_R            (*((volatile unsigned long *)0x40050418))
+#define USB0_GPCS_R             (*((volatile unsigned long *)0x4005041C))
 #define USB0_VDC_R              (*((volatile unsigned long *)0x40050430))
 #define USB0_VDCRIS_R           (*((volatile unsigned long *)0x40050434))
 #define USB0_VDCIM_R            (*((volatile unsigned long *)0x40050438))
@@ -1322,11 +1319,11 @@
 #define USB0_IDVRIS_R           (*((volatile unsigned long *)0x40050444))
 #define USB0_IDVIM_R            (*((volatile unsigned long *)0x40050448))
 #define USB0_IDVISC_R           (*((volatile unsigned long *)0x4005044C))
-#define USB0_EPS_R              (*((volatile unsigned long *)0x40050450))
+#define USB0_DMASEL_R           (*((volatile unsigned long *)0x40050450))
 
 //*****************************************************************************
 //
-// Inter-Integrated Circuit Sound (I2S0) Interface
+// Inter-Integrated Circuit Sound registers (I2S0)
 //
 //*****************************************************************************
 #define I2S0_TXFIFO_R           (*((volatile unsigned long *)0x40054000))
@@ -1349,7 +1346,7 @@
 
 //*****************************************************************************
 //
-// General-Purpose Input/Outputs (AHB)
+// GPIO registers (PORTA AHB)
 //
 //*****************************************************************************
 #define GPIO_PORTA_AHB_DATA_BITS_R \
@@ -1379,7 +1376,7 @@
 
 //*****************************************************************************
 //
-// General-Purpose Input/Outputs (AHB)
+// GPIO registers (PORTB AHB)
 //
 //*****************************************************************************
 #define GPIO_PORTB_AHB_DATA_BITS_R \
@@ -1409,7 +1406,7 @@
 
 //*****************************************************************************
 //
-// General-Purpose Input/Outputs (AHB)
+// GPIO registers (PORTC AHB)
 //
 //*****************************************************************************
 #define GPIO_PORTC_AHB_DATA_BITS_R \
@@ -1439,7 +1436,7 @@
 
 //*****************************************************************************
 //
-// General-Purpose Input/Outputs (AHB)
+// GPIO registers (PORTD AHB)
 //
 //*****************************************************************************
 #define GPIO_PORTD_AHB_DATA_BITS_R \
@@ -1469,7 +1466,7 @@
 
 //*****************************************************************************
 //
-// General-Purpose Input/Outputs (AHB)
+// GPIO registers (PORTE AHB)
 //
 //*****************************************************************************
 #define GPIO_PORTE_AHB_DATA_BITS_R \
@@ -1499,7 +1496,7 @@
 
 //*****************************************************************************
 //
-// General-Purpose Input/Outputs (AHB)
+// GPIO registers (PORTF AHB)
 //
 //*****************************************************************************
 #define GPIO_PORTF_AHB_DATA_BITS_R \
@@ -1529,7 +1526,7 @@
 
 //*****************************************************************************
 //
-// General-Purpose Input/Outputs (AHB)
+// GPIO registers (PORTG AHB)
 //
 //*****************************************************************************
 #define GPIO_PORTG_AHB_DATA_BITS_R \
@@ -1559,7 +1556,7 @@
 
 //*****************************************************************************
 //
-// General-Purpose Input/Outputs (AHB)
+// GPIO registers (PORTH AHB)
 //
 //*****************************************************************************
 #define GPIO_PORTH_AHB_DATA_BITS_R \
@@ -1589,7 +1586,7 @@
 
 //*****************************************************************************
 //
-// General-Purpose Input/Outputs (AHB)
+// GPIO registers (PORTJ AHB)
 //
 //*****************************************************************************
 #define GPIO_PORTJ_AHB_DATA_BITS_R \
@@ -1619,16 +1616,17 @@
 
 //*****************************************************************************
 //
-// External Peripheral Interface (EPI0)
+// External Peripheral Interface registers (EPI0)
 //
 //*****************************************************************************
 #define EPI0_CFG_R              (*((volatile unsigned long *)0x400D0000))
 #define EPI0_BAUD_R             (*((volatile unsigned long *)0x400D0004))
-#define EPI0_SDRAMCFG_R         (*((volatile unsigned long *)0x400D0010))
+#define EPI0_HB16CFG_R          (*((volatile unsigned long *)0x400D0010))
 #define EPI0_GPCFG_R            (*((volatile unsigned long *)0x400D0010))
+#define EPI0_SDRAMCFG_R         (*((volatile unsigned long *)0x400D0010))
 #define EPI0_HB8CFG_R           (*((volatile unsigned long *)0x400D0010))
-#define EPI0_SDRAMCFG2_R        (*((volatile unsigned long *)0x400D0014))
 #define EPI0_HB8CFG2_R          (*((volatile unsigned long *)0x400D0014))
+#define EPI0_HB16CFG2_R         (*((volatile unsigned long *)0x400D0014))
 #define EPI0_GPCFG2_R           (*((volatile unsigned long *)0x400D0014))
 #define EPI0_ADDRMAP_R          (*((volatile unsigned long *)0x400D001C))
 #define EPI0_RSIZE0_R           (*((volatile unsigned long *)0x400D0020))
@@ -1656,7 +1654,7 @@
 
 //*****************************************************************************
 //
-// Internal Memory (FLASH)
+// FLASH registers (FLASH CTRL)
 //
 //*****************************************************************************
 #define FLASH_FMA_R             (*((volatile unsigned long *)0x400FD000))
@@ -1667,10 +1665,12 @@
 #define FLASH_FCMISC_R          (*((volatile unsigned long *)0x400FD014))
 #define FLASH_FMC2_R            (*((volatile unsigned long *)0x400FD020))
 #define FLASH_FWBVAL_R          (*((volatile unsigned long *)0x400FD030))
+#define FLASH_FCTL_R            (*((volatile unsigned long *)0x400FD0F8))
 #define FLASH_FWBN_R            (*((volatile unsigned long *)0x400FD100))
 #define FLASH_RMCTL_R           (*((volatile unsigned long *)0x400FE0F0))
 #define FLASH_RMVER_R           (*((volatile unsigned long *)0x400FE0F4))
 #define FLASH_USERDBG_R         (*((volatile unsigned long *)0x400FE1D0))
+#define FLASH_BOOTCFG_R         (*((volatile unsigned long *)0x400FE1D0))
 #define FLASH_USERREG0_R        (*((volatile unsigned long *)0x400FE1E0))
 #define FLASH_USERREG1_R        (*((volatile unsigned long *)0x400FE1E4))
 #define FLASH_USERREG2_R        (*((volatile unsigned long *)0x400FE1E8))
@@ -1686,7 +1686,7 @@
 
 //*****************************************************************************
 //
-// System Control (SYSCTL)
+// System Control registers (SYSCTL)
 //
 //*****************************************************************************
 #define SYSCTL_DID0_R           (*((volatile unsigned long *)0x400FE000))
@@ -1723,7 +1723,6 @@
 #define SYSCTL_DCGC1_R          (*((volatile unsigned long *)0x400FE124))
 #define SYSCTL_DCGC2_R          (*((volatile unsigned long *)0x400FE128))
 #define SYSCTL_DSLPCLKCFG_R     (*((volatile unsigned long *)0x400FE144))
-#define SYSCTL_DSFLASHCFG_R     (*((volatile unsigned long *)0x400FE14C))
 #define SYSCTL_PIOSCCAL_R       (*((volatile unsigned long *)0x400FE150))
 #define SYSCTL_I2SMCLKCFG_R     (*((volatile unsigned long *)0x400FE170))
 #define SYSCTL_DC9_R            (*((volatile unsigned long *)0x400FE190))
@@ -1731,7 +1730,7 @@
 
 //*****************************************************************************
 //
-// Micro Direct Memory Access (UDMA)
+// Micro Direct Memory Access registers (UDMA)
 //
 //*****************************************************************************
 #define UDMA_STAT_R             (*((volatile unsigned long *)0x400FF000))
@@ -1751,24 +1750,26 @@
 #define UDMA_PRIOSET_R          (*((volatile unsigned long *)0x400FF038))
 #define UDMA_PRIOCLR_R          (*((volatile unsigned long *)0x400FF03C))
 #define UDMA_ERRCLR_R           (*((volatile unsigned long *)0x400FF04C))
-#define UDMA_CHALT_R            (*((volatile unsigned long *)0x400FF500))
-#define UDMA_CHIS_R             (*((volatile unsigned long *)0x400FF504))
+#define UDMA_CHASGN_R           (*((volatile unsigned long *)0x400FF500))
 
 //*****************************************************************************
 //
-// Micro Direct Memory Access (UDMA) Offsets
+// Micro Direct Memory Access (uDMA) offsets (UDMA)
 //
 //*****************************************************************************
-#define UDMA_SRCENDP            0x0x00000000
-#define UDMA_DSTENDP            0x0x00000004
-#define UDMA_CHCTL              0x0x00000008
+#define UDMA_SRCENDP            0x00000000  // DMA Channel Source Address End
+                                            // Pointer
+#define UDMA_DSTENDP            0x00000004  // DMA Channel Destination Address
+                                            // End Pointer
+#define UDMA_CHCTL              0x00000008  // DMA Channel Control Word
 
 //*****************************************************************************
 //
-// Nested Vectored Interrupt Ctrl (NVIC)
+// NVIC registers (NVIC)
 //
 //*****************************************************************************
 #define NVIC_INT_TYPE_R         (*((volatile unsigned long *)0xE000E004))
+#define NVIC_ACTLR_R            (*((volatile unsigned long *)0xE000E008))
 #define NVIC_ST_CTRL_R          (*((volatile unsigned long *)0xE000E010))
 #define NVIC_ST_RELOAD_R        (*((volatile unsigned long *)0xE000E014))
 #define NVIC_ST_CURRENT_R       (*((volatile unsigned long *)0xE000E018))
@@ -1815,8 +1816,14 @@
 #define NVIC_MPU_TYPE_R         (*((volatile unsigned long *)0xE000ED90))
 #define NVIC_MPU_CTRL_R         (*((volatile unsigned long *)0xE000ED94))
 #define NVIC_MPU_NUMBER_R       (*((volatile unsigned long *)0xE000ED98))
-#define NVIC_MPU_R              (*((volatile unsigned long *)0xE000ED9C))
+#define NVIC_MPU_BASE_R         (*((volatile unsigned long *)0xE000ED9C))
 #define NVIC_MPU_ATTR_R         (*((volatile unsigned long *)0xE000EDA0))
+#define NVIC_MPU_BASE1_R        (*((volatile unsigned long *)0xE000EDA4))
+#define NVIC_MPU_ATTR1_R        (*((volatile unsigned long *)0xE000EDA8))
+#define NVIC_MPU_BASE2_R        (*((volatile unsigned long *)0xE000EDAC))
+#define NVIC_MPU_ATTR2_R        (*((volatile unsigned long *)0xE000EDB0))
+#define NVIC_MPU_BASE3_R        (*((volatile unsigned long *)0xE000EDB4))
+#define NVIC_MPU_ATTR3_R        (*((volatile unsigned long *)0xE000EDB8))
 #define NVIC_DBG_CTRL_R         (*((volatile unsigned long *)0xE000EDF0))
 #define NVIC_DBG_XFER_R         (*((volatile unsigned long *)0xE000EDF4))
 #define NVIC_DBG_DATA_R         (*((volatile unsigned long *)0xE000EDF8))
@@ -1828,7 +1835,7 @@
 // The following are defines for the bit fields in the WDT_O_LOAD register.
 //
 //*****************************************************************************
-#define WDT_LOAD_M              0xFFFFFFFF  // Watchdog Load Value.
+#define WDT_LOAD_M              0xFFFFFFFF  // Watchdog Load Value
 #define WDT_LOAD_S              0
 
 //*****************************************************************************
@@ -1836,7 +1843,7 @@
 // The following are defines for the bit fields in the WDT_O_VALUE register.
 //
 //*****************************************************************************
-#define WDT_VALUE_M             0xFFFFFFFF  // Watchdog Value.
+#define WDT_VALUE_M             0xFFFFFFFF  // Watchdog Value
 #define WDT_VALUE_S             0
 
 //*****************************************************************************
@@ -1844,16 +1851,16 @@
 // The following are defines for the bit fields in the WDT_O_CTL register.
 //
 //*****************************************************************************
-#define WDT_CTL_WRC             0x80000000  // Write Complete.
-#define WDT_CTL_RESEN           0x00000002  // Watchdog Reset Enable.
-#define WDT_CTL_INTEN           0x00000001  // Watchdog Interrupt Enable.
+#define WDT_CTL_WRC             0x80000000  // Write Complete
+#define WDT_CTL_RESEN           0x00000002  // Watchdog Reset Enable
+#define WDT_CTL_INTEN           0x00000001  // Watchdog Interrupt Enable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the WDT_O_ICR register.
 //
 //*****************************************************************************
-#define WDT_ICR_M               0xFFFFFFFF  // Watchdog Interrupt Clear.
+#define WDT_ICR_M               0xFFFFFFFF  // Watchdog Interrupt Clear
 #define WDT_ICR_S               0
 
 //*****************************************************************************
@@ -1861,58 +1868,473 @@
 // The following are defines for the bit fields in the WDT_O_RIS register.
 //
 //*****************************************************************************
-#define WDT_RIS_WDTRIS          0x00000001  // Watchdog Raw Interrupt Status.
+#define WDT_RIS_WDTRIS          0x00000001  // Watchdog Raw Interrupt Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the WDT_O_MIS register.
 //
 //*****************************************************************************
-#define WDT_MIS_WDTMIS          0x00000001  // Watchdog Masked Interrupt
-                                            // Status.
+#define WDT_MIS_WDTMIS          0x00000001  // Watchdog Masked Interrupt Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the WDT_O_TEST register.
 //
 //*****************************************************************************
-#define WDT_TEST_STALL          0x00000100  // Watchdog Stall Enable.
+#define WDT_TEST_STALL          0x00000100  // Watchdog Stall Enable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the WDT_O_LOCK register.
 //
 //*****************************************************************************
-#define WDT_LOCK_M              0xFFFFFFFF  // Watchdog Lock.
+#define WDT_LOCK_M              0xFFFFFFFF  // Watchdog Lock
 #define WDT_LOCK_UNLOCKED       0x00000000  // Unlocked
 #define WDT_LOCK_LOCKED         0x00000001  // Locked
+#define WDT_LOCK_UNLOCK         0x1ACCE551  // Unlocks the watchdog timer
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the GPIO_O_LOCK register.
 //
 //*****************************************************************************
-#define GPIO_LOCK_M             0xFFFFFFFF  // GPIO Lock.
+#define GPIO_LOCK_M             0xFFFFFFFF  // GPIO Lock
 #define GPIO_LOCK_UNLOCKED      0x00000000  // The GPIOCR register is unlocked
-                                            // and may be modified.
+                                            // and may be modified
 #define GPIO_LOCK_LOCKED        0x00000001  // The GPIOCR register is locked
-                                            // and may not be modified.
+                                            // and may not be modified
 #define GPIO_LOCK_KEY           0x4C4F434B  // Unlocks the GPIO_CR register
 
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_PCTL register for
+// port A.
+//
+//*****************************************************************************
+#define GPIO_PCTL_PA7_M         0xF0000000  // PA7 mask
+#define GPIO_PCTL_PA7_I2C1SDA   0x10000000  // I2C1SDA on PA7
+#define GPIO_PCTL_PA7_CCP4      0x20000000  // CCP4 on PA7
+#define GPIO_PCTL_PA7_PWM1      0x40000000  // PWM1 on PA7
+#define GPIO_PCTL_PA7_PWM5      0x50000000  // PWM5 on PA7
+#define GPIO_PCTL_PA7_CAN0TX    0x60000000  // CAN0TX on PA7
+#define GPIO_PCTL_PA7_CCP3      0x70000000  // CCP3 on PA7
+#define GPIO_PCTL_PA7_USB0PFLT  0x80000000  // USB0PFLT on PA7
+#define GPIO_PCTL_PA7_U1DCD     0x90000000  // U1DCD on PA7
+#define GPIO_PCTL_PA6_M         0x0F000000  // PA6 mask
+#define GPIO_PCTL_PA6_I2C1SCL   0x01000000  // I2C1SCL on PA6
+#define GPIO_PCTL_PA6_CCP1      0x02000000  // CCP1 on PA6
+#define GPIO_PCTL_PA6_PWM0      0x04000000  // PWM0 on PA6
+#define GPIO_PCTL_PA6_PWM4      0x05000000  // PWM4 on PA6
+#define GPIO_PCTL_PA6_CAN0RX    0x06000000  // CAN0RX on PA6
+#define GPIO_PCTL_PA6_USB0EPEN  0x08000000  // USB0EPEN on PA6
+#define GPIO_PCTL_PA6_U1CTS     0x09000000  // U1CTS on PA6
+#define GPIO_PCTL_PA5_M         0x00F00000  // PA5 mask
+#define GPIO_PCTL_PA5_SSI0TX    0x00100000  // SSI0TX on PA5
+#define GPIO_PCTL_PA5_PWM7      0x00400000  // PWM7 on PA5
+#define GPIO_PCTL_PA5_CAN0TX    0x00500000  // CAN0TX on PA5
+#define GPIO_PCTL_PA5_I2S0TXWS  0x00900000  // I2S0TXWS on PA5
+#define GPIO_PCTL_PA4_M         0x000F0000  // PA4 mask
+#define GPIO_PCTL_PA4_SSI0RX    0x00010000  // SSI0RX on PA4
+#define GPIO_PCTL_PA4_PWM6      0x00040000  // PWM6 on PA4
+#define GPIO_PCTL_PA4_CAN0RX    0x00050000  // CAN0RX on PA4
+#define GPIO_PCTL_PA4_I2S0TXSCK 0x00090000  // I2S0TXSCK on PA4
+#define GPIO_PCTL_PA3_M         0x0000F000  // PA3 mask
+#define GPIO_PCTL_PA3_SSI0FSS   0x00001000  // SSI0FSS on PA3
+#define GPIO_PCTL_PA3_PWM5      0x00004000  // PWM5 on PA3
+#define GPIO_PCTL_PA3_I2S0RXMCLK \
+                                0x00009000  // I2S0RXMCLK on PA3
+#define GPIO_PCTL_PA2_M         0x00000F00  // PA2 mask
+#define GPIO_PCTL_PA2_SSI0CLK   0x00000100  // SSI0CLK on PA2
+#define GPIO_PCTL_PA2_PWM4      0x00000400  // PWM4 on PA2
+#define GPIO_PCTL_PA2_I2S0RXSD  0x00000900  // I2S0RXSD on PA2
+#define GPIO_PCTL_PA1_M         0x000000F0  // PA1 mask
+#define GPIO_PCTL_PA1_U0TX      0x00000010  // U0TX on PA1
+#define GPIO_PCTL_PA1_I2C1SDA   0x00000080  // I2C1SDA on PA1
+#define GPIO_PCTL_PA1_U1TX      0x00000090  // U1TX on PA1
+#define GPIO_PCTL_PA0_M         0x0000000F  // PA0 mask
+#define GPIO_PCTL_PA0_U0RX      0x00000001  // U0RX on PA0
+#define GPIO_PCTL_PA0_I2C1SCL   0x00000008  // I2C1SCL on PA0
+#define GPIO_PCTL_PA0_U1RX      0x00000009  // U1RX on PA0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_PCTL register for
+// port B.
+//
+//*****************************************************************************
+#define GPIO_PCTL_PB7_M         0xF0000000  // PB7 mask
+#define GPIO_PCTL_PB7_NMI       0x40000000  // NMI on PB7
+#define GPIO_PCTL_PB6_M         0x0F000000  // PB6 mask
+#define GPIO_PCTL_PB6_CCP1      0x01000000  // CCP1 on PB6
+#define GPIO_PCTL_PB6_CCP7      0x02000000  // CCP7 on PB6
+#define GPIO_PCTL_PB6_C0O       0x03000000  // C0O on PB6
+#define GPIO_PCTL_PB6_FAULT1    0x04000000  // FAULT1 on PB6
+#define GPIO_PCTL_PB6_IDX0      0x05000000  // IDX0 on PB6
+#define GPIO_PCTL_PB6_CCP5      0x06000000  // CCP5 on PB6
+#define GPIO_PCTL_PB6_I2S0TXSCK 0x09000000  // I2S0TXSCK on PB6
+#define GPIO_PCTL_PB5_M         0x00F00000  // PB5 mask
+#define GPIO_PCTL_PB5_C0O       0x00100000  // C0O on PB5
+#define GPIO_PCTL_PB5_CCP5      0x00200000  // CCP5 on PB5
+#define GPIO_PCTL_PB5_CCP6      0x00300000  // CCP6 on PB5
+#define GPIO_PCTL_PB5_CCP0      0x00400000  // CCP0 on PB5
+#define GPIO_PCTL_PB5_CAN0TX    0x00500000  // CAN0TX on PB5
+#define GPIO_PCTL_PB5_CCP2      0x00600000  // CCP2 on PB5
+#define GPIO_PCTL_PB5_U1TX      0x00700000  // U1TX on PB5
+#define GPIO_PCTL_PB5_EPI0S22   0x00800000  // EPI0S22 on PB5
+#define GPIO_PCTL_PB4_M         0x000F0000  // PB4 mask
+#define GPIO_PCTL_PB4_U2RX      0x00040000  // U2RX on PB4
+#define GPIO_PCTL_PB4_CAN0RX    0x00050000  // CAN0RX on PB4
+#define GPIO_PCTL_PB4_IDX0      0x00060000  // IDX0 on PB4
+#define GPIO_PCTL_PB4_U1RX      0x00070000  // U1RX on PB4
+#define GPIO_PCTL_PB4_EPI0S23   0x00080000  // EPI0S23 on PB4
+#define GPIO_PCTL_PB3_M         0x0000F000  // PB3 mask
+#define GPIO_PCTL_PB3_I2C0SDA   0x00001000  // I2C0SDA on PB3
+#define GPIO_PCTL_PB3_FAULT0    0x00002000  // FAULT0 on PB3
+#define GPIO_PCTL_PB3_FAULT3    0x00004000  // FAULT3 on PB3
+#define GPIO_PCTL_PB3_USB0PFLT  0x00008000  // USB0PFLT on PB3
+#define GPIO_PCTL_PB2_M         0x00000F00  // PB2 mask
+#define GPIO_PCTL_PB2_I2C0SCL   0x00000100  // I2C0SCL on PB2
+#define GPIO_PCTL_PB2_IDX0      0x00000200  // IDX0 on PB2
+#define GPIO_PCTL_PB2_CCP3      0x00000400  // CCP3 on PB2
+#define GPIO_PCTL_PB2_CCP0      0x00000500  // CCP0 on PB2
+#define GPIO_PCTL_PB2_USB0EPEN  0x00000800  // USB0EPEN on PB2
+#define GPIO_PCTL_PB1_M         0x000000F0  // PB1 mask
+#define GPIO_PCTL_PB1_CCP2      0x00000010  // CCP2 on PB1
+#define GPIO_PCTL_PB1_PWM3      0x00000020  // PWM3 on PB1
+#define GPIO_PCTL_PB1_CCP1      0x00000040  // CCP1 on PB1
+#define GPIO_PCTL_PB1_U1TX      0x00000050  // U1TX on PB1
+#define GPIO_PCTL_PB0_M         0x0000000F  // PB0 mask
+#define GPIO_PCTL_PB0_CCP0      0x00000001  // CCP0 on PB0
+#define GPIO_PCTL_PB0_PWM2      0x00000002  // PWM2 on PB0
+#define GPIO_PCTL_PB0_U1RX      0x00000005  // U1RX on PB0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_PCTL register for
+// port C.
+//
+//*****************************************************************************
+#define GPIO_PCTL_PC7_M         0xF0000000  // PC7 mask
+#define GPIO_PCTL_PC7_CCP4      0x10000000  // CCP4 on PC7
+#define GPIO_PCTL_PC7_PHB0      0x20000000  // PHB0 on PC7
+#define GPIO_PCTL_PC7_CCP0      0x40000000  // CCP0 on PC7
+#define GPIO_PCTL_PC7_U1TX      0x50000000  // U1TX on PC7
+#define GPIO_PCTL_PC7_USB0PFLT  0x60000000  // USB0PFLT on PC7
+#define GPIO_PCTL_PC7_C1O       0x70000000  // C1O on PC7
+#define GPIO_PCTL_PC7_EPI0S5    0x80000000  // EPI0S5 on PC7
+#define GPIO_PCTL_PC6_M         0x0F000000  // PC6 mask
+#define GPIO_PCTL_PC6_CCP3      0x01000000  // CCP3 on PC6
+#define GPIO_PCTL_PC6_PHB0      0x02000000  // PHB0 on PC6
+#define GPIO_PCTL_PC6_C2O       0x03000000  // C2O on PC6
+#define GPIO_PCTL_PC6_PWM7      0x04000000  // PWM7 on PC6
+#define GPIO_PCTL_PC6_U1RX      0x05000000  // U1RX on PC6
+#define GPIO_PCTL_PC6_CCP0      0x06000000  // CCP0 on PC6
+#define GPIO_PCTL_PC6_USB0PFLT  0x07000000  // USB0PFLT on PC6
+#define GPIO_PCTL_PC6_EPI0S4    0x08000000  // EPI0S4 on PC6
+#define GPIO_PCTL_PC5_M         0x00F00000  // PC5 mask
+#define GPIO_PCTL_PC5_CCP1      0x00100000  // CCP1 on PC5
+#define GPIO_PCTL_PC5_C1O       0x00200000  // C1O on PC5
+#define GPIO_PCTL_PC5_C0O       0x00300000  // C0O on PC5
+#define GPIO_PCTL_PC5_FAULT2    0x00400000  // FAULT2 on PC5
+#define GPIO_PCTL_PC5_CCP3      0x00500000  // CCP3 on PC5
+#define GPIO_PCTL_PC5_USB0EPEN  0x00600000  // USB0EPEN on PC5
+#define GPIO_PCTL_PC5_EPI0S3    0x00800000  // EPI0S3 on PC5
+#define GPIO_PCTL_PC4_M         0x000F0000  // PC4 mask
+#define GPIO_PCTL_PC4_CCP5      0x00010000  // CCP5 on PC4
+#define GPIO_PCTL_PC4_PHA0      0x00020000  // PHA0 on PC4
+#define GPIO_PCTL_PC4_PWM6      0x00040000  // PWM6 on PC4
+#define GPIO_PCTL_PC4_CCP2      0x00050000  // CCP2 on PC4
+#define GPIO_PCTL_PC4_CCP4      0x00060000  // CCP4 on PC4
+#define GPIO_PCTL_PC4_EPI0S2    0x00080000  // EPI0S2 on PC4
+#define GPIO_PCTL_PC4_CCP1      0x00090000  // CCP1 on PC4
+#define GPIO_PCTL_PC3_M         0x0000F000  // PC3 mask
+#define GPIO_PCTL_PC3_TDO       0x00003000  // TDO on PC3
+#define GPIO_PCTL_PC2_M         0x00000F00  // PC2 mask
+#define GPIO_PCTL_PC2_TDI       0x00000300  // TDI on PC2
+#define GPIO_PCTL_PC1_M         0x000000F0  // PC1 mask
+#define GPIO_PCTL_PC1_TMS       0x00000030  // TMS on PC1
+#define GPIO_PCTL_PC0_M         0x0000000F  // PC0 mask
+#define GPIO_PCTL_PC0_TCK       0x00000003  // TCK on PC0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_PCTL register for
+// port D.
+//
+//*****************************************************************************
+#define GPIO_PCTL_PD7_M         0xF0000000  // PD7 mask
+#define GPIO_PCTL_PD7_IDX0      0x10000000  // IDX0 on PD7
+#define GPIO_PCTL_PD7_C0O       0x20000000  // C0O on PD7
+#define GPIO_PCTL_PD7_CCP1      0x30000000  // CCP1 on PD7
+#define GPIO_PCTL_PD7_I2S0TXWS  0x80000000  // I2S0TXWS on PD7
+#define GPIO_PCTL_PD7_U1DTR     0x90000000  // U1DTR on PD7
+#define GPIO_PCTL_PD7_EPI0S30   0xA0000000  // EPI0S30 on PD7
+#define GPIO_PCTL_PD6_M         0x0F000000  // PD6 mask
+#define GPIO_PCTL_PD6_FAULT0    0x01000000  // FAULT0 on PD6
+#define GPIO_PCTL_PD6_I2S0TXSCK 0x08000000  // I2S0TXSCK on PD6
+#define GPIO_PCTL_PD6_U2TX      0x09000000  // U2TX on PD6
+#define GPIO_PCTL_PD6_EPI0S29   0x0A000000  // EPI0S29 on PD6
+#define GPIO_PCTL_PD5_M         0x00F00000  // PD5 mask
+#define GPIO_PCTL_PD5_CCP2      0x00100000  // CCP2 on PD5
+#define GPIO_PCTL_PD5_CCP4      0x00200000  // CCP4 on PD5
+#define GPIO_PCTL_PD5_I2S0RXMCLK \
+                                0x00800000  // I2S0RXMCLK on PD5
+#define GPIO_PCTL_PD5_U2RX      0x00900000  // U2RX on PD5
+#define GPIO_PCTL_PD5_EPI0S28   0x00A00000  // EPI0S28 on PD5
+#define GPIO_PCTL_PD4_M         0x000F0000  // PD4 mask
+#define GPIO_PCTL_PD4_CCP0      0x00010000  // CCP0 on PD4
+#define GPIO_PCTL_PD4_CCP3      0x00020000  // CCP3 on PD4
+#define GPIO_PCTL_PD4_I2S0RXSD  0x00080000  // I2S0RXSD on PD4
+#define GPIO_PCTL_PD4_U1RI      0x00090000  // U1RI on PD4
+#define GPIO_PCTL_PD4_EPI0S19   0x000A0000  // EPI0S19 on PD4
+#define GPIO_PCTL_PD3_M         0x0000F000  // PD3 mask
+#define GPIO_PCTL_PD3_U1TX      0x00001000  // U1TX on PD3
+#define GPIO_PCTL_PD3_CCP7      0x00002000  // CCP7 on PD3
+#define GPIO_PCTL_PD3_PWM3      0x00003000  // PWM3 on PD3
+#define GPIO_PCTL_PD3_CCP0      0x00004000  // CCP0 on PD3
+#define GPIO_PCTL_PD3_EPI0S21   0x00008000  // EPI0S21 on PD3
+#define GPIO_PCTL_PD2_M         0x00000F00  // PD2 mask
+#define GPIO_PCTL_PD2_U1RX      0x00000100  // U1RX on PD2
+#define GPIO_PCTL_PD2_CCP6      0x00000200  // CCP6 on PD2
+#define GPIO_PCTL_PD2_PWM2      0x00000300  // PWM2 on PD2
+#define GPIO_PCTL_PD2_CCP5      0x00000400  // CCP5 on PD2
+#define GPIO_PCTL_PD2_EPI0S20   0x00000800  // EPI0S20 on PD2
+#define GPIO_PCTL_PD1_M         0x000000F0  // PD1 mask
+#define GPIO_PCTL_PD1_PWM1      0x00000010  // PWM1 on PD1
+#define GPIO_PCTL_PD1_CAN0TX    0x00000020  // CAN0TX on PD1
+#define GPIO_PCTL_PD1_PHA0      0x00000030  // PHA0 on PD1
+#define GPIO_PCTL_PD1_U2TX      0x00000040  // U2TX on PD1
+#define GPIO_PCTL_PD1_U1TX      0x00000050  // U1TX on PD1
+#define GPIO_PCTL_PD1_CCP7      0x00000060  // CCP7 on PD1
+#define GPIO_PCTL_PD1_I2S0RXWS  0x00000080  // I2S0RXWS on PD1
+#define GPIO_PCTL_PD1_U1DCD     0x00000090  // U1DCD on PD1
+#define GPIO_PCTL_PD1_CCP2      0x000000A0  // CCP2 on PD1
+#define GPIO_PCTL_PD1_PHB1      0x000000B0  // PHB1 on PD1
+#define GPIO_PCTL_PD0_M         0x0000000F  // PD0 mask
+#define GPIO_PCTL_PD0_PWM0      0x00000001  // PWM0 on PD0
+#define GPIO_PCTL_PD0_CAN0RX    0x00000002  // CAN0RX on PD0
+#define GPIO_PCTL_PD0_IDX0      0x00000003  // IDX0 on PD0
+#define GPIO_PCTL_PD0_U2RX      0x00000004  // U2RX on PD0
+#define GPIO_PCTL_PD0_U1RX      0x00000005  // U1RX on PD0
+#define GPIO_PCTL_PD0_CCP6      0x00000006  // CCP6 on PD0
+#define GPIO_PCTL_PD0_I2S0RXSCK 0x00000008  // I2S0RXSCK on PD0
+#define GPIO_PCTL_PD0_U1CTS     0x00000009  // U1CTS on PD0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_PCTL register for
+// port E.
+//
+//*****************************************************************************
+#define GPIO_PCTL_PE7_M         0xF0000000  // PE7 mask
+#define GPIO_PCTL_PE7_PWM5      0x10000000  // PWM5 on PE7
+#define GPIO_PCTL_PE7_C2O       0x20000000  // C2O on PE7
+#define GPIO_PCTL_PE7_U1DCD     0x90000000  // U1DCD on PE7
+#define GPIO_PCTL_PE6_M         0x0F000000  // PE6 mask
+#define GPIO_PCTL_PE6_PWM4      0x01000000  // PWM4 on PE6
+#define GPIO_PCTL_PE6_C1O       0x02000000  // C1O on PE6
+#define GPIO_PCTL_PE6_U1CTS     0x09000000  // U1CTS on PE6
+#define GPIO_PCTL_PE5_M         0x00F00000  // PE5 mask
+#define GPIO_PCTL_PE5_CCP5      0x00100000  // CCP5 on PE5
+#define GPIO_PCTL_PE5_I2S0TXSD  0x00900000  // I2S0TXSD on PE5
+#define GPIO_PCTL_PE4_M         0x000F0000  // PE4 mask
+#define GPIO_PCTL_PE4_CCP3      0x00010000  // CCP3 on PE4
+#define GPIO_PCTL_PE4_FAULT0    0x00040000  // FAULT0 on PE4
+#define GPIO_PCTL_PE4_U2TX      0x00050000  // U2TX on PE4
+#define GPIO_PCTL_PE4_CCP2      0x00060000  // CCP2 on PE4
+#define GPIO_PCTL_PE4_I2S0TXWS  0x00090000  // I2S0TXWS on PE4
+#define GPIO_PCTL_PE3_M         0x0000F000  // PE3 mask
+#define GPIO_PCTL_PE3_CCP1      0x00001000  // CCP1 on PE3
+#define GPIO_PCTL_PE3_SSI1TX    0x00002000  // SSI1TX on PE3
+#define GPIO_PCTL_PE3_PHA1      0x00003000  // PHA1 on PE3
+#define GPIO_PCTL_PE3_PHB0      0x00004000  // PHB0 on PE3
+#define GPIO_PCTL_PE3_CCP7      0x00005000  // CCP7 on PE3
+#define GPIO_PCTL_PE3_EPI0S25   0x00008000  // EPI0S25 on PE3
+#define GPIO_PCTL_PE2_M         0x00000F00  // PE2 mask
+#define GPIO_PCTL_PE2_CCP4      0x00000100  // CCP4 on PE2
+#define GPIO_PCTL_PE2_SSI1RX    0x00000200  // SSI1RX on PE2
+#define GPIO_PCTL_PE2_PHB1      0x00000300  // PHB1 on PE2
+#define GPIO_PCTL_PE2_PHA0      0x00000400  // PHA0 on PE2
+#define GPIO_PCTL_PE2_CCP2      0x00000500  // CCP2 on PE2
+#define GPIO_PCTL_PE2_EPI0S24   0x00000800  // EPI0S24 on PE2
+#define GPIO_PCTL_PE1_M         0x000000F0  // PE1 mask
+#define GPIO_PCTL_PE1_PWM5      0x00000010  // PWM5 on PE1
+#define GPIO_PCTL_PE1_SSI1FSS   0x00000020  // SSI1FSS on PE1
+#define GPIO_PCTL_PE1_FAULT0    0x00000030  // FAULT0 on PE1
+#define GPIO_PCTL_PE1_CCP2      0x00000040  // CCP2 on PE1
+#define GPIO_PCTL_PE1_CCP6      0x00000050  // CCP6 on PE1
+#define GPIO_PCTL_PE1_EPI0S9    0x00000080  // EPI0S9 on PE1
+#define GPIO_PCTL_PE0_M         0x0000000F  // PE0 mask
+#define GPIO_PCTL_PE0_PWM4      0x00000001  // PWM4 on PE0
+#define GPIO_PCTL_PE0_SSI1CLK   0x00000002  // SSI1CLK on PE0
+#define GPIO_PCTL_PE0_CCP3      0x00000003  // CCP3 on PE0
+#define GPIO_PCTL_PE0_EPI0S8    0x00000008  // EPI0S8 on PE0
+#define GPIO_PCTL_PE0_USB0PFLT  0x00000009  // USB0PFLT on PE0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_PCTL register for
+// port F.
+//
+//*****************************************************************************
+#define GPIO_PCTL_PF5_M         0x00F00000  // PF5 mask
+#define GPIO_PCTL_PF5_CCP2      0x00100000  // CCP2 on PF5
+#define GPIO_PCTL_PF5_C1O       0x00200000  // C1O on PF5
+#define GPIO_PCTL_PF5_EPI0S15   0x00800000  // EPI0S15 on PF5
+#define GPIO_PCTL_PF5_SSI1TX    0x00900000  // SSI1TX on PF5
+#define GPIO_PCTL_PF4_M         0x000F0000  // PF4 mask
+#define GPIO_PCTL_PF4_CCP0      0x00010000  // CCP0 on PF4
+#define GPIO_PCTL_PF4_C0O       0x00020000  // C0O on PF4
+#define GPIO_PCTL_PF4_FAULT0    0x00040000  // FAULT0 on PF4
+#define GPIO_PCTL_PF4_EPI0S12   0x00080000  // EPI0S12 on PF4
+#define GPIO_PCTL_PF4_SSI1RX    0x00090000  // SSI1RX on PF4
+#define GPIO_PCTL_PF3_M         0x0000F000  // PF3 mask
+#define GPIO_PCTL_PF3_LED0      0x00001000  // LED0 on PF3
+#define GPIO_PCTL_PF3_PWM5      0x00002000  // PWM5 on PF3
+#define GPIO_PCTL_PF3_PWM3      0x00004000  // PWM3 on PF3
+#define GPIO_PCTL_PF3_SSI1FSS   0x00009000  // SSI1FSS on PF3
+#define GPIO_PCTL_PF2_M         0x00000F00  // PF2 mask
+#define GPIO_PCTL_PF2_LED1      0x00000100  // LED1 on PF2
+#define GPIO_PCTL_PF2_PWM4      0x00000200  // PWM4 on PF2
+#define GPIO_PCTL_PF2_PWM2      0x00000400  // PWM2 on PF2
+#define GPIO_PCTL_PF2_SSI1CLK   0x00000900  // SSI1CLK on PF2
+#define GPIO_PCTL_PF1_M         0x000000F0  // PF1 mask
+#define GPIO_PCTL_PF1_CAN1TX    0x00000010  // CAN1TX on PF1
+#define GPIO_PCTL_PF1_IDX1      0x00000020  // IDX1 on PF1
+#define GPIO_PCTL_PF1_PWM1      0x00000030  // PWM1 on PF1
+#define GPIO_PCTL_PF1_I2S0TXMCLK \
+                                0x00000080  // I2S0TXMCLK on PF1
+#define GPIO_PCTL_PF1_U1RTS     0x00000090  // U1RTS on PF1
+#define GPIO_PCTL_PF1_CCP3      0x000000A0  // CCP3 on PF1
+#define GPIO_PCTL_PF0_M         0x0000000F  // PF0 mask
+#define GPIO_PCTL_PF0_CAN1RX    0x00000001  // CAN1RX on PF0
+#define GPIO_PCTL_PF0_PHB0      0x00000002  // PHB0 on PF0
+#define GPIO_PCTL_PF0_PWM0      0x00000003  // PWM0 on PF0
+#define GPIO_PCTL_PF0_I2S0TXSD  0x00000008  // I2S0TXSD on PF0
+#define GPIO_PCTL_PF0_U1DSR     0x00000009  // U1DSR on PF0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_PCTL register for
+// port G.
+//
+//*****************************************************************************
+#define GPIO_PCTL_PG7_M         0xF0000000  // PG7 mask
+#define GPIO_PCTL_PG7_PHB1      0x10000000  // PHB1 on PG7
+#define GPIO_PCTL_PG7_PWM7      0x40000000  // PWM7 on PG7
+#define GPIO_PCTL_PG7_CCP5      0x80000000  // CCP5 on PG7
+#define GPIO_PCTL_PG7_EPI0S31   0x90000000  // EPI0S31 on PG7
+#define GPIO_PCTL_PG1_M         0x000000F0  // PG1 mask
+#define GPIO_PCTL_PG1_U2TX      0x00000010  // U2TX on PG1
+#define GPIO_PCTL_PG1_PWM1      0x00000020  // PWM1 on PG1
+#define GPIO_PCTL_PG1_I2C1SDA   0x00000030  // I2C1SDA on PG1
+#define GPIO_PCTL_PG1_PWM5      0x00000040  // PWM5 on PG1
+#define GPIO_PCTL_PG1_EPI0S14   0x00000080  // EPI0S14 on PG1
+#define GPIO_PCTL_PG0_M         0x0000000F  // PG0 mask
+#define GPIO_PCTL_PG0_U2RX      0x00000001  // U2RX on PG0
+#define GPIO_PCTL_PG0_PWM0      0x00000002  // PWM0 on PG0
+#define GPIO_PCTL_PG0_I2C1SCL   0x00000003  // I2C1SCL on PG0
+#define GPIO_PCTL_PG0_PWM4      0x00000004  // PWM4 on PG0
+#define GPIO_PCTL_PG0_USB0EPEN  0x00000007  // USB0EPEN on PG0
+#define GPIO_PCTL_PG0_EPI0S13   0x00000008  // EPI0S13 on PG0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_PCTL register for
+// port H.
+//
+//*****************************************************************************
+#define GPIO_PCTL_PH7_M         0xF0000000  // PH7 mask
+#define GPIO_PCTL_PH7_EPI0S27   0x80000000  // EPI0S27 on PH7
+#define GPIO_PCTL_PH7_PWM5      0xA0000000  // PWM5 on PH7
+#define GPIO_PCTL_PH7_SSI1TX    0xB0000000  // SSI1TX on PH7
+#define GPIO_PCTL_PH6_M         0x0F000000  // PH6 mask
+#define GPIO_PCTL_PH6_EPI0S26   0x08000000  // EPI0S26 on PH6
+#define GPIO_PCTL_PH6_PWM4      0x0A000000  // PWM4 on PH6
+#define GPIO_PCTL_PH6_SSI1RX    0x0B000000  // SSI1RX on PH6
+#define GPIO_PCTL_PH5_M         0x00F00000  // PH5 mask
+#define GPIO_PCTL_PH5_EPI0S11   0x00800000  // EPI0S11 on PH5
+#define GPIO_PCTL_PH5_FAULT2    0x00A00000  // FAULT2 on PH5
+#define GPIO_PCTL_PH5_SSI1FSS   0x00B00000  // SSI1FSS on PH5
+#define GPIO_PCTL_PH4_M         0x000F0000  // PH4 mask
+#define GPIO_PCTL_PH4_USB0PFLT  0x00040000  // USB0PFLT on PH4
+#define GPIO_PCTL_PH4_EPI0S10   0x00080000  // EPI0S10 on PH4
+#define GPIO_PCTL_PH4_SSI1CLK   0x000B0000  // SSI1CLK on PH4
+#define GPIO_PCTL_PH3_M         0x0000F000  // PH3 mask
+#define GPIO_PCTL_PH3_PHB0      0x00001000  // PHB0 on PH3
+#define GPIO_PCTL_PH3_FAULT0    0x00002000  // FAULT0 on PH3
+#define GPIO_PCTL_PH3_USB0EPEN  0x00004000  // USB0EPEN on PH3
+#define GPIO_PCTL_PH3_EPI0S0    0x00008000  // EPI0S0 on PH3
+#define GPIO_PCTL_PH2_M         0x00000F00  // PH2 mask
+#define GPIO_PCTL_PH2_IDX1      0x00000100  // IDX1 on PH2
+#define GPIO_PCTL_PH2_C1O       0x00000200  // C1O on PH2
+#define GPIO_PCTL_PH2_FAULT3    0x00000400  // FAULT3 on PH2
+#define GPIO_PCTL_PH2_EPI0S1    0x00000800  // EPI0S1 on PH2
+#define GPIO_PCTL_PH1_M         0x000000F0  // PH1 mask
+#define GPIO_PCTL_PH1_CCP7      0x00000010  // CCP7 on PH1
+#define GPIO_PCTL_PH1_PWM3      0x00000020  // PWM3 on PH1
+#define GPIO_PCTL_PH1_EPI0S7    0x00000080  // EPI0S7 on PH1
+#define GPIO_PCTL_PH1_PWM5      0x00000090  // PWM5 on PH1
+#define GPIO_PCTL_PH0_M         0x0000000F  // PH0 mask
+#define GPIO_PCTL_PH0_CCP6      0x00000001  // CCP6 on PH0
+#define GPIO_PCTL_PH0_PWM2      0x00000002  // PWM2 on PH0
+#define GPIO_PCTL_PH0_EPI0S6    0x00000008  // EPI0S6 on PH0
+#define GPIO_PCTL_PH0_PWM4      0x00000009  // PWM4 on PH0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_PCTL register for
+// port J.
+//
+//*****************************************************************************
+#define GPIO_PCTL_PJ7_M         0xF0000000  // PJ7 mask
+#define GPIO_PCTL_PJ7_U1DTR     0x90000000  // U1DTR on PJ7
+#define GPIO_PCTL_PJ7_CCP0      0xA0000000  // CCP0 on PJ7
+#define GPIO_PCTL_PJ6_M         0x0F000000  // PJ6 mask
+#define GPIO_PCTL_PJ6_EPI0S30   0x08000000  // EPI0S30 on PJ6
+#define GPIO_PCTL_PJ6_U1RTS     0x09000000  // U1RTS on PJ6
+#define GPIO_PCTL_PJ6_CCP1      0x0A000000  // CCP1 on PJ6
+#define GPIO_PCTL_PJ5_M         0x00F00000  // PJ5 mask
+#define GPIO_PCTL_PJ5_EPI0S29   0x00800000  // EPI0S29 on PJ5
+#define GPIO_PCTL_PJ5_U1DSR     0x00900000  // U1DSR on PJ5
+#define GPIO_PCTL_PJ5_CCP2      0x00A00000  // CCP2 on PJ5
+#define GPIO_PCTL_PJ4_M         0x000F0000  // PJ4 mask
+#define GPIO_PCTL_PJ4_EPI0S28   0x00080000  // EPI0S28 on PJ4
+#define GPIO_PCTL_PJ4_U1DCD     0x00090000  // U1DCD on PJ4
+#define GPIO_PCTL_PJ4_CCP4      0x000A0000  // CCP4 on PJ4
+#define GPIO_PCTL_PJ3_M         0x0000F000  // PJ3 mask
+#define GPIO_PCTL_PJ3_EPI0S19   0x00008000  // EPI0S19 on PJ3
+#define GPIO_PCTL_PJ3_U1CTS     0x00009000  // U1CTS on PJ3
+#define GPIO_PCTL_PJ3_CCP6      0x0000A000  // CCP6 on PJ3
+#define GPIO_PCTL_PJ2_M         0x00000F00  // PJ2 mask
+#define GPIO_PCTL_PJ2_EPI0S18   0x00000800  // EPI0S18 on PJ2
+#define GPIO_PCTL_PJ2_CCP0      0x00000900  // CCP0 on PJ2
+#define GPIO_PCTL_PJ2_FAULT0    0x00000A00  // FAULT0 on PJ2
+#define GPIO_PCTL_PJ1_M         0x000000F0  // PJ1 mask
+#define GPIO_PCTL_PJ1_EPI0S17   0x00000080  // EPI0S17 on PJ1
+#define GPIO_PCTL_PJ1_USB0PFLT  0x00000090  // USB0PFLT on PJ1
+#define GPIO_PCTL_PJ1_PWM1      0x000000A0  // PWM1 on PJ1
+#define GPIO_PCTL_PJ1_I2C1SDA   0x000000B0  // I2C1SDA on PJ1
+#define GPIO_PCTL_PJ0_M         0x0000000F  // PJ0 mask
+#define GPIO_PCTL_PJ0_EPI0S16   0x00000008  // EPI0S16 on PJ0
+#define GPIO_PCTL_PJ0_PWM0      0x0000000A  // PWM0 on PJ0
+#define GPIO_PCTL_PJ0_I2C1SCL   0x0000000B  // I2C1SCL on PJ0
+
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SSI_O_CR0 register.
 //
 //*****************************************************************************
-#define SSI_CR0_SCR_M           0x0000FF00  // SSI Serial Clock Rate.
-#define SSI_CR0_SPH             0x00000080  // SSI Serial Clock Phase.
-#define SSI_CR0_SPO             0x00000040  // SSI Serial Clock Polarity.
-#define SSI_CR0_FRF_M           0x00000030  // SSI Frame Format Select.
+#define SSI_CR0_SCR_M           0x0000FF00  // SSI Serial Clock Rate
+#define SSI_CR0_SPH             0x00000080  // SSI Serial Clock Phase
+#define SSI_CR0_SPO             0x00000040  // SSI Serial Clock Polarity
+#define SSI_CR0_FRF_M           0x00000030  // SSI Frame Format Select
 #define SSI_CR0_FRF_MOTO        0x00000000  // Freescale SPI Frame Format
 #define SSI_CR0_FRF_TI          0x00000010  // Texas Instruments Synchronous
                                             // Serial Frame Format
 #define SSI_CR0_FRF_NMW         0x00000020  // MICROWIRE Frame Format
-#define SSI_CR0_DSS_M           0x0000000F  // SSI Data Size Select.
+#define SSI_CR0_DSS_M           0x0000000F  // SSI Data Size Select
 #define SSI_CR0_DSS_4           0x00000003  // 4-bit data
 #define SSI_CR0_DSS_5           0x00000004  // 5-bit data
 #define SSI_CR0_DSS_6           0x00000005  // 6-bit data
@@ -1933,19 +2355,19 @@
 // The following are defines for the bit fields in the SSI_O_CR1 register.
 //
 //*****************************************************************************
-#define SSI_CR1_EOT             0x00000010  // End of Transmission.
-#define SSI_CR1_SOD             0x00000008  // SSI Slave Mode Output Disable.
-#define SSI_CR1_MS              0x00000004  // SSI Master/Slave Select.
+#define SSI_CR1_EOT             0x00000010  // End of Transmission
+#define SSI_CR1_SOD             0x00000008  // SSI Slave Mode Output Disable
+#define SSI_CR1_MS              0x00000004  // SSI Master/Slave Select
 #define SSI_CR1_SSE             0x00000002  // SSI Synchronous Serial Port
-                                            // Enable.
-#define SSI_CR1_LBM             0x00000001  // SSI Loopback Mode.
+                                            // Enable
+#define SSI_CR1_LBM             0x00000001  // SSI Loopback Mode
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SSI_O_DR register.
 //
 //*****************************************************************************
-#define SSI_DR_DATA_M           0x0000FFFF  // SSI Receive/Transmit Data.
+#define SSI_DR_DATA_M           0x0000FFFF  // SSI Receive/Transmit Data
 #define SSI_DR_DATA_S           0
 
 //*****************************************************************************
@@ -1953,18 +2375,18 @@
 // The following are defines for the bit fields in the SSI_O_SR register.
 //
 //*****************************************************************************
-#define SSI_SR_BSY              0x00000010  // SSI Busy Bit.
-#define SSI_SR_RFF              0x00000008  // SSI Receive FIFO Full.
-#define SSI_SR_RNE              0x00000004  // SSI Receive FIFO Not Empty.
-#define SSI_SR_TNF              0x00000002  // SSI Transmit FIFO Not Full.
-#define SSI_SR_TFE              0x00000001  // SSI Transmit FIFO Empty.
+#define SSI_SR_BSY              0x00000010  // SSI Busy Bit
+#define SSI_SR_RFF              0x00000008  // SSI Receive FIFO Full
+#define SSI_SR_RNE              0x00000004  // SSI Receive FIFO Not Empty
+#define SSI_SR_TNF              0x00000002  // SSI Transmit FIFO Not Full
+#define SSI_SR_TFE              0x00000001  // SSI Transmit FIFO Empty
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SSI_O_CPSR register.
 //
 //*****************************************************************************
-#define SSI_CPSR_CPSDVSR_M      0x000000FF  // SSI Clock Prescale Divisor.
+#define SSI_CPSR_CPSDVSR_M      0x000000FF  // SSI Clock Prescale Divisor
 #define SSI_CPSR_CPSDVSR_S      0
 
 //*****************************************************************************
@@ -1972,13 +2394,12 @@
 // The following are defines for the bit fields in the SSI_O_IM register.
 //
 //*****************************************************************************
-#define SSI_IM_TXIM             0x00000008  // SSI Transmit FIFO Interrupt
-                                            // Mask.
-#define SSI_IM_RXIM             0x00000004  // SSI Receive FIFO Interrupt Mask.
+#define SSI_IM_TXIM             0x00000008  // SSI Transmit FIFO Interrupt Mask
+#define SSI_IM_RXIM             0x00000004  // SSI Receive FIFO Interrupt Mask
 #define SSI_IM_RTIM             0x00000002  // SSI Receive Time-Out Interrupt
-                                            // Mask.
+                                            // Mask
 #define SSI_IM_RORIM            0x00000001  // SSI Receive Overrun Interrupt
-                                            // Mask.
+                                            // Mask
 
 //*****************************************************************************
 //
@@ -1986,13 +2407,13 @@
 //
 //*****************************************************************************
 #define SSI_RIS_TXRIS           0x00000008  // SSI Transmit FIFO Raw Interrupt
-                                            // Status.
+                                            // Status
 #define SSI_RIS_RXRIS           0x00000004  // SSI Receive FIFO Raw Interrupt
-                                            // Status.
+                                            // Status
 #define SSI_RIS_RTRIS           0x00000002  // SSI Receive Time-Out Raw
-                                            // Interrupt Status.
+                                            // Interrupt Status
 #define SSI_RIS_RORRIS          0x00000001  // SSI Receive Overrun Raw
-                                            // Interrupt Status.
+                                            // Interrupt Status
 
 //*****************************************************************************
 //
@@ -2000,13 +2421,13 @@
 //
 //*****************************************************************************
 #define SSI_MIS_TXMIS           0x00000008  // SSI Transmit FIFO Masked
-                                            // Interrupt Status.
+                                            // Interrupt Status
 #define SSI_MIS_RXMIS           0x00000004  // SSI Receive FIFO Masked
-                                            // Interrupt Status.
+                                            // Interrupt Status
 #define SSI_MIS_RTMIS           0x00000002  // SSI Receive Time-Out Masked
-                                            // Interrupt Status.
+                                            // Interrupt Status
 #define SSI_MIS_RORMIS          0x00000001  // SSI Receive Overrun Masked
-                                            // Interrupt Status.
+                                            // Interrupt Status
 
 //*****************************************************************************
 //
@@ -2014,28 +2435,28 @@
 //
 //*****************************************************************************
 #define SSI_ICR_RTIC            0x00000002  // SSI Receive Time-Out Interrupt
-                                            // Clear.
+                                            // Clear
 #define SSI_ICR_RORIC           0x00000001  // SSI Receive Overrun Interrupt
-                                            // Clear.
+                                            // Clear
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SSI_O_DMACTL register.
 //
 //*****************************************************************************
-#define SSI_DMACTL_TXDMAE       0x00000002  // Transmit DMA Enable.
-#define SSI_DMACTL_RXDMAE       0x00000001  // Receive DMA Enable.
+#define SSI_DMACTL_TXDMAE       0x00000002  // Transmit DMA Enable
+#define SSI_DMACTL_RXDMAE       0x00000001  // Receive DMA Enable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the UART_O_DR register.
 //
 //*****************************************************************************
-#define UART_DR_OE              0x00000800  // UART Overrun Error.
-#define UART_DR_BE              0x00000400  // UART Break Error.
-#define UART_DR_PE              0x00000200  // UART Parity Error.
-#define UART_DR_FE              0x00000100  // UART Framing Error.
-#define UART_DR_DATA_M          0x000000FF  // Data Transmitted or Received.
+#define UART_DR_OE              0x00000800  // UART Overrun Error
+#define UART_DR_BE              0x00000400  // UART Break Error
+#define UART_DR_PE              0x00000200  // UART Parity Error
+#define UART_DR_FE              0x00000100  // UART Framing Error
+#define UART_DR_DATA_M          0x000000FF  // Data Transmitted or Received
 #define UART_DR_DATA_S          0
 
 //*****************************************************************************
@@ -2043,17 +2464,17 @@
 // The following are defines for the bit fields in the UART_O_RSR register.
 //
 //*****************************************************************************
-#define UART_RSR_OE             0x00000008  // UART Overrun Error.
-#define UART_RSR_BE             0x00000004  // UART Break Error.
-#define UART_RSR_PE             0x00000002  // UART Parity Error.
-#define UART_RSR_FE             0x00000001  // UART Framing Error.
+#define UART_RSR_OE             0x00000008  // UART Overrun Error
+#define UART_RSR_BE             0x00000004  // UART Break Error
+#define UART_RSR_PE             0x00000002  // UART Parity Error
+#define UART_RSR_FE             0x00000001  // UART Framing Error
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the UART_O_ECR register.
 //
 //*****************************************************************************
-#define UART_ECR_DATA_M         0x000000FF  // Error Clear.
+#define UART_ECR_DATA_M         0x000000FF  // Error Clear
 #define UART_ECR_DATA_S         0
 
 //*****************************************************************************
@@ -2061,22 +2482,22 @@
 // The following are defines for the bit fields in the UART_O_FR register.
 //
 //*****************************************************************************
-#define UART_FR_RI              0x00000100  // Ring Indicator.
-#define UART_FR_TXFE            0x00000080  // UART Transmit FIFO Empty.
-#define UART_FR_RXFF            0x00000040  // UART Receive FIFO Full.
-#define UART_FR_TXFF            0x00000020  // UART Transmit FIFO Full.
-#define UART_FR_RXFE            0x00000010  // UART Receive FIFO Empty.
-#define UART_FR_BUSY            0x00000008  // UART Busy.
-#define UART_FR_DCD             0x00000004  // Data Carrier Detect.
-#define UART_FR_DSR             0x00000002  // Data Set Ready.
-#define UART_FR_CTS             0x00000001  // Clear To Send.
+#define UART_FR_RI              0x00000100  // Ring Indicator
+#define UART_FR_TXFE            0x00000080  // UART Transmit FIFO Empty
+#define UART_FR_RXFF            0x00000040  // UART Receive FIFO Full
+#define UART_FR_TXFF            0x00000020  // UART Transmit FIFO Full
+#define UART_FR_RXFE            0x00000010  // UART Receive FIFO Empty
+#define UART_FR_BUSY            0x00000008  // UART Busy
+#define UART_FR_DCD             0x00000004  // Data Carrier Detect
+#define UART_FR_DSR             0x00000002  // Data Set Ready
+#define UART_FR_CTS             0x00000001  // Clear To Send
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the UART_O_ILPR register.
 //
 //*****************************************************************************
-#define UART_ILPR_ILPDVSR_M     0x000000FF  // IrDA Low-Power Divisor.
+#define UART_ILPR_ILPDVSR_M     0x000000FF  // IrDA Low-Power Divisor
 #define UART_ILPR_ILPDVSR_S     0
 
 //*****************************************************************************
@@ -2084,7 +2505,7 @@
 // The following are defines for the bit fields in the UART_O_IBRD register.
 //
 //*****************************************************************************
-#define UART_IBRD_DIVINT_M      0x0000FFFF  // Integer Baud-Rate Divisor.
+#define UART_IBRD_DIVINT_M      0x0000FFFF  // Integer Baud-Rate Divisor
 #define UART_IBRD_DIVINT_S      0
 
 //*****************************************************************************
@@ -2092,7 +2513,7 @@
 // The following are defines for the bit fields in the UART_O_FBRD register.
 //
 //*****************************************************************************
-#define UART_FBRD_DIVFRAC_M     0x0000003F  // Fractional Baud-Rate Divisor.
+#define UART_FBRD_DIVFRAC_M     0x0000003F  // Fractional Baud-Rate Divisor
 #define UART_FBRD_DIVFRAC_S     0
 
 //*****************************************************************************
@@ -2100,37 +2521,37 @@
 // The following are defines for the bit fields in the UART_O_LCRH register.
 //
 //*****************************************************************************
-#define UART_LCRH_SPS           0x00000080  // UART Stick Parity Select.
-#define UART_LCRH_WLEN_M        0x00000060  // UART Word Length.
+#define UART_LCRH_SPS           0x00000080  // UART Stick Parity Select
+#define UART_LCRH_WLEN_M        0x00000060  // UART Word Length
 #define UART_LCRH_WLEN_5        0x00000000  // 5 bits (default)
 #define UART_LCRH_WLEN_6        0x00000020  // 6 bits
 #define UART_LCRH_WLEN_7        0x00000040  // 7 bits
 #define UART_LCRH_WLEN_8        0x00000060  // 8 bits
-#define UART_LCRH_FEN           0x00000010  // UART Enable FIFOs.
-#define UART_LCRH_STP2          0x00000008  // UART Two Stop Bits Select.
-#define UART_LCRH_EPS           0x00000004  // UART Even Parity Select.
-#define UART_LCRH_PEN           0x00000002  // UART Parity Enable.
-#define UART_LCRH_BRK           0x00000001  // UART Send Break.
+#define UART_LCRH_FEN           0x00000010  // UART Enable FIFOs
+#define UART_LCRH_STP2          0x00000008  // UART Two Stop Bits Select
+#define UART_LCRH_EPS           0x00000004  // UART Even Parity Select
+#define UART_LCRH_PEN           0x00000002  // UART Parity Enable
+#define UART_LCRH_BRK           0x00000001  // UART Send Break
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the UART_O_CTL register.
 //
 //*****************************************************************************
-#define UART_CTL_CTSEN          0x00008000  // Enable Clear To Send.
-#define UART_CTL_RTSEN          0x00004000  // Enable Request to Send.
-#define UART_CTL_RTS            0x00000800  // Request to Send.
-#define UART_CTL_DTR            0x00000400  // Data Terminal Ready.
-#define UART_CTL_RXE            0x00000200  // UART Receive Enable.
-#define UART_CTL_TXE            0x00000100  // UART Transmit Enable.
-#define UART_CTL_LBE            0x00000080  // UART Loop Back Enable.
-#define UART_CTL_LIN            0x00000040  // LIN Mode Enable.
-#define UART_CTL_HSE            0x00000020  // High-Speed Enable.
-#define UART_CTL_EOT            0x00000010  // End of Transmission.
-#define UART_CTL_SMART          0x00000008  // ISO 7816 Smart Card Support.
-#define UART_CTL_SIRLP          0x00000004  // UART SIR Low Power Mode.
-#define UART_CTL_SIREN          0x00000002  // UART SIR Enable.
-#define UART_CTL_UARTEN         0x00000001  // UART Enable.
+#define UART_CTL_CTSEN          0x00008000  // Enable Clear To Send
+#define UART_CTL_RTSEN          0x00004000  // Enable Request to Send
+#define UART_CTL_RTS            0x00000800  // Request to Send
+#define UART_CTL_DTR            0x00000400  // Data Terminal Ready
+#define UART_CTL_RXE            0x00000200  // UART Receive Enable
+#define UART_CTL_TXE            0x00000100  // UART Transmit Enable
+#define UART_CTL_LBE            0x00000080  // UART Loop Back Enable
+#define UART_CTL_LIN            0x00000040  // LIN Mode Enable
+#define UART_CTL_HSE            0x00000020  // High-Speed Enable
+#define UART_CTL_EOT            0x00000010  // End of Transmission
+#define UART_CTL_SMART          0x00000008  // ISO 7816 Smart Card Support
+#define UART_CTL_SIRLP          0x00000004  // UART SIR Low-Power Mode
+#define UART_CTL_SIREN          0x00000002  // UART SIR Enable
+#define UART_CTL_UARTEN         0x00000001  // UART Enable
 
 //*****************************************************************************
 //
@@ -2138,48 +2559,47 @@
 //
 //*****************************************************************************
 #define UART_IFLS_RX_M          0x00000038  // UART Receive Interrupt FIFO
-                                            // Level Select.
-#define UART_IFLS_RX1_8         0x00000000  // RX FIFO <= 1/8 full
-#define UART_IFLS_RX2_8         0x00000008  // RX FIFO <= 1/4 full
-#define UART_IFLS_RX4_8         0x00000010  // RX FIFO <= 1/2 full (default)
-#define UART_IFLS_RX6_8         0x00000018  // RX FIFO <= 3/4 full
-#define UART_IFLS_RX7_8         0x00000020  // RX FIFO <= 7/8 full
+                                            // Level Select
+#define UART_IFLS_RX1_8         0x00000000  // RX FIFO >= 1/8 full
+#define UART_IFLS_RX2_8         0x00000008  // RX FIFO >= 1/4 full
+#define UART_IFLS_RX4_8         0x00000010  // RX FIFO >= 1/2 full (default)
+#define UART_IFLS_RX6_8         0x00000018  // RX FIFO >= 3/4 full
+#define UART_IFLS_RX7_8         0x00000020  // RX FIFO >= 7/8 full
 #define UART_IFLS_TX_M          0x00000007  // UART Transmit Interrupt FIFO
-                                            // Level Select.
-#define UART_IFLS_TX1_8         0x00000000  // TX FIFO >= 1/8 full
-#define UART_IFLS_TX2_8         0x00000001  // TX FIFO >= 1/4 full
-#define UART_IFLS_TX4_8         0x00000002  // TX FIFO >= 1/2 full (default)
-#define UART_IFLS_TX6_8         0x00000003  // TX FIFO >= 3/4 full
-#define UART_IFLS_TX7_8         0x00000004  // TX FIFO >= 7/8 full
+                                            // Level Select
+#define UART_IFLS_TX1_8         0x00000000  // TX FIFO <= 1/8 full
+#define UART_IFLS_TX2_8         0x00000001  // TX FIFO <= 1/4 full
+#define UART_IFLS_TX4_8         0x00000002  // TX FIFO <= 1/2 full (default)
+#define UART_IFLS_TX6_8         0x00000003  // TX FIFO <= 3/4 full
+#define UART_IFLS_TX7_8         0x00000004  // TX FIFO <= 7/8 full
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the UART_O_IM register.
 //
 //*****************************************************************************
-#define UART_IM_LME5IM          0x00008000  // LIN Mode Edge 5 Interrupt Mask.
-#define UART_IM_LME1IM          0x00004000  // LIN Mode Edge 1 Interrupt Mask.
+#define UART_IM_LME5IM          0x00008000  // LIN Mode Edge 5 Interrupt Mask
+#define UART_IM_LME1IM          0x00004000  // LIN Mode Edge 1 Interrupt Mask
 #define UART_IM_LMSBIM          0x00002000  // LIN Mode Sync Break Interrupt
-                                            // Mask.
+                                            // Mask
 #define UART_IM_OEIM            0x00000400  // UART Overrun Error Interrupt
-                                            // Mask.
-#define UART_IM_BEIM            0x00000200  // UART Break Error Interrupt Mask.
-#define UART_IM_PEIM            0x00000100  // UART Parity Error Interrupt
-                                            // Mask.
+                                            // Mask
+#define UART_IM_BEIM            0x00000200  // UART Break Error Interrupt Mask
+#define UART_IM_PEIM            0x00000100  // UART Parity Error Interrupt Mask
 #define UART_IM_FEIM            0x00000080  // UART Framing Error Interrupt
-                                            // Mask.
+                                            // Mask
 #define UART_IM_RTIM            0x00000040  // UART Receive Time-Out Interrupt
-                                            // Mask.
-#define UART_IM_TXIM            0x00000020  // UART Transmit Interrupt Mask.
-#define UART_IM_RXIM            0x00000010  // UART Receive Interrupt Mask.
+                                            // Mask
+#define UART_IM_TXIM            0x00000020  // UART Transmit Interrupt Mask
+#define UART_IM_RXIM            0x00000010  // UART Receive Interrupt Mask
 #define UART_IM_DSRMIM          0x00000008  // UART Data Set Ready Modem
-                                            // Interrupt Mask.
+                                            // Interrupt Mask
 #define UART_IM_DCDMIM          0x00000004  // UART Data Carrier Detect Modem
-                                            // Interrupt Mask.
+                                            // Interrupt Mask
 #define UART_IM_CTSMIM          0x00000002  // UART Clear to Send Modem
-                                            // Interrupt Mask.
+                                            // Interrupt Mask
 #define UART_IM_RIMIM           0x00000001  // UART Ring Indicator Modem
-                                            // Interrupt Mask.
+                                            // Interrupt Mask
 
 //*****************************************************************************
 //
@@ -2187,33 +2607,33 @@
 //
 //*****************************************************************************
 #define UART_RIS_LME5RIS        0x00008000  // LIN Mode Edge 5 Raw Interrupt
-                                            // Status.
+                                            // Status
 #define UART_RIS_LME1RIS        0x00004000  // LIN Mode Edge 1 Raw Interrupt
-                                            // Status.
+                                            // Status
 #define UART_RIS_LMSBRIS        0x00002000  // LIN Mode Sync Break Raw
-                                            // Interrupt Status.
+                                            // Interrupt Status
 #define UART_RIS_OERIS          0x00000400  // UART Overrun Error Raw Interrupt
-                                            // Status.
+                                            // Status
 #define UART_RIS_BERIS          0x00000200  // UART Break Error Raw Interrupt
-                                            // Status.
+                                            // Status
 #define UART_RIS_PERIS          0x00000100  // UART Parity Error Raw Interrupt
-                                            // Status.
+                                            // Status
 #define UART_RIS_FERIS          0x00000080  // UART Framing Error Raw Interrupt
-                                            // Status.
+                                            // Status
 #define UART_RIS_RTRIS          0x00000040  // UART Receive Time-Out Raw
-                                            // Interrupt Status.
+                                            // Interrupt Status
 #define UART_RIS_TXRIS          0x00000020  // UART Transmit Raw Interrupt
-                                            // Status.
+                                            // Status
 #define UART_RIS_RXRIS          0x00000010  // UART Receive Raw Interrupt
-                                            // Status.
+                                            // Status
 #define UART_RIS_DSRRIS         0x00000008  // UART Data Set Ready Modem Raw
-                                            // Interrupt Status.
-#define UART_RIS_DCDRIS         0x00000004  // UART Data Carrier Detect odem
-                                            // Raw Interrupt Status.
+                                            // Interrupt Status
+#define UART_RIS_DCDRIS         0x00000004  // UART Data Carrier Detect Modem
+                                            // Raw Interrupt Status
 #define UART_RIS_CTSRIS         0x00000002  // UART Clear to Send Modem Raw
-                                            // Interrupt Status.
+                                            // Interrupt Status
 #define UART_RIS_RIRIS          0x00000001  // UART Ring Indicator Modem Raw
-                                            // Interrupt Status.
+                                            // Interrupt Status
 
 //*****************************************************************************
 //
@@ -2221,88 +2641,91 @@
 //
 //*****************************************************************************
 #define UART_MIS_LME5MIS        0x00008000  // LIN Mode Edge 5 Masked Interrupt
-                                            // Status.
+                                            // Status
 #define UART_MIS_LME1MIS        0x00004000  // LIN Mode Edge 1 Masked Interrupt
-                                            // Status.
+                                            // Status
 #define UART_MIS_LMSBMIS        0x00002000  // LIN Mode Sync Break Masked
-                                            // Interrupt Status.
+                                            // Interrupt Status
 #define UART_MIS_OEMIS          0x00000400  // UART Overrun Error Masked
-                                            // Interrupt Status.
+                                            // Interrupt Status
 #define UART_MIS_BEMIS          0x00000200  // UART Break Error Masked
-                                            // Interrupt Status.
+                                            // Interrupt Status
 #define UART_MIS_PEMIS          0x00000100  // UART Parity Error Masked
-                                            // Interrupt Status.
+                                            // Interrupt Status
 #define UART_MIS_FEMIS          0x00000080  // UART Framing Error Masked
-                                            // Interrupt Status.
+                                            // Interrupt Status
 #define UART_MIS_RTMIS          0x00000040  // UART Receive Time-Out Masked
-                                            // Interrupt Status.
+                                            // Interrupt Status
 #define UART_MIS_TXMIS          0x00000020  // UART Transmit Masked Interrupt
-                                            // Status.
+                                            // Status
 #define UART_MIS_RXMIS          0x00000010  // UART Receive Masked Interrupt
-                                            // Status.
+                                            // Status
 #define UART_MIS_DSRMIS         0x00000008  // UART Data Set Ready Modem Masked
-                                            // Interrupt Status.
-#define UART_MIS_DCDMIS         0x00000004  // UART Data Carrier Detect odem
-                                            // Masked Interrupt Status.
+                                            // Interrupt Status
+#define UART_MIS_DCDMIS         0x00000004  // UART Data Carrier Detect Modem
+                                            // Masked Interrupt Status
 #define UART_MIS_CTSMIS         0x00000002  // UART Clear to Send Modem Masked
-                                            // Interrupt Status.
+                                            // Interrupt Status
 #define UART_MIS_RIMIS          0x00000001  // UART Ring Indicator Modem Masked
-                                            // Interrupt Status.
+                                            // Interrupt Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the UART_O_ICR register.
 //
 //*****************************************************************************
-#define UART_ICR_LME5MIC        0x00008000  // LIN Mode Edge 5 Interrupt Clear.
-#define UART_ICR_LME1MIC        0x00004000  // LIN Mode Edge 1 Interrupt Clear.
+#define UART_ICR_LME5IC         0x00008000  // LIN Mode Edge 5 Interrupt Clear
+#define UART_ICR_LME5MIC        0x00008000  // LIN Mode Edge 5 Interrupt Clear
+#define UART_ICR_LME1MIC        0x00004000  // LIN Mode Edge 1 Interrupt Clear
+#define UART_ICR_LME1IC         0x00004000  // LIN Mode Edge 1 Interrupt Clear
 #define UART_ICR_LMSBMIC        0x00002000  // LIN Mode Sync Break Interrupt
-                                            // Clear.
-#define UART_ICR_OEIC           0x00000400  // Overrun Error Interrupt Clear.
-#define UART_ICR_BEIC           0x00000200  // Break Error Interrupt Clear.
-#define UART_ICR_PEIC           0x00000100  // Parity Error Interrupt Clear.
-#define UART_ICR_FEIC           0x00000080  // Framing Error Interrupt Clear.
-#define UART_ICR_RTIC           0x00000040  // Receive Time-Out Interrupt
-                                            // Clear.
-#define UART_ICR_TXIC           0x00000020  // Transmit Interrupt Clear.
-#define UART_ICR_RXIC           0x00000010  // Receive Interrupt Clear.
+                                            // Clear
+#define UART_ICR_LMSBIC         0x00002000  // LIN Mode Sync Break Interrupt
+                                            // Clear
+#define UART_ICR_OEIC           0x00000400  // Overrun Error Interrupt Clear
+#define UART_ICR_BEIC           0x00000200  // Break Error Interrupt Clear
+#define UART_ICR_PEIC           0x00000100  // Parity Error Interrupt Clear
+#define UART_ICR_FEIC           0x00000080  // Framing Error Interrupt Clear
+#define UART_ICR_RTIC           0x00000040  // Receive Time-Out Interrupt Clear
+#define UART_ICR_TXIC           0x00000020  // Transmit Interrupt Clear
+#define UART_ICR_RXIC           0x00000010  // Receive Interrupt Clear
 #define UART_ICR_DSRMIC         0x00000008  // UART Data Set Ready Modem
-                                            // Interrupt Clear.
-#define UART_ICR_DCDMIC         0x00000004  // UART Data Carrier Detect odem
-                                            // Interrupt Clear.
+                                            // Interrupt Clear
+#define UART_ICR_DCDMIC         0x00000004  // UART Data Carrier Detect Modem
+                                            // Interrupt Clear
 #define UART_ICR_CTSMIC         0x00000002  // UART Clear to Send Modem
-                                            // Interrupt Clear.
+                                            // Interrupt Clear
 #define UART_ICR_RIMIC          0x00000001  // UART Ring Indicator Modem
-                                            // Interrupt Clear.
+                                            // Interrupt Clear
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the UART_O_DMACTL register.
 //
 //*****************************************************************************
-#define UART_DMACTL_DMAERR      0x00000004  // DMA on Error.
-#define UART_DMACTL_TXDMAE      0x00000002  // Transmit DMA Enable.
-#define UART_DMACTL_RXDMAE      0x00000001  // Receive DMA Enable.
+#define UART_DMACTL_DMAERR      0x00000004  // DMA on Error
+#define UART_DMACTL_TXDMAE      0x00000002  // Transmit DMA Enable
+#define UART_DMACTL_RXDMAE      0x00000001  // Receive DMA Enable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the UART_O_LCTL register.
 //
 //*****************************************************************************
-#define UART_LCTL_BLEN_M        0x00000030  // Sync Break Length.
+#define UART_LCTL_BLEN_M        0x00000030  // Sync Break Length
 #define UART_LCTL_BLEN_13T      0x00000000  // Sync break length is 13T bits
                                             // (default)
 #define UART_LCTL_BLEN_14T      0x00000010  // Sync break length is 14T bits
 #define UART_LCTL_BLEN_15T      0x00000020  // Sync break length is 15T bits
 #define UART_LCTL_BLEN_16T      0x00000030  // Sync break length is 16T bits
-#define UART_LCTL_MASTER        0x00000001  // LIN Master Enable.
+#define UART_LCTL_MASTER        0x00000001  // LIN Master Enable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the UART_O_LSS register.
 //
 //*****************************************************************************
-#define UART_LSS_TSS_M          0x0000FFFF  // Timer Snap Shot.
+#define UART_LSS_TSS_M          0x0000FFFF  // Timer Snap Shot
 #define UART_LSS_TSS_S          0
 
 //*****************************************************************************
@@ -2310,7 +2733,7 @@
 // The following are defines for the bit fields in the UART_O_LTIM register.
 //
 //*****************************************************************************
-#define UART_LTIM_TIMER_M       0x0000FFFF  // Timer Value.
+#define UART_LTIM_TIMER_M       0x0000FFFF  // Timer Value
 #define UART_LTIM_TIMER_S       0
 
 //*****************************************************************************
@@ -2318,8 +2741,8 @@
 // The following are defines for the bit fields in the I2C_O_MSA register.
 //
 //*****************************************************************************
-#define I2C_MSA_SA_M            0x000000FE  // I2C Slave Address.
-#define I2C_MSA_RS              0x00000001  // Receive not send.
+#define I2C_MSA_SA_M            0x000000FE  // I2C Slave Address
+#define I2C_MSA_RS              0x00000001  // Receive not send
 #define I2C_MSA_SA_S            1
 
 //*****************************************************************************
@@ -2327,7 +2750,7 @@
 // The following are defines for the bit fields in the I2C_O_SOAR register.
 //
 //*****************************************************************************
-#define I2C_SOAR_OAR_M          0x0000007F  // I2C Slave Own Address.
+#define I2C_SOAR_OAR_M          0x0000007F  // I2C Slave Own Address
 #define I2C_SOAR_OAR_S          0
 
 //*****************************************************************************
@@ -2335,34 +2758,34 @@
 // The following are defines for the bit fields in the I2C_O_SCSR register.
 //
 //*****************************************************************************
-#define I2C_SCSR_FBR            0x00000004  // First Byte Received.
-#define I2C_SCSR_TREQ           0x00000002  // Transmit Request.
-#define I2C_SCSR_DA             0x00000001  // Device Active.
-#define I2C_SCSR_RREQ           0x00000001  // Receive Request.
+#define I2C_SCSR_FBR            0x00000004  // First Byte Received
+#define I2C_SCSR_TREQ           0x00000002  // Transmit Request
+#define I2C_SCSR_DA             0x00000001  // Device Active
+#define I2C_SCSR_RREQ           0x00000001  // Receive Request
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2C_O_MCS register.
 //
 //*****************************************************************************
-#define I2C_MCS_BUSBSY          0x00000040  // Bus Busy.
-#define I2C_MCS_IDLE            0x00000020  // I2C Idle.
-#define I2C_MCS_ARBLST          0x00000010  // Arbitration Lost.
-#define I2C_MCS_ACK             0x00000008  // Data Acknowledge Enable.
-#define I2C_MCS_DATACK          0x00000008  // Acknowledge Data.
-#define I2C_MCS_ADRACK          0x00000004  // Acknowledge Address.
-#define I2C_MCS_STOP            0x00000004  // Generate STOP.
-#define I2C_MCS_START           0x00000002  // Generate START.
-#define I2C_MCS_ERROR           0x00000002  // Error.
-#define I2C_MCS_RUN             0x00000001  // I2C Master Enable.
-#define I2C_MCS_BUSY            0x00000001  // I2C Busy.
+#define I2C_MCS_BUSBSY          0x00000040  // Bus Busy
+#define I2C_MCS_IDLE            0x00000020  // I2C Idle
+#define I2C_MCS_ARBLST          0x00000010  // Arbitration Lost
+#define I2C_MCS_ACK             0x00000008  // Data Acknowledge Enable
+#define I2C_MCS_DATACK          0x00000008  // Acknowledge Data
+#define I2C_MCS_ADRACK          0x00000004  // Acknowledge Address
+#define I2C_MCS_STOP            0x00000004  // Generate STOP
+#define I2C_MCS_START           0x00000002  // Generate START
+#define I2C_MCS_ERROR           0x00000002  // Error
+#define I2C_MCS_RUN             0x00000001  // I2C Master Enable
+#define I2C_MCS_BUSY            0x00000001  // I2C Busy
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2C_O_SDR register.
 //
 //*****************************************************************************
-#define I2C_SDR_DATA_M          0x000000FF  // Data for Transfer.
+#define I2C_SDR_DATA_M          0x000000FF  // Data for Transfer
 #define I2C_SDR_DATA_S          0
 
 //*****************************************************************************
@@ -2370,7 +2793,7 @@
 // The following are defines for the bit fields in the I2C_O_MDR register.
 //
 //*****************************************************************************
-#define I2C_MDR_DATA_M          0x000000FF  // Data Transferred.
+#define I2C_MDR_DATA_M          0x000000FF  // Data Transferred
 #define I2C_MDR_DATA_S          0
 
 //*****************************************************************************
@@ -2378,7 +2801,7 @@
 // The following are defines for the bit fields in the I2C_O_MTPR register.
 //
 //*****************************************************************************
-#define I2C_MTPR_TPR_M          0x000000FF  // SCL Clock Period.
+#define I2C_MTPR_TPR_M          0x0000007F  // SCL Clock Period
 #define I2C_MTPR_TPR_S          0
 
 //*****************************************************************************
@@ -2386,9 +2809,9 @@
 // The following are defines for the bit fields in the I2C_O_SIMR register.
 //
 //*****************************************************************************
-#define I2C_SIMR_STOPIM         0x00000004  // Stop Condition Interrupt Mask.
-#define I2C_SIMR_STARTIM        0x00000002  // Start Condition Interrupt Mask.
-#define I2C_SIMR_DATAIM         0x00000001  // Data Interrupt Mask.
+#define I2C_SIMR_STOPIM         0x00000004  // Stop Condition Interrupt Mask
+#define I2C_SIMR_STARTIM        0x00000002  // Start Condition Interrupt Mask
+#define I2C_SIMR_DATAIM         0x00000001  // Data Interrupt Mask
 
 //*****************************************************************************
 //
@@ -2396,24 +2819,24 @@
 //
 //*****************************************************************************
 #define I2C_SRIS_STOPRIS        0x00000004  // Stop Condition Raw Interrupt
-                                            // Status.
+                                            // Status
 #define I2C_SRIS_STARTRIS       0x00000002  // Start Condition Raw Interrupt
-                                            // Status.
-#define I2C_SRIS_DATARIS        0x00000001  // Data Raw Interrupt Status.
+                                            // Status
+#define I2C_SRIS_DATARIS        0x00000001  // Data Raw Interrupt Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2C_O_MIMR register.
 //
 //*****************************************************************************
-#define I2C_MIMR_IM             0x00000001  // Interrupt Mask.
+#define I2C_MIMR_IM             0x00000001  // Interrupt Mask
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2C_O_MRIS register.
 //
 //*****************************************************************************
-#define I2C_MRIS_RIS            0x00000001  // Raw Interrupt Status.
+#define I2C_MRIS_RIS            0x00000001  // Raw Interrupt Status
 
 //*****************************************************************************
 //
@@ -2421,515 +2844,534 @@
 //
 //*****************************************************************************
 #define I2C_SMIS_STOPMIS        0x00000004  // Stop Condition Masked Interrupt
-                                            // Status.
+                                            // Status
 #define I2C_SMIS_STARTMIS       0x00000002  // Start Condition Masked Interrupt
-                                            // Status.
-#define I2C_SMIS_DATAMIS        0x00000001  // Data Masked Interrupt Status.
+                                            // Status
+#define I2C_SMIS_DATAMIS        0x00000001  // Data Masked Interrupt Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2C_O_SICR register.
 //
 //*****************************************************************************
-#define I2C_SICR_STOPIC         0x00000004  // Stop Condition Interrupt Clear.
-#define I2C_SICR_STARTIC        0x00000002  // Start Condition Interrupt Clear.
-#define I2C_SICR_DATAIC         0x00000001  // Data Interrupt Clear.
+#define I2C_SICR_STOPIC         0x00000004  // Stop Condition Interrupt Clear
+#define I2C_SICR_STARTIC        0x00000002  // Start Condition Interrupt Clear
+#define I2C_SICR_DATAIC         0x00000001  // Data Interrupt Clear
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2C_O_MMIS register.
 //
 //*****************************************************************************
-#define I2C_MMIS_MIS            0x00000001  // Masked Interrupt Status.
+#define I2C_MMIS_MIS            0x00000001  // Masked Interrupt Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2C_O_MICR register.
 //
 //*****************************************************************************
-#define I2C_MICR_IC             0x00000001  // Interrupt Clear.
+#define I2C_MICR_IC             0x00000001  // Interrupt Clear
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2C_O_MCR register.
 //
 //*****************************************************************************
-#define I2C_MCR_SFE             0x00000020  // I2C Slave Function Enable.
-#define I2C_MCR_MFE             0x00000010  // I2C Master Function Enable.
-#define I2C_MCR_LPBK            0x00000001  // I2C Loopback.
+#define I2C_MCR_SFE             0x00000020  // I2C Slave Function Enable
+#define I2C_MCR_MFE             0x00000010  // I2C Master Function Enable
+#define I2C_MCR_LPBK            0x00000001  // I2C Loopback
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the PWM_O_CTL register.
 //
 //*****************************************************************************
-#define PWM_CTL_GLOBALSYNC3     0x00000008  // Update PWM Generator 3.
-#define PWM_CTL_GLOBALSYNC2     0x00000004  // Update PWM Generator 2.
-#define PWM_CTL_GLOBALSYNC1     0x00000002  // Update PWM Generator 1.
-#define PWM_CTL_GLOBALSYNC0     0x00000001  // Update PWM Generator 0.
+#define PWM_CTL_GLOBALSYNC3     0x00000008  // Update PWM Generator 3
+#define PWM_CTL_GLOBALSYNC2     0x00000004  // Update PWM Generator 2
+#define PWM_CTL_GLOBALSYNC1     0x00000002  // Update PWM Generator 1
+#define PWM_CTL_GLOBALSYNC0     0x00000001  // Update PWM Generator 0
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the PWM_O_SYNC register.
 //
 //*****************************************************************************
-#define PWM_SYNC_SYNC3          0x00000008  // Reset Generator 3 Counter.
-#define PWM_SYNC_SYNC2          0x00000004  // Reset Generator 2 Counter.
-#define PWM_SYNC_SYNC1          0x00000002  // Reset Generator 1 Counter.
-#define PWM_SYNC_SYNC0          0x00000001  // Reset Generator 0 Counter.
+#define PWM_SYNC_SYNC3          0x00000008  // Reset Generator 3 Counter
+#define PWM_SYNC_SYNC2          0x00000004  // Reset Generator 2 Counter
+#define PWM_SYNC_SYNC1          0x00000002  // Reset Generator 1 Counter
+#define PWM_SYNC_SYNC0          0x00000001  // Reset Generator 0 Counter
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the PWM_O_ENABLE register.
 //
 //*****************************************************************************
-#define PWM_ENABLE_PWM7EN       0x00000080  // PWM7 Output Enable.
-#define PWM_ENABLE_PWM6EN       0x00000040  // PWM6 Output Enable.
-#define PWM_ENABLE_PWM5EN       0x00000020  // PWM5 Output Enable.
-#define PWM_ENABLE_PWM4EN       0x00000010  // PWM4 Output Enable.
-#define PWM_ENABLE_PWM3EN       0x00000008  // PWM3 Output Enable.
-#define PWM_ENABLE_PWM2EN       0x00000004  // PWM2 Output Enable.
-#define PWM_ENABLE_PWM1EN       0x00000002  // PWM1 Output Enable.
-#define PWM_ENABLE_PWM0EN       0x00000001  // PWM0 Output Enable.
+#define PWM_ENABLE_PWM7EN       0x00000080  // PWM7 Output Enable
+#define PWM_ENABLE_PWM6EN       0x00000040  // PWM6 Output Enable
+#define PWM_ENABLE_PWM5EN       0x00000020  // PWM5 Output Enable
+#define PWM_ENABLE_PWM4EN       0x00000010  // PWM4 Output Enable
+#define PWM_ENABLE_PWM3EN       0x00000008  // PWM3 Output Enable
+#define PWM_ENABLE_PWM2EN       0x00000004  // PWM2 Output Enable
+#define PWM_ENABLE_PWM1EN       0x00000002  // PWM1 Output Enable
+#define PWM_ENABLE_PWM0EN       0x00000001  // PWM0 Output Enable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the PWM_O_INVERT register.
 //
 //*****************************************************************************
-#define PWM_INVERT_PWM7INV      0x00000080  // Invert PWM7 Signal.
-#define PWM_INVERT_PWM6INV      0x00000040  // Invert PWM6 Signal.
-#define PWM_INVERT_PWM5INV      0x00000020  // Invert PWM5 Signal.
-#define PWM_INVERT_PWM4INV      0x00000010  // Invert PWM4 Signal.
-#define PWM_INVERT_PWM3INV      0x00000008  // Invert PWM3 Signal.
-#define PWM_INVERT_PWM2INV      0x00000004  // Invert PWM2 Signal.
-#define PWM_INVERT_PWM1INV      0x00000002  // Invert PWM1 Signal.
-#define PWM_INVERT_PWM0INV      0x00000001  // Invert PWM0 Signal.
+#define PWM_INVERT_PWM7INV      0x00000080  // Invert PWM7 Signal
+#define PWM_INVERT_PWM6INV      0x00000040  // Invert PWM6 Signal
+#define PWM_INVERT_PWM5INV      0x00000020  // Invert PWM5 Signal
+#define PWM_INVERT_PWM4INV      0x00000010  // Invert PWM4 Signal
+#define PWM_INVERT_PWM3INV      0x00000008  // Invert PWM3 Signal
+#define PWM_INVERT_PWM2INV      0x00000004  // Invert PWM2 Signal
+#define PWM_INVERT_PWM1INV      0x00000002  // Invert PWM1 Signal
+#define PWM_INVERT_PWM0INV      0x00000001  // Invert PWM0 Signal
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the PWM_O_FAULT register.
 //
 //*****************************************************************************
-#define PWM_FAULT_FAULT7        0x00000080  // PWM7 Fault.
-#define PWM_FAULT_FAULT6        0x00000040  // PWM6 Fault.
-#define PWM_FAULT_FAULT5        0x00000020  // PWM5 Fault.
-#define PWM_FAULT_FAULT4        0x00000010  // PWM4 Fault.
-#define PWM_FAULT_FAULT3        0x00000008  // PWM3 Fault.
-#define PWM_FAULT_FAULT2        0x00000004  // PWM2 Fault.
-#define PWM_FAULT_FAULT1        0x00000002  // PWM1 Fault.
-#define PWM_FAULT_FAULT0        0x00000001  // PWM0 Fault.
+#define PWM_FAULT_FAULT7        0x00000080  // PWM7 Fault
+#define PWM_FAULT_FAULT6        0x00000040  // PWM6 Fault
+#define PWM_FAULT_FAULT5        0x00000020  // PWM5 Fault
+#define PWM_FAULT_FAULT4        0x00000010  // PWM4 Fault
+#define PWM_FAULT_FAULT3        0x00000008  // PWM3 Fault
+#define PWM_FAULT_FAULT2        0x00000004  // PWM2 Fault
+#define PWM_FAULT_FAULT1        0x00000002  // PWM1 Fault
+#define PWM_FAULT_FAULT0        0x00000001  // PWM0 Fault
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the PWM_O_INTEN register.
 //
 //*****************************************************************************
-#define PWM_INTEN_INTFAULT3     0x00080000  // Interrupt Fault 3.
-#define PWM_INTEN_INTFAULT2     0x00040000  // Interrupt Fault 2.
-#define PWM_INTEN_INTFAULT1     0x00020000  // Interrupt Fault 1.
-#define PWM_INTEN_INTFAULT0     0x00010000  // Interrupt Fault 0.
-#define PWM_INTEN_INTPWM3       0x00000008  // PWM3 Interrupt Enable.
-#define PWM_INTEN_INTPWM2       0x00000004  // PWM2 Interrupt Enable.
-#define PWM_INTEN_INTPWM1       0x00000002  // PWM1 Interrupt Enable.
-#define PWM_INTEN_INTPWM0       0x00000001  // PWM0 Interrupt Enable.
+#define PWM_INTEN_INTFAULT3     0x00080000  // Interrupt Fault 3
+#define PWM_INTEN_INTFAULT2     0x00040000  // Interrupt Fault 2
+#define PWM_INTEN_INTFAULT1     0x00020000  // Interrupt Fault 1
+#define PWM_INTEN_INTFAULT0     0x00010000  // Interrupt Fault 0
+#define PWM_INTEN_INTPWM3       0x00000008  // PWM3 Interrupt Enable
+#define PWM_INTEN_INTPWM2       0x00000004  // PWM2 Interrupt Enable
+#define PWM_INTEN_INTPWM1       0x00000002  // PWM1 Interrupt Enable
+#define PWM_INTEN_INTPWM0       0x00000001  // PWM0 Interrupt Enable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the PWM_O_RIS register.
 //
 //*****************************************************************************
-#define PWM_RIS_INTFAULT3       0x00080000  // Interrupt Fault PWM 3.
-#define PWM_RIS_INTFAULT2       0x00040000  // Interrupt Fault PWM 2.
-#define PWM_RIS_INTFAULT1       0x00020000  // Interrupt Fault PWM 1.
-#define PWM_RIS_INTFAULT0       0x00010000  // Interrupt Fault PWM 0.
-#define PWM_RIS_INTPWM3         0x00000008  // PWM3 Interrupt Asserted.
-#define PWM_RIS_INTPWM2         0x00000004  // PWM2 Interrupt Asserted.
-#define PWM_RIS_INTPWM1         0x00000002  // PWM1 Interrupt Asserted.
-#define PWM_RIS_INTPWM0         0x00000001  // PWM0 Interrupt Asserted.
+#define PWM_RIS_INTFAULT3       0x00080000  // Interrupt Fault PWM 3
+#define PWM_RIS_INTFAULT2       0x00040000  // Interrupt Fault PWM 2
+#define PWM_RIS_INTFAULT1       0x00020000  // Interrupt Fault PWM 1
+#define PWM_RIS_INTFAULT0       0x00010000  // Interrupt Fault PWM 0
+#define PWM_RIS_INTPWM3         0x00000008  // PWM3 Interrupt Asserted
+#define PWM_RIS_INTPWM2         0x00000004  // PWM2 Interrupt Asserted
+#define PWM_RIS_INTPWM1         0x00000002  // PWM1 Interrupt Asserted
+#define PWM_RIS_INTPWM0         0x00000001  // PWM0 Interrupt Asserted
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the PWM_O_ISC register.
 //
 //*****************************************************************************
-#define PWM_ISC_INTFAULT3       0x00080000  // FAULT3 Interrupt Asserted.
-#define PWM_ISC_INTFAULT2       0x00040000  // FAULT2 Interrupt Asserted.
-#define PWM_ISC_INTFAULT1       0x00020000  // FAULT1 Interrupt Asserted.
-#define PWM_ISC_INTFAULT0       0x00010000  // FAULT0 Interrupt Asserted.
-#define PWM_ISC_INTPWM3         0x00000008  // PWM3 Interrupt Status.
-#define PWM_ISC_INTPWM2         0x00000004  // PWM2 Interrupt Status.
-#define PWM_ISC_INTPWM1         0x00000002  // PWM1 Interrupt Status.
-#define PWM_ISC_INTPWM0         0x00000001  // PWM0 Interrupt Status.
+#define PWM_ISC_INTFAULT3       0x00080000  // FAULT3 Interrupt Asserted
+#define PWM_ISC_INTFAULT2       0x00040000  // FAULT2 Interrupt Asserted
+#define PWM_ISC_INTFAULT1       0x00020000  // FAULT1 Interrupt Asserted
+#define PWM_ISC_INTFAULT0       0x00010000  // FAULT0 Interrupt Asserted
+#define PWM_ISC_INTPWM3         0x00000008  // PWM3 Interrupt Status
+#define PWM_ISC_INTPWM2         0x00000004  // PWM2 Interrupt Status
+#define PWM_ISC_INTPWM1         0x00000002  // PWM1 Interrupt Status
+#define PWM_ISC_INTPWM0         0x00000001  // PWM0 Interrupt Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the PWM_O_STATUS register.
 //
 //*****************************************************************************
-#define PWM_STATUS_FAULT3       0x00000008  // Fault3 Interrupt Status.
-#define PWM_STATUS_FAULT2       0x00000004  // Fault2 Interrupt Status.
-#define PWM_STATUS_FAULT1       0x00000002  // Fault1 Interrupt Status.
-#define PWM_STATUS_FAULT0       0x00000001  // Fault0 Interrupt Status.
+#define PWM_STATUS_FAULT3       0x00000008  // Generator 3 Fault Status
+#define PWM_STATUS_FAULT2       0x00000004  // Generator 2 Fault Status
+#define PWM_STATUS_FAULT1       0x00000002  // Generator 1 Fault Status
+#define PWM_STATUS_FAULT0       0x00000001  // Generator 0 Fault Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the PWM_O_FAULTVAL register.
 //
 //*****************************************************************************
-#define PWM_FAULTVAL_PWM7       0x00000080  // PWM7 Fault Value.
-#define PWM_FAULTVAL_PWM6       0x00000040  // PWM6 Fault Value.
-#define PWM_FAULTVAL_PWM5       0x00000020  // PWM5 Fault Value.
-#define PWM_FAULTVAL_PWM4       0x00000010  // PWM4 Fault Value.
-#define PWM_FAULTVAL_PWM3       0x00000008  // PWM3 Fault Value.
-#define PWM_FAULTVAL_PWM2       0x00000004  // PWM2 Fault Value.
-#define PWM_FAULTVAL_PWM1       0x00000002  // PWM1 Fault Value.
-#define PWM_FAULTVAL_PWM0       0x00000001  // PWM0 Fault Value.
+#define PWM_FAULTVAL_PWM7       0x00000080  // PWM7 Fault Value
+#define PWM_FAULTVAL_PWM6       0x00000040  // PWM6 Fault Value
+#define PWM_FAULTVAL_PWM5       0x00000020  // PWM5 Fault Value
+#define PWM_FAULTVAL_PWM4       0x00000010  // PWM4 Fault Value
+#define PWM_FAULTVAL_PWM3       0x00000008  // PWM3 Fault Value
+#define PWM_FAULTVAL_PWM2       0x00000004  // PWM2 Fault Value
+#define PWM_FAULTVAL_PWM1       0x00000002  // PWM1 Fault Value
+#define PWM_FAULTVAL_PWM0       0x00000001  // PWM0 Fault Value
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the PWM_O_0_CTL,
-// PWM_O_1_CTL, PWM_O_2_CTL, and PWM_O_3_CTL registers.
+// The following are defines for the bit fields in the PWM_O_ENUPD register.
 //
 //*****************************************************************************
-#define PWM_X_CTL_LATCH         0x00040000  // Latch Fault Input.
-#define PWM_X_CTL_MINFLTPER     0x00020000  // Minimum Fault Period.
-#define PWM_X_CTL_FLTSRC        0x00010000  // Fault Condition Source.
-#define PWM_X_CTL_DBFALLUPD_M   0x0000C000  // Specifies the update mode for
-                                            // the PWMnDBFALL register.
+#define PWM_ENUPD_ENUPD7_M      0x0000C000  // PWM7 Enable Update Mode
+#define PWM_ENUPD_ENUPD7_IMM    0x00000000  // Immediate
+#define PWM_ENUPD_ENUPD7_LSYNC  0x00008000  // Locally Synchronized
+#define PWM_ENUPD_ENUPD7_GSYNC  0x0000C000  // Globally Synchronized
+#define PWM_ENUPD_ENUPD6_M      0x00003000  // PWM6 Enable Update Mode
+#define PWM_ENUPD_ENUPD6_IMM    0x00000000  // Immediate
+#define PWM_ENUPD_ENUPD6_LSYNC  0x00002000  // Locally Synchronized
+#define PWM_ENUPD_ENUPD6_GSYNC  0x00003000  // Globally Synchronized
+#define PWM_ENUPD_ENUPD5_M      0x00000C00  // PWM5 Enable Update Mode
+#define PWM_ENUPD_ENUPD5_IMM    0x00000000  // Immediate
+#define PWM_ENUPD_ENUPD5_LSYNC  0x00000800  // Locally Synchronized
+#define PWM_ENUPD_ENUPD5_GSYNC  0x00000C00  // Globally Synchronized
+#define PWM_ENUPD_ENUPD4_M      0x00000300  // PWM4 Enable Update Mode
+#define PWM_ENUPD_ENUPD4_IMM    0x00000000  // Immediate
+#define PWM_ENUPD_ENUPD4_LSYNC  0x00000200  // Locally Synchronized
+#define PWM_ENUPD_ENUPD4_GSYNC  0x00000300  // Globally Synchronized
+#define PWM_ENUPD_ENUPD3_M      0x000000C0  // PWM3 Enable Update Mode
+#define PWM_ENUPD_ENUPD3_IMM    0x00000000  // Immediate
+#define PWM_ENUPD_ENUPD3_LSYNC  0x00000080  // Locally Synchronized
+#define PWM_ENUPD_ENUPD3_GSYNC  0x000000C0  // Globally Synchronized
+#define PWM_ENUPD_ENUPD2_M      0x00000030  // PWM2 Enable Update Mode
+#define PWM_ENUPD_ENUPD2_IMM    0x00000000  // Immediate
+#define PWM_ENUPD_ENUPD2_LSYNC  0x00000020  // Locally Synchronized
+#define PWM_ENUPD_ENUPD2_GSYNC  0x00000030  // Globally Synchronized
+#define PWM_ENUPD_ENUPD1_M      0x0000000C  // PWM1 Enable Update Mode
+#define PWM_ENUPD_ENUPD1_IMM    0x00000000  // Immediate
+#define PWM_ENUPD_ENUPD1_LSYNC  0x00000008  // Locally Synchronized
+#define PWM_ENUPD_ENUPD1_GSYNC  0x0000000C  // Globally Synchronized
+#define PWM_ENUPD_ENUPD0_M      0x00000003  // PWM0 Enable Update Mode
+#define PWM_ENUPD_ENUPD0_IMM    0x00000000  // Immediate
+#define PWM_ENUPD_ENUPD0_LSYNC  0x00000002  // Locally Synchronized
+#define PWM_ENUPD_ENUPD0_GSYNC  0x00000003  // Globally Synchronized
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_CTL register.
+//
+//*****************************************************************************
+#define PWM_X_CTL_LATCH         0x00040000  // Latch Fault Input
+#define PWM_X_CTL_MINFLTPER     0x00020000  // Minimum Fault Period
+#define PWM_X_CTL_FLTSRC        0x00010000  // Fault Condition Source
+#define PWM_X_CTL_DBFALLUPD_M   0x0000C000  // PWMnDBFALL Update Mode
 #define PWM_X_CTL_DBFALLUPD_I   0x00000000  // Immediate
 #define PWM_X_CTL_DBFALLUPD_LS  0x00008000  // Locally Synchronized
 #define PWM_X_CTL_DBFALLUPD_GS  0x0000C000  // Globally Synchronized
-#define PWM_X_CTL_DBRISEUPD_M   0x00003000  // PWMnDBRISE Update Mode.
+#define PWM_X_CTL_DBRISEUPD_M   0x00003000  // PWMnDBRISE Update Mode
 #define PWM_X_CTL_DBRISEUPD_I   0x00000000  // Immediate
 #define PWM_X_CTL_DBRISEUPD_LS  0x00002000  // Locally Synchronized
 #define PWM_X_CTL_DBRISEUPD_GS  0x00003000  // Globally Synchronized
-#define PWM_X_CTL_DBCTLUPD_M    0x00000C00  // PWMnDBCTL Update Mode.
+#define PWM_X_CTL_DBCTLUPD_M    0x00000C00  // PWMnDBCTL Update Mode
 #define PWM_X_CTL_DBCTLUPD_I    0x00000000  // Immediate
 #define PWM_X_CTL_DBCTLUPD_LS   0x00000800  // Locally Synchronized
 #define PWM_X_CTL_DBCTLUPD_GS   0x00000C00  // Globally Synchronized
-#define PWM_X_CTL_GENBUPD_M     0x00000300  // PWMnGENB Update Mode.
+#define PWM_X_CTL_GENBUPD_M     0x00000300  // PWMnGENB Update Mode
 #define PWM_X_CTL_GENBUPD_I     0x00000000  // Immediate
 #define PWM_X_CTL_GENBUPD_LS    0x00000200  // Locally Synchronized
 #define PWM_X_CTL_GENBUPD_GS    0x00000300  // Globally Synchronized
-#define PWM_X_CTL_GENAUPD_M     0x000000C0  // PWMnGENA Update Mode.
+#define PWM_X_CTL_GENAUPD_M     0x000000C0  // PWMnGENA Update Mode
 #define PWM_X_CTL_GENAUPD_I     0x00000000  // Immediate
 #define PWM_X_CTL_GENAUPD_LS    0x00000080  // Locally Synchronized
 #define PWM_X_CTL_GENAUPD_GS    0x000000C0  // Globally Synchronized
-#define PWM_X_CTL_CMPBUPD       0x00000020  // Comparator B Update Mode.
-#define PWM_X_CTL_CMPAUPD       0x00000010  // Comparator A Update Mode.
-#define PWM_X_CTL_LOADUPD       0x00000008  // Load Register Update Mode.
-#define PWM_X_CTL_DEBUG         0x00000004  // Debug Mode.
-#define PWM_X_CTL_MODE          0x00000002  // Counter Mode.
-#define PWM_X_CTL_ENABLE        0x00000001  // PWM Block Enable.
+#define PWM_X_CTL_CMPBUPD       0x00000020  // Comparator B Update Mode
+#define PWM_X_CTL_CMPAUPD       0x00000010  // Comparator A Update Mode
+#define PWM_X_CTL_LOADUPD       0x00000008  // Load Register Update Mode
+#define PWM_X_CTL_DEBUG         0x00000004  // Debug Mode
+#define PWM_X_CTL_MODE          0x00000002  // Counter Mode
+#define PWM_X_CTL_ENABLE        0x00000001  // PWM Block Enable
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the PWM_O_0_INTEN,
-// PWM_O_1_INTEN, PWM_O_2_INTEN, and PWM_O_3_INTEN registers.
+// The following are defines for the bit fields in the PWM_O_X_INTEN register.
 //
 //*****************************************************************************
-#define PWM_X_INTEN_TRCMPBD     0x00002000  // Trigger for Counter=Comparator B
-                                            // Down.
-#define PWM_X_INTEN_TRCMPBU     0x00001000  // Trigger for Counter=Comparator B
-                                            // Up.
-#define PWM_X_INTEN_TRCMPAD     0x00000800  // Trigger for Counter=Comparator A
-                                            // Down.
-#define PWM_X_INTEN_TRCMPAU     0x00000400  // Trigger for Counter=Comparator A
-                                            // Up.
-#define PWM_X_INTEN_TRCNTLOAD   0x00000200  // Trigger for Counter=Load.
-#define PWM_X_INTEN_TRCNTZERO   0x00000100  // Trigger for Counter=0.
-#define PWM_X_INTEN_INTCMPBD    0x00000020  // Interrupt for Counter=Comparator
-                                            // B Down.
-#define PWM_X_INTEN_INTCMPBU    0x00000010  // Interrupt for Counter=Comparator
-                                            // B Up.
-#define PWM_X_INTEN_INTCMPAD    0x00000008  // Interrupt for Counter=Comparator
-                                            // A Down.
-#define PWM_X_INTEN_INTCMPAU    0x00000004  // Interrupt for Counter=Comparator
-                                            // A Up.
-#define PWM_X_INTEN_INTCNTLOAD  0x00000002  // Interrupt for Counter=Load.
-#define PWM_X_INTEN_INTCNTZERO  0x00000001  // Interrupt for Counter=0.
+#define PWM_X_INTEN_TRCMPBD     0x00002000  // Trigger for Counter=PWMnCMPB
+                                            // Down
+#define PWM_X_INTEN_TRCMPBU     0x00001000  // Trigger for Counter=PWMnCMPB Up
+#define PWM_X_INTEN_TRCMPAD     0x00000800  // Trigger for Counter=PWMnCMPA
+                                            // Down
+#define PWM_X_INTEN_TRCMPAU     0x00000400  // Trigger for Counter=PWMnCMPA Up
+#define PWM_X_INTEN_TRCNTLOAD   0x00000200  // Trigger for Counter=PWMnLOAD
+#define PWM_X_INTEN_TRCNTZERO   0x00000100  // Trigger for Counter=0
+#define PWM_X_INTEN_INTCMPBD    0x00000020  // Interrupt for Counter=PWMnCMPB
+                                            // Down
+#define PWM_X_INTEN_INTCMPBU    0x00000010  // Interrupt for Counter=PWMnCMPB
+                                            // Up
+#define PWM_X_INTEN_INTCMPAD    0x00000008  // Interrupt for Counter=PWMnCMPA
+                                            // Down
+#define PWM_X_INTEN_INTCMPAU    0x00000004  // Interrupt for Counter=PWMnCMPA
+                                            // Up
+#define PWM_X_INTEN_INTCNTLOAD  0x00000002  // Interrupt for Counter=PWMnLOAD
+#define PWM_X_INTEN_INTCNTZERO  0x00000001  // Interrupt for Counter=0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the PWM_O_0_RIS,
-// PWM_O_1_RIS, PWM_O_2_RIS, and PWM_O_3_RIS registers.
+// The following are defines for the bit fields in the PWM_O_X_RIS register.
 //
 //*****************************************************************************
 #define PWM_X_RIS_INTCMPBD      0x00000020  // Comparator B Down Interrupt
-                                            // Status.
-#define PWM_X_RIS_INTCMPBU      0x00000010  // Comparator B Up Interrupt
-                                            // Status.
+                                            // Status
+#define PWM_X_RIS_INTCMPBU      0x00000010  // Comparator B Up Interrupt Status
 #define PWM_X_RIS_INTCMPAD      0x00000008  // Comparator A Down Interrupt
-                                            // Status.
-#define PWM_X_RIS_INTCMPAU      0x00000004  // Comparator A Up Interrupt
-                                            // Status.
-#define PWM_X_RIS_INTCNTLOAD    0x00000002  // Counter=Load Interrupt Status.
-#define PWM_X_RIS_INTCNTZERO    0x00000001  // Counter=0 Interrupt Status.
+                                            // Status
+#define PWM_X_RIS_INTCMPAU      0x00000004  // Comparator A Up Interrupt Status
+#define PWM_X_RIS_INTCNTLOAD    0x00000002  // Counter=Load Interrupt Status
+#define PWM_X_RIS_INTCNTZERO    0x00000001  // Counter=0 Interrupt Status
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the PWM_O_0_ISC,
-// PWM_O_1_ISC, PWM_O_2_ISC, and PWM_O_3_ISC registers.
+// The following are defines for the bit fields in the PWM_O_X_ISC register.
 //
 //*****************************************************************************
-#define PWM_X_ISC_INTCMPBD      0x00000020  // Comparator B Down Interrupt.
-#define PWM_X_ISC_INTCMPBU      0x00000010  // Comparator B Up Interrupt.
-#define PWM_X_ISC_INTCMPAD      0x00000008  // Comparator A Down Interrupt.
-#define PWM_X_ISC_INTCMPAU      0x00000004  // Comparator A Up Interrupt.
-#define PWM_X_ISC_INTCNTLOAD    0x00000002  // Counter=Load Interrupt.
-#define PWM_X_ISC_INTCNTZERO    0x00000001  // Counter=0 Interrupt.
+#define PWM_X_ISC_INTCMPBD      0x00000020  // Comparator B Down Interrupt
+#define PWM_X_ISC_INTCMPBU      0x00000010  // Comparator B Up Interrupt
+#define PWM_X_ISC_INTCMPAD      0x00000008  // Comparator A Down Interrupt
+#define PWM_X_ISC_INTCMPAU      0x00000004  // Comparator A Up Interrupt
+#define PWM_X_ISC_INTCNTLOAD    0x00000002  // Counter=Load Interrupt
+#define PWM_X_ISC_INTCNTZERO    0x00000001  // Counter=0 Interrupt
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the PWM_O_0_LOAD,
-// PWM_O_1_LOAD, PWM_O_2_LOAD, and PWM_O_3_LOAD registers.
+// The following are defines for the bit fields in the PWM_O_X_LOAD register.
 //
 //*****************************************************************************
-#define PWM_X_LOAD_M            0x0000FFFF  // Counter Load Value.
+#define PWM_X_LOAD_M            0x0000FFFF  // Counter Load Value
 #define PWM_X_LOAD_S            0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the PWM_O_0_COUNT,
-// PWM_O_1_COUNT, PWM_O_2_COUNT, and PWM_O_3_COUNT registers.
+// The following are defines for the bit fields in the PWM_O_X_COUNT register.
 //
 //*****************************************************************************
-#define PWM_X_COUNT_M           0x0000FFFF  // Counter Value.
+#define PWM_X_COUNT_M           0x0000FFFF  // Counter Value
 #define PWM_X_COUNT_S           0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the PWM_O_0_CMPA,
-// PWM_O_1_CMPA, PWM_O_2_CMPA, and PWM_O_3_CMPA registers.
+// The following are defines for the bit fields in the PWM_O_X_CMPA register.
 //
 //*****************************************************************************
-#define PWM_X_CMPA_M            0x0000FFFF  // Comparator A Value.
+#define PWM_X_CMPA_M            0x0000FFFF  // Comparator A Value
 #define PWM_X_CMPA_S            0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the PWM_O_0_CMPB,
-// PWM_O_1_CMPB, PWM_O_2_CMPB, and PWM_O_3_CMPB registers.
+// The following are defines for the bit fields in the PWM_O_X_CMPB register.
 //
 //*****************************************************************************
-#define PWM_X_CMPB_M            0x0000FFFF  // Comparator B Value.
+#define PWM_X_CMPB_M            0x0000FFFF  // Comparator B Value
 #define PWM_X_CMPB_S            0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the PWM_O_0_GENA,
-// PWM_O_1_GENA, PWM_O_2_GENA, and PWM_O_3_GENA registers.
+// The following are defines for the bit fields in the PWM_O_X_GENA register.
 //
 //*****************************************************************************
-#define PWM_X_GENA_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down.
+#define PWM_X_GENA_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down
 #define PWM_X_GENA_ACTCMPBD_NONE \
-                                0x00000000  // Do nothing.
-#define PWM_X_GENA_ACTCMPBD_INV 0x00000400  // Invert the output signal.
+                                0x00000000  // Do nothing
+#define PWM_X_GENA_ACTCMPBD_INV 0x00000400  // Invert pwmA
 #define PWM_X_GENA_ACTCMPBD_ZERO \
-                                0x00000800  // Set the output signal to 0.
-#define PWM_X_GENA_ACTCMPBD_ONE 0x00000C00  // Set the output signal to 1.
-#define PWM_X_GENA_ACTCMPBU_M   0x00000300  // Action for Comparator B Up.
+                                0x00000800  // Drive pwmA Low
+#define PWM_X_GENA_ACTCMPBD_ONE 0x00000C00  // Drive pwmA High
+#define PWM_X_GENA_ACTCMPBU_M   0x00000300  // Action for Comparator B Up
 #define PWM_X_GENA_ACTCMPBU_NONE \
-                                0x00000000  // Do nothing.
-#define PWM_X_GENA_ACTCMPBU_INV 0x00000100  // Invert the output signal.
+                                0x00000000  // Do nothing
+#define PWM_X_GENA_ACTCMPBU_INV 0x00000100  // Invert pwmA
 #define PWM_X_GENA_ACTCMPBU_ZERO \
-                                0x00000200  // Set the output signal to 0.
-#define PWM_X_GENA_ACTCMPBU_ONE 0x00000300  // Set the output signal to 1.
-#define PWM_X_GENA_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down.
+                                0x00000200  // Drive pwmA Low
+#define PWM_X_GENA_ACTCMPBU_ONE 0x00000300  // Drive pwmA High
+#define PWM_X_GENA_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down
 #define PWM_X_GENA_ACTCMPAD_NONE \
-                                0x00000000  // Do nothing.
-#define PWM_X_GENA_ACTCMPAD_INV 0x00000040  // Invert the output signal.
+                                0x00000000  // Do nothing
+#define PWM_X_GENA_ACTCMPAD_INV 0x00000040  // Invert pwmA
 #define PWM_X_GENA_ACTCMPAD_ZERO \
-                                0x00000080  // Set the output signal to 0.
-#define PWM_X_GENA_ACTCMPAD_ONE 0x000000C0  // Set the output signal to 1.
-#define PWM_X_GENA_ACTCMPAU_M   0x00000030  // Action for Comparator A Up.
+                                0x00000080  // Drive pwmA Low
+#define PWM_X_GENA_ACTCMPAD_ONE 0x000000C0  // Drive pwmA High
+#define PWM_X_GENA_ACTCMPAU_M   0x00000030  // Action for Comparator A Up
 #define PWM_X_GENA_ACTCMPAU_NONE \
-                                0x00000000  // Do nothing.
-#define PWM_X_GENA_ACTCMPAU_INV 0x00000010  // Invert the output signal.
+                                0x00000000  // Do nothing
+#define PWM_X_GENA_ACTCMPAU_INV 0x00000010  // Invert pwmA
 #define PWM_X_GENA_ACTCMPAU_ZERO \
-                                0x00000020  // Set the output signal to 0.
-#define PWM_X_GENA_ACTCMPAU_ONE 0x00000030  // Set the output signal to 1.
-#define PWM_X_GENA_ACTLOAD_M    0x0000000C  // Action for Counter=Load.
-#define PWM_X_GENA_ACTLOAD_NONE 0x00000000  // Do nothing.
-#define PWM_X_GENA_ACTLOAD_INV  0x00000004  // Invert the output signal.
-#define PWM_X_GENA_ACTLOAD_ZERO 0x00000008  // Set the output signal to 0.
-#define PWM_X_GENA_ACTLOAD_ONE  0x0000000C  // Set the output signal to 1.
-#define PWM_X_GENA_ACTZERO_M    0x00000003  // Action for Counter=0.
-#define PWM_X_GENA_ACTZERO_NONE 0x00000000  // Do nothing.
-#define PWM_X_GENA_ACTZERO_INV  0x00000001  // Invert the output signal.
-#define PWM_X_GENA_ACTZERO_ZERO 0x00000002  // Set the output signal to 0.
-#define PWM_X_GENA_ACTZERO_ONE  0x00000003  // Set the output signal to 1.
+                                0x00000020  // Drive pwmA Low
+#define PWM_X_GENA_ACTCMPAU_ONE 0x00000030  // Drive pwmA High
+#define PWM_X_GENA_ACTLOAD_M    0x0000000C  // Action for Counter=LOAD
+#define PWM_X_GENA_ACTLOAD_NONE 0x00000000  // Do nothing
+#define PWM_X_GENA_ACTLOAD_INV  0x00000004  // Invert pwmA
+#define PWM_X_GENA_ACTLOAD_ZERO 0x00000008  // Drive pwmA Low
+#define PWM_X_GENA_ACTLOAD_ONE  0x0000000C  // Drive pwmA High
+#define PWM_X_GENA_ACTZERO_M    0x00000003  // Action for Counter=0
+#define PWM_X_GENA_ACTZERO_NONE 0x00000000  // Do nothing
+#define PWM_X_GENA_ACTZERO_INV  0x00000001  // Invert pwmA
+#define PWM_X_GENA_ACTZERO_ZERO 0x00000002  // Drive pwmA Low
+#define PWM_X_GENA_ACTZERO_ONE  0x00000003  // Drive pwmA High
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the PWM_O_0_GENB,
-// PWM_O_1_GENB, PWM_O_2_GENB, and PWM_O_3_GENB registers.
+// The following are defines for the bit fields in the PWM_O_X_GENB register.
 //
 //*****************************************************************************
-#define PWM_X_GENB_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down.
+#define PWM_X_GENB_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down
 #define PWM_X_GENB_ACTCMPBD_NONE \
-                                0x00000000  // Do nothing.
-#define PWM_X_GENB_ACTCMPBD_INV 0x00000400  // Invert the output signal.
+                                0x00000000  // Do nothing
+#define PWM_X_GENB_ACTCMPBD_INV 0x00000400  // Invert pwmB
 #define PWM_X_GENB_ACTCMPBD_ZERO \
-                                0x00000800  // Set the output signal to 0.
-#define PWM_X_GENB_ACTCMPBD_ONE 0x00000C00  // Set the output signal to 1.
-#define PWM_X_GENB_ACTCMPBU_M   0x00000300  // Action for Comparator B Up.
+                                0x00000800  // Drive pwmB Low
+#define PWM_X_GENB_ACTCMPBD_ONE 0x00000C00  // Drive pwmB High
+#define PWM_X_GENB_ACTCMPBU_M   0x00000300  // Action for Comparator B Up
 #define PWM_X_GENB_ACTCMPBU_NONE \
-                                0x00000000  // Do nothing.
-#define PWM_X_GENB_ACTCMPBU_INV 0x00000100  // Invert the output signal.
+                                0x00000000  // Do nothing
+#define PWM_X_GENB_ACTCMPBU_INV 0x00000100  // Invert pwmB
 #define PWM_X_GENB_ACTCMPBU_ZERO \
-                                0x00000200  // Set the output signal to 0.
-#define PWM_X_GENB_ACTCMPBU_ONE 0x00000300  // Set the output signal to 1.
-#define PWM_X_GENB_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down.
+                                0x00000200  // Drive pwmB Low
+#define PWM_X_GENB_ACTCMPBU_ONE 0x00000300  // Drive pwmB High
+#define PWM_X_GENB_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down
 #define PWM_X_GENB_ACTCMPAD_NONE \
-                                0x00000000  // Do nothing.
-#define PWM_X_GENB_ACTCMPAD_INV 0x00000040  // Invert the output signal.
+                                0x00000000  // Do nothing
+#define PWM_X_GENB_ACTCMPAD_INV 0x00000040  // Invert pwmB
 #define PWM_X_GENB_ACTCMPAD_ZERO \
-                                0x00000080  // Set the output signal to 0.
-#define PWM_X_GENB_ACTCMPAD_ONE 0x000000C0  // Set the output signal to 1.
-#define PWM_X_GENB_ACTCMPAU_M   0x00000030  // Action for Comparator A Up.
+                                0x00000080  // Drive pwmB Low
+#define PWM_X_GENB_ACTCMPAD_ONE 0x000000C0  // Drive pwmB High
+#define PWM_X_GENB_ACTCMPAU_M   0x00000030  // Action for Comparator A Up
 #define PWM_X_GENB_ACTCMPAU_NONE \
-                                0x00000000  // Do nothing.
-#define PWM_X_GENB_ACTCMPAU_INV 0x00000010  // Invert the output signal.
+                                0x00000000  // Do nothing
+#define PWM_X_GENB_ACTCMPAU_INV 0x00000010  // Invert pwmB
 #define PWM_X_GENB_ACTCMPAU_ZERO \
-                                0x00000020  // Set the output signal to 0.
-#define PWM_X_GENB_ACTCMPAU_ONE 0x00000030  // Set the output signal to 1.
-#define PWM_X_GENB_ACTLOAD_M    0x0000000C  // Action for Counter=Load.
-#define PWM_X_GENB_ACTLOAD_NONE 0x00000000  // Do nothing.
-#define PWM_X_GENB_ACTLOAD_INV  0x00000004  // Invert the output signal.
-#define PWM_X_GENB_ACTLOAD_ZERO 0x00000008  // Set the output signal to 0.
-#define PWM_X_GENB_ACTLOAD_ONE  0x0000000C  // Set the output signal to 1.
-#define PWM_X_GENB_ACTZERO_M    0x00000003  // Action for Counter=0.
-#define PWM_X_GENB_ACTZERO_NONE 0x00000000  // Do nothing.
-#define PWM_X_GENB_ACTZERO_INV  0x00000001  // Invert the output signal.
-#define PWM_X_GENB_ACTZERO_ZERO 0x00000002  // Set the output signal to 0.
-#define PWM_X_GENB_ACTZERO_ONE  0x00000003  // Set the output signal to 1.
+                                0x00000020  // Drive pwmB Low
+#define PWM_X_GENB_ACTCMPAU_ONE 0x00000030  // Drive pwmB High
+#define PWM_X_GENB_ACTLOAD_M    0x0000000C  // Action for Counter=LOAD
+#define PWM_X_GENB_ACTLOAD_NONE 0x00000000  // Do nothing
+#define PWM_X_GENB_ACTLOAD_INV  0x00000004  // Invert pwmB
+#define PWM_X_GENB_ACTLOAD_ZERO 0x00000008  // Drive pwmB Low
+#define PWM_X_GENB_ACTLOAD_ONE  0x0000000C  // Drive pwmB High
+#define PWM_X_GENB_ACTZERO_M    0x00000003  // Action for Counter=0
+#define PWM_X_GENB_ACTZERO_NONE 0x00000000  // Do nothing
+#define PWM_X_GENB_ACTZERO_INV  0x00000001  // Invert pwmB
+#define PWM_X_GENB_ACTZERO_ZERO 0x00000002  // Drive pwmB Low
+#define PWM_X_GENB_ACTZERO_ONE  0x00000003  // Drive pwmB High
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the PWM_O_0_DBCTL,
-// PWM_O_1_DBCTL, PWM_O_2_DBCTL, and PWM_O_3_DBCTL registers.
+// The following are defines for the bit fields in the PWM_O_X_DBCTL register.
 //
 //*****************************************************************************
-#define PWM_X_DBCTL_ENABLE      0x00000001  // Dead-Band Generator Enable.
+#define PWM_X_DBCTL_ENABLE      0x00000001  // Dead-Band Generator Enable
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the PWM_O_0_DBRISE,
-// PWM_O_1_DBRISE, PWM_O_2_DBRISE, and PWM_O_3_DBRISE registers.
+// The following are defines for the bit fields in the PWM_O_X_DBRISE register.
 //
 //*****************************************************************************
-#define PWM_X_DBRISE_DELAY_M    0x00000FFF  // Dead-Band Rise Delay.
+#define PWM_X_DBRISE_DELAY_M    0x00000FFF  // Dead-Band Rise Delay
 #define PWM_X_DBRISE_DELAY_S    0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the PWM_O_0_DBFALL,
-// PWM_O_1_DBFALL, PWM_O_2_DBFALL, and PWM_O_3_DBFALL registers.
+// The following are defines for the bit fields in the PWM_O_X_DBFALL register.
 //
 //*****************************************************************************
-#define PWM_X_DBFALL_DELAY_M    0x00000FFF  // Dead-Band Fall Delay.
+#define PWM_X_DBFALL_DELAY_M    0x00000FFF  // Dead-Band Fall Delay
 #define PWM_X_DBFALL_DELAY_S    0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the PWM_O_0_FLTSRC0,
-// PWM_O_1_FLTSRC0, PWM_O_2_FLTSRC0, and PWM_O_3_FLTSRC0 registers.
+// The following are defines for the bit fields in the PWM_O_X_FLTSRC0
+// register.
 //
 //*****************************************************************************
-#define PWM_X_FLTSRC0_FAULT3    0x00000008  // Fault3.
-#define PWM_X_FLTSRC0_FAULT2    0x00000004  // Fault2.
-#define PWM_X_FLTSRC0_FAULT1    0x00000002  // Fault1.
-#define PWM_X_FLTSRC0_FAULT0    0x00000001  // Fault0.
+#define PWM_X_FLTSRC0_FAULT3    0x00000008  // Fault3 Input
+#define PWM_X_FLTSRC0_FAULT2    0x00000004  // Fault2 Input
+#define PWM_X_FLTSRC0_FAULT1    0x00000002  // Fault1 Input
+#define PWM_X_FLTSRC0_FAULT0    0x00000001  // Fault0 Input
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the PWM_O_0_FLTSRC1,
-// PWM_O_1_FLTSRC1, PWM_O_2_FLTSRC1, and PWM_O_3_FLTSRC1 registers.
+// The following are defines for the bit fields in the PWM_O_X_FLTSRC1
+// register.
 //
 //*****************************************************************************
-#define PWM_X_FLTSRC1_DCMP7     0x00000080  // Digital Comparator 7.
-#define PWM_X_FLTSRC1_DCMP6     0x00000040  // Digital Comparator 6.
-#define PWM_X_FLTSRC1_DCMP5     0x00000020  // Digital Comparator 5.
-#define PWM_X_FLTSRC1_DCMP4     0x00000010  // Digital Comparator 4.
-#define PWM_X_FLTSRC1_DCMP3     0x00000008  // Digital Comparator 3.
-#define PWM_X_FLTSRC1_DCMP2     0x00000004  // Digital Comparator 2.
-#define PWM_X_FLTSRC1_DCMP1     0x00000002  // Digital Comparator 1.
-#define PWM_X_FLTSRC1_DCMP0     0x00000001  // Digital Comparator 0.
+#define PWM_X_FLTSRC1_DCMP7     0x00000080  // Digital Comparator 7
+#define PWM_X_FLTSRC1_DCMP6     0x00000040  // Digital Comparator 6
+#define PWM_X_FLTSRC1_DCMP5     0x00000020  // Digital Comparator 5
+#define PWM_X_FLTSRC1_DCMP4     0x00000010  // Digital Comparator 4
+#define PWM_X_FLTSRC1_DCMP3     0x00000008  // Digital Comparator 3
+#define PWM_X_FLTSRC1_DCMP2     0x00000004  // Digital Comparator 2
+#define PWM_X_FLTSRC1_DCMP1     0x00000002  // Digital Comparator 1
+#define PWM_X_FLTSRC1_DCMP0     0x00000001  // Digital Comparator 0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the PWM_O_0_MINFLTPER,
-// PWM_O_1_MINFLTPER, PWM_O_2_MINFLTPER, and PWM_O_3_MINFLTPER registers.
+// The following are defines for the bit fields in the PWM_O_X_MINFLTPER
+// register.
 //
 //*****************************************************************************
-#define PWM_X_MINFLTPER_M       0x0000FFFF  // Minimum Fault Period.
+#define PWM_X_MINFLTPER_M       0x0000FFFF  // Minimum Fault Period
 #define PWM_X_MINFLTPER_S       0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the PWM_O_0_FLTSEN,
-// PWM_O_1_FLTSEN, PWM_O_2_FLTSEN, and PWM_O_3_FLTSEN registers.
+// The following are defines for the bit fields in the PWM_O_X_FLTSEN register.
 //
 //*****************************************************************************
-#define PWM_X_FLTSEN_FAULT3     0x00000008  // Fault3 Sense.
-#define PWM_X_FLTSEN_FAULT2     0x00000004  // Fault2 Sense.
-#define PWM_X_FLTSEN_FAULT1     0x00000002  // Fault1 Sense.
-#define PWM_X_FLTSEN_FAULT0     0x00000001  // Fault0 Sense.
+#define PWM_X_FLTSEN_FAULT3     0x00000008  // Fault3 Sense
+#define PWM_X_FLTSEN_FAULT2     0x00000004  // Fault2 Sense
+#define PWM_X_FLTSEN_FAULT1     0x00000002  // Fault1 Sense
+#define PWM_X_FLTSEN_FAULT0     0x00000001  // Fault0 Sense
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the PWM_O_0_FLTSTAT0,
-// PWM_O_1_FLTSTAT0, PWM_O_2_FLTSTAT0, and PWM_O_3_FLTSTAT0 registers.
+// The following are defines for the bit fields in the PWM_O_X_FLTSTAT0
+// register.
 //
 //*****************************************************************************
-#define PWM_X_FLTSTAT0_FAULT3   0x00000008  // Fault Input 3.
-#define PWM_X_FLTSTAT0_FAULT2   0x00000004  // Fault Input 2.
-#define PWM_X_FLTSTAT0_FAULT1   0x00000002  // Fault Input 1.
-#define PWM_X_FLTSTAT0_FAULT0   0x00000001  // Fault Input 0.
+#define PWM_X_FLTSTAT0_FAULT3   0x00000008  // Fault Input 3
+#define PWM_X_FLTSTAT0_FAULT2   0x00000004  // Fault Input 2
+#define PWM_X_FLTSTAT0_FAULT1   0x00000002  // Fault Input 1
+#define PWM_X_FLTSTAT0_FAULT0   0x00000001  // Fault Input 0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the PWM_O_0_FLTSTAT1,
-// PWM_O_1_FLTSTAT1, PWM_O_2_FLTSTAT1, and PWM_O_3_FLTSTAT1 registers.
+// The following are defines for the bit fields in the PWM_O_X_FLTSTAT1
+// register.
 //
 //*****************************************************************************
-#define PWM_X_FLTSTAT1_DCMP7    0x00000080  // Digital Comparator 7 Trigger.
-#define PWM_X_FLTSTAT1_DCMP6    0x00000040  // Digital Comparator 6 Trigger.
-#define PWM_X_FLTSTAT1_DCMP5    0x00000020  // Digital Comparator 5 Trigger.
-#define PWM_X_FLTSTAT1_DCMP4    0x00000010  // Digital Comparator 4 Trigger.
-#define PWM_X_FLTSTAT1_DCMP3    0x00000008  // Digital Comparator 3 Trigger.
-#define PWM_X_FLTSTAT1_DCMP2    0x00000004  // Digital Comparator 2 Trigger.
-#define PWM_X_FLTSTAT1_DCMP1    0x00000002  // Digital Comparator 1 Trigger.
-#define PWM_X_FLTSTAT1_DCMP0    0x00000001  // Digital Comparator 0 Trigger.
+#define PWM_X_FLTSTAT1_DCMP7    0x00000080  // Digital Comparator 7 Trigger
+#define PWM_X_FLTSTAT1_DCMP6    0x00000040  // Digital Comparator 6 Trigger
+#define PWM_X_FLTSTAT1_DCMP5    0x00000020  // Digital Comparator 5 Trigger
+#define PWM_X_FLTSTAT1_DCMP4    0x00000010  // Digital Comparator 4 Trigger
+#define PWM_X_FLTSTAT1_DCMP3    0x00000008  // Digital Comparator 3 Trigger
+#define PWM_X_FLTSTAT1_DCMP2    0x00000004  // Digital Comparator 2 Trigger
+#define PWM_X_FLTSTAT1_DCMP1    0x00000002  // Digital Comparator 1 Trigger
+#define PWM_X_FLTSTAT1_DCMP0    0x00000001  // Digital Comparator 0 Trigger
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the QEI_O_CTL register.
 //
 //*****************************************************************************
-#define QEI_CTL_FILTCNT_M       0x000F0000  // Input Filter Pre-Scale Count.
-#define QEI_CTL_FILTEN          0x00002000  // Enable Input Filter.
-#define QEI_CTL_STALLEN         0x00001000  // Stall QEI.
-#define QEI_CTL_INVI            0x00000800  // Invert Index Pulse.
-#define QEI_CTL_INVB            0x00000400  // Invert PhB.
-#define QEI_CTL_INVA            0x00000200  // Invert PhA.
-#define QEI_CTL_VELDIV_M        0x000001C0  // Predivide Velocity.
-#define QEI_CTL_VELDIV_1        0x00000000  // /1
-#define QEI_CTL_VELDIV_2        0x00000040  // /2
-#define QEI_CTL_VELDIV_4        0x00000080  // /4
-#define QEI_CTL_VELDIV_8        0x000000C0  // /8
-#define QEI_CTL_VELDIV_16       0x00000100  // /16
-#define QEI_CTL_VELDIV_32       0x00000140  // /32
-#define QEI_CTL_VELDIV_64       0x00000180  // /64
-#define QEI_CTL_VELDIV_128      0x000001C0  // /128
-#define QEI_CTL_VELEN           0x00000020  // Capture Velocity.
-#define QEI_CTL_RESMODE         0x00000010  // Reset Mode.
-#define QEI_CTL_CAPMODE         0x00000008  // Capture Mode.
-#define QEI_CTL_SIGMODE         0x00000004  // Signal Mode.
-#define QEI_CTL_SWAP            0x00000002  // Swap Signals.
-#define QEI_CTL_ENABLE          0x00000001  // Enable QEI.
+#define QEI_CTL_FILTCNT_M       0x000F0000  // Input Filter Prescale Count
+#define QEI_CTL_FILTEN          0x00002000  // Enable Input Filter
+#define QEI_CTL_STALLEN         0x00001000  // Stall QEI
+#define QEI_CTL_INVI            0x00000800  // Invert Index Pulse
+#define QEI_CTL_INVB            0x00000400  // Invert PhB
+#define QEI_CTL_INVA            0x00000200  // Invert PhA
+#define QEI_CTL_VELDIV_M        0x000001C0  // Predivide Velocity
+#define QEI_CTL_VELDIV_1        0x00000000  // QEI clock /1
+#define QEI_CTL_VELDIV_2        0x00000040  // QEI clock /2
+#define QEI_CTL_VELDIV_4        0x00000080  // QEI clock /4
+#define QEI_CTL_VELDIV_8        0x000000C0  // QEI clock /8
+#define QEI_CTL_VELDIV_16       0x00000100  // QEI clock /16
+#define QEI_CTL_VELDIV_32       0x00000140  // QEI clock /32
+#define QEI_CTL_VELDIV_64       0x00000180  // QEI clock /64
+#define QEI_CTL_VELDIV_128      0x000001C0  // QEI clock /128
+#define QEI_CTL_VELEN           0x00000020  // Capture Velocity
+#define QEI_CTL_RESMODE         0x00000010  // Reset Mode
+#define QEI_CTL_CAPMODE         0x00000008  // Capture Mode
+#define QEI_CTL_SIGMODE         0x00000004  // Signal Mode
+#define QEI_CTL_SWAP            0x00000002  // Swap Signals
+#define QEI_CTL_ENABLE          0x00000001  // Enable QEI
 #define QEI_CTL_FILTCNT_S       16
 
 //*****************************************************************************
@@ -2937,8 +3379,8 @@
 // The following are defines for the bit fields in the QEI_O_STAT register.
 //
 //*****************************************************************************
-#define QEI_STAT_DIRECTION      0x00000002  // Direction of Rotation.
-#define QEI_STAT_ERROR          0x00000001  // Error Detected.
+#define QEI_STAT_DIRECTION      0x00000002  // Direction of Rotation
+#define QEI_STAT_ERROR          0x00000001  // Error Detected
 
 //*****************************************************************************
 //
@@ -2946,7 +3388,7 @@
 //
 //*****************************************************************************
 #define QEI_POS_M               0xFFFFFFFF  // Current Position Integrator
-                                            // Value.
+                                            // Value
 #define QEI_POS_S               0
 
 //*****************************************************************************
@@ -2955,7 +3397,7 @@
 //
 //*****************************************************************************
 #define QEI_MAXPOS_M            0xFFFFFFFF  // Maximum Position Integrator
-                                            // Value.
+                                            // Value
 #define QEI_MAXPOS_S            0
 
 //*****************************************************************************
@@ -2963,7 +3405,7 @@
 // The following are defines for the bit fields in the QEI_O_LOAD register.
 //
 //*****************************************************************************
-#define QEI_LOAD_M              0xFFFFFFFF  // Velocity Timer Load Value.
+#define QEI_LOAD_M              0xFFFFFFFF  // Velocity Timer Load Value
 #define QEI_LOAD_S              0
 
 //*****************************************************************************
@@ -2971,7 +3413,7 @@
 // The following are defines for the bit fields in the QEI_O_TIME register.
 //
 //*****************************************************************************
-#define QEI_TIME_M              0xFFFFFFFF  // Velocity Timer Current Value.
+#define QEI_TIME_M              0xFFFFFFFF  // Velocity Timer Current Value
 #define QEI_TIME_S              0
 
 //*****************************************************************************
@@ -2979,7 +3421,7 @@
 // The following are defines for the bit fields in the QEI_O_COUNT register.
 //
 //*****************************************************************************
-#define QEI_COUNT_M             0xFFFFFFFF  // Velocity Pulse Count.
+#define QEI_COUNT_M             0xFFFFFFFF  // Velocity Pulse Count
 #define QEI_COUNT_S             0
 
 //*****************************************************************************
@@ -2987,7 +3429,7 @@
 // The following are defines for the bit fields in the QEI_O_SPEED register.
 //
 //*****************************************************************************
-#define QEI_SPEED_M             0xFFFFFFFF  // Velocity.
+#define QEI_SPEED_M             0xFFFFFFFF  // Velocity
 #define QEI_SPEED_S             0
 
 //*****************************************************************************
@@ -2995,61 +3437,60 @@
 // The following are defines for the bit fields in the QEI_O_INTEN register.
 //
 //*****************************************************************************
-#define QEI_INTEN_ERROR         0x00000008  // Phase Error Interrupt Enable.
+#define QEI_INTEN_ERROR         0x00000008  // Phase Error Interrupt Enable
 #define QEI_INTEN_DIR           0x00000004  // Direction Change Interrupt
-                                            // Enable.
-#define QEI_INTEN_TIMER         0x00000002  // Timer Expires Interrupt Enable.
+                                            // Enable
+#define QEI_INTEN_TIMER         0x00000002  // Timer Expires Interrupt Enable
 #define QEI_INTEN_INDEX         0x00000001  // Index Pulse Detected Interrupt
-                                            // Enable.
+                                            // Enable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the QEI_O_RIS register.
 //
 //*****************************************************************************
-#define QEI_RIS_ERROR           0x00000008  // Phase Error Detected.
-#define QEI_RIS_DIR             0x00000004  // Direction Change Detected.
-#define QEI_RIS_TIMER           0x00000002  // Velocity Timer Expired.
-#define QEI_RIS_INDEX           0x00000001  // Index Pulse Asserted.
+#define QEI_RIS_ERROR           0x00000008  // Phase Error Detected
+#define QEI_RIS_DIR             0x00000004  // Direction Change Detected
+#define QEI_RIS_TIMER           0x00000002  // Velocity Timer Expired
+#define QEI_RIS_INDEX           0x00000001  // Index Pulse Asserted
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the QEI_O_ISC register.
 //
 //*****************************************************************************
-#define QEI_ISC_ERROR           0x00000008  // Phase Error Interrupt.
-#define QEI_ISC_DIR             0x00000004  // Direction Change Interrupt.
-#define QEI_ISC_TIMER           0x00000002  // Velocity Timer Expired
-                                            // Interrupt.
-#define QEI_ISC_INDEX           0x00000001  // Index Pulse Interrupt.
+#define QEI_ISC_ERROR           0x00000008  // Phase Error Interrupt
+#define QEI_ISC_DIR             0x00000004  // Direction Change Interrupt
+#define QEI_ISC_TIMER           0x00000002  // Velocity Timer Expired Interrupt
+#define QEI_ISC_INDEX           0x00000001  // Index Pulse Interrupt
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the TIMER_O_CFG register.
 //
 //*****************************************************************************
-#define TIMER_CFG_M             0x00000007  // GPTM Configuration.
-#define TIMER_CFG_32_BIT_TIMER  0x00000000  // 32-bit timer configuration.
+#define TIMER_CFG_M             0x00000007  // GPTM Configuration
+#define TIMER_CFG_32_BIT_TIMER  0x00000000  // 32-bit timer configuration
 #define TIMER_CFG_32_BIT_RTC    0x00000001  // 32-bit real-time clock (RTC)
-                                            // counter configuration.
-#define TIMER_CFG_16_BIT        0x00000004  // 16-bit timer configuration,
+                                            // counter configuration
+#define TIMER_CFG_16_BIT        0x00000004  // 16-bit timer configuration. The
                                             // function is controlled by bits
-                                            // 1:0 of GPTMTAMR and GPTMTBMR.
+                                            // 1:0 of GPTMTAMR and GPTMTBMR
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the TIMER_O_TAMR register.
 //
 //*****************************************************************************
-#define TIMER_TAMR_TASNAPS      0x00000080  // GPTM Timer A Snap-Shot Mode.
-#define TIMER_TAMR_TAWOT        0x00000040  // GPTM Timer A Wait-on-Trigger.
+#define TIMER_TAMR_TASNAPS      0x00000080  // GPTM Timer A Snap-Shot Mode
+#define TIMER_TAMR_TAWOT        0x00000040  // GPTM Timer A Wait-on-Trigger
 #define TIMER_TAMR_TAMIE        0x00000020  // GPTM Timer A Match Interrupt
-                                            // Enable.
-#define TIMER_TAMR_TACDIR       0x00000010  // GPTM Timer A Count Direction.
+                                            // Enable
+#define TIMER_TAMR_TACDIR       0x00000010  // GPTM Timer A Count Direction
 #define TIMER_TAMR_TAAMS        0x00000008  // GPTM Timer A Alternate Mode
-                                            // Select.
-#define TIMER_TAMR_TACMR        0x00000004  // GPTM Timer A Capture Mode.
-#define TIMER_TAMR_TAMR_M       0x00000003  // GPTM Timer A Mode.
+                                            // Select
+#define TIMER_TAMR_TACMR        0x00000004  // GPTM Timer A Capture Mode
+#define TIMER_TAMR_TAMR_M       0x00000003  // GPTM Timer A Mode
 #define TIMER_TAMR_TAMR_1_SHOT  0x00000001  // One-Shot Timer mode
 #define TIMER_TAMR_TAMR_PERIOD  0x00000002  // Periodic Timer mode
 #define TIMER_TAMR_TAMR_CAP     0x00000003  // Capture mode
@@ -3059,15 +3500,15 @@
 // The following are defines for the bit fields in the TIMER_O_TBMR register.
 //
 //*****************************************************************************
-#define TIMER_TBMR_TBSNAPS      0x00000080  // GPTM Timer B Snap-Shot Mode.
-#define TIMER_TBMR_TBWOT        0x00000040  // GPTM Timer B Wait-on-Trigger.
+#define TIMER_TBMR_TBSNAPS      0x00000080  // GPTM Timer B Snap-Shot Mode
+#define TIMER_TBMR_TBWOT        0x00000040  // GPTM Timer B Wait-on-Trigger
 #define TIMER_TBMR_TBMIE        0x00000020  // GPTM Timer B Match Interrupt
-                                            // Enable.
-#define TIMER_TBMR_TBCDIR       0x00000010  // GPTM Timer B Count Direction.
+                                            // Enable
+#define TIMER_TBMR_TBCDIR       0x00000010  // GPTM Timer B Count Direction
 #define TIMER_TBMR_TBAMS        0x00000008  // GPTM Timer B Alternate Mode
-                                            // Select.
-#define TIMER_TBMR_TBCMR        0x00000004  // GPTM Timer B Capture Mode.
-#define TIMER_TBMR_TBMR_M       0x00000003  // GPTM Timer B Mode.
+                                            // Select
+#define TIMER_TBMR_TBCMR        0x00000004  // GPTM Timer B Capture Mode
+#define TIMER_TBMR_TBMR_M       0x00000003  // GPTM Timer B Mode
 #define TIMER_TBMR_TBMR_1_SHOT  0x00000001  // One-Shot Timer mode
 #define TIMER_TBMR_TBMR_PERIOD  0x00000002  // Periodic Timer mode
 #define TIMER_TBMR_TBMR_CAP     0x00000003  // Capture mode
@@ -3077,25 +3518,25 @@
 // The following are defines for the bit fields in the TIMER_O_CTL register.
 //
 //*****************************************************************************
-#define TIMER_CTL_TBPWML        0x00004000  // GPTM Timer B PWM Output Level.
+#define TIMER_CTL_TBPWML        0x00004000  // GPTM Timer B PWM Output Level
 #define TIMER_CTL_TBOTE         0x00002000  // GPTM Timer B Output Trigger
-                                            // Enable.
-#define TIMER_CTL_TBEVENT_M     0x00000C00  // GPTM Timer B Event Mode.
+                                            // Enable
+#define TIMER_CTL_TBEVENT_M     0x00000C00  // GPTM Timer B Event Mode
 #define TIMER_CTL_TBEVENT_POS   0x00000000  // Positive edge
 #define TIMER_CTL_TBEVENT_NEG   0x00000400  // Negative edge
 #define TIMER_CTL_TBEVENT_BOTH  0x00000C00  // Both edges
-#define TIMER_CTL_TBSTALL       0x00000200  // GPTM Timer B Stall Enable.
-#define TIMER_CTL_TBEN          0x00000100  // GPTM Timer B Enable.
-#define TIMER_CTL_TAPWML        0x00000040  // GPTM Timer A PWM Output Level.
+#define TIMER_CTL_TBSTALL       0x00000200  // GPTM Timer B Stall Enable
+#define TIMER_CTL_TBEN          0x00000100  // GPTM Timer B Enable
+#define TIMER_CTL_TAPWML        0x00000040  // GPTM Timer A PWM Output Level
 #define TIMER_CTL_TAOTE         0x00000020  // GPTM Timer A Output Trigger
-                                            // Enable.
-#define TIMER_CTL_RTCEN         0x00000010  // GPTM RTC Enable.
-#define TIMER_CTL_TAEVENT_M     0x0000000C  // GPTM Timer A Event Mode.
+                                            // Enable
+#define TIMER_CTL_RTCEN         0x00000010  // GPTM RTC Enable
+#define TIMER_CTL_TAEVENT_M     0x0000000C  // GPTM Timer A Event Mode
 #define TIMER_CTL_TAEVENT_POS   0x00000000  // Positive edge
 #define TIMER_CTL_TAEVENT_NEG   0x00000004  // Negative edge
 #define TIMER_CTL_TAEVENT_BOTH  0x0000000C  // Both edges
-#define TIMER_CTL_TASTALL       0x00000002  // GPTM Timer A Stall Enable.
-#define TIMER_CTL_TAEN          0x00000001  // GPTM Timer A Enable.
+#define TIMER_CTL_TASTALL       0x00000002  // GPTM Timer A Stall Enable
+#define TIMER_CTL_TAEN          0x00000001  // GPTM Timer A Enable
 
 //*****************************************************************************
 //
@@ -3103,22 +3544,22 @@
 //
 //*****************************************************************************
 #define TIMER_IMR_TBMIM         0x00000800  // GPTM Timer B Mode Match
-                                            // Interrupt Mask.
+                                            // Interrupt Mask
 #define TIMER_IMR_CBEIM         0x00000400  // GPTM Capture B Event Interrupt
-                                            // Mask.
+                                            // Mask
 #define TIMER_IMR_CBMIM         0x00000200  // GPTM Capture B Match Interrupt
-                                            // Mask.
+                                            // Mask
 #define TIMER_IMR_TBTOIM        0x00000100  // GPTM Timer B Time-Out Interrupt
-                                            // Mask.
+                                            // Mask
 #define TIMER_IMR_TAMIM         0x00000010  // GPTM Timer A Mode Match
-                                            // Interrupt Mask.
-#define TIMER_IMR_RTCIM         0x00000008  // GPTM RTC Interrupt Mask.
+                                            // Interrupt Mask
+#define TIMER_IMR_RTCIM         0x00000008  // GPTM RTC Interrupt Mask
 #define TIMER_IMR_CAEIM         0x00000004  // GPTM Capture A Event Interrupt
-                                            // Mask.
+                                            // Mask
 #define TIMER_IMR_CAMIM         0x00000002  // GPTM Capture A Match Interrupt
-                                            // Mask.
+                                            // Mask
 #define TIMER_IMR_TATOIM        0x00000001  // GPTM Timer A Time-Out Interrupt
-                                            // Mask.
+                                            // Mask
 
 //*****************************************************************************
 //
@@ -3126,22 +3567,22 @@
 //
 //*****************************************************************************
 #define TIMER_RIS_TBMRIS        0x00000800  // GPTM Timer B Mode Match Raw
-                                            // Interrupt.
+                                            // Interrupt
 #define TIMER_RIS_CBERIS        0x00000400  // GPTM Capture B Event Raw
-                                            // Interrupt.
+                                            // Interrupt
 #define TIMER_RIS_CBMRIS        0x00000200  // GPTM Capture B Match Raw
-                                            // Interrupt.
+                                            // Interrupt
 #define TIMER_RIS_TBTORIS       0x00000100  // GPTM Timer B Time-Out Raw
-                                            // Interrupt.
+                                            // Interrupt
 #define TIMER_RIS_TAMRIS        0x00000010  // GPTM Timer A Mode Match Raw
-                                            // Interrupt.
-#define TIMER_RIS_RTCRIS        0x00000008  // GPTM RTC Raw Interrupt.
+                                            // Interrupt
+#define TIMER_RIS_RTCRIS        0x00000008  // GPTM RTC Raw Interrupt
 #define TIMER_RIS_CAERIS        0x00000004  // GPTM Capture A Event Raw
-                                            // Interrupt.
+                                            // Interrupt
 #define TIMER_RIS_CAMRIS        0x00000002  // GPTM Capture A Match Raw
-                                            // Interrupt.
+                                            // Interrupt
 #define TIMER_RIS_TATORIS       0x00000001  // GPTM Timer A Time-Out Raw
-                                            // Interrupt.
+                                            // Interrupt
 
 //*****************************************************************************
 //
@@ -3149,22 +3590,22 @@
 //
 //*****************************************************************************
 #define TIMER_MIS_TBMMIS        0x00000800  // GPTM Timer B Mode Match Masked
-                                            // Interrupt.
+                                            // Interrupt
 #define TIMER_MIS_CBEMIS        0x00000400  // GPTM Capture B Event Masked
-                                            // Interrupt.
+                                            // Interrupt
 #define TIMER_MIS_CBMMIS        0x00000200  // GPTM Capture B Match Masked
-                                            // Interrupt.
+                                            // Interrupt
 #define TIMER_MIS_TBTOMIS       0x00000100  // GPTM Timer B Time-Out Masked
-                                            // Interrupt.
+                                            // Interrupt
 #define TIMER_MIS_TAMMIS        0x00000010  // GPTM Timer A Mode Match Masked
-                                            // Interrupt.
-#define TIMER_MIS_RTCMIS        0x00000008  // GPTM RTC Masked Interrupt.
+                                            // Interrupt
+#define TIMER_MIS_RTCMIS        0x00000008  // GPTM RTC Masked Interrupt
 #define TIMER_MIS_CAEMIS        0x00000004  // GPTM Capture A Event Masked
-                                            // Interrupt.
+                                            // Interrupt
 #define TIMER_MIS_CAMMIS        0x00000002  // GPTM Capture A Match Masked
-                                            // Interrupt.
+                                            // Interrupt
 #define TIMER_MIS_TATOMIS       0x00000001  // GPTM Timer A Time-Out Masked
-                                            // Interrupt.
+                                            // Interrupt
 
 //*****************************************************************************
 //
@@ -3172,22 +3613,22 @@
 //
 //*****************************************************************************
 #define TIMER_ICR_TBMCINT       0x00000800  // GPTM Timer B Mode Match
-                                            // Interrupt Clear.
+                                            // Interrupt Clear
 #define TIMER_ICR_CBECINT       0x00000400  // GPTM Capture B Event Interrupt
-                                            // Clear.
+                                            // Clear
 #define TIMER_ICR_CBMCINT       0x00000200  // GPTM Capture B Match Interrupt
-                                            // Clear.
+                                            // Clear
 #define TIMER_ICR_TBTOCINT      0x00000100  // GPTM Timer B Time-Out Interrupt
-                                            // Clear.
+                                            // Clear
 #define TIMER_ICR_TAMCINT       0x00000010  // GPTM Timer A Mode Match
-                                            // Interrupt Clear.
-#define TIMER_ICR_RTCCINT       0x00000008  // GPTM RTC Interrupt Clear.
+                                            // Interrupt Clear
+#define TIMER_ICR_RTCCINT       0x00000008  // GPTM RTC Interrupt Clear
 #define TIMER_ICR_CAECINT       0x00000004  // GPTM Capture A Event Interrupt
-                                            // Clear.
+                                            // Clear
 #define TIMER_ICR_CAMCINT       0x00000002  // GPTM Capture A Match Interrupt
-                                            // Clear.
+                                            // Clear
 #define TIMER_ICR_TATOCINT      0x00000001  // GPTM Timer A Time-Out Raw
-                                            // Interrupt.
+                                            // Interrupt
 
 //*****************************************************************************
 //
@@ -3195,9 +3636,9 @@
 //
 //*****************************************************************************
 #define TIMER_TAILR_TAILRH_M    0xFFFF0000  // GPTM Timer A Interval Load
-                                            // Register High.
+                                            // Register High
 #define TIMER_TAILR_TAILRL_M    0x0000FFFF  // GPTM Timer A Interval Load
-                                            // Register Low.
+                                            // Register Low
 #define TIMER_TAILR_TAILRH_S    16
 #define TIMER_TAILR_TAILRL_S    0
 
@@ -3207,7 +3648,7 @@
 //
 //*****************************************************************************
 #define TIMER_TBILR_TBILRL_M    0x0000FFFF  // GPTM Timer B Interval Load
-                                            // Register.
+                                            // Register
 #define TIMER_TBILR_TBILRL_S    0
 
 //*****************************************************************************
@@ -3216,9 +3657,8 @@
 // register.
 //
 //*****************************************************************************
-#define TIMER_TAMATCHR_TAMRH_M  0xFFFF0000  // GPTM Timer A Match Register
-                                            // High.
-#define TIMER_TAMATCHR_TAMRL_M  0x0000FFFF  // GPTM Timer A Match Register Low.
+#define TIMER_TAMATCHR_TAMRH_M  0xFFFF0000  // GPTM Timer A Match Register High
+#define TIMER_TAMATCHR_TAMRL_M  0x0000FFFF  // GPTM Timer A Match Register Low
 #define TIMER_TAMATCHR_TAMRH_S  16
 #define TIMER_TAMATCHR_TAMRL_S  0
 
@@ -3228,7 +3668,7 @@
 // register.
 //
 //*****************************************************************************
-#define TIMER_TBMATCHR_TBMRL_M  0x0000FFFF  // GPTM Timer B Match Register Low.
+#define TIMER_TBMATCHR_TBMRL_M  0x0000FFFF  // GPTM Timer B Match Register Low
 #define TIMER_TBMATCHR_TBMRL_S  0
 
 //*****************************************************************************
@@ -3236,7 +3676,7 @@
 // The following are defines for the bit fields in the TIMER_O_TAPR register.
 //
 //*****************************************************************************
-#define TIMER_TAPR_TAPSR_M      0x000000FF  // GPTM Timer A Prescale.
+#define TIMER_TAPR_TAPSR_M      0x000000FF  // GPTM Timer A Prescale
 #define TIMER_TAPR_TAPSR_S      0
 
 //*****************************************************************************
@@ -3244,16 +3684,32 @@
 // The following are defines for the bit fields in the TIMER_O_TBPR register.
 //
 //*****************************************************************************
-#define TIMER_TBPR_TBPSR_M      0x000000FF  // GPTM Timer B Prescale.
+#define TIMER_TBPR_TBPSR_M      0x000000FF  // GPTM Timer B Prescale
 #define TIMER_TBPR_TBPSR_S      0
 
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAPMR register.
+//
+//*****************************************************************************
+#define TIMER_TAPMR_TAPSMR_M    0x000000FF  // GPTM TimerA Prescale Match
+#define TIMER_TAPMR_TAPSMR_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBPMR register.
+//
+//*****************************************************************************
+#define TIMER_TBPMR_TBPSMR_M    0x000000FF  // GPTM TimerB Prescale Match
+#define TIMER_TBPMR_TBPSMR_S    0
+
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the TIMER_O_TAR register.
 //
 //*****************************************************************************
-#define TIMER_TAR_TARH_M        0xFFFF0000  // GPTM Timer A Register High.
-#define TIMER_TAR_TARL_M        0x0000FFFF  // GPTM Timer A Register Low.
+#define TIMER_TAR_TARH_M        0xFFFF0000  // GPTM Timer A Register High
+#define TIMER_TAR_TARL_M        0x0000FFFF  // GPTM Timer A Register Low
 #define TIMER_TAR_TARH_S        16
 #define TIMER_TAR_TARL_S        0
 
@@ -3262,7 +3718,7 @@
 // The following are defines for the bit fields in the TIMER_O_TBR register.
 //
 //*****************************************************************************
-#define TIMER_TBR_TBRL_M        0x0000FFFF  // GPTM Timer B.
+#define TIMER_TBR_TBRL_M        0x00FFFFFF  // GPTM Timer B
 #define TIMER_TBR_TBRL_S        0
 
 //*****************************************************************************
@@ -3270,8 +3726,8 @@
 // The following are defines for the bit fields in the TIMER_O_TAV register.
 //
 //*****************************************************************************
-#define TIMER_TAV_TAVH_M        0xFFFF0000  // GPTM Timer A Value High.
-#define TIMER_TAV_TAVL_M        0x0000FFFF  // GPTM Timer A Register Low.
+#define TIMER_TAV_TAVH_M        0xFFFF0000  // GPTM Timer A Value High
+#define TIMER_TAV_TAVL_M        0x0000FFFF  // GPTM Timer A Register Low
 #define TIMER_TAV_TAVH_S        16
 #define TIMER_TAV_TAVL_S        0
 
@@ -3280,7 +3736,7 @@
 // The following are defines for the bit fields in the TIMER_O_TBV register.
 //
 //*****************************************************************************
-#define TIMER_TBV_TBVL_M        0x0000FFFF  // GPTM Timer B Register.
+#define TIMER_TBV_TBVL_M        0x0000FFFF  // GPTM Timer B Register
 #define TIMER_TBV_TBVL_S        0
 
 //*****************************************************************************
@@ -3288,10 +3744,10 @@
 // The following are defines for the bit fields in the ADC_O_ACTSS register.
 //
 //*****************************************************************************
-#define ADC_ACTSS_ASEN3         0x00000008  // ADC SS3 Enable.
-#define ADC_ACTSS_ASEN2         0x00000004  // ADC SS2 Enable.
-#define ADC_ACTSS_ASEN1         0x00000002  // ADC SS1 Enable.
-#define ADC_ACTSS_ASEN0         0x00000001  // ADC SS0 Enable.
+#define ADC_ACTSS_ASEN3         0x00000008  // ADC SS3 Enable
+#define ADC_ACTSS_ASEN2         0x00000004  // ADC SS2 Enable
+#define ADC_ACTSS_ASEN1         0x00000002  // ADC SS1 Enable
+#define ADC_ACTSS_ASEN0         0x00000001  // ADC SS0 Enable
 
 //*****************************************************************************
 //
@@ -3299,11 +3755,11 @@
 //
 //*****************************************************************************
 #define ADC_RIS_INRDC           0x00010000  // Digital Comparator Raw Interrupt
-                                            // Status.
-#define ADC_RIS_INR3            0x00000008  // SS3 Raw Interrupt Status.
-#define ADC_RIS_INR2            0x00000004  // SS2 Raw Interrupt Status.
-#define ADC_RIS_INR1            0x00000002  // SS1 Raw Interrupt Status.
-#define ADC_RIS_INR0            0x00000001  // SS0 Raw Interrupt Status.
+                                            // Status
+#define ADC_RIS_INR3            0x00000008  // SS3 Raw Interrupt Status
+#define ADC_RIS_INR2            0x00000004  // SS2 Raw Interrupt Status
+#define ADC_RIS_INR1            0x00000002  // SS1 Raw Interrupt Status
+#define ADC_RIS_INR0            0x00000001  // SS0 Raw Interrupt Status
 
 //*****************************************************************************
 //
@@ -3311,17 +3767,17 @@
 //
 //*****************************************************************************
 #define ADC_IM_DCONSS3          0x00080000  // Digital Comparator Interrupt on
-                                            // SS3.
+                                            // SS3
 #define ADC_IM_DCONSS2          0x00040000  // Digital Comparator Interrupt on
-                                            // SS2.
+                                            // SS2
 #define ADC_IM_DCONSS1          0x00020000  // Digital Comparator Interrupt on
-                                            // SS1.
+                                            // SS1
 #define ADC_IM_DCONSS0          0x00010000  // Digital Comparator Interrupt on
-                                            // SS0.
-#define ADC_IM_MASK3            0x00000008  // SS3 Interrupt Mask.
-#define ADC_IM_MASK2            0x00000004  // SS2 Interrupt Mask.
-#define ADC_IM_MASK1            0x00000002  // SS1 Interrupt Mask.
-#define ADC_IM_MASK0            0x00000001  // SS0 Interrupt Mask.
+                                            // SS0
+#define ADC_IM_MASK3            0x00000008  // SS3 Interrupt Mask
+#define ADC_IM_MASK2            0x00000004  // SS2 Interrupt Mask
+#define ADC_IM_MASK1            0x00000002  // SS1 Interrupt Mask
+#define ADC_IM_MASK0            0x00000001  // SS0 Interrupt Mask
 
 //*****************************************************************************
 //
@@ -3329,34 +3785,34 @@
 //
 //*****************************************************************************
 #define ADC_ISC_DCINSS3         0x00080000  // Digital Comparator Interrupt
-                                            // Status on SS3.
+                                            // Status on SS3
 #define ADC_ISC_DCINSS2         0x00040000  // Digital Comparator Interrupt
-                                            // Status on SS2.
+                                            // Status on SS2
 #define ADC_ISC_DCINSS1         0x00020000  // Digital Comparator Interrupt
-                                            // Status on SS1.
+                                            // Status on SS1
 #define ADC_ISC_DCINSS0         0x00010000  // Digital Comparator Interrupt
-                                            // Status on SS0.
-#define ADC_ISC_IN3             0x00000008  // SS3 Interrupt Status and Clear.
-#define ADC_ISC_IN2             0x00000004  // SS2 Interrupt Status and Clear.
-#define ADC_ISC_IN1             0x00000002  // SS1 Interrupt Status and Clear.
-#define ADC_ISC_IN0             0x00000001  // SS0 Interrupt Status and Clear.
+                                            // Status on SS0
+#define ADC_ISC_IN3             0x00000008  // SS3 Interrupt Status and Clear
+#define ADC_ISC_IN2             0x00000004  // SS2 Interrupt Status and Clear
+#define ADC_ISC_IN1             0x00000002  // SS1 Interrupt Status and Clear
+#define ADC_ISC_IN0             0x00000001  // SS0 Interrupt Status and Clear
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the ADC_O_OSTAT register.
 //
 //*****************************************************************************
-#define ADC_OSTAT_OV3           0x00000008  // SS3 FIFO Overflow.
-#define ADC_OSTAT_OV2           0x00000004  // SS2 FIFO Overflow.
-#define ADC_OSTAT_OV1           0x00000002  // SS1 FIFO Overflow.
-#define ADC_OSTAT_OV0           0x00000001  // SS0 FIFO Overflow.
+#define ADC_OSTAT_OV3           0x00000008  // SS3 FIFO Overflow
+#define ADC_OSTAT_OV2           0x00000004  // SS2 FIFO Overflow
+#define ADC_OSTAT_OV1           0x00000002  // SS1 FIFO Overflow
+#define ADC_OSTAT_OV0           0x00000001  // SS0 FIFO Overflow
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the ADC_O_EMUX register.
 //
 //*****************************************************************************
-#define ADC_EMUX_EM3_M          0x0000F000  // SS3 Trigger Select.
+#define ADC_EMUX_EM3_M          0x0000F000  // SS3 Trigger Select
 #define ADC_EMUX_EM3_PROCESSOR  0x00000000  // Processor (default)
 #define ADC_EMUX_EM3_COMP0      0x00001000  // Analog Comparator 0
 #define ADC_EMUX_EM3_COMP1      0x00002000  // Analog Comparator 1
@@ -3368,7 +3824,7 @@
 #define ADC_EMUX_EM3_PWM2       0x00008000  // PWM2
 #define ADC_EMUX_EM3_PWM3       0x00009000  // PWM3
 #define ADC_EMUX_EM3_ALWAYS     0x0000F000  // Always (continuously sample)
-#define ADC_EMUX_EM2_M          0x00000F00  // SS2 Trigger Select.
+#define ADC_EMUX_EM2_M          0x00000F00  // SS2 Trigger Select
 #define ADC_EMUX_EM2_PROCESSOR  0x00000000  // Processor (default)
 #define ADC_EMUX_EM2_COMP0      0x00000100  // Analog Comparator 0
 #define ADC_EMUX_EM2_COMP1      0x00000200  // Analog Comparator 1
@@ -3380,7 +3836,7 @@
 #define ADC_EMUX_EM2_PWM2       0x00000800  // PWM2
 #define ADC_EMUX_EM2_PWM3       0x00000900  // PWM3
 #define ADC_EMUX_EM2_ALWAYS     0x00000F00  // Always (continuously sample)
-#define ADC_EMUX_EM1_M          0x000000F0  // SS1 Trigger Select.
+#define ADC_EMUX_EM1_M          0x000000F0  // SS1 Trigger Select
 #define ADC_EMUX_EM1_PROCESSOR  0x00000000  // Processor (default)
 #define ADC_EMUX_EM1_COMP0      0x00000010  // Analog Comparator 0
 #define ADC_EMUX_EM1_COMP1      0x00000020  // Analog Comparator 1
@@ -3392,7 +3848,7 @@
 #define ADC_EMUX_EM1_PWM2       0x00000080  // PWM2
 #define ADC_EMUX_EM1_PWM3       0x00000090  // PWM3
 #define ADC_EMUX_EM1_ALWAYS     0x000000F0  // Always (continuously sample)
-#define ADC_EMUX_EM0_M          0x0000000F  // SS0 Trigger Select.
+#define ADC_EMUX_EM0_M          0x0000000F  // SS0 Trigger Select
 #define ADC_EMUX_EM0_PROCESSOR  0x00000000  // Processor (default)
 #define ADC_EMUX_EM0_COMP0      0x00000001  // Analog Comparator 0
 #define ADC_EMUX_EM0_COMP1      0x00000002  // Analog Comparator 1
@@ -3410,55 +3866,78 @@
 // The following are defines for the bit fields in the ADC_O_USTAT register.
 //
 //*****************************************************************************
-#define ADC_USTAT_UV3           0x00000008  // SS3 FIFO Underflow.
-#define ADC_USTAT_UV2           0x00000004  // SS2 FIFO Underflow.
-#define ADC_USTAT_UV1           0x00000002  // SS1 FIFO Underflow.
-#define ADC_USTAT_UV0           0x00000001  // SS0 FIFO Underflow.
+#define ADC_USTAT_UV3           0x00000008  // SS3 FIFO Underflow
+#define ADC_USTAT_UV2           0x00000004  // SS2 FIFO Underflow
+#define ADC_USTAT_UV1           0x00000002  // SS1 FIFO Underflow
+#define ADC_USTAT_UV0           0x00000001  // SS0 FIFO Underflow
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the ADC_O_SSPRI register.
 //
 //*****************************************************************************
-#define ADC_SSPRI_SS3_M         0x00003000  // SS3 Priority.
+#define ADC_SSPRI_SS3_M         0x00003000  // SS3 Priority
 #define ADC_SSPRI_SS3_1ST       0x00000000  // First priority
 #define ADC_SSPRI_SS3_2ND       0x00001000  // Second priority
 #define ADC_SSPRI_SS3_3RD       0x00002000  // Third priority
 #define ADC_SSPRI_SS3_4TH       0x00003000  // Fourth priority
-#define ADC_SSPRI_SS2_M         0x00000300  // SS2 Priority.
+#define ADC_SSPRI_SS2_M         0x00000300  // SS2 Priority
 #define ADC_SSPRI_SS2_1ST       0x00000000  // First priority
 #define ADC_SSPRI_SS2_2ND       0x00000100  // Second priority
 #define ADC_SSPRI_SS2_3RD       0x00000200  // Third priority
 #define ADC_SSPRI_SS2_4TH       0x00000300  // Fourth priority
-#define ADC_SSPRI_SS1_M         0x00000030  // SS1 Priority.
+#define ADC_SSPRI_SS1_M         0x00000030  // SS1 Priority
 #define ADC_SSPRI_SS1_1ST       0x00000000  // First priority
 #define ADC_SSPRI_SS1_2ND       0x00000010  // Second priority
 #define ADC_SSPRI_SS1_3RD       0x00000020  // Third priority
 #define ADC_SSPRI_SS1_4TH       0x00000030  // Fourth priority
-#define ADC_SSPRI_SS0_M         0x00000003  // SS0 Priority.
+#define ADC_SSPRI_SS0_M         0x00000003  // SS0 Priority
 #define ADC_SSPRI_SS0_1ST       0x00000000  // First priority
 #define ADC_SSPRI_SS0_2ND       0x00000001  // Second priority
 #define ADC_SSPRI_SS0_3RD       0x00000002  // Third priority
 #define ADC_SSPRI_SS0_4TH       0x00000003  // Fourth priority
 
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SPC register.
+//
+//*****************************************************************************
+#define ADC_SPC_PHASE_M         0x0000000F  // Phase Difference
+#define ADC_SPC_PHASE_0         0x00000000  // ADC sample lags by 0.0
+#define ADC_SPC_PHASE_22_5      0x00000001  // ADC sample lags by 22.5
+#define ADC_SPC_PHASE_45        0x00000002  // ADC sample lags by 45.0
+#define ADC_SPC_PHASE_67_5      0x00000003  // ADC sample lags by 67.5
+#define ADC_SPC_PHASE_90        0x00000004  // ADC sample lags by 90.0
+#define ADC_SPC_PHASE_112_5     0x00000005  // ADC sample lags by 112.5
+#define ADC_SPC_PHASE_135       0x00000006  // ADC sample lags by 135.0
+#define ADC_SPC_PHASE_157_5     0x00000007  // ADC sample lags by 157.5
+#define ADC_SPC_PHASE_180       0x00000008  // ADC sample lags by 180.0
+#define ADC_SPC_PHASE_202_5     0x00000009  // ADC sample lags by 202.5
+#define ADC_SPC_PHASE_225       0x0000000A  // ADC sample lags by 225.0
+#define ADC_SPC_PHASE_247_5     0x0000000B  // ADC sample lags by 247.5
+#define ADC_SPC_PHASE_270       0x0000000C  // ADC sample lags by 270.0
+#define ADC_SPC_PHASE_292_5     0x0000000D  // ADC sample lags by 292.5
+#define ADC_SPC_PHASE_315       0x0000000E  // ADC sample lags by 315.0
+#define ADC_SPC_PHASE_337_5     0x0000000F  // ADC sample lags by 337.5
+
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the ADC_O_PSSI register.
 //
 //*****************************************************************************
-#define ADC_PSSI_GSYNC          0x80000000  // Global Synchronize.
-#define ADC_PSSI_SYNCWAIT       0x08000000  // Synchronize Wait.
-#define ADC_PSSI_SS3            0x00000008  // SS3 Initiate.
-#define ADC_PSSI_SS2            0x00000004  // SS2 Initiate.
-#define ADC_PSSI_SS1            0x00000002  // SS1 Initiate.
-#define ADC_PSSI_SS0            0x00000001  // SS0 Initiate.
+#define ADC_PSSI_GSYNC          0x80000000  // Global Synchronize
+#define ADC_PSSI_SYNCWAIT       0x08000000  // Synchronize Wait
+#define ADC_PSSI_SS3            0x00000008  // SS3 Initiate
+#define ADC_PSSI_SS2            0x00000004  // SS2 Initiate
+#define ADC_PSSI_SS1            0x00000002  // SS1 Initiate
+#define ADC_PSSI_SS0            0x00000001  // SS0 Initiate
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the ADC_O_SAC register.
 //
 //*****************************************************************************
-#define ADC_SAC_AVG_M           0x00000007  // Hardware Averaging Control.
+#define ADC_SAC_AVG_M           0x00000007  // Hardware Averaging Control
 #define ADC_SAC_AVG_OFF         0x00000000  // No hardware oversampling
 #define ADC_SAC_AVG_2X          0x00000001  // 2x hardware oversampling
 #define ADC_SAC_AVG_4X          0x00000002  // 4x hardware oversampling
@@ -3473,42 +3952,42 @@
 //
 //*****************************************************************************
 #define ADC_DCISC_DCINT7        0x00000080  // Digital Comparator 7 Interrupt
-                                            // Status and Clear.
+                                            // Status and Clear
 #define ADC_DCISC_DCINT6        0x00000040  // Digital Comparator 6 Interrupt
-                                            // Status and Clear.
+                                            // Status and Clear
 #define ADC_DCISC_DCINT5        0x00000020  // Digital Comparator 5 Interrupt
-                                            // Status and Clear.
+                                            // Status and Clear
 #define ADC_DCISC_DCINT4        0x00000010  // Digital Comparator 4 Interrupt
-                                            // Status and Clear.
+                                            // Status and Clear
 #define ADC_DCISC_DCINT3        0x00000008  // Digital Comparator 3 Interrupt
-                                            // Status and Clear.
+                                            // Status and Clear
 #define ADC_DCISC_DCINT2        0x00000004  // Digital Comparator 2 Interrupt
-                                            // Status and Clear.
+                                            // Status and Clear
 #define ADC_DCISC_DCINT1        0x00000002  // Digital Comparator 1 Interrupt
-                                            // Status and Clear.
+                                            // Status and Clear
 #define ADC_DCISC_DCINT0        0x00000001  // Digital Comparator 0 Interrupt
-                                            // Status and Clear.
+                                            // Status and Clear
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the ADC_O_CTL register.
 //
 //*****************************************************************************
-#define ADC_CTL_VREF            0x00000001  // Voltage Reference Select.
+#define ADC_CTL_VREF            0x00000001  // Voltage Reference Select
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the ADC_O_SSMUX0 register.
 //
 //*****************************************************************************
-#define ADC_SSMUX0_MUX7_M       0xF0000000  // 8th Sample Input Select.
-#define ADC_SSMUX0_MUX6_M       0x0F000000  // 7th Sample Input Select.
-#define ADC_SSMUX0_MUX5_M       0x00F00000  // 6th Sample Input Select.
-#define ADC_SSMUX0_MUX4_M       0x000F0000  // 5th Sample Input Select.
-#define ADC_SSMUX0_MUX3_M       0x0000F000  // 4th Sample Input Select.
-#define ADC_SSMUX0_MUX2_M       0x00000F00  // 3rd Sample Input Select.
-#define ADC_SSMUX0_MUX1_M       0x000000F0  // 2nd Sample Input Select.
-#define ADC_SSMUX0_MUX0_M       0x0000000F  // 1st Sample Input Select.
+#define ADC_SSMUX0_MUX7_M       0xF0000000  // 8th Sample Input Select
+#define ADC_SSMUX0_MUX6_M       0x0F000000  // 7th Sample Input Select
+#define ADC_SSMUX0_MUX5_M       0x00F00000  // 6th Sample Input Select
+#define ADC_SSMUX0_MUX4_M       0x000F0000  // 5th Sample Input Select
+#define ADC_SSMUX0_MUX3_M       0x0000F000  // 4th Sample Input Select
+#define ADC_SSMUX0_MUX2_M       0x00000F00  // 3rd Sample Input Select
+#define ADC_SSMUX0_MUX1_M       0x000000F0  // 2nd Sample Input Select
+#define ADC_SSMUX0_MUX0_M       0x0000000F  // 1st Sample Input Select
 #define ADC_SSMUX0_MUX7_S       28
 #define ADC_SSMUX0_MUX6_S       24
 #define ADC_SSMUX0_MUX5_S       20
@@ -3523,45 +4002,45 @@
 // The following are defines for the bit fields in the ADC_O_SSCTL0 register.
 //
 //*****************************************************************************
-#define ADC_SSCTL0_TS7          0x80000000  // 8th Sample Temp Sensor Select.
-#define ADC_SSCTL0_IE7          0x40000000  // 8th Sample Interrupt Enable.
-#define ADC_SSCTL0_END7         0x20000000  // 8th Sample is End of Sequence.
-#define ADC_SSCTL0_D7           0x10000000  // 8th Sample Diff Input Select.
-#define ADC_SSCTL0_TS6          0x08000000  // 7th Sample Temp Sensor Select.
-#define ADC_SSCTL0_IE6          0x04000000  // 7th Sample Interrupt Enable.
-#define ADC_SSCTL0_END6         0x02000000  // 7th Sample is End of Sequence.
-#define ADC_SSCTL0_D6           0x01000000  // 7th Sample Diff Input Select.
-#define ADC_SSCTL0_TS5          0x00800000  // 6th Sample Temp Sensor Select.
-#define ADC_SSCTL0_IE5          0x00400000  // 6th Sample Interrupt Enable.
-#define ADC_SSCTL0_END5         0x00200000  // 6th Sample is End of Sequence.
-#define ADC_SSCTL0_D5           0x00100000  // 6th Sample Diff Input Select.
-#define ADC_SSCTL0_TS4          0x00080000  // 5th Sample Temp Sensor Select.
-#define ADC_SSCTL0_IE4          0x00040000  // 5th Sample Interrupt Enable.
-#define ADC_SSCTL0_END4         0x00020000  // 5th Sample is End of Sequence.
-#define ADC_SSCTL0_D4           0x00010000  // 5th Sample Diff Input Select.
-#define ADC_SSCTL0_TS3          0x00008000  // 4th Sample Temp Sensor Select.
-#define ADC_SSCTL0_IE3          0x00004000  // 4th Sample Interrupt Enable.
-#define ADC_SSCTL0_END3         0x00002000  // 4th Sample is End of Sequence.
-#define ADC_SSCTL0_D3           0x00001000  // 4th Sample Diff Input Select.
-#define ADC_SSCTL0_TS2          0x00000800  // 3rd Sample Temp Sensor Select.
-#define ADC_SSCTL0_IE2          0x00000400  // 3rd Sample Interrupt Enable.
-#define ADC_SSCTL0_END2         0x00000200  // 3rd Sample is End of Sequence.
-#define ADC_SSCTL0_D2           0x00000100  // 3rd Sample Diff Input Select.
-#define ADC_SSCTL0_TS1          0x00000080  // 2nd Sample Temp Sensor Select.
-#define ADC_SSCTL0_IE1          0x00000040  // 2nd Sample Interrupt Enable.
-#define ADC_SSCTL0_END1         0x00000020  // 2nd Sample is End of Sequence.
-#define ADC_SSCTL0_D1           0x00000010  // 2nd Sample Diff Input Select.
-#define ADC_SSCTL0_TS0          0x00000008  // 1st Sample Temp Sensor Select.
-#define ADC_SSCTL0_IE0          0x00000004  // 1st Sample Interrupt Enable.
-#define ADC_SSCTL0_END0         0x00000002  // 1st Sample is End of Sequence.
-#define ADC_SSCTL0_D0           0x00000001  // 1st Sample Diff Input Select.
+#define ADC_SSCTL0_TS7          0x80000000  // 8th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE7          0x40000000  // 8th Sample Interrupt Enable
+#define ADC_SSCTL0_END7         0x20000000  // 8th Sample is End of Sequence
+#define ADC_SSCTL0_D7           0x10000000  // 8th Sample Diff Input Select
+#define ADC_SSCTL0_TS6          0x08000000  // 7th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE6          0x04000000  // 7th Sample Interrupt Enable
+#define ADC_SSCTL0_END6         0x02000000  // 7th Sample is End of Sequence
+#define ADC_SSCTL0_D6           0x01000000  // 7th Sample Diff Input Select
+#define ADC_SSCTL0_TS5          0x00800000  // 6th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE5          0x00400000  // 6th Sample Interrupt Enable
+#define ADC_SSCTL0_END5         0x00200000  // 6th Sample is End of Sequence
+#define ADC_SSCTL0_D5           0x00100000  // 6th Sample Diff Input Select
+#define ADC_SSCTL0_TS4          0x00080000  // 5th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE4          0x00040000  // 5th Sample Interrupt Enable
+#define ADC_SSCTL0_END4         0x00020000  // 5th Sample is End of Sequence
+#define ADC_SSCTL0_D4           0x00010000  // 5th Sample Diff Input Select
+#define ADC_SSCTL0_TS3          0x00008000  // 4th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE3          0x00004000  // 4th Sample Interrupt Enable
+#define ADC_SSCTL0_END3         0x00002000  // 4th Sample is End of Sequence
+#define ADC_SSCTL0_D3           0x00001000  // 4th Sample Diff Input Select
+#define ADC_SSCTL0_TS2          0x00000800  // 3rd Sample Temp Sensor Select
+#define ADC_SSCTL0_IE2          0x00000400  // 3rd Sample Interrupt Enable
+#define ADC_SSCTL0_END2         0x00000200  // 3rd Sample is End of Sequence
+#define ADC_SSCTL0_D2           0x00000100  // 3rd Sample Diff Input Select
+#define ADC_SSCTL0_TS1          0x00000080  // 2nd Sample Temp Sensor Select
+#define ADC_SSCTL0_IE1          0x00000040  // 2nd Sample Interrupt Enable
+#define ADC_SSCTL0_END1         0x00000020  // 2nd Sample is End of Sequence
+#define ADC_SSCTL0_D1           0x00000010  // 2nd Sample Diff Input Select
+#define ADC_SSCTL0_TS0          0x00000008  // 1st Sample Temp Sensor Select
+#define ADC_SSCTL0_IE0          0x00000004  // 1st Sample Interrupt Enable
+#define ADC_SSCTL0_END0         0x00000002  // 1st Sample is End of Sequence
+#define ADC_SSCTL0_D0           0x00000001  // 1st Sample Diff Input Select
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the ADC_O_SSFIFO0 register.
 //
 //*****************************************************************************
-#define ADC_SSFIFO0_DATA_M      0x000003FF  // Conversion Result Data.
+#define ADC_SSFIFO0_DATA_M      0x000003FF  // Conversion Result Data
 #define ADC_SSFIFO0_DATA_S      0
 
 //*****************************************************************************
@@ -3569,10 +4048,10 @@
 // The following are defines for the bit fields in the ADC_O_SSFSTAT0 register.
 //
 //*****************************************************************************
-#define ADC_SSFSTAT0_FULL       0x00001000  // FIFO Full.
-#define ADC_SSFSTAT0_EMPTY      0x00000100  // FIFO Empty.
-#define ADC_SSFSTAT0_HPTR_M     0x000000F0  // FIFO Head Pointer.
-#define ADC_SSFSTAT0_TPTR_M     0x0000000F  // FIFO Tail Pointer.
+#define ADC_SSFSTAT0_FULL       0x00001000  // FIFO Full
+#define ADC_SSFSTAT0_EMPTY      0x00000100  // FIFO Empty
+#define ADC_SSFSTAT0_HPTR_M     0x000000F0  // FIFO Head Pointer
+#define ADC_SSFSTAT0_TPTR_M     0x0000000F  // FIFO Tail Pointer
 #define ADC_SSFSTAT0_HPTR_S     4
 #define ADC_SSFSTAT0_TPTR_S     0
 
@@ -3582,21 +4061,21 @@
 //
 //*****************************************************************************
 #define ADC_SSOP0_S7DCOP        0x10000000  // Sample 7 Digital Comparator
-                                            // Operation.
+                                            // Operation
 #define ADC_SSOP0_S6DCOP        0x01000000  // Sample 6 Digital Comparator
-                                            // Operation.
+                                            // Operation
 #define ADC_SSOP0_S5DCOP        0x00100000  // Sample 5 Digital Comparator
-                                            // Operation.
+                                            // Operation
 #define ADC_SSOP0_S4DCOP        0x00010000  // Sample 4 Digital Comparator
-                                            // Operation.
+                                            // Operation
 #define ADC_SSOP0_S3DCOP        0x00001000  // Sample 3 Digital Comparator
-                                            // Operation.
+                                            // Operation
 #define ADC_SSOP0_S2DCOP        0x00000100  // Sample 2 Digital Comparator
-                                            // Operation.
+                                            // Operation
 #define ADC_SSOP0_S1DCOP        0x00000010  // Sample 1 Digital Comparator
-                                            // Operation.
+                                            // Operation
 #define ADC_SSOP0_S0DCOP        0x00000001  // Sample 0 Digital Comparator
-                                            // Operation.
+                                            // Operation
 
 //*****************************************************************************
 //
@@ -3604,37 +4083,21 @@
 //
 //*****************************************************************************
 #define ADC_SSDC0_S7DCSEL_M     0xF0000000  // Sample 7 Digital Comparator
-                                            // Select.
-#define ADC_SSDC0_S7DCSEL_0     0x00000000  // Digital Comparator Unit 0
-                                            // (ADCDCCMP0 and ADCCCTL0)
-#define ADC_SSDC0_S7DCSEL_1     0x10000000  // Digital Comparator Unit 1
-                                            // (ADCDCCMP1 and ADCCCTL1)
-#define ADC_SSDC0_S7DCSEL_2     0x20000000  // Digital Comparator Unit 2
-                                            // (ADCDCCMP2 and ADCCCTL2)
-#define ADC_SSDC0_S7DCSEL_3     0x30000000  // Digital Comparator Unit 3
-                                            // (ADCDCCMP3 and ADCCCTL3)
-#define ADC_SSDC0_S7DCSEL_4     0x40000000  // Digital Comparator Unit 4
-                                            // (ADCDCCMP4 and ADCCCTL4)
-#define ADC_SSDC0_S7DCSEL_5     0x50000000  // Digital Comparator Unit 5
-                                            // (ADCDCCMP5 and ADCCCTL5)
-#define ADC_SSDC0_S7DCSEL_6     0x60000000  // Digital Comparator Unit 6
-                                            // (ADCDCCMP6 and ADCCCTL6)
-#define ADC_SSDC0_S7DCSEL_7     0x70000000  // Digital Comparator Unit 7
-                                            // (ADCDCCMP7 and ADCCCTL7)
+                                            // Select
 #define ADC_SSDC0_S6DCSEL_M     0x0F000000  // Sample 6 Digital Comparator
-                                            // Select.
+                                            // Select
 #define ADC_SSDC0_S5DCSEL_M     0x00F00000  // Sample 5 Digital Comparator
-                                            // Select.
+                                            // Select
 #define ADC_SSDC0_S4DCSEL_M     0x000F0000  // Sample 4 Digital Comparator
-                                            // Select.
+                                            // Select
 #define ADC_SSDC0_S3DCSEL_M     0x0000F000  // Sample 3 Digital Comparator
-                                            // Select.
+                                            // Select
 #define ADC_SSDC0_S2DCSEL_M     0x00000F00  // Sample 2 Digital Comparator
-                                            // Select.
+                                            // Select
 #define ADC_SSDC0_S1DCSEL_M     0x000000F0  // Sample 1 Digital Comparator
-                                            // Select.
+                                            // Select
 #define ADC_SSDC0_S0DCSEL_M     0x0000000F  // Sample 0 Digital Comparator
-                                            // Select.
+                                            // Select
 #define ADC_SSDC0_S6DCSEL_S     24
 #define ADC_SSDC0_S5DCSEL_S     20
 #define ADC_SSDC0_S4DCSEL_S     16
@@ -3648,10 +4111,10 @@
 // The following are defines for the bit fields in the ADC_O_SSMUX1 register.
 //
 //*****************************************************************************
-#define ADC_SSMUX1_MUX3_M       0x0000F000  // 4th Sample Input Select.
-#define ADC_SSMUX1_MUX2_M       0x00000F00  // 3rd Sample Input Select.
-#define ADC_SSMUX1_MUX1_M       0x000000F0  // 2nd Sample Input Select.
-#define ADC_SSMUX1_MUX0_M       0x0000000F  // 1st Sample Input Select.
+#define ADC_SSMUX1_MUX3_M       0x0000F000  // 4th Sample Input Select
+#define ADC_SSMUX1_MUX2_M       0x00000F00  // 3rd Sample Input Select
+#define ADC_SSMUX1_MUX1_M       0x000000F0  // 2nd Sample Input Select
+#define ADC_SSMUX1_MUX0_M       0x0000000F  // 1st Sample Input Select
 #define ADC_SSMUX1_MUX3_S       12
 #define ADC_SSMUX1_MUX2_S       8
 #define ADC_SSMUX1_MUX1_S       4
@@ -3662,29 +4125,29 @@
 // The following are defines for the bit fields in the ADC_O_SSCTL1 register.
 //
 //*****************************************************************************
-#define ADC_SSCTL1_TS3          0x00008000  // 4th Sample Temp Sensor Select.
-#define ADC_SSCTL1_IE3          0x00004000  // 4th Sample Interrupt Enable.
-#define ADC_SSCTL1_END3         0x00002000  // 4th Sample is End of Sequence.
-#define ADC_SSCTL1_D3           0x00001000  // 4th Sample Diff Input Select.
-#define ADC_SSCTL1_TS2          0x00000800  // 3rd Sample Temp Sensor Select.
-#define ADC_SSCTL1_IE2          0x00000400  // 3rd Sample Interrupt Enable.
-#define ADC_SSCTL1_END2         0x00000200  // 3rd Sample is End of Sequence.
-#define ADC_SSCTL1_D2           0x00000100  // 3rd Sample Diff Input Select.
-#define ADC_SSCTL1_TS1          0x00000080  // 2nd Sample Temp Sensor Select.
-#define ADC_SSCTL1_IE1          0x00000040  // 2nd Sample Interrupt Enable.
-#define ADC_SSCTL1_END1         0x00000020  // 2nd Sample is End of Sequence.
-#define ADC_SSCTL1_D1           0x00000010  // 2nd Sample Diff Input Select.
-#define ADC_SSCTL1_TS0          0x00000008  // 1st Sample Temp Sensor Select.
-#define ADC_SSCTL1_IE0          0x00000004  // 1st Sample Interrupt Enable.
-#define ADC_SSCTL1_END0         0x00000002  // 1st Sample is End of Sequence.
-#define ADC_SSCTL1_D0           0x00000001  // 1st Sample Diff Input Select.
+#define ADC_SSCTL1_TS3          0x00008000  // 4th Sample Temp Sensor Select
+#define ADC_SSCTL1_IE3          0x00004000  // 4th Sample Interrupt Enable
+#define ADC_SSCTL1_END3         0x00002000  // 4th Sample is End of Sequence
+#define ADC_SSCTL1_D3           0x00001000  // 4th Sample Diff Input Select
+#define ADC_SSCTL1_TS2          0x00000800  // 3rd Sample Temp Sensor Select
+#define ADC_SSCTL1_IE2          0x00000400  // 3rd Sample Interrupt Enable
+#define ADC_SSCTL1_END2         0x00000200  // 3rd Sample is End of Sequence
+#define ADC_SSCTL1_D2           0x00000100  // 3rd Sample Diff Input Select
+#define ADC_SSCTL1_TS1          0x00000080  // 2nd Sample Temp Sensor Select
+#define ADC_SSCTL1_IE1          0x00000040  // 2nd Sample Interrupt Enable
+#define ADC_SSCTL1_END1         0x00000020  // 2nd Sample is End of Sequence
+#define ADC_SSCTL1_D1           0x00000010  // 2nd Sample Diff Input Select
+#define ADC_SSCTL1_TS0          0x00000008  // 1st Sample Temp Sensor Select
+#define ADC_SSCTL1_IE0          0x00000004  // 1st Sample Interrupt Enable
+#define ADC_SSCTL1_END0         0x00000002  // 1st Sample is End of Sequence
+#define ADC_SSCTL1_D0           0x00000001  // 1st Sample Diff Input Select
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the ADC_O_SSFIFO1 register.
 //
 //*****************************************************************************
-#define ADC_SSFIFO1_DATA_M      0x000003FF  // Conversion Result Data.
+#define ADC_SSFIFO1_DATA_M      0x000003FF  // Conversion Result Data
 #define ADC_SSFIFO1_DATA_S      0
 
 //*****************************************************************************
@@ -3692,10 +4155,10 @@
 // The following are defines for the bit fields in the ADC_O_SSFSTAT1 register.
 //
 //*****************************************************************************
-#define ADC_SSFSTAT1_FULL       0x00001000  // FIFO Full.
-#define ADC_SSFSTAT1_EMPTY      0x00000100  // FIFO Empty.
-#define ADC_SSFSTAT1_HPTR_M     0x000000F0  // FIFO Head Pointer.
-#define ADC_SSFSTAT1_TPTR_M     0x0000000F  // FIFO Tail Pointer.
+#define ADC_SSFSTAT1_FULL       0x00001000  // FIFO Full
+#define ADC_SSFSTAT1_EMPTY      0x00000100  // FIFO Empty
+#define ADC_SSFSTAT1_HPTR_M     0x000000F0  // FIFO Head Pointer
+#define ADC_SSFSTAT1_TPTR_M     0x0000000F  // FIFO Tail Pointer
 #define ADC_SSFSTAT1_HPTR_S     4
 #define ADC_SSFSTAT1_TPTR_S     0
 
@@ -3705,13 +4168,13 @@
 //
 //*****************************************************************************
 #define ADC_SSOP1_S3DCOP        0x00001000  // Sample 3 Digital Comparator
-                                            // Operation.
+                                            // Operation
 #define ADC_SSOP1_S2DCOP        0x00000100  // Sample 2 Digital Comparator
-                                            // Operation.
+                                            // Operation
 #define ADC_SSOP1_S1DCOP        0x00000010  // Sample 1 Digital Comparator
-                                            // Operation.
+                                            // Operation
 #define ADC_SSOP1_S0DCOP        0x00000001  // Sample 0 Digital Comparator
-                                            // Operation.
+                                            // Operation
 
 //*****************************************************************************
 //
@@ -3719,29 +4182,13 @@
 //
 //*****************************************************************************
 #define ADC_SSDC1_S3DCSEL_M     0x0000F000  // Sample 3 Digital Comparator
-                                            // Select.
-#define ADC_SSDC1_S3DCSEL_0     0x00000000  // Digital Comparator Unit 0
-                                            // (ADCDCCMP0 and ADCCCTL0)
-#define ADC_SSDC1_S3DCSEL_1     0x00001000  // Digital Comparator Unit 1
-                                            // (ADCDCCMP1 and ADCCCTL1)
-#define ADC_SSDC1_S3DCSEL_2     0x00002000  // Digital Comparator Unit 2
-                                            // (ADCDCCMP2 and ADCCCTL2)
-#define ADC_SSDC1_S3DCSEL_3     0x00003000  // Digital Comparator Unit 3
-                                            // (ADCDCCMP3 and ADCCCTL3)
-#define ADC_SSDC1_S3DCSEL_4     0x00004000  // Digital Comparator Unit 4
-                                            // (ADCDCCMP4 and ADCCCTL4)
-#define ADC_SSDC1_S3DCSEL_5     0x00005000  // Digital Comparator Unit 5
-                                            // (ADCDCCMP5 and ADCCCTL5)
-#define ADC_SSDC1_S3DCSEL_6     0x00006000  // Digital Comparator Unit 6
-                                            // (ADCDCCMP6 and ADCCCTL6)
-#define ADC_SSDC1_S3DCSEL_7     0x00007000  // Digital Comparator Unit 7
-                                            // (ADCDCCMP7 and ADCCCTL7)
+                                            // Select
 #define ADC_SSDC1_S2DCSEL_M     0x00000F00  // Sample 2 Digital Comparator
-                                            // Select.
+                                            // Select
 #define ADC_SSDC1_S1DCSEL_M     0x000000F0  // Sample 1 Digital Comparator
-                                            // Select.
+                                            // Select
 #define ADC_SSDC1_S0DCSEL_M     0x0000000F  // Sample 0 Digital Comparator
-                                            // Select.
+                                            // Select
 #define ADC_SSDC1_S2DCSEL_S     8
 #define ADC_SSDC1_S1DCSEL_S     4
 #define ADC_SSDC1_S0DCSEL_S     0
@@ -3751,10 +4198,10 @@
 // The following are defines for the bit fields in the ADC_O_SSMUX2 register.
 //
 //*****************************************************************************
-#define ADC_SSMUX2_MUX3_M       0x0000F000  // 4th Sample Input Select.
-#define ADC_SSMUX2_MUX2_M       0x00000F00  // 3rd Sample Input Select.
-#define ADC_SSMUX2_MUX1_M       0x000000F0  // 2nd Sample Input Select.
-#define ADC_SSMUX2_MUX0_M       0x0000000F  // 1st Sample Input Select.
+#define ADC_SSMUX2_MUX3_M       0x0000F000  // 4th Sample Input Select
+#define ADC_SSMUX2_MUX2_M       0x00000F00  // 3rd Sample Input Select
+#define ADC_SSMUX2_MUX1_M       0x000000F0  // 2nd Sample Input Select
+#define ADC_SSMUX2_MUX0_M       0x0000000F  // 1st Sample Input Select
 #define ADC_SSMUX2_MUX3_S       12
 #define ADC_SSMUX2_MUX2_S       8
 #define ADC_SSMUX2_MUX1_S       4
@@ -3765,29 +4212,29 @@
 // The following are defines for the bit fields in the ADC_O_SSCTL2 register.
 //
 //*****************************************************************************
-#define ADC_SSCTL2_TS3          0x00008000  // 4th Sample Temp Sensor Select.
-#define ADC_SSCTL2_IE3          0x00004000  // 4th Sample Interrupt Enable.
-#define ADC_SSCTL2_END3         0x00002000  // 4th Sample is End of Sequence.
-#define ADC_SSCTL2_D3           0x00001000  // 4th Sample Diff Input Select.
-#define ADC_SSCTL2_TS2          0x00000800  // 3rd Sample Temp Sensor Select.
-#define ADC_SSCTL2_IE2          0x00000400  // 3rd Sample Interrupt Enable.
-#define ADC_SSCTL2_END2         0x00000200  // 3rd Sample is End of Sequence.
-#define ADC_SSCTL2_D2           0x00000100  // 3rd Sample Diff Input Select.
-#define ADC_SSCTL2_TS1          0x00000080  // 2nd Sample Temp Sensor Select.
-#define ADC_SSCTL2_IE1          0x00000040  // 2nd Sample Interrupt Enable.
-#define ADC_SSCTL2_END1         0x00000020  // 2nd Sample is End of Sequence.
-#define ADC_SSCTL2_D1           0x00000010  // 2nd Sample Diff Input Select.
-#define ADC_SSCTL2_TS0          0x00000008  // 1st Sample Temp Sensor Select.
-#define ADC_SSCTL2_IE0          0x00000004  // 1st Sample Interrupt Enable.
-#define ADC_SSCTL2_END0         0x00000002  // 1st Sample is End of Sequence.
-#define ADC_SSCTL2_D0           0x00000001  // 1st Sample Diff Input Select.
+#define ADC_SSCTL2_TS3          0x00008000  // 4th Sample Temp Sensor Select
+#define ADC_SSCTL2_IE3          0x00004000  // 4th Sample Interrupt Enable
+#define ADC_SSCTL2_END3         0x00002000  // 4th Sample is End of Sequence
+#define ADC_SSCTL2_D3           0x00001000  // 4th Sample Diff Input Select
+#define ADC_SSCTL2_TS2          0x00000800  // 3rd Sample Temp Sensor Select
+#define ADC_SSCTL2_IE2          0x00000400  // 3rd Sample Interrupt Enable
+#define ADC_SSCTL2_END2         0x00000200  // 3rd Sample is End of Sequence
+#define ADC_SSCTL2_D2           0x00000100  // 3rd Sample Diff Input Select
+#define ADC_SSCTL2_TS1          0x00000080  // 2nd Sample Temp Sensor Select
+#define ADC_SSCTL2_IE1          0x00000040  // 2nd Sample Interrupt Enable
+#define ADC_SSCTL2_END1         0x00000020  // 2nd Sample is End of Sequence
+#define ADC_SSCTL2_D1           0x00000010  // 2nd Sample Diff Input Select
+#define ADC_SSCTL2_TS0          0x00000008  // 1st Sample Temp Sensor Select
+#define ADC_SSCTL2_IE0          0x00000004  // 1st Sample Interrupt Enable
+#define ADC_SSCTL2_END0         0x00000002  // 1st Sample is End of Sequence
+#define ADC_SSCTL2_D0           0x00000001  // 1st Sample Diff Input Select
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the ADC_O_SSFIFO2 register.
 //
 //*****************************************************************************
-#define ADC_SSFIFO2_DATA_M      0x000003FF  // Conversion Result Data.
+#define ADC_SSFIFO2_DATA_M      0x000003FF  // Conversion Result Data
 #define ADC_SSFIFO2_DATA_S      0
 
 //*****************************************************************************
@@ -3795,10 +4242,10 @@
 // The following are defines for the bit fields in the ADC_O_SSFSTAT2 register.
 //
 //*****************************************************************************
-#define ADC_SSFSTAT2_FULL       0x00001000  // FIFO Full.
-#define ADC_SSFSTAT2_EMPTY      0x00000100  // FIFO Empty.
-#define ADC_SSFSTAT2_HPTR_M     0x000000F0  // FIFO Head Pointer.
-#define ADC_SSFSTAT2_TPTR_M     0x0000000F  // FIFO Tail Pointer.
+#define ADC_SSFSTAT2_FULL       0x00001000  // FIFO Full
+#define ADC_SSFSTAT2_EMPTY      0x00000100  // FIFO Empty
+#define ADC_SSFSTAT2_HPTR_M     0x000000F0  // FIFO Head Pointer
+#define ADC_SSFSTAT2_TPTR_M     0x0000000F  // FIFO Tail Pointer
 #define ADC_SSFSTAT2_HPTR_S     4
 #define ADC_SSFSTAT2_TPTR_S     0
 
@@ -3808,13 +4255,13 @@
 //
 //*****************************************************************************
 #define ADC_SSOP2_S3DCOP        0x00001000  // Sample 3 Digital Comparator
-                                            // Operation.
+                                            // Operation
 #define ADC_SSOP2_S2DCOP        0x00000100  // Sample 2 Digital Comparator
-                                            // Operation.
+                                            // Operation
 #define ADC_SSOP2_S1DCOP        0x00000010  // Sample 1 Digital Comparator
-                                            // Operation.
+                                            // Operation
 #define ADC_SSOP2_S0DCOP        0x00000001  // Sample 0 Digital Comparator
-                                            // Operation.
+                                            // Operation
 
 //*****************************************************************************
 //
@@ -3822,29 +4269,13 @@
 //
 //*****************************************************************************
 #define ADC_SSDC2_S3DCSEL_M     0x0000F000  // Sample 3 Digital Comparator
-                                            // Select.
-#define ADC_SSDC2_S3DCSEL_0     0x00000000  // Digital Comparator Unit 0
-                                            // (ADCDCCMP0 and ADCCCTL0)
-#define ADC_SSDC2_S3DCSEL_1     0x00001000  // Digital Comparator Unit 1
-                                            // (ADCDCCMP1 and ADCCCTL1)
-#define ADC_SSDC2_S3DCSEL_2     0x00002000  // Digital Comparator Unit 2
-                                            // (ADCDCCMP2 and ADCCCTL2)
-#define ADC_SSDC2_S3DCSEL_3     0x00003000  // Digital Comparator Unit 3
-                                            // (ADCDCCMP3 and ADCCCTL3)
-#define ADC_SSDC2_S3DCSEL_4     0x00004000  // Digital Comparator Unit 4
-                                            // (ADCDCCMP4 and ADCCCTL4)
-#define ADC_SSDC2_S3DCSEL_5     0x00005000  // Digital Comparator Unit 5
-                                            // (ADCDCCMP5 and ADCCCTL5)
-#define ADC_SSDC2_S3DCSEL_6     0x00006000  // Digital Comparator Unit 6
-                                            // (ADCDCCMP6 and ADCCCTL6)
-#define ADC_SSDC2_S3DCSEL_7     0x00007000  // Digital Comparator Unit 7
-                                            // (ADCDCCMP7 and ADCCCTL7)
+                                            // Select
 #define ADC_SSDC2_S2DCSEL_M     0x00000F00  // Sample 2 Digital Comparator
-                                            // Select.
+                                            // Select
 #define ADC_SSDC2_S1DCSEL_M     0x000000F0  // Sample 1 Digital Comparator
-                                            // Select.
+                                            // Select
 #define ADC_SSDC2_S0DCSEL_M     0x0000000F  // Sample 0 Digital Comparator
-                                            // Select.
+                                            // Select
 #define ADC_SSDC2_S2DCSEL_S     8
 #define ADC_SSDC2_S1DCSEL_S     4
 #define ADC_SSDC2_S0DCSEL_S     0
@@ -3854,7 +4285,7 @@
 // The following are defines for the bit fields in the ADC_O_SSMUX3 register.
 //
 //*****************************************************************************
-#define ADC_SSMUX3_MUX0_M       0x0000000F  // 1st Sample Input Select.
+#define ADC_SSMUX3_MUX0_M       0x0000000F  // 1st Sample Input Select
 #define ADC_SSMUX3_MUX0_S       0
 
 //*****************************************************************************
@@ -3862,17 +4293,17 @@
 // The following are defines for the bit fields in the ADC_O_SSCTL3 register.
 //
 //*****************************************************************************
-#define ADC_SSCTL3_TS0          0x00000008  // 1st Sample Temp Sensor Select.
-#define ADC_SSCTL3_IE0          0x00000004  // 1st Sample Interrupt Enable.
-#define ADC_SSCTL3_END0         0x00000002  // 1st Sample is End of Sequence.
-#define ADC_SSCTL3_D0           0x00000001  // 1st Sample Diff Input Select.
+#define ADC_SSCTL3_TS0          0x00000008  // 1st Sample Temp Sensor Select
+#define ADC_SSCTL3_IE0          0x00000004  // 1st Sample Interrupt Enable
+#define ADC_SSCTL3_END0         0x00000002  // 1st Sample is End of Sequence
+#define ADC_SSCTL3_D0           0x00000001  // 1st Sample Diff Input Select
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the ADC_O_SSFIFO3 register.
 //
 //*****************************************************************************
-#define ADC_SSFIFO3_DATA_M      0x000003FF  // Conversion Result Data.
+#define ADC_SSFIFO3_DATA_M      0x000003FF  // Conversion Result Data
 #define ADC_SSFIFO3_DATA_S      0
 
 //*****************************************************************************
@@ -3880,10 +4311,10 @@
 // The following are defines for the bit fields in the ADC_O_SSFSTAT3 register.
 //
 //*****************************************************************************
-#define ADC_SSFSTAT3_FULL       0x00001000  // FIFO Full.
-#define ADC_SSFSTAT3_EMPTY      0x00000100  // FIFO Empty.
-#define ADC_SSFSTAT3_HPTR_M     0x000000F0  // FIFO Head Pointer.
-#define ADC_SSFSTAT3_TPTR_M     0x0000000F  // FIFO Tail Pointer.
+#define ADC_SSFSTAT3_FULL       0x00001000  // FIFO Full
+#define ADC_SSFSTAT3_EMPTY      0x00000100  // FIFO Empty
+#define ADC_SSFSTAT3_HPTR_M     0x000000F0  // FIFO Head Pointer
+#define ADC_SSFSTAT3_TPTR_M     0x0000000F  // FIFO Tail Pointer
 #define ADC_SSFSTAT3_HPTR_S     4
 #define ADC_SSFSTAT3_TPTR_S     0
 
@@ -3893,7 +4324,7 @@
 //
 //*****************************************************************************
 #define ADC_SSOP3_S0DCOP        0x00000001  // Sample 0 Digital Comparator
-                                            // Operation.
+                                            // Operation
 
 //*****************************************************************************
 //
@@ -3901,67 +4332,51 @@
 //
 //*****************************************************************************
 #define ADC_SSDC3_S0DCSEL_M     0x0000000F  // Sample 0 Digital Comparator
-                                            // Select.
-#define ADC_SSDC3_S0DCSEL_0     0x00000000  // Digital Comparator Unit 0
-                                            // (ADCDCCMP0 and ADCCCTL0)
-#define ADC_SSDC3_S0DCSEL_1     0x00000001  // Digital Comparator Unit 1
-                                            // (ADCDCCMP1 and ADCCCTL1)
-#define ADC_SSDC3_S0DCSEL_2     0x00000002  // Digital Comparator Unit 2
-                                            // (ADCDCCMP2 and ADCCCTL2)
-#define ADC_SSDC3_S0DCSEL_3     0x00000003  // Digital Comparator Unit 3
-                                            // (ADCDCCMP3 and ADCCCTL3)
-#define ADC_SSDC3_S0DCSEL_4     0x00000004  // Digital Comparator Unit 4
-                                            // (ADCDCCMP4 and ADCCCTL4)
-#define ADC_SSDC3_S0DCSEL_5     0x00000005  // Digital Comparator Unit 5
-                                            // (ADCDCCMP5 and ADCCCTL5)
-#define ADC_SSDC3_S0DCSEL_6     0x00000006  // Digital Comparator Unit 6
-                                            // (ADCDCCMP6 and ADCCCTL6)
-#define ADC_SSDC3_S0DCSEL_7     0x00000007  // Digital Comparator Unit 7
-                                            // (ADCDCCMP7 and ADCCCTL7)
+                                            // Select
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the ADC_O_DCRIC register.
 //
 //*****************************************************************************
-#define ADC_DCRIC_DCTRIG7       0x00800000  // Digital Comparator Trigger 7.
-#define ADC_DCRIC_DCTRIG6       0x00400000  // Digital Comparator Trigger 6.
-#define ADC_DCRIC_DCTRIG5       0x00200000  // Digital Comparator Trigger 5.
-#define ADC_DCRIC_DCTRIG4       0x00100000  // Digital Comparator Trigger 4.
-#define ADC_DCRIC_DCTRIG3       0x00080000  // Digital Comparator Trigger 3.
-#define ADC_DCRIC_DCTRIG2       0x00040000  // Digital Comparator Trigger 2.
-#define ADC_DCRIC_DCTRIG1       0x00020000  // Digital Comparator Trigger 1.
-#define ADC_DCRIC_DCTRIG0       0x00010000  // Digital Comparator Trigger 0.
-#define ADC_DCRIC_DCINT7        0x00000080  // Digital Comparator Trigger 7.
-#define ADC_DCRIC_DCINT6        0x00000040  // Digital Comparator Trigger 6.
-#define ADC_DCRIC_DCINT5        0x00000020  // Digital Comparator Trigger 5.
-#define ADC_DCRIC_DCINT4        0x00000010  // Digital Comparator Trigger 4.
-#define ADC_DCRIC_DCINT3        0x00000008  // Digital Comparator Trigger 3.
-#define ADC_DCRIC_DCINT2        0x00000004  // Digital Comparator Trigger 2.
-#define ADC_DCRIC_DCINT1        0x00000002  // Digital Comparator Trigger 1.
-#define ADC_DCRIC_DCINT0        0x00000001  // Digital Comparator Trigger 0.
+#define ADC_DCRIC_DCTRIG7       0x00800000  // Digital Comparator Trigger 7
+#define ADC_DCRIC_DCTRIG6       0x00400000  // Digital Comparator Trigger 6
+#define ADC_DCRIC_DCTRIG5       0x00200000  // Digital Comparator Trigger 5
+#define ADC_DCRIC_DCTRIG4       0x00100000  // Digital Comparator Trigger 4
+#define ADC_DCRIC_DCTRIG3       0x00080000  // Digital Comparator Trigger 3
+#define ADC_DCRIC_DCTRIG2       0x00040000  // Digital Comparator Trigger 2
+#define ADC_DCRIC_DCTRIG1       0x00020000  // Digital Comparator Trigger 1
+#define ADC_DCRIC_DCTRIG0       0x00010000  // Digital Comparator Trigger 0
+#define ADC_DCRIC_DCINT7        0x00000080  // Digital Comparator Interrupt 7
+#define ADC_DCRIC_DCINT6        0x00000040  // Digital Comparator Interrupt 6
+#define ADC_DCRIC_DCINT5        0x00000020  // Digital Comparator Interrupt 5
+#define ADC_DCRIC_DCINT4        0x00000010  // Digital Comparator Interrupt 4
+#define ADC_DCRIC_DCINT3        0x00000008  // Digital Comparator Interrupt 3
+#define ADC_DCRIC_DCINT2        0x00000004  // Digital Comparator Interrupt 2
+#define ADC_DCRIC_DCINT1        0x00000002  // Digital Comparator Interrupt 1
+#define ADC_DCRIC_DCINT0        0x00000001  // Digital Comparator Interrupt 0
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the ADC_O_DCCTL0 register.
 //
 //*****************************************************************************
-#define ADC_DCCTL0_CTE          0x00001000  // Comparison Trigger Enable.
-#define ADC_DCCTL0_CTC_M        0x00000C00  // Comparison Trigger Condition.
+#define ADC_DCCTL0_CTE          0x00001000  // Comparison Trigger Enable
+#define ADC_DCCTL0_CTC_M        0x00000C00  // Comparison Trigger Condition
 #define ADC_DCCTL0_CTC_LOW      0x00000000  // Low Band
 #define ADC_DCCTL0_CTC_MID      0x00000400  // Mid Band
 #define ADC_DCCTL0_CTC_HIGH     0x00000C00  // High Band
-#define ADC_DCCTL0_CTM_M        0x00000300  // Comparison Trigger Mode.
+#define ADC_DCCTL0_CTM_M        0x00000300  // Comparison Trigger Mode
 #define ADC_DCCTL0_CTM_ALWAYS   0x00000000  // Always
 #define ADC_DCCTL0_CTM_ONCE     0x00000100  // Once
 #define ADC_DCCTL0_CTM_HALWAYS  0x00000200  // Hysteresis Always
 #define ADC_DCCTL0_CTM_HONCE    0x00000300  // Hysteresis Once
-#define ADC_DCCTL0_CIE          0x00000010  // Comparison Interrupt Enable.
-#define ADC_DCCTL0_CIC_M        0x0000000C  // Comparison Interrupt Condition.
+#define ADC_DCCTL0_CIE          0x00000010  // Comparison Interrupt Enable
+#define ADC_DCCTL0_CIC_M        0x0000000C  // Comparison Interrupt Condition
 #define ADC_DCCTL0_CIC_LOW      0x00000000  // Low Band
 #define ADC_DCCTL0_CIC_MID      0x00000004  // Mid Band
 #define ADC_DCCTL0_CIC_HIGH     0x0000000C  // High Band
-#define ADC_DCCTL0_CIM_M        0x00000003  // Comparison Interrupt Mode.
+#define ADC_DCCTL0_CIM_M        0x00000003  // Comparison Interrupt Mode
 #define ADC_DCCTL0_CIM_ALWAYS   0x00000000  // Always
 #define ADC_DCCTL0_CIM_ONCE     0x00000001  // Once
 #define ADC_DCCTL0_CIM_HALWAYS  0x00000002  // Hysteresis Always
@@ -3972,22 +4387,22 @@
 // The following are defines for the bit fields in the ADC_O_DCCTL1 register.
 //
 //*****************************************************************************
-#define ADC_DCCTL1_CTE          0x00001000  // Comparison Trigger Enable.
-#define ADC_DCCTL1_CTC_M        0x00000C00  // Comparison Trigger Condition.
+#define ADC_DCCTL1_CTE          0x00001000  // Comparison Trigger Enable
+#define ADC_DCCTL1_CTC_M        0x00000C00  // Comparison Trigger Condition
 #define ADC_DCCTL1_CTC_LOW      0x00000000  // Low Band
 #define ADC_DCCTL1_CTC_MID      0x00000400  // Mid Band
 #define ADC_DCCTL1_CTC_HIGH     0x00000C00  // High Band
-#define ADC_DCCTL1_CTM_M        0x00000300  // Comparison Trigger Mode.
+#define ADC_DCCTL1_CTM_M        0x00000300  // Comparison Trigger Mode
 #define ADC_DCCTL1_CTM_ALWAYS   0x00000000  // Always
 #define ADC_DCCTL1_CTM_ONCE     0x00000100  // Once
 #define ADC_DCCTL1_CTM_HALWAYS  0x00000200  // Hysteresis Always
 #define ADC_DCCTL1_CTM_HONCE    0x00000300  // Hysteresis Once
-#define ADC_DCCTL1_CIE          0x00000010  // Comparison Interrupt Enable.
-#define ADC_DCCTL1_CIC_M        0x0000000C  // Comparison Interrupt Condition.
+#define ADC_DCCTL1_CIE          0x00000010  // Comparison Interrupt Enable
+#define ADC_DCCTL1_CIC_M        0x0000000C  // Comparison Interrupt Condition
 #define ADC_DCCTL1_CIC_LOW      0x00000000  // Low Band
 #define ADC_DCCTL1_CIC_MID      0x00000004  // Mid Band
 #define ADC_DCCTL1_CIC_HIGH     0x0000000C  // High Band
-#define ADC_DCCTL1_CIM_M        0x00000003  // Comparison Interrupt Mode.
+#define ADC_DCCTL1_CIM_M        0x00000003  // Comparison Interrupt Mode
 #define ADC_DCCTL1_CIM_ALWAYS   0x00000000  // Always
 #define ADC_DCCTL1_CIM_ONCE     0x00000001  // Once
 #define ADC_DCCTL1_CIM_HALWAYS  0x00000002  // Hysteresis Always
@@ -3998,22 +4413,22 @@
 // The following are defines for the bit fields in the ADC_O_DCCTL2 register.
 //
 //*****************************************************************************
-#define ADC_DCCTL2_CTE          0x00001000  // Comparison Trigger Enable.
-#define ADC_DCCTL2_CTC_M        0x00000C00  // Comparison Trigger Condition.
+#define ADC_DCCTL2_CTE          0x00001000  // Comparison Trigger Enable
+#define ADC_DCCTL2_CTC_M        0x00000C00  // Comparison Trigger Condition
 #define ADC_DCCTL2_CTC_LOW      0x00000000  // Low Band
 #define ADC_DCCTL2_CTC_MID      0x00000400  // Mid Band
 #define ADC_DCCTL2_CTC_HIGH     0x00000C00  // High Band
-#define ADC_DCCTL2_CTM_M        0x00000300  // Comparison Trigger Mode.
+#define ADC_DCCTL2_CTM_M        0x00000300  // Comparison Trigger Mode
 #define ADC_DCCTL2_CTM_ALWAYS   0x00000000  // Always
 #define ADC_DCCTL2_CTM_ONCE     0x00000100  // Once
 #define ADC_DCCTL2_CTM_HALWAYS  0x00000200  // Hysteresis Always
 #define ADC_DCCTL2_CTM_HONCE    0x00000300  // Hysteresis Once
-#define ADC_DCCTL2_CIE          0x00000010  // Comparison Interrupt Enable.
-#define ADC_DCCTL2_CIC_M        0x0000000C  // Comparison Interrupt Condition.
+#define ADC_DCCTL2_CIE          0x00000010  // Comparison Interrupt Enable
+#define ADC_DCCTL2_CIC_M        0x0000000C  // Comparison Interrupt Condition
 #define ADC_DCCTL2_CIC_LOW      0x00000000  // Low Band
 #define ADC_DCCTL2_CIC_MID      0x00000004  // Mid Band
 #define ADC_DCCTL2_CIC_HIGH     0x0000000C  // High Band
-#define ADC_DCCTL2_CIM_M        0x00000003  // Comparison Interrupt Mode.
+#define ADC_DCCTL2_CIM_M        0x00000003  // Comparison Interrupt Mode
 #define ADC_DCCTL2_CIM_ALWAYS   0x00000000  // Always
 #define ADC_DCCTL2_CIM_ONCE     0x00000001  // Once
 #define ADC_DCCTL2_CIM_HALWAYS  0x00000002  // Hysteresis Always
@@ -4024,22 +4439,22 @@
 // The following are defines for the bit fields in the ADC_O_DCCTL3 register.
 //
 //*****************************************************************************
-#define ADC_DCCTL3_CTE          0x00001000  // Comparison Trigger Enable.
-#define ADC_DCCTL3_CTC_M        0x00000C00  // Comparison Trigger Condition.
+#define ADC_DCCTL3_CTE          0x00001000  // Comparison Trigger Enable
+#define ADC_DCCTL3_CTC_M        0x00000C00  // Comparison Trigger Condition
 #define ADC_DCCTL3_CTC_LOW      0x00000000  // Low Band
 #define ADC_DCCTL3_CTC_MID      0x00000400  // Mid Band
 #define ADC_DCCTL3_CTC_HIGH     0x00000C00  // High Band
-#define ADC_DCCTL3_CTM_M        0x00000300  // Comparison Trigger Mode.
+#define ADC_DCCTL3_CTM_M        0x00000300  // Comparison Trigger Mode
 #define ADC_DCCTL3_CTM_ALWAYS   0x00000000  // Always
 #define ADC_DCCTL3_CTM_ONCE     0x00000100  // Once
 #define ADC_DCCTL3_CTM_HALWAYS  0x00000200  // Hysteresis Always
 #define ADC_DCCTL3_CTM_HONCE    0x00000300  // Hysteresis Once
-#define ADC_DCCTL3_CIE          0x00000010  // Comparison Interrupt Enable.
-#define ADC_DCCTL3_CIC_M        0x0000000C  // Comparison Interrupt Condition.
+#define ADC_DCCTL3_CIE          0x00000010  // Comparison Interrupt Enable
+#define ADC_DCCTL3_CIC_M        0x0000000C  // Comparison Interrupt Condition
 #define ADC_DCCTL3_CIC_LOW      0x00000000  // Low Band
 #define ADC_DCCTL3_CIC_MID      0x00000004  // Mid Band
 #define ADC_DCCTL3_CIC_HIGH     0x0000000C  // High Band
-#define ADC_DCCTL3_CIM_M        0x00000003  // Comparison Interrupt Mode.
+#define ADC_DCCTL3_CIM_M        0x00000003  // Comparison Interrupt Mode
 #define ADC_DCCTL3_CIM_ALWAYS   0x00000000  // Always
 #define ADC_DCCTL3_CIM_ONCE     0x00000001  // Once
 #define ADC_DCCTL3_CIM_HALWAYS  0x00000002  // Hysteresis Always
@@ -4050,22 +4465,22 @@
 // The following are defines for the bit fields in the ADC_O_DCCTL4 register.
 //
 //*****************************************************************************
-#define ADC_DCCTL4_CTE          0x00001000  // Comparison Trigger Enable.
-#define ADC_DCCTL4_CTC_M        0x00000C00  // Comparison Trigger Condition.
+#define ADC_DCCTL4_CTE          0x00001000  // Comparison Trigger Enable
+#define ADC_DCCTL4_CTC_M        0x00000C00  // Comparison Trigger Condition
 #define ADC_DCCTL4_CTC_LOW      0x00000000  // Low Band
 #define ADC_DCCTL4_CTC_MID      0x00000400  // Mid Band
 #define ADC_DCCTL4_CTC_HIGH     0x00000C00  // High Band
-#define ADC_DCCTL4_CTM_M        0x00000300  // Comparison Trigger Mode.
+#define ADC_DCCTL4_CTM_M        0x00000300  // Comparison Trigger Mode
 #define ADC_DCCTL4_CTM_ALWAYS   0x00000000  // Always
 #define ADC_DCCTL4_CTM_ONCE     0x00000100  // Once
 #define ADC_DCCTL4_CTM_HALWAYS  0x00000200  // Hysteresis Always
 #define ADC_DCCTL4_CTM_HONCE    0x00000300  // Hysteresis Once
-#define ADC_DCCTL4_CIE          0x00000010  // Comparison Interrupt Enable.
-#define ADC_DCCTL4_CIC_M        0x0000000C  // Comparison Interrupt Condition.
+#define ADC_DCCTL4_CIE          0x00000010  // Comparison Interrupt Enable
+#define ADC_DCCTL4_CIC_M        0x0000000C  // Comparison Interrupt Condition
 #define ADC_DCCTL4_CIC_LOW      0x00000000  // Low Band
 #define ADC_DCCTL4_CIC_MID      0x00000004  // Mid Band
 #define ADC_DCCTL4_CIC_HIGH     0x0000000C  // High Band
-#define ADC_DCCTL4_CIM_M        0x00000003  // Comparison Interrupt Mode.
+#define ADC_DCCTL4_CIM_M        0x00000003  // Comparison Interrupt Mode
 #define ADC_DCCTL4_CIM_ALWAYS   0x00000000  // Always
 #define ADC_DCCTL4_CIM_ONCE     0x00000001  // Once
 #define ADC_DCCTL4_CIM_HALWAYS  0x00000002  // Hysteresis Always
@@ -4076,22 +4491,22 @@
 // The following are defines for the bit fields in the ADC_O_DCCTL5 register.
 //
 //*****************************************************************************
-#define ADC_DCCTL5_CTE          0x00001000  // Comparison Trigger Enable.
-#define ADC_DCCTL5_CTC_M        0x00000C00  // Comparison Trigger Condition.
+#define ADC_DCCTL5_CTE          0x00001000  // Comparison Trigger Enable
+#define ADC_DCCTL5_CTC_M        0x00000C00  // Comparison Trigger Condition
 #define ADC_DCCTL5_CTC_LOW      0x00000000  // Low Band
 #define ADC_DCCTL5_CTC_MID      0x00000400  // Mid Band
 #define ADC_DCCTL5_CTC_HIGH     0x00000C00  // High Band
-#define ADC_DCCTL5_CTM_M        0x00000300  // Comparison Trigger Mode.
+#define ADC_DCCTL5_CTM_M        0x00000300  // Comparison Trigger Mode
 #define ADC_DCCTL5_CTM_ALWAYS   0x00000000  // Always
 #define ADC_DCCTL5_CTM_ONCE     0x00000100  // Once
 #define ADC_DCCTL5_CTM_HALWAYS  0x00000200  // Hysteresis Always
 #define ADC_DCCTL5_CTM_HONCE    0x00000300  // Hysteresis Once
-#define ADC_DCCTL5_CIE          0x00000010  // Comparison Interrupt Enable.
-#define ADC_DCCTL5_CIC_M        0x0000000C  // Comparison Interrupt Condition.
+#define ADC_DCCTL5_CIE          0x00000010  // Comparison Interrupt Enable
+#define ADC_DCCTL5_CIC_M        0x0000000C  // Comparison Interrupt Condition
 #define ADC_DCCTL5_CIC_LOW      0x00000000  // Low Band
 #define ADC_DCCTL5_CIC_MID      0x00000004  // Mid Band
 #define ADC_DCCTL5_CIC_HIGH     0x0000000C  // High Band
-#define ADC_DCCTL5_CIM_M        0x00000003  // Comparison Interrupt Mode.
+#define ADC_DCCTL5_CIM_M        0x00000003  // Comparison Interrupt Mode
 #define ADC_DCCTL5_CIM_ALWAYS   0x00000000  // Always
 #define ADC_DCCTL5_CIM_ONCE     0x00000001  // Once
 #define ADC_DCCTL5_CIM_HALWAYS  0x00000002  // Hysteresis Always
@@ -4102,22 +4517,22 @@
 // The following are defines for the bit fields in the ADC_O_DCCTL6 register.
 //
 //*****************************************************************************
-#define ADC_DCCTL6_CTE          0x00001000  // Comparison Trigger Enable.
-#define ADC_DCCTL6_CTC_M        0x00000C00  // Comparison Trigger Condition.
+#define ADC_DCCTL6_CTE          0x00001000  // Comparison Trigger Enable
+#define ADC_DCCTL6_CTC_M        0x00000C00  // Comparison Trigger Condition
 #define ADC_DCCTL6_CTC_LOW      0x00000000  // Low Band
 #define ADC_DCCTL6_CTC_MID      0x00000400  // Mid Band
 #define ADC_DCCTL6_CTC_HIGH     0x00000C00  // High Band
-#define ADC_DCCTL6_CTM_M        0x00000300  // Comparison Trigger Mode.
+#define ADC_DCCTL6_CTM_M        0x00000300  // Comparison Trigger Mode
 #define ADC_DCCTL6_CTM_ALWAYS   0x00000000  // Always
 #define ADC_DCCTL6_CTM_ONCE     0x00000100  // Once
 #define ADC_DCCTL6_CTM_HALWAYS  0x00000200  // Hysteresis Always
 #define ADC_DCCTL6_CTM_HONCE    0x00000300  // Hysteresis Once
-#define ADC_DCCTL6_CIE          0x00000010  // Comparison Interrupt Enable.
-#define ADC_DCCTL6_CIC_M        0x0000000C  // Comparison Interrupt Condition.
+#define ADC_DCCTL6_CIE          0x00000010  // Comparison Interrupt Enable
+#define ADC_DCCTL6_CIC_M        0x0000000C  // Comparison Interrupt Condition
 #define ADC_DCCTL6_CIC_LOW      0x00000000  // Low Band
 #define ADC_DCCTL6_CIC_MID      0x00000004  // Mid Band
 #define ADC_DCCTL6_CIC_HIGH     0x0000000C  // High Band
-#define ADC_DCCTL6_CIM_M        0x00000003  // Comparison Interrupt Mode.
+#define ADC_DCCTL6_CIM_M        0x00000003  // Comparison Interrupt Mode
 #define ADC_DCCTL6_CIM_ALWAYS   0x00000000  // Always
 #define ADC_DCCTL6_CIM_ONCE     0x00000001  // Once
 #define ADC_DCCTL6_CIM_HALWAYS  0x00000002  // Hysteresis Always
@@ -4128,22 +4543,22 @@
 // The following are defines for the bit fields in the ADC_O_DCCTL7 register.
 //
 //*****************************************************************************
-#define ADC_DCCTL7_CTE          0x00001000  // Comparison Trigger Enable.
-#define ADC_DCCTL7_CTC_M        0x00000C00  // Comparison Trigger Condition.
+#define ADC_DCCTL7_CTE          0x00001000  // Comparison Trigger Enable
+#define ADC_DCCTL7_CTC_M        0x00000C00  // Comparison Trigger Condition
 #define ADC_DCCTL7_CTC_LOW      0x00000000  // Low Band
 #define ADC_DCCTL7_CTC_MID      0x00000400  // Mid Band
 #define ADC_DCCTL7_CTC_HIGH     0x00000C00  // High Band
-#define ADC_DCCTL7_CTM_M        0x00000300  // Comparison Trigger Mode.
+#define ADC_DCCTL7_CTM_M        0x00000300  // Comparison Trigger Mode
 #define ADC_DCCTL7_CTM_ALWAYS   0x00000000  // Always
 #define ADC_DCCTL7_CTM_ONCE     0x00000100  // Once
 #define ADC_DCCTL7_CTM_HALWAYS  0x00000200  // Hysteresis Always
 #define ADC_DCCTL7_CTM_HONCE    0x00000300  // Hysteresis Once
-#define ADC_DCCTL7_CIE          0x00000010  // Comparison Interrupt Enable.
-#define ADC_DCCTL7_CIC_M        0x0000000C  // Comparison Interrupt Condition.
+#define ADC_DCCTL7_CIE          0x00000010  // Comparison Interrupt Enable
+#define ADC_DCCTL7_CIC_M        0x0000000C  // Comparison Interrupt Condition
 #define ADC_DCCTL7_CIC_LOW      0x00000000  // Low Band
 #define ADC_DCCTL7_CIC_MID      0x00000004  // Mid Band
 #define ADC_DCCTL7_CIC_HIGH     0x0000000C  // High Band
-#define ADC_DCCTL7_CIM_M        0x00000003  // Comparison Interrupt Mode.
+#define ADC_DCCTL7_CIM_M        0x00000003  // Comparison Interrupt Mode
 #define ADC_DCCTL7_CIM_ALWAYS   0x00000000  // Always
 #define ADC_DCCTL7_CIM_ONCE     0x00000001  // Once
 #define ADC_DCCTL7_CIM_HALWAYS  0x00000002  // Hysteresis Always
@@ -4154,8 +4569,8 @@
 // The following are defines for the bit fields in the ADC_O_DCCMP0 register.
 //
 //*****************************************************************************
-#define ADC_DCCMP0_COMP1_M      0x03FF0000  // Compare 1.
-#define ADC_DCCMP0_COMP0_M      0x000003FF  // Compare 0.
+#define ADC_DCCMP0_COMP1_M      0x03FF0000  // Compare 1
+#define ADC_DCCMP0_COMP0_M      0x000003FF  // Compare 0
 #define ADC_DCCMP0_COMP1_S      16
 #define ADC_DCCMP0_COMP0_S      0
 
@@ -4164,8 +4579,8 @@
 // The following are defines for the bit fields in the ADC_O_DCCMP1 register.
 //
 //*****************************************************************************
-#define ADC_DCCMP1_COMP1_M      0x03FF0000  // Compare 1.
-#define ADC_DCCMP1_COMP0_M      0x000003FF  // Compare 0.
+#define ADC_DCCMP1_COMP1_M      0x03FF0000  // Compare 1
+#define ADC_DCCMP1_COMP0_M      0x000003FF  // Compare 0
 #define ADC_DCCMP1_COMP1_S      16
 #define ADC_DCCMP1_COMP0_S      0
 
@@ -4174,8 +4589,8 @@
 // The following are defines for the bit fields in the ADC_O_DCCMP2 register.
 //
 //*****************************************************************************
-#define ADC_DCCMP2_COMP1_M      0x03FF0000  // Compare 1.
-#define ADC_DCCMP2_COMP0_M      0x000003FF  // Compare 0.
+#define ADC_DCCMP2_COMP1_M      0x03FF0000  // Compare 1
+#define ADC_DCCMP2_COMP0_M      0x000003FF  // Compare 0
 #define ADC_DCCMP2_COMP1_S      16
 #define ADC_DCCMP2_COMP0_S      0
 
@@ -4184,8 +4599,8 @@
 // The following are defines for the bit fields in the ADC_O_DCCMP3 register.
 //
 //*****************************************************************************
-#define ADC_DCCMP3_COMP1_M      0x03FF0000  // Compare 1.
-#define ADC_DCCMP3_COMP0_M      0x000003FF  // Compare 0.
+#define ADC_DCCMP3_COMP1_M      0x03FF0000  // Compare 1
+#define ADC_DCCMP3_COMP0_M      0x000003FF  // Compare 0
 #define ADC_DCCMP3_COMP1_S      16
 #define ADC_DCCMP3_COMP0_S      0
 
@@ -4194,8 +4609,8 @@
 // The following are defines for the bit fields in the ADC_O_DCCMP4 register.
 //
 //*****************************************************************************
-#define ADC_DCCMP4_COMP1_M      0x03FF0000  // Compare 1.
-#define ADC_DCCMP4_COMP0_M      0x000003FF  // Compare 0.
+#define ADC_DCCMP4_COMP1_M      0x03FF0000  // Compare 1
+#define ADC_DCCMP4_COMP0_M      0x000003FF  // Compare 0
 #define ADC_DCCMP4_COMP1_S      16
 #define ADC_DCCMP4_COMP0_S      0
 
@@ -4204,8 +4619,8 @@
 // The following are defines for the bit fields in the ADC_O_DCCMP5 register.
 //
 //*****************************************************************************
-#define ADC_DCCMP5_COMP1_M      0x03FF0000  // Compare 1.
-#define ADC_DCCMP5_COMP0_M      0x000003FF  // Compare 0.
+#define ADC_DCCMP5_COMP1_M      0x03FF0000  // Compare 1
+#define ADC_DCCMP5_COMP0_M      0x000003FF  // Compare 0
 #define ADC_DCCMP5_COMP1_S      16
 #define ADC_DCCMP5_COMP0_S      0
 
@@ -4214,8 +4629,8 @@
 // The following are defines for the bit fields in the ADC_O_DCCMP6 register.
 //
 //*****************************************************************************
-#define ADC_DCCMP6_COMP1_M      0x03FF0000  // Compare 1.
-#define ADC_DCCMP6_COMP0_M      0x000003FF  // Compare 0.
+#define ADC_DCCMP6_COMP1_M      0x03FF0000  // Compare 1
+#define ADC_DCCMP6_COMP0_M      0x000003FF  // Compare 0
 #define ADC_DCCMP6_COMP1_S      16
 #define ADC_DCCMP6_COMP0_S      0
 
@@ -4224,8 +4639,8 @@
 // The following are defines for the bit fields in the ADC_O_DCCMP7 register.
 //
 //*****************************************************************************
-#define ADC_DCCMP7_COMP1_M      0x03FF0000  // Compare 1.
-#define ADC_DCCMP7_COMP0_M      0x000003FF  // Compare 0.
+#define ADC_DCCMP7_COMP1_M      0x03FF0000  // Compare 1
+#define ADC_DCCMP7_COMP0_M      0x000003FF  // Compare 0
 #define ADC_DCCMP7_COMP1_S      16
 #define ADC_DCCMP7_COMP0_S      0
 
@@ -4235,11 +4650,11 @@
 // SSFIFOx when the ADC TMLB is enabled.
 //
 //*****************************************************************************
-#define ADC_SSFIFO_TMLB_CNT_M   0x000003C0  // Continuous Sample Counter.
-#define ADC_SSFIFO_TMLB_CONT    0x00000020  // Continuation Sample Indicator.
-#define ADC_SSFIFO_TMLB_DIFF    0x00000010  // Differential Sample Indicator.
-#define ADC_SSFIFO_TMLB_TS      0x00000008  // Temp Sensor Sample Indicator.
-#define ADC_SSFIFO_TMLB_MUX_M   0x00000007  // Analog Input Indicator.
+#define ADC_SSFIFO_TMLB_CNT_M   0x000003C0  // Continuous Sample Counter
+#define ADC_SSFIFO_TMLB_CONT    0x00000020  // Continuation Sample Indicator
+#define ADC_SSFIFO_TMLB_DIFF    0x00000010  // Differential Sample Indicator
+#define ADC_SSFIFO_TMLB_TS      0x00000008  // Temp Sensor Sample Indicator
+#define ADC_SSFIFO_TMLB_MUX_M   0x00000007  // Analog Input Indicator
 #define ADC_SSFIFO_TMLB_CNT_S   6           // Sample counter shift
 #define ADC_SSFIFO_TMLB_MUX_S   0           // Input channel number shift
 
@@ -4249,29 +4664,29 @@
 //
 //*****************************************************************************
 #define COMP_ACMIS_IN2          0x00000004  // Comparator 2 Masked Interrupt
-                                            // Status.
+                                            // Status
 #define COMP_ACMIS_IN1          0x00000002  // Comparator 1 Masked Interrupt
-                                            // Status.
+                                            // Status
 #define COMP_ACMIS_IN0          0x00000001  // Comparator 0 Masked Interrupt
-                                            // Status.
+                                            // Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the COMP_O_ACRIS register.
 //
 //*****************************************************************************
-#define COMP_ACRIS_IN2          0x00000004  // Comparator 2 Interrupt Status.
-#define COMP_ACRIS_IN1          0x00000002  // Comparator 1 Interrupt Status.
-#define COMP_ACRIS_IN0          0x00000001  // Comparator 0 Interrupt Status.
+#define COMP_ACRIS_IN2          0x00000004  // Comparator 2 Interrupt Status
+#define COMP_ACRIS_IN1          0x00000002  // Comparator 1 Interrupt Status
+#define COMP_ACRIS_IN0          0x00000001  // Comparator 0 Interrupt Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the COMP_O_ACINTEN register.
 //
 //*****************************************************************************
-#define COMP_ACINTEN_IN2        0x00000004  // Comparator 2 Interrupt Enable.
-#define COMP_ACINTEN_IN1        0x00000002  // Comparator 1 Interrupt Enable.
-#define COMP_ACINTEN_IN0        0x00000001  // Comparator 0 Interrupt Enable.
+#define COMP_ACINTEN_IN2        0x00000004  // Comparator 2 Interrupt Enable
+#define COMP_ACINTEN_IN1        0x00000002  // Comparator 1 Interrupt Enable
+#define COMP_ACINTEN_IN0        0x00000001  // Comparator 0 Interrupt Enable
 
 //*****************************************************************************
 //
@@ -4279,9 +4694,9 @@
 // register.
 //
 //*****************************************************************************
-#define COMP_ACREFCTL_EN        0x00000200  // Resistor Ladder Enable.
-#define COMP_ACREFCTL_RNG       0x00000100  // Resistor Ladder Range.
-#define COMP_ACREFCTL_VREF_M    0x0000000F  // Resistor Ladder Voltage Ref.
+#define COMP_ACREFCTL_EN        0x00000200  // Resistor Ladder Enable
+#define COMP_ACREFCTL_RNG       0x00000100  // Resistor Ladder Range
+#define COMP_ACREFCTL_VREF_M    0x0000000F  // Resistor Ladder Voltage Ref
 #define COMP_ACREFCTL_VREF_S    0
 
 //*****************************************************************************
@@ -4289,123 +4704,122 @@
 // The following are defines for the bit fields in the COMP_O_ACSTAT0 register.
 //
 //*****************************************************************************
-#define COMP_ACSTAT0_OVAL       0x00000002  // Comparator Output Value.
+#define COMP_ACSTAT0_OVAL       0x00000002  // Comparator Output Value
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the COMP_O_ACCTL0 register.
 //
 //*****************************************************************************
-#define COMP_ACCTL0_TOEN        0x00000800  // Trigger Output Enable.
-#define COMP_ACCTL0_ASRCP_M     0x00000600  // Analog Source Positive.
-#define COMP_ACCTL0_ASRCP_PIN   0x00000000  // Pin value
+#define COMP_ACCTL0_TOEN        0x00000800  // Trigger Output Enable
+#define COMP_ACCTL0_ASRCP_M     0x00000600  // Analog Source Positive
+#define COMP_ACCTL0_ASRCP_PIN   0x00000000  // Pin value of Cn+
 #define COMP_ACCTL0_ASRCP_PIN0  0x00000200  // Pin value of C0+
 #define COMP_ACCTL0_ASRCP_REF   0x00000400  // Internal voltage reference
                                             // (VIREF)
-#define COMP_ACCTL0_TSLVAL      0x00000080  // Trigger Sense Level Value.
-#define COMP_ACCTL0_TSEN_M      0x00000060  // Trigger Sense.
+#define COMP_ACCTL0_TSLVAL      0x00000080  // Trigger Sense Level Value
+#define COMP_ACCTL0_TSEN_M      0x00000060  // Trigger Sense
 #define COMP_ACCTL0_TSEN_LEVEL  0x00000000  // Level sense, see TSLVAL
 #define COMP_ACCTL0_TSEN_FALL   0x00000020  // Falling edge
 #define COMP_ACCTL0_TSEN_RISE   0x00000040  // Rising edge
 #define COMP_ACCTL0_TSEN_BOTH   0x00000060  // Either edge
-#define COMP_ACCTL0_ISLVAL      0x00000010  // Interrupt Sense Level Value.
-#define COMP_ACCTL0_ISEN_M      0x0000000C  // Interrupt Sense.
+#define COMP_ACCTL0_ISLVAL      0x00000010  // Interrupt Sense Level Value
+#define COMP_ACCTL0_ISEN_M      0x0000000C  // Interrupt Sense
 #define COMP_ACCTL0_ISEN_LEVEL  0x00000000  // Level sense, see ISLVAL
 #define COMP_ACCTL0_ISEN_FALL   0x00000004  // Falling edge
 #define COMP_ACCTL0_ISEN_RISE   0x00000008  // Rising edge
 #define COMP_ACCTL0_ISEN_BOTH   0x0000000C  // Either edge
-#define COMP_ACCTL0_CINV        0x00000002  // Comparator Output Invert.
+#define COMP_ACCTL0_CINV        0x00000002  // Comparator Output Invert
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the COMP_O_ACSTAT1 register.
 //
 //*****************************************************************************
-#define COMP_ACSTAT1_OVAL       0x00000002  // Comparator Output Value.
+#define COMP_ACSTAT1_OVAL       0x00000002  // Comparator Output Value
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the COMP_O_ACCTL1 register.
 //
 //*****************************************************************************
-#define COMP_ACCTL1_TOEN        0x00000800  // Trigger Output Enable.
-#define COMP_ACCTL1_ASRCP_M     0x00000600  // Analog Source Positive.
-#define COMP_ACCTL1_ASRCP_PIN   0x00000000  // Pin value
+#define COMP_ACCTL1_TOEN        0x00000800  // Trigger Output Enable
+#define COMP_ACCTL1_ASRCP_M     0x00000600  // Analog Source Positive
+#define COMP_ACCTL1_ASRCP_PIN   0x00000000  // Pin value of Cn+
 #define COMP_ACCTL1_ASRCP_PIN0  0x00000200  // Pin value of C0+
 #define COMP_ACCTL1_ASRCP_REF   0x00000400  // Internal voltage reference
                                             // (VIREF)
-#define COMP_ACCTL1_TSLVAL      0x00000080  // Trigger Sense Level Value.
-#define COMP_ACCTL1_TSEN_M      0x00000060  // Trigger Sense.
+#define COMP_ACCTL1_TSLVAL      0x00000080  // Trigger Sense Level Value
+#define COMP_ACCTL1_TSEN_M      0x00000060  // Trigger Sense
 #define COMP_ACCTL1_TSEN_LEVEL  0x00000000  // Level sense, see TSLVAL
 #define COMP_ACCTL1_TSEN_FALL   0x00000020  // Falling edge
 #define COMP_ACCTL1_TSEN_RISE   0x00000040  // Rising edge
 #define COMP_ACCTL1_TSEN_BOTH   0x00000060  // Either edge
-#define COMP_ACCTL1_ISLVAL      0x00000010  // Interrupt Sense Level Value.
-#define COMP_ACCTL1_ISEN_M      0x0000000C  // Interrupt Sense.
+#define COMP_ACCTL1_ISLVAL      0x00000010  // Interrupt Sense Level Value
+#define COMP_ACCTL1_ISEN_M      0x0000000C  // Interrupt Sense
 #define COMP_ACCTL1_ISEN_LEVEL  0x00000000  // Level sense, see ISLVAL
 #define COMP_ACCTL1_ISEN_FALL   0x00000004  // Falling edge
 #define COMP_ACCTL1_ISEN_RISE   0x00000008  // Rising edge
 #define COMP_ACCTL1_ISEN_BOTH   0x0000000C  // Either edge
-#define COMP_ACCTL1_CINV        0x00000002  // Comparator Output Invert.
+#define COMP_ACCTL1_CINV        0x00000002  // Comparator Output Invert
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the COMP_O_ACSTAT2 register.
 //
 //*****************************************************************************
-#define COMP_ACSTAT2_OVAL       0x00000002  // Comparator Output Value.
+#define COMP_ACSTAT2_OVAL       0x00000002  // Comparator Output Value
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the COMP_O_ACCTL2 register.
 //
 //*****************************************************************************
-#define COMP_ACCTL2_TOEN        0x00000800  // Trigger Output Enable.
-#define COMP_ACCTL2_ASRCP_M     0x00000600  // Analog Source Positive.
-#define COMP_ACCTL2_ASRCP_PIN   0x00000000  // Pin value
+#define COMP_ACCTL2_TOEN        0x00000800  // Trigger Output Enable
+#define COMP_ACCTL2_ASRCP_M     0x00000600  // Analog Source Positive
+#define COMP_ACCTL2_ASRCP_PIN   0x00000000  // Pin value of Cn+
 #define COMP_ACCTL2_ASRCP_PIN0  0x00000200  // Pin value of C0+
 #define COMP_ACCTL2_ASRCP_REF   0x00000400  // Internal voltage reference
                                             // (VIREF)
-#define COMP_ACCTL2_TSLVAL      0x00000080  // Trigger Sense Level Value.
-#define COMP_ACCTL2_TSEN_M      0x00000060  // Trigger Sense.
+#define COMP_ACCTL2_TSLVAL      0x00000080  // Trigger Sense Level Value
+#define COMP_ACCTL2_TSEN_M      0x00000060  // Trigger Sense
 #define COMP_ACCTL2_TSEN_LEVEL  0x00000000  // Level sense, see TSLVAL
 #define COMP_ACCTL2_TSEN_FALL   0x00000020  // Falling edge
 #define COMP_ACCTL2_TSEN_RISE   0x00000040  // Rising edge
 #define COMP_ACCTL2_TSEN_BOTH   0x00000060  // Either edge
-#define COMP_ACCTL2_ISLVAL      0x00000010  // Interrupt Sense Level Value.
-#define COMP_ACCTL2_ISEN_M      0x0000000C  // Interrupt Sense.
+#define COMP_ACCTL2_ISLVAL      0x00000010  // Interrupt Sense Level Value
+#define COMP_ACCTL2_ISEN_M      0x0000000C  // Interrupt Sense
 #define COMP_ACCTL2_ISEN_LEVEL  0x00000000  // Level sense, see ISLVAL
 #define COMP_ACCTL2_ISEN_FALL   0x00000004  // Falling edge
 #define COMP_ACCTL2_ISEN_RISE   0x00000008  // Rising edge
 #define COMP_ACCTL2_ISEN_BOTH   0x0000000C  // Either edge
-#define COMP_ACCTL2_CINV        0x00000002  // Comparator Output Invert.
+#define COMP_ACCTL2_CINV        0x00000002  // Comparator Output Invert
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the CAN_O_CTL register.
 //
 //*****************************************************************************
-#define CAN_CTL_TEST            0x00000080  // Test Mode Enable.
-#define CAN_CTL_CCE             0x00000040  // Configuration Change Enable.
-#define CAN_CTL_DAR             0x00000020  // Disable
-                                            // Automatic-Retransmission.
-#define CAN_CTL_EIE             0x00000008  // Error Interrupt Enable.
-#define CAN_CTL_SIE             0x00000004  // Status Interrupt Enable.
-#define CAN_CTL_IE              0x00000002  // CAN Interrupt Enable.
-#define CAN_CTL_INIT            0x00000001  // Initialization.
+#define CAN_CTL_TEST            0x00000080  // Test Mode Enable
+#define CAN_CTL_CCE             0x00000040  // Configuration Change Enable
+#define CAN_CTL_DAR             0x00000020  // Disable Automatic-Retransmission
+#define CAN_CTL_EIE             0x00000008  // Error Interrupt Enable
+#define CAN_CTL_SIE             0x00000004  // Status Interrupt Enable
+#define CAN_CTL_IE              0x00000002  // CAN Interrupt Enable
+#define CAN_CTL_INIT            0x00000001  // Initialization
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the CAN_O_STS register.
 //
 //*****************************************************************************
-#define CAN_STS_BOFF            0x00000080  // Bus-Off Status.
-#define CAN_STS_EWARN           0x00000040  // Warning Status.
-#define CAN_STS_EPASS           0x00000020  // Error Passive.
-#define CAN_STS_RXOK            0x00000010  // Received a Message Successfully.
+#define CAN_STS_BOFF            0x00000080  // Bus-Off Status
+#define CAN_STS_EWARN           0x00000040  // Warning Status
+#define CAN_STS_EPASS           0x00000020  // Error Passive
+#define CAN_STS_RXOK            0x00000010  // Received a Message Successfully
 #define CAN_STS_TXOK            0x00000008  // Transmitted a Message
-                                            // Successfully.
-#define CAN_STS_LEC_M           0x00000007  // Last Error Code.
+                                            // Successfully
+#define CAN_STS_LEC_M           0x00000007  // Last Error Code
 #define CAN_STS_LEC_NONE        0x00000000  // No Error
 #define CAN_STS_LEC_STUFF       0x00000001  // Stuff Error
 #define CAN_STS_LEC_FORM        0x00000002  // Format Error
@@ -4413,16 +4827,16 @@
 #define CAN_STS_LEC_BIT1        0x00000004  // Bit 1 Error
 #define CAN_STS_LEC_BIT0        0x00000005  // Bit 0 Error
 #define CAN_STS_LEC_CRC         0x00000006  // CRC Error
-#define CAN_STS_LEC_NOEVENT     0x00000007  // Unused
+#define CAN_STS_LEC_NOEVENT     0x00000007  // No Event
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the CAN_O_ERR register.
 //
 //*****************************************************************************
-#define CAN_ERR_RP              0x00008000  // Received Error Passive.
-#define CAN_ERR_REC_M           0x00007F00  // Receive Error Counter.
-#define CAN_ERR_TEC_M           0x000000FF  // Transmit Error Counter.
+#define CAN_ERR_RP              0x00008000  // Received Error Passive
+#define CAN_ERR_REC_M           0x00007F00  // Receive Error Counter
+#define CAN_ERR_TEC_M           0x000000FF  // Transmit Error Counter
 #define CAN_ERR_REC_S           8
 #define CAN_ERR_TEC_S           0
 
@@ -4431,11 +4845,10 @@
 // The following are defines for the bit fields in the CAN_O_BIT register.
 //
 //*****************************************************************************
-#define CAN_BIT_TSEG2_M         0x00007000  // Time Segment after Sample Point.
-#define CAN_BIT_TSEG1_M         0x00000F00  // Time Segment Before Sample
-                                            // Point.
-#define CAN_BIT_SJW_M           0x000000C0  // (Re)Synchronization Jump Width.
-#define CAN_BIT_BRP_M           0x0000003F  // Baud Rate Prescaler.
+#define CAN_BIT_TSEG2_M         0x00007000  // Time Segment after Sample Point
+#define CAN_BIT_TSEG1_M         0x00000F00  // Time Segment Before Sample Point
+#define CAN_BIT_SJW_M           0x000000C0  // (Re)Synchronization Jump Width
+#define CAN_BIT_BRP_M           0x0000003F  // Baud Rate Prescaler
 #define CAN_BIT_TSEG2_S         12
 #define CAN_BIT_TSEG1_S         8
 #define CAN_BIT_SJW_S           6
@@ -4446,7 +4859,7 @@
 // The following are defines for the bit fields in the CAN_O_INT register.
 //
 //*****************************************************************************
-#define CAN_INT_INTID_M         0x0000FFFF  // Interrupt Identifier.
+#define CAN_INT_INTID_M         0x0000FFFF  // Interrupt Identifier
 #define CAN_INT_INTID_NONE      0x00000000  // No interrupt pending
 #define CAN_INT_INTID_STATUS    0x00008000  // Status Interrupt
 
@@ -4455,29 +4868,22 @@
 // The following are defines for the bit fields in the CAN_O_TST register.
 //
 //*****************************************************************************
-#define CAN_TST_RX              0x00000080  // Receive Observation.
-#define CAN_TST_TX_M            0x00000060  // Transmit Control.
-#define CAN_TST_TX_CANCTL       0x00000000  // CANnTx is controlled by the CAN
-                                            // module; default operation
-#define CAN_TST_TX_SAMPLE       0x00000020  // The sample point is driven on
-                                            // the CANnTx signal. This mode is
-                                            // useful to monitor bit timing.
-#define CAN_TST_TX_DOMINANT     0x00000040  // CANnTx drives a low value. This
-                                            // mode is useful for checking the
-                                            // physical layer of the CAN bus.
-#define CAN_TST_TX_RECESSIVE    0x00000060  // CANnTx drives a high value. This
-                                            // mode is useful for checking the
-                                            // physical layer of the CAN bus.
-#define CAN_TST_LBACK           0x00000010  // Loopback Mode.
-#define CAN_TST_SILENT          0x00000008  // Silent Mode.
-#define CAN_TST_BASIC           0x00000004  // Basic Mode.
+#define CAN_TST_RX              0x00000080  // Receive Observation
+#define CAN_TST_TX_M            0x00000060  // Transmit Control
+#define CAN_TST_TX_CANCTL       0x00000000  // CAN Module Control
+#define CAN_TST_TX_SAMPLE       0x00000020  // Sample Point
+#define CAN_TST_TX_DOMINANT     0x00000040  // Driven Low
+#define CAN_TST_TX_RECESSIVE    0x00000060  // Driven High
+#define CAN_TST_LBACK           0x00000010  // Loopback Mode
+#define CAN_TST_SILENT          0x00000008  // Silent Mode
+#define CAN_TST_BASIC           0x00000004  // Basic Mode
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the CAN_O_BRPE register.
 //
 //*****************************************************************************
-#define CAN_BRPE_BRPE_M         0x0000000F  // Baud Rate Prescaler Extension.
+#define CAN_BRPE_BRPE_M         0x0000000F  // Baud Rate Prescaler Extension
 #define CAN_BRPE_BRPE_S         0
 
 //*****************************************************************************
@@ -4485,33 +4891,34 @@
 // The following are defines for the bit fields in the CAN_O_IF1CRQ register.
 //
 //*****************************************************************************
-#define CAN_IF1CRQ_BUSY         0x00008000  // Busy Flag.
-#define CAN_IF1CRQ_MNUM_M       0x0000003F  // Message Number.
+#define CAN_IF1CRQ_BUSY         0x00008000  // Busy Flag
+#define CAN_IF1CRQ_MNUM_M       0x0000003F  // Message Number
 #define CAN_IF1CRQ_MNUM_RSVD    0x00000000  // 0 is not a valid message number;
                                             // it is interpreted as 0x20, or
-                                            // object 32.
+                                            // object 32
+#define CAN_IF1CRQ_MNUM_S       0
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the CAN_O_IF1CMSK register.
 //
 //*****************************************************************************
-#define CAN_IF1CMSK_WRNRD       0x00000080  // Write, Not Read.
-#define CAN_IF1CMSK_MASK        0x00000040  // Access Mask Bits.
-#define CAN_IF1CMSK_ARB         0x00000020  // Access Arbitration Bits.
-#define CAN_IF1CMSK_CONTROL     0x00000010  // Access Control Bits.
-#define CAN_IF1CMSK_CLRINTPND   0x00000008  // Clear Interrupt Pending Bit.
-#define CAN_IF1CMSK_NEWDAT      0x00000004  // NEWDAT 
-#define CAN_IF1CMSK_TXRQST      0x00000004  //  TXRQST Bit.
-#define CAN_IF1CMSK_DATAA       0x00000002  // Access Data Byte 0 to 3.
-#define CAN_IF1CMSK_DATAB       0x00000001  // Access Data Byte 4 to 7.
+#define CAN_IF1CMSK_WRNRD       0x00000080  // Write, Not Read
+#define CAN_IF1CMSK_MASK        0x00000040  // Access Mask Bits
+#define CAN_IF1CMSK_ARB         0x00000020  // Access Arbitration Bits
+#define CAN_IF1CMSK_CONTROL     0x00000010  // Access Control Bits
+#define CAN_IF1CMSK_CLRINTPND   0x00000008  // Clear Interrupt Pending Bit
+#define CAN_IF1CMSK_NEWDAT      0x00000004  // Access New Data
+#define CAN_IF1CMSK_TXRQST      0x00000004  // Access Transmission Request
+#define CAN_IF1CMSK_DATAA       0x00000002  // Access Data Byte 0 to 3
+#define CAN_IF1CMSK_DATAB       0x00000001  // Access Data Byte 4 to 7
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the CAN_O_IF1MSK1 register.
 //
 //*****************************************************************************
-#define CAN_IF1MSK1_IDMSK_M     0x0000FFFF  // Identifier Mask.
+#define CAN_IF1MSK1_IDMSK_M     0x0000FFFF  // Identifier Mask
 #define CAN_IF1MSK1_IDMSK_S     0
 
 //*****************************************************************************
@@ -4519,9 +4926,9 @@
 // The following are defines for the bit fields in the CAN_O_IF1MSK2 register.
 //
 //*****************************************************************************
-#define CAN_IF1MSK2_MXTD        0x00008000  // Mask Extended Identifier.
-#define CAN_IF1MSK2_MDIR        0x00004000  // Mask Message Direction.
-#define CAN_IF1MSK2_IDMSK_M     0x00001FFF  // Identifier Mask.
+#define CAN_IF1MSK2_MXTD        0x00008000  // Mask Extended Identifier
+#define CAN_IF1MSK2_MDIR        0x00004000  // Mask Message Direction
+#define CAN_IF1MSK2_IDMSK_M     0x00001FFF  // Identifier Mask
 #define CAN_IF1MSK2_IDMSK_S     0
 
 //*****************************************************************************
@@ -4529,7 +4936,7 @@
 // The following are defines for the bit fields in the CAN_O_IF1ARB1 register.
 //
 //*****************************************************************************
-#define CAN_IF1ARB1_ID_M        0x0000FFFF  // Message Identifier.
+#define CAN_IF1ARB1_ID_M        0x0000FFFF  // Message Identifier
 #define CAN_IF1ARB1_ID_S        0
 
 //*****************************************************************************
@@ -4537,10 +4944,10 @@
 // The following are defines for the bit fields in the CAN_O_IF1ARB2 register.
 //
 //*****************************************************************************
-#define CAN_IF1ARB2_MSGVAL      0x00008000  // Message Valid.
-#define CAN_IF1ARB2_XTD         0x00004000  // Extended Identifier.
-#define CAN_IF1ARB2_DIR         0x00002000  // Message Direction.
-#define CAN_IF1ARB2_ID_M        0x00001FFF  // Message Identifier.
+#define CAN_IF1ARB2_MSGVAL      0x00008000  // Message Valid
+#define CAN_IF1ARB2_XTD         0x00004000  // Extended Identifier
+#define CAN_IF1ARB2_DIR         0x00002000  // Message Direction
+#define CAN_IF1ARB2_ID_M        0x00001FFF  // Message Identifier
 #define CAN_IF1ARB2_ID_S        0
 
 //*****************************************************************************
@@ -4548,16 +4955,16 @@
 // The following are defines for the bit fields in the CAN_O_IF1MCTL register.
 //
 //*****************************************************************************
-#define CAN_IF1MCTL_NEWDAT      0x00008000  // New Data.
-#define CAN_IF1MCTL_MSGLST      0x00004000  // Message Lost.
-#define CAN_IF1MCTL_INTPND      0x00002000  // Interrupt Pending.
-#define CAN_IF1MCTL_UMASK       0x00001000  // Use Acceptance Mask.
-#define CAN_IF1MCTL_TXIE        0x00000800  // Transmit Interrupt Enable.
-#define CAN_IF1MCTL_RXIE        0x00000400  // Receive Interrupt Enable.
-#define CAN_IF1MCTL_RMTEN       0x00000200  // Remote Enable.
-#define CAN_IF1MCTL_TXRQST      0x00000100  // Transmit Request.
-#define CAN_IF1MCTL_EOB         0x00000080  // End of Buffer.
-#define CAN_IF1MCTL_DLC_M       0x0000000F  // Data Length Code.
+#define CAN_IF1MCTL_NEWDAT      0x00008000  // New Data
+#define CAN_IF1MCTL_MSGLST      0x00004000  // Message Lost
+#define CAN_IF1MCTL_INTPND      0x00002000  // Interrupt Pending
+#define CAN_IF1MCTL_UMASK       0x00001000  // Use Acceptance Mask
+#define CAN_IF1MCTL_TXIE        0x00000800  // Transmit Interrupt Enable
+#define CAN_IF1MCTL_RXIE        0x00000400  // Receive Interrupt Enable
+#define CAN_IF1MCTL_RMTEN       0x00000200  // Remote Enable
+#define CAN_IF1MCTL_TXRQST      0x00000100  // Transmit Request
+#define CAN_IF1MCTL_EOB         0x00000080  // End of Buffer
+#define CAN_IF1MCTL_DLC_M       0x0000000F  // Data Length Code
 #define CAN_IF1MCTL_DLC_S       0
 
 //*****************************************************************************
@@ -4565,7 +4972,7 @@
 // The following are defines for the bit fields in the CAN_O_IF1DA1 register.
 //
 //*****************************************************************************
-#define CAN_IF1DA1_DATA_M       0x0000FFFF  // Data.
+#define CAN_IF1DA1_DATA_M       0x0000FFFF  // Data
 #define CAN_IF1DA1_DATA_S       0
 
 //*****************************************************************************
@@ -4573,7 +4980,7 @@
 // The following are defines for the bit fields in the CAN_O_IF1DA2 register.
 //
 //*****************************************************************************
-#define CAN_IF1DA2_DATA_M       0x0000FFFF  // Data.
+#define CAN_IF1DA2_DATA_M       0x0000FFFF  // Data
 #define CAN_IF1DA2_DATA_S       0
 
 //*****************************************************************************
@@ -4581,7 +4988,7 @@
 // The following are defines for the bit fields in the CAN_O_IF1DB1 register.
 //
 //*****************************************************************************
-#define CAN_IF1DB1_DATA_M       0x0000FFFF  // Data.
+#define CAN_IF1DB1_DATA_M       0x0000FFFF  // Data
 #define CAN_IF1DB1_DATA_S       0
 
 //*****************************************************************************
@@ -4589,7 +4996,7 @@
 // The following are defines for the bit fields in the CAN_O_IF1DB2 register.
 //
 //*****************************************************************************
-#define CAN_IF1DB2_DATA_M       0x0000FFFF  // Data.
+#define CAN_IF1DB2_DATA_M       0x0000FFFF  // Data
 #define CAN_IF1DB2_DATA_S       0
 
 //*****************************************************************************
@@ -4597,33 +5004,34 @@
 // The following are defines for the bit fields in the CAN_O_IF2CRQ register.
 //
 //*****************************************************************************
-#define CAN_IF2CRQ_BUSY         0x00008000  // Busy Flag.
-#define CAN_IF2CRQ_MNUM_M       0x0000003F  // Message Number.
+#define CAN_IF2CRQ_BUSY         0x00008000  // Busy Flag
+#define CAN_IF2CRQ_MNUM_M       0x0000003F  // Message Number
 #define CAN_IF2CRQ_MNUM_RSVD    0x00000000  // 0 is not a valid message number;
                                             // it is interpreted as 0x20, or
-                                            // object 32.
+                                            // object 32
+#define CAN_IF2CRQ_MNUM_S       0
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the CAN_O_IF2CMSK register.
 //
 //*****************************************************************************
-#define CAN_IF2CMSK_WRNRD       0x00000080  // Write, Not Read.
-#define CAN_IF2CMSK_MASK        0x00000040  // Access Mask Bits.
-#define CAN_IF2CMSK_ARB         0x00000020  // Access Arbitration Bits.
-#define CAN_IF2CMSK_CONTROL     0x00000010  // Access Control Bits.
-#define CAN_IF2CMSK_CLRINTPND   0x00000008  // Clear Interrupt Pending Bit.
-#define CAN_IF2CMSK_NEWDAT      0x00000004  // NEWDAT 
-#define CAN_IF2CMSK_TXRQST      0x00000004  //  TXRQST Bit.
-#define CAN_IF2CMSK_DATAA       0x00000002  // Access Data Byte 0 to 3.
-#define CAN_IF2CMSK_DATAB       0x00000001  // Access Data Byte 4 to 7.
+#define CAN_IF2CMSK_WRNRD       0x00000080  // Write, Not Read
+#define CAN_IF2CMSK_MASK        0x00000040  // Access Mask Bits
+#define CAN_IF2CMSK_ARB         0x00000020  // Access Arbitration Bits
+#define CAN_IF2CMSK_CONTROL     0x00000010  // Access Control Bits
+#define CAN_IF2CMSK_CLRINTPND   0x00000008  // Clear Interrupt Pending Bit
+#define CAN_IF2CMSK_NEWDAT      0x00000004  // Access New Data
+#define CAN_IF2CMSK_TXRQST      0x00000004  // Access Transmission Request
+#define CAN_IF2CMSK_DATAA       0x00000002  // Access Data Byte 0 to 3
+#define CAN_IF2CMSK_DATAB       0x00000001  // Access Data Byte 4 to 7
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the CAN_O_IF2MSK1 register.
 //
 //*****************************************************************************
-#define CAN_IF2MSK1_IDMSK_M     0x0000FFFF  // Identifier Mask.
+#define CAN_IF2MSK1_IDMSK_M     0x0000FFFF  // Identifier Mask
 #define CAN_IF2MSK1_IDMSK_S     0
 
 //*****************************************************************************
@@ -4631,9 +5039,9 @@
 // The following are defines for the bit fields in the CAN_O_IF2MSK2 register.
 //
 //*****************************************************************************
-#define CAN_IF2MSK2_MXTD        0x00008000  // Mask Extended Identifier.
-#define CAN_IF2MSK2_MDIR        0x00004000  // Mask Message Direction.
-#define CAN_IF2MSK2_IDMSK_M     0x00001FFF  // Identifier Mask.
+#define CAN_IF2MSK2_MXTD        0x00008000  // Mask Extended Identifier
+#define CAN_IF2MSK2_MDIR        0x00004000  // Mask Message Direction
+#define CAN_IF2MSK2_IDMSK_M     0x00001FFF  // Identifier Mask
 #define CAN_IF2MSK2_IDMSK_S     0
 
 //*****************************************************************************
@@ -4641,7 +5049,7 @@
 // The following are defines for the bit fields in the CAN_O_IF2ARB1 register.
 //
 //*****************************************************************************
-#define CAN_IF2ARB1_ID_M        0x0000FFFF  // Message Identifier.
+#define CAN_IF2ARB1_ID_M        0x0000FFFF  // Message Identifier
 #define CAN_IF2ARB1_ID_S        0
 
 //*****************************************************************************
@@ -4649,10 +5057,10 @@
 // The following are defines for the bit fields in the CAN_O_IF2ARB2 register.
 //
 //*****************************************************************************
-#define CAN_IF2ARB2_MSGVAL      0x00008000  // Message Valid.
-#define CAN_IF2ARB2_XTD         0x00004000  // Extended Identifier.
-#define CAN_IF2ARB2_DIR         0x00002000  // Message Direction.
-#define CAN_IF2ARB2_ID_M        0x00001FFF  // Message Identifier.
+#define CAN_IF2ARB2_MSGVAL      0x00008000  // Message Valid
+#define CAN_IF2ARB2_XTD         0x00004000  // Extended Identifier
+#define CAN_IF2ARB2_DIR         0x00002000  // Message Direction
+#define CAN_IF2ARB2_ID_M        0x00001FFF  // Message Identifier
 #define CAN_IF2ARB2_ID_S        0
 
 //*****************************************************************************
@@ -4660,16 +5068,16 @@
 // The following are defines for the bit fields in the CAN_O_IF2MCTL register.
 //
 //*****************************************************************************
-#define CAN_IF2MCTL_NEWDAT      0x00008000  // New Data.
-#define CAN_IF2MCTL_MSGLST      0x00004000  // Message Lost.
-#define CAN_IF2MCTL_INTPND      0x00002000  // Interrupt Pending.
-#define CAN_IF2MCTL_UMASK       0x00001000  // Use Acceptance Mask.
-#define CAN_IF2MCTL_TXIE        0x00000800  // Transmit Interrupt Enable.
-#define CAN_IF2MCTL_RXIE        0x00000400  // Receive Interrupt Enable.
-#define CAN_IF2MCTL_RMTEN       0x00000200  // Remote Enable.
-#define CAN_IF2MCTL_TXRQST      0x00000100  // Transmit Request.
-#define CAN_IF2MCTL_EOB         0x00000080  // End of Buffer.
-#define CAN_IF2MCTL_DLC_M       0x0000000F  // Data Length Code.
+#define CAN_IF2MCTL_NEWDAT      0x00008000  // New Data
+#define CAN_IF2MCTL_MSGLST      0x00004000  // Message Lost
+#define CAN_IF2MCTL_INTPND      0x00002000  // Interrupt Pending
+#define CAN_IF2MCTL_UMASK       0x00001000  // Use Acceptance Mask
+#define CAN_IF2MCTL_TXIE        0x00000800  // Transmit Interrupt Enable
+#define CAN_IF2MCTL_RXIE        0x00000400  // Receive Interrupt Enable
+#define CAN_IF2MCTL_RMTEN       0x00000200  // Remote Enable
+#define CAN_IF2MCTL_TXRQST      0x00000100  // Transmit Request
+#define CAN_IF2MCTL_EOB         0x00000080  // End of Buffer
+#define CAN_IF2MCTL_DLC_M       0x0000000F  // Data Length Code
 #define CAN_IF2MCTL_DLC_S       0
 
 //*****************************************************************************
@@ -4677,7 +5085,7 @@
 // The following are defines for the bit fields in the CAN_O_IF2DA1 register.
 //
 //*****************************************************************************
-#define CAN_IF2DA1_DATA_M       0x0000FFFF  // Data.
+#define CAN_IF2DA1_DATA_M       0x0000FFFF  // Data
 #define CAN_IF2DA1_DATA_S       0
 
 //*****************************************************************************
@@ -4685,7 +5093,7 @@
 // The following are defines for the bit fields in the CAN_O_IF2DA2 register.
 //
 //*****************************************************************************
-#define CAN_IF2DA2_DATA_M       0x0000FFFF  // Data.
+#define CAN_IF2DA2_DATA_M       0x0000FFFF  // Data
 #define CAN_IF2DA2_DATA_S       0
 
 //*****************************************************************************
@@ -4693,7 +5101,7 @@
 // The following are defines for the bit fields in the CAN_O_IF2DB1 register.
 //
 //*****************************************************************************
-#define CAN_IF2DB1_DATA_M       0x0000FFFF  // Data.
+#define CAN_IF2DB1_DATA_M       0x0000FFFF  // Data
 #define CAN_IF2DB1_DATA_S       0
 
 //*****************************************************************************
@@ -4701,7 +5109,7 @@
 // The following are defines for the bit fields in the CAN_O_IF2DB2 register.
 //
 //*****************************************************************************
-#define CAN_IF2DB2_DATA_M       0x0000FFFF  // Data.
+#define CAN_IF2DB2_DATA_M       0x0000FFFF  // Data
 #define CAN_IF2DB2_DATA_S       0
 
 //*****************************************************************************
@@ -4709,7 +5117,7 @@
 // The following are defines for the bit fields in the CAN_O_TXRQ1 register.
 //
 //*****************************************************************************
-#define CAN_TXRQ1_TXRQST_M      0x0000FFFF  // Transmission Request Bits.
+#define CAN_TXRQ1_TXRQST_M      0x0000FFFF  // Transmission Request Bits
 #define CAN_TXRQ1_TXRQST_S      0
 
 //*****************************************************************************
@@ -4717,7 +5125,7 @@
 // The following are defines for the bit fields in the CAN_O_TXRQ2 register.
 //
 //*****************************************************************************
-#define CAN_TXRQ2_TXRQST_M      0x0000FFFF  // Transmission Request Bits.
+#define CAN_TXRQ2_TXRQST_M      0x0000FFFF  // Transmission Request Bits
 #define CAN_TXRQ2_TXRQST_S      0
 
 //*****************************************************************************
@@ -4725,7 +5133,7 @@
 // The following are defines for the bit fields in the CAN_O_NWDA1 register.
 //
 //*****************************************************************************
-#define CAN_NWDA1_NEWDAT_M      0x0000FFFF  // New Data Bits.
+#define CAN_NWDA1_NEWDAT_M      0x0000FFFF  // New Data Bits
 #define CAN_NWDA1_NEWDAT_S      0
 
 //*****************************************************************************
@@ -4733,7 +5141,7 @@
 // The following are defines for the bit fields in the CAN_O_NWDA2 register.
 //
 //*****************************************************************************
-#define CAN_NWDA2_NEWDAT_M      0x0000FFFF  // New Data Bits.
+#define CAN_NWDA2_NEWDAT_M      0x0000FFFF  // New Data Bits
 #define CAN_NWDA2_NEWDAT_S      0
 
 //*****************************************************************************
@@ -4741,7 +5149,7 @@
 // The following are defines for the bit fields in the CAN_O_MSG1INT register.
 //
 //*****************************************************************************
-#define CAN_MSG1INT_INTPND_M    0x0000FFFF  // Interrupt Pending Bits.
+#define CAN_MSG1INT_INTPND_M    0x0000FFFF  // Interrupt Pending Bits
 #define CAN_MSG1INT_INTPND_S    0
 
 //*****************************************************************************
@@ -4749,7 +5157,7 @@
 // The following are defines for the bit fields in the CAN_O_MSG2INT register.
 //
 //*****************************************************************************
-#define CAN_MSG2INT_INTPND_M    0x0000FFFF  // Interrupt Pending Bits.
+#define CAN_MSG2INT_INTPND_M    0x0000FFFF  // Interrupt Pending Bits
 #define CAN_MSG2INT_INTPND_S    0
 
 //*****************************************************************************
@@ -4757,7 +5165,7 @@
 // The following are defines for the bit fields in the CAN_O_MSG1VAL register.
 //
 //*****************************************************************************
-#define CAN_MSG1VAL_MSGVAL_M    0x0000FFFF  // Message Valid Bits.
+#define CAN_MSG1VAL_MSGVAL_M    0x0000FFFF  // Message Valid Bits
 #define CAN_MSG1VAL_MSGVAL_S    0
 
 //*****************************************************************************
@@ -4765,206 +5173,75 @@
 // The following are defines for the bit fields in the CAN_O_MSG2VAL register.
 //
 //*****************************************************************************
-#define CAN_MSG2VAL_MSGVAL_M    0x0000FFFF  // Message Valid Bits.
+#define CAN_MSG2VAL_MSGVAL_M    0x0000FFFF  // Message Valid Bits
 #define CAN_MSG2VAL_MSGVAL_S    0
 
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_MR0 register.
-//
-//*****************************************************************************
-#define PHY_MR0_RESET           0x00008000  // Reset Registers.
-#define PHY_MR0_LOOPBK          0x00004000  // Loopback Mode.
-#define PHY_MR0_SPEEDSL         0x00002000  // Speed Select.
-#define PHY_MR0_ANEGEN          0x00001000  // Auto-Negotiation Enable.
-#define PHY_MR0_PWRDN           0x00000800  // Power Down.
-#define PHY_MR0_ISO             0x00000400  // Isolate.
-#define PHY_MR0_RANEG           0x00000200  // Restart Auto-Negotiation.
-#define PHY_MR0_DUPLEX          0x00000100  // Set Duplex Mode.
-#define PHY_MR0_COLT            0x00000080  // Collision Test.
-
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the MAC_O_RIS register.
 //
 //*****************************************************************************
-#define MAC_RIS_PHYINT          0x00000040  // PHY Interrupt.
-#define MAC_RIS_MDINT           0x00000020  // MII Transaction Complete.
-#define MAC_RIS_RXER            0x00000010  // Receive Error.
-#define MAC_RIS_FOV             0x00000008  // FIFO Overrun.
-#define MAC_RIS_TXEMP           0x00000004  // Transmit FIFO Empty.
-#define MAC_RIS_TXER            0x00000002  // Transmit Error.
-#define MAC_RIS_RXINT           0x00000001  // Packet Received.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_IACK register.
-//
-//*****************************************************************************
-#define MAC_IACK_PHYINT         0x00000040  // Clear PHY Interrupt.
-#define MAC_IACK_MDINT          0x00000020  // Clear MII Transaction Complete.
-#define MAC_IACK_RXER           0x00000010  // Clear Receive Error.
-#define MAC_IACK_FOV            0x00000008  // Clear FIFO Overrun.
-#define MAC_IACK_TXEMP          0x00000004  // Clear Transmit FIFO Empty.
-#define MAC_IACK_TXER           0x00000002  // Clear Transmit Error.
-#define MAC_IACK_RXINT          0x00000001  // Clear Packet Received.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_MR1 register.
-//
-//*****************************************************************************
-#define PHY_MR1_100X_F          0x00004000  // 100BASE-TX Full-Duplex Mode.
-#define PHY_MR1_100X_H          0x00002000  // 100BASE-TX Half-Duplex Mode.
-#define PHY_MR1_10T_F           0x00001000  // 10BASE-T Full-Duplex Mode.
-#define PHY_MR1_10T_H           0x00000800  // 10BASE-T Half-Duplex Mode.
-#define PHY_MR1_ANEGC           0x00000020  // Auto-Negotiation Complete.
-#define PHY_MR1_RFAULT          0x00000010  // Remote Fault.
-#define PHY_MR1_ANEGA           0x00000008  // Auto-Negotiation.
-#define PHY_MR1_LINK            0x00000004  // Link Made.
-#define PHY_MR1_JAB             0x00000002  // Jabber Condition.
-#define PHY_MR1_EXTD            0x00000001  // Extended Capabilities.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_MR2 register.
-//
-//*****************************************************************************
-#define PHY_MR2_OUI_M           0x0000FFFF  // Organizationally Unique
-                                            // Identifier[21:6].
-#define PHY_MR2_OUI_S           0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_MR3 register.
-//
-//*****************************************************************************
-#define PHY_MR3_OUI_M           0x0000FC00  // Organizationally Unique
-                                            // Identifier[5:0].
-#define PHY_MR3_MN_M            0x000003F0  // Model Number.
-#define PHY_MR3_RN_M            0x0000000F  // Revision Number.
-#define PHY_MR3_OUI_S           10
-#define PHY_MR3_MN_S            4
-#define PHY_MR3_RN_S            0
+#define MAC_RIS_PHYINT          0x00000040  // PHY Interrupt
+#define MAC_RIS_MDINT           0x00000020  // MII Transaction Complete
+#define MAC_RIS_RXER            0x00000010  // Receive Error
+#define MAC_RIS_FOV             0x00000008  // FIFO Overrun
+#define MAC_RIS_TXEMP           0x00000004  // Transmit FIFO Empty
+#define MAC_RIS_TXER            0x00000002  // Transmit Error
+#define MAC_RIS_RXINT           0x00000001  // Packet Received
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the MAC_O_IM register.
 //
 //*****************************************************************************
-#define MAC_IM_PHYINTM          0x00000040  // Mask PHY Interrupt.
-#define MAC_IM_MDINTM           0x00000020  // Mask MII Transaction Complete.
-#define MAC_IM_RXERM            0x00000010  // Mask Receive Error.
-#define MAC_IM_FOVM             0x00000008  // Mask FIFO Overrun.
-#define MAC_IM_TXEMPM           0x00000004  // Mask Transmit FIFO Empty.
-#define MAC_IM_TXERM            0x00000002  // Mask Transmit Error.
-#define MAC_IM_RXINTM           0x00000001  // Mask Packet Received.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_MR4 register.
-//
-//*****************************************************************************
-#define PHY_MR4_NP              0x00008000  // Next Page.
-#define PHY_MR4_RF              0x00002000  // Remote Fault.
-#define PHY_MR4_A3              0x00000100  // Technology Ability Field[3].
-#define PHY_MR4_A2              0x00000080  // Technology Ability Field[2].
-#define PHY_MR4_A1              0x00000040  // Technology Ability Field[1].
-#define PHY_MR4_A0              0x00000020  // Technology Ability Field[0].
-#define PHY_MR4_S_M             0x0000001F  // Selector Field.
-#define PHY_MR4_S_S             0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_MR5 register.
-//
-//*****************************************************************************
-#define PHY_MR5_NP              0x00008000  // Next Page.
-#define PHY_MR5_ACK             0x00004000  // Acknowledge.
-#define PHY_MR5_RF              0x00002000  // Remote Fault.
-#define PHY_MR5_A_M             0x00001FE0  // Technology Ability Field.
-#define PHY_MR5_S_M             0x0000001F  // Selector Field.
-#define PHY_MR5_S_8023          0x00000001  // IEEE Std 802.3
-#define PHY_MR5_S_8029          0x00000002  // IEEE Std 802.9 ISLAN-16T
-#define PHY_MR5_S_8025          0x00000003  // IEEE Std 802.5
-#define PHY_MR5_S_1394          0x00000004  // IEEE Std 1394
-#define PHY_MR5_A_S             5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_MR6 register.
-//
-//*****************************************************************************
-#define PHY_MR6_PDF             0x00000010  // Parallel Detection Fault.
-#define PHY_MR6_LPNPA           0x00000008  // Link Partner is Next Page Able.
-#define PHY_MR6_PRX             0x00000002  // New Page Received.
-#define PHY_MR6_LPANEGA         0x00000001  // Link Partner is Auto-Negotiation
-                                            // Able.
+#define MAC_IM_PHYINTM          0x00000040  // Mask PHY Interrupt
+#define MAC_IM_MDINTM           0x00000020  // Mask MII Transaction Complete
+#define MAC_IM_RXERM            0x00000010  // Mask Receive Error
+#define MAC_IM_FOVM             0x00000008  // Mask FIFO Overrun
+#define MAC_IM_TXEMPM           0x00000004  // Mask Transmit FIFO Empty
+#define MAC_IM_TXERM            0x00000002  // Mask Transmit Error
+#define MAC_IM_RXINTM           0x00000001  // Mask Packet Received
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the MAC_O_RCTL register.
 //
 //*****************************************************************************
-#define MAC_RCTL_RSTFIFO        0x00000010  // Clear Receive FIFO.
-#define MAC_RCTL_BADCRC         0x00000008  // Enable Reject Bad CRC.
-#define MAC_RCTL_PRMS           0x00000004  // Enable Promiscuous Mode.
-#define MAC_RCTL_AMUL           0x00000002  // Enable Multicast Frames.
-#define MAC_RCTL_RXEN           0x00000001  // Enable Receiver.
+#define MAC_RCTL_RSTFIFO        0x00000010  // Clear Receive FIFO
+#define MAC_RCTL_BADCRC         0x00000008  // Enable Reject Bad CRC
+#define MAC_RCTL_PRMS           0x00000004  // Enable Promiscuous Mode
+#define MAC_RCTL_AMUL           0x00000002  // Enable Multicast Frames
+#define MAC_RCTL_RXEN           0x00000001  // Enable Receiver
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the MAC_O_TCTL register.
 //
 //*****************************************************************************
-#define MAC_TCTL_DUPLEX         0x00000010  // Enable Duplex Mode.
-#define MAC_TCTL_CRC            0x00000004  // Enable CRC Generation.
-#define MAC_TCTL_PADEN          0x00000002  // Enable Packet Padding.
-#define MAC_TCTL_TXEN           0x00000001  // Enable Transmitter.
+#define MAC_TCTL_DUPLEX         0x00000010  // Enable Duplex Mode
+#define MAC_TCTL_CRC            0x00000004  // Enable CRC Generation
+#define MAC_TCTL_PADEN          0x00000002  // Enable Packet Padding
+#define MAC_TCTL_TXEN           0x00000001  // Enable Transmitter
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the MAC_O_DATA register.
 //
 //*****************************************************************************
-#define MAC_DATA_TXDATA_M       0xFFFFFFFF  // Transmit FIFO Data.
-#define MAC_DATA_RXDATA_M       0xFFFFFFFF  // Receive FIFO Data.
+#define MAC_DATA_TXDATA_M       0xFFFFFFFF  // Transmit FIFO Data
+#define MAC_DATA_RXDATA_M       0xFFFFFFFF  // Receive FIFO Data
 #define MAC_DATA_RXDATA_S       0
 #define MAC_DATA_TXDATA_S       0
 
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_MR16 register.
-//
-//*****************************************************************************
-#define PHY_MR16_SR_M           0x000003C0  // Silicon Revision Identifier.
-#define PHY_MR16_SR_S           6
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_MR17 register.
-//
-//*****************************************************************************
-#define PHY_MR17_FASTRIP        0x00004000  // 10-BASE-T Fast Mode Enable.
-#define PHY_MR17_EDPD           0x00002000  // Enable Energy Detect Power Down.
-#define PHY_MR17_LSQE           0x00000800  // Low Squelch Enable.
-#define PHY_MR17_MDPB           0x00000400  // Management Data Preamble Bypass.
-#define PHY_MR17_FLPBK          0x00000200  // Far Loopback Mode.
-#define PHY_MR17_FASTEST        0x00000100  // Auto-Negotiation Test Mode.
-#define PHY_MR17_REFCE          0x00000010  // Reference Clock Enable.
-#define PHY_MR17_PADBP          0x00000008  // PHY Address Bypass.
-#define PHY_MR17_FGLS           0x00000004  // Force Good Link Status.
-#define PHY_MR17_ENON           0x00000002  // Energy On.
-
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the MAC_O_IA0 register.
 //
 //*****************************************************************************
-#define MAC_IA0_MACOCT4_M       0xFF000000  // MAC Address Octet 4.
-#define MAC_IA0_MACOCT3_M       0x00FF0000  // MAC Address Octet 3.
-#define MAC_IA0_MACOCT2_M       0x0000FF00  // MAC Address Octet 2.
-#define MAC_IA0_MACOCT1_M       0x000000FF  // MAC Address Octet 1.
+#define MAC_IA0_MACOCT4_M       0xFF000000  // MAC Address Octet 4
+#define MAC_IA0_MACOCT3_M       0x00FF0000  // MAC Address Octet 3
+#define MAC_IA0_MACOCT2_M       0x0000FF00  // MAC Address Octet 2
+#define MAC_IA0_MACOCT1_M       0x000000FF  // MAC Address Octet 1
 #define MAC_IA0_MACOCT4_S       24
 #define MAC_IA0_MACOCT3_S       16
 #define MAC_IA0_MACOCT2_S       8
@@ -4975,75 +5252,27 @@
 // The following are defines for the bit fields in the MAC_O_IA1 register.
 //
 //*****************************************************************************
-#define MAC_IA1_MACOCT6_M       0x0000FF00  // MAC Address Octet 6.
-#define MAC_IA1_MACOCT5_M       0x000000FF  // MAC Address Octet 5.
+#define MAC_IA1_MACOCT6_M       0x0000FF00  // MAC Address Octet 6
+#define MAC_IA1_MACOCT5_M       0x000000FF  // MAC Address Octet 5
 #define MAC_IA1_MACOCT6_S       8
 #define MAC_IA1_MACOCT5_S       0
 
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_MR27 register.
-//
-//*****************************************************************************
-#define PHY_MR27_XPOL           0x00000010  // Polarity State of 10 BASE-T.
-
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the MAC_O_THR register.
 //
 //*****************************************************************************
-#define MAC_THR_THRESH_M        0x0000003F  // Threshold Value.
+#define MAC_THR_THRESH_M        0x0000003F  // Threshold Value
 #define MAC_THR_THRESH_S        0
 
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_MR29 register.
-//
-//*****************************************************************************
-#define PHY_MR29_EONIS          0x00000080  // ENERGYON Interrupt.
-#define PHY_MR29_ANCOMPIS       0x00000040  // Auto-Negotiation Complete
-                                            // Interrupt.
-#define PHY_MR29_RFLTIS         0x00000020  // Remote Fault Interrupt.
-#define PHY_MR29_LDIS           0x00000010  // Link Down Interrupt.
-#define PHY_MR29_LPACKIS        0x00000008  // Auto-Negotiation LP Acknowledge.
-#define PHY_MR29_PDFIS          0x00000004  // Parallel Detection Fault.
-#define PHY_MR29_PRXIS          0x00000002  // Auto Negotiation Page Received.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_MR30 register.
-//
-//*****************************************************************************
-#define PHY_MR30_EONIM          0x00000080  // ENERGYON Interrupt Enabled.
-#define PHY_MR30_ANCOMPIM       0x00000040  // Auto-Negotiation Complete
-                                            // Interrupt Enabled.
-#define PHY_MR30_RFLTIM         0x00000020  // Remote Fault Interrupt Enabled.
-#define PHY_MR30_LDIM           0x00000010  // Link Down Interrupt Enabled.
-#define PHY_MR30_LPACKIM        0x00000008  // Auto-Negotiation LP Acknowledge
-                                            // Enabled.
-#define PHY_MR30_PDFIM          0x00000004  // Parallel Detection Fault
-                                            // Enabled.
-#define PHY_MR30_PRXIM          0x00000002  // Auto Negotiation Page Received
-                                            // Enabled.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_MR31 register.
-//
-//*****************************************************************************
-#define PHY_MR31_AUTODONE       0x00001000  // Auto Negotiation Done.
-#define PHY_MR31_SPEED_M        0x0000001C  // HCD Speed Value.
-#define PHY_MR31_SCRDIS         0x00000001  // Scramble Disable.
-#define PHY_MR31_SPEED_S        2
-
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the MAC_O_MCTL register.
 //
 //*****************************************************************************
-#define MAC_MCTL_REGADR_M       0x000000F8  // MII Register Address.
-#define MAC_MCTL_WRITE          0x00000002  // MII Register Transaction Type.
-#define MAC_MCTL_START          0x00000001  // MII Register Transaction Enable.
+#define MAC_MCTL_REGADR_M       0x000000F8  // MII Register Address
+#define MAC_MCTL_WRITE          0x00000002  // MII Register Transaction Type
+#define MAC_MCTL_START          0x00000001  // MII Register Transaction Enable
 #define MAC_MCTL_REGADR_S       3
 
 //*****************************************************************************
@@ -5051,7 +5280,7 @@
 // The following are defines for the bit fields in the MAC_O_MDV register.
 //
 //*****************************************************************************
-#define MAC_MDV_DIV_M           0x000000FF  // Clock Divider.
+#define MAC_MDV_DIV_M           0x000000FF  // Clock Divider
 #define MAC_MDV_DIV_S           0
 
 //*****************************************************************************
@@ -5059,7 +5288,7 @@
 // The following are defines for the bit fields in the MAC_O_MTXD register.
 //
 //*****************************************************************************
-#define MAC_MTXD_MDTX_M         0x0000FFFF  // MII Register Transmit Data.
+#define MAC_MTXD_MDTX_M         0x0000FFFF  // MII Register Transmit Data
 #define MAC_MTXD_MDTX_S         0
 
 //*****************************************************************************
@@ -5067,7 +5296,7 @@
 // The following are defines for the bit fields in the MAC_O_MRXD register.
 //
 //*****************************************************************************
-#define MAC_MRXD_MDRX_M         0x0000FFFF  // MII Register Receive Data.
+#define MAC_MRXD_MDRX_M         0x0000FFFF  // MII Register Receive Data
 #define MAC_MRXD_MDRX_S         0
 
 //*****************************************************************************
@@ -5076,7 +5305,7 @@
 //
 //*****************************************************************************
 #define MAC_NP_NPR_M            0x0000003F  // Number of Packets in Receive
-                                            // FIFO.
+                                            // FIFO
 #define MAC_NP_NPR_S            0
 
 //*****************************************************************************
@@ -5084,22 +5313,22 @@
 // The following are defines for the bit fields in the MAC_O_TR register.
 //
 //*****************************************************************************
-#define MAC_TR_NEWTX            0x00000001  // New Transmission.
+#define MAC_TR_NEWTX            0x00000001  // New Transmission
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the MAC_O_LED register.
 //
 //*****************************************************************************
-#define MAC_LED_LED1_M          0x000000F0  // LED1 Source.
+#define MAC_LED_LED1_M          0x00000F00  // LED1 Source
 #define MAC_LED_LED1_LINK       0x00000000  // Link OK
-#define MAC_LED_LED1_RXTX       0x00000010  // RX or TX Activity (Default LED1)
-#define MAC_LED_LED1_100        0x00000050  // 100BASE-TX mode
-#define MAC_LED_LED1_10         0x00000060  // 10BASE-T mode
-#define MAC_LED_LED1_DUPLEX     0x00000070  // Full-Duplex
-#define MAC_LED_LED1_LINKACT    0x00000080  // Link OK & Blink=RX or TX
+#define MAC_LED_LED1_RXTX       0x00000100  // RX or TX Activity (Default LED1)
+#define MAC_LED_LED1_100        0x00000500  // 100BASE-TX mode
+#define MAC_LED_LED1_10         0x00000600  // 10BASE-T mode
+#define MAC_LED_LED1_DUPLEX     0x00000700  // Full-Duplex
+#define MAC_LED_LED1_LINKACT    0x00000800  // Link OK & Blink=RX or TX
                                             // Activity
-#define MAC_LED_LED0_M          0x0000000F  // LED0 Source.
+#define MAC_LED_LED0_M          0x0000000F  // LED0 Source
 #define MAC_LED_LED0_LINK       0x00000000  // Link OK (Default LED0)
 #define MAC_LED_LED0_RXTX       0x00000001  // RX or TX Activity
 #define MAC_LED_LED0_100        0x00000005  // 100BASE-TX mode
@@ -5113,14 +5342,178 @@
 // The following are defines for the bit fields in the MAC_O_MDIX register.
 //
 //*****************************************************************************
-#define MAC_MDIX_EN             0x00000001  // MDI/MDI-X Enable.
+#define MAC_MDIX_EN             0x00000001  // MDI/MDI-X Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR0 register.
+//
+//*****************************************************************************
+#define PHY_MR0_RESET           0x00008000  // Reset Registers
+#define PHY_MR0_LOOPBK          0x00004000  // Loopback Mode
+#define PHY_MR0_SPEEDSL         0x00002000  // Speed Select
+#define PHY_MR0_ANEGEN          0x00001000  // Auto-Negotiation Enable
+#define PHY_MR0_PWRDN           0x00000800  // Power Down
+#define PHY_MR0_ISO             0x00000400  // Isolate
+#define PHY_MR0_RANEG           0x00000200  // Restart Auto-Negotiation
+#define PHY_MR0_DUPLEX          0x00000100  // Set Duplex Mode
+#define PHY_MR0_COLT            0x00000080  // Collision Test
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR1 register.
+//
+//*****************************************************************************
+#define PHY_MR1_100X_F          0x00004000  // 100BASE-TX Full-Duplex Mode
+#define PHY_MR1_100X_H          0x00002000  // 100BASE-TX Half-Duplex Mode
+#define PHY_MR1_10T_F           0x00001000  // 10BASE-T Full-Duplex Mode
+#define PHY_MR1_10T_H           0x00000800  // 10BASE-T Half-Duplex Mode
+#define PHY_MR1_ANEGC           0x00000020  // Auto-Negotiation Complete
+#define PHY_MR1_RFAULT          0x00000010  // Remote Fault
+#define PHY_MR1_ANEGA           0x00000008  // Auto-Negotiation
+#define PHY_MR1_LINK            0x00000004  // Link Made
+#define PHY_MR1_JAB             0x00000002  // Jabber Condition
+#define PHY_MR1_EXTD            0x00000001  // Extended Capabilities
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR2 register.
+//
+//*****************************************************************************
+#define PHY_MR2_OUI_M           0x0000FFFF  // Organizationally Unique
+                                            // Identifier[21:6]
+#define PHY_MR2_OUI_S           0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR3 register.
+//
+//*****************************************************************************
+#define PHY_MR3_OUI_M           0x0000FC00  // Organizationally Unique
+                                            // Identifier[5:0]
+#define PHY_MR3_MN_M            0x000003F0  // Model Number
+#define PHY_MR3_RN_M            0x0000000F  // Revision Number
+#define PHY_MR3_OUI_S           10
+#define PHY_MR3_MN_S            4
+#define PHY_MR3_RN_S            0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR4 register.
+//
+//*****************************************************************************
+#define PHY_MR4_NP              0x00008000  // Next Page
+#define PHY_MR4_RF              0x00002000  // Remote Fault
+#define PHY_MR4_A3              0x00000100  // Technology Ability Field [3]
+#define PHY_MR4_A2              0x00000080  // Technology Ability Field [2]
+#define PHY_MR4_A1              0x00000040  // Technology Ability Field [1]
+#define PHY_MR4_A0              0x00000020  // Technology Ability Field [0]
+#define PHY_MR4_S_M             0x0000001F  // Selector Field
+#define PHY_MR4_S_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR5 register.
+//
+//*****************************************************************************
+#define PHY_MR5_NP              0x00008000  // Next Page
+#define PHY_MR5_ACK             0x00004000  // Acknowledge
+#define PHY_MR5_RF              0x00002000  // Remote Fault
+#define PHY_MR5_A_M             0x00001FE0  // Technology Ability Field
+#define PHY_MR5_S_M             0x0000001F  // Selector Field
+#define PHY_MR5_S_8023          0x00000001  // IEEE Std 802.3
+#define PHY_MR5_S_8029          0x00000002  // IEEE Std 802.9 ISLAN-16T
+#define PHY_MR5_S_8025          0x00000003  // IEEE Std 802.5
+#define PHY_MR5_S_1394          0x00000004  // IEEE Std 1394
+#define PHY_MR5_A_S             5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR6 register.
+//
+//*****************************************************************************
+#define PHY_MR6_PDF             0x00000010  // Parallel Detection Fault
+#define PHY_MR6_LPNPA           0x00000008  // Link Partner is Next Page Able
+#define PHY_MR6_PRX             0x00000002  // New Page Received
+#define PHY_MR6_LPANEGA         0x00000001  // Link Partner is Auto-Negotiation
+                                            // Able
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR16 register.
+//
+//*****************************************************************************
+#define PHY_MR16_SR_M           0x000003C0  // Silicon Revision Identifier
+#define PHY_MR16_SR_S           6
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR17 register.
+//
+//*****************************************************************************
+#define PHY_MR17_FASTRIP        0x00004000  // 10-BASE-T Fast Mode Enable
+#define PHY_MR17_EDPD           0x00002000  // Enable Energy Detect Power Down
+#define PHY_MR17_LSQE           0x00000800  // Low Squelch Enable
+#define PHY_MR17_FASTEST        0x00000100  // Auto-Negotiation Test Mode
+#define PHY_MR17_FGLS           0x00000004  // Force Good Link Status
+#define PHY_MR17_ENON           0x00000002  // Energy On
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR27 register.
+//
+//*****************************************************************************
+#define PHY_MR27_XPOL           0x00000010  // Polarity State of 10 BASE-T
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR29 register.
+//
+//*****************************************************************************
+#define PHY_MR29_EONIS          0x00000080  // ENERGYON Interrupt
+#define PHY_MR29_ANCOMPIS       0x00000040  // Auto-Negotiation Complete
+                                            // Interrupt
+#define PHY_MR29_RFLTIS         0x00000020  // Remote Fault Interrupt
+#define PHY_MR29_LDIS           0x00000010  // Link Down Interrupt
+#define PHY_MR29_LPACKIS        0x00000008  // Auto-Negotiation LP Acknowledge
+#define PHY_MR29_PDFIS          0x00000004  // Parallel Detection Fault
+#define PHY_MR29_PRXIS          0x00000002  // Auto Negotiation Page Received
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR30 register.
+//
+//*****************************************************************************
+#define PHY_MR30_EONIM          0x00000080  // ENERGYON Interrupt Enabled
+#define PHY_MR30_ANCOMPIM       0x00000040  // Auto-Negotiation Complete
+                                            // Interrupt Enabled
+#define PHY_MR30_RFLTIM         0x00000020  // Remote Fault Interrupt Enabled
+#define PHY_MR30_LDIM           0x00000010  // Link Down Interrupt Enabled
+#define PHY_MR30_LPACKIM        0x00000008  // Auto-Negotiation LP Acknowledge
+                                            // Enabled
+#define PHY_MR30_PDFIM          0x00000004  // Parallel Detection Fault Enabled
+#define PHY_MR30_PRXIM          0x00000002  // Auto Negotiation Page Received
+                                            // Enabled
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR31 register.
+//
+//*****************************************************************************
+#define PHY_MR31_AUTODONE       0x00001000  // Auto Negotiation Done
+#define PHY_MR31_SPEED_M        0x0000001C  // HCD Speed Value
+#define PHY_MR31_SPEED_10HD     0x00000004  // 10BASE-T half duplex
+#define PHY_MR31_SPEED_100HD    0x00000008  // 100BASE-T half duplex
+#define PHY_MR31_SPEED_10FD     0x00000014  // 10BASE-T full duplex
+#define PHY_MR31_SPEED_100FD    0x00000018  // 100BASE-T full duplex
+#define PHY_MR31_SCRDIS         0x00000001  // Scramble Disable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_FADDR register.
 //
 //*****************************************************************************
-#define USB_FADDR_M             0x0000007F  // Function Address.
+#define USB_FADDR_M             0x0000007F  // Function Address
 #define USB_FADDR_S             0
 
 //*****************************************************************************
@@ -5128,137 +5521,136 @@
 // The following are defines for the bit fields in the USB_O_POWER register.
 //
 //*****************************************************************************
-#define USB_POWER_ISOUP         0x00000080  // ISO Update.
-#define USB_POWER_SOFTCONN      0x00000040  // Soft Connect/Disconnect.
-#define USB_POWER_RESET         0x00000008  // Reset.
-#define USB_POWER_RESUME        0x00000004  // Resume Signaling.
-#define USB_POWER_SUSPEND       0x00000002  // Suspend Mode.
-#define USB_POWER_PWRDNPHY      0x00000001  // Power Down PHY.
+#define USB_POWER_ISOUP         0x00000080  // Isochronous Update
+#define USB_POWER_SOFTCONN      0x00000040  // Soft Connect/Disconnect
+#define USB_POWER_RESET         0x00000008  // RESET Signaling
+#define USB_POWER_RESUME        0x00000004  // RESUME Signaling
+#define USB_POWER_SUSPEND       0x00000002  // SUSPEND Mode
+#define USB_POWER_PWRDNPHY      0x00000001  // Power Down PHY
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_TXIS register.
 //
 //*****************************************************************************
-#define USB_TXIS_EP15           0x00008000  // TX Endpoint 15 Interrupt.
-#define USB_TXIS_EP14           0x00004000  // TX Endpoint 14 Interrupt.
-#define USB_TXIS_EP13           0x00002000  // TX Endpoint 13 Interrupt.
-#define USB_TXIS_EP12           0x00001000  // TX Endpoint 12 Interrupt.
-#define USB_TXIS_EP11           0x00000800  // TX Endpoint 11 Interrupt.
-#define USB_TXIS_EP10           0x00000400  // TX Endpoint 10 Interrupt.
-#define USB_TXIS_EP9            0x00000200  // TX Endpoint 9 Interrupt.
-#define USB_TXIS_EP8            0x00000100  // TX Endpoint 8 Interrupt.
-#define USB_TXIS_EP7            0x00000080  // TX Endpoint 7 Interrupt.
-#define USB_TXIS_EP6            0x00000040  // TX Endpoint 6 Interrupt.
-#define USB_TXIS_EP5            0x00000020  // TX Endpoint 5 Interrupt.
-#define USB_TXIS_EP4            0x00000010  // TX Endpoint 4 Interrupt.
-#define USB_TXIS_EP3            0x00000008  // TX Endpoint 3 Interrupt.
-#define USB_TXIS_EP2            0x00000004  // TX Endpoint 2 Interrupt.
-#define USB_TXIS_EP1            0x00000002  // TX Endpoint 1 Interrupt.
-#define USB_TXIS_EP0            0x00000001  // TX and RX Endpoint 0 Interrupt.
+#define USB_TXIS_EP15           0x00008000  // TX Endpoint 15 Interrupt
+#define USB_TXIS_EP14           0x00004000  // TX Endpoint 14 Interrupt
+#define USB_TXIS_EP13           0x00002000  // TX Endpoint 13 Interrupt
+#define USB_TXIS_EP12           0x00001000  // TX Endpoint 12 Interrupt
+#define USB_TXIS_EP11           0x00000800  // TX Endpoint 11 Interrupt
+#define USB_TXIS_EP10           0x00000400  // TX Endpoint 10 Interrupt
+#define USB_TXIS_EP9            0x00000200  // TX Endpoint 9 Interrupt
+#define USB_TXIS_EP8            0x00000100  // TX Endpoint 8 Interrupt
+#define USB_TXIS_EP7            0x00000080  // TX Endpoint 7 Interrupt
+#define USB_TXIS_EP6            0x00000040  // TX Endpoint 6 Interrupt
+#define USB_TXIS_EP5            0x00000020  // TX Endpoint 5 Interrupt
+#define USB_TXIS_EP4            0x00000010  // TX Endpoint 4 Interrupt
+#define USB_TXIS_EP3            0x00000008  // TX Endpoint 3 Interrupt
+#define USB_TXIS_EP2            0x00000004  // TX Endpoint 2 Interrupt
+#define USB_TXIS_EP1            0x00000002  // TX Endpoint 1 Interrupt
+#define USB_TXIS_EP0            0x00000001  // TX and RX Endpoint 0 Interrupt
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXIS register.
 //
 //*****************************************************************************
-#define USB_RXIS_EP15           0x00008000  // RX Endpoint 15 Interrupt.
-#define USB_RXIS_EP14           0x00004000  // RX Endpoint 14 Interrupt.
-#define USB_RXIS_EP13           0x00002000  // RX Endpoint 13 Interrupt.
-#define USB_RXIS_EP12           0x00001000  // RX Endpoint 12 Interrupt.
-#define USB_RXIS_EP11           0x00000800  // RX Endpoint 11 Interrupt.
-#define USB_RXIS_EP10           0x00000400  // RX Endpoint 10 Interrupt.
-#define USB_RXIS_EP9            0x00000200  // RX Endpoint 9 Interrupt.
-#define USB_RXIS_EP8            0x00000100  // RX Endpoint 8 Interrupt.
-#define USB_RXIS_EP7            0x00000080  // RX Endpoint 7 Interrupt.
-#define USB_RXIS_EP6            0x00000040  // RX Endpoint 6 Interrupt.
-#define USB_RXIS_EP5            0x00000020  // RX Endpoint 5 Interrupt.
-#define USB_RXIS_EP4            0x00000010  // RX Endpoint 4 Interrupt.
-#define USB_RXIS_EP3            0x00000008  // RX Endpoint 3 Interrupt.
-#define USB_RXIS_EP2            0x00000004  // RX Endpoint 2 Interrupt.
-#define USB_RXIS_EP1            0x00000002  // RX Endpoint 1 Interrupt.
+#define USB_RXIS_EP15           0x00008000  // RX Endpoint 15 Interrupt
+#define USB_RXIS_EP14           0x00004000  // RX Endpoint 14 Interrupt
+#define USB_RXIS_EP13           0x00002000  // RX Endpoint 13 Interrupt
+#define USB_RXIS_EP12           0x00001000  // RX Endpoint 12 Interrupt
+#define USB_RXIS_EP11           0x00000800  // RX Endpoint 11 Interrupt
+#define USB_RXIS_EP10           0x00000400  // RX Endpoint 10 Interrupt
+#define USB_RXIS_EP9            0x00000200  // RX Endpoint 9 Interrupt
+#define USB_RXIS_EP8            0x00000100  // RX Endpoint 8 Interrupt
+#define USB_RXIS_EP7            0x00000080  // RX Endpoint 7 Interrupt
+#define USB_RXIS_EP6            0x00000040  // RX Endpoint 6 Interrupt
+#define USB_RXIS_EP5            0x00000020  // RX Endpoint 5 Interrupt
+#define USB_RXIS_EP4            0x00000010  // RX Endpoint 4 Interrupt
+#define USB_RXIS_EP3            0x00000008  // RX Endpoint 3 Interrupt
+#define USB_RXIS_EP2            0x00000004  // RX Endpoint 2 Interrupt
+#define USB_RXIS_EP1            0x00000002  // RX Endpoint 1 Interrupt
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_TXIE register.
 //
 //*****************************************************************************
-#define USB_TXIE_EP15           0x00008000  // TX Endpoint 15 Interrupt Enable.
-#define USB_TXIE_EP14           0x00004000  // TX Endpoint 14 Interrupt Enable.
-#define USB_TXIE_EP13           0x00002000  // TX Endpoint 13 Interrupt Enable.
-#define USB_TXIE_EP12           0x00001000  // TX Endpoint 12 Interrupt Enable.
-#define USB_TXIE_EP11           0x00000800  // TX Endpoint 11 Interrupt Enable.
-#define USB_TXIE_EP10           0x00000400  // TX Endpoint 10 Interrupt Enable.
-#define USB_TXIE_EP9            0x00000200  // TX Endpoint 9 Interrupt Enable.
-#define USB_TXIE_EP8            0x00000100  // TX Endpoint 8 Interrupt Enable.
-#define USB_TXIE_EP7            0x00000080  // TX Endpoint 7 Interrupt Enable.
-#define USB_TXIE_EP6            0x00000040  // TX Endpoint 6 Interrupt Enable.
-#define USB_TXIE_EP5            0x00000020  // TX Endpoint 5 Interrupt Enable.
-#define USB_TXIE_EP4            0x00000010  // TX Endpoint 4 Interrupt Enable.
-#define USB_TXIE_EP3            0x00000008  // TX Endpoint 3 Interrupt Enable.
-#define USB_TXIE_EP2            0x00000004  // TX Endpoint 2 Interrupt Enable.
-#define USB_TXIE_EP1            0x00000002  // TX Endpoint 1 Interrupt Enable.
+#define USB_TXIE_EP15           0x00008000  // TX Endpoint 15 Interrupt Enable
+#define USB_TXIE_EP14           0x00004000  // TX Endpoint 14 Interrupt Enable
+#define USB_TXIE_EP13           0x00002000  // TX Endpoint 13 Interrupt Enable
+#define USB_TXIE_EP12           0x00001000  // TX Endpoint 12 Interrupt Enable
+#define USB_TXIE_EP11           0x00000800  // TX Endpoint 11 Interrupt Enable
+#define USB_TXIE_EP10           0x00000400  // TX Endpoint 10 Interrupt Enable
+#define USB_TXIE_EP9            0x00000200  // TX Endpoint 9 Interrupt Enable
+#define USB_TXIE_EP8            0x00000100  // TX Endpoint 8 Interrupt Enable
+#define USB_TXIE_EP7            0x00000080  // TX Endpoint 7 Interrupt Enable
+#define USB_TXIE_EP6            0x00000040  // TX Endpoint 6 Interrupt Enable
+#define USB_TXIE_EP5            0x00000020  // TX Endpoint 5 Interrupt Enable
+#define USB_TXIE_EP4            0x00000010  // TX Endpoint 4 Interrupt Enable
+#define USB_TXIE_EP3            0x00000008  // TX Endpoint 3 Interrupt Enable
+#define USB_TXIE_EP2            0x00000004  // TX Endpoint 2 Interrupt Enable
+#define USB_TXIE_EP1            0x00000002  // TX Endpoint 1 Interrupt Enable
 #define USB_TXIE_EP0            0x00000001  // TX and RX Endpoint 0 Interrupt
-                                            // Enable.
+                                            // Enable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXIE register.
 //
 //*****************************************************************************
-#define USB_RXIE_EP15           0x00008000  // RX Endpoint 15 Interrupt Enable.
-#define USB_RXIE_EP14           0x00004000  // RX Endpoint 14 Interrupt Enable.
-#define USB_RXIE_EP13           0x00002000  // RX Endpoint 13 Interrupt Enable.
-#define USB_RXIE_EP12           0x00001000  // RX Endpoint 12 Interrupt Enable.
-#define USB_RXIE_EP11           0x00000800  // RX Endpoint 11 Interrupt Enable.
-#define USB_RXIE_EP10           0x00000400  // RX Endpoint 10 Interrupt Enable.
-#define USB_RXIE_EP9            0x00000200  // RX Endpoint 9 Interrupt Enable.
-#define USB_RXIE_EP8            0x00000100  // RX Endpoint 8 Interrupt Enable.
-#define USB_RXIE_EP7            0x00000080  // RX Endpoint 7 Interrupt Enable.
-#define USB_RXIE_EP6            0x00000040  // RX Endpoint 6 Interrupt Enable.
-#define USB_RXIE_EP5            0x00000020  // RX Endpoint 5 Interrupt Enable.
-#define USB_RXIE_EP4            0x00000010  // RX Endpoint 4 Interrupt Enable.
-#define USB_RXIE_EP3            0x00000008  // RX Endpoint 3 Interrupt Enable.
-#define USB_RXIE_EP2            0x00000004  // RX Endpoint 2 Interrupt Enable.
-#define USB_RXIE_EP1            0x00000002  // RX Endpoint 1 Interrupt Enable.
+#define USB_RXIE_EP15           0x00008000  // RX Endpoint 15 Interrupt Enable
+#define USB_RXIE_EP14           0x00004000  // RX Endpoint 14 Interrupt Enable
+#define USB_RXIE_EP13           0x00002000  // RX Endpoint 13 Interrupt Enable
+#define USB_RXIE_EP12           0x00001000  // RX Endpoint 12 Interrupt Enable
+#define USB_RXIE_EP11           0x00000800  // RX Endpoint 11 Interrupt Enable
+#define USB_RXIE_EP10           0x00000400  // RX Endpoint 10 Interrupt Enable
+#define USB_RXIE_EP9            0x00000200  // RX Endpoint 9 Interrupt Enable
+#define USB_RXIE_EP8            0x00000100  // RX Endpoint 8 Interrupt Enable
+#define USB_RXIE_EP7            0x00000080  // RX Endpoint 7 Interrupt Enable
+#define USB_RXIE_EP6            0x00000040  // RX Endpoint 6 Interrupt Enable
+#define USB_RXIE_EP5            0x00000020  // RX Endpoint 5 Interrupt Enable
+#define USB_RXIE_EP4            0x00000010  // RX Endpoint 4 Interrupt Enable
+#define USB_RXIE_EP3            0x00000008  // RX Endpoint 3 Interrupt Enable
+#define USB_RXIE_EP2            0x00000004  // RX Endpoint 2 Interrupt Enable
+#define USB_RXIE_EP1            0x00000002  // RX Endpoint 1 Interrupt Enable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_IS register.
 //
 //*****************************************************************************
-#define USB_IS_VBUSERR          0x00000080  // VBus Error.
-#define USB_IS_SESREQ           0x00000040  // Session Request.
-#define USB_IS_DISCON           0x00000020  // Session Disconnect.
-#define USB_IS_CONN             0x00000010  // Session Connect.
-#define USB_IS_SOF              0x00000008  // Start of Frame.
-#define USB_IS_BABBLE           0x00000004  // Babble Detected.
-#define USB_IS_RESET            0x00000004  // Reset Signal Detected.
-#define USB_IS_RESUME           0x00000002  // Resume Signal Detected.
-#define USB_IS_SUSPEND          0x00000001  // Suspend Signal Detected.
+#define USB_IS_VBUSERR          0x00000080  // VBUS Error
+#define USB_IS_SESREQ           0x00000040  // SESSION REQUEST
+#define USB_IS_DISCON           0x00000020  // Session Disconnect
+#define USB_IS_CONN             0x00000010  // Session Connect
+#define USB_IS_SOF              0x00000008  // Start of Frame
+#define USB_IS_BABBLE           0x00000004  // Babble Detected
+#define USB_IS_RESET            0x00000004  // RESET Signaling Detected
+#define USB_IS_RESUME           0x00000002  // RESUME Signaling Detected
+#define USB_IS_SUSPEND          0x00000001  // SUSPEND Signaling Detected
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_IE register.
 //
 //*****************************************************************************
-#define USB_IE_VBUSERR          0x00000080  // Enable VBUS Error Interrupt.
+#define USB_IE_VBUSERR          0x00000080  // Enable VBUS Error Interrupt
 #define USB_IE_SESREQ           0x00000040  // Enable Session Request
-                                            // Interrupt.
-#define USB_IE_DISCON           0x00000020  // Enable Disconnect Interrupt.
-#define USB_IE_CONN             0x00000010  // Enable Connect Interrupt.
-#define USB_IE_SOF              0x00000008  // Enable Start-of-Frame Interrupt.
-#define USB_IE_BABBLE           0x00000004  // Enable Babble Interrupt.
-#define USB_IE_RESET            0x00000004  // Enable Reset Interrupt.
-#define USB_IE_RESUME           0x00000002  // Enable Resume Interrupt.
-#define USB_IE_SUSPND           0x00000001  // Enable Suspend Interrupt.
+#define USB_IE_DISCON           0x00000020  // Enable Disconnect Interrupt
+#define USB_IE_CONN             0x00000010  // Enable Connect Interrupt
+#define USB_IE_SOF              0x00000008  // Enable Start-of-Frame Interrupt
+#define USB_IE_BABBLE           0x00000004  // Enable Babble Interrupt
+#define USB_IE_RESET            0x00000004  // Enable RESET Interrupt
+#define USB_IE_RESUME           0x00000002  // Enable RESUME Interrupt
+#define USB_IE_SUSPND           0x00000001  // Enable SUSPEND Interrupt
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_FRAME register.
 //
 //*****************************************************************************
-#define USB_FRAME_M             0x000007FF  // Frame Number.
+#define USB_FRAME_M             0x000007FF  // Frame Number
 #define USB_FRAME_S             0
 
 //*****************************************************************************
@@ -5266,7 +5658,7 @@
 // The following are defines for the bit fields in the USB_O_EPIDX register.
 //
 //*****************************************************************************
-#define USB_EPIDX_EPIDX_M       0x0000000F  // Endpoint Index.
+#define USB_EPIDX_EPIDX_M       0x0000000F  // Endpoint Index
 #define USB_EPIDX_EPIDX_S       0
 
 //*****************************************************************************
@@ -5274,16 +5666,16 @@
 // The following are defines for the bit fields in the USB_O_TEST register.
 //
 //*****************************************************************************
-#define USB_TEST_FORCEH         0x00000080  // Force Host Mode.
-#define USB_TEST_FIFOACC        0x00000040  // FIFO Access.
-#define USB_TEST_FORCEFS        0x00000020  // Force Full Speed.
+#define USB_TEST_FORCEH         0x00000080  // Force Host Mode
+#define USB_TEST_FIFOACC        0x00000040  // FIFO Access
+#define USB_TEST_FORCEFS        0x00000020  // Force Full-Speed Mode
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_FIFO0 register.
 //
 //*****************************************************************************
-#define USB_FIFO0_EPDATA_M      0xFFFFFFFF  // Endpoint Data.
+#define USB_FIFO0_EPDATA_M      0xFFFFFFFF  // Endpoint Data
 #define USB_FIFO0_EPDATA_S      0
 
 //*****************************************************************************
@@ -5291,7 +5683,7 @@
 // The following are defines for the bit fields in the USB_O_FIFO1 register.
 //
 //*****************************************************************************
-#define USB_FIFO1_EPDATA_M      0xFFFFFFFF  // Endpoint Data.
+#define USB_FIFO1_EPDATA_M      0xFFFFFFFF  // Endpoint Data
 #define USB_FIFO1_EPDATA_S      0
 
 //*****************************************************************************
@@ -5299,7 +5691,7 @@
 // The following are defines for the bit fields in the USB_O_FIFO2 register.
 //
 //*****************************************************************************
-#define USB_FIFO2_EPDATA_M      0xFFFFFFFF  // Endpoint Data.
+#define USB_FIFO2_EPDATA_M      0xFFFFFFFF  // Endpoint Data
 #define USB_FIFO2_EPDATA_S      0
 
 //*****************************************************************************
@@ -5307,7 +5699,7 @@
 // The following are defines for the bit fields in the USB_O_FIFO3 register.
 //
 //*****************************************************************************
-#define USB_FIFO3_EPDATA_M      0xFFFFFFFF  // Endpoint Data.
+#define USB_FIFO3_EPDATA_M      0xFFFFFFFF  // Endpoint Data
 #define USB_FIFO3_EPDATA_S      0
 
 //*****************************************************************************
@@ -5315,7 +5707,7 @@
 // The following are defines for the bit fields in the USB_O_FIFO4 register.
 //
 //*****************************************************************************
-#define USB_FIFO4_EPDATA_M      0xFFFFFFFF  // Endpoint Data.
+#define USB_FIFO4_EPDATA_M      0xFFFFFFFF  // Endpoint Data
 #define USB_FIFO4_EPDATA_S      0
 
 //*****************************************************************************
@@ -5323,7 +5715,7 @@
 // The following are defines for the bit fields in the USB_O_FIFO5 register.
 //
 //*****************************************************************************
-#define USB_FIFO5_EPDATA_M      0xFFFFFFFF  // Endpoint Data.
+#define USB_FIFO5_EPDATA_M      0xFFFFFFFF  // Endpoint Data
 #define USB_FIFO5_EPDATA_S      0
 
 //*****************************************************************************
@@ -5331,7 +5723,7 @@
 // The following are defines for the bit fields in the USB_O_FIFO6 register.
 //
 //*****************************************************************************
-#define USB_FIFO6_EPDATA_M      0xFFFFFFFF  // Endpoint Data.
+#define USB_FIFO6_EPDATA_M      0xFFFFFFFF  // Endpoint Data
 #define USB_FIFO6_EPDATA_S      0
 
 //*****************************************************************************
@@ -5339,7 +5731,7 @@
 // The following are defines for the bit fields in the USB_O_FIFO7 register.
 //
 //*****************************************************************************
-#define USB_FIFO7_EPDATA_M      0xFFFFFFFF  // Endpoint Data.
+#define USB_FIFO7_EPDATA_M      0xFFFFFFFF  // Endpoint Data
 #define USB_FIFO7_EPDATA_S      0
 
 //*****************************************************************************
@@ -5347,7 +5739,7 @@
 // The following are defines for the bit fields in the USB_O_FIFO8 register.
 //
 //*****************************************************************************
-#define USB_FIFO8_EPDATA_M      0xFFFFFFFF  // Endpoint Data.
+#define USB_FIFO8_EPDATA_M      0xFFFFFFFF  // Endpoint Data
 #define USB_FIFO8_EPDATA_S      0
 
 //*****************************************************************************
@@ -5355,7 +5747,7 @@
 // The following are defines for the bit fields in the USB_O_FIFO9 register.
 //
 //*****************************************************************************
-#define USB_FIFO9_EPDATA_M      0xFFFFFFFF  // Endpoint Data.
+#define USB_FIFO9_EPDATA_M      0xFFFFFFFF  // Endpoint Data
 #define USB_FIFO9_EPDATA_S      0
 
 //*****************************************************************************
@@ -5363,7 +5755,7 @@
 // The following are defines for the bit fields in the USB_O_FIFO10 register.
 //
 //*****************************************************************************
-#define USB_FIFO10_EPDATA_M     0xFFFFFFFF  // Endpoint Data.
+#define USB_FIFO10_EPDATA_M     0xFFFFFFFF  // Endpoint Data
 #define USB_FIFO10_EPDATA_S     0
 
 //*****************************************************************************
@@ -5371,7 +5763,7 @@
 // The following are defines for the bit fields in the USB_O_FIFO11 register.
 //
 //*****************************************************************************
-#define USB_FIFO11_EPDATA_M     0xFFFFFFFF  // Endpoint Data.
+#define USB_FIFO11_EPDATA_M     0xFFFFFFFF  // Endpoint Data
 #define USB_FIFO11_EPDATA_S     0
 
 //*****************************************************************************
@@ -5379,7 +5771,7 @@
 // The following are defines for the bit fields in the USB_O_FIFO12 register.
 //
 //*****************************************************************************
-#define USB_FIFO12_EPDATA_M     0xFFFFFFFF  // Endpoint Data.
+#define USB_FIFO12_EPDATA_M     0xFFFFFFFF  // Endpoint Data
 #define USB_FIFO12_EPDATA_S     0
 
 //*****************************************************************************
@@ -5387,7 +5779,7 @@
 // The following are defines for the bit fields in the USB_O_FIFO13 register.
 //
 //*****************************************************************************
-#define USB_FIFO13_EPDATA_M     0xFFFFFFFF  // Endpoint Data.
+#define USB_FIFO13_EPDATA_M     0xFFFFFFFF  // Endpoint Data
 #define USB_FIFO13_EPDATA_S     0
 
 //*****************************************************************************
@@ -5395,7 +5787,7 @@
 // The following are defines for the bit fields in the USB_O_FIFO14 register.
 //
 //*****************************************************************************
-#define USB_FIFO14_EPDATA_M     0xFFFFFFFF  // Endpoint Data.
+#define USB_FIFO14_EPDATA_M     0xFFFFFFFF  // Endpoint Data
 #define USB_FIFO14_EPDATA_S     0
 
 //*****************************************************************************
@@ -5403,7 +5795,7 @@
 // The following are defines for the bit fields in the USB_O_FIFO15 register.
 //
 //*****************************************************************************
-#define USB_FIFO15_EPDATA_M     0xFFFFFFFF  // Endpoint Data.
+#define USB_FIFO15_EPDATA_M     0xFFFFFFFF  // Endpoint Data
 #define USB_FIFO15_EPDATA_S     0
 
 //*****************************************************************************
@@ -5411,25 +5803,25 @@
 // The following are defines for the bit fields in the USB_O_DEVCTL register.
 //
 //*****************************************************************************
-#define USB_DEVCTL_DEV          0x00000080  // Device Mode.
-#define USB_DEVCTL_FSDEV        0x00000040  // Full-Speed Device Detected.
-#define USB_DEVCTL_LSDEV        0x00000020  // Low-Speed Device Detected.
-#define USB_DEVCTL_VBUS_M       0x00000018  // VBus Level.
+#define USB_DEVCTL_DEV          0x00000080  // Device Mode
+#define USB_DEVCTL_FSDEV        0x00000040  // Full-Speed Device Detected
+#define USB_DEVCTL_LSDEV        0x00000020  // Low-Speed Device Detected
+#define USB_DEVCTL_VBUS_M       0x00000018  // VBUS Level
 #define USB_DEVCTL_VBUS_NONE    0x00000000  // Below SessionEnd
 #define USB_DEVCTL_VBUS_SEND    0x00000008  // Above SessionEnd, below AValid
-#define USB_DEVCTL_VBUS_AVALID  0x00000010  // Above AValid, below VBusValid
-#define USB_DEVCTL_VBUS_VALID   0x00000018  // Above VBusValid
-#define USB_DEVCTL_HOST         0x00000004  // Host Mode.
-#define USB_DEVCTL_HOSTREQ      0x00000002  // Host Request.
-#define USB_DEVCTL_SESSION      0x00000001  // Session Start/End.
+#define USB_DEVCTL_VBUS_AVALID  0x00000010  // Above AValid, below VBUSValid
+#define USB_DEVCTL_VBUS_VALID   0x00000018  // Above VBUSValid
+#define USB_DEVCTL_HOST         0x00000004  // Host Mode
+#define USB_DEVCTL_HOSTREQ      0x00000002  // Host Request
+#define USB_DEVCTL_SESSION      0x00000001  // Session Start/End
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_TXFIFOSZ register.
 //
 //*****************************************************************************
-#define USB_TXFIFOSZ_DPB        0x00000010  // Double Packet Buffer Support.
-#define USB_TXFIFOSZ_SIZE_M     0x0000000F  // Max Packet Size.
+#define USB_TXFIFOSZ_DPB        0x00000010  // Double Packet Buffer Support
+#define USB_TXFIFOSZ_SIZE_M     0x0000000F  // Max Packet Size
 #define USB_TXFIFOSZ_SIZE_8     0x00000000  // 8
 #define USB_TXFIFOSZ_SIZE_16    0x00000001  // 16
 #define USB_TXFIFOSZ_SIZE_32    0x00000002  // 32
@@ -5445,8 +5837,8 @@
 // The following are defines for the bit fields in the USB_O_RXFIFOSZ register.
 //
 //*****************************************************************************
-#define USB_RXFIFOSZ_DPB        0x00000010  // Double Packet Buffer Support.
-#define USB_RXFIFOSZ_SIZE_M     0x0000000F  // Max Packet Size.
+#define USB_RXFIFOSZ_DPB        0x00000010  // Double Packet Buffer Support
+#define USB_RXFIFOSZ_SIZE_M     0x0000000F  // Max Packet Size
 #define USB_RXFIFOSZ_SIZE_8     0x00000000  // 8
 #define USB_RXFIFOSZ_SIZE_16    0x00000001  // 16
 #define USB_RXFIFOSZ_SIZE_32    0x00000002  // 32
@@ -5463,17 +5855,8 @@
 // register.
 //
 //*****************************************************************************
-#define USB_TXFIFOADD_ADDR_M    0x00001FFF  // Transmit/Receive Start Address.
-#define USB_TXFIFOADD_ADDR_0    0x00000000  // 0
-#define USB_TXFIFOADD_ADDR_8    0x00000001  // 8
-#define USB_TXFIFOADD_ADDR_16   0x00000002  // 16
-#define USB_TXFIFOADD_ADDR_32   0x00000003  // 32
-#define USB_TXFIFOADD_ADDR_64   0x00000004  // 64
-#define USB_TXFIFOADD_ADDR_128  0x00000005  // 128
-#define USB_TXFIFOADD_ADDR_256  0x00000006  // 256
-#define USB_TXFIFOADD_ADDR_512  0x00000007  // 512
-#define USB_TXFIFOADD_ADDR_1024 0x00000008  // 1024
-#define USB_TXFIFOADD_ADDR_2048 0x00000009  // 2048
+#define USB_TXFIFOADD_ADDR_M    0x000001FF  // Transmit/Receive Start Address
+#define USB_TXFIFOADD_ADDR_S    0
 
 //*****************************************************************************
 //
@@ -5481,25 +5864,16 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RXFIFOADD_ADDR_M    0x00001FFF  // Transmit/Receive Start Address.
-#define USB_RXFIFOADD_ADDR_0    0x00000000  // 0
-#define USB_RXFIFOADD_ADDR_8    0x00000001  // 8
-#define USB_RXFIFOADD_ADDR_16   0x00000002  // 16
-#define USB_RXFIFOADD_ADDR_32   0x00000003  // 32
-#define USB_RXFIFOADD_ADDR_64   0x00000004  // 64
-#define USB_RXFIFOADD_ADDR_128  0x00000005  // 128
-#define USB_RXFIFOADD_ADDR_256  0x00000006  // 256
-#define USB_RXFIFOADD_ADDR_512  0x00000007  // 512
-#define USB_RXFIFOADD_ADDR_1024 0x00000008  // 1024
-#define USB_RXFIFOADD_ADDR_2048 0x00000009  // 2048
+#define USB_RXFIFOADD_ADDR_M    0x000001FF  // Transmit/Receive Start Address
+#define USB_RXFIFOADD_ADDR_S    0
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_CONTIM register.
 //
 //*****************************************************************************
-#define USB_CONTIM_WTCON_M      0x000000F0  // Connect Wait.
-#define USB_CONTIM_WTID_M       0x0000000F  // Wait ID.
+#define USB_CONTIM_WTCON_M      0x000000F0  // Connect Wait
+#define USB_CONTIM_WTID_M       0x0000000F  // Wait ID
 #define USB_CONTIM_WTCON_S      4
 #define USB_CONTIM_WTID_S       0
 
@@ -5508,7 +5882,7 @@
 // The following are defines for the bit fields in the USB_O_VPLEN register.
 //
 //*****************************************************************************
-#define USB_VPLEN_VPLEN_M       0x000000FF  // VBus Pulse Length.
+#define USB_VPLEN_VPLEN_M       0x000000FF  // VBUS Pulse Length
 #define USB_VPLEN_VPLEN_S       0
 
 //*****************************************************************************
@@ -5516,7 +5890,7 @@
 // The following are defines for the bit fields in the USB_O_FSEOF register.
 //
 //*****************************************************************************
-#define USB_FSEOF_FSEOFG_M      0x000000FF  // Full-Speed End-of-Frame Gap.
+#define USB_FSEOF_FSEOFG_M      0x000000FF  // Full-Speed End-of-Frame Gap
 #define USB_FSEOF_FSEOFG_S      0
 
 //*****************************************************************************
@@ -5524,7 +5898,7 @@
 // The following are defines for the bit fields in the USB_O_LSEOF register.
 //
 //*****************************************************************************
-#define USB_LSEOF_LSEOFG_M      0x000000FF  // Low-Speed End-of-Frame Gap.
+#define USB_LSEOF_LSEOFG_M      0x000000FF  // Low-Speed End-of-Frame Gap
 #define USB_LSEOF_LSEOFG_S      0
 
 //*****************************************************************************
@@ -5533,7 +5907,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_TXFUNCADDR0_ADDR_M  0x0000007F  // Device Address.
+#define USB_TXFUNCADDR0_ADDR_M  0x0000007F  // Device Address
 #define USB_TXFUNCADDR0_ADDR_S  0
 
 //*****************************************************************************
@@ -5542,8 +5916,8 @@
 // register.
 //
 //*****************************************************************************
-#define USB_TXHUBADDR0_MULTTRAN 0x00000080  // Multiple Translators.
-#define USB_TXHUBADDR0_ADDR_M   0x0000007F  // Hub Address.
+#define USB_TXHUBADDR0_MULTTRAN 0x00000080  // Multiple Translators
+#define USB_TXHUBADDR0_ADDR_M   0x0000007F  // Hub Address
 #define USB_TXHUBADDR0_ADDR_S   0
 
 //*****************************************************************************
@@ -5552,7 +5926,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_TXHUBPORT0_PORT_M   0x0000007F  // Hub Port.
+#define USB_TXHUBPORT0_PORT_M   0x0000007F  // Hub Port
 #define USB_TXHUBPORT0_PORT_S   0
 
 //*****************************************************************************
@@ -5561,7 +5935,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_TXFUNCADDR1_ADDR_M  0x0000007F  // Device Address.
+#define USB_TXFUNCADDR1_ADDR_M  0x0000007F  // Device Address
 #define USB_TXFUNCADDR1_ADDR_S  0
 
 //*****************************************************************************
@@ -5570,8 +5944,8 @@
 // register.
 //
 //*****************************************************************************
-#define USB_TXHUBADDR1_MULTTRAN 0x00000080  // Multiple Translators.
-#define USB_TXHUBADDR1_ADDR_M   0x0000007F  // Hub Address.
+#define USB_TXHUBADDR1_MULTTRAN 0x00000080  // Multiple Translators
+#define USB_TXHUBADDR1_ADDR_M   0x0000007F  // Hub Address
 #define USB_TXHUBADDR1_ADDR_S   0
 
 //*****************************************************************************
@@ -5580,7 +5954,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_TXHUBPORT1_PORT_M   0x0000007F  // Hub Port.
+#define USB_TXHUBPORT1_PORT_M   0x0000007F  // Hub Port
 #define USB_TXHUBPORT1_PORT_S   0
 
 //*****************************************************************************
@@ -5589,7 +5963,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RXFUNCADDR1_ADDR_M  0x0000007F  // Device Address.
+#define USB_RXFUNCADDR1_ADDR_M  0x0000007F  // Device Address
 #define USB_RXFUNCADDR1_ADDR_S  0
 
 //*****************************************************************************
@@ -5598,8 +5972,8 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RXHUBADDR1_MULTTRAN 0x00000080  // Multiple Translators.
-#define USB_RXHUBADDR1_ADDR_M   0x0000007F  // Hub Address.
+#define USB_RXHUBADDR1_MULTTRAN 0x00000080  // Multiple Translators
+#define USB_RXHUBADDR1_ADDR_M   0x0000007F  // Hub Address
 #define USB_RXHUBADDR1_ADDR_S   0
 
 //*****************************************************************************
@@ -5608,7 +5982,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RXHUBPORT1_PORT_M   0x0000007F  // Hub Port.
+#define USB_RXHUBPORT1_PORT_M   0x0000007F  // Hub Port
 #define USB_RXHUBPORT1_PORT_S   0
 
 //*****************************************************************************
@@ -5617,7 +5991,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_TXFUNCADDR2_ADDR_M  0x0000007F  // Device Address.
+#define USB_TXFUNCADDR2_ADDR_M  0x0000007F  // Device Address
 #define USB_TXFUNCADDR2_ADDR_S  0
 
 //*****************************************************************************
@@ -5626,8 +6000,8 @@
 // register.
 //
 //*****************************************************************************
-#define USB_TXHUBADDR2_MULTTRAN 0x00000080  // Multiple Translators.
-#define USB_TXHUBADDR2_ADDR_M   0x0000007F  // Hub Address.
+#define USB_TXHUBADDR2_MULTTRAN 0x00000080  // Multiple Translators
+#define USB_TXHUBADDR2_ADDR_M   0x0000007F  // Hub Address
 #define USB_TXHUBADDR2_ADDR_S   0
 
 //*****************************************************************************
@@ -5636,7 +6010,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_TXHUBPORT2_PORT_M   0x0000007F  // Hub Port.
+#define USB_TXHUBPORT2_PORT_M   0x0000007F  // Hub Port
 #define USB_TXHUBPORT2_PORT_S   0
 
 //*****************************************************************************
@@ -5645,7 +6019,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RXFUNCADDR2_ADDR_M  0x0000007F  // Device Address.
+#define USB_RXFUNCADDR2_ADDR_M  0x0000007F  // Device Address
 #define USB_RXFUNCADDR2_ADDR_S  0
 
 //*****************************************************************************
@@ -5654,8 +6028,8 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RXHUBADDR2_MULTTRAN 0x00000080  // Multiple Translators.
-#define USB_RXHUBADDR2_ADDR_M   0x0000007F  // Hub Address.
+#define USB_RXHUBADDR2_MULTTRAN 0x00000080  // Multiple Translators
+#define USB_RXHUBADDR2_ADDR_M   0x0000007F  // Hub Address
 #define USB_RXHUBADDR2_ADDR_S   0
 
 //*****************************************************************************
@@ -5664,7 +6038,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RXHUBPORT2_PORT_M   0x0000007F  // Hub Port.
+#define USB_RXHUBPORT2_PORT_M   0x0000007F  // Hub Port
 #define USB_RXHUBPORT2_PORT_S   0
 
 //*****************************************************************************
@@ -5673,7 +6047,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_TXFUNCADDR3_ADDR_M  0x0000007F  // Device Address.
+#define USB_TXFUNCADDR3_ADDR_M  0x0000007F  // Device Address
 #define USB_TXFUNCADDR3_ADDR_S  0
 
 //*****************************************************************************
@@ -5682,8 +6056,8 @@
 // register.
 //
 //*****************************************************************************
-#define USB_TXHUBADDR3_MULTTRAN 0x00000080  // Multiple Translators.
-#define USB_TXHUBADDR3_ADDR_M   0x0000007F  // Hub Address.
+#define USB_TXHUBADDR3_MULTTRAN 0x00000080  // Multiple Translators
+#define USB_TXHUBADDR3_ADDR_M   0x0000007F  // Hub Address
 #define USB_TXHUBADDR3_ADDR_S   0
 
 //*****************************************************************************
@@ -5692,7 +6066,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_TXHUBPORT3_PORT_M   0x0000007F  // Hub Port.
+#define USB_TXHUBPORT3_PORT_M   0x0000007F  // Hub Port
 #define USB_TXHUBPORT3_PORT_S   0
 
 //*****************************************************************************
@@ -5701,7 +6075,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RXFUNCADDR3_ADDR_M  0x0000007F  // Device Address.
+#define USB_RXFUNCADDR3_ADDR_M  0x0000007F  // Device Address
 #define USB_RXFUNCADDR3_ADDR_S  0
 
 //*****************************************************************************
@@ -5710,8 +6084,8 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RXHUBADDR3_MULTTRAN 0x00000080  // Multiple Translators.
-#define USB_RXHUBADDR3_ADDR_M   0x0000007F  // Hub Address.
+#define USB_RXHUBADDR3_MULTTRAN 0x00000080  // Multiple Translators
+#define USB_RXHUBADDR3_ADDR_M   0x0000007F  // Hub Address
 #define USB_RXHUBADDR3_ADDR_S   0
 
 //*****************************************************************************
@@ -5720,7 +6094,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RXHUBPORT3_PORT_M   0x0000007F  // Hub Port.
+#define USB_RXHUBPORT3_PORT_M   0x0000007F  // Hub Port
 #define USB_RXHUBPORT3_PORT_S   0
 
 //*****************************************************************************
@@ -5729,7 +6103,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_TXFUNCADDR4_ADDR_M  0x0000007F  // Device Address.
+#define USB_TXFUNCADDR4_ADDR_M  0x0000007F  // Device Address
 #define USB_TXFUNCADDR4_ADDR_S  0
 
 //*****************************************************************************
@@ -5738,8 +6112,8 @@
 // register.
 //
 //*****************************************************************************
-#define USB_TXHUBADDR4_MULTTRAN 0x00000080  // Multiple Translators.
-#define USB_TXHUBADDR4_ADDR_M   0x0000007F  // Hub Address.
+#define USB_TXHUBADDR4_MULTTRAN 0x00000080  // Multiple Translators
+#define USB_TXHUBADDR4_ADDR_M   0x0000007F  // Hub Address
 #define USB_TXHUBADDR4_ADDR_S   0
 
 //*****************************************************************************
@@ -5748,7 +6122,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_TXHUBPORT4_PORT_M   0x0000007F  // Hub Port.
+#define USB_TXHUBPORT4_PORT_M   0x0000007F  // Hub Port
 #define USB_TXHUBPORT4_PORT_S   0
 
 //*****************************************************************************
@@ -5757,7 +6131,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RXFUNCADDR4_ADDR_M  0x0000007F  // Device Address.
+#define USB_RXFUNCADDR4_ADDR_M  0x0000007F  // Device Address
 #define USB_RXFUNCADDR4_ADDR_S  0
 
 //*****************************************************************************
@@ -5766,8 +6140,8 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RXHUBADDR4_MULTTRAN 0x00000080  // Multiple Translators.
-#define USB_RXHUBADDR4_ADDR_M   0x0000007F  // Hub Address.
+#define USB_RXHUBADDR4_MULTTRAN 0x00000080  // Multiple Translators
+#define USB_RXHUBADDR4_ADDR_M   0x0000007F  // Hub Address
 #define USB_RXHUBADDR4_ADDR_S   0
 
 //*****************************************************************************
@@ -5776,7 +6150,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RXHUBPORT4_PORT_M   0x0000007F  // Hub Port.
+#define USB_RXHUBPORT4_PORT_M   0x0000007F  // Hub Port
 #define USB_RXHUBPORT4_PORT_S   0
 
 //*****************************************************************************
@@ -5785,7 +6159,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_TXFUNCADDR5_ADDR_M  0x0000007F  // Device Address.
+#define USB_TXFUNCADDR5_ADDR_M  0x0000007F  // Device Address
 #define USB_TXFUNCADDR5_ADDR_S  0
 
 //*****************************************************************************
@@ -5794,8 +6168,8 @@
 // register.
 //
 //*****************************************************************************
-#define USB_TXHUBADDR5_MULTTRAN 0x00000080  // Multiple Translators.
-#define USB_TXHUBADDR5_ADDR_M   0x0000007F  // Hub Address.
+#define USB_TXHUBADDR5_MULTTRAN 0x00000080  // Multiple Translators
+#define USB_TXHUBADDR5_ADDR_M   0x0000007F  // Hub Address
 #define USB_TXHUBADDR5_ADDR_S   0
 
 //*****************************************************************************
@@ -5804,7 +6178,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_TXHUBPORT5_PORT_M   0x0000007F  // Hub Port.
+#define USB_TXHUBPORT5_PORT_M   0x0000007F  // Hub Port
 #define USB_TXHUBPORT5_PORT_S   0
 
 //*****************************************************************************
@@ -5813,7 +6187,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RXFUNCADDR5_ADDR_M  0x0000007F  // Device Address.
+#define USB_RXFUNCADDR5_ADDR_M  0x0000007F  // Device Address
 #define USB_RXFUNCADDR5_ADDR_S  0
 
 //*****************************************************************************
@@ -5822,8 +6196,8 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RXHUBADDR5_MULTTRAN 0x00000080  // Multiple Translators.
-#define USB_RXHUBADDR5_ADDR_M   0x0000007F  // Hub Address.
+#define USB_RXHUBADDR5_MULTTRAN 0x00000080  // Multiple Translators
+#define USB_RXHUBADDR5_ADDR_M   0x0000007F  // Hub Address
 #define USB_RXHUBADDR5_ADDR_S   0
 
 //*****************************************************************************
@@ -5832,7 +6206,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RXHUBPORT5_PORT_M   0x0000007F  // Hub Port.
+#define USB_RXHUBPORT5_PORT_M   0x0000007F  // Hub Port
 #define USB_RXHUBPORT5_PORT_S   0
 
 //*****************************************************************************
@@ -5841,7 +6215,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_TXFUNCADDR6_ADDR_M  0x0000007F  // Device Address.
+#define USB_TXFUNCADDR6_ADDR_M  0x0000007F  // Device Address
 #define USB_TXFUNCADDR6_ADDR_S  0
 
 //*****************************************************************************
@@ -5850,8 +6224,8 @@
 // register.
 //
 //*****************************************************************************
-#define USB_TXHUBADDR6_MULTTRAN 0x00000080  // Multiple Translators.
-#define USB_TXHUBADDR6_ADDR_M   0x0000007F  // Hub Address.
+#define USB_TXHUBADDR6_MULTTRAN 0x00000080  // Multiple Translators
+#define USB_TXHUBADDR6_ADDR_M   0x0000007F  // Hub Address
 #define USB_TXHUBADDR6_ADDR_S   0
 
 //*****************************************************************************
@@ -5860,7 +6234,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_TXHUBPORT6_PORT_M   0x0000007F  // Hub Port.
+#define USB_TXHUBPORT6_PORT_M   0x0000007F  // Hub Port
 #define USB_TXHUBPORT6_PORT_S   0
 
 //*****************************************************************************
@@ -5869,7 +6243,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RXFUNCADDR6_ADDR_M  0x0000007F  // Device Address.
+#define USB_RXFUNCADDR6_ADDR_M  0x0000007F  // Device Address
 #define USB_RXFUNCADDR6_ADDR_S  0
 
 //*****************************************************************************
@@ -5878,8 +6252,8 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RXHUBADDR6_MULTTRAN 0x00000080  // Multiple Translators.
-#define USB_RXHUBADDR6_ADDR_M   0x0000007F  // Hub Address.
+#define USB_RXHUBADDR6_MULTTRAN 0x00000080  // Multiple Translators
+#define USB_RXHUBADDR6_ADDR_M   0x0000007F  // Hub Address
 #define USB_RXHUBADDR6_ADDR_S   0
 
 //*****************************************************************************
@@ -5888,7 +6262,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RXHUBPORT6_PORT_M   0x0000007F  // Hub Port.
+#define USB_RXHUBPORT6_PORT_M   0x0000007F  // Hub Port
 #define USB_RXHUBPORT6_PORT_S   0
 
 //*****************************************************************************
@@ -5897,7 +6271,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_TXFUNCADDR7_ADDR_M  0x0000007F  // Device Address.
+#define USB_TXFUNCADDR7_ADDR_M  0x0000007F  // Device Address
 #define USB_TXFUNCADDR7_ADDR_S  0
 
 //*****************************************************************************
@@ -5906,8 +6280,8 @@
 // register.
 //
 //*****************************************************************************
-#define USB_TXHUBADDR7_MULTTRAN 0x00000080  // Multiple Translators.
-#define USB_TXHUBADDR7_ADDR_M   0x0000007F  // Hub Address.
+#define USB_TXHUBADDR7_MULTTRAN 0x00000080  // Multiple Translators
+#define USB_TXHUBADDR7_ADDR_M   0x0000007F  // Hub Address
 #define USB_TXHUBADDR7_ADDR_S   0
 
 //*****************************************************************************
@@ -5916,7 +6290,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_TXHUBPORT7_PORT_M   0x0000007F  // Hub Port.
+#define USB_TXHUBPORT7_PORT_M   0x0000007F  // Hub Port
 #define USB_TXHUBPORT7_PORT_S   0
 
 //*****************************************************************************
@@ -5925,7 +6299,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RXFUNCADDR7_ADDR_M  0x0000007F  // Device Address.
+#define USB_RXFUNCADDR7_ADDR_M  0x0000007F  // Device Address
 #define USB_RXFUNCADDR7_ADDR_S  0
 
 //*****************************************************************************
@@ -5934,8 +6308,8 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RXHUBADDR7_MULTTRAN 0x00000080  // Multiple Translators.
-#define USB_RXHUBADDR7_ADDR_M   0x0000007F  // Hub Address.
+#define USB_RXHUBADDR7_MULTTRAN 0x00000080  // Multiple Translators
+#define USB_RXHUBADDR7_ADDR_M   0x0000007F  // Hub Address
 #define USB_RXHUBADDR7_ADDR_S   0
 
 //*****************************************************************************
@@ -5944,7 +6318,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RXHUBPORT7_PORT_M   0x0000007F  // Hub Port.
+#define USB_RXHUBPORT7_PORT_M   0x0000007F  // Hub Port
 #define USB_RXHUBPORT7_PORT_S   0
 
 //*****************************************************************************
@@ -5953,7 +6327,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_TXFUNCADDR8_ADDR_M  0x0000007F  // Device Address.
+#define USB_TXFUNCADDR8_ADDR_M  0x0000007F  // Device Address
 #define USB_TXFUNCADDR8_ADDR_S  0
 
 //*****************************************************************************
@@ -5962,8 +6336,8 @@
 // register.
 //
 //*****************************************************************************
-#define USB_TXHUBADDR8_MULTTRAN 0x00000080  // Multiple Translators.
-#define USB_TXHUBADDR8_ADDR_M   0x0000007F  // Hub Address.
+#define USB_TXHUBADDR8_MULTTRAN 0x00000080  // Multiple Translators
+#define USB_TXHUBADDR8_ADDR_M   0x0000007F  // Hub Address
 #define USB_TXHUBADDR8_ADDR_S   0
 
 //*****************************************************************************
@@ -5972,7 +6346,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_TXHUBPORT8_PORT_M   0x0000007F  // Hub Port.
+#define USB_TXHUBPORT8_PORT_M   0x0000007F  // Hub Port
 #define USB_TXHUBPORT8_PORT_S   0
 
 //*****************************************************************************
@@ -5981,7 +6355,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RXFUNCADDR8_ADDR_M  0x0000007F  // Device Address.
+#define USB_RXFUNCADDR8_ADDR_M  0x0000007F  // Device Address
 #define USB_RXFUNCADDR8_ADDR_S  0
 
 //*****************************************************************************
@@ -5990,8 +6364,8 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RXHUBADDR8_MULTTRAN 0x00000080  // Multiple Translators.
-#define USB_RXHUBADDR8_ADDR_M   0x0000007F  // Hub Address.
+#define USB_RXHUBADDR8_MULTTRAN 0x00000080  // Multiple Translators
+#define USB_RXHUBADDR8_ADDR_M   0x0000007F  // Hub Address
 #define USB_RXHUBADDR8_ADDR_S   0
 
 //*****************************************************************************
@@ -6000,7 +6374,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RXHUBPORT8_PORT_M   0x0000007F  // Hub Port.
+#define USB_RXHUBPORT8_PORT_M   0x0000007F  // Hub Port
 #define USB_RXHUBPORT8_PORT_S   0
 
 //*****************************************************************************
@@ -6009,7 +6383,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_TXFUNCADDR9_ADDR_M  0x0000007F  // Device Address.
+#define USB_TXFUNCADDR9_ADDR_M  0x0000007F  // Device Address
 #define USB_TXFUNCADDR9_ADDR_S  0
 
 //*****************************************************************************
@@ -6018,8 +6392,8 @@
 // register.
 //
 //*****************************************************************************
-#define USB_TXHUBADDR9_MULTTRAN 0x00000080  // Multiple Translators.
-#define USB_TXHUBADDR9_ADDR_M   0x0000007F  // Hub Address.
+#define USB_TXHUBADDR9_MULTTRAN 0x00000080  // Multiple Translators
+#define USB_TXHUBADDR9_ADDR_M   0x0000007F  // Hub Address
 #define USB_TXHUBADDR9_ADDR_S   0
 
 //*****************************************************************************
@@ -6028,7 +6402,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_TXHUBPORT9_PORT_M   0x0000007F  // Hub Port.
+#define USB_TXHUBPORT9_PORT_M   0x0000007F  // Hub Port
 #define USB_TXHUBPORT9_PORT_S   0
 
 //*****************************************************************************
@@ -6037,7 +6411,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RXFUNCADDR9_ADDR_M  0x0000007F  // Device Address.
+#define USB_RXFUNCADDR9_ADDR_M  0x0000007F  // Device Address
 #define USB_RXFUNCADDR9_ADDR_S  0
 
 //*****************************************************************************
@@ -6046,8 +6420,8 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RXHUBADDR9_MULTTRAN 0x00000080  // Multiple Translators.
-#define USB_RXHUBADDR9_ADDR_M   0x0000007F  // Hub Address.
+#define USB_RXHUBADDR9_MULTTRAN 0x00000080  // Multiple Translators
+#define USB_RXHUBADDR9_ADDR_M   0x0000007F  // Hub Address
 #define USB_RXHUBADDR9_ADDR_S   0
 
 //*****************************************************************************
@@ -6056,7 +6430,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RXHUBPORT9_PORT_M   0x0000007F  // Hub Port.
+#define USB_RXHUBPORT9_PORT_M   0x0000007F  // Hub Port
 #define USB_RXHUBPORT9_PORT_S   0
 
 //*****************************************************************************
@@ -6065,7 +6439,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_TXFUNCADDR10_ADDR_M 0x0000007F  // Device Address.
+#define USB_TXFUNCADDR10_ADDR_M 0x0000007F  // Device Address
 #define USB_TXFUNCADDR10_ADDR_S 0
 
 //*****************************************************************************
@@ -6075,8 +6449,8 @@
 //
 //*****************************************************************************
 #define USB_TXHUBADDR10_MULTTRAN \
-                                0x00000080  // Multiple Translators.
-#define USB_TXHUBADDR10_ADDR_M  0x0000007F  // Hub Address.
+                                0x00000080  // Multiple Translators
+#define USB_TXHUBADDR10_ADDR_M  0x0000007F  // Hub Address
 #define USB_TXHUBADDR10_ADDR_S  0
 
 //*****************************************************************************
@@ -6085,7 +6459,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_TXHUBPORT10_PORT_M  0x0000007F  // Hub Port.
+#define USB_TXHUBPORT10_PORT_M  0x0000007F  // Hub Port
 #define USB_TXHUBPORT10_PORT_S  0
 
 //*****************************************************************************
@@ -6094,7 +6468,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RXFUNCADDR10_ADDR_M 0x0000007F  // Device Address.
+#define USB_RXFUNCADDR10_ADDR_M 0x0000007F  // Device Address
 #define USB_RXFUNCADDR10_ADDR_S 0
 
 //*****************************************************************************
@@ -6104,8 +6478,8 @@
 //
 //*****************************************************************************
 #define USB_RXHUBADDR10_MULTTRAN \
-                                0x00000080  // Multiple Translators.
-#define USB_RXHUBADDR10_ADDR_M  0x0000007F  // Hub Address.
+                                0x00000080  // Multiple Translators
+#define USB_RXHUBADDR10_ADDR_M  0x0000007F  // Hub Address
 #define USB_RXHUBADDR10_ADDR_S  0
 
 //*****************************************************************************
@@ -6114,7 +6488,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RXHUBPORT10_PORT_M  0x0000007F  // Hub Port.
+#define USB_RXHUBPORT10_PORT_M  0x0000007F  // Hub Port
 #define USB_RXHUBPORT10_PORT_S  0
 
 //*****************************************************************************
@@ -6123,7 +6497,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_TXFUNCADDR11_ADDR_M 0x0000007F  // Device Address.
+#define USB_TXFUNCADDR11_ADDR_M 0x0000007F  // Device Address
 #define USB_TXFUNCADDR11_ADDR_S 0
 
 //*****************************************************************************
@@ -6133,8 +6507,8 @@
 //
 //*****************************************************************************
 #define USB_TXHUBADDR11_MULTTRAN \
-                                0x00000080  // Multiple Translators.
-#define USB_TXHUBADDR11_ADDR_M  0x0000007F  // Hub Address.
+                                0x00000080  // Multiple Translators
+#define USB_TXHUBADDR11_ADDR_M  0x0000007F  // Hub Address
 #define USB_TXHUBADDR11_ADDR_S  0
 
 //*****************************************************************************
@@ -6143,7 +6517,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_TXHUBPORT11_PORT_M  0x0000007F  // Hub Port.
+#define USB_TXHUBPORT11_PORT_M  0x0000007F  // Hub Port
 #define USB_TXHUBPORT11_PORT_S  0
 
 //*****************************************************************************
@@ -6152,7 +6526,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RXFUNCADDR11_ADDR_M 0x0000007F  // Device Address.
+#define USB_RXFUNCADDR11_ADDR_M 0x0000007F  // Device Address
 #define USB_RXFUNCADDR11_ADDR_S 0
 
 //*****************************************************************************
@@ -6162,8 +6536,8 @@
 //
 //*****************************************************************************
 #define USB_RXHUBADDR11_MULTTRAN \
-                                0x00000080  // Multiple Translators.
-#define USB_RXHUBADDR11_ADDR_M  0x0000007F  // Hub Address.
+                                0x00000080  // Multiple Translators
+#define USB_RXHUBADDR11_ADDR_M  0x0000007F  // Hub Address
 #define USB_RXHUBADDR11_ADDR_S  0
 
 //*****************************************************************************
@@ -6172,7 +6546,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RXHUBPORT11_PORT_M  0x0000007F  // Hub Port.
+#define USB_RXHUBPORT11_PORT_M  0x0000007F  // Hub Port
 #define USB_RXHUBPORT11_PORT_S  0
 
 //*****************************************************************************
@@ -6181,7 +6555,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_TXFUNCADDR12_ADDR_M 0x0000007F  // Device Address.
+#define USB_TXFUNCADDR12_ADDR_M 0x0000007F  // Device Address
 #define USB_TXFUNCADDR12_ADDR_S 0
 
 //*****************************************************************************
@@ -6191,8 +6565,8 @@
 //
 //*****************************************************************************
 #define USB_TXHUBADDR12_MULTTRAN \
-                                0x00000080  // Multiple Translators.
-#define USB_TXHUBADDR12_ADDR_M  0x0000007F  // Hub Address.
+                                0x00000080  // Multiple Translators
+#define USB_TXHUBADDR12_ADDR_M  0x0000007F  // Hub Address
 #define USB_TXHUBADDR12_ADDR_S  0
 
 //*****************************************************************************
@@ -6201,7 +6575,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_TXHUBPORT12_PORT_M  0x0000007F  // Hub Port.
+#define USB_TXHUBPORT12_PORT_M  0x0000007F  // Hub Port
 #define USB_TXHUBPORT12_PORT_S  0
 
 //*****************************************************************************
@@ -6210,7 +6584,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RXFUNCADDR12_ADDR_M 0x0000007F  // Device Address.
+#define USB_RXFUNCADDR12_ADDR_M 0x0000007F  // Device Address
 #define USB_RXFUNCADDR12_ADDR_S 0
 
 //*****************************************************************************
@@ -6220,8 +6594,8 @@
 //
 //*****************************************************************************
 #define USB_RXHUBADDR12_MULTTRAN \
-                                0x00000080  // Multiple Translators.
-#define USB_RXHUBADDR12_ADDR_M  0x0000007F  // Hub Address.
+                                0x00000080  // Multiple Translators
+#define USB_RXHUBADDR12_ADDR_M  0x0000007F  // Hub Address
 #define USB_RXHUBADDR12_ADDR_S  0
 
 //*****************************************************************************
@@ -6230,7 +6604,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RXHUBPORT12_PORT_M  0x0000007F  // Hub Port.
+#define USB_RXHUBPORT12_PORT_M  0x0000007F  // Hub Port
 #define USB_RXHUBPORT12_PORT_S  0
 
 //*****************************************************************************
@@ -6239,7 +6613,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_TXFUNCADDR13_ADDR_M 0x0000007F  // Device Address.
+#define USB_TXFUNCADDR13_ADDR_M 0x0000007F  // Device Address
 #define USB_TXFUNCADDR13_ADDR_S 0
 
 //*****************************************************************************
@@ -6249,8 +6623,8 @@
 //
 //*****************************************************************************
 #define USB_TXHUBADDR13_MULTTRAN \
-                                0x00000080  // Multiple Translators.
-#define USB_TXHUBADDR13_ADDR_M  0x0000007F  // Hub Address.
+                                0x00000080  // Multiple Translators
+#define USB_TXHUBADDR13_ADDR_M  0x0000007F  // Hub Address
 #define USB_TXHUBADDR13_ADDR_S  0
 
 //*****************************************************************************
@@ -6259,7 +6633,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_TXHUBPORT13_PORT_M  0x0000007F  // Hub Port.
+#define USB_TXHUBPORT13_PORT_M  0x0000007F  // Hub Port
 #define USB_TXHUBPORT13_PORT_S  0
 
 //*****************************************************************************
@@ -6268,7 +6642,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RXFUNCADDR13_ADDR_M 0x0000007F  // Device Address.
+#define USB_RXFUNCADDR13_ADDR_M 0x0000007F  // Device Address
 #define USB_RXFUNCADDR13_ADDR_S 0
 
 //*****************************************************************************
@@ -6278,8 +6652,8 @@
 //
 //*****************************************************************************
 #define USB_RXHUBADDR13_MULTTRAN \
-                                0x00000080  // Multiple Translators.
-#define USB_RXHUBADDR13_ADDR_M  0x0000007F  // Hub Address.
+                                0x00000080  // Multiple Translators
+#define USB_RXHUBADDR13_ADDR_M  0x0000007F  // Hub Address
 #define USB_RXHUBADDR13_ADDR_S  0
 
 //*****************************************************************************
@@ -6288,7 +6662,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RXHUBPORT13_PORT_M  0x0000007F  // Hub Port.
+#define USB_RXHUBPORT13_PORT_M  0x0000007F  // Hub Port
 #define USB_RXHUBPORT13_PORT_S  0
 
 //*****************************************************************************
@@ -6297,7 +6671,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_TXFUNCADDR14_ADDR_M 0x0000007F  // Device Address.
+#define USB_TXFUNCADDR14_ADDR_M 0x0000007F  // Device Address
 #define USB_TXFUNCADDR14_ADDR_S 0
 
 //*****************************************************************************
@@ -6307,8 +6681,8 @@
 //
 //*****************************************************************************
 #define USB_TXHUBADDR14_MULTTRAN \
-                                0x00000080  // Multiple Translators.
-#define USB_TXHUBADDR14_ADDR_M  0x0000007F  // Hub Address.
+                                0x00000080  // Multiple Translators
+#define USB_TXHUBADDR14_ADDR_M  0x0000007F  // Hub Address
 #define USB_TXHUBADDR14_ADDR_S  0
 
 //*****************************************************************************
@@ -6317,7 +6691,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_TXHUBPORT14_PORT_M  0x0000007F  // Hub Port.
+#define USB_TXHUBPORT14_PORT_M  0x0000007F  // Hub Port
 #define USB_TXHUBPORT14_PORT_S  0
 
 //*****************************************************************************
@@ -6326,7 +6700,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RXFUNCADDR14_ADDR_M 0x0000007F  // Device Address.
+#define USB_RXFUNCADDR14_ADDR_M 0x0000007F  // Device Address
 #define USB_RXFUNCADDR14_ADDR_S 0
 
 //*****************************************************************************
@@ -6336,8 +6710,8 @@
 //
 //*****************************************************************************
 #define USB_RXHUBADDR14_MULTTRAN \
-                                0x00000080  // Multiple Translators.
-#define USB_RXHUBADDR14_ADDR_M  0x0000007F  // Hub Address.
+                                0x00000080  // Multiple Translators
+#define USB_RXHUBADDR14_ADDR_M  0x0000007F  // Hub Address
 #define USB_RXHUBADDR14_ADDR_S  0
 
 //*****************************************************************************
@@ -6346,7 +6720,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RXHUBPORT14_PORT_M  0x0000007F  // Hub Port.
+#define USB_RXHUBPORT14_PORT_M  0x0000007F  // Hub Port
 #define USB_RXHUBPORT14_PORT_S  0
 
 //*****************************************************************************
@@ -6355,7 +6729,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_TXFUNCADDR15_ADDR_M 0x0000007F  // Device Address.
+#define USB_TXFUNCADDR15_ADDR_M 0x0000007F  // Device Address
 #define USB_TXFUNCADDR15_ADDR_S 0
 
 //*****************************************************************************
@@ -6365,8 +6739,8 @@
 //
 //*****************************************************************************
 #define USB_TXHUBADDR15_MULTTRAN \
-                                0x00000080  // Multiple Translators.
-#define USB_TXHUBADDR15_ADDR_M  0x0000007F  // Hub Address.
+                                0x00000080  // Multiple Translators
+#define USB_TXHUBADDR15_ADDR_M  0x0000007F  // Hub Address
 #define USB_TXHUBADDR15_ADDR_S  0
 
 //*****************************************************************************
@@ -6375,7 +6749,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_TXHUBPORT15_PORT_M  0x0000007F  // Hub Port.
+#define USB_TXHUBPORT15_PORT_M  0x0000007F  // Hub Port
 #define USB_TXHUBPORT15_PORT_S  0
 
 //*****************************************************************************
@@ -6384,7 +6758,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RXFUNCADDR15_ADDR_M 0x0000007F  // Device Address.
+#define USB_RXFUNCADDR15_ADDR_M 0x0000007F  // Device Address
 #define USB_RXFUNCADDR15_ADDR_S 0
 
 //*****************************************************************************
@@ -6394,8 +6768,8 @@
 //
 //*****************************************************************************
 #define USB_RXHUBADDR15_MULTTRAN \
-                                0x00000080  // Multiple Translators.
-#define USB_RXHUBADDR15_ADDR_M  0x0000007F  // Hub Address.
+                                0x00000080  // Multiple Translators
+#define USB_RXHUBADDR15_ADDR_M  0x0000007F  // Hub Address
 #define USB_RXHUBADDR15_ADDR_S  0
 
 //*****************************************************************************
@@ -6404,7 +6778,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RXHUBPORT15_PORT_M  0x0000007F  // Hub Port.
+#define USB_RXHUBPORT15_PORT_M  0x0000007F  // Hub Port
 #define USB_RXHUBPORT15_PORT_S  0
 
 //*****************************************************************************
@@ -6412,35 +6786,35 @@
 // The following are defines for the bit fields in the USB_O_CSRL0 register.
 //
 //*****************************************************************************
-#define USB_CSRL0_NAKTO         0x00000080  // NAK Timeout.
-#define USB_CSRL0_SETENDC       0x00000080  // Setup End Clear.
-#define USB_CSRL0_STATUS        0x00000040  // Status Packet.
-#define USB_CSRL0_RXRDYC        0x00000040  // RXRDY Clear.
-#define USB_CSRL0_REQPKT        0x00000020  // Request Packet.
-#define USB_CSRL0_STALL         0x00000020  // Send Stall.
-#define USB_CSRL0_SETEND        0x00000010  // Setup End.
-#define USB_CSRL0_ERROR         0x00000010  // Error.
-#define USB_CSRL0_DATAEND       0x00000008  // Data End.
-#define USB_CSRL0_SETUP         0x00000008  // Setup Packet.
-#define USB_CSRL0_STALLED       0x00000004  // Endpoint Stalled.
-#define USB_CSRL0_TXRDY         0x00000002  // Transmit Packet Ready.
-#define USB_CSRL0_RXRDY         0x00000001  // Receive Packet Ready.
+#define USB_CSRL0_NAKTO         0x00000080  // NAK Timeout
+#define USB_CSRL0_SETENDC       0x00000080  // Setup End Clear
+#define USB_CSRL0_STATUS        0x00000040  // STATUS Packet
+#define USB_CSRL0_RXRDYC        0x00000040  // RXRDY Clear
+#define USB_CSRL0_REQPKT        0x00000020  // Request Packet
+#define USB_CSRL0_STALL         0x00000020  // Send Stall
+#define USB_CSRL0_SETEND        0x00000010  // Setup End
+#define USB_CSRL0_ERROR         0x00000010  // Error
+#define USB_CSRL0_DATAEND       0x00000008  // Data End
+#define USB_CSRL0_SETUP         0x00000008  // Setup Packet
+#define USB_CSRL0_STALLED       0x00000004  // Endpoint Stalled
+#define USB_CSRL0_TXRDY         0x00000002  // Transmit Packet Ready
+#define USB_CSRL0_RXRDY         0x00000001  // Receive Packet Ready
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_CSRH0 register.
 //
 //*****************************************************************************
-#define USB_CSRH0_DTWE          0x00000004  // Data Toggle Write Enable.
-#define USB_CSRH0_DT            0x00000002  // Data Toggle.
-#define USB_CSRH0_FLUSH         0x00000001  // Flush FIFO.
+#define USB_CSRH0_DTWE          0x00000004  // Data Toggle Write Enable
+#define USB_CSRH0_DT            0x00000002  // Data Toggle
+#define USB_CSRH0_FLUSH         0x00000001  // Flush FIFO
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_COUNT0 register.
 //
 //*****************************************************************************
-#define USB_COUNT0_COUNT_M      0x0000007F  // Count.
+#define USB_COUNT0_COUNT_M      0x0000007F  // FIFO Count
 #define USB_COUNT0_COUNT_S      0
 
 //*****************************************************************************
@@ -6448,7 +6822,7 @@
 // The following are defines for the bit fields in the USB_O_TYPE0 register.
 //
 //*****************************************************************************
-#define USB_TYPE0_SPEED_M       0x000000C0  // Operating Speed.
+#define USB_TYPE0_SPEED_M       0x000000C0  // Operating Speed
 #define USB_TYPE0_SPEED_FULL    0x00000080  // Full
 #define USB_TYPE0_SPEED_LOW     0x000000C0  // Low
 
@@ -6457,7 +6831,7 @@
 // The following are defines for the bit fields in the USB_O_NAKLMT register.
 //
 //*****************************************************************************
-#define USB_NAKLMT_NAKLMT_M     0x0000001F  // EP0 NAK Limit.
+#define USB_NAKLMT_NAKLMT_M     0x0000001F  // EP0 NAK Limit
 #define USB_NAKLMT_NAKLMT_S     0
 
 //*****************************************************************************
@@ -6465,7 +6839,7 @@
 // The following are defines for the bit fields in the USB_O_TXMAXP1 register.
 //
 //*****************************************************************************
-#define USB_TXMAXP1_MAXLOAD_M   0x000007FF  // Maximum Payload.
+#define USB_TXMAXP1_MAXLOAD_M   0x000007FF  // Maximum Payload
 #define USB_TXMAXP1_MAXLOAD_S   0
 
 //*****************************************************************************
@@ -6473,38 +6847,37 @@
 // The following are defines for the bit fields in the USB_O_TXCSRL1 register.
 //
 //*****************************************************************************
-#define USB_TXCSRL1_NAKTO       0x00000080  // NAK Timeout 
-#define USB_TXCSRL1_INCTX       0x00000080  // Incomplete Transmit.
-#define USB_TXCSRL1_CLRDT       0x00000040  // Clear Data Toggle.
-#define USB_TXCSRL1_STALLED     0x00000020  // Endpoint Stalled.
-#define USB_TXCSRL1_STALL       0x00000010  // Send Stall.
-#define USB_TXCSRL1_SETUP       0x00000010  // Setup Packet.
-#define USB_TXCSRL1_FLUSH       0x00000008  // Flush FIFO.
-#define USB_TXCSRL1_ERROR       0x00000004  // Error.
-#define USB_TXCSRL1_UNDRN       0x00000004  // Underrun.
-#define USB_TXCSRL1_FIFONE      0x00000002  // FIFO Not Empty.
-#define USB_TXCSRL1_TXRDY       0x00000001  // Transmit Packet Ready.
+#define USB_TXCSRL1_NAKTO       0x00000080  // NAK Timeout
+#define USB_TXCSRL1_CLRDT       0x00000040  // Clear Data Toggle
+#define USB_TXCSRL1_STALLED     0x00000020  // Endpoint Stalled
+#define USB_TXCSRL1_STALL       0x00000010  // Send STALL
+#define USB_TXCSRL1_SETUP       0x00000010  // Setup Packet
+#define USB_TXCSRL1_FLUSH       0x00000008  // Flush FIFO
+#define USB_TXCSRL1_ERROR       0x00000004  // Error
+#define USB_TXCSRL1_UNDRN       0x00000004  // Underrun
+#define USB_TXCSRL1_FIFONE      0x00000002  // FIFO Not Empty
+#define USB_TXCSRL1_TXRDY       0x00000001  // Transmit Packet Ready
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_TXCSRH1 register.
 //
 //*****************************************************************************
-#define USB_TXCSRH1_AUTOSET     0x00000080  // Auto Set.
-#define USB_TXCSRH1_ISO         0x00000040  // ISO.
-#define USB_TXCSRH1_MODE        0x00000020  // Mode.
-#define USB_TXCSRH1_DMAEN       0x00000010  // DMA Request Enable.
-#define USB_TXCSRH1_FDT         0x00000008  // Force Data Toggle.
-#define USB_TXCSRH1_DMAMOD      0x00000004  // DMA Request Mode.
-#define USB_TXCSRH1_DTWE        0x00000002  // Data Toggle Write Enable.
-#define USB_TXCSRH1_DT          0x00000001  // Data Toggle.
+#define USB_TXCSRH1_AUTOSET     0x00000080  // Auto Set
+#define USB_TXCSRH1_ISO         0x00000040  // Isochronous Transfers
+#define USB_TXCSRH1_MODE        0x00000020  // Mode
+#define USB_TXCSRH1_DMAEN       0x00000010  // DMA Request Enable
+#define USB_TXCSRH1_FDT         0x00000008  // Force Data Toggle
+#define USB_TXCSRH1_DMAMOD      0x00000004  // DMA Request Mode
+#define USB_TXCSRH1_DTWE        0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH1_DT          0x00000001  // Data Toggle
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXMAXP1 register.
 //
 //*****************************************************************************
-#define USB_RXMAXP1_MAXLOAD_M   0x000007FF  // Maximum Payload.
+#define USB_RXMAXP1_MAXLOAD_M   0x000007FF  // Maximum Payload
 #define USB_RXMAXP1_MAXLOAD_S   0
 
 //*****************************************************************************
@@ -6512,40 +6885,39 @@
 // The following are defines for the bit fields in the USB_O_RXCSRL1 register.
 //
 //*****************************************************************************
-#define USB_RXCSRL1_CLRDT       0x00000080  // Clear Data Toggle.
-#define USB_RXCSRL1_STALLED     0x00000040  // Endpoint Stalled.
-#define USB_RXCSRL1_STALL       0x00000020  // Send Stall.
-#define USB_RXCSRL1_REQPKT      0x00000020  // Request Packet.
-#define USB_RXCSRL1_FLUSH       0x00000010  // Flush FIFO.
-#define USB_RXCSRL1_DATAERR     0x00000008  // Data Error.
-#define USB_RXCSRL1_NAKTO       0x00000008  //  NAK Timeout.
-#define USB_RXCSRL1_OVER        0x00000004  // Overrun.
-#define USB_RXCSRL1_ERROR       0x00000004  // Error.
-#define USB_RXCSRL1_FULL        0x00000002  // FIFO Full.
-#define USB_RXCSRL1_RXRDY       0x00000001  // Receive Packet Ready.
+#define USB_RXCSRL1_CLRDT       0x00000080  // Clear Data Toggle
+#define USB_RXCSRL1_STALLED     0x00000040  // Endpoint Stalled
+#define USB_RXCSRL1_STALL       0x00000020  // Send STALL
+#define USB_RXCSRL1_REQPKT      0x00000020  // Request Packet
+#define USB_RXCSRL1_FLUSH       0x00000010  // Flush FIFO
+#define USB_RXCSRL1_DATAERR     0x00000008  // Data Error
+#define USB_RXCSRL1_NAKTO       0x00000008  // NAK Timeout
+#define USB_RXCSRL1_OVER        0x00000004  // Overrun
+#define USB_RXCSRL1_ERROR       0x00000004  // Error
+#define USB_RXCSRL1_FULL        0x00000002  // FIFO Full
+#define USB_RXCSRL1_RXRDY       0x00000001  // Receive Packet Ready
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXCSRH1 register.
 //
 //*****************************************************************************
-#define USB_RXCSRH1_AUTOCL      0x00000080  // Auto Clear.
-#define USB_RXCSRH1_AUTORQ      0x00000040  // Auto Request.
-#define USB_RXCSRH1_ISO         0x00000040  // ISO.
-#define USB_RXCSRH1_DMAEN       0x00000020  // DMA Request Enable.
-#define USB_RXCSRH1_DISNYET     0x00000010  // Disable NYET 
-#define USB_RXCSRH1_PIDERR      0x00000010  //  PID Error.
-#define USB_RXCSRH1_DMAMOD      0x00000008  // DMA Request Mode.
-#define USB_RXCSRH1_DTWE        0x00000004  // Data Toggle Write Enable.
-#define USB_RXCSRH1_DT          0x00000002  // Data Toggle.
-#define USB_RXCSRH1_INCRX       0x00000001  // Incomplete Receive.
+#define USB_RXCSRH1_AUTOCL      0x00000080  // Auto Clear
+#define USB_RXCSRH1_AUTORQ      0x00000040  // Auto Request
+#define USB_RXCSRH1_ISO         0x00000040  // Isochronous Transfers
+#define USB_RXCSRH1_DMAEN       0x00000020  // DMA Request Enable
+#define USB_RXCSRH1_DISNYET     0x00000010  // Disable NYET
+#define USB_RXCSRH1_PIDERR      0x00000010  // PID Error
+#define USB_RXCSRH1_DMAMOD      0x00000008  // DMA Request Mode
+#define USB_RXCSRH1_DTWE        0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH1_DT          0x00000002  // Data Toggle
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXCOUNT1 register.
 //
 //*****************************************************************************
-#define USB_RXCOUNT1_COUNT_M    0x00001FFF  // Receive Packet Count.
+#define USB_RXCOUNT1_COUNT_M    0x00001FFF  // Receive Packet Count
 #define USB_RXCOUNT1_COUNT_S    0
 
 //*****************************************************************************
@@ -6553,16 +6925,16 @@
 // The following are defines for the bit fields in the USB_O_TXTYPE1 register.
 //
 //*****************************************************************************
-#define USB_TXTYPE1_SPEED_M     0x000000C0  // Operating Speed.
+#define USB_TXTYPE1_SPEED_M     0x000000C0  // Operating Speed
 #define USB_TXTYPE1_SPEED_DFLT  0x00000000  // Default
 #define USB_TXTYPE1_SPEED_FULL  0x00000080  // Full
 #define USB_TXTYPE1_SPEED_LOW   0x000000C0  // Low
-#define USB_TXTYPE1_PROTO_M     0x00000030  // Protocol.
+#define USB_TXTYPE1_PROTO_M     0x00000030  // Protocol
 #define USB_TXTYPE1_PROTO_CTRL  0x00000000  // Control
 #define USB_TXTYPE1_PROTO_ISOC  0x00000010  // Isochronous
 #define USB_TXTYPE1_PROTO_BULK  0x00000020  // Bulk
 #define USB_TXTYPE1_PROTO_INT   0x00000030  // Interrupt
-#define USB_TXTYPE1_TEP_M       0x0000000F  // Target Endpoint Number.
+#define USB_TXTYPE1_TEP_M       0x0000000F  // Target Endpoint Number
 #define USB_TXTYPE1_TEP_S       0
 
 //*****************************************************************************
@@ -6572,9 +6944,9 @@
 //
 //*****************************************************************************
 #define USB_TXINTERVAL1_NAKLMT_M \
-                                0x000000FF  //  NAK Limit.
+                                0x000000FF  // NAK Limit
 #define USB_TXINTERVAL1_TXPOLL_M \
-                                0x000000FF  // TX Polling 
+                                0x000000FF  // TX Polling
 #define USB_TXINTERVAL1_TXPOLL_S \
                                 0
 #define USB_TXINTERVAL1_NAKLMT_S \
@@ -6585,16 +6957,16 @@
 // The following are defines for the bit fields in the USB_O_RXTYPE1 register.
 //
 //*****************************************************************************
-#define USB_RXTYPE1_SPEED_M     0x000000C0  // Operating Speed.
+#define USB_RXTYPE1_SPEED_M     0x000000C0  // Operating Speed
 #define USB_RXTYPE1_SPEED_DFLT  0x00000000  // Default
 #define USB_RXTYPE1_SPEED_FULL  0x00000080  // Full
 #define USB_RXTYPE1_SPEED_LOW   0x000000C0  // Low
-#define USB_RXTYPE1_PROTO_M     0x00000030  // Protocol.
+#define USB_RXTYPE1_PROTO_M     0x00000030  // Protocol
 #define USB_RXTYPE1_PROTO_CTRL  0x00000000  // Control
 #define USB_RXTYPE1_PROTO_ISOC  0x00000010  // Isochronous
 #define USB_RXTYPE1_PROTO_BULK  0x00000020  // Bulk
 #define USB_RXTYPE1_PROTO_INT   0x00000030  // Interrupt
-#define USB_RXTYPE1_TEP_M       0x0000000F  // Target Endpoint Number.
+#define USB_RXTYPE1_TEP_M       0x0000000F  // Target Endpoint Number
 #define USB_RXTYPE1_TEP_S       0
 
 //*****************************************************************************
@@ -6604,9 +6976,9 @@
 //
 //*****************************************************************************
 #define USB_RXINTERVAL1_TXPOLL_M \
-                                0x000000FF  // RX Polling 
+                                0x000000FF  // RX Polling
 #define USB_RXINTERVAL1_NAKLMT_M \
-                                0x000000FF  //  NAK Limit.
+                                0x000000FF  // NAK Limit
 #define USB_RXINTERVAL1_TXPOLL_S \
                                 0
 #define USB_RXINTERVAL1_NAKLMT_S \
@@ -6617,7 +6989,7 @@
 // The following are defines for the bit fields in the USB_O_TXMAXP2 register.
 //
 //*****************************************************************************
-#define USB_TXMAXP2_MAXLOAD_M   0x000007FF  // Maximum Payload.
+#define USB_TXMAXP2_MAXLOAD_M   0x000007FF  // Maximum Payload
 #define USB_TXMAXP2_MAXLOAD_S   0
 
 //*****************************************************************************
@@ -6625,38 +6997,37 @@
 // The following are defines for the bit fields in the USB_O_TXCSRL2 register.
 //
 //*****************************************************************************
-#define USB_TXCSRL2_INCTX       0x00000080  // Incomplete Transmit.
-#define USB_TXCSRL2_NAKTO       0x00000080  // NAK Timeout 
-#define USB_TXCSRL2_CLRDT       0x00000040  // Clear Data Toggle.
-#define USB_TXCSRL2_STALLED     0x00000020  // Endpoint Stalled.
-#define USB_TXCSRL2_SETUP       0x00000010  // Setup Packet.
-#define USB_TXCSRL2_STALL       0x00000010  // Send Stall.
-#define USB_TXCSRL2_FLUSH       0x00000008  // Flush FIFO.
-#define USB_TXCSRL2_ERROR       0x00000004  // Error.
-#define USB_TXCSRL2_UNDRN       0x00000004  // Underrun.
-#define USB_TXCSRL2_FIFONE      0x00000002  // FIFO Not Empty.
-#define USB_TXCSRL2_TXRDY       0x00000001  // Transmit Packet Ready.
+#define USB_TXCSRL2_NAKTO       0x00000080  // NAK Timeout
+#define USB_TXCSRL2_CLRDT       0x00000040  // Clear Data Toggle
+#define USB_TXCSRL2_STALLED     0x00000020  // Endpoint Stalled
+#define USB_TXCSRL2_SETUP       0x00000010  // Setup Packet
+#define USB_TXCSRL2_STALL       0x00000010  // Send STALL
+#define USB_TXCSRL2_FLUSH       0x00000008  // Flush FIFO
+#define USB_TXCSRL2_ERROR       0x00000004  // Error
+#define USB_TXCSRL2_UNDRN       0x00000004  // Underrun
+#define USB_TXCSRL2_FIFONE      0x00000002  // FIFO Not Empty
+#define USB_TXCSRL2_TXRDY       0x00000001  // Transmit Packet Ready
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_TXCSRH2 register.
 //
 //*****************************************************************************
-#define USB_TXCSRH2_AUTOSET     0x00000080  // Auto Set.
-#define USB_TXCSRH2_ISO         0x00000040  // ISO.
-#define USB_TXCSRH2_MODE        0x00000020  // Mode.
-#define USB_TXCSRH2_DMAEN       0x00000010  // DMA Request Enable.
-#define USB_TXCSRH2_FDT         0x00000008  // Force Data Toggle.
-#define USB_TXCSRH2_DMAMOD      0x00000004  // DMA Request Mode.
-#define USB_TXCSRH2_DTWE        0x00000002  // Data Toggle Write Enable.
-#define USB_TXCSRH2_DT          0x00000001  // Data Toggle.
+#define USB_TXCSRH2_AUTOSET     0x00000080  // Auto Set
+#define USB_TXCSRH2_ISO         0x00000040  // Isochronous Transfers
+#define USB_TXCSRH2_MODE        0x00000020  // Mode
+#define USB_TXCSRH2_DMAEN       0x00000010  // DMA Request Enable
+#define USB_TXCSRH2_FDT         0x00000008  // Force Data Toggle
+#define USB_TXCSRH2_DMAMOD      0x00000004  // DMA Request Mode
+#define USB_TXCSRH2_DTWE        0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH2_DT          0x00000001  // Data Toggle
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXMAXP2 register.
 //
 //*****************************************************************************
-#define USB_RXMAXP2_MAXLOAD_M   0x000007FF  // Maximum Payload.
+#define USB_RXMAXP2_MAXLOAD_M   0x000007FF  // Maximum Payload
 #define USB_RXMAXP2_MAXLOAD_S   0
 
 //*****************************************************************************
@@ -6664,40 +7035,39 @@
 // The following are defines for the bit fields in the USB_O_RXCSRL2 register.
 //
 //*****************************************************************************
-#define USB_RXCSRL2_CLRDT       0x00000080  // Clear Data Toggle.
-#define USB_RXCSRL2_STALLED     0x00000040  // Endpoint Stalled.
-#define USB_RXCSRL2_REQPKT      0x00000020  // Request Packet.
-#define USB_RXCSRL2_STALL       0x00000020  // Send Stall.
-#define USB_RXCSRL2_FLUSH       0x00000010  // Flush FIFO.
-#define USB_RXCSRL2_DATAERR     0x00000008  // Data Error.
-#define USB_RXCSRL2_NAKTO       0x00000008  //  NAK Timeout.
-#define USB_RXCSRL2_ERROR       0x00000004  // Error.
-#define USB_RXCSRL2_OVER        0x00000004  // Overrun.
-#define USB_RXCSRL2_FULL        0x00000002  // FIFO Full.
-#define USB_RXCSRL2_RXRDY       0x00000001  // Receive Packet Ready.
+#define USB_RXCSRL2_CLRDT       0x00000080  // Clear Data Toggle
+#define USB_RXCSRL2_STALLED     0x00000040  // Endpoint Stalled
+#define USB_RXCSRL2_REQPKT      0x00000020  // Request Packet
+#define USB_RXCSRL2_STALL       0x00000020  // Send STALL
+#define USB_RXCSRL2_FLUSH       0x00000010  // Flush FIFO
+#define USB_RXCSRL2_DATAERR     0x00000008  // Data Error
+#define USB_RXCSRL2_NAKTO       0x00000008  // NAK Timeout
+#define USB_RXCSRL2_ERROR       0x00000004  // Error
+#define USB_RXCSRL2_OVER        0x00000004  // Overrun
+#define USB_RXCSRL2_FULL        0x00000002  // FIFO Full
+#define USB_RXCSRL2_RXRDY       0x00000001  // Receive Packet Ready
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXCSRH2 register.
 //
 //*****************************************************************************
-#define USB_RXCSRH2_AUTOCL      0x00000080  // Auto Clear.
-#define USB_RXCSRH2_AUTORQ      0x00000040  // Auto Request.
-#define USB_RXCSRH2_ISO         0x00000040  // ISO.
-#define USB_RXCSRH2_DMAEN       0x00000020  // DMA Request Enable.
-#define USB_RXCSRH2_DISNYET     0x00000010  // Disable NYET 
-#define USB_RXCSRH2_PIDERR      0x00000010  //  PID Error.
-#define USB_RXCSRH2_DMAMOD      0x00000008  // DMA Request Mode.
-#define USB_RXCSRH2_DTWE        0x00000004  // Data Toggle Write Enable.
-#define USB_RXCSRH2_DT          0x00000002  // Data Toggle.
-#define USB_RXCSRH2_INCRX       0x00000001  // Incomplete Receive.
+#define USB_RXCSRH2_AUTOCL      0x00000080  // Auto Clear
+#define USB_RXCSRH2_AUTORQ      0x00000040  // Auto Request
+#define USB_RXCSRH2_ISO         0x00000040  // Isochronous Transfers
+#define USB_RXCSRH2_DMAEN       0x00000020  // DMA Request Enable
+#define USB_RXCSRH2_DISNYET     0x00000010  // Disable NYET
+#define USB_RXCSRH2_PIDERR      0x00000010  // PID Error
+#define USB_RXCSRH2_DMAMOD      0x00000008  // DMA Request Mode
+#define USB_RXCSRH2_DTWE        0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH2_DT          0x00000002  // Data Toggle
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXCOUNT2 register.
 //
 //*****************************************************************************
-#define USB_RXCOUNT2_COUNT_M    0x00001FFF  // Receive Packet Count.
+#define USB_RXCOUNT2_COUNT_M    0x00001FFF  // Receive Packet Count
 #define USB_RXCOUNT2_COUNT_S    0
 
 //*****************************************************************************
@@ -6705,16 +7075,16 @@
 // The following are defines for the bit fields in the USB_O_TXTYPE2 register.
 //
 //*****************************************************************************
-#define USB_TXTYPE2_SPEED_M     0x000000C0  // Operating Speed.
+#define USB_TXTYPE2_SPEED_M     0x000000C0  // Operating Speed
 #define USB_TXTYPE2_SPEED_DFLT  0x00000000  // Default
 #define USB_TXTYPE2_SPEED_FULL  0x00000080  // Full
 #define USB_TXTYPE2_SPEED_LOW   0x000000C0  // Low
-#define USB_TXTYPE2_PROTO_M     0x00000030  // Protocol.
+#define USB_TXTYPE2_PROTO_M     0x00000030  // Protocol
 #define USB_TXTYPE2_PROTO_CTRL  0x00000000  // Control
 #define USB_TXTYPE2_PROTO_ISOC  0x00000010  // Isochronous
 #define USB_TXTYPE2_PROTO_BULK  0x00000020  // Bulk
 #define USB_TXTYPE2_PROTO_INT   0x00000030  // Interrupt
-#define USB_TXTYPE2_TEP_M       0x0000000F  // Target Endpoint Number.
+#define USB_TXTYPE2_TEP_M       0x0000000F  // Target Endpoint Number
 #define USB_TXTYPE2_TEP_S       0
 
 //*****************************************************************************
@@ -6723,10 +7093,10 @@
 // register.
 //
 //*****************************************************************************
-#define USB_TXINTERVAL2_NAKLMT_M \
-                                0x000000FF  //  NAK Limit.
 #define USB_TXINTERVAL2_TXPOLL_M \
-                                0x000000FF  // TX Polling 
+                                0x000000FF  // TX Polling
+#define USB_TXINTERVAL2_NAKLMT_M \
+                                0x000000FF  // NAK Limit
 #define USB_TXINTERVAL2_NAKLMT_S \
                                 0
 #define USB_TXINTERVAL2_TXPOLL_S \
@@ -6737,16 +7107,16 @@
 // The following are defines for the bit fields in the USB_O_RXTYPE2 register.
 //
 //*****************************************************************************
-#define USB_RXTYPE2_SPEED_M     0x000000C0  // Operating Speed.
+#define USB_RXTYPE2_SPEED_M     0x000000C0  // Operating Speed
 #define USB_RXTYPE2_SPEED_DFLT  0x00000000  // Default
 #define USB_RXTYPE2_SPEED_FULL  0x00000080  // Full
 #define USB_RXTYPE2_SPEED_LOW   0x000000C0  // Low
-#define USB_RXTYPE2_PROTO_M     0x00000030  // Protocol.
+#define USB_RXTYPE2_PROTO_M     0x00000030  // Protocol
 #define USB_RXTYPE2_PROTO_CTRL  0x00000000  // Control
 #define USB_RXTYPE2_PROTO_ISOC  0x00000010  // Isochronous
 #define USB_RXTYPE2_PROTO_BULK  0x00000020  // Bulk
 #define USB_RXTYPE2_PROTO_INT   0x00000030  // Interrupt
-#define USB_RXTYPE2_TEP_M       0x0000000F  // Target Endpoint Number.
+#define USB_RXTYPE2_TEP_M       0x0000000F  // Target Endpoint Number
 #define USB_RXTYPE2_TEP_S       0
 
 //*****************************************************************************
@@ -6756,9 +7126,9 @@
 //
 //*****************************************************************************
 #define USB_RXINTERVAL2_TXPOLL_M \
-                                0x000000FF  // RX Polling 
+                                0x000000FF  // RX Polling
 #define USB_RXINTERVAL2_NAKLMT_M \
-                                0x000000FF  //  NAK Limit.
+                                0x000000FF  // NAK Limit
 #define USB_RXINTERVAL2_TXPOLL_S \
                                 0
 #define USB_RXINTERVAL2_NAKLMT_S \
@@ -6769,7 +7139,7 @@
 // The following are defines for the bit fields in the USB_O_TXMAXP3 register.
 //
 //*****************************************************************************
-#define USB_TXMAXP3_MAXLOAD_M   0x000007FF  // Maximum Payload.
+#define USB_TXMAXP3_MAXLOAD_M   0x000007FF  // Maximum Payload
 #define USB_TXMAXP3_MAXLOAD_S   0
 
 //*****************************************************************************
@@ -6777,38 +7147,37 @@
 // The following are defines for the bit fields in the USB_O_TXCSRL3 register.
 //
 //*****************************************************************************
-#define USB_TXCSRL3_INCTX       0x00000080  // Incomplete Transmit.
-#define USB_TXCSRL3_NAKTO       0x00000080  // NAK Timeout 
-#define USB_TXCSRL3_CLRDT       0x00000040  // Clear Data Toggle.
-#define USB_TXCSRL3_STALLED     0x00000020  // Endpoint Stalled.
-#define USB_TXCSRL3_SETUP       0x00000010  // Setup Packet.
-#define USB_TXCSRL3_STALL       0x00000010  // Send Stall.
-#define USB_TXCSRL3_FLUSH       0x00000008  // Flush FIFO.
-#define USB_TXCSRL3_ERROR       0x00000004  // Error.
-#define USB_TXCSRL3_UNDRN       0x00000004  // Underrun.
-#define USB_TXCSRL3_FIFONE      0x00000002  // FIFO Not Empty.
-#define USB_TXCSRL3_TXRDY       0x00000001  // Transmit Packet Ready.
+#define USB_TXCSRL3_NAKTO       0x00000080  // NAK Timeout
+#define USB_TXCSRL3_CLRDT       0x00000040  // Clear Data Toggle
+#define USB_TXCSRL3_STALLED     0x00000020  // Endpoint Stalled
+#define USB_TXCSRL3_SETUP       0x00000010  // Setup Packet
+#define USB_TXCSRL3_STALL       0x00000010  // Send STALL
+#define USB_TXCSRL3_FLUSH       0x00000008  // Flush FIFO
+#define USB_TXCSRL3_ERROR       0x00000004  // Error
+#define USB_TXCSRL3_UNDRN       0x00000004  // Underrun
+#define USB_TXCSRL3_FIFONE      0x00000002  // FIFO Not Empty
+#define USB_TXCSRL3_TXRDY       0x00000001  // Transmit Packet Ready
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_TXCSRH3 register.
 //
 //*****************************************************************************
-#define USB_TXCSRH3_AUTOSET     0x00000080  // Auto Set.
-#define USB_TXCSRH3_ISO         0x00000040  // ISO.
-#define USB_TXCSRH3_MODE        0x00000020  // Mode.
-#define USB_TXCSRH3_DMAEN       0x00000010  // DMA Request Enable.
-#define USB_TXCSRH3_FDT         0x00000008  // Force Data Toggle.
-#define USB_TXCSRH3_DMAMOD      0x00000004  // DMA Request Mode.
-#define USB_TXCSRH3_DTWE        0x00000002  // Data Toggle Write Enable.
-#define USB_TXCSRH3_DT          0x00000001  // Data Toggle.
+#define USB_TXCSRH3_AUTOSET     0x00000080  // Auto Set
+#define USB_TXCSRH3_ISO         0x00000040  // Isochronous Transfers
+#define USB_TXCSRH3_MODE        0x00000020  // Mode
+#define USB_TXCSRH3_DMAEN       0x00000010  // DMA Request Enable
+#define USB_TXCSRH3_FDT         0x00000008  // Force Data Toggle
+#define USB_TXCSRH3_DMAMOD      0x00000004  // DMA Request Mode
+#define USB_TXCSRH3_DTWE        0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH3_DT          0x00000001  // Data Toggle
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXMAXP3 register.
 //
 //*****************************************************************************
-#define USB_RXMAXP3_MAXLOAD_M   0x000007FF  // Maximum Payload.
+#define USB_RXMAXP3_MAXLOAD_M   0x000007FF  // Maximum Payload
 #define USB_RXMAXP3_MAXLOAD_S   0
 
 //*****************************************************************************
@@ -6816,40 +7185,39 @@
 // The following are defines for the bit fields in the USB_O_RXCSRL3 register.
 //
 //*****************************************************************************
-#define USB_RXCSRL3_CLRDT       0x00000080  // Clear Data Toggle.
-#define USB_RXCSRL3_STALLED     0x00000040  // Endpoint Stalled.
-#define USB_RXCSRL3_STALL       0x00000020  // Send Stall.
-#define USB_RXCSRL3_REQPKT      0x00000020  // Request Packet.
-#define USB_RXCSRL3_FLUSH       0x00000010  // Flush FIFO.
-#define USB_RXCSRL3_DATAERR     0x00000008  // Data Error.
-#define USB_RXCSRL3_NAKTO       0x00000008  //  NAK Timeout.
-#define USB_RXCSRL3_ERROR       0x00000004  // Error.
-#define USB_RXCSRL3_OVER        0x00000004  // Overrun.
-#define USB_RXCSRL3_FULL        0x00000002  // FIFO Full.
-#define USB_RXCSRL3_RXRDY       0x00000001  // Receive Packet Ready.
+#define USB_RXCSRL3_CLRDT       0x00000080  // Clear Data Toggle
+#define USB_RXCSRL3_STALLED     0x00000040  // Endpoint Stalled
+#define USB_RXCSRL3_STALL       0x00000020  // Send STALL
+#define USB_RXCSRL3_REQPKT      0x00000020  // Request Packet
+#define USB_RXCSRL3_FLUSH       0x00000010  // Flush FIFO
+#define USB_RXCSRL3_DATAERR     0x00000008  // Data Error
+#define USB_RXCSRL3_NAKTO       0x00000008  // NAK Timeout
+#define USB_RXCSRL3_ERROR       0x00000004  // Error
+#define USB_RXCSRL3_OVER        0x00000004  // Overrun
+#define USB_RXCSRL3_FULL        0x00000002  // FIFO Full
+#define USB_RXCSRL3_RXRDY       0x00000001  // Receive Packet Ready
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXCSRH3 register.
 //
 //*****************************************************************************
-#define USB_RXCSRH3_AUTOCL      0x00000080  // Auto Clear.
-#define USB_RXCSRH3_AUTORQ      0x00000040  // Auto Request.
-#define USB_RXCSRH3_ISO         0x00000040  // ISO.
-#define USB_RXCSRH3_DMAEN       0x00000020  // DMA Request Enable.
-#define USB_RXCSRH3_DISNYET     0x00000010  // Disable NYET 
-#define USB_RXCSRH3_PIDERR      0x00000010  //  PID Error.
-#define USB_RXCSRH3_DMAMOD      0x00000008  // DMA Request Mode.
-#define USB_RXCSRH3_DTWE        0x00000004  // Data Toggle Write Enable.
-#define USB_RXCSRH3_DT          0x00000002  // Data Toggle.
-#define USB_RXCSRH3_INCRX       0x00000001  // Incomplete Receive.
+#define USB_RXCSRH3_AUTOCL      0x00000080  // Auto Clear
+#define USB_RXCSRH3_AUTORQ      0x00000040  // Auto Request
+#define USB_RXCSRH3_ISO         0x00000040  // Isochronous Transfers
+#define USB_RXCSRH3_DMAEN       0x00000020  // DMA Request Enable
+#define USB_RXCSRH3_DISNYET     0x00000010  // Disable NYET
+#define USB_RXCSRH3_PIDERR      0x00000010  // PID Error
+#define USB_RXCSRH3_DMAMOD      0x00000008  // DMA Request Mode
+#define USB_RXCSRH3_DTWE        0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH3_DT          0x00000002  // Data Toggle
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXCOUNT3 register.
 //
 //*****************************************************************************
-#define USB_RXCOUNT3_COUNT_M    0x00001FFF  // Receive Packet Count.
+#define USB_RXCOUNT3_COUNT_M    0x00001FFF  // Receive Packet Count
 #define USB_RXCOUNT3_COUNT_S    0
 
 //*****************************************************************************
@@ -6857,16 +7225,16 @@
 // The following are defines for the bit fields in the USB_O_TXTYPE3 register.
 //
 //*****************************************************************************
-#define USB_TXTYPE3_SPEED_M     0x000000C0  // Operating Speed.
+#define USB_TXTYPE3_SPEED_M     0x000000C0  // Operating Speed
 #define USB_TXTYPE3_SPEED_DFLT  0x00000000  // Default
 #define USB_TXTYPE3_SPEED_FULL  0x00000080  // Full
 #define USB_TXTYPE3_SPEED_LOW   0x000000C0  // Low
-#define USB_TXTYPE3_PROTO_M     0x00000030  // Protocol.
+#define USB_TXTYPE3_PROTO_M     0x00000030  // Protocol
 #define USB_TXTYPE3_PROTO_CTRL  0x00000000  // Control
 #define USB_TXTYPE3_PROTO_ISOC  0x00000010  // Isochronous
 #define USB_TXTYPE3_PROTO_BULK  0x00000020  // Bulk
 #define USB_TXTYPE3_PROTO_INT   0x00000030  // Interrupt
-#define USB_TXTYPE3_TEP_M       0x0000000F  // Target Endpoint Number.
+#define USB_TXTYPE3_TEP_M       0x0000000F  // Target Endpoint Number
 #define USB_TXTYPE3_TEP_S       0
 
 //*****************************************************************************
@@ -6876,9 +7244,9 @@
 //
 //*****************************************************************************
 #define USB_TXINTERVAL3_TXPOLL_M \
-                                0x000000FF  // TX Polling 
+                                0x000000FF  // TX Polling
 #define USB_TXINTERVAL3_NAKLMT_M \
-                                0x000000FF  //  NAK Limit.
+                                0x000000FF  // NAK Limit
 #define USB_TXINTERVAL3_TXPOLL_S \
                                 0
 #define USB_TXINTERVAL3_NAKLMT_S \
@@ -6889,16 +7257,16 @@
 // The following are defines for the bit fields in the USB_O_RXTYPE3 register.
 //
 //*****************************************************************************
-#define USB_RXTYPE3_SPEED_M     0x000000C0  // Operating Speed.
+#define USB_RXTYPE3_SPEED_M     0x000000C0  // Operating Speed
 #define USB_RXTYPE3_SPEED_DFLT  0x00000000  // Default
 #define USB_RXTYPE3_SPEED_FULL  0x00000080  // Full
 #define USB_RXTYPE3_SPEED_LOW   0x000000C0  // Low
-#define USB_RXTYPE3_PROTO_M     0x00000030  // Protocol.
+#define USB_RXTYPE3_PROTO_M     0x00000030  // Protocol
 #define USB_RXTYPE3_PROTO_CTRL  0x00000000  // Control
 #define USB_RXTYPE3_PROTO_ISOC  0x00000010  // Isochronous
 #define USB_RXTYPE3_PROTO_BULK  0x00000020  // Bulk
 #define USB_RXTYPE3_PROTO_INT   0x00000030  // Interrupt
-#define USB_RXTYPE3_TEP_M       0x0000000F  // Target Endpoint Number.
+#define USB_RXTYPE3_TEP_M       0x0000000F  // Target Endpoint Number
 #define USB_RXTYPE3_TEP_S       0
 
 //*****************************************************************************
@@ -6908,9 +7276,9 @@
 //
 //*****************************************************************************
 #define USB_RXINTERVAL3_TXPOLL_M \
-                                0x000000FF  // RX Polling 
+                                0x000000FF  // RX Polling
 #define USB_RXINTERVAL3_NAKLMT_M \
-                                0x000000FF  //  NAK Limit.
+                                0x000000FF  // NAK Limit
 #define USB_RXINTERVAL3_TXPOLL_S \
                                 0
 #define USB_RXINTERVAL3_NAKLMT_S \
@@ -6921,7 +7289,7 @@
 // The following are defines for the bit fields in the USB_O_TXMAXP4 register.
 //
 //*****************************************************************************
-#define USB_TXMAXP4_MAXLOAD_M   0x000007FF  // Maximum Payload.
+#define USB_TXMAXP4_MAXLOAD_M   0x000007FF  // Maximum Payload
 #define USB_TXMAXP4_MAXLOAD_S   0
 
 //*****************************************************************************
@@ -6929,38 +7297,37 @@
 // The following are defines for the bit fields in the USB_O_TXCSRL4 register.
 //
 //*****************************************************************************
-#define USB_TXCSRL4_INCTX       0x00000080  // Incomplete Transmit.
-#define USB_TXCSRL4_NAKTO       0x00000080  // NAK Timeout 
-#define USB_TXCSRL4_CLRDT       0x00000040  // Clear Data Toggle.
-#define USB_TXCSRL4_STALLED     0x00000020  // Endpoint Stalled.
-#define USB_TXCSRL4_SETUP       0x00000010  // Setup Packet.
-#define USB_TXCSRL4_STALL       0x00000010  // Send Stall.
-#define USB_TXCSRL4_FLUSH       0x00000008  // Flush FIFO.
-#define USB_TXCSRL4_ERROR       0x00000004  // Error.
-#define USB_TXCSRL4_UNDRN       0x00000004  // Underrun.
-#define USB_TXCSRL4_FIFONE      0x00000002  // FIFO Not Empty.
-#define USB_TXCSRL4_TXRDY       0x00000001  // Transmit Packet Ready.
+#define USB_TXCSRL4_NAKTO       0x00000080  // NAK Timeout
+#define USB_TXCSRL4_CLRDT       0x00000040  // Clear Data Toggle
+#define USB_TXCSRL4_STALLED     0x00000020  // Endpoint Stalled
+#define USB_TXCSRL4_SETUP       0x00000010  // Setup Packet
+#define USB_TXCSRL4_STALL       0x00000010  // Send STALL
+#define USB_TXCSRL4_FLUSH       0x00000008  // Flush FIFO
+#define USB_TXCSRL4_ERROR       0x00000004  // Error
+#define USB_TXCSRL4_UNDRN       0x00000004  // Underrun
+#define USB_TXCSRL4_FIFONE      0x00000002  // FIFO Not Empty
+#define USB_TXCSRL4_TXRDY       0x00000001  // Transmit Packet Ready
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_TXCSRH4 register.
 //
 //*****************************************************************************
-#define USB_TXCSRH4_AUTOSET     0x00000080  // Auto Set.
-#define USB_TXCSRH4_ISO         0x00000040  // ISO.
-#define USB_TXCSRH4_MODE        0x00000020  // Mode.
-#define USB_TXCSRH4_DMAEN       0x00000010  // DMA Request Enable.
-#define USB_TXCSRH4_FDT         0x00000008  // Force Data Toggle.
-#define USB_TXCSRH4_DMAMOD      0x00000004  // DMA Request Mode.
-#define USB_TXCSRH4_DTWE        0x00000002  // Data Toggle Write Enable.
-#define USB_TXCSRH4_DT          0x00000001  // Data Toggle.
+#define USB_TXCSRH4_AUTOSET     0x00000080  // Auto Set
+#define USB_TXCSRH4_ISO         0x00000040  // Isochronous Transfers
+#define USB_TXCSRH4_MODE        0x00000020  // Mode
+#define USB_TXCSRH4_DMAEN       0x00000010  // DMA Request Enable
+#define USB_TXCSRH4_FDT         0x00000008  // Force Data Toggle
+#define USB_TXCSRH4_DMAMOD      0x00000004  // DMA Request Mode
+#define USB_TXCSRH4_DTWE        0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH4_DT          0x00000001  // Data Toggle
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXMAXP4 register.
 //
 //*****************************************************************************
-#define USB_RXMAXP4_MAXLOAD_M   0x000007FF  // Maximum Payload.
+#define USB_RXMAXP4_MAXLOAD_M   0x000007FF  // Maximum Payload
 #define USB_RXMAXP4_MAXLOAD_S   0
 
 //*****************************************************************************
@@ -6968,40 +7335,39 @@
 // The following are defines for the bit fields in the USB_O_RXCSRL4 register.
 //
 //*****************************************************************************
-#define USB_RXCSRL4_CLRDT       0x00000080  // Clear Data Toggle.
-#define USB_RXCSRL4_STALLED     0x00000040  // Endpoint Stalled.
-#define USB_RXCSRL4_STALL       0x00000020  // Send Stall.
-#define USB_RXCSRL4_REQPKT      0x00000020  // Request Packet.
-#define USB_RXCSRL4_FLUSH       0x00000010  // Flush FIFO.
-#define USB_RXCSRL4_NAKTO       0x00000008  //  NAK Timeout.
-#define USB_RXCSRL4_DATAERR     0x00000008  // Data Error.
-#define USB_RXCSRL4_OVER        0x00000004  // Overrun.
-#define USB_RXCSRL4_ERROR       0x00000004  // Error.
-#define USB_RXCSRL4_FULL        0x00000002  // FIFO Full.
-#define USB_RXCSRL4_RXRDY       0x00000001  // Receive Packet Ready.
+#define USB_RXCSRL4_CLRDT       0x00000080  // Clear Data Toggle
+#define USB_RXCSRL4_STALLED     0x00000040  // Endpoint Stalled
+#define USB_RXCSRL4_STALL       0x00000020  // Send STALL
+#define USB_RXCSRL4_REQPKT      0x00000020  // Request Packet
+#define USB_RXCSRL4_FLUSH       0x00000010  // Flush FIFO
+#define USB_RXCSRL4_NAKTO       0x00000008  // NAK Timeout
+#define USB_RXCSRL4_DATAERR     0x00000008  // Data Error
+#define USB_RXCSRL4_OVER        0x00000004  // Overrun
+#define USB_RXCSRL4_ERROR       0x00000004  // Error
+#define USB_RXCSRL4_FULL        0x00000002  // FIFO Full
+#define USB_RXCSRL4_RXRDY       0x00000001  // Receive Packet Ready
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXCSRH4 register.
 //
 //*****************************************************************************
-#define USB_RXCSRH4_AUTOCL      0x00000080  // Auto Clear.
-#define USB_RXCSRH4_AUTORQ      0x00000040  // Auto Request.
-#define USB_RXCSRH4_ISO         0x00000040  // ISO.
-#define USB_RXCSRH4_DMAEN       0x00000020  // DMA Request Enable.
-#define USB_RXCSRH4_DISNYET     0x00000010  // Disable NYET 
-#define USB_RXCSRH4_PIDERR      0x00000010  //  PID Error.
-#define USB_RXCSRH4_DMAMOD      0x00000008  // DMA Request Mode.
-#define USB_RXCSRH4_DTWE        0x00000004  // Data Toggle Write Enable.
-#define USB_RXCSRH4_DT          0x00000002  // Data Toggle.
-#define USB_RXCSRH4_INCRX       0x00000001  // Incomplete Receive.
+#define USB_RXCSRH4_AUTOCL      0x00000080  // Auto Clear
+#define USB_RXCSRH4_AUTORQ      0x00000040  // Auto Request
+#define USB_RXCSRH4_ISO         0x00000040  // Isochronous Transfers
+#define USB_RXCSRH4_DMAEN       0x00000020  // DMA Request Enable
+#define USB_RXCSRH4_DISNYET     0x00000010  // Disable NYET
+#define USB_RXCSRH4_PIDERR      0x00000010  // PID Error
+#define USB_RXCSRH4_DMAMOD      0x00000008  // DMA Request Mode
+#define USB_RXCSRH4_DTWE        0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH4_DT          0x00000002  // Data Toggle
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXCOUNT4 register.
 //
 //*****************************************************************************
-#define USB_RXCOUNT4_COUNT_M    0x00001FFF  // Receive Packet Count.
+#define USB_RXCOUNT4_COUNT_M    0x00001FFF  // Receive Packet Count
 #define USB_RXCOUNT4_COUNT_S    0
 
 //*****************************************************************************
@@ -7009,16 +7375,16 @@
 // The following are defines for the bit fields in the USB_O_TXTYPE4 register.
 //
 //*****************************************************************************
-#define USB_TXTYPE4_SPEED_M     0x000000C0  // Operating Speed.
+#define USB_TXTYPE4_SPEED_M     0x000000C0  // Operating Speed
 #define USB_TXTYPE4_SPEED_DFLT  0x00000000  // Default
 #define USB_TXTYPE4_SPEED_FULL  0x00000080  // Full
 #define USB_TXTYPE4_SPEED_LOW   0x000000C0  // Low
-#define USB_TXTYPE4_PROTO_M     0x00000030  // Protocol.
+#define USB_TXTYPE4_PROTO_M     0x00000030  // Protocol
 #define USB_TXTYPE4_PROTO_CTRL  0x00000000  // Control
 #define USB_TXTYPE4_PROTO_ISOC  0x00000010  // Isochronous
 #define USB_TXTYPE4_PROTO_BULK  0x00000020  // Bulk
 #define USB_TXTYPE4_PROTO_INT   0x00000030  // Interrupt
-#define USB_TXTYPE4_TEP_M       0x0000000F  // Target Endpoint Number.
+#define USB_TXTYPE4_TEP_M       0x0000000F  // Target Endpoint Number
 #define USB_TXTYPE4_TEP_S       0
 
 //*****************************************************************************
@@ -7027,10 +7393,10 @@
 // register.
 //
 //*****************************************************************************
-#define USB_TXINTERVAL4_NAKLMT_M \
-                                0x000000FF  //  NAK Limit.
 #define USB_TXINTERVAL4_TXPOLL_M \
-                                0x000000FF  // TX Polling 
+                                0x000000FF  // TX Polling
+#define USB_TXINTERVAL4_NAKLMT_M \
+                                0x000000FF  // NAK Limit
 #define USB_TXINTERVAL4_NAKLMT_S \
                                 0
 #define USB_TXINTERVAL4_TXPOLL_S \
@@ -7041,16 +7407,16 @@
 // The following are defines for the bit fields in the USB_O_RXTYPE4 register.
 //
 //*****************************************************************************
-#define USB_RXTYPE4_SPEED_M     0x000000C0  // Operating Speed.
+#define USB_RXTYPE4_SPEED_M     0x000000C0  // Operating Speed
 #define USB_RXTYPE4_SPEED_DFLT  0x00000000  // Default
 #define USB_RXTYPE4_SPEED_FULL  0x00000080  // Full
 #define USB_RXTYPE4_SPEED_LOW   0x000000C0  // Low
-#define USB_RXTYPE4_PROTO_M     0x00000030  // Protocol.
+#define USB_RXTYPE4_PROTO_M     0x00000030  // Protocol
 #define USB_RXTYPE4_PROTO_CTRL  0x00000000  // Control
 #define USB_RXTYPE4_PROTO_ISOC  0x00000010  // Isochronous
 #define USB_RXTYPE4_PROTO_BULK  0x00000020  // Bulk
 #define USB_RXTYPE4_PROTO_INT   0x00000030  // Interrupt
-#define USB_RXTYPE4_TEP_M       0x0000000F  // Target Endpoint Number.
+#define USB_RXTYPE4_TEP_M       0x0000000F  // Target Endpoint Number
 #define USB_RXTYPE4_TEP_S       0
 
 //*****************************************************************************
@@ -7060,9 +7426,9 @@
 //
 //*****************************************************************************
 #define USB_RXINTERVAL4_TXPOLL_M \
-                                0x000000FF  // RX Polling 
+                                0x000000FF  // RX Polling
 #define USB_RXINTERVAL4_NAKLMT_M \
-                                0x000000FF  //  NAK Limit.
+                                0x000000FF  // NAK Limit
 #define USB_RXINTERVAL4_NAKLMT_S \
                                 0
 #define USB_RXINTERVAL4_TXPOLL_S \
@@ -7073,7 +7439,7 @@
 // The following are defines for the bit fields in the USB_O_TXMAXP5 register.
 //
 //*****************************************************************************
-#define USB_TXMAXP5_MAXLOAD_M   0x000007FF  // Maximum Payload.
+#define USB_TXMAXP5_MAXLOAD_M   0x000007FF  // Maximum Payload
 #define USB_TXMAXP5_MAXLOAD_S   0
 
 //*****************************************************************************
@@ -7081,38 +7447,37 @@
 // The following are defines for the bit fields in the USB_O_TXCSRL5 register.
 //
 //*****************************************************************************
-#define USB_TXCSRL5_NAKTO       0x00000080  // NAK Timeout 
-#define USB_TXCSRL5_INCTX       0x00000080  // Incomplete Transmit.
-#define USB_TXCSRL5_CLRDT       0x00000040  // Clear Data Toggle.
-#define USB_TXCSRL5_STALLED     0x00000020  // Endpoint Stalled.
-#define USB_TXCSRL5_SETUP       0x00000010  // Setup Packet.
-#define USB_TXCSRL5_STALL       0x00000010  // Send Stall.
-#define USB_TXCSRL5_FLUSH       0x00000008  // Flush FIFO.
-#define USB_TXCSRL5_ERROR       0x00000004  // Error.
-#define USB_TXCSRL5_UNDRN       0x00000004  // Underrun.
-#define USB_TXCSRL5_FIFONE      0x00000002  // FIFO Not Empty.
-#define USB_TXCSRL5_TXRDY       0x00000001  // Transmit Packet Ready.
+#define USB_TXCSRL5_NAKTO       0x00000080  // NAK Timeout
+#define USB_TXCSRL5_CLRDT       0x00000040  // Clear Data Toggle
+#define USB_TXCSRL5_STALLED     0x00000020  // Endpoint Stalled
+#define USB_TXCSRL5_SETUP       0x00000010  // Setup Packet
+#define USB_TXCSRL5_STALL       0x00000010  // Send STALL
+#define USB_TXCSRL5_FLUSH       0x00000008  // Flush FIFO
+#define USB_TXCSRL5_ERROR       0x00000004  // Error
+#define USB_TXCSRL5_UNDRN       0x00000004  // Underrun
+#define USB_TXCSRL5_FIFONE      0x00000002  // FIFO Not Empty
+#define USB_TXCSRL5_TXRDY       0x00000001  // Transmit Packet Ready
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_TXCSRH5 register.
 //
 //*****************************************************************************
-#define USB_TXCSRH5_AUTOSET     0x00000080  // Auto Set.
-#define USB_TXCSRH5_ISO         0x00000040  // ISO.
-#define USB_TXCSRH5_MODE        0x00000020  // Mode.
-#define USB_TXCSRH5_DMAEN       0x00000010  // DMA Request Enable.
-#define USB_TXCSRH5_FDT         0x00000008  // Force Data Toggle.
-#define USB_TXCSRH5_DMAMOD      0x00000004  // DMA Request Mode.
-#define USB_TXCSRH5_DTWE        0x00000002  // Data Toggle Write Enable.
-#define USB_TXCSRH5_DT          0x00000001  // Data Toggle.
+#define USB_TXCSRH5_AUTOSET     0x00000080  // Auto Set
+#define USB_TXCSRH5_ISO         0x00000040  // Isochronous Transfers
+#define USB_TXCSRH5_MODE        0x00000020  // Mode
+#define USB_TXCSRH5_DMAEN       0x00000010  // DMA Request Enable
+#define USB_TXCSRH5_FDT         0x00000008  // Force Data Toggle
+#define USB_TXCSRH5_DMAMOD      0x00000004  // DMA Request Mode
+#define USB_TXCSRH5_DTWE        0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH5_DT          0x00000001  // Data Toggle
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXMAXP5 register.
 //
 //*****************************************************************************
-#define USB_RXMAXP5_MAXLOAD_M   0x000007FF  // Maximum Payload.
+#define USB_RXMAXP5_MAXLOAD_M   0x000007FF  // Maximum Payload
 #define USB_RXMAXP5_MAXLOAD_S   0
 
 //*****************************************************************************
@@ -7120,40 +7485,39 @@
 // The following are defines for the bit fields in the USB_O_RXCSRL5 register.
 //
 //*****************************************************************************
-#define USB_RXCSRL5_CLRDT       0x00000080  // Clear Data Toggle.
-#define USB_RXCSRL5_STALLED     0x00000040  // Endpoint Stalled.
-#define USB_RXCSRL5_STALL       0x00000020  // Send Stall.
-#define USB_RXCSRL5_REQPKT      0x00000020  // Request Packet.
-#define USB_RXCSRL5_FLUSH       0x00000010  // Flush FIFO.
-#define USB_RXCSRL5_NAKTO       0x00000008  //  NAK Timeout.
-#define USB_RXCSRL5_DATAERR     0x00000008  // Data Error.
-#define USB_RXCSRL5_ERROR       0x00000004  // Error.
-#define USB_RXCSRL5_OVER        0x00000004  // Overrun.
-#define USB_RXCSRL5_FULL        0x00000002  // FIFO Full.
-#define USB_RXCSRL5_RXRDY       0x00000001  // Receive Packet Ready.
+#define USB_RXCSRL5_CLRDT       0x00000080  // Clear Data Toggle
+#define USB_RXCSRL5_STALLED     0x00000040  // Endpoint Stalled
+#define USB_RXCSRL5_STALL       0x00000020  // Send STALL
+#define USB_RXCSRL5_REQPKT      0x00000020  // Request Packet
+#define USB_RXCSRL5_FLUSH       0x00000010  // Flush FIFO
+#define USB_RXCSRL5_NAKTO       0x00000008  // NAK Timeout
+#define USB_RXCSRL5_DATAERR     0x00000008  // Data Error
+#define USB_RXCSRL5_ERROR       0x00000004  // Error
+#define USB_RXCSRL5_OVER        0x00000004  // Overrun
+#define USB_RXCSRL5_FULL        0x00000002  // FIFO Full
+#define USB_RXCSRL5_RXRDY       0x00000001  // Receive Packet Ready
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXCSRH5 register.
 //
 //*****************************************************************************
-#define USB_RXCSRH5_AUTOCL      0x00000080  // Auto Clear.
-#define USB_RXCSRH5_AUTORQ      0x00000040  // Auto Request.
-#define USB_RXCSRH5_ISO         0x00000040  // ISO.
-#define USB_RXCSRH5_DMAEN       0x00000020  // DMA Request Enable.
-#define USB_RXCSRH5_DISNYET     0x00000010  // Disable NYET 
-#define USB_RXCSRH5_PIDERR      0x00000010  //  PID Error.
-#define USB_RXCSRH5_DMAMOD      0x00000008  // DMA Request Mode.
-#define USB_RXCSRH5_DTWE        0x00000004  // Data Toggle Write Enable.
-#define USB_RXCSRH5_DT          0x00000002  // Data Toggle.
-#define USB_RXCSRH5_INCRX       0x00000001  // Incomplete Receive.
+#define USB_RXCSRH5_AUTOCL      0x00000080  // Auto Clear
+#define USB_RXCSRH5_AUTORQ      0x00000040  // Auto Request
+#define USB_RXCSRH5_ISO         0x00000040  // Isochronous Transfers
+#define USB_RXCSRH5_DMAEN       0x00000020  // DMA Request Enable
+#define USB_RXCSRH5_DISNYET     0x00000010  // Disable NYET
+#define USB_RXCSRH5_PIDERR      0x00000010  // PID Error
+#define USB_RXCSRH5_DMAMOD      0x00000008  // DMA Request Mode
+#define USB_RXCSRH5_DTWE        0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH5_DT          0x00000002  // Data Toggle
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXCOUNT5 register.
 //
 //*****************************************************************************
-#define USB_RXCOUNT5_COUNT_M    0x00001FFF  // Receive Packet Count.
+#define USB_RXCOUNT5_COUNT_M    0x00001FFF  // Receive Packet Count
 #define USB_RXCOUNT5_COUNT_S    0
 
 //*****************************************************************************
@@ -7161,16 +7525,16 @@
 // The following are defines for the bit fields in the USB_O_TXTYPE5 register.
 //
 //*****************************************************************************
-#define USB_TXTYPE5_SPEED_M     0x000000C0  // Operating Speed.
+#define USB_TXTYPE5_SPEED_M     0x000000C0  // Operating Speed
 #define USB_TXTYPE5_SPEED_DFLT  0x00000000  // Default
 #define USB_TXTYPE5_SPEED_FULL  0x00000080  // Full
 #define USB_TXTYPE5_SPEED_LOW   0x000000C0  // Low
-#define USB_TXTYPE5_PROTO_M     0x00000030  // Protocol.
+#define USB_TXTYPE5_PROTO_M     0x00000030  // Protocol
 #define USB_TXTYPE5_PROTO_CTRL  0x00000000  // Control
 #define USB_TXTYPE5_PROTO_ISOC  0x00000010  // Isochronous
 #define USB_TXTYPE5_PROTO_BULK  0x00000020  // Bulk
 #define USB_TXTYPE5_PROTO_INT   0x00000030  // Interrupt
-#define USB_TXTYPE5_TEP_M       0x0000000F  // Target Endpoint Number.
+#define USB_TXTYPE5_TEP_M       0x0000000F  // Target Endpoint Number
 #define USB_TXTYPE5_TEP_S       0
 
 //*****************************************************************************
@@ -7180,9 +7544,9 @@
 //
 //*****************************************************************************
 #define USB_TXINTERVAL5_TXPOLL_M \
-                                0x000000FF  // TX Polling 
+                                0x000000FF  // TX Polling
 #define USB_TXINTERVAL5_NAKLMT_M \
-                                0x000000FF  //  NAK Limit.
+                                0x000000FF  // NAK Limit
 #define USB_TXINTERVAL5_NAKLMT_S \
                                 0
 #define USB_TXINTERVAL5_TXPOLL_S \
@@ -7193,16 +7557,16 @@
 // The following are defines for the bit fields in the USB_O_RXTYPE5 register.
 //
 //*****************************************************************************
-#define USB_RXTYPE5_SPEED_M     0x000000C0  // Operating Speed.
+#define USB_RXTYPE5_SPEED_M     0x000000C0  // Operating Speed
 #define USB_RXTYPE5_SPEED_DFLT  0x00000000  // Default
 #define USB_RXTYPE5_SPEED_FULL  0x00000080  // Full
 #define USB_RXTYPE5_SPEED_LOW   0x000000C0  // Low
-#define USB_RXTYPE5_PROTO_M     0x00000030  // Protocol.
+#define USB_RXTYPE5_PROTO_M     0x00000030  // Protocol
 #define USB_RXTYPE5_PROTO_CTRL  0x00000000  // Control
 #define USB_RXTYPE5_PROTO_ISOC  0x00000010  // Isochronous
 #define USB_RXTYPE5_PROTO_BULK  0x00000020  // Bulk
 #define USB_RXTYPE5_PROTO_INT   0x00000030  // Interrupt
-#define USB_RXTYPE5_TEP_M       0x0000000F  // Target Endpoint Number.
+#define USB_RXTYPE5_TEP_M       0x0000000F  // Target Endpoint Number
 #define USB_RXTYPE5_TEP_S       0
 
 //*****************************************************************************
@@ -7212,9 +7576,9 @@
 //
 //*****************************************************************************
 #define USB_RXINTERVAL5_TXPOLL_M \
-                                0x000000FF  // RX Polling 
+                                0x000000FF  // RX Polling
 #define USB_RXINTERVAL5_NAKLMT_M \
-                                0x000000FF  //  NAK Limit.
+                                0x000000FF  // NAK Limit
 #define USB_RXINTERVAL5_TXPOLL_S \
                                 0
 #define USB_RXINTERVAL5_NAKLMT_S \
@@ -7225,7 +7589,7 @@
 // The following are defines for the bit fields in the USB_O_TXMAXP6 register.
 //
 //*****************************************************************************
-#define USB_TXMAXP6_MAXLOAD_M   0x000007FF  // Maximum Payload.
+#define USB_TXMAXP6_MAXLOAD_M   0x000007FF  // Maximum Payload
 #define USB_TXMAXP6_MAXLOAD_S   0
 
 //*****************************************************************************
@@ -7233,38 +7597,37 @@
 // The following are defines for the bit fields in the USB_O_TXCSRL6 register.
 //
 //*****************************************************************************
-#define USB_TXCSRL6_INCTX       0x00000080  // Incomplete Transmit.
-#define USB_TXCSRL6_NAKTO       0x00000080  // NAK Timeout 
-#define USB_TXCSRL6_CLRDT       0x00000040  // Clear Data Toggle.
-#define USB_TXCSRL6_STALLED     0x00000020  // Endpoint Stalled.
-#define USB_TXCSRL6_STALL       0x00000010  // Send Stall.
-#define USB_TXCSRL6_SETUP       0x00000010  // Setup Packet.
-#define USB_TXCSRL6_FLUSH       0x00000008  // Flush FIFO.
-#define USB_TXCSRL6_ERROR       0x00000004  // Error.
-#define USB_TXCSRL6_UNDRN       0x00000004  // Underrun.
-#define USB_TXCSRL6_FIFONE      0x00000002  // FIFO Not Empty.
-#define USB_TXCSRL6_TXRDY       0x00000001  // Transmit Packet Ready.
+#define USB_TXCSRL6_NAKTO       0x00000080  // NAK Timeout
+#define USB_TXCSRL6_CLRDT       0x00000040  // Clear Data Toggle
+#define USB_TXCSRL6_STALLED     0x00000020  // Endpoint Stalled
+#define USB_TXCSRL6_STALL       0x00000010  // Send STALL
+#define USB_TXCSRL6_SETUP       0x00000010  // Setup Packet
+#define USB_TXCSRL6_FLUSH       0x00000008  // Flush FIFO
+#define USB_TXCSRL6_ERROR       0x00000004  // Error
+#define USB_TXCSRL6_UNDRN       0x00000004  // Underrun
+#define USB_TXCSRL6_FIFONE      0x00000002  // FIFO Not Empty
+#define USB_TXCSRL6_TXRDY       0x00000001  // Transmit Packet Ready
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_TXCSRH6 register.
 //
 //*****************************************************************************
-#define USB_TXCSRH6_AUTOSET     0x00000080  // Auto Set.
-#define USB_TXCSRH6_ISO         0x00000040  // ISO.
-#define USB_TXCSRH6_MODE        0x00000020  // Mode.
-#define USB_TXCSRH6_DMAEN       0x00000010  // DMA Request Enable.
-#define USB_TXCSRH6_FDT         0x00000008  // Force Data Toggle.
-#define USB_TXCSRH6_DMAMOD      0x00000004  // DMA Request Mode.
-#define USB_TXCSRH6_DTWE        0x00000002  // Data Toggle Write Enable.
-#define USB_TXCSRH6_DT          0x00000001  // Data Toggle.
+#define USB_TXCSRH6_AUTOSET     0x00000080  // Auto Set
+#define USB_TXCSRH6_ISO         0x00000040  // Isochronous Transfers
+#define USB_TXCSRH6_MODE        0x00000020  // Mode
+#define USB_TXCSRH6_DMAEN       0x00000010  // DMA Request Enable
+#define USB_TXCSRH6_FDT         0x00000008  // Force Data Toggle
+#define USB_TXCSRH6_DMAMOD      0x00000004  // DMA Request Mode
+#define USB_TXCSRH6_DTWE        0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH6_DT          0x00000001  // Data Toggle
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXMAXP6 register.
 //
 //*****************************************************************************
-#define USB_RXMAXP6_MAXLOAD_M   0x000007FF  // Maximum Payload.
+#define USB_RXMAXP6_MAXLOAD_M   0x000007FF  // Maximum Payload
 #define USB_RXMAXP6_MAXLOAD_S   0
 
 //*****************************************************************************
@@ -7272,40 +7635,39 @@
 // The following are defines for the bit fields in the USB_O_RXCSRL6 register.
 //
 //*****************************************************************************
-#define USB_RXCSRL6_CLRDT       0x00000080  // Clear Data Toggle.
-#define USB_RXCSRL6_STALLED     0x00000040  // Endpoint Stalled.
-#define USB_RXCSRL6_REQPKT      0x00000020  // Request Packet.
-#define USB_RXCSRL6_STALL       0x00000020  // Send Stall.
-#define USB_RXCSRL6_FLUSH       0x00000010  // Flush FIFO.
-#define USB_RXCSRL6_NAKTO       0x00000008  //  NAK Timeout.
-#define USB_RXCSRL6_DATAERR     0x00000008  // Data Error.
-#define USB_RXCSRL6_ERROR       0x00000004  // Error.
-#define USB_RXCSRL6_OVER        0x00000004  // Overrun.
-#define USB_RXCSRL6_FULL        0x00000002  // FIFO Full.
-#define USB_RXCSRL6_RXRDY       0x00000001  // Receive Packet Ready.
+#define USB_RXCSRL6_CLRDT       0x00000080  // Clear Data Toggle
+#define USB_RXCSRL6_STALLED     0x00000040  // Endpoint Stalled
+#define USB_RXCSRL6_REQPKT      0x00000020  // Request Packet
+#define USB_RXCSRL6_STALL       0x00000020  // Send STALL
+#define USB_RXCSRL6_FLUSH       0x00000010  // Flush FIFO
+#define USB_RXCSRL6_NAKTO       0x00000008  // NAK Timeout
+#define USB_RXCSRL6_DATAERR     0x00000008  // Data Error
+#define USB_RXCSRL6_ERROR       0x00000004  // Error
+#define USB_RXCSRL6_OVER        0x00000004  // Overrun
+#define USB_RXCSRL6_FULL        0x00000002  // FIFO Full
+#define USB_RXCSRL6_RXRDY       0x00000001  // Receive Packet Ready
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXCSRH6 register.
 //
 //*****************************************************************************
-#define USB_RXCSRH6_AUTOCL      0x00000080  // Auto Clear.
-#define USB_RXCSRH6_AUTORQ      0x00000040  // Auto Request.
-#define USB_RXCSRH6_ISO         0x00000040  // ISO.
-#define USB_RXCSRH6_DMAEN       0x00000020  // DMA Request Enable.
-#define USB_RXCSRH6_DISNYET     0x00000010  // Disable NYET 
-#define USB_RXCSRH6_PIDERR      0x00000010  //  PID Error.
-#define USB_RXCSRH6_DMAMOD      0x00000008  // DMA Request Mode.
-#define USB_RXCSRH6_DTWE        0x00000004  // Data Toggle Write Enable.
-#define USB_RXCSRH6_DT          0x00000002  // Data Toggle.
-#define USB_RXCSRH6_INCRX       0x00000001  // Incomplete Receive.
+#define USB_RXCSRH6_AUTOCL      0x00000080  // Auto Clear
+#define USB_RXCSRH6_AUTORQ      0x00000040  // Auto Request
+#define USB_RXCSRH6_ISO         0x00000040  // Isochronous Transfers
+#define USB_RXCSRH6_DMAEN       0x00000020  // DMA Request Enable
+#define USB_RXCSRH6_DISNYET     0x00000010  // Disable NYET
+#define USB_RXCSRH6_PIDERR      0x00000010  // PID Error
+#define USB_RXCSRH6_DMAMOD      0x00000008  // DMA Request Mode
+#define USB_RXCSRH6_DTWE        0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH6_DT          0x00000002  // Data Toggle
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXCOUNT6 register.
 //
 //*****************************************************************************
-#define USB_RXCOUNT6_COUNT_M    0x00001FFF  // Receive Packet Count.
+#define USB_RXCOUNT6_COUNT_M    0x00001FFF  // Receive Packet Count
 #define USB_RXCOUNT6_COUNT_S    0
 
 //*****************************************************************************
@@ -7313,16 +7675,16 @@
 // The following are defines for the bit fields in the USB_O_TXTYPE6 register.
 //
 //*****************************************************************************
-#define USB_TXTYPE6_SPEED_M     0x000000C0  // Operating Speed.
+#define USB_TXTYPE6_SPEED_M     0x000000C0  // Operating Speed
 #define USB_TXTYPE6_SPEED_DFLT  0x00000000  // Default
 #define USB_TXTYPE6_SPEED_FULL  0x00000080  // Full
 #define USB_TXTYPE6_SPEED_LOW   0x000000C0  // Low
-#define USB_TXTYPE6_PROTO_M     0x00000030  // Protocol.
+#define USB_TXTYPE6_PROTO_M     0x00000030  // Protocol
 #define USB_TXTYPE6_PROTO_CTRL  0x00000000  // Control
 #define USB_TXTYPE6_PROTO_ISOC  0x00000010  // Isochronous
 #define USB_TXTYPE6_PROTO_BULK  0x00000020  // Bulk
 #define USB_TXTYPE6_PROTO_INT   0x00000030  // Interrupt
-#define USB_TXTYPE6_TEP_M       0x0000000F  // Target Endpoint Number.
+#define USB_TXTYPE6_TEP_M       0x0000000F  // Target Endpoint Number
 #define USB_TXTYPE6_TEP_S       0
 
 //*****************************************************************************
@@ -7332,9 +7694,9 @@
 //
 //*****************************************************************************
 #define USB_TXINTERVAL6_TXPOLL_M \
-                                0x000000FF  // TX Polling 
+                                0x000000FF  // TX Polling
 #define USB_TXINTERVAL6_NAKLMT_M \
-                                0x000000FF  //  NAK Limit.
+                                0x000000FF  // NAK Limit
 #define USB_TXINTERVAL6_TXPOLL_S \
                                 0
 #define USB_TXINTERVAL6_NAKLMT_S \
@@ -7345,16 +7707,16 @@
 // The following are defines for the bit fields in the USB_O_RXTYPE6 register.
 //
 //*****************************************************************************
-#define USB_RXTYPE6_SPEED_M     0x000000C0  // Operating Speed.
+#define USB_RXTYPE6_SPEED_M     0x000000C0  // Operating Speed
 #define USB_RXTYPE6_SPEED_DFLT  0x00000000  // Default
 #define USB_RXTYPE6_SPEED_FULL  0x00000080  // Full
 #define USB_RXTYPE6_SPEED_LOW   0x000000C0  // Low
-#define USB_RXTYPE6_PROTO_M     0x00000030  // Protocol.
+#define USB_RXTYPE6_PROTO_M     0x00000030  // Protocol
 #define USB_RXTYPE6_PROTO_CTRL  0x00000000  // Control
 #define USB_RXTYPE6_PROTO_ISOC  0x00000010  // Isochronous
 #define USB_RXTYPE6_PROTO_BULK  0x00000020  // Bulk
 #define USB_RXTYPE6_PROTO_INT   0x00000030  // Interrupt
-#define USB_RXTYPE6_TEP_M       0x0000000F  // Target Endpoint Number.
+#define USB_RXTYPE6_TEP_M       0x0000000F  // Target Endpoint Number
 #define USB_RXTYPE6_TEP_S       0
 
 //*****************************************************************************
@@ -7364,9 +7726,9 @@
 //
 //*****************************************************************************
 #define USB_RXINTERVAL6_TXPOLL_M \
-                                0x000000FF  // RX Polling 
+                                0x000000FF  // RX Polling
 #define USB_RXINTERVAL6_NAKLMT_M \
-                                0x000000FF  //  NAK Limit.
+                                0x000000FF  // NAK Limit
 #define USB_RXINTERVAL6_NAKLMT_S \
                                 0
 #define USB_RXINTERVAL6_TXPOLL_S \
@@ -7377,7 +7739,7 @@
 // The following are defines for the bit fields in the USB_O_TXMAXP7 register.
 //
 //*****************************************************************************
-#define USB_TXMAXP7_MAXLOAD_M   0x000007FF  // Maximum Payload.
+#define USB_TXMAXP7_MAXLOAD_M   0x000007FF  // Maximum Payload
 #define USB_TXMAXP7_MAXLOAD_S   0
 
 //*****************************************************************************
@@ -7385,38 +7747,37 @@
 // The following are defines for the bit fields in the USB_O_TXCSRL7 register.
 //
 //*****************************************************************************
-#define USB_TXCSRL7_INCTX       0x00000080  // Incomplete Transmit.
-#define USB_TXCSRL7_NAKTO       0x00000080  // NAK Timeout 
-#define USB_TXCSRL7_CLRDT       0x00000040  // Clear Data Toggle.
-#define USB_TXCSRL7_STALLED     0x00000020  // Endpoint Stalled.
-#define USB_TXCSRL7_STALL       0x00000010  // Send Stall.
-#define USB_TXCSRL7_SETUP       0x00000010  // Setup Packet.
-#define USB_TXCSRL7_FLUSH       0x00000008  // Flush FIFO.
-#define USB_TXCSRL7_ERROR       0x00000004  // Error.
-#define USB_TXCSRL7_UNDRN       0x00000004  // Underrun.
-#define USB_TXCSRL7_FIFONE      0x00000002  // FIFO Not Empty.
-#define USB_TXCSRL7_TXRDY       0x00000001  // Transmit Packet Ready.
+#define USB_TXCSRL7_NAKTO       0x00000080  // NAK Timeout
+#define USB_TXCSRL7_CLRDT       0x00000040  // Clear Data Toggle
+#define USB_TXCSRL7_STALLED     0x00000020  // Endpoint Stalled
+#define USB_TXCSRL7_STALL       0x00000010  // Send STALL
+#define USB_TXCSRL7_SETUP       0x00000010  // Setup Packet
+#define USB_TXCSRL7_FLUSH       0x00000008  // Flush FIFO
+#define USB_TXCSRL7_ERROR       0x00000004  // Error
+#define USB_TXCSRL7_UNDRN       0x00000004  // Underrun
+#define USB_TXCSRL7_FIFONE      0x00000002  // FIFO Not Empty
+#define USB_TXCSRL7_TXRDY       0x00000001  // Transmit Packet Ready
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_TXCSRH7 register.
 //
 //*****************************************************************************
-#define USB_TXCSRH7_AUTOSET     0x00000080  // Auto Set.
-#define USB_TXCSRH7_ISO         0x00000040  // ISO.
-#define USB_TXCSRH7_MODE        0x00000020  // Mode.
-#define USB_TXCSRH7_DMAEN       0x00000010  // DMA Request Enable.
-#define USB_TXCSRH7_FDT         0x00000008  // Force Data Toggle.
-#define USB_TXCSRH7_DMAMOD      0x00000004  // DMA Request Mode.
-#define USB_TXCSRH7_DTWE        0x00000002  // Data Toggle Write Enable.
-#define USB_TXCSRH7_DT          0x00000001  // Data Toggle.
+#define USB_TXCSRH7_AUTOSET     0x00000080  // Auto Set
+#define USB_TXCSRH7_ISO         0x00000040  // Isochronous Transfers
+#define USB_TXCSRH7_MODE        0x00000020  // Mode
+#define USB_TXCSRH7_DMAEN       0x00000010  // DMA Request Enable
+#define USB_TXCSRH7_FDT         0x00000008  // Force Data Toggle
+#define USB_TXCSRH7_DMAMOD      0x00000004  // DMA Request Mode
+#define USB_TXCSRH7_DTWE        0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH7_DT          0x00000001  // Data Toggle
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXMAXP7 register.
 //
 //*****************************************************************************
-#define USB_RXMAXP7_MAXLOAD_M   0x000007FF  // Maximum Payload.
+#define USB_RXMAXP7_MAXLOAD_M   0x000007FF  // Maximum Payload
 #define USB_RXMAXP7_MAXLOAD_S   0
 
 //*****************************************************************************
@@ -7424,40 +7785,39 @@
 // The following are defines for the bit fields in the USB_O_RXCSRL7 register.
 //
 //*****************************************************************************
-#define USB_RXCSRL7_CLRDT       0x00000080  // Clear Data Toggle.
-#define USB_RXCSRL7_STALLED     0x00000040  // Endpoint Stalled.
-#define USB_RXCSRL7_REQPKT      0x00000020  // Request Packet.
-#define USB_RXCSRL7_STALL       0x00000020  // Send Stall.
-#define USB_RXCSRL7_FLUSH       0x00000010  // Flush FIFO.
-#define USB_RXCSRL7_DATAERR     0x00000008  // Data Error.
-#define USB_RXCSRL7_NAKTO       0x00000008  //  NAK Timeout.
-#define USB_RXCSRL7_ERROR       0x00000004  // Error.
-#define USB_RXCSRL7_OVER        0x00000004  // Overrun.
-#define USB_RXCSRL7_FULL        0x00000002  // FIFO Full.
-#define USB_RXCSRL7_RXRDY       0x00000001  // Receive Packet Ready.
+#define USB_RXCSRL7_CLRDT       0x00000080  // Clear Data Toggle
+#define USB_RXCSRL7_STALLED     0x00000040  // Endpoint Stalled
+#define USB_RXCSRL7_REQPKT      0x00000020  // Request Packet
+#define USB_RXCSRL7_STALL       0x00000020  // Send STALL
+#define USB_RXCSRL7_FLUSH       0x00000010  // Flush FIFO
+#define USB_RXCSRL7_DATAERR     0x00000008  // Data Error
+#define USB_RXCSRL7_NAKTO       0x00000008  // NAK Timeout
+#define USB_RXCSRL7_ERROR       0x00000004  // Error
+#define USB_RXCSRL7_OVER        0x00000004  // Overrun
+#define USB_RXCSRL7_FULL        0x00000002  // FIFO Full
+#define USB_RXCSRL7_RXRDY       0x00000001  // Receive Packet Ready
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXCSRH7 register.
 //
 //*****************************************************************************
-#define USB_RXCSRH7_AUTOCL      0x00000080  // Auto Clear.
-#define USB_RXCSRH7_ISO         0x00000040  // ISO.
-#define USB_RXCSRH7_AUTORQ      0x00000040  // Auto Request.
-#define USB_RXCSRH7_DMAEN       0x00000020  // DMA Request Enable.
-#define USB_RXCSRH7_PIDERR      0x00000010  //  PID Error.
-#define USB_RXCSRH7_DISNYET     0x00000010  // Disable NYET 
-#define USB_RXCSRH7_DMAMOD      0x00000008  // DMA Request Mode.
-#define USB_RXCSRH7_DTWE        0x00000004  // Data Toggle Write Enable.
-#define USB_RXCSRH7_DT          0x00000002  // Data Toggle.
-#define USB_RXCSRH7_INCRX       0x00000001  // Incomplete Receive.
+#define USB_RXCSRH7_AUTOCL      0x00000080  // Auto Clear
+#define USB_RXCSRH7_ISO         0x00000040  // Isochronous Transfers
+#define USB_RXCSRH7_AUTORQ      0x00000040  // Auto Request
+#define USB_RXCSRH7_DMAEN       0x00000020  // DMA Request Enable
+#define USB_RXCSRH7_PIDERR      0x00000010  // PID Error
+#define USB_RXCSRH7_DISNYET     0x00000010  // Disable NYET
+#define USB_RXCSRH7_DMAMOD      0x00000008  // DMA Request Mode
+#define USB_RXCSRH7_DTWE        0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH7_DT          0x00000002  // Data Toggle
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXCOUNT7 register.
 //
 //*****************************************************************************
-#define USB_RXCOUNT7_COUNT_M    0x00001FFF  // Receive Packet Count.
+#define USB_RXCOUNT7_COUNT_M    0x00001FFF  // Receive Packet Count
 #define USB_RXCOUNT7_COUNT_S    0
 
 //*****************************************************************************
@@ -7465,16 +7825,16 @@
 // The following are defines for the bit fields in the USB_O_TXTYPE7 register.
 //
 //*****************************************************************************
-#define USB_TXTYPE7_SPEED_M     0x000000C0  // Operating Speed.
+#define USB_TXTYPE7_SPEED_M     0x000000C0  // Operating Speed
 #define USB_TXTYPE7_SPEED_DFLT  0x00000000  // Default
 #define USB_TXTYPE7_SPEED_FULL  0x00000080  // Full
 #define USB_TXTYPE7_SPEED_LOW   0x000000C0  // Low
-#define USB_TXTYPE7_PROTO_M     0x00000030  // Protocol.
+#define USB_TXTYPE7_PROTO_M     0x00000030  // Protocol
 #define USB_TXTYPE7_PROTO_CTRL  0x00000000  // Control
 #define USB_TXTYPE7_PROTO_ISOC  0x00000010  // Isochronous
 #define USB_TXTYPE7_PROTO_BULK  0x00000020  // Bulk
 #define USB_TXTYPE7_PROTO_INT   0x00000030  // Interrupt
-#define USB_TXTYPE7_TEP_M       0x0000000F  // Target Endpoint Number.
+#define USB_TXTYPE7_TEP_M       0x0000000F  // Target Endpoint Number
 #define USB_TXTYPE7_TEP_S       0
 
 //*****************************************************************************
@@ -7484,9 +7844,9 @@
 //
 //*****************************************************************************
 #define USB_TXINTERVAL7_TXPOLL_M \
-                                0x000000FF  // TX Polling 
+                                0x000000FF  // TX Polling
 #define USB_TXINTERVAL7_NAKLMT_M \
-                                0x000000FF  //  NAK Limit.
+                                0x000000FF  // NAK Limit
 #define USB_TXINTERVAL7_NAKLMT_S \
                                 0
 #define USB_TXINTERVAL7_TXPOLL_S \
@@ -7497,16 +7857,16 @@
 // The following are defines for the bit fields in the USB_O_RXTYPE7 register.
 //
 //*****************************************************************************
-#define USB_RXTYPE7_SPEED_M     0x000000C0  // Operating Speed.
+#define USB_RXTYPE7_SPEED_M     0x000000C0  // Operating Speed
 #define USB_RXTYPE7_SPEED_DFLT  0x00000000  // Default
 #define USB_RXTYPE7_SPEED_FULL  0x00000080  // Full
 #define USB_RXTYPE7_SPEED_LOW   0x000000C0  // Low
-#define USB_RXTYPE7_PROTO_M     0x00000030  // Protocol.
+#define USB_RXTYPE7_PROTO_M     0x00000030  // Protocol
 #define USB_RXTYPE7_PROTO_CTRL  0x00000000  // Control
 #define USB_RXTYPE7_PROTO_ISOC  0x00000010  // Isochronous
 #define USB_RXTYPE7_PROTO_BULK  0x00000020  // Bulk
 #define USB_RXTYPE7_PROTO_INT   0x00000030  // Interrupt
-#define USB_RXTYPE7_TEP_M       0x0000000F  // Target Endpoint Number.
+#define USB_RXTYPE7_TEP_M       0x0000000F  // Target Endpoint Number
 #define USB_RXTYPE7_TEP_S       0
 
 //*****************************************************************************
@@ -7516,9 +7876,9 @@
 //
 //*****************************************************************************
 #define USB_RXINTERVAL7_TXPOLL_M \
-                                0x000000FF  // RX Polling 
+                                0x000000FF  // RX Polling
 #define USB_RXINTERVAL7_NAKLMT_M \
-                                0x000000FF  //  NAK Limit.
+                                0x000000FF  // NAK Limit
 #define USB_RXINTERVAL7_NAKLMT_S \
                                 0
 #define USB_RXINTERVAL7_TXPOLL_S \
@@ -7529,7 +7889,7 @@
 // The following are defines for the bit fields in the USB_O_TXMAXP8 register.
 //
 //*****************************************************************************
-#define USB_TXMAXP8_MAXLOAD_M   0x000007FF  // Maximum Payload.
+#define USB_TXMAXP8_MAXLOAD_M   0x000007FF  // Maximum Payload
 #define USB_TXMAXP8_MAXLOAD_S   0
 
 //*****************************************************************************
@@ -7537,38 +7897,37 @@
 // The following are defines for the bit fields in the USB_O_TXCSRL8 register.
 //
 //*****************************************************************************
-#define USB_TXCSRL8_INCTX       0x00000080  // Incomplete Transmit.
-#define USB_TXCSRL8_NAKTO       0x00000080  // NAK Timeout 
-#define USB_TXCSRL8_CLRDT       0x00000040  // Clear Data Toggle.
-#define USB_TXCSRL8_STALLED     0x00000020  // Endpoint Stalled.
-#define USB_TXCSRL8_STALL       0x00000010  // Send Stall.
-#define USB_TXCSRL8_SETUP       0x00000010  // Setup Packet.
-#define USB_TXCSRL8_FLUSH       0x00000008  // Flush FIFO.
-#define USB_TXCSRL8_ERROR       0x00000004  // Error.
-#define USB_TXCSRL8_UNDRN       0x00000004  // Underrun.
-#define USB_TXCSRL8_FIFONE      0x00000002  // FIFO Not Empty.
-#define USB_TXCSRL8_TXRDY       0x00000001  // Transmit Packet Ready.
+#define USB_TXCSRL8_NAKTO       0x00000080  // NAK Timeout
+#define USB_TXCSRL8_CLRDT       0x00000040  // Clear Data Toggle
+#define USB_TXCSRL8_STALLED     0x00000020  // Endpoint Stalled
+#define USB_TXCSRL8_STALL       0x00000010  // Send STALL
+#define USB_TXCSRL8_SETUP       0x00000010  // Setup Packet
+#define USB_TXCSRL8_FLUSH       0x00000008  // Flush FIFO
+#define USB_TXCSRL8_ERROR       0x00000004  // Error
+#define USB_TXCSRL8_UNDRN       0x00000004  // Underrun
+#define USB_TXCSRL8_FIFONE      0x00000002  // FIFO Not Empty
+#define USB_TXCSRL8_TXRDY       0x00000001  // Transmit Packet Ready
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_TXCSRH8 register.
 //
 //*****************************************************************************
-#define USB_TXCSRH8_AUTOSET     0x00000080  // Auto Set.
-#define USB_TXCSRH8_ISO         0x00000040  // ISO.
-#define USB_TXCSRH8_MODE        0x00000020  // Mode.
-#define USB_TXCSRH8_DMAEN       0x00000010  // DMA Request Enable.
-#define USB_TXCSRH8_FDT         0x00000008  // Force Data Toggle.
-#define USB_TXCSRH8_DMAMOD      0x00000004  // DMA Request Mode.
-#define USB_TXCSRH8_DTWE        0x00000002  // Data Toggle Write Enable.
-#define USB_TXCSRH8_DT          0x00000001  // Data Toggle.
+#define USB_TXCSRH8_AUTOSET     0x00000080  // Auto Set
+#define USB_TXCSRH8_ISO         0x00000040  // Isochronous Transfers
+#define USB_TXCSRH8_MODE        0x00000020  // Mode
+#define USB_TXCSRH8_DMAEN       0x00000010  // DMA Request Enable
+#define USB_TXCSRH8_FDT         0x00000008  // Force Data Toggle
+#define USB_TXCSRH8_DMAMOD      0x00000004  // DMA Request Mode
+#define USB_TXCSRH8_DTWE        0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH8_DT          0x00000001  // Data Toggle
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXMAXP8 register.
 //
 //*****************************************************************************
-#define USB_RXMAXP8_MAXLOAD_M   0x000007FF  // Maximum Payload.
+#define USB_RXMAXP8_MAXLOAD_M   0x000007FF  // Maximum Payload
 #define USB_RXMAXP8_MAXLOAD_S   0
 
 //*****************************************************************************
@@ -7576,40 +7935,39 @@
 // The following are defines for the bit fields in the USB_O_RXCSRL8 register.
 //
 //*****************************************************************************
-#define USB_RXCSRL8_CLRDT       0x00000080  // Clear Data Toggle.
-#define USB_RXCSRL8_STALLED     0x00000040  // Endpoint Stalled.
-#define USB_RXCSRL8_STALL       0x00000020  // Send Stall.
-#define USB_RXCSRL8_REQPKT      0x00000020  // Request Packet.
-#define USB_RXCSRL8_FLUSH       0x00000010  // Flush FIFO.
-#define USB_RXCSRL8_NAKTO       0x00000008  //  NAK Timeout.
-#define USB_RXCSRL8_DATAERR     0x00000008  // Data Error.
-#define USB_RXCSRL8_OVER        0x00000004  // Overrun.
-#define USB_RXCSRL8_ERROR       0x00000004  // Error.
-#define USB_RXCSRL8_FULL        0x00000002  // FIFO Full.
-#define USB_RXCSRL8_RXRDY       0x00000001  // Receive Packet Ready.
+#define USB_RXCSRL8_CLRDT       0x00000080  // Clear Data Toggle
+#define USB_RXCSRL8_STALLED     0x00000040  // Endpoint Stalled
+#define USB_RXCSRL8_STALL       0x00000020  // Send STALL
+#define USB_RXCSRL8_REQPKT      0x00000020  // Request Packet
+#define USB_RXCSRL8_FLUSH       0x00000010  // Flush FIFO
+#define USB_RXCSRL8_NAKTO       0x00000008  // NAK Timeout
+#define USB_RXCSRL8_DATAERR     0x00000008  // Data Error
+#define USB_RXCSRL8_OVER        0x00000004  // Overrun
+#define USB_RXCSRL8_ERROR       0x00000004  // Error
+#define USB_RXCSRL8_FULL        0x00000002  // FIFO Full
+#define USB_RXCSRL8_RXRDY       0x00000001  // Receive Packet Ready
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXCSRH8 register.
 //
 //*****************************************************************************
-#define USB_RXCSRH8_AUTOCL      0x00000080  // Auto Clear.
-#define USB_RXCSRH8_AUTORQ      0x00000040  // Auto Request.
-#define USB_RXCSRH8_ISO         0x00000040  // ISO.
-#define USB_RXCSRH8_DMAEN       0x00000020  // DMA Request Enable.
-#define USB_RXCSRH8_DISNYET     0x00000010  // Disable NYET 
-#define USB_RXCSRH8_PIDERR      0x00000010  //  PID Error.
-#define USB_RXCSRH8_DMAMOD      0x00000008  // DMA Request Mode.
-#define USB_RXCSRH8_DTWE        0x00000004  // Data Toggle Write Enable.
-#define USB_RXCSRH8_DT          0x00000002  // Data Toggle.
-#define USB_RXCSRH8_INCRX       0x00000001  // Incomplete Receive.
+#define USB_RXCSRH8_AUTOCL      0x00000080  // Auto Clear
+#define USB_RXCSRH8_AUTORQ      0x00000040  // Auto Request
+#define USB_RXCSRH8_ISO         0x00000040  // Isochronous Transfers
+#define USB_RXCSRH8_DMAEN       0x00000020  // DMA Request Enable
+#define USB_RXCSRH8_DISNYET     0x00000010  // Disable NYET
+#define USB_RXCSRH8_PIDERR      0x00000010  // PID Error
+#define USB_RXCSRH8_DMAMOD      0x00000008  // DMA Request Mode
+#define USB_RXCSRH8_DTWE        0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH8_DT          0x00000002  // Data Toggle
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXCOUNT8 register.
 //
 //*****************************************************************************
-#define USB_RXCOUNT8_COUNT_M    0x00001FFF  // Receive Packet Count.
+#define USB_RXCOUNT8_COUNT_M    0x00001FFF  // Receive Packet Count
 #define USB_RXCOUNT8_COUNT_S    0
 
 //*****************************************************************************
@@ -7617,16 +7975,16 @@
 // The following are defines for the bit fields in the USB_O_TXTYPE8 register.
 //
 //*****************************************************************************
-#define USB_TXTYPE8_SPEED_M     0x000000C0  // Operating Speed.
+#define USB_TXTYPE8_SPEED_M     0x000000C0  // Operating Speed
 #define USB_TXTYPE8_SPEED_DFLT  0x00000000  // Default
 #define USB_TXTYPE8_SPEED_FULL  0x00000080  // Full
 #define USB_TXTYPE8_SPEED_LOW   0x000000C0  // Low
-#define USB_TXTYPE8_PROTO_M     0x00000030  // Protocol.
+#define USB_TXTYPE8_PROTO_M     0x00000030  // Protocol
 #define USB_TXTYPE8_PROTO_CTRL  0x00000000  // Control
 #define USB_TXTYPE8_PROTO_ISOC  0x00000010  // Isochronous
 #define USB_TXTYPE8_PROTO_BULK  0x00000020  // Bulk
 #define USB_TXTYPE8_PROTO_INT   0x00000030  // Interrupt
-#define USB_TXTYPE8_TEP_M       0x0000000F  // Target Endpoint Number.
+#define USB_TXTYPE8_TEP_M       0x0000000F  // Target Endpoint Number
 #define USB_TXTYPE8_TEP_S       0
 
 //*****************************************************************************
@@ -7636,9 +7994,9 @@
 //
 //*****************************************************************************
 #define USB_TXINTERVAL8_TXPOLL_M \
-                                0x000000FF  // TX Polling 
+                                0x000000FF  // TX Polling
 #define USB_TXINTERVAL8_NAKLMT_M \
-                                0x000000FF  //  NAK Limit.
+                                0x000000FF  // NAK Limit
 #define USB_TXINTERVAL8_NAKLMT_S \
                                 0
 #define USB_TXINTERVAL8_TXPOLL_S \
@@ -7649,16 +8007,16 @@
 // The following are defines for the bit fields in the USB_O_RXTYPE8 register.
 //
 //*****************************************************************************
-#define USB_RXTYPE8_SPEED_M     0x000000C0  // Operating Speed.
+#define USB_RXTYPE8_SPEED_M     0x000000C0  // Operating Speed
 #define USB_RXTYPE8_SPEED_DFLT  0x00000000  // Default
 #define USB_RXTYPE8_SPEED_FULL  0x00000080  // Full
 #define USB_RXTYPE8_SPEED_LOW   0x000000C0  // Low
-#define USB_RXTYPE8_PROTO_M     0x00000030  // Protocol.
+#define USB_RXTYPE8_PROTO_M     0x00000030  // Protocol
 #define USB_RXTYPE8_PROTO_CTRL  0x00000000  // Control
 #define USB_RXTYPE8_PROTO_ISOC  0x00000010  // Isochronous
 #define USB_RXTYPE8_PROTO_BULK  0x00000020  // Bulk
 #define USB_RXTYPE8_PROTO_INT   0x00000030  // Interrupt
-#define USB_RXTYPE8_TEP_M       0x0000000F  // Target Endpoint Number.
+#define USB_RXTYPE8_TEP_M       0x0000000F  // Target Endpoint Number
 #define USB_RXTYPE8_TEP_S       0
 
 //*****************************************************************************
@@ -7668,9 +8026,9 @@
 //
 //*****************************************************************************
 #define USB_RXINTERVAL8_NAKLMT_M \
-                                0x000000FF  //  NAK Limit.
+                                0x000000FF  // NAK Limit
 #define USB_RXINTERVAL8_TXPOLL_M \
-                                0x000000FF  // RX Polling 
+                                0x000000FF  // RX Polling
 #define USB_RXINTERVAL8_NAKLMT_S \
                                 0
 #define USB_RXINTERVAL8_TXPOLL_S \
@@ -7681,7 +8039,7 @@
 // The following are defines for the bit fields in the USB_O_TXMAXP9 register.
 //
 //*****************************************************************************
-#define USB_TXMAXP9_MAXLOAD_M   0x000007FF  // Maximum Payload.
+#define USB_TXMAXP9_MAXLOAD_M   0x000007FF  // Maximum Payload
 #define USB_TXMAXP9_MAXLOAD_S   0
 
 //*****************************************************************************
@@ -7689,38 +8047,37 @@
 // The following are defines for the bit fields in the USB_O_TXCSRL9 register.
 //
 //*****************************************************************************
-#define USB_TXCSRL9_INCTX       0x00000080  // Incomplete Transmit.
-#define USB_TXCSRL9_NAKTO       0x00000080  // NAK Timeout 
-#define USB_TXCSRL9_CLRDT       0x00000040  // Clear Data Toggle.
-#define USB_TXCSRL9_STALLED     0x00000020  // Endpoint Stalled.
-#define USB_TXCSRL9_SETUP       0x00000010  // Setup Packet.
-#define USB_TXCSRL9_STALL       0x00000010  // Send Stall.
-#define USB_TXCSRL9_FLUSH       0x00000008  // Flush FIFO.
-#define USB_TXCSRL9_ERROR       0x00000004  // Error.
-#define USB_TXCSRL9_UNDRN       0x00000004  // Underrun.
-#define USB_TXCSRL9_FIFONE      0x00000002  // FIFO Not Empty.
-#define USB_TXCSRL9_TXRDY       0x00000001  // Transmit Packet Ready.
+#define USB_TXCSRL9_NAKTO       0x00000080  // NAK Timeout
+#define USB_TXCSRL9_CLRDT       0x00000040  // Clear Data Toggle
+#define USB_TXCSRL9_STALLED     0x00000020  // Endpoint Stalled
+#define USB_TXCSRL9_SETUP       0x00000010  // Setup Packet
+#define USB_TXCSRL9_STALL       0x00000010  // Send STALL
+#define USB_TXCSRL9_FLUSH       0x00000008  // Flush FIFO
+#define USB_TXCSRL9_ERROR       0x00000004  // Error
+#define USB_TXCSRL9_UNDRN       0x00000004  // Underrun
+#define USB_TXCSRL9_FIFONE      0x00000002  // FIFO Not Empty
+#define USB_TXCSRL9_TXRDY       0x00000001  // Transmit Packet Ready
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_TXCSRH9 register.
 //
 //*****************************************************************************
-#define USB_TXCSRH9_AUTOSET     0x00000080  // Auto Set.
-#define USB_TXCSRH9_ISO         0x00000040  // ISO.
-#define USB_TXCSRH9_MODE        0x00000020  // Mode.
-#define USB_TXCSRH9_DMAEN       0x00000010  // DMA Request Enable.
-#define USB_TXCSRH9_FDT         0x00000008  // Force Data Toggle.
-#define USB_TXCSRH9_DMAMOD      0x00000004  // DMA Request Mode.
-#define USB_TXCSRH9_DTWE        0x00000002  // Data Toggle Write Enable.
-#define USB_TXCSRH9_DT          0x00000001  // Data Toggle.
+#define USB_TXCSRH9_AUTOSET     0x00000080  // Auto Set
+#define USB_TXCSRH9_ISO         0x00000040  // Isochronous Transfers
+#define USB_TXCSRH9_MODE        0x00000020  // Mode
+#define USB_TXCSRH9_DMAEN       0x00000010  // DMA Request Enable
+#define USB_TXCSRH9_FDT         0x00000008  // Force Data Toggle
+#define USB_TXCSRH9_DMAMOD      0x00000004  // DMA Request Mode
+#define USB_TXCSRH9_DTWE        0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH9_DT          0x00000001  // Data Toggle
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXMAXP9 register.
 //
 //*****************************************************************************
-#define USB_RXMAXP9_MAXLOAD_M   0x000007FF  // Maximum Payload.
+#define USB_RXMAXP9_MAXLOAD_M   0x000007FF  // Maximum Payload
 #define USB_RXMAXP9_MAXLOAD_S   0
 
 //*****************************************************************************
@@ -7728,40 +8085,39 @@
 // The following are defines for the bit fields in the USB_O_RXCSRL9 register.
 //
 //*****************************************************************************
-#define USB_RXCSRL9_CLRDT       0x00000080  // Clear Data Toggle.
-#define USB_RXCSRL9_STALLED     0x00000040  // Endpoint Stalled.
-#define USB_RXCSRL9_STALL       0x00000020  // Send Stall.
-#define USB_RXCSRL9_REQPKT      0x00000020  // Request Packet.
-#define USB_RXCSRL9_FLUSH       0x00000010  // Flush FIFO.
-#define USB_RXCSRL9_DATAERR     0x00000008  // Data Error.
-#define USB_RXCSRL9_NAKTO       0x00000008  //  NAK Timeout.
-#define USB_RXCSRL9_ERROR       0x00000004  // Error.
-#define USB_RXCSRL9_OVER        0x00000004  // Overrun.
-#define USB_RXCSRL9_FULL        0x00000002  // FIFO Full.
-#define USB_RXCSRL9_RXRDY       0x00000001  // Receive Packet Ready.
+#define USB_RXCSRL9_CLRDT       0x00000080  // Clear Data Toggle
+#define USB_RXCSRL9_STALLED     0x00000040  // Endpoint Stalled
+#define USB_RXCSRL9_STALL       0x00000020  // Send STALL
+#define USB_RXCSRL9_REQPKT      0x00000020  // Request Packet
+#define USB_RXCSRL9_FLUSH       0x00000010  // Flush FIFO
+#define USB_RXCSRL9_DATAERR     0x00000008  // Data Error
+#define USB_RXCSRL9_NAKTO       0x00000008  // NAK Timeout
+#define USB_RXCSRL9_ERROR       0x00000004  // Error
+#define USB_RXCSRL9_OVER        0x00000004  // Overrun
+#define USB_RXCSRL9_FULL        0x00000002  // FIFO Full
+#define USB_RXCSRL9_RXRDY       0x00000001  // Receive Packet Ready
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXCSRH9 register.
 //
 //*****************************************************************************
-#define USB_RXCSRH9_AUTOCL      0x00000080  // Auto Clear.
-#define USB_RXCSRH9_ISO         0x00000040  // ISO.
-#define USB_RXCSRH9_AUTORQ      0x00000040  // Auto Request.
-#define USB_RXCSRH9_DMAEN       0x00000020  // DMA Request Enable.
-#define USB_RXCSRH9_PIDERR      0x00000010  //  PID Error.
-#define USB_RXCSRH9_DISNYET     0x00000010  // Disable NYET 
-#define USB_RXCSRH9_DMAMOD      0x00000008  // DMA Request Mode.
-#define USB_RXCSRH9_DTWE        0x00000004  // Data Toggle Write Enable.
-#define USB_RXCSRH9_DT          0x00000002  // Data Toggle.
-#define USB_RXCSRH9_INCRX       0x00000001  // Incomplete Receive.
+#define USB_RXCSRH9_AUTOCL      0x00000080  // Auto Clear
+#define USB_RXCSRH9_ISO         0x00000040  // Isochronous Transfers
+#define USB_RXCSRH9_AUTORQ      0x00000040  // Auto Request
+#define USB_RXCSRH9_DMAEN       0x00000020  // DMA Request Enable
+#define USB_RXCSRH9_PIDERR      0x00000010  // PID Error
+#define USB_RXCSRH9_DISNYET     0x00000010  // Disable NYET
+#define USB_RXCSRH9_DMAMOD      0x00000008  // DMA Request Mode
+#define USB_RXCSRH9_DTWE        0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH9_DT          0x00000002  // Data Toggle
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXCOUNT9 register.
 //
 //*****************************************************************************
-#define USB_RXCOUNT9_COUNT_M    0x00001FFF  // Receive Packet Count.
+#define USB_RXCOUNT9_COUNT_M    0x00001FFF  // Receive Packet Count
 #define USB_RXCOUNT9_COUNT_S    0
 
 //*****************************************************************************
@@ -7769,16 +8125,16 @@
 // The following are defines for the bit fields in the USB_O_TXTYPE9 register.
 //
 //*****************************************************************************
-#define USB_TXTYPE9_SPEED_M     0x000000C0  // Operating Speed.
+#define USB_TXTYPE9_SPEED_M     0x000000C0  // Operating Speed
 #define USB_TXTYPE9_SPEED_DFLT  0x00000000  // Default
 #define USB_TXTYPE9_SPEED_FULL  0x00000080  // Full
 #define USB_TXTYPE9_SPEED_LOW   0x000000C0  // Low
-#define USB_TXTYPE9_PROTO_M     0x00000030  // Protocol.
+#define USB_TXTYPE9_PROTO_M     0x00000030  // Protocol
 #define USB_TXTYPE9_PROTO_CTRL  0x00000000  // Control
 #define USB_TXTYPE9_PROTO_ISOC  0x00000010  // Isochronous
 #define USB_TXTYPE9_PROTO_BULK  0x00000020  // Bulk
 #define USB_TXTYPE9_PROTO_INT   0x00000030  // Interrupt
-#define USB_TXTYPE9_TEP_M       0x0000000F  // Target Endpoint Number.
+#define USB_TXTYPE9_TEP_M       0x0000000F  // Target Endpoint Number
 #define USB_TXTYPE9_TEP_S       0
 
 //*****************************************************************************
@@ -7788,9 +8144,9 @@
 //
 //*****************************************************************************
 #define USB_TXINTERVAL9_TXPOLL_M \
-                                0x000000FF  // TX Polling 
+                                0x000000FF  // TX Polling
 #define USB_TXINTERVAL9_NAKLMT_M \
-                                0x000000FF  //  NAK Limit.
+                                0x000000FF  // NAK Limit
 #define USB_TXINTERVAL9_TXPOLL_S \
                                 0
 #define USB_TXINTERVAL9_NAKLMT_S \
@@ -7801,16 +8157,16 @@
 // The following are defines for the bit fields in the USB_O_RXTYPE9 register.
 //
 //*****************************************************************************
-#define USB_RXTYPE9_SPEED_M     0x000000C0  // Operating Speed.
+#define USB_RXTYPE9_SPEED_M     0x000000C0  // Operating Speed
 #define USB_RXTYPE9_SPEED_DFLT  0x00000000  // Default
 #define USB_RXTYPE9_SPEED_FULL  0x00000080  // Full
 #define USB_RXTYPE9_SPEED_LOW   0x000000C0  // Low
-#define USB_RXTYPE9_PROTO_M     0x00000030  // Protocol.
+#define USB_RXTYPE9_PROTO_M     0x00000030  // Protocol
 #define USB_RXTYPE9_PROTO_CTRL  0x00000000  // Control
 #define USB_RXTYPE9_PROTO_ISOC  0x00000010  // Isochronous
 #define USB_RXTYPE9_PROTO_BULK  0x00000020  // Bulk
 #define USB_RXTYPE9_PROTO_INT   0x00000030  // Interrupt
-#define USB_RXTYPE9_TEP_M       0x0000000F  // Target Endpoint Number.
+#define USB_RXTYPE9_TEP_M       0x0000000F  // Target Endpoint Number
 #define USB_RXTYPE9_TEP_S       0
 
 //*****************************************************************************
@@ -7819,10 +8175,10 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RXINTERVAL9_NAKLMT_M \
-                                0x000000FF  //  NAK Limit.
 #define USB_RXINTERVAL9_TXPOLL_M \
-                                0x000000FF  // RX Polling 
+                                0x000000FF  // RX Polling
+#define USB_RXINTERVAL9_NAKLMT_M \
+                                0x000000FF  // NAK Limit
 #define USB_RXINTERVAL9_NAKLMT_S \
                                 0
 #define USB_RXINTERVAL9_TXPOLL_S \
@@ -7833,7 +8189,7 @@
 // The following are defines for the bit fields in the USB_O_TXMAXP10 register.
 //
 //*****************************************************************************
-#define USB_TXMAXP10_MAXLOAD_M  0x000007FF  // Maximum Payload.
+#define USB_TXMAXP10_MAXLOAD_M  0x000007FF  // Maximum Payload
 #define USB_TXMAXP10_MAXLOAD_S  0
 
 //*****************************************************************************
@@ -7841,38 +8197,37 @@
 // The following are defines for the bit fields in the USB_O_TXCSRL10 register.
 //
 //*****************************************************************************
-#define USB_TXCSRL10_NAKTO      0x00000080  // NAK Timeout 
-#define USB_TXCSRL10_INCTX      0x00000080  // Incomplete Transmit.
-#define USB_TXCSRL10_CLRDT      0x00000040  // Clear Data Toggle.
-#define USB_TXCSRL10_STALLED    0x00000020  // Endpoint Stalled.
-#define USB_TXCSRL10_SETUP      0x00000010  // Setup Packet.
-#define USB_TXCSRL10_STALL      0x00000010  // Send Stall.
-#define USB_TXCSRL10_FLUSH      0x00000008  // Flush FIFO.
-#define USB_TXCSRL10_UNDRN      0x00000004  // Underrun.
-#define USB_TXCSRL10_ERROR      0x00000004  // Error.
-#define USB_TXCSRL10_FIFONE     0x00000002  // FIFO Not Empty.
-#define USB_TXCSRL10_TXRDY      0x00000001  // Transmit Packet Ready.
+#define USB_TXCSRL10_NAKTO      0x00000080  // NAK Timeout
+#define USB_TXCSRL10_CLRDT      0x00000040  // Clear Data Toggle
+#define USB_TXCSRL10_STALLED    0x00000020  // Endpoint Stalled
+#define USB_TXCSRL10_SETUP      0x00000010  // Setup Packet
+#define USB_TXCSRL10_STALL      0x00000010  // Send STALL
+#define USB_TXCSRL10_FLUSH      0x00000008  // Flush FIFO
+#define USB_TXCSRL10_UNDRN      0x00000004  // Underrun
+#define USB_TXCSRL10_ERROR      0x00000004  // Error
+#define USB_TXCSRL10_FIFONE     0x00000002  // FIFO Not Empty
+#define USB_TXCSRL10_TXRDY      0x00000001  // Transmit Packet Ready
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_TXCSRH10 register.
 //
 //*****************************************************************************
-#define USB_TXCSRH10_AUTOSET    0x00000080  // Auto Set.
-#define USB_TXCSRH10_ISO        0x00000040  // ISO.
-#define USB_TXCSRH10_MODE       0x00000020  // Mode.
-#define USB_TXCSRH10_DMAEN      0x00000010  // DMA Request Enable.
-#define USB_TXCSRH10_FDT        0x00000008  // Force Data Toggle.
-#define USB_TXCSRH10_DMAMOD     0x00000004  // DMA Request Mode.
-#define USB_TXCSRH10_DTWE       0x00000002  // Data Toggle Write Enable.
-#define USB_TXCSRH10_DT         0x00000001  // Data Toggle.
+#define USB_TXCSRH10_AUTOSET    0x00000080  // Auto Set
+#define USB_TXCSRH10_ISO        0x00000040  // Isochronous Transfers
+#define USB_TXCSRH10_MODE       0x00000020  // Mode
+#define USB_TXCSRH10_DMAEN      0x00000010  // DMA Request Enable
+#define USB_TXCSRH10_FDT        0x00000008  // Force Data Toggle
+#define USB_TXCSRH10_DMAMOD     0x00000004  // DMA Request Mode
+#define USB_TXCSRH10_DTWE       0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH10_DT         0x00000001  // Data Toggle
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXMAXP10 register.
 //
 //*****************************************************************************
-#define USB_RXMAXP10_MAXLOAD_M  0x000007FF  // Maximum Payload.
+#define USB_RXMAXP10_MAXLOAD_M  0x000007FF  // Maximum Payload
 #define USB_RXMAXP10_MAXLOAD_S  0
 
 //*****************************************************************************
@@ -7880,33 +8235,32 @@
 // The following are defines for the bit fields in the USB_O_RXCSRL10 register.
 //
 //*****************************************************************************
-#define USB_RXCSRL10_CLRDT      0x00000080  // Clear Data Toggle.
-#define USB_RXCSRL10_STALLED    0x00000040  // Endpoint Stalled.
-#define USB_RXCSRL10_STALL      0x00000020  // Send Stall.
-#define USB_RXCSRL10_REQPKT     0x00000020  // Request Packet.
-#define USB_RXCSRL10_FLUSH      0x00000010  // Flush FIFO.
-#define USB_RXCSRL10_NAKTO      0x00000008  //  NAK Timeout.
-#define USB_RXCSRL10_DATAERR    0x00000008  // Data Error.
-#define USB_RXCSRL10_OVER       0x00000004  // Overrun.
-#define USB_RXCSRL10_ERROR      0x00000004  // Error.
-#define USB_RXCSRL10_FULL       0x00000002  // FIFO Full.
-#define USB_RXCSRL10_RXRDY      0x00000001  // Receive Packet Ready.
+#define USB_RXCSRL10_CLRDT      0x00000080  // Clear Data Toggle
+#define USB_RXCSRL10_STALLED    0x00000040  // Endpoint Stalled
+#define USB_RXCSRL10_STALL      0x00000020  // Send STALL
+#define USB_RXCSRL10_REQPKT     0x00000020  // Request Packet
+#define USB_RXCSRL10_FLUSH      0x00000010  // Flush FIFO
+#define USB_RXCSRL10_NAKTO      0x00000008  // NAK Timeout
+#define USB_RXCSRL10_DATAERR    0x00000008  // Data Error
+#define USB_RXCSRL10_OVER       0x00000004  // Overrun
+#define USB_RXCSRL10_ERROR      0x00000004  // Error
+#define USB_RXCSRL10_FULL       0x00000002  // FIFO Full
+#define USB_RXCSRL10_RXRDY      0x00000001  // Receive Packet Ready
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXCSRH10 register.
 //
 //*****************************************************************************
-#define USB_RXCSRH10_AUTOCL     0x00000080  // Auto Clear.
-#define USB_RXCSRH10_AUTORQ     0x00000040  // Auto Request.
-#define USB_RXCSRH10_ISO        0x00000040  // ISO.
-#define USB_RXCSRH10_DMAEN      0x00000020  // DMA Request Enable.
-#define USB_RXCSRH10_PIDERR     0x00000010  //  PID Error.
-#define USB_RXCSRH10_DISNYET    0x00000010  // Disable NYET 
-#define USB_RXCSRH10_DMAMOD     0x00000008  // DMA Request Mode.
-#define USB_RXCSRH10_DTWE       0x00000004  // Data Toggle Write Enable.
-#define USB_RXCSRH10_DT         0x00000002  // Data Toggle.
-#define USB_RXCSRH10_INCRX      0x00000001  // Incomplete Receive.
+#define USB_RXCSRH10_AUTOCL     0x00000080  // Auto Clear
+#define USB_RXCSRH10_AUTORQ     0x00000040  // Auto Request
+#define USB_RXCSRH10_ISO        0x00000040  // Isochronous Transfers
+#define USB_RXCSRH10_DMAEN      0x00000020  // DMA Request Enable
+#define USB_RXCSRH10_PIDERR     0x00000010  // PID Error
+#define USB_RXCSRH10_DISNYET    0x00000010  // Disable NYET
+#define USB_RXCSRH10_DMAMOD     0x00000008  // DMA Request Mode
+#define USB_RXCSRH10_DTWE       0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH10_DT         0x00000002  // Data Toggle
 
 //*****************************************************************************
 //
@@ -7914,7 +8268,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RXCOUNT10_COUNT_M   0x00001FFF  // Receive Packet Count.
+#define USB_RXCOUNT10_COUNT_M   0x00001FFF  // Receive Packet Count
 #define USB_RXCOUNT10_COUNT_S   0
 
 //*****************************************************************************
@@ -7922,16 +8276,16 @@
 // The following are defines for the bit fields in the USB_O_TXTYPE10 register.
 //
 //*****************************************************************************
-#define USB_TXTYPE10_SPEED_M    0x000000C0  // Operating Speed.
+#define USB_TXTYPE10_SPEED_M    0x000000C0  // Operating Speed
 #define USB_TXTYPE10_SPEED_DFLT 0x00000000  // Default
 #define USB_TXTYPE10_SPEED_FULL 0x00000080  // Full
 #define USB_TXTYPE10_SPEED_LOW  0x000000C0  // Low
-#define USB_TXTYPE10_PROTO_M    0x00000030  // Protocol.
+#define USB_TXTYPE10_PROTO_M    0x00000030  // Protocol
 #define USB_TXTYPE10_PROTO_CTRL 0x00000000  // Control
 #define USB_TXTYPE10_PROTO_ISOC 0x00000010  // Isochronous
 #define USB_TXTYPE10_PROTO_BULK 0x00000020  // Bulk
 #define USB_TXTYPE10_PROTO_INT  0x00000030  // Interrupt
-#define USB_TXTYPE10_TEP_M      0x0000000F  // Target Endpoint Number.
+#define USB_TXTYPE10_TEP_M      0x0000000F  // Target Endpoint Number
 #define USB_TXTYPE10_TEP_S      0
 
 //*****************************************************************************
@@ -7941,9 +8295,9 @@
 //
 //*****************************************************************************
 #define USB_TXINTERVAL10_NAKLMT_M \
-                                0x000000FF  //  NAK Limit.
+                                0x000000FF  // NAK Limit
 #define USB_TXINTERVAL10_TXPOLL_M \
-                                0x000000FF  // TX Polling 
+                                0x000000FF  // TX Polling
 #define USB_TXINTERVAL10_TXPOLL_S \
                                 0
 #define USB_TXINTERVAL10_NAKLMT_S \
@@ -7954,16 +8308,16 @@
 // The following are defines for the bit fields in the USB_O_RXTYPE10 register.
 //
 //*****************************************************************************
-#define USB_RXTYPE10_SPEED_M    0x000000C0  // Operating Speed.
+#define USB_RXTYPE10_SPEED_M    0x000000C0  // Operating Speed
 #define USB_RXTYPE10_SPEED_DFLT 0x00000000  // Default
 #define USB_RXTYPE10_SPEED_FULL 0x00000080  // Full
 #define USB_RXTYPE10_SPEED_LOW  0x000000C0  // Low
-#define USB_RXTYPE10_PROTO_M    0x00000030  // Protocol.
+#define USB_RXTYPE10_PROTO_M    0x00000030  // Protocol
 #define USB_RXTYPE10_PROTO_CTRL 0x00000000  // Control
 #define USB_RXTYPE10_PROTO_ISOC 0x00000010  // Isochronous
 #define USB_RXTYPE10_PROTO_BULK 0x00000020  // Bulk
 #define USB_RXTYPE10_PROTO_INT  0x00000030  // Interrupt
-#define USB_RXTYPE10_TEP_M      0x0000000F  // Target Endpoint Number.
+#define USB_RXTYPE10_TEP_M      0x0000000F  // Target Endpoint Number
 #define USB_RXTYPE10_TEP_S      0
 
 //*****************************************************************************
@@ -7973,9 +8327,9 @@
 //
 //*****************************************************************************
 #define USB_RXINTERVAL10_NAKLMT_M \
-                                0x000000FF  //  NAK Limit.
+                                0x000000FF  // NAK Limit
 #define USB_RXINTERVAL10_TXPOLL_M \
-                                0x000000FF  // RX Polling 
+                                0x000000FF  // RX Polling
 #define USB_RXINTERVAL10_TXPOLL_S \
                                 0
 #define USB_RXINTERVAL10_NAKLMT_S \
@@ -7986,7 +8340,7 @@
 // The following are defines for the bit fields in the USB_O_TXMAXP11 register.
 //
 //*****************************************************************************
-#define USB_TXMAXP11_MAXLOAD_M  0x000007FF  // Maximum Payload.
+#define USB_TXMAXP11_MAXLOAD_M  0x000007FF  // Maximum Payload
 #define USB_TXMAXP11_MAXLOAD_S  0
 
 //*****************************************************************************
@@ -7994,38 +8348,37 @@
 // The following are defines for the bit fields in the USB_O_TXCSRL11 register.
 //
 //*****************************************************************************
-#define USB_TXCSRL11_NAKTO      0x00000080  // NAK Timeout 
-#define USB_TXCSRL11_INCTX      0x00000080  // Incomplete Transmit.
-#define USB_TXCSRL11_CLRDT      0x00000040  // Clear Data Toggle.
-#define USB_TXCSRL11_STALLED    0x00000020  // Endpoint Stalled.
-#define USB_TXCSRL11_STALL      0x00000010  // Send Stall.
-#define USB_TXCSRL11_SETUP      0x00000010  // Setup Packet.
-#define USB_TXCSRL11_FLUSH      0x00000008  // Flush FIFO.
-#define USB_TXCSRL11_ERROR      0x00000004  // Error.
-#define USB_TXCSRL11_UNDRN      0x00000004  // Underrun.
-#define USB_TXCSRL11_FIFONE     0x00000002  // FIFO Not Empty.
-#define USB_TXCSRL11_TXRDY      0x00000001  // Transmit Packet Ready.
+#define USB_TXCSRL11_NAKTO      0x00000080  // NAK Timeout
+#define USB_TXCSRL11_CLRDT      0x00000040  // Clear Data Toggle
+#define USB_TXCSRL11_STALLED    0x00000020  // Endpoint Stalled
+#define USB_TXCSRL11_STALL      0x00000010  // Send STALL
+#define USB_TXCSRL11_SETUP      0x00000010  // Setup Packet
+#define USB_TXCSRL11_FLUSH      0x00000008  // Flush FIFO
+#define USB_TXCSRL11_ERROR      0x00000004  // Error
+#define USB_TXCSRL11_UNDRN      0x00000004  // Underrun
+#define USB_TXCSRL11_FIFONE     0x00000002  // FIFO Not Empty
+#define USB_TXCSRL11_TXRDY      0x00000001  // Transmit Packet Ready
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_TXCSRH11 register.
 //
 //*****************************************************************************
-#define USB_TXCSRH11_AUTOSET    0x00000080  // Auto Set.
-#define USB_TXCSRH11_ISO        0x00000040  // ISO.
-#define USB_TXCSRH11_MODE       0x00000020  // Mode.
-#define USB_TXCSRH11_DMAEN      0x00000010  // DMA Request Enable.
-#define USB_TXCSRH11_FDT        0x00000008  // Force Data Toggle.
-#define USB_TXCSRH11_DMAMOD     0x00000004  // DMA Request Mode.
-#define USB_TXCSRH11_DTWE       0x00000002  // Data Toggle Write Enable.
-#define USB_TXCSRH11_DT         0x00000001  // Data Toggle.
+#define USB_TXCSRH11_AUTOSET    0x00000080  // Auto Set
+#define USB_TXCSRH11_ISO        0x00000040  // Isochronous Transfers
+#define USB_TXCSRH11_MODE       0x00000020  // Mode
+#define USB_TXCSRH11_DMAEN      0x00000010  // DMA Request Enable
+#define USB_TXCSRH11_FDT        0x00000008  // Force Data Toggle
+#define USB_TXCSRH11_DMAMOD     0x00000004  // DMA Request Mode
+#define USB_TXCSRH11_DTWE       0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH11_DT         0x00000001  // Data Toggle
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXMAXP11 register.
 //
 //*****************************************************************************
-#define USB_RXMAXP11_MAXLOAD_M  0x000007FF  // Maximum Payload.
+#define USB_RXMAXP11_MAXLOAD_M  0x000007FF  // Maximum Payload
 #define USB_RXMAXP11_MAXLOAD_S  0
 
 //*****************************************************************************
@@ -8033,33 +8386,32 @@
 // The following are defines for the bit fields in the USB_O_RXCSRL11 register.
 //
 //*****************************************************************************
-#define USB_RXCSRL11_CLRDT      0x00000080  // Clear Data Toggle.
-#define USB_RXCSRL11_STALLED    0x00000040  // Endpoint Stalled.
-#define USB_RXCSRL11_STALL      0x00000020  // Send Stall.
-#define USB_RXCSRL11_REQPKT     0x00000020  // Request Packet.
-#define USB_RXCSRL11_FLUSH      0x00000010  // Flush FIFO.
-#define USB_RXCSRL11_DATAERR    0x00000008  // Data Error.
-#define USB_RXCSRL11_NAKTO      0x00000008  //  NAK Timeout.
-#define USB_RXCSRL11_OVER       0x00000004  // Overrun.
-#define USB_RXCSRL11_ERROR      0x00000004  // Error.
-#define USB_RXCSRL11_FULL       0x00000002  // FIFO Full.
-#define USB_RXCSRL11_RXRDY      0x00000001  // Receive Packet Ready.
+#define USB_RXCSRL11_CLRDT      0x00000080  // Clear Data Toggle
+#define USB_RXCSRL11_STALLED    0x00000040  // Endpoint Stalled
+#define USB_RXCSRL11_STALL      0x00000020  // Send STALL
+#define USB_RXCSRL11_REQPKT     0x00000020  // Request Packet
+#define USB_RXCSRL11_FLUSH      0x00000010  // Flush FIFO
+#define USB_RXCSRL11_DATAERR    0x00000008  // Data Error
+#define USB_RXCSRL11_NAKTO      0x00000008  // NAK Timeout
+#define USB_RXCSRL11_OVER       0x00000004  // Overrun
+#define USB_RXCSRL11_ERROR      0x00000004  // Error
+#define USB_RXCSRL11_FULL       0x00000002  // FIFO Full
+#define USB_RXCSRL11_RXRDY      0x00000001  // Receive Packet Ready
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXCSRH11 register.
 //
 //*****************************************************************************
-#define USB_RXCSRH11_AUTOCL     0x00000080  // Auto Clear.
-#define USB_RXCSRH11_ISO        0x00000040  // ISO.
-#define USB_RXCSRH11_AUTORQ     0x00000040  // Auto Request.
-#define USB_RXCSRH11_DMAEN      0x00000020  // DMA Request Enable.
-#define USB_RXCSRH11_DISNYET    0x00000010  // Disable NYET 
-#define USB_RXCSRH11_PIDERR     0x00000010  //  PID Error.
-#define USB_RXCSRH11_DMAMOD     0x00000008  // DMA Request Mode.
-#define USB_RXCSRH11_DTWE       0x00000004  // Data Toggle Write Enable.
-#define USB_RXCSRH11_DT         0x00000002  // Data Toggle.
-#define USB_RXCSRH11_INCRX      0x00000001  // Incomplete Receive.
+#define USB_RXCSRH11_AUTOCL     0x00000080  // Auto Clear
+#define USB_RXCSRH11_ISO        0x00000040  // Isochronous Transfers
+#define USB_RXCSRH11_AUTORQ     0x00000040  // Auto Request
+#define USB_RXCSRH11_DMAEN      0x00000020  // DMA Request Enable
+#define USB_RXCSRH11_DISNYET    0x00000010  // Disable NYET
+#define USB_RXCSRH11_PIDERR     0x00000010  // PID Error
+#define USB_RXCSRH11_DMAMOD     0x00000008  // DMA Request Mode
+#define USB_RXCSRH11_DTWE       0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH11_DT         0x00000002  // Data Toggle
 
 //*****************************************************************************
 //
@@ -8067,7 +8419,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RXCOUNT11_COUNT_M   0x00001FFF  // Receive Packet Count.
+#define USB_RXCOUNT11_COUNT_M   0x00001FFF  // Receive Packet Count
 #define USB_RXCOUNT11_COUNT_S   0
 
 //*****************************************************************************
@@ -8075,16 +8427,16 @@
 // The following are defines for the bit fields in the USB_O_TXTYPE11 register.
 //
 //*****************************************************************************
-#define USB_TXTYPE11_SPEED_M    0x000000C0  // Operating Speed.
+#define USB_TXTYPE11_SPEED_M    0x000000C0  // Operating Speed
 #define USB_TXTYPE11_SPEED_DFLT 0x00000000  // Default
 #define USB_TXTYPE11_SPEED_FULL 0x00000080  // Full
 #define USB_TXTYPE11_SPEED_LOW  0x000000C0  // Low
-#define USB_TXTYPE11_PROTO_M    0x00000030  // Protocol.
+#define USB_TXTYPE11_PROTO_M    0x00000030  // Protocol
 #define USB_TXTYPE11_PROTO_CTRL 0x00000000  // Control
 #define USB_TXTYPE11_PROTO_ISOC 0x00000010  // Isochronous
 #define USB_TXTYPE11_PROTO_BULK 0x00000020  // Bulk
 #define USB_TXTYPE11_PROTO_INT  0x00000030  // Interrupt
-#define USB_TXTYPE11_TEP_M      0x0000000F  // Target Endpoint Number.
+#define USB_TXTYPE11_TEP_M      0x0000000F  // Target Endpoint Number
 #define USB_TXTYPE11_TEP_S      0
 
 //*****************************************************************************
@@ -8094,9 +8446,9 @@
 //
 //*****************************************************************************
 #define USB_TXINTERVAL11_TXPOLL_M \
-                                0x000000FF  // TX Polling 
+                                0x000000FF  // TX Polling
 #define USB_TXINTERVAL11_NAKLMT_M \
-                                0x000000FF  //  NAK Limit.
+                                0x000000FF  // NAK Limit
 #define USB_TXINTERVAL11_NAKLMT_S \
                                 0
 #define USB_TXINTERVAL11_TXPOLL_S \
@@ -8107,16 +8459,16 @@
 // The following are defines for the bit fields in the USB_O_RXTYPE11 register.
 //
 //*****************************************************************************
-#define USB_RXTYPE11_SPEED_M    0x000000C0  // Operating Speed.
+#define USB_RXTYPE11_SPEED_M    0x000000C0  // Operating Speed
 #define USB_RXTYPE11_SPEED_DFLT 0x00000000  // Default
 #define USB_RXTYPE11_SPEED_FULL 0x00000080  // Full
 #define USB_RXTYPE11_SPEED_LOW  0x000000C0  // Low
-#define USB_RXTYPE11_PROTO_M    0x00000030  // Protocol.
+#define USB_RXTYPE11_PROTO_M    0x00000030  // Protocol
 #define USB_RXTYPE11_PROTO_CTRL 0x00000000  // Control
 #define USB_RXTYPE11_PROTO_ISOC 0x00000010  // Isochronous
 #define USB_RXTYPE11_PROTO_BULK 0x00000020  // Bulk
 #define USB_RXTYPE11_PROTO_INT  0x00000030  // Interrupt
-#define USB_RXTYPE11_TEP_M      0x0000000F  // Target Endpoint Number.
+#define USB_RXTYPE11_TEP_M      0x0000000F  // Target Endpoint Number
 #define USB_RXTYPE11_TEP_S      0
 
 //*****************************************************************************
@@ -8126,9 +8478,9 @@
 //
 //*****************************************************************************
 #define USB_RXINTERVAL11_NAKLMT_M \
-                                0x000000FF  //  NAK Limit.
+                                0x000000FF  // NAK Limit
 #define USB_RXINTERVAL11_TXPOLL_M \
-                                0x000000FF  // RX Polling 
+                                0x000000FF  // RX Polling
 #define USB_RXINTERVAL11_TXPOLL_S \
                                 0
 #define USB_RXINTERVAL11_NAKLMT_S \
@@ -8139,7 +8491,7 @@
 // The following are defines for the bit fields in the USB_O_TXMAXP12 register.
 //
 //*****************************************************************************
-#define USB_TXMAXP12_MAXLOAD_M  0x000007FF  // Maximum Payload.
+#define USB_TXMAXP12_MAXLOAD_M  0x000007FF  // Maximum Payload
 #define USB_TXMAXP12_MAXLOAD_S  0
 
 //*****************************************************************************
@@ -8147,38 +8499,37 @@
 // The following are defines for the bit fields in the USB_O_TXCSRL12 register.
 //
 //*****************************************************************************
-#define USB_TXCSRL12_INCTX      0x00000080  // Incomplete Transmit.
-#define USB_TXCSRL12_NAKTO      0x00000080  // NAK Timeout 
-#define USB_TXCSRL12_CLRDT      0x00000040  // Clear Data Toggle.
-#define USB_TXCSRL12_STALLED    0x00000020  // Endpoint Stalled.
-#define USB_TXCSRL12_SETUP      0x00000010  // Setup Packet.
-#define USB_TXCSRL12_STALL      0x00000010  // Send Stall.
-#define USB_TXCSRL12_FLUSH      0x00000008  // Flush FIFO.
-#define USB_TXCSRL12_UNDRN      0x00000004  // Underrun.
-#define USB_TXCSRL12_ERROR      0x00000004  // Error.
-#define USB_TXCSRL12_FIFONE     0x00000002  // FIFO Not Empty.
-#define USB_TXCSRL12_TXRDY      0x00000001  // Transmit Packet Ready.
+#define USB_TXCSRL12_NAKTO      0x00000080  // NAK Timeout
+#define USB_TXCSRL12_CLRDT      0x00000040  // Clear Data Toggle
+#define USB_TXCSRL12_STALLED    0x00000020  // Endpoint Stalled
+#define USB_TXCSRL12_SETUP      0x00000010  // Setup Packet
+#define USB_TXCSRL12_STALL      0x00000010  // Send STALL
+#define USB_TXCSRL12_FLUSH      0x00000008  // Flush FIFO
+#define USB_TXCSRL12_UNDRN      0x00000004  // Underrun
+#define USB_TXCSRL12_ERROR      0x00000004  // Error
+#define USB_TXCSRL12_FIFONE     0x00000002  // FIFO Not Empty
+#define USB_TXCSRL12_TXRDY      0x00000001  // Transmit Packet Ready
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_TXCSRH12 register.
 //
 //*****************************************************************************
-#define USB_TXCSRH12_AUTOSET    0x00000080  // Auto Set.
-#define USB_TXCSRH12_ISO        0x00000040  // ISO.
-#define USB_TXCSRH12_MODE       0x00000020  // Mode.
-#define USB_TXCSRH12_DMAEN      0x00000010  // DMA Request Enable.
-#define USB_TXCSRH12_FDT        0x00000008  // Force Data Toggle.
-#define USB_TXCSRH12_DMAMOD     0x00000004  // DMA Request Mode.
-#define USB_TXCSRH12_DTWE       0x00000002  // Data Toggle Write Enable.
-#define USB_TXCSRH12_DT         0x00000001  // Data Toggle.
+#define USB_TXCSRH12_AUTOSET    0x00000080  // Auto Set
+#define USB_TXCSRH12_ISO        0x00000040  // Isochronous Transfers
+#define USB_TXCSRH12_MODE       0x00000020  // Mode
+#define USB_TXCSRH12_DMAEN      0x00000010  // DMA Request Enable
+#define USB_TXCSRH12_FDT        0x00000008  // Force Data Toggle
+#define USB_TXCSRH12_DMAMOD     0x00000004  // DMA Request Mode
+#define USB_TXCSRH12_DTWE       0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH12_DT         0x00000001  // Data Toggle
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXMAXP12 register.
 //
 //*****************************************************************************
-#define USB_RXMAXP12_MAXLOAD_M  0x000007FF  // Maximum Payload.
+#define USB_RXMAXP12_MAXLOAD_M  0x000007FF  // Maximum Payload
 #define USB_RXMAXP12_MAXLOAD_S  0
 
 //*****************************************************************************
@@ -8186,33 +8537,32 @@
 // The following are defines for the bit fields in the USB_O_RXCSRL12 register.
 //
 //*****************************************************************************
-#define USB_RXCSRL12_CLRDT      0x00000080  // Clear Data Toggle.
-#define USB_RXCSRL12_STALLED    0x00000040  // Endpoint Stalled.
-#define USB_RXCSRL12_STALL      0x00000020  // Send Stall.
-#define USB_RXCSRL12_REQPKT     0x00000020  // Request Packet.
-#define USB_RXCSRL12_FLUSH      0x00000010  // Flush FIFO.
-#define USB_RXCSRL12_NAKTO      0x00000008  //  NAK Timeout.
-#define USB_RXCSRL12_DATAERR    0x00000008  // Data Error.
-#define USB_RXCSRL12_ERROR      0x00000004  // Error.
-#define USB_RXCSRL12_OVER       0x00000004  // Overrun.
-#define USB_RXCSRL12_FULL       0x00000002  // FIFO Full.
-#define USB_RXCSRL12_RXRDY      0x00000001  // Receive Packet Ready.
+#define USB_RXCSRL12_CLRDT      0x00000080  // Clear Data Toggle
+#define USB_RXCSRL12_STALLED    0x00000040  // Endpoint Stalled
+#define USB_RXCSRL12_STALL      0x00000020  // Send STALL
+#define USB_RXCSRL12_REQPKT     0x00000020  // Request Packet
+#define USB_RXCSRL12_FLUSH      0x00000010  // Flush FIFO
+#define USB_RXCSRL12_NAKTO      0x00000008  // NAK Timeout
+#define USB_RXCSRL12_DATAERR    0x00000008  // Data Error
+#define USB_RXCSRL12_ERROR      0x00000004  // Error
+#define USB_RXCSRL12_OVER       0x00000004  // Overrun
+#define USB_RXCSRL12_FULL       0x00000002  // FIFO Full
+#define USB_RXCSRL12_RXRDY      0x00000001  // Receive Packet Ready
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXCSRH12 register.
 //
 //*****************************************************************************
-#define USB_RXCSRH12_AUTOCL     0x00000080  // Auto Clear.
-#define USB_RXCSRH12_ISO        0x00000040  // ISO.
-#define USB_RXCSRH12_AUTORQ     0x00000040  // Auto Request.
-#define USB_RXCSRH12_DMAEN      0x00000020  // DMA Request Enable.
-#define USB_RXCSRH12_PIDERR     0x00000010  //  PID Error.
-#define USB_RXCSRH12_DISNYET    0x00000010  // Disable NYET 
-#define USB_RXCSRH12_DMAMOD     0x00000008  // DMA Request Mode.
-#define USB_RXCSRH12_DTWE       0x00000004  // Data Toggle Write Enable.
-#define USB_RXCSRH12_DT         0x00000002  // Data Toggle.
-#define USB_RXCSRH12_INCRX      0x00000001  // Incomplete Receive.
+#define USB_RXCSRH12_AUTOCL     0x00000080  // Auto Clear
+#define USB_RXCSRH12_ISO        0x00000040  // Isochronous Transfers
+#define USB_RXCSRH12_AUTORQ     0x00000040  // Auto Request
+#define USB_RXCSRH12_DMAEN      0x00000020  // DMA Request Enable
+#define USB_RXCSRH12_PIDERR     0x00000010  // PID Error
+#define USB_RXCSRH12_DISNYET    0x00000010  // Disable NYET
+#define USB_RXCSRH12_DMAMOD     0x00000008  // DMA Request Mode
+#define USB_RXCSRH12_DTWE       0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH12_DT         0x00000002  // Data Toggle
 
 //*****************************************************************************
 //
@@ -8220,7 +8570,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RXCOUNT12_COUNT_M   0x00001FFF  // Receive Packet Count.
+#define USB_RXCOUNT12_COUNT_M   0x00001FFF  // Receive Packet Count
 #define USB_RXCOUNT12_COUNT_S   0
 
 //*****************************************************************************
@@ -8228,16 +8578,16 @@
 // The following are defines for the bit fields in the USB_O_TXTYPE12 register.
 //
 //*****************************************************************************
-#define USB_TXTYPE12_SPEED_M    0x000000C0  // Operating Speed.
+#define USB_TXTYPE12_SPEED_M    0x000000C0  // Operating Speed
 #define USB_TXTYPE12_SPEED_DFLT 0x00000000  // Default
 #define USB_TXTYPE12_SPEED_FULL 0x00000080  // Full
 #define USB_TXTYPE12_SPEED_LOW  0x000000C0  // Low
-#define USB_TXTYPE12_PROTO_M    0x00000030  // Protocol.
+#define USB_TXTYPE12_PROTO_M    0x00000030  // Protocol
 #define USB_TXTYPE12_PROTO_CTRL 0x00000000  // Control
 #define USB_TXTYPE12_PROTO_ISOC 0x00000010  // Isochronous
 #define USB_TXTYPE12_PROTO_BULK 0x00000020  // Bulk
 #define USB_TXTYPE12_PROTO_INT  0x00000030  // Interrupt
-#define USB_TXTYPE12_TEP_M      0x0000000F  // Target Endpoint Number.
+#define USB_TXTYPE12_TEP_M      0x0000000F  // Target Endpoint Number
 #define USB_TXTYPE12_TEP_S      0
 
 //*****************************************************************************
@@ -8247,9 +8597,9 @@
 //
 //*****************************************************************************
 #define USB_TXINTERVAL12_TXPOLL_M \
-                                0x000000FF  // TX Polling 
+                                0x000000FF  // TX Polling
 #define USB_TXINTERVAL12_NAKLMT_M \
-                                0x000000FF  //  NAK Limit.
+                                0x000000FF  // NAK Limit
 #define USB_TXINTERVAL12_TXPOLL_S \
                                 0
 #define USB_TXINTERVAL12_NAKLMT_S \
@@ -8260,16 +8610,16 @@
 // The following are defines for the bit fields in the USB_O_RXTYPE12 register.
 //
 //*****************************************************************************
-#define USB_RXTYPE12_SPEED_M    0x000000C0  // Operating Speed.
+#define USB_RXTYPE12_SPEED_M    0x000000C0  // Operating Speed
 #define USB_RXTYPE12_SPEED_DFLT 0x00000000  // Default
 #define USB_RXTYPE12_SPEED_FULL 0x00000080  // Full
 #define USB_RXTYPE12_SPEED_LOW  0x000000C0  // Low
-#define USB_RXTYPE12_PROTO_M    0x00000030  // Protocol.
+#define USB_RXTYPE12_PROTO_M    0x00000030  // Protocol
 #define USB_RXTYPE12_PROTO_CTRL 0x00000000  // Control
 #define USB_RXTYPE12_PROTO_ISOC 0x00000010  // Isochronous
 #define USB_RXTYPE12_PROTO_BULK 0x00000020  // Bulk
 #define USB_RXTYPE12_PROTO_INT  0x00000030  // Interrupt
-#define USB_RXTYPE12_TEP_M      0x0000000F  // Target Endpoint Number.
+#define USB_RXTYPE12_TEP_M      0x0000000F  // Target Endpoint Number
 #define USB_RXTYPE12_TEP_S      0
 
 //*****************************************************************************
@@ -8279,9 +8629,9 @@
 //
 //*****************************************************************************
 #define USB_RXINTERVAL12_NAKLMT_M \
-                                0x000000FF  //  NAK Limit.
+                                0x000000FF  // NAK Limit
 #define USB_RXINTERVAL12_TXPOLL_M \
-                                0x000000FF  // RX Polling 
+                                0x000000FF  // RX Polling
 #define USB_RXINTERVAL12_NAKLMT_S \
                                 0
 #define USB_RXINTERVAL12_TXPOLL_S \
@@ -8292,7 +8642,7 @@
 // The following are defines for the bit fields in the USB_O_TXMAXP13 register.
 //
 //*****************************************************************************
-#define USB_TXMAXP13_MAXLOAD_M  0x000007FF  // Maximum Payload.
+#define USB_TXMAXP13_MAXLOAD_M  0x000007FF  // Maximum Payload
 #define USB_TXMAXP13_MAXLOAD_S  0
 
 //*****************************************************************************
@@ -8300,38 +8650,37 @@
 // The following are defines for the bit fields in the USB_O_TXCSRL13 register.
 //
 //*****************************************************************************
-#define USB_TXCSRL13_NAKTO      0x00000080  // NAK Timeout 
-#define USB_TXCSRL13_INCTX      0x00000080  // Incomplete Transmit.
-#define USB_TXCSRL13_CLRDT      0x00000040  // Clear Data Toggle.
-#define USB_TXCSRL13_STALLED    0x00000020  // Endpoint Stalled.
-#define USB_TXCSRL13_SETUP      0x00000010  // Setup Packet.
-#define USB_TXCSRL13_STALL      0x00000010  // Send Stall.
-#define USB_TXCSRL13_FLUSH      0x00000008  // Flush FIFO.
-#define USB_TXCSRL13_UNDRN      0x00000004  // Underrun.
-#define USB_TXCSRL13_ERROR      0x00000004  // Error.
-#define USB_TXCSRL13_FIFONE     0x00000002  // FIFO Not Empty.
-#define USB_TXCSRL13_TXRDY      0x00000001  // Transmit Packet Ready.
+#define USB_TXCSRL13_NAKTO      0x00000080  // NAK Timeout
+#define USB_TXCSRL13_CLRDT      0x00000040  // Clear Data Toggle
+#define USB_TXCSRL13_STALLED    0x00000020  // Endpoint Stalled
+#define USB_TXCSRL13_SETUP      0x00000010  // Setup Packet
+#define USB_TXCSRL13_STALL      0x00000010  // Send STALL
+#define USB_TXCSRL13_FLUSH      0x00000008  // Flush FIFO
+#define USB_TXCSRL13_UNDRN      0x00000004  // Underrun
+#define USB_TXCSRL13_ERROR      0x00000004  // Error
+#define USB_TXCSRL13_FIFONE     0x00000002  // FIFO Not Empty
+#define USB_TXCSRL13_TXRDY      0x00000001  // Transmit Packet Ready
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_TXCSRH13 register.
 //
 //*****************************************************************************
-#define USB_TXCSRH13_AUTOSET    0x00000080  // Auto Set.
-#define USB_TXCSRH13_ISO        0x00000040  // ISO.
-#define USB_TXCSRH13_MODE       0x00000020  // Mode.
-#define USB_TXCSRH13_DMAEN      0x00000010  // DMA Request Enable.
-#define USB_TXCSRH13_FDT        0x00000008  // Force Data Toggle.
-#define USB_TXCSRH13_DMAMOD     0x00000004  // DMA Request Mode.
-#define USB_TXCSRH13_DTWE       0x00000002  // Data Toggle Write Enable.
-#define USB_TXCSRH13_DT         0x00000001  // Data Toggle.
+#define USB_TXCSRH13_AUTOSET    0x00000080  // Auto Set
+#define USB_TXCSRH13_ISO        0x00000040  // Isochronous Transfers
+#define USB_TXCSRH13_MODE       0x00000020  // Mode
+#define USB_TXCSRH13_DMAEN      0x00000010  // DMA Request Enable
+#define USB_TXCSRH13_FDT        0x00000008  // Force Data Toggle
+#define USB_TXCSRH13_DMAMOD     0x00000004  // DMA Request Mode
+#define USB_TXCSRH13_DTWE       0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH13_DT         0x00000001  // Data Toggle
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXMAXP13 register.
 //
 //*****************************************************************************
-#define USB_RXMAXP13_MAXLOAD_M  0x000007FF  // Maximum Payload.
+#define USB_RXMAXP13_MAXLOAD_M  0x000007FF  // Maximum Payload
 #define USB_RXMAXP13_MAXLOAD_S  0
 
 //*****************************************************************************
@@ -8339,33 +8688,32 @@
 // The following are defines for the bit fields in the USB_O_RXCSRL13 register.
 //
 //*****************************************************************************
-#define USB_RXCSRL13_CLRDT      0x00000080  // Clear Data Toggle.
-#define USB_RXCSRL13_STALLED    0x00000040  // Endpoint Stalled.
-#define USB_RXCSRL13_REQPKT     0x00000020  // Request Packet.
-#define USB_RXCSRL13_STALL      0x00000020  // Send Stall.
-#define USB_RXCSRL13_FLUSH      0x00000010  // Flush FIFO.
-#define USB_RXCSRL13_NAKTO      0x00000008  //  NAK Timeout.
-#define USB_RXCSRL13_DATAERR    0x00000008  // Data Error.
-#define USB_RXCSRL13_OVER       0x00000004  // Overrun.
-#define USB_RXCSRL13_ERROR      0x00000004  // Error.
-#define USB_RXCSRL13_FULL       0x00000002  // FIFO Full.
-#define USB_RXCSRL13_RXRDY      0x00000001  // Receive Packet Ready.
+#define USB_RXCSRL13_CLRDT      0x00000080  // Clear Data Toggle
+#define USB_RXCSRL13_STALLED    0x00000040  // Endpoint Stalled
+#define USB_RXCSRL13_REQPKT     0x00000020  // Request Packet
+#define USB_RXCSRL13_STALL      0x00000020  // Send STALL
+#define USB_RXCSRL13_FLUSH      0x00000010  // Flush FIFO
+#define USB_RXCSRL13_NAKTO      0x00000008  // NAK Timeout
+#define USB_RXCSRL13_DATAERR    0x00000008  // Data Error
+#define USB_RXCSRL13_OVER       0x00000004  // Overrun
+#define USB_RXCSRL13_ERROR      0x00000004  // Error
+#define USB_RXCSRL13_FULL       0x00000002  // FIFO Full
+#define USB_RXCSRL13_RXRDY      0x00000001  // Receive Packet Ready
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXCSRH13 register.
 //
 //*****************************************************************************
-#define USB_RXCSRH13_AUTOCL     0x00000080  // Auto Clear.
-#define USB_RXCSRH13_ISO        0x00000040  // ISO.
-#define USB_RXCSRH13_AUTORQ     0x00000040  // Auto Request.
-#define USB_RXCSRH13_DMAEN      0x00000020  // DMA Request Enable.
-#define USB_RXCSRH13_DISNYET    0x00000010  // Disable NYET 
-#define USB_RXCSRH13_PIDERR     0x00000010  //  PID Error.
-#define USB_RXCSRH13_DMAMOD     0x00000008  // DMA Request Mode.
-#define USB_RXCSRH13_DTWE       0x00000004  // Data Toggle Write Enable.
-#define USB_RXCSRH13_DT         0x00000002  // Data Toggle.
-#define USB_RXCSRH13_INCRX      0x00000001  // Incomplete Receive.
+#define USB_RXCSRH13_AUTOCL     0x00000080  // Auto Clear
+#define USB_RXCSRH13_ISO        0x00000040  // Isochronous Transfers
+#define USB_RXCSRH13_AUTORQ     0x00000040  // Auto Request
+#define USB_RXCSRH13_DMAEN      0x00000020  // DMA Request Enable
+#define USB_RXCSRH13_DISNYET    0x00000010  // Disable NYET
+#define USB_RXCSRH13_PIDERR     0x00000010  // PID Error
+#define USB_RXCSRH13_DMAMOD     0x00000008  // DMA Request Mode
+#define USB_RXCSRH13_DTWE       0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH13_DT         0x00000002  // Data Toggle
 
 //*****************************************************************************
 //
@@ -8373,7 +8721,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RXCOUNT13_COUNT_M   0x00001FFF  // Receive Packet Count.
+#define USB_RXCOUNT13_COUNT_M   0x00001FFF  // Receive Packet Count
 #define USB_RXCOUNT13_COUNT_S   0
 
 //*****************************************************************************
@@ -8381,16 +8729,16 @@
 // The following are defines for the bit fields in the USB_O_TXTYPE13 register.
 //
 //*****************************************************************************
-#define USB_TXTYPE13_SPEED_M    0x000000C0  // Operating Speed.
+#define USB_TXTYPE13_SPEED_M    0x000000C0  // Operating Speed
 #define USB_TXTYPE13_SPEED_DFLT 0x00000000  // Default
 #define USB_TXTYPE13_SPEED_FULL 0x00000080  // Full
 #define USB_TXTYPE13_SPEED_LOW  0x000000C0  // Low
-#define USB_TXTYPE13_PROTO_M    0x00000030  // Protocol.
+#define USB_TXTYPE13_PROTO_M    0x00000030  // Protocol
 #define USB_TXTYPE13_PROTO_CTRL 0x00000000  // Control
 #define USB_TXTYPE13_PROTO_ISOC 0x00000010  // Isochronous
 #define USB_TXTYPE13_PROTO_BULK 0x00000020  // Bulk
 #define USB_TXTYPE13_PROTO_INT  0x00000030  // Interrupt
-#define USB_TXTYPE13_TEP_M      0x0000000F  // Target Endpoint Number.
+#define USB_TXTYPE13_TEP_M      0x0000000F  // Target Endpoint Number
 #define USB_TXTYPE13_TEP_S      0
 
 //*****************************************************************************
@@ -8400,9 +8748,9 @@
 //
 //*****************************************************************************
 #define USB_TXINTERVAL13_NAKLMT_M \
-                                0x000000FF  //  NAK Limit.
+                                0x000000FF  // NAK Limit
 #define USB_TXINTERVAL13_TXPOLL_M \
-                                0x000000FF  // TX Polling 
+                                0x000000FF  // TX Polling
 #define USB_TXINTERVAL13_TXPOLL_S \
                                 0
 #define USB_TXINTERVAL13_NAKLMT_S \
@@ -8413,16 +8761,16 @@
 // The following are defines for the bit fields in the USB_O_RXTYPE13 register.
 //
 //*****************************************************************************
-#define USB_RXTYPE13_SPEED_M    0x000000C0  // Operating Speed.
+#define USB_RXTYPE13_SPEED_M    0x000000C0  // Operating Speed
 #define USB_RXTYPE13_SPEED_DFLT 0x00000000  // Default
 #define USB_RXTYPE13_SPEED_FULL 0x00000080  // Full
 #define USB_RXTYPE13_SPEED_LOW  0x000000C0  // Low
-#define USB_RXTYPE13_PROTO_M    0x00000030  // Protocol.
+#define USB_RXTYPE13_PROTO_M    0x00000030  // Protocol
 #define USB_RXTYPE13_PROTO_CTRL 0x00000000  // Control
 #define USB_RXTYPE13_PROTO_ISOC 0x00000010  // Isochronous
 #define USB_RXTYPE13_PROTO_BULK 0x00000020  // Bulk
 #define USB_RXTYPE13_PROTO_INT  0x00000030  // Interrupt
-#define USB_RXTYPE13_TEP_M      0x0000000F  // Target Endpoint Number.
+#define USB_RXTYPE13_TEP_M      0x0000000F  // Target Endpoint Number
 #define USB_RXTYPE13_TEP_S      0
 
 //*****************************************************************************
@@ -8432,20 +8780,20 @@
 //
 //*****************************************************************************
 #define USB_RXINTERVAL13_TXPOLL_M \
-                                0x000000FF  // RX Polling 
+                                0x000000FF  // RX Polling
 #define USB_RXINTERVAL13_NAKLMT_M \
-                                0x000000FF  //  NAK Limit.
-#define USB_RXINTERVAL13_NAKLMT_S \
-                                0
+                                0x000000FF  // NAK Limit
 #define USB_RXINTERVAL13_TXPOLL_S \
                                 0
+#define USB_RXINTERVAL13_NAKLMT_S \
+                                0
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_TXMAXP14 register.
 //
 //*****************************************************************************
-#define USB_TXMAXP14_MAXLOAD_M  0x000007FF  // Maximum Payload.
+#define USB_TXMAXP14_MAXLOAD_M  0x000007FF  // Maximum Payload
 #define USB_TXMAXP14_MAXLOAD_S  0
 
 //*****************************************************************************
@@ -8453,38 +8801,37 @@
 // The following are defines for the bit fields in the USB_O_TXCSRL14 register.
 //
 //*****************************************************************************
-#define USB_TXCSRL14_NAKTO      0x00000080  // NAK Timeout 
-#define USB_TXCSRL14_INCTX      0x00000080  // Incomplete Transmit.
-#define USB_TXCSRL14_CLRDT      0x00000040  // Clear Data Toggle.
-#define USB_TXCSRL14_STALLED    0x00000020  // Endpoint Stalled.
-#define USB_TXCSRL14_STALL      0x00000010  // Send Stall.
-#define USB_TXCSRL14_SETUP      0x00000010  // Setup Packet.
-#define USB_TXCSRL14_FLUSH      0x00000008  // Flush FIFO.
-#define USB_TXCSRL14_ERROR      0x00000004  // Error.
-#define USB_TXCSRL14_UNDRN      0x00000004  // Underrun.
-#define USB_TXCSRL14_FIFONE     0x00000002  // FIFO Not Empty.
-#define USB_TXCSRL14_TXRDY      0x00000001  // Transmit Packet Ready.
+#define USB_TXCSRL14_NAKTO      0x00000080  // NAK Timeout
+#define USB_TXCSRL14_CLRDT      0x00000040  // Clear Data Toggle
+#define USB_TXCSRL14_STALLED    0x00000020  // Endpoint Stalled
+#define USB_TXCSRL14_STALL      0x00000010  // Send STALL
+#define USB_TXCSRL14_SETUP      0x00000010  // Setup Packet
+#define USB_TXCSRL14_FLUSH      0x00000008  // Flush FIFO
+#define USB_TXCSRL14_ERROR      0x00000004  // Error
+#define USB_TXCSRL14_UNDRN      0x00000004  // Underrun
+#define USB_TXCSRL14_FIFONE     0x00000002  // FIFO Not Empty
+#define USB_TXCSRL14_TXRDY      0x00000001  // Transmit Packet Ready
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_TXCSRH14 register.
 //
 //*****************************************************************************
-#define USB_TXCSRH14_AUTOSET    0x00000080  // Auto Set.
-#define USB_TXCSRH14_ISO        0x00000040  // ISO.
-#define USB_TXCSRH14_MODE       0x00000020  // Mode.
-#define USB_TXCSRH14_DMAEN      0x00000010  // DMA Request Enable.
-#define USB_TXCSRH14_FDT        0x00000008  // Force Data Toggle.
-#define USB_TXCSRH14_DMAMOD     0x00000004  // DMA Request Mode.
-#define USB_TXCSRH14_DTWE       0x00000002  // Data Toggle Write Enable.
-#define USB_TXCSRH14_DT         0x00000001  // Data Toggle.
+#define USB_TXCSRH14_AUTOSET    0x00000080  // Auto Set
+#define USB_TXCSRH14_ISO        0x00000040  // Isochronous Transfers
+#define USB_TXCSRH14_MODE       0x00000020  // Mode
+#define USB_TXCSRH14_DMAEN      0x00000010  // DMA Request Enable
+#define USB_TXCSRH14_FDT        0x00000008  // Force Data Toggle
+#define USB_TXCSRH14_DMAMOD     0x00000004  // DMA Request Mode
+#define USB_TXCSRH14_DTWE       0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH14_DT         0x00000001  // Data Toggle
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXMAXP14 register.
 //
 //*****************************************************************************
-#define USB_RXMAXP14_MAXLOAD_M  0x000007FF  // Maximum Payload.
+#define USB_RXMAXP14_MAXLOAD_M  0x000007FF  // Maximum Payload
 #define USB_RXMAXP14_MAXLOAD_S  0
 
 //*****************************************************************************
@@ -8492,33 +8839,32 @@
 // The following are defines for the bit fields in the USB_O_RXCSRL14 register.
 //
 //*****************************************************************************
-#define USB_RXCSRL14_CLRDT      0x00000080  // Clear Data Toggle.
-#define USB_RXCSRL14_STALLED    0x00000040  // Endpoint Stalled.
-#define USB_RXCSRL14_REQPKT     0x00000020  // Request Packet.
-#define USB_RXCSRL14_STALL      0x00000020  // Send Stall.
-#define USB_RXCSRL14_FLUSH      0x00000010  // Flush FIFO.
-#define USB_RXCSRL14_DATAERR    0x00000008  // Data Error.
-#define USB_RXCSRL14_NAKTO      0x00000008  //  NAK Timeout.
-#define USB_RXCSRL14_OVER       0x00000004  // Overrun.
-#define USB_RXCSRL14_ERROR      0x00000004  // Error.
-#define USB_RXCSRL14_FULL       0x00000002  // FIFO Full.
-#define USB_RXCSRL14_RXRDY      0x00000001  // Receive Packet Ready.
+#define USB_RXCSRL14_CLRDT      0x00000080  // Clear Data Toggle
+#define USB_RXCSRL14_STALLED    0x00000040  // Endpoint Stalled
+#define USB_RXCSRL14_REQPKT     0x00000020  // Request Packet
+#define USB_RXCSRL14_STALL      0x00000020  // Send STALL
+#define USB_RXCSRL14_FLUSH      0x00000010  // Flush FIFO
+#define USB_RXCSRL14_DATAERR    0x00000008  // Data Error
+#define USB_RXCSRL14_NAKTO      0x00000008  // NAK Timeout
+#define USB_RXCSRL14_OVER       0x00000004  // Overrun
+#define USB_RXCSRL14_ERROR      0x00000004  // Error
+#define USB_RXCSRL14_FULL       0x00000002  // FIFO Full
+#define USB_RXCSRL14_RXRDY      0x00000001  // Receive Packet Ready
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXCSRH14 register.
 //
 //*****************************************************************************
-#define USB_RXCSRH14_AUTOCL     0x00000080  // Auto Clear.
-#define USB_RXCSRH14_AUTORQ     0x00000040  // Auto Request.
-#define USB_RXCSRH14_ISO        0x00000040  // ISO.
-#define USB_RXCSRH14_DMAEN      0x00000020  // DMA Request Enable.
-#define USB_RXCSRH14_PIDERR     0x00000010  //  PID Error.
-#define USB_RXCSRH14_DISNYET    0x00000010  // Disable NYET 
-#define USB_RXCSRH14_DMAMOD     0x00000008  // DMA Request Mode.
-#define USB_RXCSRH14_DTWE       0x00000004  // Data Toggle Write Enable.
-#define USB_RXCSRH14_DT         0x00000002  // Data Toggle.
-#define USB_RXCSRH14_INCRX      0x00000001  // Incomplete Receive.
+#define USB_RXCSRH14_AUTOCL     0x00000080  // Auto Clear
+#define USB_RXCSRH14_AUTORQ     0x00000040  // Auto Request
+#define USB_RXCSRH14_ISO        0x00000040  // Isochronous Transfers
+#define USB_RXCSRH14_DMAEN      0x00000020  // DMA Request Enable
+#define USB_RXCSRH14_PIDERR     0x00000010  // PID Error
+#define USB_RXCSRH14_DISNYET    0x00000010  // Disable NYET
+#define USB_RXCSRH14_DMAMOD     0x00000008  // DMA Request Mode
+#define USB_RXCSRH14_DTWE       0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH14_DT         0x00000002  // Data Toggle
 
 //*****************************************************************************
 //
@@ -8526,7 +8872,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RXCOUNT14_COUNT_M   0x00001FFF  // Receive Packet Count.
+#define USB_RXCOUNT14_COUNT_M   0x00001FFF  // Receive Packet Count
 #define USB_RXCOUNT14_COUNT_S   0
 
 //*****************************************************************************
@@ -8534,16 +8880,16 @@
 // The following are defines for the bit fields in the USB_O_TXTYPE14 register.
 //
 //*****************************************************************************
-#define USB_TXTYPE14_SPEED_M    0x000000C0  // Operating Speed.
+#define USB_TXTYPE14_SPEED_M    0x000000C0  // Operating Speed
 #define USB_TXTYPE14_SPEED_DFLT 0x00000000  // Default
 #define USB_TXTYPE14_SPEED_FULL 0x00000080  // Full
 #define USB_TXTYPE14_SPEED_LOW  0x000000C0  // Low
-#define USB_TXTYPE14_PROTO_M    0x00000030  // Protocol.
+#define USB_TXTYPE14_PROTO_M    0x00000030  // Protocol
 #define USB_TXTYPE14_PROTO_CTRL 0x00000000  // Control
 #define USB_TXTYPE14_PROTO_ISOC 0x00000010  // Isochronous
 #define USB_TXTYPE14_PROTO_BULK 0x00000020  // Bulk
 #define USB_TXTYPE14_PROTO_INT  0x00000030  // Interrupt
-#define USB_TXTYPE14_TEP_M      0x0000000F  // Target Endpoint Number.
+#define USB_TXTYPE14_TEP_M      0x0000000F  // Target Endpoint Number
 #define USB_TXTYPE14_TEP_S      0
 
 //*****************************************************************************
@@ -8552,10 +8898,10 @@
 // register.
 //
 //*****************************************************************************
-#define USB_TXINTERVAL14_NAKLMT_M \
-                                0x000000FF  //  NAK Limit.
 #define USB_TXINTERVAL14_TXPOLL_M \
-                                0x000000FF  // TX Polling 
+                                0x000000FF  // TX Polling
+#define USB_TXINTERVAL14_NAKLMT_M \
+                                0x000000FF  // NAK Limit
 #define USB_TXINTERVAL14_TXPOLL_S \
                                 0
 #define USB_TXINTERVAL14_NAKLMT_S \
@@ -8566,16 +8912,16 @@
 // The following are defines for the bit fields in the USB_O_RXTYPE14 register.
 //
 //*****************************************************************************
-#define USB_RXTYPE14_SPEED_M    0x000000C0  // Operating Speed.
+#define USB_RXTYPE14_SPEED_M    0x000000C0  // Operating Speed
 #define USB_RXTYPE14_SPEED_DFLT 0x00000000  // Default
 #define USB_RXTYPE14_SPEED_FULL 0x00000080  // Full
 #define USB_RXTYPE14_SPEED_LOW  0x000000C0  // Low
-#define USB_RXTYPE14_PROTO_M    0x00000030  // Protocol.
+#define USB_RXTYPE14_PROTO_M    0x00000030  // Protocol
 #define USB_RXTYPE14_PROTO_CTRL 0x00000000  // Control
 #define USB_RXTYPE14_PROTO_ISOC 0x00000010  // Isochronous
 #define USB_RXTYPE14_PROTO_BULK 0x00000020  // Bulk
 #define USB_RXTYPE14_PROTO_INT  0x00000030  // Interrupt
-#define USB_RXTYPE14_TEP_M      0x0000000F  // Target Endpoint Number.
+#define USB_RXTYPE14_TEP_M      0x0000000F  // Target Endpoint Number
 #define USB_RXTYPE14_TEP_S      0
 
 //*****************************************************************************
@@ -8584,21 +8930,21 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RXINTERVAL14_NAKLMT_M \
-                                0x000000FF  //  NAK Limit.
 #define USB_RXINTERVAL14_TXPOLL_M \
-                                0x000000FF  // RX Polling 
-#define USB_RXINTERVAL14_NAKLMT_S \
-                                0
+                                0x000000FF  // RX Polling
+#define USB_RXINTERVAL14_NAKLMT_M \
+                                0x000000FF  // NAK Limit
 #define USB_RXINTERVAL14_TXPOLL_S \
                                 0
+#define USB_RXINTERVAL14_NAKLMT_S \
+                                0
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_TXMAXP15 register.
 //
 //*****************************************************************************
-#define USB_TXMAXP15_MAXLOAD_M  0x000007FF  // Maximum Payload.
+#define USB_TXMAXP15_MAXLOAD_M  0x000007FF  // Maximum Payload
 #define USB_TXMAXP15_MAXLOAD_S  0
 
 //*****************************************************************************
@@ -8606,38 +8952,37 @@
 // The following are defines for the bit fields in the USB_O_TXCSRL15 register.
 //
 //*****************************************************************************
-#define USB_TXCSRL15_NAKTO      0x00000080  // NAK Timeout 
-#define USB_TXCSRL15_INCTX      0x00000080  // Incomplete Transmit.
-#define USB_TXCSRL15_CLRDT      0x00000040  // Clear Data Toggle.
-#define USB_TXCSRL15_STALLED    0x00000020  // Endpoint Stalled.
-#define USB_TXCSRL15_SETUP      0x00000010  // Setup Packet.
-#define USB_TXCSRL15_STALL      0x00000010  // Send Stall.
-#define USB_TXCSRL15_FLUSH      0x00000008  // Flush FIFO.
-#define USB_TXCSRL15_UNDRN      0x00000004  // Underrun.
-#define USB_TXCSRL15_ERROR      0x00000004  // Error.
-#define USB_TXCSRL15_FIFONE     0x00000002  // FIFO Not Empty.
-#define USB_TXCSRL15_TXRDY      0x00000001  // Transmit Packet Ready.
+#define USB_TXCSRL15_NAKTO      0x00000080  // NAK Timeout
+#define USB_TXCSRL15_CLRDT      0x00000040  // Clear Data Toggle
+#define USB_TXCSRL15_STALLED    0x00000020  // Endpoint Stalled
+#define USB_TXCSRL15_SETUP      0x00000010  // Setup Packet
+#define USB_TXCSRL15_STALL      0x00000010  // Send STALL
+#define USB_TXCSRL15_FLUSH      0x00000008  // Flush FIFO
+#define USB_TXCSRL15_UNDRN      0x00000004  // Underrun
+#define USB_TXCSRL15_ERROR      0x00000004  // Error
+#define USB_TXCSRL15_FIFONE     0x00000002  // FIFO Not Empty
+#define USB_TXCSRL15_TXRDY      0x00000001  // Transmit Packet Ready
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_TXCSRH15 register.
 //
 //*****************************************************************************
-#define USB_TXCSRH15_AUTOSET    0x00000080  // Auto Set.
-#define USB_TXCSRH15_ISO        0x00000040  // ISO.
-#define USB_TXCSRH15_MODE       0x00000020  // Mode.
-#define USB_TXCSRH15_DMAEN      0x00000010  // DMA Request Enable.
-#define USB_TXCSRH15_FDT        0x00000008  // Force Data Toggle.
-#define USB_TXCSRH15_DMAMOD     0x00000004  // DMA Request Mode.
-#define USB_TXCSRH15_DTWE       0x00000002  // Data Toggle Write Enable.
-#define USB_TXCSRH15_DT         0x00000001  // Data Toggle.
+#define USB_TXCSRH15_AUTOSET    0x00000080  // Auto Set
+#define USB_TXCSRH15_ISO        0x00000040  // Isochronous Transfers
+#define USB_TXCSRH15_MODE       0x00000020  // Mode
+#define USB_TXCSRH15_DMAEN      0x00000010  // DMA Request Enable
+#define USB_TXCSRH15_FDT        0x00000008  // Force Data Toggle
+#define USB_TXCSRH15_DMAMOD     0x00000004  // DMA Request Mode
+#define USB_TXCSRH15_DTWE       0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH15_DT         0x00000001  // Data Toggle
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXMAXP15 register.
 //
 //*****************************************************************************
-#define USB_RXMAXP15_MAXLOAD_M  0x000007FF  // Maximum Payload.
+#define USB_RXMAXP15_MAXLOAD_M  0x000007FF  // Maximum Payload
 #define USB_RXMAXP15_MAXLOAD_S  0
 
 //*****************************************************************************
@@ -8645,33 +8990,32 @@
 // The following are defines for the bit fields in the USB_O_RXCSRL15 register.
 //
 //*****************************************************************************
-#define USB_RXCSRL15_CLRDT      0x00000080  // Clear Data Toggle.
-#define USB_RXCSRL15_STALLED    0x00000040  // Endpoint Stalled.
-#define USB_RXCSRL15_STALL      0x00000020  // Send Stall.
-#define USB_RXCSRL15_REQPKT     0x00000020  // Request Packet.
-#define USB_RXCSRL15_FLUSH      0x00000010  // Flush FIFO.
-#define USB_RXCSRL15_DATAERR    0x00000008  // Data Error.
-#define USB_RXCSRL15_NAKTO      0x00000008  //  NAK Timeout.
-#define USB_RXCSRL15_ERROR      0x00000004  // Error.
-#define USB_RXCSRL15_OVER       0x00000004  // Overrun.
-#define USB_RXCSRL15_FULL       0x00000002  // FIFO Full.
-#define USB_RXCSRL15_RXRDY      0x00000001  // Receive Packet Ready.
+#define USB_RXCSRL15_CLRDT      0x00000080  // Clear Data Toggle
+#define USB_RXCSRL15_STALLED    0x00000040  // Endpoint Stalled
+#define USB_RXCSRL15_STALL      0x00000020  // Send STALL
+#define USB_RXCSRL15_REQPKT     0x00000020  // Request Packet
+#define USB_RXCSRL15_FLUSH      0x00000010  // Flush FIFO
+#define USB_RXCSRL15_DATAERR    0x00000008  // Data Error
+#define USB_RXCSRL15_NAKTO      0x00000008  // NAK Timeout
+#define USB_RXCSRL15_ERROR      0x00000004  // Error
+#define USB_RXCSRL15_OVER       0x00000004  // Overrun
+#define USB_RXCSRL15_FULL       0x00000002  // FIFO Full
+#define USB_RXCSRL15_RXRDY      0x00000001  // Receive Packet Ready
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_RXCSRH15 register.
 //
 //*****************************************************************************
-#define USB_RXCSRH15_AUTOCL     0x00000080  // Auto Clear.
-#define USB_RXCSRH15_AUTORQ     0x00000040  // Auto Request.
-#define USB_RXCSRH15_ISO        0x00000040  // ISO.
-#define USB_RXCSRH15_DMAEN      0x00000020  // DMA Request Enable.
-#define USB_RXCSRH15_PIDERR     0x00000010  //  PID Error.
-#define USB_RXCSRH15_DISNYET    0x00000010  // Disable NYET 
-#define USB_RXCSRH15_DMAMOD     0x00000008  // DMA Request Mode.
-#define USB_RXCSRH15_DTWE       0x00000004  // Data Toggle Write Enable.
-#define USB_RXCSRH15_DT         0x00000002  // Data Toggle.
-#define USB_RXCSRH15_INCRX      0x00000001  // Incomplete Receive.
+#define USB_RXCSRH15_AUTOCL     0x00000080  // Auto Clear
+#define USB_RXCSRH15_AUTORQ     0x00000040  // Auto Request
+#define USB_RXCSRH15_ISO        0x00000040  // Isochronous Transfers
+#define USB_RXCSRH15_DMAEN      0x00000020  // DMA Request Enable
+#define USB_RXCSRH15_PIDERR     0x00000010  // PID Error
+#define USB_RXCSRH15_DISNYET    0x00000010  // Disable NYET
+#define USB_RXCSRH15_DMAMOD     0x00000008  // DMA Request Mode
+#define USB_RXCSRH15_DTWE       0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH15_DT         0x00000002  // Data Toggle
 
 //*****************************************************************************
 //
@@ -8679,7 +9023,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RXCOUNT15_COUNT_M   0x00001FFF  // Receive Packet Count.
+#define USB_RXCOUNT15_COUNT_M   0x00001FFF  // Receive Packet Count
 #define USB_RXCOUNT15_COUNT_S   0
 
 //*****************************************************************************
@@ -8687,16 +9031,16 @@
 // The following are defines for the bit fields in the USB_O_TXTYPE15 register.
 //
 //*****************************************************************************
-#define USB_TXTYPE15_SPEED_M    0x000000C0  // Operating Speed.
+#define USB_TXTYPE15_SPEED_M    0x000000C0  // Operating Speed
 #define USB_TXTYPE15_SPEED_DFLT 0x00000000  // Default
 #define USB_TXTYPE15_SPEED_FULL 0x00000080  // Full
 #define USB_TXTYPE15_SPEED_LOW  0x000000C0  // Low
-#define USB_TXTYPE15_PROTO_M    0x00000030  // Protocol.
+#define USB_TXTYPE15_PROTO_M    0x00000030  // Protocol
 #define USB_TXTYPE15_PROTO_CTRL 0x00000000  // Control
 #define USB_TXTYPE15_PROTO_ISOC 0x00000010  // Isochronous
 #define USB_TXTYPE15_PROTO_BULK 0x00000020  // Bulk
 #define USB_TXTYPE15_PROTO_INT  0x00000030  // Interrupt
-#define USB_TXTYPE15_TEP_M      0x0000000F  // Target Endpoint Number.
+#define USB_TXTYPE15_TEP_M      0x0000000F  // Target Endpoint Number
 #define USB_TXTYPE15_TEP_S      0
 
 //*****************************************************************************
@@ -8706,9 +9050,9 @@
 //
 //*****************************************************************************
 #define USB_TXINTERVAL15_TXPOLL_M \
-                                0x000000FF  // TX Polling 
+                                0x000000FF  // TX Polling
 #define USB_TXINTERVAL15_NAKLMT_M \
-                                0x000000FF  //  NAK Limit.
+                                0x000000FF  // NAK Limit
 #define USB_TXINTERVAL15_NAKLMT_S \
                                 0
 #define USB_TXINTERVAL15_TXPOLL_S \
@@ -8719,16 +9063,16 @@
 // The following are defines for the bit fields in the USB_O_RXTYPE15 register.
 //
 //*****************************************************************************
-#define USB_RXTYPE15_SPEED_M    0x000000C0  // Operating Speed.
+#define USB_RXTYPE15_SPEED_M    0x000000C0  // Operating Speed
 #define USB_RXTYPE15_SPEED_DFLT 0x00000000  // Default
 #define USB_RXTYPE15_SPEED_FULL 0x00000080  // Full
 #define USB_RXTYPE15_SPEED_LOW  0x000000C0  // Low
-#define USB_RXTYPE15_PROTO_M    0x00000030  // Protocol.
+#define USB_RXTYPE15_PROTO_M    0x00000030  // Protocol
 #define USB_RXTYPE15_PROTO_CTRL 0x00000000  // Control
 #define USB_RXTYPE15_PROTO_ISOC 0x00000010  // Isochronous
 #define USB_RXTYPE15_PROTO_BULK 0x00000020  // Bulk
 #define USB_RXTYPE15_PROTO_INT  0x00000030  // Interrupt
-#define USB_RXTYPE15_TEP_M      0x0000000F  // Target Endpoint Number.
+#define USB_RXTYPE15_TEP_M      0x0000000F  // Target Endpoint Number
 #define USB_RXTYPE15_TEP_S      0
 
 //*****************************************************************************
@@ -8738,9 +9082,9 @@
 //
 //*****************************************************************************
 #define USB_RXINTERVAL15_TXPOLL_M \
-                                0x000000FF  // RX Polling 
+                                0x000000FF  // RX Polling
 #define USB_RXINTERVAL15_NAKLMT_M \
-                                0x000000FF  //  NAK Limit.
+                                0x000000FF  // NAK Limit
 #define USB_RXINTERVAL15_TXPOLL_S \
                                 0
 #define USB_RXINTERVAL15_NAKLMT_S \
@@ -8752,7 +9096,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RQPKTCOUNT1_M       0x0000FFFF  // Block Transfer Packet Count.
+#define USB_RQPKTCOUNT1_M       0x0000FFFF  // Block Transfer Packet Count
 #define USB_RQPKTCOUNT1_S       0
 
 //*****************************************************************************
@@ -8761,7 +9105,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RQPKTCOUNT2_M       0x0000FFFF  // Block Transfer Packet Count.
+#define USB_RQPKTCOUNT2_M       0x0000FFFF  // Block Transfer Packet Count
 #define USB_RQPKTCOUNT2_S       0
 
 //*****************************************************************************
@@ -8770,7 +9114,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RQPKTCOUNT3_M       0x0000FFFF  // Block Transfer Packet Count.
+#define USB_RQPKTCOUNT3_M       0x0000FFFF  // Block Transfer Packet Count
 #define USB_RQPKTCOUNT3_S       0
 
 //*****************************************************************************
@@ -8779,7 +9123,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RQPKTCOUNT4_COUNT_M 0x0000FFFF  // Block Transfer Packet Count.
+#define USB_RQPKTCOUNT4_COUNT_M 0x0000FFFF  // Block Transfer Packet Count
 #define USB_RQPKTCOUNT4_COUNT_S 0
 
 //*****************************************************************************
@@ -8788,7 +9132,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RQPKTCOUNT5_COUNT_M 0x0000FFFF  // Block Transfer Packet Count.
+#define USB_RQPKTCOUNT5_COUNT_M 0x0000FFFF  // Block Transfer Packet Count
 #define USB_RQPKTCOUNT5_COUNT_S 0
 
 //*****************************************************************************
@@ -8797,7 +9141,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RQPKTCOUNT6_COUNT_M 0x0000FFFF  // Block Transfer Packet Count.
+#define USB_RQPKTCOUNT6_COUNT_M 0x0000FFFF  // Block Transfer Packet Count
 #define USB_RQPKTCOUNT6_COUNT_S 0
 
 //*****************************************************************************
@@ -8806,7 +9150,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RQPKTCOUNT7_COUNT_M 0x0000FFFF  // Block Transfer Packet Count.
+#define USB_RQPKTCOUNT7_COUNT_M 0x0000FFFF  // Block Transfer Packet Count
 #define USB_RQPKTCOUNT7_COUNT_S 0
 
 //*****************************************************************************
@@ -8815,7 +9159,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RQPKTCOUNT8_COUNT_M 0x0000FFFF  // Block Transfer Packet Count.
+#define USB_RQPKTCOUNT8_COUNT_M 0x0000FFFF  // Block Transfer Packet Count
 #define USB_RQPKTCOUNT8_COUNT_S 0
 
 //*****************************************************************************
@@ -8824,7 +9168,7 @@
 // register.
 //
 //*****************************************************************************
-#define USB_RQPKTCOUNT9_COUNT_M 0x0000FFFF  // Block Transfer Packet Count.
+#define USB_RQPKTCOUNT9_COUNT_M 0x0000FFFF  // Block Transfer Packet Count
 #define USB_RQPKTCOUNT9_COUNT_S 0
 
 //*****************************************************************************
@@ -8834,7 +9178,7 @@
 //
 //*****************************************************************************
 #define USB_RQPKTCOUNT10_COUNT_M \
-                                0x0000FFFF  // Block Transfer Packet Count.
+                                0x0000FFFF  // Block Transfer Packet Count
 #define USB_RQPKTCOUNT10_COUNT_S \
                                 0
 
@@ -8845,7 +9189,7 @@
 //
 //*****************************************************************************
 #define USB_RQPKTCOUNT11_COUNT_M \
-                                0x0000FFFF  // Block Transfer Packet Count.
+                                0x0000FFFF  // Block Transfer Packet Count
 #define USB_RQPKTCOUNT11_COUNT_S \
                                 0
 
@@ -8856,7 +9200,7 @@
 //
 //*****************************************************************************
 #define USB_RQPKTCOUNT12_COUNT_M \
-                                0x0000FFFF  // Block Transfer Packet Count.
+                                0x0000FFFF  // Block Transfer Packet Count
 #define USB_RQPKTCOUNT12_COUNT_S \
                                 0
 
@@ -8867,7 +9211,7 @@
 //
 //*****************************************************************************
 #define USB_RQPKTCOUNT13_COUNT_M \
-                                0x0000FFFF  // Block Transfer Packet Count.
+                                0x0000FFFF  // Block Transfer Packet Count
 #define USB_RQPKTCOUNT13_COUNT_S \
                                 0
 
@@ -8878,7 +9222,7 @@
 //
 //*****************************************************************************
 #define USB_RQPKTCOUNT14_COUNT_M \
-                                0x0000FFFF  // Block Transfer Packet Count.
+                                0x0000FFFF  // Block Transfer Packet Count
 #define USB_RQPKTCOUNT14_COUNT_S \
                                 0
 
@@ -8889,7 +9233,7 @@
 //
 //*****************************************************************************
 #define USB_RQPKTCOUNT15_COUNT_M \
-                                0x0000FFFF  // Block Transfer Packet Count.
+                                0x0000FFFF  // Block Transfer Packet Count
 #define USB_RQPKTCOUNT15_COUNT_S \
                                 0
 
@@ -8900,35 +9244,35 @@
 //
 //*****************************************************************************
 #define USB_RXDPKTBUFDIS_EP15   0x00008000  // EP15 RX Double-Packet Buffer
-                                            // Disable.
+                                            // Disable
 #define USB_RXDPKTBUFDIS_EP14   0x00004000  // EP14 RX Double-Packet Buffer
-                                            // Disable.
+                                            // Disable
 #define USB_RXDPKTBUFDIS_EP13   0x00002000  // EP13 RX Double-Packet Buffer
-                                            // Disable.
+                                            // Disable
 #define USB_RXDPKTBUFDIS_EP12   0x00001000  // EP12 RX Double-Packet Buffer
-                                            // Disable.
+                                            // Disable
 #define USB_RXDPKTBUFDIS_EP11   0x00000800  // EP11 RX Double-Packet Buffer
-                                            // Disable.
+                                            // Disable
 #define USB_RXDPKTBUFDIS_EP10   0x00000400  // EP10 RX Double-Packet Buffer
-                                            // Disable.
+                                            // Disable
 #define USB_RXDPKTBUFDIS_EP9    0x00000200  // EP9 RX Double-Packet Buffer
-                                            // Disable.
+                                            // Disable
 #define USB_RXDPKTBUFDIS_EP8    0x00000100  // EP8 RX Double-Packet Buffer
-                                            // Disable.
+                                            // Disable
 #define USB_RXDPKTBUFDIS_EP7    0x00000080  // EP7 RX Double-Packet Buffer
-                                            // Disable.
+                                            // Disable
 #define USB_RXDPKTBUFDIS_EP6    0x00000040  // EP6 RX Double-Packet Buffer
-                                            // Disable.
+                                            // Disable
 #define USB_RXDPKTBUFDIS_EP5    0x00000020  // EP5 RX Double-Packet Buffer
-                                            // Disable.
+                                            // Disable
 #define USB_RXDPKTBUFDIS_EP4    0x00000010  // EP4 RX Double-Packet Buffer
-                                            // Disable.
+                                            // Disable
 #define USB_RXDPKTBUFDIS_EP3    0x00000008  // EP3 RX Double-Packet Buffer
-                                            // Disable.
+                                            // Disable
 #define USB_RXDPKTBUFDIS_EP2    0x00000004  // EP2 RX Double-Packet Buffer
-                                            // Disable.
+                                            // Disable
 #define USB_RXDPKTBUFDIS_EP1    0x00000002  // EP1 RX Double-Packet Buffer
-                                            // Disable.
+                                            // Disable
 
 //*****************************************************************************
 //
@@ -8937,52 +9281,52 @@
 //
 //*****************************************************************************
 #define USB_TXDPKTBUFDIS_EP15   0x00008000  // EP15 TX Double-Packet Buffer
-                                            // Disable.
+                                            // Disable
 #define USB_TXDPKTBUFDIS_EP14   0x00004000  // EP14 TX Double-Packet Buffer
-                                            // Disable.
+                                            // Disable
 #define USB_TXDPKTBUFDIS_EP13   0x00002000  // EP13 TX Double-Packet Buffer
-                                            // Disable.
+                                            // Disable
 #define USB_TXDPKTBUFDIS_EP12   0x00001000  // EP12 TX Double-Packet Buffer
-                                            // Disable.
+                                            // Disable
 #define USB_TXDPKTBUFDIS_EP11   0x00000800  // EP11 TX Double-Packet Buffer
-                                            // Disable.
+                                            // Disable
 #define USB_TXDPKTBUFDIS_EP10   0x00000400  // EP10 TX Double-Packet Buffer
-                                            // Disable.
+                                            // Disable
 #define USB_TXDPKTBUFDIS_EP9    0x00000200  // EP9 TX Double-Packet Buffer
-                                            // Disable.
+                                            // Disable
 #define USB_TXDPKTBUFDIS_EP8    0x00000100  // EP8 TX Double-Packet Buffer
-                                            // Disable.
+                                            // Disable
 #define USB_TXDPKTBUFDIS_EP7    0x00000080  // EP7 TX Double-Packet Buffer
-                                            // Disable.
+                                            // Disable
 #define USB_TXDPKTBUFDIS_EP6    0x00000040  // EP6 TX Double-Packet Buffer
-                                            // Disable.
+                                            // Disable
 #define USB_TXDPKTBUFDIS_EP5    0x00000020  // EP5 TX Double-Packet Buffer
-                                            // Disable.
+                                            // Disable
 #define USB_TXDPKTBUFDIS_EP4    0x00000010  // EP4 TX Double-Packet Buffer
-                                            // Disable.
+                                            // Disable
 #define USB_TXDPKTBUFDIS_EP3    0x00000008  // EP3 TX Double-Packet Buffer
-                                            // Disable.
+                                            // Disable
 #define USB_TXDPKTBUFDIS_EP2    0x00000004  // EP2 TX Double-Packet Buffer
-                                            // Disable.
+                                            // Disable
 #define USB_TXDPKTBUFDIS_EP1    0x00000002  // EP1 TX Double-Packet Buffer
-                                            // Disable.
+                                            // Disable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_EPC register.
 //
 //*****************************************************************************
-#define USB_EPC_PFLTACT_M       0x00000300  // Power Fault Action.
+#define USB_EPC_PFLTACT_M       0x00000300  // Power Fault Action
 #define USB_EPC_PFLTACT_UNCHG   0x00000000  // Unchanged
 #define USB_EPC_PFLTACT_TRIS    0x00000100  // Tristate
 #define USB_EPC_PFLTACT_LOW     0x00000200  // Low
 #define USB_EPC_PFLTACT_HIGH    0x00000300  // High
-#define USB_EPC_PFLTAEN         0x00000040  // Power Fault Action Enable.
-#define USB_EPC_PFLTSEN_HIGH    0x00000020  // Power Fault Sense.
-#define USB_EPC_PFLTEN          0x00000010  // Power Fault Input Enable.
-#define USB_EPC_EPENDE          0x00000004  // EPEN Drive Enable.
+#define USB_EPC_PFLTAEN         0x00000040  // Power Fault Action Enable
+#define USB_EPC_PFLTSEN_HIGH    0x00000020  // Power Fault Sense
+#define USB_EPC_PFLTEN          0x00000010  // Power Fault Input Enable
+#define USB_EPC_EPENDE          0x00000004  // EPEN Drive Enable
 #define USB_EPC_EPEN_M          0x00000003  // External Power Supply Enable
-                                            // Configuration.
+                                            // Configuration
 #define USB_EPC_EPEN_LOW        0x00000000  // Power Enable Active Low
 #define USB_EPC_EPEN_HIGH       0x00000001  // Power Enable Active High
 #define USB_EPC_EPEN_VBLOW      0x00000002  // Power Enable High if VBUS Low
@@ -8993,15 +9337,14 @@
 // The following are defines for the bit fields in the USB_O_EPCRIS register.
 //
 //*****************************************************************************
-#define USB_EPCRIS_PF           0x00000001  // USB Power Fault Interrupt
-                                            // Status.
+#define USB_EPCRIS_PF           0x00000001  // USB Power Fault Interrupt Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_EPCIM register.
 //
 //*****************************************************************************
-#define USB_EPCIM_PF            0x00000001  // USB Power Fault Interrupt Mask.
+#define USB_EPCIM_PF            0x00000001  // USB Power Fault Interrupt Mask
 
 //*****************************************************************************
 //
@@ -9009,50 +9352,58 @@
 //
 //*****************************************************************************
 #define USB_EPCISC_PF           0x00000001  // USB Power Fault Interrupt Status
-                                            // and Clear.
+                                            // and Clear
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_DRRIS register.
 //
 //*****************************************************************************
-#define USB_DRRIS_RESUME        0x00000001  // Resume Interrupt Status.
+#define USB_DRRIS_RESUME        0x00000001  // RESUME Interrupt Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_DRIM register.
 //
 //*****************************************************************************
-#define USB_DRIM_RESUME         0x00000001  // Resume Interrupt Mask.
+#define USB_DRIM_RESUME         0x00000001  // RESUME Interrupt Mask
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_DRISC register.
 //
 //*****************************************************************************
-#define USB_DRISC_RESUME        0x00000001  // Resume Interrupt Status and
-                                            // Clear.
+#define USB_DRISC_RESUME        0x00000001  // RESUME Interrupt Status and
+                                            // Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_GPCS register.
+//
+//*****************************************************************************
+#define USB_GPCS_DEVMODOTG      0x00000002  // Enable Device Mode
+#define USB_GPCS_DEVMOD         0x00000001  // Device Mode
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_VDC register.
 //
 //*****************************************************************************
-#define USB_VDC_VBDEN           0x00000001  // VBUS Droop Enable.
+#define USB_VDC_VBDEN           0x00000001  // VBUS Droop Enable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_VDCRIS register.
 //
 //*****************************************************************************
-#define USB_VDCRIS_VD           0x00000001  // VBUS Droop Raw Interrupt Status.
+#define USB_VDCRIS_VD           0x00000001  // VBUS Droop Raw Interrupt Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_VDCIM register.
 //
 //*****************************************************************************
-#define USB_VDCIM_VD            0x00000001  // VBUS Droop Interrupt Mask.
+#define USB_VDCIM_VD            0x00000001  // VBUS Droop Interrupt Mask
 
 //*****************************************************************************
 //
@@ -9060,7 +9411,7 @@
 //
 //*****************************************************************************
 #define USB_VDCISC_VD           0x00000001  // VBUS Droop Interrupt Status and
-                                            // Clear.
+                                            // Clear
 
 //*****************************************************************************
 //
@@ -9068,14 +9419,14 @@
 //
 //*****************************************************************************
 #define USB_IDVRIS_ID           0x00000001  // ID Valid Detect Raw Interrupt
-                                            // Status.
+                                            // Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the USB_O_IDVIM register.
 //
 //*****************************************************************************
-#define USB_IDVIM_ID            0x00000001  // ID Valid Detect Interrupt Mask.
+#define USB_IDVIM_ID            0x00000001  // ID Valid Detect Interrupt Mask
 
 //*****************************************************************************
 //
@@ -9083,25 +9434,32 @@
 //
 //*****************************************************************************
 #define USB_IDVISC_ID           0x00000001  // ID Valid Detect Interrupt Status
-                                            // and Clear.
+                                            // and Clear
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the USB_O_EPS register.
+// The following are defines for the bit fields in the USB_O_DMASEL register.
 //
 //*****************************************************************************
-#define USB_EPS_DMAC_M          0x00000F00  // DMA C Select.
-#define USB_EPS_DMAB_M          0x000000F0  // DMA B Select.
-#define USB_EPS_DMAA_M          0x0000000F  // DMA A Select.
-#define USB_EPS_DMAB_S          4
-#define USB_EPS_DMAA_S          0
+#define USB_DMASEL_DMACTX_M     0x00F00000  // DMA C TX Select
+#define USB_DMASEL_DMACRX_M     0x000F0000  // DMA C RX Select
+#define USB_DMASEL_DMABTX_M     0x0000F000  // DMA B TX Select
+#define USB_DMASEL_DMABRX_M     0x00000F00  // DMA B RX Select
+#define USB_DMASEL_DMAATX_M     0x000000F0  // DMA A TX Select
+#define USB_DMASEL_DMAARX_M     0x0000000F  // DMA A RX Select
+#define USB_DMASEL_DMACTX_S     20
+#define USB_DMASEL_DMACRX_S     16
+#define USB_DMASEL_DMABTX_S     12
+#define USB_DMASEL_DMABRX_S     8
+#define USB_DMASEL_DMAATX_S     4
+#define USB_DMASEL_DMAARX_S     0
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2S_O_TXFIFO register.
 //
 //*****************************************************************************
-#define I2S_TXFIFO_M            0xFFFFFFFF  // TX Data.
+#define I2S_TXFIFO_M            0xFFFFFFFF  // TX Data
 #define I2S_TXFIFO_S            0
 
 //*****************************************************************************
@@ -9110,26 +9468,26 @@
 // register.
 //
 //*****************************************************************************
-#define I2S_TXFIFOCFG_CSS       0x00000002  // Compact Stereo Sample Size.
-#define I2S_TXFIFOCFG_LRS       0x00000001  // Left-Right Sample Indicator.
+#define I2S_TXFIFOCFG_CSS       0x00000002  // Compact Stereo Sample Size
+#define I2S_TXFIFOCFG_LRS       0x00000001  // Left-Right Sample Indicator
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2S_O_TXCFG register.
 //
 //*****************************************************************************
-#define I2S_TXCFG_JST           0x20000000  // Justification of Output Data.
-#define I2S_TXCFG_DLY           0x10000000  // Data Delay.
-#define I2S_TXCFG_SCP           0x08000000  // SCLK Polarity.
-#define I2S_TXCFG_LRP           0x04000000  // Left/Right Clock Polarity.
-#define I2S_TXCFG_WM_M          0x03000000  // Write Mode.
+#define I2S_TXCFG_JST           0x20000000  // Justification of Output Data
+#define I2S_TXCFG_DLY           0x10000000  // Data Delay
+#define I2S_TXCFG_SCP           0x08000000  // SCLK Polarity
+#define I2S_TXCFG_LRP           0x04000000  // Left/Right Clock Polarity
+#define I2S_TXCFG_WM_M          0x03000000  // Write Mode
 #define I2S_TXCFG_WM_DUAL       0x00000000  // Stereo mode
 #define I2S_TXCFG_WM_COMPACT    0x01000000  // Compact Stereo mode
 #define I2S_TXCFG_WM_MONO       0x02000000  // Mono mode
-#define I2S_TXCFG_FMT           0x00800000  // FIFO Empty.
-#define I2S_TXCFG_MSL           0x00400000  // SCLK Master/Slave.
-#define I2S_TXCFG_SSZ_M         0x0000FC00  // Sample Size.
-#define I2S_TXCFG_SDSZ_M        0x000003F0  // System Data Size.
+#define I2S_TXCFG_FMT           0x00800000  // FIFO Empty
+#define I2S_TXCFG_MSL           0x00400000  // SCLK Master/Slave
+#define I2S_TXCFG_SSZ_M         0x0000FC00  // Sample Size
+#define I2S_TXCFG_SDSZ_M        0x000003F0  // System Data Size
 #define I2S_TXCFG_SSZ_S         10
 #define I2S_TXCFG_SDSZ_S        4
 
@@ -9138,7 +9496,7 @@
 // The following are defines for the bit fields in the I2S_O_TXLIMIT register.
 //
 //*****************************************************************************
-#define I2S_TXLIMIT_LIMIT_M     0x0000001F  // FIFO Limit.
+#define I2S_TXLIMIT_LIMIT_M     0x0000001F  // FIFO Limit
 #define I2S_TXLIMIT_LIMIT_S     0
 
 //*****************************************************************************
@@ -9147,15 +9505,15 @@
 //
 //*****************************************************************************
 #define I2S_TXISM_FFI           0x00010000  // Transmit FIFO Service Request
-                                            // Interrupt.
-#define I2S_TXISM_FFM           0x00000001  // FIFO Interrupt Mask.
+                                            // Interrupt
+#define I2S_TXISM_FFM           0x00000001  // FIFO Interrupt Mask
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2S_O_TXLEV register.
 //
 //*****************************************************************************
-#define I2S_TXLEV_LEVEL_M       0x0000001F  // Number of Audio Samples.
+#define I2S_TXLEV_LEVEL_M       0x0000001F  // Number of Audio Samples
 #define I2S_TXLEV_LEVEL_S       0
 
 //*****************************************************************************
@@ -9163,7 +9521,7 @@
 // The following are defines for the bit fields in the I2S_O_RXFIFO register.
 //
 //*****************************************************************************
-#define I2S_RXFIFO_M            0xFFFFFFFF  // RX Data.
+#define I2S_RXFIFO_M            0xFFFFFFFF  // RX Data
 #define I2S_RXFIFO_S            0
 
 //*****************************************************************************
@@ -9172,23 +9530,23 @@
 // register.
 //
 //*****************************************************************************
-#define I2S_RXFIFOCFG_FMM       0x00000004  // FIFO Mono Mode.
-#define I2S_RXFIFOCFG_CSS       0x00000002  // Compact Stereo Sample Size.
-#define I2S_RXFIFOCFG_LRS       0x00000001  // Left-Right Sample Indicator.
+#define I2S_RXFIFOCFG_FMM       0x00000004  // FIFO Mono Mode
+#define I2S_RXFIFOCFG_CSS       0x00000002  // Compact Stereo Sample Size
+#define I2S_RXFIFOCFG_LRS       0x00000001  // Left-Right Sample Indicator
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2S_O_RXCFG register.
 //
 //*****************************************************************************
-#define I2S_RXCFG_JST           0x20000000  // Justification of Input Data.
-#define I2S_RXCFG_DLY           0x10000000  // Data Delay.
-#define I2S_RXCFG_SCP           0x08000000  // SCLK Polarity.
-#define I2S_RXCFG_LRP           0x04000000  // Left/Right Clock Polarity.
-#define I2S_RXCFG_RM            0x01000000  // Read Mode.
-#define I2S_RXCFG_MSL           0x00400000  // SCLK Master/Slave.
-#define I2S_RXCFG_SSZ_M         0x0000FC00  // Sample Size.
-#define I2S_RXCFG_SDSZ_M        0x000003F0  // System Data Size.
+#define I2S_RXCFG_JST           0x20000000  // Justification of Input Data
+#define I2S_RXCFG_DLY           0x10000000  // Data Delay
+#define I2S_RXCFG_SCP           0x08000000  // SCLK Polarity
+#define I2S_RXCFG_LRP           0x04000000  // Left/Right Clock Polarity
+#define I2S_RXCFG_RM            0x01000000  // Read Mode
+#define I2S_RXCFG_MSL           0x00400000  // SCLK Master/Slave
+#define I2S_RXCFG_SSZ_M         0x0000FC00  // Sample Size
+#define I2S_RXCFG_SDSZ_M        0x000003F0  // System Data Size
 #define I2S_RXCFG_SSZ_S         10
 #define I2S_RXCFG_SDSZ_S        4
 
@@ -9197,7 +9555,7 @@
 // The following are defines for the bit fields in the I2S_O_RXLIMIT register.
 //
 //*****************************************************************************
-#define I2S_RXLIMIT_LIMIT_M     0x0000001F  // FIFO Limit.
+#define I2S_RXLIMIT_LIMIT_M     0x0000001F  // FIFO Limit
 #define I2S_RXLIMIT_LIMIT_S     0
 
 //*****************************************************************************
@@ -9206,15 +9564,15 @@
 //
 //*****************************************************************************
 #define I2S_RXISM_FFI           0x00010000  // Receive FIFO Service Request
-                                            // Interrupt.
-#define I2S_RXISM_FFM           0x00000001  // FIFO Interrupt Mask.
+                                            // Interrupt
+#define I2S_RXISM_FFM           0x00000001  // FIFO Interrupt Mask
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2S_O_RXLEV register.
 //
 //*****************************************************************************
-#define I2S_RXLEV_LEVEL_M       0x0000001F  // Number of Audio Samples.
+#define I2S_RXLEV_LEVEL_M       0x0000001F  // Number of Audio Samples
 #define I2S_RXLEV_LEVEL_S       0
 
 //*****************************************************************************
@@ -9222,203 +9580,237 @@
 // The following are defines for the bit fields in the I2S_O_CFG register.
 //
 //*****************************************************************************
-#define I2S_CFG_RXSLV           0x00000020  // When set, this bit configures
-                                            // the receiver to use the
-                                            // externally driven I2S0RXMCLK
-                                            // signal.
-#define I2S_CFG_TXSLV           0x00000010  // When set, this bit configures
-                                            // the transmitter to use the
-                                            // externally driven I2S0TXMCLK
-                                            // signal.
-#define I2S_CFG_RXEN            0x00000002  // Serial Receive Engine Enable.
-#define I2S_CFG_TXEN            0x00000001  // Serial Transmit Engine Enable.
+#define I2S_CFG_RXSLV           0x00000020  // Use External I2S0RXMCLK
+#define I2S_CFG_TXSLV           0x00000010  // Use External I2S0TXMCLK
+#define I2S_CFG_RXEN            0x00000002  // Serial Receive Engine Enable
+#define I2S_CFG_TXEN            0x00000001  // Serial Transmit Engine Enable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2S_O_IM register.
 //
 //*****************************************************************************
-#define I2S_IM_RXRE             0x00000020  // Receive FIFO Read Error.
-#define I2S_IM_RXFSR            0x00000010  // Receive FIFO Service Request.
-#define I2S_IM_TXWE             0x00000002  // Transmit FIFO Write Error.
-#define I2S_IM_TXFSR            0x00000001  // Transmit FIFO Service Request.
+#define I2S_IM_RXRE             0x00000020  // Receive FIFO Read Error
+#define I2S_IM_RXFSR            0x00000010  // Receive FIFO Service Request
+#define I2S_IM_TXWE             0x00000002  // Transmit FIFO Write Error
+#define I2S_IM_TXFSR            0x00000001  // Transmit FIFO Service Request
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2S_O_RIS register.
 //
 //*****************************************************************************
-#define I2S_RIS_RXRE            0x00000020  // Receive FIFO Read Error.
-#define I2S_RIS_RXFSR           0x00000010  // Receive FIFO Service Request.
-#define I2S_RIS_TXWE            0x00000002  // Transmit FIFO Write Error.
-#define I2S_RIS_TXFSR           0x00000001  // Transmit FIFO Service Request.
+#define I2S_RIS_RXRE            0x00000020  // Receive FIFO Read Error
+#define I2S_RIS_RXFSR           0x00000010  // Receive FIFO Service Request
+#define I2S_RIS_TXWE            0x00000002  // Transmit FIFO Write Error
+#define I2S_RIS_TXFSR           0x00000001  // Transmit FIFO Service Request
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2S_O_MIS register.
 //
 //*****************************************************************************
-#define I2S_MIS_RXRE            0x00000020  // Receive FIFO Read Error.
-#define I2S_MIS_RXFSR           0x00000010  // Receive FIFO Service Request.
-#define I2S_MIS_TXWE            0x00000002  // Transmit FIFO Write Error.
-#define I2S_MIS_TXFSR           0x00000001  // Transmit FIFO Service Request.
+#define I2S_MIS_RXRE            0x00000020  // Receive FIFO Read Error
+#define I2S_MIS_RXFSR           0x00000010  // Receive FIFO Service Request
+#define I2S_MIS_TXWE            0x00000002  // Transmit FIFO Write Error
+#define I2S_MIS_TXFSR           0x00000001  // Transmit FIFO Service Request
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2S_O_IC register.
 //
 //*****************************************************************************
-#define I2S_IC_RXRE             0x00000020  // Receive FIFO Read Error.
-#define I2S_IC_TXWE             0x00000002  // Transmit FIFO Write Error.
+#define I2S_IC_RXRE             0x00000020  // Receive FIFO Read Error
+#define I2S_IC_TXWE             0x00000002  // Transmit FIFO Write Error
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the EPI_O_CFG register.
 //
 //*****************************************************************************
-#define EPI_CFG_BLKEN           0x00000010  // Block Enable.
-#define EPI_CFG_MODE_M          0x0000000F  // Mode Select.
+#define EPI_CFG_BLKEN           0x00000010  // Block Enable
+#define EPI_CFG_MODE_M          0x0000000F  // Mode Select
 #define EPI_CFG_MODE_NONE       0x00000000  // General Purpose
-#define EPI_CFG_MODE_SDRAM      0x00000001  // Supports SDR SDRAM. Control,
-                                            // address, and data pins are
-                                            // configured using the EPISDRAMCFG
-                                            // and EPISDRAMCFG2 registers.
+#define EPI_CFG_MODE_SDRAM      0x00000001  // SDRAM
 #define EPI_CFG_MODE_HB8        0x00000002  // 8-Bit Host-Bus (HB8)
+#define EPI_CFG_MODE_HB16       0x00000003  // 16-Bit Host-Bus (HB16)
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the EPI_O_BAUD register.
 //
 //*****************************************************************************
-#define EPI_BAUD_COUNT_M        0x0000FFFF  // Baud Rate Counter.
-#define EPI_BAUD_COUNT_S        0
+#define EPI_BAUD_COUNT1_M       0xFFFF0000  // Baud Rate Counter 1
+#define EPI_BAUD_COUNT0_M       0x0000FFFF  // Baud Rate Counter 0
+#define EPI_BAUD_COUNT1_S       16
+#define EPI_BAUD_COUNT0_S       0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the EPI_O_SDRAMCFG register.
+// The following are defines for the bit fields in the EPI_O_HB16CFG register.
 //
 //*****************************************************************************
-#define EPI_SDRAMCFG_FREQ_M     0xC0000000  // Frequency Range.
-#define EPI_SDRAMCFG_FREQ_NONE  0x00000000  // 0
-#define EPI_SDRAMCFG_FREQ_15MHZ 0x40000000  // 15
-#define EPI_SDRAMCFG_FREQ_30MHZ 0x80000000  // 30
-#define EPI_SDRAMCFG_FREQ_50MHZ 0xC0000000  // 50
-#define EPI_SDRAMCFG_RFSH_M     0x07FF0000  // Refresh Counter.
-#define EPI_SDRAMCFG_SLEEP      0x00000200  // Sleep Mode.
-#define EPI_SDRAMCFG_SIZE_M     0x00000003  // Size of SDRAM.
-#define EPI_SDRAMCFG_SIZE_8MB   0x00000000  // 64Mb (8MB)
-#define EPI_SDRAMCFG_SIZE_16MB  0x00000001  // 128Mb (16MB)
-#define EPI_SDRAMCFG_SIZE_32MB  0x00000002  // 256Mb (32MB)
-#define EPI_SDRAMCFG_SIZE_64MB  0x00000003  // 512Mb (64MB)
-#define EPI_SDRAMCFG_RFSH_S     16
+#define EPI_HB16CFG_XFFEN       0x00800000  // External FIFO FULL Enable
+#define EPI_HB16CFG_XFEEN       0x00400000  // External FIFO EMPTY Enable
+#define EPI_HB16CFG_WRHIGH      0x00200000  // WRITE Strobe Polarity
+#define EPI_HB16CFG_RDHIGH      0x00100000  // READ Strobe Polarity
+#define EPI_HB16CFG_MAXWAIT_M   0x0000FF00  // Maximum Wait
+#define EPI_HB16CFG_WRWS_M      0x000000C0  // CS0n Write Wait States
+#define EPI_HB16CFG_WRWS_0      0x00000000  // No wait states
+#define EPI_HB16CFG_WRWS_1      0x00000040  // 1 wait state
+#define EPI_HB16CFG_WRWS_2      0x00000080  // 2 wait states
+#define EPI_HB16CFG_WRWS_3      0x000000C0  // 3 wait states
+#define EPI_HB16CFG_RDWS_M      0x00000030  // CS0n Read Wait States
+#define EPI_HB16CFG_RDWS_0      0x00000000  // No wait states
+#define EPI_HB16CFG_RDWS_1      0x00000010  // 1 wait state
+#define EPI_HB16CFG_RDWS_2      0x00000020  // 2 wait states
+#define EPI_HB16CFG_RDWS_3      0x00000030  // 3 wait states
+#define EPI_HB16CFG_BSEL        0x00000004  // Byte Select Configuration
+#define EPI_HB16CFG_MODE_M      0x00000003  // Host Bus Sub-Mode
+#define EPI_HB16CFG_MODE_ADMUX  0x00000000  // ADMUX - AD[15:0]
+#define EPI_HB16CFG_MODE_ADNMUX 0x00000001  // ADNONMUX - D[15:0]
+#define EPI_HB16CFG_MODE_SRAM   0x00000002  // Continuous Read - D[15:0]
+#define EPI_HB16CFG_MODE_XFIFO  0x00000003  // XFIFO - D[15:0]
+#define EPI_HB16CFG_MAXWAIT_S   8
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the EPI_O_GPCFG register.
 //
 //*****************************************************************************
-#define EPI_GPCFG_CLKPIN        0x80000000  // Clock Pin.
-#define EPI_GPCFG_CLKGATE       0x40000000  // Clock Gated.
-#define EPI_GPCFG_RDYEN         0x10000000  // Ready Enable.
-#define EPI_GPCFG_FRMPIN        0x08000000  // Framing Pin.
-#define EPI_GPCFG_FRM50         0x04000000  // 50/50 Frame.
-#define EPI_GPCFG_FRMCNT_M      0x03C00000  // Frame Count.
-#define EPI_GPCFG_RW            0x00200000  // Read and Write.
-#define EPI_GPCFG_WR2CYC        0x00080000  // 2-Cycle Writes.
-#define EPI_GPCFG_RD2CYC        0x00040000  // 2-Cycle Reads.
-#define EPI_GPCFG_MAXWAIT_M     0x0000FF00  // Maximum Wait.
-#define EPI_GPCFG_ASIZE_M       0x00000030  // Address Bus Size.
+#define EPI_GPCFG_CLKPIN        0x80000000  // Clock Pin
+#define EPI_GPCFG_CLKGATE       0x40000000  // Clock Gated
+#define EPI_GPCFG_RDYEN         0x10000000  // Ready Enable
+#define EPI_GPCFG_FRMPIN        0x08000000  // Framing Pin
+#define EPI_GPCFG_FRM50         0x04000000  // 50/50 Frame
+#define EPI_GPCFG_FRMCNT_M      0x03C00000  // Frame Count
+#define EPI_GPCFG_RW            0x00200000  // Read and Write
+#define EPI_GPCFG_WR2CYC        0x00080000  // 2-Cycle Writes
+#define EPI_GPCFG_RD2CYC        0x00040000  // 2-Cycle Reads
+#define EPI_GPCFG_MAXWAIT_M     0x0000FF00  // Maximum Wait
+#define EPI_GPCFG_ASIZE_M       0x00000030  // Address Bus Size
 #define EPI_GPCFG_ASIZE_NONE    0x00000000  // No address
-#define EPI_GPCFG_ASIZE_4BIT    0x00000010  // 4 Bits Wide (EPI24 to EPI27)
-#define EPI_GPCFG_ASIZE_12BIT   0x00000020  // 12 Bits Wide (EPI16 to EPI27).
-                                            // This size cannot be used with
-                                            // 24-bit data.
-#define EPI_GPCFG_ASIZE_20BIT   0x00000030  // 20 Bits Wide
-#define EPI_GPCFG_DSIZE_M       0x00000003  // Size of Data Bus.
-#define EPI_GPCFG_DSIZE_4BIT    0x00000000  // 8 Bits Wide (EPI0 to EPI7)
-#define EPI_GPCFG_DSIZE_16BIT   0x00000001  // 16 Bits Wide (EPI0 to EPI15)
-#define EPI_GPCFG_DSIZE_24BIT   0x00000002  // 24 Bits Wide (EPI0 to EPI23)
-#define EPI_GPCFG_DSIZE_32BIT   0x00000003  // 32 Bits Wide (EPI0 to
-                                            // EPI31).This size may not be used
-                                            // with a clock. This value is
-                                            // normally used for acquisition
-                                            // input and actuator control as
-                                            // well as other general-purpose
-                                            // uses that require 32 bits per
-                                            // direction.
+#define EPI_GPCFG_ASIZE_4BIT    0x00000010  // Up to 4 bits wide
+#define EPI_GPCFG_ASIZE_12BIT   0x00000020  // Up to 12 bits wide. This size
+                                            // cannot be used with 24-bit data
+#define EPI_GPCFG_ASIZE_20BIT   0x00000030  // Up to 20 bits wide. This size
+                                            // cannot be used with data sizes
+                                            // other than 8
+#define EPI_GPCFG_DSIZE_M       0x00000003  // Size of Data Bus
+#define EPI_GPCFG_DSIZE_4BIT    0x00000000  // 8 Bits Wide (EPI0S0 to EPI0S7)
+#define EPI_GPCFG_DSIZE_16BIT   0x00000001  // 16 Bits Wide (EPI0S0 to EPI0S15)
+#define EPI_GPCFG_DSIZE_24BIT   0x00000002  // 24 Bits Wide (EPI0S0 to EPI0S23)
+#define EPI_GPCFG_DSIZE_32BIT   0x00000003  // 32 Bits Wide (EPI0S0 to EPI0S31)
 #define EPI_GPCFG_FRMCNT_S      22
 #define EPI_GPCFG_MAXWAIT_S     8
 
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_SDRAMCFG register.
+//
+//*****************************************************************************
+#define EPI_SDRAMCFG_FREQ_M     0xC0000000  // Frequency Range
+#define EPI_SDRAMCFG_FREQ_NONE  0x00000000  // 0 - 15 MHz
+#define EPI_SDRAMCFG_FREQ_15MHZ 0x40000000  // 15 - 30 MHz
+#define EPI_SDRAMCFG_FREQ_30MHZ 0x80000000  // 30 - 50 MHz
+#define EPI_SDRAMCFG_FREQ_50MHZ 0xC0000000  // 50 - 100 MHz
+#define EPI_SDRAMCFG_RFSH_M     0x07FF0000  // Refresh Counter
+#define EPI_SDRAMCFG_SLEEP      0x00000200  // Sleep Mode
+#define EPI_SDRAMCFG_SIZE_M     0x00000003  // Size of SDRAM
+#define EPI_SDRAMCFG_SIZE_8MB   0x00000000  // 64 megabits (8MB)
+#define EPI_SDRAMCFG_SIZE_16MB  0x00000001  // 128 megabits (16MB)
+#define EPI_SDRAMCFG_SIZE_32MB  0x00000002  // 256 megabits (32MB)
+#define EPI_SDRAMCFG_SIZE_64MB  0x00000003  // 512 megabits (64MB)
+#define EPI_SDRAMCFG_RFSH_S     16
+
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the EPI_O_HB8CFG register.
 //
 //*****************************************************************************
-#define EPI_HB8CFG_XFFEN        0x00800000  // External FIFO FULL Enable.
-#define EPI_HB8CFG_XFEEN        0x00400000  // External FIFO EMPTY Enable.
-#define EPI_HB8CFG_WRHIGH       0x00200000  // WRITE Strobe Polarity.
-#define EPI_HB8CFG_RDHIGH       0x00100000  // READ Strobe Polarity.
-#define EPI_HB8CFG_MAXWAIT_M    0x0000FF00  // Maximum Wait.
-#define EPI_HB8CFG_WRWS_M       0x000000C0  // Write Wait States.
+#define EPI_HB8CFG_XFFEN        0x00800000  // External FIFO FULL Enable
+#define EPI_HB8CFG_XFEEN        0x00400000  // External FIFO EMPTY Enable
+#define EPI_HB8CFG_WRHIGH       0x00200000  // CS0n WRITE Strobe Polarity
+#define EPI_HB8CFG_RDHIGH       0x00100000  // CS0n READ Strobe Polarity
+#define EPI_HB8CFG_MAXWAIT_M    0x0000FF00  // Maximum Wait
+#define EPI_HB8CFG_WRWS_M       0x000000C0  // Write Wait States
 #define EPI_HB8CFG_WRWS_0       0x00000000  // No wait states
 #define EPI_HB8CFG_WRWS_1       0x00000040  // 1 wait state
 #define EPI_HB8CFG_WRWS_2       0x00000080  // 2 wait states
 #define EPI_HB8CFG_WRWS_3       0x000000C0  // 3 wait states
-#define EPI_HB8CFG_RDWS_M       0x00000030  // Read Wait States.
+#define EPI_HB8CFG_RDWS_M       0x00000030  // Read Wait States
 #define EPI_HB8CFG_RDWS_0       0x00000000  // No wait states
 #define EPI_HB8CFG_RDWS_1       0x00000010  // 1 wait state
 #define EPI_HB8CFG_RDWS_2       0x00000020  // 2 wait states
 #define EPI_HB8CFG_RDWS_3       0x00000030  // 3 wait states
-#define EPI_HB8CFG_MODE_M       0x00000003  // Host Bus Sub-Mode.
+#define EPI_HB8CFG_MODE_M       0x00000003  // Host Bus Sub-Mode
 #define EPI_HB8CFG_MODE_MUX     0x00000000  // ADMUX - AD[7:0]
 #define EPI_HB8CFG_MODE_NMUX    0x00000001  // ADNONMUX - D[7:0]
-#define EPI_HB8CFG_MODE_SRAM    0x00000002  // SRAM
+#define EPI_HB8CFG_MODE_SRAM    0x00000002  // Continuous Read - D[7:0]
 #define EPI_HB8CFG_MODE_FIFO    0x00000003  // XFIFO - D[7:0]
 #define EPI_HB8CFG_MAXWAIT_S    8
 
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the EPI_O_SDRAMCFG2
-// register.
-//
-//*****************************************************************************
-#define EPI_SDRAMCFG2_RCM       0x80000000  // Read Capture Mode.
-
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the EPI_O_HB8CFG2 register.
 //
 //*****************************************************************************
-#define EPI_HB8CFG2_WORD        0x80000000  // Word Access Mode.
-#define EPI_HB8CFG2_CSCFG       0x01000000  // Chip Select Configuration.
+#define EPI_HB8CFG2_WORD        0x80000000  // Word Access Mode
+#define EPI_HB8CFG2_CSBAUD      0x04000000  // Chip Select Baud Rate
+#define EPI_HB8CFG2_CSCFG_M     0x03000000  // Chip Select Configuration
+#define EPI_HB8CFG2_CSCFG_ALE   0x00000000  // ALE Configuration
+#define EPI_HB8CFG2_CSCFG_CS    0x01000000  // CSn Configuration
+#define EPI_HB8CFG2_CSCFG_DCS   0x02000000  // Dual CSn Configuration
+#define EPI_HB8CFG2_CSCFG_ADCS  0x03000000  // ALE with Dual CSn Configuration
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB16CFG2 register.
+//
+//*****************************************************************************
+#define EPI_HB16CFG2_WORD       0x80000000  // Word Access Mode
+#define EPI_HB16CFG2_CSBAUD     0x04000000  // Chip Select Baud Rate
+#define EPI_HB16CFG2_CSCFG_M    0x03000000  // Chip Select Configuration
+#define EPI_HB16CFG2_CSCFG_ALE  0x00000000  // ALE Configuration
+#define EPI_HB16CFG2_CSCFG_CS   0x01000000  // CSn Configuration
+#define EPI_HB16CFG2_CSCFG_DCS  0x02000000  // Dual CSn Configuration
+#define EPI_HB16CFG2_CSCFG_ADCS 0x03000000  // ALE with Dual CSn Configuration
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the EPI_O_GPCFG2 register.
 //
 //*****************************************************************************
-#define EPI_GPCFG2_WORD         0x80000000  // Word Access Mode.
+#define EPI_GPCFG2_WORD         0x80000000  // Word Access Mode
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the EPI_O_ADDRMAP register.
 //
 //*****************************************************************************
-#define EPI_ADDRMAP_EPSZ_M      0x000000C0  // External Peripheral Size.
-#define EPI_ADDRMAP_EPSZ_256B   0x00000000  // 0x100 (256)
-#define EPI_ADDRMAP_EPSZ_64KB   0x00000040  // 0x1.0000 (64 KB)
-#define EPI_ADDRMAP_EPSZ_16MB   0x00000080  // 0x100.0000 (16 MB)
-#define EPI_ADDRMAP_EPSZ_512MB  0x000000C0  // 0x2000.0000 (512 MB)
-#define EPI_ADDRMAP_EPADR_M     0x00000030  // External Peripheral Address.
+#define EPI_ADDRMAP_EPSZ_M      0x000000C0  // External Peripheral Size
+#define EPI_ADDRMAP_EPSZ_256B   0x00000000  // 256 bytes; lower address range:
+                                            // 0x00 to 0xFF
+#define EPI_ADDRMAP_EPSZ_64KB   0x00000040  // 64 KB; lower address range:
+                                            // 0x0000 to 0xFFFF
+#define EPI_ADDRMAP_EPSZ_16MB   0x00000080  // 16 MB; lower address range:
+                                            // 0x00.0000 to 0xFF.FFFF
+#define EPI_ADDRMAP_EPSZ_256MB  0x000000C0  // 256 MB; lower address range:
+                                            // 0x000.0000 to 0xFFF.FFFF
+#define EPI_ADDRMAP_EPADR_M     0x00000030  // External Peripheral Address
 #define EPI_ADDRMAP_EPADR_NONE  0x00000000  // Not mapped
 #define EPI_ADDRMAP_EPADR_A000  0x00000010  // At 0xA000.0000
 #define EPI_ADDRMAP_EPADR_C000  0x00000020  // At 0xC000.0000
-#define EPI_ADDRMAP_ERSZ_M      0x0000000C  // External RAM Size.
-#define EPI_ADDRMAP_ERSZ_256B   0x00000000  // 0x100 (256)
-#define EPI_ADDRMAP_ERSZ_64KB   0x00000004  // 0x1.0000 (64KB)
-#define EPI_ADDRMAP_ERSZ_16MB   0x00000008  // 0x100.0000 (16MB)
-#define EPI_ADDRMAP_ERSZ_512MB  0x0000000C  // 0x2000.0000 (512MB)
-#define EPI_ADDRMAP_ERADR_M     0x00000003  // External RAM Address.
+#define EPI_ADDRMAP_ERSZ_M      0x0000000C  // External RAM Size
+#define EPI_ADDRMAP_ERSZ_256B   0x00000000  // 256 bytes; lower address range:
+                                            // 0x00 to 0xFF
+#define EPI_ADDRMAP_ERSZ_64KB   0x00000004  // 64 KB; lower address range:
+                                            // 0x0000 to 0xFFFF
+#define EPI_ADDRMAP_ERSZ_16MB   0x00000008  // 16 MB; lower address range:
+                                            // 0x00.0000 to 0xFF.FFFF
+#define EPI_ADDRMAP_ERSZ_256MB  0x0000000C  // 256 MB; lower address range:
+                                            // 0x000.0000 to 0xFFF.FFFF
+#define EPI_ADDRMAP_ERADR_M     0x00000003  // External RAM Address
 #define EPI_ADDRMAP_ERADR_NONE  0x00000000  // Not mapped
 #define EPI_ADDRMAP_ERADR_6000  0x00000001  // At 0x6000.0000
 #define EPI_ADDRMAP_ERADR_8000  0x00000002  // At 0x8000.0000
@@ -9428,7 +9820,7 @@
 // The following are defines for the bit fields in the EPI_O_RSIZE0 register.
 //
 //*****************************************************************************
-#define EPI_RSIZE0_SIZE_M       0x00000003  // Current Size.
+#define EPI_RSIZE0_SIZE_M       0x00000003  // Current Size
 #define EPI_RSIZE0_SIZE_8BIT    0x00000001  // Byte (8 bits)
 #define EPI_RSIZE0_SIZE_16BIT   0x00000002  // Half-word (16 bits)
 #define EPI_RSIZE0_SIZE_32BIT   0x00000003  // Word (32 bits)
@@ -9438,7 +9830,7 @@
 // The following are defines for the bit fields in the EPI_O_RADDR0 register.
 //
 //*****************************************************************************
-#define EPI_RADDR0_ADDR_M       0x1FFFFFFF  // Current Address.
+#define EPI_RADDR0_ADDR_M       0x1FFFFFFF  // Current Address
 #define EPI_RADDR0_ADDR_S       0
 
 //*****************************************************************************
@@ -9446,7 +9838,7 @@
 // The following are defines for the bit fields in the EPI_O_RPSTD0 register.
 //
 //*****************************************************************************
-#define EPI_RPSTD0_POSTCNT_M    0x00001FFF  // Post Count.
+#define EPI_RPSTD0_POSTCNT_M    0x00001FFF  // Post Count
 #define EPI_RPSTD0_POSTCNT_S    0
 
 //*****************************************************************************
@@ -9454,7 +9846,7 @@
 // The following are defines for the bit fields in the EPI_O_RSIZE1 register.
 //
 //*****************************************************************************
-#define EPI_RSIZE1_SIZE_M       0x00000003  // Current Size.
+#define EPI_RSIZE1_SIZE_M       0x00000003  // Current Size
 #define EPI_RSIZE1_SIZE_8BIT    0x00000001  // Byte (8 bits)
 #define EPI_RSIZE1_SIZE_16BIT   0x00000002  // Half-word (16 bits)
 #define EPI_RSIZE1_SIZE_32BIT   0x00000003  // Word (32 bits)
@@ -9464,7 +9856,7 @@
 // The following are defines for the bit fields in the EPI_O_RADDR1 register.
 //
 //*****************************************************************************
-#define EPI_RADDR1_ADDR_M       0x1FFFFFFF  // Current Address.
+#define EPI_RADDR1_ADDR_M       0x1FFFFFFF  // Current Address
 #define EPI_RADDR1_ADDR_S       0
 
 //*****************************************************************************
@@ -9472,7 +9864,7 @@
 // The following are defines for the bit fields in the EPI_O_RPSTD1 register.
 //
 //*****************************************************************************
-#define EPI_RPSTD1_POSTCNT_M    0x00001FFF  // Post Count.
+#define EPI_RPSTD1_POSTCNT_M    0x00001FFF  // Post Count
 #define EPI_RPSTD1_POSTCNT_S    0
 
 //*****************************************************************************
@@ -9480,20 +9872,20 @@
 // The following are defines for the bit fields in the EPI_O_STAT register.
 //
 //*****************************************************************************
-#define EPI_STAT_CELOW          0x00000200  // Clock Enable Low.
-#define EPI_STAT_XFFULL         0x00000100  // External FIFO Full.
-#define EPI_STAT_XFEMPTY        0x00000080  // External FIFO Empty.
-#define EPI_STAT_INITSEQ        0x00000040  // Initialization Sequence.
-#define EPI_STAT_WBUSY          0x00000020  // Write Busy.
-#define EPI_STAT_NBRBUSY        0x00000010  // Non-Blocking Read Busy.
-#define EPI_STAT_ACTIVE         0x00000001  // Register Active.
+#define EPI_STAT_CELOW          0x00000200  // Clock Enable Low
+#define EPI_STAT_XFFULL         0x00000100  // External FIFO Full
+#define EPI_STAT_XFEMPTY        0x00000080  // External FIFO Empty
+#define EPI_STAT_INITSEQ        0x00000040  // Initialization Sequence
+#define EPI_STAT_WBUSY          0x00000020  // Write Busy
+#define EPI_STAT_NBRBUSY        0x00000010  // Non-Blocking Read Busy
+#define EPI_STAT_ACTIVE         0x00000001  // Register Active
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the EPI_O_RFIFOCNT register.
 //
 //*****************************************************************************
-#define EPI_RFIFOCNT_COUNT_M    0x00000007  // FIFO Count.
+#define EPI_RFIFOCNT_COUNT_M    0x00000007  // FIFO Count
 #define EPI_RFIFOCNT_COUNT_S    0
 
 //*****************************************************************************
@@ -9501,7 +9893,7 @@
 // The following are defines for the bit fields in the EPI_O_READFIFO register.
 //
 //*****************************************************************************
-#define EPI_READFIFO_DATA_M     0xFFFFFFFF  // Reads Data.
+#define EPI_READFIFO_DATA_M     0xFFFFFFFF  // Reads Data
 #define EPI_READFIFO_DATA_S     0
 
 //*****************************************************************************
@@ -9510,7 +9902,7 @@
 // register.
 //
 //*****************************************************************************
-#define EPI_READFIFO1_DATA_M    0xFFFFFFFF  // Reads Data.
+#define EPI_READFIFO1_DATA_M    0xFFFFFFFF  // Reads Data
 #define EPI_READFIFO1_DATA_S    0
 
 //*****************************************************************************
@@ -9519,7 +9911,7 @@
 // register.
 //
 //*****************************************************************************
-#define EPI_READFIFO2_DATA_M    0xFFFFFFFF  // Reads Data.
+#define EPI_READFIFO2_DATA_M    0xFFFFFFFF  // Reads Data
 #define EPI_READFIFO2_DATA_S    0
 
 //*****************************************************************************
@@ -9528,7 +9920,7 @@
 // register.
 //
 //*****************************************************************************
-#define EPI_READFIFO3_DATA_M    0xFFFFFFFF  // Reads Data.
+#define EPI_READFIFO3_DATA_M    0xFFFFFFFF  // Reads Data
 #define EPI_READFIFO3_DATA_S    0
 
 //*****************************************************************************
@@ -9537,7 +9929,7 @@
 // register.
 //
 //*****************************************************************************
-#define EPI_READFIFO4_DATA_M    0xFFFFFFFF  // Reads Data.
+#define EPI_READFIFO4_DATA_M    0xFFFFFFFF  // Reads Data
 #define EPI_READFIFO4_DATA_S    0
 
 //*****************************************************************************
@@ -9546,7 +9938,7 @@
 // register.
 //
 //*****************************************************************************
-#define EPI_READFIFO5_DATA_M    0xFFFFFFFF  // Reads Data.
+#define EPI_READFIFO5_DATA_M    0xFFFFFFFF  // Reads Data
 #define EPI_READFIFO5_DATA_S    0
 
 //*****************************************************************************
@@ -9555,7 +9947,7 @@
 // register.
 //
 //*****************************************************************************
-#define EPI_READFIFO6_DATA_M    0xFFFFFFFF  // Reads Data.
+#define EPI_READFIFO6_DATA_M    0xFFFFFFFF  // Reads Data
 #define EPI_READFIFO6_DATA_S    0
 
 //*****************************************************************************
@@ -9564,7 +9956,7 @@
 // register.
 //
 //*****************************************************************************
-#define EPI_READFIFO7_DATA_M    0xFFFFFFFF  // Reads Data.
+#define EPI_READFIFO7_DATA_M    0xFFFFFFFF  // Reads Data
 #define EPI_READFIFO7_DATA_S    0
 
 //*****************************************************************************
@@ -9572,37 +9964,38 @@
 // The following are defines for the bit fields in the EPI_O_FIFOLVL register.
 //
 //*****************************************************************************
-#define EPI_FIFOLVL_WFERR       0x00020000  // Write Full Error.
-#define EPI_FIFOLVL_RSERR       0x00010000  // Read Stall Error.
-#define EPI_FIFOLVL_WRFIFO_M    0x00000070  // Write FIFO.
+#define EPI_FIFOLVL_WFERR       0x00020000  // Write Full Error
+#define EPI_FIFOLVL_RSERR       0x00010000  // Read Stall Error
+#define EPI_FIFOLVL_WRFIFO_M    0x00000070  // Write FIFO
 #define EPI_FIFOLVL_WRFIFO_EMPT 0x00000000  // Trigger when there are 1 to 4
-                                            // spaces available in the WFIFO.
+                                            // spaces available in the WFIFO
 #define EPI_FIFOLVL_WRFIFO_1_4  0x00000020  // Trigger when there are 1 to 3
-                                            // spaces available in the WFIFO.
+                                            // spaces available in the WFIFO
 #define EPI_FIFOLVL_WRFIFO_1_2  0x00000030  // Trigger when there are 1 to 2
-                                            // spaces available in the WFIFO.
+                                            // spaces available in the WFIFO
 #define EPI_FIFOLVL_WRFIFO_3_4  0x00000040  // Trigger when there is 1 space
-                                            // available in the WFIFO.
-#define EPI_FIFOLVL_RDFIFO_M    0x00000007  // Read FIFO.
+                                            // available in the WFIFO
+#define EPI_FIFOLVL_RDFIFO_M    0x00000007  // Read FIFO
+#define EPI_FIFOLVL_RDFIFO_EMPT 0x00000000  // Empty
 #define EPI_FIFOLVL_RDFIFO_1_8  0x00000001  // Trigger when there are 1 or more
-                                            // entries in the NBRFIFO.
+                                            // entries in the NBRFIFO
 #define EPI_FIFOLVL_RDFIFO_1_4  0x00000002  // Trigger when there are 2 or more
-                                            // entries in the NBRFIFO.
+                                            // entries in the NBRFIFO
 #define EPI_FIFOLVL_RDFIFO_1_2  0x00000003  // Trigger when there are 4 or more
-                                            // entries in the NBRFIFO.
+                                            // entries in the NBRFIFO
 #define EPI_FIFOLVL_RDFIFO_3_4  0x00000004  // Trigger when there are 6 or more
-                                            // entries in the NBRFIFO.
+                                            // entries in the NBRFIFO
 #define EPI_FIFOLVL_RDFIFO_7_8  0x00000005  // Trigger when there are 7 or more
-                                            // entries in the NBRFIFO.
+                                            // entries in the NBRFIFO
 #define EPI_FIFOLVL_RDFIFO_FULL 0x00000006  // Trigger when there are 8 entries
-                                            // in the NBRFIFO.
+                                            // in the NBRFIFO
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the EPI_O_WFIFOCNT register.
 //
 //*****************************************************************************
-#define EPI_WFIFOCNT_WTAV_M     0x00000007  // Available Write Transactions.
+#define EPI_WFIFOCNT_WTAV_M     0x00000007  // Available Write Transactions
 #define EPI_WFIFOCNT_WTAV_S     0
 
 //*****************************************************************************
@@ -9610,43 +10003,43 @@
 // The following are defines for the bit fields in the EPI_O_IM register.
 //
 //*****************************************************************************
-#define EPI_IM_WRIM             0x00000004  // Write Interrupt Mask.
-#define EPI_IM_RDIM             0x00000002  // Read Interrupt Mask.
-#define EPI_IM_ERRIM            0x00000001  // Error Interrupt Mask.
+#define EPI_IM_WRIM             0x00000004  // Write Interrupt Mask
+#define EPI_IM_RDIM             0x00000002  // Read Interrupt Mask
+#define EPI_IM_ERRIM            0x00000001  // Error Interrupt Mask
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the EPI_O_RIS register.
 //
 //*****************************************************************************
-#define EPI_RIS_WRRIS           0x00000004  // Write Raw Interrupt Status.
-#define EPI_RIS_RDRIS           0x00000002  // Read Raw Interrupt Status.
-#define EPI_RIS_ERRRIS          0x00000001  // Error Raw Interrupt Status.
+#define EPI_RIS_WRRIS           0x00000004  // Write Raw Interrupt Status
+#define EPI_RIS_RDRIS           0x00000002  // Read Raw Interrupt Status
+#define EPI_RIS_ERRRIS          0x00000001  // Error Raw Interrupt Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the EPI_O_MIS register.
 //
 //*****************************************************************************
-#define EPI_MIS_WRMIS           0x00000004  // Write Masked Interrupt Status.
-#define EPI_MIS_RDMIS           0x00000002  // Read Masked Interrupt Status.
-#define EPI_MIS_ERRMIS          0x00000001  // Error Masked Interrupt Status.
+#define EPI_MIS_WRMIS           0x00000004  // Write Masked Interrupt Status
+#define EPI_MIS_RDMIS           0x00000002  // Read Masked Interrupt Status
+#define EPI_MIS_ERRMIS          0x00000001  // Error Masked Interrupt Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the EPI_O_EISC register.
 //
 //*****************************************************************************
-#define EPI_EISC_WTFULL         0x00000004  // Write FIFO Full Error.
-#define EPI_EISC_RSTALL         0x00000002  // Read Stalled Error.
-#define EPI_EISC_TOUT           0x00000001  // Timeout Error.
+#define EPI_EISC_WTFULL         0x00000004  // Write FIFO Full Error
+#define EPI_EISC_RSTALL         0x00000002  // Read Stalled Error
+#define EPI_EISC_TOUT           0x00000001  // Timeout Error
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the FLASH_FMA register.
 //
 //*****************************************************************************
-#define FLASH_FMA_OFFSET_M      0x0003FFFF  // Address Offset.
+#define FLASH_FMA_OFFSET_M      0x0003FFFF  // Address Offset
 #define FLASH_FMA_OFFSET_S      0
 
 //*****************************************************************************
@@ -9654,7 +10047,7 @@
 // The following are defines for the bit fields in the FLASH_FMD register.
 //
 //*****************************************************************************
-#define FLASH_FMD_DATA_M        0xFFFFFFFF  // Data Value.
+#define FLASH_FMD_DATA_M        0xFFFFFFFF  // Data Value
 #define FLASH_FMD_DATA_S        0
 
 //*****************************************************************************
@@ -9662,30 +10055,27 @@
 // The following are defines for the bit fields in the FLASH_FMC register.
 //
 //*****************************************************************************
-#define FLASH_FMC_WRKEY_M       0xFFFF0000  // Flash Memory Write Key.
 #define FLASH_FMC_WRKEY         0xA4420000  // FLASH write key
-#define FLASH_FMC_COMT          0x00000008  // Commit Register Value.
-#define FLASH_FMC_MERASE        0x00000004  // Mass Erase Flash Memory.
-#define FLASH_FMC_ERASE         0x00000002  // Erase a Page of Flash Memory.
-#define FLASH_FMC_WRITE         0x00000001  // Write a Word into Flash Memory.
-#define FLASH_FMC_WRKEY_S       16
+#define FLASH_FMC_COMT          0x00000008  // Commit Register Value
+#define FLASH_FMC_MERASE        0x00000004  // Mass Erase Flash Memory
+#define FLASH_FMC_ERASE         0x00000002  // Erase a Page of Flash Memory
+#define FLASH_FMC_WRITE         0x00000001  // Write a Word into Flash Memory
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the FLASH_FCRIS register.
 //
 //*****************************************************************************
-#define FLASH_FCRIS_PRIS        0x00000002  // Programming Raw Interrupt
-                                            // Status.
-#define FLASH_FCRIS_ARIS        0x00000001  // Access Raw Interrupt Status.
+#define FLASH_FCRIS_PRIS        0x00000002  // Programming Raw Interrupt Status
+#define FLASH_FCRIS_ARIS        0x00000001  // Access Raw Interrupt Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the FLASH_FCIM register.
 //
 //*****************************************************************************
-#define FLASH_FCIM_PMASK        0x00000002  // Programming Interrupt Mask.
-#define FLASH_FCIM_AMASK        0x00000001  // Access Interrupt Mask.
+#define FLASH_FCIM_PMASK        0x00000002  // Programming Interrupt Mask
+#define FLASH_FCIM_AMASK        0x00000001  // Access Interrupt Mask
 
 //*****************************************************************************
 //
@@ -9693,54 +10083,57 @@
 //
 //*****************************************************************************
 #define FLASH_FCMISC_PMISC      0x00000002  // Programming Masked Interrupt
-                                            // Status and Clear.
+                                            // Status and Clear
 #define FLASH_FCMISC_AMISC      0x00000001  // Access Masked Interrupt Status
-                                            // and Clear.
+                                            // and Clear
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the FLASH_FMC2 register.
 //
 //*****************************************************************************
-#define FLASH_FMC2_WRKEY_M      0xFFFF0000  // Flash Memory Write Key.
-#define FLASH_FMC2_WRBUF        0x00000001  // Buffered Flash Memory Write.
-#define FLASH_FMC2_WRKEY_S      16
+#define FLASH_FMC2_WRKEY        0xA4420000  // FLASH write key
+#define FLASH_FMC2_WRBUF        0x00000001  // Buffered Flash Memory Write
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the FLASH_FWBVAL register.
 //
 //*****************************************************************************
-#define FLASH_FWBVAL_FWB_M      0xFFFFFFFF  // Flash Memory Write Buffer.
+#define FLASH_FWBVAL_FWB_M      0xFFFFFFFF  // Flash Memory Write Buffer
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FCTL register.
+//
+//*****************************************************************************
+#define FLASH_FCTL_USDACK       0x00000002  // User Shut Down Acknowledge
+#define FLASH_FCTL_USDREQ       0x00000001  // User Shut Down Request
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the FLASH_FWBN register.
 //
 //*****************************************************************************
-#define FLASH_FWBN_DATA_M       0xFFFFFFFF  // Data.
-#define FLASH_FWBN_DATA_S       0
+#define FLASH_FWBN_DATA_M       0xFFFFFFFF  // Data
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the FLASH_RMCTL register.
 //
 //*****************************************************************************
-#define FLASH_RMCTL_BA          0x00000001  // Boot Alias.
+#define FLASH_RMCTL_BA          0x00000001  // Boot Alias
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the FLASH_RMVER register.
 //
 //*****************************************************************************
-#define FLASH_RMVER_CONT_M      0xFF000000  // ROM Contents.
+#define FLASH_RMVER_CONT_M      0xFF000000  // ROM Contents
 #define FLASH_RMVER_CONT_LM_AES 0x02000000  // Stellaris Boot Loader &
                                             // DriverLib with AES
-#define FLASH_RMVER_SIZE_M      0x00FF0000  // ROM Size.
-#define FLASH_RMVER_SIZE_23_75K 0x00020000  // Stellaris Boot Loader &
-                                            // DriverLib with AES,ethernet
-#define FLASH_RMVER_VER_M       0x0000FF00  // ROM Version.
-#define FLASH_RMVER_REV_M       0x000000FF  // ROM Revision.
+#define FLASH_RMVER_VER_M       0x0000FF00  // ROM Version
+#define FLASH_RMVER_REV_M       0x000000FF  // ROM Revision
 #define FLASH_RMVER_VER_S       8
 #define FLASH_RMVER_REV_S       0
 
@@ -9749,19 +10142,48 @@
 // The following are defines for the bit fields in the FLASH_USERDBG register.
 //
 //*****************************************************************************
-#define FLASH_USERDBG_NW        0x80000000  // User Debug Not Written.
-#define FLASH_USERDBG_DATA_M    0x7FFFFFFC  // User Data.
-#define FLASH_USERDBG_DBG1      0x00000002  // Debug Control 1.
-#define FLASH_USERDBG_DBG0      0x00000001  // Debug Control 0.
+#define FLASH_USERDBG_NW        0x80000000  // User Debug Not Written
+#define FLASH_USERDBG_DATA_M    0x7FFFFFFC  // User Data
+#define FLASH_USERDBG_DBG1      0x00000002  // Debug Control 1
+#define FLASH_USERDBG_DBG0      0x00000001  // Debug Control 0
 #define FLASH_USERDBG_DATA_S    2
 
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_BOOTCFG register.
+//
+//*****************************************************************************
+#define FLASH_BOOTCFG_NW        0x80000000  // Not Written
+#define FLASH_BOOTCFG_PORT_M    0x0000E000  // Boot GPIO Port
+#define FLASH_BOOTCFG_PORT_A    0x00000000  // Port A
+#define FLASH_BOOTCFG_PORT_B    0x00002000  // Port B
+#define FLASH_BOOTCFG_PORT_C    0x00004000  // Port C
+#define FLASH_BOOTCFG_PORT_D    0x00006000  // Port D
+#define FLASH_BOOTCFG_PORT_E    0x00008000  // Port E
+#define FLASH_BOOTCFG_PORT_F    0x0000A000  // Port F
+#define FLASH_BOOTCFG_PORT_G    0x0000C000  // Port G
+#define FLASH_BOOTCFG_PORT_H    0x0000E000  // Port H
+#define FLASH_BOOTCFG_PIN_M     0x00001C00  // Boot GPIO Pin
+#define FLASH_BOOTCFG_PIN_0     0x00000000  // Pin 0
+#define FLASH_BOOTCFG_PIN_1     0x00000400  // Pin 1
+#define FLASH_BOOTCFG_PIN_2     0x00000800  // Pin 2
+#define FLASH_BOOTCFG_PIN_3     0x00000C00  // Pin 3
+#define FLASH_BOOTCFG_PIN_4     0x00001000  // Pin 4
+#define FLASH_BOOTCFG_PIN_5     0x00001400  // Pin 5
+#define FLASH_BOOTCFG_PIN_6     0x00001800  // Pin 6
+#define FLASH_BOOTCFG_PIN_7     0x00001C00  // Pin 7
+#define FLASH_BOOTCFG_POL       0x00000200  // Boot GPIO Polarity
+#define FLASH_BOOTCFG_EN        0x00000100  // Boot GPIO Enable
+#define FLASH_BOOTCFG_DBG1      0x00000002  // Debug Control 1
+#define FLASH_BOOTCFG_DBG0      0x00000001  // Debug Control 0
+
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the FLASH_USERREG0 register.
 //
 //*****************************************************************************
-#define FLASH_USERREG0_NW       0x80000000  // Not Written.
-#define FLASH_USERREG0_DATA_M   0x7FFFFFFF  // User Data.
+#define FLASH_USERREG0_NW       0x80000000  // Not Written
+#define FLASH_USERREG0_DATA_M   0x7FFFFFFF  // User Data
 #define FLASH_USERREG0_DATA_S   0
 
 //*****************************************************************************
@@ -9769,8 +10191,8 @@
 // The following are defines for the bit fields in the FLASH_USERREG1 register.
 //
 //*****************************************************************************
-#define FLASH_USERREG1_NW       0x80000000  // Not Written.
-#define FLASH_USERREG1_DATA_M   0x7FFFFFFF  // User Data.
+#define FLASH_USERREG1_NW       0x80000000  // Not Written
+#define FLASH_USERREG1_DATA_M   0x7FFFFFFF  // User Data
 #define FLASH_USERREG1_DATA_S   0
 
 //*****************************************************************************
@@ -9778,8 +10200,8 @@
 // The following are defines for the bit fields in the FLASH_USERREG2 register.
 //
 //*****************************************************************************
-#define FLASH_USERREG2_NW       0x80000000  // Not Written.
-#define FLASH_USERREG2_DATA_M   0x7FFFFFFF  // User Data.
+#define FLASH_USERREG2_NW       0x80000000  // Not Written
+#define FLASH_USERREG2_DATA_M   0x7FFFFFFF  // User Data
 #define FLASH_USERREG2_DATA_S   0
 
 //*****************************************************************************
@@ -9787,8 +10209,8 @@
 // The following are defines for the bit fields in the FLASH_USERREG3 register.
 //
 //*****************************************************************************
-#define FLASH_USERREG3_NW       0x80000000  // Not Written.
-#define FLASH_USERREG3_DATA_M   0x7FFFFFFF  // User Data.
+#define FLASH_USERREG3_NW       0x80000000  // Not Written
+#define FLASH_USERREG3_DATA_M   0x7FFFFFFF  // User Data
 #define FLASH_USERREG3_DATA_S   0
 
 //*****************************************************************************
@@ -9806,57 +10228,56 @@
 // The following are defines for the bit fields in the SYSCTL_DID0 register.
 //
 //*****************************************************************************
-#define SYSCTL_DID0_VER_M       0x70000000  // DID0 Version.
+#define SYSCTL_DID0_VER_M       0x70000000  // DID0 Version
 #define SYSCTL_DID0_VER_1       0x10000000  // Second version of the DID0
-                                            // register format.
-#define SYSCTL_DID0_CLASS_M     0x00FF0000  // Device Class.
+                                            // register format
+#define SYSCTL_DID0_CLASS_M     0x00FF0000  // Device Class
 #define SYSCTL_DID0_CLASS_TEMPEST \
-                                0x00040000  // Stellaris(r) Tempest-class
+                                0x00040000  // Stellaris(R) Tempest-class
                                             // microcontrollers
-#define SYSCTL_DID0_MAJ_M       0x0000FF00  // Major Revision.
+#define SYSCTL_DID0_MAJ_M       0x0000FF00  // Major Revision
 #define SYSCTL_DID0_MAJ_REVA    0x00000000  // Revision A (initial device)
 #define SYSCTL_DID0_MAJ_REVB    0x00000100  // Revision B (first base layer
                                             // revision)
 #define SYSCTL_DID0_MAJ_REVC    0x00000200  // Revision C (second base layer
                                             // revision)
-#define SYSCTL_DID0_MIN_M       0x000000FF  // Minor Revision.
+#define SYSCTL_DID0_MIN_M       0x000000FF  // Minor Revision
 #define SYSCTL_DID0_MIN_0       0x00000000  // Initial device, or a major
-                                            // revision update.
-#define SYSCTL_DID0_MIN_1       0x00000001  // First metal layer change.
-#define SYSCTL_DID0_MIN_2       0x00000002  // Second metal layer change.
+                                            // revision update
+#define SYSCTL_DID0_MIN_1       0x00000001  // First metal layer change
+#define SYSCTL_DID0_MIN_2       0x00000002  // Second metal layer change
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_DID1 register.
 //
 //*****************************************************************************
-#define SYSCTL_DID1_VER_M       0xF0000000  // DID1 Version.
+#define SYSCTL_DID1_VER_M       0xF0000000  // DID1 Version
 #define SYSCTL_DID1_VER_1       0x10000000  // Second version of the DID1
-                                            // register format.
-#define SYSCTL_DID1_FAM_M       0x0F000000  // Family.
+                                            // register format
+#define SYSCTL_DID1_FAM_M       0x0F000000  // Family
 #define SYSCTL_DID1_FAM_STELLARIS \
                                 0x00000000  // Stellaris family of
                                             // microcontollers, that is, all
                                             // devices with external part
-                                            // numbers starting
-                                            // with LM3S.
-#define SYSCTL_DID1_PRTNO_M     0x00FF0000  // Part Number.
+                                            // numbers starting with LM3S
+#define SYSCTL_DID1_PRTNO_M     0x00FF0000  // Part Number
 #define SYSCTL_DID1_PRTNO_9B92  0x006A0000  // LM3S9B92
-#define SYSCTL_DID1_PINCNT_M    0x0000E000  // Package Pin Count.
+#define SYSCTL_DID1_PINCNT_M    0x0000E000  // Package Pin Count
 #define SYSCTL_DID1_PINCNT_100  0x00004000  // 100-pin package
-#define SYSCTL_DID1_TEMP_M      0x000000E0  // Temperature Range.
+#define SYSCTL_DID1_TEMP_M      0x000000E0  // Temperature Range
 #define SYSCTL_DID1_TEMP_C      0x00000000  // Commercial temperature range (0C
                                             // to 70C)
 #define SYSCTL_DID1_TEMP_I      0x00000020  // Industrial temperature range
                                             // (-40C to 85C)
 #define SYSCTL_DID1_TEMP_E      0x00000040  // Extended temperature range (-40C
                                             // to 105C)
-#define SYSCTL_DID1_PKG_M       0x00000018  // Package Type.
-#define SYSCTL_DID1_PKG_28SOIC  0x00000000  // SOIC package
-#define SYSCTL_DID1_PKG_48QFP   0x00000008  // LQFP package
+#define SYSCTL_DID1_PKG_M       0x00000018  // Package Type
+#define SYSCTL_DID1_PKG_SOIC    0x00000000  // SOIC package
+#define SYSCTL_DID1_PKG_QFP     0x00000008  // LQFP package
 #define SYSCTL_DID1_PKG_BGA     0x00000010  // BGA package
-#define SYSCTL_DID1_ROHS        0x00000004  // RoHS-Compliance.
-#define SYSCTL_DID1_QUAL_M      0x00000003  // Qualification Status.
+#define SYSCTL_DID1_ROHS        0x00000004  // RoHS-Compliance
+#define SYSCTL_DID1_QUAL_M      0x00000003  // Qualification Status
 #define SYSCTL_DID1_QUAL_ES     0x00000000  // Engineering Sample (unqualified)
 #define SYSCTL_DID1_QUAL_PP     0x00000001  // Pilot Production (unqualified)
 #define SYSCTL_DID1_QUAL_FQ     0x00000002  // Fully Qualified
@@ -9866,9 +10287,9 @@
 // The following are defines for the bit fields in the SYSCTL_DC0 register.
 //
 //*****************************************************************************
-#define SYSCTL_DC0_SRAMSZ_M     0xFFFF0000  // SRAM Size.
+#define SYSCTL_DC0_SRAMSZ_M     0xFFFF0000  // SRAM Size
 #define SYSCTL_DC0_SRAMSZ_96KB  0x017F0000  // 96 KB of SRAM
-#define SYSCTL_DC0_FLASHSZ_M    0x0000FFFF  // Flash Size.
+#define SYSCTL_DC0_FLASHSZ_M    0x0000FFFF  // Flash Size
 #define SYSCTL_DC0_FLASHSZ_256K 0x0000007F  // 256 KB of Flash
 #define SYSCTL_DC0_SRAMSZ_S     16          // SRAM size shift
 #define SYSCTL_DC0_FLASHSZ_S    0           // Flash size shift
@@ -9878,280 +10299,284 @@
 // The following are defines for the bit fields in the SYSCTL_DC1 register.
 //
 //*****************************************************************************
-#define SYSCTL_DC1_WDT1         0x10000000  // Watchdog Timer1 Present.
-#define SYSCTL_DC1_CAN1         0x02000000  // CAN Module 1 Present.
-#define SYSCTL_DC1_CAN0         0x01000000  // CAN Module 0 Present.
-#define SYSCTL_DC1_PWM          0x00100000  // PWM Module Present.
-#define SYSCTL_DC1_ADC1         0x00020000  // ADC Module 1 Present.
-#define SYSCTL_DC1_ADC0         0x00010000  // ADC Module 0 Present.
-#define SYSCTL_DC1_MINSYSDIV_M  0x0000F000  // System Clock Divider.
+#define SYSCTL_DC1_WDT1         0x10000000  // Watchdog Timer1 Present
+#define SYSCTL_DC1_CAN1         0x02000000  // CAN Module 1 Present
+#define SYSCTL_DC1_CAN0         0x01000000  // CAN Module 0 Present
+#define SYSCTL_DC1_PWM          0x00100000  // PWM Module Present
+#define SYSCTL_DC1_ADC1         0x00020000  // ADC Module 1 Present
+#define SYSCTL_DC1_ADC0         0x00010000  // ADC Module 0 Present
+#define SYSCTL_DC1_MINSYSDIV_M  0x0000F000  // System Clock Divider
 #define SYSCTL_DC1_MINSYSDIV_100 \
                                 0x00001000  // Divide VCO (400MHZ) by 5 minimum
 #define SYSCTL_DC1_MINSYSDIV_66 0x00002000  // Divide VCO (400MHZ) by 2*2 + 2 =
                                             // 6 minimum
 #define SYSCTL_DC1_MINSYSDIV_50 0x00003000  // Specifies a 50-MHz CPU clock
-                                            // with a PLL divider of 4.
+                                            // with a PLL divider of 4
 #define SYSCTL_DC1_MINSYSDIV_25 0x00007000  // Specifies a 25-MHz clock with a
-                                            // PLL divider of 8.
+                                            // PLL divider of 8
 #define SYSCTL_DC1_MINSYSDIV_20 0x00009000  // Specifies a 20-MHz clock with a
-                                            // PLL divider of 10.
-#define SYSCTL_DC1_ADC1SPD_M    0x00000C00  // Max ADC1 Speed.
+                                            // PLL divider of 10
+#define SYSCTL_DC1_ADC1SPD_M    0x00000C00  // Max ADC1 Speed
 #define SYSCTL_DC1_ADC1SPD_1M   0x00000C00  // 1M samples/second
-#define SYSCTL_DC1_ADC0SPD_M    0x00000300  // Max ADC0 Speed.
+#define SYSCTL_DC1_ADC0SPD_M    0x00000300  // Max ADC0 Speed
 #define SYSCTL_DC1_ADC0SPD_1M   0x00000300  // 1M samples/second
-#define SYSCTL_DC1_MPU          0x00000080  // MPU Present.
-#define SYSCTL_DC1_TEMP         0x00000020  // Temp Sensor Present.
-#define SYSCTL_DC1_PLL          0x00000010  // PLL Present.
-#define SYSCTL_DC1_WDT0         0x00000008  // Watchdog Timer 0 Present.
-#define SYSCTL_DC1_SWO          0x00000004  // SWO Trace Port Present.
-#define SYSCTL_DC1_SWD          0x00000002  // SWD Present.
-#define SYSCTL_DC1_JTAG         0x00000001  // JTAG Present.
+#define SYSCTL_DC1_MPU          0x00000080  // MPU Present
+#define SYSCTL_DC1_TEMP         0x00000020  // Temp Sensor Present
+#define SYSCTL_DC1_PLL          0x00000010  // PLL Present
+#define SYSCTL_DC1_WDT0         0x00000008  // Watchdog Timer 0 Present
+#define SYSCTL_DC1_SWO          0x00000004  // SWO Trace Port Present
+#define SYSCTL_DC1_SWD          0x00000002  // SWD Present
+#define SYSCTL_DC1_JTAG         0x00000001  // JTAG Present
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_DC2 register.
 //
 //*****************************************************************************
-#define SYSCTL_DC2_EPI0         0x40000000  // EPI Module 0 Present.
-#define SYSCTL_DC2_I2S0         0x10000000  // I2S Module 0 Present.
-#define SYSCTL_DC2_COMP2        0x04000000  // Analog Comparator 2 Present.
-#define SYSCTL_DC2_COMP1        0x02000000  // Analog Comparator 1 Present.
-#define SYSCTL_DC2_COMP0        0x01000000  // Analog Comparator 0 Present.
-#define SYSCTL_DC2_TIMER3       0x00080000  // Timer Module 3 Present.
-#define SYSCTL_DC2_TIMER2       0x00040000  // Timer Module 2 Present.
-#define SYSCTL_DC2_TIMER1       0x00020000  // Timer Module 1 Present.
-#define SYSCTL_DC2_TIMER0       0x00010000  // Timer Module 0 Present.
-#define SYSCTL_DC2_I2C1         0x00004000  // I2C Module 1 Present.
-#define SYSCTL_DC2_I2C0         0x00001000  // I2C Module 0 Present.
-#define SYSCTL_DC2_QEI1         0x00000200  // QEI Module 1 Present.
-#define SYSCTL_DC2_QEI0         0x00000100  // QEI Module 0 Present.
-#define SYSCTL_DC2_SSI1         0x00000020  // SSI Module 1 Present.
-#define SYSCTL_DC2_SSI0         0x00000010  // SSI Module 0 Present.
-#define SYSCTL_DC2_UART2        0x00000004  // UART Module 2 Present.
-#define SYSCTL_DC2_UART1        0x00000002  // UART Module 1 Present.
-#define SYSCTL_DC2_UART0        0x00000001  // UART Module 0 Present.
+#define SYSCTL_DC2_EPI0         0x40000000  // EPI Module 0 Present
+#define SYSCTL_DC2_I2S0         0x10000000  // I2S Module 0 Present
+#define SYSCTL_DC2_COMP2        0x04000000  // Analog Comparator 2 Present
+#define SYSCTL_DC2_COMP1        0x02000000  // Analog Comparator 1 Present
+#define SYSCTL_DC2_COMP0        0x01000000  // Analog Comparator 0 Present
+#define SYSCTL_DC2_TIMER3       0x00080000  // Timer Module 3 Present
+#define SYSCTL_DC2_TIMER2       0x00040000  // Timer Module 2 Present
+#define SYSCTL_DC2_TIMER1       0x00020000  // Timer Module 1 Present
+#define SYSCTL_DC2_TIMER0       0x00010000  // Timer Module 0 Present
+#define SYSCTL_DC2_I2C1         0x00004000  // I2C Module 1 Present
+#define SYSCTL_DC2_I2C0         0x00001000  // I2C Module 0 Present
+#define SYSCTL_DC2_QEI1         0x00000200  // QEI Module 1 Present
+#define SYSCTL_DC2_QEI0         0x00000100  // QEI Module 0 Present
+#define SYSCTL_DC2_SSI1         0x00000020  // SSI Module 1 Present
+#define SYSCTL_DC2_SSI0         0x00000010  // SSI Module 0 Present
+#define SYSCTL_DC2_UART2        0x00000004  // UART Module 2 Present
+#define SYSCTL_DC2_UART1        0x00000002  // UART Module 1 Present
+#define SYSCTL_DC2_UART0        0x00000001  // UART Module 0 Present
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_DC3 register.
 //
 //*****************************************************************************
-#define SYSCTL_DC3_32KHZ        0x80000000  // 32KHz Input Clock Available.
-#define SYSCTL_DC3_CCP5         0x20000000  // CCP5 Pin Present.
-#define SYSCTL_DC3_CCP4         0x10000000  // CCP4 Pin Present.
-#define SYSCTL_DC3_CCP3         0x08000000  // CCP3 Pin Present.
-#define SYSCTL_DC3_CCP2         0x04000000  // CCP2 Pin Present.
-#define SYSCTL_DC3_CCP1         0x02000000  // CCP1 Pin Present.
-#define SYSCTL_DC3_CCP0         0x01000000  // CCP0 Pin Present.
-#define SYSCTL_DC3_ADC0AIN7     0x00800000  // ADC Module 0 AIN7 Pin Present.
-#define SYSCTL_DC3_ADC0AIN6     0x00400000  // ADC Module 0 AIN6 Pin Present.
-#define SYSCTL_DC3_ADC0AIN5     0x00200000  // ADC Module 0 AIN5 Pin Present.
-#define SYSCTL_DC3_ADC0AIN4     0x00100000  // ADC Module 0 AIN4 Pin Present.
-#define SYSCTL_DC3_ADC0AIN3     0x00080000  // ADC Module 0 AIN3 Pin Present.
-#define SYSCTL_DC3_ADC0AIN2     0x00040000  // ADC Module 0 AIN2 Pin Present.
-#define SYSCTL_DC3_ADC0AIN1     0x00020000  // ADC Module 0 AIN1 Pin Present.
-#define SYSCTL_DC3_ADC0AIN0     0x00010000  // ADC Module 0 AIN0 Pin Present.
-#define SYSCTL_DC3_PWMFAULT     0x00008000  // PWM Fault Pin Present.
-#define SYSCTL_DC3_C2PLUS       0x00002000  // C2+ Pin Present.
-#define SYSCTL_DC3_C2MINUS      0x00001000  // C2- Pin Present.
-#define SYSCTL_DC3_C1PLUS       0x00000400  // C1+ Pin Present.
-#define SYSCTL_DC3_C1MINUS      0x00000200  // C1- Pin Present.
-#define SYSCTL_DC3_C0PLUS       0x00000080  // C0+ Pin Present.
-#define SYSCTL_DC3_C0MINUS      0x00000040  // C0- Pin Present.
-#define SYSCTL_DC3_PWM5         0x00000020  // PWM5 Pin Present.
-#define SYSCTL_DC3_PWM4         0x00000010  // PWM4 Pin Present.
-#define SYSCTL_DC3_PWM3         0x00000008  // PWM3 Pin Present.
-#define SYSCTL_DC3_PWM2         0x00000004  // PWM2 Pin Present.
-#define SYSCTL_DC3_PWM1         0x00000002  // PWM1 Pin Present.
-#define SYSCTL_DC3_PWM0         0x00000001  // PWM0 Pin Present.
+#define SYSCTL_DC3_32KHZ        0x80000000  // 32KHz Input Clock Available
+#define SYSCTL_DC3_CCP5         0x20000000  // CCP5 Pin Present
+#define SYSCTL_DC3_CCP4         0x10000000  // CCP4 Pin Present
+#define SYSCTL_DC3_CCP3         0x08000000  // CCP3 Pin Present
+#define SYSCTL_DC3_CCP2         0x04000000  // CCP2 Pin Present
+#define SYSCTL_DC3_CCP1         0x02000000  // CCP1 Pin Present
+#define SYSCTL_DC3_CCP0         0x01000000  // CCP0 Pin Present
+#define SYSCTL_DC3_ADC0AIN7     0x00800000  // ADC Module 0 AIN7 Pin Present
+#define SYSCTL_DC3_ADC0AIN6     0x00400000  // ADC Module 0 AIN6 Pin Present
+#define SYSCTL_DC3_ADC0AIN5     0x00200000  // ADC Module 0 AIN5 Pin Present
+#define SYSCTL_DC3_ADC0AIN4     0x00100000  // ADC Module 0 AIN4 Pin Present
+#define SYSCTL_DC3_ADC0AIN3     0x00080000  // ADC Module 0 AIN3 Pin Present
+#define SYSCTL_DC3_ADC0AIN2     0x00040000  // ADC Module 0 AIN2 Pin Present
+#define SYSCTL_DC3_ADC0AIN1     0x00020000  // ADC Module 0 AIN1 Pin Present
+#define SYSCTL_DC3_ADC0AIN0     0x00010000  // ADC Module 0 AIN0 Pin Present
+#define SYSCTL_DC3_PWMFAULT     0x00008000  // PWM Fault Pin Present
+#define SYSCTL_DC3_C2O          0x00004000  // C2o Pin Present
+#define SYSCTL_DC3_C2PLUS       0x00002000  // C2+ Pin Present
+#define SYSCTL_DC3_C2MINUS      0x00001000  // C2- Pin Present
+#define SYSCTL_DC3_C1O          0x00000800  // C1o Pin Present
+#define SYSCTL_DC3_C1PLUS       0x00000400  // C1+ Pin Present
+#define SYSCTL_DC3_C1MINUS      0x00000200  // C1- Pin Present
+#define SYSCTL_DC3_C0O          0x00000100  // C0o Pin Present
+#define SYSCTL_DC3_C0PLUS       0x00000080  // C0+ Pin Present
+#define SYSCTL_DC3_C0MINUS      0x00000040  // C0- Pin Present
+#define SYSCTL_DC3_PWM5         0x00000020  // PWM5 Pin Present
+#define SYSCTL_DC3_PWM4         0x00000010  // PWM4 Pin Present
+#define SYSCTL_DC3_PWM3         0x00000008  // PWM3 Pin Present
+#define SYSCTL_DC3_PWM2         0x00000004  // PWM2 Pin Present
+#define SYSCTL_DC3_PWM1         0x00000002  // PWM1 Pin Present
+#define SYSCTL_DC3_PWM0         0x00000001  // PWM0 Pin Present
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_DC4 register.
 //
 //*****************************************************************************
-#define SYSCTL_DC4_EPHY0        0x40000000  // Ethernet PHY Layer 0 Present.
-#define SYSCTL_DC4_EMAC0        0x10000000  // Ethernet MAC Layer 0 Present.
-#define SYSCTL_DC4_CCP7         0x00008000  // CCP7 Pin Present.
-#define SYSCTL_DC4_CCP6         0x00004000  // CCP6 Pin Present.
-#define SYSCTL_DC4_UDMA         0x00002000  // Micro-DMA Module Present.
-#define SYSCTL_DC4_ROM          0x00001000  // Internal Code ROM Present.
-#define SYSCTL_DC4_GPIOJ        0x00000100  // GPIO Port J Present.
-#define SYSCTL_DC4_GPIOH        0x00000080  // GPIO Port H Present.
-#define SYSCTL_DC4_GPIOG        0x00000040  // GPIO Port G Present.
-#define SYSCTL_DC4_GPIOF        0x00000020  // GPIO Port F Present.
-#define SYSCTL_DC4_GPIOE        0x00000010  // GPIO Port E Present.
-#define SYSCTL_DC4_GPIOD        0x00000008  // GPIO Port D Present.
-#define SYSCTL_DC4_GPIOC        0x00000004  // GPIO Port C Present.
-#define SYSCTL_DC4_GPIOB        0x00000002  // GPIO Port B Present.
-#define SYSCTL_DC4_GPIOA        0x00000001  // GPIO Port A Present.
+#define SYSCTL_DC4_EPHY0        0x40000000  // Ethernet PHY Layer 0 Present
+#define SYSCTL_DC4_EMAC0        0x10000000  // Ethernet MAC Layer 0 Present
+#define SYSCTL_DC4_PICAL        0x00040000  // PIOSC Calibrate
+#define SYSCTL_DC4_CCP7         0x00008000  // CCP7 Pin Present
+#define SYSCTL_DC4_CCP6         0x00004000  // CCP6 Pin Present
+#define SYSCTL_DC4_UDMA         0x00002000  // Micro-DMA Module Present
+#define SYSCTL_DC4_ROM          0x00001000  // Internal Code ROM Present
+#define SYSCTL_DC4_GPIOJ        0x00000100  // GPIO Port J Present
+#define SYSCTL_DC4_GPIOH        0x00000080  // GPIO Port H Present
+#define SYSCTL_DC4_GPIOG        0x00000040  // GPIO Port G Present
+#define SYSCTL_DC4_GPIOF        0x00000020  // GPIO Port F Present
+#define SYSCTL_DC4_GPIOE        0x00000010  // GPIO Port E Present
+#define SYSCTL_DC4_GPIOD        0x00000008  // GPIO Port D Present
+#define SYSCTL_DC4_GPIOC        0x00000004  // GPIO Port C Present
+#define SYSCTL_DC4_GPIOB        0x00000002  // GPIO Port B Present
+#define SYSCTL_DC4_GPIOA        0x00000001  // GPIO Port A Present
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_DC5 register.
 //
 //*****************************************************************************
-#define SYSCTL_DC5_PWMFAULT3    0x08000000  // PWM Fault 3 Pin Present.
-#define SYSCTL_DC5_PWMFAULT2    0x04000000  // PWM Fault 2 Pin Present.
-#define SYSCTL_DC5_PWMFAULT1    0x02000000  // PWM Fault 1 Pin Present.
-#define SYSCTL_DC5_PWMFAULT0    0x01000000  // PWM Fault 0 Pin Present.
-#define SYSCTL_DC5_PWMEFLT      0x00200000  // PWM Extended Fault Active.
-#define SYSCTL_DC5_PWMESYNC     0x00100000  // PWM Extended SYNC Active.
-#define SYSCTL_DC5_PWM7         0x00000080  // PWM7 Pin Present.
-#define SYSCTL_DC5_PWM6         0x00000040  // PWM6 Pin Present.
-#define SYSCTL_DC5_PWM5         0x00000020  // PWM5 Pin Present.
-#define SYSCTL_DC5_PWM4         0x00000010  // PWM4 Pin Present.
-#define SYSCTL_DC5_PWM3         0x00000008  // PWM3 Pin Present.
-#define SYSCTL_DC5_PWM2         0x00000004  // PWM2 Pin Present.
-#define SYSCTL_DC5_PWM1         0x00000002  // PWM1 Pin Present.
-#define SYSCTL_DC5_PWM0         0x00000001  // PWM0 Pin Present.
+#define SYSCTL_DC5_PWMFAULT3    0x08000000  // PWM Fault 3 Pin Present
+#define SYSCTL_DC5_PWMFAULT2    0x04000000  // PWM Fault 2 Pin Present
+#define SYSCTL_DC5_PWMFAULT1    0x02000000  // PWM Fault 1 Pin Present
+#define SYSCTL_DC5_PWMFAULT0    0x01000000  // PWM Fault 0 Pin Present
+#define SYSCTL_DC5_PWMEFLT      0x00200000  // PWM Extended Fault Active
+#define SYSCTL_DC5_PWMESYNC     0x00100000  // PWM Extended SYNC Active
+#define SYSCTL_DC5_PWM7         0x00000080  // PWM7 Pin Present
+#define SYSCTL_DC5_PWM6         0x00000040  // PWM6 Pin Present
+#define SYSCTL_DC5_PWM5         0x00000020  // PWM5 Pin Present
+#define SYSCTL_DC5_PWM4         0x00000010  // PWM4 Pin Present
+#define SYSCTL_DC5_PWM3         0x00000008  // PWM3 Pin Present
+#define SYSCTL_DC5_PWM2         0x00000004  // PWM2 Pin Present
+#define SYSCTL_DC5_PWM1         0x00000002  // PWM1 Pin Present
+#define SYSCTL_DC5_PWM0         0x00000001  // PWM0 Pin Present
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_DC6 register.
 //
 //*****************************************************************************
-#define SYSCTL_DC6_USB0PHY      0x00000010  // USB Module 0 PHY Present.
-#define SYSCTL_DC6_USB0_M       0x00000003  // USB Module 0 Present.
-#define SYSCTL_DC6_USB0_OTG     0x00000003  // USB0 is OTG.
+#define SYSCTL_DC6_USB0PHY      0x00000010  // USB Module 0 PHY Present
+#define SYSCTL_DC6_USB0_M       0x00000003  // USB Module 0 Present
+#define SYSCTL_DC6_USB0_OTG     0x00000003  // USB0 is OTG
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_DC7 register.
 //
 //*****************************************************************************
-#define SYSCTL_DC7_DMACH30      0x40000000  // SW.
-#define SYSCTL_DC7_DMACH29      0x20000000  // I2S0_TX / CAN1_TX.
-#define SYSCTL_DC7_DMACH28      0x10000000  // I2S0_RX / CAN1_RX.
-#define SYSCTL_DC7_DMACH27      0x08000000  // CAN1_TX / ADC1_SS3.
-#define SYSCTL_DC7_DMACH26      0x04000000  // CAN1_RX / ADC1_SS2.
-#define SYSCTL_DC7_DMACH25      0x02000000  // SSI1_TX / ADC1_SS1.
-#define SYSCTL_DC7_DMACH24      0x01000000  // SSI1_RX / ADC1_SS0.
-#define SYSCTL_DC7_DMACH23      0x00800000  // UART1_TX / CAN2_TX.
-#define SYSCTL_DC7_DMACH22      0x00400000  // UART1_RX / CAN2_RX.
-#define SYSCTL_DC7_DMACH21      0x00200000  // Timer1B / EPI0_TX.
-#define SYSCTL_DC7_DMACH20      0x00100000  // Timer1A / EPI0_RX.
-#define SYSCTL_DC7_DMACH19      0x00080000  // Timer0B / Timer1B.
-#define SYSCTL_DC7_DMACH18      0x00040000  // Timer0A / Timer1A.
-#define SYSCTL_DC7_DMACH17      0x00020000  // ADC0_SS3.
-#define SYSCTL_DC7_DMACH16      0x00010000  // ADC0_SS2.
-#define SYSCTL_DC7_DMACH15      0x00008000  // ADC0_SS1 / Timer2B.
-#define SYSCTL_DC7_DMACH14      0x00004000  // ADC0_SS0 / Timer2A.
-#define SYSCTL_DC7_DMACH13      0x00002000  // CAN0_TX / UART2_TX.
-#define SYSCTL_DC7_DMACH12      0x00001000  // CAN0_RX / UART2_RX.
-#define SYSCTL_DC7_DMACH11      0x00000800  // SSI0_TX / UART1_TX.
-#define SYSCTL_DC7_DMACH10      0x00000400  // SSI0_RX / UART1_RX.
-#define SYSCTL_DC7_DMACH9       0x00000200  // UART0_TX / SSI1_TX.
-#define SYSCTL_DC7_DMACH8       0x00000100  // UART0_RX / SSI1_RX.
-#define SYSCTL_DC7_DMACH7       0x00000080  // ETH_TX / Timer2B.
-#define SYSCTL_DC7_DMACH6       0x00000040  // ETH_RX / Timer2A.
-#define SYSCTL_DC7_DMACH5       0x00000020  // USB_EP3_TX / Timer2B.
-#define SYSCTL_DC7_DMACH4       0x00000010  // USB_EP3_RX / Timer2A.
-#define SYSCTL_DC7_DMACH3       0x00000008  // USB_EP2_TX / Timer3B.
-#define SYSCTL_DC7_DMACH2       0x00000004  // USB_EP2_RX / Timer3A.
-#define SYSCTL_DC7_DMACH1       0x00000002  // USB_EP1_TX / UART2_TX.
-#define SYSCTL_DC7_DMACH0       0x00000001  // USB_EP1_RX / UART2_RX.
+#define SYSCTL_DC7_DMACH30      0x40000000  // SW
+#define SYSCTL_DC7_DMACH29      0x20000000  // I2S0_TX / CAN1_TX
+#define SYSCTL_DC7_DMACH28      0x10000000  // I2S0_RX / CAN1_RX
+#define SYSCTL_DC7_DMACH27      0x08000000  // CAN1_TX / ADC1_SS3
+#define SYSCTL_DC7_DMACH26      0x04000000  // CAN1_RX / ADC1_SS2
+#define SYSCTL_DC7_DMACH25      0x02000000  // SSI1_TX / ADC1_SS1
+#define SYSCTL_DC7_DMACH24      0x01000000  // SSI1_RX / ADC1_SS0
+#define SYSCTL_DC7_DMACH23      0x00800000  // UART1_TX / CAN2_TX
+#define SYSCTL_DC7_DMACH22      0x00400000  // UART1_RX / CAN2_RX
+#define SYSCTL_DC7_DMACH21      0x00200000  // Timer1B / EPI0_WFIFO
+#define SYSCTL_DC7_DMACH20      0x00100000  // Timer1A / EPI0_NBRFIFO
+#define SYSCTL_DC7_DMACH19      0x00080000  // Timer0B / Timer1B
+#define SYSCTL_DC7_DMACH18      0x00040000  // Timer0A / Timer1A
+#define SYSCTL_DC7_DMACH17      0x00020000  // ADC0_SS3
+#define SYSCTL_DC7_DMACH16      0x00010000  // ADC0_SS2
+#define SYSCTL_DC7_DMACH15      0x00008000  // ADC0_SS1 / Timer2B
+#define SYSCTL_DC7_DMACH14      0x00004000  // ADC0_SS0 / Timer2A
+#define SYSCTL_DC7_DMACH13      0x00002000  // CAN0_TX / UART2_TX
+#define SYSCTL_DC7_DMACH12      0x00001000  // CAN0_RX / UART2_RX
+#define SYSCTL_DC7_DMACH11      0x00000800  // SSI0_TX / SSI1_TX
+#define SYSCTL_DC7_DMACH10      0x00000400  // SSI0_RX / SSI1_RX
+#define SYSCTL_DC7_DMACH9       0x00000200  // UART0_TX / UART1_TX
+#define SYSCTL_DC7_DMACH8       0x00000100  // UART0_RX / UART1_RX
+#define SYSCTL_DC7_DMACH7       0x00000080  // ETH_TX / Timer2B
+#define SYSCTL_DC7_DMACH6       0x00000040  // ETH_RX / Timer2A
+#define SYSCTL_DC7_DMACH5       0x00000020  // USB_EP3_TX / Timer2B
+#define SYSCTL_DC7_DMACH4       0x00000010  // USB_EP3_RX / Timer2A
+#define SYSCTL_DC7_DMACH3       0x00000008  // USB_EP2_TX / Timer3B
+#define SYSCTL_DC7_DMACH2       0x00000004  // USB_EP2_RX / Timer3A
+#define SYSCTL_DC7_DMACH1       0x00000002  // USB_EP1_TX / UART2_TX
+#define SYSCTL_DC7_DMACH0       0x00000001  // USB_EP1_RX / UART2_RX
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_DC8 register.
 //
 //*****************************************************************************
-#define SYSCTL_DC8_ADC1AIN15    0x80000000  // ADC Module 1 AIN15 Pin Present.
-#define SYSCTL_DC8_ADC1AIN14    0x40000000  // ADC Module 1 AIN14 Pin Present.
-#define SYSCTL_DC8_ADC1AIN13    0x20000000  // ADC Module 1 AIN13 Pin Present.
-#define SYSCTL_DC8_ADC1AIN12    0x10000000  // ADC Module 1 AIN12 Pin Present.
-#define SYSCTL_DC8_ADC1AIN11    0x08000000  // ADC Module 1 AIN11 Pin Present.
-#define SYSCTL_DC8_ADC1AIN10    0x04000000  // ADC Module 1 AIN10 Pin Present.
-#define SYSCTL_DC8_ADC1AIN9     0x02000000  // ADC Module 1 AIN9 Pin Present.
-#define SYSCTL_DC8_ADC1AIN8     0x01000000  // ADC Module 1 AIN8 Pin Present.
-#define SYSCTL_DC8_ADC1AIN7     0x00800000  // ADC Module 1 AIN7 Pin Present.
-#define SYSCTL_DC8_ADC1AIN6     0x00400000  // ADC Module 1 AIN6 Pin Present.
-#define SYSCTL_DC8_ADC1AIN5     0x00200000  // ADC Module 1 AIN5 Pin Present.
-#define SYSCTL_DC8_ADC1AIN4     0x00100000  // ADC Module 1 AIN4 Pin Present.
-#define SYSCTL_DC8_ADC1AIN3     0x00080000  // ADC Module 1 AIN3 Pin Present.
-#define SYSCTL_DC8_ADC1AIN2     0x00040000  // ADC Module 1 AIN2 Pin Present.
-#define SYSCTL_DC8_ADC1AIN1     0x00020000  // ADC Module 1 AIN1 Pin Present.
-#define SYSCTL_DC8_ADC1AIN0     0x00010000  // ADC Module 1 AIN0 Pin Present.
-#define SYSCTL_DC8_ADC0AIN15    0x00008000  // ADC Module 0 AIN15 Pin Present.
-#define SYSCTL_DC8_ADC0AIN14    0x00004000  // ADC Module 0 AIN14 Pin Present.
-#define SYSCTL_DC8_ADC0AIN13    0x00002000  // ADC Module 0 AIN13 Pin Present.
-#define SYSCTL_DC8_ADC0AIN12    0x00001000  // ADC Module 0 AIN12 Pin Present.
-#define SYSCTL_DC8_ADC0AIN11    0x00000800  // ADC Module 0 AIN11 Pin Present.
-#define SYSCTL_DC8_ADC0AIN10    0x00000400  // ADC Module 0 AIN10 Pin Present.
-#define SYSCTL_DC8_ADC0AIN9     0x00000200  // ADC Module 0 AIN9 Pin Present.
-#define SYSCTL_DC8_ADC0AIN8     0x00000100  // ADC Module 0 AIN8 Pin Present.
-#define SYSCTL_DC8_ADC0AIN7     0x00000080  // ADC Module 0 AIN7 Pin Present.
-#define SYSCTL_DC8_ADC0AIN6     0x00000040  // ADC Module 0 AIN6 Pin Present.
-#define SYSCTL_DC8_ADC0AIN5     0x00000020  // ADC Module 0 AIN5 Pin Present.
-#define SYSCTL_DC8_ADC0AIN4     0x00000010  // ADC Module 0 AIN4 Pin Present.
-#define SYSCTL_DC8_ADC0AIN3     0x00000008  // ADC Module 0 AIN3 Pin Present.
-#define SYSCTL_DC8_ADC0AIN2     0x00000004  // ADC Module 0 AIN2 Pin Present.
-#define SYSCTL_DC8_ADC0AIN1     0x00000002  // ADC Module 0 AIN1 Pin Present.
-#define SYSCTL_DC8_ADC0AIN0     0x00000001  // ADC Module 0 AIN0 Pin Present.
+#define SYSCTL_DC8_ADC1AIN15    0x80000000  // ADC Module 1 AIN15 Pin Present
+#define SYSCTL_DC8_ADC1AIN14    0x40000000  // ADC Module 1 AIN14 Pin Present
+#define SYSCTL_DC8_ADC1AIN13    0x20000000  // ADC Module 1 AIN13 Pin Present
+#define SYSCTL_DC8_ADC1AIN12    0x10000000  // ADC Module 1 AIN12 Pin Present
+#define SYSCTL_DC8_ADC1AIN11    0x08000000  // ADC Module 1 AIN11 Pin Present
+#define SYSCTL_DC8_ADC1AIN10    0x04000000  // ADC Module 1 AIN10 Pin Present
+#define SYSCTL_DC8_ADC1AIN9     0x02000000  // ADC Module 1 AIN9 Pin Present
+#define SYSCTL_DC8_ADC1AIN8     0x01000000  // ADC Module 1 AIN8 Pin Present
+#define SYSCTL_DC8_ADC1AIN7     0x00800000  // ADC Module 1 AIN7 Pin Present
+#define SYSCTL_DC8_ADC1AIN6     0x00400000  // ADC Module 1 AIN6 Pin Present
+#define SYSCTL_DC8_ADC1AIN5     0x00200000  // ADC Module 1 AIN5 Pin Present
+#define SYSCTL_DC8_ADC1AIN4     0x00100000  // ADC Module 1 AIN4 Pin Present
+#define SYSCTL_DC8_ADC1AIN3     0x00080000  // ADC Module 1 AIN3 Pin Present
+#define SYSCTL_DC8_ADC1AIN2     0x00040000  // ADC Module 1 AIN2 Pin Present
+#define SYSCTL_DC8_ADC1AIN1     0x00020000  // ADC Module 1 AIN1 Pin Present
+#define SYSCTL_DC8_ADC1AIN0     0x00010000  // ADC Module 1 AIN0 Pin Present
+#define SYSCTL_DC8_ADC0AIN15    0x00008000  // ADC Module 0 AIN15 Pin Present
+#define SYSCTL_DC8_ADC0AIN14    0x00004000  // ADC Module 0 AIN14 Pin Present
+#define SYSCTL_DC8_ADC0AIN13    0x00002000  // ADC Module 0 AIN13 Pin Present
+#define SYSCTL_DC8_ADC0AIN12    0x00001000  // ADC Module 0 AIN12 Pin Present
+#define SYSCTL_DC8_ADC0AIN11    0x00000800  // ADC Module 0 AIN11 Pin Present
+#define SYSCTL_DC8_ADC0AIN10    0x00000400  // ADC Module 0 AIN10 Pin Present
+#define SYSCTL_DC8_ADC0AIN9     0x00000200  // ADC Module 0 AIN9 Pin Present
+#define SYSCTL_DC8_ADC0AIN8     0x00000100  // ADC Module 0 AIN8 Pin Present
+#define SYSCTL_DC8_ADC0AIN7     0x00000080  // ADC Module 0 AIN7 Pin Present
+#define SYSCTL_DC8_ADC0AIN6     0x00000040  // ADC Module 0 AIN6 Pin Present
+#define SYSCTL_DC8_ADC0AIN5     0x00000020  // ADC Module 0 AIN5 Pin Present
+#define SYSCTL_DC8_ADC0AIN4     0x00000010  // ADC Module 0 AIN4 Pin Present
+#define SYSCTL_DC8_ADC0AIN3     0x00000008  // ADC Module 0 AIN3 Pin Present
+#define SYSCTL_DC8_ADC0AIN2     0x00000004  // ADC Module 0 AIN2 Pin Present
+#define SYSCTL_DC8_ADC0AIN1     0x00000002  // ADC Module 0 AIN1 Pin Present
+#define SYSCTL_DC8_ADC0AIN0     0x00000001  // ADC Module 0 AIN0 Pin Present
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_PBORCTL register.
 //
 //*****************************************************************************
-#define SYSCTL_PBORCTL_BORIOR   0x00000002  // BOR Interrupt or Reset.
+#define SYSCTL_PBORCTL_BORIOR   0x00000002  // BOR Interrupt or Reset
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_SRCR0 register.
 //
 //*****************************************************************************
-#define SYSCTL_SRCR0_WDT1       0x10000000  // WDT1 Reset Control.
-#define SYSCTL_SRCR0_CAN1       0x02000000  // CAN1 Reset Control.
-#define SYSCTL_SRCR0_CAN0       0x01000000  // CAN0 Reset Control.
-#define SYSCTL_SRCR0_PWM        0x00100000  // PWM Reset Control.
-#define SYSCTL_SRCR0_ADC1       0x00020000  // ADC1 Reset Control.
-#define SYSCTL_SRCR0_ADC0       0x00010000  // ADC0 Reset Control.
-#define SYSCTL_SRCR0_WDT0       0x00000008  // WDT0 Reset Control.
+#define SYSCTL_SRCR0_WDT1       0x10000000  // WDT1 Reset Control
+#define SYSCTL_SRCR0_CAN1       0x02000000  // CAN1 Reset Control
+#define SYSCTL_SRCR0_CAN0       0x01000000  // CAN0 Reset Control
+#define SYSCTL_SRCR0_PWM        0x00100000  // PWM Reset Control
+#define SYSCTL_SRCR0_ADC1       0x00020000  // ADC1 Reset Control
+#define SYSCTL_SRCR0_ADC0       0x00010000  // ADC0 Reset Control
+#define SYSCTL_SRCR0_WDT0       0x00000008  // WDT0 Reset Control
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_SRCR1 register.
 //
 //*****************************************************************************
-#define SYSCTL_SRCR1_EPI0       0x40000000  // EPI0 Reset Control.
-#define SYSCTL_SRCR1_I2S0       0x10000000  // I2S0 Reset Control.
-#define SYSCTL_SRCR1_COMP2      0x04000000  // Analog Comp 2 Reset Control.
-#define SYSCTL_SRCR1_COMP1      0x02000000  // Analog Comp 1 Reset Control.
-#define SYSCTL_SRCR1_COMP0      0x01000000  // Analog Comp 0 Reset Control.
-#define SYSCTL_SRCR1_TIMER3     0x00080000  // Timer 3 Reset Control.
-#define SYSCTL_SRCR1_TIMER2     0x00040000  // Timer 2 Reset Control.
-#define SYSCTL_SRCR1_TIMER1     0x00020000  // Timer 1 Reset Control.
-#define SYSCTL_SRCR1_TIMER0     0x00010000  // Timer 0 Reset Control.
-#define SYSCTL_SRCR1_I2C1       0x00004000  // I2C1 Reset Control.
-#define SYSCTL_SRCR1_I2C0       0x00001000  // I2C0 Reset Control.
-#define SYSCTL_SRCR1_QEI1       0x00000200  // QEI1 Reset Control.
-#define SYSCTL_SRCR1_QEI0       0x00000100  // QEI0 Reset Control.
-#define SYSCTL_SRCR1_SSI1       0x00000020  // SSI1 Reset Control.
-#define SYSCTL_SRCR1_SSI0       0x00000010  // SSI0 Reset Control.
-#define SYSCTL_SRCR1_UART2      0x00000004  // UART2 Reset Control.
-#define SYSCTL_SRCR1_UART1      0x00000002  // UART1 Reset Control.
-#define SYSCTL_SRCR1_UART0      0x00000001  // UART0 Reset Control.
+#define SYSCTL_SRCR1_EPI0       0x40000000  // EPI0 Reset Control
+#define SYSCTL_SRCR1_I2S0       0x10000000  // I2S0 Reset Control
+#define SYSCTL_SRCR1_COMP2      0x04000000  // Analog Comp 2 Reset Control
+#define SYSCTL_SRCR1_COMP1      0x02000000  // Analog Comp 1 Reset Control
+#define SYSCTL_SRCR1_COMP0      0x01000000  // Analog Comp 0 Reset Control
+#define SYSCTL_SRCR1_TIMER3     0x00080000  // Timer 3 Reset Control
+#define SYSCTL_SRCR1_TIMER2     0x00040000  // Timer 2 Reset Control
+#define SYSCTL_SRCR1_TIMER1     0x00020000  // Timer 1 Reset Control
+#define SYSCTL_SRCR1_TIMER0     0x00010000  // Timer 0 Reset Control
+#define SYSCTL_SRCR1_I2C1       0x00004000  // I2C1 Reset Control
+#define SYSCTL_SRCR1_I2C0       0x00001000  // I2C0 Reset Control
+#define SYSCTL_SRCR1_QEI1       0x00000200  // QEI1 Reset Control
+#define SYSCTL_SRCR1_QEI0       0x00000100  // QEI0 Reset Control
+#define SYSCTL_SRCR1_SSI1       0x00000020  // SSI1 Reset Control
+#define SYSCTL_SRCR1_SSI0       0x00000010  // SSI0 Reset Control
+#define SYSCTL_SRCR1_UART2      0x00000004  // UART2 Reset Control
+#define SYSCTL_SRCR1_UART1      0x00000002  // UART1 Reset Control
+#define SYSCTL_SRCR1_UART0      0x00000001  // UART0 Reset Control
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_SRCR2 register.
 //
 //*****************************************************************************
-#define SYSCTL_SRCR2_EPHY0      0x40000000  // PHY0 Reset Control.
-#define SYSCTL_SRCR2_EMAC0      0x10000000  // MAC0 Reset Control.
-#define SYSCTL_SRCR2_USB0       0x00010000  // USB0 Reset Control.
-#define SYSCTL_SRCR2_UDMA       0x00002000  // Micro-DMA Reset Control.
-#define SYSCTL_SRCR2_GPIOJ      0x00000100  // Port J Reset Control.
-#define SYSCTL_SRCR2_GPIOH      0x00000080  // Port H Reset Control.
-#define SYSCTL_SRCR2_GPIOG      0x00000040  // Port G Reset Control.
-#define SYSCTL_SRCR2_GPIOF      0x00000020  // Port F Reset Control.
-#define SYSCTL_SRCR2_GPIOE      0x00000010  // Port E Reset Control.
-#define SYSCTL_SRCR2_GPIOD      0x00000008  // Port D Reset Control.
-#define SYSCTL_SRCR2_GPIOC      0x00000004  // Port C Reset Control.
-#define SYSCTL_SRCR2_GPIOB      0x00000002  // Port B Reset Control.
-#define SYSCTL_SRCR2_GPIOA      0x00000001  // Port A Reset Control.
+#define SYSCTL_SRCR2_EPHY0      0x40000000  // PHY0 Reset Control
+#define SYSCTL_SRCR2_EMAC0      0x10000000  // MAC0 Reset Control
+#define SYSCTL_SRCR2_USB0       0x00010000  // USB0 Reset Control
+#define SYSCTL_SRCR2_UDMA       0x00002000  // Micro-DMA Reset Control
+#define SYSCTL_SRCR2_GPIOJ      0x00000100  // Port J Reset Control
+#define SYSCTL_SRCR2_GPIOH      0x00000080  // Port H Reset Control
+#define SYSCTL_SRCR2_GPIOG      0x00000040  // Port G Reset Control
+#define SYSCTL_SRCR2_GPIOF      0x00000020  // Port F Reset Control
+#define SYSCTL_SRCR2_GPIOE      0x00000010  // Port E Reset Control
+#define SYSCTL_SRCR2_GPIOD      0x00000008  // Port D Reset Control
+#define SYSCTL_SRCR2_GPIOC      0x00000004  // Port C Reset Control
+#define SYSCTL_SRCR2_GPIOB      0x00000002  // Port B Reset Control
+#define SYSCTL_SRCR2_GPIOA      0x00000001  // Port A Reset Control
 
 //*****************************************************************************
 //
@@ -10159,22 +10584,22 @@
 //
 //*****************************************************************************
 #define SYSCTL_RIS_MOSCPUPRIS   0x00000100  // MOSC Power Up Raw Interrupt
-                                            // Status.
+                                            // Status
 #define SYSCTL_RIS_USBPLLLRIS   0x00000080  // USB PLL Lock Raw Interrupt
-                                            // Status.
-#define SYSCTL_RIS_PLLLRIS      0x00000040  // PLL Lock Raw Interrupt Status.
+                                            // Status
+#define SYSCTL_RIS_PLLLRIS      0x00000040  // PLL Lock Raw Interrupt Status
 #define SYSCTL_RIS_BORRIS       0x00000002  // Brown-Out Reset Raw Interrupt
-                                            // Status.
+                                            // Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_IMC register.
 //
 //*****************************************************************************
-#define SYSCTL_IMC_MOSCPUPIM    0x00000100  // MOSC Power Up Interrupt Mask.
-#define SYSCTL_IMC_USBPLLLIM    0x00000080  // USB PLL Lock Interrupt Mask.
-#define SYSCTL_IMC_PLLLIM       0x00000040  // PLL Lock Interrupt Mask.
-#define SYSCTL_IMC_BORIM        0x00000002  // Brown-Out Reset Interrupt Mask.
+#define SYSCTL_IMC_MOSCPUPIM    0x00000100  // MOSC Power Up Interrupt Mask
+#define SYSCTL_IMC_USBPLLLIM    0x00000080  // USB PLL Lock Interrupt Mask
+#define SYSCTL_IMC_PLLLIM       0x00000040  // PLL Lock Interrupt Mask
+#define SYSCTL_IMC_BORIM        0x00000002  // Brown-Out Reset Interrupt Mask
 
 //*****************************************************************************
 //
@@ -10182,99 +10607,98 @@
 //
 //*****************************************************************************
 #define SYSCTL_MISC_MOSCPUPMIS  0x00000100  // MOSC Power Up Masked Interrupt
-                                            // Status.
+                                            // Status
 #define SYSCTL_MISC_USBPLLLMIS  0x00000080  // USB PLL Lock Masked Interrupt
-                                            // Status.
-#define SYSCTL_MISC_PLLLMIS     0x00000040  // PLL Lock Masked Interrupt
-                                            // Status.
-#define SYSCTL_MISC_BORMIS      0x00000002  // BOR Masked Interrupt Status.
+                                            // Status
+#define SYSCTL_MISC_PLLLMIS     0x00000040  // PLL Lock Masked Interrupt Status
+#define SYSCTL_MISC_BORMIS      0x00000002  // BOR Masked Interrupt Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_RESC register.
 //
 //*****************************************************************************
-#define SYSCTL_RESC_MOSCFAIL    0x00010000  // MOSC Failure Reset.
-#define SYSCTL_RESC_WDT1        0x00000020  // Watchdog Timer 1 Reset.
-#define SYSCTL_RESC_SW          0x00000010  // Software Reset.
-#define SYSCTL_RESC_WDT0        0x00000008  // Watchdog Timer 0 Reset.
-#define SYSCTL_RESC_BOR         0x00000004  // Brown-Out Reset.
-#define SYSCTL_RESC_POR         0x00000002  // Power-On Reset.
-#define SYSCTL_RESC_EXT         0x00000001  // External Reset.
+#define SYSCTL_RESC_MOSCFAIL    0x00010000  // MOSC Failure Reset
+#define SYSCTL_RESC_WDT1        0x00000020  // Watchdog Timer 1 Reset
+#define SYSCTL_RESC_SW          0x00000010  // Software Reset
+#define SYSCTL_RESC_WDT0        0x00000008  // Watchdog Timer 0 Reset
+#define SYSCTL_RESC_BOR         0x00000004  // Brown-Out Reset
+#define SYSCTL_RESC_POR         0x00000002  // Power-On Reset
+#define SYSCTL_RESC_EXT         0x00000001  // External Reset
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_RCC register.
 //
 //*****************************************************************************
-#define SYSCTL_RCC_ACG          0x08000000  // Auto Clock Gating.
-#define SYSCTL_RCC_SYSDIV_M     0x07800000  // System Clock Divisor.
-#define SYSCTL_RCC_SYSDIV_2     0x00800000  // /2
-#define SYSCTL_RCC_SYSDIV_3     0x01000000  // /3
-#define SYSCTL_RCC_SYSDIV_4     0x01800000  // /4
-#define SYSCTL_RCC_SYSDIV_5     0x02000000  // /5
-#define SYSCTL_RCC_SYSDIV_6     0x02800000  // /6
-#define SYSCTL_RCC_SYSDIV_7     0x03000000  // /7
-#define SYSCTL_RCC_SYSDIV_8     0x03800000  // /8
-#define SYSCTL_RCC_SYSDIV_9     0x04000000  // /9
-#define SYSCTL_RCC_SYSDIV_10    0x04800000  // /10
-#define SYSCTL_RCC_SYSDIV_11    0x05000000  // /11
-#define SYSCTL_RCC_SYSDIV_12    0x05800000  // /12
-#define SYSCTL_RCC_SYSDIV_13    0x06000000  // /13
-#define SYSCTL_RCC_SYSDIV_14    0x06800000  // /14
-#define SYSCTL_RCC_SYSDIV_15    0x07000000  // /15
-#define SYSCTL_RCC_SYSDIV_16    0x07800000  // /16
-#define SYSCTL_RCC_USESYSDIV    0x00400000  // Enable System Clock Divider.
-#define SYSCTL_RCC_USEPWMDIV    0x00100000  // Enable PWM Clock Divisor.
-#define SYSCTL_RCC_PWMDIV_M     0x000E0000  // PWM Unit Clock Divisor.
-#define SYSCTL_RCC_PWMDIV_2     0x00000000  // /2
-#define SYSCTL_RCC_PWMDIV_4     0x00020000  // /4
-#define SYSCTL_RCC_PWMDIV_8     0x00040000  // /8
-#define SYSCTL_RCC_PWMDIV_16    0x00060000  // /16
-#define SYSCTL_RCC_PWMDIV_32    0x00080000  // /32
-#define SYSCTL_RCC_PWMDIV_64    0x000A0000  // /64
-#define SYSCTL_RCC_PWRDN        0x00002000  // PLL Power Down.
-#define SYSCTL_RCC_BYPASS       0x00000800  // PLL Bypass.
-#define SYSCTL_RCC_XTAL_M       0x000007C0  // Crystal Value.
-#define SYSCTL_RCC_XTAL_1MHZ    0x00000000  // 1.000
-#define SYSCTL_RCC_XTAL_1_84MHZ 0x00000040  // 1.8432
-#define SYSCTL_RCC_XTAL_2MHZ    0x00000080  // 2.000
-#define SYSCTL_RCC_XTAL_2_45MHZ 0x000000C0  // 2.4576
+#define SYSCTL_RCC_ACG          0x08000000  // Auto Clock Gating
+#define SYSCTL_RCC_SYSDIV_M     0x07800000  // System Clock Divisor
+#define SYSCTL_RCC_SYSDIV_2     0x00800000  // System clock /2
+#define SYSCTL_RCC_SYSDIV_3     0x01000000  // System clock /3
+#define SYSCTL_RCC_SYSDIV_4     0x01800000  // System clock /4
+#define SYSCTL_RCC_SYSDIV_5     0x02000000  // System clock /5
+#define SYSCTL_RCC_SYSDIV_6     0x02800000  // System clock /6
+#define SYSCTL_RCC_SYSDIV_7     0x03000000  // System clock /7
+#define SYSCTL_RCC_SYSDIV_8     0x03800000  // System clock /8
+#define SYSCTL_RCC_SYSDIV_9     0x04000000  // System clock /9
+#define SYSCTL_RCC_SYSDIV_10    0x04800000  // System clock /10
+#define SYSCTL_RCC_SYSDIV_11    0x05000000  // System clock /11
+#define SYSCTL_RCC_SYSDIV_12    0x05800000  // System clock /12
+#define SYSCTL_RCC_SYSDIV_13    0x06000000  // System clock /13
+#define SYSCTL_RCC_SYSDIV_14    0x06800000  // System clock /14
+#define SYSCTL_RCC_SYSDIV_15    0x07000000  // System clock /15
+#define SYSCTL_RCC_SYSDIV_16    0x07800000  // System clock /16
+#define SYSCTL_RCC_USESYSDIV    0x00400000  // Enable System Clock Divider
+#define SYSCTL_RCC_USEPWMDIV    0x00100000  // Enable PWM Clock Divisor
+#define SYSCTL_RCC_PWMDIV_M     0x000E0000  // PWM Unit Clock Divisor
+#define SYSCTL_RCC_PWMDIV_2     0x00000000  // PWM clock /2
+#define SYSCTL_RCC_PWMDIV_4     0x00020000  // PWM clock /4
+#define SYSCTL_RCC_PWMDIV_8     0x00040000  // PWM clock /8
+#define SYSCTL_RCC_PWMDIV_16    0x00060000  // PWM clock /16
+#define SYSCTL_RCC_PWMDIV_32    0x00080000  // PWM clock /32
+#define SYSCTL_RCC_PWMDIV_64    0x000A0000  // PWM clock /64
+#define SYSCTL_RCC_PWRDN        0x00002000  // PLL Power Down
+#define SYSCTL_RCC_BYPASS       0x00000800  // PLL Bypass
+#define SYSCTL_RCC_XTAL_M       0x000007C0  // Crystal Value
+#define SYSCTL_RCC_XTAL_1MHZ    0x00000000  // 1 MHz
+#define SYSCTL_RCC_XTAL_1_84MHZ 0x00000040  // 1.8432 MHz
+#define SYSCTL_RCC_XTAL_2MHZ    0x00000080  // 2 MHz
+#define SYSCTL_RCC_XTAL_2_45MHZ 0x000000C0  // 2.4576 MHz
 #define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100  // 3.579545 MHz
 #define SYSCTL_RCC_XTAL_3_68MHZ 0x00000140  // 3.6864 MHz
-#define SYSCTL_RCC_XTAL_4MHZ    0x00000180  // 4 MHz (USB)
+#define SYSCTL_RCC_XTAL_4MHZ    0x00000180  // 4 MHz
 #define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0  // 4.096 MHz
 #define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200  // 4.9152 MHz
-#define SYSCTL_RCC_XTAL_5MHZ    0x00000240  // 5 MHz (USB)
+#define SYSCTL_RCC_XTAL_5MHZ    0x00000240  // 5 MHz
 #define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280  // 5.12 MHz
-#define SYSCTL_RCC_XTAL_6MHZ    0x000002C0  // 6 MHz (reset value)(USB)
+#define SYSCTL_RCC_XTAL_6MHZ    0x000002C0  // 6 MHz
 #define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300  // 6.144 MHz
 #define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340  // 7.3728 MHz
-#define SYSCTL_RCC_XTAL_8MHZ    0x00000380  // 8 MHz (USB)
+#define SYSCTL_RCC_XTAL_8MHZ    0x00000380  // 8 MHz
 #define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0  // 8.192 MHz
-#define SYSCTL_RCC_XTAL_10MHZ   0x00000400  // 10.0 MHz (USB)
-#define SYSCTL_RCC_XTAL_12MHZ   0x00000440  // 12.0 MHz (USB)
+#define SYSCTL_RCC_XTAL_10MHZ   0x00000400  // 10 MHz
+#define SYSCTL_RCC_XTAL_12MHZ   0x00000440  // 12 MHz
 #define SYSCTL_RCC_XTAL_12_2MHZ 0x00000480  // 12.288 MHz
 #define SYSCTL_RCC_XTAL_13_5MHZ 0x000004C0  // 13.56 MHz
 #define SYSCTL_RCC_XTAL_14_3MHZ 0x00000500  // 14.31818 MHz
-#define SYSCTL_RCC_XTAL_16MHZ   0x00000540  // 16.0 MHz (USB)
+#define SYSCTL_RCC_XTAL_16MHZ   0x00000540  // 16 MHz
 #define SYSCTL_RCC_XTAL_16_3MHZ 0x00000580  // 16.384 MHz
-#define SYSCTL_RCC_OSCSRC_M     0x00000030  // Oscillator Source.
+#define SYSCTL_RCC_OSCSRC_M     0x00000030  // Oscillator Source
 #define SYSCTL_RCC_OSCSRC_MAIN  0x00000000  // MOSC
-#define SYSCTL_RCC_OSCSRC_INT   0x00000010  // PIOSC
-#define SYSCTL_RCC_OSCSRC_INT4  0x00000020  // PIOSC/4
+#define SYSCTL_RCC_OSCSRC_INT   0x00000010  // IOSC
+#define SYSCTL_RCC_OSCSRC_INT4  0x00000020  // IOSC/4
 #define SYSCTL_RCC_OSCSRC_30    0x00000030  // 30 kHz
-#define SYSCTL_RCC_IOSCDIS      0x00000002  // Precision Internal Oscillator
-                                            // Disable.
-#define SYSCTL_RCC_MOSCDIS      0x00000001  // Main Oscillator Disable.
+#define SYSCTL_RCC_IOSCDIS      0x00000002  // Internal Oscillator Disable
+#define SYSCTL_RCC_MOSCDIS      0x00000001  // Main Oscillator Disable
+#define SYSCTL_RCC_SYSDIV_S     23
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_PLLCFG register.
 //
 //*****************************************************************************
-#define SYSCTL_PLLCFG_F_M       0x00003FE0  // PLL F Value.
-#define SYSCTL_PLLCFG_R_M       0x0000001F  // PLL R Value.
+#define SYSCTL_PLLCFG_F_M       0x00003FE0  // PLL F Value
+#define SYSCTL_PLLCFG_R_M       0x0000001F  // PLL R Value
 #define SYSCTL_PLLCFG_F_S       5
 #define SYSCTL_PLLCFG_R_S       0
 
@@ -10284,24 +10708,34 @@
 // register.
 //
 //*****************************************************************************
-#define SYSCTL_GPIOHBCTL_PORTJ  0x00000100  // Port J Advanced Host Bus.
-#define SYSCTL_GPIOHBCTL_PORTH  0x00000080  // Port H Advanced Host Bus.
-#define SYSCTL_GPIOHBCTL_PORTG  0x00000040  // Port G Advanced Host Bus.
-#define SYSCTL_GPIOHBCTL_PORTF  0x00000020  // Port F Advanced Host Bus.
-#define SYSCTL_GPIOHBCTL_PORTE  0x00000010  // Port E Advanced Host Bus.
-#define SYSCTL_GPIOHBCTL_PORTD  0x00000008  // Port D Advanced Host Bus.
-#define SYSCTL_GPIOHBCTL_PORTC  0x00000004  // Port C Advanced Host Bus.
-#define SYSCTL_GPIOHBCTL_PORTB  0x00000002  // Port B Advanced Host Bus.
-#define SYSCTL_GPIOHBCTL_PORTA  0x00000001  // Port A Advanced Host Bus.
+#define SYSCTL_GPIOHBCTL_PORTJ  0x00000100  // Port J Advanced High-Performance
+                                            // Bus
+#define SYSCTL_GPIOHBCTL_PORTH  0x00000080  // Port H Advanced High-Performance
+                                            // Bus
+#define SYSCTL_GPIOHBCTL_PORTG  0x00000040  // Port G Advanced High-Performance
+                                            // Bus
+#define SYSCTL_GPIOHBCTL_PORTF  0x00000020  // Port F Advanced High-Performance
+                                            // Bus
+#define SYSCTL_GPIOHBCTL_PORTE  0x00000010  // Port E Advanced High-Performance
+                                            // Bus
+#define SYSCTL_GPIOHBCTL_PORTD  0x00000008  // Port D Advanced High-Performance
+                                            // Bus
+#define SYSCTL_GPIOHBCTL_PORTC  0x00000004  // Port C Advanced High-Performance
+                                            // Bus
+#define SYSCTL_GPIOHBCTL_PORTB  0x00000002  // Port B Advanced High-Performance
+                                            // Bus
+#define SYSCTL_GPIOHBCTL_PORTA  0x00000001  // Port A Advanced High-Performance
+                                            // Bus
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_RCC2 register.
 //
 //*****************************************************************************
-#define SYSCTL_RCC2_USERCC2     0x80000000  // Use RCC2.
-#define SYSCTL_RCC2_USEFRACT    0x40000000  // Use FRACT.
-#define SYSCTL_RCC2_SYSDIV2_M   0x1F800000  // System Clock Divisor.
+#define SYSCTL_RCC2_USERCC2     0x80000000  // Use RCC2
+#define SYSCTL_RCC2_DIV400      0x40000000  // Divide PLL as 400 MHz vs. 200
+                                            // MHz
+#define SYSCTL_RCC2_SYSDIV2_M   0x1F800000  // System Clock Divisor 2
 #define SYSCTL_RCC2_SYSDIV2_2   0x00800000  // System clock /2
 #define SYSCTL_RCC2_SYSDIV2_3   0x01000000  // System clock /3
 #define SYSCTL_RCC2_SYSDIV2_4   0x01800000  // System clock /4
@@ -10365,11 +10799,11 @@
 #define SYSCTL_RCC2_SYSDIV2_62  0x1E800000  // System clock /62
 #define SYSCTL_RCC2_SYSDIV2_63  0x1F000000  // System clock /63
 #define SYSCTL_RCC2_SYSDIV2_64  0x1F800000  // System clock /64
-#define SYSCTL_RCC2_FRACT       0x00400000  // Fractional Divider.
-#define SYSCTL_RCC2_USBPWRDN    0x00004000  // Power-Down USB PLL.
-#define SYSCTL_RCC2_PWRDN2      0x00002000  // Power-Down PLL.
-#define SYSCTL_RCC2_BYPASS2     0x00000800  // PLL Bypass.
-#define SYSCTL_RCC2_OSCSRC2_M   0x00000070  // Oscillator Source.
+#define SYSCTL_RCC2_SYSDIV2LSB  0x00400000  // Additional LSB for SYSDIV2
+#define SYSCTL_RCC2_USBPWRDN    0x00004000  // Power-Down USB PLL
+#define SYSCTL_RCC2_PWRDN2      0x00002000  // Power-Down PLL 2
+#define SYSCTL_RCC2_BYPASS2     0x00000800  // PLL Bypass 2
+#define SYSCTL_RCC2_OSCSRC2_M   0x00000070  // Oscillator Source 2
 #define SYSCTL_RCC2_OSCSRC2_MO  0x00000000  // MOSC
 #define SYSCTL_RCC2_OSCSRC2_IO  0x00000010  // PIOSC
 #define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020  // PIOSC/4
@@ -10381,196 +10815,207 @@
 // The following are defines for the bit fields in the SYSCTL_MOSCCTL register.
 //
 //*****************************************************************************
-#define SYSCTL_MOSCCTL_CVAL     0x00000001  // Clock Validation for MOSC.
+#define SYSCTL_MOSCCTL_CVAL     0x00000001  // Clock Validation for MOSC
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_RCGC0 register.
 //
 //*****************************************************************************
-#define SYSCTL_RCGC0_WDT1       0x10000000  // WDT1 Clock Gating Control.
-#define SYSCTL_RCGC0_CAN1       0x02000000  // CAN1 Clock Gating Control.
-#define SYSCTL_RCGC0_CAN0       0x01000000  // CAN0 Clock Gating Control.
-#define SYSCTL_RCGC0_PWM        0x00100000  // PWM Clock Gating Control.
-#define SYSCTL_RCGC0_ADC1       0x00020000  // ADC1 Clock Gating Control.
-#define SYSCTL_RCGC0_ADC0       0x00010000  // ADC0 Clock Gating Control.
-#define SYSCTL_RCGC0_ADC1SPD_M  0x00000C00  // ADC1 Sample Speed.
+#define SYSCTL_RCGC0_WDT1       0x10000000  // WDT1 Clock Gating Control
+#define SYSCTL_RCGC0_CAN1       0x02000000  // CAN1 Clock Gating Control
+#define SYSCTL_RCGC0_CAN0       0x01000000  // CAN0 Clock Gating Control
+#define SYSCTL_RCGC0_PWM        0x00100000  // PWM Clock Gating Control
+#define SYSCTL_RCGC0_ADC1       0x00020000  // ADC1 Clock Gating Control
+#define SYSCTL_RCGC0_ADC0       0x00010000  // ADC0 Clock Gating Control
+#define SYSCTL_RCGC0_ADC1SPD_M  0x00000C00  // ADC1 Sample Speed
+#define SYSCTL_RCGC0_ADC1SPD_125K \
+                                0x00000000  // 125K samples/second
+#define SYSCTL_RCGC0_ADC1SPD_250K \
+                                0x00000400  // 250K samples/second
+#define SYSCTL_RCGC0_ADC1SPD_500K \
+                                0x00000800  // 500K samples/second
 #define SYSCTL_RCGC0_ADC1SPD_1M 0x00000C00  // 1M samples/second
-#define SYSCTL_RCGC0_ADC0SPD_M  0x00000300  // ADC0 Sample Speed.
+#define SYSCTL_RCGC0_ADC0SPD_M  0x00000300  // ADC0 Sample Speed
+#define SYSCTL_RCGC0_ADC0SPD_125K \
+                                0x00000000  // 125K samples/second
+#define SYSCTL_RCGC0_ADC0SPD_250K \
+                                0x00000100  // 250K samples/second
+#define SYSCTL_RCGC0_ADC0SPD_500K \
+                                0x00000200  // 500K samples/second
 #define SYSCTL_RCGC0_ADC0SPD_1M 0x00000300  // 1M samples/second
-#define SYSCTL_RCGC0_WDT0       0x00000008  // WDT0 Clock Gating Control.
+#define SYSCTL_RCGC0_WDT0       0x00000008  // WDT0 Clock Gating Control
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_RCGC1 register.
 //
 //*****************************************************************************
-#define SYSCTL_RCGC1_EPI0       0x40000000  // EPI0 Clock Gating.
-#define SYSCTL_RCGC1_I2S0       0x10000000  // I2S0 Clock Gating.
-#define SYSCTL_RCGC1_COMP2      0x04000000  // Analog Comparator 2 Clock
-                                            // Gating.
-#define SYSCTL_RCGC1_COMP1      0x02000000  // Analog Comparator 1 Clock
-                                            // Gating.
-#define SYSCTL_RCGC1_COMP0      0x01000000  // Analog Comparator 0 Clock
-                                            // Gating.
-#define SYSCTL_RCGC1_TIMER3     0x00080000  // Timer 3 Clock Gating Control.
-#define SYSCTL_RCGC1_TIMER2     0x00040000  // Timer 2 Clock Gating Control.
-#define SYSCTL_RCGC1_TIMER1     0x00020000  // Timer 1 Clock Gating Control.
-#define SYSCTL_RCGC1_TIMER0     0x00010000  // Timer 0 Clock Gating Control.
-#define SYSCTL_RCGC1_I2C1       0x00004000  // I2C1 Clock Gating Control.
-#define SYSCTL_RCGC1_I2C0       0x00001000  // I2C0 Clock Gating Control.
-#define SYSCTL_RCGC1_QEI1       0x00000200  // QEI1 Clock Gating Control.
-#define SYSCTL_RCGC1_QEI0       0x00000100  // QEI0 Clock Gating Control.
-#define SYSCTL_RCGC1_SSI1       0x00000020  // SSI1 Clock Gating Control.
-#define SYSCTL_RCGC1_SSI0       0x00000010  // SSI0 Clock Gating Control.
-#define SYSCTL_RCGC1_UART2      0x00000004  // UART2 Clock Gating Control.
-#define SYSCTL_RCGC1_UART1      0x00000002  // UART1 Clock Gating Control.
-#define SYSCTL_RCGC1_UART0      0x00000001  // UART0 Clock Gating Control.
+#define SYSCTL_RCGC1_EPI0       0x40000000  // EPI0 Clock Gating
+#define SYSCTL_RCGC1_I2S0       0x10000000  // I2S0 Clock Gating
+#define SYSCTL_RCGC1_COMP2      0x04000000  // Analog Comparator 2 Clock Gating
+#define SYSCTL_RCGC1_COMP1      0x02000000  // Analog Comparator 1 Clock Gating
+#define SYSCTL_RCGC1_COMP0      0x01000000  // Analog Comparator 0 Clock Gating
+#define SYSCTL_RCGC1_TIMER3     0x00080000  // Timer 3 Clock Gating Control
+#define SYSCTL_RCGC1_TIMER2     0x00040000  // Timer 2 Clock Gating Control
+#define SYSCTL_RCGC1_TIMER1     0x00020000  // Timer 1 Clock Gating Control
+#define SYSCTL_RCGC1_TIMER0     0x00010000  // Timer 0 Clock Gating Control
+#define SYSCTL_RCGC1_I2C1       0x00004000  // I2C1 Clock Gating Control
+#define SYSCTL_RCGC1_I2C0       0x00001000  // I2C0 Clock Gating Control
+#define SYSCTL_RCGC1_QEI1       0x00000200  // QEI1 Clock Gating Control
+#define SYSCTL_RCGC1_QEI0       0x00000100  // QEI0 Clock Gating Control
+#define SYSCTL_RCGC1_SSI1       0x00000020  // SSI1 Clock Gating Control
+#define SYSCTL_RCGC1_SSI0       0x00000010  // SSI0 Clock Gating Control
+#define SYSCTL_RCGC1_UART2      0x00000004  // UART2 Clock Gating Control
+#define SYSCTL_RCGC1_UART1      0x00000002  // UART1 Clock Gating Control
+#define SYSCTL_RCGC1_UART0      0x00000001  // UART0 Clock Gating Control
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_RCGC2 register.
 //
 //*****************************************************************************
-#define SYSCTL_RCGC2_EPHY0      0x40000000  // PHY0 Clock Gating Control.
-#define SYSCTL_RCGC2_EMAC0      0x10000000  // MAC0 Clock Gating Control.
-#define SYSCTL_RCGC2_USB0       0x00010000  // USB0 Clock Gating Control.
-#define SYSCTL_RCGC2_UDMA       0x00002000  // Micro-DMA Clock Gating Control.
-#define SYSCTL_RCGC2_GPIOJ      0x00000100  // Port J Clock Gating Control.
-#define SYSCTL_RCGC2_GPIOH      0x00000080  // Port H Clock Gating Control.
-#define SYSCTL_RCGC2_GPIOG      0x00000040  // Port G Clock Gating Control.
-#define SYSCTL_RCGC2_GPIOF      0x00000020  // Port F Clock Gating Control.
-#define SYSCTL_RCGC2_GPIOE      0x00000010  // Port E Clock Gating Control.
-#define SYSCTL_RCGC2_GPIOD      0x00000008  // Port D Clock Gating Control.
-#define SYSCTL_RCGC2_GPIOC      0x00000004  // Port C Clock Gating Control.
-#define SYSCTL_RCGC2_GPIOB      0x00000002  // Port B Clock Gating Control.
-#define SYSCTL_RCGC2_GPIOA      0x00000001  // Port A Clock Gating Control.
+#define SYSCTL_RCGC2_EPHY0      0x40000000  // PHY0 Clock Gating Control
+#define SYSCTL_RCGC2_EMAC0      0x10000000  // MAC0 Clock Gating Control
+#define SYSCTL_RCGC2_USB0       0x00010000  // USB0 Clock Gating Control
+#define SYSCTL_RCGC2_UDMA       0x00002000  // Micro-DMA Clock Gating Control
+#define SYSCTL_RCGC2_GPIOJ      0x00000100  // Port J Clock Gating Control
+#define SYSCTL_RCGC2_GPIOH      0x00000080  // Port H Clock Gating Control
+#define SYSCTL_RCGC2_GPIOG      0x00000040  // Port G Clock Gating Control
+#define SYSCTL_RCGC2_GPIOF      0x00000020  // Port F Clock Gating Control
+#define SYSCTL_RCGC2_GPIOE      0x00000010  // Port E Clock Gating Control
+#define SYSCTL_RCGC2_GPIOD      0x00000008  // Port D Clock Gating Control
+#define SYSCTL_RCGC2_GPIOC      0x00000004  // Port C Clock Gating Control
+#define SYSCTL_RCGC2_GPIOB      0x00000002  // Port B Clock Gating Control
+#define SYSCTL_RCGC2_GPIOA      0x00000001  // Port A Clock Gating Control
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_SCGC0 register.
 //
 //*****************************************************************************
-#define SYSCTL_SCGC0_WDT1       0x10000000  // WDT1 Clock Gating Control.
-#define SYSCTL_SCGC0_CAN1       0x02000000  // CAN1 Clock Gating Control.
-#define SYSCTL_SCGC0_CAN0       0x01000000  // CAN0 Clock Gating Control.
-#define SYSCTL_SCGC0_PWM        0x00100000  // PWM Clock Gating Control.
-#define SYSCTL_SCGC0_ADC1       0x00020000  // ADC1 Clock Gating Control.
-#define SYSCTL_SCGC0_ADC0       0x00010000  // ADC0 Clock Gating Control.
-#define SYSCTL_SCGC0_ADC1SPD_M  0x00000C00  // ADC1 Sample Speed.
+#define SYSCTL_SCGC0_WDT1       0x10000000  // WDT1 Clock Gating Control
+#define SYSCTL_SCGC0_CAN1       0x02000000  // CAN1 Clock Gating Control
+#define SYSCTL_SCGC0_CAN0       0x01000000  // CAN0 Clock Gating Control
+#define SYSCTL_SCGC0_PWM        0x00100000  // PWM Clock Gating Control
+#define SYSCTL_SCGC0_ADC1       0x00020000  // ADC1 Clock Gating Control
+#define SYSCTL_SCGC0_ADC0       0x00010000  // ADC0 Clock Gating Control
+#define SYSCTL_SCGC0_ADC1SPD_M  0x00000C00  // ADC1 Sample Speed
+#define SYSCTL_SCGC0_ADC1SPD_125K \
+                                0x00000000  // 125K samples/second
+#define SYSCTL_SCGC0_ADC1SPD_250K \
+                                0x00000400  // 250K samples/second
+#define SYSCTL_SCGC0_ADC1SPD_500K \
+                                0x00000800  // 500K samples/second
 #define SYSCTL_SCGC0_ADC1SPD_1M 0x00000C00  // 1M samples/second
-#define SYSCTL_SCGC0_ADC0SPD_M  0x00000300  // ADC0 Sample Speed.
+#define SYSCTL_SCGC0_ADC0SPD_M  0x00000300  // ADC0 Sample Speed
+#define SYSCTL_SCGC0_ADC0SPD_125K \
+                                0x00000000  // 125K samples/second
+#define SYSCTL_SCGC0_ADC0SPD_250K \
+                                0x00000100  // 250K samples/second
+#define SYSCTL_SCGC0_ADC0SPD_500K \
+                                0x00000200  // 500K samples/second
 #define SYSCTL_SCGC0_ADC0SPD_1M 0x00000300  // 1M samples/second
-#define SYSCTL_SCGC0_WDT0       0x00000008  // WDT0 Clock Gating Control.
+#define SYSCTL_SCGC0_WDT0       0x00000008  // WDT0 Clock Gating Control
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_SCGC1 register.
 //
 //*****************************************************************************
-#define SYSCTL_SCGC1_EPI0       0x40000000  // EPI0 Clock Gating.
-#define SYSCTL_SCGC1_I2S0       0x10000000  // I2S0 Clock Gating.
-#define SYSCTL_SCGC1_COMP2      0x04000000  // Analog Comparator 2 Clock
-                                            // Gating.
-#define SYSCTL_SCGC1_COMP1      0x02000000  // Analog Comparator 1 Clock
-                                            // Gating.
-#define SYSCTL_SCGC1_COMP0      0x01000000  // Analog Comparator 0 Clock
-                                            // Gating.
-#define SYSCTL_SCGC1_TIMER3     0x00080000  // Timer 3 Clock Gating Control.
-#define SYSCTL_SCGC1_TIMER2     0x00040000  // Timer 2 Clock Gating Control.
-#define SYSCTL_SCGC1_TIMER1     0x00020000  // Timer 1 Clock Gating Control.
-#define SYSCTL_SCGC1_TIMER0     0x00010000  // Timer 0 Clock Gating Control.
-#define SYSCTL_SCGC1_I2C1       0x00004000  // I2C1 Clock Gating Control.
-#define SYSCTL_SCGC1_I2C0       0x00001000  // I2C0 Clock Gating Control.
-#define SYSCTL_SCGC1_QEI1       0x00000200  // QEI1 Clock Gating Control.
-#define SYSCTL_SCGC1_QEI0       0x00000100  // QEI0 Clock Gating Control.
-#define SYSCTL_SCGC1_SSI1       0x00000020  // SSI1 Clock Gating Control.
-#define SYSCTL_SCGC1_SSI0       0x00000010  // SSI0 Clock Gating Control.
-#define SYSCTL_SCGC1_UART2      0x00000004  // UART2 Clock Gating Control.
-#define SYSCTL_SCGC1_UART1      0x00000002  // UART1 Clock Gating Control.
-#define SYSCTL_SCGC1_UART0      0x00000001  // UART0 Clock Gating Control.
+#define SYSCTL_SCGC1_EPI0       0x40000000  // EPI0 Clock Gating
+#define SYSCTL_SCGC1_I2S0       0x10000000  // I2S0 Clock Gating
+#define SYSCTL_SCGC1_COMP2      0x04000000  // Analog Comparator 2 Clock Gating
+#define SYSCTL_SCGC1_COMP1      0x02000000  // Analog Comparator 1 Clock Gating
+#define SYSCTL_SCGC1_COMP0      0x01000000  // Analog Comparator 0 Clock Gating
+#define SYSCTL_SCGC1_TIMER3     0x00080000  // Timer 3 Clock Gating Control
+#define SYSCTL_SCGC1_TIMER2     0x00040000  // Timer 2 Clock Gating Control
+#define SYSCTL_SCGC1_TIMER1     0x00020000  // Timer 1 Clock Gating Control
+#define SYSCTL_SCGC1_TIMER0     0x00010000  // Timer 0 Clock Gating Control
+#define SYSCTL_SCGC1_I2C1       0x00004000  // I2C1 Clock Gating Control
+#define SYSCTL_SCGC1_I2C0       0x00001000  // I2C0 Clock Gating Control
+#define SYSCTL_SCGC1_QEI1       0x00000200  // QEI1 Clock Gating Control
+#define SYSCTL_SCGC1_QEI0       0x00000100  // QEI0 Clock Gating Control
+#define SYSCTL_SCGC1_SSI1       0x00000020  // SSI1 Clock Gating Control
+#define SYSCTL_SCGC1_SSI0       0x00000010  // SSI0 Clock Gating Control
+#define SYSCTL_SCGC1_UART2      0x00000004  // UART2 Clock Gating Control
+#define SYSCTL_SCGC1_UART1      0x00000002  // UART1 Clock Gating Control
+#define SYSCTL_SCGC1_UART0      0x00000001  // UART0 Clock Gating Control
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_SCGC2 register.
 //
 //*****************************************************************************
-#define SYSCTL_SCGC2_EPHY0      0x40000000  // PHY0 Clock Gating Control.
-#define SYSCTL_SCGC2_EMAC0      0x10000000  // MAC0 Clock Gating Control.
-#define SYSCTL_SCGC2_USB0       0x00010000  // USB0 Clock Gating Control.
-#define SYSCTL_SCGC2_UDMA       0x00002000  // Micro-DMA Clock Gating Control.
-#define SYSCTL_SCGC2_GPIOJ      0x00000100  // Port J Clock Gating Control.
-#define SYSCTL_SCGC2_GPIOH      0x00000080  // Port H Clock Gating Control.
-#define SYSCTL_SCGC2_GPIOG      0x00000040  // Port G Clock Gating Control.
-#define SYSCTL_SCGC2_GPIOF      0x00000020  // Port F Clock Gating Control.
-#define SYSCTL_SCGC2_GPIOE      0x00000010  // Port E Clock Gating Control.
-#define SYSCTL_SCGC2_GPIOD      0x00000008  // Port D Clock Gating Control.
-#define SYSCTL_SCGC2_GPIOC      0x00000004  // Port C Clock Gating Control.
-#define SYSCTL_SCGC2_GPIOB      0x00000002  // Port B Clock Gating Control.
-#define SYSCTL_SCGC2_GPIOA      0x00000001  // Port A Clock Gating Control.
+#define SYSCTL_SCGC2_EPHY0      0x40000000  // PHY0 Clock Gating Control
+#define SYSCTL_SCGC2_EMAC0      0x10000000  // MAC0 Clock Gating Control
+#define SYSCTL_SCGC2_USB0       0x00010000  // USB0 Clock Gating Control
+#define SYSCTL_SCGC2_UDMA       0x00002000  // Micro-DMA Clock Gating Control
+#define SYSCTL_SCGC2_GPIOJ      0x00000100  // Port J Clock Gating Control
+#define SYSCTL_SCGC2_GPIOH      0x00000080  // Port H Clock Gating Control
+#define SYSCTL_SCGC2_GPIOG      0x00000040  // Port G Clock Gating Control
+#define SYSCTL_SCGC2_GPIOF      0x00000020  // Port F Clock Gating Control
+#define SYSCTL_SCGC2_GPIOE      0x00000010  // Port E Clock Gating Control
+#define SYSCTL_SCGC2_GPIOD      0x00000008  // Port D Clock Gating Control
+#define SYSCTL_SCGC2_GPIOC      0x00000004  // Port C Clock Gating Control
+#define SYSCTL_SCGC2_GPIOB      0x00000002  // Port B Clock Gating Control
+#define SYSCTL_SCGC2_GPIOA      0x00000001  // Port A Clock Gating Control
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_DCGC0 register.
 //
 //*****************************************************************************
-#define SYSCTL_DCGC0_WDT1       0x10000000  // WDT1 Clock Gating Control.
-#define SYSCTL_DCGC0_CAN1       0x02000000  // CAN1 Clock Gating Control.
-#define SYSCTL_DCGC0_CAN0       0x01000000  // CAN0 Clock Gating Control.
-#define SYSCTL_DCGC0_PWM        0x00100000  // PWM Clock Gating Control.
-#define SYSCTL_DCGC0_ADC1       0x00020000  // ADC1 Clock Gating Control.
-#define SYSCTL_DCGC0_ADC0       0x00010000  // ADC0 Clock Gating Control.
-#define SYSCTL_DCGC0_ADC1SPD_M  0x00000C00  // ADC1 Sample Speed.
-#define SYSCTL_DCGC0_ADC1SPD_1M 0x00000C00  // 1M samples/second
-#define SYSCTL_DCGC0_ADC0SPD_M  0x00000300  // ADC0 Sample Speed.
-#define SYSCTL_DCGC0_ADC0SPD_1M 0x00000300  // 1M samples/second
-#define SYSCTL_DCGC0_WDT0       0x00000008  // WDT0 Clock Gating Control.
+#define SYSCTL_DCGC0_WDT1       0x10000000  // WDT1 Clock Gating Control
+#define SYSCTL_DCGC0_CAN1       0x02000000  // CAN1 Clock Gating Control
+#define SYSCTL_DCGC0_CAN0       0x01000000  // CAN0 Clock Gating Control
+#define SYSCTL_DCGC0_PWM        0x00100000  // PWM Clock Gating Control
+#define SYSCTL_DCGC0_ADC1       0x00020000  // ADC1 Clock Gating Control
+#define SYSCTL_DCGC0_ADC0       0x00010000  // ADC0 Clock Gating Control
+#define SYSCTL_DCGC0_WDT0       0x00000008  // WDT0 Clock Gating Control
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_DCGC1 register.
 //
 //*****************************************************************************
-#define SYSCTL_DCGC1_EPI0       0x40000000  // EPI0 Clock Gating.
-#define SYSCTL_DCGC1_I2S0       0x10000000  // I2S0 Clock Gating.
-#define SYSCTL_DCGC1_COMP2      0x04000000  // Analog Comparator 2 Clock
-                                            // Gating.
-#define SYSCTL_DCGC1_COMP1      0x02000000  // Analog Comparator 1 Clock
-                                            // Gating.
-#define SYSCTL_DCGC1_COMP0      0x01000000  // Analog Comparator 0 Clock
-                                            // Gating.
-#define SYSCTL_DCGC1_TIMER3     0x00080000  // Timer 3 Clock Gating Control.
-#define SYSCTL_DCGC1_TIMER2     0x00040000  // Timer 2 Clock Gating Control.
-#define SYSCTL_DCGC1_TIMER1     0x00020000  // Timer 1 Clock Gating Control.
-#define SYSCTL_DCGC1_TIMER0     0x00010000  // Timer 0 Clock Gating Control.
-#define SYSCTL_DCGC1_I2C1       0x00004000  // I2C1 Clock Gating Control.
-#define SYSCTL_DCGC1_I2C0       0x00001000  // I2C0 Clock Gating Control.
-#define SYSCTL_DCGC1_QEI1       0x00000200  // QEI1 Clock Gating Control.
-#define SYSCTL_DCGC1_QEI0       0x00000100  // QEI0 Clock Gating Control.
-#define SYSCTL_DCGC1_SSI1       0x00000020  // SSI1 Clock Gating Control.
-#define SYSCTL_DCGC1_SSI0       0x00000010  // SSI0 Clock Gating Control.
-#define SYSCTL_DCGC1_UART2      0x00000004  // UART2 Clock Gating Control.
-#define SYSCTL_DCGC1_UART1      0x00000002  // UART1 Clock Gating Control.
-#define SYSCTL_DCGC1_UART0      0x00000001  // UART0 Clock Gating Control.
+#define SYSCTL_DCGC1_EPI0       0x40000000  // EPI0 Clock Gating
+#define SYSCTL_DCGC1_I2S0       0x10000000  // I2S0 Clock Gating
+#define SYSCTL_DCGC1_COMP2      0x04000000  // Analog Comparator 2 Clock Gating
+#define SYSCTL_DCGC1_COMP1      0x02000000  // Analog Comparator 1 Clock Gating
+#define SYSCTL_DCGC1_COMP0      0x01000000  // Analog Comparator 0 Clock Gating
+#define SYSCTL_DCGC1_TIMER3     0x00080000  // Timer 3 Clock Gating Control
+#define SYSCTL_DCGC1_TIMER2     0x00040000  // Timer 2 Clock Gating Control
+#define SYSCTL_DCGC1_TIMER1     0x00020000  // Timer 1 Clock Gating Control
+#define SYSCTL_DCGC1_TIMER0     0x00010000  // Timer 0 Clock Gating Control
+#define SYSCTL_DCGC1_I2C1       0x00004000  // I2C1 Clock Gating Control
+#define SYSCTL_DCGC1_I2C0       0x00001000  // I2C0 Clock Gating Control
+#define SYSCTL_DCGC1_QEI1       0x00000200  // QEI1 Clock Gating Control
+#define SYSCTL_DCGC1_QEI0       0x00000100  // QEI0 Clock Gating Control
+#define SYSCTL_DCGC1_SSI1       0x00000020  // SSI1 Clock Gating Control
+#define SYSCTL_DCGC1_SSI0       0x00000010  // SSI0 Clock Gating Control
+#define SYSCTL_DCGC1_UART2      0x00000004  // UART2 Clock Gating Control
+#define SYSCTL_DCGC1_UART1      0x00000002  // UART1 Clock Gating Control
+#define SYSCTL_DCGC1_UART0      0x00000001  // UART0 Clock Gating Control
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_DCGC2 register.
 //
 //*****************************************************************************
-#define SYSCTL_DCGC2_EPHY0      0x40000000  // PHY0 Clock Gating Control.
-#define SYSCTL_DCGC2_EMAC0      0x10000000  // MAC0 Clock Gating Control.
-#define SYSCTL_DCGC2_USB0       0x00010000  // USB0 Clock Gating Control.
-#define SYSCTL_DCGC2_UDMA       0x00002000  // Micro-DMA Clock Gating Control.
-#define SYSCTL_DCGC2_GPIOJ      0x00000100  // Port J Clock Gating Control.
-#define SYSCTL_DCGC2_GPIOH      0x00000080  // Port H Clock Gating Control.
-#define SYSCTL_DCGC2_GPIOG      0x00000040  // Port G Clock Gating Control.
-#define SYSCTL_DCGC2_GPIOF      0x00000020  // Port F Clock Gating Control.
-#define SYSCTL_DCGC2_GPIOE      0x00000010  // Port E Clock Gating Control.
-#define SYSCTL_DCGC2_GPIOD      0x00000008  // Port D Clock Gating Control.
-#define SYSCTL_DCGC2_GPIOC      0x00000004  // Port C Clock Gating Control.
-#define SYSCTL_DCGC2_GPIOB      0x00000002  // Port B Clock Gating Control.
-#define SYSCTL_DCGC2_GPIOA      0x00000001  // Port A Clock Gating Control.
+#define SYSCTL_DCGC2_EPHY0      0x40000000  // PHY0 Clock Gating Control
+#define SYSCTL_DCGC2_EMAC0      0x10000000  // MAC0 Clock Gating Control
+#define SYSCTL_DCGC2_USB0       0x00010000  // USB0 Clock Gating Control
+#define SYSCTL_DCGC2_UDMA       0x00002000  // Micro-DMA Clock Gating Control
+#define SYSCTL_DCGC2_GPIOJ      0x00000100  // Port J Clock Gating Control
+#define SYSCTL_DCGC2_GPIOH      0x00000080  // Port H Clock Gating Control
+#define SYSCTL_DCGC2_GPIOG      0x00000040  // Port G Clock Gating Control
+#define SYSCTL_DCGC2_GPIOF      0x00000020  // Port F Clock Gating Control
+#define SYSCTL_DCGC2_GPIOE      0x00000010  // Port E Clock Gating Control
+#define SYSCTL_DCGC2_GPIOD      0x00000008  // Port D Clock Gating Control
+#define SYSCTL_DCGC2_GPIOC      0x00000004  // Port C Clock Gating Control
+#define SYSCTL_DCGC2_GPIOB      0x00000002  // Port B Clock Gating Control
+#define SYSCTL_DCGC2_GPIOA      0x00000001  // Port A Clock Gating Control
 
 //*****************************************************************************
 //
@@ -10578,44 +11023,85 @@
 // register.
 //
 //*****************************************************************************
-#define SYSCTL_DSLPCLKCFG_D_M   0x1F800000  // Divider Field Override.
-#define SYSCTL_DSLPCLKCFG_D_2   0x00800000  // /2
-#define SYSCTL_DSLPCLKCFG_D_3   0x01000000  // /3
-#define SYSCTL_DSLPCLKCFG_D_4   0x01800000  // /4
-#define SYSCTL_DSLPCLKCFG_D_5   0x02000000  // /5
-#define SYSCTL_DSLPCLKCFG_D_6   0x02800000  // /6
-#define SYSCTL_DSLPCLKCFG_D_7   0x03000000  // /7
-#define SYSCTL_DSLPCLKCFG_D_8   0x03800000  // /8
-#define SYSCTL_DSLPCLKCFG_D_9   0x04000000  // /9
-#define SYSCTL_DSLPCLKCFG_D_10  0x04800000  // /10
-#define SYSCTL_DSLPCLKCFG_D_11  0x05000000  // /11
-#define SYSCTL_DSLPCLKCFG_D_12  0x05800000  // /12
-#define SYSCTL_DSLPCLKCFG_D_13  0x06000000  // /13
-#define SYSCTL_DSLPCLKCFG_D_14  0x06800000  // /14
-#define SYSCTL_DSLPCLKCFG_D_15  0x07000000  // /15
-#define SYSCTL_DSLPCLKCFG_D_16  0x07800000  // /16
-#define SYSCTL_DSLPCLKCFG_O_M   0x00000070  // Clock Source.
+#define SYSCTL_DSLPCLKCFG_D_M   0x1F800000  // Divider Field Override
+#define SYSCTL_DSLPCLKCFG_D_1   0x00000000  // System clock /1
+#define SYSCTL_DSLPCLKCFG_D_2   0x00800000  // System clock /2
+#define SYSCTL_DSLPCLKCFG_D_3   0x01000000  // System clock /3
+#define SYSCTL_DSLPCLKCFG_D_4   0x01800000  // System clock /4
+#define SYSCTL_DSLPCLKCFG_D_5   0x02000000  // System clock /5
+#define SYSCTL_DSLPCLKCFG_D_6   0x02800000  // System clock /6
+#define SYSCTL_DSLPCLKCFG_D_7   0x03000000  // System clock /7
+#define SYSCTL_DSLPCLKCFG_D_8   0x03800000  // System clock /8
+#define SYSCTL_DSLPCLKCFG_D_9   0x04000000  // System clock /9
+#define SYSCTL_DSLPCLKCFG_D_10  0x04800000  // System clock /10
+#define SYSCTL_DSLPCLKCFG_D_11  0x05000000  // System clock /11
+#define SYSCTL_DSLPCLKCFG_D_12  0x05800000  // System clock /12
+#define SYSCTL_DSLPCLKCFG_D_13  0x06000000  // System clock /13
+#define SYSCTL_DSLPCLKCFG_D_14  0x06800000  // System clock /14
+#define SYSCTL_DSLPCLKCFG_D_15  0x07000000  // System clock /15
+#define SYSCTL_DSLPCLKCFG_D_16  0x07800000  // System clock /16
+#define SYSCTL_DSLPCLKCFG_D_17  0x08000000  // System clock /17
+#define SYSCTL_DSLPCLKCFG_D_18  0x08800000  // System clock /18
+#define SYSCTL_DSLPCLKCFG_D_19  0x09000000  // System clock /19
+#define SYSCTL_DSLPCLKCFG_D_20  0x09800000  // System clock /20
+#define SYSCTL_DSLPCLKCFG_D_21  0x0A000000  // System clock /21
+#define SYSCTL_DSLPCLKCFG_D_22  0x0A800000  // System clock /22
+#define SYSCTL_DSLPCLKCFG_D_23  0x0B000000  // System clock /23
+#define SYSCTL_DSLPCLKCFG_D_24  0x0B800000  // System clock /24
+#define SYSCTL_DSLPCLKCFG_D_25  0x0C000000  // System clock /25
+#define SYSCTL_DSLPCLKCFG_D_26  0x0C800000  // System clock /26
+#define SYSCTL_DSLPCLKCFG_D_27  0x0D000000  // System clock /27
+#define SYSCTL_DSLPCLKCFG_D_28  0x0D800000  // System clock /28
+#define SYSCTL_DSLPCLKCFG_D_29  0x0E000000  // System clock /29
+#define SYSCTL_DSLPCLKCFG_D_30  0x0E800000  // System clock /30
+#define SYSCTL_DSLPCLKCFG_D_31  0x0F000000  // System clock /31
+#define SYSCTL_DSLPCLKCFG_D_32  0x0F800000  // System clock /32
+#define SYSCTL_DSLPCLKCFG_D_33  0x10000000  // System clock /33
+#define SYSCTL_DSLPCLKCFG_D_34  0x10800000  // System clock /34
+#define SYSCTL_DSLPCLKCFG_D_35  0x11000000  // System clock /35
+#define SYSCTL_DSLPCLKCFG_D_36  0x11800000  // System clock /36
+#define SYSCTL_DSLPCLKCFG_D_37  0x12000000  // System clock /37
+#define SYSCTL_DSLPCLKCFG_D_38  0x12800000  // System clock /38
+#define SYSCTL_DSLPCLKCFG_D_39  0x13000000  // System clock /39
+#define SYSCTL_DSLPCLKCFG_D_40  0x13800000  // System clock /40
+#define SYSCTL_DSLPCLKCFG_D_41  0x14000000  // System clock /41
+#define SYSCTL_DSLPCLKCFG_D_42  0x14800000  // System clock /42
+#define SYSCTL_DSLPCLKCFG_D_43  0x15000000  // System clock /43
+#define SYSCTL_DSLPCLKCFG_D_44  0x15800000  // System clock /44
+#define SYSCTL_DSLPCLKCFG_D_45  0x16000000  // System clock /45
+#define SYSCTL_DSLPCLKCFG_D_46  0x16800000  // System clock /46
+#define SYSCTL_DSLPCLKCFG_D_47  0x17000000  // System clock /47
+#define SYSCTL_DSLPCLKCFG_D_48  0x17800000  // System clock /48
+#define SYSCTL_DSLPCLKCFG_D_49  0x18000000  // System clock /49
+#define SYSCTL_DSLPCLKCFG_D_50  0x18800000  // System clock /50
+#define SYSCTL_DSLPCLKCFG_D_51  0x19000000  // System clock /51
+#define SYSCTL_DSLPCLKCFG_D_52  0x19800000  // System clock /52
+#define SYSCTL_DSLPCLKCFG_D_53  0x1A000000  // System clock /53
+#define SYSCTL_DSLPCLKCFG_D_54  0x1A800000  // System clock /54
+#define SYSCTL_DSLPCLKCFG_D_55  0x1B000000  // System clock /55
+#define SYSCTL_DSLPCLKCFG_D_56  0x1B800000  // System clock /56
+#define SYSCTL_DSLPCLKCFG_D_57  0x1C000000  // System clock /57
+#define SYSCTL_DSLPCLKCFG_D_58  0x1C800000  // System clock /58
+#define SYSCTL_DSLPCLKCFG_D_59  0x1D000000  // System clock /59
+#define SYSCTL_DSLPCLKCFG_D_60  0x1D800000  // System clock /60
+#define SYSCTL_DSLPCLKCFG_D_61  0x1E000000  // System clock /61
+#define SYSCTL_DSLPCLKCFG_D_62  0x1E800000  // System clock /62
+#define SYSCTL_DSLPCLKCFG_D_63  0x1F000000  // System clock /63
+#define SYSCTL_DSLPCLKCFG_D_64  0x1F800000  // System clock /64
+#define SYSCTL_DSLPCLKCFG_O_M   0x00000070  // Clock Source
 #define SYSCTL_DSLPCLKCFG_O_IGN 0x00000000  // MOSC
 #define SYSCTL_DSLPCLKCFG_O_IO  0x00000010  // PIOSC
 #define SYSCTL_DSLPCLKCFG_O_30  0x00000030  // 30 kHz
 
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_DSFLASHCFG
-// register.
-//
-//*****************************************************************************
-#define SYSCTL_DSFLASHCFG_SHDWN 0x00000001  // Flash Shutdown.
-
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_PIOSCCAL
 // register.
 //
 //*****************************************************************************
-#define SYSCTL_PIOSCCAL_UTEN    0x80000000  // Use User Trim Value.
-#define SYSCTL_PIOSCCAL_UPDATE  0x00000100  // Update Trim.
-#define SYSCTL_PIOSCCAL_UT_M    0x0000007F  // User Trim Value.
+#define SYSCTL_PIOSCCAL_UTEN    0x80000000  // Use User Trim Value
+#define SYSCTL_PIOSCCAL_UPDATE  0x00000100  // Update Trim
+#define SYSCTL_PIOSCCAL_UT_M    0x0000007F  // User Trim Value
 #define SYSCTL_PIOSCCAL_UT_S    0
 
 //*****************************************************************************
@@ -10624,12 +11110,12 @@
 // register.
 //
 //*****************************************************************************
-#define SYSCTL_I2SMCLKCFG_RXEN  0x80000000  // RX Clock Enable.
-#define SYSCTL_I2SMCLKCFG_RXI_M 0x0FF00000  // RX Clock Integer Input.
-#define SYSCTL_I2SMCLKCFG_RXF_M 0x000F0000  // RX Clock Fractional Input.
-#define SYSCTL_I2SMCLKCFG_TXEN  0x00008000  // TX Clock Enable.
-#define SYSCTL_I2SMCLKCFG_TXI_M 0x00000FF0  // TX Clock Integer Input.
-#define SYSCTL_I2SMCLKCFG_TXF_M 0x0000000F  // TX Clock Fractional Input.
+#define SYSCTL_I2SMCLKCFG_RXEN  0x80000000  // RX Clock Enable
+#define SYSCTL_I2SMCLKCFG_RXI_M 0x3FF00000  // RX Clock Integer Input
+#define SYSCTL_I2SMCLKCFG_RXF_M 0x000F0000  // RX Clock Fractional Input
+#define SYSCTL_I2SMCLKCFG_TXEN  0x00008000  // TX Clock Enable
+#define SYSCTL_I2SMCLKCFG_TXI_M 0x00003FF0  // TX Clock Integer Input
+#define SYSCTL_I2SMCLKCFG_TXF_M 0x0000000F  // TX Clock Fractional Input
 #define SYSCTL_I2SMCLKCFG_RXI_S 20
 #define SYSCTL_I2SMCLKCFG_RXF_S 16
 #define SYSCTL_I2SMCLKCFG_TXI_S 4
@@ -10640,22 +11126,22 @@
 // The following are defines for the bit fields in the SYSCTL_DC9 register.
 //
 //*****************************************************************************
-#define SYSCTL_DC9_ADC1DC7      0x00800000  // ADC1 DC7 Present.
-#define SYSCTL_DC9_ADC1DC6      0x00400000  // ADC1 DC6 Present.
-#define SYSCTL_DC9_ADC1DC5      0x00200000  // ADC1 DC5 Present.
-#define SYSCTL_DC9_ADC1DC4      0x00100000  // ADC1 DC4 Present.
-#define SYSCTL_DC9_ADC1DC3      0x00080000  // ADC1 DC3 Present.
-#define SYSCTL_DC9_ADC1DC2      0x00040000  // ADC1 DC2 Present.
-#define SYSCTL_DC9_ADC1DC1      0x00020000  // ADC1 DC1 Present.
-#define SYSCTL_DC9_ADC1DC0      0x00010000  // ADC1 DC0 Present.
-#define SYSCTL_DC9_ADC0DC7      0x00000080  // ADC0 DC7 Present.
-#define SYSCTL_DC9_ADC0DC6      0x00000040  // ADC0 DC6 Present.
-#define SYSCTL_DC9_ADC0DC5      0x00000020  // ADC0 DC5 Present.
-#define SYSCTL_DC9_ADC0DC4      0x00000010  // ADC0 DC4 Present.
-#define SYSCTL_DC9_ADC0DC3      0x00000008  // ADC0 DC3 Present.
-#define SYSCTL_DC9_ADC0DC2      0x00000004  // ADC0 DC2 Present.
-#define SYSCTL_DC9_ADC0DC1      0x00000002  // ADC0 DC1 Present.
-#define SYSCTL_DC9_ADC0DC0      0x00000001  // ADC0 DC0 Present.
+#define SYSCTL_DC9_ADC1DC7      0x00800000  // ADC1 DC7 Present
+#define SYSCTL_DC9_ADC1DC6      0x00400000  // ADC1 DC6 Present
+#define SYSCTL_DC9_ADC1DC5      0x00200000  // ADC1 DC5 Present
+#define SYSCTL_DC9_ADC1DC4      0x00100000  // ADC1 DC4 Present
+#define SYSCTL_DC9_ADC1DC3      0x00080000  // ADC1 DC3 Present
+#define SYSCTL_DC9_ADC1DC2      0x00040000  // ADC1 DC2 Present
+#define SYSCTL_DC9_ADC1DC1      0x00020000  // ADC1 DC1 Present
+#define SYSCTL_DC9_ADC1DC0      0x00010000  // ADC1 DC0 Present
+#define SYSCTL_DC9_ADC0DC7      0x00000080  // ADC0 DC7 Present
+#define SYSCTL_DC9_ADC0DC6      0x00000040  // ADC0 DC6 Present
+#define SYSCTL_DC9_ADC0DC5      0x00000020  // ADC0 DC5 Present
+#define SYSCTL_DC9_ADC0DC4      0x00000010  // ADC0 DC4 Present
+#define SYSCTL_DC9_ADC0DC3      0x00000008  // ADC0 DC3 Present
+#define SYSCTL_DC9_ADC0DC2      0x00000004  // ADC0 DC2 Present
+#define SYSCTL_DC9_ADC0DC1      0x00000002  // ADC0 DC1 Present
+#define SYSCTL_DC9_ADC0DC0      0x00000001  // ADC0 DC0 Present
 
 //*****************************************************************************
 //
@@ -10663,14 +11149,170 @@
 //
 //*****************************************************************************
 #define SYSCTL_NVMSTAT_FWB      0x00000001  // 32 Word Flash Write Buffer
-                                            // Active.
+                                            // Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_STAT register.
+//
+//*****************************************************************************
+#define UDMA_STAT_DMACHANS_M    0x001F0000  // Available uDMA Channels Minus 1
+#define UDMA_STAT_STATE_M       0x000000F0  // Control State Machine Status
+#define UDMA_STAT_STATE_IDLE    0x00000000  // Idle
+#define UDMA_STAT_STATE_RD_CTRL 0x00000010  // Reading channel controller data
+#define UDMA_STAT_STATE_RD_SRCENDP \
+                                0x00000020  // Reading source end pointer
+#define UDMA_STAT_STATE_RD_DSTENDP \
+                                0x00000030  // Reading destination end pointer
+#define UDMA_STAT_STATE_RD_SRCDAT \
+                                0x00000040  // Reading source data
+#define UDMA_STAT_STATE_WR_DSTDAT \
+                                0x00000050  // Writing destination data
+#define UDMA_STAT_STATE_WAIT    0x00000060  // Waiting for uDMA request to
+                                            // clear
+#define UDMA_STAT_STATE_WR_CTRL 0x00000070  // Writing channel controller data
+#define UDMA_STAT_STATE_STALL   0x00000080  // Stalled
+#define UDMA_STAT_STATE_DONE    0x00000090  // Done
+#define UDMA_STAT_STATE_UNDEF   0x000000A0  // Undefined
+#define UDMA_STAT_MASTEN        0x00000001  // Master Enable Status
+#define UDMA_STAT_DMACHANS_S    16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CFG register.
+//
+//*****************************************************************************
+#define UDMA_CFG_MASTEN         0x00000001  // Controller Master Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CTLBASE register.
+//
+//*****************************************************************************
+#define UDMA_CTLBASE_ADDR_M     0xFFFFFC00  // Channel Control Base Address
+#define UDMA_CTLBASE_ADDR_S     10
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ALTBASE register.
+//
+//*****************************************************************************
+#define UDMA_ALTBASE_ADDR_M     0xFFFFFFFF  // Alternate Channel Address
+                                            // Pointer
+#define UDMA_ALTBASE_ADDR_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_WAITSTAT register.
+//
+//*****************************************************************************
+#define UDMA_WAITSTAT_WAITREQ_M 0xFFFFFFFF  // Channel [n] Wait Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_SWREQ register.
+//
+//*****************************************************************************
+#define UDMA_SWREQ_M            0xFFFFFFFF  // Channel [n] Software Request
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_USEBURSTSET
+// register.
+//
+//*****************************************************************************
+#define UDMA_USEBURSTSET_SET_M  0xFFFFFFFF  // Channel [n] Useburst Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_USEBURSTCLR
+// register.
+//
+//*****************************************************************************
+#define UDMA_USEBURSTCLR_CLR_M  0xFFFFFFFF  // Channel [n] Useburst Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_REQMASKSET
+// register.
+//
+//*****************************************************************************
+#define UDMA_REQMASKSET_SET_M   0xFFFFFFFF  // Channel [n] Request Mask Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_REQMASKCLR
+// register.
+//
+//*****************************************************************************
+#define UDMA_REQMASKCLR_CLR_M   0xFFFFFFFF  // Channel [n] Request Mask Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ENASET register.
+//
+//*****************************************************************************
+#define UDMA_ENASET_SET_M       0xFFFFFFFF  // Channel [n] Enable Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ENACLR register.
+//
+//*****************************************************************************
+#define UDMA_ENACLR_CLR_M       0xFFFFFFFF  // Clear Channel [n] Enable Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ALTSET register.
+//
+//*****************************************************************************
+#define UDMA_ALTSET_SET_M       0xFFFFFFFF  // Channel [n] Alternate Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ALTCLR register.
+//
+//*****************************************************************************
+#define UDMA_ALTCLR_CLR_M       0xFFFFFFFF  // Channel [n] Alternate Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_PRIOSET register.
+//
+//*****************************************************************************
+#define UDMA_PRIOSET_SET_M      0xFFFFFFFF  // Channel [n] Priority Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_PRIOCLR register.
+//
+//*****************************************************************************
+#define UDMA_PRIOCLR_CLR_M      0xFFFFFFFF  // Channel [n] Priority Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ERRCLR register.
+//
+//*****************************************************************************
+#define UDMA_ERRCLR_ERRCLR      0x00000001  // uDMA Bus Error Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CHASGN register.
+//
+//*****************************************************************************
+#define UDMA_CHASGN_M           0xFFFFFFFF  // Channel [n] Assignment Select
+#define UDMA_CHASGN_PRIMARY     0x00000000  // Use the primary channel
+                                            // assignment
+#define UDMA_CHASGN_SECONDARY   0x00000001  // Use the secondary channel
+                                            // assignment
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the UDMA_O_SRCENDP register.
 //
 //*****************************************************************************
-#define UDMA_SRCENDP_ADDR_M     0xFFFFFFFF  // Source Address End Pointer.
+#define UDMA_SRCENDP_ADDR_M     0xFFFFFFFF  // Source Address End Pointer
 #define UDMA_SRCENDP_ADDR_S     0
 
 //*****************************************************************************
@@ -10678,7 +11320,7 @@
 // The following are defines for the bit fields in the UDMA_O_DSTENDP register.
 //
 //*****************************************************************************
-#define UDMA_DSTENDP_ADDR_M     0xFFFFFFFF  // Destination Address End Pointer.
+#define UDMA_DSTENDP_ADDR_M     0xFFFFFFFF  // Destination Address End Pointer
 #define UDMA_DSTENDP_ADDR_S     0
 
 //*****************************************************************************
@@ -10686,25 +11328,25 @@
 // The following are defines for the bit fields in the UDMA_O_CHCTL register.
 //
 //*****************************************************************************
-#define UDMA_CHCTL_DSTINC_M     0xC0000000  // Destination Address Increment.
+#define UDMA_CHCTL_DSTINC_M     0xC0000000  // Destination Address Increment
 #define UDMA_CHCTL_DSTINC_8     0x00000000  // Byte
 #define UDMA_CHCTL_DSTINC_16    0x40000000  // Half-word
 #define UDMA_CHCTL_DSTINC_32    0x80000000  // Word
 #define UDMA_CHCTL_DSTINC_NONE  0xC0000000  // No increment
-#define UDMA_CHCTL_DSTSIZE_M    0x30000000  // Destination Data Size.
+#define UDMA_CHCTL_DSTSIZE_M    0x30000000  // Destination Data Size
 #define UDMA_CHCTL_DSTSIZE_8    0x00000000  // Byte
 #define UDMA_CHCTL_DSTSIZE_16   0x10000000  // Half-word
 #define UDMA_CHCTL_DSTSIZE_32   0x20000000  // Word
-#define UDMA_CHCTL_SRCINC_M     0x0C000000  // Source Address Increment.
+#define UDMA_CHCTL_SRCINC_M     0x0C000000  // Source Address Increment
 #define UDMA_CHCTL_SRCINC_8     0x00000000  // Byte
 #define UDMA_CHCTL_SRCINC_16    0x04000000  // Half-word
 #define UDMA_CHCTL_SRCINC_32    0x08000000  // Word
 #define UDMA_CHCTL_SRCINC_NONE  0x0C000000  // No increment
-#define UDMA_CHCTL_SRCSIZE_M    0x03000000  // Source Data Size.
+#define UDMA_CHCTL_SRCSIZE_M    0x03000000  // Source Data Size
 #define UDMA_CHCTL_SRCSIZE_8    0x00000000  // Byte
 #define UDMA_CHCTL_SRCSIZE_16   0x01000000  // Half-word
 #define UDMA_CHCTL_SRCSIZE_32   0x02000000  // Word
-#define UDMA_CHCTL_ARBSIZE_M    0x0003C000  // Arbitration Size.
+#define UDMA_CHCTL_ARBSIZE_M    0x0003C000  // Arbitration Size
 #define UDMA_CHCTL_ARBSIZE_1    0x00000000  // 1 Transfer
 #define UDMA_CHCTL_ARBSIZE_2    0x00004000  // 2 Transfers
 #define UDMA_CHCTL_ARBSIZE_4    0x00008000  // 4 Transfers
@@ -10716,9 +11358,9 @@
 #define UDMA_CHCTL_ARBSIZE_256  0x00020000  // 256 Transfers
 #define UDMA_CHCTL_ARBSIZE_512  0x00024000  // 512 Transfers
 #define UDMA_CHCTL_ARBSIZE_1024 0x00028000  // 1024 Transfers
-#define UDMA_CHCTL_XFERSIZE_M   0x00003FF0  // Transfer Size (minus 1).
-#define UDMA_CHCTL_NXTUSEBURST  0x00000008  // Next Useburst.
-#define UDMA_CHCTL_XFERMODE_M   0x00000007  // DMA Transfer Mode.
+#define UDMA_CHCTL_XFERSIZE_M   0x00003FF0  // Transfer Size (minus 1)
+#define UDMA_CHCTL_NXTUSEBURST  0x00000008  // Next Useburst
+#define UDMA_CHCTL_XFERMODE_M   0x00000007  // uDMA Transfer Mode
 #define UDMA_CHCTL_XFERMODE_STOP \
                                 0x00000000  // Stop
 #define UDMA_CHCTL_XFERMODE_BASIC \
@@ -10738,165 +11380,6 @@
                                             // Scatter-Gather
 #define UDMA_CHCTL_XFERSIZE_S   4
 
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_STAT register.
-//
-//*****************************************************************************
-#define UDMA_STAT_DMACHANS_M    0x001F0000  // Available DMA Channels Minus 1.
-#define UDMA_STAT_STATE_M       0x000000F0  // Control State Machine Status.
-#define UDMA_STAT_STATE_IDLE    0x00000000  // Idle
-#define UDMA_STAT_STATE_RD_CTRL 0x00000010  // Read Chan Control Data
-#define UDMA_STAT_STATE_RD_SRCENDP \
-                                0x00000020  // Read Source End Ptr
-#define UDMA_STAT_STATE_RD_DSTENDP \
-                                0x00000030  // Read Dest End Ptr
-#define UDMA_STAT_STATE_RD_SRCDAT \
-                                0x00000040  // Read Source Data
-#define UDMA_STAT_STATE_WR_DSTDAT \
-                                0x00000050  // Write Dest Data
-#define UDMA_STAT_STATE_WAIT    0x00000060  // Wait for Req Clear
-#define UDMA_STAT_STATE_WR_CTRL 0x00000070  // Write Chan Control Data
-#define UDMA_STAT_STATE_STALL   0x00000080  // Stalled
-#define UDMA_STAT_STATE_DONE    0x00000090  // Done
-#define UDMA_STAT_STATE_UNDEF   0x000000A0  // Undefined
-#define UDMA_STAT_MASTEN        0x00000001  // Master Enable.
-#define UDMA_STAT_DMACHANS_S    16
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_CFG register.
-//
-//*****************************************************************************
-#define UDMA_CFG_MASTEN         0x00000001  // Controller Master Enable.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_CTLBASE register.
-//
-//*****************************************************************************
-#define UDMA_CTLBASE_ADDR_M     0xFFFFFC00  // Channel Control Base Address.
-#define UDMA_CTLBASE_ADDR_S     10
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_ALTBASE register.
-//
-//*****************************************************************************
-#define UDMA_ALTBASE_ADDR_M     0xFFFFFFFF  // Alternate Channel Address
-                                            // Pointer.
-#define UDMA_ALTBASE_ADDR_S     0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_WAITSTAT register.
-//
-//*****************************************************************************
-#define UDMA_WAITSTAT_WAITREQ_M 0xFFFFFFFF  // Channel [n] Wait Status.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_SWREQ register.
-//
-//*****************************************************************************
-#define UDMA_SWREQ_M            0xFFFFFFFF  // Channel [n] Software Request.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_USEBURSTSET
-// register.
-//
-//*****************************************************************************
-#define UDMA_USEBURSTSET_SET_M  0xFFFFFFFF  // Channel [n] Useburst Set.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_USEBURSTCLR
-// register.
-//
-//*****************************************************************************
-#define UDMA_USEBURSTCLR_CLR_M  0xFFFFFFFF  // Channel [n] Useburst Clear.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_REQMASKSET
-// register.
-//
-//*****************************************************************************
-#define UDMA_REQMASKSET_SET_M   0xFFFFFFFF  // Channel [n] Request Mask Set.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_REQMASKCLR
-// register.
-//
-//*****************************************************************************
-#define UDMA_REQMASKCLR_CLR_M   0xFFFFFFFF  // Channel [n] Request Mask Clear.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_ENASET register.
-//
-//*****************************************************************************
-#define UDMA_ENASET_SET_M       0xFFFFFFFF  // Channel [n] Enable Set.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_ENACLR register.
-//
-//*****************************************************************************
-#define UDMA_ENACLR_CLR_M       0xFFFFFFFF  // Clear Channel [n] Enable.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_ALTSET register.
-//
-//*****************************************************************************
-#define UDMA_ALTSET_SET_M       0xFFFFFFFF  // Channel [n] Alternate Set.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_ALTCLR register.
-//
-//*****************************************************************************
-#define UDMA_ALTCLR_CLR_M       0xFFFFFFFF  // Channel [n] Alternate Clear.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_PRIOSET register.
-//
-//*****************************************************************************
-#define UDMA_PRIOSET_SET_M      0xFFFFFFFF  // Channel [n] Priority Set.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_PRIOCLR register.
-//
-//*****************************************************************************
-#define UDMA_PRIOCLR_CLR_M      0xFFFFFFFF  // Channel [n] Priority Clear.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_ERRCLR register.
-//
-//*****************************************************************************
-#define UDMA_ERRCLR_ERRCLR      0x00000001  // DMA Bus Error Clear.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_CHALT register.
-//
-//*****************************************************************************
-#define UDMA_CHALT_M            0xFFFFFFFF  // Channel [n] Alternate Assignment
-                                            // Select.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_CHIS register.
-//
-//*****************************************************************************
-#define UDMA_CHIS_M             0xFFFFFFFF  // Channel [n] Interrupt Status.
-
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_INT_TYPE register.
@@ -10905,22 +11388,32 @@
 #define NVIC_INT_TYPE_LINES_M   0x0000001F  // Number of interrupt lines (x32)
 #define NVIC_INT_TYPE_LINES_S   0
 
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTLR register.
+//
+//*****************************************************************************
+#define NVIC_ACTLR_DISFOLD      0x00000004  // Disable IT Folding
+#define NVIC_ACTLR_DISWBUF      0x00000002  // Disable Write Buffer
+#define NVIC_ACTLR_DISMCYC      0x00000001  // Disable Interrupts of Multiple
+                                            // Cycle Instructions
+
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_ST_CTRL register.
 //
 //*****************************************************************************
-#define NVIC_ST_CTRL_COUNT      0x00010000  // Count flag
+#define NVIC_ST_CTRL_COUNT      0x00010000  // Count Flag
 #define NVIC_ST_CTRL_CLK_SRC    0x00000004  // Clock Source
-#define NVIC_ST_CTRL_INTEN      0x00000002  // Interrupt enable
-#define NVIC_ST_CTRL_ENABLE     0x00000001  // Counter mode
+#define NVIC_ST_CTRL_INTEN      0x00000002  // Interrupt Enable
+#define NVIC_ST_CTRL_ENABLE     0x00000001  // Enable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_ST_RELOAD register.
 //
 //*****************************************************************************
-#define NVIC_ST_RELOAD_M        0x00FFFFFF  // Counter load value
+#define NVIC_ST_RELOAD_M        0x00FFFFFF  // Reload Value
 #define NVIC_ST_RELOAD_S        0
 
 //*****************************************************************************
@@ -10929,7 +11422,7 @@
 // register.
 //
 //*****************************************************************************
-#define NVIC_ST_CURRENT_M       0x00FFFFFF  // Counter current value
+#define NVIC_ST_CURRENT_M       0x00FFFFFF  // Current Value
 #define NVIC_ST_CURRENT_S       0
 
 //*****************************************************************************
@@ -10947,539 +11440,583 @@
 // The following are defines for the bit fields in the NVIC_EN0 register.
 //
 //*****************************************************************************
-#define NVIC_EN0_INT31          0x80000000  // Interrupt 31 enable
-#define NVIC_EN0_INT30          0x40000000  // Interrupt 30 enable
-#define NVIC_EN0_INT29          0x20000000  // Interrupt 29 enable
-#define NVIC_EN0_INT28          0x10000000  // Interrupt 28 enable
-#define NVIC_EN0_INT27          0x08000000  // Interrupt 27 enable
-#define NVIC_EN0_INT26          0x04000000  // Interrupt 26 enable
-#define NVIC_EN0_INT25          0x02000000  // Interrupt 25 enable
-#define NVIC_EN0_INT24          0x01000000  // Interrupt 24 enable
-#define NVIC_EN0_INT23          0x00800000  // Interrupt 23 enable
-#define NVIC_EN0_INT22          0x00400000  // Interrupt 22 enable
-#define NVIC_EN0_INT21          0x00200000  // Interrupt 21 enable
-#define NVIC_EN0_INT20          0x00100000  // Interrupt 20 enable
-#define NVIC_EN0_INT19          0x00080000  // Interrupt 19 enable
-#define NVIC_EN0_INT18          0x00040000  // Interrupt 18 enable
-#define NVIC_EN0_INT17          0x00020000  // Interrupt 17 enable
-#define NVIC_EN0_INT16          0x00010000  // Interrupt 16 enable
-#define NVIC_EN0_INT15          0x00008000  // Interrupt 15 enable
-#define NVIC_EN0_INT14          0x00004000  // Interrupt 14 enable
-#define NVIC_EN0_INT13          0x00002000  // Interrupt 13 enable
-#define NVIC_EN0_INT12          0x00001000  // Interrupt 12 enable
-#define NVIC_EN0_INT11          0x00000800  // Interrupt 11 enable
-#define NVIC_EN0_INT10          0x00000400  // Interrupt 10 enable
-#define NVIC_EN0_INT9           0x00000200  // Interrupt 9 enable
-#define NVIC_EN0_INT8           0x00000100  // Interrupt 8 enable
-#define NVIC_EN0_INT7           0x00000080  // Interrupt 7 enable
-#define NVIC_EN0_INT6           0x00000040  // Interrupt 6 enable
-#define NVIC_EN0_INT5           0x00000020  // Interrupt 5 enable
-#define NVIC_EN0_INT4           0x00000010  // Interrupt 4 enable
-#define NVIC_EN0_INT3           0x00000008  // Interrupt 3 enable
-#define NVIC_EN0_INT2           0x00000004  // Interrupt 2 enable
-#define NVIC_EN0_INT1           0x00000002  // Interrupt 1 enable
+#define NVIC_EN0_INT_M          0xFFFFFFFF  // Interrupt Enable
 #define NVIC_EN0_INT0           0x00000001  // Interrupt 0 enable
+#define NVIC_EN0_INT1           0x00000002  // Interrupt 1 enable
+#define NVIC_EN0_INT2           0x00000004  // Interrupt 2 enable
+#define NVIC_EN0_INT3           0x00000008  // Interrupt 3 enable
+#define NVIC_EN0_INT4           0x00000010  // Interrupt 4 enable
+#define NVIC_EN0_INT5           0x00000020  // Interrupt 5 enable
+#define NVIC_EN0_INT6           0x00000040  // Interrupt 6 enable
+#define NVIC_EN0_INT7           0x00000080  // Interrupt 7 enable
+#define NVIC_EN0_INT8           0x00000100  // Interrupt 8 enable
+#define NVIC_EN0_INT9           0x00000200  // Interrupt 9 enable
+#define NVIC_EN0_INT10          0x00000400  // Interrupt 10 enable
+#define NVIC_EN0_INT11          0x00000800  // Interrupt 11 enable
+#define NVIC_EN0_INT12          0x00001000  // Interrupt 12 enable
+#define NVIC_EN0_INT13          0x00002000  // Interrupt 13 enable
+#define NVIC_EN0_INT14          0x00004000  // Interrupt 14 enable
+#define NVIC_EN0_INT15          0x00008000  // Interrupt 15 enable
+#define NVIC_EN0_INT16          0x00010000  // Interrupt 16 enable
+#define NVIC_EN0_INT17          0x00020000  // Interrupt 17 enable
+#define NVIC_EN0_INT18          0x00040000  // Interrupt 18 enable
+#define NVIC_EN0_INT19          0x00080000  // Interrupt 19 enable
+#define NVIC_EN0_INT20          0x00100000  // Interrupt 20 enable
+#define NVIC_EN0_INT21          0x00200000  // Interrupt 21 enable
+#define NVIC_EN0_INT22          0x00400000  // Interrupt 22 enable
+#define NVIC_EN0_INT23          0x00800000  // Interrupt 23 enable
+#define NVIC_EN0_INT24          0x01000000  // Interrupt 24 enable
+#define NVIC_EN0_INT25          0x02000000  // Interrupt 25 enable
+#define NVIC_EN0_INT26          0x04000000  // Interrupt 26 enable
+#define NVIC_EN0_INT27          0x08000000  // Interrupt 27 enable
+#define NVIC_EN0_INT28          0x10000000  // Interrupt 28 enable
+#define NVIC_EN0_INT29          0x20000000  // Interrupt 29 enable
+#define NVIC_EN0_INT30          0x40000000  // Interrupt 30 enable
+#define NVIC_EN0_INT31          0x80000000  // Interrupt 31 enable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_EN1 register.
 //
 //*****************************************************************************
-#define NVIC_EN1_INT59          0x08000000  // Interrupt 59 enable
-#define NVIC_EN1_INT58          0x04000000  // Interrupt 58 enable
-#define NVIC_EN1_INT57          0x02000000  // Interrupt 57 enable
-#define NVIC_EN1_INT56          0x01000000  // Interrupt 56 enable
-#define NVIC_EN1_INT55          0x00800000  // Interrupt 55 enable
-#define NVIC_EN1_INT54          0x00400000  // Interrupt 54 enable
-#define NVIC_EN1_INT53          0x00200000  // Interrupt 53 enable
-#define NVIC_EN1_INT52          0x00100000  // Interrupt 52 enable
-#define NVIC_EN1_INT51          0x00080000  // Interrupt 51 enable
-#define NVIC_EN1_INT50          0x00040000  // Interrupt 50 enable
-#define NVIC_EN1_INT49          0x00020000  // Interrupt 49 enable
-#define NVIC_EN1_INT48          0x00010000  // Interrupt 48 enable
-#define NVIC_EN1_INT47          0x00008000  // Interrupt 47 enable
-#define NVIC_EN1_INT46          0x00004000  // Interrupt 46 enable
-#define NVIC_EN1_INT45          0x00002000  // Interrupt 45 enable
-#define NVIC_EN1_INT44          0x00001000  // Interrupt 44 enable
-#define NVIC_EN1_INT43          0x00000800  // Interrupt 43 enable
-#define NVIC_EN1_INT42          0x00000400  // Interrupt 42 enable
-#define NVIC_EN1_INT41          0x00000200  // Interrupt 41 enable
-#define NVIC_EN1_INT40          0x00000100  // Interrupt 40 enable
-#define NVIC_EN1_INT39          0x00000080  // Interrupt 39 enable
-#define NVIC_EN1_INT38          0x00000040  // Interrupt 38 enable
-#define NVIC_EN1_INT37          0x00000020  // Interrupt 37 enable
-#define NVIC_EN1_INT36          0x00000010  // Interrupt 36 enable
-#define NVIC_EN1_INT35          0x00000008  // Interrupt 35 enable
-#define NVIC_EN1_INT34          0x00000004  // Interrupt 34 enable
-#define NVIC_EN1_INT33          0x00000002  // Interrupt 33 enable
+#define NVIC_EN1_INT_M          0x007FFFFF  // Interrupt Enable
 #define NVIC_EN1_INT32          0x00000001  // Interrupt 32 enable
+#define NVIC_EN1_INT33          0x00000002  // Interrupt 33 enable
+#define NVIC_EN1_INT34          0x00000004  // Interrupt 34 enable
+#define NVIC_EN1_INT35          0x00000008  // Interrupt 35 enable
+#define NVIC_EN1_INT36          0x00000010  // Interrupt 36 enable
+#define NVIC_EN1_INT37          0x00000020  // Interrupt 37 enable
+#define NVIC_EN1_INT38          0x00000040  // Interrupt 38 enable
+#define NVIC_EN1_INT39          0x00000080  // Interrupt 39 enable
+#define NVIC_EN1_INT40          0x00000100  // Interrupt 40 enable
+#define NVIC_EN1_INT41          0x00000200  // Interrupt 41 enable
+#define NVIC_EN1_INT42          0x00000400  // Interrupt 42 enable
+#define NVIC_EN1_INT43          0x00000800  // Interrupt 43 enable
+#define NVIC_EN1_INT44          0x00001000  // Interrupt 44 enable
+#define NVIC_EN1_INT45          0x00002000  // Interrupt 45 enable
+#define NVIC_EN1_INT46          0x00004000  // Interrupt 46 enable
+#define NVIC_EN1_INT47          0x00008000  // Interrupt 47 enable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_DIS0 register.
 //
 //*****************************************************************************
-#define NVIC_DIS0_INT31         0x80000000  // Interrupt 31 disable
-#define NVIC_DIS0_INT30         0x40000000  // Interrupt 30 disable
-#define NVIC_DIS0_INT29         0x20000000  // Interrupt 29 disable
-#define NVIC_DIS0_INT28         0x10000000  // Interrupt 28 disable
-#define NVIC_DIS0_INT27         0x08000000  // Interrupt 27 disable
-#define NVIC_DIS0_INT26         0x04000000  // Interrupt 26 disable
-#define NVIC_DIS0_INT25         0x02000000  // Interrupt 25 disable
-#define NVIC_DIS0_INT24         0x01000000  // Interrupt 24 disable
-#define NVIC_DIS0_INT23         0x00800000  // Interrupt 23 disable
-#define NVIC_DIS0_INT22         0x00400000  // Interrupt 22 disable
-#define NVIC_DIS0_INT21         0x00200000  // Interrupt 21 disable
-#define NVIC_DIS0_INT20         0x00100000  // Interrupt 20 disable
-#define NVIC_DIS0_INT19         0x00080000  // Interrupt 19 disable
-#define NVIC_DIS0_INT18         0x00040000  // Interrupt 18 disable
-#define NVIC_DIS0_INT17         0x00020000  // Interrupt 17 disable
-#define NVIC_DIS0_INT16         0x00010000  // Interrupt 16 disable
-#define NVIC_DIS0_INT15         0x00008000  // Interrupt 15 disable
-#define NVIC_DIS0_INT14         0x00004000  // Interrupt 14 disable
-#define NVIC_DIS0_INT13         0x00002000  // Interrupt 13 disable
-#define NVIC_DIS0_INT12         0x00001000  // Interrupt 12 disable
-#define NVIC_DIS0_INT11         0x00000800  // Interrupt 11 disable
-#define NVIC_DIS0_INT10         0x00000400  // Interrupt 10 disable
-#define NVIC_DIS0_INT9          0x00000200  // Interrupt 9 disable
-#define NVIC_DIS0_INT8          0x00000100  // Interrupt 8 disable
-#define NVIC_DIS0_INT7          0x00000080  // Interrupt 7 disable
-#define NVIC_DIS0_INT6          0x00000040  // Interrupt 6 disable
-#define NVIC_DIS0_INT5          0x00000020  // Interrupt 5 disable
-#define NVIC_DIS0_INT4          0x00000010  // Interrupt 4 disable
-#define NVIC_DIS0_INT3          0x00000008  // Interrupt 3 disable
-#define NVIC_DIS0_INT2          0x00000004  // Interrupt 2 disable
-#define NVIC_DIS0_INT1          0x00000002  // Interrupt 1 disable
+#define NVIC_DIS0_INT_M         0xFFFFFFFF  // Interrupt Disable
 #define NVIC_DIS0_INT0          0x00000001  // Interrupt 0 disable
+#define NVIC_DIS0_INT1          0x00000002  // Interrupt 1 disable
+#define NVIC_DIS0_INT2          0x00000004  // Interrupt 2 disable
+#define NVIC_DIS0_INT3          0x00000008  // Interrupt 3 disable
+#define NVIC_DIS0_INT4          0x00000010  // Interrupt 4 disable
+#define NVIC_DIS0_INT5          0x00000020  // Interrupt 5 disable
+#define NVIC_DIS0_INT6          0x00000040  // Interrupt 6 disable
+#define NVIC_DIS0_INT7          0x00000080  // Interrupt 7 disable
+#define NVIC_DIS0_INT8          0x00000100  // Interrupt 8 disable
+#define NVIC_DIS0_INT9          0x00000200  // Interrupt 9 disable
+#define NVIC_DIS0_INT10         0x00000400  // Interrupt 10 disable
+#define NVIC_DIS0_INT11         0x00000800  // Interrupt 11 disable
+#define NVIC_DIS0_INT12         0x00001000  // Interrupt 12 disable
+#define NVIC_DIS0_INT13         0x00002000  // Interrupt 13 disable
+#define NVIC_DIS0_INT14         0x00004000  // Interrupt 14 disable
+#define NVIC_DIS0_INT15         0x00008000  // Interrupt 15 disable
+#define NVIC_DIS0_INT16         0x00010000  // Interrupt 16 disable
+#define NVIC_DIS0_INT17         0x00020000  // Interrupt 17 disable
+#define NVIC_DIS0_INT18         0x00040000  // Interrupt 18 disable
+#define NVIC_DIS0_INT19         0x00080000  // Interrupt 19 disable
+#define NVIC_DIS0_INT20         0x00100000  // Interrupt 20 disable
+#define NVIC_DIS0_INT21         0x00200000  // Interrupt 21 disable
+#define NVIC_DIS0_INT22         0x00400000  // Interrupt 22 disable
+#define NVIC_DIS0_INT23         0x00800000  // Interrupt 23 disable
+#define NVIC_DIS0_INT24         0x01000000  // Interrupt 24 disable
+#define NVIC_DIS0_INT25         0x02000000  // Interrupt 25 disable
+#define NVIC_DIS0_INT26         0x04000000  // Interrupt 26 disable
+#define NVIC_DIS0_INT27         0x08000000  // Interrupt 27 disable
+#define NVIC_DIS0_INT28         0x10000000  // Interrupt 28 disable
+#define NVIC_DIS0_INT29         0x20000000  // Interrupt 29 disable
+#define NVIC_DIS0_INT30         0x40000000  // Interrupt 30 disable
+#define NVIC_DIS0_INT31         0x80000000  // Interrupt 31 disable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_DIS1 register.
 //
 //*****************************************************************************
-#define NVIC_DIS1_INT59         0x08000000  // Interrupt 59 disable
-#define NVIC_DIS1_INT58         0x04000000  // Interrupt 58 disable
-#define NVIC_DIS1_INT57         0x02000000  // Interrupt 57 disable
-#define NVIC_DIS1_INT56         0x01000000  // Interrupt 56 disable
-#define NVIC_DIS1_INT55         0x00800000  // Interrupt 55 disable
-#define NVIC_DIS1_INT54         0x00400000  // Interrupt 54 disable
-#define NVIC_DIS1_INT53         0x00200000  // Interrupt 53 disable
-#define NVIC_DIS1_INT52         0x00100000  // Interrupt 52 disable
-#define NVIC_DIS1_INT51         0x00080000  // Interrupt 51 disable
-#define NVIC_DIS1_INT50         0x00040000  // Interrupt 50 disable
-#define NVIC_DIS1_INT49         0x00020000  // Interrupt 49 disable
-#define NVIC_DIS1_INT48         0x00010000  // Interrupt 48 disable
-#define NVIC_DIS1_INT47         0x00008000  // Interrupt 47 disable
-#define NVIC_DIS1_INT46         0x00004000  // Interrupt 46 disable
-#define NVIC_DIS1_INT45         0x00002000  // Interrupt 45 disable
-#define NVIC_DIS1_INT44         0x00001000  // Interrupt 44 disable
-#define NVIC_DIS1_INT43         0x00000800  // Interrupt 43 disable
-#define NVIC_DIS1_INT42         0x00000400  // Interrupt 42 disable
-#define NVIC_DIS1_INT41         0x00000200  // Interrupt 41 disable
-#define NVIC_DIS1_INT40         0x00000100  // Interrupt 40 disable
-#define NVIC_DIS1_INT39         0x00000080  // Interrupt 39 disable
-#define NVIC_DIS1_INT38         0x00000040  // Interrupt 38 disable
-#define NVIC_DIS1_INT37         0x00000020  // Interrupt 37 disable
-#define NVIC_DIS1_INT36         0x00000010  // Interrupt 36 disable
-#define NVIC_DIS1_INT35         0x00000008  // Interrupt 35 disable
-#define NVIC_DIS1_INT34         0x00000004  // Interrupt 34 disable
-#define NVIC_DIS1_INT33         0x00000002  // Interrupt 33 disable
+#define NVIC_DIS1_INT_M         0x007FFFFF  // Interrupt Disable
 #define NVIC_DIS1_INT32         0x00000001  // Interrupt 32 disable
+#define NVIC_DIS1_INT33         0x00000002  // Interrupt 33 disable
+#define NVIC_DIS1_INT34         0x00000004  // Interrupt 34 disable
+#define NVIC_DIS1_INT35         0x00000008  // Interrupt 35 disable
+#define NVIC_DIS1_INT36         0x00000010  // Interrupt 36 disable
+#define NVIC_DIS1_INT37         0x00000020  // Interrupt 37 disable
+#define NVIC_DIS1_INT38         0x00000040  // Interrupt 38 disable
+#define NVIC_DIS1_INT39         0x00000080  // Interrupt 39 disable
+#define NVIC_DIS1_INT40         0x00000100  // Interrupt 40 disable
+#define NVIC_DIS1_INT41         0x00000200  // Interrupt 41 disable
+#define NVIC_DIS1_INT42         0x00000400  // Interrupt 42 disable
+#define NVIC_DIS1_INT43         0x00000800  // Interrupt 43 disable
+#define NVIC_DIS1_INT44         0x00001000  // Interrupt 44 disable
+#define NVIC_DIS1_INT45         0x00002000  // Interrupt 45 disable
+#define NVIC_DIS1_INT46         0x00004000  // Interrupt 46 disable
+#define NVIC_DIS1_INT47         0x00008000  // Interrupt 47 disable
+#define NVIC_DIS1_INT48         0x00010000  // Interrupt 48 disable
+#define NVIC_DIS1_INT49         0x00020000  // Interrupt 49 disable
+#define NVIC_DIS1_INT50         0x00040000  // Interrupt 50 disable
+#define NVIC_DIS1_INT51         0x00080000  // Interrupt 51 disable
+#define NVIC_DIS1_INT52         0x00100000  // Interrupt 52 disable
+#define NVIC_DIS1_INT53         0x00200000  // Interrupt 53 disable
+#define NVIC_DIS1_INT54         0x00400000  // Interrupt 54 disable
+#define NVIC_DIS1_INT55         0x00800000  // Interrupt 55 disable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_PEND0 register.
 //
 //*****************************************************************************
-#define NVIC_PEND0_INT31        0x80000000  // Interrupt 31 pend
-#define NVIC_PEND0_INT30        0x40000000  // Interrupt 30 pend
-#define NVIC_PEND0_INT29        0x20000000  // Interrupt 29 pend
-#define NVIC_PEND0_INT28        0x10000000  // Interrupt 28 pend
-#define NVIC_PEND0_INT27        0x08000000  // Interrupt 27 pend
-#define NVIC_PEND0_INT26        0x04000000  // Interrupt 26 pend
-#define NVIC_PEND0_INT25        0x02000000  // Interrupt 25 pend
-#define NVIC_PEND0_INT24        0x01000000  // Interrupt 24 pend
-#define NVIC_PEND0_INT23        0x00800000  // Interrupt 23 pend
-#define NVIC_PEND0_INT22        0x00400000  // Interrupt 22 pend
-#define NVIC_PEND0_INT21        0x00200000  // Interrupt 21 pend
-#define NVIC_PEND0_INT20        0x00100000  // Interrupt 20 pend
-#define NVIC_PEND0_INT19        0x00080000  // Interrupt 19 pend
-#define NVIC_PEND0_INT18        0x00040000  // Interrupt 18 pend
-#define NVIC_PEND0_INT17        0x00020000  // Interrupt 17 pend
-#define NVIC_PEND0_INT16        0x00010000  // Interrupt 16 pend
-#define NVIC_PEND0_INT15        0x00008000  // Interrupt 15 pend
-#define NVIC_PEND0_INT14        0x00004000  // Interrupt 14 pend
-#define NVIC_PEND0_INT13        0x00002000  // Interrupt 13 pend
-#define NVIC_PEND0_INT12        0x00001000  // Interrupt 12 pend
-#define NVIC_PEND0_INT11        0x00000800  // Interrupt 11 pend
-#define NVIC_PEND0_INT10        0x00000400  // Interrupt 10 pend
-#define NVIC_PEND0_INT9         0x00000200  // Interrupt 9 pend
-#define NVIC_PEND0_INT8         0x00000100  // Interrupt 8 pend
-#define NVIC_PEND0_INT7         0x00000080  // Interrupt 7 pend
-#define NVIC_PEND0_INT6         0x00000040  // Interrupt 6 pend
-#define NVIC_PEND0_INT5         0x00000020  // Interrupt 5 pend
-#define NVIC_PEND0_INT4         0x00000010  // Interrupt 4 pend
-#define NVIC_PEND0_INT3         0x00000008  // Interrupt 3 pend
-#define NVIC_PEND0_INT2         0x00000004  // Interrupt 2 pend
-#define NVIC_PEND0_INT1         0x00000002  // Interrupt 1 pend
+#define NVIC_PEND0_INT_M        0xFFFFFFFF  // Interrupt Set Pending
 #define NVIC_PEND0_INT0         0x00000001  // Interrupt 0 pend
+#define NVIC_PEND0_INT1         0x00000002  // Interrupt 1 pend
+#define NVIC_PEND0_INT2         0x00000004  // Interrupt 2 pend
+#define NVIC_PEND0_INT3         0x00000008  // Interrupt 3 pend
+#define NVIC_PEND0_INT4         0x00000010  // Interrupt 4 pend
+#define NVIC_PEND0_INT5         0x00000020  // Interrupt 5 pend
+#define NVIC_PEND0_INT6         0x00000040  // Interrupt 6 pend
+#define NVIC_PEND0_INT7         0x00000080  // Interrupt 7 pend
+#define NVIC_PEND0_INT8         0x00000100  // Interrupt 8 pend
+#define NVIC_PEND0_INT9         0x00000200  // Interrupt 9 pend
+#define NVIC_PEND0_INT10        0x00000400  // Interrupt 10 pend
+#define NVIC_PEND0_INT11        0x00000800  // Interrupt 11 pend
+#define NVIC_PEND0_INT12        0x00001000  // Interrupt 12 pend
+#define NVIC_PEND0_INT13        0x00002000  // Interrupt 13 pend
+#define NVIC_PEND0_INT14        0x00004000  // Interrupt 14 pend
+#define NVIC_PEND0_INT15        0x00008000  // Interrupt 15 pend
+#define NVIC_PEND0_INT16        0x00010000  // Interrupt 16 pend
+#define NVIC_PEND0_INT17        0x00020000  // Interrupt 17 pend
+#define NVIC_PEND0_INT18        0x00040000  // Interrupt 18 pend
+#define NVIC_PEND0_INT19        0x00080000  // Interrupt 19 pend
+#define NVIC_PEND0_INT20        0x00100000  // Interrupt 20 pend
+#define NVIC_PEND0_INT21        0x00200000  // Interrupt 21 pend
+#define NVIC_PEND0_INT22        0x00400000  // Interrupt 22 pend
+#define NVIC_PEND0_INT23        0x00800000  // Interrupt 23 pend
+#define NVIC_PEND0_INT24        0x01000000  // Interrupt 24 pend
+#define NVIC_PEND0_INT25        0x02000000  // Interrupt 25 pend
+#define NVIC_PEND0_INT26        0x04000000  // Interrupt 26 pend
+#define NVIC_PEND0_INT27        0x08000000  // Interrupt 27 pend
+#define NVIC_PEND0_INT28        0x10000000  // Interrupt 28 pend
+#define NVIC_PEND0_INT29        0x20000000  // Interrupt 29 pend
+#define NVIC_PEND0_INT30        0x40000000  // Interrupt 30 pend
+#define NVIC_PEND0_INT31        0x80000000  // Interrupt 31 pend
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_PEND1 register.
 //
 //*****************************************************************************
-#define NVIC_PEND1_INT59        0x08000000  // Interrupt 59 pend
-#define NVIC_PEND1_INT58        0x04000000  // Interrupt 58 pend
-#define NVIC_PEND1_INT57        0x02000000  // Interrupt 57 pend
-#define NVIC_PEND1_INT56        0x01000000  // Interrupt 56 pend
-#define NVIC_PEND1_INT55        0x00800000  // Interrupt 55 pend
-#define NVIC_PEND1_INT54        0x00400000  // Interrupt 54 pend
-#define NVIC_PEND1_INT53        0x00200000  // Interrupt 53 pend
-#define NVIC_PEND1_INT52        0x00100000  // Interrupt 52 pend
-#define NVIC_PEND1_INT51        0x00080000  // Interrupt 51 pend
-#define NVIC_PEND1_INT50        0x00040000  // Interrupt 50 pend
-#define NVIC_PEND1_INT49        0x00020000  // Interrupt 49 pend
-#define NVIC_PEND1_INT48        0x00010000  // Interrupt 48 pend
-#define NVIC_PEND1_INT47        0x00008000  // Interrupt 47 pend
-#define NVIC_PEND1_INT46        0x00004000  // Interrupt 46 pend
-#define NVIC_PEND1_INT45        0x00002000  // Interrupt 45 pend
-#define NVIC_PEND1_INT44        0x00001000  // Interrupt 44 pend
-#define NVIC_PEND1_INT43        0x00000800  // Interrupt 43 pend
-#define NVIC_PEND1_INT42        0x00000400  // Interrupt 42 pend
-#define NVIC_PEND1_INT41        0x00000200  // Interrupt 41 pend
-#define NVIC_PEND1_INT40        0x00000100  // Interrupt 40 pend
-#define NVIC_PEND1_INT39        0x00000080  // Interrupt 39 pend
-#define NVIC_PEND1_INT38        0x00000040  // Interrupt 38 pend
-#define NVIC_PEND1_INT37        0x00000020  // Interrupt 37 pend
-#define NVIC_PEND1_INT36        0x00000010  // Interrupt 36 pend
-#define NVIC_PEND1_INT35        0x00000008  // Interrupt 35 pend
-#define NVIC_PEND1_INT34        0x00000004  // Interrupt 34 pend
-#define NVIC_PEND1_INT33        0x00000002  // Interrupt 33 pend
+#define NVIC_PEND1_INT_M        0x007FFFFF  // Interrupt Set Pending
 #define NVIC_PEND1_INT32        0x00000001  // Interrupt 32 pend
+#define NVIC_PEND1_INT33        0x00000002  // Interrupt 33 pend
+#define NVIC_PEND1_INT34        0x00000004  // Interrupt 34 pend
+#define NVIC_PEND1_INT35        0x00000008  // Interrupt 35 pend
+#define NVIC_PEND1_INT36        0x00000010  // Interrupt 36 pend
+#define NVIC_PEND1_INT37        0x00000020  // Interrupt 37 pend
+#define NVIC_PEND1_INT38        0x00000040  // Interrupt 38 pend
+#define NVIC_PEND1_INT39        0x00000080  // Interrupt 39 pend
+#define NVIC_PEND1_INT40        0x00000100  // Interrupt 40 pend
+#define NVIC_PEND1_INT41        0x00000200  // Interrupt 41 pend
+#define NVIC_PEND1_INT42        0x00000400  // Interrupt 42 pend
+#define NVIC_PEND1_INT43        0x00000800  // Interrupt 43 pend
+#define NVIC_PEND1_INT44        0x00001000  // Interrupt 44 pend
+#define NVIC_PEND1_INT45        0x00002000  // Interrupt 45 pend
+#define NVIC_PEND1_INT46        0x00004000  // Interrupt 46 pend
+#define NVIC_PEND1_INT47        0x00008000  // Interrupt 47 pend
+#define NVIC_PEND1_INT48        0x00010000  // Interrupt 48 pend
+#define NVIC_PEND1_INT49        0x00020000  // Interrupt 49 pend
+#define NVIC_PEND1_INT50        0x00040000  // Interrupt 50 pend
+#define NVIC_PEND1_INT51        0x00080000  // Interrupt 51 pend
+#define NVIC_PEND1_INT52        0x00100000  // Interrupt 52 pend
+#define NVIC_PEND1_INT53        0x00200000  // Interrupt 53 pend
+#define NVIC_PEND1_INT54        0x00400000  // Interrupt 54 pend
+#define NVIC_PEND1_INT55        0x00800000  // Interrupt 55 pend
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_UNPEND0 register.
 //
 //*****************************************************************************
-#define NVIC_UNPEND0_INT31      0x80000000  // Interrupt 31 unpend
-#define NVIC_UNPEND0_INT30      0x40000000  // Interrupt 30 unpend
-#define NVIC_UNPEND0_INT29      0x20000000  // Interrupt 29 unpend
-#define NVIC_UNPEND0_INT28      0x10000000  // Interrupt 28 unpend
-#define NVIC_UNPEND0_INT27      0x08000000  // Interrupt 27 unpend
-#define NVIC_UNPEND0_INT26      0x04000000  // Interrupt 26 unpend
-#define NVIC_UNPEND0_INT25      0x02000000  // Interrupt 25 unpend
-#define NVIC_UNPEND0_INT24      0x01000000  // Interrupt 24 unpend
-#define NVIC_UNPEND0_INT23      0x00800000  // Interrupt 23 unpend
-#define NVIC_UNPEND0_INT22      0x00400000  // Interrupt 22 unpend
-#define NVIC_UNPEND0_INT21      0x00200000  // Interrupt 21 unpend
-#define NVIC_UNPEND0_INT20      0x00100000  // Interrupt 20 unpend
-#define NVIC_UNPEND0_INT19      0x00080000  // Interrupt 19 unpend
-#define NVIC_UNPEND0_INT18      0x00040000  // Interrupt 18 unpend
-#define NVIC_UNPEND0_INT17      0x00020000  // Interrupt 17 unpend
-#define NVIC_UNPEND0_INT16      0x00010000  // Interrupt 16 unpend
-#define NVIC_UNPEND0_INT15      0x00008000  // Interrupt 15 unpend
-#define NVIC_UNPEND0_INT14      0x00004000  // Interrupt 14 unpend
-#define NVIC_UNPEND0_INT13      0x00002000  // Interrupt 13 unpend
-#define NVIC_UNPEND0_INT12      0x00001000  // Interrupt 12 unpend
-#define NVIC_UNPEND0_INT11      0x00000800  // Interrupt 11 unpend
-#define NVIC_UNPEND0_INT10      0x00000400  // Interrupt 10 unpend
-#define NVIC_UNPEND0_INT9       0x00000200  // Interrupt 9 unpend
-#define NVIC_UNPEND0_INT8       0x00000100  // Interrupt 8 unpend
-#define NVIC_UNPEND0_INT7       0x00000080  // Interrupt 7 unpend
-#define NVIC_UNPEND0_INT6       0x00000040  // Interrupt 6 unpend
-#define NVIC_UNPEND0_INT5       0x00000020  // Interrupt 5 unpend
-#define NVIC_UNPEND0_INT4       0x00000010  // Interrupt 4 unpend
-#define NVIC_UNPEND0_INT3       0x00000008  // Interrupt 3 unpend
-#define NVIC_UNPEND0_INT2       0x00000004  // Interrupt 2 unpend
-#define NVIC_UNPEND0_INT1       0x00000002  // Interrupt 1 unpend
+#define NVIC_UNPEND0_INT_M      0xFFFFFFFF  // Interrupt Clear Pending
 #define NVIC_UNPEND0_INT0       0x00000001  // Interrupt 0 unpend
+#define NVIC_UNPEND0_INT1       0x00000002  // Interrupt 1 unpend
+#define NVIC_UNPEND0_INT2       0x00000004  // Interrupt 2 unpend
+#define NVIC_UNPEND0_INT3       0x00000008  // Interrupt 3 unpend
+#define NVIC_UNPEND0_INT4       0x00000010  // Interrupt 4 unpend
+#define NVIC_UNPEND0_INT5       0x00000020  // Interrupt 5 unpend
+#define NVIC_UNPEND0_INT6       0x00000040  // Interrupt 6 unpend
+#define NVIC_UNPEND0_INT7       0x00000080  // Interrupt 7 unpend
+#define NVIC_UNPEND0_INT8       0x00000100  // Interrupt 8 unpend
+#define NVIC_UNPEND0_INT9       0x00000200  // Interrupt 9 unpend
+#define NVIC_UNPEND0_INT10      0x00000400  // Interrupt 10 unpend
+#define NVIC_UNPEND0_INT11      0x00000800  // Interrupt 11 unpend
+#define NVIC_UNPEND0_INT12      0x00001000  // Interrupt 12 unpend
+#define NVIC_UNPEND0_INT13      0x00002000  // Interrupt 13 unpend
+#define NVIC_UNPEND0_INT14      0x00004000  // Interrupt 14 unpend
+#define NVIC_UNPEND0_INT15      0x00008000  // Interrupt 15 unpend
+#define NVIC_UNPEND0_INT16      0x00010000  // Interrupt 16 unpend
+#define NVIC_UNPEND0_INT17      0x00020000  // Interrupt 17 unpend
+#define NVIC_UNPEND0_INT18      0x00040000  // Interrupt 18 unpend
+#define NVIC_UNPEND0_INT19      0x00080000  // Interrupt 19 unpend
+#define NVIC_UNPEND0_INT20      0x00100000  // Interrupt 20 unpend
+#define NVIC_UNPEND0_INT21      0x00200000  // Interrupt 21 unpend
+#define NVIC_UNPEND0_INT22      0x00400000  // Interrupt 22 unpend
+#define NVIC_UNPEND0_INT23      0x00800000  // Interrupt 23 unpend
+#define NVIC_UNPEND0_INT24      0x01000000  // Interrupt 24 unpend
+#define NVIC_UNPEND0_INT25      0x02000000  // Interrupt 25 unpend
+#define NVIC_UNPEND0_INT26      0x04000000  // Interrupt 26 unpend
+#define NVIC_UNPEND0_INT27      0x08000000  // Interrupt 27 unpend
+#define NVIC_UNPEND0_INT28      0x10000000  // Interrupt 28 unpend
+#define NVIC_UNPEND0_INT29      0x20000000  // Interrupt 29 unpend
+#define NVIC_UNPEND0_INT30      0x40000000  // Interrupt 30 unpend
+#define NVIC_UNPEND0_INT31      0x80000000  // Interrupt 31 unpend
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_UNPEND1 register.
 //
 //*****************************************************************************
-#define NVIC_UNPEND1_INT59      0x08000000  // Interrupt 59 unpend
-#define NVIC_UNPEND1_INT58      0x04000000  // Interrupt 58 unpend
-#define NVIC_UNPEND1_INT57      0x02000000  // Interrupt 57 unpend
-#define NVIC_UNPEND1_INT56      0x01000000  // Interrupt 56 unpend
-#define NVIC_UNPEND1_INT55      0x00800000  // Interrupt 55 unpend
-#define NVIC_UNPEND1_INT54      0x00400000  // Interrupt 54 unpend
-#define NVIC_UNPEND1_INT53      0x00200000  // Interrupt 53 unpend
-#define NVIC_UNPEND1_INT52      0x00100000  // Interrupt 52 unpend
-#define NVIC_UNPEND1_INT51      0x00080000  // Interrupt 51 unpend
-#define NVIC_UNPEND1_INT50      0x00040000  // Interrupt 50 unpend
-#define NVIC_UNPEND1_INT49      0x00020000  // Interrupt 49 unpend
-#define NVIC_UNPEND1_INT48      0x00010000  // Interrupt 48 unpend
-#define NVIC_UNPEND1_INT47      0x00008000  // Interrupt 47 unpend
-#define NVIC_UNPEND1_INT46      0x00004000  // Interrupt 46 unpend
-#define NVIC_UNPEND1_INT45      0x00002000  // Interrupt 45 unpend
-#define NVIC_UNPEND1_INT44      0x00001000  // Interrupt 44 unpend
-#define NVIC_UNPEND1_INT43      0x00000800  // Interrupt 43 unpend
-#define NVIC_UNPEND1_INT42      0x00000400  // Interrupt 42 unpend
-#define NVIC_UNPEND1_INT41      0x00000200  // Interrupt 41 unpend
-#define NVIC_UNPEND1_INT40      0x00000100  // Interrupt 40 unpend
-#define NVIC_UNPEND1_INT39      0x00000080  // Interrupt 39 unpend
-#define NVIC_UNPEND1_INT38      0x00000040  // Interrupt 38 unpend
-#define NVIC_UNPEND1_INT37      0x00000020  // Interrupt 37 unpend
-#define NVIC_UNPEND1_INT36      0x00000010  // Interrupt 36 unpend
-#define NVIC_UNPEND1_INT35      0x00000008  // Interrupt 35 unpend
-#define NVIC_UNPEND1_INT34      0x00000004  // Interrupt 34 unpend
-#define NVIC_UNPEND1_INT33      0x00000002  // Interrupt 33 unpend
+#define NVIC_UNPEND1_INT_M      0x007FFFFF  // Interrupt Clear Pending
 #define NVIC_UNPEND1_INT32      0x00000001  // Interrupt 32 unpend
+#define NVIC_UNPEND1_INT33      0x00000002  // Interrupt 33 unpend
+#define NVIC_UNPEND1_INT34      0x00000004  // Interrupt 34 unpend
+#define NVIC_UNPEND1_INT35      0x00000008  // Interrupt 35 unpend
+#define NVIC_UNPEND1_INT36      0x00000010  // Interrupt 36 unpend
+#define NVIC_UNPEND1_INT37      0x00000020  // Interrupt 37 unpend
+#define NVIC_UNPEND1_INT38      0x00000040  // Interrupt 38 unpend
+#define NVIC_UNPEND1_INT39      0x00000080  // Interrupt 39 unpend
+#define NVIC_UNPEND1_INT40      0x00000100  // Interrupt 40 unpend
+#define NVIC_UNPEND1_INT41      0x00000200  // Interrupt 41 unpend
+#define NVIC_UNPEND1_INT42      0x00000400  // Interrupt 42 unpend
+#define NVIC_UNPEND1_INT43      0x00000800  // Interrupt 43 unpend
+#define NVIC_UNPEND1_INT44      0x00001000  // Interrupt 44 unpend
+#define NVIC_UNPEND1_INT45      0x00002000  // Interrupt 45 unpend
+#define NVIC_UNPEND1_INT46      0x00004000  // Interrupt 46 unpend
+#define NVIC_UNPEND1_INT47      0x00008000  // Interrupt 47 unpend
+#define NVIC_UNPEND1_INT48      0x00010000  // Interrupt 48 unpend
+#define NVIC_UNPEND1_INT49      0x00020000  // Interrupt 49 unpend
+#define NVIC_UNPEND1_INT50      0x00040000  // Interrupt 50 unpend
+#define NVIC_UNPEND1_INT51      0x00080000  // Interrupt 51 unpend
+#define NVIC_UNPEND1_INT52      0x00100000  // Interrupt 52 unpend
+#define NVIC_UNPEND1_INT53      0x00200000  // Interrupt 53 unpend
+#define NVIC_UNPEND1_INT54      0x00400000  // Interrupt 54 unpend
+#define NVIC_UNPEND1_INT55      0x00800000  // Interrupt 55 unpend
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_ACTIVE0 register.
 //
 //*****************************************************************************
-#define NVIC_ACTIVE0_INT31      0x80000000  // Interrupt 31 active
-#define NVIC_ACTIVE0_INT30      0x40000000  // Interrupt 30 active
-#define NVIC_ACTIVE0_INT29      0x20000000  // Interrupt 29 active
-#define NVIC_ACTIVE0_INT28      0x10000000  // Interrupt 28 active
-#define NVIC_ACTIVE0_INT27      0x08000000  // Interrupt 27 active
-#define NVIC_ACTIVE0_INT26      0x04000000  // Interrupt 26 active
-#define NVIC_ACTIVE0_INT25      0x02000000  // Interrupt 25 active
-#define NVIC_ACTIVE0_INT24      0x01000000  // Interrupt 24 active
-#define NVIC_ACTIVE0_INT23      0x00800000  // Interrupt 23 active
-#define NVIC_ACTIVE0_INT22      0x00400000  // Interrupt 22 active
-#define NVIC_ACTIVE0_INT21      0x00200000  // Interrupt 21 active
-#define NVIC_ACTIVE0_INT20      0x00100000  // Interrupt 20 active
-#define NVIC_ACTIVE0_INT19      0x00080000  // Interrupt 19 active
-#define NVIC_ACTIVE0_INT18      0x00040000  // Interrupt 18 active
-#define NVIC_ACTIVE0_INT17      0x00020000  // Interrupt 17 active
-#define NVIC_ACTIVE0_INT16      0x00010000  // Interrupt 16 active
-#define NVIC_ACTIVE0_INT15      0x00008000  // Interrupt 15 active
-#define NVIC_ACTIVE0_INT14      0x00004000  // Interrupt 14 active
-#define NVIC_ACTIVE0_INT13      0x00002000  // Interrupt 13 active
-#define NVIC_ACTIVE0_INT12      0x00001000  // Interrupt 12 active
-#define NVIC_ACTIVE0_INT11      0x00000800  // Interrupt 11 active
-#define NVIC_ACTIVE0_INT10      0x00000400  // Interrupt 10 active
-#define NVIC_ACTIVE0_INT9       0x00000200  // Interrupt 9 active
-#define NVIC_ACTIVE0_INT8       0x00000100  // Interrupt 8 active
-#define NVIC_ACTIVE0_INT7       0x00000080  // Interrupt 7 active
-#define NVIC_ACTIVE0_INT6       0x00000040  // Interrupt 6 active
-#define NVIC_ACTIVE0_INT5       0x00000020  // Interrupt 5 active
-#define NVIC_ACTIVE0_INT4       0x00000010  // Interrupt 4 active
-#define NVIC_ACTIVE0_INT3       0x00000008  // Interrupt 3 active
-#define NVIC_ACTIVE0_INT2       0x00000004  // Interrupt 2 active
-#define NVIC_ACTIVE0_INT1       0x00000002  // Interrupt 1 active
+#define NVIC_ACTIVE0_INT_M      0xFFFFFFFF  // Interrupt Active
 #define NVIC_ACTIVE0_INT0       0x00000001  // Interrupt 0 active
+#define NVIC_ACTIVE0_INT1       0x00000002  // Interrupt 1 active
+#define NVIC_ACTIVE0_INT2       0x00000004  // Interrupt 2 active
+#define NVIC_ACTIVE0_INT3       0x00000008  // Interrupt 3 active
+#define NVIC_ACTIVE0_INT4       0x00000010  // Interrupt 4 active
+#define NVIC_ACTIVE0_INT5       0x00000020  // Interrupt 5 active
+#define NVIC_ACTIVE0_INT6       0x00000040  // Interrupt 6 active
+#define NVIC_ACTIVE0_INT7       0x00000080  // Interrupt 7 active
+#define NVIC_ACTIVE0_INT8       0x00000100  // Interrupt 8 active
+#define NVIC_ACTIVE0_INT9       0x00000200  // Interrupt 9 active
+#define NVIC_ACTIVE0_INT10      0x00000400  // Interrupt 10 active
+#define NVIC_ACTIVE0_INT11      0x00000800  // Interrupt 11 active
+#define NVIC_ACTIVE0_INT12      0x00001000  // Interrupt 12 active
+#define NVIC_ACTIVE0_INT13      0x00002000  // Interrupt 13 active
+#define NVIC_ACTIVE0_INT14      0x00004000  // Interrupt 14 active
+#define NVIC_ACTIVE0_INT15      0x00008000  // Interrupt 15 active
+#define NVIC_ACTIVE0_INT16      0x00010000  // Interrupt 16 active
+#define NVIC_ACTIVE0_INT17      0x00020000  // Interrupt 17 active
+#define NVIC_ACTIVE0_INT18      0x00040000  // Interrupt 18 active
+#define NVIC_ACTIVE0_INT19      0x00080000  // Interrupt 19 active
+#define NVIC_ACTIVE0_INT20      0x00100000  // Interrupt 20 active
+#define NVIC_ACTIVE0_INT21      0x00200000  // Interrupt 21 active
+#define NVIC_ACTIVE0_INT22      0x00400000  // Interrupt 22 active
+#define NVIC_ACTIVE0_INT23      0x00800000  // Interrupt 23 active
+#define NVIC_ACTIVE0_INT24      0x01000000  // Interrupt 24 active
+#define NVIC_ACTIVE0_INT25      0x02000000  // Interrupt 25 active
+#define NVIC_ACTIVE0_INT26      0x04000000  // Interrupt 26 active
+#define NVIC_ACTIVE0_INT27      0x08000000  // Interrupt 27 active
+#define NVIC_ACTIVE0_INT28      0x10000000  // Interrupt 28 active
+#define NVIC_ACTIVE0_INT29      0x20000000  // Interrupt 29 active
+#define NVIC_ACTIVE0_INT30      0x40000000  // Interrupt 30 active
+#define NVIC_ACTIVE0_INT31      0x80000000  // Interrupt 31 active
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_ACTIVE1 register.
 //
 //*****************************************************************************
-#define NVIC_ACTIVE1_INT59      0x08000000  // Interrupt 59 active
-#define NVIC_ACTIVE1_INT58      0x04000000  // Interrupt 58 active
-#define NVIC_ACTIVE1_INT57      0x02000000  // Interrupt 57 active
-#define NVIC_ACTIVE1_INT56      0x01000000  // Interrupt 56 active
-#define NVIC_ACTIVE1_INT55      0x00800000  // Interrupt 55 active
-#define NVIC_ACTIVE1_INT54      0x00400000  // Interrupt 54 active
-#define NVIC_ACTIVE1_INT53      0x00200000  // Interrupt 53 active
-#define NVIC_ACTIVE1_INT52      0x00100000  // Interrupt 52 active
-#define NVIC_ACTIVE1_INT51      0x00080000  // Interrupt 51 active
-#define NVIC_ACTIVE1_INT50      0x00040000  // Interrupt 50 active
-#define NVIC_ACTIVE1_INT49      0x00020000  // Interrupt 49 active
-#define NVIC_ACTIVE1_INT48      0x00010000  // Interrupt 48 active
-#define NVIC_ACTIVE1_INT47      0x00008000  // Interrupt 47 active
-#define NVIC_ACTIVE1_INT46      0x00004000  // Interrupt 46 active
-#define NVIC_ACTIVE1_INT45      0x00002000  // Interrupt 45 active
-#define NVIC_ACTIVE1_INT44      0x00001000  // Interrupt 44 active
-#define NVIC_ACTIVE1_INT43      0x00000800  // Interrupt 43 active
-#define NVIC_ACTIVE1_INT42      0x00000400  // Interrupt 42 active
-#define NVIC_ACTIVE1_INT41      0x00000200  // Interrupt 41 active
-#define NVIC_ACTIVE1_INT40      0x00000100  // Interrupt 40 active
-#define NVIC_ACTIVE1_INT39      0x00000080  // Interrupt 39 active
-#define NVIC_ACTIVE1_INT38      0x00000040  // Interrupt 38 active
-#define NVIC_ACTIVE1_INT37      0x00000020  // Interrupt 37 active
-#define NVIC_ACTIVE1_INT36      0x00000010  // Interrupt 36 active
-#define NVIC_ACTIVE1_INT35      0x00000008  // Interrupt 35 active
-#define NVIC_ACTIVE1_INT34      0x00000004  // Interrupt 34 active
-#define NVIC_ACTIVE1_INT33      0x00000002  // Interrupt 33 active
+#define NVIC_ACTIVE1_INT_M      0x007FFFFF  // Interrupt Active
 #define NVIC_ACTIVE1_INT32      0x00000001  // Interrupt 32 active
+#define NVIC_ACTIVE1_INT33      0x00000002  // Interrupt 33 active
+#define NVIC_ACTIVE1_INT34      0x00000004  // Interrupt 34 active
+#define NVIC_ACTIVE1_INT35      0x00000008  // Interrupt 35 active
+#define NVIC_ACTIVE1_INT36      0x00000010  // Interrupt 36 active
+#define NVIC_ACTIVE1_INT37      0x00000020  // Interrupt 37 active
+#define NVIC_ACTIVE1_INT38      0x00000040  // Interrupt 38 active
+#define NVIC_ACTIVE1_INT39      0x00000080  // Interrupt 39 active
+#define NVIC_ACTIVE1_INT40      0x00000100  // Interrupt 40 active
+#define NVIC_ACTIVE1_INT41      0x00000200  // Interrupt 41 active
+#define NVIC_ACTIVE1_INT42      0x00000400  // Interrupt 42 active
+#define NVIC_ACTIVE1_INT43      0x00000800  // Interrupt 43 active
+#define NVIC_ACTIVE1_INT44      0x00001000  // Interrupt 44 active
+#define NVIC_ACTIVE1_INT45      0x00002000  // Interrupt 45 active
+#define NVIC_ACTIVE1_INT46      0x00004000  // Interrupt 46 active
+#define NVIC_ACTIVE1_INT47      0x00008000  // Interrupt 47 active
+#define NVIC_ACTIVE1_INT48      0x00010000  // Interrupt 48 active
+#define NVIC_ACTIVE1_INT49      0x00020000  // Interrupt 49 active
+#define NVIC_ACTIVE1_INT50      0x00040000  // Interrupt 50 active
+#define NVIC_ACTIVE1_INT51      0x00080000  // Interrupt 51 active
+#define NVIC_ACTIVE1_INT52      0x00100000  // Interrupt 52 active
+#define NVIC_ACTIVE1_INT53      0x00200000  // Interrupt 53 active
+#define NVIC_ACTIVE1_INT54      0x00400000  // Interrupt 54 active
+#define NVIC_ACTIVE1_INT55      0x00800000  // Interrupt 55 active
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_PRI0 register.
 //
 //*****************************************************************************
-#define NVIC_PRI0_INT3_M        0xFF000000  // Interrupt 3 priority mask
-#define NVIC_PRI0_INT2_M        0x00FF0000  // Interrupt 2 priority mask
-#define NVIC_PRI0_INT1_M        0x0000FF00  // Interrupt 1 priority mask
-#define NVIC_PRI0_INT0_M        0x000000FF  // Interrupt 0 priority mask
-#define NVIC_PRI0_INT3_S        24
-#define NVIC_PRI0_INT2_S        16
-#define NVIC_PRI0_INT1_S        8
-#define NVIC_PRI0_INT0_S        0
+#define NVIC_PRI0_INT3_M        0xE0000000  // Interrupt 3 Priority Mask
+#define NVIC_PRI0_INT2_M        0x00E00000  // Interrupt 2 Priority Mask
+#define NVIC_PRI0_INT1_M        0x0000E000  // Interrupt 1 Priority Mask
+#define NVIC_PRI0_INT0_M        0x000000E0  // Interrupt 0 Priority Mask
+#define NVIC_PRI0_INT3_S        29
+#define NVIC_PRI0_INT2_S        21
+#define NVIC_PRI0_INT1_S        13
+#define NVIC_PRI0_INT0_S        5
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_PRI1 register.
 //
 //*****************************************************************************
-#define NVIC_PRI1_INT7_M        0xFF000000  // Interrupt 7 priority mask
-#define NVIC_PRI1_INT6_M        0x00FF0000  // Interrupt 6 priority mask
-#define NVIC_PRI1_INT5_M        0x0000FF00  // Interrupt 5 priority mask
-#define NVIC_PRI1_INT4_M        0x000000FF  // Interrupt 4 priority mask
-#define NVIC_PRI1_INT7_S        24
-#define NVIC_PRI1_INT6_S        16
-#define NVIC_PRI1_INT5_S        8
-#define NVIC_PRI1_INT4_S        0
+#define NVIC_PRI1_INT7_M        0xE0000000  // Interrupt 7 Priority Mask
+#define NVIC_PRI1_INT6_M        0x00E00000  // Interrupt 6 Priority Mask
+#define NVIC_PRI1_INT5_M        0x0000E000  // Interrupt 5 Priority Mask
+#define NVIC_PRI1_INT4_M        0x000000E0  // Interrupt 4 Priority Mask
+#define NVIC_PRI1_INT7_S        29
+#define NVIC_PRI1_INT6_S        21
+#define NVIC_PRI1_INT5_S        13
+#define NVIC_PRI1_INT4_S        5
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_PRI2 register.
 //
 //*****************************************************************************
-#define NVIC_PRI2_INT11_M       0xFF000000  // Interrupt 11 priority mask
-#define NVIC_PRI2_INT10_M       0x00FF0000  // Interrupt 10 priority mask
-#define NVIC_PRI2_INT9_M        0x0000FF00  // Interrupt 9 priority mask
-#define NVIC_PRI2_INT8_M        0x000000FF  // Interrupt 8 priority mask
-#define NVIC_PRI2_INT11_S       24
-#define NVIC_PRI2_INT10_S       16
-#define NVIC_PRI2_INT9_S        8
-#define NVIC_PRI2_INT8_S        0
+#define NVIC_PRI2_INT11_M       0xE0000000  // Interrupt 11 Priority Mask
+#define NVIC_PRI2_INT10_M       0x00E00000  // Interrupt 10 Priority Mask
+#define NVIC_PRI2_INT9_M        0x0000E000  // Interrupt 9 Priority Mask
+#define NVIC_PRI2_INT8_M        0x000000E0  // Interrupt 8 Priority Mask
+#define NVIC_PRI2_INT11_S       29
+#define NVIC_PRI2_INT10_S       21
+#define NVIC_PRI2_INT9_S        13
+#define NVIC_PRI2_INT8_S        5
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_PRI3 register.
 //
 //*****************************************************************************
-#define NVIC_PRI3_INT15_M       0xFF000000  // Interrupt 15 priority mask
-#define NVIC_PRI3_INT14_M       0x00FF0000  // Interrupt 14 priority mask
-#define NVIC_PRI3_INT13_M       0x0000FF00  // Interrupt 13 priority mask
-#define NVIC_PRI3_INT12_M       0x000000FF  // Interrupt 12 priority mask
-#define NVIC_PRI3_INT15_S       24
-#define NVIC_PRI3_INT14_S       16
-#define NVIC_PRI3_INT13_S       8
-#define NVIC_PRI3_INT12_S       0
+#define NVIC_PRI3_INT15_M       0xE0000000  // Interrupt 15 Priority Mask
+#define NVIC_PRI3_INT14_M       0x00E00000  // Interrupt 14 Priority Mask
+#define NVIC_PRI3_INT13_M       0x0000E000  // Interrupt 13 Priority Mask
+#define NVIC_PRI3_INT12_M       0x000000E0  // Interrupt 12 Priority Mask
+#define NVIC_PRI3_INT15_S       29
+#define NVIC_PRI3_INT14_S       21
+#define NVIC_PRI3_INT13_S       13
+#define NVIC_PRI3_INT12_S       5
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_PRI4 register.
 //
 //*****************************************************************************
-#define NVIC_PRI4_INT19_M       0xFF000000  // Interrupt 19 priority mask
-#define NVIC_PRI4_INT18_M       0x00FF0000  // Interrupt 18 priority mask
-#define NVIC_PRI4_INT17_M       0x0000FF00  // Interrupt 17 priority mask
-#define NVIC_PRI4_INT16_M       0x000000FF  // Interrupt 16 priority mask
-#define NVIC_PRI4_INT19_S       24
-#define NVIC_PRI4_INT18_S       16
-#define NVIC_PRI4_INT17_S       8
-#define NVIC_PRI4_INT16_S       0
+#define NVIC_PRI4_INT19_M       0xE0000000  // Interrupt 19 Priority Mask
+#define NVIC_PRI4_INT18_M       0x00E00000  // Interrupt 18 Priority Mask
+#define NVIC_PRI4_INT17_M       0x0000E000  // Interrupt 17 Priority Mask
+#define NVIC_PRI4_INT16_M       0x000000E0  // Interrupt 16 Priority Mask
+#define NVIC_PRI4_INT19_S       29
+#define NVIC_PRI4_INT18_S       21
+#define NVIC_PRI4_INT17_S       13
+#define NVIC_PRI4_INT16_S       5
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_PRI5 register.
 //
 //*****************************************************************************
-#define NVIC_PRI5_INT23_M       0xFF000000  // Interrupt 23 priority mask
-#define NVIC_PRI5_INT22_M       0x00FF0000  // Interrupt 22 priority mask
-#define NVIC_PRI5_INT21_M       0x0000FF00  // Interrupt 21 priority mask
-#define NVIC_PRI5_INT20_M       0x000000FF  // Interrupt 20 priority mask
-#define NVIC_PRI5_INT23_S       24
-#define NVIC_PRI5_INT22_S       16
-#define NVIC_PRI5_INT21_S       8
-#define NVIC_PRI5_INT20_S       0
+#define NVIC_PRI5_INT23_M       0xE0000000  // Interrupt 23 Priority Mask
+#define NVIC_PRI5_INT22_M       0x00E00000  // Interrupt 22 Priority Mask
+#define NVIC_PRI5_INT21_M       0x0000E000  // Interrupt 21 Priority Mask
+#define NVIC_PRI5_INT20_M       0x000000E0  // Interrupt 20 Priority Mask
+#define NVIC_PRI5_INT23_S       29
+#define NVIC_PRI5_INT22_S       21
+#define NVIC_PRI5_INT21_S       13
+#define NVIC_PRI5_INT20_S       5
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_PRI6 register.
 //
 //*****************************************************************************
-#define NVIC_PRI6_INT27_M       0xFF000000  // Interrupt 27 priority mask
-#define NVIC_PRI6_INT26_M       0x00FF0000  // Interrupt 26 priority mask
-#define NVIC_PRI6_INT25_M       0x0000FF00  // Interrupt 25 priority mask
-#define NVIC_PRI6_INT24_M       0x000000FF  // Interrupt 24 priority mask
-#define NVIC_PRI6_INT27_S       24
-#define NVIC_PRI6_INT26_S       16
-#define NVIC_PRI6_INT25_S       8
-#define NVIC_PRI6_INT24_S       0
+#define NVIC_PRI6_INT27_M       0xE0000000  // Interrupt 27 Priority Mask
+#define NVIC_PRI6_INT26_M       0x00E00000  // Interrupt 26 Priority Mask
+#define NVIC_PRI6_INT25_M       0x0000E000  // Interrupt 25 Priority Mask
+#define NVIC_PRI6_INT24_M       0x000000E0  // Interrupt 24 Priority Mask
+#define NVIC_PRI6_INT27_S       29
+#define NVIC_PRI6_INT26_S       21
+#define NVIC_PRI6_INT25_S       13
+#define NVIC_PRI6_INT24_S       5
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_PRI7 register.
 //
 //*****************************************************************************
-#define NVIC_PRI7_INT31_M       0xFF000000  // Interrupt 31 priority mask
-#define NVIC_PRI7_INT30_M       0x00FF0000  // Interrupt 30 priority mask
-#define NVIC_PRI7_INT29_M       0x0000FF00  // Interrupt 29 priority mask
-#define NVIC_PRI7_INT28_M       0x000000FF  // Interrupt 28 priority mask
-#define NVIC_PRI7_INT31_S       24
-#define NVIC_PRI7_INT30_S       16
-#define NVIC_PRI7_INT29_S       8
-#define NVIC_PRI7_INT28_S       0
+#define NVIC_PRI7_INT31_M       0xE0000000  // Interrupt 31 Priority Mask
+#define NVIC_PRI7_INT30_M       0x00E00000  // Interrupt 30 Priority Mask
+#define NVIC_PRI7_INT29_M       0x0000E000  // Interrupt 29 Priority Mask
+#define NVIC_PRI7_INT28_M       0x000000E0  // Interrupt 28 Priority Mask
+#define NVIC_PRI7_INT31_S       29
+#define NVIC_PRI7_INT30_S       21
+#define NVIC_PRI7_INT29_S       13
+#define NVIC_PRI7_INT28_S       5
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_PRI8 register.
 //
 //*****************************************************************************
-#define NVIC_PRI8_INT35_M       0xFF000000  // Interrupt 35 priority mask
-#define NVIC_PRI8_INT34_M       0x00FF0000  // Interrupt 34 priority mask
-#define NVIC_PRI8_INT33_M       0x0000FF00  // Interrupt 33 priority mask
-#define NVIC_PRI8_INT32_M       0x000000FF  // Interrupt 32 priority mask
-#define NVIC_PRI8_INT35_S       24
-#define NVIC_PRI8_INT34_S       16
-#define NVIC_PRI8_INT33_S       8
-#define NVIC_PRI8_INT32_S       0
+#define NVIC_PRI8_INT35_M       0xE0000000  // Interrupt 35 Priority Mask
+#define NVIC_PRI8_INT34_M       0x00E00000  // Interrupt 34 Priority Mask
+#define NVIC_PRI8_INT33_M       0x0000E000  // Interrupt 33 Priority Mask
+#define NVIC_PRI8_INT32_M       0x000000E0  // Interrupt 32 Priority Mask
+#define NVIC_PRI8_INT35_S       29
+#define NVIC_PRI8_INT34_S       21
+#define NVIC_PRI8_INT33_S       13
+#define NVIC_PRI8_INT32_S       5
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_PRI9 register.
 //
 //*****************************************************************************
-#define NVIC_PRI9_INT39_M       0xFF000000  // Interrupt 39 priority mask
-#define NVIC_PRI9_INT38_M       0x00FF0000  // Interrupt 38 priority mask
-#define NVIC_PRI9_INT37_M       0x0000FF00  // Interrupt 37 priority mask
-#define NVIC_PRI9_INT36_M       0x000000FF  // Interrupt 36 priority mask
-#define NVIC_PRI9_INT39_S       24
-#define NVIC_PRI9_INT38_S       16
-#define NVIC_PRI9_INT37_S       8
-#define NVIC_PRI9_INT36_S       0
+#define NVIC_PRI9_INT39_M       0xE0000000  // Interrupt 39 Priority Mask
+#define NVIC_PRI9_INT38_M       0x00E00000  // Interrupt 38 Priority Mask
+#define NVIC_PRI9_INT37_M       0x0000E000  // Interrupt 37 Priority Mask
+#define NVIC_PRI9_INT36_M       0x000000E0  // Interrupt 36 Priority Mask
+#define NVIC_PRI9_INT39_S       29
+#define NVIC_PRI9_INT38_S       21
+#define NVIC_PRI9_INT37_S       13
+#define NVIC_PRI9_INT36_S       5
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_PRI10 register.
 //
 //*****************************************************************************
-#define NVIC_PRI10_INT43_M      0xFF000000  // Interrupt 43 priority mask
-#define NVIC_PRI10_INT42_M      0x00FF0000  // Interrupt 42 priority mask
-#define NVIC_PRI10_INT41_M      0x0000FF00  // Interrupt 41 priority mask
-#define NVIC_PRI10_INT40_M      0x000000FF  // Interrupt 40 priority mask
-#define NVIC_PRI10_INT43_S      24
-#define NVIC_PRI10_INT42_S      16
-#define NVIC_PRI10_INT41_S      8
-#define NVIC_PRI10_INT40_S      0
+#define NVIC_PRI10_INT43_M      0xE0000000  // Interrupt 43 Priority Mask
+#define NVIC_PRI10_INT42_M      0x00E00000  // Interrupt 42 Priority Mask
+#define NVIC_PRI10_INT41_M      0x0000E000  // Interrupt 41 Priority Mask
+#define NVIC_PRI10_INT40_M      0x000000E0  // Interrupt 40 Priority Mask
+#define NVIC_PRI10_INT43_S      29
+#define NVIC_PRI10_INT42_S      21
+#define NVIC_PRI10_INT41_S      13
+#define NVIC_PRI10_INT40_S      5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI11 register.
+//
+//*****************************************************************************
+#define NVIC_PRI11_INT47_M      0xE0000000  // Interrupt 47 Priority Mask
+#define NVIC_PRI11_INT46_M      0x00E00000  // Interrupt 46 Priority Mask
+#define NVIC_PRI11_INT45_M      0x0000E000  // Interrupt 45 Priority Mask
+#define NVIC_PRI11_INT44_M      0x000000E0  // Interrupt 44 Priority Mask
+#define NVIC_PRI11_INT47_S      29
+#define NVIC_PRI11_INT46_S      21
+#define NVIC_PRI11_INT45_S      13
+#define NVIC_PRI11_INT44_S      5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI12 register.
+//
+//*****************************************************************************
+#define NVIC_PRI12_INT51_M      0xE0000000  // Interrupt 51 Priority Mask
+#define NVIC_PRI12_INT50_M      0x00E00000  // Interrupt 50 Priority Mask
+#define NVIC_PRI12_INT49_M      0x0000E000  // Interrupt 49 Priority Mask
+#define NVIC_PRI12_INT48_M      0x000000E0  // Interrupt 48 Priority Mask
+#define NVIC_PRI12_INT51_S      29
+#define NVIC_PRI12_INT50_S      21
+#define NVIC_PRI12_INT49_S      13
+#define NVIC_PRI12_INT48_S      5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI13 register.
+//
+//*****************************************************************************
+#define NVIC_PRI13_INT55_M      0xE0000000  // Interrupt 55 Priority Mask
+#define NVIC_PRI13_INT54_M      0x00E00000  // Interrupt 54 Priority Mask
+#define NVIC_PRI13_INT53_M      0x0000E000  // Interrupt 53 Priority Mask
+#define NVIC_PRI13_INT52_M      0x000000E0  // Interrupt 52 Priority Mask
+#define NVIC_PRI13_INT55_S      29
+#define NVIC_PRI13_INT54_S      21
+#define NVIC_PRI13_INT53_S      13
+#define NVIC_PRI13_INT52_S      5
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_CPUID register.
 //
 //*****************************************************************************
-#define NVIC_CPUID_IMP_M        0xFF000000  // Implementer
-#define NVIC_CPUID_VAR_M        0x00F00000  // Variant
-#define NVIC_CPUID_PARTNO_M     0x0000FFF0  // Processor part number
-#define NVIC_CPUID_REV_M        0x0000000F  // Revision
+#define NVIC_CPUID_IMP_M        0xFF000000  // Implementer Code
+#define NVIC_CPUID_IMP_ARM      0x41000000  // ARM
+#define NVIC_CPUID_VAR_M        0x00F00000  // Variant Number
+#define NVIC_CPUID_CON_M        0x000F0000  // Constant
+#define NVIC_CPUID_PARTNO_M     0x0000FFF0  // Part Number
+#define NVIC_CPUID_PARTNO_CM3   0x0000C230  // Cortex-M3 processor
+#define NVIC_CPUID_REV_M        0x0000000F  // Revision Number
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_INT_CTRL register.
 //
 //*****************************************************************************
-#define NVIC_INT_CTRL_NMI_SET   0x80000000  // Pend a NMI
-#define NVIC_INT_CTRL_PEND_SV   0x10000000  // Pend a PendSV
-#define NVIC_INT_CTRL_UNPEND_SV 0x08000000  // Unpend a PendSV
-#define NVIC_INT_CTRL_ISR_PRE   0x00800000  // Debug interrupt handling
-#define NVIC_INT_CTRL_ISR_PEND  0x00400000  // Debug interrupt pending
-#define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000  // Highest pending exception
-#define NVIC_INT_CTRL_RET_BASE  0x00000800  // Return to base
-#define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF  // Current active exception
-#define NVIC_INT_CTRL_VEC_PEN_S 12
+#define NVIC_INT_CTRL_NMI_SET   0x80000000  // NMI Set Pending
+#define NVIC_INT_CTRL_PEND_SV   0x10000000  // PendSV Set Pending
+#define NVIC_INT_CTRL_UNPEND_SV 0x08000000  // PendSV Clear Pending
+#define NVIC_INT_CTRL_PENDSTSET 0x04000000  // SysTick Set Pending
+#define NVIC_INT_CTRL_PENDSTCLR 0x02000000  // SysTick Clear Pending
+#define NVIC_INT_CTRL_ISR_PRE   0x00800000  // Debug Interrupt Handling
+#define NVIC_INT_CTRL_ISR_PEND  0x00400000  // Interrupt Pending
+#define NVIC_INT_CTRL_VEC_PEN_M 0x0007F000  // Interrupt Pending Vector Number
+#define NVIC_INT_CTRL_VEC_PEN_NMI \
+                                0x00002000  // NMI
+#define NVIC_INT_CTRL_VEC_PEN_HARD \
+                                0x00003000  // Hard fault
+#define NVIC_INT_CTRL_VEC_PEN_MEM \
+                                0x00004000  // Memory management fault
+#define NVIC_INT_CTRL_VEC_PEN_BUS \
+                                0x00005000  // Bus fault
+#define NVIC_INT_CTRL_VEC_PEN_USG \
+                                0x00006000  // Usage fault
+#define NVIC_INT_CTRL_VEC_PEN_SVC \
+                                0x0000B000  // SVCall
+#define NVIC_INT_CTRL_VEC_PEN_PNDSV \
+                                0x0000E000  // PendSV
+#define NVIC_INT_CTRL_VEC_PEN_TICK \
+                                0x0000F000  // SysTick
+#define NVIC_INT_CTRL_RET_BASE  0x00000800  // Return to Base
+#define NVIC_INT_CTRL_VEC_ACT_M 0x0000007F  // Interrupt Pending Vector Number
 #define NVIC_INT_CTRL_VEC_ACT_S 0
 
 //*****************************************************************************
@@ -11487,86 +12024,85 @@
 // The following are defines for the bit fields in the NVIC_VTABLE register.
 //
 //*****************************************************************************
-#define NVIC_VTABLE_BASE        0x20000000  // Vector table base
-#define NVIC_VTABLE_OFFSET_M    0x1FFFFF00  // Vector table offset
-#define NVIC_VTABLE_OFFSET_S    8
+#define NVIC_VTABLE_BASE        0x20000000  // Vector Table Base
+#define NVIC_VTABLE_OFFSET_M    0x1FFFFE00  // Vector Table Offset
+#define NVIC_VTABLE_OFFSET_S    9
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_APINT register.
 //
 //*****************************************************************************
-#define NVIC_APINT_VECTKEY_M    0xFFFF0000  // Vector key mask
+#define NVIC_APINT_VECTKEY_M    0xFFFF0000  // Register Key
 #define NVIC_APINT_VECTKEY      0x05FA0000  // Vector key
-#define NVIC_APINT_ENDIANESS    0x00008000  // Data endianess
-#define NVIC_APINT_PRIGROUP_M   0x00000700  // Priority group
-#define NVIC_APINT_PRIGROUP_0_8 0x00000700  // Priority group 0.8 split
-#define NVIC_APINT_PRIGROUP_1_7 0x00000600  // Priority group 1.7 split
-#define NVIC_APINT_PRIGROUP_2_6 0x00000500  // Priority group 2.6 split
-#define NVIC_APINT_PRIGROUP_3_5 0x00000400  // Priority group 3.5 split
-#define NVIC_APINT_PRIGROUP_4_4 0x00000300  // Priority group 4.4 split
-#define NVIC_APINT_PRIGROUP_5_3 0x00000200  // Priority group 5.3 split
-#define NVIC_APINT_PRIGROUP_6_2 0x00000100  // Priority group 6.2 split
-#define NVIC_APINT_SYSRESETREQ  0x00000004  // System reset request
-#define NVIC_APINT_VECT_CLR_ACT 0x00000002  // Clear active NMI/fault info
-#define NVIC_APINT_VECT_RESET   0x00000001  // System reset
+#define NVIC_APINT_ENDIANESS    0x00008000  // Data Endianess
+#define NVIC_APINT_PRIGROUP_M   0x00000700  // Interrupt Priority Grouping
 #define NVIC_APINT_PRIGROUP_7_1 0x00000000  // Priority group 7.1 split
+#define NVIC_APINT_PRIGROUP_6_2 0x00000100  // Priority group 6.2 split
+#define NVIC_APINT_PRIGROUP_5_3 0x00000200  // Priority group 5.3 split
+#define NVIC_APINT_PRIGROUP_4_4 0x00000300  // Priority group 4.4 split
+#define NVIC_APINT_PRIGROUP_3_5 0x00000400  // Priority group 3.5 split
+#define NVIC_APINT_PRIGROUP_2_6 0x00000500  // Priority group 2.6 split
+#define NVIC_APINT_PRIGROUP_1_7 0x00000600  // Priority group 1.7 split
+#define NVIC_APINT_PRIGROUP_0_8 0x00000700  // Priority group 0.8 split
+#define NVIC_APINT_SYSRESETREQ  0x00000004  // System Reset Request
+#define NVIC_APINT_VECT_CLR_ACT 0x00000002  // Clear Active NMI / Fault
+#define NVIC_APINT_VECT_RESET   0x00000001  // System Reset
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_SYS_CTRL register.
 //
 //*****************************************************************************
-#define NVIC_SYS_CTRL_SEVONPEND 0x00000010  // Wakeup on pend
-#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004  // Deep sleep enable
-#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002  // Sleep on ISR exit
+#define NVIC_SYS_CTRL_SEVONPEND 0x00000010  // Wake Up on Pending
+#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004  // Deep Sleep Enable
+#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002  // Sleep on ISR Exit
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_CFG_CTRL register.
 //
 //*****************************************************************************
-#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100  // Ignore bus fault in NMI/fault
-#define NVIC_CFG_CTRL_DIV0      0x00000010  // Trap on divide by 0
-#define NVIC_CFG_CTRL_UNALIGNED 0x00000008  // Trap on unaligned access
-#define NVIC_CFG_CTRL_DEEP_PEND 0x00000004  // Allow deep interrupt trigger
-#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002  // Allow main interrupt trigger
-#define NVIC_CFG_CTRL_BASE_THR  0x00000001  // Thread state control
+#define NVIC_CFG_CTRL_STKALIGN  0x00000200  // Stack Alignment on Exception
+                                            // Entry
+#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100  // Ignore Bus Fault in NMI and
+                                            // Fault
+#define NVIC_CFG_CTRL_DIV0      0x00000010  // Trap on Divide by 0
+#define NVIC_CFG_CTRL_UNALIGNED 0x00000008  // Trap on Unaligned Access
+#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002  // Allow Main Interrupt Trigger
+#define NVIC_CFG_CTRL_BASE_THR  0x00000001  // Thread State Control
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_SYS_PRI1 register.
 //
 //*****************************************************************************
-#define NVIC_SYS_PRI1_RES_M     0xFF000000  // Priority of reserved handler
-#define NVIC_SYS_PRI1_USAGE_M   0x00FF0000  // Priority of usage fault handler
-#define NVIC_SYS_PRI1_BUS_M     0x0000FF00  // Priority of bus fault handler
-#define NVIC_SYS_PRI1_MEM_M     0x000000FF  // Priority of mem manage handler
-#define NVIC_SYS_PRI1_USAGE_S   16
-#define NVIC_SYS_PRI1_BUS_S     8
-#define NVIC_SYS_PRI1_MEM_S     0
+#define NVIC_SYS_PRI1_USAGE_M   0x00E00000  // Usage Fault Priority
+#define NVIC_SYS_PRI1_BUS_M     0x0000E000  // Bus Fault Priority
+#define NVIC_SYS_PRI1_MEM_M     0x000000E0  // Memory Management Fault Priority
+#define NVIC_SYS_PRI1_USAGE_S   21
+#define NVIC_SYS_PRI1_BUS_S     13
+#define NVIC_SYS_PRI1_MEM_S     5
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_SYS_PRI2 register.
 //
 //*****************************************************************************
-#define NVIC_SYS_PRI2_SVC_M     0xFF000000  // Priority of SVCall handler
-#define NVIC_SYS_PRI2_RES_M     0x00FFFFFF  // Priority of reserved handlers
-#define NVIC_SYS_PRI2_SVC_S     24
+#define NVIC_SYS_PRI2_SVC_M     0xE0000000  // SVCall Priority
+#define NVIC_SYS_PRI2_SVC_S     29
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the NVIC_SYS_PRI3 register.
 //
 //*****************************************************************************
-#define NVIC_SYS_PRI3_TICK_M    0xFF000000  // Priority of Sys Tick handler
-#define NVIC_SYS_PRI3_PENDSV_M  0x00FF0000  // Priority of PendSV handler
-#define NVIC_SYS_PRI3_RES_M     0x0000FF00  // Priority of reserved handler
-#define NVIC_SYS_PRI3_DEBUG_M   0x000000FF  // Priority of debug handler
-#define NVIC_SYS_PRI3_TICK_S    24
-#define NVIC_SYS_PRI3_PENDSV_S  16
-#define NVIC_SYS_PRI3_DEBUG_S   0
+#define NVIC_SYS_PRI3_TICK_M    0xE0000000  // SysTick Exception Priority
+#define NVIC_SYS_PRI3_PENDSV_M  0x00E00000  // PendSV Priority
+#define NVIC_SYS_PRI3_DEBUG_M   0x000000E0  // Debug Priority
+#define NVIC_SYS_PRI3_TICK_S    29
+#define NVIC_SYS_PRI3_PENDSV_S  21
+#define NVIC_SYS_PRI3_DEBUG_S   5
 
 //*****************************************************************************
 //
@@ -11574,18 +12110,21 @@
 // register.
 //
 //*****************************************************************************
-#define NVIC_SYS_HND_CTRL_USAGE 0x00040000  // Usage fault enable
-#define NVIC_SYS_HND_CTRL_BUS   0x00020000  // Bus fault enable
-#define NVIC_SYS_HND_CTRL_MEM   0x00010000  // Mem manage fault enable
-#define NVIC_SYS_HND_CTRL_SVC   0x00008000  // SVCall is pended
-#define NVIC_SYS_HND_CTRL_BUSP  0x00004000  // Bus fault is pended
-#define NVIC_SYS_HND_CTRL_TICK  0x00000800  // Sys tick is active
-#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400  // PendSV is active
-#define NVIC_SYS_HND_CTRL_MON   0x00000100  // Monitor is active
-#define NVIC_SYS_HND_CTRL_SVCA  0x00000080  // SVCall is active
-#define NVIC_SYS_HND_CTRL_USGA  0x00000008  // Usage fault is active
-#define NVIC_SYS_HND_CTRL_BUSA  0x00000002  // Bus fault is active
-#define NVIC_SYS_HND_CTRL_MEMA  0x00000001  // Mem manage is active
+#define NVIC_SYS_HND_CTRL_USAGE 0x00040000  // Usage Fault Enable
+#define NVIC_SYS_HND_CTRL_BUS   0x00020000  // Bus Fault Enable
+#define NVIC_SYS_HND_CTRL_MEM   0x00010000  // Memory Management Fault Enable
+#define NVIC_SYS_HND_CTRL_SVC   0x00008000  // SVC Call Pending
+#define NVIC_SYS_HND_CTRL_BUSP  0x00004000  // Bus Fault Pending
+#define NVIC_SYS_HND_CTRL_MEMP  0x00002000  // Memory Management Fault Pending
+#define NVIC_SYS_HND_CTRL_USAGEP \
+                                0x00001000  // Usage Fault Pending
+#define NVIC_SYS_HND_CTRL_TICK  0x00000800  // SysTick Exception Active
+#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400  // PendSV Exception Active
+#define NVIC_SYS_HND_CTRL_MON   0x00000100  // Debug Monitor Active
+#define NVIC_SYS_HND_CTRL_SVCA  0x00000080  // SVC Call Active
+#define NVIC_SYS_HND_CTRL_USGA  0x00000008  // Usage Fault Active
+#define NVIC_SYS_HND_CTRL_BUSA  0x00000002  // Bus Fault Active
+#define NVIC_SYS_HND_CTRL_MEMA  0x00000001  // Memory Management Fault Active
 
 //*****************************************************************************
 //
@@ -11593,23 +12132,25 @@
 // register.
 //
 //*****************************************************************************
-#define NVIC_FAULT_STAT_DIV0    0x02000000  // Divide by zero fault
-#define NVIC_FAULT_STAT_UNALIGN 0x01000000  // Unaligned access fault
-#define NVIC_FAULT_STAT_NOCP    0x00080000  // No coprocessor fault
-#define NVIC_FAULT_STAT_INVPC   0x00040000  // Invalid PC fault
-#define NVIC_FAULT_STAT_INVSTAT 0x00020000  // Invalid state fault
-#define NVIC_FAULT_STAT_UNDEF   0x00010000  // Undefined instruction fault
-#define NVIC_FAULT_STAT_BFARV   0x00008000  // BFAR is valid
-#define NVIC_FAULT_STAT_BSTKE   0x00001000  // Stack bus fault
-#define NVIC_FAULT_STAT_BUSTKE  0x00000800  // Unstack bus fault
-#define NVIC_FAULT_STAT_IMPRE   0x00000400  // Imprecise data bus error
-#define NVIC_FAULT_STAT_PRECISE 0x00000200  // Precise data bus error
-#define NVIC_FAULT_STAT_IBUS    0x00000100  // Instruction bus fault
-#define NVIC_FAULT_STAT_MMARV   0x00000080  // MMAR is valid
-#define NVIC_FAULT_STAT_MSTKE   0x00000010  // Stack access violation
-#define NVIC_FAULT_STAT_MUSTKE  0x00000008  // Unstack access violation
-#define NVIC_FAULT_STAT_DERR    0x00000002  // Data access violation
-#define NVIC_FAULT_STAT_IERR    0x00000001  // Instruction access violation
+#define NVIC_FAULT_STAT_DIV0    0x02000000  // Divide-by-Zero Usage Fault
+#define NVIC_FAULT_STAT_UNALIGN 0x01000000  // Unaligned Access Usage Fault
+#define NVIC_FAULT_STAT_NOCP    0x00080000  // No Coprocessor Usage Fault
+#define NVIC_FAULT_STAT_INVPC   0x00040000  // Invalid PC Load Usage Fault
+#define NVIC_FAULT_STAT_INVSTAT 0x00020000  // Invalid State Usage Fault
+#define NVIC_FAULT_STAT_UNDEF   0x00010000  // Undefined Instruction Usage
+                                            // Fault
+#define NVIC_FAULT_STAT_BFARV   0x00008000  // Bus Fault Address Register Valid
+#define NVIC_FAULT_STAT_BSTKE   0x00001000  // Stack Bus Fault
+#define NVIC_FAULT_STAT_BUSTKE  0x00000800  // Unstack Bus Fault
+#define NVIC_FAULT_STAT_IMPRE   0x00000400  // Imprecise Data Bus Error
+#define NVIC_FAULT_STAT_PRECISE 0x00000200  // Precise Data Bus Error
+#define NVIC_FAULT_STAT_IBUS    0x00000100  // Instruction Bus Error
+#define NVIC_FAULT_STAT_MMARV   0x00000080  // Memory Management Fault Address
+                                            // Register Valid
+#define NVIC_FAULT_STAT_MSTKE   0x00000010  // Stack Access Violation
+#define NVIC_FAULT_STAT_MUSTKE  0x00000008  // Unstack Access Violation
+#define NVIC_FAULT_STAT_DERR    0x00000002  // Data Access Violation
+#define NVIC_FAULT_STAT_IERR    0x00000001  // Instruction Access Violation
 
 //*****************************************************************************
 //
@@ -11617,9 +12158,9 @@
 // register.
 //
 //*****************************************************************************
-#define NVIC_HFAULT_STAT_DBG    0x80000000  // Debug event
-#define NVIC_HFAULT_STAT_FORCED 0x40000000  // Cannot execute fault handler
-#define NVIC_HFAULT_STAT_VECT   0x00000002  // Vector table read fault
+#define NVIC_HFAULT_STAT_DBG    0x80000000  // Debug Event
+#define NVIC_HFAULT_STAT_FORCED 0x40000000  // Forced Hard Fault
+#define NVIC_HFAULT_STAT_VECT   0x00000002  // Vector Table Read Fault
 
 //*****************************************************************************
 //
@@ -11638,7 +12179,7 @@
 // The following are defines for the bit fields in the NVIC_MM_ADDR register.
 //
 //*****************************************************************************
-#define NVIC_MM_ADDR_M          0xFFFFFFFF  // Data fault address
+#define NVIC_MM_ADDR_M          0xFFFFFFFF  // Fault Address
 #define NVIC_MM_ADDR_S          0
 
 //*****************************************************************************
@@ -11647,7 +12188,7 @@
 // register.
 //
 //*****************************************************************************
-#define NVIC_FAULT_ADDR_M       0xFFFFFFFF  // Data bus fault address
+#define NVIC_FAULT_ADDR_M       0xFFFFFFFF  // Fault Address
 #define NVIC_FAULT_ADDR_S       0
 
 //*****************************************************************************
@@ -11655,9 +12196,9 @@
 // The following are defines for the bit fields in the NVIC_MPU_TYPE register.
 //
 //*****************************************************************************
-#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000  // Number of I regions
-#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00  // Number of D regions
-#define NVIC_MPU_TYPE_SEPARATE  0x00000001  // Separate or unified MPU
+#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000  // Number of I Regions
+#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00  // Number of D Regions
+#define NVIC_MPU_TYPE_SEPARATE  0x00000001  // Separate or Unified MPU
 #define NVIC_MPU_TYPE_IREGION_S 16
 #define NVIC_MPU_TYPE_DREGION_S 8
 
@@ -11666,9 +12207,9 @@
 // The following are defines for the bit fields in the NVIC_MPU_CTRL register.
 //
 //*****************************************************************************
-#define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004  // MPU default region in priv mode
-#define NVIC_MPU_CTRL_HFNMIENA  0x00000002  // MPU enabled during faults
-#define NVIC_MPU_CTRL_ENABLE    0x00000001  // MPU enable
+#define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004  // MPU Default Region
+#define NVIC_MPU_CTRL_HFNMIENA  0x00000002  // MPU Enabled During Faults
+#define NVIC_MPU_CTRL_ENABLE    0x00000001  // MPU Enable
 
 //*****************************************************************************
 //
@@ -11676,7 +12217,7 @@
 // register.
 //
 //*****************************************************************************
-#define NVIC_MPU_NUMBER_M       0x000000FF  // MPU region to access
+#define NVIC_MPU_NUMBER_M       0x00000007  // MPU Region to Access
 #define NVIC_MPU_NUMBER_S       0
 
 //*****************************************************************************
@@ -11684,10 +12225,10 @@
 // The following are defines for the bit fields in the NVIC_MPU_BASE register.
 //
 //*****************************************************************************
-#define NVIC_MPU_BASE_ADDR_M    0xFFFFFFE0  // Base address mask
-#define NVIC_MPU_BASE_VALID     0x00000010  // Region number valid
-#define NVIC_MPU_BASE_REGION_M  0x0000000F  // Region number
-#define NVIC_MPU_BASE_ADDR_S    8
+#define NVIC_MPU_BASE_ADDR_M    0xFFFFFFE0  // Base Address Mask
+#define NVIC_MPU_BASE_VALID     0x00000010  // Region Number Valid
+#define NVIC_MPU_BASE_REGION_M  0x00000007  // Region Number
+#define NVIC_MPU_BASE_ADDR_S    5
 #define NVIC_MPU_BASE_REGION_S  0
 
 //*****************************************************************************
@@ -11696,19 +12237,19 @@
 //
 //*****************************************************************************
 #define NVIC_MPU_ATTR_M         0xFFFF0000  // Attributes
+#define NVIC_MPU_ATTR_XN        0x10000000  // Instruction Access Disable
+#define NVIC_MPU_ATTR_AP_M      0x07000000  // Access Privilege
 #define NVIC_MPU_ATTR_AP_NO_NO  0x00000000  // prv: no access, usr: no access
-#define NVIC_MPU_ATTR_BUFFRABLE 0x00010000  // Bufferable
-#define NVIC_MPU_ATTR_CACHEABLE 0x00020000  // Cacheable
-#define NVIC_MPU_ATTR_SHAREABLE 0x00040000  // Shareable
-#define NVIC_MPU_ATTR_TEX_M     0x00380000  // Type extension mask
 #define NVIC_MPU_ATTR_AP_RW_NO  0x01000000  // prv: rw, usr: none
 #define NVIC_MPU_ATTR_AP_RW_RO  0x02000000  // prv: rw, usr: read-only
 #define NVIC_MPU_ATTR_AP_RW_RW  0x03000000  // prv: rw, usr: rw
 #define NVIC_MPU_ATTR_AP_RO_NO  0x05000000  // prv: ro, usr: none
 #define NVIC_MPU_ATTR_AP_RO_RO  0x06000000  // prv: ro, usr: ro
-#define NVIC_MPU_ATTR_AP_M      0x07000000  // Access permissions mask
-#define NVIC_MPU_ATTR_XN        0x10000000  // Execute disable
-#define NVIC_MPU_ATTR_SRD_M     0x0000FF00  // Sub-region disable mask
+#define NVIC_MPU_ATTR_TEX_M     0x00380000  // Type Extension Mask
+#define NVIC_MPU_ATTR_SHAREABLE 0x00040000  // Shareable
+#define NVIC_MPU_ATTR_CACHEABLE 0x00020000  // Cacheable
+#define NVIC_MPU_ATTR_BUFFRABLE 0x00010000  // Bufferable
+#define NVIC_MPU_ATTR_SRD_M     0x0000FF00  // Subregion Disable Bits
 #define NVIC_MPU_ATTR_SRD_0     0x00000100  // Sub-region 0 disable
 #define NVIC_MPU_ATTR_SRD_1     0x00000200  // Sub-region 1 disable
 #define NVIC_MPU_ATTR_SRD_2     0x00000400  // Sub-region 2 disable
@@ -11717,7 +12258,7 @@
 #define NVIC_MPU_ATTR_SRD_5     0x00002000  // Sub-region 5 disable
 #define NVIC_MPU_ATTR_SRD_6     0x00004000  // Sub-region 6 disable
 #define NVIC_MPU_ATTR_SRD_7     0x00008000  // Sub-region 7 disable
-#define NVIC_MPU_ATTR_SIZE_M    0x0000003E  // Region size mask
+#define NVIC_MPU_ATTR_SIZE_M    0x0000003E  // Region Size Mask
 #define NVIC_MPU_ATTR_SIZE_32B  0x00000008  // Region size 32 bytes
 #define NVIC_MPU_ATTR_SIZE_64B  0x0000000A  // Region size 64 bytes
 #define NVIC_MPU_ATTR_SIZE_128B 0x0000000C  // Region size 128 bytes
@@ -11746,7 +12287,94 @@
 #define NVIC_MPU_ATTR_SIZE_1G   0x0000003A  // Region size 1 Gbytes
 #define NVIC_MPU_ATTR_SIZE_2G   0x0000003C  // Region size 2 Gbytes
 #define NVIC_MPU_ATTR_SIZE_4G   0x0000003E  // Region size 4 Gbytes
-#define NVIC_MPU_ATTR_ENABLE    0x00000001  // Region enable
+#define NVIC_MPU_ATTR_ENABLE    0x00000001  // Region Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE1 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE1_ADDR_M   0xFFFFFFE0  // Base Address Mask
+#define NVIC_MPU_BASE1_VALID    0x00000010  // Region Number Valid
+#define NVIC_MPU_BASE1_REGION_M 0x00000007  // Region Number
+#define NVIC_MPU_BASE1_ADDR_S   5
+#define NVIC_MPU_BASE1_REGION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR1 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR1_XN       0x10000000  // Instruction Access Disable
+#define NVIC_MPU_ATTR1_AP_M     0x07000000  // Access Privilege
+#define NVIC_MPU_ATTR1_TEX_M    0x00380000  // Type Extension Mask
+#define NVIC_MPU_ATTR1_SHAREABLE \
+                                0x00040000  // Shareable
+#define NVIC_MPU_ATTR1_CACHEABLE \
+                                0x00020000  // Cacheable
+#define NVIC_MPU_ATTR1_BUFFRABLE \
+                                0x00010000  // Bufferable
+#define NVIC_MPU_ATTR1_SRD_M    0x0000FF00  // Subregion Disable Bits
+#define NVIC_MPU_ATTR1_SIZE_M   0x0000003E  // Region Size Mask
+#define NVIC_MPU_ATTR1_ENABLE   0x00000001  // Region Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE2 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE2_ADDR_M   0xFFFFFFE0  // Base Address Mask
+#define NVIC_MPU_BASE2_VALID    0x00000010  // Region Number Valid
+#define NVIC_MPU_BASE2_REGION_M 0x00000007  // Region Number
+#define NVIC_MPU_BASE2_ADDR_S   5
+#define NVIC_MPU_BASE2_REGION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR2 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR2_XN       0x10000000  // Instruction Access Disable
+#define NVIC_MPU_ATTR2_AP_M     0x07000000  // Access Privilege
+#define NVIC_MPU_ATTR2_TEX_M    0x00380000  // Type Extension Mask
+#define NVIC_MPU_ATTR2_SHAREABLE \
+                                0x00040000  // Shareable
+#define NVIC_MPU_ATTR2_CACHEABLE \
+                                0x00020000  // Cacheable
+#define NVIC_MPU_ATTR2_BUFFRABLE \
+                                0x00010000  // Bufferable
+#define NVIC_MPU_ATTR2_SRD_M    0x0000FF00  // Subregion Disable Bits
+#define NVIC_MPU_ATTR2_SIZE_M   0x0000003E  // Region Size Mask
+#define NVIC_MPU_ATTR2_ENABLE   0x00000001  // Region Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE3 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE3_ADDR_M   0xFFFFFFE0  // Base Address Mask
+#define NVIC_MPU_BASE3_VALID    0x00000010  // Region Number Valid
+#define NVIC_MPU_BASE3_REGION_M 0x00000007  // Region Number
+#define NVIC_MPU_BASE3_ADDR_S   5
+#define NVIC_MPU_BASE3_REGION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR3 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR3_XN       0x10000000  // Instruction Access Disable
+#define NVIC_MPU_ATTR3_AP_M     0x07000000  // Access Privilege
+#define NVIC_MPU_ATTR3_TEX_M    0x00380000  // Type Extension Mask
+#define NVIC_MPU_ATTR3_SHAREABLE \
+                                0x00040000  // Shareable
+#define NVIC_MPU_ATTR3_CACHEABLE \
+                                0x00020000  // Cacheable
+#define NVIC_MPU_ATTR3_BUFFRABLE \
+                                0x00010000  // Bufferable
+#define NVIC_MPU_ATTR3_SRD_M    0x0000FF00  // Subregion Disable Bits
+#define NVIC_MPU_ATTR3_SIZE_M   0x0000003E  // Region Size Mask
+#define NVIC_MPU_ATTR3_ENABLE   0x00000001  // Region Enable
 
 //*****************************************************************************
 //
@@ -11778,27 +12406,27 @@
 //*****************************************************************************
 #define NVIC_DBG_XFER_REG_WNR   0x00010000  // Write or not read
 #define NVIC_DBG_XFER_REG_SEL_M 0x0000001F  // Register
-#define NVIC_DBG_XFER_REG_CFBP  0x00000014  // Control/Fault/BasePri/PriMask
-#define NVIC_DBG_XFER_REG_DSP   0x00000013  // Deep SP
-#define NVIC_DBG_XFER_REG_PSP   0x00000012  // Process SP
-#define NVIC_DBG_XFER_REG_MSP   0x00000011  // Main SP
-#define NVIC_DBG_XFER_REG_FLAGS 0x00000010  // xPSR/Flags register
-#define NVIC_DBG_XFER_REG_R15   0x0000000F  // Register R15
-#define NVIC_DBG_XFER_REG_R14   0x0000000E  // Register R14
-#define NVIC_DBG_XFER_REG_R13   0x0000000D  // Register R13
-#define NVIC_DBG_XFER_REG_R12   0x0000000C  // Register R12
-#define NVIC_DBG_XFER_REG_R11   0x0000000B  // Register R11
-#define NVIC_DBG_XFER_REG_R10   0x0000000A  // Register R10
-#define NVIC_DBG_XFER_REG_R9    0x00000009  // Register R9
-#define NVIC_DBG_XFER_REG_R8    0x00000008  // Register R8
-#define NVIC_DBG_XFER_REG_R7    0x00000007  // Register R7
-#define NVIC_DBG_XFER_REG_R6    0x00000006  // Register R6
-#define NVIC_DBG_XFER_REG_R5    0x00000005  // Register R5
-#define NVIC_DBG_XFER_REG_R4    0x00000004  // Register R4
-#define NVIC_DBG_XFER_REG_R3    0x00000003  // Register R3
-#define NVIC_DBG_XFER_REG_R2    0x00000002  // Register R2
-#define NVIC_DBG_XFER_REG_R1    0x00000001  // Register R1
 #define NVIC_DBG_XFER_REG_R0    0x00000000  // Register R0
+#define NVIC_DBG_XFER_REG_R1    0x00000001  // Register R1
+#define NVIC_DBG_XFER_REG_R2    0x00000002  // Register R2
+#define NVIC_DBG_XFER_REG_R3    0x00000003  // Register R3
+#define NVIC_DBG_XFER_REG_R4    0x00000004  // Register R4
+#define NVIC_DBG_XFER_REG_R5    0x00000005  // Register R5
+#define NVIC_DBG_XFER_REG_R6    0x00000006  // Register R6
+#define NVIC_DBG_XFER_REG_R7    0x00000007  // Register R7
+#define NVIC_DBG_XFER_REG_R8    0x00000008  // Register R8
+#define NVIC_DBG_XFER_REG_R9    0x00000009  // Register R9
+#define NVIC_DBG_XFER_REG_R10   0x0000000A  // Register R10
+#define NVIC_DBG_XFER_REG_R11   0x0000000B  // Register R11
+#define NVIC_DBG_XFER_REG_R12   0x0000000C  // Register R12
+#define NVIC_DBG_XFER_REG_R13   0x0000000D  // Register R13
+#define NVIC_DBG_XFER_REG_R14   0x0000000E  // Register R14
+#define NVIC_DBG_XFER_REG_R15   0x0000000F  // Register R15
+#define NVIC_DBG_XFER_REG_FLAGS 0x00000010  // xPSR/Flags register
+#define NVIC_DBG_XFER_REG_MSP   0x00000011  // Main SP
+#define NVIC_DBG_XFER_REG_PSP   0x00000012  // Process SP
+#define NVIC_DBG_XFER_REG_DSP   0x00000013  // Deep SP
+#define NVIC_DBG_XFER_REG_CFBP  0x00000014  // Control/Fault/BasePri/PriMask
 
 //*****************************************************************************
 //
@@ -11830,7 +12458,109 @@
 // The following are defines for the bit fields in the NVIC_SW_TRIG register.
 //
 //*****************************************************************************
-#define NVIC_SW_TRIG_INTID_M    0x000003FF  // Interrupt to trigger
+#define NVIC_SW_TRIG_INTID_M    0x0000003F  // Interrupt ID
 #define NVIC_SW_TRIG_INTID_S    0
 
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// Deprecated defines for the bit fields in the USB_O_RXFIFOADD register.
+//
+//*****************************************************************************
+#define USB_RXFIFOADD_ADDR_0    0x00000000  // 0
+#define USB_RXFIFOADD_ADDR_8    0x00000001  // 8
+#define USB_RXFIFOADD_ADDR_16   0x00000002  // 16
+#define USB_RXFIFOADD_ADDR_32   0x00000003  // 32
+#define USB_RXFIFOADD_ADDR_64   0x00000004  // 64
+#define USB_RXFIFOADD_ADDR_128  0x00000005  // 128
+#define USB_RXFIFOADD_ADDR_256  0x00000006  // 256
+#define USB_RXFIFOADD_ADDR_512  0x00000007  // 512
+#define USB_RXFIFOADD_ADDR_1024 0x00000008  // 1024
+#define USB_RXFIFOADD_ADDR_2048 0x00000009  // 2048
+
+//*****************************************************************************
+//
+// Deprecated defines for the bit fields in the USB_O_TXFIFOADD register.
+//
+//*****************************************************************************
+#define USB_TXFIFOADD_ADDR_0    0x00000000  // 0
+#define USB_TXFIFOADD_ADDR_8    0x00000001  // 8
+#define USB_TXFIFOADD_ADDR_16   0x00000002  // 16
+#define USB_TXFIFOADD_ADDR_32   0x00000003  // 32
+#define USB_TXFIFOADD_ADDR_64   0x00000004  // 64
+#define USB_TXFIFOADD_ADDR_128  0x00000005  // 128
+#define USB_TXFIFOADD_ADDR_256  0x00000006  // 256
+#define USB_TXFIFOADD_ADDR_512  0x00000007  // 512
+#define USB_TXFIFOADD_ADDR_1024 0x00000008  // 1024
+#define USB_TXFIFOADD_ADDR_2048 0x00000009  // 2048
+
+//*****************************************************************************
+//
+// Deprecated defines for the bit fields in the EPI_O_HB8CFG2 register.
+//
+//*****************************************************************************
+#define EPI_HB8CFG2_CSCFG       0x01000000  // CSn Configuration
+
+//*****************************************************************************
+//
+// Deprecated defines for the bit fields in the EPI_O_BAUD register.
+//
+//*****************************************************************************
+#define EPI_BAUD_COUNT_M        0x0000FFFF  // Baud Rate Counter
+#define EPI_BAUD_COUNT_S        0
+
+//*****************************************************************************
+//
+// Deprecated defines for the bit fields in the FLASH_FMC register.
+//
+//*****************************************************************************
+#define FLASH_FMC_WRKEY_M       0xFFFF0000  // Flash Memory Write Key
+#define FLASH_FMC_WRKEY_S       16
+
+//*****************************************************************************
+//
+// Deprecated defines for the bit fields in the SYSCTL_RCC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCC2_FRACT       0x00400000  // Fractional divide
+#define SYSCTL_RCC2_USEFRACT    0x40000000  // Use fractional divider
+
+//*****************************************************************************
+//
+// Deprecated defines for the bit fields in the SYSCTL_DID1 register.
+//
+//*****************************************************************************
+#define SYSCTL_DID1_PKG_28SOIC  0x00000000  // SOIC package
+#define SYSCTL_DID1_PKG_48QFP   0x00000008  // QFP package
+
+//*****************************************************************************
+//
+// Deprecated defines for the Micro Direct Memory Access register addresses.
+//
+//*****************************************************************************
+#define UDMA_CHALT              (*((volatile unsigned long *)0x400FF500))
+
+//*****************************************************************************
+//
+// Deprecated defines for the bit fields in the UDMA_CHALT register.
+//
+//*****************************************************************************
+#define UDMA_CHALT_M            0xFFFFFFFF  // Channel [n] Alternate Assignment
+                                            // Select
+
+//*****************************************************************************
+//
+// Deprecated defines for the NVIC register addresses.
+//
+//*****************************************************************************
+#define NVIC_MPU_R              (*((volatile unsigned long *)0xE000ED9C))
+
+#endif
+
 #endif // __LM3S9B92_H__
diff --git a/src/platform/lm3s/lm3s9d92.h b/src/platform/lm3s/lm3s9d92.h
new file mode 100755
index 00000000..742a90d8
--- /dev/null
+++ b/src/platform/lm3s/lm3s9d92.h
@@ -0,0 +1,12444 @@
+//*****************************************************************************
+//
+// lm3s9d92.h - LM3S9D92 Register Definitions
+//
+// Copyright (c) 2010-2011 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 7611 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __LM3S9D92_H__
+#define __LM3S9D92_H__
+
+//*****************************************************************************
+//
+// Watchdog Timer registers (WATCHDOG0)
+//
+//*****************************************************************************
+#define WATCHDOG0_LOAD_R        (*((volatile unsigned long *)0x40000000))
+#define WATCHDOG0_VALUE_R       (*((volatile unsigned long *)0x40000004))
+#define WATCHDOG0_CTL_R         (*((volatile unsigned long *)0x40000008))
+#define WATCHDOG0_ICR_R         (*((volatile unsigned long *)0x4000000C))
+#define WATCHDOG0_RIS_R         (*((volatile unsigned long *)0x40000010))
+#define WATCHDOG0_MIS_R         (*((volatile unsigned long *)0x40000014))
+#define WATCHDOG0_TEST_R        (*((volatile unsigned long *)0x40000418))
+#define WATCHDOG0_LOCK_R        (*((volatile unsigned long *)0x40000C00))
+
+//*****************************************************************************
+//
+// Watchdog Timer registers (WATCHDOG1)
+//
+//*****************************************************************************
+#define WATCHDOG1_LOAD_R        (*((volatile unsigned long *)0x40001000))
+#define WATCHDOG1_VALUE_R       (*((volatile unsigned long *)0x40001004))
+#define WATCHDOG1_CTL_R         (*((volatile unsigned long *)0x40001008))
+#define WATCHDOG1_ICR_R         (*((volatile unsigned long *)0x4000100C))
+#define WATCHDOG1_RIS_R         (*((volatile unsigned long *)0x40001010))
+#define WATCHDOG1_MIS_R         (*((volatile unsigned long *)0x40001014))
+#define WATCHDOG1_TEST_R        (*((volatile unsigned long *)0x40001418))
+#define WATCHDOG1_LOCK_R        (*((volatile unsigned long *)0x40001C00))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTA)
+//
+//*****************************************************************************
+#define GPIO_PORTA_DATA_BITS_R  ((volatile unsigned long *)0x40004000)
+#define GPIO_PORTA_DATA_R       (*((volatile unsigned long *)0x400043FC))
+#define GPIO_PORTA_DIR_R        (*((volatile unsigned long *)0x40004400))
+#define GPIO_PORTA_IS_R         (*((volatile unsigned long *)0x40004404))
+#define GPIO_PORTA_IBE_R        (*((volatile unsigned long *)0x40004408))
+#define GPIO_PORTA_IEV_R        (*((volatile unsigned long *)0x4000440C))
+#define GPIO_PORTA_IM_R         (*((volatile unsigned long *)0x40004410))
+#define GPIO_PORTA_RIS_R        (*((volatile unsigned long *)0x40004414))
+#define GPIO_PORTA_MIS_R        (*((volatile unsigned long *)0x40004418))
+#define GPIO_PORTA_ICR_R        (*((volatile unsigned long *)0x4000441C))
+#define GPIO_PORTA_AFSEL_R      (*((volatile unsigned long *)0x40004420))
+#define GPIO_PORTA_DR2R_R       (*((volatile unsigned long *)0x40004500))
+#define GPIO_PORTA_DR4R_R       (*((volatile unsigned long *)0x40004504))
+#define GPIO_PORTA_DR8R_R       (*((volatile unsigned long *)0x40004508))
+#define GPIO_PORTA_ODR_R        (*((volatile unsigned long *)0x4000450C))
+#define GPIO_PORTA_PUR_R        (*((volatile unsigned long *)0x40004510))
+#define GPIO_PORTA_PDR_R        (*((volatile unsigned long *)0x40004514))
+#define GPIO_PORTA_SLR_R        (*((volatile unsigned long *)0x40004518))
+#define GPIO_PORTA_DEN_R        (*((volatile unsigned long *)0x4000451C))
+#define GPIO_PORTA_LOCK_R       (*((volatile unsigned long *)0x40004520))
+#define GPIO_PORTA_CR_R         (*((volatile unsigned long *)0x40004524))
+#define GPIO_PORTA_AMSEL_R      (*((volatile unsigned long *)0x40004528))
+#define GPIO_PORTA_PCTL_R       (*((volatile unsigned long *)0x4000452C))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTB)
+//
+//*****************************************************************************
+#define GPIO_PORTB_DATA_BITS_R  ((volatile unsigned long *)0x40005000)
+#define GPIO_PORTB_DATA_R       (*((volatile unsigned long *)0x400053FC))
+#define GPIO_PORTB_DIR_R        (*((volatile unsigned long *)0x40005400))
+#define GPIO_PORTB_IS_R         (*((volatile unsigned long *)0x40005404))
+#define GPIO_PORTB_IBE_R        (*((volatile unsigned long *)0x40005408))
+#define GPIO_PORTB_IEV_R        (*((volatile unsigned long *)0x4000540C))
+#define GPIO_PORTB_IM_R         (*((volatile unsigned long *)0x40005410))
+#define GPIO_PORTB_RIS_R        (*((volatile unsigned long *)0x40005414))
+#define GPIO_PORTB_MIS_R        (*((volatile unsigned long *)0x40005418))
+#define GPIO_PORTB_ICR_R        (*((volatile unsigned long *)0x4000541C))
+#define GPIO_PORTB_AFSEL_R      (*((volatile unsigned long *)0x40005420))
+#define GPIO_PORTB_DR2R_R       (*((volatile unsigned long *)0x40005500))
+#define GPIO_PORTB_DR4R_R       (*((volatile unsigned long *)0x40005504))
+#define GPIO_PORTB_DR8R_R       (*((volatile unsigned long *)0x40005508))
+#define GPIO_PORTB_ODR_R        (*((volatile unsigned long *)0x4000550C))
+#define GPIO_PORTB_PUR_R        (*((volatile unsigned long *)0x40005510))
+#define GPIO_PORTB_PDR_R        (*((volatile unsigned long *)0x40005514))
+#define GPIO_PORTB_SLR_R        (*((volatile unsigned long *)0x40005518))
+#define GPIO_PORTB_DEN_R        (*((volatile unsigned long *)0x4000551C))
+#define GPIO_PORTB_LOCK_R       (*((volatile unsigned long *)0x40005520))
+#define GPIO_PORTB_CR_R         (*((volatile unsigned long *)0x40005524))
+#define GPIO_PORTB_AMSEL_R      (*((volatile unsigned long *)0x40005528))
+#define GPIO_PORTB_PCTL_R       (*((volatile unsigned long *)0x4000552C))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTC)
+//
+//*****************************************************************************
+#define GPIO_PORTC_DATA_BITS_R  ((volatile unsigned long *)0x40006000)
+#define GPIO_PORTC_DATA_R       (*((volatile unsigned long *)0x400063FC))
+#define GPIO_PORTC_DIR_R        (*((volatile unsigned long *)0x40006400))
+#define GPIO_PORTC_IS_R         (*((volatile unsigned long *)0x40006404))
+#define GPIO_PORTC_IBE_R        (*((volatile unsigned long *)0x40006408))
+#define GPIO_PORTC_IEV_R        (*((volatile unsigned long *)0x4000640C))
+#define GPIO_PORTC_IM_R         (*((volatile unsigned long *)0x40006410))
+#define GPIO_PORTC_RIS_R        (*((volatile unsigned long *)0x40006414))
+#define GPIO_PORTC_MIS_R        (*((volatile unsigned long *)0x40006418))
+#define GPIO_PORTC_ICR_R        (*((volatile unsigned long *)0x4000641C))
+#define GPIO_PORTC_AFSEL_R      (*((volatile unsigned long *)0x40006420))
+#define GPIO_PORTC_DR2R_R       (*((volatile unsigned long *)0x40006500))
+#define GPIO_PORTC_DR4R_R       (*((volatile unsigned long *)0x40006504))
+#define GPIO_PORTC_DR8R_R       (*((volatile unsigned long *)0x40006508))
+#define GPIO_PORTC_ODR_R        (*((volatile unsigned long *)0x4000650C))
+#define GPIO_PORTC_PUR_R        (*((volatile unsigned long *)0x40006510))
+#define GPIO_PORTC_PDR_R        (*((volatile unsigned long *)0x40006514))
+#define GPIO_PORTC_SLR_R        (*((volatile unsigned long *)0x40006518))
+#define GPIO_PORTC_DEN_R        (*((volatile unsigned long *)0x4000651C))
+#define GPIO_PORTC_LOCK_R       (*((volatile unsigned long *)0x40006520))
+#define GPIO_PORTC_CR_R         (*((volatile unsigned long *)0x40006524))
+#define GPIO_PORTC_AMSEL_R      (*((volatile unsigned long *)0x40006528))
+#define GPIO_PORTC_PCTL_R       (*((volatile unsigned long *)0x4000652C))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTD)
+//
+//*****************************************************************************
+#define GPIO_PORTD_DATA_BITS_R  ((volatile unsigned long *)0x40007000)
+#define GPIO_PORTD_DATA_R       (*((volatile unsigned long *)0x400073FC))
+#define GPIO_PORTD_DIR_R        (*((volatile unsigned long *)0x40007400))
+#define GPIO_PORTD_IS_R         (*((volatile unsigned long *)0x40007404))
+#define GPIO_PORTD_IBE_R        (*((volatile unsigned long *)0x40007408))
+#define GPIO_PORTD_IEV_R        (*((volatile unsigned long *)0x4000740C))
+#define GPIO_PORTD_IM_R         (*((volatile unsigned long *)0x40007410))
+#define GPIO_PORTD_RIS_R        (*((volatile unsigned long *)0x40007414))
+#define GPIO_PORTD_MIS_R        (*((volatile unsigned long *)0x40007418))
+#define GPIO_PORTD_ICR_R        (*((volatile unsigned long *)0x4000741C))
+#define GPIO_PORTD_AFSEL_R      (*((volatile unsigned long *)0x40007420))
+#define GPIO_PORTD_DR2R_R       (*((volatile unsigned long *)0x40007500))
+#define GPIO_PORTD_DR4R_R       (*((volatile unsigned long *)0x40007504))
+#define GPIO_PORTD_DR8R_R       (*((volatile unsigned long *)0x40007508))
+#define GPIO_PORTD_ODR_R        (*((volatile unsigned long *)0x4000750C))
+#define GPIO_PORTD_PUR_R        (*((volatile unsigned long *)0x40007510))
+#define GPIO_PORTD_PDR_R        (*((volatile unsigned long *)0x40007514))
+#define GPIO_PORTD_SLR_R        (*((volatile unsigned long *)0x40007518))
+#define GPIO_PORTD_DEN_R        (*((volatile unsigned long *)0x4000751C))
+#define GPIO_PORTD_LOCK_R       (*((volatile unsigned long *)0x40007520))
+#define GPIO_PORTD_CR_R         (*((volatile unsigned long *)0x40007524))
+#define GPIO_PORTD_AMSEL_R      (*((volatile unsigned long *)0x40007528))
+#define GPIO_PORTD_PCTL_R       (*((volatile unsigned long *)0x4000752C))
+
+//*****************************************************************************
+//
+// SSI registers (SSI0)
+//
+//*****************************************************************************
+#define SSI0_CR0_R              (*((volatile unsigned long *)0x40008000))
+#define SSI0_CR1_R              (*((volatile unsigned long *)0x40008004))
+#define SSI0_DR_R               (*((volatile unsigned long *)0x40008008))
+#define SSI0_SR_R               (*((volatile unsigned long *)0x4000800C))
+#define SSI0_CPSR_R             (*((volatile unsigned long *)0x40008010))
+#define SSI0_IM_R               (*((volatile unsigned long *)0x40008014))
+#define SSI0_RIS_R              (*((volatile unsigned long *)0x40008018))
+#define SSI0_MIS_R              (*((volatile unsigned long *)0x4000801C))
+#define SSI0_ICR_R              (*((volatile unsigned long *)0x40008020))
+#define SSI0_DMACTL_R           (*((volatile unsigned long *)0x40008024))
+
+//*****************************************************************************
+//
+// SSI registers (SSI1)
+//
+//*****************************************************************************
+#define SSI1_CR0_R              (*((volatile unsigned long *)0x40009000))
+#define SSI1_CR1_R              (*((volatile unsigned long *)0x40009004))
+#define SSI1_DR_R               (*((volatile unsigned long *)0x40009008))
+#define SSI1_SR_R               (*((volatile unsigned long *)0x4000900C))
+#define SSI1_CPSR_R             (*((volatile unsigned long *)0x40009010))
+#define SSI1_IM_R               (*((volatile unsigned long *)0x40009014))
+#define SSI1_RIS_R              (*((volatile unsigned long *)0x40009018))
+#define SSI1_MIS_R              (*((volatile unsigned long *)0x4000901C))
+#define SSI1_ICR_R              (*((volatile unsigned long *)0x40009020))
+#define SSI1_DMACTL_R           (*((volatile unsigned long *)0x40009024))
+
+//*****************************************************************************
+//
+// UART registers (UART0)
+//
+//*****************************************************************************
+#define UART0_DR_R              (*((volatile unsigned long *)0x4000C000))
+#define UART0_RSR_R             (*((volatile unsigned long *)0x4000C004))
+#define UART0_ECR_R             (*((volatile unsigned long *)0x4000C004))
+#define UART0_FR_R              (*((volatile unsigned long *)0x4000C018))
+#define UART0_ILPR_R            (*((volatile unsigned long *)0x4000C020))
+#define UART0_IBRD_R            (*((volatile unsigned long *)0x4000C024))
+#define UART0_FBRD_R            (*((volatile unsigned long *)0x4000C028))
+#define UART0_LCRH_R            (*((volatile unsigned long *)0x4000C02C))
+#define UART0_CTL_R             (*((volatile unsigned long *)0x4000C030))
+#define UART0_IFLS_R            (*((volatile unsigned long *)0x4000C034))
+#define UART0_IM_R              (*((volatile unsigned long *)0x4000C038))
+#define UART0_RIS_R             (*((volatile unsigned long *)0x4000C03C))
+#define UART0_MIS_R             (*((volatile unsigned long *)0x4000C040))
+#define UART0_ICR_R             (*((volatile unsigned long *)0x4000C044))
+#define UART0_DMACTL_R          (*((volatile unsigned long *)0x4000C048))
+#define UART0_LCTL_R            (*((volatile unsigned long *)0x4000C090))
+#define UART0_LSS_R             (*((volatile unsigned long *)0x4000C094))
+#define UART0_LTIM_R            (*((volatile unsigned long *)0x4000C098))
+
+//*****************************************************************************
+//
+// UART registers (UART1)
+//
+//*****************************************************************************
+#define UART1_DR_R              (*((volatile unsigned long *)0x4000D000))
+#define UART1_RSR_R             (*((volatile unsigned long *)0x4000D004))
+#define UART1_ECR_R             (*((volatile unsigned long *)0x4000D004))
+#define UART1_FR_R              (*((volatile unsigned long *)0x4000D018))
+#define UART1_ILPR_R            (*((volatile unsigned long *)0x4000D020))
+#define UART1_IBRD_R            (*((volatile unsigned long *)0x4000D024))
+#define UART1_FBRD_R            (*((volatile unsigned long *)0x4000D028))
+#define UART1_LCRH_R            (*((volatile unsigned long *)0x4000D02C))
+#define UART1_CTL_R             (*((volatile unsigned long *)0x4000D030))
+#define UART1_IFLS_R            (*((volatile unsigned long *)0x4000D034))
+#define UART1_IM_R              (*((volatile unsigned long *)0x4000D038))
+#define UART1_RIS_R             (*((volatile unsigned long *)0x4000D03C))
+#define UART1_MIS_R             (*((volatile unsigned long *)0x4000D040))
+#define UART1_ICR_R             (*((volatile unsigned long *)0x4000D044))
+#define UART1_DMACTL_R          (*((volatile unsigned long *)0x4000D048))
+#define UART1_LCTL_R            (*((volatile unsigned long *)0x4000D090))
+#define UART1_LSS_R             (*((volatile unsigned long *)0x4000D094))
+#define UART1_LTIM_R            (*((volatile unsigned long *)0x4000D098))
+
+//*****************************************************************************
+//
+// UART registers (UART2)
+//
+//*****************************************************************************
+#define UART2_DR_R              (*((volatile unsigned long *)0x4000E000))
+#define UART2_RSR_R             (*((volatile unsigned long *)0x4000E004))
+#define UART2_ECR_R             (*((volatile unsigned long *)0x4000E004))
+#define UART2_FR_R              (*((volatile unsigned long *)0x4000E018))
+#define UART2_ILPR_R            (*((volatile unsigned long *)0x4000E020))
+#define UART2_IBRD_R            (*((volatile unsigned long *)0x4000E024))
+#define UART2_FBRD_R            (*((volatile unsigned long *)0x4000E028))
+#define UART2_LCRH_R            (*((volatile unsigned long *)0x4000E02C))
+#define UART2_CTL_R             (*((volatile unsigned long *)0x4000E030))
+#define UART2_IFLS_R            (*((volatile unsigned long *)0x4000E034))
+#define UART2_IM_R              (*((volatile unsigned long *)0x4000E038))
+#define UART2_RIS_R             (*((volatile unsigned long *)0x4000E03C))
+#define UART2_MIS_R             (*((volatile unsigned long *)0x4000E040))
+#define UART2_ICR_R             (*((volatile unsigned long *)0x4000E044))
+#define UART2_DMACTL_R          (*((volatile unsigned long *)0x4000E048))
+#define UART2_LCTL_R            (*((volatile unsigned long *)0x4000E090))
+#define UART2_LSS_R             (*((volatile unsigned long *)0x4000E094))
+#define UART2_LTIM_R            (*((volatile unsigned long *)0x4000E098))
+
+//*****************************************************************************
+//
+// I2C registers (I2C0 MASTER)
+//
+//*****************************************************************************
+#define I2C0_MASTER_MSA_R       (*((volatile unsigned long *)0x40020000))
+#define I2C0_MASTER_MCS_R       (*((volatile unsigned long *)0x40020004))
+#define I2C0_MASTER_MDR_R       (*((volatile unsigned long *)0x40020008))
+#define I2C0_MASTER_MTPR_R      (*((volatile unsigned long *)0x4002000C))
+#define I2C0_MASTER_MIMR_R      (*((volatile unsigned long *)0x40020010))
+#define I2C0_MASTER_MRIS_R      (*((volatile unsigned long *)0x40020014))
+#define I2C0_MASTER_MMIS_R      (*((volatile unsigned long *)0x40020018))
+#define I2C0_MASTER_MICR_R      (*((volatile unsigned long *)0x4002001C))
+#define I2C0_MASTER_MCR_R       (*((volatile unsigned long *)0x40020020))
+
+//*****************************************************************************
+//
+// I2C registers (I2C0 SLAVE)
+//
+//*****************************************************************************
+#define I2C0_SLAVE_SOAR_R       (*((volatile unsigned long *)0x40020800))
+#define I2C0_SLAVE_SCSR_R       (*((volatile unsigned long *)0x40020804))
+#define I2C0_SLAVE_SDR_R        (*((volatile unsigned long *)0x40020808))
+#define I2C0_SLAVE_SIMR_R       (*((volatile unsigned long *)0x4002080C))
+#define I2C0_SLAVE_SRIS_R       (*((volatile unsigned long *)0x40020810))
+#define I2C0_SLAVE_SMIS_R       (*((volatile unsigned long *)0x40020814))
+#define I2C0_SLAVE_SICR_R       (*((volatile unsigned long *)0x40020818))
+
+//*****************************************************************************
+//
+// I2C registers (I2C1 MASTER)
+//
+//*****************************************************************************
+#define I2C1_MASTER_MSA_R       (*((volatile unsigned long *)0x40021000))
+#define I2C1_MASTER_MCS_R       (*((volatile unsigned long *)0x40021004))
+#define I2C1_MASTER_MDR_R       (*((volatile unsigned long *)0x40021008))
+#define I2C1_MASTER_MTPR_R      (*((volatile unsigned long *)0x4002100C))
+#define I2C1_MASTER_MIMR_R      (*((volatile unsigned long *)0x40021010))
+#define I2C1_MASTER_MRIS_R      (*((volatile unsigned long *)0x40021014))
+#define I2C1_MASTER_MMIS_R      (*((volatile unsigned long *)0x40021018))
+#define I2C1_MASTER_MICR_R      (*((volatile unsigned long *)0x4002101C))
+#define I2C1_MASTER_MCR_R       (*((volatile unsigned long *)0x40021020))
+
+//*****************************************************************************
+//
+// I2C registers (I2C1 SLAVE)
+//
+//*****************************************************************************
+#define I2C1_SLAVE_SOAR_R       (*((volatile unsigned long *)0x40021800))
+#define I2C1_SLAVE_SCSR_R       (*((volatile unsigned long *)0x40021804))
+#define I2C1_SLAVE_SDR_R        (*((volatile unsigned long *)0x40021808))
+#define I2C1_SLAVE_SIMR_R       (*((volatile unsigned long *)0x4002180C))
+#define I2C1_SLAVE_SRIS_R       (*((volatile unsigned long *)0x40021810))
+#define I2C1_SLAVE_SMIS_R       (*((volatile unsigned long *)0x40021814))
+#define I2C1_SLAVE_SICR_R       (*((volatile unsigned long *)0x40021818))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTE)
+//
+//*****************************************************************************
+#define GPIO_PORTE_DATA_BITS_R  ((volatile unsigned long *)0x40024000)
+#define GPIO_PORTE_DATA_R       (*((volatile unsigned long *)0x400243FC))
+#define GPIO_PORTE_DIR_R        (*((volatile unsigned long *)0x40024400))
+#define GPIO_PORTE_IS_R         (*((volatile unsigned long *)0x40024404))
+#define GPIO_PORTE_IBE_R        (*((volatile unsigned long *)0x40024408))
+#define GPIO_PORTE_IEV_R        (*((volatile unsigned long *)0x4002440C))
+#define GPIO_PORTE_IM_R         (*((volatile unsigned long *)0x40024410))
+#define GPIO_PORTE_RIS_R        (*((volatile unsigned long *)0x40024414))
+#define GPIO_PORTE_MIS_R        (*((volatile unsigned long *)0x40024418))
+#define GPIO_PORTE_ICR_R        (*((volatile unsigned long *)0x4002441C))
+#define GPIO_PORTE_AFSEL_R      (*((volatile unsigned long *)0x40024420))
+#define GPIO_PORTE_DR2R_R       (*((volatile unsigned long *)0x40024500))
+#define GPIO_PORTE_DR4R_R       (*((volatile unsigned long *)0x40024504))
+#define GPIO_PORTE_DR8R_R       (*((volatile unsigned long *)0x40024508))
+#define GPIO_PORTE_ODR_R        (*((volatile unsigned long *)0x4002450C))
+#define GPIO_PORTE_PUR_R        (*((volatile unsigned long *)0x40024510))
+#define GPIO_PORTE_PDR_R        (*((volatile unsigned long *)0x40024514))
+#define GPIO_PORTE_SLR_R        (*((volatile unsigned long *)0x40024518))
+#define GPIO_PORTE_DEN_R        (*((volatile unsigned long *)0x4002451C))
+#define GPIO_PORTE_LOCK_R       (*((volatile unsigned long *)0x40024520))
+#define GPIO_PORTE_CR_R         (*((volatile unsigned long *)0x40024524))
+#define GPIO_PORTE_AMSEL_R      (*((volatile unsigned long *)0x40024528))
+#define GPIO_PORTE_PCTL_R       (*((volatile unsigned long *)0x4002452C))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTF)
+//
+//*****************************************************************************
+#define GPIO_PORTF_DATA_BITS_R  ((volatile unsigned long *)0x40025000)
+#define GPIO_PORTF_DATA_R       (*((volatile unsigned long *)0x400253FC))
+#define GPIO_PORTF_DIR_R        (*((volatile unsigned long *)0x40025400))
+#define GPIO_PORTF_IS_R         (*((volatile unsigned long *)0x40025404))
+#define GPIO_PORTF_IBE_R        (*((volatile unsigned long *)0x40025408))
+#define GPIO_PORTF_IEV_R        (*((volatile unsigned long *)0x4002540C))
+#define GPIO_PORTF_IM_R         (*((volatile unsigned long *)0x40025410))
+#define GPIO_PORTF_RIS_R        (*((volatile unsigned long *)0x40025414))
+#define GPIO_PORTF_MIS_R        (*((volatile unsigned long *)0x40025418))
+#define GPIO_PORTF_ICR_R        (*((volatile unsigned long *)0x4002541C))
+#define GPIO_PORTF_AFSEL_R      (*((volatile unsigned long *)0x40025420))
+#define GPIO_PORTF_DR2R_R       (*((volatile unsigned long *)0x40025500))
+#define GPIO_PORTF_DR4R_R       (*((volatile unsigned long *)0x40025504))
+#define GPIO_PORTF_DR8R_R       (*((volatile unsigned long *)0x40025508))
+#define GPIO_PORTF_ODR_R        (*((volatile unsigned long *)0x4002550C))
+#define GPIO_PORTF_PUR_R        (*((volatile unsigned long *)0x40025510))
+#define GPIO_PORTF_PDR_R        (*((volatile unsigned long *)0x40025514))
+#define GPIO_PORTF_SLR_R        (*((volatile unsigned long *)0x40025518))
+#define GPIO_PORTF_DEN_R        (*((volatile unsigned long *)0x4002551C))
+#define GPIO_PORTF_LOCK_R       (*((volatile unsigned long *)0x40025520))
+#define GPIO_PORTF_CR_R         (*((volatile unsigned long *)0x40025524))
+#define GPIO_PORTF_AMSEL_R      (*((volatile unsigned long *)0x40025528))
+#define GPIO_PORTF_PCTL_R       (*((volatile unsigned long *)0x4002552C))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTG)
+//
+//*****************************************************************************
+#define GPIO_PORTG_DATA_BITS_R  ((volatile unsigned long *)0x40026000)
+#define GPIO_PORTG_DATA_R       (*((volatile unsigned long *)0x400263FC))
+#define GPIO_PORTG_DIR_R        (*((volatile unsigned long *)0x40026400))
+#define GPIO_PORTG_IS_R         (*((volatile unsigned long *)0x40026404))
+#define GPIO_PORTG_IBE_R        (*((volatile unsigned long *)0x40026408))
+#define GPIO_PORTG_IEV_R        (*((volatile unsigned long *)0x4002640C))
+#define GPIO_PORTG_IM_R         (*((volatile unsigned long *)0x40026410))
+#define GPIO_PORTG_RIS_R        (*((volatile unsigned long *)0x40026414))
+#define GPIO_PORTG_MIS_R        (*((volatile unsigned long *)0x40026418))
+#define GPIO_PORTG_ICR_R        (*((volatile unsigned long *)0x4002641C))
+#define GPIO_PORTG_AFSEL_R      (*((volatile unsigned long *)0x40026420))
+#define GPIO_PORTG_DR2R_R       (*((volatile unsigned long *)0x40026500))
+#define GPIO_PORTG_DR4R_R       (*((volatile unsigned long *)0x40026504))
+#define GPIO_PORTG_DR8R_R       (*((volatile unsigned long *)0x40026508))
+#define GPIO_PORTG_ODR_R        (*((volatile unsigned long *)0x4002650C))
+#define GPIO_PORTG_PUR_R        (*((volatile unsigned long *)0x40026510))
+#define GPIO_PORTG_PDR_R        (*((volatile unsigned long *)0x40026514))
+#define GPIO_PORTG_SLR_R        (*((volatile unsigned long *)0x40026518))
+#define GPIO_PORTG_DEN_R        (*((volatile unsigned long *)0x4002651C))
+#define GPIO_PORTG_LOCK_R       (*((volatile unsigned long *)0x40026520))
+#define GPIO_PORTG_CR_R         (*((volatile unsigned long *)0x40026524))
+#define GPIO_PORTG_AMSEL_R      (*((volatile unsigned long *)0x40026528))
+#define GPIO_PORTG_PCTL_R       (*((volatile unsigned long *)0x4002652C))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTH)
+//
+//*****************************************************************************
+#define GPIO_PORTH_DATA_BITS_R  ((volatile unsigned long *)0x40027000)
+#define GPIO_PORTH_DATA_R       (*((volatile unsigned long *)0x400273FC))
+#define GPIO_PORTH_DIR_R        (*((volatile unsigned long *)0x40027400))
+#define GPIO_PORTH_IS_R         (*((volatile unsigned long *)0x40027404))
+#define GPIO_PORTH_IBE_R        (*((volatile unsigned long *)0x40027408))
+#define GPIO_PORTH_IEV_R        (*((volatile unsigned long *)0x4002740C))
+#define GPIO_PORTH_IM_R         (*((volatile unsigned long *)0x40027410))
+#define GPIO_PORTH_RIS_R        (*((volatile unsigned long *)0x40027414))
+#define GPIO_PORTH_MIS_R        (*((volatile unsigned long *)0x40027418))
+#define GPIO_PORTH_ICR_R        (*((volatile unsigned long *)0x4002741C))
+#define GPIO_PORTH_AFSEL_R      (*((volatile unsigned long *)0x40027420))
+#define GPIO_PORTH_DR2R_R       (*((volatile unsigned long *)0x40027500))
+#define GPIO_PORTH_DR4R_R       (*((volatile unsigned long *)0x40027504))
+#define GPIO_PORTH_DR8R_R       (*((volatile unsigned long *)0x40027508))
+#define GPIO_PORTH_ODR_R        (*((volatile unsigned long *)0x4002750C))
+#define GPIO_PORTH_PUR_R        (*((volatile unsigned long *)0x40027510))
+#define GPIO_PORTH_PDR_R        (*((volatile unsigned long *)0x40027514))
+#define GPIO_PORTH_SLR_R        (*((volatile unsigned long *)0x40027518))
+#define GPIO_PORTH_DEN_R        (*((volatile unsigned long *)0x4002751C))
+#define GPIO_PORTH_LOCK_R       (*((volatile unsigned long *)0x40027520))
+#define GPIO_PORTH_CR_R         (*((volatile unsigned long *)0x40027524))
+#define GPIO_PORTH_AMSEL_R      (*((volatile unsigned long *)0x40027528))
+#define GPIO_PORTH_PCTL_R       (*((volatile unsigned long *)0x4002752C))
+
+//*****************************************************************************
+//
+// PWM registers (PWM)
+//
+//*****************************************************************************
+#define PWM_CTL_R               (*((volatile unsigned long *)0x40028000))
+#define PWM_SYNC_R              (*((volatile unsigned long *)0x40028004))
+#define PWM_ENABLE_R            (*((volatile unsigned long *)0x40028008))
+#define PWM_INVERT_R            (*((volatile unsigned long *)0x4002800C))
+#define PWM_FAULT_R             (*((volatile unsigned long *)0x40028010))
+#define PWM_INTEN_R             (*((volatile unsigned long *)0x40028014))
+#define PWM_RIS_R               (*((volatile unsigned long *)0x40028018))
+#define PWM_ISC_R               (*((volatile unsigned long *)0x4002801C))
+#define PWM_STATUS_R            (*((volatile unsigned long *)0x40028020))
+#define PWM_FAULTVAL_R          (*((volatile unsigned long *)0x40028024))
+#define PWM_ENUPD_R             (*((volatile unsigned long *)0x40028028))
+#define PWM_0_CTL_R             (*((volatile unsigned long *)0x40028040))
+#define PWM_0_INTEN_R           (*((volatile unsigned long *)0x40028044))
+#define PWM_0_RIS_R             (*((volatile unsigned long *)0x40028048))
+#define PWM_0_ISC_R             (*((volatile unsigned long *)0x4002804C))
+#define PWM_0_LOAD_R            (*((volatile unsigned long *)0x40028050))
+#define PWM_0_COUNT_R           (*((volatile unsigned long *)0x40028054))
+#define PWM_0_CMPA_R            (*((volatile unsigned long *)0x40028058))
+#define PWM_0_CMPB_R            (*((volatile unsigned long *)0x4002805C))
+#define PWM_0_GENA_R            (*((volatile unsigned long *)0x40028060))
+#define PWM_0_GENB_R            (*((volatile unsigned long *)0x40028064))
+#define PWM_0_DBCTL_R           (*((volatile unsigned long *)0x40028068))
+#define PWM_0_DBRISE_R          (*((volatile unsigned long *)0x4002806C))
+#define PWM_0_DBFALL_R          (*((volatile unsigned long *)0x40028070))
+#define PWM_0_FLTSRC0_R         (*((volatile unsigned long *)0x40028074))
+#define PWM_0_FLTSRC1_R         (*((volatile unsigned long *)0x40028078))
+#define PWM_0_MINFLTPER_R       (*((volatile unsigned long *)0x4002807C))
+#define PWM_1_CTL_R             (*((volatile unsigned long *)0x40028080))
+#define PWM_1_INTEN_R           (*((volatile unsigned long *)0x40028084))
+#define PWM_1_RIS_R             (*((volatile unsigned long *)0x40028088))
+#define PWM_1_ISC_R             (*((volatile unsigned long *)0x4002808C))
+#define PWM_1_LOAD_R            (*((volatile unsigned long *)0x40028090))
+#define PWM_1_COUNT_R           (*((volatile unsigned long *)0x40028094))
+#define PWM_1_CMPA_R            (*((volatile unsigned long *)0x40028098))
+#define PWM_1_CMPB_R            (*((volatile unsigned long *)0x4002809C))
+#define PWM_1_GENA_R            (*((volatile unsigned long *)0x400280A0))
+#define PWM_1_GENB_R            (*((volatile unsigned long *)0x400280A4))
+#define PWM_1_DBCTL_R           (*((volatile unsigned long *)0x400280A8))
+#define PWM_1_DBRISE_R          (*((volatile unsigned long *)0x400280AC))
+#define PWM_1_DBFALL_R          (*((volatile unsigned long *)0x400280B0))
+#define PWM_1_FLTSRC0_R         (*((volatile unsigned long *)0x400280B4))
+#define PWM_1_FLTSRC1_R         (*((volatile unsigned long *)0x400280B8))
+#define PWM_1_MINFLTPER_R       (*((volatile unsigned long *)0x400280BC))
+#define PWM_2_CTL_R             (*((volatile unsigned long *)0x400280C0))
+#define PWM_2_INTEN_R           (*((volatile unsigned long *)0x400280C4))
+#define PWM_2_RIS_R             (*((volatile unsigned long *)0x400280C8))
+#define PWM_2_ISC_R             (*((volatile unsigned long *)0x400280CC))
+#define PWM_2_LOAD_R            (*((volatile unsigned long *)0x400280D0))
+#define PWM_2_COUNT_R           (*((volatile unsigned long *)0x400280D4))
+#define PWM_2_CMPA_R            (*((volatile unsigned long *)0x400280D8))
+#define PWM_2_CMPB_R            (*((volatile unsigned long *)0x400280DC))
+#define PWM_2_GENA_R            (*((volatile unsigned long *)0x400280E0))
+#define PWM_2_GENB_R            (*((volatile unsigned long *)0x400280E4))
+#define PWM_2_DBCTL_R           (*((volatile unsigned long *)0x400280E8))
+#define PWM_2_DBRISE_R          (*((volatile unsigned long *)0x400280EC))
+#define PWM_2_DBFALL_R          (*((volatile unsigned long *)0x400280F0))
+#define PWM_2_FLTSRC0_R         (*((volatile unsigned long *)0x400280F4))
+#define PWM_2_FLTSRC1_R         (*((volatile unsigned long *)0x400280F8))
+#define PWM_2_MINFLTPER_R       (*((volatile unsigned long *)0x400280FC))
+#define PWM_3_CTL_R             (*((volatile unsigned long *)0x40028100))
+#define PWM_3_INTEN_R           (*((volatile unsigned long *)0x40028104))
+#define PWM_3_RIS_R             (*((volatile unsigned long *)0x40028108))
+#define PWM_3_ISC_R             (*((volatile unsigned long *)0x4002810C))
+#define PWM_3_LOAD_R            (*((volatile unsigned long *)0x40028110))
+#define PWM_3_COUNT_R           (*((volatile unsigned long *)0x40028114))
+#define PWM_3_CMPA_R            (*((volatile unsigned long *)0x40028118))
+#define PWM_3_CMPB_R            (*((volatile unsigned long *)0x4002811C))
+#define PWM_3_GENA_R            (*((volatile unsigned long *)0x40028120))
+#define PWM_3_GENB_R            (*((volatile unsigned long *)0x40028124))
+#define PWM_3_DBCTL_R           (*((volatile unsigned long *)0x40028128))
+#define PWM_3_DBRISE_R          (*((volatile unsigned long *)0x4002812C))
+#define PWM_3_DBFALL_R          (*((volatile unsigned long *)0x40028130))
+#define PWM_3_FLTSRC0_R         (*((volatile unsigned long *)0x40028134))
+#define PWM_3_FLTSRC1_R         (*((volatile unsigned long *)0x40028138))
+#define PWM_3_MINFLTPER_R       (*((volatile unsigned long *)0x4002813C))
+#define PWM_0_FLTSEN_R          (*((volatile unsigned long *)0x40028800))
+#define PWM_0_FLTSTAT0_R        (*((volatile unsigned long *)0x40028804))
+#define PWM_0_FLTSTAT1_R        (*((volatile unsigned long *)0x40028808))
+#define PWM_1_FLTSEN_R          (*((volatile unsigned long *)0x40028880))
+#define PWM_1_FLTSTAT0_R        (*((volatile unsigned long *)0x40028884))
+#define PWM_1_FLTSTAT1_R        (*((volatile unsigned long *)0x40028888))
+#define PWM_2_FLTSEN_R          (*((volatile unsigned long *)0x40028900))
+#define PWM_2_FLTSTAT0_R        (*((volatile unsigned long *)0x40028904))
+#define PWM_2_FLTSTAT1_R        (*((volatile unsigned long *)0x40028908))
+#define PWM_3_FLTSEN_R          (*((volatile unsigned long *)0x40028980))
+#define PWM_3_FLTSTAT0_R        (*((volatile unsigned long *)0x40028984))
+#define PWM_3_FLTSTAT1_R        (*((volatile unsigned long *)0x40028988))
+
+//*****************************************************************************
+//
+// QEI registers (QEI0)
+//
+//*****************************************************************************
+#define QEI0_CTL_R              (*((volatile unsigned long *)0x4002C000))
+#define QEI0_STAT_R             (*((volatile unsigned long *)0x4002C004))
+#define QEI0_POS_R              (*((volatile unsigned long *)0x4002C008))
+#define QEI0_MAXPOS_R           (*((volatile unsigned long *)0x4002C00C))
+#define QEI0_LOAD_R             (*((volatile unsigned long *)0x4002C010))
+#define QEI0_TIME_R             (*((volatile unsigned long *)0x4002C014))
+#define QEI0_COUNT_R            (*((volatile unsigned long *)0x4002C018))
+#define QEI0_SPEED_R            (*((volatile unsigned long *)0x4002C01C))
+#define QEI0_INTEN_R            (*((volatile unsigned long *)0x4002C020))
+#define QEI0_RIS_R              (*((volatile unsigned long *)0x4002C024))
+#define QEI0_ISC_R              (*((volatile unsigned long *)0x4002C028))
+
+//*****************************************************************************
+//
+// QEI registers (QEI1)
+//
+//*****************************************************************************
+#define QEI1_CTL_R              (*((volatile unsigned long *)0x4002D000))
+#define QEI1_STAT_R             (*((volatile unsigned long *)0x4002D004))
+#define QEI1_POS_R              (*((volatile unsigned long *)0x4002D008))
+#define QEI1_MAXPOS_R           (*((volatile unsigned long *)0x4002D00C))
+#define QEI1_LOAD_R             (*((volatile unsigned long *)0x4002D010))
+#define QEI1_TIME_R             (*((volatile unsigned long *)0x4002D014))
+#define QEI1_COUNT_R            (*((volatile unsigned long *)0x4002D018))
+#define QEI1_SPEED_R            (*((volatile unsigned long *)0x4002D01C))
+#define QEI1_INTEN_R            (*((volatile unsigned long *)0x4002D020))
+#define QEI1_RIS_R              (*((volatile unsigned long *)0x4002D024))
+#define QEI1_ISC_R              (*((volatile unsigned long *)0x4002D028))
+
+//*****************************************************************************
+//
+// Timer registers (TIMER0)
+//
+//*****************************************************************************
+#define TIMER0_CFG_R            (*((volatile unsigned long *)0x40030000))
+#define TIMER0_TAMR_R           (*((volatile unsigned long *)0x40030004))
+#define TIMER0_TBMR_R           (*((volatile unsigned long *)0x40030008))
+#define TIMER0_CTL_R            (*((volatile unsigned long *)0x4003000C))
+#define TIMER0_IMR_R            (*((volatile unsigned long *)0x40030018))
+#define TIMER0_RIS_R            (*((volatile unsigned long *)0x4003001C))
+#define TIMER0_MIS_R            (*((volatile unsigned long *)0x40030020))
+#define TIMER0_ICR_R            (*((volatile unsigned long *)0x40030024))
+#define TIMER0_TAILR_R          (*((volatile unsigned long *)0x40030028))
+#define TIMER0_TBILR_R          (*((volatile unsigned long *)0x4003002C))
+#define TIMER0_TAMATCHR_R       (*((volatile unsigned long *)0x40030030))
+#define TIMER0_TBMATCHR_R       (*((volatile unsigned long *)0x40030034))
+#define TIMER0_TAPR_R           (*((volatile unsigned long *)0x40030038))
+#define TIMER0_TBPR_R           (*((volatile unsigned long *)0x4003003C))
+#define TIMER0_TAPMR_R          (*((volatile unsigned long *)0x40030040))
+#define TIMER0_TBPMR_R          (*((volatile unsigned long *)0x40030044))
+#define TIMER0_TAR_R            (*((volatile unsigned long *)0x40030048))
+#define TIMER0_TBR_R            (*((volatile unsigned long *)0x4003004C))
+#define TIMER0_TAV_R            (*((volatile unsigned long *)0x40030050))
+#define TIMER0_TBV_R            (*((volatile unsigned long *)0x40030054))
+
+//*****************************************************************************
+//
+// Timer registers (TIMER1)
+//
+//*****************************************************************************
+#define TIMER1_CFG_R            (*((volatile unsigned long *)0x40031000))
+#define TIMER1_TAMR_R           (*((volatile unsigned long *)0x40031004))
+#define TIMER1_TBMR_R           (*((volatile unsigned long *)0x40031008))
+#define TIMER1_CTL_R            (*((volatile unsigned long *)0x4003100C))
+#define TIMER1_IMR_R            (*((volatile unsigned long *)0x40031018))
+#define TIMER1_RIS_R            (*((volatile unsigned long *)0x4003101C))
+#define TIMER1_MIS_R            (*((volatile unsigned long *)0x40031020))
+#define TIMER1_ICR_R            (*((volatile unsigned long *)0x40031024))
+#define TIMER1_TAILR_R          (*((volatile unsigned long *)0x40031028))
+#define TIMER1_TBILR_R          (*((volatile unsigned long *)0x4003102C))
+#define TIMER1_TAMATCHR_R       (*((volatile unsigned long *)0x40031030))
+#define TIMER1_TBMATCHR_R       (*((volatile unsigned long *)0x40031034))
+#define TIMER1_TAPR_R           (*((volatile unsigned long *)0x40031038))
+#define TIMER1_TBPR_R           (*((volatile unsigned long *)0x4003103C))
+#define TIMER1_TAPMR_R          (*((volatile unsigned long *)0x40031040))
+#define TIMER1_TBPMR_R          (*((volatile unsigned long *)0x40031044))
+#define TIMER1_TAR_R            (*((volatile unsigned long *)0x40031048))
+#define TIMER1_TBR_R            (*((volatile unsigned long *)0x4003104C))
+#define TIMER1_TAV_R            (*((volatile unsigned long *)0x40031050))
+#define TIMER1_TBV_R            (*((volatile unsigned long *)0x40031054))
+
+//*****************************************************************************
+//
+// Timer registers (TIMER2)
+//
+//*****************************************************************************
+#define TIMER2_CFG_R            (*((volatile unsigned long *)0x40032000))
+#define TIMER2_TAMR_R           (*((volatile unsigned long *)0x40032004))
+#define TIMER2_TBMR_R           (*((volatile unsigned long *)0x40032008))
+#define TIMER2_CTL_R            (*((volatile unsigned long *)0x4003200C))
+#define TIMER2_IMR_R            (*((volatile unsigned long *)0x40032018))
+#define TIMER2_RIS_R            (*((volatile unsigned long *)0x4003201C))
+#define TIMER2_MIS_R            (*((volatile unsigned long *)0x40032020))
+#define TIMER2_ICR_R            (*((volatile unsigned long *)0x40032024))
+#define TIMER2_TAILR_R          (*((volatile unsigned long *)0x40032028))
+#define TIMER2_TBILR_R          (*((volatile unsigned long *)0x4003202C))
+#define TIMER2_TAMATCHR_R       (*((volatile unsigned long *)0x40032030))
+#define TIMER2_TBMATCHR_R       (*((volatile unsigned long *)0x40032034))
+#define TIMER2_TAPR_R           (*((volatile unsigned long *)0x40032038))
+#define TIMER2_TBPR_R           (*((volatile unsigned long *)0x4003203C))
+#define TIMER2_TAPMR_R          (*((volatile unsigned long *)0x40032040))
+#define TIMER2_TBPMR_R          (*((volatile unsigned long *)0x40032044))
+#define TIMER2_TAR_R            (*((volatile unsigned long *)0x40032048))
+#define TIMER2_TBR_R            (*((volatile unsigned long *)0x4003204C))
+#define TIMER2_TAV_R            (*((volatile unsigned long *)0x40032050))
+#define TIMER2_TBV_R            (*((volatile unsigned long *)0x40032054))
+
+//*****************************************************************************
+//
+// Timer registers (TIMER3)
+//
+//*****************************************************************************
+#define TIMER3_CFG_R            (*((volatile unsigned long *)0x40033000))
+#define TIMER3_TAMR_R           (*((volatile unsigned long *)0x40033004))
+#define TIMER3_TBMR_R           (*((volatile unsigned long *)0x40033008))
+#define TIMER3_CTL_R            (*((volatile unsigned long *)0x4003300C))
+#define TIMER3_IMR_R            (*((volatile unsigned long *)0x40033018))
+#define TIMER3_RIS_R            (*((volatile unsigned long *)0x4003301C))
+#define TIMER3_MIS_R            (*((volatile unsigned long *)0x40033020))
+#define TIMER3_ICR_R            (*((volatile unsigned long *)0x40033024))
+#define TIMER3_TAILR_R          (*((volatile unsigned long *)0x40033028))
+#define TIMER3_TBILR_R          (*((volatile unsigned long *)0x4003302C))
+#define TIMER3_TAMATCHR_R       (*((volatile unsigned long *)0x40033030))
+#define TIMER3_TBMATCHR_R       (*((volatile unsigned long *)0x40033034))
+#define TIMER3_TAPR_R           (*((volatile unsigned long *)0x40033038))
+#define TIMER3_TBPR_R           (*((volatile unsigned long *)0x4003303C))
+#define TIMER3_TAPMR_R          (*((volatile unsigned long *)0x40033040))
+#define TIMER3_TBPMR_R          (*((volatile unsigned long *)0x40033044))
+#define TIMER3_TAR_R            (*((volatile unsigned long *)0x40033048))
+#define TIMER3_TBR_R            (*((volatile unsigned long *)0x4003304C))
+#define TIMER3_TAV_R            (*((volatile unsigned long *)0x40033050))
+#define TIMER3_TBV_R            (*((volatile unsigned long *)0x40033054))
+
+//*****************************************************************************
+//
+// ADC registers (ADC0)
+//
+//*****************************************************************************
+#define ADC0_ACTSS_R            (*((volatile unsigned long *)0x40038000))
+#define ADC0_RIS_R              (*((volatile unsigned long *)0x40038004))
+#define ADC0_IM_R               (*((volatile unsigned long *)0x40038008))
+#define ADC0_ISC_R              (*((volatile unsigned long *)0x4003800C))
+#define ADC0_OSTAT_R            (*((volatile unsigned long *)0x40038010))
+#define ADC0_EMUX_R             (*((volatile unsigned long *)0x40038014))
+#define ADC0_USTAT_R            (*((volatile unsigned long *)0x40038018))
+#define ADC0_SSPRI_R            (*((volatile unsigned long *)0x40038020))
+#define ADC0_SPC_R              (*((volatile unsigned long *)0x40038024))
+#define ADC0_PSSI_R             (*((volatile unsigned long *)0x40038028))
+#define ADC0_SAC_R              (*((volatile unsigned long *)0x40038030))
+#define ADC0_DCISC_R            (*((volatile unsigned long *)0x40038034))
+#define ADC0_CTL_R              (*((volatile unsigned long *)0x40038038))
+#define ADC0_SSMUX0_R           (*((volatile unsigned long *)0x40038040))
+#define ADC0_SSCTL0_R           (*((volatile unsigned long *)0x40038044))
+#define ADC0_SSFIFO0_R          (*((volatile unsigned long *)0x40038048))
+#define ADC0_SSFSTAT0_R         (*((volatile unsigned long *)0x4003804C))
+#define ADC0_SSOP0_R            (*((volatile unsigned long *)0x40038050))
+#define ADC0_SSDC0_R            (*((volatile unsigned long *)0x40038054))
+#define ADC0_SSMUX1_R           (*((volatile unsigned long *)0x40038060))
+#define ADC0_SSCTL1_R           (*((volatile unsigned long *)0x40038064))
+#define ADC0_SSFIFO1_R          (*((volatile unsigned long *)0x40038068))
+#define ADC0_SSFSTAT1_R         (*((volatile unsigned long *)0x4003806C))
+#define ADC0_SSOP1_R            (*((volatile unsigned long *)0x40038070))
+#define ADC0_SSDC1_R            (*((volatile unsigned long *)0x40038074))
+#define ADC0_SSMUX2_R           (*((volatile unsigned long *)0x40038080))
+#define ADC0_SSCTL2_R           (*((volatile unsigned long *)0x40038084))
+#define ADC0_SSFIFO2_R          (*((volatile unsigned long *)0x40038088))
+#define ADC0_SSFSTAT2_R         (*((volatile unsigned long *)0x4003808C))
+#define ADC0_SSOP2_R            (*((volatile unsigned long *)0x40038090))
+#define ADC0_SSDC2_R            (*((volatile unsigned long *)0x40038094))
+#define ADC0_SSMUX3_R           (*((volatile unsigned long *)0x400380A0))
+#define ADC0_SSCTL3_R           (*((volatile unsigned long *)0x400380A4))
+#define ADC0_SSFIFO3_R          (*((volatile unsigned long *)0x400380A8))
+#define ADC0_SSFSTAT3_R         (*((volatile unsigned long *)0x400380AC))
+#define ADC0_SSOP3_R            (*((volatile unsigned long *)0x400380B0))
+#define ADC0_SSDC3_R            (*((volatile unsigned long *)0x400380B4))
+#define ADC0_DCRIC_R            (*((volatile unsigned long *)0x40038D00))
+#define ADC0_DCCTL0_R           (*((volatile unsigned long *)0x40038E00))
+#define ADC0_DCCTL1_R           (*((volatile unsigned long *)0x40038E04))
+#define ADC0_DCCTL2_R           (*((volatile unsigned long *)0x40038E08))
+#define ADC0_DCCTL3_R           (*((volatile unsigned long *)0x40038E0C))
+#define ADC0_DCCTL4_R           (*((volatile unsigned long *)0x40038E10))
+#define ADC0_DCCTL5_R           (*((volatile unsigned long *)0x40038E14))
+#define ADC0_DCCTL6_R           (*((volatile unsigned long *)0x40038E18))
+#define ADC0_DCCTL7_R           (*((volatile unsigned long *)0x40038E1C))
+#define ADC0_DCCMP0_R           (*((volatile unsigned long *)0x40038E40))
+#define ADC0_DCCMP1_R           (*((volatile unsigned long *)0x40038E44))
+#define ADC0_DCCMP2_R           (*((volatile unsigned long *)0x40038E48))
+#define ADC0_DCCMP3_R           (*((volatile unsigned long *)0x40038E4C))
+#define ADC0_DCCMP4_R           (*((volatile unsigned long *)0x40038E50))
+#define ADC0_DCCMP5_R           (*((volatile unsigned long *)0x40038E54))
+#define ADC0_DCCMP6_R           (*((volatile unsigned long *)0x40038E58))
+#define ADC0_DCCMP7_R           (*((volatile unsigned long *)0x40038E5C))
+
+//*****************************************************************************
+//
+// ADC registers (ADC1)
+//
+//*****************************************************************************
+#define ADC1_ACTSS_R            (*((volatile unsigned long *)0x40039000))
+#define ADC1_RIS_R              (*((volatile unsigned long *)0x40039004))
+#define ADC1_IM_R               (*((volatile unsigned long *)0x40039008))
+#define ADC1_ISC_R              (*((volatile unsigned long *)0x4003900C))
+#define ADC1_OSTAT_R            (*((volatile unsigned long *)0x40039010))
+#define ADC1_EMUX_R             (*((volatile unsigned long *)0x40039014))
+#define ADC1_USTAT_R            (*((volatile unsigned long *)0x40039018))
+#define ADC1_SSPRI_R            (*((volatile unsigned long *)0x40039020))
+#define ADC1_SPC_R              (*((volatile unsigned long *)0x40039024))
+#define ADC1_PSSI_R             (*((volatile unsigned long *)0x40039028))
+#define ADC1_SAC_R              (*((volatile unsigned long *)0x40039030))
+#define ADC1_DCISC_R            (*((volatile unsigned long *)0x40039034))
+#define ADC1_CTL_R              (*((volatile unsigned long *)0x40039038))
+#define ADC1_SSMUX0_R           (*((volatile unsigned long *)0x40039040))
+#define ADC1_SSCTL0_R           (*((volatile unsigned long *)0x40039044))
+#define ADC1_SSFIFO0_R          (*((volatile unsigned long *)0x40039048))
+#define ADC1_SSFSTAT0_R         (*((volatile unsigned long *)0x4003904C))
+#define ADC1_SSOP0_R            (*((volatile unsigned long *)0x40039050))
+#define ADC1_SSDC0_R            (*((volatile unsigned long *)0x40039054))
+#define ADC1_SSMUX1_R           (*((volatile unsigned long *)0x40039060))
+#define ADC1_SSCTL1_R           (*((volatile unsigned long *)0x40039064))
+#define ADC1_SSFIFO1_R          (*((volatile unsigned long *)0x40039068))
+#define ADC1_SSFSTAT1_R         (*((volatile unsigned long *)0x4003906C))
+#define ADC1_SSOP1_R            (*((volatile unsigned long *)0x40039070))
+#define ADC1_SSDC1_R            (*((volatile unsigned long *)0x40039074))
+#define ADC1_SSMUX2_R           (*((volatile unsigned long *)0x40039080))
+#define ADC1_SSCTL2_R           (*((volatile unsigned long *)0x40039084))
+#define ADC1_SSFIFO2_R          (*((volatile unsigned long *)0x40039088))
+#define ADC1_SSFSTAT2_R         (*((volatile unsigned long *)0x4003908C))
+#define ADC1_SSOP2_R            (*((volatile unsigned long *)0x40039090))
+#define ADC1_SSDC2_R            (*((volatile unsigned long *)0x40039094))
+#define ADC1_SSMUX3_R           (*((volatile unsigned long *)0x400390A0))
+#define ADC1_SSCTL3_R           (*((volatile unsigned long *)0x400390A4))
+#define ADC1_SSFIFO3_R          (*((volatile unsigned long *)0x400390A8))
+#define ADC1_SSFSTAT3_R         (*((volatile unsigned long *)0x400390AC))
+#define ADC1_SSOP3_R            (*((volatile unsigned long *)0x400390B0))
+#define ADC1_SSDC3_R            (*((volatile unsigned long *)0x400390B4))
+#define ADC1_DCRIC_R            (*((volatile unsigned long *)0x40039D00))
+#define ADC1_DCCTL0_R           (*((volatile unsigned long *)0x40039E00))
+#define ADC1_DCCTL1_R           (*((volatile unsigned long *)0x40039E04))
+#define ADC1_DCCTL2_R           (*((volatile unsigned long *)0x40039E08))
+#define ADC1_DCCTL3_R           (*((volatile unsigned long *)0x40039E0C))
+#define ADC1_DCCTL4_R           (*((volatile unsigned long *)0x40039E10))
+#define ADC1_DCCTL5_R           (*((volatile unsigned long *)0x40039E14))
+#define ADC1_DCCTL6_R           (*((volatile unsigned long *)0x40039E18))
+#define ADC1_DCCTL7_R           (*((volatile unsigned long *)0x40039E1C))
+#define ADC1_DCCMP0_R           (*((volatile unsigned long *)0x40039E40))
+#define ADC1_DCCMP1_R           (*((volatile unsigned long *)0x40039E44))
+#define ADC1_DCCMP2_R           (*((volatile unsigned long *)0x40039E48))
+#define ADC1_DCCMP3_R           (*((volatile unsigned long *)0x40039E4C))
+#define ADC1_DCCMP4_R           (*((volatile unsigned long *)0x40039E50))
+#define ADC1_DCCMP5_R           (*((volatile unsigned long *)0x40039E54))
+#define ADC1_DCCMP6_R           (*((volatile unsigned long *)0x40039E58))
+#define ADC1_DCCMP7_R           (*((volatile unsigned long *)0x40039E5C))
+
+//*****************************************************************************
+//
+// Comparator registers (COMP)
+//
+//*****************************************************************************
+#define COMP_ACMIS_R            (*((volatile unsigned long *)0x4003C000))
+#define COMP_ACRIS_R            (*((volatile unsigned long *)0x4003C004))
+#define COMP_ACINTEN_R          (*((volatile unsigned long *)0x4003C008))
+#define COMP_ACREFCTL_R         (*((volatile unsigned long *)0x4003C010))
+#define COMP_ACSTAT0_R          (*((volatile unsigned long *)0x4003C020))
+#define COMP_ACCTL0_R           (*((volatile unsigned long *)0x4003C024))
+#define COMP_ACSTAT1_R          (*((volatile unsigned long *)0x4003C040))
+#define COMP_ACCTL1_R           (*((volatile unsigned long *)0x4003C044))
+#define COMP_ACSTAT2_R          (*((volatile unsigned long *)0x4003C060))
+#define COMP_ACCTL2_R           (*((volatile unsigned long *)0x4003C064))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTJ)
+//
+//*****************************************************************************
+#define GPIO_PORTJ_DATA_BITS_R  ((volatile unsigned long *)0x4003D000)
+#define GPIO_PORTJ_DATA_R       (*((volatile unsigned long *)0x4003D3FC))
+#define GPIO_PORTJ_DIR_R        (*((volatile unsigned long *)0x4003D400))
+#define GPIO_PORTJ_IS_R         (*((volatile unsigned long *)0x4003D404))
+#define GPIO_PORTJ_IBE_R        (*((volatile unsigned long *)0x4003D408))
+#define GPIO_PORTJ_IEV_R        (*((volatile unsigned long *)0x4003D40C))
+#define GPIO_PORTJ_IM_R         (*((volatile unsigned long *)0x4003D410))
+#define GPIO_PORTJ_RIS_R        (*((volatile unsigned long *)0x4003D414))
+#define GPIO_PORTJ_MIS_R        (*((volatile unsigned long *)0x4003D418))
+#define GPIO_PORTJ_ICR_R        (*((volatile unsigned long *)0x4003D41C))
+#define GPIO_PORTJ_AFSEL_R      (*((volatile unsigned long *)0x4003D420))
+#define GPIO_PORTJ_DR2R_R       (*((volatile unsigned long *)0x4003D500))
+#define GPIO_PORTJ_DR4R_R       (*((volatile unsigned long *)0x4003D504))
+#define GPIO_PORTJ_DR8R_R       (*((volatile unsigned long *)0x4003D508))
+#define GPIO_PORTJ_ODR_R        (*((volatile unsigned long *)0x4003D50C))
+#define GPIO_PORTJ_PUR_R        (*((volatile unsigned long *)0x4003D510))
+#define GPIO_PORTJ_PDR_R        (*((volatile unsigned long *)0x4003D514))
+#define GPIO_PORTJ_SLR_R        (*((volatile unsigned long *)0x4003D518))
+#define GPIO_PORTJ_DEN_R        (*((volatile unsigned long *)0x4003D51C))
+#define GPIO_PORTJ_LOCK_R       (*((volatile unsigned long *)0x4003D520))
+#define GPIO_PORTJ_CR_R         (*((volatile unsigned long *)0x4003D524))
+#define GPIO_PORTJ_AMSEL_R      (*((volatile unsigned long *)0x4003D528))
+#define GPIO_PORTJ_PCTL_R       (*((volatile unsigned long *)0x4003D52C))
+
+//*****************************************************************************
+//
+// CAN registers (CAN0)
+//
+//*****************************************************************************
+#define CAN0_CTL_R              (*((volatile unsigned long *)0x40040000))
+#define CAN0_STS_R              (*((volatile unsigned long *)0x40040004))
+#define CAN0_ERR_R              (*((volatile unsigned long *)0x40040008))
+#define CAN0_BIT_R              (*((volatile unsigned long *)0x4004000C))
+#define CAN0_INT_R              (*((volatile unsigned long *)0x40040010))
+#define CAN0_TST_R              (*((volatile unsigned long *)0x40040014))
+#define CAN0_BRPE_R             (*((volatile unsigned long *)0x40040018))
+#define CAN0_IF1CRQ_R           (*((volatile unsigned long *)0x40040020))
+#define CAN0_IF1CMSK_R          (*((volatile unsigned long *)0x40040024))
+#define CAN0_IF1MSK1_R          (*((volatile unsigned long *)0x40040028))
+#define CAN0_IF1MSK2_R          (*((volatile unsigned long *)0x4004002C))
+#define CAN0_IF1ARB1_R          (*((volatile unsigned long *)0x40040030))
+#define CAN0_IF1ARB2_R          (*((volatile unsigned long *)0x40040034))
+#define CAN0_IF1MCTL_R          (*((volatile unsigned long *)0x40040038))
+#define CAN0_IF1DA1_R           (*((volatile unsigned long *)0x4004003C))
+#define CAN0_IF1DA2_R           (*((volatile unsigned long *)0x40040040))
+#define CAN0_IF1DB1_R           (*((volatile unsigned long *)0x40040044))
+#define CAN0_IF1DB2_R           (*((volatile unsigned long *)0x40040048))
+#define CAN0_IF2CRQ_R           (*((volatile unsigned long *)0x40040080))
+#define CAN0_IF2CMSK_R          (*((volatile unsigned long *)0x40040084))
+#define CAN0_IF2MSK1_R          (*((volatile unsigned long *)0x40040088))
+#define CAN0_IF2MSK2_R          (*((volatile unsigned long *)0x4004008C))
+#define CAN0_IF2ARB1_R          (*((volatile unsigned long *)0x40040090))
+#define CAN0_IF2ARB2_R          (*((volatile unsigned long *)0x40040094))
+#define CAN0_IF2MCTL_R          (*((volatile unsigned long *)0x40040098))
+#define CAN0_IF2DA1_R           (*((volatile unsigned long *)0x4004009C))
+#define CAN0_IF2DA2_R           (*((volatile unsigned long *)0x400400A0))
+#define CAN0_IF2DB1_R           (*((volatile unsigned long *)0x400400A4))
+#define CAN0_IF2DB2_R           (*((volatile unsigned long *)0x400400A8))
+#define CAN0_TXRQ1_R            (*((volatile unsigned long *)0x40040100))
+#define CAN0_TXRQ2_R            (*((volatile unsigned long *)0x40040104))
+#define CAN0_NWDA1_R            (*((volatile unsigned long *)0x40040120))
+#define CAN0_NWDA2_R            (*((volatile unsigned long *)0x40040124))
+#define CAN0_MSG1INT_R          (*((volatile unsigned long *)0x40040140))
+#define CAN0_MSG2INT_R          (*((volatile unsigned long *)0x40040144))
+#define CAN0_MSG1VAL_R          (*((volatile unsigned long *)0x40040160))
+#define CAN0_MSG2VAL_R          (*((volatile unsigned long *)0x40040164))
+
+//*****************************************************************************
+//
+// CAN registers (CAN1)
+//
+//*****************************************************************************
+#define CAN1_CTL_R              (*((volatile unsigned long *)0x40041000))
+#define CAN1_STS_R              (*((volatile unsigned long *)0x40041004))
+#define CAN1_ERR_R              (*((volatile unsigned long *)0x40041008))
+#define CAN1_BIT_R              (*((volatile unsigned long *)0x4004100C))
+#define CAN1_INT_R              (*((volatile unsigned long *)0x40041010))
+#define CAN1_TST_R              (*((volatile unsigned long *)0x40041014))
+#define CAN1_BRPE_R             (*((volatile unsigned long *)0x40041018))
+#define CAN1_IF1CRQ_R           (*((volatile unsigned long *)0x40041020))
+#define CAN1_IF1CMSK_R          (*((volatile unsigned long *)0x40041024))
+#define CAN1_IF1MSK1_R          (*((volatile unsigned long *)0x40041028))
+#define CAN1_IF1MSK2_R          (*((volatile unsigned long *)0x4004102C))
+#define CAN1_IF1ARB1_R          (*((volatile unsigned long *)0x40041030))
+#define CAN1_IF1ARB2_R          (*((volatile unsigned long *)0x40041034))
+#define CAN1_IF1MCTL_R          (*((volatile unsigned long *)0x40041038))
+#define CAN1_IF1DA1_R           (*((volatile unsigned long *)0x4004103C))
+#define CAN1_IF1DA2_R           (*((volatile unsigned long *)0x40041040))
+#define CAN1_IF1DB1_R           (*((volatile unsigned long *)0x40041044))
+#define CAN1_IF1DB2_R           (*((volatile unsigned long *)0x40041048))
+#define CAN1_IF2CRQ_R           (*((volatile unsigned long *)0x40041080))
+#define CAN1_IF2CMSK_R          (*((volatile unsigned long *)0x40041084))
+#define CAN1_IF2MSK1_R          (*((volatile unsigned long *)0x40041088))
+#define CAN1_IF2MSK2_R          (*((volatile unsigned long *)0x4004108C))
+#define CAN1_IF2ARB1_R          (*((volatile unsigned long *)0x40041090))
+#define CAN1_IF2ARB2_R          (*((volatile unsigned long *)0x40041094))
+#define CAN1_IF2MCTL_R          (*((volatile unsigned long *)0x40041098))
+#define CAN1_IF2DA1_R           (*((volatile unsigned long *)0x4004109C))
+#define CAN1_IF2DA2_R           (*((volatile unsigned long *)0x400410A0))
+#define CAN1_IF2DB1_R           (*((volatile unsigned long *)0x400410A4))
+#define CAN1_IF2DB2_R           (*((volatile unsigned long *)0x400410A8))
+#define CAN1_TXRQ1_R            (*((volatile unsigned long *)0x40041100))
+#define CAN1_TXRQ2_R            (*((volatile unsigned long *)0x40041104))
+#define CAN1_NWDA1_R            (*((volatile unsigned long *)0x40041120))
+#define CAN1_NWDA2_R            (*((volatile unsigned long *)0x40041124))
+#define CAN1_MSG1INT_R          (*((volatile unsigned long *)0x40041140))
+#define CAN1_MSG2INT_R          (*((volatile unsigned long *)0x40041144))
+#define CAN1_MSG1VAL_R          (*((volatile unsigned long *)0x40041160))
+#define CAN1_MSG2VAL_R          (*((volatile unsigned long *)0x40041164))
+
+//*****************************************************************************
+//
+// Ethernet MAC registers (MAC)
+//
+//*****************************************************************************
+#define MAC_RIS_R               (*((volatile unsigned long *)0x40048000))
+#define MAC_IM_R                (*((volatile unsigned long *)0x40048004))
+#define MAC_RCTL_R              (*((volatile unsigned long *)0x40048008))
+#define MAC_TCTL_R              (*((volatile unsigned long *)0x4004800C))
+#define MAC_DATA_R              (*((volatile unsigned long *)0x40048010))
+#define MAC_IA0_R               (*((volatile unsigned long *)0x40048014))
+#define MAC_IA1_R               (*((volatile unsigned long *)0x40048018))
+#define MAC_THR_R               (*((volatile unsigned long *)0x4004801C))
+#define MAC_MCTL_R              (*((volatile unsigned long *)0x40048020))
+#define MAC_MDV_R               (*((volatile unsigned long *)0x40048024))
+#define MAC_MTXD_R              (*((volatile unsigned long *)0x4004802C))
+#define MAC_MRXD_R              (*((volatile unsigned long *)0x40048030))
+#define MAC_NP_R                (*((volatile unsigned long *)0x40048034))
+#define MAC_TR_R                (*((volatile unsigned long *)0x40048038))
+#define MAC_TS_R                (*((volatile unsigned long *)0x4004803C))
+#define MAC_LED_R               (*((volatile unsigned long *)0x40048040))
+#define MAC_MDIX_R              (*((volatile unsigned long *)0x40048044))
+
+//*****************************************************************************
+//
+// Ethernet Controller PHY registers (MAC)
+//
+//*****************************************************************************
+#define PHY_MR0                 0x00000000  // Ethernet PHY Management Register
+                                            // 0 - Control
+#define PHY_MR1                 0x00000001  // Ethernet PHY Management Register
+                                            // 1 - Status
+#define PHY_MR2                 0x00000002  // Ethernet PHY Management Register
+                                            // 2 - PHY Identifier 1
+#define PHY_MR3                 0x00000003  // Ethernet PHY Management Register
+                                            // 3 - PHY Identifier 2
+#define PHY_MR4                 0x00000004  // Ethernet PHY Management Register
+                                            // 4 - Auto-Negotiation
+                                            // Advertisement
+#define PHY_MR5                 0x00000005  // Ethernet PHY Management Register
+                                            // 5 - Auto-Negotiation Link
+                                            // Partner Base Page Ability
+#define PHY_MR6                 0x00000006  // Ethernet PHY Management Register
+                                            // 6 - Auto-Negotiation Expansion
+#define PHY_MR16                0x00000010  // Ethernet PHY Management Register
+                                            // 16 - Vendor-Specific
+#define PHY_MR17                0x00000011  // Ethernet PHY Management Register
+                                            // 17 - Mode Control/Status
+#define PHY_MR27                0x0000001B  // Ethernet PHY Management Register
+                                            // 27 - Special Control/Status
+#define PHY_MR29                0x0000001D  // Ethernet PHY Management Register
+                                            // 29 - Interrupt Status
+#define PHY_MR30                0x0000001E  // Ethernet PHY Management Register
+                                            // 30 - Interrupt Mask
+#define PHY_MR31                0x0000001F  // Ethernet PHY Management Register
+                                            // 31 - PHY Special Control/Status
+
+//*****************************************************************************
+//
+// Univeral Serial Bus registers (USB0)
+//
+//*****************************************************************************
+#define USB0_FADDR_R            (*((volatile unsigned char *)0x40050000))
+#define USB0_POWER_R            (*((volatile unsigned char *)0x40050001))
+#define USB0_TXIS_R             (*((volatile unsigned short *)0x40050002))
+#define USB0_RXIS_R             (*((volatile unsigned short *)0x40050004))
+#define USB0_TXIE_R             (*((volatile unsigned short *)0x40050006))
+#define USB0_RXIE_R             (*((volatile unsigned short *)0x40050008))
+#define USB0_IS_R               (*((volatile unsigned char *)0x4005000A))
+#define USB0_IE_R               (*((volatile unsigned char *)0x4005000B))
+#define USB0_FRAME_R            (*((volatile unsigned short *)0x4005000C))
+#define USB0_EPIDX_R            (*((volatile unsigned char *)0x4005000E))
+#define USB0_TEST_R             (*((volatile unsigned char *)0x4005000F))
+#define USB0_FIFO0_R            (*((volatile unsigned long *)0x40050020))
+#define USB0_FIFO1_R            (*((volatile unsigned long *)0x40050024))
+#define USB0_FIFO2_R            (*((volatile unsigned long *)0x40050028))
+#define USB0_FIFO3_R            (*((volatile unsigned long *)0x4005002C))
+#define USB0_FIFO4_R            (*((volatile unsigned long *)0x40050030))
+#define USB0_FIFO5_R            (*((volatile unsigned long *)0x40050034))
+#define USB0_FIFO6_R            (*((volatile unsigned long *)0x40050038))
+#define USB0_FIFO7_R            (*((volatile unsigned long *)0x4005003C))
+#define USB0_FIFO8_R            (*((volatile unsigned long *)0x40050040))
+#define USB0_FIFO9_R            (*((volatile unsigned long *)0x40050044))
+#define USB0_FIFO10_R           (*((volatile unsigned long *)0x40050048))
+#define USB0_FIFO11_R           (*((volatile unsigned long *)0x4005004C))
+#define USB0_FIFO12_R           (*((volatile unsigned long *)0x40050050))
+#define USB0_FIFO13_R           (*((volatile unsigned long *)0x40050054))
+#define USB0_FIFO14_R           (*((volatile unsigned long *)0x40050058))
+#define USB0_FIFO15_R           (*((volatile unsigned long *)0x4005005C))
+#define USB0_DEVCTL_R           (*((volatile unsigned char *)0x40050060))
+#define USB0_TXFIFOSZ_R         (*((volatile unsigned char *)0x40050062))
+#define USB0_RXFIFOSZ_R         (*((volatile unsigned char *)0x40050063))
+#define USB0_TXFIFOADD_R        (*((volatile unsigned short *)0x40050064))
+#define USB0_RXFIFOADD_R        (*((volatile unsigned short *)0x40050066))
+#define USB0_CONTIM_R           (*((volatile unsigned char *)0x4005007A))
+#define USB0_VPLEN_R            (*((volatile unsigned char *)0x4005007B))
+#define USB0_FSEOF_R            (*((volatile unsigned char *)0x4005007D))
+#define USB0_LSEOF_R            (*((volatile unsigned char *)0x4005007E))
+#define USB0_TXFUNCADDR0_R      (*((volatile unsigned char *)0x40050080))
+#define USB0_TXHUBADDR0_R       (*((volatile unsigned char *)0x40050082))
+#define USB0_TXHUBPORT0_R       (*((volatile unsigned char *)0x40050083))
+#define USB0_TXFUNCADDR1_R      (*((volatile unsigned char *)0x40050088))
+#define USB0_TXHUBADDR1_R       (*((volatile unsigned char *)0x4005008A))
+#define USB0_TXHUBPORT1_R       (*((volatile unsigned char *)0x4005008B))
+#define USB0_RXFUNCADDR1_R      (*((volatile unsigned char *)0x4005008C))
+#define USB0_RXHUBADDR1_R       (*((volatile unsigned char *)0x4005008E))
+#define USB0_RXHUBPORT1_R       (*((volatile unsigned char *)0x4005008F))
+#define USB0_TXFUNCADDR2_R      (*((volatile unsigned char *)0x40050090))
+#define USB0_TXHUBADDR2_R       (*((volatile unsigned char *)0x40050092))
+#define USB0_TXHUBPORT2_R       (*((volatile unsigned char *)0x40050093))
+#define USB0_RXFUNCADDR2_R      (*((volatile unsigned char *)0x40050094))
+#define USB0_RXHUBADDR2_R       (*((volatile unsigned char *)0x40050096))
+#define USB0_RXHUBPORT2_R       (*((volatile unsigned char *)0x40050097))
+#define USB0_TXFUNCADDR3_R      (*((volatile unsigned char *)0x40050098))
+#define USB0_TXHUBADDR3_R       (*((volatile unsigned char *)0x4005009A))
+#define USB0_TXHUBPORT3_R       (*((volatile unsigned char *)0x4005009B))
+#define USB0_RXFUNCADDR3_R      (*((volatile unsigned char *)0x4005009C))
+#define USB0_RXHUBADDR3_R       (*((volatile unsigned char *)0x4005009E))
+#define USB0_RXHUBPORT3_R       (*((volatile unsigned char *)0x4005009F))
+#define USB0_TXFUNCADDR4_R      (*((volatile unsigned char *)0x400500A0))
+#define USB0_TXHUBADDR4_R       (*((volatile unsigned char *)0x400500A2))
+#define USB0_TXHUBPORT4_R       (*((volatile unsigned char *)0x400500A3))
+#define USB0_RXFUNCADDR4_R      (*((volatile unsigned char *)0x400500A4))
+#define USB0_RXHUBADDR4_R       (*((volatile unsigned char *)0x400500A6))
+#define USB0_RXHUBPORT4_R       (*((volatile unsigned char *)0x400500A7))
+#define USB0_TXFUNCADDR5_R      (*((volatile unsigned char *)0x400500A8))
+#define USB0_TXHUBADDR5_R       (*((volatile unsigned char *)0x400500AA))
+#define USB0_TXHUBPORT5_R       (*((volatile unsigned char *)0x400500AB))
+#define USB0_RXFUNCADDR5_R      (*((volatile unsigned char *)0x400500AC))
+#define USB0_RXHUBADDR5_R       (*((volatile unsigned char *)0x400500AE))
+#define USB0_RXHUBPORT5_R       (*((volatile unsigned char *)0x400500AF))
+#define USB0_TXFUNCADDR6_R      (*((volatile unsigned char *)0x400500B0))
+#define USB0_TXHUBADDR6_R       (*((volatile unsigned char *)0x400500B2))
+#define USB0_TXHUBPORT6_R       (*((volatile unsigned char *)0x400500B3))
+#define USB0_RXFUNCADDR6_R      (*((volatile unsigned char *)0x400500B4))
+#define USB0_RXHUBADDR6_R       (*((volatile unsigned char *)0x400500B6))
+#define USB0_RXHUBPORT6_R       (*((volatile unsigned char *)0x400500B7))
+#define USB0_TXFUNCADDR7_R      (*((volatile unsigned char *)0x400500B8))
+#define USB0_TXHUBADDR7_R       (*((volatile unsigned char *)0x400500BA))
+#define USB0_TXHUBPORT7_R       (*((volatile unsigned char *)0x400500BB))
+#define USB0_RXFUNCADDR7_R      (*((volatile unsigned char *)0x400500BC))
+#define USB0_RXHUBADDR7_R       (*((volatile unsigned char *)0x400500BE))
+#define USB0_RXHUBPORT7_R       (*((volatile unsigned char *)0x400500BF))
+#define USB0_TXFUNCADDR8_R      (*((volatile unsigned char *)0x400500C0))
+#define USB0_TXHUBADDR8_R       (*((volatile unsigned char *)0x400500C2))
+#define USB0_TXHUBPORT8_R       (*((volatile unsigned char *)0x400500C3))
+#define USB0_RXFUNCADDR8_R      (*((volatile unsigned char *)0x400500C4))
+#define USB0_RXHUBADDR8_R       (*((volatile unsigned char *)0x400500C6))
+#define USB0_RXHUBPORT8_R       (*((volatile unsigned char *)0x400500C7))
+#define USB0_TXFUNCADDR9_R      (*((volatile unsigned char *)0x400500C8))
+#define USB0_TXHUBADDR9_R       (*((volatile unsigned char *)0x400500CA))
+#define USB0_TXHUBPORT9_R       (*((volatile unsigned char *)0x400500CB))
+#define USB0_RXFUNCADDR9_R      (*((volatile unsigned char *)0x400500CC))
+#define USB0_RXHUBADDR9_R       (*((volatile unsigned char *)0x400500CE))
+#define USB0_RXHUBPORT9_R       (*((volatile unsigned char *)0x400500CF))
+#define USB0_TXFUNCADDR10_R     (*((volatile unsigned char *)0x400500D0))
+#define USB0_TXHUBADDR10_R      (*((volatile unsigned char *)0x400500D2))
+#define USB0_TXHUBPORT10_R      (*((volatile unsigned char *)0x400500D3))
+#define USB0_RXFUNCADDR10_R     (*((volatile unsigned char *)0x400500D4))
+#define USB0_RXHUBADDR10_R      (*((volatile unsigned char *)0x400500D6))
+#define USB0_RXHUBPORT10_R      (*((volatile unsigned char *)0x400500D7))
+#define USB0_TXFUNCADDR11_R     (*((volatile unsigned char *)0x400500D8))
+#define USB0_TXHUBADDR11_R      (*((volatile unsigned char *)0x400500DA))
+#define USB0_TXHUBPORT11_R      (*((volatile unsigned char *)0x400500DB))
+#define USB0_RXFUNCADDR11_R     (*((volatile unsigned char *)0x400500DC))
+#define USB0_RXHUBADDR11_R      (*((volatile unsigned char *)0x400500DE))
+#define USB0_RXHUBPORT11_R      (*((volatile unsigned char *)0x400500DF))
+#define USB0_TXFUNCADDR12_R     (*((volatile unsigned char *)0x400500E0))
+#define USB0_TXHUBADDR12_R      (*((volatile unsigned char *)0x400500E2))
+#define USB0_TXHUBPORT12_R      (*((volatile unsigned char *)0x400500E3))
+#define USB0_RXFUNCADDR12_R     (*((volatile unsigned char *)0x400500E4))
+#define USB0_RXHUBADDR12_R      (*((volatile unsigned char *)0x400500E6))
+#define USB0_RXHUBPORT12_R      (*((volatile unsigned char *)0x400500E7))
+#define USB0_TXFUNCADDR13_R     (*((volatile unsigned char *)0x400500E8))
+#define USB0_TXHUBADDR13_R      (*((volatile unsigned char *)0x400500EA))
+#define USB0_TXHUBPORT13_R      (*((volatile unsigned char *)0x400500EB))
+#define USB0_RXFUNCADDR13_R     (*((volatile unsigned char *)0x400500EC))
+#define USB0_RXHUBADDR13_R      (*((volatile unsigned char *)0x400500EE))
+#define USB0_RXHUBPORT13_R      (*((volatile unsigned char *)0x400500EF))
+#define USB0_TXFUNCADDR14_R     (*((volatile unsigned char *)0x400500F0))
+#define USB0_TXHUBADDR14_R      (*((volatile unsigned char *)0x400500F2))
+#define USB0_TXHUBPORT14_R      (*((volatile unsigned char *)0x400500F3))
+#define USB0_RXFUNCADDR14_R     (*((volatile unsigned char *)0x400500F4))
+#define USB0_RXHUBADDR14_R      (*((volatile unsigned char *)0x400500F6))
+#define USB0_RXHUBPORT14_R      (*((volatile unsigned char *)0x400500F7))
+#define USB0_TXFUNCADDR15_R     (*((volatile unsigned char *)0x400500F8))
+#define USB0_TXHUBADDR15_R      (*((volatile unsigned char *)0x400500FA))
+#define USB0_TXHUBPORT15_R      (*((volatile unsigned char *)0x400500FB))
+#define USB0_RXFUNCADDR15_R     (*((volatile unsigned char *)0x400500FC))
+#define USB0_RXHUBADDR15_R      (*((volatile unsigned char *)0x400500FE))
+#define USB0_RXHUBPORT15_R      (*((volatile unsigned char *)0x400500FF))
+#define USB0_CSRL0_R            (*((volatile unsigned char *)0x40050102))
+#define USB0_CSRH0_R            (*((volatile unsigned char *)0x40050103))
+#define USB0_COUNT0_R           (*((volatile unsigned char *)0x40050108))
+#define USB0_TYPE0_R            (*((volatile unsigned char *)0x4005010A))
+#define USB0_NAKLMT_R           (*((volatile unsigned char *)0x4005010B))
+#define USB0_TXMAXP1_R          (*((volatile unsigned short *)0x40050110))
+#define USB0_TXCSRL1_R          (*((volatile unsigned char *)0x40050112))
+#define USB0_TXCSRH1_R          (*((volatile unsigned char *)0x40050113))
+#define USB0_RXMAXP1_R          (*((volatile unsigned short *)0x40050114))
+#define USB0_RXCSRL1_R          (*((volatile unsigned char *)0x40050116))
+#define USB0_RXCSRH1_R          (*((volatile unsigned char *)0x40050117))
+#define USB0_RXCOUNT1_R         (*((volatile unsigned short *)0x40050118))
+#define USB0_TXTYPE1_R          (*((volatile unsigned char *)0x4005011A))
+#define USB0_TXINTERVAL1_R      (*((volatile unsigned char *)0x4005011B))
+#define USB0_RXTYPE1_R          (*((volatile unsigned char *)0x4005011C))
+#define USB0_RXINTERVAL1_R      (*((volatile unsigned char *)0x4005011D))
+#define USB0_TXMAXP2_R          (*((volatile unsigned short *)0x40050120))
+#define USB0_TXCSRL2_R          (*((volatile unsigned char *)0x40050122))
+#define USB0_TXCSRH2_R          (*((volatile unsigned char *)0x40050123))
+#define USB0_RXMAXP2_R          (*((volatile unsigned short *)0x40050124))
+#define USB0_RXCSRL2_R          (*((volatile unsigned char *)0x40050126))
+#define USB0_RXCSRH2_R          (*((volatile unsigned char *)0x40050127))
+#define USB0_RXCOUNT2_R         (*((volatile unsigned short *)0x40050128))
+#define USB0_TXTYPE2_R          (*((volatile unsigned char *)0x4005012A))
+#define USB0_TXINTERVAL2_R      (*((volatile unsigned char *)0x4005012B))
+#define USB0_RXTYPE2_R          (*((volatile unsigned char *)0x4005012C))
+#define USB0_RXINTERVAL2_R      (*((volatile unsigned char *)0x4005012D))
+#define USB0_TXMAXP3_R          (*((volatile unsigned short *)0x40050130))
+#define USB0_TXCSRL3_R          (*((volatile unsigned char *)0x40050132))
+#define USB0_TXCSRH3_R          (*((volatile unsigned char *)0x40050133))
+#define USB0_RXMAXP3_R          (*((volatile unsigned short *)0x40050134))
+#define USB0_RXCSRL3_R          (*((volatile unsigned char *)0x40050136))
+#define USB0_RXCSRH3_R          (*((volatile unsigned char *)0x40050137))
+#define USB0_RXCOUNT3_R         (*((volatile unsigned short *)0x40050138))
+#define USB0_TXTYPE3_R          (*((volatile unsigned char *)0x4005013A))
+#define USB0_TXINTERVAL3_R      (*((volatile unsigned char *)0x4005013B))
+#define USB0_RXTYPE3_R          (*((volatile unsigned char *)0x4005013C))
+#define USB0_RXINTERVAL3_R      (*((volatile unsigned char *)0x4005013D))
+#define USB0_TXMAXP4_R          (*((volatile unsigned short *)0x40050140))
+#define USB0_TXCSRL4_R          (*((volatile unsigned char *)0x40050142))
+#define USB0_TXCSRH4_R          (*((volatile unsigned char *)0x40050143))
+#define USB0_RXMAXP4_R          (*((volatile unsigned short *)0x40050144))
+#define USB0_RXCSRL4_R          (*((volatile unsigned char *)0x40050146))
+#define USB0_RXCSRH4_R          (*((volatile unsigned char *)0x40050147))
+#define USB0_RXCOUNT4_R         (*((volatile unsigned short *)0x40050148))
+#define USB0_TXTYPE4_R          (*((volatile unsigned char *)0x4005014A))
+#define USB0_TXINTERVAL4_R      (*((volatile unsigned char *)0x4005014B))
+#define USB0_RXTYPE4_R          (*((volatile unsigned char *)0x4005014C))
+#define USB0_RXINTERVAL4_R      (*((volatile unsigned char *)0x4005014D))
+#define USB0_TXMAXP5_R          (*((volatile unsigned short *)0x40050150))
+#define USB0_TXCSRL5_R          (*((volatile unsigned char *)0x40050152))
+#define USB0_TXCSRH5_R          (*((volatile unsigned char *)0x40050153))
+#define USB0_RXMAXP5_R          (*((volatile unsigned short *)0x40050154))
+#define USB0_RXCSRL5_R          (*((volatile unsigned char *)0x40050156))
+#define USB0_RXCSRH5_R          (*((volatile unsigned char *)0x40050157))
+#define USB0_RXCOUNT5_R         (*((volatile unsigned short *)0x40050158))
+#define USB0_TXTYPE5_R          (*((volatile unsigned char *)0x4005015A))
+#define USB0_TXINTERVAL5_R      (*((volatile unsigned char *)0x4005015B))
+#define USB0_RXTYPE5_R          (*((volatile unsigned char *)0x4005015C))
+#define USB0_RXINTERVAL5_R      (*((volatile unsigned char *)0x4005015D))
+#define USB0_TXMAXP6_R          (*((volatile unsigned short *)0x40050160))
+#define USB0_TXCSRL6_R          (*((volatile unsigned char *)0x40050162))
+#define USB0_TXCSRH6_R          (*((volatile unsigned char *)0x40050163))
+#define USB0_RXMAXP6_R          (*((volatile unsigned short *)0x40050164))
+#define USB0_RXCSRL6_R          (*((volatile unsigned char *)0x40050166))
+#define USB0_RXCSRH6_R          (*((volatile unsigned char *)0x40050167))
+#define USB0_RXCOUNT6_R         (*((volatile unsigned short *)0x40050168))
+#define USB0_TXTYPE6_R          (*((volatile unsigned char *)0x4005016A))
+#define USB0_TXINTERVAL6_R      (*((volatile unsigned char *)0x4005016B))
+#define USB0_RXTYPE6_R          (*((volatile unsigned char *)0x4005016C))
+#define USB0_RXINTERVAL6_R      (*((volatile unsigned char *)0x4005016D))
+#define USB0_TXMAXP7_R          (*((volatile unsigned short *)0x40050170))
+#define USB0_TXCSRL7_R          (*((volatile unsigned char *)0x40050172))
+#define USB0_TXCSRH7_R          (*((volatile unsigned char *)0x40050173))
+#define USB0_RXMAXP7_R          (*((volatile unsigned short *)0x40050174))
+#define USB0_RXCSRL7_R          (*((volatile unsigned char *)0x40050176))
+#define USB0_RXCSRH7_R          (*((volatile unsigned char *)0x40050177))
+#define USB0_RXCOUNT7_R         (*((volatile unsigned short *)0x40050178))
+#define USB0_TXTYPE7_R          (*((volatile unsigned char *)0x4005017A))
+#define USB0_TXINTERVAL7_R      (*((volatile unsigned char *)0x4005017B))
+#define USB0_RXTYPE7_R          (*((volatile unsigned char *)0x4005017C))
+#define USB0_RXINTERVAL7_R      (*((volatile unsigned char *)0x4005017D))
+#define USB0_TXMAXP8_R          (*((volatile unsigned short *)0x40050180))
+#define USB0_TXCSRL8_R          (*((volatile unsigned char *)0x40050182))
+#define USB0_TXCSRH8_R          (*((volatile unsigned char *)0x40050183))
+#define USB0_RXMAXP8_R          (*((volatile unsigned short *)0x40050184))
+#define USB0_RXCSRL8_R          (*((volatile unsigned char *)0x40050186))
+#define USB0_RXCSRH8_R          (*((volatile unsigned char *)0x40050187))
+#define USB0_RXCOUNT8_R         (*((volatile unsigned short *)0x40050188))
+#define USB0_TXTYPE8_R          (*((volatile unsigned char *)0x4005018A))
+#define USB0_TXINTERVAL8_R      (*((volatile unsigned char *)0x4005018B))
+#define USB0_RXTYPE8_R          (*((volatile unsigned char *)0x4005018C))
+#define USB0_RXINTERVAL8_R      (*((volatile unsigned char *)0x4005018D))
+#define USB0_TXMAXP9_R          (*((volatile unsigned short *)0x40050190))
+#define USB0_TXCSRL9_R          (*((volatile unsigned char *)0x40050192))
+#define USB0_TXCSRH9_R          (*((volatile unsigned char *)0x40050193))
+#define USB0_RXMAXP9_R          (*((volatile unsigned short *)0x40050194))
+#define USB0_RXCSRL9_R          (*((volatile unsigned char *)0x40050196))
+#define USB0_RXCSRH9_R          (*((volatile unsigned char *)0x40050197))
+#define USB0_RXCOUNT9_R         (*((volatile unsigned short *)0x40050198))
+#define USB0_TXTYPE9_R          (*((volatile unsigned char *)0x4005019A))
+#define USB0_TXINTERVAL9_R      (*((volatile unsigned char *)0x4005019B))
+#define USB0_RXTYPE9_R          (*((volatile unsigned char *)0x4005019C))
+#define USB0_RXINTERVAL9_R      (*((volatile unsigned char *)0x4005019D))
+#define USB0_TXMAXP10_R         (*((volatile unsigned short *)0x400501A0))
+#define USB0_TXCSRL10_R         (*((volatile unsigned char *)0x400501A2))
+#define USB0_TXCSRH10_R         (*((volatile unsigned char *)0x400501A3))
+#define USB0_RXMAXP10_R         (*((volatile unsigned short *)0x400501A4))
+#define USB0_RXCSRL10_R         (*((volatile unsigned char *)0x400501A6))
+#define USB0_RXCSRH10_R         (*((volatile unsigned char *)0x400501A7))
+#define USB0_RXCOUNT10_R        (*((volatile unsigned short *)0x400501A8))
+#define USB0_TXTYPE10_R         (*((volatile unsigned char *)0x400501AA))
+#define USB0_TXINTERVAL10_R     (*((volatile unsigned char *)0x400501AB))
+#define USB0_RXTYPE10_R         (*((volatile unsigned char *)0x400501AC))
+#define USB0_RXINTERVAL10_R     (*((volatile unsigned char *)0x400501AD))
+#define USB0_TXMAXP11_R         (*((volatile unsigned short *)0x400501B0))
+#define USB0_TXCSRL11_R         (*((volatile unsigned char *)0x400501B2))
+#define USB0_TXCSRH11_R         (*((volatile unsigned char *)0x400501B3))
+#define USB0_RXMAXP11_R         (*((volatile unsigned short *)0x400501B4))
+#define USB0_RXCSRL11_R         (*((volatile unsigned char *)0x400501B6))
+#define USB0_RXCSRH11_R         (*((volatile unsigned char *)0x400501B7))
+#define USB0_RXCOUNT11_R        (*((volatile unsigned short *)0x400501B8))
+#define USB0_TXTYPE11_R         (*((volatile unsigned char *)0x400501BA))
+#define USB0_TXINTERVAL11_R     (*((volatile unsigned char *)0x400501BB))
+#define USB0_RXTYPE11_R         (*((volatile unsigned char *)0x400501BC))
+#define USB0_RXINTERVAL11_R     (*((volatile unsigned char *)0x400501BD))
+#define USB0_TXMAXP12_R         (*((volatile unsigned short *)0x400501C0))
+#define USB0_TXCSRL12_R         (*((volatile unsigned char *)0x400501C2))
+#define USB0_TXCSRH12_R         (*((volatile unsigned char *)0x400501C3))
+#define USB0_RXMAXP12_R         (*((volatile unsigned short *)0x400501C4))
+#define USB0_RXCSRL12_R         (*((volatile unsigned char *)0x400501C6))
+#define USB0_RXCSRH12_R         (*((volatile unsigned char *)0x400501C7))
+#define USB0_RXCOUNT12_R        (*((volatile unsigned short *)0x400501C8))
+#define USB0_TXTYPE12_R         (*((volatile unsigned char *)0x400501CA))
+#define USB0_TXINTERVAL12_R     (*((volatile unsigned char *)0x400501CB))
+#define USB0_RXTYPE12_R         (*((volatile unsigned char *)0x400501CC))
+#define USB0_RXINTERVAL12_R     (*((volatile unsigned char *)0x400501CD))
+#define USB0_TXMAXP13_R         (*((volatile unsigned short *)0x400501D0))
+#define USB0_TXCSRL13_R         (*((volatile unsigned char *)0x400501D2))
+#define USB0_TXCSRH13_R         (*((volatile unsigned char *)0x400501D3))
+#define USB0_RXMAXP13_R         (*((volatile unsigned short *)0x400501D4))
+#define USB0_RXCSRL13_R         (*((volatile unsigned char *)0x400501D6))
+#define USB0_RXCSRH13_R         (*((volatile unsigned char *)0x400501D7))
+#define USB0_RXCOUNT13_R        (*((volatile unsigned short *)0x400501D8))
+#define USB0_TXTYPE13_R         (*((volatile unsigned char *)0x400501DA))
+#define USB0_TXINTERVAL13_R     (*((volatile unsigned char *)0x400501DB))
+#define USB0_RXTYPE13_R         (*((volatile unsigned char *)0x400501DC))
+#define USB0_RXINTERVAL13_R     (*((volatile unsigned char *)0x400501DD))
+#define USB0_TXMAXP14_R         (*((volatile unsigned short *)0x400501E0))
+#define USB0_TXCSRL14_R         (*((volatile unsigned char *)0x400501E2))
+#define USB0_TXCSRH14_R         (*((volatile unsigned char *)0x400501E3))
+#define USB0_RXMAXP14_R         (*((volatile unsigned short *)0x400501E4))
+#define USB0_RXCSRL14_R         (*((volatile unsigned char *)0x400501E6))
+#define USB0_RXCSRH14_R         (*((volatile unsigned char *)0x400501E7))
+#define USB0_RXCOUNT14_R        (*((volatile unsigned short *)0x400501E8))
+#define USB0_TXTYPE14_R         (*((volatile unsigned char *)0x400501EA))
+#define USB0_TXINTERVAL14_R     (*((volatile unsigned char *)0x400501EB))
+#define USB0_RXTYPE14_R         (*((volatile unsigned char *)0x400501EC))
+#define USB0_RXINTERVAL14_R     (*((volatile unsigned char *)0x400501ED))
+#define USB0_TXMAXP15_R         (*((volatile unsigned short *)0x400501F0))
+#define USB0_TXCSRL15_R         (*((volatile unsigned char *)0x400501F2))
+#define USB0_TXCSRH15_R         (*((volatile unsigned char *)0x400501F3))
+#define USB0_RXMAXP15_R         (*((volatile unsigned short *)0x400501F4))
+#define USB0_RXCSRL15_R         (*((volatile unsigned char *)0x400501F6))
+#define USB0_RXCSRH15_R         (*((volatile unsigned char *)0x400501F7))
+#define USB0_RXCOUNT15_R        (*((volatile unsigned short *)0x400501F8))
+#define USB0_TXTYPE15_R         (*((volatile unsigned char *)0x400501FA))
+#define USB0_TXINTERVAL15_R     (*((volatile unsigned char *)0x400501FB))
+#define USB0_RXTYPE15_R         (*((volatile unsigned char *)0x400501FC))
+#define USB0_RXINTERVAL15_R     (*((volatile unsigned char *)0x400501FD))
+#define USB0_RQPKTCOUNT1_R      (*((volatile unsigned short *)0x40050304))
+#define USB0_RQPKTCOUNT2_R      (*((volatile unsigned short *)0x40050308))
+#define USB0_RQPKTCOUNT3_R      (*((volatile unsigned short *)0x4005030C))
+#define USB0_RQPKTCOUNT4_R      (*((volatile unsigned short *)0x40050310))
+#define USB0_RQPKTCOUNT5_R      (*((volatile unsigned short *)0x40050314))
+#define USB0_RQPKTCOUNT6_R      (*((volatile unsigned short *)0x40050318))
+#define USB0_RQPKTCOUNT7_R      (*((volatile unsigned short *)0x4005031C))
+#define USB0_RQPKTCOUNT8_R      (*((volatile unsigned short *)0x40050320))
+#define USB0_RQPKTCOUNT9_R      (*((volatile unsigned short *)0x40050324))
+#define USB0_RQPKTCOUNT10_R     (*((volatile unsigned short *)0x40050328))
+#define USB0_RQPKTCOUNT11_R     (*((volatile unsigned short *)0x4005032C))
+#define USB0_RQPKTCOUNT12_R     (*((volatile unsigned short *)0x40050330))
+#define USB0_RQPKTCOUNT13_R     (*((volatile unsigned short *)0x40050334))
+#define USB0_RQPKTCOUNT14_R     (*((volatile unsigned short *)0x40050338))
+#define USB0_RQPKTCOUNT15_R     (*((volatile unsigned short *)0x4005033C))
+#define USB0_RXDPKTBUFDIS_R     (*((volatile unsigned short *)0x40050340))
+#define USB0_TXDPKTBUFDIS_R     (*((volatile unsigned short *)0x40050342))
+#define USB0_EPC_R              (*((volatile unsigned long *)0x40050400))
+#define USB0_EPCRIS_R           (*((volatile unsigned long *)0x40050404))
+#define USB0_EPCIM_R            (*((volatile unsigned long *)0x40050408))
+#define USB0_EPCISC_R           (*((volatile unsigned long *)0x4005040C))
+#define USB0_DRRIS_R            (*((volatile unsigned long *)0x40050410))
+#define USB0_DRIM_R             (*((volatile unsigned long *)0x40050414))
+#define USB0_DRISC_R            (*((volatile unsigned long *)0x40050418))
+#define USB0_GPCS_R             (*((volatile unsigned long *)0x4005041C))
+#define USB0_VDC_R              (*((volatile unsigned long *)0x40050430))
+#define USB0_VDCRIS_R           (*((volatile unsigned long *)0x40050434))
+#define USB0_VDCIM_R            (*((volatile unsigned long *)0x40050438))
+#define USB0_VDCISC_R           (*((volatile unsigned long *)0x4005043C))
+#define USB0_IDVRIS_R           (*((volatile unsigned long *)0x40050444))
+#define USB0_IDVIM_R            (*((volatile unsigned long *)0x40050448))
+#define USB0_IDVISC_R           (*((volatile unsigned long *)0x4005044C))
+#define USB0_DMASEL_R           (*((volatile unsigned long *)0x40050450))
+
+//*****************************************************************************
+//
+// Inter-Integrated Circuit Sound registers (I2S0)
+//
+//*****************************************************************************
+#define I2S0_TXFIFO_R           (*((volatile unsigned long *)0x40054000))
+#define I2S0_TXFIFOCFG_R        (*((volatile unsigned long *)0x40054004))
+#define I2S0_TXCFG_R            (*((volatile unsigned long *)0x40054008))
+#define I2S0_TXLIMIT_R          (*((volatile unsigned long *)0x4005400C))
+#define I2S0_TXISM_R            (*((volatile unsigned long *)0x40054010))
+#define I2S0_TXLEV_R            (*((volatile unsigned long *)0x40054018))
+#define I2S0_RXFIFO_R           (*((volatile unsigned long *)0x40054800))
+#define I2S0_RXFIFOCFG_R        (*((volatile unsigned long *)0x40054804))
+#define I2S0_RXCFG_R            (*((volatile unsigned long *)0x40054808))
+#define I2S0_RXLIMIT_R          (*((volatile unsigned long *)0x4005480C))
+#define I2S0_RXISM_R            (*((volatile unsigned long *)0x40054810))
+#define I2S0_RXLEV_R            (*((volatile unsigned long *)0x40054818))
+#define I2S0_CFG_R              (*((volatile unsigned long *)0x40054C00))
+#define I2S0_IM_R               (*((volatile unsigned long *)0x40054C10))
+#define I2S0_RIS_R              (*((volatile unsigned long *)0x40054C14))
+#define I2S0_MIS_R              (*((volatile unsigned long *)0x40054C18))
+#define I2S0_IC_R               (*((volatile unsigned long *)0x40054C1C))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTA AHB)
+//
+//*****************************************************************************
+#define GPIO_PORTA_AHB_DATA_BITS_R \
+                                ((volatile unsigned long *)0x40058000)
+#define GPIO_PORTA_AHB_DATA_R   (*((volatile unsigned long *)0x400583FC))
+#define GPIO_PORTA_AHB_DIR_R    (*((volatile unsigned long *)0x40058400))
+#define GPIO_PORTA_AHB_IS_R     (*((volatile unsigned long *)0x40058404))
+#define GPIO_PORTA_AHB_IBE_R    (*((volatile unsigned long *)0x40058408))
+#define GPIO_PORTA_AHB_IEV_R    (*((volatile unsigned long *)0x4005840C))
+#define GPIO_PORTA_AHB_IM_R     (*((volatile unsigned long *)0x40058410))
+#define GPIO_PORTA_AHB_RIS_R    (*((volatile unsigned long *)0x40058414))
+#define GPIO_PORTA_AHB_MIS_R    (*((volatile unsigned long *)0x40058418))
+#define GPIO_PORTA_AHB_ICR_R    (*((volatile unsigned long *)0x4005841C))
+#define GPIO_PORTA_AHB_AFSEL_R  (*((volatile unsigned long *)0x40058420))
+#define GPIO_PORTA_AHB_DR2R_R   (*((volatile unsigned long *)0x40058500))
+#define GPIO_PORTA_AHB_DR4R_R   (*((volatile unsigned long *)0x40058504))
+#define GPIO_PORTA_AHB_DR8R_R   (*((volatile unsigned long *)0x40058508))
+#define GPIO_PORTA_AHB_ODR_R    (*((volatile unsigned long *)0x4005850C))
+#define GPIO_PORTA_AHB_PUR_R    (*((volatile unsigned long *)0x40058510))
+#define GPIO_PORTA_AHB_PDR_R    (*((volatile unsigned long *)0x40058514))
+#define GPIO_PORTA_AHB_SLR_R    (*((volatile unsigned long *)0x40058518))
+#define GPIO_PORTA_AHB_DEN_R    (*((volatile unsigned long *)0x4005851C))
+#define GPIO_PORTA_AHB_LOCK_R   (*((volatile unsigned long *)0x40058520))
+#define GPIO_PORTA_AHB_CR_R     (*((volatile unsigned long *)0x40058524))
+#define GPIO_PORTA_AHB_AMSEL_R  (*((volatile unsigned long *)0x40058528))
+#define GPIO_PORTA_AHB_PCTL_R   (*((volatile unsigned long *)0x4005852C))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTB AHB)
+//
+//*****************************************************************************
+#define GPIO_PORTB_AHB_DATA_BITS_R \
+                                ((volatile unsigned long *)0x40059000)
+#define GPIO_PORTB_AHB_DATA_R   (*((volatile unsigned long *)0x400593FC))
+#define GPIO_PORTB_AHB_DIR_R    (*((volatile unsigned long *)0x40059400))
+#define GPIO_PORTB_AHB_IS_R     (*((volatile unsigned long *)0x40059404))
+#define GPIO_PORTB_AHB_IBE_R    (*((volatile unsigned long *)0x40059408))
+#define GPIO_PORTB_AHB_IEV_R    (*((volatile unsigned long *)0x4005940C))
+#define GPIO_PORTB_AHB_IM_R     (*((volatile unsigned long *)0x40059410))
+#define GPIO_PORTB_AHB_RIS_R    (*((volatile unsigned long *)0x40059414))
+#define GPIO_PORTB_AHB_MIS_R    (*((volatile unsigned long *)0x40059418))
+#define GPIO_PORTB_AHB_ICR_R    (*((volatile unsigned long *)0x4005941C))
+#define GPIO_PORTB_AHB_AFSEL_R  (*((volatile unsigned long *)0x40059420))
+#define GPIO_PORTB_AHB_DR2R_R   (*((volatile unsigned long *)0x40059500))
+#define GPIO_PORTB_AHB_DR4R_R   (*((volatile unsigned long *)0x40059504))
+#define GPIO_PORTB_AHB_DR8R_R   (*((volatile unsigned long *)0x40059508))
+#define GPIO_PORTB_AHB_ODR_R    (*((volatile unsigned long *)0x4005950C))
+#define GPIO_PORTB_AHB_PUR_R    (*((volatile unsigned long *)0x40059510))
+#define GPIO_PORTB_AHB_PDR_R    (*((volatile unsigned long *)0x40059514))
+#define GPIO_PORTB_AHB_SLR_R    (*((volatile unsigned long *)0x40059518))
+#define GPIO_PORTB_AHB_DEN_R    (*((volatile unsigned long *)0x4005951C))
+#define GPIO_PORTB_AHB_LOCK_R   (*((volatile unsigned long *)0x40059520))
+#define GPIO_PORTB_AHB_CR_R     (*((volatile unsigned long *)0x40059524))
+#define GPIO_PORTB_AHB_AMSEL_R  (*((volatile unsigned long *)0x40059528))
+#define GPIO_PORTB_AHB_PCTL_R   (*((volatile unsigned long *)0x4005952C))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTC AHB)
+//
+//*****************************************************************************
+#define GPIO_PORTC_AHB_DATA_BITS_R \
+                                ((volatile unsigned long *)0x4005A000)
+#define GPIO_PORTC_AHB_DATA_R   (*((volatile unsigned long *)0x4005A3FC))
+#define GPIO_PORTC_AHB_DIR_R    (*((volatile unsigned long *)0x4005A400))
+#define GPIO_PORTC_AHB_IS_R     (*((volatile unsigned long *)0x4005A404))
+#define GPIO_PORTC_AHB_IBE_R    (*((volatile unsigned long *)0x4005A408))
+#define GPIO_PORTC_AHB_IEV_R    (*((volatile unsigned long *)0x4005A40C))
+#define GPIO_PORTC_AHB_IM_R     (*((volatile unsigned long *)0x4005A410))
+#define GPIO_PORTC_AHB_RIS_R    (*((volatile unsigned long *)0x4005A414))
+#define GPIO_PORTC_AHB_MIS_R    (*((volatile unsigned long *)0x4005A418))
+#define GPIO_PORTC_AHB_ICR_R    (*((volatile unsigned long *)0x4005A41C))
+#define GPIO_PORTC_AHB_AFSEL_R  (*((volatile unsigned long *)0x4005A420))
+#define GPIO_PORTC_AHB_DR2R_R   (*((volatile unsigned long *)0x4005A500))
+#define GPIO_PORTC_AHB_DR4R_R   (*((volatile unsigned long *)0x4005A504))
+#define GPIO_PORTC_AHB_DR8R_R   (*((volatile unsigned long *)0x4005A508))
+#define GPIO_PORTC_AHB_ODR_R    (*((volatile unsigned long *)0x4005A50C))
+#define GPIO_PORTC_AHB_PUR_R    (*((volatile unsigned long *)0x4005A510))
+#define GPIO_PORTC_AHB_PDR_R    (*((volatile unsigned long *)0x4005A514))
+#define GPIO_PORTC_AHB_SLR_R    (*((volatile unsigned long *)0x4005A518))
+#define GPIO_PORTC_AHB_DEN_R    (*((volatile unsigned long *)0x4005A51C))
+#define GPIO_PORTC_AHB_LOCK_R   (*((volatile unsigned long *)0x4005A520))
+#define GPIO_PORTC_AHB_CR_R     (*((volatile unsigned long *)0x4005A524))
+#define GPIO_PORTC_AHB_AMSEL_R  (*((volatile unsigned long *)0x4005A528))
+#define GPIO_PORTC_AHB_PCTL_R   (*((volatile unsigned long *)0x4005A52C))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTD AHB)
+//
+//*****************************************************************************
+#define GPIO_PORTD_AHB_DATA_BITS_R \
+                                ((volatile unsigned long *)0x4005B000)
+#define GPIO_PORTD_AHB_DATA_R   (*((volatile unsigned long *)0x4005B3FC))
+#define GPIO_PORTD_AHB_DIR_R    (*((volatile unsigned long *)0x4005B400))
+#define GPIO_PORTD_AHB_IS_R     (*((volatile unsigned long *)0x4005B404))
+#define GPIO_PORTD_AHB_IBE_R    (*((volatile unsigned long *)0x4005B408))
+#define GPIO_PORTD_AHB_IEV_R    (*((volatile unsigned long *)0x4005B40C))
+#define GPIO_PORTD_AHB_IM_R     (*((volatile unsigned long *)0x4005B410))
+#define GPIO_PORTD_AHB_RIS_R    (*((volatile unsigned long *)0x4005B414))
+#define GPIO_PORTD_AHB_MIS_R    (*((volatile unsigned long *)0x4005B418))
+#define GPIO_PORTD_AHB_ICR_R    (*((volatile unsigned long *)0x4005B41C))
+#define GPIO_PORTD_AHB_AFSEL_R  (*((volatile unsigned long *)0x4005B420))
+#define GPIO_PORTD_AHB_DR2R_R   (*((volatile unsigned long *)0x4005B500))
+#define GPIO_PORTD_AHB_DR4R_R   (*((volatile unsigned long *)0x4005B504))
+#define GPIO_PORTD_AHB_DR8R_R   (*((volatile unsigned long *)0x4005B508))
+#define GPIO_PORTD_AHB_ODR_R    (*((volatile unsigned long *)0x4005B50C))
+#define GPIO_PORTD_AHB_PUR_R    (*((volatile unsigned long *)0x4005B510))
+#define GPIO_PORTD_AHB_PDR_R    (*((volatile unsigned long *)0x4005B514))
+#define GPIO_PORTD_AHB_SLR_R    (*((volatile unsigned long *)0x4005B518))
+#define GPIO_PORTD_AHB_DEN_R    (*((volatile unsigned long *)0x4005B51C))
+#define GPIO_PORTD_AHB_LOCK_R   (*((volatile unsigned long *)0x4005B520))
+#define GPIO_PORTD_AHB_CR_R     (*((volatile unsigned long *)0x4005B524))
+#define GPIO_PORTD_AHB_AMSEL_R  (*((volatile unsigned long *)0x4005B528))
+#define GPIO_PORTD_AHB_PCTL_R   (*((volatile unsigned long *)0x4005B52C))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTE AHB)
+//
+//*****************************************************************************
+#define GPIO_PORTE_AHB_DATA_BITS_R \
+                                ((volatile unsigned long *)0x4005C000)
+#define GPIO_PORTE_AHB_DATA_R   (*((volatile unsigned long *)0x4005C3FC))
+#define GPIO_PORTE_AHB_DIR_R    (*((volatile unsigned long *)0x4005C400))
+#define GPIO_PORTE_AHB_IS_R     (*((volatile unsigned long *)0x4005C404))
+#define GPIO_PORTE_AHB_IBE_R    (*((volatile unsigned long *)0x4005C408))
+#define GPIO_PORTE_AHB_IEV_R    (*((volatile unsigned long *)0x4005C40C))
+#define GPIO_PORTE_AHB_IM_R     (*((volatile unsigned long *)0x4005C410))
+#define GPIO_PORTE_AHB_RIS_R    (*((volatile unsigned long *)0x4005C414))
+#define GPIO_PORTE_AHB_MIS_R    (*((volatile unsigned long *)0x4005C418))
+#define GPIO_PORTE_AHB_ICR_R    (*((volatile unsigned long *)0x4005C41C))
+#define GPIO_PORTE_AHB_AFSEL_R  (*((volatile unsigned long *)0x4005C420))
+#define GPIO_PORTE_AHB_DR2R_R   (*((volatile unsigned long *)0x4005C500))
+#define GPIO_PORTE_AHB_DR4R_R   (*((volatile unsigned long *)0x4005C504))
+#define GPIO_PORTE_AHB_DR8R_R   (*((volatile unsigned long *)0x4005C508))
+#define GPIO_PORTE_AHB_ODR_R    (*((volatile unsigned long *)0x4005C50C))
+#define GPIO_PORTE_AHB_PUR_R    (*((volatile unsigned long *)0x4005C510))
+#define GPIO_PORTE_AHB_PDR_R    (*((volatile unsigned long *)0x4005C514))
+#define GPIO_PORTE_AHB_SLR_R    (*((volatile unsigned long *)0x4005C518))
+#define GPIO_PORTE_AHB_DEN_R    (*((volatile unsigned long *)0x4005C51C))
+#define GPIO_PORTE_AHB_LOCK_R   (*((volatile unsigned long *)0x4005C520))
+#define GPIO_PORTE_AHB_CR_R     (*((volatile unsigned long *)0x4005C524))
+#define GPIO_PORTE_AHB_AMSEL_R  (*((volatile unsigned long *)0x4005C528))
+#define GPIO_PORTE_AHB_PCTL_R   (*((volatile unsigned long *)0x4005C52C))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTF AHB)
+//
+//*****************************************************************************
+#define GPIO_PORTF_AHB_DATA_BITS_R \
+                                ((volatile unsigned long *)0x4005D000)
+#define GPIO_PORTF_AHB_DATA_R   (*((volatile unsigned long *)0x4005D3FC))
+#define GPIO_PORTF_AHB_DIR_R    (*((volatile unsigned long *)0x4005D400))
+#define GPIO_PORTF_AHB_IS_R     (*((volatile unsigned long *)0x4005D404))
+#define GPIO_PORTF_AHB_IBE_R    (*((volatile unsigned long *)0x4005D408))
+#define GPIO_PORTF_AHB_IEV_R    (*((volatile unsigned long *)0x4005D40C))
+#define GPIO_PORTF_AHB_IM_R     (*((volatile unsigned long *)0x4005D410))
+#define GPIO_PORTF_AHB_RIS_R    (*((volatile unsigned long *)0x4005D414))
+#define GPIO_PORTF_AHB_MIS_R    (*((volatile unsigned long *)0x4005D418))
+#define GPIO_PORTF_AHB_ICR_R    (*((volatile unsigned long *)0x4005D41C))
+#define GPIO_PORTF_AHB_AFSEL_R  (*((volatile unsigned long *)0x4005D420))
+#define GPIO_PORTF_AHB_DR2R_R   (*((volatile unsigned long *)0x4005D500))
+#define GPIO_PORTF_AHB_DR4R_R   (*((volatile unsigned long *)0x4005D504))
+#define GPIO_PORTF_AHB_DR8R_R   (*((volatile unsigned long *)0x4005D508))
+#define GPIO_PORTF_AHB_ODR_R    (*((volatile unsigned long *)0x4005D50C))
+#define GPIO_PORTF_AHB_PUR_R    (*((volatile unsigned long *)0x4005D510))
+#define GPIO_PORTF_AHB_PDR_R    (*((volatile unsigned long *)0x4005D514))
+#define GPIO_PORTF_AHB_SLR_R    (*((volatile unsigned long *)0x4005D518))
+#define GPIO_PORTF_AHB_DEN_R    (*((volatile unsigned long *)0x4005D51C))
+#define GPIO_PORTF_AHB_LOCK_R   (*((volatile unsigned long *)0x4005D520))
+#define GPIO_PORTF_AHB_CR_R     (*((volatile unsigned long *)0x4005D524))
+#define GPIO_PORTF_AHB_AMSEL_R  (*((volatile unsigned long *)0x4005D528))
+#define GPIO_PORTF_AHB_PCTL_R   (*((volatile unsigned long *)0x4005D52C))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTG AHB)
+//
+//*****************************************************************************
+#define GPIO_PORTG_AHB_DATA_BITS_R \
+                                ((volatile unsigned long *)0x4005E000)
+#define GPIO_PORTG_AHB_DATA_R   (*((volatile unsigned long *)0x4005E3FC))
+#define GPIO_PORTG_AHB_DIR_R    (*((volatile unsigned long *)0x4005E400))
+#define GPIO_PORTG_AHB_IS_R     (*((volatile unsigned long *)0x4005E404))
+#define GPIO_PORTG_AHB_IBE_R    (*((volatile unsigned long *)0x4005E408))
+#define GPIO_PORTG_AHB_IEV_R    (*((volatile unsigned long *)0x4005E40C))
+#define GPIO_PORTG_AHB_IM_R     (*((volatile unsigned long *)0x4005E410))
+#define GPIO_PORTG_AHB_RIS_R    (*((volatile unsigned long *)0x4005E414))
+#define GPIO_PORTG_AHB_MIS_R    (*((volatile unsigned long *)0x4005E418))
+#define GPIO_PORTG_AHB_ICR_R    (*((volatile unsigned long *)0x4005E41C))
+#define GPIO_PORTG_AHB_AFSEL_R  (*((volatile unsigned long *)0x4005E420))
+#define GPIO_PORTG_AHB_DR2R_R   (*((volatile unsigned long *)0x4005E500))
+#define GPIO_PORTG_AHB_DR4R_R   (*((volatile unsigned long *)0x4005E504))
+#define GPIO_PORTG_AHB_DR8R_R   (*((volatile unsigned long *)0x4005E508))
+#define GPIO_PORTG_AHB_ODR_R    (*((volatile unsigned long *)0x4005E50C))
+#define GPIO_PORTG_AHB_PUR_R    (*((volatile unsigned long *)0x4005E510))
+#define GPIO_PORTG_AHB_PDR_R    (*((volatile unsigned long *)0x4005E514))
+#define GPIO_PORTG_AHB_SLR_R    (*((volatile unsigned long *)0x4005E518))
+#define GPIO_PORTG_AHB_DEN_R    (*((volatile unsigned long *)0x4005E51C))
+#define GPIO_PORTG_AHB_LOCK_R   (*((volatile unsigned long *)0x4005E520))
+#define GPIO_PORTG_AHB_CR_R     (*((volatile unsigned long *)0x4005E524))
+#define GPIO_PORTG_AHB_AMSEL_R  (*((volatile unsigned long *)0x4005E528))
+#define GPIO_PORTG_AHB_PCTL_R   (*((volatile unsigned long *)0x4005E52C))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTH AHB)
+//
+//*****************************************************************************
+#define GPIO_PORTH_AHB_DATA_BITS_R \
+                                ((volatile unsigned long *)0x4005F000)
+#define GPIO_PORTH_AHB_DATA_R   (*((volatile unsigned long *)0x4005F3FC))
+#define GPIO_PORTH_AHB_DIR_R    (*((volatile unsigned long *)0x4005F400))
+#define GPIO_PORTH_AHB_IS_R     (*((volatile unsigned long *)0x4005F404))
+#define GPIO_PORTH_AHB_IBE_R    (*((volatile unsigned long *)0x4005F408))
+#define GPIO_PORTH_AHB_IEV_R    (*((volatile unsigned long *)0x4005F40C))
+#define GPIO_PORTH_AHB_IM_R     (*((volatile unsigned long *)0x4005F410))
+#define GPIO_PORTH_AHB_RIS_R    (*((volatile unsigned long *)0x4005F414))
+#define GPIO_PORTH_AHB_MIS_R    (*((volatile unsigned long *)0x4005F418))
+#define GPIO_PORTH_AHB_ICR_R    (*((volatile unsigned long *)0x4005F41C))
+#define GPIO_PORTH_AHB_AFSEL_R  (*((volatile unsigned long *)0x4005F420))
+#define GPIO_PORTH_AHB_DR2R_R   (*((volatile unsigned long *)0x4005F500))
+#define GPIO_PORTH_AHB_DR4R_R   (*((volatile unsigned long *)0x4005F504))
+#define GPIO_PORTH_AHB_DR8R_R   (*((volatile unsigned long *)0x4005F508))
+#define GPIO_PORTH_AHB_ODR_R    (*((volatile unsigned long *)0x4005F50C))
+#define GPIO_PORTH_AHB_PUR_R    (*((volatile unsigned long *)0x4005F510))
+#define GPIO_PORTH_AHB_PDR_R    (*((volatile unsigned long *)0x4005F514))
+#define GPIO_PORTH_AHB_SLR_R    (*((volatile unsigned long *)0x4005F518))
+#define GPIO_PORTH_AHB_DEN_R    (*((volatile unsigned long *)0x4005F51C))
+#define GPIO_PORTH_AHB_LOCK_R   (*((volatile unsigned long *)0x4005F520))
+#define GPIO_PORTH_AHB_CR_R     (*((volatile unsigned long *)0x4005F524))
+#define GPIO_PORTH_AHB_AMSEL_R  (*((volatile unsigned long *)0x4005F528))
+#define GPIO_PORTH_AHB_PCTL_R   (*((volatile unsigned long *)0x4005F52C))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTJ AHB)
+//
+//*****************************************************************************
+#define GPIO_PORTJ_AHB_DATA_BITS_R \
+                                ((volatile unsigned long *)0x40060000)
+#define GPIO_PORTJ_AHB_DATA_R   (*((volatile unsigned long *)0x400603FC))
+#define GPIO_PORTJ_AHB_DIR_R    (*((volatile unsigned long *)0x40060400))
+#define GPIO_PORTJ_AHB_IS_R     (*((volatile unsigned long *)0x40060404))
+#define GPIO_PORTJ_AHB_IBE_R    (*((volatile unsigned long *)0x40060408))
+#define GPIO_PORTJ_AHB_IEV_R    (*((volatile unsigned long *)0x4006040C))
+#define GPIO_PORTJ_AHB_IM_R     (*((volatile unsigned long *)0x40060410))
+#define GPIO_PORTJ_AHB_RIS_R    (*((volatile unsigned long *)0x40060414))
+#define GPIO_PORTJ_AHB_MIS_R    (*((volatile unsigned long *)0x40060418))
+#define GPIO_PORTJ_AHB_ICR_R    (*((volatile unsigned long *)0x4006041C))
+#define GPIO_PORTJ_AHB_AFSEL_R  (*((volatile unsigned long *)0x40060420))
+#define GPIO_PORTJ_AHB_DR2R_R   (*((volatile unsigned long *)0x40060500))
+#define GPIO_PORTJ_AHB_DR4R_R   (*((volatile unsigned long *)0x40060504))
+#define GPIO_PORTJ_AHB_DR8R_R   (*((volatile unsigned long *)0x40060508))
+#define GPIO_PORTJ_AHB_ODR_R    (*((volatile unsigned long *)0x4006050C))
+#define GPIO_PORTJ_AHB_PUR_R    (*((volatile unsigned long *)0x40060510))
+#define GPIO_PORTJ_AHB_PDR_R    (*((volatile unsigned long *)0x40060514))
+#define GPIO_PORTJ_AHB_SLR_R    (*((volatile unsigned long *)0x40060518))
+#define GPIO_PORTJ_AHB_DEN_R    (*((volatile unsigned long *)0x4006051C))
+#define GPIO_PORTJ_AHB_LOCK_R   (*((volatile unsigned long *)0x40060520))
+#define GPIO_PORTJ_AHB_CR_R     (*((volatile unsigned long *)0x40060524))
+#define GPIO_PORTJ_AHB_AMSEL_R  (*((volatile unsigned long *)0x40060528))
+#define GPIO_PORTJ_AHB_PCTL_R   (*((volatile unsigned long *)0x4006052C))
+
+//*****************************************************************************
+//
+// External Peripheral Interface registers (EPI0)
+//
+//*****************************************************************************
+#define EPI0_CFG_R              (*((volatile unsigned long *)0x400D0000))
+#define EPI0_BAUD_R             (*((volatile unsigned long *)0x400D0004))
+#define EPI0_HB16CFG_R          (*((volatile unsigned long *)0x400D0010))
+#define EPI0_GPCFG_R            (*((volatile unsigned long *)0x400D0010))
+#define EPI0_SDRAMCFG_R         (*((volatile unsigned long *)0x400D0010))
+#define EPI0_HB8CFG_R           (*((volatile unsigned long *)0x400D0010))
+#define EPI0_HB8CFG2_R          (*((volatile unsigned long *)0x400D0014))
+#define EPI0_HB16CFG2_R         (*((volatile unsigned long *)0x400D0014))
+#define EPI0_GPCFG2_R           (*((volatile unsigned long *)0x400D0014))
+#define EPI0_ADDRMAP_R          (*((volatile unsigned long *)0x400D001C))
+#define EPI0_RSIZE0_R           (*((volatile unsigned long *)0x400D0020))
+#define EPI0_RADDR0_R           (*((volatile unsigned long *)0x400D0024))
+#define EPI0_RPSTD0_R           (*((volatile unsigned long *)0x400D0028))
+#define EPI0_RSIZE1_R           (*((volatile unsigned long *)0x400D0030))
+#define EPI0_RADDR1_R           (*((volatile unsigned long *)0x400D0034))
+#define EPI0_RPSTD1_R           (*((volatile unsigned long *)0x400D0038))
+#define EPI0_STAT_R             (*((volatile unsigned long *)0x400D0060))
+#define EPI0_RFIFOCNT_R         (*((volatile unsigned long *)0x400D006C))
+#define EPI0_READFIFO_R         (*((volatile unsigned long *)0x400D0070))
+#define EPI0_READFIFO1_R        (*((volatile unsigned long *)0x400D0074))
+#define EPI0_READFIFO2_R        (*((volatile unsigned long *)0x400D0078))
+#define EPI0_READFIFO3_R        (*((volatile unsigned long *)0x400D007C))
+#define EPI0_READFIFO4_R        (*((volatile unsigned long *)0x400D0080))
+#define EPI0_READFIFO5_R        (*((volatile unsigned long *)0x400D0084))
+#define EPI0_READFIFO6_R        (*((volatile unsigned long *)0x400D0088))
+#define EPI0_READFIFO7_R        (*((volatile unsigned long *)0x400D008C))
+#define EPI0_FIFOLVL_R          (*((volatile unsigned long *)0x400D0200))
+#define EPI0_WFIFOCNT_R         (*((volatile unsigned long *)0x400D0204))
+#define EPI0_IM_R               (*((volatile unsigned long *)0x400D0210))
+#define EPI0_RIS_R              (*((volatile unsigned long *)0x400D0214))
+#define EPI0_MIS_R              (*((volatile unsigned long *)0x400D0218))
+#define EPI0_EISC_R             (*((volatile unsigned long *)0x400D021C))
+
+//*****************************************************************************
+//
+// FLASH registers (FLASH CTRL)
+//
+//*****************************************************************************
+#define FLASH_FMA_R             (*((volatile unsigned long *)0x400FD000))
+#define FLASH_FMD_R             (*((volatile unsigned long *)0x400FD004))
+#define FLASH_FMC_R             (*((volatile unsigned long *)0x400FD008))
+#define FLASH_FCRIS_R           (*((volatile unsigned long *)0x400FD00C))
+#define FLASH_FCIM_R            (*((volatile unsigned long *)0x400FD010))
+#define FLASH_FCMISC_R          (*((volatile unsigned long *)0x400FD014))
+#define FLASH_FMC2_R            (*((volatile unsigned long *)0x400FD020))
+#define FLASH_FWBVAL_R          (*((volatile unsigned long *)0x400FD030))
+#define FLASH_FCTL_R            (*((volatile unsigned long *)0x400FD0F8))
+#define FLASH_FWBN_R            (*((volatile unsigned long *)0x400FD100))
+#define FLASH_RMCTL_R           (*((volatile unsigned long *)0x400FE0F0))
+#define FLASH_RMVER_R           (*((volatile unsigned long *)0x400FE0F4))
+#define FLASH_USERDBG_R         (*((volatile unsigned long *)0x400FE1D0))
+#define FLASH_BOOTCFG_R         (*((volatile unsigned long *)0x400FE1D0))
+#define FLASH_USERREG0_R        (*((volatile unsigned long *)0x400FE1E0))
+#define FLASH_USERREG1_R        (*((volatile unsigned long *)0x400FE1E4))
+#define FLASH_USERREG2_R        (*((volatile unsigned long *)0x400FE1E8))
+#define FLASH_USERREG3_R        (*((volatile unsigned long *)0x400FE1EC))
+#define FLASH_FMPRE0_R          (*((volatile unsigned long *)0x400FE200))
+#define FLASH_FMPRE1_R          (*((volatile unsigned long *)0x400FE204))
+#define FLASH_FMPRE2_R          (*((volatile unsigned long *)0x400FE208))
+#define FLASH_FMPRE3_R          (*((volatile unsigned long *)0x400FE20C))
+#define FLASH_FMPRE4_R          (*((volatile unsigned long *)0x400FE210))
+#define FLASH_FMPRE5_R          (*((volatile unsigned long *)0x400FE214))
+#define FLASH_FMPRE6_R          (*((volatile unsigned long *)0x400FE218))
+#define FLASH_FMPRE7_R          (*((volatile unsigned long *)0x400FE21C))
+#define FLASH_FMPPE0_R          (*((volatile unsigned long *)0x400FE400))
+#define FLASH_FMPPE1_R          (*((volatile unsigned long *)0x400FE404))
+#define FLASH_FMPPE2_R          (*((volatile unsigned long *)0x400FE408))
+#define FLASH_FMPPE3_R          (*((volatile unsigned long *)0x400FE40C))
+#define FLASH_FMPPE4_R          (*((volatile unsigned long *)0x400FE410))
+#define FLASH_FMPPE5_R          (*((volatile unsigned long *)0x400FE414))
+#define FLASH_FMPPE6_R          (*((volatile unsigned long *)0x400FE418))
+#define FLASH_FMPPE7_R          (*((volatile unsigned long *)0x400FE41C))
+
+//*****************************************************************************
+//
+// System Control registers (SYSCTL)
+//
+//*****************************************************************************
+#define SYSCTL_DID0_R           (*((volatile unsigned long *)0x400FE000))
+#define SYSCTL_DID1_R           (*((volatile unsigned long *)0x400FE004))
+#define SYSCTL_DC0_R            (*((volatile unsigned long *)0x400FE008))
+#define SYSCTL_DC1_R            (*((volatile unsigned long *)0x400FE010))
+#define SYSCTL_DC2_R            (*((volatile unsigned long *)0x400FE014))
+#define SYSCTL_DC3_R            (*((volatile unsigned long *)0x400FE018))
+#define SYSCTL_DC4_R            (*((volatile unsigned long *)0x400FE01C))
+#define SYSCTL_DC5_R            (*((volatile unsigned long *)0x400FE020))
+#define SYSCTL_DC6_R            (*((volatile unsigned long *)0x400FE024))
+#define SYSCTL_DC7_R            (*((volatile unsigned long *)0x400FE028))
+#define SYSCTL_DC8_R            (*((volatile unsigned long *)0x400FE02C))
+#define SYSCTL_PBORCTL_R        (*((volatile unsigned long *)0x400FE030))
+#define SYSCTL_SRCR0_R          (*((volatile unsigned long *)0x400FE040))
+#define SYSCTL_SRCR1_R          (*((volatile unsigned long *)0x400FE044))
+#define SYSCTL_SRCR2_R          (*((volatile unsigned long *)0x400FE048))
+#define SYSCTL_RIS_R            (*((volatile unsigned long *)0x400FE050))
+#define SYSCTL_IMC_R            (*((volatile unsigned long *)0x400FE054))
+#define SYSCTL_MISC_R           (*((volatile unsigned long *)0x400FE058))
+#define SYSCTL_RESC_R           (*((volatile unsigned long *)0x400FE05C))
+#define SYSCTL_RCC_R            (*((volatile unsigned long *)0x400FE060))
+#define SYSCTL_PLLCFG_R         (*((volatile unsigned long *)0x400FE064))
+#define SYSCTL_GPIOHBCTL_R      (*((volatile unsigned long *)0x400FE06C))
+#define SYSCTL_RCC2_R           (*((volatile unsigned long *)0x400FE070))
+#define SYSCTL_MOSCCTL_R        (*((volatile unsigned long *)0x400FE07C))
+#define SYSCTL_RCGC0_R          (*((volatile unsigned long *)0x400FE100))
+#define SYSCTL_RCGC1_R          (*((volatile unsigned long *)0x400FE104))
+#define SYSCTL_RCGC2_R          (*((volatile unsigned long *)0x400FE108))
+#define SYSCTL_SCGC0_R          (*((volatile unsigned long *)0x400FE110))
+#define SYSCTL_SCGC1_R          (*((volatile unsigned long *)0x400FE114))
+#define SYSCTL_SCGC2_R          (*((volatile unsigned long *)0x400FE118))
+#define SYSCTL_DCGC0_R          (*((volatile unsigned long *)0x400FE120))
+#define SYSCTL_DCGC1_R          (*((volatile unsigned long *)0x400FE124))
+#define SYSCTL_DCGC2_R          (*((volatile unsigned long *)0x400FE128))
+#define SYSCTL_DSLPCLKCFG_R     (*((volatile unsigned long *)0x400FE144))
+#define SYSCTL_PIOSCCAL_R       (*((volatile unsigned long *)0x400FE150))
+#define SYSCTL_I2SMCLKCFG_R     (*((volatile unsigned long *)0x400FE170))
+#define SYSCTL_DC9_R            (*((volatile unsigned long *)0x400FE190))
+#define SYSCTL_NVMSTAT_R        (*((volatile unsigned long *)0x400FE1A0))
+
+//*****************************************************************************
+//
+// Micro Direct Memory Access registers (UDMA)
+//
+//*****************************************************************************
+#define UDMA_STAT_R             (*((volatile unsigned long *)0x400FF000))
+#define UDMA_CFG_R              (*((volatile unsigned long *)0x400FF004))
+#define UDMA_CTLBASE_R          (*((volatile unsigned long *)0x400FF008))
+#define UDMA_ALTBASE_R          (*((volatile unsigned long *)0x400FF00C))
+#define UDMA_WAITSTAT_R         (*((volatile unsigned long *)0x400FF010))
+#define UDMA_SWREQ_R            (*((volatile unsigned long *)0x400FF014))
+#define UDMA_USEBURSTSET_R      (*((volatile unsigned long *)0x400FF018))
+#define UDMA_USEBURSTCLR_R      (*((volatile unsigned long *)0x400FF01C))
+#define UDMA_REQMASKSET_R       (*((volatile unsigned long *)0x400FF020))
+#define UDMA_REQMASKCLR_R       (*((volatile unsigned long *)0x400FF024))
+#define UDMA_ENASET_R           (*((volatile unsigned long *)0x400FF028))
+#define UDMA_ENACLR_R           (*((volatile unsigned long *)0x400FF02C))
+#define UDMA_ALTSET_R           (*((volatile unsigned long *)0x400FF030))
+#define UDMA_ALTCLR_R           (*((volatile unsigned long *)0x400FF034))
+#define UDMA_PRIOSET_R          (*((volatile unsigned long *)0x400FF038))
+#define UDMA_PRIOCLR_R          (*((volatile unsigned long *)0x400FF03C))
+#define UDMA_ERRCLR_R           (*((volatile unsigned long *)0x400FF04C))
+#define UDMA_CHASGN_R           (*((volatile unsigned long *)0x400FF500))
+#define UDMA_CHIS_R             (*((volatile unsigned long *)0x400FF504))
+
+//*****************************************************************************
+//
+// Micro Direct Memory Access (uDMA) offsets (UDMA)
+//
+//*****************************************************************************
+#define UDMA_SRCENDP            0x00000000  // DMA Channel Source Address End
+                                            // Pointer
+#define UDMA_DSTENDP            0x00000004  // DMA Channel Destination Address
+                                            // End Pointer
+#define UDMA_CHCTL              0x00000008  // DMA Channel Control Word
+
+//*****************************************************************************
+//
+// NVIC registers (NVIC)
+//
+//*****************************************************************************
+#define NVIC_INT_TYPE_R         (*((volatile unsigned long *)0xE000E004))
+#define NVIC_ACTLR_R            (*((volatile unsigned long *)0xE000E008))
+#define NVIC_ST_CTRL_R          (*((volatile unsigned long *)0xE000E010))
+#define NVIC_ST_RELOAD_R        (*((volatile unsigned long *)0xE000E014))
+#define NVIC_ST_CURRENT_R       (*((volatile unsigned long *)0xE000E018))
+#define NVIC_ST_CAL_R           (*((volatile unsigned long *)0xE000E01C))
+#define NVIC_EN0_R              (*((volatile unsigned long *)0xE000E100))
+#define NVIC_EN1_R              (*((volatile unsigned long *)0xE000E104))
+#define NVIC_DIS0_R             (*((volatile unsigned long *)0xE000E180))
+#define NVIC_DIS1_R             (*((volatile unsigned long *)0xE000E184))
+#define NVIC_PEND0_R            (*((volatile unsigned long *)0xE000E200))
+#define NVIC_PEND1_R            (*((volatile unsigned long *)0xE000E204))
+#define NVIC_UNPEND0_R          (*((volatile unsigned long *)0xE000E280))
+#define NVIC_UNPEND1_R          (*((volatile unsigned long *)0xE000E284))
+#define NVIC_ACTIVE0_R          (*((volatile unsigned long *)0xE000E300))
+#define NVIC_ACTIVE1_R          (*((volatile unsigned long *)0xE000E304))
+#define NVIC_PRI0_R             (*((volatile unsigned long *)0xE000E400))
+#define NVIC_PRI1_R             (*((volatile unsigned long *)0xE000E404))
+#define NVIC_PRI2_R             (*((volatile unsigned long *)0xE000E408))
+#define NVIC_PRI3_R             (*((volatile unsigned long *)0xE000E40C))
+#define NVIC_PRI4_R             (*((volatile unsigned long *)0xE000E410))
+#define NVIC_PRI5_R             (*((volatile unsigned long *)0xE000E414))
+#define NVIC_PRI6_R             (*((volatile unsigned long *)0xE000E418))
+#define NVIC_PRI7_R             (*((volatile unsigned long *)0xE000E41C))
+#define NVIC_PRI8_R             (*((volatile unsigned long *)0xE000E420))
+#define NVIC_PRI9_R             (*((volatile unsigned long *)0xE000E424))
+#define NVIC_PRI10_R            (*((volatile unsigned long *)0xE000E428))
+#define NVIC_PRI11_R            (*((volatile unsigned long *)0xE000E42C))
+#define NVIC_PRI12_R            (*((volatile unsigned long *)0xE000E430))
+#define NVIC_PRI13_R            (*((volatile unsigned long *)0xE000E434))
+#define NVIC_CPUID_R            (*((volatile unsigned long *)0xE000ED00))
+#define NVIC_INT_CTRL_R         (*((volatile unsigned long *)0xE000ED04))
+#define NVIC_VTABLE_R           (*((volatile unsigned long *)0xE000ED08))
+#define NVIC_APINT_R            (*((volatile unsigned long *)0xE000ED0C))
+#define NVIC_SYS_CTRL_R         (*((volatile unsigned long *)0xE000ED10))
+#define NVIC_CFG_CTRL_R         (*((volatile unsigned long *)0xE000ED14))
+#define NVIC_SYS_PRI1_R         (*((volatile unsigned long *)0xE000ED18))
+#define NVIC_SYS_PRI2_R         (*((volatile unsigned long *)0xE000ED1C))
+#define NVIC_SYS_PRI3_R         (*((volatile unsigned long *)0xE000ED20))
+#define NVIC_SYS_HND_CTRL_R     (*((volatile unsigned long *)0xE000ED24))
+#define NVIC_FAULT_STAT_R       (*((volatile unsigned long *)0xE000ED28))
+#define NVIC_HFAULT_STAT_R      (*((volatile unsigned long *)0xE000ED2C))
+#define NVIC_DEBUG_STAT_R       (*((volatile unsigned long *)0xE000ED30))
+#define NVIC_MM_ADDR_R          (*((volatile unsigned long *)0xE000ED34))
+#define NVIC_FAULT_ADDR_R       (*((volatile unsigned long *)0xE000ED38))
+#define NVIC_MPU_TYPE_R         (*((volatile unsigned long *)0xE000ED90))
+#define NVIC_MPU_CTRL_R         (*((volatile unsigned long *)0xE000ED94))
+#define NVIC_MPU_NUMBER_R       (*((volatile unsigned long *)0xE000ED98))
+#define NVIC_MPU_BASE_R         (*((volatile unsigned long *)0xE000ED9C))
+#define NVIC_MPU_ATTR_R         (*((volatile unsigned long *)0xE000EDA0))
+#define NVIC_MPU_BASE1_R        (*((volatile unsigned long *)0xE000EDA4))
+#define NVIC_MPU_ATTR1_R        (*((volatile unsigned long *)0xE000EDA8))
+#define NVIC_MPU_BASE2_R        (*((volatile unsigned long *)0xE000EDAC))
+#define NVIC_MPU_ATTR2_R        (*((volatile unsigned long *)0xE000EDB0))
+#define NVIC_MPU_BASE3_R        (*((volatile unsigned long *)0xE000EDB4))
+#define NVIC_MPU_ATTR3_R        (*((volatile unsigned long *)0xE000EDB8))
+#define NVIC_DBG_CTRL_R         (*((volatile unsigned long *)0xE000EDF0))
+#define NVIC_DBG_XFER_R         (*((volatile unsigned long *)0xE000EDF4))
+#define NVIC_DBG_DATA_R         (*((volatile unsigned long *)0xE000EDF8))
+#define NVIC_DBG_INT_R          (*((volatile unsigned long *)0xE000EDFC))
+#define NVIC_SW_TRIG_R          (*((volatile unsigned long *)0xE000EF00))
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_LOAD register.
+//
+//*****************************************************************************
+#define WDT_LOAD_M              0xFFFFFFFF  // Watchdog Load Value
+#define WDT_LOAD_S              0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_VALUE register.
+//
+//*****************************************************************************
+#define WDT_VALUE_M             0xFFFFFFFF  // Watchdog Value
+#define WDT_VALUE_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_CTL register.
+//
+//*****************************************************************************
+#define WDT_CTL_WRC             0x80000000  // Write Complete
+#define WDT_CTL_RESEN           0x00000002  // Watchdog Reset Enable
+#define WDT_CTL_INTEN           0x00000001  // Watchdog Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_ICR register.
+//
+//*****************************************************************************
+#define WDT_ICR_M               0xFFFFFFFF  // Watchdog Interrupt Clear
+#define WDT_ICR_S               0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_RIS register.
+//
+//*****************************************************************************
+#define WDT_RIS_WDTRIS          0x00000001  // Watchdog Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_MIS register.
+//
+//*****************************************************************************
+#define WDT_MIS_WDTMIS          0x00000001  // Watchdog Masked Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_TEST register.
+//
+//*****************************************************************************
+#define WDT_TEST_STALL          0x00000100  // Watchdog Stall Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_LOCK register.
+//
+//*****************************************************************************
+#define WDT_LOCK_M              0xFFFFFFFF  // Watchdog Lock
+#define WDT_LOCK_UNLOCKED       0x00000000  // Unlocked
+#define WDT_LOCK_LOCKED         0x00000001  // Locked
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_LOCK register.
+//
+//*****************************************************************************
+#define GPIO_LOCK_M             0xFFFFFFFF  // GPIO Lock
+#define GPIO_LOCK_UNLOCKED      0x00000000  // The GPIOCR register is unlocked
+                                            // and may be modified
+#define GPIO_LOCK_LOCKED        0x00000001  // The GPIOCR register is locked
+                                            // and may not be modified
+#define GPIO_LOCK_KEY           0x4C4F434B  // Unlocks the GPIO_CR register
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_PCTL register for
+// port A.
+//
+//*****************************************************************************
+#define GPIO_PCTL_PA7_M         0xF0000000  // PA7 mask
+#define GPIO_PCTL_PA7_I2C1SDA   0x10000000  // I2C1SDA on PA7
+#define GPIO_PCTL_PA7_CCP4      0x20000000  // CCP4 on PA7
+#define GPIO_PCTL_PA7_PWM1      0x40000000  // PWM1 on PA7
+#define GPIO_PCTL_PA7_PWM5      0x50000000  // PWM5 on PA7
+#define GPIO_PCTL_PA7_CAN0TX    0x60000000  // CAN0TX on PA7
+#define GPIO_PCTL_PA7_CCP3      0x70000000  // CCP3 on PA7
+#define GPIO_PCTL_PA7_USB0PFLT  0x80000000  // USB0PFLT on PA7
+#define GPIO_PCTL_PA7_U1DCD     0x90000000  // U1DCD on PA7
+#define GPIO_PCTL_PA6_M         0x0F000000  // PA6 mask
+#define GPIO_PCTL_PA6_I2C1SCL   0x01000000  // I2C1SCL on PA6
+#define GPIO_PCTL_PA6_CCP1      0x02000000  // CCP1 on PA6
+#define GPIO_PCTL_PA6_PWM0      0x04000000  // PWM0 on PA6
+#define GPIO_PCTL_PA6_PWM4      0x05000000  // PWM4 on PA6
+#define GPIO_PCTL_PA6_CAN0RX    0x06000000  // CAN0RX on PA6
+#define GPIO_PCTL_PA6_USB0EPEN  0x08000000  // USB0EPEN on PA6
+#define GPIO_PCTL_PA6_U1CTS     0x09000000  // U1CTS on PA6
+#define GPIO_PCTL_PA5_M         0x00F00000  // PA5 mask
+#define GPIO_PCTL_PA5_SSI0TX    0x00100000  // SSI0TX on PA5
+#define GPIO_PCTL_PA5_PWM7      0x00400000  // PWM7 on PA5
+#define GPIO_PCTL_PA5_CAN0TX    0x00500000  // CAN0TX on PA5
+#define GPIO_PCTL_PA5_I2S0TXWS  0x00900000  // I2S0TXWS on PA5
+#define GPIO_PCTL_PA4_M         0x000F0000  // PA4 mask
+#define GPIO_PCTL_PA4_SSI0RX    0x00010000  // SSI0RX on PA4
+#define GPIO_PCTL_PA4_PWM6      0x00040000  // PWM6 on PA4
+#define GPIO_PCTL_PA4_CAN0RX    0x00050000  // CAN0RX on PA4
+#define GPIO_PCTL_PA4_I2S0TXSCK 0x00090000  // I2S0TXSCK on PA4
+#define GPIO_PCTL_PA3_M         0x0000F000  // PA3 mask
+#define GPIO_PCTL_PA3_SSI0FSS   0x00001000  // SSI0FSS on PA3
+#define GPIO_PCTL_PA3_PWM5      0x00004000  // PWM5 on PA3
+#define GPIO_PCTL_PA3_I2S0RXMCLK \
+                                0x00009000  // I2S0RXMCLK on PA3
+#define GPIO_PCTL_PA2_M         0x00000F00  // PA2 mask
+#define GPIO_PCTL_PA2_SSI0CLK   0x00000100  // SSI0CLK on PA2
+#define GPIO_PCTL_PA2_PWM4      0x00000400  // PWM4 on PA2
+#define GPIO_PCTL_PA2_I2S0RXSD  0x00000900  // I2S0RXSD on PA2
+#define GPIO_PCTL_PA1_M         0x000000F0  // PA1 mask
+#define GPIO_PCTL_PA1_U0TX      0x00000010  // U0TX on PA1
+#define GPIO_PCTL_PA1_I2C1SDA   0x00000080  // I2C1SDA on PA1
+#define GPIO_PCTL_PA1_U1TX      0x00000090  // U1TX on PA1
+#define GPIO_PCTL_PA0_M         0x0000000F  // PA0 mask
+#define GPIO_PCTL_PA0_U0RX      0x00000001  // U0RX on PA0
+#define GPIO_PCTL_PA0_I2C1SCL   0x00000008  // I2C1SCL on PA0
+#define GPIO_PCTL_PA0_U1RX      0x00000009  // U1RX on PA0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_PCTL register for
+// port B.
+//
+//*****************************************************************************
+#define GPIO_PCTL_PB7_M         0xF0000000  // PB7 mask
+#define GPIO_PCTL_PB7_NMI       0x40000000  // NMI on PB7
+#define GPIO_PCTL_PB6_M         0x0F000000  // PB6 mask
+#define GPIO_PCTL_PB6_CCP1      0x01000000  // CCP1 on PB6
+#define GPIO_PCTL_PB6_CCP7      0x02000000  // CCP7 on PB6
+#define GPIO_PCTL_PB6_C0O       0x03000000  // C0O on PB6
+#define GPIO_PCTL_PB6_FAULT1    0x04000000  // FAULT1 on PB6
+#define GPIO_PCTL_PB6_IDX0      0x05000000  // IDX0 on PB6
+#define GPIO_PCTL_PB6_CCP5      0x06000000  // CCP5 on PB6
+#define GPIO_PCTL_PB6_I2S0TXSCK 0x09000000  // I2S0TXSCK on PB6
+#define GPIO_PCTL_PB5_M         0x00F00000  // PB5 mask
+#define GPIO_PCTL_PB5_C0O       0x00100000  // C0O on PB5
+#define GPIO_PCTL_PB5_CCP5      0x00200000  // CCP5 on PB5
+#define GPIO_PCTL_PB5_CCP6      0x00300000  // CCP6 on PB5
+#define GPIO_PCTL_PB5_CCP0      0x00400000  // CCP0 on PB5
+#define GPIO_PCTL_PB5_CAN0TX    0x00500000  // CAN0TX on PB5
+#define GPIO_PCTL_PB5_CCP2      0x00600000  // CCP2 on PB5
+#define GPIO_PCTL_PB5_U1TX      0x00700000  // U1TX on PB5
+#define GPIO_PCTL_PB5_EPI0S22   0x00800000  // EPI0S22 on PB5
+#define GPIO_PCTL_PB4_M         0x000F0000  // PB4 mask
+#define GPIO_PCTL_PB4_U2RX      0x00040000  // U2RX on PB4
+#define GPIO_PCTL_PB4_CAN0RX    0x00050000  // CAN0RX on PB4
+#define GPIO_PCTL_PB4_IDX0      0x00060000  // IDX0 on PB4
+#define GPIO_PCTL_PB4_U1RX      0x00070000  // U1RX on PB4
+#define GPIO_PCTL_PB4_EPI0S23   0x00080000  // EPI0S23 on PB4
+#define GPIO_PCTL_PB3_M         0x0000F000  // PB3 mask
+#define GPIO_PCTL_PB3_I2C0SDA   0x00001000  // I2C0SDA on PB3
+#define GPIO_PCTL_PB3_FAULT0    0x00002000  // FAULT0 on PB3
+#define GPIO_PCTL_PB3_FAULT3    0x00004000  // FAULT3 on PB3
+#define GPIO_PCTL_PB3_USB0PFLT  0x00008000  // USB0PFLT on PB3
+#define GPIO_PCTL_PB2_M         0x00000F00  // PB2 mask
+#define GPIO_PCTL_PB2_I2C0SCL   0x00000100  // I2C0SCL on PB2
+#define GPIO_PCTL_PB2_IDX0      0x00000200  // IDX0 on PB2
+#define GPIO_PCTL_PB2_CCP3      0x00000400  // CCP3 on PB2
+#define GPIO_PCTL_PB2_CCP0      0x00000500  // CCP0 on PB2
+#define GPIO_PCTL_PB2_USB0EPEN  0x00000800  // USB0EPEN on PB2
+#define GPIO_PCTL_PB1_M         0x000000F0  // PB1 mask
+#define GPIO_PCTL_PB1_CCP2      0x00000010  // CCP2 on PB1
+#define GPIO_PCTL_PB1_PWM3      0x00000020  // PWM3 on PB1
+#define GPIO_PCTL_PB1_CCP1      0x00000040  // CCP1 on PB1
+#define GPIO_PCTL_PB1_U1TX      0x00000050  // U1TX on PB1
+#define GPIO_PCTL_PB0_M         0x0000000F  // PB0 mask
+#define GPIO_PCTL_PB0_CCP0      0x00000001  // CCP0 on PB0
+#define GPIO_PCTL_PB0_PWM2      0x00000002  // PWM2 on PB0
+#define GPIO_PCTL_PB0_U1RX      0x00000005  // U1RX on PB0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_PCTL register for
+// port C.
+//
+//*****************************************************************************
+#define GPIO_PCTL_PC7_M         0xF0000000  // PC7 mask
+#define GPIO_PCTL_PC7_CCP4      0x10000000  // CCP4 on PC7
+#define GPIO_PCTL_PC7_PHB0      0x20000000  // PHB0 on PC7
+#define GPIO_PCTL_PC7_CCP0      0x40000000  // CCP0 on PC7
+#define GPIO_PCTL_PC7_U1TX      0x50000000  // U1TX on PC7
+#define GPIO_PCTL_PC7_USB0PFLT  0x60000000  // USB0PFLT on PC7
+#define GPIO_PCTL_PC7_C1O       0x70000000  // C1O on PC7
+#define GPIO_PCTL_PC7_EPI0S5    0x80000000  // EPI0S5 on PC7
+#define GPIO_PCTL_PC6_M         0x0F000000  // PC6 mask
+#define GPIO_PCTL_PC6_CCP3      0x01000000  // CCP3 on PC6
+#define GPIO_PCTL_PC6_PHB0      0x02000000  // PHB0 on PC6
+#define GPIO_PCTL_PC6_C2O       0x03000000  // C2O on PC6
+#define GPIO_PCTL_PC6_PWM7      0x04000000  // PWM7 on PC6
+#define GPIO_PCTL_PC6_U1RX      0x05000000  // U1RX on PC6
+#define GPIO_PCTL_PC6_CCP0      0x06000000  // CCP0 on PC6
+#define GPIO_PCTL_PC6_USB0PFLT  0x07000000  // USB0PFLT on PC6
+#define GPIO_PCTL_PC6_EPI0S4    0x08000000  // EPI0S4 on PC6
+#define GPIO_PCTL_PC5_M         0x00F00000  // PC5 mask
+#define GPIO_PCTL_PC5_CCP1      0x00100000  // CCP1 on PC5
+#define GPIO_PCTL_PC5_C1O       0x00200000  // C1O on PC5
+#define GPIO_PCTL_PC5_C0O       0x00300000  // C0O on PC5
+#define GPIO_PCTL_PC5_FAULT2    0x00400000  // FAULT2 on PC5
+#define GPIO_PCTL_PC5_CCP3      0x00500000  // CCP3 on PC5
+#define GPIO_PCTL_PC5_USB0EPEN  0x00600000  // USB0EPEN on PC5
+#define GPIO_PCTL_PC5_EPI0S3    0x00800000  // EPI0S3 on PC5
+#define GPIO_PCTL_PC4_M         0x000F0000  // PC4 mask
+#define GPIO_PCTL_PC4_CCP5      0x00010000  // CCP5 on PC4
+#define GPIO_PCTL_PC4_PHA0      0x00020000  // PHA0 on PC4
+#define GPIO_PCTL_PC4_PWM6      0x00040000  // PWM6 on PC4
+#define GPIO_PCTL_PC4_CCP2      0x00050000  // CCP2 on PC4
+#define GPIO_PCTL_PC4_CCP4      0x00060000  // CCP4 on PC4
+#define GPIO_PCTL_PC4_EPI0S2    0x00080000  // EPI0S2 on PC4
+#define GPIO_PCTL_PC4_CCP1      0x00090000  // CCP1 on PC4
+#define GPIO_PCTL_PC3_M         0x0000F000  // PC3 mask
+#define GPIO_PCTL_PC3_TDO       0x00003000  // TDO on PC3
+#define GPIO_PCTL_PC2_M         0x00000F00  // PC2 mask
+#define GPIO_PCTL_PC2_TDI       0x00000300  // TDI on PC2
+#define GPIO_PCTL_PC1_M         0x000000F0  // PC1 mask
+#define GPIO_PCTL_PC1_TMS       0x00000030  // TMS on PC1
+#define GPIO_PCTL_PC0_M         0x0000000F  // PC0 mask
+#define GPIO_PCTL_PC0_TCK       0x00000003  // TCK on PC0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_PCTL register for
+// port D.
+//
+//*****************************************************************************
+#define GPIO_PCTL_PD7_M         0xF0000000  // PD7 mask
+#define GPIO_PCTL_PD7_IDX0      0x10000000  // IDX0 on PD7
+#define GPIO_PCTL_PD7_C0O       0x20000000  // C0O on PD7
+#define GPIO_PCTL_PD7_CCP1      0x30000000  // CCP1 on PD7
+#define GPIO_PCTL_PD7_I2S0TXWS  0x80000000  // I2S0TXWS on PD7
+#define GPIO_PCTL_PD7_U1DTR     0x90000000  // U1DTR on PD7
+#define GPIO_PCTL_PD7_EPI0S30   0xA0000000  // EPI0S30 on PD7
+#define GPIO_PCTL_PD6_M         0x0F000000  // PD6 mask
+#define GPIO_PCTL_PD6_FAULT0    0x01000000  // FAULT0 on PD6
+#define GPIO_PCTL_PD6_I2S0TXSCK 0x08000000  // I2S0TXSCK on PD6
+#define GPIO_PCTL_PD6_U2TX      0x09000000  // U2TX on PD6
+#define GPIO_PCTL_PD6_EPI0S29   0x0A000000  // EPI0S29 on PD6
+#define GPIO_PCTL_PD5_M         0x00F00000  // PD5 mask
+#define GPIO_PCTL_PD5_CCP2      0x00100000  // CCP2 on PD5
+#define GPIO_PCTL_PD5_CCP4      0x00200000  // CCP4 on PD5
+#define GPIO_PCTL_PD5_I2S0RXMCLK \
+                                0x00800000  // I2S0RXMCLK on PD5
+#define GPIO_PCTL_PD5_U2RX      0x00900000  // U2RX on PD5
+#define GPIO_PCTL_PD5_EPI0S28   0x00A00000  // EPI0S28 on PD5
+#define GPIO_PCTL_PD4_M         0x000F0000  // PD4 mask
+#define GPIO_PCTL_PD4_CCP0      0x00010000  // CCP0 on PD4
+#define GPIO_PCTL_PD4_CCP3      0x00020000  // CCP3 on PD4
+#define GPIO_PCTL_PD4_I2S0RXSD  0x00080000  // I2S0RXSD on PD4
+#define GPIO_PCTL_PD4_U1RI      0x00090000  // U1RI on PD4
+#define GPIO_PCTL_PD4_EPI0S19   0x000A0000  // EPI0S19 on PD4
+#define GPIO_PCTL_PD3_M         0x0000F000  // PD3 mask
+#define GPIO_PCTL_PD3_U1TX      0x00001000  // U1TX on PD3
+#define GPIO_PCTL_PD3_CCP7      0x00002000  // CCP7 on PD3
+#define GPIO_PCTL_PD3_PWM3      0x00003000  // PWM3 on PD3
+#define GPIO_PCTL_PD3_CCP0      0x00004000  // CCP0 on PD3
+#define GPIO_PCTL_PD3_EPI0S21   0x00008000  // EPI0S21 on PD3
+#define GPIO_PCTL_PD2_M         0x00000F00  // PD2 mask
+#define GPIO_PCTL_PD2_U1RX      0x00000100  // U1RX on PD2
+#define GPIO_PCTL_PD2_CCP6      0x00000200  // CCP6 on PD2
+#define GPIO_PCTL_PD2_PWM2      0x00000300  // PWM2 on PD2
+#define GPIO_PCTL_PD2_CCP5      0x00000400  // CCP5 on PD2
+#define GPIO_PCTL_PD2_EPI0S20   0x00000800  // EPI0S20 on PD2
+#define GPIO_PCTL_PD1_M         0x000000F0  // PD1 mask
+#define GPIO_PCTL_PD1_PWM1      0x00000010  // PWM1 on PD1
+#define GPIO_PCTL_PD1_CAN0TX    0x00000020  // CAN0TX on PD1
+#define GPIO_PCTL_PD1_PHA0      0x00000030  // PHA0 on PD1
+#define GPIO_PCTL_PD1_U2TX      0x00000040  // U2TX on PD1
+#define GPIO_PCTL_PD1_U1TX      0x00000050  // U1TX on PD1
+#define GPIO_PCTL_PD1_CCP7      0x00000060  // CCP7 on PD1
+#define GPIO_PCTL_PD1_I2S0RXWS  0x00000080  // I2S0RXWS on PD1
+#define GPIO_PCTL_PD1_U1DCD     0x00000090  // U1DCD on PD1
+#define GPIO_PCTL_PD1_CCP2      0x000000A0  // CCP2 on PD1
+#define GPIO_PCTL_PD1_PHB1      0x000000B0  // PHB1 on PD1
+#define GPIO_PCTL_PD0_M         0x0000000F  // PD0 mask
+#define GPIO_PCTL_PD0_PWM0      0x00000001  // PWM0 on PD0
+#define GPIO_PCTL_PD0_CAN0RX    0x00000002  // CAN0RX on PD0
+#define GPIO_PCTL_PD0_IDX0      0x00000003  // IDX0 on PD0
+#define GPIO_PCTL_PD0_U2RX      0x00000004  // U2RX on PD0
+#define GPIO_PCTL_PD0_U1RX      0x00000005  // U1RX on PD0
+#define GPIO_PCTL_PD0_CCP6      0x00000006  // CCP6 on PD0
+#define GPIO_PCTL_PD0_I2S0RXSCK 0x00000008  // I2S0RXSCK on PD0
+#define GPIO_PCTL_PD0_U1CTS     0x00000009  // U1CTS on PD0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_PCTL register for
+// port E.
+//
+//*****************************************************************************
+#define GPIO_PCTL_PE7_M         0xF0000000  // PE7 mask
+#define GPIO_PCTL_PE7_PWM5      0x10000000  // PWM5 on PE7
+#define GPIO_PCTL_PE7_C2O       0x20000000  // C2O on PE7
+#define GPIO_PCTL_PE7_U1DCD     0x90000000  // U1DCD on PE7
+#define GPIO_PCTL_PE6_M         0x0F000000  // PE6 mask
+#define GPIO_PCTL_PE6_PWM4      0x01000000  // PWM4 on PE6
+#define GPIO_PCTL_PE6_C1O       0x02000000  // C1O on PE6
+#define GPIO_PCTL_PE6_U1CTS     0x09000000  // U1CTS on PE6
+#define GPIO_PCTL_PE5_M         0x00F00000  // PE5 mask
+#define GPIO_PCTL_PE5_CCP5      0x00100000  // CCP5 on PE5
+#define GPIO_PCTL_PE5_I2S0TXSD  0x00900000  // I2S0TXSD on PE5
+#define GPIO_PCTL_PE4_M         0x000F0000  // PE4 mask
+#define GPIO_PCTL_PE4_CCP3      0x00010000  // CCP3 on PE4
+#define GPIO_PCTL_PE4_FAULT0    0x00040000  // FAULT0 on PE4
+#define GPIO_PCTL_PE4_U2TX      0x00050000  // U2TX on PE4
+#define GPIO_PCTL_PE4_CCP2      0x00060000  // CCP2 on PE4
+#define GPIO_PCTL_PE4_I2S0TXWS  0x00090000  // I2S0TXWS on PE4
+#define GPIO_PCTL_PE3_M         0x0000F000  // PE3 mask
+#define GPIO_PCTL_PE3_CCP1      0x00001000  // CCP1 on PE3
+#define GPIO_PCTL_PE3_SSI1TX    0x00002000  // SSI1TX on PE3
+#define GPIO_PCTL_PE3_PHA1      0x00003000  // PHA1 on PE3
+#define GPIO_PCTL_PE3_PHB0      0x00004000  // PHB0 on PE3
+#define GPIO_PCTL_PE3_CCP7      0x00005000  // CCP7 on PE3
+#define GPIO_PCTL_PE3_EPI0S25   0x00008000  // EPI0S25 on PE3
+#define GPIO_PCTL_PE2_M         0x00000F00  // PE2 mask
+#define GPIO_PCTL_PE2_CCP4      0x00000100  // CCP4 on PE2
+#define GPIO_PCTL_PE2_SSI1RX    0x00000200  // SSI1RX on PE2
+#define GPIO_PCTL_PE2_PHB1      0x00000300  // PHB1 on PE2
+#define GPIO_PCTL_PE2_PHA0      0x00000400  // PHA0 on PE2
+#define GPIO_PCTL_PE2_CCP2      0x00000500  // CCP2 on PE2
+#define GPIO_PCTL_PE2_EPI0S24   0x00000800  // EPI0S24 on PE2
+#define GPIO_PCTL_PE1_M         0x000000F0  // PE1 mask
+#define GPIO_PCTL_PE1_PWM5      0x00000010  // PWM5 on PE1
+#define GPIO_PCTL_PE1_SSI1FSS   0x00000020  // SSI1FSS on PE1
+#define GPIO_PCTL_PE1_FAULT0    0x00000030  // FAULT0 on PE1
+#define GPIO_PCTL_PE1_CCP2      0x00000040  // CCP2 on PE1
+#define GPIO_PCTL_PE1_CCP6      0x00000050  // CCP6 on PE1
+#define GPIO_PCTL_PE1_EPI0S9    0x00000080  // EPI0S9 on PE1
+#define GPIO_PCTL_PE0_M         0x0000000F  // PE0 mask
+#define GPIO_PCTL_PE0_PWM4      0x00000001  // PWM4 on PE0
+#define GPIO_PCTL_PE0_SSI1CLK   0x00000002  // SSI1CLK on PE0
+#define GPIO_PCTL_PE0_CCP3      0x00000003  // CCP3 on PE0
+#define GPIO_PCTL_PE0_EPI0S8    0x00000008  // EPI0S8 on PE0
+#define GPIO_PCTL_PE0_USB0PFLT  0x00000009  // USB0PFLT on PE0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_PCTL register for
+// port F.
+//
+//*****************************************************************************
+#define GPIO_PCTL_PF5_M         0x00F00000  // PF5 mask
+#define GPIO_PCTL_PF5_CCP2      0x00100000  // CCP2 on PF5
+#define GPIO_PCTL_PF5_C1O       0x00200000  // C1O on PF5
+#define GPIO_PCTL_PF5_EPI0S15   0x00800000  // EPI0S15 on PF5
+#define GPIO_PCTL_PF5_SSI1TX    0x00900000  // SSI1TX on PF5
+#define GPIO_PCTL_PF4_M         0x000F0000  // PF4 mask
+#define GPIO_PCTL_PF4_CCP0      0x00010000  // CCP0 on PF4
+#define GPIO_PCTL_PF4_C0O       0x00020000  // C0O on PF4
+#define GPIO_PCTL_PF4_FAULT0    0x00040000  // FAULT0 on PF4
+#define GPIO_PCTL_PF4_EPI0S12   0x00080000  // EPI0S12 on PF4
+#define GPIO_PCTL_PF4_SSI1RX    0x00090000  // SSI1RX on PF4
+#define GPIO_PCTL_PF3_M         0x0000F000  // PF3 mask
+#define GPIO_PCTL_PF3_LED0      0x00001000  // LED0 on PF3
+#define GPIO_PCTL_PF3_PWM5      0x00002000  // PWM5 on PF3
+#define GPIO_PCTL_PF3_PWM3      0x00004000  // PWM3 on PF3
+#define GPIO_PCTL_PF3_SSI1FSS   0x00009000  // SSI1FSS on PF3
+#define GPIO_PCTL_PF2_M         0x00000F00  // PF2 mask
+#define GPIO_PCTL_PF2_LED1      0x00000100  // LED1 on PF2
+#define GPIO_PCTL_PF2_PWM4      0x00000200  // PWM4 on PF2
+#define GPIO_PCTL_PF2_PWM2      0x00000400  // PWM2 on PF2
+#define GPIO_PCTL_PF2_SSI1CLK   0x00000900  // SSI1CLK on PF2
+#define GPIO_PCTL_PF1_M         0x000000F0  // PF1 mask
+#define GPIO_PCTL_PF1_CAN1TX    0x00000010  // CAN1TX on PF1
+#define GPIO_PCTL_PF1_IDX1      0x00000020  // IDX1 on PF1
+#define GPIO_PCTL_PF1_PWM1      0x00000030  // PWM1 on PF1
+#define GPIO_PCTL_PF1_I2S0TXMCLK \
+                                0x00000080  // I2S0TXMCLK on PF1
+#define GPIO_PCTL_PF1_U1RTS     0x00000090  // U1RTS on PF1
+#define GPIO_PCTL_PF1_CCP3      0x000000A0  // CCP3 on PF1
+#define GPIO_PCTL_PF0_M         0x0000000F  // PF0 mask
+#define GPIO_PCTL_PF0_CAN1RX    0x00000001  // CAN1RX on PF0
+#define GPIO_PCTL_PF0_PHB0      0x00000002  // PHB0 on PF0
+#define GPIO_PCTL_PF0_PWM0      0x00000003  // PWM0 on PF0
+#define GPIO_PCTL_PF0_I2S0TXSD  0x00000008  // I2S0TXSD on PF0
+#define GPIO_PCTL_PF0_U1DSR     0x00000009  // U1DSR on PF0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_PCTL register for
+// port G.
+//
+//*****************************************************************************
+#define GPIO_PCTL_PG7_M         0xF0000000  // PG7 mask
+#define GPIO_PCTL_PG7_PHB1      0x10000000  // PHB1 on PG7
+#define GPIO_PCTL_PG7_PWM7      0x40000000  // PWM7 on PG7
+#define GPIO_PCTL_PG7_CCP5      0x80000000  // CCP5 on PG7
+#define GPIO_PCTL_PG7_EPI0S31   0x90000000  // EPI0S31 on PG7
+#define GPIO_PCTL_PG1_M         0x000000F0  // PG1 mask
+#define GPIO_PCTL_PG1_U2TX      0x00000010  // U2TX on PG1
+#define GPIO_PCTL_PG1_PWM1      0x00000020  // PWM1 on PG1
+#define GPIO_PCTL_PG1_I2C1SDA   0x00000030  // I2C1SDA on PG1
+#define GPIO_PCTL_PG1_PWM5      0x00000040  // PWM5 on PG1
+#define GPIO_PCTL_PG1_EPI0S14   0x00000080  // EPI0S14 on PG1
+#define GPIO_PCTL_PG0_M         0x0000000F  // PG0 mask
+#define GPIO_PCTL_PG0_U2RX      0x00000001  // U2RX on PG0
+#define GPIO_PCTL_PG0_PWM0      0x00000002  // PWM0 on PG0
+#define GPIO_PCTL_PG0_I2C1SCL   0x00000003  // I2C1SCL on PG0
+#define GPIO_PCTL_PG0_PWM4      0x00000004  // PWM4 on PG0
+#define GPIO_PCTL_PG0_USB0EPEN  0x00000007  // USB0EPEN on PG0
+#define GPIO_PCTL_PG0_EPI0S13   0x00000008  // EPI0S13 on PG0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_PCTL register for
+// port H.
+//
+//*****************************************************************************
+#define GPIO_PCTL_PH7_M         0xF0000000  // PH7 mask
+#define GPIO_PCTL_PH7_EPI0S27   0x80000000  // EPI0S27 on PH7
+#define GPIO_PCTL_PH7_PWM5      0xA0000000  // PWM5 on PH7
+#define GPIO_PCTL_PH7_SSI1TX    0xB0000000  // SSI1TX on PH7
+#define GPIO_PCTL_PH6_M         0x0F000000  // PH6 mask
+#define GPIO_PCTL_PH6_EPI0S26   0x08000000  // EPI0S26 on PH6
+#define GPIO_PCTL_PH6_PWM4      0x0A000000  // PWM4 on PH6
+#define GPIO_PCTL_PH6_SSI1RX    0x0B000000  // SSI1RX on PH6
+#define GPIO_PCTL_PH5_M         0x00F00000  // PH5 mask
+#define GPIO_PCTL_PH5_EPI0S11   0x00800000  // EPI0S11 on PH5
+#define GPIO_PCTL_PH5_FAULT2    0x00A00000  // FAULT2 on PH5
+#define GPIO_PCTL_PH5_SSI1FSS   0x00B00000  // SSI1FSS on PH5
+#define GPIO_PCTL_PH4_M         0x000F0000  // PH4 mask
+#define GPIO_PCTL_PH4_USB0PFLT  0x00040000  // USB0PFLT on PH4
+#define GPIO_PCTL_PH4_EPI0S10   0x00080000  // EPI0S10 on PH4
+#define GPIO_PCTL_PH4_SSI1CLK   0x000B0000  // SSI1CLK on PH4
+#define GPIO_PCTL_PH3_M         0x0000F000  // PH3 mask
+#define GPIO_PCTL_PH3_PHB0      0x00001000  // PHB0 on PH3
+#define GPIO_PCTL_PH3_FAULT0    0x00002000  // FAULT0 on PH3
+#define GPIO_PCTL_PH3_USB0EPEN  0x00004000  // USB0EPEN on PH3
+#define GPIO_PCTL_PH3_EPI0S0    0x00008000  // EPI0S0 on PH3
+#define GPIO_PCTL_PH2_M         0x00000F00  // PH2 mask
+#define GPIO_PCTL_PH2_IDX1      0x00000100  // IDX1 on PH2
+#define GPIO_PCTL_PH2_C1O       0x00000200  // C1O on PH2
+#define GPIO_PCTL_PH2_FAULT3    0x00000400  // FAULT3 on PH2
+#define GPIO_PCTL_PH2_EPI0S1    0x00000800  // EPI0S1 on PH2
+#define GPIO_PCTL_PH1_M         0x000000F0  // PH1 mask
+#define GPIO_PCTL_PH1_CCP7      0x00000010  // CCP7 on PH1
+#define GPIO_PCTL_PH1_PWM3      0x00000020  // PWM3 on PH1
+#define GPIO_PCTL_PH1_EPI0S7    0x00000080  // EPI0S7 on PH1
+#define GPIO_PCTL_PH1_PWM5      0x00000090  // PWM5 on PH1
+#define GPIO_PCTL_PH0_M         0x0000000F  // PH0 mask
+#define GPIO_PCTL_PH0_CCP6      0x00000001  // CCP6 on PH0
+#define GPIO_PCTL_PH0_PWM2      0x00000002  // PWM2 on PH0
+#define GPIO_PCTL_PH0_EPI0S6    0x00000008  // EPI0S6 on PH0
+#define GPIO_PCTL_PH0_PWM4      0x00000009  // PWM4 on PH0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_PCTL register for
+// port J.
+//
+//*****************************************************************************
+#define GPIO_PCTL_PJ7_M         0xF0000000  // PJ7 mask
+#define GPIO_PCTL_PJ7_U1DTR     0x90000000  // U1DTR on PJ7
+#define GPIO_PCTL_PJ7_CCP0      0xA0000000  // CCP0 on PJ7
+#define GPIO_PCTL_PJ6_M         0x0F000000  // PJ6 mask
+#define GPIO_PCTL_PJ6_EPI0S30   0x08000000  // EPI0S30 on PJ6
+#define GPIO_PCTL_PJ6_U1RTS     0x09000000  // U1RTS on PJ6
+#define GPIO_PCTL_PJ6_CCP1      0x0A000000  // CCP1 on PJ6
+#define GPIO_PCTL_PJ5_M         0x00F00000  // PJ5 mask
+#define GPIO_PCTL_PJ5_EPI0S29   0x00800000  // EPI0S29 on PJ5
+#define GPIO_PCTL_PJ5_U1DSR     0x00900000  // U1DSR on PJ5
+#define GPIO_PCTL_PJ5_CCP2      0x00A00000  // CCP2 on PJ5
+#define GPIO_PCTL_PJ4_M         0x000F0000  // PJ4 mask
+#define GPIO_PCTL_PJ4_EPI0S28   0x00080000  // EPI0S28 on PJ4
+#define GPIO_PCTL_PJ4_U1DCD     0x00090000  // U1DCD on PJ4
+#define GPIO_PCTL_PJ4_CCP4      0x000A0000  // CCP4 on PJ4
+#define GPIO_PCTL_PJ3_M         0x0000F000  // PJ3 mask
+#define GPIO_PCTL_PJ3_EPI0S19   0x00008000  // EPI0S19 on PJ3
+#define GPIO_PCTL_PJ3_U1CTS     0x00009000  // U1CTS on PJ3
+#define GPIO_PCTL_PJ3_CCP6      0x0000A000  // CCP6 on PJ3
+#define GPIO_PCTL_PJ2_M         0x00000F00  // PJ2 mask
+#define GPIO_PCTL_PJ2_EPI0S18   0x00000800  // EPI0S18 on PJ2
+#define GPIO_PCTL_PJ2_CCP0      0x00000900  // CCP0 on PJ2
+#define GPIO_PCTL_PJ2_FAULT0    0x00000A00  // FAULT0 on PJ2
+#define GPIO_PCTL_PJ1_M         0x000000F0  // PJ1 mask
+#define GPIO_PCTL_PJ1_EPI0S17   0x00000080  // EPI0S17 on PJ1
+#define GPIO_PCTL_PJ1_USB0PFLT  0x00000090  // USB0PFLT on PJ1
+#define GPIO_PCTL_PJ1_PWM1      0x000000A0  // PWM1 on PJ1
+#define GPIO_PCTL_PJ1_I2C1SDA   0x000000B0  // I2C1SDA on PJ1
+#define GPIO_PCTL_PJ0_M         0x0000000F  // PJ0 mask
+#define GPIO_PCTL_PJ0_EPI0S16   0x00000008  // EPI0S16 on PJ0
+#define GPIO_PCTL_PJ0_PWM0      0x0000000A  // PWM0 on PJ0
+#define GPIO_PCTL_PJ0_I2C1SCL   0x0000000B  // I2C1SCL on PJ0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_CR0 register.
+//
+//*****************************************************************************
+#define SSI_CR0_SCR_M           0x0000FF00  // SSI Serial Clock Rate
+#define SSI_CR0_SPH             0x00000080  // SSI Serial Clock Phase
+#define SSI_CR0_SPO             0x00000040  // SSI Serial Clock Polarity
+#define SSI_CR0_FRF_M           0x00000030  // SSI Frame Format Select
+#define SSI_CR0_FRF_MOTO        0x00000000  // Freescale SPI Frame Format
+#define SSI_CR0_FRF_TI          0x00000010  // Texas Instruments Synchronous
+                                            // Serial Frame Format
+#define SSI_CR0_FRF_NMW         0x00000020  // MICROWIRE Frame Format
+#define SSI_CR0_DSS_M           0x0000000F  // SSI Data Size Select
+#define SSI_CR0_DSS_4           0x00000003  // 4-bit data
+#define SSI_CR0_DSS_5           0x00000004  // 5-bit data
+#define SSI_CR0_DSS_6           0x00000005  // 6-bit data
+#define SSI_CR0_DSS_7           0x00000006  // 7-bit data
+#define SSI_CR0_DSS_8           0x00000007  // 8-bit data
+#define SSI_CR0_DSS_9           0x00000008  // 9-bit data
+#define SSI_CR0_DSS_10          0x00000009  // 10-bit data
+#define SSI_CR0_DSS_11          0x0000000A  // 11-bit data
+#define SSI_CR0_DSS_12          0x0000000B  // 12-bit data
+#define SSI_CR0_DSS_13          0x0000000C  // 13-bit data
+#define SSI_CR0_DSS_14          0x0000000D  // 14-bit data
+#define SSI_CR0_DSS_15          0x0000000E  // 15-bit data
+#define SSI_CR0_DSS_16          0x0000000F  // 16-bit data
+#define SSI_CR0_SCR_S           8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_CR1 register.
+//
+//*****************************************************************************
+#define SSI_CR1_EOT             0x00000010  // End of Transmission
+#define SSI_CR1_SOD             0x00000008  // SSI Slave Mode Output Disable
+#define SSI_CR1_MS              0x00000004  // SSI Master/Slave Select
+#define SSI_CR1_SSE             0x00000002  // SSI Synchronous Serial Port
+                                            // Enable
+#define SSI_CR1_LBM             0x00000001  // SSI Loopback Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_DR register.
+//
+//*****************************************************************************
+#define SSI_DR_DATA_M           0x0000FFFF  // SSI Receive/Transmit Data
+#define SSI_DR_DATA_S           0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_SR register.
+//
+//*****************************************************************************
+#define SSI_SR_BSY              0x00000010  // SSI Busy Bit
+#define SSI_SR_RFF              0x00000008  // SSI Receive FIFO Full
+#define SSI_SR_RNE              0x00000004  // SSI Receive FIFO Not Empty
+#define SSI_SR_TNF              0x00000002  // SSI Transmit FIFO Not Full
+#define SSI_SR_TFE              0x00000001  // SSI Transmit FIFO Empty
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_CPSR register.
+//
+//*****************************************************************************
+#define SSI_CPSR_CPSDVSR_M      0x000000FF  // SSI Clock Prescale Divisor
+#define SSI_CPSR_CPSDVSR_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_IM register.
+//
+//*****************************************************************************
+#define SSI_IM_TXIM             0x00000008  // SSI Transmit FIFO Interrupt Mask
+#define SSI_IM_RXIM             0x00000004  // SSI Receive FIFO Interrupt Mask
+#define SSI_IM_RTIM             0x00000002  // SSI Receive Time-Out Interrupt
+                                            // Mask
+#define SSI_IM_RORIM            0x00000001  // SSI Receive Overrun Interrupt
+                                            // Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_RIS register.
+//
+//*****************************************************************************
+#define SSI_RIS_TXRIS           0x00000008  // SSI Transmit FIFO Raw Interrupt
+                                            // Status
+#define SSI_RIS_RXRIS           0x00000004  // SSI Receive FIFO Raw Interrupt
+                                            // Status
+#define SSI_RIS_RTRIS           0x00000002  // SSI Receive Time-Out Raw
+                                            // Interrupt Status
+#define SSI_RIS_RORRIS          0x00000001  // SSI Receive Overrun Raw
+                                            // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_MIS register.
+//
+//*****************************************************************************
+#define SSI_MIS_TXMIS           0x00000008  // SSI Transmit FIFO Masked
+                                            // Interrupt Status
+#define SSI_MIS_RXMIS           0x00000004  // SSI Receive FIFO Masked
+                                            // Interrupt Status
+#define SSI_MIS_RTMIS           0x00000002  // SSI Receive Time-Out Masked
+                                            // Interrupt Status
+#define SSI_MIS_RORMIS          0x00000001  // SSI Receive Overrun Masked
+                                            // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_ICR register.
+//
+//*****************************************************************************
+#define SSI_ICR_RTIC            0x00000002  // SSI Receive Time-Out Interrupt
+                                            // Clear
+#define SSI_ICR_RORIC           0x00000001  // SSI Receive Overrun Interrupt
+                                            // Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_DMACTL register.
+//
+//*****************************************************************************
+#define SSI_DMACTL_TXDMAE       0x00000002  // Transmit DMA Enable
+#define SSI_DMACTL_RXDMAE       0x00000001  // Receive DMA Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_DR register.
+//
+//*****************************************************************************
+#define UART_DR_OE              0x00000800  // UART Overrun Error
+#define UART_DR_BE              0x00000400  // UART Break Error
+#define UART_DR_PE              0x00000200  // UART Parity Error
+#define UART_DR_FE              0x00000100  // UART Framing Error
+#define UART_DR_DATA_M          0x000000FF  // Data Transmitted or Received
+#define UART_DR_DATA_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_RSR register.
+//
+//*****************************************************************************
+#define UART_RSR_OE             0x00000008  // UART Overrun Error
+#define UART_RSR_BE             0x00000004  // UART Break Error
+#define UART_RSR_PE             0x00000002  // UART Parity Error
+#define UART_RSR_FE             0x00000001  // UART Framing Error
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_ECR register.
+//
+//*****************************************************************************
+#define UART_ECR_DATA_M         0x000000FF  // Error Clear
+#define UART_ECR_DATA_S         0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_FR register.
+//
+//*****************************************************************************
+#define UART_FR_RI              0x00000100  // Ring Indicator
+#define UART_FR_TXFE            0x00000080  // UART Transmit FIFO Empty
+#define UART_FR_RXFF            0x00000040  // UART Receive FIFO Full
+#define UART_FR_TXFF            0x00000020  // UART Transmit FIFO Full
+#define UART_FR_RXFE            0x00000010  // UART Receive FIFO Empty
+#define UART_FR_BUSY            0x00000008  // UART Busy
+#define UART_FR_DCD             0x00000004  // Data Carrier Detect
+#define UART_FR_DSR             0x00000002  // Data Set Ready
+#define UART_FR_CTS             0x00000001  // Clear To Send
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_ILPR register.
+//
+//*****************************************************************************
+#define UART_ILPR_ILPDVSR_M     0x000000FF  // IrDA Low-Power Divisor
+#define UART_ILPR_ILPDVSR_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_IBRD register.
+//
+//*****************************************************************************
+#define UART_IBRD_DIVINT_M      0x0000FFFF  // Integer Baud-Rate Divisor
+#define UART_IBRD_DIVINT_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_FBRD register.
+//
+//*****************************************************************************
+#define UART_FBRD_DIVFRAC_M     0x0000003F  // Fractional Baud-Rate Divisor
+#define UART_FBRD_DIVFRAC_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_LCRH register.
+//
+//*****************************************************************************
+#define UART_LCRH_SPS           0x00000080  // UART Stick Parity Select
+#define UART_LCRH_WLEN_M        0x00000060  // UART Word Length
+#define UART_LCRH_WLEN_5        0x00000000  // 5 bits (default)
+#define UART_LCRH_WLEN_6        0x00000020  // 6 bits
+#define UART_LCRH_WLEN_7        0x00000040  // 7 bits
+#define UART_LCRH_WLEN_8        0x00000060  // 8 bits
+#define UART_LCRH_FEN           0x00000010  // UART Enable FIFOs
+#define UART_LCRH_STP2          0x00000008  // UART Two Stop Bits Select
+#define UART_LCRH_EPS           0x00000004  // UART Even Parity Select
+#define UART_LCRH_PEN           0x00000002  // UART Parity Enable
+#define UART_LCRH_BRK           0x00000001  // UART Send Break
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_CTL register.
+//
+//*****************************************************************************
+#define UART_CTL_CTSEN          0x00008000  // Enable Clear To Send
+#define UART_CTL_RTSEN          0x00004000  // Enable Request to Send
+#define UART_CTL_RTS            0x00000800  // Request to Send
+#define UART_CTL_DTR            0x00000400  // Data Terminal Ready
+#define UART_CTL_RXE            0x00000200  // UART Receive Enable
+#define UART_CTL_TXE            0x00000100  // UART Transmit Enable
+#define UART_CTL_LBE            0x00000080  // UART Loop Back Enable
+#define UART_CTL_LIN            0x00000040  // LIN Mode Enable
+#define UART_CTL_HSE            0x00000020  // High-Speed Enable
+#define UART_CTL_EOT            0x00000010  // End of Transmission
+#define UART_CTL_SMART          0x00000008  // ISO 7816 Smart Card Support
+#define UART_CTL_SIRLP          0x00000004  // UART SIR Low-Power Mode
+#define UART_CTL_SIREN          0x00000002  // UART SIR Enable
+#define UART_CTL_UARTEN         0x00000001  // UART Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_IFLS register.
+//
+//*****************************************************************************
+#define UART_IFLS_RX_M          0x00000038  // UART Receive Interrupt FIFO
+                                            // Level Select
+#define UART_IFLS_RX1_8         0x00000000  // RX FIFO >= 1/8 full
+#define UART_IFLS_RX2_8         0x00000008  // RX FIFO >= 1/4 full
+#define UART_IFLS_RX4_8         0x00000010  // RX FIFO >= 1/2 full (default)
+#define UART_IFLS_RX6_8         0x00000018  // RX FIFO >= 3/4 full
+#define UART_IFLS_RX7_8         0x00000020  // RX FIFO >= 7/8 full
+#define UART_IFLS_TX_M          0x00000007  // UART Transmit Interrupt FIFO
+                                            // Level Select
+#define UART_IFLS_TX1_8         0x00000000  // TX FIFO <= 1/8 full
+#define UART_IFLS_TX2_8         0x00000001  // TX FIFO <= 1/4 full
+#define UART_IFLS_TX4_8         0x00000002  // TX FIFO <= 1/2 full (default)
+#define UART_IFLS_TX6_8         0x00000003  // TX FIFO <= 3/4 full
+#define UART_IFLS_TX7_8         0x00000004  // TX FIFO <= 7/8 full
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_IM register.
+//
+//*****************************************************************************
+#define UART_IM_LME5IM          0x00008000  // LIN Mode Edge 5 Interrupt Mask
+#define UART_IM_LME1IM          0x00004000  // LIN Mode Edge 1 Interrupt Mask
+#define UART_IM_LMSBIM          0x00002000  // LIN Mode Sync Break Interrupt
+                                            // Mask
+#define UART_IM_OEIM            0x00000400  // UART Overrun Error Interrupt
+                                            // Mask
+#define UART_IM_BEIM            0x00000200  // UART Break Error Interrupt Mask
+#define UART_IM_PEIM            0x00000100  // UART Parity Error Interrupt Mask
+#define UART_IM_FEIM            0x00000080  // UART Framing Error Interrupt
+                                            // Mask
+#define UART_IM_RTIM            0x00000040  // UART Receive Time-Out Interrupt
+                                            // Mask
+#define UART_IM_TXIM            0x00000020  // UART Transmit Interrupt Mask
+#define UART_IM_RXIM            0x00000010  // UART Receive Interrupt Mask
+#define UART_IM_DSRMIM          0x00000008  // UART Data Set Ready Modem
+                                            // Interrupt Mask
+#define UART_IM_DCDMIM          0x00000004  // UART Data Carrier Detect Modem
+                                            // Interrupt Mask
+#define UART_IM_CTSMIM          0x00000002  // UART Clear to Send Modem
+                                            // Interrupt Mask
+#define UART_IM_RIMIM           0x00000001  // UART Ring Indicator Modem
+                                            // Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_RIS register.
+//
+//*****************************************************************************
+#define UART_RIS_LME5RIS        0x00008000  // LIN Mode Edge 5 Raw Interrupt
+                                            // Status
+#define UART_RIS_LME1RIS        0x00004000  // LIN Mode Edge 1 Raw Interrupt
+                                            // Status
+#define UART_RIS_LMSBRIS        0x00002000  // LIN Mode Sync Break Raw
+                                            // Interrupt Status
+#define UART_RIS_OERIS          0x00000400  // UART Overrun Error Raw Interrupt
+                                            // Status
+#define UART_RIS_BERIS          0x00000200  // UART Break Error Raw Interrupt
+                                            // Status
+#define UART_RIS_PERIS          0x00000100  // UART Parity Error Raw Interrupt
+                                            // Status
+#define UART_RIS_FERIS          0x00000080  // UART Framing Error Raw Interrupt
+                                            // Status
+#define UART_RIS_RTRIS          0x00000040  // UART Receive Time-Out Raw
+                                            // Interrupt Status
+#define UART_RIS_TXRIS          0x00000020  // UART Transmit Raw Interrupt
+                                            // Status
+#define UART_RIS_RXRIS          0x00000010  // UART Receive Raw Interrupt
+                                            // Status
+#define UART_RIS_DSRRIS         0x00000008  // UART Data Set Ready Modem Raw
+                                            // Interrupt Status
+#define UART_RIS_DCDRIS         0x00000004  // UART Data Carrier Detect Modem
+                                            // Raw Interrupt Status
+#define UART_RIS_CTSRIS         0x00000002  // UART Clear to Send Modem Raw
+                                            // Interrupt Status
+#define UART_RIS_RIRIS          0x00000001  // UART Ring Indicator Modem Raw
+                                            // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_MIS register.
+//
+//*****************************************************************************
+#define UART_MIS_LME5MIS        0x00008000  // LIN Mode Edge 5 Masked Interrupt
+                                            // Status
+#define UART_MIS_LME1MIS        0x00004000  // LIN Mode Edge 1 Masked Interrupt
+                                            // Status
+#define UART_MIS_LMSBMIS        0x00002000  // LIN Mode Sync Break Masked
+                                            // Interrupt Status
+#define UART_MIS_OEMIS          0x00000400  // UART Overrun Error Masked
+                                            // Interrupt Status
+#define UART_MIS_BEMIS          0x00000200  // UART Break Error Masked
+                                            // Interrupt Status
+#define UART_MIS_PEMIS          0x00000100  // UART Parity Error Masked
+                                            // Interrupt Status
+#define UART_MIS_FEMIS          0x00000080  // UART Framing Error Masked
+                                            // Interrupt Status
+#define UART_MIS_RTMIS          0x00000040  // UART Receive Time-Out Masked
+                                            // Interrupt Status
+#define UART_MIS_TXMIS          0x00000020  // UART Transmit Masked Interrupt
+                                            // Status
+#define UART_MIS_RXMIS          0x00000010  // UART Receive Masked Interrupt
+                                            // Status
+#define UART_MIS_DSRMIS         0x00000008  // UART Data Set Ready Modem Masked
+                                            // Interrupt Status
+#define UART_MIS_DCDMIS         0x00000004  // UART Data Carrier Detect Modem
+                                            // Masked Interrupt Status
+#define UART_MIS_CTSMIS         0x00000002  // UART Clear to Send Modem Masked
+                                            // Interrupt Status
+#define UART_MIS_RIMIS          0x00000001  // UART Ring Indicator Modem Masked
+                                            // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_ICR register.
+//
+//*****************************************************************************
+#define UART_ICR_LME5IC         0x00008000  // LIN Mode Edge 5 Interrupt Clear
+#define UART_ICR_LME5MIC        0x00008000  // LIN Mode Edge 5 Interrupt Clear
+#define UART_ICR_LME1MIC        0x00004000  // LIN Mode Edge 1 Interrupt Clear
+#define UART_ICR_LME1IC         0x00004000  // LIN Mode Edge 1 Interrupt Clear
+#define UART_ICR_LMSBMIC        0x00002000  // LIN Mode Sync Break Interrupt
+                                            // Clear
+#define UART_ICR_LMSBIC         0x00002000  // LIN Mode Sync Break Interrupt
+                                            // Clear
+#define UART_ICR_OEIC           0x00000400  // Overrun Error Interrupt Clear
+#define UART_ICR_BEIC           0x00000200  // Break Error Interrupt Clear
+#define UART_ICR_PEIC           0x00000100  // Parity Error Interrupt Clear
+#define UART_ICR_FEIC           0x00000080  // Framing Error Interrupt Clear
+#define UART_ICR_RTIC           0x00000040  // Receive Time-Out Interrupt Clear
+#define UART_ICR_TXIC           0x00000020  // Transmit Interrupt Clear
+#define UART_ICR_RXIC           0x00000010  // Receive Interrupt Clear
+#define UART_ICR_DSRMIC         0x00000008  // UART Data Set Ready Modem
+                                            // Interrupt Clear
+#define UART_ICR_DCDMIC         0x00000004  // UART Data Carrier Detect Modem
+                                            // Interrupt Clear
+#define UART_ICR_CTSMIC         0x00000002  // UART Clear to Send Modem
+                                            // Interrupt Clear
+#define UART_ICR_RIMIC          0x00000001  // UART Ring Indicator Modem
+                                            // Interrupt Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_DMACTL register.
+//
+//*****************************************************************************
+#define UART_DMACTL_DMAERR      0x00000004  // DMA on Error
+#define UART_DMACTL_TXDMAE      0x00000002  // Transmit DMA Enable
+#define UART_DMACTL_RXDMAE      0x00000001  // Receive DMA Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_LCTL register.
+//
+//*****************************************************************************
+#define UART_LCTL_BLEN_M        0x00000030  // Sync Break Length
+#define UART_LCTL_BLEN_13T      0x00000000  // Sync break length is 13T bits
+                                            // (default)
+#define UART_LCTL_BLEN_14T      0x00000010  // Sync break length is 14T bits
+#define UART_LCTL_BLEN_15T      0x00000020  // Sync break length is 15T bits
+#define UART_LCTL_BLEN_16T      0x00000030  // Sync break length is 16T bits
+#define UART_LCTL_MASTER        0x00000001  // LIN Master Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_LSS register.
+//
+//*****************************************************************************
+#define UART_LSS_TSS_M          0x0000FFFF  // Timer Snap Shot
+#define UART_LSS_TSS_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_LTIM register.
+//
+//*****************************************************************************
+#define UART_LTIM_TIMER_M       0x0000FFFF  // Timer Value
+#define UART_LTIM_TIMER_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MSA register.
+//
+//*****************************************************************************
+#define I2C_MSA_SA_M            0x000000FE  // I2C Slave Address
+#define I2C_MSA_RS              0x00000001  // Receive not send
+#define I2C_MSA_SA_S            1
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SOAR register.
+//
+//*****************************************************************************
+#define I2C_SOAR_OAR_M          0x0000007F  // I2C Slave Own Address
+#define I2C_SOAR_OAR_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SCSR register.
+//
+//*****************************************************************************
+#define I2C_SCSR_FBR            0x00000004  // First Byte Received
+#define I2C_SCSR_TREQ           0x00000002  // Transmit Request
+#define I2C_SCSR_DA             0x00000001  // Device Active
+#define I2C_SCSR_RREQ           0x00000001  // Receive Request
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MCS register.
+//
+//*****************************************************************************
+#define I2C_MCS_BUSBSY          0x00000040  // Bus Busy
+#define I2C_MCS_IDLE            0x00000020  // I2C Idle
+#define I2C_MCS_ARBLST          0x00000010  // Arbitration Lost
+#define I2C_MCS_ACK             0x00000008  // Data Acknowledge Enable
+#define I2C_MCS_DATACK          0x00000008  // Acknowledge Data
+#define I2C_MCS_ADRACK          0x00000004  // Acknowledge Address
+#define I2C_MCS_STOP            0x00000004  // Generate STOP
+#define I2C_MCS_START           0x00000002  // Generate START
+#define I2C_MCS_ERROR           0x00000002  // Error
+#define I2C_MCS_RUN             0x00000001  // I2C Master Enable
+#define I2C_MCS_BUSY            0x00000001  // I2C Busy
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SDR register.
+//
+//*****************************************************************************
+#define I2C_SDR_DATA_M          0x000000FF  // Data for Transfer
+#define I2C_SDR_DATA_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MDR register.
+//
+//*****************************************************************************
+#define I2C_MDR_DATA_M          0x000000FF  // Data Transferred
+#define I2C_MDR_DATA_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MTPR register.
+//
+//*****************************************************************************
+#define I2C_MTPR_TPR_M          0x0000007F  // SCL Clock Period
+#define I2C_MTPR_TPR_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SIMR register.
+//
+//*****************************************************************************
+#define I2C_SIMR_STOPIM         0x00000004  // Stop Condition Interrupt Mask
+#define I2C_SIMR_STARTIM        0x00000002  // Start Condition Interrupt Mask
+#define I2C_SIMR_DATAIM         0x00000001  // Data Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SRIS register.
+//
+//*****************************************************************************
+#define I2C_SRIS_STOPRIS        0x00000004  // Stop Condition Raw Interrupt
+                                            // Status
+#define I2C_SRIS_STARTRIS       0x00000002  // Start Condition Raw Interrupt
+                                            // Status
+#define I2C_SRIS_DATARIS        0x00000001  // Data Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MIMR register.
+//
+//*****************************************************************************
+#define I2C_MIMR_IM             0x00000001  // Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MRIS register.
+//
+//*****************************************************************************
+#define I2C_MRIS_RIS            0x00000001  // Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SMIS register.
+//
+//*****************************************************************************
+#define I2C_SMIS_STOPMIS        0x00000004  // Stop Condition Masked Interrupt
+                                            // Status
+#define I2C_SMIS_STARTMIS       0x00000002  // Start Condition Masked Interrupt
+                                            // Status
+#define I2C_SMIS_DATAMIS        0x00000001  // Data Masked Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SICR register.
+//
+//*****************************************************************************
+#define I2C_SICR_STOPIC         0x00000004  // Stop Condition Interrupt Clear
+#define I2C_SICR_STARTIC        0x00000002  // Start Condition Interrupt Clear
+#define I2C_SICR_DATAIC         0x00000001  // Data Interrupt Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MMIS register.
+//
+//*****************************************************************************
+#define I2C_MMIS_MIS            0x00000001  // Masked Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MICR register.
+//
+//*****************************************************************************
+#define I2C_MICR_IC             0x00000001  // Interrupt Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MCR register.
+//
+//*****************************************************************************
+#define I2C_MCR_SFE             0x00000020  // I2C Slave Function Enable
+#define I2C_MCR_MFE             0x00000010  // I2C Master Function Enable
+#define I2C_MCR_LPBK            0x00000001  // I2C Loopback
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_CTL register.
+//
+//*****************************************************************************
+#define PWM_CTL_GLOBALSYNC3     0x00000008  // Update PWM Generator 3
+#define PWM_CTL_GLOBALSYNC2     0x00000004  // Update PWM Generator 2
+#define PWM_CTL_GLOBALSYNC1     0x00000002  // Update PWM Generator 1
+#define PWM_CTL_GLOBALSYNC0     0x00000001  // Update PWM Generator 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_SYNC register.
+//
+//*****************************************************************************
+#define PWM_SYNC_SYNC3          0x00000008  // Reset Generator 3 Counter
+#define PWM_SYNC_SYNC2          0x00000004  // Reset Generator 2 Counter
+#define PWM_SYNC_SYNC1          0x00000002  // Reset Generator 1 Counter
+#define PWM_SYNC_SYNC0          0x00000001  // Reset Generator 0 Counter
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_ENABLE register.
+//
+//*****************************************************************************
+#define PWM_ENABLE_PWM7EN       0x00000080  // PWM7 Output Enable
+#define PWM_ENABLE_PWM6EN       0x00000040  // PWM6 Output Enable
+#define PWM_ENABLE_PWM5EN       0x00000020  // PWM5 Output Enable
+#define PWM_ENABLE_PWM4EN       0x00000010  // PWM4 Output Enable
+#define PWM_ENABLE_PWM3EN       0x00000008  // PWM3 Output Enable
+#define PWM_ENABLE_PWM2EN       0x00000004  // PWM2 Output Enable
+#define PWM_ENABLE_PWM1EN       0x00000002  // PWM1 Output Enable
+#define PWM_ENABLE_PWM0EN       0x00000001  // PWM0 Output Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_INVERT register.
+//
+//*****************************************************************************
+#define PWM_INVERT_PWM7INV      0x00000080  // Invert PWM7 Signal
+#define PWM_INVERT_PWM6INV      0x00000040  // Invert PWM6 Signal
+#define PWM_INVERT_PWM5INV      0x00000020  // Invert PWM5 Signal
+#define PWM_INVERT_PWM4INV      0x00000010  // Invert PWM4 Signal
+#define PWM_INVERT_PWM3INV      0x00000008  // Invert PWM3 Signal
+#define PWM_INVERT_PWM2INV      0x00000004  // Invert PWM2 Signal
+#define PWM_INVERT_PWM1INV      0x00000002  // Invert PWM1 Signal
+#define PWM_INVERT_PWM0INV      0x00000001  // Invert PWM0 Signal
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_FAULT register.
+//
+//*****************************************************************************
+#define PWM_FAULT_FAULT7        0x00000080  // PWM7 Fault
+#define PWM_FAULT_FAULT6        0x00000040  // PWM6 Fault
+#define PWM_FAULT_FAULT5        0x00000020  // PWM5 Fault
+#define PWM_FAULT_FAULT4        0x00000010  // PWM4 Fault
+#define PWM_FAULT_FAULT3        0x00000008  // PWM3 Fault
+#define PWM_FAULT_FAULT2        0x00000004  // PWM2 Fault
+#define PWM_FAULT_FAULT1        0x00000002  // PWM1 Fault
+#define PWM_FAULT_FAULT0        0x00000001  // PWM0 Fault
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_INTEN register.
+//
+//*****************************************************************************
+#define PWM_INTEN_INTFAULT3     0x00080000  // Interrupt Fault 3
+#define PWM_INTEN_INTFAULT2     0x00040000  // Interrupt Fault 2
+#define PWM_INTEN_INTFAULT1     0x00020000  // Interrupt Fault 1
+#define PWM_INTEN_INTFAULT0     0x00010000  // Interrupt Fault 0
+#define PWM_INTEN_INTPWM3       0x00000008  // PWM3 Interrupt Enable
+#define PWM_INTEN_INTPWM2       0x00000004  // PWM2 Interrupt Enable
+#define PWM_INTEN_INTPWM1       0x00000002  // PWM1 Interrupt Enable
+#define PWM_INTEN_INTPWM0       0x00000001  // PWM0 Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_RIS register.
+//
+//*****************************************************************************
+#define PWM_RIS_INTFAULT3       0x00080000  // Interrupt Fault PWM 3
+#define PWM_RIS_INTFAULT2       0x00040000  // Interrupt Fault PWM 2
+#define PWM_RIS_INTFAULT1       0x00020000  // Interrupt Fault PWM 1
+#define PWM_RIS_INTFAULT0       0x00010000  // Interrupt Fault PWM 0
+#define PWM_RIS_INTPWM3         0x00000008  // PWM3 Interrupt Asserted
+#define PWM_RIS_INTPWM2         0x00000004  // PWM2 Interrupt Asserted
+#define PWM_RIS_INTPWM1         0x00000002  // PWM1 Interrupt Asserted
+#define PWM_RIS_INTPWM0         0x00000001  // PWM0 Interrupt Asserted
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_ISC register.
+//
+//*****************************************************************************
+#define PWM_ISC_INTFAULT3       0x00080000  // FAULT3 Interrupt Asserted
+#define PWM_ISC_INTFAULT2       0x00040000  // FAULT2 Interrupt Asserted
+#define PWM_ISC_INTFAULT1       0x00020000  // FAULT1 Interrupt Asserted
+#define PWM_ISC_INTFAULT0       0x00010000  // FAULT0 Interrupt Asserted
+#define PWM_ISC_INTPWM3         0x00000008  // PWM3 Interrupt Status
+#define PWM_ISC_INTPWM2         0x00000004  // PWM2 Interrupt Status
+#define PWM_ISC_INTPWM1         0x00000002  // PWM1 Interrupt Status
+#define PWM_ISC_INTPWM0         0x00000001  // PWM0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_STATUS register.
+//
+//*****************************************************************************
+#define PWM_STATUS_FAULT3       0x00000008  // Generator 3 Fault Status
+#define PWM_STATUS_FAULT2       0x00000004  // Generator 2 Fault Status
+#define PWM_STATUS_FAULT1       0x00000002  // Generator 1 Fault Status
+#define PWM_STATUS_FAULT0       0x00000001  // Generator 0 Fault Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_FAULTVAL register.
+//
+//*****************************************************************************
+#define PWM_FAULTVAL_PWM7       0x00000080  // PWM7 Fault Value
+#define PWM_FAULTVAL_PWM6       0x00000040  // PWM6 Fault Value
+#define PWM_FAULTVAL_PWM5       0x00000020  // PWM5 Fault Value
+#define PWM_FAULTVAL_PWM4       0x00000010  // PWM4 Fault Value
+#define PWM_FAULTVAL_PWM3       0x00000008  // PWM3 Fault Value
+#define PWM_FAULTVAL_PWM2       0x00000004  // PWM2 Fault Value
+#define PWM_FAULTVAL_PWM1       0x00000002  // PWM1 Fault Value
+#define PWM_FAULTVAL_PWM0       0x00000001  // PWM0 Fault Value
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_ENUPD register.
+//
+//*****************************************************************************
+#define PWM_ENUPD_ENUPD7_M      0x0000C000  // PWM7 Enable Update Mode
+#define PWM_ENUPD_ENUPD7_IMM    0x00000000  // Immediate
+#define PWM_ENUPD_ENUPD7_LSYNC  0x00008000  // Locally Synchronized
+#define PWM_ENUPD_ENUPD7_GSYNC  0x0000C000  // Globally Synchronized
+#define PWM_ENUPD_ENUPD6_M      0x00003000  // PWM6 Enable Update Mode
+#define PWM_ENUPD_ENUPD6_IMM    0x00000000  // Immediate
+#define PWM_ENUPD_ENUPD6_LSYNC  0x00002000  // Locally Synchronized
+#define PWM_ENUPD_ENUPD6_GSYNC  0x00003000  // Globally Synchronized
+#define PWM_ENUPD_ENUPD5_M      0x00000C00  // PWM5 Enable Update Mode
+#define PWM_ENUPD_ENUPD5_IMM    0x00000000  // Immediate
+#define PWM_ENUPD_ENUPD5_LSYNC  0x00000800  // Locally Synchronized
+#define PWM_ENUPD_ENUPD5_GSYNC  0x00000C00  // Globally Synchronized
+#define PWM_ENUPD_ENUPD4_M      0x00000300  // PWM4 Enable Update Mode
+#define PWM_ENUPD_ENUPD4_IMM    0x00000000  // Immediate
+#define PWM_ENUPD_ENUPD4_LSYNC  0x00000200  // Locally Synchronized
+#define PWM_ENUPD_ENUPD4_GSYNC  0x00000300  // Globally Synchronized
+#define PWM_ENUPD_ENUPD3_M      0x000000C0  // PWM3 Enable Update Mode
+#define PWM_ENUPD_ENUPD3_IMM    0x00000000  // Immediate
+#define PWM_ENUPD_ENUPD3_LSYNC  0x00000080  // Locally Synchronized
+#define PWM_ENUPD_ENUPD3_GSYNC  0x000000C0  // Globally Synchronized
+#define PWM_ENUPD_ENUPD2_M      0x00000030  // PWM2 Enable Update Mode
+#define PWM_ENUPD_ENUPD2_IMM    0x00000000  // Immediate
+#define PWM_ENUPD_ENUPD2_LSYNC  0x00000020  // Locally Synchronized
+#define PWM_ENUPD_ENUPD2_GSYNC  0x00000030  // Globally Synchronized
+#define PWM_ENUPD_ENUPD1_M      0x0000000C  // PWM1 Enable Update Mode
+#define PWM_ENUPD_ENUPD1_IMM    0x00000000  // Immediate
+#define PWM_ENUPD_ENUPD1_LSYNC  0x00000008  // Locally Synchronized
+#define PWM_ENUPD_ENUPD1_GSYNC  0x0000000C  // Globally Synchronized
+#define PWM_ENUPD_ENUPD0_M      0x00000003  // PWM0 Enable Update Mode
+#define PWM_ENUPD_ENUPD0_IMM    0x00000000  // Immediate
+#define PWM_ENUPD_ENUPD0_LSYNC  0x00000002  // Locally Synchronized
+#define PWM_ENUPD_ENUPD0_GSYNC  0x00000003  // Globally Synchronized
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_CTL register.
+//
+//*****************************************************************************
+#define PWM_X_CTL_LATCH         0x00040000  // Latch Fault Input
+#define PWM_X_CTL_MINFLTPER     0x00020000  // Minimum Fault Period
+#define PWM_X_CTL_FLTSRC        0x00010000  // Fault Condition Source
+#define PWM_X_CTL_DBFALLUPD_M   0x0000C000  // PWMnDBFALL Update Mode
+#define PWM_X_CTL_DBFALLUPD_I   0x00000000  // Immediate
+#define PWM_X_CTL_DBFALLUPD_LS  0x00008000  // Locally Synchronized
+#define PWM_X_CTL_DBFALLUPD_GS  0x0000C000  // Globally Synchronized
+#define PWM_X_CTL_DBRISEUPD_M   0x00003000  // PWMnDBRISE Update Mode
+#define PWM_X_CTL_DBRISEUPD_I   0x00000000  // Immediate
+#define PWM_X_CTL_DBRISEUPD_LS  0x00002000  // Locally Synchronized
+#define PWM_X_CTL_DBRISEUPD_GS  0x00003000  // Globally Synchronized
+#define PWM_X_CTL_DBCTLUPD_M    0x00000C00  // PWMnDBCTL Update Mode
+#define PWM_X_CTL_DBCTLUPD_I    0x00000000  // Immediate
+#define PWM_X_CTL_DBCTLUPD_LS   0x00000800  // Locally Synchronized
+#define PWM_X_CTL_DBCTLUPD_GS   0x00000C00  // Globally Synchronized
+#define PWM_X_CTL_GENBUPD_M     0x00000300  // PWMnGENB Update Mode
+#define PWM_X_CTL_GENBUPD_I     0x00000000  // Immediate
+#define PWM_X_CTL_GENBUPD_LS    0x00000200  // Locally Synchronized
+#define PWM_X_CTL_GENBUPD_GS    0x00000300  // Globally Synchronized
+#define PWM_X_CTL_GENAUPD_M     0x000000C0  // PWMnGENA Update Mode
+#define PWM_X_CTL_GENAUPD_I     0x00000000  // Immediate
+#define PWM_X_CTL_GENAUPD_LS    0x00000080  // Locally Synchronized
+#define PWM_X_CTL_GENAUPD_GS    0x000000C0  // Globally Synchronized
+#define PWM_X_CTL_CMPBUPD       0x00000020  // Comparator B Update Mode
+#define PWM_X_CTL_CMPAUPD       0x00000010  // Comparator A Update Mode
+#define PWM_X_CTL_LOADUPD       0x00000008  // Load Register Update Mode
+#define PWM_X_CTL_DEBUG         0x00000004  // Debug Mode
+#define PWM_X_CTL_MODE          0x00000002  // Counter Mode
+#define PWM_X_CTL_ENABLE        0x00000001  // PWM Block Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_INTEN register.
+//
+//*****************************************************************************
+#define PWM_X_INTEN_TRCMPBD     0x00002000  // Trigger for Counter=PWMnCMPB
+                                            // Down
+#define PWM_X_INTEN_TRCMPBU     0x00001000  // Trigger for Counter=PWMnCMPB Up
+#define PWM_X_INTEN_TRCMPAD     0x00000800  // Trigger for Counter=PWMnCMPA
+                                            // Down
+#define PWM_X_INTEN_TRCMPAU     0x00000400  // Trigger for Counter=PWMnCMPA Up
+#define PWM_X_INTEN_TRCNTLOAD   0x00000200  // Trigger for Counter=PWMnLOAD
+#define PWM_X_INTEN_TRCNTZERO   0x00000100  // Trigger for Counter=0
+#define PWM_X_INTEN_INTCMPBD    0x00000020  // Interrupt for Counter=PWMnCMPB
+                                            // Down
+#define PWM_X_INTEN_INTCMPBU    0x00000010  // Interrupt for Counter=PWMnCMPB
+                                            // Up
+#define PWM_X_INTEN_INTCMPAD    0x00000008  // Interrupt for Counter=PWMnCMPA
+                                            // Down
+#define PWM_X_INTEN_INTCMPAU    0x00000004  // Interrupt for Counter=PWMnCMPA
+                                            // Up
+#define PWM_X_INTEN_INTCNTLOAD  0x00000002  // Interrupt for Counter=PWMnLOAD
+#define PWM_X_INTEN_INTCNTZERO  0x00000001  // Interrupt for Counter=0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_RIS register.
+//
+//*****************************************************************************
+#define PWM_X_RIS_INTCMPBD      0x00000020  // Comparator B Down Interrupt
+                                            // Status
+#define PWM_X_RIS_INTCMPBU      0x00000010  // Comparator B Up Interrupt Status
+#define PWM_X_RIS_INTCMPAD      0x00000008  // Comparator A Down Interrupt
+                                            // Status
+#define PWM_X_RIS_INTCMPAU      0x00000004  // Comparator A Up Interrupt Status
+#define PWM_X_RIS_INTCNTLOAD    0x00000002  // Counter=Load Interrupt Status
+#define PWM_X_RIS_INTCNTZERO    0x00000001  // Counter=0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_ISC register.
+//
+//*****************************************************************************
+#define PWM_X_ISC_INTCMPBD      0x00000020  // Comparator B Down Interrupt
+#define PWM_X_ISC_INTCMPBU      0x00000010  // Comparator B Up Interrupt
+#define PWM_X_ISC_INTCMPAD      0x00000008  // Comparator A Down Interrupt
+#define PWM_X_ISC_INTCMPAU      0x00000004  // Comparator A Up Interrupt
+#define PWM_X_ISC_INTCNTLOAD    0x00000002  // Counter=Load Interrupt
+#define PWM_X_ISC_INTCNTZERO    0x00000001  // Counter=0 Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_LOAD register.
+//
+//*****************************************************************************
+#define PWM_X_LOAD_M            0x0000FFFF  // Counter Load Value
+#define PWM_X_LOAD_S            0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_COUNT register.
+//
+//*****************************************************************************
+#define PWM_X_COUNT_M           0x0000FFFF  // Counter Value
+#define PWM_X_COUNT_S           0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_CMPA register.
+//
+//*****************************************************************************
+#define PWM_X_CMPA_M            0x0000FFFF  // Comparator A Value
+#define PWM_X_CMPA_S            0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_CMPB register.
+//
+//*****************************************************************************
+#define PWM_X_CMPB_M            0x0000FFFF  // Comparator B Value
+#define PWM_X_CMPB_S            0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_GENA register.
+//
+//*****************************************************************************
+#define PWM_X_GENA_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down
+#define PWM_X_GENA_ACTCMPBD_NONE \
+                                0x00000000  // Do nothing
+#define PWM_X_GENA_ACTCMPBD_INV 0x00000400  // Invert pwmA
+#define PWM_X_GENA_ACTCMPBD_ZERO \
+                                0x00000800  // Drive pwmA Low
+#define PWM_X_GENA_ACTCMPBD_ONE 0x00000C00  // Drive pwmA High
+#define PWM_X_GENA_ACTCMPBU_M   0x00000300  // Action for Comparator B Up
+#define PWM_X_GENA_ACTCMPBU_NONE \
+                                0x00000000  // Do nothing
+#define PWM_X_GENA_ACTCMPBU_INV 0x00000100  // Invert pwmA
+#define PWM_X_GENA_ACTCMPBU_ZERO \
+                                0x00000200  // Drive pwmA Low
+#define PWM_X_GENA_ACTCMPBU_ONE 0x00000300  // Drive pwmA High
+#define PWM_X_GENA_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down
+#define PWM_X_GENA_ACTCMPAD_NONE \
+                                0x00000000  // Do nothing
+#define PWM_X_GENA_ACTCMPAD_INV 0x00000040  // Invert pwmA
+#define PWM_X_GENA_ACTCMPAD_ZERO \
+                                0x00000080  // Drive pwmA Low
+#define PWM_X_GENA_ACTCMPAD_ONE 0x000000C0  // Drive pwmA High
+#define PWM_X_GENA_ACTCMPAU_M   0x00000030  // Action for Comparator A Up
+#define PWM_X_GENA_ACTCMPAU_NONE \
+                                0x00000000  // Do nothing
+#define PWM_X_GENA_ACTCMPAU_INV 0x00000010  // Invert pwmA
+#define PWM_X_GENA_ACTCMPAU_ZERO \
+                                0x00000020  // Drive pwmA Low
+#define PWM_X_GENA_ACTCMPAU_ONE 0x00000030  // Drive pwmA High
+#define PWM_X_GENA_ACTLOAD_M    0x0000000C  // Action for Counter=LOAD
+#define PWM_X_GENA_ACTLOAD_NONE 0x00000000  // Do nothing
+#define PWM_X_GENA_ACTLOAD_INV  0x00000004  // Invert pwmA
+#define PWM_X_GENA_ACTLOAD_ZERO 0x00000008  // Drive pwmA Low
+#define PWM_X_GENA_ACTLOAD_ONE  0x0000000C  // Drive pwmA High
+#define PWM_X_GENA_ACTZERO_M    0x00000003  // Action for Counter=0
+#define PWM_X_GENA_ACTZERO_NONE 0x00000000  // Do nothing
+#define PWM_X_GENA_ACTZERO_INV  0x00000001  // Invert pwmA
+#define PWM_X_GENA_ACTZERO_ZERO 0x00000002  // Drive pwmA Low
+#define PWM_X_GENA_ACTZERO_ONE  0x00000003  // Drive pwmA High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_GENB register.
+//
+//*****************************************************************************
+#define PWM_X_GENB_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down
+#define PWM_X_GENB_ACTCMPBD_NONE \
+                                0x00000000  // Do nothing
+#define PWM_X_GENB_ACTCMPBD_INV 0x00000400  // Invert pwmB
+#define PWM_X_GENB_ACTCMPBD_ZERO \
+                                0x00000800  // Drive pwmB Low
+#define PWM_X_GENB_ACTCMPBD_ONE 0x00000C00  // Drive pwmB High
+#define PWM_X_GENB_ACTCMPBU_M   0x00000300  // Action for Comparator B Up
+#define PWM_X_GENB_ACTCMPBU_NONE \
+                                0x00000000  // Do nothing
+#define PWM_X_GENB_ACTCMPBU_INV 0x00000100  // Invert pwmB
+#define PWM_X_GENB_ACTCMPBU_ZERO \
+                                0x00000200  // Drive pwmB Low
+#define PWM_X_GENB_ACTCMPBU_ONE 0x00000300  // Drive pwmB High
+#define PWM_X_GENB_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down
+#define PWM_X_GENB_ACTCMPAD_NONE \
+                                0x00000000  // Do nothing
+#define PWM_X_GENB_ACTCMPAD_INV 0x00000040  // Invert pwmB
+#define PWM_X_GENB_ACTCMPAD_ZERO \
+                                0x00000080  // Drive pwmB Low
+#define PWM_X_GENB_ACTCMPAD_ONE 0x000000C0  // Drive pwmB High
+#define PWM_X_GENB_ACTCMPAU_M   0x00000030  // Action for Comparator A Up
+#define PWM_X_GENB_ACTCMPAU_NONE \
+                                0x00000000  // Do nothing
+#define PWM_X_GENB_ACTCMPAU_INV 0x00000010  // Invert pwmB
+#define PWM_X_GENB_ACTCMPAU_ZERO \
+                                0x00000020  // Drive pwmB Low
+#define PWM_X_GENB_ACTCMPAU_ONE 0x00000030  // Drive pwmB High
+#define PWM_X_GENB_ACTLOAD_M    0x0000000C  // Action for Counter=LOAD
+#define PWM_X_GENB_ACTLOAD_NONE 0x00000000  // Do nothing
+#define PWM_X_GENB_ACTLOAD_INV  0x00000004  // Invert pwmB
+#define PWM_X_GENB_ACTLOAD_ZERO 0x00000008  // Drive pwmB Low
+#define PWM_X_GENB_ACTLOAD_ONE  0x0000000C  // Drive pwmB High
+#define PWM_X_GENB_ACTZERO_M    0x00000003  // Action for Counter=0
+#define PWM_X_GENB_ACTZERO_NONE 0x00000000  // Do nothing
+#define PWM_X_GENB_ACTZERO_INV  0x00000001  // Invert pwmB
+#define PWM_X_GENB_ACTZERO_ZERO 0x00000002  // Drive pwmB Low
+#define PWM_X_GENB_ACTZERO_ONE  0x00000003  // Drive pwmB High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_DBCTL register.
+//
+//*****************************************************************************
+#define PWM_X_DBCTL_ENABLE      0x00000001  // Dead-Band Generator Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_DBRISE register.
+//
+//*****************************************************************************
+#define PWM_X_DBRISE_DELAY_M    0x00000FFF  // Dead-Band Rise Delay
+#define PWM_X_DBRISE_DELAY_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_DBFALL register.
+//
+//*****************************************************************************
+#define PWM_X_DBFALL_DELAY_M    0x00000FFF  // Dead-Band Fall Delay
+#define PWM_X_DBFALL_DELAY_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_FLTSRC0
+// register.
+//
+//*****************************************************************************
+#define PWM_X_FLTSRC0_FAULT3    0x00000008  // Fault3 Input
+#define PWM_X_FLTSRC0_FAULT2    0x00000004  // Fault2 Input
+#define PWM_X_FLTSRC0_FAULT1    0x00000002  // Fault1 Input
+#define PWM_X_FLTSRC0_FAULT0    0x00000001  // Fault0 Input
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_FLTSRC1
+// register.
+//
+//*****************************************************************************
+#define PWM_X_FLTSRC1_DCMP7     0x00000080  // Digital Comparator 7
+#define PWM_X_FLTSRC1_DCMP6     0x00000040  // Digital Comparator 6
+#define PWM_X_FLTSRC1_DCMP5     0x00000020  // Digital Comparator 5
+#define PWM_X_FLTSRC1_DCMP4     0x00000010  // Digital Comparator 4
+#define PWM_X_FLTSRC1_DCMP3     0x00000008  // Digital Comparator 3
+#define PWM_X_FLTSRC1_DCMP2     0x00000004  // Digital Comparator 2
+#define PWM_X_FLTSRC1_DCMP1     0x00000002  // Digital Comparator 1
+#define PWM_X_FLTSRC1_DCMP0     0x00000001  // Digital Comparator 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_MINFLTPER
+// register.
+//
+//*****************************************************************************
+#define PWM_X_MINFLTPER_M       0x0000FFFF  // Minimum Fault Period
+#define PWM_X_MINFLTPER_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_FLTSEN register.
+//
+//*****************************************************************************
+#define PWM_X_FLTSEN_FAULT3     0x00000008  // Fault3 Sense
+#define PWM_X_FLTSEN_FAULT2     0x00000004  // Fault2 Sense
+#define PWM_X_FLTSEN_FAULT1     0x00000002  // Fault1 Sense
+#define PWM_X_FLTSEN_FAULT0     0x00000001  // Fault0 Sense
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_FLTSTAT0
+// register.
+//
+//*****************************************************************************
+#define PWM_X_FLTSTAT0_FAULT3   0x00000008  // Fault Input 3
+#define PWM_X_FLTSTAT0_FAULT2   0x00000004  // Fault Input 2
+#define PWM_X_FLTSTAT0_FAULT1   0x00000002  // Fault Input 1
+#define PWM_X_FLTSTAT0_FAULT0   0x00000001  // Fault Input 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_FLTSTAT1
+// register.
+//
+//*****************************************************************************
+#define PWM_X_FLTSTAT1_DCMP7    0x00000080  // Digital Comparator 7 Trigger
+#define PWM_X_FLTSTAT1_DCMP6    0x00000040  // Digital Comparator 6 Trigger
+#define PWM_X_FLTSTAT1_DCMP5    0x00000020  // Digital Comparator 5 Trigger
+#define PWM_X_FLTSTAT1_DCMP4    0x00000010  // Digital Comparator 4 Trigger
+#define PWM_X_FLTSTAT1_DCMP3    0x00000008  // Digital Comparator 3 Trigger
+#define PWM_X_FLTSTAT1_DCMP2    0x00000004  // Digital Comparator 2 Trigger
+#define PWM_X_FLTSTAT1_DCMP1    0x00000002  // Digital Comparator 1 Trigger
+#define PWM_X_FLTSTAT1_DCMP0    0x00000001  // Digital Comparator 0 Trigger
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_CTL register.
+//
+//*****************************************************************************
+#define QEI_CTL_FILTCNT_M       0x000F0000  // Input Filter Prescale Count
+#define QEI_CTL_FILTEN          0x00002000  // Enable Input Filter
+#define QEI_CTL_STALLEN         0x00001000  // Stall QEI
+#define QEI_CTL_INVI            0x00000800  // Invert Index Pulse
+#define QEI_CTL_INVB            0x00000400  // Invert PhB
+#define QEI_CTL_INVA            0x00000200  // Invert PhA
+#define QEI_CTL_VELDIV_M        0x000001C0  // Predivide Velocity
+#define QEI_CTL_VELDIV_1        0x00000000  // QEI clock /1
+#define QEI_CTL_VELDIV_2        0x00000040  // QEI clock /2
+#define QEI_CTL_VELDIV_4        0x00000080  // QEI clock /4
+#define QEI_CTL_VELDIV_8        0x000000C0  // QEI clock /8
+#define QEI_CTL_VELDIV_16       0x00000100  // QEI clock /16
+#define QEI_CTL_VELDIV_32       0x00000140  // QEI clock /32
+#define QEI_CTL_VELDIV_64       0x00000180  // QEI clock /64
+#define QEI_CTL_VELDIV_128      0x000001C0  // QEI clock /128
+#define QEI_CTL_VELEN           0x00000020  // Capture Velocity
+#define QEI_CTL_RESMODE         0x00000010  // Reset Mode
+#define QEI_CTL_CAPMODE         0x00000008  // Capture Mode
+#define QEI_CTL_SIGMODE         0x00000004  // Signal Mode
+#define QEI_CTL_SWAP            0x00000002  // Swap Signals
+#define QEI_CTL_ENABLE          0x00000001  // Enable QEI
+#define QEI_CTL_FILTCNT_S       16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_STAT register.
+//
+//*****************************************************************************
+#define QEI_STAT_DIRECTION      0x00000002  // Direction of Rotation
+#define QEI_STAT_ERROR          0x00000001  // Error Detected
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_POS register.
+//
+//*****************************************************************************
+#define QEI_POS_M               0xFFFFFFFF  // Current Position Integrator
+                                            // Value
+#define QEI_POS_S               0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_MAXPOS register.
+//
+//*****************************************************************************
+#define QEI_MAXPOS_M            0xFFFFFFFF  // Maximum Position Integrator
+                                            // Value
+#define QEI_MAXPOS_S            0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_LOAD register.
+//
+//*****************************************************************************
+#define QEI_LOAD_M              0xFFFFFFFF  // Velocity Timer Load Value
+#define QEI_LOAD_S              0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_TIME register.
+//
+//*****************************************************************************
+#define QEI_TIME_M              0xFFFFFFFF  // Velocity Timer Current Value
+#define QEI_TIME_S              0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_COUNT register.
+//
+//*****************************************************************************
+#define QEI_COUNT_M             0xFFFFFFFF  // Velocity Pulse Count
+#define QEI_COUNT_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_SPEED register.
+//
+//*****************************************************************************
+#define QEI_SPEED_M             0xFFFFFFFF  // Velocity
+#define QEI_SPEED_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_INTEN register.
+//
+//*****************************************************************************
+#define QEI_INTEN_ERROR         0x00000008  // Phase Error Interrupt Enable
+#define QEI_INTEN_DIR           0x00000004  // Direction Change Interrupt
+                                            // Enable
+#define QEI_INTEN_TIMER         0x00000002  // Timer Expires Interrupt Enable
+#define QEI_INTEN_INDEX         0x00000001  // Index Pulse Detected Interrupt
+                                            // Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_RIS register.
+//
+//*****************************************************************************
+#define QEI_RIS_ERROR           0x00000008  // Phase Error Detected
+#define QEI_RIS_DIR             0x00000004  // Direction Change Detected
+#define QEI_RIS_TIMER           0x00000002  // Velocity Timer Expired
+#define QEI_RIS_INDEX           0x00000001  // Index Pulse Asserted
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_ISC register.
+//
+//*****************************************************************************
+#define QEI_ISC_ERROR           0x00000008  // Phase Error Interrupt
+#define QEI_ISC_DIR             0x00000004  // Direction Change Interrupt
+#define QEI_ISC_TIMER           0x00000002  // Velocity Timer Expired Interrupt
+#define QEI_ISC_INDEX           0x00000001  // Index Pulse Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_CFG register.
+//
+//*****************************************************************************
+#define TIMER_CFG_M             0x00000007  // GPTM Configuration
+#define TIMER_CFG_32_BIT_TIMER  0x00000000  // 32-bit timer configuration
+#define TIMER_CFG_32_BIT_RTC    0x00000001  // 32-bit real-time clock (RTC)
+                                            // counter configuration
+#define TIMER_CFG_16_BIT        0x00000004  // 16-bit timer configuration. The
+                                            // function is controlled by bits
+                                            // 1:0 of GPTMTAMR and GPTMTBMR
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAMR register.
+//
+//*****************************************************************************
+#define TIMER_TAMR_TASNAPS      0x00000080  // GPTM Timer A Snap-Shot Mode
+#define TIMER_TAMR_TAWOT        0x00000040  // GPTM Timer A Wait-on-Trigger
+#define TIMER_TAMR_TAMIE        0x00000020  // GPTM Timer A Match Interrupt
+                                            // Enable
+#define TIMER_TAMR_TACDIR       0x00000010  // GPTM Timer A Count Direction
+#define TIMER_TAMR_TAAMS        0x00000008  // GPTM Timer A Alternate Mode
+                                            // Select
+#define TIMER_TAMR_TACMR        0x00000004  // GPTM Timer A Capture Mode
+#define TIMER_TAMR_TAMR_M       0x00000003  // GPTM Timer A Mode
+#define TIMER_TAMR_TAMR_1_SHOT  0x00000001  // One-Shot Timer mode
+#define TIMER_TAMR_TAMR_PERIOD  0x00000002  // Periodic Timer mode
+#define TIMER_TAMR_TAMR_CAP     0x00000003  // Capture mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBMR register.
+//
+//*****************************************************************************
+#define TIMER_TBMR_TBSNAPS      0x00000080  // GPTM Timer B Snap-Shot Mode
+#define TIMER_TBMR_TBWOT        0x00000040  // GPTM Timer B Wait-on-Trigger
+#define TIMER_TBMR_TBMIE        0x00000020  // GPTM Timer B Match Interrupt
+                                            // Enable
+#define TIMER_TBMR_TBCDIR       0x00000010  // GPTM Timer B Count Direction
+#define TIMER_TBMR_TBAMS        0x00000008  // GPTM Timer B Alternate Mode
+                                            // Select
+#define TIMER_TBMR_TBCMR        0x00000004  // GPTM Timer B Capture Mode
+#define TIMER_TBMR_TBMR_M       0x00000003  // GPTM Timer B Mode
+#define TIMER_TBMR_TBMR_1_SHOT  0x00000001  // One-Shot Timer mode
+#define TIMER_TBMR_TBMR_PERIOD  0x00000002  // Periodic Timer mode
+#define TIMER_TBMR_TBMR_CAP     0x00000003  // Capture mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_CTL register.
+//
+//*****************************************************************************
+#define TIMER_CTL_TBPWML        0x00004000  // GPTM Timer B PWM Output Level
+#define TIMER_CTL_TBOTE         0x00002000  // GPTM Timer B Output Trigger
+                                            // Enable
+#define TIMER_CTL_TBEVENT_M     0x00000C00  // GPTM Timer B Event Mode
+#define TIMER_CTL_TBEVENT_POS   0x00000000  // Positive edge
+#define TIMER_CTL_TBEVENT_NEG   0x00000400  // Negative edge
+#define TIMER_CTL_TBEVENT_BOTH  0x00000C00  // Both edges
+#define TIMER_CTL_TBSTALL       0x00000200  // GPTM Timer B Stall Enable
+#define TIMER_CTL_TBEN          0x00000100  // GPTM Timer B Enable
+#define TIMER_CTL_TAPWML        0x00000040  // GPTM Timer A PWM Output Level
+#define TIMER_CTL_TAOTE         0x00000020  // GPTM Timer A Output Trigger
+                                            // Enable
+#define TIMER_CTL_RTCEN         0x00000010  // GPTM RTC Enable
+#define TIMER_CTL_TAEVENT_M     0x0000000C  // GPTM Timer A Event Mode
+#define TIMER_CTL_TAEVENT_POS   0x00000000  // Positive edge
+#define TIMER_CTL_TAEVENT_NEG   0x00000004  // Negative edge
+#define TIMER_CTL_TAEVENT_BOTH  0x0000000C  // Both edges
+#define TIMER_CTL_TASTALL       0x00000002  // GPTM Timer A Stall Enable
+#define TIMER_CTL_TAEN          0x00000001  // GPTM Timer A Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_IMR register.
+//
+//*****************************************************************************
+#define TIMER_IMR_TBMIM         0x00000800  // GPTM Timer B Mode Match
+                                            // Interrupt Mask
+#define TIMER_IMR_CBEIM         0x00000400  // GPTM Capture B Event Interrupt
+                                            // Mask
+#define TIMER_IMR_CBMIM         0x00000200  // GPTM Capture B Match Interrupt
+                                            // Mask
+#define TIMER_IMR_TBTOIM        0x00000100  // GPTM Timer B Time-Out Interrupt
+                                            // Mask
+#define TIMER_IMR_TAMIM         0x00000010  // GPTM Timer A Mode Match
+                                            // Interrupt Mask
+#define TIMER_IMR_RTCIM         0x00000008  // GPTM RTC Interrupt Mask
+#define TIMER_IMR_CAEIM         0x00000004  // GPTM Capture A Event Interrupt
+                                            // Mask
+#define TIMER_IMR_CAMIM         0x00000002  // GPTM Capture A Match Interrupt
+                                            // Mask
+#define TIMER_IMR_TATOIM        0x00000001  // GPTM Timer A Time-Out Interrupt
+                                            // Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_RIS register.
+//
+//*****************************************************************************
+#define TIMER_RIS_TBMRIS        0x00000800  // GPTM Timer B Mode Match Raw
+                                            // Interrupt
+#define TIMER_RIS_CBERIS        0x00000400  // GPTM Capture B Event Raw
+                                            // Interrupt
+#define TIMER_RIS_CBMRIS        0x00000200  // GPTM Capture B Match Raw
+                                            // Interrupt
+#define TIMER_RIS_TBTORIS       0x00000100  // GPTM Timer B Time-Out Raw
+                                            // Interrupt
+#define TIMER_RIS_TAMRIS        0x00000010  // GPTM Timer A Mode Match Raw
+                                            // Interrupt
+#define TIMER_RIS_RTCRIS        0x00000008  // GPTM RTC Raw Interrupt
+#define TIMER_RIS_CAERIS        0x00000004  // GPTM Capture A Event Raw
+                                            // Interrupt
+#define TIMER_RIS_CAMRIS        0x00000002  // GPTM Capture A Match Raw
+                                            // Interrupt
+#define TIMER_RIS_TATORIS       0x00000001  // GPTM Timer A Time-Out Raw
+                                            // Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_MIS register.
+//
+//*****************************************************************************
+#define TIMER_MIS_TBMMIS        0x00000800  // GPTM Timer B Mode Match Masked
+                                            // Interrupt
+#define TIMER_MIS_CBEMIS        0x00000400  // GPTM Capture B Event Masked
+                                            // Interrupt
+#define TIMER_MIS_CBMMIS        0x00000200  // GPTM Capture B Match Masked
+                                            // Interrupt
+#define TIMER_MIS_TBTOMIS       0x00000100  // GPTM Timer B Time-Out Masked
+                                            // Interrupt
+#define TIMER_MIS_TAMMIS        0x00000010  // GPTM Timer A Mode Match Masked
+                                            // Interrupt
+#define TIMER_MIS_RTCMIS        0x00000008  // GPTM RTC Masked Interrupt
+#define TIMER_MIS_CAEMIS        0x00000004  // GPTM Capture A Event Masked
+                                            // Interrupt
+#define TIMER_MIS_CAMMIS        0x00000002  // GPTM Capture A Match Masked
+                                            // Interrupt
+#define TIMER_MIS_TATOMIS       0x00000001  // GPTM Timer A Time-Out Masked
+                                            // Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_ICR register.
+//
+//*****************************************************************************
+#define TIMER_ICR_TBMCINT       0x00000800  // GPTM Timer B Mode Match
+                                            // Interrupt Clear
+#define TIMER_ICR_CBECINT       0x00000400  // GPTM Capture B Event Interrupt
+                                            // Clear
+#define TIMER_ICR_CBMCINT       0x00000200  // GPTM Capture B Match Interrupt
+                                            // Clear
+#define TIMER_ICR_TBTOCINT      0x00000100  // GPTM Timer B Time-Out Interrupt
+                                            // Clear
+#define TIMER_ICR_TAMCINT       0x00000010  // GPTM Timer A Mode Match
+                                            // Interrupt Clear
+#define TIMER_ICR_RTCCINT       0x00000008  // GPTM RTC Interrupt Clear
+#define TIMER_ICR_CAECINT       0x00000004  // GPTM Capture A Event Interrupt
+                                            // Clear
+#define TIMER_ICR_CAMCINT       0x00000002  // GPTM Capture A Match Interrupt
+                                            // Clear
+#define TIMER_ICR_TATOCINT      0x00000001  // GPTM Timer A Time-Out Raw
+                                            // Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAILR register.
+//
+//*****************************************************************************
+#define TIMER_TAILR_TAILRH_M    0xFFFF0000  // GPTM Timer A Interval Load
+                                            // Register High
+#define TIMER_TAILR_TAILRL_M    0x0000FFFF  // GPTM Timer A Interval Load
+                                            // Register Low
+#define TIMER_TAILR_TAILRH_S    16
+#define TIMER_TAILR_TAILRL_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBILR register.
+//
+//*****************************************************************************
+#define TIMER_TBILR_TBILRL_M    0x0000FFFF  // GPTM Timer B Interval Load
+                                            // Register
+#define TIMER_TBILR_TBILRL_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAMATCHR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TAMATCHR_TAMRH_M  0xFFFF0000  // GPTM Timer A Match Register High
+#define TIMER_TAMATCHR_TAMRL_M  0x0000FFFF  // GPTM Timer A Match Register Low
+#define TIMER_TAMATCHR_TAMRH_S  16
+#define TIMER_TAMATCHR_TAMRL_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBMATCHR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TBMATCHR_TBMRL_M  0x0000FFFF  // GPTM Timer B Match Register Low
+#define TIMER_TBMATCHR_TBMRL_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAPR register.
+//
+//*****************************************************************************
+#define TIMER_TAPR_TAPSR_M      0x000000FF  // GPTM Timer A Prescale
+#define TIMER_TAPR_TAPSR_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBPR register.
+//
+//*****************************************************************************
+#define TIMER_TBPR_TBPSR_M      0x000000FF  // GPTM Timer B Prescale
+#define TIMER_TBPR_TBPSR_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAPMR register.
+//
+//*****************************************************************************
+#define TIMER_TAPMR_TAPSMR_M    0x000000FF  // GPTM TimerA Prescale Match
+#define TIMER_TAPMR_TAPSMR_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBPMR register.
+//
+//*****************************************************************************
+#define TIMER_TBPMR_TBPSMR_M    0x000000FF  // GPTM TimerB Prescale Match
+#define TIMER_TBPMR_TBPSMR_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAR register.
+//
+//*****************************************************************************
+#define TIMER_TAR_TARH_M        0xFFFF0000  // GPTM Timer A Register High
+#define TIMER_TAR_TARL_M        0x0000FFFF  // GPTM Timer A Register Low
+#define TIMER_TAR_TARH_S        16
+#define TIMER_TAR_TARL_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBR register.
+//
+//*****************************************************************************
+#define TIMER_TBR_TBRL_M        0x00FFFFFF  // GPTM Timer B
+#define TIMER_TBR_TBRL_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAV register.
+//
+//*****************************************************************************
+#define TIMER_TAV_TAVH_M        0xFFFF0000  // GPTM Timer A Value High
+#define TIMER_TAV_TAVL_M        0x0000FFFF  // GPTM Timer A Register Low
+#define TIMER_TAV_TAVH_S        16
+#define TIMER_TAV_TAVL_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBV register.
+//
+//*****************************************************************************
+#define TIMER_TBV_TBVL_M        0x0000FFFF  // GPTM Timer B Register
+#define TIMER_TBV_TBVL_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_ACTSS register.
+//
+//*****************************************************************************
+#define ADC_ACTSS_ASEN3         0x00000008  // ADC SS3 Enable
+#define ADC_ACTSS_ASEN2         0x00000004  // ADC SS2 Enable
+#define ADC_ACTSS_ASEN1         0x00000002  // ADC SS1 Enable
+#define ADC_ACTSS_ASEN0         0x00000001  // ADC SS0 Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_RIS register.
+//
+//*****************************************************************************
+#define ADC_RIS_INRDC           0x00010000  // Digital Comparator Raw Interrupt
+                                            // Status
+#define ADC_RIS_INR3            0x00000008  // SS3 Raw Interrupt Status
+#define ADC_RIS_INR2            0x00000004  // SS2 Raw Interrupt Status
+#define ADC_RIS_INR1            0x00000002  // SS1 Raw Interrupt Status
+#define ADC_RIS_INR0            0x00000001  // SS0 Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_IM register.
+//
+//*****************************************************************************
+#define ADC_IM_DCONSS3          0x00080000  // Digital Comparator Interrupt on
+                                            // SS3
+#define ADC_IM_DCONSS2          0x00040000  // Digital Comparator Interrupt on
+                                            // SS2
+#define ADC_IM_DCONSS1          0x00020000  // Digital Comparator Interrupt on
+                                            // SS1
+#define ADC_IM_DCONSS0          0x00010000  // Digital Comparator Interrupt on
+                                            // SS0
+#define ADC_IM_MASK3            0x00000008  // SS3 Interrupt Mask
+#define ADC_IM_MASK2            0x00000004  // SS2 Interrupt Mask
+#define ADC_IM_MASK1            0x00000002  // SS1 Interrupt Mask
+#define ADC_IM_MASK0            0x00000001  // SS0 Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_ISC register.
+//
+//*****************************************************************************
+#define ADC_ISC_DCINSS3         0x00080000  // Digital Comparator Interrupt
+                                            // Status on SS3
+#define ADC_ISC_DCINSS2         0x00040000  // Digital Comparator Interrupt
+                                            // Status on SS2
+#define ADC_ISC_DCINSS1         0x00020000  // Digital Comparator Interrupt
+                                            // Status on SS1
+#define ADC_ISC_DCINSS0         0x00010000  // Digital Comparator Interrupt
+                                            // Status on SS0
+#define ADC_ISC_IN3             0x00000008  // SS3 Interrupt Status and Clear
+#define ADC_ISC_IN2             0x00000004  // SS2 Interrupt Status and Clear
+#define ADC_ISC_IN1             0x00000002  // SS1 Interrupt Status and Clear
+#define ADC_ISC_IN0             0x00000001  // SS0 Interrupt Status and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_OSTAT register.
+//
+//*****************************************************************************
+#define ADC_OSTAT_OV3           0x00000008  // SS3 FIFO Overflow
+#define ADC_OSTAT_OV2           0x00000004  // SS2 FIFO Overflow
+#define ADC_OSTAT_OV1           0x00000002  // SS1 FIFO Overflow
+#define ADC_OSTAT_OV0           0x00000001  // SS0 FIFO Overflow
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_EMUX register.
+//
+//*****************************************************************************
+#define ADC_EMUX_EM3_M          0x0000F000  // SS3 Trigger Select
+#define ADC_EMUX_EM3_PROCESSOR  0x00000000  // Processor (default)
+#define ADC_EMUX_EM3_COMP0      0x00001000  // Analog Comparator 0
+#define ADC_EMUX_EM3_COMP1      0x00002000  // Analog Comparator 1
+#define ADC_EMUX_EM3_COMP2      0x00003000  // Analog Comparator 2
+#define ADC_EMUX_EM3_EXTERNAL   0x00004000  // External (GPIO PB4)
+#define ADC_EMUX_EM3_TIMER      0x00005000  // Timer
+#define ADC_EMUX_EM3_PWM0       0x00006000  // PWM0
+#define ADC_EMUX_EM3_PWM1       0x00007000  // PWM1
+#define ADC_EMUX_EM3_PWM2       0x00008000  // PWM2
+#define ADC_EMUX_EM3_PWM3       0x00009000  // PWM3
+#define ADC_EMUX_EM3_ALWAYS     0x0000F000  // Always (continuously sample)
+#define ADC_EMUX_EM2_M          0x00000F00  // SS2 Trigger Select
+#define ADC_EMUX_EM2_PROCESSOR  0x00000000  // Processor (default)
+#define ADC_EMUX_EM2_COMP0      0x00000100  // Analog Comparator 0
+#define ADC_EMUX_EM2_COMP1      0x00000200  // Analog Comparator 1
+#define ADC_EMUX_EM2_COMP2      0x00000300  // Analog Comparator 2
+#define ADC_EMUX_EM2_EXTERNAL   0x00000400  // External (GPIO PB4)
+#define ADC_EMUX_EM2_TIMER      0x00000500  // Timer
+#define ADC_EMUX_EM2_PWM0       0x00000600  // PWM0
+#define ADC_EMUX_EM2_PWM1       0x00000700  // PWM1
+#define ADC_EMUX_EM2_PWM2       0x00000800  // PWM2
+#define ADC_EMUX_EM2_PWM3       0x00000900  // PWM3
+#define ADC_EMUX_EM2_ALWAYS     0x00000F00  // Always (continuously sample)
+#define ADC_EMUX_EM1_M          0x000000F0  // SS1 Trigger Select
+#define ADC_EMUX_EM1_PROCESSOR  0x00000000  // Processor (default)
+#define ADC_EMUX_EM1_COMP0      0x00000010  // Analog Comparator 0
+#define ADC_EMUX_EM1_COMP1      0x00000020  // Analog Comparator 1
+#define ADC_EMUX_EM1_COMP2      0x00000030  // Analog Comparator 2
+#define ADC_EMUX_EM1_EXTERNAL   0x00000040  // External (GPIO PB4)
+#define ADC_EMUX_EM1_TIMER      0x00000050  // Timer
+#define ADC_EMUX_EM1_PWM0       0x00000060  // PWM0
+#define ADC_EMUX_EM1_PWM1       0x00000070  // PWM1
+#define ADC_EMUX_EM1_PWM2       0x00000080  // PWM2
+#define ADC_EMUX_EM1_PWM3       0x00000090  // PWM3
+#define ADC_EMUX_EM1_ALWAYS     0x000000F0  // Always (continuously sample)
+#define ADC_EMUX_EM0_M          0x0000000F  // SS0 Trigger Select
+#define ADC_EMUX_EM0_PROCESSOR  0x00000000  // Processor (default)
+#define ADC_EMUX_EM0_COMP0      0x00000001  // Analog Comparator 0
+#define ADC_EMUX_EM0_COMP1      0x00000002  // Analog Comparator 1
+#define ADC_EMUX_EM0_COMP2      0x00000003  // Analog Comparator 2
+#define ADC_EMUX_EM0_EXTERNAL   0x00000004  // External (GPIO PB4)
+#define ADC_EMUX_EM0_TIMER      0x00000005  // Timer
+#define ADC_EMUX_EM0_PWM0       0x00000006  // PWM0
+#define ADC_EMUX_EM0_PWM1       0x00000007  // PWM1
+#define ADC_EMUX_EM0_PWM2       0x00000008  // PWM2
+#define ADC_EMUX_EM0_PWM3       0x00000009  // PWM3
+#define ADC_EMUX_EM0_ALWAYS     0x0000000F  // Always (continuously sample)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_USTAT register.
+//
+//*****************************************************************************
+#define ADC_USTAT_UV3           0x00000008  // SS3 FIFO Underflow
+#define ADC_USTAT_UV2           0x00000004  // SS2 FIFO Underflow
+#define ADC_USTAT_UV1           0x00000002  // SS1 FIFO Underflow
+#define ADC_USTAT_UV0           0x00000001  // SS0 FIFO Underflow
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSPRI register.
+//
+//*****************************************************************************
+#define ADC_SSPRI_SS3_M         0x00003000  // SS3 Priority
+#define ADC_SSPRI_SS3_1ST       0x00000000  // First priority
+#define ADC_SSPRI_SS3_2ND       0x00001000  // Second priority
+#define ADC_SSPRI_SS3_3RD       0x00002000  // Third priority
+#define ADC_SSPRI_SS3_4TH       0x00003000  // Fourth priority
+#define ADC_SSPRI_SS2_M         0x00000300  // SS2 Priority
+#define ADC_SSPRI_SS2_1ST       0x00000000  // First priority
+#define ADC_SSPRI_SS2_2ND       0x00000100  // Second priority
+#define ADC_SSPRI_SS2_3RD       0x00000200  // Third priority
+#define ADC_SSPRI_SS2_4TH       0x00000300  // Fourth priority
+#define ADC_SSPRI_SS1_M         0x00000030  // SS1 Priority
+#define ADC_SSPRI_SS1_1ST       0x00000000  // First priority
+#define ADC_SSPRI_SS1_2ND       0x00000010  // Second priority
+#define ADC_SSPRI_SS1_3RD       0x00000020  // Third priority
+#define ADC_SSPRI_SS1_4TH       0x00000030  // Fourth priority
+#define ADC_SSPRI_SS0_M         0x00000003  // SS0 Priority
+#define ADC_SSPRI_SS0_1ST       0x00000000  // First priority
+#define ADC_SSPRI_SS0_2ND       0x00000001  // Second priority
+#define ADC_SSPRI_SS0_3RD       0x00000002  // Third priority
+#define ADC_SSPRI_SS0_4TH       0x00000003  // Fourth priority
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SPC register.
+//
+//*****************************************************************************
+#define ADC_SPC_PHASE_M         0x0000000F  // Phase Difference
+#define ADC_SPC_PHASE_0         0x00000000  // ADC sample lags by 0.0
+#define ADC_SPC_PHASE_22_5      0x00000001  // ADC sample lags by 22.5
+#define ADC_SPC_PHASE_45        0x00000002  // ADC sample lags by 45.0
+#define ADC_SPC_PHASE_67_5      0x00000003  // ADC sample lags by 67.5
+#define ADC_SPC_PHASE_90        0x00000004  // ADC sample lags by 90.0
+#define ADC_SPC_PHASE_112_5     0x00000005  // ADC sample lags by 112.5
+#define ADC_SPC_PHASE_135       0x00000006  // ADC sample lags by 135.0
+#define ADC_SPC_PHASE_157_5     0x00000007  // ADC sample lags by 157.5
+#define ADC_SPC_PHASE_180       0x00000008  // ADC sample lags by 180.0
+#define ADC_SPC_PHASE_202_5     0x00000009  // ADC sample lags by 202.5
+#define ADC_SPC_PHASE_225       0x0000000A  // ADC sample lags by 225.0
+#define ADC_SPC_PHASE_247_5     0x0000000B  // ADC sample lags by 247.5
+#define ADC_SPC_PHASE_270       0x0000000C  // ADC sample lags by 270.0
+#define ADC_SPC_PHASE_292_5     0x0000000D  // ADC sample lags by 292.5
+#define ADC_SPC_PHASE_315       0x0000000E  // ADC sample lags by 315.0
+#define ADC_SPC_PHASE_337_5     0x0000000F  // ADC sample lags by 337.5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_PSSI register.
+//
+//*****************************************************************************
+#define ADC_PSSI_GSYNC          0x80000000  // Global Synchronize
+#define ADC_PSSI_SYNCWAIT       0x08000000  // Synchronize Wait
+#define ADC_PSSI_SS3            0x00000008  // SS3 Initiate
+#define ADC_PSSI_SS2            0x00000004  // SS2 Initiate
+#define ADC_PSSI_SS1            0x00000002  // SS1 Initiate
+#define ADC_PSSI_SS0            0x00000001  // SS0 Initiate
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SAC register.
+//
+//*****************************************************************************
+#define ADC_SAC_AVG_M           0x00000007  // Hardware Averaging Control
+#define ADC_SAC_AVG_OFF         0x00000000  // No hardware oversampling
+#define ADC_SAC_AVG_2X          0x00000001  // 2x hardware oversampling
+#define ADC_SAC_AVG_4X          0x00000002  // 4x hardware oversampling
+#define ADC_SAC_AVG_8X          0x00000003  // 8x hardware oversampling
+#define ADC_SAC_AVG_16X         0x00000004  // 16x hardware oversampling
+#define ADC_SAC_AVG_32X         0x00000005  // 32x hardware oversampling
+#define ADC_SAC_AVG_64X         0x00000006  // 64x hardware oversampling
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCISC register.
+//
+//*****************************************************************************
+#define ADC_DCISC_DCINT7        0x00000080  // Digital Comparator 7 Interrupt
+                                            // Status and Clear
+#define ADC_DCISC_DCINT6        0x00000040  // Digital Comparator 6 Interrupt
+                                            // Status and Clear
+#define ADC_DCISC_DCINT5        0x00000020  // Digital Comparator 5 Interrupt
+                                            // Status and Clear
+#define ADC_DCISC_DCINT4        0x00000010  // Digital Comparator 4 Interrupt
+                                            // Status and Clear
+#define ADC_DCISC_DCINT3        0x00000008  // Digital Comparator 3 Interrupt
+                                            // Status and Clear
+#define ADC_DCISC_DCINT2        0x00000004  // Digital Comparator 2 Interrupt
+                                            // Status and Clear
+#define ADC_DCISC_DCINT1        0x00000002  // Digital Comparator 1 Interrupt
+                                            // Status and Clear
+#define ADC_DCISC_DCINT0        0x00000001  // Digital Comparator 0 Interrupt
+                                            // Status and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_CTL register.
+//
+//*****************************************************************************
+#define ADC_CTL_RES             0x00000010  // Sample Resolution
+#define ADC_CTL_VREF_M          0x00000003  // Voltage Reference Select
+#define ADC_CTL_VREF_INTERNAL   0x00000000  // The internal reference as the
+                                            // voltage reference
+#define ADC_CTL_VREF_EXT_3V     0x00000001  // A 3.0 V external VREFA input is
+                                            // the voltage reference. The ADC
+                                            // conversion range is 0.0 V to the
+                                            // external reference value
+#define ADC_CTL_VREF_EXT_1V     0x00000003  // A 1.0 V external VREFA input is
+                                            // the voltage reference. The ADC
+                                            // conversion range is 0.0 V to
+                                            // three times the external
+                                            // reference value
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX0 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX0_MUX7_M       0xF0000000  // 8th Sample Input Select
+#define ADC_SSMUX0_MUX6_M       0x0F000000  // 7th Sample Input Select
+#define ADC_SSMUX0_MUX5_M       0x00F00000  // 6th Sample Input Select
+#define ADC_SSMUX0_MUX4_M       0x000F0000  // 5th Sample Input Select
+#define ADC_SSMUX0_MUX3_M       0x0000F000  // 4th Sample Input Select
+#define ADC_SSMUX0_MUX2_M       0x00000F00  // 3rd Sample Input Select
+#define ADC_SSMUX0_MUX1_M       0x000000F0  // 2nd Sample Input Select
+#define ADC_SSMUX0_MUX0_M       0x0000000F  // 1st Sample Input Select
+#define ADC_SSMUX0_MUX7_S       28
+#define ADC_SSMUX0_MUX6_S       24
+#define ADC_SSMUX0_MUX5_S       20
+#define ADC_SSMUX0_MUX4_S       16
+#define ADC_SSMUX0_MUX3_S       12
+#define ADC_SSMUX0_MUX2_S       8
+#define ADC_SSMUX0_MUX1_S       4
+#define ADC_SSMUX0_MUX0_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL0 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL0_TS7          0x80000000  // 8th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE7          0x40000000  // 8th Sample Interrupt Enable
+#define ADC_SSCTL0_END7         0x20000000  // 8th Sample is End of Sequence
+#define ADC_SSCTL0_D7           0x10000000  // 8th Sample Diff Input Select
+#define ADC_SSCTL0_TS6          0x08000000  // 7th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE6          0x04000000  // 7th Sample Interrupt Enable
+#define ADC_SSCTL0_END6         0x02000000  // 7th Sample is End of Sequence
+#define ADC_SSCTL0_D6           0x01000000  // 7th Sample Diff Input Select
+#define ADC_SSCTL0_TS5          0x00800000  // 6th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE5          0x00400000  // 6th Sample Interrupt Enable
+#define ADC_SSCTL0_END5         0x00200000  // 6th Sample is End of Sequence
+#define ADC_SSCTL0_D5           0x00100000  // 6th Sample Diff Input Select
+#define ADC_SSCTL0_TS4          0x00080000  // 5th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE4          0x00040000  // 5th Sample Interrupt Enable
+#define ADC_SSCTL0_END4         0x00020000  // 5th Sample is End of Sequence
+#define ADC_SSCTL0_D4           0x00010000  // 5th Sample Diff Input Select
+#define ADC_SSCTL0_TS3          0x00008000  // 4th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE3          0x00004000  // 4th Sample Interrupt Enable
+#define ADC_SSCTL0_END3         0x00002000  // 4th Sample is End of Sequence
+#define ADC_SSCTL0_D3           0x00001000  // 4th Sample Diff Input Select
+#define ADC_SSCTL0_TS2          0x00000800  // 3rd Sample Temp Sensor Select
+#define ADC_SSCTL0_IE2          0x00000400  // 3rd Sample Interrupt Enable
+#define ADC_SSCTL0_END2         0x00000200  // 3rd Sample is End of Sequence
+#define ADC_SSCTL0_D2           0x00000100  // 3rd Sample Diff Input Select
+#define ADC_SSCTL0_TS1          0x00000080  // 2nd Sample Temp Sensor Select
+#define ADC_SSCTL0_IE1          0x00000040  // 2nd Sample Interrupt Enable
+#define ADC_SSCTL0_END1         0x00000020  // 2nd Sample is End of Sequence
+#define ADC_SSCTL0_D1           0x00000010  // 2nd Sample Diff Input Select
+#define ADC_SSCTL0_TS0          0x00000008  // 1st Sample Temp Sensor Select
+#define ADC_SSCTL0_IE0          0x00000004  // 1st Sample Interrupt Enable
+#define ADC_SSCTL0_END0         0x00000002  // 1st Sample is End of Sequence
+#define ADC_SSCTL0_D0           0x00000001  // 1st Sample Diff Input Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO0 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO0_DATA_M      0x00000FFF  // Conversion Result Data
+#define ADC_SSFIFO0_DATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT0 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT0_FULL       0x00001000  // FIFO Full
+#define ADC_SSFSTAT0_EMPTY      0x00000100  // FIFO Empty
+#define ADC_SSFSTAT0_HPTR_M     0x000000F0  // FIFO Head Pointer
+#define ADC_SSFSTAT0_TPTR_M     0x0000000F  // FIFO Tail Pointer
+#define ADC_SSFSTAT0_HPTR_S     4
+#define ADC_SSFSTAT0_TPTR_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSOP0 register.
+//
+//*****************************************************************************
+#define ADC_SSOP0_S7DCOP        0x10000000  // Sample 7 Digital Comparator
+                                            // Operation
+#define ADC_SSOP0_S6DCOP        0x01000000  // Sample 6 Digital Comparator
+                                            // Operation
+#define ADC_SSOP0_S5DCOP        0x00100000  // Sample 5 Digital Comparator
+                                            // Operation
+#define ADC_SSOP0_S4DCOP        0x00010000  // Sample 4 Digital Comparator
+                                            // Operation
+#define ADC_SSOP0_S3DCOP        0x00001000  // Sample 3 Digital Comparator
+                                            // Operation
+#define ADC_SSOP0_S2DCOP        0x00000100  // Sample 2 Digital Comparator
+                                            // Operation
+#define ADC_SSOP0_S1DCOP        0x00000010  // Sample 1 Digital Comparator
+                                            // Operation
+#define ADC_SSOP0_S0DCOP        0x00000001  // Sample 0 Digital Comparator
+                                            // Operation
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSDC0 register.
+//
+//*****************************************************************************
+#define ADC_SSDC0_S7DCSEL_M     0xF0000000  // Sample 7 Digital Comparator
+                                            // Select
+#define ADC_SSDC0_S6DCSEL_M     0x0F000000  // Sample 6 Digital Comparator
+                                            // Select
+#define ADC_SSDC0_S5DCSEL_M     0x00F00000  // Sample 5 Digital Comparator
+                                            // Select
+#define ADC_SSDC0_S4DCSEL_M     0x000F0000  // Sample 4 Digital Comparator
+                                            // Select
+#define ADC_SSDC0_S3DCSEL_M     0x0000F000  // Sample 3 Digital Comparator
+                                            // Select
+#define ADC_SSDC0_S2DCSEL_M     0x00000F00  // Sample 2 Digital Comparator
+                                            // Select
+#define ADC_SSDC0_S1DCSEL_M     0x000000F0  // Sample 1 Digital Comparator
+                                            // Select
+#define ADC_SSDC0_S0DCSEL_M     0x0000000F  // Sample 0 Digital Comparator
+                                            // Select
+#define ADC_SSDC0_S6DCSEL_S     24
+#define ADC_SSDC0_S5DCSEL_S     20
+#define ADC_SSDC0_S4DCSEL_S     16
+#define ADC_SSDC0_S3DCSEL_S     12
+#define ADC_SSDC0_S2DCSEL_S     8
+#define ADC_SSDC0_S1DCSEL_S     4
+#define ADC_SSDC0_S0DCSEL_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX1 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX1_MUX3_M       0x0000F000  // 4th Sample Input Select
+#define ADC_SSMUX1_MUX2_M       0x00000F00  // 3rd Sample Input Select
+#define ADC_SSMUX1_MUX1_M       0x000000F0  // 2nd Sample Input Select
+#define ADC_SSMUX1_MUX0_M       0x0000000F  // 1st Sample Input Select
+#define ADC_SSMUX1_MUX3_S       12
+#define ADC_SSMUX1_MUX2_S       8
+#define ADC_SSMUX1_MUX1_S       4
+#define ADC_SSMUX1_MUX0_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL1 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL1_TS3          0x00008000  // 4th Sample Temp Sensor Select
+#define ADC_SSCTL1_IE3          0x00004000  // 4th Sample Interrupt Enable
+#define ADC_SSCTL1_END3         0x00002000  // 4th Sample is End of Sequence
+#define ADC_SSCTL1_D3           0x00001000  // 4th Sample Diff Input Select
+#define ADC_SSCTL1_TS2          0x00000800  // 3rd Sample Temp Sensor Select
+#define ADC_SSCTL1_IE2          0x00000400  // 3rd Sample Interrupt Enable
+#define ADC_SSCTL1_END2         0x00000200  // 3rd Sample is End of Sequence
+#define ADC_SSCTL1_D2           0x00000100  // 3rd Sample Diff Input Select
+#define ADC_SSCTL1_TS1          0x00000080  // 2nd Sample Temp Sensor Select
+#define ADC_SSCTL1_IE1          0x00000040  // 2nd Sample Interrupt Enable
+#define ADC_SSCTL1_END1         0x00000020  // 2nd Sample is End of Sequence
+#define ADC_SSCTL1_D1           0x00000010  // 2nd Sample Diff Input Select
+#define ADC_SSCTL1_TS0          0x00000008  // 1st Sample Temp Sensor Select
+#define ADC_SSCTL1_IE0          0x00000004  // 1st Sample Interrupt Enable
+#define ADC_SSCTL1_END0         0x00000002  // 1st Sample is End of Sequence
+#define ADC_SSCTL1_D0           0x00000001  // 1st Sample Diff Input Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO1 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO1_DATA_M      0x00000FFF  // Conversion Result Data
+#define ADC_SSFIFO1_DATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT1 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT1_FULL       0x00001000  // FIFO Full
+#define ADC_SSFSTAT1_EMPTY      0x00000100  // FIFO Empty
+#define ADC_SSFSTAT1_HPTR_M     0x000000F0  // FIFO Head Pointer
+#define ADC_SSFSTAT1_TPTR_M     0x0000000F  // FIFO Tail Pointer
+#define ADC_SSFSTAT1_HPTR_S     4
+#define ADC_SSFSTAT1_TPTR_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSOP1 register.
+//
+//*****************************************************************************
+#define ADC_SSOP1_S3DCOP        0x00001000  // Sample 3 Digital Comparator
+                                            // Operation
+#define ADC_SSOP1_S2DCOP        0x00000100  // Sample 2 Digital Comparator
+                                            // Operation
+#define ADC_SSOP1_S1DCOP        0x00000010  // Sample 1 Digital Comparator
+                                            // Operation
+#define ADC_SSOP1_S0DCOP        0x00000001  // Sample 0 Digital Comparator
+                                            // Operation
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSDC1 register.
+//
+//*****************************************************************************
+#define ADC_SSDC1_S3DCSEL_M     0x0000F000  // Sample 3 Digital Comparator
+                                            // Select
+#define ADC_SSDC1_S2DCSEL_M     0x00000F00  // Sample 2 Digital Comparator
+                                            // Select
+#define ADC_SSDC1_S1DCSEL_M     0x000000F0  // Sample 1 Digital Comparator
+                                            // Select
+#define ADC_SSDC1_S0DCSEL_M     0x0000000F  // Sample 0 Digital Comparator
+                                            // Select
+#define ADC_SSDC1_S2DCSEL_S     8
+#define ADC_SSDC1_S1DCSEL_S     4
+#define ADC_SSDC1_S0DCSEL_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX2 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX2_MUX3_M       0x0000F000  // 4th Sample Input Select
+#define ADC_SSMUX2_MUX2_M       0x00000F00  // 3rd Sample Input Select
+#define ADC_SSMUX2_MUX1_M       0x000000F0  // 2nd Sample Input Select
+#define ADC_SSMUX2_MUX0_M       0x0000000F  // 1st Sample Input Select
+#define ADC_SSMUX2_MUX3_S       12
+#define ADC_SSMUX2_MUX2_S       8
+#define ADC_SSMUX2_MUX1_S       4
+#define ADC_SSMUX2_MUX0_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL2 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL2_TS3          0x00008000  // 4th Sample Temp Sensor Select
+#define ADC_SSCTL2_IE3          0x00004000  // 4th Sample Interrupt Enable
+#define ADC_SSCTL2_END3         0x00002000  // 4th Sample is End of Sequence
+#define ADC_SSCTL2_D3           0x00001000  // 4th Sample Diff Input Select
+#define ADC_SSCTL2_TS2          0x00000800  // 3rd Sample Temp Sensor Select
+#define ADC_SSCTL2_IE2          0x00000400  // 3rd Sample Interrupt Enable
+#define ADC_SSCTL2_END2         0x00000200  // 3rd Sample is End of Sequence
+#define ADC_SSCTL2_D2           0x00000100  // 3rd Sample Diff Input Select
+#define ADC_SSCTL2_TS1          0x00000080  // 2nd Sample Temp Sensor Select
+#define ADC_SSCTL2_IE1          0x00000040  // 2nd Sample Interrupt Enable
+#define ADC_SSCTL2_END1         0x00000020  // 2nd Sample is End of Sequence
+#define ADC_SSCTL2_D1           0x00000010  // 2nd Sample Diff Input Select
+#define ADC_SSCTL2_TS0          0x00000008  // 1st Sample Temp Sensor Select
+#define ADC_SSCTL2_IE0          0x00000004  // 1st Sample Interrupt Enable
+#define ADC_SSCTL2_END0         0x00000002  // 1st Sample is End of Sequence
+#define ADC_SSCTL2_D0           0x00000001  // 1st Sample Diff Input Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO2 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO2_DATA_M      0x00000FFF  // Conversion Result Data
+#define ADC_SSFIFO2_DATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT2 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT2_FULL       0x00001000  // FIFO Full
+#define ADC_SSFSTAT2_EMPTY      0x00000100  // FIFO Empty
+#define ADC_SSFSTAT2_HPTR_M     0x000000F0  // FIFO Head Pointer
+#define ADC_SSFSTAT2_TPTR_M     0x0000000F  // FIFO Tail Pointer
+#define ADC_SSFSTAT2_HPTR_S     4
+#define ADC_SSFSTAT2_TPTR_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSOP2 register.
+//
+//*****************************************************************************
+#define ADC_SSOP2_S3DCOP        0x00001000  // Sample 3 Digital Comparator
+                                            // Operation
+#define ADC_SSOP2_S2DCOP        0x00000100  // Sample 2 Digital Comparator
+                                            // Operation
+#define ADC_SSOP2_S1DCOP        0x00000010  // Sample 1 Digital Comparator
+                                            // Operation
+#define ADC_SSOP2_S0DCOP        0x00000001  // Sample 0 Digital Comparator
+                                            // Operation
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSDC2 register.
+//
+//*****************************************************************************
+#define ADC_SSDC2_S3DCSEL_M     0x0000F000  // Sample 3 Digital Comparator
+                                            // Select
+#define ADC_SSDC2_S2DCSEL_M     0x00000F00  // Sample 2 Digital Comparator
+                                            // Select
+#define ADC_SSDC2_S1DCSEL_M     0x000000F0  // Sample 1 Digital Comparator
+                                            // Select
+#define ADC_SSDC2_S0DCSEL_M     0x0000000F  // Sample 0 Digital Comparator
+                                            // Select
+#define ADC_SSDC2_S2DCSEL_S     8
+#define ADC_SSDC2_S1DCSEL_S     4
+#define ADC_SSDC2_S0DCSEL_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX3 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX3_MUX0_M       0x0000000F  // 1st Sample Input Select
+#define ADC_SSMUX3_MUX0_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL3 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL3_TS0          0x00000008  // 1st Sample Temp Sensor Select
+#define ADC_SSCTL3_IE0          0x00000004  // 1st Sample Interrupt Enable
+#define ADC_SSCTL3_END0         0x00000002  // 1st Sample is End of Sequence
+#define ADC_SSCTL3_D0           0x00000001  // 1st Sample Diff Input Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO3 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO3_DATA_M      0x00000FFF  // Conversion Result Data
+#define ADC_SSFIFO3_DATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT3 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT3_FULL       0x00001000  // FIFO Full
+#define ADC_SSFSTAT3_EMPTY      0x00000100  // FIFO Empty
+#define ADC_SSFSTAT3_HPTR_M     0x000000F0  // FIFO Head Pointer
+#define ADC_SSFSTAT3_TPTR_M     0x0000000F  // FIFO Tail Pointer
+#define ADC_SSFSTAT3_HPTR_S     4
+#define ADC_SSFSTAT3_TPTR_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSOP3 register.
+//
+//*****************************************************************************
+#define ADC_SSOP3_S0DCOP        0x00000001  // Sample 0 Digital Comparator
+                                            // Operation
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSDC3 register.
+//
+//*****************************************************************************
+#define ADC_SSDC3_S0DCSEL_M     0x0000000F  // Sample 0 Digital Comparator
+                                            // Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCRIC register.
+//
+//*****************************************************************************
+#define ADC_DCRIC_DCTRIG7       0x00800000  // Digital Comparator Trigger 7
+#define ADC_DCRIC_DCTRIG6       0x00400000  // Digital Comparator Trigger 6
+#define ADC_DCRIC_DCTRIG5       0x00200000  // Digital Comparator Trigger 5
+#define ADC_DCRIC_DCTRIG4       0x00100000  // Digital Comparator Trigger 4
+#define ADC_DCRIC_DCTRIG3       0x00080000  // Digital Comparator Trigger 3
+#define ADC_DCRIC_DCTRIG2       0x00040000  // Digital Comparator Trigger 2
+#define ADC_DCRIC_DCTRIG1       0x00020000  // Digital Comparator Trigger 1
+#define ADC_DCRIC_DCTRIG0       0x00010000  // Digital Comparator Trigger 0
+#define ADC_DCRIC_DCINT7        0x00000080  // Digital Comparator Interrupt 7
+#define ADC_DCRIC_DCINT6        0x00000040  // Digital Comparator Interrupt 6
+#define ADC_DCRIC_DCINT5        0x00000020  // Digital Comparator Interrupt 5
+#define ADC_DCRIC_DCINT4        0x00000010  // Digital Comparator Interrupt 4
+#define ADC_DCRIC_DCINT3        0x00000008  // Digital Comparator Interrupt 3
+#define ADC_DCRIC_DCINT2        0x00000004  // Digital Comparator Interrupt 2
+#define ADC_DCRIC_DCINT1        0x00000002  // Digital Comparator Interrupt 1
+#define ADC_DCRIC_DCINT0        0x00000001  // Digital Comparator Interrupt 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL0 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL0_CTE          0x00001000  // Comparison Trigger Enable
+#define ADC_DCCTL0_CTC_M        0x00000C00  // Comparison Trigger Condition
+#define ADC_DCCTL0_CTC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL0_CTC_MID      0x00000400  // Mid Band
+#define ADC_DCCTL0_CTC_HIGH     0x00000C00  // High Band
+#define ADC_DCCTL0_CTM_M        0x00000300  // Comparison Trigger Mode
+#define ADC_DCCTL0_CTM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL0_CTM_ONCE     0x00000100  // Once
+#define ADC_DCCTL0_CTM_HALWAYS  0x00000200  // Hysteresis Always
+#define ADC_DCCTL0_CTM_HONCE    0x00000300  // Hysteresis Once
+#define ADC_DCCTL0_CIE          0x00000010  // Comparison Interrupt Enable
+#define ADC_DCCTL0_CIC_M        0x0000000C  // Comparison Interrupt Condition
+#define ADC_DCCTL0_CIC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL0_CIC_MID      0x00000004  // Mid Band
+#define ADC_DCCTL0_CIC_HIGH     0x0000000C  // High Band
+#define ADC_DCCTL0_CIM_M        0x00000003  // Comparison Interrupt Mode
+#define ADC_DCCTL0_CIM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL0_CIM_ONCE     0x00000001  // Once
+#define ADC_DCCTL0_CIM_HALWAYS  0x00000002  // Hysteresis Always
+#define ADC_DCCTL0_CIM_HONCE    0x00000003  // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL1 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL1_CTE          0x00001000  // Comparison Trigger Enable
+#define ADC_DCCTL1_CTC_M        0x00000C00  // Comparison Trigger Condition
+#define ADC_DCCTL1_CTC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL1_CTC_MID      0x00000400  // Mid Band
+#define ADC_DCCTL1_CTC_HIGH     0x00000C00  // High Band
+#define ADC_DCCTL1_CTM_M        0x00000300  // Comparison Trigger Mode
+#define ADC_DCCTL1_CTM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL1_CTM_ONCE     0x00000100  // Once
+#define ADC_DCCTL1_CTM_HALWAYS  0x00000200  // Hysteresis Always
+#define ADC_DCCTL1_CTM_HONCE    0x00000300  // Hysteresis Once
+#define ADC_DCCTL1_CIE          0x00000010  // Comparison Interrupt Enable
+#define ADC_DCCTL1_CIC_M        0x0000000C  // Comparison Interrupt Condition
+#define ADC_DCCTL1_CIC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL1_CIC_MID      0x00000004  // Mid Band
+#define ADC_DCCTL1_CIC_HIGH     0x0000000C  // High Band
+#define ADC_DCCTL1_CIM_M        0x00000003  // Comparison Interrupt Mode
+#define ADC_DCCTL1_CIM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL1_CIM_ONCE     0x00000001  // Once
+#define ADC_DCCTL1_CIM_HALWAYS  0x00000002  // Hysteresis Always
+#define ADC_DCCTL1_CIM_HONCE    0x00000003  // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL2 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL2_CTE          0x00001000  // Comparison Trigger Enable
+#define ADC_DCCTL2_CTC_M        0x00000C00  // Comparison Trigger Condition
+#define ADC_DCCTL2_CTC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL2_CTC_MID      0x00000400  // Mid Band
+#define ADC_DCCTL2_CTC_HIGH     0x00000C00  // High Band
+#define ADC_DCCTL2_CTM_M        0x00000300  // Comparison Trigger Mode
+#define ADC_DCCTL2_CTM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL2_CTM_ONCE     0x00000100  // Once
+#define ADC_DCCTL2_CTM_HALWAYS  0x00000200  // Hysteresis Always
+#define ADC_DCCTL2_CTM_HONCE    0x00000300  // Hysteresis Once
+#define ADC_DCCTL2_CIE          0x00000010  // Comparison Interrupt Enable
+#define ADC_DCCTL2_CIC_M        0x0000000C  // Comparison Interrupt Condition
+#define ADC_DCCTL2_CIC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL2_CIC_MID      0x00000004  // Mid Band
+#define ADC_DCCTL2_CIC_HIGH     0x0000000C  // High Band
+#define ADC_DCCTL2_CIM_M        0x00000003  // Comparison Interrupt Mode
+#define ADC_DCCTL2_CIM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL2_CIM_ONCE     0x00000001  // Once
+#define ADC_DCCTL2_CIM_HALWAYS  0x00000002  // Hysteresis Always
+#define ADC_DCCTL2_CIM_HONCE    0x00000003  // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL3 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL3_CTE          0x00001000  // Comparison Trigger Enable
+#define ADC_DCCTL3_CTC_M        0x00000C00  // Comparison Trigger Condition
+#define ADC_DCCTL3_CTC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL3_CTC_MID      0x00000400  // Mid Band
+#define ADC_DCCTL3_CTC_HIGH     0x00000C00  // High Band
+#define ADC_DCCTL3_CTM_M        0x00000300  // Comparison Trigger Mode
+#define ADC_DCCTL3_CTM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL3_CTM_ONCE     0x00000100  // Once
+#define ADC_DCCTL3_CTM_HALWAYS  0x00000200  // Hysteresis Always
+#define ADC_DCCTL3_CTM_HONCE    0x00000300  // Hysteresis Once
+#define ADC_DCCTL3_CIE          0x00000010  // Comparison Interrupt Enable
+#define ADC_DCCTL3_CIC_M        0x0000000C  // Comparison Interrupt Condition
+#define ADC_DCCTL3_CIC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL3_CIC_MID      0x00000004  // Mid Band
+#define ADC_DCCTL3_CIC_HIGH     0x0000000C  // High Band
+#define ADC_DCCTL3_CIM_M        0x00000003  // Comparison Interrupt Mode
+#define ADC_DCCTL3_CIM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL3_CIM_ONCE     0x00000001  // Once
+#define ADC_DCCTL3_CIM_HALWAYS  0x00000002  // Hysteresis Always
+#define ADC_DCCTL3_CIM_HONCE    0x00000003  // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL4 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL4_CTE          0x00001000  // Comparison Trigger Enable
+#define ADC_DCCTL4_CTC_M        0x00000C00  // Comparison Trigger Condition
+#define ADC_DCCTL4_CTC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL4_CTC_MID      0x00000400  // Mid Band
+#define ADC_DCCTL4_CTC_HIGH     0x00000C00  // High Band
+#define ADC_DCCTL4_CTM_M        0x00000300  // Comparison Trigger Mode
+#define ADC_DCCTL4_CTM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL4_CTM_ONCE     0x00000100  // Once
+#define ADC_DCCTL4_CTM_HALWAYS  0x00000200  // Hysteresis Always
+#define ADC_DCCTL4_CTM_HONCE    0x00000300  // Hysteresis Once
+#define ADC_DCCTL4_CIE          0x00000010  // Comparison Interrupt Enable
+#define ADC_DCCTL4_CIC_M        0x0000000C  // Comparison Interrupt Condition
+#define ADC_DCCTL4_CIC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL4_CIC_MID      0x00000004  // Mid Band
+#define ADC_DCCTL4_CIC_HIGH     0x0000000C  // High Band
+#define ADC_DCCTL4_CIM_M        0x00000003  // Comparison Interrupt Mode
+#define ADC_DCCTL4_CIM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL4_CIM_ONCE     0x00000001  // Once
+#define ADC_DCCTL4_CIM_HALWAYS  0x00000002  // Hysteresis Always
+#define ADC_DCCTL4_CIM_HONCE    0x00000003  // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL5 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL5_CTE          0x00001000  // Comparison Trigger Enable
+#define ADC_DCCTL5_CTC_M        0x00000C00  // Comparison Trigger Condition
+#define ADC_DCCTL5_CTC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL5_CTC_MID      0x00000400  // Mid Band
+#define ADC_DCCTL5_CTC_HIGH     0x00000C00  // High Band
+#define ADC_DCCTL5_CTM_M        0x00000300  // Comparison Trigger Mode
+#define ADC_DCCTL5_CTM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL5_CTM_ONCE     0x00000100  // Once
+#define ADC_DCCTL5_CTM_HALWAYS  0x00000200  // Hysteresis Always
+#define ADC_DCCTL5_CTM_HONCE    0x00000300  // Hysteresis Once
+#define ADC_DCCTL5_CIE          0x00000010  // Comparison Interrupt Enable
+#define ADC_DCCTL5_CIC_M        0x0000000C  // Comparison Interrupt Condition
+#define ADC_DCCTL5_CIC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL5_CIC_MID      0x00000004  // Mid Band
+#define ADC_DCCTL5_CIC_HIGH     0x0000000C  // High Band
+#define ADC_DCCTL5_CIM_M        0x00000003  // Comparison Interrupt Mode
+#define ADC_DCCTL5_CIM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL5_CIM_ONCE     0x00000001  // Once
+#define ADC_DCCTL5_CIM_HALWAYS  0x00000002  // Hysteresis Always
+#define ADC_DCCTL5_CIM_HONCE    0x00000003  // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL6 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL6_CTE          0x00001000  // Comparison Trigger Enable
+#define ADC_DCCTL6_CTC_M        0x00000C00  // Comparison Trigger Condition
+#define ADC_DCCTL6_CTC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL6_CTC_MID      0x00000400  // Mid Band
+#define ADC_DCCTL6_CTC_HIGH     0x00000C00  // High Band
+#define ADC_DCCTL6_CTM_M        0x00000300  // Comparison Trigger Mode
+#define ADC_DCCTL6_CTM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL6_CTM_ONCE     0x00000100  // Once
+#define ADC_DCCTL6_CTM_HALWAYS  0x00000200  // Hysteresis Always
+#define ADC_DCCTL6_CTM_HONCE    0x00000300  // Hysteresis Once
+#define ADC_DCCTL6_CIE          0x00000010  // Comparison Interrupt Enable
+#define ADC_DCCTL6_CIC_M        0x0000000C  // Comparison Interrupt Condition
+#define ADC_DCCTL6_CIC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL6_CIC_MID      0x00000004  // Mid Band
+#define ADC_DCCTL6_CIC_HIGH     0x0000000C  // High Band
+#define ADC_DCCTL6_CIM_M        0x00000003  // Comparison Interrupt Mode
+#define ADC_DCCTL6_CIM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL6_CIM_ONCE     0x00000001  // Once
+#define ADC_DCCTL6_CIM_HALWAYS  0x00000002  // Hysteresis Always
+#define ADC_DCCTL6_CIM_HONCE    0x00000003  // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL7 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL7_CTE          0x00001000  // Comparison Trigger Enable
+#define ADC_DCCTL7_CTC_M        0x00000C00  // Comparison Trigger Condition
+#define ADC_DCCTL7_CTC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL7_CTC_MID      0x00000400  // Mid Band
+#define ADC_DCCTL7_CTC_HIGH     0x00000C00  // High Band
+#define ADC_DCCTL7_CTM_M        0x00000300  // Comparison Trigger Mode
+#define ADC_DCCTL7_CTM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL7_CTM_ONCE     0x00000100  // Once
+#define ADC_DCCTL7_CTM_HALWAYS  0x00000200  // Hysteresis Always
+#define ADC_DCCTL7_CTM_HONCE    0x00000300  // Hysteresis Once
+#define ADC_DCCTL7_CIE          0x00000010  // Comparison Interrupt Enable
+#define ADC_DCCTL7_CIC_M        0x0000000C  // Comparison Interrupt Condition
+#define ADC_DCCTL7_CIC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL7_CIC_MID      0x00000004  // Mid Band
+#define ADC_DCCTL7_CIC_HIGH     0x0000000C  // High Band
+#define ADC_DCCTL7_CIM_M        0x00000003  // Comparison Interrupt Mode
+#define ADC_DCCTL7_CIM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL7_CIM_ONCE     0x00000001  // Once
+#define ADC_DCCTL7_CIM_HALWAYS  0x00000002  // Hysteresis Always
+#define ADC_DCCTL7_CIM_HONCE    0x00000003  // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP0 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP0_COMP1_M      0x0FFF0000  // Compare 1
+#define ADC_DCCMP0_COMP0_M      0x00000FFF  // Compare 0
+#define ADC_DCCMP0_COMP1_S      16
+#define ADC_DCCMP0_COMP0_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP1 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP1_COMP1_M      0x0FFF0000  // Compare 1
+#define ADC_DCCMP1_COMP0_M      0x00000FFF  // Compare 0
+#define ADC_DCCMP1_COMP1_S      16
+#define ADC_DCCMP1_COMP0_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP2 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP2_COMP1_M      0x0FFF0000  // Compare 1
+#define ADC_DCCMP2_COMP0_M      0x00000FFF  // Compare 0
+#define ADC_DCCMP2_COMP1_S      16
+#define ADC_DCCMP2_COMP0_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP3 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP3_COMP1_M      0x0FFF0000  // Compare 1
+#define ADC_DCCMP3_COMP0_M      0x00000FFF  // Compare 0
+#define ADC_DCCMP3_COMP1_S      16
+#define ADC_DCCMP3_COMP0_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP4 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP4_COMP1_M      0x0FFF0000  // Compare 1
+#define ADC_DCCMP4_COMP0_M      0x00000FFF  // Compare 0
+#define ADC_DCCMP4_COMP1_S      16
+#define ADC_DCCMP4_COMP0_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP5 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP5_COMP1_M      0x0FFF0000  // Compare 1
+#define ADC_DCCMP5_COMP0_M      0x00000FFF  // Compare 0
+#define ADC_DCCMP5_COMP1_S      16
+#define ADC_DCCMP5_COMP0_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP6 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP6_COMP1_M      0x0FFF0000  // Compare 1
+#define ADC_DCCMP6_COMP0_M      0x00000FFF  // Compare 0
+#define ADC_DCCMP6_COMP1_S      16
+#define ADC_DCCMP6_COMP0_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP7 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP7_COMP1_M      0x0FFF0000  // Compare 1
+#define ADC_DCCMP7_COMP0_M      0x00000FFF  // Compare 0
+#define ADC_DCCMP7_COMP1_S      16
+#define ADC_DCCMP7_COMP0_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACMIS register.
+//
+//*****************************************************************************
+#define COMP_ACMIS_IN2          0x00000004  // Comparator 2 Masked Interrupt
+                                            // Status
+#define COMP_ACMIS_IN1          0x00000002  // Comparator 1 Masked Interrupt
+                                            // Status
+#define COMP_ACMIS_IN0          0x00000001  // Comparator 0 Masked Interrupt
+                                            // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACRIS register.
+//
+//*****************************************************************************
+#define COMP_ACRIS_IN2          0x00000004  // Comparator 2 Interrupt Status
+#define COMP_ACRIS_IN1          0x00000002  // Comparator 1 Interrupt Status
+#define COMP_ACRIS_IN0          0x00000001  // Comparator 0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACINTEN register.
+//
+//*****************************************************************************
+#define COMP_ACINTEN_IN2        0x00000004  // Comparator 2 Interrupt Enable
+#define COMP_ACINTEN_IN1        0x00000002  // Comparator 1 Interrupt Enable
+#define COMP_ACINTEN_IN0        0x00000001  // Comparator 0 Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACREFCTL
+// register.
+//
+//*****************************************************************************
+#define COMP_ACREFCTL_EN        0x00000200  // Resistor Ladder Enable
+#define COMP_ACREFCTL_RNG       0x00000100  // Resistor Ladder Range
+#define COMP_ACREFCTL_VREF_M    0x0000000F  // Resistor Ladder Voltage Ref
+#define COMP_ACREFCTL_VREF_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACSTAT0 register.
+//
+//*****************************************************************************
+#define COMP_ACSTAT0_OVAL       0x00000002  // Comparator Output Value
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACCTL0 register.
+//
+//*****************************************************************************
+#define COMP_ACCTL0_TOEN        0x00000800  // Trigger Output Enable
+#define COMP_ACCTL0_ASRCP_M     0x00000600  // Analog Source Positive
+#define COMP_ACCTL0_ASRCP_PIN   0x00000000  // Pin value of Cn+
+#define COMP_ACCTL0_ASRCP_PIN0  0x00000200  // Pin value of C0+
+#define COMP_ACCTL0_ASRCP_REF   0x00000400  // Internal voltage reference
+                                            // (VIREF)
+#define COMP_ACCTL0_TSLVAL      0x00000080  // Trigger Sense Level Value
+#define COMP_ACCTL0_TSEN_M      0x00000060  // Trigger Sense
+#define COMP_ACCTL0_TSEN_LEVEL  0x00000000  // Level sense, see TSLVAL
+#define COMP_ACCTL0_TSEN_FALL   0x00000020  // Falling edge
+#define COMP_ACCTL0_TSEN_RISE   0x00000040  // Rising edge
+#define COMP_ACCTL0_TSEN_BOTH   0x00000060  // Either edge
+#define COMP_ACCTL0_ISLVAL      0x00000010  // Interrupt Sense Level Value
+#define COMP_ACCTL0_ISEN_M      0x0000000C  // Interrupt Sense
+#define COMP_ACCTL0_ISEN_LEVEL  0x00000000  // Level sense, see ISLVAL
+#define COMP_ACCTL0_ISEN_FALL   0x00000004  // Falling edge
+#define COMP_ACCTL0_ISEN_RISE   0x00000008  // Rising edge
+#define COMP_ACCTL0_ISEN_BOTH   0x0000000C  // Either edge
+#define COMP_ACCTL0_CINV        0x00000002  // Comparator Output Invert
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACSTAT1 register.
+//
+//*****************************************************************************
+#define COMP_ACSTAT1_OVAL       0x00000002  // Comparator Output Value
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACCTL1 register.
+//
+//*****************************************************************************
+#define COMP_ACCTL1_TOEN        0x00000800  // Trigger Output Enable
+#define COMP_ACCTL1_ASRCP_M     0x00000600  // Analog Source Positive
+#define COMP_ACCTL1_ASRCP_PIN   0x00000000  // Pin value of Cn+
+#define COMP_ACCTL1_ASRCP_PIN0  0x00000200  // Pin value of C0+
+#define COMP_ACCTL1_ASRCP_REF   0x00000400  // Internal voltage reference
+                                            // (VIREF)
+#define COMP_ACCTL1_TSLVAL      0x00000080  // Trigger Sense Level Value
+#define COMP_ACCTL1_TSEN_M      0x00000060  // Trigger Sense
+#define COMP_ACCTL1_TSEN_LEVEL  0x00000000  // Level sense, see TSLVAL
+#define COMP_ACCTL1_TSEN_FALL   0x00000020  // Falling edge
+#define COMP_ACCTL1_TSEN_RISE   0x00000040  // Rising edge
+#define COMP_ACCTL1_TSEN_BOTH   0x00000060  // Either edge
+#define COMP_ACCTL1_ISLVAL      0x00000010  // Interrupt Sense Level Value
+#define COMP_ACCTL1_ISEN_M      0x0000000C  // Interrupt Sense
+#define COMP_ACCTL1_ISEN_LEVEL  0x00000000  // Level sense, see ISLVAL
+#define COMP_ACCTL1_ISEN_FALL   0x00000004  // Falling edge
+#define COMP_ACCTL1_ISEN_RISE   0x00000008  // Rising edge
+#define COMP_ACCTL1_ISEN_BOTH   0x0000000C  // Either edge
+#define COMP_ACCTL1_CINV        0x00000002  // Comparator Output Invert
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACSTAT2 register.
+//
+//*****************************************************************************
+#define COMP_ACSTAT2_OVAL       0x00000002  // Comparator Output Value
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACCTL2 register.
+//
+//*****************************************************************************
+#define COMP_ACCTL2_TOEN        0x00000800  // Trigger Output Enable
+#define COMP_ACCTL2_ASRCP_M     0x00000600  // Analog Source Positive
+#define COMP_ACCTL2_ASRCP_PIN   0x00000000  // Pin value of Cn+
+#define COMP_ACCTL2_ASRCP_PIN0  0x00000200  // Pin value of C0+
+#define COMP_ACCTL2_ASRCP_REF   0x00000400  // Internal voltage reference
+                                            // (VIREF)
+#define COMP_ACCTL2_TSLVAL      0x00000080  // Trigger Sense Level Value
+#define COMP_ACCTL2_TSEN_M      0x00000060  // Trigger Sense
+#define COMP_ACCTL2_TSEN_LEVEL  0x00000000  // Level sense, see TSLVAL
+#define COMP_ACCTL2_TSEN_FALL   0x00000020  // Falling edge
+#define COMP_ACCTL2_TSEN_RISE   0x00000040  // Rising edge
+#define COMP_ACCTL2_TSEN_BOTH   0x00000060  // Either edge
+#define COMP_ACCTL2_ISLVAL      0x00000010  // Interrupt Sense Level Value
+#define COMP_ACCTL2_ISEN_M      0x0000000C  // Interrupt Sense
+#define COMP_ACCTL2_ISEN_LEVEL  0x00000000  // Level sense, see ISLVAL
+#define COMP_ACCTL2_ISEN_FALL   0x00000004  // Falling edge
+#define COMP_ACCTL2_ISEN_RISE   0x00000008  // Rising edge
+#define COMP_ACCTL2_ISEN_BOTH   0x0000000C  // Either edge
+#define COMP_ACCTL2_CINV        0x00000002  // Comparator Output Invert
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_CTL register.
+//
+//*****************************************************************************
+#define CAN_CTL_TEST            0x00000080  // Test Mode Enable
+#define CAN_CTL_CCE             0x00000040  // Configuration Change Enable
+#define CAN_CTL_DAR             0x00000020  // Disable Automatic-Retransmission
+#define CAN_CTL_EIE             0x00000008  // Error Interrupt Enable
+#define CAN_CTL_SIE             0x00000004  // Status Interrupt Enable
+#define CAN_CTL_IE              0x00000002  // CAN Interrupt Enable
+#define CAN_CTL_INIT            0x00000001  // Initialization
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_STS register.
+//
+//*****************************************************************************
+#define CAN_STS_BOFF            0x00000080  // Bus-Off Status
+#define CAN_STS_EWARN           0x00000040  // Warning Status
+#define CAN_STS_EPASS           0x00000020  // Error Passive
+#define CAN_STS_RXOK            0x00000010  // Received a Message Successfully
+#define CAN_STS_TXOK            0x00000008  // Transmitted a Message
+                                            // Successfully
+#define CAN_STS_LEC_M           0x00000007  // Last Error Code
+#define CAN_STS_LEC_NONE        0x00000000  // No Error
+#define CAN_STS_LEC_STUFF       0x00000001  // Stuff Error
+#define CAN_STS_LEC_FORM        0x00000002  // Format Error
+#define CAN_STS_LEC_ACK         0x00000003  // ACK Error
+#define CAN_STS_LEC_BIT1        0x00000004  // Bit 1 Error
+#define CAN_STS_LEC_BIT0        0x00000005  // Bit 0 Error
+#define CAN_STS_LEC_CRC         0x00000006  // CRC Error
+#define CAN_STS_LEC_NOEVENT     0x00000007  // No Event
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_ERR register.
+//
+//*****************************************************************************
+#define CAN_ERR_RP              0x00008000  // Received Error Passive
+#define CAN_ERR_REC_M           0x00007F00  // Receive Error Counter
+#define CAN_ERR_TEC_M           0x000000FF  // Transmit Error Counter
+#define CAN_ERR_REC_S           8
+#define CAN_ERR_TEC_S           0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_BIT register.
+//
+//*****************************************************************************
+#define CAN_BIT_TSEG2_M         0x00007000  // Time Segment after Sample Point
+#define CAN_BIT_TSEG1_M         0x00000F00  // Time Segment Before Sample Point
+#define CAN_BIT_SJW_M           0x000000C0  // (Re)Synchronization Jump Width
+#define CAN_BIT_BRP_M           0x0000003F  // Baud Rate Prescaler
+#define CAN_BIT_TSEG2_S         12
+#define CAN_BIT_TSEG1_S         8
+#define CAN_BIT_SJW_S           6
+#define CAN_BIT_BRP_S           0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_INT register.
+//
+//*****************************************************************************
+#define CAN_INT_INTID_M         0x0000FFFF  // Interrupt Identifier
+#define CAN_INT_INTID_NONE      0x00000000  // No interrupt pending
+#define CAN_INT_INTID_STATUS    0x00008000  // Status Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_TST register.
+//
+//*****************************************************************************
+#define CAN_TST_RX              0x00000080  // Receive Observation
+#define CAN_TST_TX_M            0x00000060  // Transmit Control
+#define CAN_TST_TX_CANCTL       0x00000000  // CAN Module Control
+#define CAN_TST_TX_SAMPLE       0x00000020  // Sample Point
+#define CAN_TST_TX_DOMINANT     0x00000040  // Driven Low
+#define CAN_TST_TX_RECESSIVE    0x00000060  // Driven High
+#define CAN_TST_LBACK           0x00000010  // Loopback Mode
+#define CAN_TST_SILENT          0x00000008  // Silent Mode
+#define CAN_TST_BASIC           0x00000004  // Basic Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_BRPE register.
+//
+//*****************************************************************************
+#define CAN_BRPE_BRPE_M         0x0000000F  // Baud Rate Prescaler Extension
+#define CAN_BRPE_BRPE_S         0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1CRQ register.
+//
+//*****************************************************************************
+#define CAN_IF1CRQ_BUSY         0x00008000  // Busy Flag
+#define CAN_IF1CRQ_MNUM_M       0x0000003F  // Message Number
+#define CAN_IF1CRQ_MNUM_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1CMSK register.
+//
+//*****************************************************************************
+#define CAN_IF1CMSK_WRNRD       0x00000080  // Write, Not Read
+#define CAN_IF1CMSK_MASK        0x00000040  // Access Mask Bits
+#define CAN_IF1CMSK_ARB         0x00000020  // Access Arbitration Bits
+#define CAN_IF1CMSK_CONTROL     0x00000010  // Access Control Bits
+#define CAN_IF1CMSK_CLRINTPND   0x00000008  // Clear Interrupt Pending Bit
+#define CAN_IF1CMSK_NEWDAT      0x00000004  // Access New Data
+#define CAN_IF1CMSK_TXRQST      0x00000004  // Access Transmission Request
+#define CAN_IF1CMSK_DATAA       0x00000002  // Access Data Byte 0 to 3
+#define CAN_IF1CMSK_DATAB       0x00000001  // Access Data Byte 4 to 7
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1MSK1 register.
+//
+//*****************************************************************************
+#define CAN_IF1MSK1_IDMSK_M     0x0000FFFF  // Identifier Mask
+#define CAN_IF1MSK1_IDMSK_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1MSK2 register.
+//
+//*****************************************************************************
+#define CAN_IF1MSK2_MXTD        0x00008000  // Mask Extended Identifier
+#define CAN_IF1MSK2_MDIR        0x00004000  // Mask Message Direction
+#define CAN_IF1MSK2_IDMSK_M     0x00001FFF  // Identifier Mask
+#define CAN_IF1MSK2_IDMSK_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1ARB1 register.
+//
+//*****************************************************************************
+#define CAN_IF1ARB1_ID_M        0x0000FFFF  // Message Identifier
+#define CAN_IF1ARB1_ID_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1ARB2 register.
+//
+//*****************************************************************************
+#define CAN_IF1ARB2_MSGVAL      0x00008000  // Message Valid
+#define CAN_IF1ARB2_XTD         0x00004000  // Extended Identifier
+#define CAN_IF1ARB2_DIR         0x00002000  // Message Direction
+#define CAN_IF1ARB2_ID_M        0x00001FFF  // Message Identifier
+#define CAN_IF1ARB2_ID_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1MCTL register.
+//
+//*****************************************************************************
+#define CAN_IF1MCTL_NEWDAT      0x00008000  // New Data
+#define CAN_IF1MCTL_MSGLST      0x00004000  // Message Lost
+#define CAN_IF1MCTL_INTPND      0x00002000  // Interrupt Pending
+#define CAN_IF1MCTL_UMASK       0x00001000  // Use Acceptance Mask
+#define CAN_IF1MCTL_TXIE        0x00000800  // Transmit Interrupt Enable
+#define CAN_IF1MCTL_RXIE        0x00000400  // Receive Interrupt Enable
+#define CAN_IF1MCTL_RMTEN       0x00000200  // Remote Enable
+#define CAN_IF1MCTL_TXRQST      0x00000100  // Transmit Request
+#define CAN_IF1MCTL_EOB         0x00000080  // End of Buffer
+#define CAN_IF1MCTL_DLC_M       0x0000000F  // Data Length Code
+#define CAN_IF1MCTL_DLC_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1DA1 register.
+//
+//*****************************************************************************
+#define CAN_IF1DA1_DATA_M       0x0000FFFF  // Data
+#define CAN_IF1DA1_DATA_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1DA2 register.
+//
+//*****************************************************************************
+#define CAN_IF1DA2_DATA_M       0x0000FFFF  // Data
+#define CAN_IF1DA2_DATA_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1DB1 register.
+//
+//*****************************************************************************
+#define CAN_IF1DB1_DATA_M       0x0000FFFF  // Data
+#define CAN_IF1DB1_DATA_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1DB2 register.
+//
+//*****************************************************************************
+#define CAN_IF1DB2_DATA_M       0x0000FFFF  // Data
+#define CAN_IF1DB2_DATA_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2CRQ register.
+//
+//*****************************************************************************
+#define CAN_IF2CRQ_BUSY         0x00008000  // Busy Flag
+#define CAN_IF2CRQ_MNUM_M       0x0000003F  // Message Number
+#define CAN_IF2CRQ_MNUM_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2CMSK register.
+//
+//*****************************************************************************
+#define CAN_IF2CMSK_WRNRD       0x00000080  // Write, Not Read
+#define CAN_IF2CMSK_MASK        0x00000040  // Access Mask Bits
+#define CAN_IF2CMSK_ARB         0x00000020  // Access Arbitration Bits
+#define CAN_IF2CMSK_CONTROL     0x00000010  // Access Control Bits
+#define CAN_IF2CMSK_CLRINTPND   0x00000008  // Clear Interrupt Pending Bit
+#define CAN_IF2CMSK_NEWDAT      0x00000004  // Access New Data
+#define CAN_IF2CMSK_TXRQST      0x00000004  // Access Transmission Request
+#define CAN_IF2CMSK_DATAA       0x00000002  // Access Data Byte 0 to 3
+#define CAN_IF2CMSK_DATAB       0x00000001  // Access Data Byte 4 to 7
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2MSK1 register.
+//
+//*****************************************************************************
+#define CAN_IF2MSK1_IDMSK_M     0x0000FFFF  // Identifier Mask
+#define CAN_IF2MSK1_IDMSK_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2MSK2 register.
+//
+//*****************************************************************************
+#define CAN_IF2MSK2_MXTD        0x00008000  // Mask Extended Identifier
+#define CAN_IF2MSK2_MDIR        0x00004000  // Mask Message Direction
+#define CAN_IF2MSK2_IDMSK_M     0x00001FFF  // Identifier Mask
+#define CAN_IF2MSK2_IDMSK_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2ARB1 register.
+//
+//*****************************************************************************
+#define CAN_IF2ARB1_ID_M        0x0000FFFF  // Message Identifier
+#define CAN_IF2ARB1_ID_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2ARB2 register.
+//
+//*****************************************************************************
+#define CAN_IF2ARB2_MSGVAL      0x00008000  // Message Valid
+#define CAN_IF2ARB2_XTD         0x00004000  // Extended Identifier
+#define CAN_IF2ARB2_DIR         0x00002000  // Message Direction
+#define CAN_IF2ARB2_ID_M        0x00001FFF  // Message Identifier
+#define CAN_IF2ARB2_ID_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2MCTL register.
+//
+//*****************************************************************************
+#define CAN_IF2MCTL_NEWDAT      0x00008000  // New Data
+#define CAN_IF2MCTL_MSGLST      0x00004000  // Message Lost
+#define CAN_IF2MCTL_INTPND      0x00002000  // Interrupt Pending
+#define CAN_IF2MCTL_UMASK       0x00001000  // Use Acceptance Mask
+#define CAN_IF2MCTL_TXIE        0x00000800  // Transmit Interrupt Enable
+#define CAN_IF2MCTL_RXIE        0x00000400  // Receive Interrupt Enable
+#define CAN_IF2MCTL_RMTEN       0x00000200  // Remote Enable
+#define CAN_IF2MCTL_TXRQST      0x00000100  // Transmit Request
+#define CAN_IF2MCTL_EOB         0x00000080  // End of Buffer
+#define CAN_IF2MCTL_DLC_M       0x0000000F  // Data Length Code
+#define CAN_IF2MCTL_DLC_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2DA1 register.
+//
+//*****************************************************************************
+#define CAN_IF2DA1_DATA_M       0x0000FFFF  // Data
+#define CAN_IF2DA1_DATA_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2DA2 register.
+//
+//*****************************************************************************
+#define CAN_IF2DA2_DATA_M       0x0000FFFF  // Data
+#define CAN_IF2DA2_DATA_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2DB1 register.
+//
+//*****************************************************************************
+#define CAN_IF2DB1_DATA_M       0x0000FFFF  // Data
+#define CAN_IF2DB1_DATA_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2DB2 register.
+//
+//*****************************************************************************
+#define CAN_IF2DB2_DATA_M       0x0000FFFF  // Data
+#define CAN_IF2DB2_DATA_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_TXRQ1 register.
+//
+//*****************************************************************************
+#define CAN_TXRQ1_TXRQST_M      0x0000FFFF  // Transmission Request Bits
+#define CAN_TXRQ1_TXRQST_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_TXRQ2 register.
+//
+//*****************************************************************************
+#define CAN_TXRQ2_TXRQST_M      0x0000FFFF  // Transmission Request Bits
+#define CAN_TXRQ2_TXRQST_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_NWDA1 register.
+//
+//*****************************************************************************
+#define CAN_NWDA1_NEWDAT_M      0x0000FFFF  // New Data Bits
+#define CAN_NWDA1_NEWDAT_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_NWDA2 register.
+//
+//*****************************************************************************
+#define CAN_NWDA2_NEWDAT_M      0x0000FFFF  // New Data Bits
+#define CAN_NWDA2_NEWDAT_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_MSG1INT register.
+//
+//*****************************************************************************
+#define CAN_MSG1INT_INTPND_M    0x0000FFFF  // Interrupt Pending Bits
+#define CAN_MSG1INT_INTPND_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_MSG2INT register.
+//
+//*****************************************************************************
+#define CAN_MSG2INT_INTPND_M    0x0000FFFF  // Interrupt Pending Bits
+#define CAN_MSG2INT_INTPND_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_MSG1VAL register.
+//
+//*****************************************************************************
+#define CAN_MSG1VAL_MSGVAL_M    0x0000FFFF  // Message Valid Bits
+#define CAN_MSG1VAL_MSGVAL_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_MSG2VAL register.
+//
+//*****************************************************************************
+#define CAN_MSG2VAL_MSGVAL_M    0x0000FFFF  // Message Valid Bits
+#define CAN_MSG2VAL_MSGVAL_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_RIS register.
+//
+//*****************************************************************************
+#define MAC_RIS_PHYINT          0x00000040  // PHY Interrupt
+#define MAC_RIS_MDINT           0x00000020  // MII Transaction Complete
+#define MAC_RIS_RXER            0x00000010  // Receive Error
+#define MAC_RIS_FOV             0x00000008  // FIFO Overrun
+#define MAC_RIS_TXEMP           0x00000004  // Transmit FIFO Empty
+#define MAC_RIS_TXER            0x00000002  // Transmit Error
+#define MAC_RIS_RXINT           0x00000001  // Packet Received
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_IM register.
+//
+//*****************************************************************************
+#define MAC_IM_PHYINTM          0x00000040  // Mask PHY Interrupt
+#define MAC_IM_MDINTM           0x00000020  // Mask MII Transaction Complete
+#define MAC_IM_RXERM            0x00000010  // Mask Receive Error
+#define MAC_IM_FOVM             0x00000008  // Mask FIFO Overrun
+#define MAC_IM_TXEMPM           0x00000004  // Mask Transmit FIFO Empty
+#define MAC_IM_TXERM            0x00000002  // Mask Transmit Error
+#define MAC_IM_RXINTM           0x00000001  // Mask Packet Received
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_RCTL register.
+//
+//*****************************************************************************
+#define MAC_RCTL_RSTFIFO        0x00000010  // Clear Receive FIFO
+#define MAC_RCTL_BADCRC         0x00000008  // Enable Reject Bad CRC
+#define MAC_RCTL_PRMS           0x00000004  // Enable Promiscuous Mode
+#define MAC_RCTL_AMUL           0x00000002  // Enable Multicast Frames
+#define MAC_RCTL_RXEN           0x00000001  // Enable Receiver
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_TCTL register.
+//
+//*****************************************************************************
+#define MAC_TCTL_DUPLEX         0x00000010  // Enable Duplex Mode
+#define MAC_TCTL_CRC            0x00000004  // Enable CRC Generation
+#define MAC_TCTL_PADEN          0x00000002  // Enable Packet Padding
+#define MAC_TCTL_TXEN           0x00000001  // Enable Transmitter
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_DATA register.
+//
+//*****************************************************************************
+#define MAC_DATA_TXDATA_M       0xFFFFFFFF  // Transmit FIFO Data
+#define MAC_DATA_RXDATA_M       0xFFFFFFFF  // Receive FIFO Data
+#define MAC_DATA_RXDATA_S       0
+#define MAC_DATA_TXDATA_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_IA0 register.
+//
+//*****************************************************************************
+#define MAC_IA0_MACOCT4_M       0xFF000000  // MAC Address Octet 4
+#define MAC_IA0_MACOCT3_M       0x00FF0000  // MAC Address Octet 3
+#define MAC_IA0_MACOCT2_M       0x0000FF00  // MAC Address Octet 2
+#define MAC_IA0_MACOCT1_M       0x000000FF  // MAC Address Octet 1
+#define MAC_IA0_MACOCT4_S       24
+#define MAC_IA0_MACOCT3_S       16
+#define MAC_IA0_MACOCT2_S       8
+#define MAC_IA0_MACOCT1_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_IA1 register.
+//
+//*****************************************************************************
+#define MAC_IA1_MACOCT6_M       0x0000FF00  // MAC Address Octet 6
+#define MAC_IA1_MACOCT5_M       0x000000FF  // MAC Address Octet 5
+#define MAC_IA1_MACOCT6_S       8
+#define MAC_IA1_MACOCT5_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_THR register.
+//
+//*****************************************************************************
+#define MAC_THR_THRESH_M        0x0000003F  // Threshold Value
+#define MAC_THR_THRESH_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MCTL register.
+//
+//*****************************************************************************
+#define MAC_MCTL_REGADR_M       0x000000F8  // MII Register Address
+#define MAC_MCTL_WRITE          0x00000002  // MII Register Transaction Type
+#define MAC_MCTL_START          0x00000001  // MII Register Transaction Enable
+#define MAC_MCTL_REGADR_S       3
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MDV register.
+//
+//*****************************************************************************
+#define MAC_MDV_DIV_M           0x000000FF  // Clock Divider
+#define MAC_MDV_DIV_S           0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MTXD register.
+//
+//*****************************************************************************
+#define MAC_MTXD_MDTX_M         0x0000FFFF  // MII Register Transmit Data
+#define MAC_MTXD_MDTX_S         0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MRXD register.
+//
+//*****************************************************************************
+#define MAC_MRXD_MDRX_M         0x0000FFFF  // MII Register Receive Data
+#define MAC_MRXD_MDRX_S         0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_NP register.
+//
+//*****************************************************************************
+#define MAC_NP_NPR_M            0x0000003F  // Number of Packets in Receive
+                                            // FIFO
+#define MAC_NP_NPR_S            0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_TR register.
+//
+//*****************************************************************************
+#define MAC_TR_NEWTX            0x00000001  // New Transmission
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_TS register.
+//
+//*****************************************************************************
+#define MAC_TS_TSEN             0x00000001  // Time Stamp Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_LED register.
+//
+//*****************************************************************************
+#define MAC_LED_LED1_M          0x00000F00  // LED1 Source
+#define MAC_LED_LED1_LINK       0x00000000  // Link OK
+#define MAC_LED_LED1_RXTX       0x00000100  // RX or TX Activity (Default LED1)
+#define MAC_LED_LED1_100        0x00000500  // 100BASE-TX mode
+#define MAC_LED_LED1_10         0x00000600  // 10BASE-T mode
+#define MAC_LED_LED1_DUPLEX     0x00000700  // Full-Duplex
+#define MAC_LED_LED1_LINKACT    0x00000800  // Link OK & Blink=RX or TX
+                                            // Activity
+#define MAC_LED_LED0_M          0x0000000F  // LED0 Source
+#define MAC_LED_LED0_LINK       0x00000000  // Link OK (Default LED0)
+#define MAC_LED_LED0_RXTX       0x00000001  // RX or TX Activity
+#define MAC_LED_LED0_100        0x00000005  // 100BASE-TX mode
+#define MAC_LED_LED0_10         0x00000006  // 10BASE-T mode
+#define MAC_LED_LED0_DUPLEX     0x00000007  // Full-Duplex
+#define MAC_LED_LED0_LINKACT    0x00000008  // Link OK & Blink=RX or TX
+                                            // Activity
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MDIX register.
+//
+//*****************************************************************************
+#define MAC_MDIX_EN             0x00000001  // MDI/MDI-X Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR0 register.
+//
+//*****************************************************************************
+#define PHY_MR0_RESET           0x00008000  // Reset Registers
+#define PHY_MR0_LOOPBK          0x00004000  // Loopback Mode
+#define PHY_MR0_SPEEDSL         0x00002000  // Speed Select
+#define PHY_MR0_ANEGEN          0x00001000  // Auto-Negotiation Enable
+#define PHY_MR0_PWRDN           0x00000800  // Power Down
+#define PHY_MR0_ISO             0x00000400  // Isolate
+#define PHY_MR0_RANEG           0x00000200  // Restart Auto-Negotiation
+#define PHY_MR0_DUPLEX          0x00000100  // Set Duplex Mode
+#define PHY_MR0_COLT            0x00000080  // Collision Test
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR1 register.
+//
+//*****************************************************************************
+#define PHY_MR1_100X_F          0x00004000  // 100BASE-TX Full-Duplex Mode
+#define PHY_MR1_100X_H          0x00002000  // 100BASE-TX Half-Duplex Mode
+#define PHY_MR1_10T_F           0x00001000  // 10BASE-T Full-Duplex Mode
+#define PHY_MR1_10T_H           0x00000800  // 10BASE-T Half-Duplex Mode
+#define PHY_MR1_ANEGC           0x00000020  // Auto-Negotiation Complete
+#define PHY_MR1_RFAULT          0x00000010  // Remote Fault
+#define PHY_MR1_ANEGA           0x00000008  // Auto-Negotiation
+#define PHY_MR1_LINK            0x00000004  // Link Made
+#define PHY_MR1_JAB             0x00000002  // Jabber Condition
+#define PHY_MR1_EXTD            0x00000001  // Extended Capabilities
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR2 register.
+//
+//*****************************************************************************
+#define PHY_MR2_OUI_M           0x0000FFFF  // Organizationally Unique
+                                            // Identifier[21:6]
+#define PHY_MR2_OUI_S           0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR3 register.
+//
+//*****************************************************************************
+#define PHY_MR3_OUI_M           0x0000FC00  // Organizationally Unique
+                                            // Identifier[5:0]
+#define PHY_MR3_MN_M            0x000003F0  // Model Number
+#define PHY_MR3_RN_M            0x0000000F  // Revision Number
+#define PHY_MR3_OUI_S           10
+#define PHY_MR3_MN_S            4
+#define PHY_MR3_RN_S            0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR4 register.
+//
+//*****************************************************************************
+#define PHY_MR4_NP              0x00008000  // Next Page
+#define PHY_MR4_RF              0x00002000  // Remote Fault
+#define PHY_MR4_A3              0x00000100  // Technology Ability Field [3]
+#define PHY_MR4_A2              0x00000080  // Technology Ability Field [2]
+#define PHY_MR4_A1              0x00000040  // Technology Ability Field [1]
+#define PHY_MR4_A0              0x00000020  // Technology Ability Field [0]
+#define PHY_MR4_S_M             0x0000001F  // Selector Field
+#define PHY_MR4_S_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR5 register.
+//
+//*****************************************************************************
+#define PHY_MR5_NP              0x00008000  // Next Page
+#define PHY_MR5_ACK             0x00004000  // Acknowledge
+#define PHY_MR5_RF              0x00002000  // Remote Fault
+#define PHY_MR5_A_M             0x00001FE0  // Technology Ability Field
+#define PHY_MR5_S_M             0x0000001F  // Selector Field
+#define PHY_MR5_S_8023          0x00000001  // IEEE Std 802.3
+#define PHY_MR5_S_8029          0x00000002  // IEEE Std 802.9 ISLAN-16T
+#define PHY_MR5_S_8025          0x00000003  // IEEE Std 802.5
+#define PHY_MR5_S_1394          0x00000004  // IEEE Std 1394
+#define PHY_MR5_A_S             5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR6 register.
+//
+//*****************************************************************************
+#define PHY_MR6_PDF             0x00000010  // Parallel Detection Fault
+#define PHY_MR6_LPNPA           0x00000008  // Link Partner is Next Page Able
+#define PHY_MR6_PRX             0x00000002  // New Page Received
+#define PHY_MR6_LPANEGA         0x00000001  // Link Partner is Auto-Negotiation
+                                            // Able
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR16 register.
+//
+//*****************************************************************************
+#define PHY_MR16_SR_M           0x000003C0  // Silicon Revision Identifier
+#define PHY_MR16_SR_S           6
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR17 register.
+//
+//*****************************************************************************
+#define PHY_MR17_FASTRIP        0x00004000  // 10-BASE-T Fast Mode Enable
+#define PHY_MR17_EDPD           0x00002000  // Enable Energy Detect Power Down
+#define PHY_MR17_LSQE           0x00000800  // Low Squelch Enable
+#define PHY_MR17_FASTEST        0x00000100  // Auto-Negotiation Test Mode
+#define PHY_MR17_FGLS           0x00000004  // Force Good Link Status
+#define PHY_MR17_ENON           0x00000002  // Energy On
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR27 register.
+//
+//*****************************************************************************
+#define PHY_MR27_XPOL           0x00000010  // Polarity State of 10 BASE-T
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR29 register.
+//
+//*****************************************************************************
+#define PHY_MR29_EONIS          0x00000080  // ENERGYON Interrupt
+#define PHY_MR29_ANCOMPIS       0x00000040  // Auto-Negotiation Complete
+                                            // Interrupt
+#define PHY_MR29_RFLTIS         0x00000020  // Remote Fault Interrupt
+#define PHY_MR29_LDIS           0x00000010  // Link Down Interrupt
+#define PHY_MR29_LPACKIS        0x00000008  // Auto-Negotiation LP Acknowledge
+#define PHY_MR29_PDFIS          0x00000004  // Parallel Detection Fault
+#define PHY_MR29_PRXIS          0x00000002  // Auto Negotiation Page Received
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR30 register.
+//
+//*****************************************************************************
+#define PHY_MR30_EONIM          0x00000080  // ENERGYON Interrupt Enabled
+#define PHY_MR30_ANCOMPIM       0x00000040  // Auto-Negotiation Complete
+                                            // Interrupt Enabled
+#define PHY_MR30_RFLTIM         0x00000020  // Remote Fault Interrupt Enabled
+#define PHY_MR30_LDIM           0x00000010  // Link Down Interrupt Enabled
+#define PHY_MR30_LPACKIM        0x00000008  // Auto-Negotiation LP Acknowledge
+                                            // Enabled
+#define PHY_MR30_PDFIM          0x00000004  // Parallel Detection Fault Enabled
+#define PHY_MR30_PRXIM          0x00000002  // Auto Negotiation Page Received
+                                            // Enabled
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR31 register.
+//
+//*****************************************************************************
+#define PHY_MR31_AUTODONE       0x00001000  // Auto Negotiation Done
+#define PHY_MR31_SPEED_M        0x0000001C  // HCD Speed Value
+#define PHY_MR31_SPEED_10HD     0x00000004  // 10BASE-T half duplex
+#define PHY_MR31_SPEED_100HD    0x00000008  // 100BASE-T half duplex
+#define PHY_MR31_SPEED_10FD     0x00000014  // 10BASE-T full duplex
+#define PHY_MR31_SPEED_100FD    0x00000018  // 100BASE-T full duplex
+#define PHY_MR31_SCRDIS         0x00000001  // Scramble Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FADDR register.
+//
+//*****************************************************************************
+#define USB_FADDR_M             0x0000007F  // Function Address
+#define USB_FADDR_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_POWER register.
+//
+//*****************************************************************************
+#define USB_POWER_ISOUP         0x00000080  // Isochronous Update
+#define USB_POWER_SOFTCONN      0x00000040  // Soft Connect/Disconnect
+#define USB_POWER_RESET         0x00000008  // RESET Signaling
+#define USB_POWER_RESUME        0x00000004  // RESUME Signaling
+#define USB_POWER_SUSPEND       0x00000002  // SUSPEND Mode
+#define USB_POWER_PWRDNPHY      0x00000001  // Power Down PHY
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXIS register.
+//
+//*****************************************************************************
+#define USB_TXIS_EP15           0x00008000  // TX Endpoint 15 Interrupt
+#define USB_TXIS_EP14           0x00004000  // TX Endpoint 14 Interrupt
+#define USB_TXIS_EP13           0x00002000  // TX Endpoint 13 Interrupt
+#define USB_TXIS_EP12           0x00001000  // TX Endpoint 12 Interrupt
+#define USB_TXIS_EP11           0x00000800  // TX Endpoint 11 Interrupt
+#define USB_TXIS_EP10           0x00000400  // TX Endpoint 10 Interrupt
+#define USB_TXIS_EP9            0x00000200  // TX Endpoint 9 Interrupt
+#define USB_TXIS_EP8            0x00000100  // TX Endpoint 8 Interrupt
+#define USB_TXIS_EP7            0x00000080  // TX Endpoint 7 Interrupt
+#define USB_TXIS_EP6            0x00000040  // TX Endpoint 6 Interrupt
+#define USB_TXIS_EP5            0x00000020  // TX Endpoint 5 Interrupt
+#define USB_TXIS_EP4            0x00000010  // TX Endpoint 4 Interrupt
+#define USB_TXIS_EP3            0x00000008  // TX Endpoint 3 Interrupt
+#define USB_TXIS_EP2            0x00000004  // TX Endpoint 2 Interrupt
+#define USB_TXIS_EP1            0x00000002  // TX Endpoint 1 Interrupt
+#define USB_TXIS_EP0            0x00000001  // TX and RX Endpoint 0 Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXIS register.
+//
+//*****************************************************************************
+#define USB_RXIS_EP15           0x00008000  // RX Endpoint 15 Interrupt
+#define USB_RXIS_EP14           0x00004000  // RX Endpoint 14 Interrupt
+#define USB_RXIS_EP13           0x00002000  // RX Endpoint 13 Interrupt
+#define USB_RXIS_EP12           0x00001000  // RX Endpoint 12 Interrupt
+#define USB_RXIS_EP11           0x00000800  // RX Endpoint 11 Interrupt
+#define USB_RXIS_EP10           0x00000400  // RX Endpoint 10 Interrupt
+#define USB_RXIS_EP9            0x00000200  // RX Endpoint 9 Interrupt
+#define USB_RXIS_EP8            0x00000100  // RX Endpoint 8 Interrupt
+#define USB_RXIS_EP7            0x00000080  // RX Endpoint 7 Interrupt
+#define USB_RXIS_EP6            0x00000040  // RX Endpoint 6 Interrupt
+#define USB_RXIS_EP5            0x00000020  // RX Endpoint 5 Interrupt
+#define USB_RXIS_EP4            0x00000010  // RX Endpoint 4 Interrupt
+#define USB_RXIS_EP3            0x00000008  // RX Endpoint 3 Interrupt
+#define USB_RXIS_EP2            0x00000004  // RX Endpoint 2 Interrupt
+#define USB_RXIS_EP1            0x00000002  // RX Endpoint 1 Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXIE register.
+//
+//*****************************************************************************
+#define USB_TXIE_EP15           0x00008000  // TX Endpoint 15 Interrupt Enable
+#define USB_TXIE_EP14           0x00004000  // TX Endpoint 14 Interrupt Enable
+#define USB_TXIE_EP13           0x00002000  // TX Endpoint 13 Interrupt Enable
+#define USB_TXIE_EP12           0x00001000  // TX Endpoint 12 Interrupt Enable
+#define USB_TXIE_EP11           0x00000800  // TX Endpoint 11 Interrupt Enable
+#define USB_TXIE_EP10           0x00000400  // TX Endpoint 10 Interrupt Enable
+#define USB_TXIE_EP9            0x00000200  // TX Endpoint 9 Interrupt Enable
+#define USB_TXIE_EP8            0x00000100  // TX Endpoint 8 Interrupt Enable
+#define USB_TXIE_EP7            0x00000080  // TX Endpoint 7 Interrupt Enable
+#define USB_TXIE_EP6            0x00000040  // TX Endpoint 6 Interrupt Enable
+#define USB_TXIE_EP5            0x00000020  // TX Endpoint 5 Interrupt Enable
+#define USB_TXIE_EP4            0x00000010  // TX Endpoint 4 Interrupt Enable
+#define USB_TXIE_EP3            0x00000008  // TX Endpoint 3 Interrupt Enable
+#define USB_TXIE_EP2            0x00000004  // TX Endpoint 2 Interrupt Enable
+#define USB_TXIE_EP1            0x00000002  // TX Endpoint 1 Interrupt Enable
+#define USB_TXIE_EP0            0x00000001  // TX and RX Endpoint 0 Interrupt
+                                            // Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXIE register.
+//
+//*****************************************************************************
+#define USB_RXIE_EP15           0x00008000  // RX Endpoint 15 Interrupt Enable
+#define USB_RXIE_EP14           0x00004000  // RX Endpoint 14 Interrupt Enable
+#define USB_RXIE_EP13           0x00002000  // RX Endpoint 13 Interrupt Enable
+#define USB_RXIE_EP12           0x00001000  // RX Endpoint 12 Interrupt Enable
+#define USB_RXIE_EP11           0x00000800  // RX Endpoint 11 Interrupt Enable
+#define USB_RXIE_EP10           0x00000400  // RX Endpoint 10 Interrupt Enable
+#define USB_RXIE_EP9            0x00000200  // RX Endpoint 9 Interrupt Enable
+#define USB_RXIE_EP8            0x00000100  // RX Endpoint 8 Interrupt Enable
+#define USB_RXIE_EP7            0x00000080  // RX Endpoint 7 Interrupt Enable
+#define USB_RXIE_EP6            0x00000040  // RX Endpoint 6 Interrupt Enable
+#define USB_RXIE_EP5            0x00000020  // RX Endpoint 5 Interrupt Enable
+#define USB_RXIE_EP4            0x00000010  // RX Endpoint 4 Interrupt Enable
+#define USB_RXIE_EP3            0x00000008  // RX Endpoint 3 Interrupt Enable
+#define USB_RXIE_EP2            0x00000004  // RX Endpoint 2 Interrupt Enable
+#define USB_RXIE_EP1            0x00000002  // RX Endpoint 1 Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_IS register.
+//
+//*****************************************************************************
+#define USB_IS_VBUSERR          0x00000080  // VBUS Error
+#define USB_IS_SESREQ           0x00000040  // SESSION REQUEST
+#define USB_IS_DISCON           0x00000020  // Session Disconnect
+#define USB_IS_CONN             0x00000010  // Session Connect
+#define USB_IS_SOF              0x00000008  // Start of Frame
+#define USB_IS_BABBLE           0x00000004  // Babble Detected
+#define USB_IS_RESET            0x00000004  // RESET Signaling Detected
+#define USB_IS_RESUME           0x00000002  // RESUME Signaling Detected
+#define USB_IS_SUSPEND          0x00000001  // SUSPEND Signaling Detected
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_IE register.
+//
+//*****************************************************************************
+#define USB_IE_VBUSERR          0x00000080  // Enable VBUS Error Interrupt
+#define USB_IE_SESREQ           0x00000040  // Enable Session Request
+#define USB_IE_DISCON           0x00000020  // Enable Disconnect Interrupt
+#define USB_IE_CONN             0x00000010  // Enable Connect Interrupt
+#define USB_IE_SOF              0x00000008  // Enable Start-of-Frame Interrupt
+#define USB_IE_BABBLE           0x00000004  // Enable Babble Interrupt
+#define USB_IE_RESET            0x00000004  // Enable RESET Interrupt
+#define USB_IE_RESUME           0x00000002  // Enable RESUME Interrupt
+#define USB_IE_SUSPND           0x00000001  // Enable SUSPEND Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FRAME register.
+//
+//*****************************************************************************
+#define USB_FRAME_M             0x000007FF  // Frame Number
+#define USB_FRAME_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPIDX register.
+//
+//*****************************************************************************
+#define USB_EPIDX_EPIDX_M       0x0000000F  // Endpoint Index
+#define USB_EPIDX_EPIDX_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TEST register.
+//
+//*****************************************************************************
+#define USB_TEST_FORCEH         0x00000080  // Force Host Mode
+#define USB_TEST_FIFOACC        0x00000040  // FIFO Access
+#define USB_TEST_FORCEFS        0x00000020  // Force Full-Speed Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO0 register.
+//
+//*****************************************************************************
+#define USB_FIFO0_EPDATA_M      0xFFFFFFFF  // Endpoint Data
+#define USB_FIFO0_EPDATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO1 register.
+//
+//*****************************************************************************
+#define USB_FIFO1_EPDATA_M      0xFFFFFFFF  // Endpoint Data
+#define USB_FIFO1_EPDATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO2 register.
+//
+//*****************************************************************************
+#define USB_FIFO2_EPDATA_M      0xFFFFFFFF  // Endpoint Data
+#define USB_FIFO2_EPDATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO3 register.
+//
+//*****************************************************************************
+#define USB_FIFO3_EPDATA_M      0xFFFFFFFF  // Endpoint Data
+#define USB_FIFO3_EPDATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO4 register.
+//
+//*****************************************************************************
+#define USB_FIFO4_EPDATA_M      0xFFFFFFFF  // Endpoint Data
+#define USB_FIFO4_EPDATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO5 register.
+//
+//*****************************************************************************
+#define USB_FIFO5_EPDATA_M      0xFFFFFFFF  // Endpoint Data
+#define USB_FIFO5_EPDATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO6 register.
+//
+//*****************************************************************************
+#define USB_FIFO6_EPDATA_M      0xFFFFFFFF  // Endpoint Data
+#define USB_FIFO6_EPDATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO7 register.
+//
+//*****************************************************************************
+#define USB_FIFO7_EPDATA_M      0xFFFFFFFF  // Endpoint Data
+#define USB_FIFO7_EPDATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO8 register.
+//
+//*****************************************************************************
+#define USB_FIFO8_EPDATA_M      0xFFFFFFFF  // Endpoint Data
+#define USB_FIFO8_EPDATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO9 register.
+//
+//*****************************************************************************
+#define USB_FIFO9_EPDATA_M      0xFFFFFFFF  // Endpoint Data
+#define USB_FIFO9_EPDATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO10 register.
+//
+//*****************************************************************************
+#define USB_FIFO10_EPDATA_M     0xFFFFFFFF  // Endpoint Data
+#define USB_FIFO10_EPDATA_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO11 register.
+//
+//*****************************************************************************
+#define USB_FIFO11_EPDATA_M     0xFFFFFFFF  // Endpoint Data
+#define USB_FIFO11_EPDATA_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO12 register.
+//
+//*****************************************************************************
+#define USB_FIFO12_EPDATA_M     0xFFFFFFFF  // Endpoint Data
+#define USB_FIFO12_EPDATA_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO13 register.
+//
+//*****************************************************************************
+#define USB_FIFO13_EPDATA_M     0xFFFFFFFF  // Endpoint Data
+#define USB_FIFO13_EPDATA_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO14 register.
+//
+//*****************************************************************************
+#define USB_FIFO14_EPDATA_M     0xFFFFFFFF  // Endpoint Data
+#define USB_FIFO14_EPDATA_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO15 register.
+//
+//*****************************************************************************
+#define USB_FIFO15_EPDATA_M     0xFFFFFFFF  // Endpoint Data
+#define USB_FIFO15_EPDATA_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DEVCTL register.
+//
+//*****************************************************************************
+#define USB_DEVCTL_DEV          0x00000080  // Device Mode
+#define USB_DEVCTL_FSDEV        0x00000040  // Full-Speed Device Detected
+#define USB_DEVCTL_LSDEV        0x00000020  // Low-Speed Device Detected
+#define USB_DEVCTL_VBUS_M       0x00000018  // VBUS Level
+#define USB_DEVCTL_VBUS_NONE    0x00000000  // Below SessionEnd
+#define USB_DEVCTL_VBUS_SEND    0x00000008  // Above SessionEnd, below AValid
+#define USB_DEVCTL_VBUS_AVALID  0x00000010  // Above AValid, below VBUSValid
+#define USB_DEVCTL_VBUS_VALID   0x00000018  // Above VBUSValid
+#define USB_DEVCTL_HOST         0x00000004  // Host Mode
+#define USB_DEVCTL_HOSTREQ      0x00000002  // Host Request
+#define USB_DEVCTL_SESSION      0x00000001  // Session Start/End
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFIFOSZ register.
+//
+//*****************************************************************************
+#define USB_TXFIFOSZ_DPB        0x00000010  // Double Packet Buffer Support
+#define USB_TXFIFOSZ_SIZE_M     0x0000000F  // Max Packet Size
+#define USB_TXFIFOSZ_SIZE_8     0x00000000  // 8
+#define USB_TXFIFOSZ_SIZE_16    0x00000001  // 16
+#define USB_TXFIFOSZ_SIZE_32    0x00000002  // 32
+#define USB_TXFIFOSZ_SIZE_64    0x00000003  // 64
+#define USB_TXFIFOSZ_SIZE_128   0x00000004  // 128
+#define USB_TXFIFOSZ_SIZE_256   0x00000005  // 256
+#define USB_TXFIFOSZ_SIZE_512   0x00000006  // 512
+#define USB_TXFIFOSZ_SIZE_1024  0x00000007  // 1024
+#define USB_TXFIFOSZ_SIZE_2048  0x00000008  // 2048
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFIFOSZ register.
+//
+//*****************************************************************************
+#define USB_RXFIFOSZ_DPB        0x00000010  // Double Packet Buffer Support
+#define USB_RXFIFOSZ_SIZE_M     0x0000000F  // Max Packet Size
+#define USB_RXFIFOSZ_SIZE_8     0x00000000  // 8
+#define USB_RXFIFOSZ_SIZE_16    0x00000001  // 16
+#define USB_RXFIFOSZ_SIZE_32    0x00000002  // 32
+#define USB_RXFIFOSZ_SIZE_64    0x00000003  // 64
+#define USB_RXFIFOSZ_SIZE_128   0x00000004  // 128
+#define USB_RXFIFOSZ_SIZE_256   0x00000005  // 256
+#define USB_RXFIFOSZ_SIZE_512   0x00000006  // 512
+#define USB_RXFIFOSZ_SIZE_1024  0x00000007  // 1024
+#define USB_RXFIFOSZ_SIZE_2048  0x00000008  // 2048
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFIFOADD
+// register.
+//
+//*****************************************************************************
+#define USB_TXFIFOADD_ADDR_M    0x000001FF  // Transmit/Receive Start Address
+#define USB_TXFIFOADD_ADDR_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFIFOADD
+// register.
+//
+//*****************************************************************************
+#define USB_RXFIFOADD_ADDR_M    0x000001FF  // Transmit/Receive Start Address
+#define USB_RXFIFOADD_ADDR_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_CONTIM register.
+//
+//*****************************************************************************
+#define USB_CONTIM_WTCON_M      0x000000F0  // Connect Wait
+#define USB_CONTIM_WTID_M       0x0000000F  // Wait ID
+#define USB_CONTIM_WTCON_S      4
+#define USB_CONTIM_WTID_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VPLEN register.
+//
+//*****************************************************************************
+#define USB_VPLEN_VPLEN_M       0x000000FF  // VBUS Pulse Length
+#define USB_VPLEN_VPLEN_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FSEOF register.
+//
+//*****************************************************************************
+#define USB_FSEOF_FSEOFG_M      0x000000FF  // Full-Speed End-of-Frame Gap
+#define USB_FSEOF_FSEOFG_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_LSEOF register.
+//
+//*****************************************************************************
+#define USB_LSEOF_LSEOFG_M      0x000000FF  // Low-Speed End-of-Frame Gap
+#define USB_LSEOF_LSEOFG_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR0
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR0_ADDR_M  0x0000007F  // Device Address
+#define USB_TXFUNCADDR0_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR0
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR0_MULTTRAN 0x00000080  // Multiple Translators
+#define USB_TXHUBADDR0_ADDR_M   0x0000007F  // Hub Address
+#define USB_TXHUBADDR0_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT0
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT0_PORT_M   0x0000007F  // Hub Port
+#define USB_TXHUBPORT0_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR1
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR1_ADDR_M  0x0000007F  // Device Address
+#define USB_TXFUNCADDR1_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR1
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR1_MULTTRAN 0x00000080  // Multiple Translators
+#define USB_TXHUBADDR1_ADDR_M   0x0000007F  // Hub Address
+#define USB_TXHUBADDR1_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT1
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT1_PORT_M   0x0000007F  // Hub Port
+#define USB_TXHUBPORT1_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR1
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR1_ADDR_M  0x0000007F  // Device Address
+#define USB_RXFUNCADDR1_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR1
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR1_MULTTRAN 0x00000080  // Multiple Translators
+#define USB_RXHUBADDR1_ADDR_M   0x0000007F  // Hub Address
+#define USB_RXHUBADDR1_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT1
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT1_PORT_M   0x0000007F  // Hub Port
+#define USB_RXHUBPORT1_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR2
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR2_ADDR_M  0x0000007F  // Device Address
+#define USB_TXFUNCADDR2_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR2
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR2_MULTTRAN 0x00000080  // Multiple Translators
+#define USB_TXHUBADDR2_ADDR_M   0x0000007F  // Hub Address
+#define USB_TXHUBADDR2_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT2
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT2_PORT_M   0x0000007F  // Hub Port
+#define USB_TXHUBPORT2_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR2
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR2_ADDR_M  0x0000007F  // Device Address
+#define USB_RXFUNCADDR2_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR2
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR2_MULTTRAN 0x00000080  // Multiple Translators
+#define USB_RXHUBADDR2_ADDR_M   0x0000007F  // Hub Address
+#define USB_RXHUBADDR2_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT2
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT2_PORT_M   0x0000007F  // Hub Port
+#define USB_RXHUBPORT2_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR3
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR3_ADDR_M  0x0000007F  // Device Address
+#define USB_TXFUNCADDR3_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR3
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR3_MULTTRAN 0x00000080  // Multiple Translators
+#define USB_TXHUBADDR3_ADDR_M   0x0000007F  // Hub Address
+#define USB_TXHUBADDR3_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT3
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT3_PORT_M   0x0000007F  // Hub Port
+#define USB_TXHUBPORT3_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR3
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR3_ADDR_M  0x0000007F  // Device Address
+#define USB_RXFUNCADDR3_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR3
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR3_MULTTRAN 0x00000080  // Multiple Translators
+#define USB_RXHUBADDR3_ADDR_M   0x0000007F  // Hub Address
+#define USB_RXHUBADDR3_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT3
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT3_PORT_M   0x0000007F  // Hub Port
+#define USB_RXHUBPORT3_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR4
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR4_ADDR_M  0x0000007F  // Device Address
+#define USB_TXFUNCADDR4_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR4
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR4_MULTTRAN 0x00000080  // Multiple Translators
+#define USB_TXHUBADDR4_ADDR_M   0x0000007F  // Hub Address
+#define USB_TXHUBADDR4_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT4
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT4_PORT_M   0x0000007F  // Hub Port
+#define USB_TXHUBPORT4_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR4
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR4_ADDR_M  0x0000007F  // Device Address
+#define USB_RXFUNCADDR4_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR4
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR4_MULTTRAN 0x00000080  // Multiple Translators
+#define USB_RXHUBADDR4_ADDR_M   0x0000007F  // Hub Address
+#define USB_RXHUBADDR4_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT4
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT4_PORT_M   0x0000007F  // Hub Port
+#define USB_RXHUBPORT4_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR5
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR5_ADDR_M  0x0000007F  // Device Address
+#define USB_TXFUNCADDR5_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR5
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR5_MULTTRAN 0x00000080  // Multiple Translators
+#define USB_TXHUBADDR5_ADDR_M   0x0000007F  // Hub Address
+#define USB_TXHUBADDR5_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT5
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT5_PORT_M   0x0000007F  // Hub Port
+#define USB_TXHUBPORT5_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR5
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR5_ADDR_M  0x0000007F  // Device Address
+#define USB_RXFUNCADDR5_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR5
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR5_MULTTRAN 0x00000080  // Multiple Translators
+#define USB_RXHUBADDR5_ADDR_M   0x0000007F  // Hub Address
+#define USB_RXHUBADDR5_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT5
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT5_PORT_M   0x0000007F  // Hub Port
+#define USB_RXHUBPORT5_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR6
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR6_ADDR_M  0x0000007F  // Device Address
+#define USB_TXFUNCADDR6_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR6
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR6_MULTTRAN 0x00000080  // Multiple Translators
+#define USB_TXHUBADDR6_ADDR_M   0x0000007F  // Hub Address
+#define USB_TXHUBADDR6_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT6
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT6_PORT_M   0x0000007F  // Hub Port
+#define USB_TXHUBPORT6_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR6
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR6_ADDR_M  0x0000007F  // Device Address
+#define USB_RXFUNCADDR6_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR6
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR6_MULTTRAN 0x00000080  // Multiple Translators
+#define USB_RXHUBADDR6_ADDR_M   0x0000007F  // Hub Address
+#define USB_RXHUBADDR6_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT6
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT6_PORT_M   0x0000007F  // Hub Port
+#define USB_RXHUBPORT6_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR7
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR7_ADDR_M  0x0000007F  // Device Address
+#define USB_TXFUNCADDR7_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR7
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR7_MULTTRAN 0x00000080  // Multiple Translators
+#define USB_TXHUBADDR7_ADDR_M   0x0000007F  // Hub Address
+#define USB_TXHUBADDR7_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT7
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT7_PORT_M   0x0000007F  // Hub Port
+#define USB_TXHUBPORT7_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR7
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR7_ADDR_M  0x0000007F  // Device Address
+#define USB_RXFUNCADDR7_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR7
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR7_MULTTRAN 0x00000080  // Multiple Translators
+#define USB_RXHUBADDR7_ADDR_M   0x0000007F  // Hub Address
+#define USB_RXHUBADDR7_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT7
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT7_PORT_M   0x0000007F  // Hub Port
+#define USB_RXHUBPORT7_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR8
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR8_ADDR_M  0x0000007F  // Device Address
+#define USB_TXFUNCADDR8_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR8
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR8_MULTTRAN 0x00000080  // Multiple Translators
+#define USB_TXHUBADDR8_ADDR_M   0x0000007F  // Hub Address
+#define USB_TXHUBADDR8_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT8
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT8_PORT_M   0x0000007F  // Hub Port
+#define USB_TXHUBPORT8_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR8
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR8_ADDR_M  0x0000007F  // Device Address
+#define USB_RXFUNCADDR8_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR8
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR8_MULTTRAN 0x00000080  // Multiple Translators
+#define USB_RXHUBADDR8_ADDR_M   0x0000007F  // Hub Address
+#define USB_RXHUBADDR8_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT8
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT8_PORT_M   0x0000007F  // Hub Port
+#define USB_RXHUBPORT8_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR9
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR9_ADDR_M  0x0000007F  // Device Address
+#define USB_TXFUNCADDR9_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR9
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR9_MULTTRAN 0x00000080  // Multiple Translators
+#define USB_TXHUBADDR9_ADDR_M   0x0000007F  // Hub Address
+#define USB_TXHUBADDR9_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT9
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT9_PORT_M   0x0000007F  // Hub Port
+#define USB_TXHUBPORT9_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR9
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR9_ADDR_M  0x0000007F  // Device Address
+#define USB_RXFUNCADDR9_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR9
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR9_MULTTRAN 0x00000080  // Multiple Translators
+#define USB_RXHUBADDR9_ADDR_M   0x0000007F  // Hub Address
+#define USB_RXHUBADDR9_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT9
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT9_PORT_M   0x0000007F  // Hub Port
+#define USB_RXHUBPORT9_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR10
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR10_ADDR_M 0x0000007F  // Device Address
+#define USB_TXFUNCADDR10_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR10
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR10_MULTTRAN \
+                                0x00000080  // Multiple Translators
+#define USB_TXHUBADDR10_ADDR_M  0x0000007F  // Hub Address
+#define USB_TXHUBADDR10_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT10
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT10_PORT_M  0x0000007F  // Hub Port
+#define USB_TXHUBPORT10_PORT_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR10
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR10_ADDR_M 0x0000007F  // Device Address
+#define USB_RXFUNCADDR10_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR10
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR10_MULTTRAN \
+                                0x00000080  // Multiple Translators
+#define USB_RXHUBADDR10_ADDR_M  0x0000007F  // Hub Address
+#define USB_RXHUBADDR10_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT10
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT10_PORT_M  0x0000007F  // Hub Port
+#define USB_RXHUBPORT10_PORT_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR11
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR11_ADDR_M 0x0000007F  // Device Address
+#define USB_TXFUNCADDR11_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR11
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR11_MULTTRAN \
+                                0x00000080  // Multiple Translators
+#define USB_TXHUBADDR11_ADDR_M  0x0000007F  // Hub Address
+#define USB_TXHUBADDR11_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT11
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT11_PORT_M  0x0000007F  // Hub Port
+#define USB_TXHUBPORT11_PORT_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR11
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR11_ADDR_M 0x0000007F  // Device Address
+#define USB_RXFUNCADDR11_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR11
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR11_MULTTRAN \
+                                0x00000080  // Multiple Translators
+#define USB_RXHUBADDR11_ADDR_M  0x0000007F  // Hub Address
+#define USB_RXHUBADDR11_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT11
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT11_PORT_M  0x0000007F  // Hub Port
+#define USB_RXHUBPORT11_PORT_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR12
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR12_ADDR_M 0x0000007F  // Device Address
+#define USB_TXFUNCADDR12_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR12
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR12_MULTTRAN \
+                                0x00000080  // Multiple Translators
+#define USB_TXHUBADDR12_ADDR_M  0x0000007F  // Hub Address
+#define USB_TXHUBADDR12_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT12
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT12_PORT_M  0x0000007F  // Hub Port
+#define USB_TXHUBPORT12_PORT_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR12
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR12_ADDR_M 0x0000007F  // Device Address
+#define USB_RXFUNCADDR12_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR12
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR12_MULTTRAN \
+                                0x00000080  // Multiple Translators
+#define USB_RXHUBADDR12_ADDR_M  0x0000007F  // Hub Address
+#define USB_RXHUBADDR12_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT12
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT12_PORT_M  0x0000007F  // Hub Port
+#define USB_RXHUBPORT12_PORT_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR13
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR13_ADDR_M 0x0000007F  // Device Address
+#define USB_TXFUNCADDR13_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR13
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR13_MULTTRAN \
+                                0x00000080  // Multiple Translators
+#define USB_TXHUBADDR13_ADDR_M  0x0000007F  // Hub Address
+#define USB_TXHUBADDR13_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT13
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT13_PORT_M  0x0000007F  // Hub Port
+#define USB_TXHUBPORT13_PORT_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR13
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR13_ADDR_M 0x0000007F  // Device Address
+#define USB_RXFUNCADDR13_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR13
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR13_MULTTRAN \
+                                0x00000080  // Multiple Translators
+#define USB_RXHUBADDR13_ADDR_M  0x0000007F  // Hub Address
+#define USB_RXHUBADDR13_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT13
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT13_PORT_M  0x0000007F  // Hub Port
+#define USB_RXHUBPORT13_PORT_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR14
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR14_ADDR_M 0x0000007F  // Device Address
+#define USB_TXFUNCADDR14_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR14
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR14_MULTTRAN \
+                                0x00000080  // Multiple Translators
+#define USB_TXHUBADDR14_ADDR_M  0x0000007F  // Hub Address
+#define USB_TXHUBADDR14_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT14
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT14_PORT_M  0x0000007F  // Hub Port
+#define USB_TXHUBPORT14_PORT_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR14
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR14_ADDR_M 0x0000007F  // Device Address
+#define USB_RXFUNCADDR14_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR14
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR14_MULTTRAN \
+                                0x00000080  // Multiple Translators
+#define USB_RXHUBADDR14_ADDR_M  0x0000007F  // Hub Address
+#define USB_RXHUBADDR14_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT14
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT14_PORT_M  0x0000007F  // Hub Port
+#define USB_RXHUBPORT14_PORT_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR15
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR15_ADDR_M 0x0000007F  // Device Address
+#define USB_TXFUNCADDR15_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR15
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR15_MULTTRAN \
+                                0x00000080  // Multiple Translators
+#define USB_TXHUBADDR15_ADDR_M  0x0000007F  // Hub Address
+#define USB_TXHUBADDR15_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT15
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT15_PORT_M  0x0000007F  // Hub Port
+#define USB_TXHUBPORT15_PORT_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR15
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR15_ADDR_M 0x0000007F  // Device Address
+#define USB_RXFUNCADDR15_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR15
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR15_MULTTRAN \
+                                0x00000080  // Multiple Translators
+#define USB_RXHUBADDR15_ADDR_M  0x0000007F  // Hub Address
+#define USB_RXHUBADDR15_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT15
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT15_PORT_M  0x0000007F  // Hub Port
+#define USB_RXHUBPORT15_PORT_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_CSRL0 register.
+//
+//*****************************************************************************
+#define USB_CSRL0_NAKTO         0x00000080  // NAK Timeout
+#define USB_CSRL0_SETENDC       0x00000080  // Setup End Clear
+#define USB_CSRL0_STATUS        0x00000040  // STATUS Packet
+#define USB_CSRL0_RXRDYC        0x00000040  // RXRDY Clear
+#define USB_CSRL0_REQPKT        0x00000020  // Request Packet
+#define USB_CSRL0_STALL         0x00000020  // Send Stall
+#define USB_CSRL0_SETEND        0x00000010  // Setup End
+#define USB_CSRL0_ERROR         0x00000010  // Error
+#define USB_CSRL0_DATAEND       0x00000008  // Data End
+#define USB_CSRL0_SETUP         0x00000008  // Setup Packet
+#define USB_CSRL0_STALLED       0x00000004  // Endpoint Stalled
+#define USB_CSRL0_TXRDY         0x00000002  // Transmit Packet Ready
+#define USB_CSRL0_RXRDY         0x00000001  // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_CSRH0 register.
+//
+//*****************************************************************************
+#define USB_CSRH0_DTWE          0x00000004  // Data Toggle Write Enable
+#define USB_CSRH0_DT            0x00000002  // Data Toggle
+#define USB_CSRH0_FLUSH         0x00000001  // Flush FIFO
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_COUNT0 register.
+//
+//*****************************************************************************
+#define USB_COUNT0_COUNT_M      0x0000007F  // FIFO Count
+#define USB_COUNT0_COUNT_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TYPE0 register.
+//
+//*****************************************************************************
+#define USB_TYPE0_SPEED_M       0x000000C0  // Operating Speed
+#define USB_TYPE0_SPEED_FULL    0x00000080  // Full
+#define USB_TYPE0_SPEED_LOW     0x000000C0  // Low
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_NAKLMT register.
+//
+//*****************************************************************************
+#define USB_NAKLMT_NAKLMT_M     0x0000001F  // EP0 NAK Limit
+#define USB_NAKLMT_NAKLMT_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP1 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP1_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_TXMAXP1_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL1 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL1_NAKTO       0x00000080  // NAK Timeout
+#define USB_TXCSRL1_CLRDT       0x00000040  // Clear Data Toggle
+#define USB_TXCSRL1_STALLED     0x00000020  // Endpoint Stalled
+#define USB_TXCSRL1_STALL       0x00000010  // Send STALL
+#define USB_TXCSRL1_SETUP       0x00000010  // Setup Packet
+#define USB_TXCSRL1_FLUSH       0x00000008  // Flush FIFO
+#define USB_TXCSRL1_ERROR       0x00000004  // Error
+#define USB_TXCSRL1_UNDRN       0x00000004  // Underrun
+#define USB_TXCSRL1_FIFONE      0x00000002  // FIFO Not Empty
+#define USB_TXCSRL1_TXRDY       0x00000001  // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH1 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH1_AUTOSET     0x00000080  // Auto Set
+#define USB_TXCSRH1_ISO         0x00000040  // Isochronous Transfers
+#define USB_TXCSRH1_MODE        0x00000020  // Mode
+#define USB_TXCSRH1_DMAEN       0x00000010  // DMA Request Enable
+#define USB_TXCSRH1_FDT         0x00000008  // Force Data Toggle
+#define USB_TXCSRH1_DMAMOD      0x00000004  // DMA Request Mode
+#define USB_TXCSRH1_DTWE        0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH1_DT          0x00000001  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP1 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP1_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_RXMAXP1_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL1 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL1_CLRDT       0x00000080  // Clear Data Toggle
+#define USB_RXCSRL1_STALLED     0x00000040  // Endpoint Stalled
+#define USB_RXCSRL1_STALL       0x00000020  // Send STALL
+#define USB_RXCSRL1_REQPKT      0x00000020  // Request Packet
+#define USB_RXCSRL1_FLUSH       0x00000010  // Flush FIFO
+#define USB_RXCSRL1_DATAERR     0x00000008  // Data Error
+#define USB_RXCSRL1_NAKTO       0x00000008  // NAK Timeout
+#define USB_RXCSRL1_OVER        0x00000004  // Overrun
+#define USB_RXCSRL1_ERROR       0x00000004  // Error
+#define USB_RXCSRL1_FULL        0x00000002  // FIFO Full
+#define USB_RXCSRL1_RXRDY       0x00000001  // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH1 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH1_AUTOCL      0x00000080  // Auto Clear
+#define USB_RXCSRH1_AUTORQ      0x00000040  // Auto Request
+#define USB_RXCSRH1_ISO         0x00000040  // Isochronous Transfers
+#define USB_RXCSRH1_DMAEN       0x00000020  // DMA Request Enable
+#define USB_RXCSRH1_DISNYET     0x00000010  // Disable NYET
+#define USB_RXCSRH1_PIDERR      0x00000010  // PID Error
+#define USB_RXCSRH1_DMAMOD      0x00000008  // DMA Request Mode
+#define USB_RXCSRH1_DTWE        0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH1_DT          0x00000002  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT1 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT1_COUNT_M    0x00001FFF  // Receive Packet Count
+#define USB_RXCOUNT1_COUNT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE1 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE1_SPEED_M     0x000000C0  // Operating Speed
+#define USB_TXTYPE1_SPEED_DFLT  0x00000000  // Default
+#define USB_TXTYPE1_SPEED_FULL  0x00000080  // Full
+#define USB_TXTYPE1_SPEED_LOW   0x000000C0  // Low
+#define USB_TXTYPE1_PROTO_M     0x00000030  // Protocol
+#define USB_TXTYPE1_PROTO_CTRL  0x00000000  // Control
+#define USB_TXTYPE1_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_TXTYPE1_PROTO_BULK  0x00000020  // Bulk
+#define USB_TXTYPE1_PROTO_INT   0x00000030  // Interrupt
+#define USB_TXTYPE1_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_TXTYPE1_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL1
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL1_NAKLMT_M \
+                                0x000000FF  // NAK Limit
+#define USB_TXINTERVAL1_TXPOLL_M \
+                                0x000000FF  // TX Polling
+#define USB_TXINTERVAL1_TXPOLL_S \
+                                0
+#define USB_TXINTERVAL1_NAKLMT_S \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE1 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE1_SPEED_M     0x000000C0  // Operating Speed
+#define USB_RXTYPE1_SPEED_DFLT  0x00000000  // Default
+#define USB_RXTYPE1_SPEED_FULL  0x00000080  // Full
+#define USB_RXTYPE1_SPEED_LOW   0x000000C0  // Low
+#define USB_RXTYPE1_PROTO_M     0x00000030  // Protocol
+#define USB_RXTYPE1_PROTO_CTRL  0x00000000  // Control
+#define USB_RXTYPE1_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_RXTYPE1_PROTO_BULK  0x00000020  // Bulk
+#define USB_RXTYPE1_PROTO_INT   0x00000030  // Interrupt
+#define USB_RXTYPE1_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_RXTYPE1_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL1
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL1_TXPOLL_M \
+                                0x000000FF  // RX Polling
+#define USB_RXINTERVAL1_NAKLMT_M \
+                                0x000000FF  // NAK Limit
+#define USB_RXINTERVAL1_TXPOLL_S \
+                                0
+#define USB_RXINTERVAL1_NAKLMT_S \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP2 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP2_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_TXMAXP2_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL2 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL2_NAKTO       0x00000080  // NAK Timeout
+#define USB_TXCSRL2_CLRDT       0x00000040  // Clear Data Toggle
+#define USB_TXCSRL2_STALLED     0x00000020  // Endpoint Stalled
+#define USB_TXCSRL2_SETUP       0x00000010  // Setup Packet
+#define USB_TXCSRL2_STALL       0x00000010  // Send STALL
+#define USB_TXCSRL2_FLUSH       0x00000008  // Flush FIFO
+#define USB_TXCSRL2_ERROR       0x00000004  // Error
+#define USB_TXCSRL2_UNDRN       0x00000004  // Underrun
+#define USB_TXCSRL2_FIFONE      0x00000002  // FIFO Not Empty
+#define USB_TXCSRL2_TXRDY       0x00000001  // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH2 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH2_AUTOSET     0x00000080  // Auto Set
+#define USB_TXCSRH2_ISO         0x00000040  // Isochronous Transfers
+#define USB_TXCSRH2_MODE        0x00000020  // Mode
+#define USB_TXCSRH2_DMAEN       0x00000010  // DMA Request Enable
+#define USB_TXCSRH2_FDT         0x00000008  // Force Data Toggle
+#define USB_TXCSRH2_DMAMOD      0x00000004  // DMA Request Mode
+#define USB_TXCSRH2_DTWE        0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH2_DT          0x00000001  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP2 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP2_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_RXMAXP2_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL2 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL2_CLRDT       0x00000080  // Clear Data Toggle
+#define USB_RXCSRL2_STALLED     0x00000040  // Endpoint Stalled
+#define USB_RXCSRL2_REQPKT      0x00000020  // Request Packet
+#define USB_RXCSRL2_STALL       0x00000020  // Send STALL
+#define USB_RXCSRL2_FLUSH       0x00000010  // Flush FIFO
+#define USB_RXCSRL2_DATAERR     0x00000008  // Data Error
+#define USB_RXCSRL2_NAKTO       0x00000008  // NAK Timeout
+#define USB_RXCSRL2_ERROR       0x00000004  // Error
+#define USB_RXCSRL2_OVER        0x00000004  // Overrun
+#define USB_RXCSRL2_FULL        0x00000002  // FIFO Full
+#define USB_RXCSRL2_RXRDY       0x00000001  // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH2 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH2_AUTOCL      0x00000080  // Auto Clear
+#define USB_RXCSRH2_AUTORQ      0x00000040  // Auto Request
+#define USB_RXCSRH2_ISO         0x00000040  // Isochronous Transfers
+#define USB_RXCSRH2_DMAEN       0x00000020  // DMA Request Enable
+#define USB_RXCSRH2_DISNYET     0x00000010  // Disable NYET
+#define USB_RXCSRH2_PIDERR      0x00000010  // PID Error
+#define USB_RXCSRH2_DMAMOD      0x00000008  // DMA Request Mode
+#define USB_RXCSRH2_DTWE        0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH2_DT          0x00000002  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT2 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT2_COUNT_M    0x00001FFF  // Receive Packet Count
+#define USB_RXCOUNT2_COUNT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE2 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE2_SPEED_M     0x000000C0  // Operating Speed
+#define USB_TXTYPE2_SPEED_DFLT  0x00000000  // Default
+#define USB_TXTYPE2_SPEED_FULL  0x00000080  // Full
+#define USB_TXTYPE2_SPEED_LOW   0x000000C0  // Low
+#define USB_TXTYPE2_PROTO_M     0x00000030  // Protocol
+#define USB_TXTYPE2_PROTO_CTRL  0x00000000  // Control
+#define USB_TXTYPE2_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_TXTYPE2_PROTO_BULK  0x00000020  // Bulk
+#define USB_TXTYPE2_PROTO_INT   0x00000030  // Interrupt
+#define USB_TXTYPE2_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_TXTYPE2_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL2
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL2_TXPOLL_M \
+                                0x000000FF  // TX Polling
+#define USB_TXINTERVAL2_NAKLMT_M \
+                                0x000000FF  // NAK Limit
+#define USB_TXINTERVAL2_NAKLMT_S \
+                                0
+#define USB_TXINTERVAL2_TXPOLL_S \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE2 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE2_SPEED_M     0x000000C0  // Operating Speed
+#define USB_RXTYPE2_SPEED_DFLT  0x00000000  // Default
+#define USB_RXTYPE2_SPEED_FULL  0x00000080  // Full
+#define USB_RXTYPE2_SPEED_LOW   0x000000C0  // Low
+#define USB_RXTYPE2_PROTO_M     0x00000030  // Protocol
+#define USB_RXTYPE2_PROTO_CTRL  0x00000000  // Control
+#define USB_RXTYPE2_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_RXTYPE2_PROTO_BULK  0x00000020  // Bulk
+#define USB_RXTYPE2_PROTO_INT   0x00000030  // Interrupt
+#define USB_RXTYPE2_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_RXTYPE2_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL2
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL2_TXPOLL_M \
+                                0x000000FF  // RX Polling
+#define USB_RXINTERVAL2_NAKLMT_M \
+                                0x000000FF  // NAK Limit
+#define USB_RXINTERVAL2_TXPOLL_S \
+                                0
+#define USB_RXINTERVAL2_NAKLMT_S \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP3 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP3_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_TXMAXP3_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL3 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL3_NAKTO       0x00000080  // NAK Timeout
+#define USB_TXCSRL3_CLRDT       0x00000040  // Clear Data Toggle
+#define USB_TXCSRL3_STALLED     0x00000020  // Endpoint Stalled
+#define USB_TXCSRL3_SETUP       0x00000010  // Setup Packet
+#define USB_TXCSRL3_STALL       0x00000010  // Send STALL
+#define USB_TXCSRL3_FLUSH       0x00000008  // Flush FIFO
+#define USB_TXCSRL3_ERROR       0x00000004  // Error
+#define USB_TXCSRL3_UNDRN       0x00000004  // Underrun
+#define USB_TXCSRL3_FIFONE      0x00000002  // FIFO Not Empty
+#define USB_TXCSRL3_TXRDY       0x00000001  // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH3 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH3_AUTOSET     0x00000080  // Auto Set
+#define USB_TXCSRH3_ISO         0x00000040  // Isochronous Transfers
+#define USB_TXCSRH3_MODE        0x00000020  // Mode
+#define USB_TXCSRH3_DMAEN       0x00000010  // DMA Request Enable
+#define USB_TXCSRH3_FDT         0x00000008  // Force Data Toggle
+#define USB_TXCSRH3_DMAMOD      0x00000004  // DMA Request Mode
+#define USB_TXCSRH3_DTWE        0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH3_DT          0x00000001  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP3 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP3_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_RXMAXP3_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL3 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL3_CLRDT       0x00000080  // Clear Data Toggle
+#define USB_RXCSRL3_STALLED     0x00000040  // Endpoint Stalled
+#define USB_RXCSRL3_STALL       0x00000020  // Send STALL
+#define USB_RXCSRL3_REQPKT      0x00000020  // Request Packet
+#define USB_RXCSRL3_FLUSH       0x00000010  // Flush FIFO
+#define USB_RXCSRL3_DATAERR     0x00000008  // Data Error
+#define USB_RXCSRL3_NAKTO       0x00000008  // NAK Timeout
+#define USB_RXCSRL3_ERROR       0x00000004  // Error
+#define USB_RXCSRL3_OVER        0x00000004  // Overrun
+#define USB_RXCSRL3_FULL        0x00000002  // FIFO Full
+#define USB_RXCSRL3_RXRDY       0x00000001  // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH3 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH3_AUTOCL      0x00000080  // Auto Clear
+#define USB_RXCSRH3_AUTORQ      0x00000040  // Auto Request
+#define USB_RXCSRH3_ISO         0x00000040  // Isochronous Transfers
+#define USB_RXCSRH3_DMAEN       0x00000020  // DMA Request Enable
+#define USB_RXCSRH3_DISNYET     0x00000010  // Disable NYET
+#define USB_RXCSRH3_PIDERR      0x00000010  // PID Error
+#define USB_RXCSRH3_DMAMOD      0x00000008  // DMA Request Mode
+#define USB_RXCSRH3_DTWE        0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH3_DT          0x00000002  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT3 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT3_COUNT_M    0x00001FFF  // Receive Packet Count
+#define USB_RXCOUNT3_COUNT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE3 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE3_SPEED_M     0x000000C0  // Operating Speed
+#define USB_TXTYPE3_SPEED_DFLT  0x00000000  // Default
+#define USB_TXTYPE3_SPEED_FULL  0x00000080  // Full
+#define USB_TXTYPE3_SPEED_LOW   0x000000C0  // Low
+#define USB_TXTYPE3_PROTO_M     0x00000030  // Protocol
+#define USB_TXTYPE3_PROTO_CTRL  0x00000000  // Control
+#define USB_TXTYPE3_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_TXTYPE3_PROTO_BULK  0x00000020  // Bulk
+#define USB_TXTYPE3_PROTO_INT   0x00000030  // Interrupt
+#define USB_TXTYPE3_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_TXTYPE3_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL3
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL3_TXPOLL_M \
+                                0x000000FF  // TX Polling
+#define USB_TXINTERVAL3_NAKLMT_M \
+                                0x000000FF  // NAK Limit
+#define USB_TXINTERVAL3_TXPOLL_S \
+                                0
+#define USB_TXINTERVAL3_NAKLMT_S \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE3 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE3_SPEED_M     0x000000C0  // Operating Speed
+#define USB_RXTYPE3_SPEED_DFLT  0x00000000  // Default
+#define USB_RXTYPE3_SPEED_FULL  0x00000080  // Full
+#define USB_RXTYPE3_SPEED_LOW   0x000000C0  // Low
+#define USB_RXTYPE3_PROTO_M     0x00000030  // Protocol
+#define USB_RXTYPE3_PROTO_CTRL  0x00000000  // Control
+#define USB_RXTYPE3_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_RXTYPE3_PROTO_BULK  0x00000020  // Bulk
+#define USB_RXTYPE3_PROTO_INT   0x00000030  // Interrupt
+#define USB_RXTYPE3_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_RXTYPE3_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL3
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL3_TXPOLL_M \
+                                0x000000FF  // RX Polling
+#define USB_RXINTERVAL3_NAKLMT_M \
+                                0x000000FF  // NAK Limit
+#define USB_RXINTERVAL3_TXPOLL_S \
+                                0
+#define USB_RXINTERVAL3_NAKLMT_S \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP4 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP4_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_TXMAXP4_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL4 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL4_NAKTO       0x00000080  // NAK Timeout
+#define USB_TXCSRL4_CLRDT       0x00000040  // Clear Data Toggle
+#define USB_TXCSRL4_STALLED     0x00000020  // Endpoint Stalled
+#define USB_TXCSRL4_SETUP       0x00000010  // Setup Packet
+#define USB_TXCSRL4_STALL       0x00000010  // Send STALL
+#define USB_TXCSRL4_FLUSH       0x00000008  // Flush FIFO
+#define USB_TXCSRL4_ERROR       0x00000004  // Error
+#define USB_TXCSRL4_UNDRN       0x00000004  // Underrun
+#define USB_TXCSRL4_FIFONE      0x00000002  // FIFO Not Empty
+#define USB_TXCSRL4_TXRDY       0x00000001  // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH4 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH4_AUTOSET     0x00000080  // Auto Set
+#define USB_TXCSRH4_ISO         0x00000040  // Isochronous Transfers
+#define USB_TXCSRH4_MODE        0x00000020  // Mode
+#define USB_TXCSRH4_DMAEN       0x00000010  // DMA Request Enable
+#define USB_TXCSRH4_FDT         0x00000008  // Force Data Toggle
+#define USB_TXCSRH4_DMAMOD      0x00000004  // DMA Request Mode
+#define USB_TXCSRH4_DTWE        0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH4_DT          0x00000001  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP4 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP4_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_RXMAXP4_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL4 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL4_CLRDT       0x00000080  // Clear Data Toggle
+#define USB_RXCSRL4_STALLED     0x00000040  // Endpoint Stalled
+#define USB_RXCSRL4_STALL       0x00000020  // Send STALL
+#define USB_RXCSRL4_REQPKT      0x00000020  // Request Packet
+#define USB_RXCSRL4_FLUSH       0x00000010  // Flush FIFO
+#define USB_RXCSRL4_NAKTO       0x00000008  // NAK Timeout
+#define USB_RXCSRL4_DATAERR     0x00000008  // Data Error
+#define USB_RXCSRL4_OVER        0x00000004  // Overrun
+#define USB_RXCSRL4_ERROR       0x00000004  // Error
+#define USB_RXCSRL4_FULL        0x00000002  // FIFO Full
+#define USB_RXCSRL4_RXRDY       0x00000001  // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH4 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH4_AUTOCL      0x00000080  // Auto Clear
+#define USB_RXCSRH4_AUTORQ      0x00000040  // Auto Request
+#define USB_RXCSRH4_ISO         0x00000040  // Isochronous Transfers
+#define USB_RXCSRH4_DMAEN       0x00000020  // DMA Request Enable
+#define USB_RXCSRH4_DISNYET     0x00000010  // Disable NYET
+#define USB_RXCSRH4_PIDERR      0x00000010  // PID Error
+#define USB_RXCSRH4_DMAMOD      0x00000008  // DMA Request Mode
+#define USB_RXCSRH4_DTWE        0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH4_DT          0x00000002  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT4 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT4_COUNT_M    0x00001FFF  // Receive Packet Count
+#define USB_RXCOUNT4_COUNT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE4 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE4_SPEED_M     0x000000C0  // Operating Speed
+#define USB_TXTYPE4_SPEED_DFLT  0x00000000  // Default
+#define USB_TXTYPE4_SPEED_FULL  0x00000080  // Full
+#define USB_TXTYPE4_SPEED_LOW   0x000000C0  // Low
+#define USB_TXTYPE4_PROTO_M     0x00000030  // Protocol
+#define USB_TXTYPE4_PROTO_CTRL  0x00000000  // Control
+#define USB_TXTYPE4_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_TXTYPE4_PROTO_BULK  0x00000020  // Bulk
+#define USB_TXTYPE4_PROTO_INT   0x00000030  // Interrupt
+#define USB_TXTYPE4_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_TXTYPE4_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL4
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL4_TXPOLL_M \
+                                0x000000FF  // TX Polling
+#define USB_TXINTERVAL4_NAKLMT_M \
+                                0x000000FF  // NAK Limit
+#define USB_TXINTERVAL4_NAKLMT_S \
+                                0
+#define USB_TXINTERVAL4_TXPOLL_S \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE4 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE4_SPEED_M     0x000000C0  // Operating Speed
+#define USB_RXTYPE4_SPEED_DFLT  0x00000000  // Default
+#define USB_RXTYPE4_SPEED_FULL  0x00000080  // Full
+#define USB_RXTYPE4_SPEED_LOW   0x000000C0  // Low
+#define USB_RXTYPE4_PROTO_M     0x00000030  // Protocol
+#define USB_RXTYPE4_PROTO_CTRL  0x00000000  // Control
+#define USB_RXTYPE4_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_RXTYPE4_PROTO_BULK  0x00000020  // Bulk
+#define USB_RXTYPE4_PROTO_INT   0x00000030  // Interrupt
+#define USB_RXTYPE4_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_RXTYPE4_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL4
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL4_TXPOLL_M \
+                                0x000000FF  // RX Polling
+#define USB_RXINTERVAL4_NAKLMT_M \
+                                0x000000FF  // NAK Limit
+#define USB_RXINTERVAL4_NAKLMT_S \
+                                0
+#define USB_RXINTERVAL4_TXPOLL_S \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP5 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP5_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_TXMAXP5_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL5 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL5_NAKTO       0x00000080  // NAK Timeout
+#define USB_TXCSRL5_CLRDT       0x00000040  // Clear Data Toggle
+#define USB_TXCSRL5_STALLED     0x00000020  // Endpoint Stalled
+#define USB_TXCSRL5_SETUP       0x00000010  // Setup Packet
+#define USB_TXCSRL5_STALL       0x00000010  // Send STALL
+#define USB_TXCSRL5_FLUSH       0x00000008  // Flush FIFO
+#define USB_TXCSRL5_ERROR       0x00000004  // Error
+#define USB_TXCSRL5_UNDRN       0x00000004  // Underrun
+#define USB_TXCSRL5_FIFONE      0x00000002  // FIFO Not Empty
+#define USB_TXCSRL5_TXRDY       0x00000001  // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH5 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH5_AUTOSET     0x00000080  // Auto Set
+#define USB_TXCSRH5_ISO         0x00000040  // Isochronous Transfers
+#define USB_TXCSRH5_MODE        0x00000020  // Mode
+#define USB_TXCSRH5_DMAEN       0x00000010  // DMA Request Enable
+#define USB_TXCSRH5_FDT         0x00000008  // Force Data Toggle
+#define USB_TXCSRH5_DMAMOD      0x00000004  // DMA Request Mode
+#define USB_TXCSRH5_DTWE        0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH5_DT          0x00000001  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP5 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP5_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_RXMAXP5_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL5 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL5_CLRDT       0x00000080  // Clear Data Toggle
+#define USB_RXCSRL5_STALLED     0x00000040  // Endpoint Stalled
+#define USB_RXCSRL5_STALL       0x00000020  // Send STALL
+#define USB_RXCSRL5_REQPKT      0x00000020  // Request Packet
+#define USB_RXCSRL5_FLUSH       0x00000010  // Flush FIFO
+#define USB_RXCSRL5_NAKTO       0x00000008  // NAK Timeout
+#define USB_RXCSRL5_DATAERR     0x00000008  // Data Error
+#define USB_RXCSRL5_ERROR       0x00000004  // Error
+#define USB_RXCSRL5_OVER        0x00000004  // Overrun
+#define USB_RXCSRL5_FULL        0x00000002  // FIFO Full
+#define USB_RXCSRL5_RXRDY       0x00000001  // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH5 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH5_AUTOCL      0x00000080  // Auto Clear
+#define USB_RXCSRH5_AUTORQ      0x00000040  // Auto Request
+#define USB_RXCSRH5_ISO         0x00000040  // Isochronous Transfers
+#define USB_RXCSRH5_DMAEN       0x00000020  // DMA Request Enable
+#define USB_RXCSRH5_DISNYET     0x00000010  // Disable NYET
+#define USB_RXCSRH5_PIDERR      0x00000010  // PID Error
+#define USB_RXCSRH5_DMAMOD      0x00000008  // DMA Request Mode
+#define USB_RXCSRH5_DTWE        0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH5_DT          0x00000002  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT5 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT5_COUNT_M    0x00001FFF  // Receive Packet Count
+#define USB_RXCOUNT5_COUNT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE5 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE5_SPEED_M     0x000000C0  // Operating Speed
+#define USB_TXTYPE5_SPEED_DFLT  0x00000000  // Default
+#define USB_TXTYPE5_SPEED_FULL  0x00000080  // Full
+#define USB_TXTYPE5_SPEED_LOW   0x000000C0  // Low
+#define USB_TXTYPE5_PROTO_M     0x00000030  // Protocol
+#define USB_TXTYPE5_PROTO_CTRL  0x00000000  // Control
+#define USB_TXTYPE5_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_TXTYPE5_PROTO_BULK  0x00000020  // Bulk
+#define USB_TXTYPE5_PROTO_INT   0x00000030  // Interrupt
+#define USB_TXTYPE5_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_TXTYPE5_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL5
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL5_TXPOLL_M \
+                                0x000000FF  // TX Polling
+#define USB_TXINTERVAL5_NAKLMT_M \
+                                0x000000FF  // NAK Limit
+#define USB_TXINTERVAL5_NAKLMT_S \
+                                0
+#define USB_TXINTERVAL5_TXPOLL_S \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE5 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE5_SPEED_M     0x000000C0  // Operating Speed
+#define USB_RXTYPE5_SPEED_DFLT  0x00000000  // Default
+#define USB_RXTYPE5_SPEED_FULL  0x00000080  // Full
+#define USB_RXTYPE5_SPEED_LOW   0x000000C0  // Low
+#define USB_RXTYPE5_PROTO_M     0x00000030  // Protocol
+#define USB_RXTYPE5_PROTO_CTRL  0x00000000  // Control
+#define USB_RXTYPE5_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_RXTYPE5_PROTO_BULK  0x00000020  // Bulk
+#define USB_RXTYPE5_PROTO_INT   0x00000030  // Interrupt
+#define USB_RXTYPE5_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_RXTYPE5_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL5
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL5_TXPOLL_M \
+                                0x000000FF  // RX Polling
+#define USB_RXINTERVAL5_NAKLMT_M \
+                                0x000000FF  // NAK Limit
+#define USB_RXINTERVAL5_TXPOLL_S \
+                                0
+#define USB_RXINTERVAL5_NAKLMT_S \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP6 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP6_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_TXMAXP6_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL6 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL6_NAKTO       0x00000080  // NAK Timeout
+#define USB_TXCSRL6_CLRDT       0x00000040  // Clear Data Toggle
+#define USB_TXCSRL6_STALLED     0x00000020  // Endpoint Stalled
+#define USB_TXCSRL6_STALL       0x00000010  // Send STALL
+#define USB_TXCSRL6_SETUP       0x00000010  // Setup Packet
+#define USB_TXCSRL6_FLUSH       0x00000008  // Flush FIFO
+#define USB_TXCSRL6_ERROR       0x00000004  // Error
+#define USB_TXCSRL6_UNDRN       0x00000004  // Underrun
+#define USB_TXCSRL6_FIFONE      0x00000002  // FIFO Not Empty
+#define USB_TXCSRL6_TXRDY       0x00000001  // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH6 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH6_AUTOSET     0x00000080  // Auto Set
+#define USB_TXCSRH6_ISO         0x00000040  // Isochronous Transfers
+#define USB_TXCSRH6_MODE        0x00000020  // Mode
+#define USB_TXCSRH6_DMAEN       0x00000010  // DMA Request Enable
+#define USB_TXCSRH6_FDT         0x00000008  // Force Data Toggle
+#define USB_TXCSRH6_DMAMOD      0x00000004  // DMA Request Mode
+#define USB_TXCSRH6_DTWE        0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH6_DT          0x00000001  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP6 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP6_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_RXMAXP6_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL6 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL6_CLRDT       0x00000080  // Clear Data Toggle
+#define USB_RXCSRL6_STALLED     0x00000040  // Endpoint Stalled
+#define USB_RXCSRL6_REQPKT      0x00000020  // Request Packet
+#define USB_RXCSRL6_STALL       0x00000020  // Send STALL
+#define USB_RXCSRL6_FLUSH       0x00000010  // Flush FIFO
+#define USB_RXCSRL6_NAKTO       0x00000008  // NAK Timeout
+#define USB_RXCSRL6_DATAERR     0x00000008  // Data Error
+#define USB_RXCSRL6_ERROR       0x00000004  // Error
+#define USB_RXCSRL6_OVER        0x00000004  // Overrun
+#define USB_RXCSRL6_FULL        0x00000002  // FIFO Full
+#define USB_RXCSRL6_RXRDY       0x00000001  // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH6 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH6_AUTOCL      0x00000080  // Auto Clear
+#define USB_RXCSRH6_AUTORQ      0x00000040  // Auto Request
+#define USB_RXCSRH6_ISO         0x00000040  // Isochronous Transfers
+#define USB_RXCSRH6_DMAEN       0x00000020  // DMA Request Enable
+#define USB_RXCSRH6_DISNYET     0x00000010  // Disable NYET
+#define USB_RXCSRH6_PIDERR      0x00000010  // PID Error
+#define USB_RXCSRH6_DMAMOD      0x00000008  // DMA Request Mode
+#define USB_RXCSRH6_DTWE        0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH6_DT          0x00000002  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT6 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT6_COUNT_M    0x00001FFF  // Receive Packet Count
+#define USB_RXCOUNT6_COUNT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE6 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE6_SPEED_M     0x000000C0  // Operating Speed
+#define USB_TXTYPE6_SPEED_DFLT  0x00000000  // Default
+#define USB_TXTYPE6_SPEED_FULL  0x00000080  // Full
+#define USB_TXTYPE6_SPEED_LOW   0x000000C0  // Low
+#define USB_TXTYPE6_PROTO_M     0x00000030  // Protocol
+#define USB_TXTYPE6_PROTO_CTRL  0x00000000  // Control
+#define USB_TXTYPE6_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_TXTYPE6_PROTO_BULK  0x00000020  // Bulk
+#define USB_TXTYPE6_PROTO_INT   0x00000030  // Interrupt
+#define USB_TXTYPE6_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_TXTYPE6_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL6
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL6_TXPOLL_M \
+                                0x000000FF  // TX Polling
+#define USB_TXINTERVAL6_NAKLMT_M \
+                                0x000000FF  // NAK Limit
+#define USB_TXINTERVAL6_TXPOLL_S \
+                                0
+#define USB_TXINTERVAL6_NAKLMT_S \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE6 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE6_SPEED_M     0x000000C0  // Operating Speed
+#define USB_RXTYPE6_SPEED_DFLT  0x00000000  // Default
+#define USB_RXTYPE6_SPEED_FULL  0x00000080  // Full
+#define USB_RXTYPE6_SPEED_LOW   0x000000C0  // Low
+#define USB_RXTYPE6_PROTO_M     0x00000030  // Protocol
+#define USB_RXTYPE6_PROTO_CTRL  0x00000000  // Control
+#define USB_RXTYPE6_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_RXTYPE6_PROTO_BULK  0x00000020  // Bulk
+#define USB_RXTYPE6_PROTO_INT   0x00000030  // Interrupt
+#define USB_RXTYPE6_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_RXTYPE6_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL6
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL6_TXPOLL_M \
+                                0x000000FF  // RX Polling
+#define USB_RXINTERVAL6_NAKLMT_M \
+                                0x000000FF  // NAK Limit
+#define USB_RXINTERVAL6_NAKLMT_S \
+                                0
+#define USB_RXINTERVAL6_TXPOLL_S \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP7 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP7_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_TXMAXP7_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL7 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL7_NAKTO       0x00000080  // NAK Timeout
+#define USB_TXCSRL7_CLRDT       0x00000040  // Clear Data Toggle
+#define USB_TXCSRL7_STALLED     0x00000020  // Endpoint Stalled
+#define USB_TXCSRL7_STALL       0x00000010  // Send STALL
+#define USB_TXCSRL7_SETUP       0x00000010  // Setup Packet
+#define USB_TXCSRL7_FLUSH       0x00000008  // Flush FIFO
+#define USB_TXCSRL7_ERROR       0x00000004  // Error
+#define USB_TXCSRL7_UNDRN       0x00000004  // Underrun
+#define USB_TXCSRL7_FIFONE      0x00000002  // FIFO Not Empty
+#define USB_TXCSRL7_TXRDY       0x00000001  // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH7 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH7_AUTOSET     0x00000080  // Auto Set
+#define USB_TXCSRH7_ISO         0x00000040  // Isochronous Transfers
+#define USB_TXCSRH7_MODE        0x00000020  // Mode
+#define USB_TXCSRH7_DMAEN       0x00000010  // DMA Request Enable
+#define USB_TXCSRH7_FDT         0x00000008  // Force Data Toggle
+#define USB_TXCSRH7_DMAMOD      0x00000004  // DMA Request Mode
+#define USB_TXCSRH7_DTWE        0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH7_DT          0x00000001  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP7 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP7_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_RXMAXP7_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL7 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL7_CLRDT       0x00000080  // Clear Data Toggle
+#define USB_RXCSRL7_STALLED     0x00000040  // Endpoint Stalled
+#define USB_RXCSRL7_REQPKT      0x00000020  // Request Packet
+#define USB_RXCSRL7_STALL       0x00000020  // Send STALL
+#define USB_RXCSRL7_FLUSH       0x00000010  // Flush FIFO
+#define USB_RXCSRL7_DATAERR     0x00000008  // Data Error
+#define USB_RXCSRL7_NAKTO       0x00000008  // NAK Timeout
+#define USB_RXCSRL7_ERROR       0x00000004  // Error
+#define USB_RXCSRL7_OVER        0x00000004  // Overrun
+#define USB_RXCSRL7_FULL        0x00000002  // FIFO Full
+#define USB_RXCSRL7_RXRDY       0x00000001  // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH7 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH7_AUTOCL      0x00000080  // Auto Clear
+#define USB_RXCSRH7_ISO         0x00000040  // Isochronous Transfers
+#define USB_RXCSRH7_AUTORQ      0x00000040  // Auto Request
+#define USB_RXCSRH7_DMAEN       0x00000020  // DMA Request Enable
+#define USB_RXCSRH7_PIDERR      0x00000010  // PID Error
+#define USB_RXCSRH7_DISNYET     0x00000010  // Disable NYET
+#define USB_RXCSRH7_DMAMOD      0x00000008  // DMA Request Mode
+#define USB_RXCSRH7_DTWE        0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH7_DT          0x00000002  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT7 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT7_COUNT_M    0x00001FFF  // Receive Packet Count
+#define USB_RXCOUNT7_COUNT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE7 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE7_SPEED_M     0x000000C0  // Operating Speed
+#define USB_TXTYPE7_SPEED_DFLT  0x00000000  // Default
+#define USB_TXTYPE7_SPEED_FULL  0x00000080  // Full
+#define USB_TXTYPE7_SPEED_LOW   0x000000C0  // Low
+#define USB_TXTYPE7_PROTO_M     0x00000030  // Protocol
+#define USB_TXTYPE7_PROTO_CTRL  0x00000000  // Control
+#define USB_TXTYPE7_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_TXTYPE7_PROTO_BULK  0x00000020  // Bulk
+#define USB_TXTYPE7_PROTO_INT   0x00000030  // Interrupt
+#define USB_TXTYPE7_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_TXTYPE7_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL7
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL7_TXPOLL_M \
+                                0x000000FF  // TX Polling
+#define USB_TXINTERVAL7_NAKLMT_M \
+                                0x000000FF  // NAK Limit
+#define USB_TXINTERVAL7_NAKLMT_S \
+                                0
+#define USB_TXINTERVAL7_TXPOLL_S \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE7 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE7_SPEED_M     0x000000C0  // Operating Speed
+#define USB_RXTYPE7_SPEED_DFLT  0x00000000  // Default
+#define USB_RXTYPE7_SPEED_FULL  0x00000080  // Full
+#define USB_RXTYPE7_SPEED_LOW   0x000000C0  // Low
+#define USB_RXTYPE7_PROTO_M     0x00000030  // Protocol
+#define USB_RXTYPE7_PROTO_CTRL  0x00000000  // Control
+#define USB_RXTYPE7_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_RXTYPE7_PROTO_BULK  0x00000020  // Bulk
+#define USB_RXTYPE7_PROTO_INT   0x00000030  // Interrupt
+#define USB_RXTYPE7_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_RXTYPE7_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL7
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL7_TXPOLL_M \
+                                0x000000FF  // RX Polling
+#define USB_RXINTERVAL7_NAKLMT_M \
+                                0x000000FF  // NAK Limit
+#define USB_RXINTERVAL7_NAKLMT_S \
+                                0
+#define USB_RXINTERVAL7_TXPOLL_S \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP8 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP8_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_TXMAXP8_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL8 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL8_NAKTO       0x00000080  // NAK Timeout
+#define USB_TXCSRL8_CLRDT       0x00000040  // Clear Data Toggle
+#define USB_TXCSRL8_STALLED     0x00000020  // Endpoint Stalled
+#define USB_TXCSRL8_STALL       0x00000010  // Send STALL
+#define USB_TXCSRL8_SETUP       0x00000010  // Setup Packet
+#define USB_TXCSRL8_FLUSH       0x00000008  // Flush FIFO
+#define USB_TXCSRL8_ERROR       0x00000004  // Error
+#define USB_TXCSRL8_UNDRN       0x00000004  // Underrun
+#define USB_TXCSRL8_FIFONE      0x00000002  // FIFO Not Empty
+#define USB_TXCSRL8_TXRDY       0x00000001  // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH8 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH8_AUTOSET     0x00000080  // Auto Set
+#define USB_TXCSRH8_ISO         0x00000040  // Isochronous Transfers
+#define USB_TXCSRH8_MODE        0x00000020  // Mode
+#define USB_TXCSRH8_DMAEN       0x00000010  // DMA Request Enable
+#define USB_TXCSRH8_FDT         0x00000008  // Force Data Toggle
+#define USB_TXCSRH8_DMAMOD      0x00000004  // DMA Request Mode
+#define USB_TXCSRH8_DTWE        0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH8_DT          0x00000001  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP8 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP8_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_RXMAXP8_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL8 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL8_CLRDT       0x00000080  // Clear Data Toggle
+#define USB_RXCSRL8_STALLED     0x00000040  // Endpoint Stalled
+#define USB_RXCSRL8_STALL       0x00000020  // Send STALL
+#define USB_RXCSRL8_REQPKT      0x00000020  // Request Packet
+#define USB_RXCSRL8_FLUSH       0x00000010  // Flush FIFO
+#define USB_RXCSRL8_NAKTO       0x00000008  // NAK Timeout
+#define USB_RXCSRL8_DATAERR     0x00000008  // Data Error
+#define USB_RXCSRL8_OVER        0x00000004  // Overrun
+#define USB_RXCSRL8_ERROR       0x00000004  // Error
+#define USB_RXCSRL8_FULL        0x00000002  // FIFO Full
+#define USB_RXCSRL8_RXRDY       0x00000001  // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH8 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH8_AUTOCL      0x00000080  // Auto Clear
+#define USB_RXCSRH8_AUTORQ      0x00000040  // Auto Request
+#define USB_RXCSRH8_ISO         0x00000040  // Isochronous Transfers
+#define USB_RXCSRH8_DMAEN       0x00000020  // DMA Request Enable
+#define USB_RXCSRH8_DISNYET     0x00000010  // Disable NYET
+#define USB_RXCSRH8_PIDERR      0x00000010  // PID Error
+#define USB_RXCSRH8_DMAMOD      0x00000008  // DMA Request Mode
+#define USB_RXCSRH8_DTWE        0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH8_DT          0x00000002  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT8 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT8_COUNT_M    0x00001FFF  // Receive Packet Count
+#define USB_RXCOUNT8_COUNT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE8 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE8_SPEED_M     0x000000C0  // Operating Speed
+#define USB_TXTYPE8_SPEED_DFLT  0x00000000  // Default
+#define USB_TXTYPE8_SPEED_FULL  0x00000080  // Full
+#define USB_TXTYPE8_SPEED_LOW   0x000000C0  // Low
+#define USB_TXTYPE8_PROTO_M     0x00000030  // Protocol
+#define USB_TXTYPE8_PROTO_CTRL  0x00000000  // Control
+#define USB_TXTYPE8_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_TXTYPE8_PROTO_BULK  0x00000020  // Bulk
+#define USB_TXTYPE8_PROTO_INT   0x00000030  // Interrupt
+#define USB_TXTYPE8_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_TXTYPE8_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL8
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL8_TXPOLL_M \
+                                0x000000FF  // TX Polling
+#define USB_TXINTERVAL8_NAKLMT_M \
+                                0x000000FF  // NAK Limit
+#define USB_TXINTERVAL8_NAKLMT_S \
+                                0
+#define USB_TXINTERVAL8_TXPOLL_S \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE8 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE8_SPEED_M     0x000000C0  // Operating Speed
+#define USB_RXTYPE8_SPEED_DFLT  0x00000000  // Default
+#define USB_RXTYPE8_SPEED_FULL  0x00000080  // Full
+#define USB_RXTYPE8_SPEED_LOW   0x000000C0  // Low
+#define USB_RXTYPE8_PROTO_M     0x00000030  // Protocol
+#define USB_RXTYPE8_PROTO_CTRL  0x00000000  // Control
+#define USB_RXTYPE8_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_RXTYPE8_PROTO_BULK  0x00000020  // Bulk
+#define USB_RXTYPE8_PROTO_INT   0x00000030  // Interrupt
+#define USB_RXTYPE8_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_RXTYPE8_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL8
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL8_NAKLMT_M \
+                                0x000000FF  // NAK Limit
+#define USB_RXINTERVAL8_TXPOLL_M \
+                                0x000000FF  // RX Polling
+#define USB_RXINTERVAL8_NAKLMT_S \
+                                0
+#define USB_RXINTERVAL8_TXPOLL_S \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP9 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP9_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_TXMAXP9_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL9 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL9_NAKTO       0x00000080  // NAK Timeout
+#define USB_TXCSRL9_CLRDT       0x00000040  // Clear Data Toggle
+#define USB_TXCSRL9_STALLED     0x00000020  // Endpoint Stalled
+#define USB_TXCSRL9_SETUP       0x00000010  // Setup Packet
+#define USB_TXCSRL9_STALL       0x00000010  // Send STALL
+#define USB_TXCSRL9_FLUSH       0x00000008  // Flush FIFO
+#define USB_TXCSRL9_ERROR       0x00000004  // Error
+#define USB_TXCSRL9_UNDRN       0x00000004  // Underrun
+#define USB_TXCSRL9_FIFONE      0x00000002  // FIFO Not Empty
+#define USB_TXCSRL9_TXRDY       0x00000001  // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH9 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH9_AUTOSET     0x00000080  // Auto Set
+#define USB_TXCSRH9_ISO         0x00000040  // Isochronous Transfers
+#define USB_TXCSRH9_MODE        0x00000020  // Mode
+#define USB_TXCSRH9_DMAEN       0x00000010  // DMA Request Enable
+#define USB_TXCSRH9_FDT         0x00000008  // Force Data Toggle
+#define USB_TXCSRH9_DMAMOD      0x00000004  // DMA Request Mode
+#define USB_TXCSRH9_DTWE        0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH9_DT          0x00000001  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP9 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP9_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_RXMAXP9_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL9 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL9_CLRDT       0x00000080  // Clear Data Toggle
+#define USB_RXCSRL9_STALLED     0x00000040  // Endpoint Stalled
+#define USB_RXCSRL9_STALL       0x00000020  // Send STALL
+#define USB_RXCSRL9_REQPKT      0x00000020  // Request Packet
+#define USB_RXCSRL9_FLUSH       0x00000010  // Flush FIFO
+#define USB_RXCSRL9_DATAERR     0x00000008  // Data Error
+#define USB_RXCSRL9_NAKTO       0x00000008  // NAK Timeout
+#define USB_RXCSRL9_ERROR       0x00000004  // Error
+#define USB_RXCSRL9_OVER        0x00000004  // Overrun
+#define USB_RXCSRL9_FULL        0x00000002  // FIFO Full
+#define USB_RXCSRL9_RXRDY       0x00000001  // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH9 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH9_AUTOCL      0x00000080  // Auto Clear
+#define USB_RXCSRH9_ISO         0x00000040  // Isochronous Transfers
+#define USB_RXCSRH9_AUTORQ      0x00000040  // Auto Request
+#define USB_RXCSRH9_DMAEN       0x00000020  // DMA Request Enable
+#define USB_RXCSRH9_PIDERR      0x00000010  // PID Error
+#define USB_RXCSRH9_DISNYET     0x00000010  // Disable NYET
+#define USB_RXCSRH9_DMAMOD      0x00000008  // DMA Request Mode
+#define USB_RXCSRH9_DTWE        0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH9_DT          0x00000002  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT9 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT9_COUNT_M    0x00001FFF  // Receive Packet Count
+#define USB_RXCOUNT9_COUNT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE9 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE9_SPEED_M     0x000000C0  // Operating Speed
+#define USB_TXTYPE9_SPEED_DFLT  0x00000000  // Default
+#define USB_TXTYPE9_SPEED_FULL  0x00000080  // Full
+#define USB_TXTYPE9_SPEED_LOW   0x000000C0  // Low
+#define USB_TXTYPE9_PROTO_M     0x00000030  // Protocol
+#define USB_TXTYPE9_PROTO_CTRL  0x00000000  // Control
+#define USB_TXTYPE9_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_TXTYPE9_PROTO_BULK  0x00000020  // Bulk
+#define USB_TXTYPE9_PROTO_INT   0x00000030  // Interrupt
+#define USB_TXTYPE9_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_TXTYPE9_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL9
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL9_TXPOLL_M \
+                                0x000000FF  // TX Polling
+#define USB_TXINTERVAL9_NAKLMT_M \
+                                0x000000FF  // NAK Limit
+#define USB_TXINTERVAL9_TXPOLL_S \
+                                0
+#define USB_TXINTERVAL9_NAKLMT_S \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE9 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE9_SPEED_M     0x000000C0  // Operating Speed
+#define USB_RXTYPE9_SPEED_DFLT  0x00000000  // Default
+#define USB_RXTYPE9_SPEED_FULL  0x00000080  // Full
+#define USB_RXTYPE9_SPEED_LOW   0x000000C0  // Low
+#define USB_RXTYPE9_PROTO_M     0x00000030  // Protocol
+#define USB_RXTYPE9_PROTO_CTRL  0x00000000  // Control
+#define USB_RXTYPE9_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_RXTYPE9_PROTO_BULK  0x00000020  // Bulk
+#define USB_RXTYPE9_PROTO_INT   0x00000030  // Interrupt
+#define USB_RXTYPE9_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_RXTYPE9_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL9
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL9_TXPOLL_M \
+                                0x000000FF  // RX Polling
+#define USB_RXINTERVAL9_NAKLMT_M \
+                                0x000000FF  // NAK Limit
+#define USB_RXINTERVAL9_NAKLMT_S \
+                                0
+#define USB_RXINTERVAL9_TXPOLL_S \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP10 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP10_MAXLOAD_M  0x000007FF  // Maximum Payload
+#define USB_TXMAXP10_MAXLOAD_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL10 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL10_NAKTO      0x00000080  // NAK Timeout
+#define USB_TXCSRL10_CLRDT      0x00000040  // Clear Data Toggle
+#define USB_TXCSRL10_STALLED    0x00000020  // Endpoint Stalled
+#define USB_TXCSRL10_SETUP      0x00000010  // Setup Packet
+#define USB_TXCSRL10_STALL      0x00000010  // Send STALL
+#define USB_TXCSRL10_FLUSH      0x00000008  // Flush FIFO
+#define USB_TXCSRL10_UNDRN      0x00000004  // Underrun
+#define USB_TXCSRL10_ERROR      0x00000004  // Error
+#define USB_TXCSRL10_FIFONE     0x00000002  // FIFO Not Empty
+#define USB_TXCSRL10_TXRDY      0x00000001  // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH10 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH10_AUTOSET    0x00000080  // Auto Set
+#define USB_TXCSRH10_ISO        0x00000040  // Isochronous Transfers
+#define USB_TXCSRH10_MODE       0x00000020  // Mode
+#define USB_TXCSRH10_DMAEN      0x00000010  // DMA Request Enable
+#define USB_TXCSRH10_FDT        0x00000008  // Force Data Toggle
+#define USB_TXCSRH10_DMAMOD     0x00000004  // DMA Request Mode
+#define USB_TXCSRH10_DTWE       0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH10_DT         0x00000001  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP10 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP10_MAXLOAD_M  0x000007FF  // Maximum Payload
+#define USB_RXMAXP10_MAXLOAD_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL10 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL10_CLRDT      0x00000080  // Clear Data Toggle
+#define USB_RXCSRL10_STALLED    0x00000040  // Endpoint Stalled
+#define USB_RXCSRL10_STALL      0x00000020  // Send STALL
+#define USB_RXCSRL10_REQPKT     0x00000020  // Request Packet
+#define USB_RXCSRL10_FLUSH      0x00000010  // Flush FIFO
+#define USB_RXCSRL10_NAKTO      0x00000008  // NAK Timeout
+#define USB_RXCSRL10_DATAERR    0x00000008  // Data Error
+#define USB_RXCSRL10_OVER       0x00000004  // Overrun
+#define USB_RXCSRL10_ERROR      0x00000004  // Error
+#define USB_RXCSRL10_FULL       0x00000002  // FIFO Full
+#define USB_RXCSRL10_RXRDY      0x00000001  // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH10 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH10_AUTOCL     0x00000080  // Auto Clear
+#define USB_RXCSRH10_AUTORQ     0x00000040  // Auto Request
+#define USB_RXCSRH10_ISO        0x00000040  // Isochronous Transfers
+#define USB_RXCSRH10_DMAEN      0x00000020  // DMA Request Enable
+#define USB_RXCSRH10_PIDERR     0x00000010  // PID Error
+#define USB_RXCSRH10_DISNYET    0x00000010  // Disable NYET
+#define USB_RXCSRH10_DMAMOD     0x00000008  // DMA Request Mode
+#define USB_RXCSRH10_DTWE       0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH10_DT         0x00000002  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT10
+// register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT10_COUNT_M   0x00001FFF  // Receive Packet Count
+#define USB_RXCOUNT10_COUNT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE10 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE10_SPEED_M    0x000000C0  // Operating Speed
+#define USB_TXTYPE10_SPEED_DFLT 0x00000000  // Default
+#define USB_TXTYPE10_SPEED_FULL 0x00000080  // Full
+#define USB_TXTYPE10_SPEED_LOW  0x000000C0  // Low
+#define USB_TXTYPE10_PROTO_M    0x00000030  // Protocol
+#define USB_TXTYPE10_PROTO_CTRL 0x00000000  // Control
+#define USB_TXTYPE10_PROTO_ISOC 0x00000010  // Isochronous
+#define USB_TXTYPE10_PROTO_BULK 0x00000020  // Bulk
+#define USB_TXTYPE10_PROTO_INT  0x00000030  // Interrupt
+#define USB_TXTYPE10_TEP_M      0x0000000F  // Target Endpoint Number
+#define USB_TXTYPE10_TEP_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL10
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL10_NAKLMT_M \
+                                0x000000FF  // NAK Limit
+#define USB_TXINTERVAL10_TXPOLL_M \
+                                0x000000FF  // TX Polling
+#define USB_TXINTERVAL10_TXPOLL_S \
+                                0
+#define USB_TXINTERVAL10_NAKLMT_S \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE10 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE10_SPEED_M    0x000000C0  // Operating Speed
+#define USB_RXTYPE10_SPEED_DFLT 0x00000000  // Default
+#define USB_RXTYPE10_SPEED_FULL 0x00000080  // Full
+#define USB_RXTYPE10_SPEED_LOW  0x000000C0  // Low
+#define USB_RXTYPE10_PROTO_M    0x00000030  // Protocol
+#define USB_RXTYPE10_PROTO_CTRL 0x00000000  // Control
+#define USB_RXTYPE10_PROTO_ISOC 0x00000010  // Isochronous
+#define USB_RXTYPE10_PROTO_BULK 0x00000020  // Bulk
+#define USB_RXTYPE10_PROTO_INT  0x00000030  // Interrupt
+#define USB_RXTYPE10_TEP_M      0x0000000F  // Target Endpoint Number
+#define USB_RXTYPE10_TEP_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL10
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL10_NAKLMT_M \
+                                0x000000FF  // NAK Limit
+#define USB_RXINTERVAL10_TXPOLL_M \
+                                0x000000FF  // RX Polling
+#define USB_RXINTERVAL10_TXPOLL_S \
+                                0
+#define USB_RXINTERVAL10_NAKLMT_S \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP11 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP11_MAXLOAD_M  0x000007FF  // Maximum Payload
+#define USB_TXMAXP11_MAXLOAD_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL11 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL11_NAKTO      0x00000080  // NAK Timeout
+#define USB_TXCSRL11_CLRDT      0x00000040  // Clear Data Toggle
+#define USB_TXCSRL11_STALLED    0x00000020  // Endpoint Stalled
+#define USB_TXCSRL11_STALL      0x00000010  // Send STALL
+#define USB_TXCSRL11_SETUP      0x00000010  // Setup Packet
+#define USB_TXCSRL11_FLUSH      0x00000008  // Flush FIFO
+#define USB_TXCSRL11_ERROR      0x00000004  // Error
+#define USB_TXCSRL11_UNDRN      0x00000004  // Underrun
+#define USB_TXCSRL11_FIFONE     0x00000002  // FIFO Not Empty
+#define USB_TXCSRL11_TXRDY      0x00000001  // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH11 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH11_AUTOSET    0x00000080  // Auto Set
+#define USB_TXCSRH11_ISO        0x00000040  // Isochronous Transfers
+#define USB_TXCSRH11_MODE       0x00000020  // Mode
+#define USB_TXCSRH11_DMAEN      0x00000010  // DMA Request Enable
+#define USB_TXCSRH11_FDT        0x00000008  // Force Data Toggle
+#define USB_TXCSRH11_DMAMOD     0x00000004  // DMA Request Mode
+#define USB_TXCSRH11_DTWE       0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH11_DT         0x00000001  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP11 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP11_MAXLOAD_M  0x000007FF  // Maximum Payload
+#define USB_RXMAXP11_MAXLOAD_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL11 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL11_CLRDT      0x00000080  // Clear Data Toggle
+#define USB_RXCSRL11_STALLED    0x00000040  // Endpoint Stalled
+#define USB_RXCSRL11_STALL      0x00000020  // Send STALL
+#define USB_RXCSRL11_REQPKT     0x00000020  // Request Packet
+#define USB_RXCSRL11_FLUSH      0x00000010  // Flush FIFO
+#define USB_RXCSRL11_DATAERR    0x00000008  // Data Error
+#define USB_RXCSRL11_NAKTO      0x00000008  // NAK Timeout
+#define USB_RXCSRL11_OVER       0x00000004  // Overrun
+#define USB_RXCSRL11_ERROR      0x00000004  // Error
+#define USB_RXCSRL11_FULL       0x00000002  // FIFO Full
+#define USB_RXCSRL11_RXRDY      0x00000001  // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH11 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH11_AUTOCL     0x00000080  // Auto Clear
+#define USB_RXCSRH11_ISO        0x00000040  // Isochronous Transfers
+#define USB_RXCSRH11_AUTORQ     0x00000040  // Auto Request
+#define USB_RXCSRH11_DMAEN      0x00000020  // DMA Request Enable
+#define USB_RXCSRH11_DISNYET    0x00000010  // Disable NYET
+#define USB_RXCSRH11_PIDERR     0x00000010  // PID Error
+#define USB_RXCSRH11_DMAMOD     0x00000008  // DMA Request Mode
+#define USB_RXCSRH11_DTWE       0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH11_DT         0x00000002  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT11
+// register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT11_COUNT_M   0x00001FFF  // Receive Packet Count
+#define USB_RXCOUNT11_COUNT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE11 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE11_SPEED_M    0x000000C0  // Operating Speed
+#define USB_TXTYPE11_SPEED_DFLT 0x00000000  // Default
+#define USB_TXTYPE11_SPEED_FULL 0x00000080  // Full
+#define USB_TXTYPE11_SPEED_LOW  0x000000C0  // Low
+#define USB_TXTYPE11_PROTO_M    0x00000030  // Protocol
+#define USB_TXTYPE11_PROTO_CTRL 0x00000000  // Control
+#define USB_TXTYPE11_PROTO_ISOC 0x00000010  // Isochronous
+#define USB_TXTYPE11_PROTO_BULK 0x00000020  // Bulk
+#define USB_TXTYPE11_PROTO_INT  0x00000030  // Interrupt
+#define USB_TXTYPE11_TEP_M      0x0000000F  // Target Endpoint Number
+#define USB_TXTYPE11_TEP_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL11
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL11_TXPOLL_M \
+                                0x000000FF  // TX Polling
+#define USB_TXINTERVAL11_NAKLMT_M \
+                                0x000000FF  // NAK Limit
+#define USB_TXINTERVAL11_NAKLMT_S \
+                                0
+#define USB_TXINTERVAL11_TXPOLL_S \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE11 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE11_SPEED_M    0x000000C0  // Operating Speed
+#define USB_RXTYPE11_SPEED_DFLT 0x00000000  // Default
+#define USB_RXTYPE11_SPEED_FULL 0x00000080  // Full
+#define USB_RXTYPE11_SPEED_LOW  0x000000C0  // Low
+#define USB_RXTYPE11_PROTO_M    0x00000030  // Protocol
+#define USB_RXTYPE11_PROTO_CTRL 0x00000000  // Control
+#define USB_RXTYPE11_PROTO_ISOC 0x00000010  // Isochronous
+#define USB_RXTYPE11_PROTO_BULK 0x00000020  // Bulk
+#define USB_RXTYPE11_PROTO_INT  0x00000030  // Interrupt
+#define USB_RXTYPE11_TEP_M      0x0000000F  // Target Endpoint Number
+#define USB_RXTYPE11_TEP_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL11
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL11_NAKLMT_M \
+                                0x000000FF  // NAK Limit
+#define USB_RXINTERVAL11_TXPOLL_M \
+                                0x000000FF  // RX Polling
+#define USB_RXINTERVAL11_TXPOLL_S \
+                                0
+#define USB_RXINTERVAL11_NAKLMT_S \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP12 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP12_MAXLOAD_M  0x000007FF  // Maximum Payload
+#define USB_TXMAXP12_MAXLOAD_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL12 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL12_NAKTO      0x00000080  // NAK Timeout
+#define USB_TXCSRL12_CLRDT      0x00000040  // Clear Data Toggle
+#define USB_TXCSRL12_STALLED    0x00000020  // Endpoint Stalled
+#define USB_TXCSRL12_SETUP      0x00000010  // Setup Packet
+#define USB_TXCSRL12_STALL      0x00000010  // Send STALL
+#define USB_TXCSRL12_FLUSH      0x00000008  // Flush FIFO
+#define USB_TXCSRL12_UNDRN      0x00000004  // Underrun
+#define USB_TXCSRL12_ERROR      0x00000004  // Error
+#define USB_TXCSRL12_FIFONE     0x00000002  // FIFO Not Empty
+#define USB_TXCSRL12_TXRDY      0x00000001  // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH12 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH12_AUTOSET    0x00000080  // Auto Set
+#define USB_TXCSRH12_ISO        0x00000040  // Isochronous Transfers
+#define USB_TXCSRH12_MODE       0x00000020  // Mode
+#define USB_TXCSRH12_DMAEN      0x00000010  // DMA Request Enable
+#define USB_TXCSRH12_FDT        0x00000008  // Force Data Toggle
+#define USB_TXCSRH12_DMAMOD     0x00000004  // DMA Request Mode
+#define USB_TXCSRH12_DTWE       0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH12_DT         0x00000001  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP12 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP12_MAXLOAD_M  0x000007FF  // Maximum Payload
+#define USB_RXMAXP12_MAXLOAD_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL12 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL12_CLRDT      0x00000080  // Clear Data Toggle
+#define USB_RXCSRL12_STALLED    0x00000040  // Endpoint Stalled
+#define USB_RXCSRL12_STALL      0x00000020  // Send STALL
+#define USB_RXCSRL12_REQPKT     0x00000020  // Request Packet
+#define USB_RXCSRL12_FLUSH      0x00000010  // Flush FIFO
+#define USB_RXCSRL12_NAKTO      0x00000008  // NAK Timeout
+#define USB_RXCSRL12_DATAERR    0x00000008  // Data Error
+#define USB_RXCSRL12_ERROR      0x00000004  // Error
+#define USB_RXCSRL12_OVER       0x00000004  // Overrun
+#define USB_RXCSRL12_FULL       0x00000002  // FIFO Full
+#define USB_RXCSRL12_RXRDY      0x00000001  // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH12 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH12_AUTOCL     0x00000080  // Auto Clear
+#define USB_RXCSRH12_ISO        0x00000040  // Isochronous Transfers
+#define USB_RXCSRH12_AUTORQ     0x00000040  // Auto Request
+#define USB_RXCSRH12_DMAEN      0x00000020  // DMA Request Enable
+#define USB_RXCSRH12_PIDERR     0x00000010  // PID Error
+#define USB_RXCSRH12_DISNYET    0x00000010  // Disable NYET
+#define USB_RXCSRH12_DMAMOD     0x00000008  // DMA Request Mode
+#define USB_RXCSRH12_DTWE       0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH12_DT         0x00000002  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT12
+// register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT12_COUNT_M   0x00001FFF  // Receive Packet Count
+#define USB_RXCOUNT12_COUNT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE12 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE12_SPEED_M    0x000000C0  // Operating Speed
+#define USB_TXTYPE12_SPEED_DFLT 0x00000000  // Default
+#define USB_TXTYPE12_SPEED_FULL 0x00000080  // Full
+#define USB_TXTYPE12_SPEED_LOW  0x000000C0  // Low
+#define USB_TXTYPE12_PROTO_M    0x00000030  // Protocol
+#define USB_TXTYPE12_PROTO_CTRL 0x00000000  // Control
+#define USB_TXTYPE12_PROTO_ISOC 0x00000010  // Isochronous
+#define USB_TXTYPE12_PROTO_BULK 0x00000020  // Bulk
+#define USB_TXTYPE12_PROTO_INT  0x00000030  // Interrupt
+#define USB_TXTYPE12_TEP_M      0x0000000F  // Target Endpoint Number
+#define USB_TXTYPE12_TEP_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL12
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL12_TXPOLL_M \
+                                0x000000FF  // TX Polling
+#define USB_TXINTERVAL12_NAKLMT_M \
+                                0x000000FF  // NAK Limit
+#define USB_TXINTERVAL12_TXPOLL_S \
+                                0
+#define USB_TXINTERVAL12_NAKLMT_S \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE12 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE12_SPEED_M    0x000000C0  // Operating Speed
+#define USB_RXTYPE12_SPEED_DFLT 0x00000000  // Default
+#define USB_RXTYPE12_SPEED_FULL 0x00000080  // Full
+#define USB_RXTYPE12_SPEED_LOW  0x000000C0  // Low
+#define USB_RXTYPE12_PROTO_M    0x00000030  // Protocol
+#define USB_RXTYPE12_PROTO_CTRL 0x00000000  // Control
+#define USB_RXTYPE12_PROTO_ISOC 0x00000010  // Isochronous
+#define USB_RXTYPE12_PROTO_BULK 0x00000020  // Bulk
+#define USB_RXTYPE12_PROTO_INT  0x00000030  // Interrupt
+#define USB_RXTYPE12_TEP_M      0x0000000F  // Target Endpoint Number
+#define USB_RXTYPE12_TEP_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL12
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL12_NAKLMT_M \
+                                0x000000FF  // NAK Limit
+#define USB_RXINTERVAL12_TXPOLL_M \
+                                0x000000FF  // RX Polling
+#define USB_RXINTERVAL12_NAKLMT_S \
+                                0
+#define USB_RXINTERVAL12_TXPOLL_S \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP13 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP13_MAXLOAD_M  0x000007FF  // Maximum Payload
+#define USB_TXMAXP13_MAXLOAD_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL13 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL13_NAKTO      0x00000080  // NAK Timeout
+#define USB_TXCSRL13_CLRDT      0x00000040  // Clear Data Toggle
+#define USB_TXCSRL13_STALLED    0x00000020  // Endpoint Stalled
+#define USB_TXCSRL13_SETUP      0x00000010  // Setup Packet
+#define USB_TXCSRL13_STALL      0x00000010  // Send STALL
+#define USB_TXCSRL13_FLUSH      0x00000008  // Flush FIFO
+#define USB_TXCSRL13_UNDRN      0x00000004  // Underrun
+#define USB_TXCSRL13_ERROR      0x00000004  // Error
+#define USB_TXCSRL13_FIFONE     0x00000002  // FIFO Not Empty
+#define USB_TXCSRL13_TXRDY      0x00000001  // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH13 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH13_AUTOSET    0x00000080  // Auto Set
+#define USB_TXCSRH13_ISO        0x00000040  // Isochronous Transfers
+#define USB_TXCSRH13_MODE       0x00000020  // Mode
+#define USB_TXCSRH13_DMAEN      0x00000010  // DMA Request Enable
+#define USB_TXCSRH13_FDT        0x00000008  // Force Data Toggle
+#define USB_TXCSRH13_DMAMOD     0x00000004  // DMA Request Mode
+#define USB_TXCSRH13_DTWE       0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH13_DT         0x00000001  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP13 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP13_MAXLOAD_M  0x000007FF  // Maximum Payload
+#define USB_RXMAXP13_MAXLOAD_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL13 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL13_CLRDT      0x00000080  // Clear Data Toggle
+#define USB_RXCSRL13_STALLED    0x00000040  // Endpoint Stalled
+#define USB_RXCSRL13_REQPKT     0x00000020  // Request Packet
+#define USB_RXCSRL13_STALL      0x00000020  // Send STALL
+#define USB_RXCSRL13_FLUSH      0x00000010  // Flush FIFO
+#define USB_RXCSRL13_NAKTO      0x00000008  // NAK Timeout
+#define USB_RXCSRL13_DATAERR    0x00000008  // Data Error
+#define USB_RXCSRL13_OVER       0x00000004  // Overrun
+#define USB_RXCSRL13_ERROR      0x00000004  // Error
+#define USB_RXCSRL13_FULL       0x00000002  // FIFO Full
+#define USB_RXCSRL13_RXRDY      0x00000001  // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH13 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH13_AUTOCL     0x00000080  // Auto Clear
+#define USB_RXCSRH13_ISO        0x00000040  // Isochronous Transfers
+#define USB_RXCSRH13_AUTORQ     0x00000040  // Auto Request
+#define USB_RXCSRH13_DMAEN      0x00000020  // DMA Request Enable
+#define USB_RXCSRH13_DISNYET    0x00000010  // Disable NYET
+#define USB_RXCSRH13_PIDERR     0x00000010  // PID Error
+#define USB_RXCSRH13_DMAMOD     0x00000008  // DMA Request Mode
+#define USB_RXCSRH13_DTWE       0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH13_DT         0x00000002  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT13
+// register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT13_COUNT_M   0x00001FFF  // Receive Packet Count
+#define USB_RXCOUNT13_COUNT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE13 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE13_SPEED_M    0x000000C0  // Operating Speed
+#define USB_TXTYPE13_SPEED_DFLT 0x00000000  // Default
+#define USB_TXTYPE13_SPEED_FULL 0x00000080  // Full
+#define USB_TXTYPE13_SPEED_LOW  0x000000C0  // Low
+#define USB_TXTYPE13_PROTO_M    0x00000030  // Protocol
+#define USB_TXTYPE13_PROTO_CTRL 0x00000000  // Control
+#define USB_TXTYPE13_PROTO_ISOC 0x00000010  // Isochronous
+#define USB_TXTYPE13_PROTO_BULK 0x00000020  // Bulk
+#define USB_TXTYPE13_PROTO_INT  0x00000030  // Interrupt
+#define USB_TXTYPE13_TEP_M      0x0000000F  // Target Endpoint Number
+#define USB_TXTYPE13_TEP_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL13
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL13_NAKLMT_M \
+                                0x000000FF  // NAK Limit
+#define USB_TXINTERVAL13_TXPOLL_M \
+                                0x000000FF  // TX Polling
+#define USB_TXINTERVAL13_TXPOLL_S \
+                                0
+#define USB_TXINTERVAL13_NAKLMT_S \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE13 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE13_SPEED_M    0x000000C0  // Operating Speed
+#define USB_RXTYPE13_SPEED_DFLT 0x00000000  // Default
+#define USB_RXTYPE13_SPEED_FULL 0x00000080  // Full
+#define USB_RXTYPE13_SPEED_LOW  0x000000C0  // Low
+#define USB_RXTYPE13_PROTO_M    0x00000030  // Protocol
+#define USB_RXTYPE13_PROTO_CTRL 0x00000000  // Control
+#define USB_RXTYPE13_PROTO_ISOC 0x00000010  // Isochronous
+#define USB_RXTYPE13_PROTO_BULK 0x00000020  // Bulk
+#define USB_RXTYPE13_PROTO_INT  0x00000030  // Interrupt
+#define USB_RXTYPE13_TEP_M      0x0000000F  // Target Endpoint Number
+#define USB_RXTYPE13_TEP_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL13
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL13_TXPOLL_M \
+                                0x000000FF  // RX Polling
+#define USB_RXINTERVAL13_NAKLMT_M \
+                                0x000000FF  // NAK Limit
+#define USB_RXINTERVAL13_TXPOLL_S \
+                                0
+#define USB_RXINTERVAL13_NAKLMT_S \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP14 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP14_MAXLOAD_M  0x000007FF  // Maximum Payload
+#define USB_TXMAXP14_MAXLOAD_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL14 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL14_NAKTO      0x00000080  // NAK Timeout
+#define USB_TXCSRL14_CLRDT      0x00000040  // Clear Data Toggle
+#define USB_TXCSRL14_STALLED    0x00000020  // Endpoint Stalled
+#define USB_TXCSRL14_STALL      0x00000010  // Send STALL
+#define USB_TXCSRL14_SETUP      0x00000010  // Setup Packet
+#define USB_TXCSRL14_FLUSH      0x00000008  // Flush FIFO
+#define USB_TXCSRL14_ERROR      0x00000004  // Error
+#define USB_TXCSRL14_UNDRN      0x00000004  // Underrun
+#define USB_TXCSRL14_FIFONE     0x00000002  // FIFO Not Empty
+#define USB_TXCSRL14_TXRDY      0x00000001  // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH14 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH14_AUTOSET    0x00000080  // Auto Set
+#define USB_TXCSRH14_ISO        0x00000040  // Isochronous Transfers
+#define USB_TXCSRH14_MODE       0x00000020  // Mode
+#define USB_TXCSRH14_DMAEN      0x00000010  // DMA Request Enable
+#define USB_TXCSRH14_FDT        0x00000008  // Force Data Toggle
+#define USB_TXCSRH14_DMAMOD     0x00000004  // DMA Request Mode
+#define USB_TXCSRH14_DTWE       0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH14_DT         0x00000001  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP14 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP14_MAXLOAD_M  0x000007FF  // Maximum Payload
+#define USB_RXMAXP14_MAXLOAD_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL14 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL14_CLRDT      0x00000080  // Clear Data Toggle
+#define USB_RXCSRL14_STALLED    0x00000040  // Endpoint Stalled
+#define USB_RXCSRL14_REQPKT     0x00000020  // Request Packet
+#define USB_RXCSRL14_STALL      0x00000020  // Send STALL
+#define USB_RXCSRL14_FLUSH      0x00000010  // Flush FIFO
+#define USB_RXCSRL14_DATAERR    0x00000008  // Data Error
+#define USB_RXCSRL14_NAKTO      0x00000008  // NAK Timeout
+#define USB_RXCSRL14_OVER       0x00000004  // Overrun
+#define USB_RXCSRL14_ERROR      0x00000004  // Error
+#define USB_RXCSRL14_FULL       0x00000002  // FIFO Full
+#define USB_RXCSRL14_RXRDY      0x00000001  // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH14 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH14_AUTOCL     0x00000080  // Auto Clear
+#define USB_RXCSRH14_AUTORQ     0x00000040  // Auto Request
+#define USB_RXCSRH14_ISO        0x00000040  // Isochronous Transfers
+#define USB_RXCSRH14_DMAEN      0x00000020  // DMA Request Enable
+#define USB_RXCSRH14_PIDERR     0x00000010  // PID Error
+#define USB_RXCSRH14_DISNYET    0x00000010  // Disable NYET
+#define USB_RXCSRH14_DMAMOD     0x00000008  // DMA Request Mode
+#define USB_RXCSRH14_DTWE       0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH14_DT         0x00000002  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT14
+// register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT14_COUNT_M   0x00001FFF  // Receive Packet Count
+#define USB_RXCOUNT14_COUNT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE14 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE14_SPEED_M    0x000000C0  // Operating Speed
+#define USB_TXTYPE14_SPEED_DFLT 0x00000000  // Default
+#define USB_TXTYPE14_SPEED_FULL 0x00000080  // Full
+#define USB_TXTYPE14_SPEED_LOW  0x000000C0  // Low
+#define USB_TXTYPE14_PROTO_M    0x00000030  // Protocol
+#define USB_TXTYPE14_PROTO_CTRL 0x00000000  // Control
+#define USB_TXTYPE14_PROTO_ISOC 0x00000010  // Isochronous
+#define USB_TXTYPE14_PROTO_BULK 0x00000020  // Bulk
+#define USB_TXTYPE14_PROTO_INT  0x00000030  // Interrupt
+#define USB_TXTYPE14_TEP_M      0x0000000F  // Target Endpoint Number
+#define USB_TXTYPE14_TEP_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL14
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL14_TXPOLL_M \
+                                0x000000FF  // TX Polling
+#define USB_TXINTERVAL14_NAKLMT_M \
+                                0x000000FF  // NAK Limit
+#define USB_TXINTERVAL14_TXPOLL_S \
+                                0
+#define USB_TXINTERVAL14_NAKLMT_S \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE14 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE14_SPEED_M    0x000000C0  // Operating Speed
+#define USB_RXTYPE14_SPEED_DFLT 0x00000000  // Default
+#define USB_RXTYPE14_SPEED_FULL 0x00000080  // Full
+#define USB_RXTYPE14_SPEED_LOW  0x000000C0  // Low
+#define USB_RXTYPE14_PROTO_M    0x00000030  // Protocol
+#define USB_RXTYPE14_PROTO_CTRL 0x00000000  // Control
+#define USB_RXTYPE14_PROTO_ISOC 0x00000010  // Isochronous
+#define USB_RXTYPE14_PROTO_BULK 0x00000020  // Bulk
+#define USB_RXTYPE14_PROTO_INT  0x00000030  // Interrupt
+#define USB_RXTYPE14_TEP_M      0x0000000F  // Target Endpoint Number
+#define USB_RXTYPE14_TEP_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL14
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL14_TXPOLL_M \
+                                0x000000FF  // RX Polling
+#define USB_RXINTERVAL14_NAKLMT_M \
+                                0x000000FF  // NAK Limit
+#define USB_RXINTERVAL14_TXPOLL_S \
+                                0
+#define USB_RXINTERVAL14_NAKLMT_S \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP15 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP15_MAXLOAD_M  0x000007FF  // Maximum Payload
+#define USB_TXMAXP15_MAXLOAD_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL15 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL15_NAKTO      0x00000080  // NAK Timeout
+#define USB_TXCSRL15_CLRDT      0x00000040  // Clear Data Toggle
+#define USB_TXCSRL15_STALLED    0x00000020  // Endpoint Stalled
+#define USB_TXCSRL15_SETUP      0x00000010  // Setup Packet
+#define USB_TXCSRL15_STALL      0x00000010  // Send STALL
+#define USB_TXCSRL15_FLUSH      0x00000008  // Flush FIFO
+#define USB_TXCSRL15_UNDRN      0x00000004  // Underrun
+#define USB_TXCSRL15_ERROR      0x00000004  // Error
+#define USB_TXCSRL15_FIFONE     0x00000002  // FIFO Not Empty
+#define USB_TXCSRL15_TXRDY      0x00000001  // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH15 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH15_AUTOSET    0x00000080  // Auto Set
+#define USB_TXCSRH15_ISO        0x00000040  // Isochronous Transfers
+#define USB_TXCSRH15_MODE       0x00000020  // Mode
+#define USB_TXCSRH15_DMAEN      0x00000010  // DMA Request Enable
+#define USB_TXCSRH15_FDT        0x00000008  // Force Data Toggle
+#define USB_TXCSRH15_DMAMOD     0x00000004  // DMA Request Mode
+#define USB_TXCSRH15_DTWE       0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH15_DT         0x00000001  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP15 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP15_MAXLOAD_M  0x000007FF  // Maximum Payload
+#define USB_RXMAXP15_MAXLOAD_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL15 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL15_CLRDT      0x00000080  // Clear Data Toggle
+#define USB_RXCSRL15_STALLED    0x00000040  // Endpoint Stalled
+#define USB_RXCSRL15_STALL      0x00000020  // Send STALL
+#define USB_RXCSRL15_REQPKT     0x00000020  // Request Packet
+#define USB_RXCSRL15_FLUSH      0x00000010  // Flush FIFO
+#define USB_RXCSRL15_DATAERR    0x00000008  // Data Error
+#define USB_RXCSRL15_NAKTO      0x00000008  // NAK Timeout
+#define USB_RXCSRL15_ERROR      0x00000004  // Error
+#define USB_RXCSRL15_OVER       0x00000004  // Overrun
+#define USB_RXCSRL15_FULL       0x00000002  // FIFO Full
+#define USB_RXCSRL15_RXRDY      0x00000001  // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH15 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH15_AUTOCL     0x00000080  // Auto Clear
+#define USB_RXCSRH15_AUTORQ     0x00000040  // Auto Request
+#define USB_RXCSRH15_ISO        0x00000040  // Isochronous Transfers
+#define USB_RXCSRH15_DMAEN      0x00000020  // DMA Request Enable
+#define USB_RXCSRH15_PIDERR     0x00000010  // PID Error
+#define USB_RXCSRH15_DISNYET    0x00000010  // Disable NYET
+#define USB_RXCSRH15_DMAMOD     0x00000008  // DMA Request Mode
+#define USB_RXCSRH15_DTWE       0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH15_DT         0x00000002  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT15
+// register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT15_COUNT_M   0x00001FFF  // Receive Packet Count
+#define USB_RXCOUNT15_COUNT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE15 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE15_SPEED_M    0x000000C0  // Operating Speed
+#define USB_TXTYPE15_SPEED_DFLT 0x00000000  // Default
+#define USB_TXTYPE15_SPEED_FULL 0x00000080  // Full
+#define USB_TXTYPE15_SPEED_LOW  0x000000C0  // Low
+#define USB_TXTYPE15_PROTO_M    0x00000030  // Protocol
+#define USB_TXTYPE15_PROTO_CTRL 0x00000000  // Control
+#define USB_TXTYPE15_PROTO_ISOC 0x00000010  // Isochronous
+#define USB_TXTYPE15_PROTO_BULK 0x00000020  // Bulk
+#define USB_TXTYPE15_PROTO_INT  0x00000030  // Interrupt
+#define USB_TXTYPE15_TEP_M      0x0000000F  // Target Endpoint Number
+#define USB_TXTYPE15_TEP_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL15
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL15_TXPOLL_M \
+                                0x000000FF  // TX Polling
+#define USB_TXINTERVAL15_NAKLMT_M \
+                                0x000000FF  // NAK Limit
+#define USB_TXINTERVAL15_NAKLMT_S \
+                                0
+#define USB_TXINTERVAL15_TXPOLL_S \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE15 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE15_SPEED_M    0x000000C0  // Operating Speed
+#define USB_RXTYPE15_SPEED_DFLT 0x00000000  // Default
+#define USB_RXTYPE15_SPEED_FULL 0x00000080  // Full
+#define USB_RXTYPE15_SPEED_LOW  0x000000C0  // Low
+#define USB_RXTYPE15_PROTO_M    0x00000030  // Protocol
+#define USB_RXTYPE15_PROTO_CTRL 0x00000000  // Control
+#define USB_RXTYPE15_PROTO_ISOC 0x00000010  // Isochronous
+#define USB_RXTYPE15_PROTO_BULK 0x00000020  // Bulk
+#define USB_RXTYPE15_PROTO_INT  0x00000030  // Interrupt
+#define USB_RXTYPE15_TEP_M      0x0000000F  // Target Endpoint Number
+#define USB_RXTYPE15_TEP_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL15
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL15_TXPOLL_M \
+                                0x000000FF  // RX Polling
+#define USB_RXINTERVAL15_NAKLMT_M \
+                                0x000000FF  // NAK Limit
+#define USB_RXINTERVAL15_TXPOLL_S \
+                                0
+#define USB_RXINTERVAL15_NAKLMT_S \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT1
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT1_M       0x0000FFFF  // Block Transfer Packet Count
+#define USB_RQPKTCOUNT1_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT2
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT2_M       0x0000FFFF  // Block Transfer Packet Count
+#define USB_RQPKTCOUNT2_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT3
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT3_M       0x0000FFFF  // Block Transfer Packet Count
+#define USB_RQPKTCOUNT3_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT4
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT4_COUNT_M 0x0000FFFF  // Block Transfer Packet Count
+#define USB_RQPKTCOUNT4_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT5
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT5_COUNT_M 0x0000FFFF  // Block Transfer Packet Count
+#define USB_RQPKTCOUNT5_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT6
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT6_COUNT_M 0x0000FFFF  // Block Transfer Packet Count
+#define USB_RQPKTCOUNT6_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT7
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT7_COUNT_M 0x0000FFFF  // Block Transfer Packet Count
+#define USB_RQPKTCOUNT7_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT8
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT8_COUNT_M 0x0000FFFF  // Block Transfer Packet Count
+#define USB_RQPKTCOUNT8_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT9
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT9_COUNT_M 0x0000FFFF  // Block Transfer Packet Count
+#define USB_RQPKTCOUNT9_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT10
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT10_COUNT_M \
+                                0x0000FFFF  // Block Transfer Packet Count
+#define USB_RQPKTCOUNT10_COUNT_S \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT11
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT11_COUNT_M \
+                                0x0000FFFF  // Block Transfer Packet Count
+#define USB_RQPKTCOUNT11_COUNT_S \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT12
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT12_COUNT_M \
+                                0x0000FFFF  // Block Transfer Packet Count
+#define USB_RQPKTCOUNT12_COUNT_S \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT13
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT13_COUNT_M \
+                                0x0000FFFF  // Block Transfer Packet Count
+#define USB_RQPKTCOUNT13_COUNT_S \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT14
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT14_COUNT_M \
+                                0x0000FFFF  // Block Transfer Packet Count
+#define USB_RQPKTCOUNT14_COUNT_S \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT15
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT15_COUNT_M \
+                                0x0000FFFF  // Block Transfer Packet Count
+#define USB_RQPKTCOUNT15_COUNT_S \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXDPKTBUFDIS
+// register.
+//
+//*****************************************************************************
+#define USB_RXDPKTBUFDIS_EP15   0x00008000  // EP15 RX Double-Packet Buffer
+                                            // Disable
+#define USB_RXDPKTBUFDIS_EP14   0x00004000  // EP14 RX Double-Packet Buffer
+                                            // Disable
+#define USB_RXDPKTBUFDIS_EP13   0x00002000  // EP13 RX Double-Packet Buffer
+                                            // Disable
+#define USB_RXDPKTBUFDIS_EP12   0x00001000  // EP12 RX Double-Packet Buffer
+                                            // Disable
+#define USB_RXDPKTBUFDIS_EP11   0x00000800  // EP11 RX Double-Packet Buffer
+                                            // Disable
+#define USB_RXDPKTBUFDIS_EP10   0x00000400  // EP10 RX Double-Packet Buffer
+                                            // Disable
+#define USB_RXDPKTBUFDIS_EP9    0x00000200  // EP9 RX Double-Packet Buffer
+                                            // Disable
+#define USB_RXDPKTBUFDIS_EP8    0x00000100  // EP8 RX Double-Packet Buffer
+                                            // Disable
+#define USB_RXDPKTBUFDIS_EP7    0x00000080  // EP7 RX Double-Packet Buffer
+                                            // Disable
+#define USB_RXDPKTBUFDIS_EP6    0x00000040  // EP6 RX Double-Packet Buffer
+                                            // Disable
+#define USB_RXDPKTBUFDIS_EP5    0x00000020  // EP5 RX Double-Packet Buffer
+                                            // Disable
+#define USB_RXDPKTBUFDIS_EP4    0x00000010  // EP4 RX Double-Packet Buffer
+                                            // Disable
+#define USB_RXDPKTBUFDIS_EP3    0x00000008  // EP3 RX Double-Packet Buffer
+                                            // Disable
+#define USB_RXDPKTBUFDIS_EP2    0x00000004  // EP2 RX Double-Packet Buffer
+                                            // Disable
+#define USB_RXDPKTBUFDIS_EP1    0x00000002  // EP1 RX Double-Packet Buffer
+                                            // Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXDPKTBUFDIS
+// register.
+//
+//*****************************************************************************
+#define USB_TXDPKTBUFDIS_EP15   0x00008000  // EP15 TX Double-Packet Buffer
+                                            // Disable
+#define USB_TXDPKTBUFDIS_EP14   0x00004000  // EP14 TX Double-Packet Buffer
+                                            // Disable
+#define USB_TXDPKTBUFDIS_EP13   0x00002000  // EP13 TX Double-Packet Buffer
+                                            // Disable
+#define USB_TXDPKTBUFDIS_EP12   0x00001000  // EP12 TX Double-Packet Buffer
+                                            // Disable
+#define USB_TXDPKTBUFDIS_EP11   0x00000800  // EP11 TX Double-Packet Buffer
+                                            // Disable
+#define USB_TXDPKTBUFDIS_EP10   0x00000400  // EP10 TX Double-Packet Buffer
+                                            // Disable
+#define USB_TXDPKTBUFDIS_EP9    0x00000200  // EP9 TX Double-Packet Buffer
+                                            // Disable
+#define USB_TXDPKTBUFDIS_EP8    0x00000100  // EP8 TX Double-Packet Buffer
+                                            // Disable
+#define USB_TXDPKTBUFDIS_EP7    0x00000080  // EP7 TX Double-Packet Buffer
+                                            // Disable
+#define USB_TXDPKTBUFDIS_EP6    0x00000040  // EP6 TX Double-Packet Buffer
+                                            // Disable
+#define USB_TXDPKTBUFDIS_EP5    0x00000020  // EP5 TX Double-Packet Buffer
+                                            // Disable
+#define USB_TXDPKTBUFDIS_EP4    0x00000010  // EP4 TX Double-Packet Buffer
+                                            // Disable
+#define USB_TXDPKTBUFDIS_EP3    0x00000008  // EP3 TX Double-Packet Buffer
+                                            // Disable
+#define USB_TXDPKTBUFDIS_EP2    0x00000004  // EP2 TX Double-Packet Buffer
+                                            // Disable
+#define USB_TXDPKTBUFDIS_EP1    0x00000002  // EP1 TX Double-Packet Buffer
+                                            // Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPC register.
+//
+//*****************************************************************************
+#define USB_EPC_PFLTACT_M       0x00000300  // Power Fault Action
+#define USB_EPC_PFLTACT_UNCHG   0x00000000  // Unchanged
+#define USB_EPC_PFLTACT_TRIS    0x00000100  // Tristate
+#define USB_EPC_PFLTACT_LOW     0x00000200  // Low
+#define USB_EPC_PFLTACT_HIGH    0x00000300  // High
+#define USB_EPC_PFLTAEN         0x00000040  // Power Fault Action Enable
+#define USB_EPC_PFLTSEN_HIGH    0x00000020  // Power Fault Sense
+#define USB_EPC_PFLTEN          0x00000010  // Power Fault Input Enable
+#define USB_EPC_EPENDE          0x00000004  // EPEN Drive Enable
+#define USB_EPC_EPEN_M          0x00000003  // External Power Supply Enable
+                                            // Configuration
+#define USB_EPC_EPEN_LOW        0x00000000  // Power Enable Active Low
+#define USB_EPC_EPEN_HIGH       0x00000001  // Power Enable Active High
+#define USB_EPC_EPEN_VBLOW      0x00000002  // Power Enable High if VBUS Low
+#define USB_EPC_EPEN_VBHIGH     0x00000003  // Power Enable High if VBUS High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPCRIS register.
+//
+//*****************************************************************************
+#define USB_EPCRIS_PF           0x00000001  // USB Power Fault Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPCIM register.
+//
+//*****************************************************************************
+#define USB_EPCIM_PF            0x00000001  // USB Power Fault Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPCISC register.
+//
+//*****************************************************************************
+#define USB_EPCISC_PF           0x00000001  // USB Power Fault Interrupt Status
+                                            // and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DRRIS register.
+//
+//*****************************************************************************
+#define USB_DRRIS_RESUME        0x00000001  // RESUME Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DRIM register.
+//
+//*****************************************************************************
+#define USB_DRIM_RESUME         0x00000001  // RESUME Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DRISC register.
+//
+//*****************************************************************************
+#define USB_DRISC_RESUME        0x00000001  // RESUME Interrupt Status and
+                                            // Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_GPCS register.
+//
+//*****************************************************************************
+#define USB_GPCS_DEVMODOTG      0x00000002  // Enable Device Mode
+#define USB_GPCS_DEVMOD         0x00000001  // Device Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VDC register.
+//
+//*****************************************************************************
+#define USB_VDC_VBDEN           0x00000001  // VBUS Droop Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VDCRIS register.
+//
+//*****************************************************************************
+#define USB_VDCRIS_VD           0x00000001  // VBUS Droop Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VDCIM register.
+//
+//*****************************************************************************
+#define USB_VDCIM_VD            0x00000001  // VBUS Droop Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VDCISC register.
+//
+//*****************************************************************************
+#define USB_VDCISC_VD           0x00000001  // VBUS Droop Interrupt Status and
+                                            // Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_IDVRIS register.
+//
+//*****************************************************************************
+#define USB_IDVRIS_ID           0x00000001  // ID Valid Detect Raw Interrupt
+                                            // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_IDVIM register.
+//
+//*****************************************************************************
+#define USB_IDVIM_ID            0x00000001  // ID Valid Detect Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_IDVISC register.
+//
+//*****************************************************************************
+#define USB_IDVISC_ID           0x00000001  // ID Valid Detect Interrupt Status
+                                            // and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMASEL register.
+//
+//*****************************************************************************
+#define USB_DMASEL_DMACTX_M     0x00F00000  // DMA C TX Select
+#define USB_DMASEL_DMACRX_M     0x000F0000  // DMA C RX Select
+#define USB_DMASEL_DMABTX_M     0x0000F000  // DMA B TX Select
+#define USB_DMASEL_DMABRX_M     0x00000F00  // DMA B RX Select
+#define USB_DMASEL_DMAATX_M     0x000000F0  // DMA A TX Select
+#define USB_DMASEL_DMAARX_M     0x0000000F  // DMA A RX Select
+#define USB_DMASEL_DMACTX_S     20
+#define USB_DMASEL_DMACRX_S     16
+#define USB_DMASEL_DMABTX_S     12
+#define USB_DMASEL_DMABRX_S     8
+#define USB_DMASEL_DMAATX_S     4
+#define USB_DMASEL_DMAARX_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_TXFIFO register.
+//
+//*****************************************************************************
+#define I2S_TXFIFO_M            0xFFFFFFFF  // TX Data
+#define I2S_TXFIFO_S            0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_TXFIFOCFG
+// register.
+//
+//*****************************************************************************
+#define I2S_TXFIFOCFG_CSS       0x00000002  // Compact Stereo Sample Size
+#define I2S_TXFIFOCFG_LRS       0x00000001  // Left-Right Sample Indicator
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_TXCFG register.
+//
+//*****************************************************************************
+#define I2S_TXCFG_JST           0x20000000  // Justification of Output Data
+#define I2S_TXCFG_DLY           0x10000000  // Data Delay
+#define I2S_TXCFG_SCP           0x08000000  // SCLK Polarity
+#define I2S_TXCFG_LRP           0x04000000  // Left/Right Clock Polarity
+#define I2S_TXCFG_WM_M          0x03000000  // Write Mode
+#define I2S_TXCFG_WM_DUAL       0x00000000  // Stereo mode
+#define I2S_TXCFG_WM_COMPACT    0x01000000  // Compact Stereo mode
+#define I2S_TXCFG_WM_MONO       0x02000000  // Mono mode
+#define I2S_TXCFG_FMT           0x00800000  // FIFO Empty
+#define I2S_TXCFG_MSL           0x00400000  // SCLK Master/Slave
+#define I2S_TXCFG_SSZ_M         0x0000FC00  // Sample Size
+#define I2S_TXCFG_SDSZ_M        0x000003F0  // System Data Size
+#define I2S_TXCFG_SSZ_S         10
+#define I2S_TXCFG_SDSZ_S        4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_TXLIMIT register.
+//
+//*****************************************************************************
+#define I2S_TXLIMIT_LIMIT_M     0x0000001F  // FIFO Limit
+#define I2S_TXLIMIT_LIMIT_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_TXISM register.
+//
+//*****************************************************************************
+#define I2S_TXISM_FFI           0x00010000  // Transmit FIFO Service Request
+                                            // Interrupt
+#define I2S_TXISM_FFM           0x00000001  // FIFO Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_TXLEV register.
+//
+//*****************************************************************************
+#define I2S_TXLEV_LEVEL_M       0x0000001F  // Number of Audio Samples
+#define I2S_TXLEV_LEVEL_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_RXFIFO register.
+//
+//*****************************************************************************
+#define I2S_RXFIFO_M            0xFFFFFFFF  // RX Data
+#define I2S_RXFIFO_S            0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_RXFIFOCFG
+// register.
+//
+//*****************************************************************************
+#define I2S_RXFIFOCFG_FMM       0x00000004  // FIFO Mono Mode
+#define I2S_RXFIFOCFG_CSS       0x00000002  // Compact Stereo Sample Size
+#define I2S_RXFIFOCFG_LRS       0x00000001  // Left-Right Sample Indicator
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_RXCFG register.
+//
+//*****************************************************************************
+#define I2S_RXCFG_JST           0x20000000  // Justification of Input Data
+#define I2S_RXCFG_DLY           0x10000000  // Data Delay
+#define I2S_RXCFG_SCP           0x08000000  // SCLK Polarity
+#define I2S_RXCFG_LRP           0x04000000  // Left/Right Clock Polarity
+#define I2S_RXCFG_RM            0x01000000  // Read Mode
+#define I2S_RXCFG_MSL           0x00400000  // SCLK Master/Slave
+#define I2S_RXCFG_SSZ_M         0x0000FC00  // Sample Size
+#define I2S_RXCFG_SDSZ_M        0x000003F0  // System Data Size
+#define I2S_RXCFG_SSZ_S         10
+#define I2S_RXCFG_SDSZ_S        4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_RXLIMIT register.
+//
+//*****************************************************************************
+#define I2S_RXLIMIT_LIMIT_M     0x0000001F  // FIFO Limit
+#define I2S_RXLIMIT_LIMIT_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_RXISM register.
+//
+//*****************************************************************************
+#define I2S_RXISM_FFI           0x00010000  // Receive FIFO Service Request
+                                            // Interrupt
+#define I2S_RXISM_FFM           0x00000001  // FIFO Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_RXLEV register.
+//
+//*****************************************************************************
+#define I2S_RXLEV_LEVEL_M       0x0000001F  // Number of Audio Samples
+#define I2S_RXLEV_LEVEL_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_CFG register.
+//
+//*****************************************************************************
+#define I2S_CFG_RXSLV           0x00000020  // Use External I2S0RXMCLK
+#define I2S_CFG_TXSLV           0x00000010  // Use External I2S0TXMCLK
+#define I2S_CFG_RXEN            0x00000002  // Serial Receive Engine Enable
+#define I2S_CFG_TXEN            0x00000001  // Serial Transmit Engine Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_IM register.
+//
+//*****************************************************************************
+#define I2S_IM_RXRE             0x00000020  // Receive FIFO Read Error
+#define I2S_IM_RXFSR            0x00000010  // Receive FIFO Service Request
+#define I2S_IM_TXWE             0x00000002  // Transmit FIFO Write Error
+#define I2S_IM_TXFSR            0x00000001  // Transmit FIFO Service Request
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_RIS register.
+//
+//*****************************************************************************
+#define I2S_RIS_RXRE            0x00000020  // Receive FIFO Read Error
+#define I2S_RIS_RXFSR           0x00000010  // Receive FIFO Service Request
+#define I2S_RIS_TXWE            0x00000002  // Transmit FIFO Write Error
+#define I2S_RIS_TXFSR           0x00000001  // Transmit FIFO Service Request
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_MIS register.
+//
+//*****************************************************************************
+#define I2S_MIS_RXRE            0x00000020  // Receive FIFO Read Error
+#define I2S_MIS_RXFSR           0x00000010  // Receive FIFO Service Request
+#define I2S_MIS_TXWE            0x00000002  // Transmit FIFO Write Error
+#define I2S_MIS_TXFSR           0x00000001  // Transmit FIFO Service Request
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_IC register.
+//
+//*****************************************************************************
+#define I2S_IC_RXRE             0x00000020  // Receive FIFO Read Error
+#define I2S_IC_TXWE             0x00000002  // Transmit FIFO Write Error
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_CFG register.
+//
+//*****************************************************************************
+#define EPI_CFG_BLKEN           0x00000010  // Block Enable
+#define EPI_CFG_MODE_M          0x0000000F  // Mode Select
+#define EPI_CFG_MODE_NONE       0x00000000  // General Purpose
+#define EPI_CFG_MODE_SDRAM      0x00000001  // SDRAM
+#define EPI_CFG_MODE_HB8        0x00000002  // 8-Bit Host-Bus (HB8)
+#define EPI_CFG_MODE_HB16       0x00000003  // 16-Bit Host-Bus (HB16)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_BAUD register.
+//
+//*****************************************************************************
+#define EPI_BAUD_COUNT1_M       0xFFFF0000  // Baud Rate Counter 1
+#define EPI_BAUD_COUNT0_M       0x0000FFFF  // Baud Rate Counter 0
+#define EPI_BAUD_COUNT1_S       16
+#define EPI_BAUD_COUNT0_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB16CFG register.
+//
+//*****************************************************************************
+#define EPI_HB16CFG_XFFEN       0x00800000  // External FIFO FULL Enable
+#define EPI_HB16CFG_XFEEN       0x00400000  // External FIFO EMPTY Enable
+#define EPI_HB16CFG_WRHIGH      0x00200000  // WRITE Strobe Polarity
+#define EPI_HB16CFG_RDHIGH      0x00100000  // READ Strobe Polarity
+#define EPI_HB16CFG_MAXWAIT_M   0x0000FF00  // Maximum Wait
+#define EPI_HB16CFG_WRWS_M      0x000000C0  // CS0n Write Wait States
+#define EPI_HB16CFG_WRWS_0      0x00000000  // No wait states
+#define EPI_HB16CFG_WRWS_1      0x00000040  // 1 wait state
+#define EPI_HB16CFG_WRWS_2      0x00000080  // 2 wait states
+#define EPI_HB16CFG_WRWS_3      0x000000C0  // 3 wait states
+#define EPI_HB16CFG_RDWS_M      0x00000030  // CS0n Read Wait States
+#define EPI_HB16CFG_RDWS_0      0x00000000  // No wait states
+#define EPI_HB16CFG_RDWS_1      0x00000010  // 1 wait state
+#define EPI_HB16CFG_RDWS_2      0x00000020  // 2 wait states
+#define EPI_HB16CFG_RDWS_3      0x00000030  // 3 wait states
+#define EPI_HB16CFG_BSEL        0x00000004  // Byte Select Configuration
+#define EPI_HB16CFG_MODE_M      0x00000003  // Host Bus Sub-Mode
+#define EPI_HB16CFG_MODE_ADMUX  0x00000000  // ADMUX - AD[15:0]
+#define EPI_HB16CFG_MODE_ADNMUX 0x00000001  // ADNONMUX - D[15:0]
+#define EPI_HB16CFG_MODE_SRAM   0x00000002  // Continuous Read - D[15:0]
+#define EPI_HB16CFG_MODE_XFIFO  0x00000003  // XFIFO - D[15:0]
+#define EPI_HB16CFG_MAXWAIT_S   8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_GPCFG register.
+//
+//*****************************************************************************
+#define EPI_GPCFG_CLKPIN        0x80000000  // Clock Pin
+#define EPI_GPCFG_CLKGATE       0x40000000  // Clock Gated
+#define EPI_GPCFG_RDYEN         0x10000000  // Ready Enable
+#define EPI_GPCFG_FRMPIN        0x08000000  // Framing Pin
+#define EPI_GPCFG_FRM50         0x04000000  // 50/50 Frame
+#define EPI_GPCFG_FRMCNT_M      0x03C00000  // Frame Count
+#define EPI_GPCFG_RW            0x00200000  // Read and Write
+#define EPI_GPCFG_WR2CYC        0x00080000  // 2-Cycle Writes
+#define EPI_GPCFG_RD2CYC        0x00040000  // 2-Cycle Reads
+#define EPI_GPCFG_MAXWAIT_M     0x0000FF00  // Maximum Wait
+#define EPI_GPCFG_ASIZE_M       0x00000030  // Address Bus Size
+#define EPI_GPCFG_ASIZE_NONE    0x00000000  // No address
+#define EPI_GPCFG_ASIZE_4BIT    0x00000010  // Up to 4 bits wide
+#define EPI_GPCFG_ASIZE_12BIT   0x00000020  // Up to 12 bits wide. This size
+                                            // cannot be used with 24-bit data
+#define EPI_GPCFG_ASIZE_20BIT   0x00000030  // Up to 20 bits wide. This size
+                                            // cannot be used with data sizes
+                                            // other than 8
+#define EPI_GPCFG_DSIZE_M       0x00000003  // Size of Data Bus
+#define EPI_GPCFG_DSIZE_4BIT    0x00000000  // 8 Bits Wide (EPI0S0 to EPI0S7)
+#define EPI_GPCFG_DSIZE_16BIT   0x00000001  // 16 Bits Wide (EPI0S0 to EPI0S15)
+#define EPI_GPCFG_DSIZE_24BIT   0x00000002  // 24 Bits Wide (EPI0S0 to EPI0S23)
+#define EPI_GPCFG_DSIZE_32BIT   0x00000003  // 32 Bits Wide (EPI0S0 to EPI0S31)
+#define EPI_GPCFG_FRMCNT_S      22
+#define EPI_GPCFG_MAXWAIT_S     8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_SDRAMCFG register.
+//
+//*****************************************************************************
+#define EPI_SDRAMCFG_FREQ_M     0xC0000000  // Frequency Range
+#define EPI_SDRAMCFG_FREQ_NONE  0x00000000  // 0 - 15 MHz
+#define EPI_SDRAMCFG_FREQ_15MHZ 0x40000000  // 15 - 30 MHz
+#define EPI_SDRAMCFG_FREQ_30MHZ 0x80000000  // 30 - 50 MHz
+#define EPI_SDRAMCFG_FREQ_50MHZ 0xC0000000  // 50 - 100 MHz
+#define EPI_SDRAMCFG_RFSH_M     0x07FF0000  // Refresh Counter
+#define EPI_SDRAMCFG_SLEEP      0x00000200  // Sleep Mode
+#define EPI_SDRAMCFG_SIZE_M     0x00000003  // Size of SDRAM
+#define EPI_SDRAMCFG_SIZE_8MB   0x00000000  // 64 megabits (8MB)
+#define EPI_SDRAMCFG_SIZE_16MB  0x00000001  // 128 megabits (16MB)
+#define EPI_SDRAMCFG_SIZE_32MB  0x00000002  // 256 megabits (32MB)
+#define EPI_SDRAMCFG_SIZE_64MB  0x00000003  // 512 megabits (64MB)
+#define EPI_SDRAMCFG_RFSH_S     16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB8CFG register.
+//
+//*****************************************************************************
+#define EPI_HB8CFG_XFFEN        0x00800000  // External FIFO FULL Enable
+#define EPI_HB8CFG_XFEEN        0x00400000  // External FIFO EMPTY Enable
+#define EPI_HB8CFG_WRHIGH       0x00200000  // CS0n WRITE Strobe Polarity
+#define EPI_HB8CFG_RDHIGH       0x00100000  // CS0n READ Strobe Polarity
+#define EPI_HB8CFG_MAXWAIT_M    0x0000FF00  // Maximum Wait
+#define EPI_HB8CFG_WRWS_M       0x000000C0  // Write Wait States
+#define EPI_HB8CFG_WRWS_0       0x00000000  // No wait states
+#define EPI_HB8CFG_WRWS_1       0x00000040  // 1 wait state
+#define EPI_HB8CFG_WRWS_2       0x00000080  // 2 wait states
+#define EPI_HB8CFG_WRWS_3       0x000000C0  // 3 wait states
+#define EPI_HB8CFG_RDWS_M       0x00000030  // Read Wait States
+#define EPI_HB8CFG_RDWS_0       0x00000000  // No wait states
+#define EPI_HB8CFG_RDWS_1       0x00000010  // 1 wait state
+#define EPI_HB8CFG_RDWS_2       0x00000020  // 2 wait states
+#define EPI_HB8CFG_RDWS_3       0x00000030  // 3 wait states
+#define EPI_HB8CFG_MODE_M       0x00000003  // Host Bus Sub-Mode
+#define EPI_HB8CFG_MODE_MUX     0x00000000  // ADMUX - AD[7:0]
+#define EPI_HB8CFG_MODE_NMUX    0x00000001  // ADNONMUX - D[7:0]
+#define EPI_HB8CFG_MODE_SRAM    0x00000002  // Continuous Read - D[7:0]
+#define EPI_HB8CFG_MODE_FIFO    0x00000003  // XFIFO - D[7:0]
+#define EPI_HB8CFG_MAXWAIT_S    8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB8CFG2 register.
+//
+//*****************************************************************************
+#define EPI_HB8CFG2_WORD        0x80000000  // Word Access Mode
+#define EPI_HB8CFG2_CSBAUD      0x04000000  // Chip Select Baud Rate
+#define EPI_HB8CFG2_CSCFG_M     0x03000000  // Chip Select Configuration
+#define EPI_HB8CFG2_CSCFG_ALE   0x00000000  // ALE Configuration
+#define EPI_HB8CFG2_CSCFG_CS    0x01000000  // CSn Configuration
+#define EPI_HB8CFG2_CSCFG_DCS   0x02000000  // Dual CSn Configuration
+#define EPI_HB8CFG2_CSCFG_ADCS  0x03000000  // ALE with Dual CSn Configuration
+#define EPI_HB8CFG2_WRHIGH      0x00200000  // CS1n WRITE Strobe Polarity
+#define EPI_HB8CFG2_RDHIGH      0x00100000  // CS1n READ Strobe Polarity
+#define EPI_HB8CFG2_WRWS_M      0x000000C0  // CS1n Write Wait States
+#define EPI_HB8CFG2_WRWS_0      0x00000000  // No wait states
+#define EPI_HB8CFG2_WRWS_1      0x00000040  // 1 wait state
+#define EPI_HB8CFG2_WRWS_2      0x00000080  // 2 wait states
+#define EPI_HB8CFG2_WRWS_3      0x000000C0  // 3 wait states
+#define EPI_HB8CFG2_RDWS_M      0x00000030  // CS1n Read Wait States
+#define EPI_HB8CFG2_RDWS_0      0x00000000  // No wait states
+#define EPI_HB8CFG2_RDWS_1      0x00000010  // 1 wait state
+#define EPI_HB8CFG2_RDWS_2      0x00000020  // 2 wait states
+#define EPI_HB8CFG2_RDWS_3      0x00000030  // 3 wait states
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB16CFG2 register.
+//
+//*****************************************************************************
+#define EPI_HB16CFG2_WORD       0x80000000  // Word Access Mode
+#define EPI_HB16CFG2_CSBAUD     0x04000000  // Chip Select Baud Rate
+#define EPI_HB16CFG2_CSCFG_M    0x03000000  // Chip Select Configuration
+#define EPI_HB16CFG2_CSCFG_ALE  0x00000000  // ALE Configuration
+#define EPI_HB16CFG2_CSCFG_CS   0x01000000  // CSn Configuration
+#define EPI_HB16CFG2_CSCFG_DCS  0x02000000  // Dual CSn Configuration
+#define EPI_HB16CFG2_CSCFG_ADCS 0x03000000  // ALE with Dual CSn Configuration
+#define EPI_HB16CFG2_WRHIGH     0x00200000  // CS1n WRITE Strobe Polarity
+#define EPI_HB16CFG2_RDHIGH     0x00100000  // CS1n READ Strobe Polarity
+#define EPI_HB16CFG2_WRWS_M     0x000000C0  // CS1n Write Wait States
+#define EPI_HB16CFG2_WRWS_0     0x00000000  // No wait states
+#define EPI_HB16CFG2_WRWS_1     0x00000040  // 1 wait state
+#define EPI_HB16CFG2_WRWS_2     0x00000080  // 2 wait states
+#define EPI_HB16CFG2_WRWS_3     0x000000C0  // 3 wait states
+#define EPI_HB16CFG2_RDWS_M     0x00000030  // CS1n Read Wait States
+#define EPI_HB16CFG2_RDWS_0     0x00000000  // No wait states
+#define EPI_HB16CFG2_RDWS_1     0x00000010  // 1 wait state
+#define EPI_HB16CFG2_RDWS_2     0x00000020  // 2 wait states
+#define EPI_HB16CFG2_RDWS_3     0x00000030  // 3 wait states
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_GPCFG2 register.
+//
+//*****************************************************************************
+#define EPI_GPCFG2_WORD         0x80000000  // Word Access Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_ADDRMAP register.
+//
+//*****************************************************************************
+#define EPI_ADDRMAP_EPSZ_M      0x000000C0  // External Peripheral Size
+#define EPI_ADDRMAP_EPSZ_256B   0x00000000  // 256 bytes; lower address range:
+                                            // 0x00 to 0xFF
+#define EPI_ADDRMAP_EPSZ_64KB   0x00000040  // 64 KB; lower address range:
+                                            // 0x0000 to 0xFFFF
+#define EPI_ADDRMAP_EPSZ_16MB   0x00000080  // 16 MB; lower address range:
+                                            // 0x00.0000 to 0xFF.FFFF
+#define EPI_ADDRMAP_EPSZ_256MB  0x000000C0  // 256 MB; lower address range:
+                                            // 0x000.0000 to 0xFFF.FFFF
+#define EPI_ADDRMAP_EPADR_M     0x00000030  // External Peripheral Address
+#define EPI_ADDRMAP_EPADR_NONE  0x00000000  // Not mapped
+#define EPI_ADDRMAP_EPADR_A000  0x00000010  // At 0xA000.0000
+#define EPI_ADDRMAP_EPADR_C000  0x00000020  // At 0xC000.0000
+#define EPI_ADDRMAP_ERSZ_M      0x0000000C  // External RAM Size
+#define EPI_ADDRMAP_ERSZ_256B   0x00000000  // 256 bytes; lower address range:
+                                            // 0x00 to 0xFF
+#define EPI_ADDRMAP_ERSZ_64KB   0x00000004  // 64 KB; lower address range:
+                                            // 0x0000 to 0xFFFF
+#define EPI_ADDRMAP_ERSZ_16MB   0x00000008  // 16 MB; lower address range:
+                                            // 0x00.0000 to 0xFF.FFFF
+#define EPI_ADDRMAP_ERSZ_256MB  0x0000000C  // 256 MB; lower address range:
+                                            // 0x000.0000 to 0xFFF.FFFF
+#define EPI_ADDRMAP_ERADR_M     0x00000003  // External RAM Address
+#define EPI_ADDRMAP_ERADR_NONE  0x00000000  // Not mapped
+#define EPI_ADDRMAP_ERADR_6000  0x00000001  // At 0x6000.0000
+#define EPI_ADDRMAP_ERADR_8000  0x00000002  // At 0x8000.0000
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RSIZE0 register.
+//
+//*****************************************************************************
+#define EPI_RSIZE0_SIZE_M       0x00000003  // Current Size
+#define EPI_RSIZE0_SIZE_8BIT    0x00000001  // Byte (8 bits)
+#define EPI_RSIZE0_SIZE_16BIT   0x00000002  // Half-word (16 bits)
+#define EPI_RSIZE0_SIZE_32BIT   0x00000003  // Word (32 bits)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RADDR0 register.
+//
+//*****************************************************************************
+#define EPI_RADDR0_ADDR_M       0x1FFFFFFF  // Current Address
+#define EPI_RADDR0_ADDR_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RPSTD0 register.
+//
+//*****************************************************************************
+#define EPI_RPSTD0_POSTCNT_M    0x00001FFF  // Post Count
+#define EPI_RPSTD0_POSTCNT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RSIZE1 register.
+//
+//*****************************************************************************
+#define EPI_RSIZE1_SIZE_M       0x00000003  // Current Size
+#define EPI_RSIZE1_SIZE_8BIT    0x00000001  // Byte (8 bits)
+#define EPI_RSIZE1_SIZE_16BIT   0x00000002  // Half-word (16 bits)
+#define EPI_RSIZE1_SIZE_32BIT   0x00000003  // Word (32 bits)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RADDR1 register.
+//
+//*****************************************************************************
+#define EPI_RADDR1_ADDR_M       0x1FFFFFFF  // Current Address
+#define EPI_RADDR1_ADDR_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RPSTD1 register.
+//
+//*****************************************************************************
+#define EPI_RPSTD1_POSTCNT_M    0x00001FFF  // Post Count
+#define EPI_RPSTD1_POSTCNT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_STAT register.
+//
+//*****************************************************************************
+#define EPI_STAT_CELOW          0x00000200  // Clock Enable Low
+#define EPI_STAT_XFFULL         0x00000100  // External FIFO Full
+#define EPI_STAT_XFEMPTY        0x00000080  // External FIFO Empty
+#define EPI_STAT_INITSEQ        0x00000040  // Initialization Sequence
+#define EPI_STAT_WBUSY          0x00000020  // Write Busy
+#define EPI_STAT_NBRBUSY        0x00000010  // Non-Blocking Read Busy
+#define EPI_STAT_ACTIVE         0x00000001  // Register Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RFIFOCNT register.
+//
+//*****************************************************************************
+#define EPI_RFIFOCNT_COUNT_M    0x00000007  // FIFO Count
+#define EPI_RFIFOCNT_COUNT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO register.
+//
+//*****************************************************************************
+#define EPI_READFIFO_DATA_M     0xFFFFFFFF  // Reads Data
+#define EPI_READFIFO_DATA_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO1
+// register.
+//
+//*****************************************************************************
+#define EPI_READFIFO1_DATA_M    0xFFFFFFFF  // Reads Data
+#define EPI_READFIFO1_DATA_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO2
+// register.
+//
+//*****************************************************************************
+#define EPI_READFIFO2_DATA_M    0xFFFFFFFF  // Reads Data
+#define EPI_READFIFO2_DATA_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO3
+// register.
+//
+//*****************************************************************************
+#define EPI_READFIFO3_DATA_M    0xFFFFFFFF  // Reads Data
+#define EPI_READFIFO3_DATA_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO4
+// register.
+//
+//*****************************************************************************
+#define EPI_READFIFO4_DATA_M    0xFFFFFFFF  // Reads Data
+#define EPI_READFIFO4_DATA_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO5
+// register.
+//
+//*****************************************************************************
+#define EPI_READFIFO5_DATA_M    0xFFFFFFFF  // Reads Data
+#define EPI_READFIFO5_DATA_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO6
+// register.
+//
+//*****************************************************************************
+#define EPI_READFIFO6_DATA_M    0xFFFFFFFF  // Reads Data
+#define EPI_READFIFO6_DATA_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO7
+// register.
+//
+//*****************************************************************************
+#define EPI_READFIFO7_DATA_M    0xFFFFFFFF  // Reads Data
+#define EPI_READFIFO7_DATA_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_FIFOLVL register.
+//
+//*****************************************************************************
+#define EPI_FIFOLVL_WFERR       0x00020000  // Write Full Error
+#define EPI_FIFOLVL_RSERR       0x00010000  // Read Stall Error
+#define EPI_FIFOLVL_WRFIFO_M    0x00000070  // Write FIFO
+#define EPI_FIFOLVL_WRFIFO_EMPT 0x00000000  // Trigger when there are 1 to 4
+                                            // spaces available in the WFIFO
+#define EPI_FIFOLVL_WRFIFO_1_4  0x00000020  // Trigger when there are 1 to 3
+                                            // spaces available in the WFIFO
+#define EPI_FIFOLVL_WRFIFO_1_2  0x00000030  // Trigger when there are 1 to 2
+                                            // spaces available in the WFIFO
+#define EPI_FIFOLVL_WRFIFO_3_4  0x00000040  // Trigger when there is 1 space
+                                            // available in the WFIFO
+#define EPI_FIFOLVL_RDFIFO_M    0x00000007  // Read FIFO
+#define EPI_FIFOLVL_RDFIFO_EMPT 0x00000000  // Empty
+#define EPI_FIFOLVL_RDFIFO_1_8  0x00000001  // Trigger when there are 1 or more
+                                            // entries in the NBRFIFO
+#define EPI_FIFOLVL_RDFIFO_1_4  0x00000002  // Trigger when there are 2 or more
+                                            // entries in the NBRFIFO
+#define EPI_FIFOLVL_RDFIFO_1_2  0x00000003  // Trigger when there are 4 or more
+                                            // entries in the NBRFIFO
+#define EPI_FIFOLVL_RDFIFO_3_4  0x00000004  // Trigger when there are 6 or more
+                                            // entries in the NBRFIFO
+#define EPI_FIFOLVL_RDFIFO_7_8  0x00000005  // Trigger when there are 7 or more
+                                            // entries in the NBRFIFO
+#define EPI_FIFOLVL_RDFIFO_FULL 0x00000006  // Trigger when there are 8 entries
+                                            // in the NBRFIFO
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_WFIFOCNT register.
+//
+//*****************************************************************************
+#define EPI_WFIFOCNT_WTAV_M     0x00000007  // Available Write Transactions
+#define EPI_WFIFOCNT_WTAV_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_IM register.
+//
+//*****************************************************************************
+#define EPI_IM_WRIM             0x00000004  // Write Interrupt Mask
+#define EPI_IM_RDIM             0x00000002  // Read Interrupt Mask
+#define EPI_IM_ERRIM            0x00000001  // Error Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RIS register.
+//
+//*****************************************************************************
+#define EPI_RIS_WRRIS           0x00000004  // Write Raw Interrupt Status
+#define EPI_RIS_RDRIS           0x00000002  // Read Raw Interrupt Status
+#define EPI_RIS_ERRRIS          0x00000001  // Error Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_MIS register.
+//
+//*****************************************************************************
+#define EPI_MIS_WRMIS           0x00000004  // Write Masked Interrupt Status
+#define EPI_MIS_RDMIS           0x00000002  // Read Masked Interrupt Status
+#define EPI_MIS_ERRMIS          0x00000001  // Error Masked Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_EISC register.
+//
+//*****************************************************************************
+#define EPI_EISC_WTFULL         0x00000004  // Write FIFO Full Error
+#define EPI_EISC_RSTALL         0x00000002  // Read Stalled Error
+#define EPI_EISC_TOUT           0x00000001  // Timeout Error
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMA register.
+//
+//*****************************************************************************
+#define FLASH_FMA_OFFSET_M      0x0007FFFF  // Address Offset
+#define FLASH_FMA_OFFSET_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMD register.
+//
+//*****************************************************************************
+#define FLASH_FMD_DATA_M        0xFFFFFFFF  // Data Value
+#define FLASH_FMD_DATA_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMC register.
+//
+//*****************************************************************************
+#define FLASH_FMC_WRKEY         0xA4420000  // FLASH write key
+#define FLASH_FMC_COMT          0x00000008  // Commit Register Value
+#define FLASH_FMC_MERASE        0x00000004  // Mass Erase Flash Memory
+#define FLASH_FMC_ERASE         0x00000002  // Erase a Page of Flash Memory
+#define FLASH_FMC_WRITE         0x00000001  // Write a Word into Flash Memory
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FCRIS register.
+//
+//*****************************************************************************
+#define FLASH_FCRIS_PRIS        0x00000002  // Programming Raw Interrupt Status
+#define FLASH_FCRIS_ARIS        0x00000001  // Access Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FCIM register.
+//
+//*****************************************************************************
+#define FLASH_FCIM_PMASK        0x00000002  // Programming Interrupt Mask
+#define FLASH_FCIM_AMASK        0x00000001  // Access Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FCMISC register.
+//
+//*****************************************************************************
+#define FLASH_FCMISC_PMISC      0x00000002  // Programming Masked Interrupt
+                                            // Status and Clear
+#define FLASH_FCMISC_AMISC      0x00000001  // Access Masked Interrupt Status
+                                            // and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMC2 register.
+//
+//*****************************************************************************
+#define FLASH_FMC2_WRKEY        0xA4420000  // FLASH write key
+#define FLASH_FMC2_WRBUF        0x00000001  // Buffered Flash Memory Write
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FWBVAL register.
+//
+//*****************************************************************************
+#define FLASH_FWBVAL_FWB_M      0xFFFFFFFF  // Flash Memory Write Buffer
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FCTL register.
+//
+//*****************************************************************************
+#define FLASH_FCTL_USDACK       0x00000002  // User Shut Down Acknowledge
+#define FLASH_FCTL_USDREQ       0x00000001  // User Shut Down Request
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FWBN register.
+//
+//*****************************************************************************
+#define FLASH_FWBN_DATA_M       0xFFFFFFFF  // Data
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_RMCTL register.
+//
+//*****************************************************************************
+#define FLASH_RMCTL_BA          0x00000001  // Boot Alias
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_RMVER register.
+//
+//*****************************************************************************
+#define FLASH_RMVER_CONT_M      0xFF000000  // ROM Contents
+#define FLASH_RMVER_CONT_LM_AES 0x02000000  // Stellaris Boot Loader &
+                                            // DriverLib with AES
+#define FLASH_RMVER_VER_M       0x0000FF00  // ROM Version
+#define FLASH_RMVER_REV_M       0x000000FF  // ROM Revision
+#define FLASH_RMVER_VER_S       8
+#define FLASH_RMVER_REV_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERDBG register.
+//
+//*****************************************************************************
+#define FLASH_USERDBG_NW        0x80000000  // User Debug Not Written
+#define FLASH_USERDBG_DATA_M    0x7FFFFFFC  // User Data
+#define FLASH_USERDBG_DBG1      0x00000002  // Debug Control 1
+#define FLASH_USERDBG_DBG0      0x00000001  // Debug Control 0
+#define FLASH_USERDBG_DATA_S    2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_BOOTCFG register.
+//
+//*****************************************************************************
+#define FLASH_BOOTCFG_NW        0x80000000  // Not Written
+#define FLASH_BOOTCFG_PORT_M    0x0000E000  // Boot GPIO Port
+#define FLASH_BOOTCFG_PORT_A    0x00000000  // Port A
+#define FLASH_BOOTCFG_PORT_B    0x00002000  // Port B
+#define FLASH_BOOTCFG_PORT_C    0x00004000  // Port C
+#define FLASH_BOOTCFG_PORT_D    0x00006000  // Port D
+#define FLASH_BOOTCFG_PORT_E    0x00008000  // Port E
+#define FLASH_BOOTCFG_PORT_F    0x0000A000  // Port F
+#define FLASH_BOOTCFG_PORT_G    0x0000C000  // Port G
+#define FLASH_BOOTCFG_PORT_H    0x0000E000  // Port H
+#define FLASH_BOOTCFG_PIN_M     0x00001C00  // Boot GPIO Pin
+#define FLASH_BOOTCFG_PIN_0     0x00000000  // Pin 0
+#define FLASH_BOOTCFG_PIN_1     0x00000400  // Pin 1
+#define FLASH_BOOTCFG_PIN_2     0x00000800  // Pin 2
+#define FLASH_BOOTCFG_PIN_3     0x00000C00  // Pin 3
+#define FLASH_BOOTCFG_PIN_4     0x00001000  // Pin 4
+#define FLASH_BOOTCFG_PIN_5     0x00001400  // Pin 5
+#define FLASH_BOOTCFG_PIN_6     0x00001800  // Pin 6
+#define FLASH_BOOTCFG_PIN_7     0x00001C00  // Pin 7
+#define FLASH_BOOTCFG_POL       0x00000200  // Boot GPIO Polarity
+#define FLASH_BOOTCFG_EN        0x00000100  // Boot GPIO Enable
+#define FLASH_BOOTCFG_DBG1      0x00000002  // Debug Control 1
+#define FLASH_BOOTCFG_DBG0      0x00000001  // Debug Control 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG0 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG0_NW       0x80000000  // Not Written
+#define FLASH_USERREG0_DATA_M   0x7FFFFFFF  // User Data
+#define FLASH_USERREG0_DATA_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG1 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG1_NW       0x80000000  // Not Written
+#define FLASH_USERREG1_DATA_M   0x7FFFFFFF  // User Data
+#define FLASH_USERREG1_DATA_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG2 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG2_NW       0x80000000  // Not Written
+#define FLASH_USERREG2_DATA_M   0x7FFFFFFF  // User Data
+#define FLASH_USERREG2_DATA_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG3 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG3_NW       0x80000000  // Not Written
+#define FLASH_USERREG3_DATA_M   0x7FFFFFFF  // User Data
+#define FLASH_USERREG3_DATA_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DID0 register.
+//
+//*****************************************************************************
+#define SYSCTL_DID0_VER_M       0x70000000  // DID0 Version
+#define SYSCTL_DID0_VER_1       0x10000000  // Second version of the DID0
+                                            // register format
+#define SYSCTL_DID0_CLASS_M     0x00FF0000  // Device Class
+#define SYSCTL_DID0_CLASS_FIRESTORM \
+                                0x00060000  // Stellaris(R) Firestorm-class
+                                            // microcontrollers
+#define SYSCTL_DID0_MAJ_M       0x0000FF00  // Major Revision
+#define SYSCTL_DID0_MAJ_REVA    0x00000000  // Revision A (initial device)
+#define SYSCTL_DID0_MAJ_REVB    0x00000100  // Revision B (first base layer
+                                            // revision)
+#define SYSCTL_DID0_MAJ_REVC    0x00000200  // Revision C (second base layer
+                                            // revision)
+#define SYSCTL_DID0_MIN_M       0x000000FF  // Minor Revision
+#define SYSCTL_DID0_MIN_0       0x00000000  // Initial device, or a major
+                                            // revision update
+#define SYSCTL_DID0_MIN_1       0x00000001  // First metal layer change
+#define SYSCTL_DID0_MIN_2       0x00000002  // Second metal layer change
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DID1 register.
+//
+//*****************************************************************************
+#define SYSCTL_DID1_VER_M       0xF0000000  // DID1 Version
+#define SYSCTL_DID1_VER_1       0x10000000  // Second version of the DID1
+                                            // register format
+#define SYSCTL_DID1_FAM_M       0x0F000000  // Family
+#define SYSCTL_DID1_FAM_STELLARIS \
+                                0x00000000  // Stellaris family of
+                                            // microcontollers, that is, all
+                                            // devices with external part
+                                            // numbers starting with LM3S
+#define SYSCTL_DID1_PRTNO_M     0x00FF0000  // Part Number
+#define SYSCTL_DID1_PRTNO_9D92  0x00920000  // LM3S9D92
+#define SYSCTL_DID1_PINCNT_M    0x0000E000  // Package Pin Count
+#define SYSCTL_DID1_PINCNT_100  0x00004000  // 100-pin package
+#define SYSCTL_DID1_TEMP_M      0x000000E0  // Temperature Range
+#define SYSCTL_DID1_TEMP_C      0x00000000  // Commercial temperature range (0C
+                                            // to 70C)
+#define SYSCTL_DID1_TEMP_I      0x00000020  // Industrial temperature range
+                                            // (-40C to 85C)
+#define SYSCTL_DID1_TEMP_E      0x00000040  // Extended temperature range (-40C
+                                            // to 105C)
+#define SYSCTL_DID1_PKG_M       0x00000018  // Package Type
+#define SYSCTL_DID1_PKG_SOIC    0x00000000  // SOIC package
+#define SYSCTL_DID1_PKG_QFP     0x00000008  // LQFP package
+#define SYSCTL_DID1_PKG_BGA     0x00000010  // BGA package
+#define SYSCTL_DID1_ROHS        0x00000004  // RoHS-Compliance
+#define SYSCTL_DID1_QUAL_M      0x00000003  // Qualification Status
+#define SYSCTL_DID1_QUAL_ES     0x00000000  // Engineering Sample (unqualified)
+#define SYSCTL_DID1_QUAL_PP     0x00000001  // Pilot Production (unqualified)
+#define SYSCTL_DID1_QUAL_FQ     0x00000002  // Fully Qualified
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC0_SRAMSZ_M     0xFFFF0000  // SRAM Size
+#define SYSCTL_DC0_SRAMSZ_96KB  0x017F0000  // 96 KB of SRAM
+#define SYSCTL_DC0_FLASHSZ_M    0x0000FFFF  // Flash Size
+#define SYSCTL_DC0_FLASHSZ_512K 0x000000FF  // 512 KB of Flash
+#define SYSCTL_DC0_SRAMSZ_S     16          // SRAM size shift
+#define SYSCTL_DC0_FLASHSZ_S    0           // Flash size shift
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC1_WDT1         0x10000000  // Watchdog Timer1 Present
+#define SYSCTL_DC1_CAN1         0x02000000  // CAN Module 1 Present
+#define SYSCTL_DC1_CAN0         0x01000000  // CAN Module 0 Present
+#define SYSCTL_DC1_PWM          0x00100000  // PWM Module Present
+#define SYSCTL_DC1_ADC1         0x00020000  // ADC Module 1 Present
+#define SYSCTL_DC1_ADC0         0x00010000  // ADC Module 0 Present
+#define SYSCTL_DC1_MINSYSDIV_M  0x0000F000  // System Clock Divider
+#define SYSCTL_DC1_MINSYSDIV_100 \
+                                0x00001000  // Divide VCO (400MHZ) by 5 minimum
+#define SYSCTL_DC1_MINSYSDIV_66 0x00002000  // Divide VCO (400MHZ) by 2*2 + 2 =
+                                            // 6 minimum
+#define SYSCTL_DC1_MINSYSDIV_50 0x00003000  // Specifies a 50-MHz CPU clock
+                                            // with a PLL divider of 4
+#define SYSCTL_DC1_MINSYSDIV_25 0x00007000  // Specifies a 25-MHz clock with a
+                                            // PLL divider of 8
+#define SYSCTL_DC1_MINSYSDIV_20 0x00009000  // Specifies a 20-MHz clock with a
+                                            // PLL divider of 10
+#define SYSCTL_DC1_ADC1SPD_M    0x00000C00  // Max ADC1 Speed
+#define SYSCTL_DC1_ADC1SPD_1M   0x00000C00  // 1M samples/second
+#define SYSCTL_DC1_ADC0SPD_M    0x00000300  // Max ADC0 Speed
+#define SYSCTL_DC1_ADC0SPD_1M   0x00000300  // 1M samples/second
+#define SYSCTL_DC1_MPU          0x00000080  // MPU Present
+#define SYSCTL_DC1_TEMP         0x00000020  // Temp Sensor Present
+#define SYSCTL_DC1_PLL          0x00000010  // PLL Present
+#define SYSCTL_DC1_WDT0         0x00000008  // Watchdog Timer 0 Present
+#define SYSCTL_DC1_SWO          0x00000004  // SWO Trace Port Present
+#define SYSCTL_DC1_SWD          0x00000002  // SWD Present
+#define SYSCTL_DC1_JTAG         0x00000001  // JTAG Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC2_EPI0         0x40000000  // EPI Module 0 Present
+#define SYSCTL_DC2_I2S0         0x10000000  // I2S Module 0 Present
+#define SYSCTL_DC2_COMP2        0x04000000  // Analog Comparator 2 Present
+#define SYSCTL_DC2_COMP1        0x02000000  // Analog Comparator 1 Present
+#define SYSCTL_DC2_COMP0        0x01000000  // Analog Comparator 0 Present
+#define SYSCTL_DC2_TIMER3       0x00080000  // Timer Module 3 Present
+#define SYSCTL_DC2_TIMER2       0x00040000  // Timer Module 2 Present
+#define SYSCTL_DC2_TIMER1       0x00020000  // Timer Module 1 Present
+#define SYSCTL_DC2_TIMER0       0x00010000  // Timer Module 0 Present
+#define SYSCTL_DC2_I2C1         0x00004000  // I2C Module 1 Present
+#define SYSCTL_DC2_I2C0         0x00001000  // I2C Module 0 Present
+#define SYSCTL_DC2_QEI1         0x00000200  // QEI Module 1 Present
+#define SYSCTL_DC2_QEI0         0x00000100  // QEI Module 0 Present
+#define SYSCTL_DC2_SSI1         0x00000020  // SSI Module 1 Present
+#define SYSCTL_DC2_SSI0         0x00000010  // SSI Module 0 Present
+#define SYSCTL_DC2_UART2        0x00000004  // UART Module 2 Present
+#define SYSCTL_DC2_UART1        0x00000002  // UART Module 1 Present
+#define SYSCTL_DC2_UART0        0x00000001  // UART Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC3 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC3_32KHZ        0x80000000  // 32KHz Input Clock Available
+#define SYSCTL_DC3_CCP5         0x20000000  // CCP5 Pin Present
+#define SYSCTL_DC3_CCP4         0x10000000  // CCP4 Pin Present
+#define SYSCTL_DC3_CCP3         0x08000000  // CCP3 Pin Present
+#define SYSCTL_DC3_CCP2         0x04000000  // CCP2 Pin Present
+#define SYSCTL_DC3_CCP1         0x02000000  // CCP1 Pin Present
+#define SYSCTL_DC3_CCP0         0x01000000  // CCP0 Pin Present
+#define SYSCTL_DC3_ADC0AIN7     0x00800000  // ADC Module 0 AIN7 Pin Present
+#define SYSCTL_DC3_ADC0AIN6     0x00400000  // ADC Module 0 AIN6 Pin Present
+#define SYSCTL_DC3_ADC0AIN5     0x00200000  // ADC Module 0 AIN5 Pin Present
+#define SYSCTL_DC3_ADC0AIN4     0x00100000  // ADC Module 0 AIN4 Pin Present
+#define SYSCTL_DC3_ADC0AIN3     0x00080000  // ADC Module 0 AIN3 Pin Present
+#define SYSCTL_DC3_ADC0AIN2     0x00040000  // ADC Module 0 AIN2 Pin Present
+#define SYSCTL_DC3_ADC0AIN1     0x00020000  // ADC Module 0 AIN1 Pin Present
+#define SYSCTL_DC3_ADC0AIN0     0x00010000  // ADC Module 0 AIN0 Pin Present
+#define SYSCTL_DC3_PWMFAULT     0x00008000  // PWM Fault Pin Present
+#define SYSCTL_DC3_C2O          0x00004000  // C2o Pin Present
+#define SYSCTL_DC3_C2PLUS       0x00002000  // C2+ Pin Present
+#define SYSCTL_DC3_C2MINUS      0x00001000  // C2- Pin Present
+#define SYSCTL_DC3_C1O          0x00000800  // C1o Pin Present
+#define SYSCTL_DC3_C1PLUS       0x00000400  // C1+ Pin Present
+#define SYSCTL_DC3_C1MINUS      0x00000200  // C1- Pin Present
+#define SYSCTL_DC3_C0O          0x00000100  // C0o Pin Present
+#define SYSCTL_DC3_C0PLUS       0x00000080  // C0+ Pin Present
+#define SYSCTL_DC3_C0MINUS      0x00000040  // C0- Pin Present
+#define SYSCTL_DC3_PWM5         0x00000020  // PWM5 Pin Present
+#define SYSCTL_DC3_PWM4         0x00000010  // PWM4 Pin Present
+#define SYSCTL_DC3_PWM3         0x00000008  // PWM3 Pin Present
+#define SYSCTL_DC3_PWM2         0x00000004  // PWM2 Pin Present
+#define SYSCTL_DC3_PWM1         0x00000002  // PWM1 Pin Present
+#define SYSCTL_DC3_PWM0         0x00000001  // PWM0 Pin Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC4 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC4_EPHY0        0x40000000  // Ethernet PHY Layer 0 Present
+#define SYSCTL_DC4_EMAC0        0x10000000  // Ethernet MAC Layer 0 Present
+#define SYSCTL_DC4_E1588        0x01000000  // 1588 Capable
+#define SYSCTL_DC4_PICAL        0x00040000  // PIOSC Calibrate
+#define SYSCTL_DC4_CCP7         0x00008000  // CCP7 Pin Present
+#define SYSCTL_DC4_CCP6         0x00004000  // CCP6 Pin Present
+#define SYSCTL_DC4_UDMA         0x00002000  // Micro-DMA Module Present
+#define SYSCTL_DC4_ROM          0x00001000  // Internal Code ROM Present
+#define SYSCTL_DC4_GPIOJ        0x00000100  // GPIO Port J Present
+#define SYSCTL_DC4_GPIOH        0x00000080  // GPIO Port H Present
+#define SYSCTL_DC4_GPIOG        0x00000040  // GPIO Port G Present
+#define SYSCTL_DC4_GPIOF        0x00000020  // GPIO Port F Present
+#define SYSCTL_DC4_GPIOE        0x00000010  // GPIO Port E Present
+#define SYSCTL_DC4_GPIOD        0x00000008  // GPIO Port D Present
+#define SYSCTL_DC4_GPIOC        0x00000004  // GPIO Port C Present
+#define SYSCTL_DC4_GPIOB        0x00000002  // GPIO Port B Present
+#define SYSCTL_DC4_GPIOA        0x00000001  // GPIO Port A Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC5 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC5_PWMFAULT3    0x08000000  // PWM Fault 3 Pin Present
+#define SYSCTL_DC5_PWMFAULT2    0x04000000  // PWM Fault 2 Pin Present
+#define SYSCTL_DC5_PWMFAULT1    0x02000000  // PWM Fault 1 Pin Present
+#define SYSCTL_DC5_PWMFAULT0    0x01000000  // PWM Fault 0 Pin Present
+#define SYSCTL_DC5_PWMEFLT      0x00200000  // PWM Extended Fault Active
+#define SYSCTL_DC5_PWMESYNC     0x00100000  // PWM Extended SYNC Active
+#define SYSCTL_DC5_PWM7         0x00000080  // PWM7 Pin Present
+#define SYSCTL_DC5_PWM6         0x00000040  // PWM6 Pin Present
+#define SYSCTL_DC5_PWM5         0x00000020  // PWM5 Pin Present
+#define SYSCTL_DC5_PWM4         0x00000010  // PWM4 Pin Present
+#define SYSCTL_DC5_PWM3         0x00000008  // PWM3 Pin Present
+#define SYSCTL_DC5_PWM2         0x00000004  // PWM2 Pin Present
+#define SYSCTL_DC5_PWM1         0x00000002  // PWM1 Pin Present
+#define SYSCTL_DC5_PWM0         0x00000001  // PWM0 Pin Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC6 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC6_USB0PHY      0x00000010  // USB Module 0 PHY Present
+#define SYSCTL_DC6_USB0_M       0x00000003  // USB Module 0 Present
+#define SYSCTL_DC6_USB0_OTG     0x00000003  // USB0 is OTG
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC7 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC7_DMACH30      0x40000000  // SW
+#define SYSCTL_DC7_DMACH29      0x20000000  // I2S0_TX / CAN1_TX
+#define SYSCTL_DC7_DMACH28      0x10000000  // I2S0_RX / CAN1_RX
+#define SYSCTL_DC7_DMACH27      0x08000000  // CAN1_TX / ADC1_SS3
+#define SYSCTL_DC7_DMACH26      0x04000000  // CAN1_RX / ADC1_SS2
+#define SYSCTL_DC7_DMACH25      0x02000000  // SSI1_TX / ADC1_SS1
+#define SYSCTL_DC7_DMACH24      0x01000000  // SSI1_RX / ADC1_SS0
+#define SYSCTL_DC7_DMACH23      0x00800000  // UART1_TX / CAN2_TX
+#define SYSCTL_DC7_DMACH22      0x00400000  // UART1_RX / CAN2_RX
+#define SYSCTL_DC7_DMACH21      0x00200000  // Timer1B / EPI0_WFIFO
+#define SYSCTL_DC7_DMACH20      0x00100000  // Timer1A / EPI0_NBRFIFO
+#define SYSCTL_DC7_DMACH19      0x00080000  // Timer0B / Timer1B
+#define SYSCTL_DC7_DMACH18      0x00040000  // Timer0A / Timer1A
+#define SYSCTL_DC7_DMACH17      0x00020000  // ADC0_SS3
+#define SYSCTL_DC7_DMACH16      0x00010000  // ADC0_SS2
+#define SYSCTL_DC7_DMACH15      0x00008000  // ADC0_SS1 / Timer2B
+#define SYSCTL_DC7_DMACH14      0x00004000  // ADC0_SS0 / Timer2A
+#define SYSCTL_DC7_DMACH13      0x00002000  // CAN0_TX / UART2_TX
+#define SYSCTL_DC7_DMACH12      0x00001000  // CAN0_RX / UART2_RX
+#define SYSCTL_DC7_DMACH11      0x00000800  // SSI0_TX / SSI1_TX
+#define SYSCTL_DC7_DMACH10      0x00000400  // SSI0_RX / SSI1_RX
+#define SYSCTL_DC7_DMACH9       0x00000200  // UART0_TX / UART1_TX
+#define SYSCTL_DC7_DMACH8       0x00000100  // UART0_RX / UART1_RX
+#define SYSCTL_DC7_DMACH7       0x00000080  // ETH_TX / Timer2B
+#define SYSCTL_DC7_DMACH6       0x00000040  // ETH_RX / Timer2A
+#define SYSCTL_DC7_DMACH5       0x00000020  // USB_EP3_TX / Timer2B
+#define SYSCTL_DC7_DMACH4       0x00000010  // USB_EP3_RX / Timer2A
+#define SYSCTL_DC7_DMACH3       0x00000008  // USB_EP2_TX / Timer3B
+#define SYSCTL_DC7_DMACH2       0x00000004  // USB_EP2_RX / Timer3A
+#define SYSCTL_DC7_DMACH1       0x00000002  // USB_EP1_TX / UART2_TX
+#define SYSCTL_DC7_DMACH0       0x00000001  // USB_EP1_RX / UART2_RX
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC8 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC8_ADC1AIN15    0x80000000  // ADC Module 1 AIN15 Pin Present
+#define SYSCTL_DC8_ADC1AIN14    0x40000000  // ADC Module 1 AIN14 Pin Present
+#define SYSCTL_DC8_ADC1AIN13    0x20000000  // ADC Module 1 AIN13 Pin Present
+#define SYSCTL_DC8_ADC1AIN12    0x10000000  // ADC Module 1 AIN12 Pin Present
+#define SYSCTL_DC8_ADC1AIN11    0x08000000  // ADC Module 1 AIN11 Pin Present
+#define SYSCTL_DC8_ADC1AIN10    0x04000000  // ADC Module 1 AIN10 Pin Present
+#define SYSCTL_DC8_ADC1AIN9     0x02000000  // ADC Module 1 AIN9 Pin Present
+#define SYSCTL_DC8_ADC1AIN8     0x01000000  // ADC Module 1 AIN8 Pin Present
+#define SYSCTL_DC8_ADC1AIN7     0x00800000  // ADC Module 1 AIN7 Pin Present
+#define SYSCTL_DC8_ADC1AIN6     0x00400000  // ADC Module 1 AIN6 Pin Present
+#define SYSCTL_DC8_ADC1AIN5     0x00200000  // ADC Module 1 AIN5 Pin Present
+#define SYSCTL_DC8_ADC1AIN4     0x00100000  // ADC Module 1 AIN4 Pin Present
+#define SYSCTL_DC8_ADC1AIN3     0x00080000  // ADC Module 1 AIN3 Pin Present
+#define SYSCTL_DC8_ADC1AIN2     0x00040000  // ADC Module 1 AIN2 Pin Present
+#define SYSCTL_DC8_ADC1AIN1     0x00020000  // ADC Module 1 AIN1 Pin Present
+#define SYSCTL_DC8_ADC1AIN0     0x00010000  // ADC Module 1 AIN0 Pin Present
+#define SYSCTL_DC8_ADC0AIN15    0x00008000  // ADC Module 0 AIN15 Pin Present
+#define SYSCTL_DC8_ADC0AIN14    0x00004000  // ADC Module 0 AIN14 Pin Present
+#define SYSCTL_DC8_ADC0AIN13    0x00002000  // ADC Module 0 AIN13 Pin Present
+#define SYSCTL_DC8_ADC0AIN12    0x00001000  // ADC Module 0 AIN12 Pin Present
+#define SYSCTL_DC8_ADC0AIN11    0x00000800  // ADC Module 0 AIN11 Pin Present
+#define SYSCTL_DC8_ADC0AIN10    0x00000400  // ADC Module 0 AIN10 Pin Present
+#define SYSCTL_DC8_ADC0AIN9     0x00000200  // ADC Module 0 AIN9 Pin Present
+#define SYSCTL_DC8_ADC0AIN8     0x00000100  // ADC Module 0 AIN8 Pin Present
+#define SYSCTL_DC8_ADC0AIN7     0x00000080  // ADC Module 0 AIN7 Pin Present
+#define SYSCTL_DC8_ADC0AIN6     0x00000040  // ADC Module 0 AIN6 Pin Present
+#define SYSCTL_DC8_ADC0AIN5     0x00000020  // ADC Module 0 AIN5 Pin Present
+#define SYSCTL_DC8_ADC0AIN4     0x00000010  // ADC Module 0 AIN4 Pin Present
+#define SYSCTL_DC8_ADC0AIN3     0x00000008  // ADC Module 0 AIN3 Pin Present
+#define SYSCTL_DC8_ADC0AIN2     0x00000004  // ADC Module 0 AIN2 Pin Present
+#define SYSCTL_DC8_ADC0AIN1     0x00000002  // ADC Module 0 AIN1 Pin Present
+#define SYSCTL_DC8_ADC0AIN0     0x00000001  // ADC Module 0 AIN0 Pin Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PBORCTL register.
+//
+//*****************************************************************************
+#define SYSCTL_PBORCTL_BORIOR   0x00000002  // BOR Interrupt or Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCR0 register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCR0_WDT1       0x10000000  // WDT1 Reset Control
+#define SYSCTL_SRCR0_CAN1       0x02000000  // CAN1 Reset Control
+#define SYSCTL_SRCR0_CAN0       0x01000000  // CAN0 Reset Control
+#define SYSCTL_SRCR0_PWM        0x00100000  // PWM Reset Control
+#define SYSCTL_SRCR0_ADC1       0x00020000  // ADC1 Reset Control
+#define SYSCTL_SRCR0_ADC0       0x00010000  // ADC0 Reset Control
+#define SYSCTL_SRCR0_WDT0       0x00000008  // WDT0 Reset Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCR1 register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCR1_EPI0       0x40000000  // EPI0 Reset Control
+#define SYSCTL_SRCR1_I2S0       0x10000000  // I2S0 Reset Control
+#define SYSCTL_SRCR1_COMP2      0x04000000  // Analog Comp 2 Reset Control
+#define SYSCTL_SRCR1_COMP1      0x02000000  // Analog Comp 1 Reset Control
+#define SYSCTL_SRCR1_COMP0      0x01000000  // Analog Comp 0 Reset Control
+#define SYSCTL_SRCR1_TIMER3     0x00080000  // Timer 3 Reset Control
+#define SYSCTL_SRCR1_TIMER2     0x00040000  // Timer 2 Reset Control
+#define SYSCTL_SRCR1_TIMER1     0x00020000  // Timer 1 Reset Control
+#define SYSCTL_SRCR1_TIMER0     0x00010000  // Timer 0 Reset Control
+#define SYSCTL_SRCR1_I2C1       0x00004000  // I2C1 Reset Control
+#define SYSCTL_SRCR1_I2C0       0x00001000  // I2C0 Reset Control
+#define SYSCTL_SRCR1_QEI1       0x00000200  // QEI1 Reset Control
+#define SYSCTL_SRCR1_QEI0       0x00000100  // QEI0 Reset Control
+#define SYSCTL_SRCR1_SSI1       0x00000020  // SSI1 Reset Control
+#define SYSCTL_SRCR1_SSI0       0x00000010  // SSI0 Reset Control
+#define SYSCTL_SRCR1_UART2      0x00000004  // UART2 Reset Control
+#define SYSCTL_SRCR1_UART1      0x00000002  // UART1 Reset Control
+#define SYSCTL_SRCR1_UART0      0x00000001  // UART0 Reset Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCR2 register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCR2_EPHY0      0x40000000  // PHY0 Reset Control
+#define SYSCTL_SRCR2_EMAC0      0x10000000  // MAC0 Reset Control
+#define SYSCTL_SRCR2_USB0       0x00010000  // USB0 Reset Control
+#define SYSCTL_SRCR2_UDMA       0x00002000  // Micro-DMA Reset Control
+#define SYSCTL_SRCR2_GPIOJ      0x00000100  // Port J Reset Control
+#define SYSCTL_SRCR2_GPIOH      0x00000080  // Port H Reset Control
+#define SYSCTL_SRCR2_GPIOG      0x00000040  // Port G Reset Control
+#define SYSCTL_SRCR2_GPIOF      0x00000020  // Port F Reset Control
+#define SYSCTL_SRCR2_GPIOE      0x00000010  // Port E Reset Control
+#define SYSCTL_SRCR2_GPIOD      0x00000008  // Port D Reset Control
+#define SYSCTL_SRCR2_GPIOC      0x00000004  // Port C Reset Control
+#define SYSCTL_SRCR2_GPIOB      0x00000002  // Port B Reset Control
+#define SYSCTL_SRCR2_GPIOA      0x00000001  // Port A Reset Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RIS register.
+//
+//*****************************************************************************
+#define SYSCTL_RIS_MOSCPUPRIS   0x00000100  // MOSC Power Up Raw Interrupt
+                                            // Status
+#define SYSCTL_RIS_USBPLLLRIS   0x00000080  // USB PLL Lock Raw Interrupt
+                                            // Status
+#define SYSCTL_RIS_PLLLRIS      0x00000040  // PLL Lock Raw Interrupt Status
+#define SYSCTL_RIS_BORRIS       0x00000002  // Brown-Out Reset Raw Interrupt
+                                            // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_IMC register.
+//
+//*****************************************************************************
+#define SYSCTL_IMC_MOSCPUPIM    0x00000100  // MOSC Power Up Interrupt Mask
+#define SYSCTL_IMC_USBPLLLIM    0x00000080  // USB PLL Lock Interrupt Mask
+#define SYSCTL_IMC_PLLLIM       0x00000040  // PLL Lock Interrupt Mask
+#define SYSCTL_IMC_BORIM        0x00000002  // Brown-Out Reset Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_MISC register.
+//
+//*****************************************************************************
+#define SYSCTL_MISC_MOSCPUPMIS  0x00000100  // MOSC Power Up Masked Interrupt
+                                            // Status
+#define SYSCTL_MISC_USBPLLLMIS  0x00000080  // USB PLL Lock Masked Interrupt
+                                            // Status
+#define SYSCTL_MISC_PLLLMIS     0x00000040  // PLL Lock Masked Interrupt Status
+#define SYSCTL_MISC_BORMIS      0x00000002  // BOR Masked Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RESC register.
+//
+//*****************************************************************************
+#define SYSCTL_RESC_MOSCFAIL    0x00010000  // MOSC Failure Reset
+#define SYSCTL_RESC_WDT1        0x00000020  // Watchdog Timer 1 Reset
+#define SYSCTL_RESC_SW          0x00000010  // Software Reset
+#define SYSCTL_RESC_WDT0        0x00000008  // Watchdog Timer 0 Reset
+#define SYSCTL_RESC_BOR         0x00000004  // Brown-Out Reset
+#define SYSCTL_RESC_POR         0x00000002  // Power-On Reset
+#define SYSCTL_RESC_EXT         0x00000001  // External Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCC register.
+//
+//*****************************************************************************
+#define SYSCTL_RCC_ACG          0x08000000  // Auto Clock Gating
+#define SYSCTL_RCC_SYSDIV_M     0x07800000  // System Clock Divisor
+#define SYSCTL_RCC_USESYSDIV    0x00400000  // Enable System Clock Divider
+#define SYSCTL_RCC_USEPWMDIV    0x00100000  // Enable PWM Clock Divisor
+#define SYSCTL_RCC_PWMDIV_M     0x000E0000  // PWM Unit Clock Divisor
+#define SYSCTL_RCC_PWMDIV_2     0x00000000  // PWM clock /2
+#define SYSCTL_RCC_PWMDIV_4     0x00020000  // PWM clock /4
+#define SYSCTL_RCC_PWMDIV_8     0x00040000  // PWM clock /8
+#define SYSCTL_RCC_PWMDIV_16    0x00060000  // PWM clock /16
+#define SYSCTL_RCC_PWMDIV_32    0x00080000  // PWM clock /32
+#define SYSCTL_RCC_PWMDIV_64    0x000A0000  // PWM clock /64
+#define SYSCTL_RCC_PWRDN        0x00002000  // PLL Power Down
+#define SYSCTL_RCC_BYPASS       0x00000800  // PLL Bypass
+#define SYSCTL_RCC_XTAL_M       0x000007C0  // Crystal Value
+#define SYSCTL_RCC_XTAL_1MHZ    0x00000000  // 1 MHz
+#define SYSCTL_RCC_XTAL_1_84MHZ 0x00000040  // 1.8432 MHz
+#define SYSCTL_RCC_XTAL_2MHZ    0x00000080  // 2 MHz
+#define SYSCTL_RCC_XTAL_2_45MHZ 0x000000C0  // 2.4576 MHz
+#define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100  // 3.579545 MHz
+#define SYSCTL_RCC_XTAL_3_68MHZ 0x00000140  // 3.6864 MHz
+#define SYSCTL_RCC_XTAL_4MHZ    0x00000180  // 4 MHz
+#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0  // 4.096 MHz
+#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200  // 4.9152 MHz
+#define SYSCTL_RCC_XTAL_5MHZ    0x00000240  // 5 MHz
+#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280  // 5.12 MHz
+#define SYSCTL_RCC_XTAL_6MHZ    0x000002C0  // 6 MHz
+#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300  // 6.144 MHz
+#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340  // 7.3728 MHz
+#define SYSCTL_RCC_XTAL_8MHZ    0x00000380  // 8 MHz
+#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0  // 8.192 MHz
+#define SYSCTL_RCC_XTAL_10MHZ   0x00000400  // 10 MHz
+#define SYSCTL_RCC_XTAL_12MHZ   0x00000440  // 12 MHz
+#define SYSCTL_RCC_XTAL_12_2MHZ 0x00000480  // 12.288 MHz
+#define SYSCTL_RCC_XTAL_13_5MHZ 0x000004C0  // 13.56 MHz
+#define SYSCTL_RCC_XTAL_14_3MHZ 0x00000500  // 14.31818 MHz
+#define SYSCTL_RCC_XTAL_16MHZ   0x00000540  // 16 MHz
+#define SYSCTL_RCC_XTAL_16_3MHZ 0x00000580  // 16.384 MHz
+#define SYSCTL_RCC_OSCSRC_M     0x00000030  // Oscillator Source
+#define SYSCTL_RCC_OSCSRC_MAIN  0x00000000  // MOSC
+#define SYSCTL_RCC_OSCSRC_INT   0x00000010  // IOSC
+#define SYSCTL_RCC_OSCSRC_INT4  0x00000020  // IOSC/4
+#define SYSCTL_RCC_OSCSRC_30    0x00000030  // 30 kHz
+#define SYSCTL_RCC_IOSCDIS      0x00000002  // Internal Oscillator Disable
+#define SYSCTL_RCC_MOSCDIS      0x00000001  // Main Oscillator Disable
+#define SYSCTL_RCC_SYSDIV_S     23
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PLLCFG register.
+//
+//*****************************************************************************
+#define SYSCTL_PLLCFG_F_M       0x00003FE0  // PLL F Value
+#define SYSCTL_PLLCFG_R_M       0x0000001F  // PLL R Value
+#define SYSCTL_PLLCFG_F_S       5
+#define SYSCTL_PLLCFG_R_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_GPIOHBCTL
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_GPIOHBCTL_PORTJ  0x00000100  // Port J Advanced High-Performance
+                                            // Bus
+#define SYSCTL_GPIOHBCTL_PORTH  0x00000080  // Port H Advanced High-Performance
+                                            // Bus
+#define SYSCTL_GPIOHBCTL_PORTG  0x00000040  // Port G Advanced High-Performance
+                                            // Bus
+#define SYSCTL_GPIOHBCTL_PORTF  0x00000020  // Port F Advanced High-Performance
+                                            // Bus
+#define SYSCTL_GPIOHBCTL_PORTE  0x00000010  // Port E Advanced High-Performance
+                                            // Bus
+#define SYSCTL_GPIOHBCTL_PORTD  0x00000008  // Port D Advanced High-Performance
+                                            // Bus
+#define SYSCTL_GPIOHBCTL_PORTC  0x00000004  // Port C Advanced High-Performance
+                                            // Bus
+#define SYSCTL_GPIOHBCTL_PORTB  0x00000002  // Port B Advanced High-Performance
+                                            // Bus
+#define SYSCTL_GPIOHBCTL_PORTA  0x00000001  // Port A Advanced High-Performance
+                                            // Bus
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCC2_USERCC2     0x80000000  // Use RCC2
+#define SYSCTL_RCC2_DIV400      0x40000000  // Divide PLL as 400 MHz vs. 200
+                                            // MHz
+#define SYSCTL_RCC2_SYSDIV2_M   0x1F800000  // System Clock Divisor 2
+#define SYSCTL_RCC2_SYSDIV2_2   0x00800000  // System clock /2
+#define SYSCTL_RCC2_SYSDIV2_3   0x01000000  // System clock /3
+#define SYSCTL_RCC2_SYSDIV2_4   0x01800000  // System clock /4
+#define SYSCTL_RCC2_SYSDIV2_5   0x02000000  // System clock /5
+#define SYSCTL_RCC2_SYSDIV2_6   0x02800000  // System clock /6
+#define SYSCTL_RCC2_SYSDIV2_7   0x03000000  // System clock /7
+#define SYSCTL_RCC2_SYSDIV2_8   0x03800000  // System clock /8
+#define SYSCTL_RCC2_SYSDIV2_9   0x04000000  // System clock /9
+#define SYSCTL_RCC2_SYSDIV2_10  0x04800000  // System clock /10
+#define SYSCTL_RCC2_SYSDIV2_11  0x05000000  // System clock /11
+#define SYSCTL_RCC2_SYSDIV2_12  0x05800000  // System clock /12
+#define SYSCTL_RCC2_SYSDIV2_13  0x06000000  // System clock /13
+#define SYSCTL_RCC2_SYSDIV2_14  0x06800000  // System clock /14
+#define SYSCTL_RCC2_SYSDIV2_15  0x07000000  // System clock /15
+#define SYSCTL_RCC2_SYSDIV2_16  0x07800000  // System clock /16
+#define SYSCTL_RCC2_SYSDIV2_17  0x08000000  // System clock /17
+#define SYSCTL_RCC2_SYSDIV2_18  0x08800000  // System clock /18
+#define SYSCTL_RCC2_SYSDIV2_19  0x09000000  // System clock /19
+#define SYSCTL_RCC2_SYSDIV2_20  0x09800000  // System clock /20
+#define SYSCTL_RCC2_SYSDIV2_21  0x0A000000  // System clock /21
+#define SYSCTL_RCC2_SYSDIV2_22  0x0A800000  // System clock /22
+#define SYSCTL_RCC2_SYSDIV2_23  0x0B000000  // System clock /23
+#define SYSCTL_RCC2_SYSDIV2_24  0x0B800000  // System clock /24
+#define SYSCTL_RCC2_SYSDIV2_25  0x0C000000  // System clock /25
+#define SYSCTL_RCC2_SYSDIV2_26  0x0C800000  // System clock /26
+#define SYSCTL_RCC2_SYSDIV2_27  0x0D000000  // System clock /27
+#define SYSCTL_RCC2_SYSDIV2_28  0x0D800000  // System clock /28
+#define SYSCTL_RCC2_SYSDIV2_29  0x0E000000  // System clock /29
+#define SYSCTL_RCC2_SYSDIV2_30  0x0E800000  // System clock /30
+#define SYSCTL_RCC2_SYSDIV2_31  0x0F000000  // System clock /31
+#define SYSCTL_RCC2_SYSDIV2_32  0x0F800000  // System clock /32
+#define SYSCTL_RCC2_SYSDIV2_33  0x10000000  // System clock /33
+#define SYSCTL_RCC2_SYSDIV2_34  0x10800000  // System clock /34
+#define SYSCTL_RCC2_SYSDIV2_35  0x11000000  // System clock /35
+#define SYSCTL_RCC2_SYSDIV2_36  0x11800000  // System clock /36
+#define SYSCTL_RCC2_SYSDIV2_37  0x12000000  // System clock /37
+#define SYSCTL_RCC2_SYSDIV2_38  0x12800000  // System clock /38
+#define SYSCTL_RCC2_SYSDIV2_39  0x13000000  // System clock /39
+#define SYSCTL_RCC2_SYSDIV2_40  0x13800000  // System clock /40
+#define SYSCTL_RCC2_SYSDIV2_41  0x14000000  // System clock /41
+#define SYSCTL_RCC2_SYSDIV2_42  0x14800000  // System clock /42
+#define SYSCTL_RCC2_SYSDIV2_43  0x15000000  // System clock /43
+#define SYSCTL_RCC2_SYSDIV2_44  0x15800000  // System clock /44
+#define SYSCTL_RCC2_SYSDIV2_45  0x16000000  // System clock /45
+#define SYSCTL_RCC2_SYSDIV2_46  0x16800000  // System clock /46
+#define SYSCTL_RCC2_SYSDIV2_47  0x17000000  // System clock /47
+#define SYSCTL_RCC2_SYSDIV2_48  0x17800000  // System clock /48
+#define SYSCTL_RCC2_SYSDIV2_49  0x18000000  // System clock /49
+#define SYSCTL_RCC2_SYSDIV2_50  0x18800000  // System clock /50
+#define SYSCTL_RCC2_SYSDIV2_51  0x19000000  // System clock /51
+#define SYSCTL_RCC2_SYSDIV2_52  0x19800000  // System clock /52
+#define SYSCTL_RCC2_SYSDIV2_53  0x1A000000  // System clock /53
+#define SYSCTL_RCC2_SYSDIV2_54  0x1A800000  // System clock /54
+#define SYSCTL_RCC2_SYSDIV2_55  0x1B000000  // System clock /55
+#define SYSCTL_RCC2_SYSDIV2_56  0x1B800000  // System clock /56
+#define SYSCTL_RCC2_SYSDIV2_57  0x1C000000  // System clock /57
+#define SYSCTL_RCC2_SYSDIV2_58  0x1C800000  // System clock /58
+#define SYSCTL_RCC2_SYSDIV2_59  0x1D000000  // System clock /59
+#define SYSCTL_RCC2_SYSDIV2_60  0x1D800000  // System clock /60
+#define SYSCTL_RCC2_SYSDIV2_61  0x1E000000  // System clock /61
+#define SYSCTL_RCC2_SYSDIV2_62  0x1E800000  // System clock /62
+#define SYSCTL_RCC2_SYSDIV2_63  0x1F000000  // System clock /63
+#define SYSCTL_RCC2_SYSDIV2_64  0x1F800000  // System clock /64
+#define SYSCTL_RCC2_SYSDIV2LSB  0x00400000  // Additional LSB for SYSDIV2
+#define SYSCTL_RCC2_USBPWRDN    0x00004000  // Power-Down USB PLL
+#define SYSCTL_RCC2_PWRDN2      0x00002000  // Power-Down PLL 2
+#define SYSCTL_RCC2_BYPASS2     0x00000800  // PLL Bypass 2
+#define SYSCTL_RCC2_OSCSRC2_M   0x00000070  // Oscillator Source 2
+#define SYSCTL_RCC2_OSCSRC2_MO  0x00000000  // MOSC
+#define SYSCTL_RCC2_OSCSRC2_IO  0x00000010  // PIOSC
+#define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020  // PIOSC/4
+#define SYSCTL_RCC2_OSCSRC2_30  0x00000030  // 30 kHz
+#define SYSCTL_RCC2_SYSDIV2_S   23
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_MOSCCTL register.
+//
+//*****************************************************************************
+#define SYSCTL_MOSCCTL_CVAL     0x00000001  // Clock Validation for MOSC
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGC0_WDT1       0x10000000  // WDT1 Clock Gating Control
+#define SYSCTL_RCGC0_CAN1       0x02000000  // CAN1 Clock Gating Control
+#define SYSCTL_RCGC0_CAN0       0x01000000  // CAN0 Clock Gating Control
+#define SYSCTL_RCGC0_PWM        0x00100000  // PWM Clock Gating Control
+#define SYSCTL_RCGC0_ADC1       0x00020000  // ADC1 Clock Gating Control
+#define SYSCTL_RCGC0_ADC0       0x00010000  // ADC0 Clock Gating Control
+#define SYSCTL_RCGC0_ADC1SPD_M  0x00000C00  // ADC1 Sample Speed
+#define SYSCTL_RCGC0_ADC1SPD_125K \
+                                0x00000000  // 125K samples/second
+#define SYSCTL_RCGC0_ADC1SPD_250K \
+                                0x00000400  // 250K samples/second
+#define SYSCTL_RCGC0_ADC1SPD_500K \
+                                0x00000800  // 500K samples/second
+#define SYSCTL_RCGC0_ADC1SPD_1M 0x00000C00  // 1M samples/second
+#define SYSCTL_RCGC0_ADC0SPD_M  0x00000300  // ADC0 Sample Speed
+#define SYSCTL_RCGC0_ADC0SPD_125K \
+                                0x00000000  // 125K samples/second
+#define SYSCTL_RCGC0_ADC0SPD_250K \
+                                0x00000100  // 250K samples/second
+#define SYSCTL_RCGC0_ADC0SPD_500K \
+                                0x00000200  // 500K samples/second
+#define SYSCTL_RCGC0_ADC0SPD_1M 0x00000300  // 1M samples/second
+#define SYSCTL_RCGC0_WDT0       0x00000008  // WDT0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGC1_EPI0       0x40000000  // EPI0 Clock Gating
+#define SYSCTL_RCGC1_I2S0       0x10000000  // I2S0 Clock Gating
+#define SYSCTL_RCGC1_COMP2      0x04000000  // Analog Comparator 2 Clock Gating
+#define SYSCTL_RCGC1_COMP1      0x02000000  // Analog Comparator 1 Clock Gating
+#define SYSCTL_RCGC1_COMP0      0x01000000  // Analog Comparator 0 Clock Gating
+#define SYSCTL_RCGC1_TIMER3     0x00080000  // Timer 3 Clock Gating Control
+#define SYSCTL_RCGC1_TIMER2     0x00040000  // Timer 2 Clock Gating Control
+#define SYSCTL_RCGC1_TIMER1     0x00020000  // Timer 1 Clock Gating Control
+#define SYSCTL_RCGC1_TIMER0     0x00010000  // Timer 0 Clock Gating Control
+#define SYSCTL_RCGC1_I2C1       0x00004000  // I2C1 Clock Gating Control
+#define SYSCTL_RCGC1_I2C0       0x00001000  // I2C0 Clock Gating Control
+#define SYSCTL_RCGC1_QEI1       0x00000200  // QEI1 Clock Gating Control
+#define SYSCTL_RCGC1_QEI0       0x00000100  // QEI0 Clock Gating Control
+#define SYSCTL_RCGC1_SSI1       0x00000020  // SSI1 Clock Gating Control
+#define SYSCTL_RCGC1_SSI0       0x00000010  // SSI0 Clock Gating Control
+#define SYSCTL_RCGC1_UART2      0x00000004  // UART2 Clock Gating Control
+#define SYSCTL_RCGC1_UART1      0x00000002  // UART1 Clock Gating Control
+#define SYSCTL_RCGC1_UART0      0x00000001  // UART0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGC2_EPHY0      0x40000000  // PHY0 Clock Gating Control
+#define SYSCTL_RCGC2_EMAC0      0x10000000  // MAC0 Clock Gating Control
+#define SYSCTL_RCGC2_USB0       0x00010000  // USB0 Clock Gating Control
+#define SYSCTL_RCGC2_UDMA       0x00002000  // Micro-DMA Clock Gating Control
+#define SYSCTL_RCGC2_GPIOJ      0x00000100  // Port J Clock Gating Control
+#define SYSCTL_RCGC2_GPIOH      0x00000080  // Port H Clock Gating Control
+#define SYSCTL_RCGC2_GPIOG      0x00000040  // Port G Clock Gating Control
+#define SYSCTL_RCGC2_GPIOF      0x00000020  // Port F Clock Gating Control
+#define SYSCTL_RCGC2_GPIOE      0x00000010  // Port E Clock Gating Control
+#define SYSCTL_RCGC2_GPIOD      0x00000008  // Port D Clock Gating Control
+#define SYSCTL_RCGC2_GPIOC      0x00000004  // Port C Clock Gating Control
+#define SYSCTL_RCGC2_GPIOB      0x00000002  // Port B Clock Gating Control
+#define SYSCTL_RCGC2_GPIOA      0x00000001  // Port A Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGC0_WDT1       0x10000000  // WDT1 Clock Gating Control
+#define SYSCTL_SCGC0_CAN1       0x02000000  // CAN1 Clock Gating Control
+#define SYSCTL_SCGC0_CAN0       0x01000000  // CAN0 Clock Gating Control
+#define SYSCTL_SCGC0_PWM        0x00100000  // PWM Clock Gating Control
+#define SYSCTL_SCGC0_ADC1       0x00020000  // ADC1 Clock Gating Control
+#define SYSCTL_SCGC0_ADC0       0x00010000  // ADC0 Clock Gating Control
+#define SYSCTL_SCGC0_ADC1SPD_M  0x00000C00  // ADC1 Sample Speed
+#define SYSCTL_SCGC0_ADC1SPD_125K \
+                                0x00000000  // 125K samples/second
+#define SYSCTL_SCGC0_ADC1SPD_250K \
+                                0x00000400  // 250K samples/second
+#define SYSCTL_SCGC0_ADC1SPD_500K \
+                                0x00000800  // 500K samples/second
+#define SYSCTL_SCGC0_ADC1SPD_1M 0x00000C00  // 1M samples/second
+#define SYSCTL_SCGC0_ADC0SPD_M  0x00000300  // ADC0 Sample Speed
+#define SYSCTL_SCGC0_ADC0SPD_125K \
+                                0x00000000  // 125K samples/second
+#define SYSCTL_SCGC0_ADC0SPD_250K \
+                                0x00000100  // 250K samples/second
+#define SYSCTL_SCGC0_ADC0SPD_500K \
+                                0x00000200  // 500K samples/second
+#define SYSCTL_SCGC0_ADC0SPD_1M 0x00000300  // 1M samples/second
+#define SYSCTL_SCGC0_WDT0       0x00000008  // WDT0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGC1_EPI0       0x40000000  // EPI0 Clock Gating
+#define SYSCTL_SCGC1_I2S0       0x10000000  // I2S0 Clock Gating
+#define SYSCTL_SCGC1_COMP2      0x04000000  // Analog Comparator 2 Clock Gating
+#define SYSCTL_SCGC1_COMP1      0x02000000  // Analog Comparator 1 Clock Gating
+#define SYSCTL_SCGC1_COMP0      0x01000000  // Analog Comparator 0 Clock Gating
+#define SYSCTL_SCGC1_TIMER3     0x00080000  // Timer 3 Clock Gating Control
+#define SYSCTL_SCGC1_TIMER2     0x00040000  // Timer 2 Clock Gating Control
+#define SYSCTL_SCGC1_TIMER1     0x00020000  // Timer 1 Clock Gating Control
+#define SYSCTL_SCGC1_TIMER0     0x00010000  // Timer 0 Clock Gating Control
+#define SYSCTL_SCGC1_I2C1       0x00004000  // I2C1 Clock Gating Control
+#define SYSCTL_SCGC1_I2C0       0x00001000  // I2C0 Clock Gating Control
+#define SYSCTL_SCGC1_QEI1       0x00000200  // QEI1 Clock Gating Control
+#define SYSCTL_SCGC1_QEI0       0x00000100  // QEI0 Clock Gating Control
+#define SYSCTL_SCGC1_SSI1       0x00000020  // SSI1 Clock Gating Control
+#define SYSCTL_SCGC1_SSI0       0x00000010  // SSI0 Clock Gating Control
+#define SYSCTL_SCGC1_UART2      0x00000004  // UART2 Clock Gating Control
+#define SYSCTL_SCGC1_UART1      0x00000002  // UART1 Clock Gating Control
+#define SYSCTL_SCGC1_UART0      0x00000001  // UART0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGC2_EPHY0      0x40000000  // PHY0 Clock Gating Control
+#define SYSCTL_SCGC2_EMAC0      0x10000000  // MAC0 Clock Gating Control
+#define SYSCTL_SCGC2_USB0       0x00010000  // USB0 Clock Gating Control
+#define SYSCTL_SCGC2_UDMA       0x00002000  // Micro-DMA Clock Gating Control
+#define SYSCTL_SCGC2_GPIOJ      0x00000100  // Port J Clock Gating Control
+#define SYSCTL_SCGC2_GPIOH      0x00000080  // Port H Clock Gating Control
+#define SYSCTL_SCGC2_GPIOG      0x00000040  // Port G Clock Gating Control
+#define SYSCTL_SCGC2_GPIOF      0x00000020  // Port F Clock Gating Control
+#define SYSCTL_SCGC2_GPIOE      0x00000010  // Port E Clock Gating Control
+#define SYSCTL_SCGC2_GPIOD      0x00000008  // Port D Clock Gating Control
+#define SYSCTL_SCGC2_GPIOC      0x00000004  // Port C Clock Gating Control
+#define SYSCTL_SCGC2_GPIOB      0x00000002  // Port B Clock Gating Control
+#define SYSCTL_SCGC2_GPIOA      0x00000001  // Port A Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGC0_WDT1       0x10000000  // WDT1 Clock Gating Control
+#define SYSCTL_DCGC0_CAN1       0x02000000  // CAN1 Clock Gating Control
+#define SYSCTL_DCGC0_CAN0       0x01000000  // CAN0 Clock Gating Control
+#define SYSCTL_DCGC0_PWM        0x00100000  // PWM Clock Gating Control
+#define SYSCTL_DCGC0_ADC1       0x00020000  // ADC1 Clock Gating Control
+#define SYSCTL_DCGC0_ADC0       0x00010000  // ADC0 Clock Gating Control
+#define SYSCTL_DCGC0_WDT0       0x00000008  // WDT0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGC1_EPI0       0x40000000  // EPI0 Clock Gating
+#define SYSCTL_DCGC1_I2S0       0x10000000  // I2S0 Clock Gating
+#define SYSCTL_DCGC1_COMP2      0x04000000  // Analog Comparator 2 Clock Gating
+#define SYSCTL_DCGC1_COMP1      0x02000000  // Analog Comparator 1 Clock Gating
+#define SYSCTL_DCGC1_COMP0      0x01000000  // Analog Comparator 0 Clock Gating
+#define SYSCTL_DCGC1_TIMER3     0x00080000  // Timer 3 Clock Gating Control
+#define SYSCTL_DCGC1_TIMER2     0x00040000  // Timer 2 Clock Gating Control
+#define SYSCTL_DCGC1_TIMER1     0x00020000  // Timer 1 Clock Gating Control
+#define SYSCTL_DCGC1_TIMER0     0x00010000  // Timer 0 Clock Gating Control
+#define SYSCTL_DCGC1_I2C1       0x00004000  // I2C1 Clock Gating Control
+#define SYSCTL_DCGC1_I2C0       0x00001000  // I2C0 Clock Gating Control
+#define SYSCTL_DCGC1_QEI1       0x00000200  // QEI1 Clock Gating Control
+#define SYSCTL_DCGC1_QEI0       0x00000100  // QEI0 Clock Gating Control
+#define SYSCTL_DCGC1_SSI1       0x00000020  // SSI1 Clock Gating Control
+#define SYSCTL_DCGC1_SSI0       0x00000010  // SSI0 Clock Gating Control
+#define SYSCTL_DCGC1_UART2      0x00000004  // UART2 Clock Gating Control
+#define SYSCTL_DCGC1_UART1      0x00000002  // UART1 Clock Gating Control
+#define SYSCTL_DCGC1_UART0      0x00000001  // UART0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGC2_EPHY0      0x40000000  // PHY0 Clock Gating Control
+#define SYSCTL_DCGC2_EMAC0      0x10000000  // MAC0 Clock Gating Control
+#define SYSCTL_DCGC2_USB0       0x00010000  // USB0 Clock Gating Control
+#define SYSCTL_DCGC2_UDMA       0x00002000  // Micro-DMA Clock Gating Control
+#define SYSCTL_DCGC2_GPIOJ      0x00000100  // Port J Clock Gating Control
+#define SYSCTL_DCGC2_GPIOH      0x00000080  // Port H Clock Gating Control
+#define SYSCTL_DCGC2_GPIOG      0x00000040  // Port G Clock Gating Control
+#define SYSCTL_DCGC2_GPIOF      0x00000020  // Port F Clock Gating Control
+#define SYSCTL_DCGC2_GPIOE      0x00000010  // Port E Clock Gating Control
+#define SYSCTL_DCGC2_GPIOD      0x00000008  // Port D Clock Gating Control
+#define SYSCTL_DCGC2_GPIOC      0x00000004  // Port C Clock Gating Control
+#define SYSCTL_DCGC2_GPIOB      0x00000002  // Port B Clock Gating Control
+#define SYSCTL_DCGC2_GPIOA      0x00000001  // Port A Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DSLPCLKCFG
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DSLPCLKCFG_D_M   0x1F800000  // Divider Field Override
+#define SYSCTL_DSLPCLKCFG_D_1   0x00000000  // System clock /1
+#define SYSCTL_DSLPCLKCFG_D_2   0x00800000  // System clock /2
+#define SYSCTL_DSLPCLKCFG_D_3   0x01000000  // System clock /3
+#define SYSCTL_DSLPCLKCFG_D_4   0x01800000  // System clock /4
+#define SYSCTL_DSLPCLKCFG_D_64  0x1F800000  // System clock /64
+#define SYSCTL_DSLPCLKCFG_O_M   0x00000070  // Clock Source
+#define SYSCTL_DSLPCLKCFG_O_IGN 0x00000000  // MOSC
+#define SYSCTL_DSLPCLKCFG_O_IO  0x00000010  // PIOSC
+#define SYSCTL_DSLPCLKCFG_O_30  0x00000030  // 30 kHz
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PIOSCCAL
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PIOSCCAL_UTEN    0x80000000  // Use User Trim Value
+#define SYSCTL_PIOSCCAL_UPDATE  0x00000100  // Update Trim
+#define SYSCTL_PIOSCCAL_UT_M    0x0000007F  // User Trim Value
+#define SYSCTL_PIOSCCAL_UT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_I2SMCLKCFG
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_I2SMCLKCFG_RXEN  0x80000000  // RX Clock Enable
+#define SYSCTL_I2SMCLKCFG_RXI_M 0x3FF00000  // RX Clock Integer Input
+#define SYSCTL_I2SMCLKCFG_RXF_M 0x000F0000  // RX Clock Fractional Input
+#define SYSCTL_I2SMCLKCFG_TXEN  0x00008000  // TX Clock Enable
+#define SYSCTL_I2SMCLKCFG_TXI_M 0x00003FF0  // TX Clock Integer Input
+#define SYSCTL_I2SMCLKCFG_TXF_M 0x0000000F  // TX Clock Fractional Input
+#define SYSCTL_I2SMCLKCFG_RXI_S 20
+#define SYSCTL_I2SMCLKCFG_RXF_S 16
+#define SYSCTL_I2SMCLKCFG_TXI_S 4
+#define SYSCTL_I2SMCLKCFG_TXF_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC9 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC9_ADC1DC7      0x00800000  // ADC1 DC7 Present
+#define SYSCTL_DC9_ADC1DC6      0x00400000  // ADC1 DC6 Present
+#define SYSCTL_DC9_ADC1DC5      0x00200000  // ADC1 DC5 Present
+#define SYSCTL_DC9_ADC1DC4      0x00100000  // ADC1 DC4 Present
+#define SYSCTL_DC9_ADC1DC3      0x00080000  // ADC1 DC3 Present
+#define SYSCTL_DC9_ADC1DC2      0x00040000  // ADC1 DC2 Present
+#define SYSCTL_DC9_ADC1DC1      0x00020000  // ADC1 DC1 Present
+#define SYSCTL_DC9_ADC1DC0      0x00010000  // ADC1 DC0 Present
+#define SYSCTL_DC9_ADC0DC7      0x00000080  // ADC0 DC7 Present
+#define SYSCTL_DC9_ADC0DC6      0x00000040  // ADC0 DC6 Present
+#define SYSCTL_DC9_ADC0DC5      0x00000020  // ADC0 DC5 Present
+#define SYSCTL_DC9_ADC0DC4      0x00000010  // ADC0 DC4 Present
+#define SYSCTL_DC9_ADC0DC3      0x00000008  // ADC0 DC3 Present
+#define SYSCTL_DC9_ADC0DC2      0x00000004  // ADC0 DC2 Present
+#define SYSCTL_DC9_ADC0DC1      0x00000002  // ADC0 DC1 Present
+#define SYSCTL_DC9_ADC0DC0      0x00000001  // ADC0 DC0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_NVMSTAT register.
+//
+//*****************************************************************************
+#define SYSCTL_NVMSTAT_FWB      0x00000001  // 32 Word Flash Write Buffer
+                                            // Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_STAT register.
+//
+//*****************************************************************************
+#define UDMA_STAT_DMACHANS_M    0x001F0000  // Available uDMA Channels Minus 1
+#define UDMA_STAT_STATE_M       0x000000F0  // Control State Machine Status
+#define UDMA_STAT_STATE_IDLE    0x00000000  // Idle
+#define UDMA_STAT_STATE_RD_CTRL 0x00000010  // Reading channel controller data
+#define UDMA_STAT_STATE_RD_SRCENDP \
+                                0x00000020  // Reading source end pointer
+#define UDMA_STAT_STATE_RD_DSTENDP \
+                                0x00000030  // Reading destination end pointer
+#define UDMA_STAT_STATE_RD_SRCDAT \
+                                0x00000040  // Reading source data
+#define UDMA_STAT_STATE_WR_DSTDAT \
+                                0x00000050  // Writing destination data
+#define UDMA_STAT_STATE_WAIT    0x00000060  // Waiting for uDMA request to
+                                            // clear
+#define UDMA_STAT_STATE_WR_CTRL 0x00000070  // Writing channel controller data
+#define UDMA_STAT_STATE_STALL   0x00000080  // Stalled
+#define UDMA_STAT_STATE_DONE    0x00000090  // Done
+#define UDMA_STAT_STATE_UNDEF   0x000000A0  // Undefined
+#define UDMA_STAT_MASTEN        0x00000001  // Master Enable Status
+#define UDMA_STAT_DMACHANS_S    16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CFG register.
+//
+//*****************************************************************************
+#define UDMA_CFG_MASTEN         0x00000001  // Controller Master Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CTLBASE register.
+//
+//*****************************************************************************
+#define UDMA_CTLBASE_ADDR_M     0xFFFFFC00  // Channel Control Base Address
+#define UDMA_CTLBASE_ADDR_S     10
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ALTBASE register.
+//
+//*****************************************************************************
+#define UDMA_ALTBASE_ADDR_M     0xFFFFFFFF  // Alternate Channel Address
+                                            // Pointer
+#define UDMA_ALTBASE_ADDR_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_WAITSTAT register.
+//
+//*****************************************************************************
+#define UDMA_WAITSTAT_WAITREQ_M 0xFFFFFFFF  // Channel [n] Wait Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_SWREQ register.
+//
+//*****************************************************************************
+#define UDMA_SWREQ_M            0xFFFFFFFF  // Channel [n] Software Request
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_USEBURSTSET
+// register.
+//
+//*****************************************************************************
+#define UDMA_USEBURSTSET_SET_M  0xFFFFFFFF  // Channel [n] Useburst Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_USEBURSTCLR
+// register.
+//
+//*****************************************************************************
+#define UDMA_USEBURSTCLR_CLR_M  0xFFFFFFFF  // Channel [n] Useburst Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_REQMASKSET
+// register.
+//
+//*****************************************************************************
+#define UDMA_REQMASKSET_SET_M   0xFFFFFFFF  // Channel [n] Request Mask Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_REQMASKCLR
+// register.
+//
+//*****************************************************************************
+#define UDMA_REQMASKCLR_CLR_M   0xFFFFFFFF  // Channel [n] Request Mask Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ENASET register.
+//
+//*****************************************************************************
+#define UDMA_ENASET_SET_M       0xFFFFFFFF  // Channel [n] Enable Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ENACLR register.
+//
+//*****************************************************************************
+#define UDMA_ENACLR_CLR_M       0xFFFFFFFF  // Clear Channel [n] Enable Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ALTSET register.
+//
+//*****************************************************************************
+#define UDMA_ALTSET_SET_M       0xFFFFFFFF  // Channel [n] Alternate Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ALTCLR register.
+//
+//*****************************************************************************
+#define UDMA_ALTCLR_CLR_M       0xFFFFFFFF  // Channel [n] Alternate Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_PRIOSET register.
+//
+//*****************************************************************************
+#define UDMA_PRIOSET_SET_M      0xFFFFFFFF  // Channel [n] Priority Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_PRIOCLR register.
+//
+//*****************************************************************************
+#define UDMA_PRIOCLR_CLR_M      0xFFFFFFFF  // Channel [n] Priority Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ERRCLR register.
+//
+//*****************************************************************************
+#define UDMA_ERRCLR_ERRCLR      0x00000001  // uDMA Bus Error Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CHASGN register.
+//
+//*****************************************************************************
+#define UDMA_CHASGN_M           0xFFFFFFFF  // Channel [n] Assignment Select
+#define UDMA_CHASGN_PRIMARY     0x00000000  // Use the primary channel
+                                            // assignment
+#define UDMA_CHASGN_SECONDARY   0x00000001  // Use the secondary channel
+                                            // assignment
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CHIS register.
+//
+//*****************************************************************************
+#define UDMA_CHIS_M             0xFFFFFFFF  // Channel [n] Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_O_SRCENDP register.
+//
+//*****************************************************************************
+#define UDMA_SRCENDP_ADDR_M     0xFFFFFFFF  // Source Address End Pointer
+#define UDMA_SRCENDP_ADDR_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_O_DSTENDP register.
+//
+//*****************************************************************************
+#define UDMA_DSTENDP_ADDR_M     0xFFFFFFFF  // Destination Address End Pointer
+#define UDMA_DSTENDP_ADDR_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_O_CHCTL register.
+//
+//*****************************************************************************
+#define UDMA_CHCTL_DSTINC_M     0xC0000000  // Destination Address Increment
+#define UDMA_CHCTL_DSTINC_8     0x00000000  // Byte
+#define UDMA_CHCTL_DSTINC_16    0x40000000  // Half-word
+#define UDMA_CHCTL_DSTINC_32    0x80000000  // Word
+#define UDMA_CHCTL_DSTINC_NONE  0xC0000000  // No increment
+#define UDMA_CHCTL_DSTSIZE_M    0x30000000  // Destination Data Size
+#define UDMA_CHCTL_DSTSIZE_8    0x00000000  // Byte
+#define UDMA_CHCTL_DSTSIZE_16   0x10000000  // Half-word
+#define UDMA_CHCTL_DSTSIZE_32   0x20000000  // Word
+#define UDMA_CHCTL_SRCINC_M     0x0C000000  // Source Address Increment
+#define UDMA_CHCTL_SRCINC_8     0x00000000  // Byte
+#define UDMA_CHCTL_SRCINC_16    0x04000000  // Half-word
+#define UDMA_CHCTL_SRCINC_32    0x08000000  // Word
+#define UDMA_CHCTL_SRCINC_NONE  0x0C000000  // No increment
+#define UDMA_CHCTL_SRCSIZE_M    0x03000000  // Source Data Size
+#define UDMA_CHCTL_SRCSIZE_8    0x00000000  // Byte
+#define UDMA_CHCTL_SRCSIZE_16   0x01000000  // Half-word
+#define UDMA_CHCTL_SRCSIZE_32   0x02000000  // Word
+#define UDMA_CHCTL_ARBSIZE_M    0x0003C000  // Arbitration Size
+#define UDMA_CHCTL_ARBSIZE_1    0x00000000  // 1 Transfer
+#define UDMA_CHCTL_ARBSIZE_2    0x00004000  // 2 Transfers
+#define UDMA_CHCTL_ARBSIZE_4    0x00008000  // 4 Transfers
+#define UDMA_CHCTL_ARBSIZE_8    0x0000C000  // 8 Transfers
+#define UDMA_CHCTL_ARBSIZE_16   0x00010000  // 16 Transfers
+#define UDMA_CHCTL_ARBSIZE_32   0x00014000  // 32 Transfers
+#define UDMA_CHCTL_ARBSIZE_64   0x00018000  // 64 Transfers
+#define UDMA_CHCTL_ARBSIZE_128  0x0001C000  // 128 Transfers
+#define UDMA_CHCTL_ARBSIZE_256  0x00020000  // 256 Transfers
+#define UDMA_CHCTL_ARBSIZE_512  0x00024000  // 512 Transfers
+#define UDMA_CHCTL_ARBSIZE_1024 0x00028000  // 1024 Transfers
+#define UDMA_CHCTL_XFERSIZE_M   0x00003FF0  // Transfer Size (minus 1)
+#define UDMA_CHCTL_NXTUSEBURST  0x00000008  // Next Useburst
+#define UDMA_CHCTL_XFERMODE_M   0x00000007  // uDMA Transfer Mode
+#define UDMA_CHCTL_XFERMODE_STOP \
+                                0x00000000  // Stop
+#define UDMA_CHCTL_XFERMODE_BASIC \
+                                0x00000001  // Basic
+#define UDMA_CHCTL_XFERMODE_AUTO \
+                                0x00000002  // Auto-Request
+#define UDMA_CHCTL_XFERMODE_PINGPONG \
+                                0x00000003  // Ping-Pong
+#define UDMA_CHCTL_XFERMODE_MEM_SG \
+                                0x00000004  // Memory Scatter-Gather
+#define UDMA_CHCTL_XFERMODE_MEM_SGA \
+                                0x00000005  // Alternate Memory Scatter-Gather
+#define UDMA_CHCTL_XFERMODE_PER_SG \
+                                0x00000006  // Peripheral Scatter-Gather
+#define UDMA_CHCTL_XFERMODE_PER_SGA \
+                                0x00000007  // Alternate Peripheral
+                                            // Scatter-Gather
+#define UDMA_CHCTL_XFERSIZE_S   4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_INT_TYPE register.
+//
+//*****************************************************************************
+#define NVIC_INT_TYPE_LINES_M   0x0000001F  // Number of interrupt lines (x32)
+#define NVIC_INT_TYPE_LINES_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTLR register.
+//
+//*****************************************************************************
+#define NVIC_ACTLR_DISFOLD      0x00000004  // Disable IT Folding
+#define NVIC_ACTLR_DISWBUF      0x00000002  // Disable Write Buffer
+#define NVIC_ACTLR_DISMCYC      0x00000001  // Disable Interrupts of Multiple
+                                            // Cycle Instructions
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_ST_CTRL_COUNT      0x00010000  // Count Flag
+#define NVIC_ST_CTRL_CLK_SRC    0x00000004  // Clock Source
+#define NVIC_ST_CTRL_INTEN      0x00000002  // Interrupt Enable
+#define NVIC_ST_CTRL_ENABLE     0x00000001  // Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_RELOAD register.
+//
+//*****************************************************************************
+#define NVIC_ST_RELOAD_M        0x00FFFFFF  // Reload Value
+#define NVIC_ST_RELOAD_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_CURRENT
+// register.
+//
+//*****************************************************************************
+#define NVIC_ST_CURRENT_M       0x00FFFFFF  // Current Value
+#define NVIC_ST_CURRENT_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_CAL register.
+//
+//*****************************************************************************
+#define NVIC_ST_CAL_NOREF       0x80000000  // No reference clock
+#define NVIC_ST_CAL_SKEW        0x40000000  // Clock skew
+#define NVIC_ST_CAL_ONEMS_M     0x00FFFFFF  // 1ms reference value
+#define NVIC_ST_CAL_ONEMS_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN0 register.
+//
+//*****************************************************************************
+#define NVIC_EN0_INT_M          0xFFFFFFFF  // Interrupt Enable
+#define NVIC_EN0_INT0           0x00000001  // Interrupt 0 enable
+#define NVIC_EN0_INT1           0x00000002  // Interrupt 1 enable
+#define NVIC_EN0_INT2           0x00000004  // Interrupt 2 enable
+#define NVIC_EN0_INT3           0x00000008  // Interrupt 3 enable
+#define NVIC_EN0_INT4           0x00000010  // Interrupt 4 enable
+#define NVIC_EN0_INT5           0x00000020  // Interrupt 5 enable
+#define NVIC_EN0_INT6           0x00000040  // Interrupt 6 enable
+#define NVIC_EN0_INT7           0x00000080  // Interrupt 7 enable
+#define NVIC_EN0_INT8           0x00000100  // Interrupt 8 enable
+#define NVIC_EN0_INT9           0x00000200  // Interrupt 9 enable
+#define NVIC_EN0_INT10          0x00000400  // Interrupt 10 enable
+#define NVIC_EN0_INT11          0x00000800  // Interrupt 11 enable
+#define NVIC_EN0_INT12          0x00001000  // Interrupt 12 enable
+#define NVIC_EN0_INT13          0x00002000  // Interrupt 13 enable
+#define NVIC_EN0_INT14          0x00004000  // Interrupt 14 enable
+#define NVIC_EN0_INT15          0x00008000  // Interrupt 15 enable
+#define NVIC_EN0_INT16          0x00010000  // Interrupt 16 enable
+#define NVIC_EN0_INT17          0x00020000  // Interrupt 17 enable
+#define NVIC_EN0_INT18          0x00040000  // Interrupt 18 enable
+#define NVIC_EN0_INT19          0x00080000  // Interrupt 19 enable
+#define NVIC_EN0_INT20          0x00100000  // Interrupt 20 enable
+#define NVIC_EN0_INT21          0x00200000  // Interrupt 21 enable
+#define NVIC_EN0_INT22          0x00400000  // Interrupt 22 enable
+#define NVIC_EN0_INT23          0x00800000  // Interrupt 23 enable
+#define NVIC_EN0_INT24          0x01000000  // Interrupt 24 enable
+#define NVIC_EN0_INT25          0x02000000  // Interrupt 25 enable
+#define NVIC_EN0_INT26          0x04000000  // Interrupt 26 enable
+#define NVIC_EN0_INT27          0x08000000  // Interrupt 27 enable
+#define NVIC_EN0_INT28          0x10000000  // Interrupt 28 enable
+#define NVIC_EN0_INT29          0x20000000  // Interrupt 29 enable
+#define NVIC_EN0_INT30          0x40000000  // Interrupt 30 enable
+#define NVIC_EN0_INT31          0x80000000  // Interrupt 31 enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN1 register.
+//
+//*****************************************************************************
+#define NVIC_EN1_INT_M          0x007FFFFF  // Interrupt Enable
+#define NVIC_EN1_INT32          0x00000001  // Interrupt 32 enable
+#define NVIC_EN1_INT33          0x00000002  // Interrupt 33 enable
+#define NVIC_EN1_INT34          0x00000004  // Interrupt 34 enable
+#define NVIC_EN1_INT35          0x00000008  // Interrupt 35 enable
+#define NVIC_EN1_INT36          0x00000010  // Interrupt 36 enable
+#define NVIC_EN1_INT37          0x00000020  // Interrupt 37 enable
+#define NVIC_EN1_INT38          0x00000040  // Interrupt 38 enable
+#define NVIC_EN1_INT39          0x00000080  // Interrupt 39 enable
+#define NVIC_EN1_INT40          0x00000100  // Interrupt 40 enable
+#define NVIC_EN1_INT41          0x00000200  // Interrupt 41 enable
+#define NVIC_EN1_INT42          0x00000400  // Interrupt 42 enable
+#define NVIC_EN1_INT43          0x00000800  // Interrupt 43 enable
+#define NVIC_EN1_INT44          0x00001000  // Interrupt 44 enable
+#define NVIC_EN1_INT45          0x00002000  // Interrupt 45 enable
+#define NVIC_EN1_INT46          0x00004000  // Interrupt 46 enable
+#define NVIC_EN1_INT47          0x00008000  // Interrupt 47 enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS0 register.
+//
+//*****************************************************************************
+#define NVIC_DIS0_INT_M         0xFFFFFFFF  // Interrupt Disable
+#define NVIC_DIS0_INT0          0x00000001  // Interrupt 0 disable
+#define NVIC_DIS0_INT1          0x00000002  // Interrupt 1 disable
+#define NVIC_DIS0_INT2          0x00000004  // Interrupt 2 disable
+#define NVIC_DIS0_INT3          0x00000008  // Interrupt 3 disable
+#define NVIC_DIS0_INT4          0x00000010  // Interrupt 4 disable
+#define NVIC_DIS0_INT5          0x00000020  // Interrupt 5 disable
+#define NVIC_DIS0_INT6          0x00000040  // Interrupt 6 disable
+#define NVIC_DIS0_INT7          0x00000080  // Interrupt 7 disable
+#define NVIC_DIS0_INT8          0x00000100  // Interrupt 8 disable
+#define NVIC_DIS0_INT9          0x00000200  // Interrupt 9 disable
+#define NVIC_DIS0_INT10         0x00000400  // Interrupt 10 disable
+#define NVIC_DIS0_INT11         0x00000800  // Interrupt 11 disable
+#define NVIC_DIS0_INT12         0x00001000  // Interrupt 12 disable
+#define NVIC_DIS0_INT13         0x00002000  // Interrupt 13 disable
+#define NVIC_DIS0_INT14         0x00004000  // Interrupt 14 disable
+#define NVIC_DIS0_INT15         0x00008000  // Interrupt 15 disable
+#define NVIC_DIS0_INT16         0x00010000  // Interrupt 16 disable
+#define NVIC_DIS0_INT17         0x00020000  // Interrupt 17 disable
+#define NVIC_DIS0_INT18         0x00040000  // Interrupt 18 disable
+#define NVIC_DIS0_INT19         0x00080000  // Interrupt 19 disable
+#define NVIC_DIS0_INT20         0x00100000  // Interrupt 20 disable
+#define NVIC_DIS0_INT21         0x00200000  // Interrupt 21 disable
+#define NVIC_DIS0_INT22         0x00400000  // Interrupt 22 disable
+#define NVIC_DIS0_INT23         0x00800000  // Interrupt 23 disable
+#define NVIC_DIS0_INT24         0x01000000  // Interrupt 24 disable
+#define NVIC_DIS0_INT25         0x02000000  // Interrupt 25 disable
+#define NVIC_DIS0_INT26         0x04000000  // Interrupt 26 disable
+#define NVIC_DIS0_INT27         0x08000000  // Interrupt 27 disable
+#define NVIC_DIS0_INT28         0x10000000  // Interrupt 28 disable
+#define NVIC_DIS0_INT29         0x20000000  // Interrupt 29 disable
+#define NVIC_DIS0_INT30         0x40000000  // Interrupt 30 disable
+#define NVIC_DIS0_INT31         0x80000000  // Interrupt 31 disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS1 register.
+//
+//*****************************************************************************
+#define NVIC_DIS1_INT_M         0x007FFFFF  // Interrupt Disable
+#define NVIC_DIS1_INT32         0x00000001  // Interrupt 32 disable
+#define NVIC_DIS1_INT33         0x00000002  // Interrupt 33 disable
+#define NVIC_DIS1_INT34         0x00000004  // Interrupt 34 disable
+#define NVIC_DIS1_INT35         0x00000008  // Interrupt 35 disable
+#define NVIC_DIS1_INT36         0x00000010  // Interrupt 36 disable
+#define NVIC_DIS1_INT37         0x00000020  // Interrupt 37 disable
+#define NVIC_DIS1_INT38         0x00000040  // Interrupt 38 disable
+#define NVIC_DIS1_INT39         0x00000080  // Interrupt 39 disable
+#define NVIC_DIS1_INT40         0x00000100  // Interrupt 40 disable
+#define NVIC_DIS1_INT41         0x00000200  // Interrupt 41 disable
+#define NVIC_DIS1_INT42         0x00000400  // Interrupt 42 disable
+#define NVIC_DIS1_INT43         0x00000800  // Interrupt 43 disable
+#define NVIC_DIS1_INT44         0x00001000  // Interrupt 44 disable
+#define NVIC_DIS1_INT45         0x00002000  // Interrupt 45 disable
+#define NVIC_DIS1_INT46         0x00004000  // Interrupt 46 disable
+#define NVIC_DIS1_INT47         0x00008000  // Interrupt 47 disable
+#define NVIC_DIS1_INT48         0x00010000  // Interrupt 48 disable
+#define NVIC_DIS1_INT49         0x00020000  // Interrupt 49 disable
+#define NVIC_DIS1_INT50         0x00040000  // Interrupt 50 disable
+#define NVIC_DIS1_INT51         0x00080000  // Interrupt 51 disable
+#define NVIC_DIS1_INT52         0x00100000  // Interrupt 52 disable
+#define NVIC_DIS1_INT53         0x00200000  // Interrupt 53 disable
+#define NVIC_DIS1_INT54         0x00400000  // Interrupt 54 disable
+#define NVIC_DIS1_INT55         0x00800000  // Interrupt 55 disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND0 register.
+//
+//*****************************************************************************
+#define NVIC_PEND0_INT_M        0xFFFFFFFF  // Interrupt Set Pending
+#define NVIC_PEND0_INT0         0x00000001  // Interrupt 0 pend
+#define NVIC_PEND0_INT1         0x00000002  // Interrupt 1 pend
+#define NVIC_PEND0_INT2         0x00000004  // Interrupt 2 pend
+#define NVIC_PEND0_INT3         0x00000008  // Interrupt 3 pend
+#define NVIC_PEND0_INT4         0x00000010  // Interrupt 4 pend
+#define NVIC_PEND0_INT5         0x00000020  // Interrupt 5 pend
+#define NVIC_PEND0_INT6         0x00000040  // Interrupt 6 pend
+#define NVIC_PEND0_INT7         0x00000080  // Interrupt 7 pend
+#define NVIC_PEND0_INT8         0x00000100  // Interrupt 8 pend
+#define NVIC_PEND0_INT9         0x00000200  // Interrupt 9 pend
+#define NVIC_PEND0_INT10        0x00000400  // Interrupt 10 pend
+#define NVIC_PEND0_INT11        0x00000800  // Interrupt 11 pend
+#define NVIC_PEND0_INT12        0x00001000  // Interrupt 12 pend
+#define NVIC_PEND0_INT13        0x00002000  // Interrupt 13 pend
+#define NVIC_PEND0_INT14        0x00004000  // Interrupt 14 pend
+#define NVIC_PEND0_INT15        0x00008000  // Interrupt 15 pend
+#define NVIC_PEND0_INT16        0x00010000  // Interrupt 16 pend
+#define NVIC_PEND0_INT17        0x00020000  // Interrupt 17 pend
+#define NVIC_PEND0_INT18        0x00040000  // Interrupt 18 pend
+#define NVIC_PEND0_INT19        0x00080000  // Interrupt 19 pend
+#define NVIC_PEND0_INT20        0x00100000  // Interrupt 20 pend
+#define NVIC_PEND0_INT21        0x00200000  // Interrupt 21 pend
+#define NVIC_PEND0_INT22        0x00400000  // Interrupt 22 pend
+#define NVIC_PEND0_INT23        0x00800000  // Interrupt 23 pend
+#define NVIC_PEND0_INT24        0x01000000  // Interrupt 24 pend
+#define NVIC_PEND0_INT25        0x02000000  // Interrupt 25 pend
+#define NVIC_PEND0_INT26        0x04000000  // Interrupt 26 pend
+#define NVIC_PEND0_INT27        0x08000000  // Interrupt 27 pend
+#define NVIC_PEND0_INT28        0x10000000  // Interrupt 28 pend
+#define NVIC_PEND0_INT29        0x20000000  // Interrupt 29 pend
+#define NVIC_PEND0_INT30        0x40000000  // Interrupt 30 pend
+#define NVIC_PEND0_INT31        0x80000000  // Interrupt 31 pend
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND1 register.
+//
+//*****************************************************************************
+#define NVIC_PEND1_INT_M        0x007FFFFF  // Interrupt Set Pending
+#define NVIC_PEND1_INT32        0x00000001  // Interrupt 32 pend
+#define NVIC_PEND1_INT33        0x00000002  // Interrupt 33 pend
+#define NVIC_PEND1_INT34        0x00000004  // Interrupt 34 pend
+#define NVIC_PEND1_INT35        0x00000008  // Interrupt 35 pend
+#define NVIC_PEND1_INT36        0x00000010  // Interrupt 36 pend
+#define NVIC_PEND1_INT37        0x00000020  // Interrupt 37 pend
+#define NVIC_PEND1_INT38        0x00000040  // Interrupt 38 pend
+#define NVIC_PEND1_INT39        0x00000080  // Interrupt 39 pend
+#define NVIC_PEND1_INT40        0x00000100  // Interrupt 40 pend
+#define NVIC_PEND1_INT41        0x00000200  // Interrupt 41 pend
+#define NVIC_PEND1_INT42        0x00000400  // Interrupt 42 pend
+#define NVIC_PEND1_INT43        0x00000800  // Interrupt 43 pend
+#define NVIC_PEND1_INT44        0x00001000  // Interrupt 44 pend
+#define NVIC_PEND1_INT45        0x00002000  // Interrupt 45 pend
+#define NVIC_PEND1_INT46        0x00004000  // Interrupt 46 pend
+#define NVIC_PEND1_INT47        0x00008000  // Interrupt 47 pend
+#define NVIC_PEND1_INT48        0x00010000  // Interrupt 48 pend
+#define NVIC_PEND1_INT49        0x00020000  // Interrupt 49 pend
+#define NVIC_PEND1_INT50        0x00040000  // Interrupt 50 pend
+#define NVIC_PEND1_INT51        0x00080000  // Interrupt 51 pend
+#define NVIC_PEND1_INT52        0x00100000  // Interrupt 52 pend
+#define NVIC_PEND1_INT53        0x00200000  // Interrupt 53 pend
+#define NVIC_PEND1_INT54        0x00400000  // Interrupt 54 pend
+#define NVIC_PEND1_INT55        0x00800000  // Interrupt 55 pend
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND0 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND0_INT_M      0xFFFFFFFF  // Interrupt Clear Pending
+#define NVIC_UNPEND0_INT0       0x00000001  // Interrupt 0 unpend
+#define NVIC_UNPEND0_INT1       0x00000002  // Interrupt 1 unpend
+#define NVIC_UNPEND0_INT2       0x00000004  // Interrupt 2 unpend
+#define NVIC_UNPEND0_INT3       0x00000008  // Interrupt 3 unpend
+#define NVIC_UNPEND0_INT4       0x00000010  // Interrupt 4 unpend
+#define NVIC_UNPEND0_INT5       0x00000020  // Interrupt 5 unpend
+#define NVIC_UNPEND0_INT6       0x00000040  // Interrupt 6 unpend
+#define NVIC_UNPEND0_INT7       0x00000080  // Interrupt 7 unpend
+#define NVIC_UNPEND0_INT8       0x00000100  // Interrupt 8 unpend
+#define NVIC_UNPEND0_INT9       0x00000200  // Interrupt 9 unpend
+#define NVIC_UNPEND0_INT10      0x00000400  // Interrupt 10 unpend
+#define NVIC_UNPEND0_INT11      0x00000800  // Interrupt 11 unpend
+#define NVIC_UNPEND0_INT12      0x00001000  // Interrupt 12 unpend
+#define NVIC_UNPEND0_INT13      0x00002000  // Interrupt 13 unpend
+#define NVIC_UNPEND0_INT14      0x00004000  // Interrupt 14 unpend
+#define NVIC_UNPEND0_INT15      0x00008000  // Interrupt 15 unpend
+#define NVIC_UNPEND0_INT16      0x00010000  // Interrupt 16 unpend
+#define NVIC_UNPEND0_INT17      0x00020000  // Interrupt 17 unpend
+#define NVIC_UNPEND0_INT18      0x00040000  // Interrupt 18 unpend
+#define NVIC_UNPEND0_INT19      0x00080000  // Interrupt 19 unpend
+#define NVIC_UNPEND0_INT20      0x00100000  // Interrupt 20 unpend
+#define NVIC_UNPEND0_INT21      0x00200000  // Interrupt 21 unpend
+#define NVIC_UNPEND0_INT22      0x00400000  // Interrupt 22 unpend
+#define NVIC_UNPEND0_INT23      0x00800000  // Interrupt 23 unpend
+#define NVIC_UNPEND0_INT24      0x01000000  // Interrupt 24 unpend
+#define NVIC_UNPEND0_INT25      0x02000000  // Interrupt 25 unpend
+#define NVIC_UNPEND0_INT26      0x04000000  // Interrupt 26 unpend
+#define NVIC_UNPEND0_INT27      0x08000000  // Interrupt 27 unpend
+#define NVIC_UNPEND0_INT28      0x10000000  // Interrupt 28 unpend
+#define NVIC_UNPEND0_INT29      0x20000000  // Interrupt 29 unpend
+#define NVIC_UNPEND0_INT30      0x40000000  // Interrupt 30 unpend
+#define NVIC_UNPEND0_INT31      0x80000000  // Interrupt 31 unpend
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND1 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND1_INT_M      0x007FFFFF  // Interrupt Clear Pending
+#define NVIC_UNPEND1_INT32      0x00000001  // Interrupt 32 unpend
+#define NVIC_UNPEND1_INT33      0x00000002  // Interrupt 33 unpend
+#define NVIC_UNPEND1_INT34      0x00000004  // Interrupt 34 unpend
+#define NVIC_UNPEND1_INT35      0x00000008  // Interrupt 35 unpend
+#define NVIC_UNPEND1_INT36      0x00000010  // Interrupt 36 unpend
+#define NVIC_UNPEND1_INT37      0x00000020  // Interrupt 37 unpend
+#define NVIC_UNPEND1_INT38      0x00000040  // Interrupt 38 unpend
+#define NVIC_UNPEND1_INT39      0x00000080  // Interrupt 39 unpend
+#define NVIC_UNPEND1_INT40      0x00000100  // Interrupt 40 unpend
+#define NVIC_UNPEND1_INT41      0x00000200  // Interrupt 41 unpend
+#define NVIC_UNPEND1_INT42      0x00000400  // Interrupt 42 unpend
+#define NVIC_UNPEND1_INT43      0x00000800  // Interrupt 43 unpend
+#define NVIC_UNPEND1_INT44      0x00001000  // Interrupt 44 unpend
+#define NVIC_UNPEND1_INT45      0x00002000  // Interrupt 45 unpend
+#define NVIC_UNPEND1_INT46      0x00004000  // Interrupt 46 unpend
+#define NVIC_UNPEND1_INT47      0x00008000  // Interrupt 47 unpend
+#define NVIC_UNPEND1_INT48      0x00010000  // Interrupt 48 unpend
+#define NVIC_UNPEND1_INT49      0x00020000  // Interrupt 49 unpend
+#define NVIC_UNPEND1_INT50      0x00040000  // Interrupt 50 unpend
+#define NVIC_UNPEND1_INT51      0x00080000  // Interrupt 51 unpend
+#define NVIC_UNPEND1_INT52      0x00100000  // Interrupt 52 unpend
+#define NVIC_UNPEND1_INT53      0x00200000  // Interrupt 53 unpend
+#define NVIC_UNPEND1_INT54      0x00400000  // Interrupt 54 unpend
+#define NVIC_UNPEND1_INT55      0x00800000  // Interrupt 55 unpend
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE0 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE0_INT_M      0xFFFFFFFF  // Interrupt Active
+#define NVIC_ACTIVE0_INT0       0x00000001  // Interrupt 0 active
+#define NVIC_ACTIVE0_INT1       0x00000002  // Interrupt 1 active
+#define NVIC_ACTIVE0_INT2       0x00000004  // Interrupt 2 active
+#define NVIC_ACTIVE0_INT3       0x00000008  // Interrupt 3 active
+#define NVIC_ACTIVE0_INT4       0x00000010  // Interrupt 4 active
+#define NVIC_ACTIVE0_INT5       0x00000020  // Interrupt 5 active
+#define NVIC_ACTIVE0_INT6       0x00000040  // Interrupt 6 active
+#define NVIC_ACTIVE0_INT7       0x00000080  // Interrupt 7 active
+#define NVIC_ACTIVE0_INT8       0x00000100  // Interrupt 8 active
+#define NVIC_ACTIVE0_INT9       0x00000200  // Interrupt 9 active
+#define NVIC_ACTIVE0_INT10      0x00000400  // Interrupt 10 active
+#define NVIC_ACTIVE0_INT11      0x00000800  // Interrupt 11 active
+#define NVIC_ACTIVE0_INT12      0x00001000  // Interrupt 12 active
+#define NVIC_ACTIVE0_INT13      0x00002000  // Interrupt 13 active
+#define NVIC_ACTIVE0_INT14      0x00004000  // Interrupt 14 active
+#define NVIC_ACTIVE0_INT15      0x00008000  // Interrupt 15 active
+#define NVIC_ACTIVE0_INT16      0x00010000  // Interrupt 16 active
+#define NVIC_ACTIVE0_INT17      0x00020000  // Interrupt 17 active
+#define NVIC_ACTIVE0_INT18      0x00040000  // Interrupt 18 active
+#define NVIC_ACTIVE0_INT19      0x00080000  // Interrupt 19 active
+#define NVIC_ACTIVE0_INT20      0x00100000  // Interrupt 20 active
+#define NVIC_ACTIVE0_INT21      0x00200000  // Interrupt 21 active
+#define NVIC_ACTIVE0_INT22      0x00400000  // Interrupt 22 active
+#define NVIC_ACTIVE0_INT23      0x00800000  // Interrupt 23 active
+#define NVIC_ACTIVE0_INT24      0x01000000  // Interrupt 24 active
+#define NVIC_ACTIVE0_INT25      0x02000000  // Interrupt 25 active
+#define NVIC_ACTIVE0_INT26      0x04000000  // Interrupt 26 active
+#define NVIC_ACTIVE0_INT27      0x08000000  // Interrupt 27 active
+#define NVIC_ACTIVE0_INT28      0x10000000  // Interrupt 28 active
+#define NVIC_ACTIVE0_INT29      0x20000000  // Interrupt 29 active
+#define NVIC_ACTIVE0_INT30      0x40000000  // Interrupt 30 active
+#define NVIC_ACTIVE0_INT31      0x80000000  // Interrupt 31 active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE1 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE1_INT_M      0x007FFFFF  // Interrupt Active
+#define NVIC_ACTIVE1_INT32      0x00000001  // Interrupt 32 active
+#define NVIC_ACTIVE1_INT33      0x00000002  // Interrupt 33 active
+#define NVIC_ACTIVE1_INT34      0x00000004  // Interrupt 34 active
+#define NVIC_ACTIVE1_INT35      0x00000008  // Interrupt 35 active
+#define NVIC_ACTIVE1_INT36      0x00000010  // Interrupt 36 active
+#define NVIC_ACTIVE1_INT37      0x00000020  // Interrupt 37 active
+#define NVIC_ACTIVE1_INT38      0x00000040  // Interrupt 38 active
+#define NVIC_ACTIVE1_INT39      0x00000080  // Interrupt 39 active
+#define NVIC_ACTIVE1_INT40      0x00000100  // Interrupt 40 active
+#define NVIC_ACTIVE1_INT41      0x00000200  // Interrupt 41 active
+#define NVIC_ACTIVE1_INT42      0x00000400  // Interrupt 42 active
+#define NVIC_ACTIVE1_INT43      0x00000800  // Interrupt 43 active
+#define NVIC_ACTIVE1_INT44      0x00001000  // Interrupt 44 active
+#define NVIC_ACTIVE1_INT45      0x00002000  // Interrupt 45 active
+#define NVIC_ACTIVE1_INT46      0x00004000  // Interrupt 46 active
+#define NVIC_ACTIVE1_INT47      0x00008000  // Interrupt 47 active
+#define NVIC_ACTIVE1_INT48      0x00010000  // Interrupt 48 active
+#define NVIC_ACTIVE1_INT49      0x00020000  // Interrupt 49 active
+#define NVIC_ACTIVE1_INT50      0x00040000  // Interrupt 50 active
+#define NVIC_ACTIVE1_INT51      0x00080000  // Interrupt 51 active
+#define NVIC_ACTIVE1_INT52      0x00100000  // Interrupt 52 active
+#define NVIC_ACTIVE1_INT53      0x00200000  // Interrupt 53 active
+#define NVIC_ACTIVE1_INT54      0x00400000  // Interrupt 54 active
+#define NVIC_ACTIVE1_INT55      0x00800000  // Interrupt 55 active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI0 register.
+//
+//*****************************************************************************
+#define NVIC_PRI0_INT3_M        0xE0000000  // Interrupt 3 Priority Mask
+#define NVIC_PRI0_INT2_M        0x00E00000  // Interrupt 2 Priority Mask
+#define NVIC_PRI0_INT1_M        0x0000E000  // Interrupt 1 Priority Mask
+#define NVIC_PRI0_INT0_M        0x000000E0  // Interrupt 0 Priority Mask
+#define NVIC_PRI0_INT3_S        29
+#define NVIC_PRI0_INT2_S        21
+#define NVIC_PRI0_INT1_S        13
+#define NVIC_PRI0_INT0_S        5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI1 register.
+//
+//*****************************************************************************
+#define NVIC_PRI1_INT7_M        0xE0000000  // Interrupt 7 Priority Mask
+#define NVIC_PRI1_INT6_M        0x00E00000  // Interrupt 6 Priority Mask
+#define NVIC_PRI1_INT5_M        0x0000E000  // Interrupt 5 Priority Mask
+#define NVIC_PRI1_INT4_M        0x000000E0  // Interrupt 4 Priority Mask
+#define NVIC_PRI1_INT7_S        29
+#define NVIC_PRI1_INT6_S        21
+#define NVIC_PRI1_INT5_S        13
+#define NVIC_PRI1_INT4_S        5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI2 register.
+//
+//*****************************************************************************
+#define NVIC_PRI2_INT11_M       0xE0000000  // Interrupt 11 Priority Mask
+#define NVIC_PRI2_INT10_M       0x00E00000  // Interrupt 10 Priority Mask
+#define NVIC_PRI2_INT9_M        0x0000E000  // Interrupt 9 Priority Mask
+#define NVIC_PRI2_INT8_M        0x000000E0  // Interrupt 8 Priority Mask
+#define NVIC_PRI2_INT11_S       29
+#define NVIC_PRI2_INT10_S       21
+#define NVIC_PRI2_INT9_S        13
+#define NVIC_PRI2_INT8_S        5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI3 register.
+//
+//*****************************************************************************
+#define NVIC_PRI3_INT15_M       0xE0000000  // Interrupt 15 Priority Mask
+#define NVIC_PRI3_INT14_M       0x00E00000  // Interrupt 14 Priority Mask
+#define NVIC_PRI3_INT13_M       0x0000E000  // Interrupt 13 Priority Mask
+#define NVIC_PRI3_INT12_M       0x000000E0  // Interrupt 12 Priority Mask
+#define NVIC_PRI3_INT15_S       29
+#define NVIC_PRI3_INT14_S       21
+#define NVIC_PRI3_INT13_S       13
+#define NVIC_PRI3_INT12_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI4 register.
+//
+//*****************************************************************************
+#define NVIC_PRI4_INT19_M       0xE0000000  // Interrupt 19 Priority Mask
+#define NVIC_PRI4_INT18_M       0x00E00000  // Interrupt 18 Priority Mask
+#define NVIC_PRI4_INT17_M       0x0000E000  // Interrupt 17 Priority Mask
+#define NVIC_PRI4_INT16_M       0x000000E0  // Interrupt 16 Priority Mask
+#define NVIC_PRI4_INT19_S       29
+#define NVIC_PRI4_INT18_S       21
+#define NVIC_PRI4_INT17_S       13
+#define NVIC_PRI4_INT16_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI5 register.
+//
+//*****************************************************************************
+#define NVIC_PRI5_INT23_M       0xE0000000  // Interrupt 23 Priority Mask
+#define NVIC_PRI5_INT22_M       0x00E00000  // Interrupt 22 Priority Mask
+#define NVIC_PRI5_INT21_M       0x0000E000  // Interrupt 21 Priority Mask
+#define NVIC_PRI5_INT20_M       0x000000E0  // Interrupt 20 Priority Mask
+#define NVIC_PRI5_INT23_S       29
+#define NVIC_PRI5_INT22_S       21
+#define NVIC_PRI5_INT21_S       13
+#define NVIC_PRI5_INT20_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI6 register.
+//
+//*****************************************************************************
+#define NVIC_PRI6_INT27_M       0xE0000000  // Interrupt 27 Priority Mask
+#define NVIC_PRI6_INT26_M       0x00E00000  // Interrupt 26 Priority Mask
+#define NVIC_PRI6_INT25_M       0x0000E000  // Interrupt 25 Priority Mask
+#define NVIC_PRI6_INT24_M       0x000000E0  // Interrupt 24 Priority Mask
+#define NVIC_PRI6_INT27_S       29
+#define NVIC_PRI6_INT26_S       21
+#define NVIC_PRI6_INT25_S       13
+#define NVIC_PRI6_INT24_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI7 register.
+//
+//*****************************************************************************
+#define NVIC_PRI7_INT31_M       0xE0000000  // Interrupt 31 Priority Mask
+#define NVIC_PRI7_INT30_M       0x00E00000  // Interrupt 30 Priority Mask
+#define NVIC_PRI7_INT29_M       0x0000E000  // Interrupt 29 Priority Mask
+#define NVIC_PRI7_INT28_M       0x000000E0  // Interrupt 28 Priority Mask
+#define NVIC_PRI7_INT31_S       29
+#define NVIC_PRI7_INT30_S       21
+#define NVIC_PRI7_INT29_S       13
+#define NVIC_PRI7_INT28_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI8 register.
+//
+//*****************************************************************************
+#define NVIC_PRI8_INT35_M       0xE0000000  // Interrupt 35 Priority Mask
+#define NVIC_PRI8_INT34_M       0x00E00000  // Interrupt 34 Priority Mask
+#define NVIC_PRI8_INT33_M       0x0000E000  // Interrupt 33 Priority Mask
+#define NVIC_PRI8_INT32_M       0x000000E0  // Interrupt 32 Priority Mask
+#define NVIC_PRI8_INT35_S       29
+#define NVIC_PRI8_INT34_S       21
+#define NVIC_PRI8_INT33_S       13
+#define NVIC_PRI8_INT32_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI9 register.
+//
+//*****************************************************************************
+#define NVIC_PRI9_INT39_M       0xE0000000  // Interrupt 39 Priority Mask
+#define NVIC_PRI9_INT38_M       0x00E00000  // Interrupt 38 Priority Mask
+#define NVIC_PRI9_INT37_M       0x0000E000  // Interrupt 37 Priority Mask
+#define NVIC_PRI9_INT36_M       0x000000E0  // Interrupt 36 Priority Mask
+#define NVIC_PRI9_INT39_S       29
+#define NVIC_PRI9_INT38_S       21
+#define NVIC_PRI9_INT37_S       13
+#define NVIC_PRI9_INT36_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI10 register.
+//
+//*****************************************************************************
+#define NVIC_PRI10_INT43_M      0xE0000000  // Interrupt 43 Priority Mask
+#define NVIC_PRI10_INT42_M      0x00E00000  // Interrupt 42 Priority Mask
+#define NVIC_PRI10_INT41_M      0x0000E000  // Interrupt 41 Priority Mask
+#define NVIC_PRI10_INT40_M      0x000000E0  // Interrupt 40 Priority Mask
+#define NVIC_PRI10_INT43_S      29
+#define NVIC_PRI10_INT42_S      21
+#define NVIC_PRI10_INT41_S      13
+#define NVIC_PRI10_INT40_S      5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI11 register.
+//
+//*****************************************************************************
+#define NVIC_PRI11_INT47_M      0xE0000000  // Interrupt 47 Priority Mask
+#define NVIC_PRI11_INT46_M      0x00E00000  // Interrupt 46 Priority Mask
+#define NVIC_PRI11_INT45_M      0x0000E000  // Interrupt 45 Priority Mask
+#define NVIC_PRI11_INT44_M      0x000000E0  // Interrupt 44 Priority Mask
+#define NVIC_PRI11_INT47_S      29
+#define NVIC_PRI11_INT46_S      21
+#define NVIC_PRI11_INT45_S      13
+#define NVIC_PRI11_INT44_S      5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI12 register.
+//
+//*****************************************************************************
+#define NVIC_PRI12_INT51_M      0xE0000000  // Interrupt 51 Priority Mask
+#define NVIC_PRI12_INT50_M      0x00E00000  // Interrupt 50 Priority Mask
+#define NVIC_PRI12_INT49_M      0x0000E000  // Interrupt 49 Priority Mask
+#define NVIC_PRI12_INT48_M      0x000000E0  // Interrupt 48 Priority Mask
+#define NVIC_PRI12_INT51_S      29
+#define NVIC_PRI12_INT50_S      21
+#define NVIC_PRI12_INT49_S      13
+#define NVIC_PRI12_INT48_S      5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI13 register.
+//
+//*****************************************************************************
+#define NVIC_PRI13_INT55_M      0xE0000000  // Interrupt 55 Priority Mask
+#define NVIC_PRI13_INT54_M      0x00E00000  // Interrupt 54 Priority Mask
+#define NVIC_PRI13_INT53_M      0x0000E000  // Interrupt 53 Priority Mask
+#define NVIC_PRI13_INT52_M      0x000000E0  // Interrupt 52 Priority Mask
+#define NVIC_PRI13_INT55_S      29
+#define NVIC_PRI13_INT54_S      21
+#define NVIC_PRI13_INT53_S      13
+#define NVIC_PRI13_INT52_S      5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_CPUID register.
+//
+//*****************************************************************************
+#define NVIC_CPUID_IMP_M        0xFF000000  // Implementer Code
+#define NVIC_CPUID_IMP_ARM      0x41000000  // ARM
+#define NVIC_CPUID_VAR_M        0x00F00000  // Variant Number
+#define NVIC_CPUID_CON_M        0x000F0000  // Constant
+#define NVIC_CPUID_PARTNO_M     0x0000FFF0  // Part Number
+#define NVIC_CPUID_PARTNO_CM3   0x0000C230  // Cortex-M3 processor
+#define NVIC_CPUID_REV_M        0x0000000F  // Revision Number
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_INT_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_INT_CTRL_NMI_SET   0x80000000  // NMI Set Pending
+#define NVIC_INT_CTRL_PEND_SV   0x10000000  // PendSV Set Pending
+#define NVIC_INT_CTRL_UNPEND_SV 0x08000000  // PendSV Clear Pending
+#define NVIC_INT_CTRL_PENDSTSET 0x04000000  // SysTick Set Pending
+#define NVIC_INT_CTRL_PENDSTCLR 0x02000000  // SysTick Clear Pending
+#define NVIC_INT_CTRL_ISR_PRE   0x00800000  // Debug Interrupt Handling
+#define NVIC_INT_CTRL_ISR_PEND  0x00400000  // Interrupt Pending
+#define NVIC_INT_CTRL_VEC_PEN_M 0x0007F000  // Interrupt Pending Vector Number
+#define NVIC_INT_CTRL_VEC_PEN_NMI \
+                                0x00002000  // NMI
+#define NVIC_INT_CTRL_VEC_PEN_HARD \
+                                0x00003000  // Hard fault
+#define NVIC_INT_CTRL_VEC_PEN_MEM \
+                                0x00004000  // Memory management fault
+#define NVIC_INT_CTRL_VEC_PEN_BUS \
+                                0x00005000  // Bus fault
+#define NVIC_INT_CTRL_VEC_PEN_USG \
+                                0x00006000  // Usage fault
+#define NVIC_INT_CTRL_VEC_PEN_SVC \
+                                0x0000B000  // SVCall
+#define NVIC_INT_CTRL_VEC_PEN_PNDSV \
+                                0x0000E000  // PendSV
+#define NVIC_INT_CTRL_VEC_PEN_TICK \
+                                0x0000F000  // SysTick
+#define NVIC_INT_CTRL_RET_BASE  0x00000800  // Return to Base
+#define NVIC_INT_CTRL_VEC_ACT_M 0x0000007F  // Interrupt Pending Vector Number
+#define NVIC_INT_CTRL_VEC_ACT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_VTABLE register.
+//
+//*****************************************************************************
+#define NVIC_VTABLE_BASE        0x20000000  // Vector Table Base
+#define NVIC_VTABLE_OFFSET_M    0x1FFFFE00  // Vector Table Offset
+#define NVIC_VTABLE_OFFSET_S    9
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_APINT register.
+//
+//*****************************************************************************
+#define NVIC_APINT_VECTKEY_M    0xFFFF0000  // Register Key
+#define NVIC_APINT_VECTKEY      0x05FA0000  // Vector key
+#define NVIC_APINT_ENDIANESS    0x00008000  // Data Endianess
+#define NVIC_APINT_PRIGROUP_M   0x00000700  // Interrupt Priority Grouping
+#define NVIC_APINT_PRIGROUP_7_1 0x00000000  // Priority group 7.1 split
+#define NVIC_APINT_PRIGROUP_6_2 0x00000100  // Priority group 6.2 split
+#define NVIC_APINT_PRIGROUP_5_3 0x00000200  // Priority group 5.3 split
+#define NVIC_APINT_PRIGROUP_4_4 0x00000300  // Priority group 4.4 split
+#define NVIC_APINT_PRIGROUP_3_5 0x00000400  // Priority group 3.5 split
+#define NVIC_APINT_PRIGROUP_2_6 0x00000500  // Priority group 2.6 split
+#define NVIC_APINT_PRIGROUP_1_7 0x00000600  // Priority group 1.7 split
+#define NVIC_APINT_PRIGROUP_0_8 0x00000700  // Priority group 0.8 split
+#define NVIC_APINT_SYSRESETREQ  0x00000004  // System Reset Request
+#define NVIC_APINT_VECT_CLR_ACT 0x00000002  // Clear Active NMI / Fault
+#define NVIC_APINT_VECT_RESET   0x00000001  // System Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_SYS_CTRL_SEVONPEND 0x00000010  // Wake Up on Pending
+#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004  // Deep Sleep Enable
+#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002  // Sleep on ISR Exit
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_CFG_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_CFG_CTRL_STKALIGN  0x00000200  // Stack Alignment on Exception
+                                            // Entry
+#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100  // Ignore Bus Fault in NMI and
+                                            // Fault
+#define NVIC_CFG_CTRL_DIV0      0x00000010  // Trap on Divide by 0
+#define NVIC_CFG_CTRL_UNALIGNED 0x00000008  // Trap on Unaligned Access
+#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002  // Allow Main Interrupt Trigger
+#define NVIC_CFG_CTRL_BASE_THR  0x00000001  // Thread State Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_PRI1 register.
+//
+//*****************************************************************************
+#define NVIC_SYS_PRI1_USAGE_M   0x00E00000  // Usage Fault Priority
+#define NVIC_SYS_PRI1_BUS_M     0x0000E000  // Bus Fault Priority
+#define NVIC_SYS_PRI1_MEM_M     0x000000E0  // Memory Management Fault Priority
+#define NVIC_SYS_PRI1_USAGE_S   21
+#define NVIC_SYS_PRI1_BUS_S     13
+#define NVIC_SYS_PRI1_MEM_S     5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_PRI2 register.
+//
+//*****************************************************************************
+#define NVIC_SYS_PRI2_SVC_M     0xE0000000  // SVCall Priority
+#define NVIC_SYS_PRI2_SVC_S     29
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_PRI3 register.
+//
+//*****************************************************************************
+#define NVIC_SYS_PRI3_TICK_M    0xE0000000  // SysTick Exception Priority
+#define NVIC_SYS_PRI3_PENDSV_M  0x00E00000  // PendSV Priority
+#define NVIC_SYS_PRI3_DEBUG_M   0x000000E0  // Debug Priority
+#define NVIC_SYS_PRI3_TICK_S    29
+#define NVIC_SYS_PRI3_PENDSV_S  21
+#define NVIC_SYS_PRI3_DEBUG_S   5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_HND_CTRL
+// register.
+//
+//*****************************************************************************
+#define NVIC_SYS_HND_CTRL_USAGE 0x00040000  // Usage Fault Enable
+#define NVIC_SYS_HND_CTRL_BUS   0x00020000  // Bus Fault Enable
+#define NVIC_SYS_HND_CTRL_MEM   0x00010000  // Memory Management Fault Enable
+#define NVIC_SYS_HND_CTRL_SVC   0x00008000  // SVC Call Pending
+#define NVIC_SYS_HND_CTRL_BUSP  0x00004000  // Bus Fault Pending
+#define NVIC_SYS_HND_CTRL_MEMP  0x00002000  // Memory Management Fault Pending
+#define NVIC_SYS_HND_CTRL_USAGEP \
+                                0x00001000  // Usage Fault Pending
+#define NVIC_SYS_HND_CTRL_TICK  0x00000800  // SysTick Exception Active
+#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400  // PendSV Exception Active
+#define NVIC_SYS_HND_CTRL_MON   0x00000100  // Debug Monitor Active
+#define NVIC_SYS_HND_CTRL_SVCA  0x00000080  // SVC Call Active
+#define NVIC_SYS_HND_CTRL_USGA  0x00000008  // Usage Fault Active
+#define NVIC_SYS_HND_CTRL_BUSA  0x00000002  // Bus Fault Active
+#define NVIC_SYS_HND_CTRL_MEMA  0x00000001  // Memory Management Fault Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FAULT_STAT
+// register.
+//
+//*****************************************************************************
+#define NVIC_FAULT_STAT_DIV0    0x02000000  // Divide-by-Zero Usage Fault
+#define NVIC_FAULT_STAT_UNALIGN 0x01000000  // Unaligned Access Usage Fault
+#define NVIC_FAULT_STAT_NOCP    0x00080000  // No Coprocessor Usage Fault
+#define NVIC_FAULT_STAT_INVPC   0x00040000  // Invalid PC Load Usage Fault
+#define NVIC_FAULT_STAT_INVSTAT 0x00020000  // Invalid State Usage Fault
+#define NVIC_FAULT_STAT_UNDEF   0x00010000  // Undefined Instruction Usage
+                                            // Fault
+#define NVIC_FAULT_STAT_BFARV   0x00008000  // Bus Fault Address Register Valid
+#define NVIC_FAULT_STAT_BSTKE   0x00001000  // Stack Bus Fault
+#define NVIC_FAULT_STAT_BUSTKE  0x00000800  // Unstack Bus Fault
+#define NVIC_FAULT_STAT_IMPRE   0x00000400  // Imprecise Data Bus Error
+#define NVIC_FAULT_STAT_PRECISE 0x00000200  // Precise Data Bus Error
+#define NVIC_FAULT_STAT_IBUS    0x00000100  // Instruction Bus Error
+#define NVIC_FAULT_STAT_MMARV   0x00000080  // Memory Management Fault Address
+                                            // Register Valid
+#define NVIC_FAULT_STAT_MSTKE   0x00000010  // Stack Access Violation
+#define NVIC_FAULT_STAT_MUSTKE  0x00000008  // Unstack Access Violation
+#define NVIC_FAULT_STAT_DERR    0x00000002  // Data Access Violation
+#define NVIC_FAULT_STAT_IERR    0x00000001  // Instruction Access Violation
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_HFAULT_STAT
+// register.
+//
+//*****************************************************************************
+#define NVIC_HFAULT_STAT_DBG    0x80000000  // Debug Event
+#define NVIC_HFAULT_STAT_FORCED 0x40000000  // Forced Hard Fault
+#define NVIC_HFAULT_STAT_VECT   0x00000002  // Vector Table Read Fault
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DEBUG_STAT
+// register.
+//
+//*****************************************************************************
+#define NVIC_DEBUG_STAT_EXTRNL  0x00000010  // EDBGRQ asserted
+#define NVIC_DEBUG_STAT_VCATCH  0x00000008  // Vector catch
+#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004  // DWT match
+#define NVIC_DEBUG_STAT_BKPT    0x00000002  // Breakpoint instruction
+#define NVIC_DEBUG_STAT_HALTED  0x00000001  // Halt request
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MM_ADDR register.
+//
+//*****************************************************************************
+#define NVIC_MM_ADDR_M          0xFFFFFFFF  // Fault Address
+#define NVIC_MM_ADDR_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FAULT_ADDR
+// register.
+//
+//*****************************************************************************
+#define NVIC_FAULT_ADDR_M       0xFFFFFFFF  // Fault Address
+#define NVIC_FAULT_ADDR_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_TYPE register.
+//
+//*****************************************************************************
+#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000  // Number of I Regions
+#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00  // Number of D Regions
+#define NVIC_MPU_TYPE_SEPARATE  0x00000001  // Separate or Unified MPU
+#define NVIC_MPU_TYPE_IREGION_S 16
+#define NVIC_MPU_TYPE_DREGION_S 8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004  // MPU Default Region
+#define NVIC_MPU_CTRL_HFNMIENA  0x00000002  // MPU Enabled During Faults
+#define NVIC_MPU_CTRL_ENABLE    0x00000001  // MPU Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_NUMBER
+// register.
+//
+//*****************************************************************************
+#define NVIC_MPU_NUMBER_M       0x00000007  // MPU Region to Access
+#define NVIC_MPU_NUMBER_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE_ADDR_M    0xFFFFFFE0  // Base Address Mask
+#define NVIC_MPU_BASE_VALID     0x00000010  // Region Number Valid
+#define NVIC_MPU_BASE_REGION_M  0x00000007  // Region Number
+#define NVIC_MPU_BASE_ADDR_S    5
+#define NVIC_MPU_BASE_REGION_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR_M         0xFFFF0000  // Attributes
+#define NVIC_MPU_ATTR_XN        0x10000000  // Instruction Access Disable
+#define NVIC_MPU_ATTR_AP_M      0x07000000  // Access Privilege
+#define NVIC_MPU_ATTR_AP_NO_NO  0x00000000  // prv: no access, usr: no access
+#define NVIC_MPU_ATTR_AP_RW_NO  0x01000000  // prv: rw, usr: none
+#define NVIC_MPU_ATTR_AP_RW_RO  0x02000000  // prv: rw, usr: read-only
+#define NVIC_MPU_ATTR_AP_RW_RW  0x03000000  // prv: rw, usr: rw
+#define NVIC_MPU_ATTR_AP_RO_NO  0x05000000  // prv: ro, usr: none
+#define NVIC_MPU_ATTR_AP_RO_RO  0x06000000  // prv: ro, usr: ro
+#define NVIC_MPU_ATTR_TEX_M     0x00380000  // Type Extension Mask
+#define NVIC_MPU_ATTR_SHAREABLE 0x00040000  // Shareable
+#define NVIC_MPU_ATTR_CACHEABLE 0x00020000  // Cacheable
+#define NVIC_MPU_ATTR_BUFFRABLE 0x00010000  // Bufferable
+#define NVIC_MPU_ATTR_SRD_M     0x0000FF00  // Subregion Disable Bits
+#define NVIC_MPU_ATTR_SRD_0     0x00000100  // Sub-region 0 disable
+#define NVIC_MPU_ATTR_SRD_1     0x00000200  // Sub-region 1 disable
+#define NVIC_MPU_ATTR_SRD_2     0x00000400  // Sub-region 2 disable
+#define NVIC_MPU_ATTR_SRD_3     0x00000800  // Sub-region 3 disable
+#define NVIC_MPU_ATTR_SRD_4     0x00001000  // Sub-region 4 disable
+#define NVIC_MPU_ATTR_SRD_5     0x00002000  // Sub-region 5 disable
+#define NVIC_MPU_ATTR_SRD_6     0x00004000  // Sub-region 6 disable
+#define NVIC_MPU_ATTR_SRD_7     0x00008000  // Sub-region 7 disable
+#define NVIC_MPU_ATTR_SIZE_M    0x0000003E  // Region Size Mask
+#define NVIC_MPU_ATTR_SIZE_32B  0x00000008  // Region size 32 bytes
+#define NVIC_MPU_ATTR_SIZE_64B  0x0000000A  // Region size 64 bytes
+#define NVIC_MPU_ATTR_SIZE_128B 0x0000000C  // Region size 128 bytes
+#define NVIC_MPU_ATTR_SIZE_256B 0x0000000E  // Region size 256 bytes
+#define NVIC_MPU_ATTR_SIZE_512B 0x00000010  // Region size 512 bytes
+#define NVIC_MPU_ATTR_SIZE_1K   0x00000012  // Region size 1 Kbytes
+#define NVIC_MPU_ATTR_SIZE_2K   0x00000014  // Region size 2 Kbytes
+#define NVIC_MPU_ATTR_SIZE_4K   0x00000016  // Region size 4 Kbytes
+#define NVIC_MPU_ATTR_SIZE_8K   0x00000018  // Region size 8 Kbytes
+#define NVIC_MPU_ATTR_SIZE_16K  0x0000001A  // Region size 16 Kbytes
+#define NVIC_MPU_ATTR_SIZE_32K  0x0000001C  // Region size 32 Kbytes
+#define NVIC_MPU_ATTR_SIZE_64K  0x0000001E  // Region size 64 Kbytes
+#define NVIC_MPU_ATTR_SIZE_128K 0x00000020  // Region size 128 Kbytes
+#define NVIC_MPU_ATTR_SIZE_256K 0x00000022  // Region size 256 Kbytes
+#define NVIC_MPU_ATTR_SIZE_512K 0x00000024  // Region size 512 Kbytes
+#define NVIC_MPU_ATTR_SIZE_1M   0x00000026  // Region size 1 Mbytes
+#define NVIC_MPU_ATTR_SIZE_2M   0x00000028  // Region size 2 Mbytes
+#define NVIC_MPU_ATTR_SIZE_4M   0x0000002A  // Region size 4 Mbytes
+#define NVIC_MPU_ATTR_SIZE_8M   0x0000002C  // Region size 8 Mbytes
+#define NVIC_MPU_ATTR_SIZE_16M  0x0000002E  // Region size 16 Mbytes
+#define NVIC_MPU_ATTR_SIZE_32M  0x00000030  // Region size 32 Mbytes
+#define NVIC_MPU_ATTR_SIZE_64M  0x00000032  // Region size 64 Mbytes
+#define NVIC_MPU_ATTR_SIZE_128M 0x00000034  // Region size 128 Mbytes
+#define NVIC_MPU_ATTR_SIZE_256M 0x00000036  // Region size 256 Mbytes
+#define NVIC_MPU_ATTR_SIZE_512M 0x00000038  // Region size 512 Mbytes
+#define NVIC_MPU_ATTR_SIZE_1G   0x0000003A  // Region size 1 Gbytes
+#define NVIC_MPU_ATTR_SIZE_2G   0x0000003C  // Region size 2 Gbytes
+#define NVIC_MPU_ATTR_SIZE_4G   0x0000003E  // Region size 4 Gbytes
+#define NVIC_MPU_ATTR_ENABLE    0x00000001  // Region Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE1 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE1_ADDR_M   0xFFFFFFE0  // Base Address Mask
+#define NVIC_MPU_BASE1_VALID    0x00000010  // Region Number Valid
+#define NVIC_MPU_BASE1_REGION_M 0x00000007  // Region Number
+#define NVIC_MPU_BASE1_ADDR_S   5
+#define NVIC_MPU_BASE1_REGION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR1 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR1_XN       0x10000000  // Instruction Access Disable
+#define NVIC_MPU_ATTR1_AP_M     0x07000000  // Access Privilege
+#define NVIC_MPU_ATTR1_TEX_M    0x00380000  // Type Extension Mask
+#define NVIC_MPU_ATTR1_SHAREABLE \
+                                0x00040000  // Shareable
+#define NVIC_MPU_ATTR1_CACHEABLE \
+                                0x00020000  // Cacheable
+#define NVIC_MPU_ATTR1_BUFFRABLE \
+                                0x00010000  // Bufferable
+#define NVIC_MPU_ATTR1_SRD_M    0x0000FF00  // Subregion Disable Bits
+#define NVIC_MPU_ATTR1_SIZE_M   0x0000003E  // Region Size Mask
+#define NVIC_MPU_ATTR1_ENABLE   0x00000001  // Region Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE2 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE2_ADDR_M   0xFFFFFFE0  // Base Address Mask
+#define NVIC_MPU_BASE2_VALID    0x00000010  // Region Number Valid
+#define NVIC_MPU_BASE2_REGION_M 0x00000007  // Region Number
+#define NVIC_MPU_BASE2_ADDR_S   5
+#define NVIC_MPU_BASE2_REGION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR2 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR2_XN       0x10000000  // Instruction Access Disable
+#define NVIC_MPU_ATTR2_AP_M     0x07000000  // Access Privilege
+#define NVIC_MPU_ATTR2_TEX_M    0x00380000  // Type Extension Mask
+#define NVIC_MPU_ATTR2_SHAREABLE \
+                                0x00040000  // Shareable
+#define NVIC_MPU_ATTR2_CACHEABLE \
+                                0x00020000  // Cacheable
+#define NVIC_MPU_ATTR2_BUFFRABLE \
+                                0x00010000  // Bufferable
+#define NVIC_MPU_ATTR2_SRD_M    0x0000FF00  // Subregion Disable Bits
+#define NVIC_MPU_ATTR2_SIZE_M   0x0000003E  // Region Size Mask
+#define NVIC_MPU_ATTR2_ENABLE   0x00000001  // Region Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE3 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE3_ADDR_M   0xFFFFFFE0  // Base Address Mask
+#define NVIC_MPU_BASE3_VALID    0x00000010  // Region Number Valid
+#define NVIC_MPU_BASE3_REGION_M 0x00000007  // Region Number
+#define NVIC_MPU_BASE3_ADDR_S   5
+#define NVIC_MPU_BASE3_REGION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR3 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR3_XN       0x10000000  // Instruction Access Disable
+#define NVIC_MPU_ATTR3_AP_M     0x07000000  // Access Privilege
+#define NVIC_MPU_ATTR3_TEX_M    0x00380000  // Type Extension Mask
+#define NVIC_MPU_ATTR3_SHAREABLE \
+                                0x00040000  // Shareable
+#define NVIC_MPU_ATTR3_CACHEABLE \
+                                0x00020000  // Cacheable
+#define NVIC_MPU_ATTR3_BUFFRABLE \
+                                0x00010000  // Bufferable
+#define NVIC_MPU_ATTR3_SRD_M    0x0000FF00  // Subregion Disable Bits
+#define NVIC_MPU_ATTR3_SIZE_M   0x0000003E  // Region Size Mask
+#define NVIC_MPU_ATTR3_ENABLE   0x00000001  // Region Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_DBG_CTRL_DBGKEY_M  0xFFFF0000  // Debug key mask
+#define NVIC_DBG_CTRL_DBGKEY    0xA05F0000  // Debug key
+#define NVIC_DBG_CTRL_S_RESET_ST \
+                                0x02000000  // Core has reset since last read
+#define NVIC_DBG_CTRL_S_RETIRE_ST \
+                                0x01000000  // Core has executed insruction
+                                            // since last read
+#define NVIC_DBG_CTRL_S_LOCKUP  0x00080000  // Core is locked up
+#define NVIC_DBG_CTRL_S_SLEEP   0x00040000  // Core is sleeping
+#define NVIC_DBG_CTRL_S_HALT    0x00020000  // Core status on halt
+#define NVIC_DBG_CTRL_S_REGRDY  0x00010000  // Register read/write available
+#define NVIC_DBG_CTRL_C_SNAPSTALL \
+                                0x00000020  // Breaks a stalled load/store
+#define NVIC_DBG_CTRL_C_MASKINT 0x00000008  // Mask interrupts when stepping
+#define NVIC_DBG_CTRL_C_STEP    0x00000004  // Step the core
+#define NVIC_DBG_CTRL_C_HALT    0x00000002  // Halt the core
+#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001  // Enable debug
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_XFER register.
+//
+//*****************************************************************************
+#define NVIC_DBG_XFER_REG_WNR   0x00010000  // Write or not read
+#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F  // Register
+#define NVIC_DBG_XFER_REG_R0    0x00000000  // Register R0
+#define NVIC_DBG_XFER_REG_R1    0x00000001  // Register R1
+#define NVIC_DBG_XFER_REG_R2    0x00000002  // Register R2
+#define NVIC_DBG_XFER_REG_R3    0x00000003  // Register R3
+#define NVIC_DBG_XFER_REG_R4    0x00000004  // Register R4
+#define NVIC_DBG_XFER_REG_R5    0x00000005  // Register R5
+#define NVIC_DBG_XFER_REG_R6    0x00000006  // Register R6
+#define NVIC_DBG_XFER_REG_R7    0x00000007  // Register R7
+#define NVIC_DBG_XFER_REG_R8    0x00000008  // Register R8
+#define NVIC_DBG_XFER_REG_R9    0x00000009  // Register R9
+#define NVIC_DBG_XFER_REG_R10   0x0000000A  // Register R10
+#define NVIC_DBG_XFER_REG_R11   0x0000000B  // Register R11
+#define NVIC_DBG_XFER_REG_R12   0x0000000C  // Register R12
+#define NVIC_DBG_XFER_REG_R13   0x0000000D  // Register R13
+#define NVIC_DBG_XFER_REG_R14   0x0000000E  // Register R14
+#define NVIC_DBG_XFER_REG_R15   0x0000000F  // Register R15
+#define NVIC_DBG_XFER_REG_FLAGS 0x00000010  // xPSR/Flags register
+#define NVIC_DBG_XFER_REG_MSP   0x00000011  // Main SP
+#define NVIC_DBG_XFER_REG_PSP   0x00000012  // Process SP
+#define NVIC_DBG_XFER_REG_DSP   0x00000013  // Deep SP
+#define NVIC_DBG_XFER_REG_CFBP  0x00000014  // Control/Fault/BasePri/PriMask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_DATA register.
+//
+//*****************************************************************************
+#define NVIC_DBG_DATA_M         0xFFFFFFFF  // Data temporary cache
+#define NVIC_DBG_DATA_S         0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_INT register.
+//
+//*****************************************************************************
+#define NVIC_DBG_INT_HARDERR    0x00000400  // Debug trap on hard fault
+#define NVIC_DBG_INT_INTERR     0x00000200  // Debug trap on interrupt errors
+#define NVIC_DBG_INT_BUSERR     0x00000100  // Debug trap on bus error
+#define NVIC_DBG_INT_STATERR    0x00000080  // Debug trap on usage fault state
+#define NVIC_DBG_INT_CHKERR     0x00000040  // Debug trap on usage fault check
+#define NVIC_DBG_INT_NOCPERR    0x00000020  // Debug trap on coprocessor error
+#define NVIC_DBG_INT_MMERR      0x00000010  // Debug trap on mem manage fault
+#define NVIC_DBG_INT_RESET      0x00000008  // Core reset status
+#define NVIC_DBG_INT_RSTPENDCLR 0x00000004  // Clear pending core reset
+#define NVIC_DBG_INT_RSTPENDING 0x00000002  // Core reset is pending
+#define NVIC_DBG_INT_RSTVCATCH  0x00000001  // Reset vector catch
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SW_TRIG register.
+//
+//*****************************************************************************
+#define NVIC_SW_TRIG_INTID_M    0x0000003F  // Interrupt ID
+#define NVIC_SW_TRIG_INTID_S    0
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// Deprecated defines for the Micro Direct Memory Access register addresses.
+//
+//*****************************************************************************
+#define UDMA_CHALT              (*((volatile unsigned long *)0x400FF500))
+
+//*****************************************************************************
+//
+// Deprecated defines for the bit fields in the UDMA_CHALT register.
+//
+//*****************************************************************************
+#define UDMA_CHALT_M            0xFFFFFFFF  // Channel [n] Alternate Assignment
+                                            // Select
+
+#endif
+
+#endif // __LM3S9D92_H__
diff --git a/src/platform/lm3s/platform.c b/src/platform/lm3s/platform.c
index f21f29c1..6aeba0f0 100644
--- a/src/platform/lm3s/platform.c
+++ b/src/platform/lm3s/platform.c
@@ -23,49 +23,54 @@
 #include "elua_int.h" 
 
 // Platform specific includes
-#include "hw_ints.h"
-#include "hw_memmap.h"
-#include "hw_types.h"
-#include "hw_pwm.h"
-#include "hw_nvic.h"
-#include "hw_can.h"
-#include "hw_ethernet.h"
-#include "debug.h"
-#include "gpio.h"
-#include "can.h"
-#include "interrupt.h"
-#include "sysctl.h"
-#include "uart.h"
-#include "ssi.h"
-#include "timer.h"
-#include "pwm.h"
-#include "utils.h"
-#include "ethernet.h"
-#include "systick.h"
-#include "flash.h"
-#include "interrupt.h"
+
+#include "driverlib/debug.h"
+#include "driverlib/gpio.h"
+#include "driverlib/can.h"
+#include "driverlib/interrupt.h"
+#include "driverlib/sysctl.h"
+#include "driverlib/uart.h"
+#include "driverlib/ssi.h"
+#include "driverlib/timer.h"
+#include "driverlib/pwm.h"
+#include "driverlib/adc.h"
+#include "driverlib/ethernet.h"
+#include "driverlib/systick.h"
+#include "driverlib/flash.h"
+#include "driverlib/interrupt.h"
 #include "elua_net.h"
 #include "dhcpc.h"
 #include "buf.h"
 #include "rit128x96x4.h"
 #include "disp.h"
-#include "adc.h"
+#include "utils.h"
 
-
-#ifdef FORLM3S9B92
+#if defined( FORLM3S9B92 )
   #define TARGET_IS_TEMPEST_RB1
 
   #include "lm3s9b92.h"
-#elif FORLM3S8962
+#elif defined( FORLM3S9D92 )
+  #define TARGET_IS_FIRESTORM_RA2
+
+  #include "lm3s9d92.h"
+#elif defined( FORLM3S8962 )
   #include "lm3s8962.h"
-#elif FORLM3S6965
+#elif defined( FORLM3S6965 )
   #include "lm3s6965.h"
-#elif FORLM3S6918
+#elif defined( FORLM3S6918 )
   #include "lm3s6918.h"
 #endif
 
-#include "rom.h"
-#include "rom_map.h"
+#include "driverlib/rom.h"
+#include "driverlib/rom_map.h"
+
+// USB CDC Stuff
+#include "driverlib/usb.h"
+#include "usblib/usblib.h"
+#include "usblib/usbcdc.h"
+#include "usblib/device/usbdevice.h"
+#include "usblib/device/usbdcdc.h"
+#include "usb_serial_structs.h"
 
 // UIP sys tick data
 // NOTE: when using virtual timers, SYSTICKHZ and VTMR_FREQ_HZ should have the
@@ -85,11 +90,12 @@ static void pwms_init();
 static void eth_init();
 static void adcs_init();
 static void cans_init();
+static void usb_init();
 
 int platform_init()
 {
   // Set the clocking to run from PLL
-#ifdef FORLM3S9B92
+#if defined( FORLM3S9B92 ) || defined( FORLM3S9D92 )
   MAP_SysCtlClockSet(SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_16MHZ);
 #else
   MAP_SysCtlClockSet(SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_8MHZ);
@@ -120,6 +126,15 @@ int platform_init()
   cans_init();
 #endif
 
+#ifdef BUILD_USB_CDC
+  // Setup USB
+  usb_init();
+#endif
+
+  // Setup system timer
+  cmn_systimer_set_base_freq( MAP_SysCtlClockGet() );
+  cmn_systimer_set_interrupt_freq( SYSTICKHZ );
+
   // Setup ethernet (TCP/IP)
   eth_init();
 
@@ -144,7 +159,7 @@ int platform_init()
 // PIO
 // Same configuration on LM3S8962, LM3S6965, LM3S6918 (8 ports)
 // 9B92 has 9 ports (Port J in addition to A-H)
-#ifdef FORLM3S9B92
+#if defined( FORLM3S9B92 ) || defined( FORLM3S9D92 )
   static const u32 pio_base[] = { GPIO_PORTA_BASE, GPIO_PORTB_BASE, GPIO_PORTC_BASE, GPIO_PORTD_BASE,
                                   GPIO_PORTE_BASE, GPIO_PORTF_BASE, GPIO_PORTG_BASE, GPIO_PORTH_BASE, 
                                   GPIO_PORTJ_BASE };
@@ -226,6 +241,8 @@ pio_type platform_pio_op( unsigned port, pio_type pinmask, int op )
 // ****************************************************************************
 // CAN
 
+#if defined( BUILD_CAN )
+
 volatile u32 can_rx_flag = 0;
 volatile u32 can_tx_flag = 0;
 volatile u32 can_err_flag = 0;
@@ -268,10 +285,6 @@ void CANIntHandler(void)
 
 void cans_init( void )
 {
-  GPIOPinConfigure(GPIO_PD0_CAN0RX);
-  GPIOPinConfigure(GPIO_PD1_CAN0TX);
-  MAP_GPIOPinTypeCAN(GPIO_PORTD_BASE, GPIO_PIN_0 | GPIO_PIN_1);
-
   MAP_SysCtlPeripheralEnable( SYSCTL_PERIPH_CAN0 ); 
   MAP_CANInit( CAN0_BASE );
   CANBitRateSet(CAN0_BASE, LM3S_CAN_CLOCK, 500000);
@@ -290,6 +303,10 @@ void cans_init( void )
 
 u32 platform_can_setup( unsigned id, u32 clock )
 {  
+  GPIOPinConfigure(GPIO_PD0_CAN0RX);
+  GPIOPinConfigure(GPIO_PD1_CAN0TX);
+  MAP_GPIOPinTypeCAN(GPIO_PORTD_BASE, GPIO_PIN_0 | GPIO_PIN_1);
+
   MAP_CANDisable(CAN0_BASE);
   CANBitRateSet(CAN0_BASE, LM3S_CAN_CLOCK, clock );
   MAP_CANEnable(CAN0_BASE);
@@ -340,6 +357,8 @@ int platform_can_recv( unsigned id, u32 *canid, u8 *idtype, u8 *len, u8 *data )
     return PLATFORM_UNDERFLOW;
 }
 
+#endif
+
 // ****************************************************************************
 // SPI
 // Same configuration on LM3S8962, LM3S6965, LM3S6918 and LM3S9B92 (2 SPI ports)
@@ -349,18 +368,37 @@ int platform_can_recv( unsigned id, u32 *canid, u8 *idtype, u8 *len, u8 *data )
 //  PIN info extracted from LM3S6950 and 5769 datasheets
 static const u32 spi_base[] = { SSI0_BASE, SSI1_BASE };
 static const u32 spi_sysctl[] = { SYSCTL_PERIPH_SSI0, SYSCTL_PERIPH_SSI1 };
+
+#if defined( ELUA_BOARD_SOLDERCORE )
+static const u32 spi_gpio_base[] = { GPIO_PORTA_BASE, GPIO_PORTF_BASE };
+static const u8 spi_gpio_pins[] = {  GPIO_PIN_4 | GPIO_PIN_5,
+                                     GPIO_PIN_4 | GPIO_PIN_5 };
+//                                   SSIxRx       SSIxTx
+
+static const u32 spi_gpio_clk_base[] = { GPIO_PORTA_BASE, GPIO_PORTH_BASE };
+static const u8 spi_gpio_clk_pin[] = { GPIO_PIN_2, GPIO_PIN_4 };
+#else
 static const u32 spi_gpio_base[] = { GPIO_PORTA_BASE, GPIO_PORTE_BASE };
-static const u8 spi_gpio_pins[] = { GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5,
-                                    GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 };
+static const u8 spi_gpio_pins[] = { GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5,
+                                    GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 };
 //                                  SSIxClk      SSIxFss      SSIxRx       SSIxTx
+static const u32 spi_gpio_clk_base[] = { GPIO_PORTA_BASE, GPIO_PORTE_BASE };
 static const u8 spi_gpio_clk_pin[] = { GPIO_PIN_2, GPIO_PIN_0 };
+#endif
+
 
 static void spis_init()
 {
   unsigned i;
 
+#if defined( ELUA_BOARD_SOLDERCORE )
+  GPIOPinConfigure( GPIO_PH4_SSI1CLK );
+  GPIOPinConfigure( GPIO_PF4_SSI1RX );
+  GPIOPinConfigure( GPIO_PF5_SSI1TX );
+#endif
+
   for( i = 0; i < NUM_SPI; i ++ )
-    MAP_SysCtlPeripheralEnable(spi_sysctl[ i ]);
+    MAP_SysCtlPeripheralEnable( spi_sysctl[ i ] );
 }
 
 u32 platform_spi_setup( unsigned id, int mode, u32 clock, unsigned cpol, unsigned cpha, unsigned databits )
@@ -375,9 +413,11 @@ u32 platform_spi_setup( unsigned id, int mode, u32 clock, unsigned cpol, unsigne
   MAP_SSIDisable( spi_base[ id ] );
 
   MAP_GPIOPinTypeSSI( spi_gpio_base[ id ], spi_gpio_pins[ id ] );
+  MAP_GPIOPinTypeSSI( spi_gpio_clk_base[ id ], spi_gpio_clk_pin[ id ] );
 
   // FIXME: not sure this is always "right"
-  GPIOPadConfigSet(spi_gpio_base[ id ], spi_gpio_pins[ id ], GPIO_STRENGTH_4MA, GPIO_PIN_TYPE_STD_WPU);
+  GPIOPadConfigSet( spi_gpio_base[ id ], spi_gpio_pins[ id ], GPIO_STRENGTH_4MA, GPIO_PIN_TYPE_STD_WPU );
+  GPIOPadConfigSet( spi_gpio_clk_base[ id ], spi_gpio_clk_pin[ id ], GPIO_STRENGTH_4MA, GPIO_PIN_TYPE_STD_WPU );
 
   MAP_SSIConfigSetExpClk( spi_base[ id ], MAP_SysCtlClockGet(), protocol, mode, clock, databits );
   MAP_SSIEnable( spi_base[ id ] );
@@ -411,7 +451,6 @@ static const u8 uart_gpio_pins[] = { GPIO_PIN_0 | GPIO_PIN_1, GPIO_PIN_2 | GPIO_
 static void uarts_init()
 {
   unsigned i;
-
   for( i = 0; i < NUM_UART; i ++ )
     MAP_SysCtlPeripheralEnable(uart_sysctl[ i ]);
 }
@@ -420,33 +459,36 @@ u32 platform_uart_setup( unsigned id, u32 baud, int databits, int parity, int st
 {
   u32 config;
 
-  MAP_GPIOPinTypeUART(uart_gpio_base [ id ], uart_gpio_pins[ id ]);
-
-  switch( databits )
+  if( id < NUM_UART )
   {
-    case 5:
-      config = UART_CONFIG_WLEN_5;
-      break;
-    case 6:
-      config = UART_CONFIG_WLEN_6;
-      break;
-    case 7:
-      config = UART_CONFIG_WLEN_7;
-      break;
-    default:
-      config = UART_CONFIG_WLEN_8;
-      break;
-  }
-  config |= ( stopbits == PLATFORM_UART_STOPBITS_1 ) ? UART_CONFIG_STOP_ONE : UART_CONFIG_STOP_TWO;
-  if( parity == PLATFORM_UART_PARITY_EVEN )
-    config |= UART_CONFIG_PAR_EVEN;
-  else if( parity == PLATFORM_UART_PARITY_ODD )
-    config |= UART_CONFIG_PAR_ODD;
-  else
-    config |= UART_CONFIG_PAR_NONE;
+    MAP_GPIOPinTypeUART(uart_gpio_base [ id ], uart_gpio_pins[ id ]);
 
-  MAP_UARTConfigSetExpClk( uart_base[ id ], MAP_SysCtlClockGet(), baud, config );
-  MAP_UARTConfigGetExpClk( uart_base[ id ], MAP_SysCtlClockGet(), &baud, &config );
+    switch( databits )
+    {
+      case 5:
+        config = UART_CONFIG_WLEN_5;
+        break;
+      case 6:
+        config = UART_CONFIG_WLEN_6;
+        break;
+      case 7:
+        config = UART_CONFIG_WLEN_7;
+        break;
+      default:
+        config = UART_CONFIG_WLEN_8;
+        break;
+    }
+    config |= ( stopbits == PLATFORM_UART_STOPBITS_1 ) ? UART_CONFIG_STOP_ONE : UART_CONFIG_STOP_TWO;
+    if( parity == PLATFORM_UART_PARITY_EVEN )
+      config |= UART_CONFIG_PAR_EVEN;
+    else if( parity == PLATFORM_UART_PARITY_ODD )
+      config |= UART_CONFIG_PAR_ODD;
+    else
+      config |= UART_CONFIG_PAR_NONE;
+
+    MAP_UARTConfigSetExpClk( uart_base[ id ], MAP_SysCtlClockGet(), baud, config );
+    MAP_UARTConfigGetExpClk( uart_base[ id ], MAP_SysCtlClockGet(), &baud, &config );
+  }
   return baud;
 }
 
@@ -455,12 +497,13 @@ void platform_s_uart_send( unsigned id, u8 data )
   MAP_UARTCharPut( uart_base[ id ], data );
 }
 
-int platform_s_uart_recv( unsigned id, s32 timeout )
+int platform_s_uart_recv( unsigned id, timer_data_type timeout )
 {
   u32 base = uart_base[ id ];
 
   if( timeout == 0 )
     return MAP_UARTCharGetNonBlocking( base );
+
   return MAP_UARTCharGet( base );
 }
 
@@ -489,7 +532,7 @@ static void timers_init()
   }
 }
 
-void platform_s_timer_delay( unsigned id, u32 delay_us )
+void platform_s_timer_delay( unsigned id, timer_data_type delay_us )
 {
   timer_data_type final;
   u32 base = timer_base[ id ];
@@ -499,7 +542,7 @@ void platform_s_timer_delay( unsigned id, u32 delay_us )
   while( MAP_TimerValueGet( base, TIMER_A ) > final );
 }
 
-u32 platform_s_timer_op( unsigned id, int op, u32 data )
+timer_data_type platform_s_timer_op( unsigned id, int op,timer_data_type data )
 {
   u32 res = 0;
   u32 base = timer_base[ id ];
@@ -517,23 +560,39 @@ u32 platform_s_timer_op( unsigned id, int op, u32 data )
       res = MAP_TimerValueGet( base, TIMER_A );
       break;
 
-    case PLATFORM_TIMER_OP_GET_MAX_DELAY:
-      res = platform_timer_get_diff_us( id, 0, 0xFFFFFFFF );
-      break;
-
-    case PLATFORM_TIMER_OP_GET_MIN_DELAY:
-      res = platform_timer_get_diff_us( id, 0, 1 );
-      break;
-
     case PLATFORM_TIMER_OP_SET_CLOCK:
     case PLATFORM_TIMER_OP_GET_CLOCK:
       res = MAP_SysCtlClockGet();
       break;
 
+    case PLATFORM_TIMER_OP_GET_MAX_CNT:
+      res = 0xFFFFFFFF;
+      break;
+
   }
   return res;
 }
 
+u64 platform_timer_sys_raw_read()
+{
+  return MAP_SysTickPeriodGet() - 1 - MAP_SysTickValueGet();
+}
+
+void platform_timer_sys_disable_int()
+{
+  MAP_SysTickIntDisable();
+}
+
+void platform_timer_sys_enable_int()
+{
+  MAP_SysTickIntEnable();
+}
+
+timer_data_type platform_timer_read_sys()
+{
+  return cmn_systimer_get();
+}
+
 // ****************************************************************************
 // PWMs
 // Similar on LM3S8962 and LM3S6965
@@ -549,24 +608,32 @@ const static u8 pwm_div_data[] = { 1, 2, 4, 8, 16, 32, 64 };
 #elif defined(FORLM3S6965)
   const static u32 pwm_ports[] =  { GPIO_PORTF_BASE, GPIO_PORTD_BASE, GPIO_PORTB_BASE, GPIO_PORTB_BASE, GPIO_PORTE_BASE, GPIO_PORTE_BASE };
   const static u8 pwm_pins[] = { GPIO_PIN_0, GPIO_PIN_1, GPIO_PIN_0, GPIO_PIN_1, GPIO_PIN_0, GPIO_PIN_1 };
-#elif defined(FORLM3S9B92)
-  const static u32 pwm_ports[] =  { GPIO_PORTD_BASE, GPIO_PORTD_BASE, GPIO_PORTB_BASE, GPIO_PORTB_BASE, GPIO_PORTE_BASE, GPIO_PORTE_BASE };
-  const static u8 pwm_pins[] = { GPIO_PIN_0, GPIO_PIN_1, GPIO_PIN_0, GPIO_PIN_1, GPIO_PIN_0, GPIO_PIN_1 };
-  // GPIOPCTL probably needs modification to do PWM for 2&3, Digital Function 2
+#elif defined( ELUA_BOARD_SOLDERCORE ) && defined( FORLM3S9D92 )
+  const static u32 pwm_ports[] =  { GPIO_PORTG_BASE, GPIO_PORTD_BASE, GPIO_PORTD_BASE, GPIO_PORTD_BASE, GPIO_PORTE_BASE, GPIO_PORTE_BASE, GPIO_PORTC_BASE, GPIO_PORTC_BASE };
+  const static u8 pwm_pins[] = { GPIO_PIN_0, GPIO_PIN_1, GPIO_PIN_2, GPIO_PIN_3, GPIO_PIN_6, GPIO_PIN_7,  GPIO_PIN_4,  GPIO_PIN_6 };
+  const static u32 pwm_configs[] = { GPIO_PG0_PWM0, GPIO_PD1_PWM1, GPIO_PD2_PWM2, GPIO_PD3_PWM3, GPIO_PE6_PWM4, GPIO_PE7_PWM5, GPIO_PC4_PWM6, GPIO_PC6_PWM7 };
+#elif defined( FORLM3S9B92 ) || ( defined(FORLM3S9D92) && !defined( ELUA_BOARD_SOLDERCORE ) )
+  const static u32 pwm_ports[] =  { GPIO_PORTD_BASE, GPIO_PORTD_BASE, GPIO_PORTD_BASE, GPIO_PORTD_BASE, GPIO_PORTE_BASE, GPIO_PORTE_BASE, GPIO_PORTC_BASE, GPIO_PORTC_BASE };
+  const static u8 pwm_pins[] = { GPIO_PIN_0, GPIO_PIN_1, GPIO_PIN_2, GPIO_PIN_3, GPIO_PIN_6, GPIO_PIN_7,  GPIO_PIN_4,  GPIO_PIN_6 };
+  const static u32 pwm_configs[] = { GPIO_PD0_PWM0, GPIO_PD1_PWM1, GPIO_PD2_PWM2, GPIO_PD3_PWM3, GPIO_PE6_PWM4, GPIO_PE7_PWM5, GPIO_PC4_PWM6, GPIO_PC6_PWM7 };
 #else
   const static u32 pwm_ports[] =  { GPIO_PORTF_BASE, GPIO_PORTG_BASE, GPIO_PORTB_BASE, GPIO_PORTB_BASE, GPIO_PORTE_BASE, GPIO_PORTE_BASE };
   const static u8 pwm_pins[] = { GPIO_PIN_0, GPIO_PIN_1, GPIO_PIN_0, GPIO_PIN_1, GPIO_PIN_0, GPIO_PIN_1 };
 #endif
 
 // PWM generators
-#ifdef FORLM3S9B92
+#if defined( FORLM3S9B92 ) || defined(FORLM3S9D92)
   const static u16 pwm_gens[] = { PWM_GEN_0, PWM_GEN_1, PWM_GEN_2, PWM_GEN_3 };
 #else
   const static u16 pwm_gens[] = { PWM_GEN_0, PWM_GEN_1, PWM_GEN_2 };
 #endif
 
 // PWM outputs
+#if defined( FORLM3S9B92 ) || defined(FORLM3S9D92)
+const static u16 pwm_outs[] = { PWM_OUT_0, PWM_OUT_1, PWM_OUT_2, PWM_OUT_3, PWM_OUT_4, PWM_OUT_5, PWM_OUT_6, PWM_OUT_7};
+#else
 const static u16 pwm_outs[] = { PWM_OUT_0, PWM_OUT_1, PWM_OUT_2, PWM_OUT_3, PWM_OUT_4, PWM_OUT_5 };
+#endif
 
 static void pwms_init()
 {
@@ -574,8 +641,8 @@ static void pwms_init()
   MAP_SysCtlPWMClockSet( SYSCTL_PWMDIV_1 );
 }
 
-// Helper function: return the PWM clock
-static u32 platform_pwm_get_clock()
+// Return the PWM clock
+u32 platform_pwm_get_clock( unsigned id )
 {
   unsigned i;
   u32 clk;
@@ -587,8 +654,8 @@ static u32 platform_pwm_get_clock()
   return MAP_SysCtlClockGet() / pwm_div_data[ i ];
 }
 
-// Helper function: set the PWM clock
-static u32 platform_pwm_set_clock( u32 clock )
+// Set the PWM clock
+u32 platform_pwm_set_clock( unsigned id, u32 clock )
 {
   unsigned i, min_i;
   u32 sysclk;
@@ -603,9 +670,13 @@ static u32 platform_pwm_set_clock( u32 clock )
 
 u32 platform_pwm_setup( unsigned id, u32 frequency, unsigned duty )
 {
-  u32 pwmclk = platform_pwm_get_clock();
+  u32 pwmclk = platform_pwm_get_clock( id );
   u32 period;
 
+#if defined( FORLM3S9B92 ) || defined(FORLM3S9D92)
+  GPIOPinConfigure( pwm_configs[ id ] );
+#endif
+
   // Set pin as PWM
   MAP_GPIOPinTypePWM( pwm_ports[ id ], pwm_pins[ id ] );
   // Compute period
@@ -619,32 +690,16 @@ u32 platform_pwm_setup( unsigned id, u32 frequency, unsigned duty )
   return pwmclk / period;
 }
 
-u32 platform_pwm_op( unsigned id, int op, u32 data )
+void platform_pwm_start( unsigned id )
 {
-  u32 res = 0;
+  MAP_PWMOutputState( PWM_BASE, 1 << id, true );
+  MAP_PWMGenEnable( PWM_BASE, pwm_gens[ id >> 1 ] );
+}
 
-  switch( op )
-  {
-    case PLATFORM_PWM_OP_SET_CLOCK:
-      res = platform_pwm_set_clock( data );
-      break;
-
-    case PLATFORM_PWM_OP_GET_CLOCK:
-      res = platform_pwm_get_clock();
-      break;
-
-    case PLATFORM_PWM_OP_START:
-      MAP_PWMOutputState( PWM_BASE, 1 << id, true );
-      MAP_PWMGenEnable( PWM_BASE, pwm_gens[ id >> 1 ] );
-      break;
-
-    case PLATFORM_PWM_OP_STOP:
-      MAP_PWMOutputState( PWM_BASE, 1 << id, false );
-      MAP_PWMGenDisable( PWM_BASE, pwm_gens[ id >> 1 ] );
-      break;
-  }
-
-  return res;
+void platform_pwm_stop( unsigned id )
+{
+  MAP_PWMOutputState( PWM_BASE, 1 << id, false );
+  MAP_PWMGenDisable( PWM_BASE, pwm_gens[ id >> 1 ] );
 }
 
 // *****************************************************************************
@@ -653,7 +708,7 @@ u32 platform_pwm_op( unsigned id, int op, u32 data )
 #ifdef BUILD_ADC
 
 // Pin configuration if necessary
-#ifdef FORLM3S9B92
+#if defined( FORLM3S9B92 ) || defined(FORLM3S9D92)
   const static u32 adc_ports[] =  { GPIO_PORTE_BASE, GPIO_PORTE_BASE, GPIO_PORTE_BASE, GPIO_PORTE_BASE,
                                     GPIO_PORTD_BASE, GPIO_PORTD_BASE, GPIO_PORTD_BASE, GPIO_PORTD_BASE,
                                     GPIO_PORTE_BASE, GPIO_PORTE_BASE, GPIO_PORTB_BASE, GPIO_PORTB_BASE,
@@ -663,11 +718,17 @@ u32 platform_pwm_op( unsigned id, int op, u32 data )
                                     GPIO_PIN_7, GPIO_PIN_6, GPIO_PIN_5, GPIO_PIN_4,
                                     GPIO_PIN_3, GPIO_PIN_2, GPIO_PIN_4, GPIO_PIN_5,
                                     GPIO_PIN_3, GPIO_PIN_2, GPIO_PIN_1, GPIO_PIN_0 };
-                                    
+
+  const static u32 adc_ctls[] = { ADC_CTL_CH0, ADC_CTL_CH1, ADC_CTL_CH2, ADC_CTL_CH3,
+                                  ADC_CTL_CH4, ADC_CTL_CH5, ADC_CTL_CH6, ADC_CTL_CH7,
+                                  ADC_CTL_CH8, ADC_CTL_CH9, ADC_CTL_CH10, ADC_CTL_CH11,
+                                  ADC_CTL_CH12, ADC_CTL_CH13, ADC_CTL_CH14, ADC_CTL_CH15 };
+
   #define ADC_PIN_CONFIG
+#else
+const static u32 adc_ctls[] = { ADC_CTL_CH0, ADC_CTL_CH1, ADC_CTL_CH2, ADC_CTL_CH3 };
 #endif
 
-const static u32 adc_ctls[] = { ADC_CTL_CH0, ADC_CTL_CH1, ADC_CTL_CH2, ADC_CTL_CH3 };
 const static u32 adc_ints[] = { INT_ADC0, INT_ADC1, INT_ADC2, INT_ADC3 };
 
 int platform_adc_check_timer_id( unsigned id, unsigned timer_id )
@@ -748,22 +809,22 @@ static void adcs_init()
   unsigned id;
   elua_adc_dev_state *d = adc_get_dev_state( 0 );
   
-	MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC);
-	
-	// Try ramping up max sampling rate
+  MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC);
+
+  // Try ramping up max sampling rate
   MAP_SysCtlADCSpeedSet(SYSCTL_ADCSPEED_500KSPS);
   MAP_SysCtlADCSpeedSet(SYSCTL_ADCSPEED_1MSPS);
   
-	for( id = 0; id < NUM_ADC; id ++ )
+  for( id = 0; id < NUM_ADC; id ++ )
     adc_init_ch_state( id );
-	
+
   // Perform sequencer setup
-  platform_adc_setclock( 0, 0 );
-	MAP_ADCIntEnable( ADC_BASE, d->seq_id );
-  MAP_IntEnable( adc_ints[ d->seq_id ] );
+  platform_adc_set_clock( 0, 0 );
+  MAP_ADCIntEnable( ADC_BASE, d->seq_id );
+  MAP_IntEnable( adc_ints[ 0 ] ); // Enable sequencer 0 int
 }
 
-u32 platform_adc_setclock( unsigned id, u32 frequency )
+u32 platform_adc_set_clock( unsigned id, u32 frequency )
 {
   elua_adc_dev_state *d = adc_get_dev_state( 0 );
   
@@ -910,7 +971,7 @@ static void eth_init()
   MAP_SysCtlPeripheralEnable( SYSCTL_PERIPH_ETH );
   MAP_SysCtlPeripheralReset( SYSCTL_PERIPH_ETH );
 
-#ifdef FORLM3S9B92
+#if defined( FORLM3S9B92 ) || defined(FORLM3S9D92)
   GPIOPinConfigure(GPIO_PF2_LED1);
   GPIOPinConfigure(GPIO_PF3_LED0);
 #endif
@@ -957,7 +1018,15 @@ static void eth_init()
   // For the Ethernet Eval Kits, the MAC address will be stored in the
   // non-volatile USER0 and USER1 registers.  These registers can be read
   // using the FlashUserGet function, as illustrated below.
+
+
+#if defined( ELUA_BOARD_SOLDERCORE )
+  user0 = 0x00b61a00;
+  user1 = 0x006d0a00;
+#else
   MAP_FlashUserGet(&user0, &user1);
+#endif
+  
 
   // Convert the 24/24 split MAC address from NV ram into a 32/16 split MAC
   // address needed to program the hardware registers, then program the MAC
@@ -992,7 +1061,7 @@ u32 platform_eth_get_packet_nb( void* buf, u32 maxlen )
 
 void platform_eth_force_interrupt()
 {
-  HWREG( NVIC_SW_TRIG) |= INT_ETH - 16;
+  NVIC_SW_TRIG_R |= INT_ETH - 16;
 }
 
 u32 platform_eth_get_elapsed_time()
@@ -1011,16 +1080,15 @@ void SysTickIntHandler()
   // Handle virtual timers
   cmn_virtual_timer_cb();
 
-#ifdef BUILD_MMCFS
-  disk_timerproc();
-#endif
-
   // Indicate that a SysTick interrupt has occurred.
   eth_timer_fired = 1;
 
   // Generate a fake Ethernet interrupt.  This will perform the actual work
   // of incrementing the timers and taking the appropriate actions.
   platform_eth_force_interrupt();
+
+  // System timer handling
+  cmn_systimer_periodic();
 }
 
 void EthernetIntHandler()
@@ -1041,9 +1109,8 @@ void SysTickIntHandler()
 {
   cmn_virtual_timer_cb();
 
-#ifdef BUILD_MMCFS
-  disk_timerproc();
-#endif
+  // System timer handling
+  cmn_systimer_periodic();
 }
 
 void EthernetIntHandler()
@@ -1051,6 +1118,196 @@ void EthernetIntHandler()
 }
 #endif // #ifdef ELUA_UIP
 
+// ****************************************************************************
+// USB functions
+
+#if defined( BUILD_USB_CDC )
+
+static void usb_init()
+{
+  USBBufferInit( &g_sTxBuffer );
+  USBBufferInit( &g_sRxBuffer );
+
+  // Pass the device information to the USB library and place the device
+  // on the bus.
+  USBDCDCInit( 0, &g_sCDCDevice );
+}
+
+void platform_usb_cdc_send( u8 data )
+{
+  USBBufferWrite( &g_sTxBuffer, &data, 1 );
+}
+
+int platform_usb_cdc_recv( s32 timeout )
+{
+  unsigned char data;
+  unsigned long read;
+
+  // Try to read one byte from buffer, if none available return -1 or
+  // retry if timeout
+  // FIXME: Respect requested timeout
+  do {
+    read = USBBufferRead(&g_sRxBuffer, &data, 1);
+  } while( read == 0 && timeout != 0 );
+
+  if( read == 0 )
+    return -1;
+  else
+    return data;
+}
+
+unsigned long TxHandler(void *pvCBData, unsigned long ulEvent, unsigned long ulMsgValue, void *pvMsgData)
+{
+  // Which event was sent?
+  switch(ulEvent)
+  {
+    case USB_EVENT_TX_COMPLETE:
+    {
+        // Nothing to do, already handled by USBBuffer
+        break;
+    }
+      
+    default:
+        break;
+  }
+  
+  return(0);
+}
+
+unsigned long RxHandler(void *pvCBData, unsigned long ulEvent, unsigned long ulMsgValue, void *pvMsgData)
+{
+  unsigned long ulCount;
+  unsigned char ucChar;
+  unsigned long ulRead;
+
+
+  // Which event was sent?
+  switch(ulEvent)
+  {
+    // A new packet has been received.
+    case USB_EVENT_RX_AVAILABLE:
+    {
+      break;
+    }
+
+    //
+    // This is a request for how much unprocessed data is still waiting to
+    // be processed.  Return 0 if the UART is currently idle or 1 if it is
+    // in the process of transmitting something.  The actual number of
+    // bytes in the UART FIFO is not important here, merely whether or
+    // not everything previously sent to us has been transmitted.
+    //
+    case USB_EVENT_DATA_REMAINING:
+    {
+      //
+      // Get the number of bytes in the buffer and add 1 if some data
+      // still has to clear the transmitter.
+      //
+      return(0);
+    }
+
+    //
+    // This is a request for a buffer into which the next packet can be
+    // read.  This mode of receiving data is not supported so let the
+    // driver know by returning 0.  The CDC driver should not be sending
+    // this message but this is included just for illustration and
+    // completeness.
+    //
+    case USB_EVENT_REQUEST_BUFFER:
+    {
+      return(0);
+    }
+
+    // Other events can be safely ignored.
+    default:
+    {
+      break;
+    }
+  }
+
+  return(0);
+}
+
+unsigned long
+ControlHandler(void *pvCBData, unsigned long ulEvent, unsigned long ulMsgValue,
+               void *pvMsgData)
+{
+  switch(ulEvent) // Check event
+  {
+    // The host has connected.
+    case USB_EVENT_CONNECTED:
+    {
+      USBBufferFlush(&g_sTxBuffer);
+      USBBufferFlush(&g_sRxBuffer);
+      break;
+    }
+
+    
+    // The host has disconnected.
+    
+    case USB_EVENT_DISCONNECTED:
+    {
+      break;
+    }
+    
+    // Return the current serial communication parameters.
+    case USBD_CDC_EVENT_GET_LINE_CODING:
+    {
+      break;
+    }
+
+    // Set the current serial communication parameters.
+    case USBD_CDC_EVENT_SET_LINE_CODING:
+    {
+      break;
+    }
+
+    
+    // Set the current serial communication parameters.
+    case USBD_CDC_EVENT_SET_CONTROL_LINE_STATE:
+    {
+      break;
+    }
+
+    //
+    // Send a break condition on the serial line.
+    //
+    case USBD_CDC_EVENT_SEND_BREAK:
+    {
+      break;
+    }
+
+    //
+    // Clear the break condition on the serial line.
+    //
+    case USBD_CDC_EVENT_CLEAR_BREAK:
+    {
+      break;
+    }
+
+    //
+    // Ignore SUSPEND and RESUME for now.
+    //
+    case USB_EVENT_SUSPEND:
+    case USB_EVENT_RESUME:
+    {
+      break;
+    }
+
+    //
+    // Other events can be safely ignored.
+    //
+    default:
+    {
+      break;
+    }
+  }
+
+  return(0);
+}
+
+#endif // BUILD_USB_CDC
+
 // ****************************************************************************
 // Platform specific modules go here
 
diff --git a/src/platform/lm3s/platform_conf.h b/src/platform/lm3s/platform_conf.h
index 16f59882..79a2b7a9 100644
--- a/src/platform/lm3s/platform_conf.h
+++ b/src/platform/lm3s/platform_conf.h
@@ -4,37 +4,54 @@
 #define __PLATFORM_CONF_H__
 
 #include "auxmods.h"
-#include "hw_memmap.h"
-#include "hw_types.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_types.h"
 #include "stacks.h"
-#include "sysctl.h"
+#include "driverlib/sysctl.h"
 #include "elua_int.h"
 
 // *****************************************************************************
 // Define here what components you want for this platform
+//#if !defined( ELUA_BOARD_SOLDERCORE )
+  #define BUILD_XMODEM
+  #define BUILD_TERM
+//#endif
 
-#define BUILD_XMODEM
 #define BUILD_SHELL
 #define BUILD_ROMFS
 #define BUILD_MMCFS
-#define BUILD_TERM
+
+#if defined( ELUA_BOARD_SOLDERCORE )
+  #define BUILD_USB_CDC
+#endif
+
 #ifndef FORLM3S1968
   #define BUILD_UIP
-//#define BUILD_DHCPC
+  #define BUILD_DHCPC
   #define BUILD_DNS
 #endif  
-#define BUILD_CON_GENERIC
+
 #define BUILD_ADC
 #define BUILD_RPC
-//#define BUILD_CON_TCP
+//#if defined( ELUA_BOARD_SOLDERCORE )
+//  #define BUILD_CON_TCP
+//#else
+  #define BUILD_CON_GENERIC
+//#endif
 #define BUILD_C_INT_HANDLERS
 
+#define PLATFORM_HAS_SYSTIMER
+
 // *****************************************************************************
 // UART/Timer IDs configuration data (used in main.c)
 
+#if defined( ELUA_BOARD_SOLDERCORE )
+#define CON_UART_ID         CDC_UART_ID
+#else
 #define CON_UART_ID           0
+#endif
+
 #define CON_UART_SPEED        115200
-#define CON_TIMER_ID          0
 #define TERM_LINES            25
 #define TERM_COLS             80
 
@@ -47,7 +64,7 @@
 #define PS_LIB_TABLE_NAME   "lm3s"
 #endif
 
-#if defined( FORLM3S8962 ) || defined( FORLM3S9B92 )
+#if defined( FORLM3S8962 ) || defined( FORLM3S9B92 ) || defined( FORLM3S9D92 )
 #define CANLINE  _ROM( AUXLIB_CAN, luaopen_can, can_map )
 #define BUILD_CAN
 #else
@@ -72,6 +89,12 @@
 #define ADCLINE
 #endif
 
+#ifdef BUILD_TERM
+#define TERMLINE _ROM( AUXLIB_TERM, luaopen_term, term_map )
+#else
+#define TERMLINE
+#endif
+
 #if defined( ELUA_BOOT_RPC ) && !defined( BUILD_RPC )
 #define BUILD_RPC
 #endif
@@ -97,7 +120,7 @@
   _ROM( AUXLIB_PD, luaopen_pd, pd_map )\
   _ROM( AUXLIB_UART, luaopen_uart, uart_map )\
   PWMLINE\
-  _ROM( AUXLIB_TERM, luaopen_term, term_map )\
+  TERMLINE\
   _ROM( AUXLIB_PACK, luaopen_pack, pack_map )\
   _ROM( AUXLIB_BIT, luaopen_bit, bit_map )\
   _ROM( AUXLIB_BITARRAY, luaopen_bitarray, bitarray_map )\
@@ -144,31 +167,41 @@
 // Number of resources (0 if not available/not implemented)
 #if defined(FORLM3S1968)
   #define NUM_PIO             8
-#elif defined(FORLM3S9B92)
-  #define NUM_PIO             7
+#elif defined(FORLM3S9B92) || defined( FORLM3S9D92 )
+  #define NUM_PIO             9
 #else
   #define NUM_PIO             7
 #endif
-#define NUM_SPI               1
-#ifdef FORLM3S6965
+#if defined( FORLM3S9B92 ) || defined( FORLM3S9D92 )
+  #define NUM_SPI            2
+#else
+  #define NUM_SPI            1
+#endif
+#if defined( FORLM3S6965 )
   #define NUM_UART            3
-#elif FORLM3S9B92
+#elif defined( FORLM3S9B92 ) || defined( FORLM3S9D92 )
   #define NUM_UART            3
 #else
   #define NUM_UART            2
 #endif
 #define NUM_TIMER             4
-#ifndef FORLM3S6918
-  #define NUM_PWM             6
-#else
+#if defined( FORLM3S6918 )
   #define NUM_PWM             0
+#elif defined( FORLM3S9B92 ) || defined( FORLM3S9D92 )
+  #define NUM_PWM             8
+#else
+  #define NUM_PWM             6
 #endif  
+#if defined( FORLM3S9B92 ) || defined( FORLM3S9D92 )
+#define NUM_ADC               16
+#else
 #define NUM_ADC               4
+#endif
 #define NUM_CAN               1
 
 // Enable RX buffering on UART
-#define BUF_ENABLE_UART
-#define CON_BUF_SIZE          BUF_SIZE_128
+//#define BUF_ENABLE_UART
+//#define CON_BUF_SIZE          BUF_SIZE_128
 
 // ADC Configuration Params
 #define ADC_BIT_RESOLUTION    10
@@ -181,13 +214,8 @@
 
 // RPC boot options
 #define RPC_UART_ID           CON_UART_ID
-#define RPC_TIMER_ID          CON_TIMER_ID
 #define RPC_UART_SPEED        CON_UART_SPEED
 
-// SD/MMC Filesystem Setup
-#define MMCFS_TICK_HZ     4
-#define MMCFS_TICK_MS     ( 1000 / MMCFS_TICK_HZ )
-
 #if defined( ELUA_BOARD_EKLM3S6965 )
   // EK-LM3S6965
   #define MMCFS_CS_PORT                3
@@ -203,13 +231,18 @@
   #define MMCFS_CS_PORT                6
   #define MMCFS_CS_PIN                 1
   #define MMCFS_SPI_NUM                0
+#elif defined( ELUA_BOARD_SOLDERCORE )
+  // Soldercore
+  #define MMCFS_CS_PORT                6
+  #define MMCFS_CS_PIN                 7
+  #define MMCFS_SPI_NUM                1
 #elif defined( BUILD_MMCFS ) && !defined( MMCFS_SPI_NUM )
   #warning "MMCFS was enabled, but required SPI & CS data are undefined, disabling MMCFS"
   #undef BUILD_MMCFS
 #endif
 
 
-// CPU frequency (needed by the CPU module, 0 if not used)
+// CPU frequency (needed by the CPU module and MMCFS code, 0 if not used)
 #define CPU_FREQUENCY         SysCtlClockGet()
 
 // PIO prefix ('0' for P0, P1, ... or 'A' for PA, PB, ...)
@@ -220,14 +253,14 @@
 // Use #define PIO_PINS_PER_PORT 0 if this isn't needed
 #if defined(FORLM3S1968)
   #define PIO_PIN_ARRAY         { 8, 8, 8, 4, 4, 8, 8, 4}
-#elif defined(FORLM3S9B92)
+#elif defined(FORLM3S9B92) || defined( FORLM3S9D92 )
   #define PIO_PIN_ARRAY         { 8, 8, 8, 8, 8, 6, 8, 8, 8 }
 #else
   #define PIO_PIN_ARRAY         { 8, 8, 8, 8, 4, 4, 2 }
 #endif
 //                                A, B, C, D, E, F, G, H, J
 
-#ifdef FORLM3S9B92
+#if defined( FORLM3S9B92 ) || defined( FORLM3S9D92 )
   #define SRAM_SIZE ( 0x18000 )
 #else
   #define SRAM_SIZE ( 0x10000 )
diff --git a/src/platform/lm3s/platform_int.c b/src/platform/lm3s/platform_int.c
index f5cdef9d..3b324348 100644
--- a/src/platform/lm3s/platform_int.c
+++ b/src/platform/lm3s/platform_int.c
@@ -9,15 +9,19 @@
 #include "common.h"
 
 // Platform includes
-#ifdef FORLM3S9B92
+#if defined( FORLM3S9B92 )
   #define TARGET_IS_TEMPEST_RB1
 
   #include "lm3s9b92.h"
-#elif FORLM3S8962
+#elif defined( FORLM3S9D92 )
+  #define TARGET_IS_FIRESTORM_RA2
+
+  #include "lm3s9d92.h"
+#elif defined( FORLM3S8962 )
   #include "lm3s8962.h"
-#elif FORLM3S6965
+#elif defined( FORLM3S6965 )
   #include "lm3s6965.h"
-#elif FORLM3S6918
+#elif defined( FORLM3S6918 )
   #include "lm3s6918.h"
 #endif
 
diff --git a/src/platform/lm3s/rom.h b/src/platform/lm3s/rom.h
deleted file mode 100755
index d8c7240b..00000000
--- a/src/platform/lm3s/rom.h
+++ /dev/null
@@ -1,2252 +0,0 @@
-//*****************************************************************************
-//
-// rom.h - Macros to facilitate calling functions in the ROM.
-//
-// Copyright (c) 2007-2009 Luminary Micro, Inc.  All rights reserved.
-// Software License Agreement
-// 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
-// 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
-// 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4781 of the Stellaris Peripheral Driver Library.
-//
-//*****************************************************************************
-
-#ifndef __ROM_H__
-#define __ROM_H__
-
-//*****************************************************************************
-//
-// Pointers to the main API tables.
-//
-//*****************************************************************************
-#define ROM_APITABLE            ((unsigned long *)0x01000010)
-#define ROM_VERSION             (ROM_APITABLE[0])
-#define ROM_UARTTABLE           ((unsigned long *)(ROM_APITABLE[1]))
-#define ROM_SSITABLE            ((unsigned long *)(ROM_APITABLE[2]))
-#define ROM_I2CTABLE            ((unsigned long *)(ROM_APITABLE[3]))
-#define ROM_GPIOTABLE           ((unsigned long *)(ROM_APITABLE[4]))
-#define ROM_ADCTABLE            ((unsigned long *)(ROM_APITABLE[5]))
-#define ROM_COMPARATORTABLE     ((unsigned long *)(ROM_APITABLE[6]))
-#define ROM_FLASHTABLE          ((unsigned long *)(ROM_APITABLE[7]))
-#define ROM_PWMTABLE            ((unsigned long *)(ROM_APITABLE[8]))
-#define ROM_QEITABLE            ((unsigned long *)(ROM_APITABLE[9]))
-#define ROM_SYSTICKTABLE        ((unsigned long *)(ROM_APITABLE[10]))
-#define ROM_TIMERTABLE          ((unsigned long *)(ROM_APITABLE[11]))
-#define ROM_WATCHDOGTABLE       ((unsigned long *)(ROM_APITABLE[12]))
-#define ROM_SYSCTLTABLE         ((unsigned long *)(ROM_APITABLE[13]))
-#define ROM_INTERRUPTTABLE      ((unsigned long *)(ROM_APITABLE[14]))
-#define ROM_ETHERNETTABLE       ((unsigned long *)(ROM_APITABLE[15]))
-#define ROM_USBTABLE            ((unsigned long *)(ROM_APITABLE[16]))
-#define ROM_UDMATABLE           ((unsigned long *)(ROM_APITABLE[17]))
-#define ROM_CANTABLE            ((unsigned long *)(ROM_APITABLE[18]))
-#define ROM_HIBERNATETABLE      ((unsigned long *)(ROM_APITABLE[19]))
-#define ROM_MPUTABLE            ((unsigned long *)(ROM_APITABLE[20]))
-#define ROM_SOFTWARETABLE       ((unsigned long *)(ROM_APITABLE[21]))
-
-//*****************************************************************************
-//
-// Macros for calling ROM functions in the ADC API.
-//
-//*****************************************************************************
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_ADCSequenceDataGet                                                \
-        ((long (*)(unsigned long ulBase,                                      \
-                   unsigned long ulSequenceNum,                               \
-                   unsigned long *pulBuffer))ROM_ADCTABLE[0])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_ADCIntDisable                                                     \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulSequenceNum))ROM_ADCTABLE[1])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_ADCIntEnable                                                      \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulSequenceNum))ROM_ADCTABLE[2])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_ADCIntStatus                                                      \
-        ((unsigned long (*)(unsigned long ulBase,                             \
-                            unsigned long ulSequenceNum,                      \
-                            tBoolean bMasked))ROM_ADCTABLE[3])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_ADCIntClear                                                       \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulSequenceNum))ROM_ADCTABLE[4])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_ADCSequenceEnable                                                 \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulSequenceNum))ROM_ADCTABLE[5])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_ADCSequenceDisable                                                \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulSequenceNum))ROM_ADCTABLE[6])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_ADCSequenceConfigure                                              \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulSequenceNum,                               \
-                   unsigned long ulTrigger,                                   \
-                   unsigned long ulPriority))ROM_ADCTABLE[7])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_ADCSequenceStepConfigure                                          \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulSequenceNum,                               \
-                   unsigned long ulStep,                                      \
-                   unsigned long ulConfig))ROM_ADCTABLE[8])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_ADCSequenceOverflow                                               \
-        ((long (*)(unsigned long ulBase,                                      \
-                   unsigned long ulSequenceNum))ROM_ADCTABLE[9])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_ADCSequenceOverflowClear                                          \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulSequenceNum))ROM_ADCTABLE[10])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_ADCSequenceUnderflow                                              \
-        ((long (*)(unsigned long ulBase,                                      \
-                   unsigned long ulSequenceNum))ROM_ADCTABLE[11])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_ADCSequenceUnderflowClear                                         \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulSequenceNum))ROM_ADCTABLE[12])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_ADCProcessorTrigger                                               \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulSequenceNum))ROM_ADCTABLE[13])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_ADCHardwareOversampleConfigure                                    \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulFactor))ROM_ADCTABLE[14])
-#endif
-
-//*****************************************************************************
-//
-// Macros for calling ROM functions in the CAN API.
-//
-//*****************************************************************************
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_CANIntClear                                                       \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulIntClr))ROM_CANTABLE[0])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_CANInit                                                           \
-        ((void (*)(unsigned long ulBase))ROM_CANTABLE[1])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_CANEnable                                                         \
-        ((void (*)(unsigned long ulBase))ROM_CANTABLE[2])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_CANDisable                                                        \
-        ((void (*)(unsigned long ulBase))ROM_CANTABLE[3])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_CANBitTimingSet                                                   \
-        ((void (*)(unsigned long ulBase,                                      \
-                   tCANBitClkParms *pClkParms))ROM_CANTABLE[4])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_CANBitTimingGet                                                   \
-        ((void (*)(unsigned long ulBase,                                      \
-                   tCANBitClkParms *pClkParms))ROM_CANTABLE[5])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_CANMessageSet                                                     \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulObjID,                                     \
-                   tCANMsgObject *pMsgObject,                                 \
-                   tMsgObjType eMsgType))ROM_CANTABLE[6])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_CANMessageGet                                                     \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulObjID,                                     \
-                   tCANMsgObject *pMsgObject,                                 \
-                   tBoolean bClrPendingInt))ROM_CANTABLE[7])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_CANStatusGet                                                      \
-        ((unsigned long (*)(unsigned long ulBase,                             \
-                            tCANStsReg eStatusReg))ROM_CANTABLE[8])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_CANMessageClear                                                   \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulObjID))ROM_CANTABLE[9])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_CANIntEnable                                                      \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulIntFlags))ROM_CANTABLE[10])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_CANIntDisable                                                     \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulIntFlags))ROM_CANTABLE[11])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_CANIntStatus                                                      \
-        ((unsigned long (*)(unsigned long ulBase,                             \
-                            tCANIntStsReg eIntStsReg))ROM_CANTABLE[12])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_CANRetryGet                                                       \
-        ((tBoolean (*)(unsigned long ulBase))ROM_CANTABLE[13])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_CANRetrySet                                                       \
-        ((void (*)(unsigned long ulBase,                                      \
-                   tBoolean bAutoRetry))ROM_CANTABLE[14])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_CANErrCntrGet                                                     \
-        ((tBoolean (*)(unsigned long ulBase,                                  \
-                       unsigned long *pulRxCount,                             \
-                       unsigned long *pulTxCount))ROM_CANTABLE[15])
-#endif
-
-//*****************************************************************************
-//
-// Macros for calling ROM functions in the Comparator API.
-//
-//*****************************************************************************
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_ComparatorIntClear                                                \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulComp))ROM_COMPARATORTABLE[0])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_ComparatorConfigure                                               \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulComp,                                      \
-                   unsigned long ulConfig))ROM_COMPARATORTABLE[1])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_ComparatorRefSet                                                  \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulRef))ROM_COMPARATORTABLE[2])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_ComparatorValueGet                                                \
-        ((tBoolean (*)(unsigned long ulBase,                                  \
-                       unsigned long ulComp))ROM_COMPARATORTABLE[3])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_ComparatorIntEnable                                               \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulComp))ROM_COMPARATORTABLE[4])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_ComparatorIntDisable                                              \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulComp))ROM_COMPARATORTABLE[5])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_ComparatorIntStatus                                               \
-        ((tBoolean (*)(unsigned long ulBase,                                  \
-                       unsigned long ulComp,                                  \
-                       tBoolean bMasked))ROM_COMPARATORTABLE[6])
-#endif
-
-//*****************************************************************************
-//
-// Macros for calling ROM functions in the Ethernet API.
-//
-//*****************************************************************************
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_EthernetIntClear                                                  \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulIntFlags))ROM_ETHERNETTABLE[0])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_EthernetInitExpClk                                                \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulEthClk))ROM_ETHERNETTABLE[1])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_EthernetConfigSet                                                 \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulConfig))ROM_ETHERNETTABLE[2])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_EthernetConfigGet                                                 \
-        ((unsigned long (*)(unsigned long ulBase))ROM_ETHERNETTABLE[3])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_EthernetMACAddrSet                                                \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned char *pucMACAddr))ROM_ETHERNETTABLE[4])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_EthernetMACAddrGet                                                \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned char *pucMACAddr))ROM_ETHERNETTABLE[5])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_EthernetEnable                                                    \
-        ((void (*)(unsigned long ulBase))ROM_ETHERNETTABLE[6])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_EthernetDisable                                                   \
-        ((void (*)(unsigned long ulBase))ROM_ETHERNETTABLE[7])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_EthernetPacketAvail                                               \
-        ((tBoolean (*)(unsigned long ulBase))ROM_ETHERNETTABLE[8])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_EthernetSpaceAvail                                                \
-        ((tBoolean (*)(unsigned long ulBase))ROM_ETHERNETTABLE[9])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_EthernetPacketGetNonBlocking                                      \
-        ((long (*)(unsigned long ulBase,                                      \
-                   unsigned char *pucBuf,                                     \
-                   long lBufLen))ROM_ETHERNETTABLE[10])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_EthernetPacketGet                                                 \
-        ((long (*)(unsigned long ulBase,                                      \
-                   unsigned char *pucBuf,                                     \
-                   long lBufLen))ROM_ETHERNETTABLE[11])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_EthernetPacketPutNonBlocking                                      \
-        ((long (*)(unsigned long ulBase,                                      \
-                   unsigned char *pucBuf,                                     \
-                   long lBufLen))ROM_ETHERNETTABLE[12])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_EthernetPacketPut                                                 \
-        ((long (*)(unsigned long ulBase,                                      \
-                   unsigned char *pucBuf,                                     \
-                   long lBufLen))ROM_ETHERNETTABLE[13])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_EthernetIntEnable                                                 \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulIntFlags))ROM_ETHERNETTABLE[14])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_EthernetIntDisable                                                \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulIntFlags))ROM_ETHERNETTABLE[15])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_EthernetIntStatus                                                 \
-        ((unsigned long (*)(unsigned long ulBase,                             \
-                            tBoolean bMasked))ROM_ETHERNETTABLE[16])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_EthernetPHYWrite                                                  \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned char ucRegAddr,                                   \
-                   unsigned long ulData))ROM_ETHERNETTABLE[17])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_EthernetPHYRead                                                   \
-        ((unsigned long (*)(unsigned long ulBase,                             \
-                            unsigned char ucRegAddr))ROM_ETHERNETTABLE[18])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_UpdateEthernet                                                    \
-        ((void (*)(unsigned long ulClock))ROM_ETHERNETTABLE[19])
-#endif
-
-//*****************************************************************************
-//
-// Macros for calling ROM functions in the Flash API.
-//
-//*****************************************************************************
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_FlashProgram                                                      \
-        ((long (*)(unsigned long *pulData,                                    \
-                   unsigned long ulAddress,                                   \
-                   unsigned long ulCount))ROM_FLASHTABLE[0])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_FlashUsecGet                                                      \
-        ((unsigned long (*)(void))ROM_FLASHTABLE[1])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_FlashUsecSet                                                      \
-        ((void (*)(unsigned long ulClocks))ROM_FLASHTABLE[2])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_FlashErase                                                        \
-        ((long (*)(unsigned long ulAddress))ROM_FLASHTABLE[3])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_FlashProtectGet                                                   \
-        ((tFlashProtection (*)(unsigned long ulAddress))ROM_FLASHTABLE[4])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_FlashProtectSet                                                   \
-        ((long (*)(unsigned long ulAddress,                                   \
-                   tFlashProtection eProtect))ROM_FLASHTABLE[5])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_FlashProtectSave                                                  \
-        ((long (*)(void))ROM_FLASHTABLE[6])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_FlashUserGet                                                      \
-        ((long (*)(unsigned long *pulUser0,                                   \
-                   unsigned long *pulUser1))ROM_FLASHTABLE[7])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_FlashUserSet                                                      \
-        ((long (*)(unsigned long ulUser0,                                     \
-                   unsigned long ulUser1))ROM_FLASHTABLE[8])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_FlashUserSave                                                     \
-        ((long (*)(void))ROM_FLASHTABLE[9])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_FlashIntEnable                                                    \
-        ((void (*)(unsigned long ulIntFlags))ROM_FLASHTABLE[10])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_FlashIntDisable                                                   \
-        ((void (*)(unsigned long ulIntFlags))ROM_FLASHTABLE[11])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_FlashIntGetStatus                                                 \
-        ((unsigned long (*)(tBoolean bMasked))ROM_FLASHTABLE[12])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_FlashIntClear                                                     \
-        ((void (*)(unsigned long ulIntFlags))ROM_FLASHTABLE[13])
-#endif
-
-//*****************************************************************************
-//
-// Macros for calling ROM functions in the GPIO API.
-//
-//*****************************************************************************
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_GPIOPinWrite                                                      \
-        ((void (*)(unsigned long ulPort,                                      \
-                   unsigned char ucPins,                                      \
-                   unsigned char ucVal))ROM_GPIOTABLE[0])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_GPIODirModeSet                                                    \
-        ((void (*)(unsigned long ulPort,                                      \
-                   unsigned char ucPins,                                      \
-                   unsigned long ulPinIO))ROM_GPIOTABLE[1])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_GPIODirModeGet                                                    \
-        ((unsigned long (*)(unsigned long ulPort,                             \
-                            unsigned char ucPin))ROM_GPIOTABLE[2])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_GPIOIntTypeSet                                                    \
-        ((void (*)(unsigned long ulPort,                                      \
-                   unsigned char ucPins,                                      \
-                   unsigned long ulIntType))ROM_GPIOTABLE[3])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_GPIOIntTypeGet                                                    \
-        ((unsigned long (*)(unsigned long ulPort,                             \
-                            unsigned char ucPin))ROM_GPIOTABLE[4])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_GPIOPadConfigSet                                                  \
-        ((void (*)(unsigned long ulPort,                                      \
-                   unsigned char ucPins,                                      \
-                   unsigned long ulStrength,                                  \
-                   unsigned long ulPadType))ROM_GPIOTABLE[5])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_GPIOPadConfigGet                                                  \
-        ((void (*)(unsigned long ulPort,                                      \
-                   unsigned char ucPin,                                       \
-                   unsigned long *pulStrength,                                \
-                   unsigned long *pulPadType))ROM_GPIOTABLE[6])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_GPIOPinIntEnable                                                  \
-        ((void (*)(unsigned long ulPort,                                      \
-                   unsigned char ucPins))ROM_GPIOTABLE[7])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_GPIOPinIntDisable                                                 \
-        ((void (*)(unsigned long ulPort,                                      \
-                   unsigned char ucPins))ROM_GPIOTABLE[8])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_GPIOPinIntStatus                                                  \
-        ((long (*)(unsigned long ulPort,                                      \
-                   tBoolean bMasked))ROM_GPIOTABLE[9])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_GPIOPinIntClear                                                   \
-        ((void (*)(unsigned long ulPort,                                      \
-                   unsigned char ucPins))ROM_GPIOTABLE[10])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_GPIOPinRead                                                       \
-        ((long (*)(unsigned long ulPort,                                      \
-                   unsigned char ucPins))ROM_GPIOTABLE[11])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_GPIOPinTypeCAN                                                    \
-        ((void (*)(unsigned long ulPort,                                      \
-                   unsigned char ucPins))ROM_GPIOTABLE[12])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_GPIOPinTypeComparator                                             \
-        ((void (*)(unsigned long ulPort,                                      \
-                   unsigned char ucPins))ROM_GPIOTABLE[13])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_GPIOPinTypeGPIOInput                                              \
-        ((void (*)(unsigned long ulPort,                                      \
-                   unsigned char ucPins))ROM_GPIOTABLE[14])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_GPIOPinTypeGPIOOutput                                             \
-        ((void (*)(unsigned long ulPort,                                      \
-                   unsigned char ucPins))ROM_GPIOTABLE[15])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_GPIOPinTypeI2C                                                    \
-        ((void (*)(unsigned long ulPort,                                      \
-                   unsigned char ucPins))ROM_GPIOTABLE[16])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_GPIOPinTypePWM                                                    \
-        ((void (*)(unsigned long ulPort,                                      \
-                   unsigned char ucPins))ROM_GPIOTABLE[17])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_GPIOPinTypeQEI                                                    \
-        ((void (*)(unsigned long ulPort,                                      \
-                   unsigned char ucPins))ROM_GPIOTABLE[18])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_GPIOPinTypeSSI                                                    \
-        ((void (*)(unsigned long ulPort,                                      \
-                   unsigned char ucPins))ROM_GPIOTABLE[19])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_GPIOPinTypeTimer                                                  \
-        ((void (*)(unsigned long ulPort,                                      \
-                   unsigned char ucPins))ROM_GPIOTABLE[20])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_GPIOPinTypeUART                                                   \
-        ((void (*)(unsigned long ulPort,                                      \
-                   unsigned char ucPins))ROM_GPIOTABLE[21])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_GPIOPinTypeGPIOOutputOD                                           \
-        ((void (*)(unsigned long ulPort,                                      \
-                   unsigned char ucPins))ROM_GPIOTABLE[22])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_GPIOPinTypeADC                                                    \
-        ((void (*)(unsigned long ulPort,                                      \
-                   unsigned char ucPins))ROM_GPIOTABLE[23])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_GPIOPinTypeUSBDigital                                             \
-        ((void (*)(unsigned long ulPort,                                      \
-                   unsigned char ucPins))ROM_GPIOTABLE[24])
-#endif
-
-//*****************************************************************************
-//
-// Macros for calling ROM functions in the Hibernate API.
-//
-//*****************************************************************************
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_HibernateIntClear                                                 \
-        ((void (*)(unsigned long ulIntFlags))ROM_HIBERNATETABLE[0])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_HibernateEnableExpClk                                             \
-        ((void (*)(unsigned long ulHibClk))ROM_HIBERNATETABLE[1])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_HibernateDisable                                                  \
-        ((void (*)(void))ROM_HIBERNATETABLE[2])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_HibernateClockSelect                                              \
-        ((void (*)(unsigned long ulClockInput))ROM_HIBERNATETABLE[3])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_HibernateRTCEnable                                                \
-        ((void (*)(void))ROM_HIBERNATETABLE[4])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_HibernateRTCDisable                                               \
-        ((void (*)(void))ROM_HIBERNATETABLE[5])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_HibernateWakeSet                                                  \
-        ((void (*)(unsigned long ulWakeFlags))ROM_HIBERNATETABLE[6])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_HibernateWakeGet                                                  \
-        ((unsigned long (*)(void))ROM_HIBERNATETABLE[7])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_HibernateLowBatSet                                                \
-        ((void (*)(unsigned long ulLowBatFlags))ROM_HIBERNATETABLE[8])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_HibernateLowBatGet                                                \
-        ((unsigned long (*)(void))ROM_HIBERNATETABLE[9])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_HibernateRTCSet                                                   \
-        ((void (*)(unsigned long ulRTCValue))ROM_HIBERNATETABLE[10])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_HibernateRTCGet                                                   \
-        ((unsigned long (*)(void))ROM_HIBERNATETABLE[11])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_HibernateRTCMatch0Set                                             \
-        ((void (*)(unsigned long ulMatch))ROM_HIBERNATETABLE[12])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_HibernateRTCMatch0Get                                             \
-        ((unsigned long (*)(void))ROM_HIBERNATETABLE[13])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_HibernateRTCMatch1Set                                             \
-        ((void (*)(unsigned long ulMatch))ROM_HIBERNATETABLE[14])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_HibernateRTCMatch1Get                                             \
-        ((unsigned long (*)(void))ROM_HIBERNATETABLE[15])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_HibernateRTCTrimSet                                               \
-        ((void (*)(unsigned long ulTrim))ROM_HIBERNATETABLE[16])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_HibernateRTCTrimGet                                               \
-        ((unsigned long (*)(void))ROM_HIBERNATETABLE[17])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_HibernateDataSet                                                  \
-        ((void (*)(unsigned long *pulData,                                    \
-                   unsigned long ulCount))ROM_HIBERNATETABLE[18])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_HibernateDataGet                                                  \
-        ((void (*)(unsigned long *pulData,                                    \
-                   unsigned long ulCount))ROM_HIBERNATETABLE[19])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_HibernateRequest                                                  \
-        ((void (*)(void))ROM_HIBERNATETABLE[20])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_HibernateIntEnable                                                \
-        ((void (*)(unsigned long ulIntFlags))ROM_HIBERNATETABLE[21])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_HibernateIntDisable                                               \
-        ((void (*)(unsigned long ulIntFlags))ROM_HIBERNATETABLE[22])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_HibernateIntStatus                                                \
-        ((unsigned long (*)(tBoolean bMasked))ROM_HIBERNATETABLE[23])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_HibernateIsActive                                                 \
-        ((unsigned int (*)(void))ROM_HIBERNATETABLE[24])
-#endif
-
-//*****************************************************************************
-//
-// Macros for calling ROM functions in the I2C API.
-//
-//*****************************************************************************
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_I2CMasterDataPut                                                  \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned char ucData))ROM_I2CTABLE[0])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_I2CMasterInitExpClk                                               \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulI2CClk,                                    \
-                   tBoolean bFast))ROM_I2CTABLE[1])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_I2CSlaveInit                                                      \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned char ucSlaveAddr))ROM_I2CTABLE[2])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_I2CMasterEnable                                                   \
-        ((void (*)(unsigned long ulBase))ROM_I2CTABLE[3])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_I2CSlaveEnable                                                    \
-        ((void (*)(unsigned long ulBase))ROM_I2CTABLE[4])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_I2CMasterDisable                                                  \
-        ((void (*)(unsigned long ulBase))ROM_I2CTABLE[5])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_I2CSlaveDisable                                                   \
-        ((void (*)(unsigned long ulBase))ROM_I2CTABLE[6])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_I2CMasterIntEnable                                                \
-        ((void (*)(unsigned long ulBase))ROM_I2CTABLE[7])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_I2CSlaveIntEnable                                                 \
-        ((void (*)(unsigned long ulBase))ROM_I2CTABLE[8])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_I2CMasterIntDisable                                               \
-        ((void (*)(unsigned long ulBase))ROM_I2CTABLE[9])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_I2CSlaveIntDisable                                                \
-        ((void (*)(unsigned long ulBase))ROM_I2CTABLE[10])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_I2CMasterIntStatus                                                \
-        ((tBoolean (*)(unsigned long ulBase,                                  \
-                       tBoolean bMasked))ROM_I2CTABLE[11])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_I2CSlaveIntStatus                                                 \
-        ((tBoolean (*)(unsigned long ulBase,                                  \
-                       tBoolean bMasked))ROM_I2CTABLE[12])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_I2CMasterIntClear                                                 \
-        ((void (*)(unsigned long ulBase))ROM_I2CTABLE[13])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_I2CSlaveIntClear                                                  \
-        ((void (*)(unsigned long ulBase))ROM_I2CTABLE[14])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_I2CMasterSlaveAddrSet                                             \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned char ucSlaveAddr,                                 \
-                   tBoolean bReceive))ROM_I2CTABLE[15])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_I2CMasterBusy                                                     \
-        ((tBoolean (*)(unsigned long ulBase))ROM_I2CTABLE[16])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_I2CMasterBusBusy                                                  \
-        ((tBoolean (*)(unsigned long ulBase))ROM_I2CTABLE[17])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_I2CMasterControl                                                  \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulCmd))ROM_I2CTABLE[18])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_I2CMasterErr                                                      \
-        ((unsigned long (*)(unsigned long ulBase))ROM_I2CTABLE[19])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_I2CMasterDataGet                                                  \
-        ((unsigned long (*)(unsigned long ulBase))ROM_I2CTABLE[20])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_I2CSlaveStatus                                                    \
-        ((unsigned long (*)(unsigned long ulBase))ROM_I2CTABLE[21])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_I2CSlaveDataPut                                                   \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned char ucData))ROM_I2CTABLE[22])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_I2CSlaveDataGet                                                   \
-        ((unsigned long (*)(unsigned long ulBase))ROM_I2CTABLE[23])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_UpdateI2C                                                         \
-        ((void (*)(void))ROM_I2CTABLE[24])
-#endif
-
-//*****************************************************************************
-//
-// Macros for calling ROM functions in the Interrupt API.
-//
-//*****************************************************************************
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_IntEnable                                                         \
-        ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[0])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_IntMasterEnable                                                   \
-        ((tBoolean (*)(void))ROM_INTERRUPTTABLE[1])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_IntMasterDisable                                                  \
-        ((tBoolean (*)(void))ROM_INTERRUPTTABLE[2])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_IntDisable                                                        \
-        ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[3])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_IntPriorityGroupingSet                                            \
-        ((void (*)(unsigned long ulBits))ROM_INTERRUPTTABLE[4])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_IntPriorityGroupingGet                                            \
-        ((unsigned long (*)(void))ROM_INTERRUPTTABLE[5])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_IntPrioritySet                                                    \
-        ((void (*)(unsigned long ulInterrupt,                                 \
-                   unsigned char ucPriority))ROM_INTERRUPTTABLE[6])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_IntPriorityGet                                                    \
-        ((long (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[7])
-#endif
-
-//*****************************************************************************
-//
-// Macros for calling ROM functions in the MPU API.
-//
-//*****************************************************************************
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_MPUEnable                                                         \
-        ((void (*)(unsigned long ulMPUConfig))ROM_MPUTABLE[0])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_MPUDisable                                                        \
-        ((void (*)(void))ROM_MPUTABLE[1])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_MPURegionCountGet                                                 \
-        ((unsigned long (*)(void))ROM_MPUTABLE[2])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_MPURegionEnable                                                   \
-        ((void (*)(unsigned long ulRegion))ROM_MPUTABLE[3])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_MPURegionDisable                                                  \
-        ((void (*)(unsigned long ulRegion))ROM_MPUTABLE[4])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_MPURegionSet                                                      \
-        ((void (*)(unsigned long ulRegion,                                    \
-                   unsigned long ulAddr,                                      \
-                   unsigned long ulFlags))ROM_MPUTABLE[5])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_MPURegionGet                                                      \
-        ((void (*)(unsigned long ulRegion,                                    \
-                   unsigned long *pulAddr,                                    \
-                   unsigned long *pulFlags))ROM_MPUTABLE[6])
-#endif
-
-//*****************************************************************************
-//
-// Macros for calling ROM functions in the PWM API.
-//
-//*****************************************************************************
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_PWMPulseWidthSet                                                  \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulPWMOut,                                    \
-                   unsigned long ulWidth))ROM_PWMTABLE[0])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_PWMGenConfigure                                                   \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulGen,                                       \
-                   unsigned long ulConfig))ROM_PWMTABLE[1])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_PWMGenPeriodSet                                                   \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulGen,                                       \
-                   unsigned long ulPeriod))ROM_PWMTABLE[2])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_PWMGenPeriodGet                                                   \
-        ((unsigned long (*)(unsigned long ulBase,                             \
-                            unsigned long ulGen))ROM_PWMTABLE[3])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_PWMGenEnable                                                      \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulGen))ROM_PWMTABLE[4])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_PWMGenDisable                                                     \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulGen))ROM_PWMTABLE[5])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_PWMPulseWidthGet                                                  \
-        ((unsigned long (*)(unsigned long ulBase,                             \
-                            unsigned long ulPWMOut))ROM_PWMTABLE[6])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_PWMDeadBandEnable                                                 \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulGen,                                       \
-                   unsigned short usRise,                                     \
-                   unsigned short usFall))ROM_PWMTABLE[7])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_PWMDeadBandDisable                                                \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulGen))ROM_PWMTABLE[8])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_PWMSyncUpdate                                                     \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulGenBits))ROM_PWMTABLE[9])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_PWMSyncTimeBase                                                   \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulGenBits))ROM_PWMTABLE[10])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_PWMOutputState                                                    \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulPWMOutBits,                                \
-                   tBoolean bEnable))ROM_PWMTABLE[11])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_PWMOutputInvert                                                   \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulPWMOutBits,                                \
-                   tBoolean bInvert))ROM_PWMTABLE[12])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_PWMOutputFault                                                    \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulPWMOutBits,                                \
-                   tBoolean bFaultSuppress))ROM_PWMTABLE[13])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_PWMGenIntTrigEnable                                               \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulGen,                                       \
-                   unsigned long ulIntTrig))ROM_PWMTABLE[14])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_PWMGenIntTrigDisable                                              \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulGen,                                       \
-                   unsigned long ulIntTrig))ROM_PWMTABLE[15])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_PWMGenIntStatus                                                   \
-        ((unsigned long (*)(unsigned long ulBase,                             \
-                            unsigned long ulGen,                              \
-                            tBoolean bMasked))ROM_PWMTABLE[16])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_PWMGenIntClear                                                    \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulGen,                                       \
-                   unsigned long ulInts))ROM_PWMTABLE[17])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_PWMIntEnable                                                      \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulGenFault))ROM_PWMTABLE[18])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_PWMIntDisable                                                     \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulGenFault))ROM_PWMTABLE[19])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_PWMFaultIntClear                                                  \
-        ((void (*)(unsigned long ulBase))ROM_PWMTABLE[20])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_PWMIntStatus                                                      \
-        ((unsigned long (*)(unsigned long ulBase,                             \
-                            tBoolean bMasked))ROM_PWMTABLE[21])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_PWMOutputFaultLevel                                               \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulPWMOutBits,                                \
-                   tBoolean bDriveHigh))ROM_PWMTABLE[22])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_PWMFaultIntClearExt                                               \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulFaultInts))ROM_PWMTABLE[23])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_PWMGenFaultConfigure                                              \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulGen,                                       \
-                   unsigned long ulMinFaultPeriod,                            \
-                   unsigned long ulFaultSenses))ROM_PWMTABLE[24])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_PWMGenFaultTriggerSet                                             \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulGen,                                       \
-                   unsigned long ulGroup,                                     \
-                   unsigned long ulFaultTriggers))ROM_PWMTABLE[25])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_PWMGenFaultTriggerGet                                             \
-        ((unsigned long (*)(unsigned long ulBase,                             \
-                            unsigned long ulGen,                              \
-                            unsigned long ulGroup))ROM_PWMTABLE[26])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_PWMGenFaultStatus                                                 \
-        ((unsigned long (*)(unsigned long ulBase,                             \
-                            unsigned long ulGen,                              \
-                            unsigned long ulGroup))ROM_PWMTABLE[27])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_PWMGenFaultClear                                                  \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulGen,                                       \
-                   unsigned long ulGroup,                                     \
-                   unsigned long ulFaultTriggers))ROM_PWMTABLE[28])
-#endif
-
-//*****************************************************************************
-//
-// Macros for calling ROM functions in the QEI API.
-//
-//*****************************************************************************
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_QEIPositionGet                                                    \
-        ((unsigned long (*)(unsigned long ulBase))ROM_QEITABLE[0])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_QEIEnable                                                         \
-        ((void (*)(unsigned long ulBase))ROM_QEITABLE[1])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_QEIDisable                                                        \
-        ((void (*)(unsigned long ulBase))ROM_QEITABLE[2])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_QEIConfigure                                                      \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulConfig,                                    \
-                   unsigned long ulMaxPosition))ROM_QEITABLE[3])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_QEIPositionSet                                                    \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulPosition))ROM_QEITABLE[4])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_QEIDirectionGet                                                   \
-        ((long (*)(unsigned long ulBase))ROM_QEITABLE[5])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_QEIErrorGet                                                       \
-        ((tBoolean (*)(unsigned long ulBase))ROM_QEITABLE[6])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_QEIVelocityEnable                                                 \
-        ((void (*)(unsigned long ulBase))ROM_QEITABLE[7])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_QEIVelocityDisable                                                \
-        ((void (*)(unsigned long ulBase))ROM_QEITABLE[8])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_QEIVelocityConfigure                                              \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulPreDiv,                                    \
-                   unsigned long ulPeriod))ROM_QEITABLE[9])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_QEIVelocityGet                                                    \
-        ((unsigned long (*)(unsigned long ulBase))ROM_QEITABLE[10])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_QEIIntEnable                                                      \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulIntFlags))ROM_QEITABLE[11])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_QEIIntDisable                                                     \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulIntFlags))ROM_QEITABLE[12])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_QEIIntStatus                                                      \
-        ((unsigned long (*)(unsigned long ulBase,                             \
-                            tBoolean bMasked))ROM_QEITABLE[13])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_QEIIntClear                                                       \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulIntFlags))ROM_QEITABLE[14])
-#endif
-
-//*****************************************************************************
-//
-// Macros for calling ROM functions in the SSI API.
-//
-//*****************************************************************************
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_SSIDataPut                                                        \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulData))ROM_SSITABLE[0])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_SSIConfigSetExpClk                                                \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulSSIClk,                                    \
-                   unsigned long ulProtocol,                                  \
-                   unsigned long ulMode,                                      \
-                   unsigned long ulBitRate,                                   \
-                   unsigned long ulDataWidth))ROM_SSITABLE[1])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_SSIEnable                                                         \
-        ((void (*)(unsigned long ulBase))ROM_SSITABLE[2])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_SSIDisable                                                        \
-        ((void (*)(unsigned long ulBase))ROM_SSITABLE[3])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_SSIIntEnable                                                      \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulIntFlags))ROM_SSITABLE[4])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_SSIIntDisable                                                     \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulIntFlags))ROM_SSITABLE[5])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_SSIIntStatus                                                      \
-        ((unsigned long (*)(unsigned long ulBase,                             \
-                            tBoolean bMasked))ROM_SSITABLE[6])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_SSIIntClear                                                       \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulIntFlags))ROM_SSITABLE[7])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_SSIDataPutNonBlocking                                             \
-        ((long (*)(unsigned long ulBase,                                      \
-                   unsigned long ulData))ROM_SSITABLE[8])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_SSIDataGet                                                        \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long *pulData))ROM_SSITABLE[9])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_SSIDataGetNonBlocking                                             \
-        ((long (*)(unsigned long ulBase,                                      \
-                   unsigned long *pulData))ROM_SSITABLE[10])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_UpdateSSI                                                         \
-        ((void (*)(void))ROM_SSITABLE[11])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_SSIDMAEnable                                                      \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulDMAFlags))ROM_SSITABLE[12])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_SSIDMADisable                                                     \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulDMAFlags))ROM_SSITABLE[13])
-#endif
-
-//*****************************************************************************
-//
-// Macros for calling ROM functions in the SysCtl API.
-//
-//*****************************************************************************
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_SysCtlSleep                                                       \
-        ((void (*)(void))ROM_SYSCTLTABLE[0])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_SysCtlSRAMSizeGet                                                 \
-        ((unsigned long (*)(void))ROM_SYSCTLTABLE[1])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_SysCtlFlashSizeGet                                                \
-        ((unsigned long (*)(void))ROM_SYSCTLTABLE[2])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_SysCtlPinPresent                                                  \
-        ((tBoolean (*)(unsigned long ulPin))ROM_SYSCTLTABLE[3])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_SysCtlPeripheralPresent                                           \
-        ((tBoolean (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[4])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_SysCtlPeripheralReset                                             \
-        ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[5])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_SysCtlPeripheralEnable                                            \
-        ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[6])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_SysCtlPeripheralDisable                                           \
-        ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[7])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_SysCtlPeripheralSleepEnable                                       \
-        ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[8])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_SysCtlPeripheralSleepDisable                                      \
-        ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[9])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_SysCtlPeripheralDeepSleepEnable                                   \
-        ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[10])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_SysCtlPeripheralDeepSleepDisable                                  \
-        ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[11])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_SysCtlPeripheralClockGating                                       \
-        ((void (*)(tBoolean bEnable))ROM_SYSCTLTABLE[12])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_SysCtlIntEnable                                                   \
-        ((void (*)(unsigned long ulInts))ROM_SYSCTLTABLE[13])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_SysCtlIntDisable                                                  \
-        ((void (*)(unsigned long ulInts))ROM_SYSCTLTABLE[14])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_SysCtlIntClear                                                    \
-        ((void (*)(unsigned long ulInts))ROM_SYSCTLTABLE[15])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_SysCtlIntStatus                                                   \
-        ((unsigned long (*)(tBoolean bMasked))ROM_SYSCTLTABLE[16])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_SysCtlLDOSet                                                      \
-        ((void (*)(unsigned long ulVoltage))ROM_SYSCTLTABLE[17])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_SysCtlLDOGet                                                      \
-        ((unsigned long (*)(void))ROM_SYSCTLTABLE[18])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_SysCtlReset                                                       \
-        ((void (*)(void))ROM_SYSCTLTABLE[19])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_SysCtlDeepSleep                                                   \
-        ((void (*)(void))ROM_SYSCTLTABLE[20])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_SysCtlResetCauseGet                                               \
-        ((unsigned long (*)(void))ROM_SYSCTLTABLE[21])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_SysCtlResetCauseClear                                             \
-        ((void (*)(unsigned long ulCauses))ROM_SYSCTLTABLE[22])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_SysCtlClockSet                                                    \
-        ((void (*)(unsigned long ulConfig))ROM_SYSCTLTABLE[23])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_SysCtlClockGet                                                    \
-        ((unsigned long (*)(void))ROM_SYSCTLTABLE[24])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_SysCtlPWMClockSet                                                 \
-        ((void (*)(unsigned long ulConfig))ROM_SYSCTLTABLE[25])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_SysCtlPWMClockGet                                                 \
-        ((unsigned long (*)(void))ROM_SYSCTLTABLE[26])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_SysCtlADCSpeedSet                                                 \
-        ((void (*)(unsigned long ulSpeed))ROM_SYSCTLTABLE[27])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_SysCtlADCSpeedGet                                                 \
-        ((unsigned long (*)(void))ROM_SYSCTLTABLE[28])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_SysCtlGPIOAHBEnable                                               \
-        ((void (*)(unsigned long ulGPIOPeripheral))ROM_SYSCTLTABLE[29])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_SysCtlGPIOAHBDisable                                              \
-        ((void (*)(unsigned long ulGPIOPeripheral))ROM_SYSCTLTABLE[30])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_SysCtlUSBPLLEnable                                                \
-        ((void (*)(void))ROM_SYSCTLTABLE[31])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_SysCtlUSBPLLDisable                                               \
-        ((void (*)(void))ROM_SYSCTLTABLE[32])
-#endif
-
-//*****************************************************************************
-//
-// Macros for calling ROM functions in the SysTick API.
-//
-//*****************************************************************************
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_SysTickValueGet                                                   \
-        ((unsigned long (*)(void))ROM_SYSTICKTABLE[0])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_SysTickEnable                                                     \
-        ((void (*)(void))ROM_SYSTICKTABLE[1])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_SysTickDisable                                                    \
-        ((void (*)(void))ROM_SYSTICKTABLE[2])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_SysTickIntEnable                                                  \
-        ((void (*)(void))ROM_SYSTICKTABLE[3])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_SysTickIntDisable                                                 \
-        ((void (*)(void))ROM_SYSTICKTABLE[4])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_SysTickPeriodSet                                                  \
-        ((void (*)(unsigned long ulPeriod))ROM_SYSTICKTABLE[5])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_SysTickPeriodGet                                                  \
-        ((unsigned long (*)(void))ROM_SYSTICKTABLE[6])
-#endif
-
-//*****************************************************************************
-//
-// Macros for calling ROM functions in the Timer API.
-//
-//*****************************************************************************
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_TimerIntClear                                                     \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulIntFlags))ROM_TIMERTABLE[0])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_TimerEnable                                                       \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulTimer))ROM_TIMERTABLE[1])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_TimerDisable                                                      \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulTimer))ROM_TIMERTABLE[2])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_TimerConfigure                                                    \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulConfig))ROM_TIMERTABLE[3])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_TimerControlLevel                                                 \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulTimer,                                     \
-                   tBoolean bInvert))ROM_TIMERTABLE[4])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_TimerControlTrigger                                               \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulTimer,                                     \
-                   tBoolean bEnable))ROM_TIMERTABLE[5])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_TimerControlEvent                                                 \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulTimer,                                     \
-                   unsigned long ulEvent))ROM_TIMERTABLE[6])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_TimerControlStall                                                 \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulTimer,                                     \
-                   tBoolean bStall))ROM_TIMERTABLE[7])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_TimerRTCEnable                                                    \
-        ((void (*)(unsigned long ulBase))ROM_TIMERTABLE[8])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_TimerRTCDisable                                                   \
-        ((void (*)(unsigned long ulBase))ROM_TIMERTABLE[9])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_TimerPrescaleSet                                                  \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulTimer,                                     \
-                   unsigned long ulValue))ROM_TIMERTABLE[10])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_TimerPrescaleGet                                                  \
-        ((unsigned long (*)(unsigned long ulBase,                             \
-                            unsigned long ulTimer))ROM_TIMERTABLE[11])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_TimerLoadSet                                                      \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulTimer,                                     \
-                   unsigned long ulValue))ROM_TIMERTABLE[14])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_TimerLoadGet                                                      \
-        ((unsigned long (*)(unsigned long ulBase,                             \
-                            unsigned long ulTimer))ROM_TIMERTABLE[15])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_TimerValueGet                                                     \
-        ((unsigned long (*)(unsigned long ulBase,                             \
-                            unsigned long ulTimer))ROM_TIMERTABLE[16])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_TimerMatchSet                                                     \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulTimer,                                     \
-                   unsigned long ulValue))ROM_TIMERTABLE[17])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_TimerMatchGet                                                     \
-        ((unsigned long (*)(unsigned long ulBase,                             \
-                            unsigned long ulTimer))ROM_TIMERTABLE[18])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_TimerIntEnable                                                    \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulIntFlags))ROM_TIMERTABLE[19])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_TimerIntDisable                                                   \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulIntFlags))ROM_TIMERTABLE[20])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_TimerIntStatus                                                    \
-        ((unsigned long (*)(unsigned long ulBase,                             \
-                            tBoolean bMasked))ROM_TIMERTABLE[21])
-#endif
-
-//*****************************************************************************
-//
-// Macros for calling ROM functions in the UART API.
-//
-//*****************************************************************************
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_UARTCharPut                                                       \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned char ucData))ROM_UARTTABLE[0])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_UARTParityModeSet                                                 \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulParity))ROM_UARTTABLE[1])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_UARTParityModeGet                                                 \
-        ((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[2])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_UARTFIFOLevelSet                                                  \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulTxLevel,                                   \
-                   unsigned long ulRxLevel))ROM_UARTTABLE[3])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_UARTFIFOLevelGet                                                  \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long *pulTxLevel,                                 \
-                   unsigned long *pulRxLevel))ROM_UARTTABLE[4])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_UARTConfigSetExpClk                                               \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulUARTClk,                                   \
-                   unsigned long ulBaud,                                      \
-                   unsigned long ulConfig))ROM_UARTTABLE[5])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_UARTConfigGetExpClk                                               \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulUARTClk,                                   \
-                   unsigned long *pulBaud,                                    \
-                   unsigned long *pulConfig))ROM_UARTTABLE[6])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_UARTEnable                                                        \
-        ((void (*)(unsigned long ulBase))ROM_UARTTABLE[7])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_UARTDisable                                                       \
-        ((void (*)(unsigned long ulBase))ROM_UARTTABLE[8])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_UARTEnableSIR                                                     \
-        ((void (*)(unsigned long ulBase,                                      \
-                   tBoolean bLowPower))ROM_UARTTABLE[9])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_UARTDisableSIR                                                    \
-        ((void (*)(unsigned long ulBase))ROM_UARTTABLE[10])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_UARTCharsAvail                                                    \
-        ((tBoolean (*)(unsigned long ulBase))ROM_UARTTABLE[11])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_UARTSpaceAvail                                                    \
-        ((tBoolean (*)(unsigned long ulBase))ROM_UARTTABLE[12])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_UARTCharGetNonBlocking                                            \
-        ((long (*)(unsigned long ulBase))ROM_UARTTABLE[13])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_UARTCharGet                                                       \
-        ((long (*)(unsigned long ulBase))ROM_UARTTABLE[14])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_UARTCharPutNonBlocking                                            \
-        ((tBoolean (*)(unsigned long ulBase,                                  \
-                       unsigned char ucData))ROM_UARTTABLE[15])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_UARTBreakCtl                                                      \
-        ((void (*)(unsigned long ulBase,                                      \
-                   tBoolean bBreakState))ROM_UARTTABLE[16])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_UARTIntEnable                                                     \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulIntFlags))ROM_UARTTABLE[17])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_UARTIntDisable                                                    \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulIntFlags))ROM_UARTTABLE[18])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_UARTIntStatus                                                     \
-        ((unsigned long (*)(unsigned long ulBase,                             \
-                            tBoolean bMasked))ROM_UARTTABLE[19])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_UARTIntClear                                                      \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulIntFlags))ROM_UARTTABLE[20])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_UpdateUART                                                        \
-        ((void (*)(void))ROM_UARTTABLE[21])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_UARTDMAEnable                                                     \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulDMAFlags))ROM_UARTTABLE[22])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_UARTDMADisable                                                    \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulDMAFlags))ROM_UARTTABLE[23])
-#endif
-
-//*****************************************************************************
-//
-// Macros for calling ROM functions in the uDMA API.
-//
-//*****************************************************************************
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_uDMAChannelTransferSet                                            \
-        ((void (*)(unsigned long ulChannel,                                   \
-                   unsigned long ulMode,                                      \
-                   void *pvSrcAddr,                                           \
-                   void *pvDstAddr,                                           \
-                   unsigned long ulTransferSize))ROM_UDMATABLE[0])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_uDMAEnable                                                        \
-        ((void (*)(void))ROM_UDMATABLE[1])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_uDMADisable                                                       \
-        ((void (*)(void))ROM_UDMATABLE[2])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_uDMAErrorStatusGet                                                \
-        ((unsigned long (*)(void))ROM_UDMATABLE[3])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_uDMAErrorStatusClear                                              \
-        ((void (*)(void))ROM_UDMATABLE[4])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_uDMAChannelEnable                                                 \
-        ((void (*)(unsigned long ulChannel))ROM_UDMATABLE[5])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_uDMAChannelDisable                                                \
-        ((void (*)(unsigned long ulChannel))ROM_UDMATABLE[6])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_uDMAChannelIsEnabled                                              \
-        ((tBoolean (*)(unsigned long ulChannel))ROM_UDMATABLE[7])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_uDMAControlBaseSet                                                \
-        ((void (*)(void *pControlTable))ROM_UDMATABLE[8])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_uDMAControlBaseGet                                                \
-        ((void * (*)(void))ROM_UDMATABLE[9])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_uDMAChannelRequest                                                \
-        ((void (*)(unsigned long ulChannel))ROM_UDMATABLE[10])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_uDMAChannelAttributeEnable                                        \
-        ((void (*)(unsigned long ulChannel,                                   \
-                   unsigned long ulAttr))ROM_UDMATABLE[11])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_uDMAChannelAttributeDisable                                       \
-        ((void (*)(unsigned long ulChannel,                                   \
-                   unsigned long ulAttr))ROM_UDMATABLE[12])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_uDMAChannelAttributeGet                                           \
-        ((unsigned long (*)(unsigned long ulChannel))ROM_UDMATABLE[13])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_uDMAChannelControlSet                                             \
-        ((void (*)(unsigned long ulChannel,                                   \
-                   unsigned long ulControl))ROM_UDMATABLE[14])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_uDMAChannelSizeGet                                                \
-        ((unsigned long (*)(unsigned long ulChannel))ROM_UDMATABLE[15])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_uDMAChannelModeGet                                                \
-        ((unsigned long (*)(unsigned long ulChannel))ROM_UDMATABLE[16])
-#endif
-
-//*****************************************************************************
-//
-// Macros for calling ROM functions in the USB API.
-//
-//*****************************************************************************
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_USBIntStatus                                                      \
-        ((unsigned long (*)(unsigned long ulBase))ROM_USBTABLE[0])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_USBDevAddrGet                                                     \
-        ((unsigned long (*)(unsigned long ulBase))ROM_USBTABLE[1])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_USBDevAddrSet                                                     \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulAddress))ROM_USBTABLE[2])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_USBDevConnect                                                     \
-        ((void (*)(unsigned long ulBase))ROM_USBTABLE[3])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_USBDevDisconnect                                                  \
-        ((void (*)(unsigned long ulBase))ROM_USBTABLE[4])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_USBDevEndpointConfig                                              \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulEndpoint,                                  \
-                   unsigned long ulMaxPacketSize,                             \
-                   unsigned long ulFlags))ROM_USBTABLE[5])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_USBDevEndpointDataAck                                             \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulEndpoint,                                  \
-                   tBoolean bIsLastPacket))ROM_USBTABLE[6])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_USBDevEndpointStall                                               \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulEndpoint,                                  \
-                   unsigned long ulFlags))ROM_USBTABLE[7])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_USBDevEndpointStallClear                                          \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulEndpoint,                                  \
-                   unsigned long ulFlags))ROM_USBTABLE[8])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_USBDevEndpointStatusClear                                         \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulEndpoint,                                  \
-                   unsigned long ulFlags))ROM_USBTABLE[9])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_USBEndpointDataGet                                                \
-        ((long (*)(unsigned long ulBase,                                      \
-                   unsigned long ulEndpoint,                                  \
-                   unsigned char *pucData,                                    \
-                   unsigned long *pulSize))ROM_USBTABLE[10])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_USBEndpointDataPut                                                \
-        ((long (*)(unsigned long ulBase,                                      \
-                   unsigned long ulEndpoint,                                  \
-                   unsigned char *pucData,                                    \
-                   unsigned long ulSize))ROM_USBTABLE[11])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_USBEndpointDataSend                                               \
-        ((long (*)(unsigned long ulBase,                                      \
-                   unsigned long ulEndpoint,                                  \
-                   unsigned long ulTransType))ROM_USBTABLE[12])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_USBEndpointDataToggleClear                                        \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulEndpoint,                                  \
-                   unsigned long ulFlags))ROM_USBTABLE[13])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_USBEndpointStatus                                                 \
-        ((unsigned long (*)(unsigned long ulBase,                             \
-                            unsigned long ulEndpoint))ROM_USBTABLE[14])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_USBFIFOAddrGet                                                    \
-        ((unsigned long (*)(unsigned long ulBase,                             \
-                            unsigned long ulEndpoint))ROM_USBTABLE[15])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_USBFIFOConfigGet                                                  \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulEndpoint,                                  \
-                   unsigned long *pulFIFOAddress,                             \
-                   unsigned long *pulFIFOSize,                                \
-                   unsigned long ulFlags))ROM_USBTABLE[16])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_USBFIFOConfigSet                                                  \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulEndpoint,                                  \
-                   unsigned long ulFIFOAddress,                               \
-                   unsigned long ulFIFOSize,                                  \
-                   unsigned long ulFlags))ROM_USBTABLE[17])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_USBFIFOFlush                                                      \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulEndpoint,                                  \
-                   unsigned long ulFlags))ROM_USBTABLE[18])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_USBFrameNumberGet                                                 \
-        ((unsigned long (*)(unsigned long ulBase))ROM_USBTABLE[19])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_USBHostAddrGet                                                    \
-        ((unsigned long (*)(unsigned long ulBase,                             \
-                            unsigned long ulEndpoint,                         \
-                            unsigned long ulFlags))ROM_USBTABLE[20])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_USBHostAddrSet                                                    \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulEndpoint,                                  \
-                   unsigned long ulAddr,                                      \
-                   unsigned long ulFlags))ROM_USBTABLE[21])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_USBHostEndpointConfig                                             \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulEndpoint,                                  \
-                   unsigned long ulMaxPacketSize,                             \
-                   unsigned long ulNAKPollInterval,                           \
-                   unsigned long ulTargetEndpoint,                            \
-                   unsigned long ulFlags))ROM_USBTABLE[22])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_USBHostEndpointDataAck                                            \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulEndpoint))ROM_USBTABLE[23])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_USBHostEndpointDataToggle                                         \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulEndpoint,                                  \
-                   tBoolean bDataToggle,                                      \
-                   unsigned long ulFlags))ROM_USBTABLE[24])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_USBHostEndpointStatusClear                                        \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulEndpoint,                                  \
-                   unsigned long ulFlags))ROM_USBTABLE[25])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_USBHostHubAddrGet                                                 \
-        ((unsigned long (*)(unsigned long ulBase,                             \
-                            unsigned long ulEndpoint,                         \
-                            unsigned long ulFlags))ROM_USBTABLE[26])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_USBHostHubAddrSet                                                 \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulEndpoint,                                  \
-                   unsigned long ulAddr,                                      \
-                   unsigned long ulFlags))ROM_USBTABLE[27])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_USBHostPwrDisable                                                 \
-        ((void (*)(unsigned long ulBase))ROM_USBTABLE[28])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_USBHostPwrEnable                                                  \
-        ((void (*)(unsigned long ulBase))ROM_USBTABLE[29])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_USBHostPwrFaultConfig                                             \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulFlags))ROM_USBTABLE[30])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_USBHostPwrFaultDisable                                            \
-        ((void (*)(unsigned long ulBase))ROM_USBTABLE[31])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_USBHostPwrFaultEnable                                             \
-        ((void (*)(unsigned long ulBase))ROM_USBTABLE[32])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_USBHostRequestIN                                                  \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulEndpoint))ROM_USBTABLE[33])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_USBHostRequestStatus                                              \
-        ((void (*)(unsigned long ulBase))ROM_USBTABLE[34])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_USBHostReset                                                      \
-        ((void (*)(unsigned long ulBase,                                      \
-                   tBoolean bStart))ROM_USBTABLE[35])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_USBHostResume                                                     \
-        ((void (*)(unsigned long ulBase,                                      \
-                   tBoolean bStart))ROM_USBTABLE[36])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_USBHostSpeedGet                                                   \
-        ((unsigned long (*)(unsigned long ulBase))ROM_USBTABLE[37])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_USBHostSuspend                                                    \
-        ((void (*)(unsigned long ulBase))ROM_USBTABLE[38])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_USBIntDisable                                                     \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulIntFlags))ROM_USBTABLE[39])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_USBIntEnable                                                      \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulIntFlags))ROM_USBTABLE[40])
-#endif
-
-//*****************************************************************************
-//
-// Macros for calling ROM functions in the Watchdog API.
-//
-//*****************************************************************************
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_WatchdogIntClear                                                  \
-        ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[0])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_WatchdogRunning                                                   \
-        ((tBoolean (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[1])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_WatchdogEnable                                                    \
-        ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[2])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_WatchdogResetEnable                                               \
-        ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[3])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_WatchdogResetDisable                                              \
-        ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[4])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_WatchdogLock                                                      \
-        ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[5])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_WatchdogUnlock                                                    \
-        ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[6])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_WatchdogLockState                                                 \
-        ((tBoolean (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[7])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_WatchdogReloadSet                                                 \
-        ((void (*)(unsigned long ulBase,                                      \
-                   unsigned long ulLoadVal))ROM_WATCHDOGTABLE[8])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_WatchdogReloadGet                                                 \
-        ((unsigned long (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[9])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_WatchdogValueGet                                                  \
-        ((unsigned long (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[10])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_WatchdogIntEnable                                                 \
-        ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[11])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_WatchdogIntStatus                                                 \
-        ((unsigned long (*)(unsigned long ulBase,                             \
-                            tBoolean bMasked))ROM_WATCHDOGTABLE[12])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_WatchdogStallEnable                                               \
-        ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[13])
-#endif
-#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
-    defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_WatchdogStallDisable                                              \
-        ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[14])
-#endif
-
-//*****************************************************************************
-//
-// Macros for calling ROM functions in the Software API.
-//
-//*****************************************************************************
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_Crc16Array                                                        \
-        ((unsigned short (*)(unsigned long ulWordLen,                         \
-                             unsigned long *pulData))ROM_SOFTWARETABLE[1])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_Crc16Array3                                                       \
-        ((void (*)(unsigned long ulWordLen,                                   \
-                   unsigned long *pulData,                                    \
-                   unsigned short *pusCrc3))ROM_SOFTWARETABLE[2])
-#endif
-#if defined(TARGET_IS_TEMPEST_RB1)
-#define ROM_pvAESTable                                                        \
-        ((void *)&(ROM_SOFTWARETABLE[7]))
-#endif
-
-#endif // __ROM_H__
diff --git a/src/platform/lm3s/startup_gcc.c b/src/platform/lm3s/startup_gcc.c
index ae74a967..2f7e4bba 100644
--- a/src/platform/lm3s/startup_gcc.c
+++ b/src/platform/lm3s/startup_gcc.c
@@ -41,15 +41,23 @@ extern void EthernetIntHandler();
 extern void SysTickIntHandler();
 extern void ADCIntHandler();
 extern void UARTIntHandler();
-extern void CANIntHandler();
+
 
 #include "hw_memmap.h"
 #include "platform_conf.h"
 
+#if defined( BUILD_CAN )
+extern void CANIntHandler();
+#endif
+
 extern void uart0_handler();
 extern void uart1_handler();
 extern void uart2_handler();
 
+#if defined( BUILD_USB_CDC )
+extern void USB0DeviceIntHandler(void);
+#endif
+
 
 //*****************************************************************************
 //
@@ -142,11 +150,34 @@ void (* const g_pfnVectors[])(void) =
     IntDefaultHandler,                      // Timer 3 subtimer B
     IntDefaultHandler,                      // I2C1 Master and Slave
     IntDefaultHandler,                      // Quadrature Encoder 1
+#if defined( BUILD_CAN )
     CANIntHandler,                          // CAN0
+#else
+    IntDefaultHandler,                      // CAN0
+#endif
     IntDefaultHandler,                      // CAN1
     IntDefaultHandler,                      // CAN2
     EthernetIntHandler,                     // Ethernet
+#if defined( FORLM3S9B92 ) || defined( FORLM3S9D92 )
+    IntDefaultHandler,                      // Hibernate
+#if defined( BUILD_USB_CDC )
+    USB0DeviceIntHandler,                   // USB0
+#else
+    IntDefaultHandler,                      // USB0
+#endif
+    IntDefaultHandler,                      // PWM Generator 3
+    IntDefaultHandler,                      // uDMA Software Transfer
+    IntDefaultHandler,                      // uDMA Error
+    IntDefaultHandler,                      // ADC1 Sequence 0
+    IntDefaultHandler,                      // ADC1 Sequence 1
+    IntDefaultHandler,                      // ADC1 Sequence 2
+    IntDefaultHandler,                      // ADC1 Sequence 3
+    IntDefaultHandler,                      // I2S0
+    IntDefaultHandler,                      // External Bus Interface 0
+    IntDefaultHandler                       // GPIO Port J    
+#else
     IntDefaultHandler                       // Hibernate
+#endif
 };
 
 //*****************************************************************************
diff --git a/src/platform/lm3s/uip-conf.h b/src/platform/lm3s/uip-conf.h
index 79a14929..32dcb927 100644
--- a/src/platform/lm3s/uip-conf.h
+++ b/src/platform/lm3s/uip-conf.h
@@ -150,8 +150,6 @@ typedef struct dhcpc_state uip_udp_appstate_t;
 #define UIP_UDP_APPCALL             elua_uip_udp_appcall
 #endif
 
-// Added for eLua: DHCP TIMER ID
-#define ELUA_DHCP_TIMER_ID          1
 #define CLOCK_SECOND                1000000UL
 
 #endif // __UIP_CONF_H_
diff --git a/src/platform/lm3s/usb_serial_structs.c b/src/platform/lm3s/usb_serial_structs.c
new file mode 100755
index 00000000..111afdc6
--- /dev/null
+++ b/src/platform/lm3s/usb_serial_structs.c
@@ -0,0 +1,216 @@
+//*****************************************************************************
+//
+// usb_serial_structs.c - Data structures defining this CDC USB device.
+//
+// Copyright (c) 2009-2011 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 7611 of the EK-LM3S9D92 Firmware Package.
+//
+//*****************************************************************************
+
+#include "inc/hw_types.h"
+#include "driverlib/usb.h"
+#include "usblib/usblib.h"
+#include "usblib/usbcdc.h"
+#include "usblib/usb-ids.h"
+#include "usblib/device/usbdevice.h"
+#include "usblib/device/usbdcdc.h"
+#include "usb_serial_structs.h"
+
+//*****************************************************************************
+//
+// The languages supported by this device.
+//
+//*****************************************************************************
+const unsigned char g_pLangDescriptor[] =
+{
+    4,
+    USB_DTYPE_STRING,
+    USBShort(USB_LANG_EN_US)
+};
+
+//*****************************************************************************
+//
+// The manufacturer string.
+//
+//*****************************************************************************
+const unsigned char g_pManufacturerString[] =
+{
+    (17 + 1) * 2,
+    USB_DTYPE_STRING,
+    'T', 0, 'e', 0, 'x', 0, 'a', 0, 's', 0, ' ', 0, 'I', 0, 'n', 0, 's', 0,
+    't', 0, 'r', 0, 'u', 0, 'm', 0, 'e', 0, 'n', 0, 't', 0, 's', 0,
+};
+
+//*****************************************************************************
+//
+// The product string.
+//
+//*****************************************************************************
+const unsigned char g_pProductString[] =
+{
+    2 + (16 * 2),
+    USB_DTYPE_STRING,
+    'V', 0, 'i', 0, 'r', 0, 't', 0, 'u', 0, 'a', 0, 'l', 0, ' ', 0,
+    'C', 0, 'O', 0, 'M', 0, ' ', 0, 'P', 0, 'o', 0, 'r', 0, 't', 0
+};
+
+//*****************************************************************************
+//
+// The serial number string.
+//
+//*****************************************************************************
+const unsigned char g_pSerialNumberString[] =
+{
+    2 + (8 * 2),
+    USB_DTYPE_STRING,
+    '1', 0, '2', 0, '3', 0, '4', 0, '5', 0, '6', 0, '7', 0, '8', 0
+};
+
+//*****************************************************************************
+//
+// The control interface description string.
+//
+//*****************************************************************************
+const unsigned char g_pControlInterfaceString[] =
+{
+    2 + (21 * 2),
+    USB_DTYPE_STRING,
+    'A', 0, 'C', 0, 'M', 0, ' ', 0, 'C', 0, 'o', 0, 'n', 0, 't', 0,
+    'r', 0, 'o', 0, 'l', 0, ' ', 0, 'I', 0, 'n', 0, 't', 0, 'e', 0,
+    'r', 0, 'f', 0, 'a', 0, 'c', 0, 'e', 0
+};
+
+//*****************************************************************************
+//
+// The configuration description string.
+//
+//*****************************************************************************
+const unsigned char g_pConfigString[] =
+{
+    2 + (26 * 2),
+    USB_DTYPE_STRING,
+    'S', 0, 'e', 0, 'l', 0, 'f', 0, ' ', 0, 'P', 0, 'o', 0, 'w', 0,
+    'e', 0, 'r', 0, 'e', 0, 'd', 0, ' ', 0, 'C', 0, 'o', 0, 'n', 0,
+    'f', 0, 'i', 0, 'g', 0, 'u', 0, 'r', 0, 'a', 0, 't', 0, 'i', 0,
+    'o', 0, 'n', 0
+};
+
+//*****************************************************************************
+//
+// The descriptor string table.
+//
+//*****************************************************************************
+const unsigned char * const g_pStringDescriptors[] =
+{
+    g_pLangDescriptor,
+    g_pManufacturerString,
+    g_pProductString,
+    g_pSerialNumberString,
+    g_pControlInterfaceString,
+    g_pConfigString
+};
+
+#define NUM_STRING_DESCRIPTORS (sizeof(g_pStringDescriptors) /                \
+                                sizeof(unsigned char *))
+
+//*****************************************************************************
+//
+// CDC device callback function prototypes.
+//
+//*****************************************************************************
+unsigned long RxHandler(void *pvCBData, unsigned long ulEvent,
+                        unsigned long ulMsgValue, void *pvMsgData);
+unsigned long TxHandler(void *pvCBData, unsigned long ulEvent,
+                        unsigned long ulMsgValue, void *pvMsgData);
+unsigned long ControlHandler(void *pvCBData, unsigned long ulEvent,
+                             unsigned long ulMsgValue, void *pvMsgData);
+
+//*****************************************************************************
+//
+// The CDC device initialization and customization structures. In this case,
+// we are using USBBuffers between the CDC device class driver and the
+// application code. The function pointers and callback data values are set
+// to insert a buffer in each of the data channels, transmit and receive.
+//
+// With the buffer in place, the CDC channel callback is set to the relevant
+// channel function and the callback data is set to point to the channel
+// instance data. The buffer, in turn, has its callback set to the application
+// function and the callback data set to our CDC instance structure.
+//
+//*****************************************************************************
+tCDCSerInstance g_sCDCInstance;
+
+extern const tUSBBuffer g_sTxBuffer;
+extern const tUSBBuffer g_sRxBuffer;
+
+const tUSBDCDCDevice g_sCDCDevice =
+{
+    USB_VID_STELLARIS,
+    USB_PID_SERIAL,
+    0,
+    USB_CONF_ATTR_SELF_PWR,
+    ControlHandler,
+    (void *)&g_sCDCDevice,
+    USBBufferEventCallback,
+    (void *)&g_sRxBuffer,
+    USBBufferEventCallback,
+    (void *)&g_sTxBuffer,
+    g_pStringDescriptors,
+    NUM_STRING_DESCRIPTORS,
+    &g_sCDCInstance
+};
+
+//*****************************************************************************
+//
+// Receive buffer (from the USB perspective).
+//
+//*****************************************************************************
+unsigned char g_pcUSBRxBuffer[UART_BUFFER_SIZE];
+unsigned char g_pucRxBufferWorkspace[USB_BUFFER_WORKSPACE_SIZE];
+const tUSBBuffer g_sRxBuffer =
+{
+    false,                          // This is a receive buffer.
+    RxHandler,                      // pfnCallback
+    (void *)&g_sCDCDevice,          // Callback data is our device pointer.
+    USBDCDCPacketRead,              // pfnTransfer
+    USBDCDCRxPacketAvailable,       // pfnAvailable
+    (void *)&g_sCDCDevice,          // pvHandle
+    g_pcUSBRxBuffer,                // pcBuffer
+    UART_BUFFER_SIZE,               // ulBufferSize
+    g_pucRxBufferWorkspace          // pvWorkspace
+};
+
+//*****************************************************************************
+//
+// Transmit buffer (from the USB perspective).
+//
+//*****************************************************************************
+unsigned char g_pcUSBTxBuffer[UART_BUFFER_SIZE];
+unsigned char g_pucTxBufferWorkspace[USB_BUFFER_WORKSPACE_SIZE];
+const tUSBBuffer g_sTxBuffer =
+{
+    true,                           // This is a transmit buffer.
+    TxHandler,                      // pfnCallback
+    (void *)&g_sCDCDevice,          // Callback data is our device pointer.
+    USBDCDCPacketWrite,             // pfnTransfer
+    USBDCDCTxPacketAvailable,       // pfnAvailable
+    (void *)&g_sCDCDevice,          // pvHandle
+    g_pcUSBTxBuffer,                // pcBuffer
+    UART_BUFFER_SIZE,               // ulBufferSize
+    g_pucTxBufferWorkspace          // pvWorkspace
+};
diff --git a/src/platform/lm3s/usb_serial_structs.h b/src/platform/lm3s/usb_serial_structs.h
new file mode 100755
index 00000000..6213dd4a
--- /dev/null
+++ b/src/platform/lm3s/usb_serial_structs.h
@@ -0,0 +1,49 @@
+//*****************************************************************************
+//
+// usb_serial_structs.h - Data structures defining this USB CDC device.
+//
+// Copyright (c) 2009-2011 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 7611 of the EK-LM3S9D92 Firmware Package.
+//
+//*****************************************************************************
+
+#ifndef __USB_SERIAL_STRUCTS_H__
+#define __USB_SERIAL_STRUCTS_H__
+
+//*****************************************************************************
+//
+// The size of the transmit and receive buffers used for the redirected UART.
+// This number should be a power of 2 for best performance.  256 is chosen
+// pretty much at random though the buffer should be at least twice the size of
+// a maxmum-sized USB packet.
+//
+//*****************************************************************************
+#define UART_BUFFER_SIZE 256
+
+extern unsigned long RxHandler(void *pvCBData, unsigned long ulEvent,
+                               unsigned long ulMsgValue, void *pvMsgData);
+extern unsigned long TxHandler(void *pvlCBData, unsigned long ulEvent,
+                               unsigned long ulMsgValue, void *pvMsgData);
+
+extern const tUSBBuffer g_sTxBuffer;
+extern const tUSBBuffer g_sRxBuffer;
+extern const tUSBDCDCDevice g_sCDCDevice;
+extern unsigned char g_pucUSBTxBuffer[];
+extern unsigned char g_pucUSBRxBuffer[];
+
+#endif // __USB_SERIAL_STRUCTS_H__
diff --git a/src/platform/lm3s/usblib/device/usbdaudio.c b/src/platform/lm3s/usblib/device/usbdaudio.c
new file mode 100755
index 00000000..9c855b7f
--- /dev/null
+++ b/src/platform/lm3s/usblib/device/usbdaudio.c
@@ -0,0 +1,1486 @@
+//*****************************************************************************
+//
+// usbdaudio.c - USB audio device class driver.
+//
+// Copyright (c) 2009-2011 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 7611 of the Stellaris USB Library.
+//
+//*****************************************************************************
+
+#include "inc/hw_memmap.h"
+#include "inc/hw_types.h"
+#include "driverlib/debug.h"
+#include "driverlib/rom.h"
+#include "driverlib/rom_map.h"
+#include "driverlib/usb.h"
+#include "driverlib/udma.h"
+#include "usblib/usblib.h"
+#include "usblib/usbaudio.h"
+#include "usblib/device/usbdevice.h"
+#include "usblib/device/usbdaudio.h"
+#include "usblib/usblibpriv.h"
+
+//*****************************************************************************
+//
+//! \addtogroup audio_device_class_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// The following are the USB audio descriptor identifiers.
+//
+//*****************************************************************************
+#define AUDIO_IN_TERMINAL_ID    1
+#define AUDIO_OUT_TERMINAL_ID   2
+#define AUDIO_CONTROL_ID        3
+
+//*****************************************************************************
+//
+// The following are the USB interface numbers for this audio device.
+//
+//*****************************************************************************
+#define AUDIO_INTERFACE_CONTROL 0
+#define AUDIO_INTERFACE_OUTPUT  1
+
+//*****************************************************************************
+//
+// Endpoints to use for each of the required endpoints in the driver.
+//
+//*****************************************************************************
+#define ISOC_OUT_ENDPOINT       USB_EP_1
+#define ISOC_OUT_DMA_CHANNEL    UDMA_CHANNEL_USBEP1RX
+
+//*****************************************************************************
+//
+// Max size is (48000 samples/sec * 4 bytes/sample) * 0.001 seconds/frame.
+//
+//*****************************************************************************
+#define ISOC_OUT_EP_MAX_SIZE    ((48000*4)/1000)
+
+//*****************************************************************************
+//
+// Device Descriptor.  This is stored in RAM to allow several fields to be
+// changed at runtime based on the client's requirements.
+//
+//*****************************************************************************
+static unsigned char g_pAudioDeviceDescriptor[] =
+{
+    18,                     // Size of this structure.
+    USB_DTYPE_DEVICE,       // Type of this structure.
+    USBShort(0x110),        // USB version 1.1 (if we say 2.0, hosts assume
+                            // high-speed - see USB 2.0 spec 9.2.6.6)
+    0,                      // USB Device Class (spec 5.1.1)
+    0,                      // USB Device Sub-class (spec 5.1.1)
+    0,                      // USB Device protocol (spec 5.1.1)
+    64,                     // Maximum packet size for default pipe.
+    USBShort(0),            // Vendor ID (filled in during USBDAudioInit).
+    USBShort(0),            // Product ID (filled in during USBDAudioInit).
+    USBShort(0x100),        // Device Version BCD.
+    1,                      // Manufacturer string identifier.
+    2,                      // Product string identifier.
+    3,                      // Product serial number.
+    1                       // Number of configurations.
+};
+
+//*****************************************************************************
+//
+// Audio class device configuration descriptor.
+//
+// It is vital that the configuration descriptor bConfigurationValue field
+// (byte 6) is 1 for the first configuration and increments by 1 for each
+// additional configuration defined here.  This relationship is assumed in the
+// device stack for simplicity even though the USB 2.0 specification imposes
+// no such restriction on the bConfigurationValue values.
+//
+// Note that this structure is deliberately located in RAM since we need to
+// be able to patch some values in it based on client requirements.
+//
+//*****************************************************************************
+static unsigned char g_pAudioDescriptor[] =
+{
+    //
+    // Configuration descriptor header.
+    //
+    9,                          // Size of the configuration descriptor.
+    USB_DTYPE_CONFIGURATION,    // Type of this descriptor.
+    USBShort(32),               // The total size of this full structure.
+    2,                          // The number of interfaces in this
+                                // configuration.
+    1,                          // The unique value for this configuration.
+    0,                          // The string identifier that describes this
+                                // configuration.
+    USB_CONF_ATTR_BUS_PWR,      // Bus Powered, Self Powered, remote wake up.
+    250,                        // The maximum power in 2mA increments.
+};
+
+//*****************************************************************************
+//
+// This is the Interface Association Descriptor for the serial device used in
+// composite devices.
+//
+//*****************************************************************************
+unsigned char g_pIADAudioDescriptor[] =
+{
+
+    8,                          // Size of the interface descriptor.
+    USB_DTYPE_INTERFACE_ASC,    // Interface Association Type.
+    0x0,                        // Default starting interface is 0.
+    0x2,                        // Number of interfaces in this association.
+    USB_CLASS_AUDIO,            // The device class for this association.
+    USB_SUBCLASS_UNDEFINED,     // The device subclass for this association.
+    USB_PROTOCOL_UNDEFINED,     // The protocol for this association.
+    0                           // The string index for this association.
+};
+
+const tConfigSection g_sIADAudioConfigSection =
+{
+    sizeof(g_pIADAudioDescriptor),
+    g_pIADAudioDescriptor
+};
+
+//*****************************************************************************
+//
+// The remainder of the configuration descriptor is stored in flash since we
+// don't need to modify anything in it at runtime.
+//
+//*****************************************************************************
+const unsigned char g_pAudioControlInterface[] =
+{
+    //
+    // Vendor-specific Interface Descriptor.
+    //
+    9,                          // Size of the interface descriptor.
+    USB_DTYPE_INTERFACE,        // Type of this descriptor.
+    AUDIO_INTERFACE_CONTROL,    // The index for this interface.
+    0,                          // The alternate setting for this interface.
+    0,                          // The number of endpoints used by this
+                                // interface.
+    USB_CLASS_AUDIO,            // The interface class
+    USB_ASC_AUDIO_CONTROL,      // The interface sub-class.
+    0,                          // The interface protocol for the sub-class
+                                // specified above.
+    0,                          // The string index for this interface.
+
+    //
+    // Audio Header Descriptor.
+    //
+    9,                          // The size of this descriptor.
+    USB_DTYPE_CS_INTERFACE,     // Interface descriptor is class specific.
+    USB_ACDSTYPE_HEADER,        // Descriptor sub-type is HEADER.
+    USBShort(0x0100),           // Audio Device Class Specification Release
+                                // Number in Binary-Coded Decimal.
+                                // Total number of bytes in
+                                // g_pAudioControlInterface
+    USBShort((9 + 9 + 12 + 13 + 9)),
+    1,                          // Number of streaming interfaces.
+    1,                          // Index of the first and only streaming
+                                // interface.
+
+    //
+    // Audio Input Terminal Descriptor.
+    //
+    12,                         // The size of this descriptor.
+    USB_DTYPE_CS_INTERFACE,     // Interface descriptor is class specific.
+    USB_ACDSTYPE_IN_TERMINAL,   // Descriptor sub-type is INPUT_TERMINAL.
+    AUDIO_IN_TERMINAL_ID,       // Terminal ID for this interface.
+                                // USB streaming interface.
+    USBShort(USB_TTYPE_STREAMING),
+    0,                          // ID of the Output Terminal to which this
+                                // Input Terminal is associated.
+    2,                          // Number of logical output channels in the
+                                // Terminal's output audio channel cluster.
+    USBShort((USB_CHANNEL_L |   // Describes the spatial location of the
+             USB_CHANNEL_R)),   // logical channels.
+    0,                          // Channel Name string index.
+    0,                          // Terminal Name string index.
+
+    //
+    // Audio Feature Unit Descriptor
+    //
+    13,                         // The size of this descriptor.
+    USB_DTYPE_CS_INTERFACE,     // Interface descriptor is class specific.
+    USB_ACDSTYPE_FEATURE_UNIT,  // Descriptor sub-type is FEATURE_UNIT.
+    AUDIO_CONTROL_ID,           // Unit ID for this interface.
+    AUDIO_IN_TERMINAL_ID,       // ID of the Unit or Terminal to which this
+                                // Feature Unit is connected.
+    2,                          // Size in bytes of an element of the
+                                // bmaControls() array that follows.
+                                // Master Mute control.
+    USBShort(USB_ACONTROL_MUTE),
+                                // Left channel volume control.
+    USBShort(USB_ACONTROL_VOLUME),
+                                // Right channel volume control.
+    USBShort(USB_ACONTROL_VOLUME),
+    0,                          // Feature unit string index.
+
+    //
+    // Audio Output Terminal Descriptor.
+    //
+    9,                          // The size of this descriptor.
+    USB_DTYPE_CS_INTERFACE,     // Interface descriptor is class specific.
+    USB_ACDSTYPE_OUT_TERMINAL,  // Descriptor sub-type is INPUT_TERMINAL.
+    AUDIO_OUT_TERMINAL_ID,      // Terminal ID for this interface.
+                                // Output type is a generic speaker.
+    USBShort(USB_ATTYPE_SPEAKER),
+    AUDIO_IN_TERMINAL_ID,       // ID of the input terminal to which this
+                                // output terminal is connected.
+    AUDIO_CONTROL_ID,           // ID of the feature unit that this output
+                                // terminal is connected to.
+    0,                          // Output terminal string index.
+
+};
+
+//*****************************************************************************
+//
+// The audio streaming interface descriptor.  This describes the two valid
+// interfaces for this class.  The first interface has no endpoints and is used
+// by host operating systems to put the device in idle mode, while the second
+// is used when the audio device is active.
+//
+//*****************************************************************************
+const unsigned char g_pAudioStreamInterface[] =
+{
+    //
+    // Vendor-specific Interface Descriptor.
+    //
+    9,                          // Size of the interface descriptor.
+    USB_DTYPE_INTERFACE,        // Type of this descriptor.
+    AUDIO_INTERFACE_OUTPUT,     // The index for this interface.
+    0,                          // The alternate setting for this interface.
+    0,                          // The number of endpoints used by this
+                                // interface.
+    USB_CLASS_AUDIO,            // The interface class
+    USB_ASC_AUDIO_STREAMING,    // The interface sub-class.
+    0,                          // Unused must be 0.
+    0,                          // The string index for this interface.
+
+    //
+    // Vendor-specific Interface Descriptor.
+    //
+    9,                          // Size of the interface descriptor.
+    USB_DTYPE_INTERFACE,        // Type of this descriptor.
+    1,                          // The index for this interface.
+    1,                          // The alternate setting for this interface.
+    1,                          // The number of endpoints used by this
+                                // interface.
+    USB_CLASS_AUDIO,            // The interface class
+    USB_ASC_AUDIO_STREAMING,    // The interface sub-class.
+    0,                          // Unused must be 0.
+    0,                          // The string index for this interface.
+
+    //
+    // Class specific Audio Streaming Interface descriptor.
+    //
+    7,                          // Size of the interface descriptor.
+    USB_DTYPE_CS_INTERFACE,     // Interface descriptor is class specific.
+    USB_ASDSTYPE_GENERAL,       // General information.
+    AUDIO_IN_TERMINAL_ID,       // ID of the terminal to which this streaming
+                                // interface is connected.
+    1,                          // One frame delay.
+    USBShort(USB_ADF_PCM),      //
+
+    //
+    // Format type Audio Streaming descriptor.
+    //
+    11,                         // Size of the interface descriptor.
+    USB_DTYPE_CS_INTERFACE,     // Interface descriptor is class specific.
+    USB_ASDSTYPE_FORMAT_TYPE,   // Audio Streaming format type.
+    USB_AF_TYPE_TYPE_I,         // Type I audio format type.
+    2,                          // Two audio channels.
+    2,                          // Two bytes per audio sub-frame.
+    16,                         // 16 bits per sample.
+    1,                          // One sample rate provided.
+    USB3Byte(48000),            // Only 48000 sample rate supported.
+
+    //
+    // Endpoint Descriptor
+    //
+    9,                              // The size of the endpoint descriptor.
+    USB_DTYPE_ENDPOINT,             // Descriptor type is an endpoint.
+                                    // OUT endpoint with address
+                                    // ISOC_OUT_ENDPOINT.
+    USB_EP_DESC_OUT | USB_EP_TO_INDEX(ISOC_OUT_ENDPOINT),
+    USB_EP_ATTR_ISOC |              // Endpoint is an adaptive isochronous data
+    USB_EP_ATTR_ISOC_ADAPT |        //  endpoint.
+    USB_EP_ATTR_USAGE_DATA,
+    USBShort(ISOC_OUT_EP_MAX_SIZE), // The maximum packet size.
+    1,                              // The polling interval for this endpoint.
+    0,                              // Refresh is unused.
+    0,                              // Synch endpoint address.
+
+    //
+    // Audio Streaming Isochronous Audio Data Endpoint Descriptor
+    //
+    7,                              // The size of the descriptor.
+    USB_ACSDT_ENDPOINT,             // Audio Class Specific Endpoint Descriptor.
+    USB_ASDSTYPE_GENERAL,           // This is a general descriptor.
+    USB_EP_ATTR_ACG_SAMPLING,       // Sampling frequency is supported.
+    USB_EP_LOCKDELAY_UNDEF,         // Undefined lock delay units.
+    USBShort(0),                    // No lock delay.
+};
+
+//*****************************************************************************
+//
+// The audio device configuration descriptor is defined as three sections,
+// one containing just the 9 byte USB configuration descriptor.  The second
+// holds the audio streaming interface and the third holds the audio control
+// interface.
+//
+//*****************************************************************************
+const tConfigSection g_sAudioConfigSection =
+{
+    sizeof(g_pAudioDescriptor),
+    g_pAudioDescriptor
+};
+
+const tConfigSection g_sAudioStreamInterfaceSection =
+{
+    sizeof(g_pAudioStreamInterface),
+    g_pAudioStreamInterface
+};
+
+const tConfigSection g_sAudioControlInterfaceSection =
+{
+    sizeof(g_pAudioControlInterface),
+    g_pAudioControlInterface
+};
+
+//*****************************************************************************
+//
+// This array lists all the sections that must be concatenated to make a
+// single, complete audio device configuration descriptor.
+//
+//*****************************************************************************
+const tConfigSection *g_psAudioSections[] =
+{
+    &g_sAudioConfigSection,
+    &g_sIADAudioConfigSection,
+    &g_sAudioControlInterfaceSection,
+    &g_sAudioStreamInterfaceSection
+};
+
+#define NUM_AUDIO_SECTIONS      (sizeof(g_psAudioSections) /                  \
+                                 sizeof(tConfigSection *))
+
+//*****************************************************************************
+//
+// The header for the single configuration we support.  This is the root of
+// the data structure that defines all the bits and pieces that are pulled
+// together to generate the configuration descriptor.
+//
+//*****************************************************************************
+const tConfigHeader g_sAudioConfigHeader =
+{
+    NUM_AUDIO_SECTIONS,
+    g_psAudioSections
+};
+
+//*****************************************************************************
+//
+// Configuration Descriptor.
+//
+//*****************************************************************************
+const tConfigHeader * const g_pAudioConfigDescriptors[] =
+{
+    &g_sAudioConfigHeader
+};
+
+//*****************************************************************************
+//
+// Various internal handlers needed by this class.
+//
+//*****************************************************************************
+static void HandleDisconnect(void *pvInstance);
+static void InterfaceChange(void *pvInstance, unsigned char ucInterface,
+                            unsigned char ucAlternateSetting);
+static void ConfigChangeHandler(void *pvInstance, unsigned long ulValue);
+static void DataReceived(void *pvInstance, unsigned long ulInfo);
+static void HandleEndpoints(void *pvInstance, unsigned long ulStatus);
+static void HandleRequests(void *pvInstance, tUSBRequest *pUSBRequest);
+static void HandleDevice(void *pvInstance, unsigned long ulRequest,
+                         void *pvRequestData);
+
+//*****************************************************************************
+//
+// The FIFO configuration for USB audio device class.
+//
+//*****************************************************************************
+const tFIFOConfig g_sUSBAudioFIFOConfig =
+{
+    //
+    // IN endpoints.
+    //
+    {
+        { 1, false, USB_EP_DEV_IN },
+        { 1, false, USB_EP_DEV_IN },
+        { 1, false, USB_EP_DEV_IN },
+        { 1, false, USB_EP_DEV_IN },
+        { 1, false, USB_EP_DEV_IN },
+        { 1, false, USB_EP_DEV_IN },
+        { 1, false, USB_EP_DEV_IN },
+        { 1, false, USB_EP_DEV_IN },
+        { 1, false, USB_EP_DEV_IN },
+        { 1, false, USB_EP_DEV_IN },
+        { 1, false, USB_EP_DEV_IN },
+        { 1, false, USB_EP_DEV_IN },
+        { 1, false, USB_EP_DEV_IN },
+        { 1, false, USB_EP_DEV_IN },
+        { 1, false, USB_EP_DEV_IN }
+    },
+
+    //
+    // OUT endpoints.
+    //
+    {
+        { 1, false, USB_EP_DEV_OUT | USB_EP_DMA_MODE_1 | USB_EP_AUTO_CLEAR },
+        { 1, false, USB_EP_DEV_OUT },
+        { 1, false, USB_EP_DEV_OUT },
+        { 1, false, USB_EP_DEV_OUT },
+        { 1, false, USB_EP_DEV_OUT },
+        { 1, false, USB_EP_DEV_OUT },
+        { 1, false, USB_EP_DEV_OUT },
+        { 1, false, USB_EP_DEV_OUT },
+        { 1, false, USB_EP_DEV_OUT },
+        { 1, false, USB_EP_DEV_OUT },
+        { 1, false, USB_EP_DEV_OUT },
+        { 1, false, USB_EP_DEV_OUT },
+        { 1, false, USB_EP_DEV_OUT },
+        { 1, false, USB_EP_DEV_OUT },
+        { 1, false, USB_EP_DEV_OUT }
+    },
+};
+
+//*****************************************************************************
+//
+// The device information structure for the USB Audio device.
+//
+//*****************************************************************************
+tDeviceInfo g_sAudioDeviceInfo =
+{
+    //
+    // Device event handler callbacks.
+    //
+    {
+        //
+        // GetDescriptor
+        //
+        0,
+
+        //
+        // RequestHandler
+        //
+        HandleRequests,
+
+        //
+        // InterfaceChange
+        //
+        InterfaceChange,
+
+        //
+        // ConfigChange
+        //
+        ConfigChangeHandler,
+
+        //
+        // DataReceived
+        //
+        DataReceived,
+
+        //
+        // DataSentCallback
+        //
+        0,
+
+        //
+        // ResetHandler
+        //
+        0,
+
+        //
+        // SuspendHandler
+        //
+        0,
+
+        //
+        // ResumeHandler
+        //
+        0,
+
+        //
+        // DisconnectHandler
+        //
+        HandleDisconnect,
+
+        //
+        // EndpointHandler
+        //
+        HandleEndpoints,
+
+        //
+        // Device handler
+        //
+        HandleDevice
+    },
+    g_pAudioDeviceDescriptor,
+    g_pAudioConfigDescriptors,
+    0,
+    0,
+    &g_sUSBAudioFIFOConfig
+};
+
+//*****************************************************************************
+//
+// This function is called to handle data being received back from the host so
+// that the application callback can be called when the new data is ready.
+//
+//*****************************************************************************
+static void
+DataReceived(void *pvInstance, unsigned long ulInfo)
+{
+    tAudioInstance *psInst;
+    const tUSBDAudioDevice *psDevice;
+
+    ASSERT(pvInstance != 0);
+
+    //
+    // Create the instance pointer.
+    //
+    psDevice = (const tUSBDAudioDevice *)pvInstance;
+
+    //
+    // Make a copy of this pointer for ease of use in this function.
+    //
+    psInst = psDevice->psPrivateData;
+
+    //
+    // If there is an update pending and the request was to set a current
+    // value then check which value was set.
+    //
+    if(psInst->usUpdate && (psInst->ucRequest == USB_AC_SET_CUR))
+    {
+        //
+        // Only handling interface requests.
+        //
+        if((psInst->usRequestType & USB_RTYPE_RECIPIENT_M) ==
+           USB_RTYPE_INTERFACE)
+        {
+            if(psInst->usUpdate == VOLUME_CONTROL)
+            {
+                //
+                // Inform the callback of the new volume.
+                //
+                psDevice->pfnCallback(0, USBD_AUDIO_EVENT_VOLUME,
+                                      psInst->sVolume, 0);
+            }
+            else if(psDevice->psPrivateData->usUpdate == MUTE_CONTROL)
+            {
+                //
+                // Inform the callback of the new data.
+                //
+                psDevice->pfnCallback(0, USBD_AUDIO_EVENT_MUTE, psInst->ucMute,
+                                      0);
+            }
+        }
+        psInst->usUpdate = 0;
+    }
+}
+
+//*****************************************************************************
+//
+// This function is called to handle the interrupts on the isochronous endpoint
+// for the audio device class.
+//
+//*****************************************************************************
+static void
+HandleEndpoints(void *pvInstance, unsigned long ulStatus)
+{
+    unsigned long ulEPStatus;
+    tAudioInstance *psInst;
+    unsigned char *pucData;
+    const tUSBDAudioDevice *psDevice;
+
+    ASSERT(pvInstance != 0);
+
+    //
+    // Create the instance pointer.
+    //
+    psDevice = (const tUSBDAudioDevice *)pvInstance;
+
+    //
+    // Make a copy of this pointer for ease of use later in this function.
+    //
+    psInst = psDevice->psPrivateData;
+
+    //
+    // Make sure this was for the isochronous out endpoint.
+    //
+    if((psInst->sBuffer.pvData != 0) &&
+       (MAP_uDMAChannelModeGet(psInst->ucOUTDMA) == UDMA_MODE_STOP))
+    {
+        //
+        // Save the pointer to the data buffer.
+        //
+        pucData = psInst->sBuffer.pvData;
+
+        //
+        // Clear out the buffer pointer to indicate it is no longer in use.
+        //
+        psInst->sBuffer.pvData = 0;
+
+        //
+        // Inform the callback of the new data.
+        //
+        psInst->sBuffer.pfnCallback(pucData, psInst->sBuffer.ulSize,
+                                    USBD_AUDIO_EVENT_DATAOUT);
+
+        //
+        // Read out the current endpoint status.
+        //
+        ulEPStatus = MAP_USBEndpointStatus(USB0_BASE, psInst->ucOUTEndpoint);
+
+        //
+        // Acknowledge that the data was read, this will not cause a bus
+        // acknowledgment.
+        //
+        MAP_USBDevEndpointDataAck(USB0_BASE, psInst->ucOUTEndpoint, 0);
+
+        //
+        // Clear the status bits.
+        //
+        MAP_USBDevEndpointStatusClear(USB0_BASE, psInst->ucOUTEndpoint,
+                                      ulEPStatus);
+    }
+}
+
+//*****************************************************************************
+//
+// Device instance specific handler.
+//
+//*****************************************************************************
+static void
+HandleDevice(void *pvInstance, unsigned long ulRequest, void *pvRequestData)
+{
+    tAudioInstance *psInst;
+    unsigned char *pucData;
+
+    //
+    // Create the serial instance data.
+    //
+    psInst = ((tUSBDAudioDevice *)pvInstance)->psPrivateData;
+
+    //
+    // Create the char array used by the events supported by the USB CDC
+    // serial class.
+    //
+    pucData = (unsigned char *)pvRequestData;
+
+    switch(ulRequest)
+    {
+        //
+        // This was an interface change event.
+        //
+        case USB_EVENT_COMP_IFACE_CHANGE:
+        {
+            //
+            // Save the change to the appropriate interface number.
+            //
+            if(pucData[0] == AUDIO_INTERFACE_CONTROL)
+            {
+                psInst->ucInterfaceControl = pucData[1];
+            }
+            else if(pucData[0] == AUDIO_INTERFACE_OUTPUT)
+            {
+                psInst->ucInterfaceAudio = pucData[1];
+            }
+            break;
+        }
+
+        //
+        // This was an endpoint change event.
+        //
+        case USB_EVENT_COMP_EP_CHANGE:
+        {
+            //
+            // Determine if this is an IN or OUT endpoint that has changed.
+            //
+            if((pucData[0] & USB_EP_DESC_IN) == 0)
+            {
+                //
+                // Extract the new endpoint number.
+                //
+                psInst->ucOUTEndpoint = INDEX_TO_USB_EP(pucData[1] & 0x7f);
+
+                //
+                // Extract the new DMA channel.
+                //
+                psInst->ucOUTDMA = UDMA_CHANNEL_USBEP1RX +
+                                   (((pucData[1] & 0x7f) - 1) * 2);
+
+                //
+                // Basic configuration for DMA on the OUT endpoint.
+                //
+                MAP_uDMAChannelControlSet(psInst->ucOUTDMA,
+                                          (UDMA_SIZE_32 | UDMA_SRC_INC_NONE|
+                                           UDMA_DST_INC_32 | UDMA_ARB_16));
+
+                //
+                // Select this channel for this endpoint, this only affects
+                // devices that have this feature.
+                //
+                MAP_USBEndpointDMAChannel(USB0_BASE, psInst->ucOUTEndpoint,
+                                          psInst->ucOUTDMA);
+            }
+            break;
+        }
+
+        //
+        // Handle class specific reconfiguring of the configuration descriptor
+        // once the composite class has built the full descriptor.
+        //
+        case USB_EVENT_COMP_CONFIG:
+        {
+            //
+            // This sets the bFirstInterface of the Interface Association
+            // descriptor to the first interface which is the control
+            // interface used by this instance.
+            //
+            pucData[2] = psInst->ucInterfaceControl;
+
+            break;
+        }
+
+        default:
+        {
+            break;
+        }
+    }
+}
+
+//*****************************************************************************
+//
+// This function is called by the USB device stack whenever the device is
+// disconnected from the host.
+//
+//*****************************************************************************
+static void
+HandleDisconnect(void *pvInstance)
+{
+    const tUSBDAudioDevice *psDevice;
+
+    ASSERT(pvInstance != 0);
+
+    //
+    // Create the instance pointer.
+    //
+    psDevice = (const tUSBDAudioDevice *)pvInstance;
+
+    //
+    // Inform the application that the device has been disconnected.
+    //
+    psDevice->pfnCallback(0, USB_EVENT_DISCONNECTED, 0, 0);
+}
+
+//*****************************************************************************
+//
+// This function is called by the USB device stack whenever the device
+// interface changes.  This occurs when the audio device transitions between
+// being active and inactive.  Interface AUDIO_INTERFACE_CONTROL is the
+// inactive interface that has no endpoints, while interface
+// AUDIO_INTERFACE_AUDIO has the single Isochronous OUT endpoint.
+//
+//*****************************************************************************
+static void
+InterfaceChange(void *pvInstance, unsigned char ucInterface,
+                unsigned char ucAlternateSetting)
+{
+    const tUSBDAudioDevice *psDevice;
+
+    ASSERT(pvInstance != 0);
+
+    //
+    // Create the instance pointer.
+    //
+    psDevice = (const tUSBDAudioDevice *)pvInstance;
+
+    //
+    // Check which interface to change into.
+    //
+    if(ucAlternateSetting == 0)
+    {
+        //
+        // Alternate setting 0 is an inactive state.
+        //
+        if(psDevice->pfnCallback)
+        {
+            psDevice->pfnCallback(0, USBD_AUDIO_EVENT_IDLE, 0, 0);
+        }
+    }
+    else
+    {
+        //
+        // Alternate setting 1 is the active state.
+        //
+        if(psDevice->pfnCallback)
+        {
+            psDevice->pfnCallback(0, USBD_AUDIO_EVENT_ACTIVE, 0, 0);
+        }
+
+        //
+        // Enable uDMA on the endpoint now that the active configuration
+        // has been selected.
+        //
+        MAP_USBEndpointDMAEnable(USB0_BASE,
+                                 psDevice->psPrivateData->ucOUTEndpoint,
+                                 USB_EP_DEV_OUT);
+    }
+}
+
+//*****************************************************************************
+//
+// This function is called by the USB device stack whenever the device
+// configuration changes.
+//
+//*****************************************************************************
+static void
+ConfigChangeHandler(void *pvInstance, unsigned long ulValue)
+{
+    const tUSBDAudioDevice *psDevice;
+
+    ASSERT(pvInstance != 0);
+
+    //
+    // Create the instance pointer.
+    //
+    psDevice = (const tUSBDAudioDevice *)pvInstance;
+
+    //
+    // If we have a control callback, let the client know we are open for
+    // business.
+    //
+    if(psDevice->pfnCallback)
+    {
+        //
+        // Pass the connected event to the client.
+        //
+        psDevice->pfnCallback(pvInstance, USB_EVENT_CONNECTED, 0, 0);
+    }
+}
+
+//*****************************************************************************
+//
+//! This function should be called once for the audio class device to
+//! initialized basic operation and prepare for enumeration.
+//!
+//! \param ulIndex is the index of the USB controller to initialize for
+//! audio class device operation.
+//! \param psDevice points to a structure containing parameters customizing
+//! the operation of the audio device.
+//!
+//! In order for an application to initialize the USB audio device class, it
+//! must first call this function with the a valid audio device class structure
+//! in the \e psDevice parameter.  This allows this function to initialize the
+//! USB controller and device code to be prepared to enumerate and function as
+//! a USB audio device.
+//!
+//! This function returns a void pointer that must be passed in to all other
+//! APIs used by the audio class.
+//!
+//! See the documentation on the tUSBDAudioDevice structure for more
+//! information on how to properly fill the structure members.
+//!
+//! \return Returns 0 on failure or a non-zero void pointer on success.
+//
+//*****************************************************************************
+void *
+USBDAudioInit(unsigned long ulIndex, const tUSBDAudioDevice *psDevice)
+{
+    //
+    // Check parameter validity.
+    //
+    ASSERT(ulIndex == 0);
+    ASSERT(psDevice);
+    ASSERT(psDevice->ppStringDescriptors);
+    ASSERT(psDevice->psPrivateData);
+
+    USBDAudioCompositeInit(ulIndex, psDevice);
+
+    //
+    // All is well so now pass the descriptors to the lower layer and put
+    // the bulk device on the bus.
+    //
+    USBDCDInit(ulIndex, psDevice->psPrivateData->psDevInfo);
+
+    //
+    // Basic configuration for DMA on the OUT endpoint.
+    //
+    MAP_uDMAChannelControlSet(psDevice->psPrivateData->ucOUTDMA,
+                              (UDMA_SIZE_32 | UDMA_SRC_INC_NONE|
+                               UDMA_DST_INC_32 | UDMA_ARB_16));
+
+    //
+    // Select this channel for this endpoint, this only affects devices that
+    // have this feature.
+    //
+    MAP_USBEndpointDMAChannel(USB0_BASE, psDevice->psPrivateData->ucOUTEndpoint,
+                              psDevice->psPrivateData->ucOUTDMA);
+
+    //
+    // Return the pointer to the instance indicating that everything went well.
+    //
+    return((void *)psDevice);
+}
+
+//*****************************************************************************
+//
+//! This function should be called once for the audio class device to
+//! initialized basic operation and prepare for enumeration.
+//!
+//! \param ulIndex is the index of the USB controller to initialize for
+//! audio class device operation.
+//! \param psDevice points to a structure containing parameters customizing
+//! the operation of the audio device.
+//!
+//! In order for an application to initialize the USB audio device class, it
+//! must first call this function with the a valid audio device class structure
+//! in the \e psDevice parameter.  This allows this function to initialize the
+//! USB controller and device code to be prepared to enumerate and function as
+//! a USB audio device.
+//!
+//! This function returns a void pointer that must be passed in to all other
+//! APIs used by the audio class.
+//!
+//! See the documentation on the tUSBDAudioDevice structure for more
+//! information on how to properly fill the structure members.
+//!
+//! \return Returns 0 on failure or a non-zero void pointer on success.
+//
+//*****************************************************************************
+void *
+USBDAudioCompositeInit(unsigned long ulIndex, const tUSBDAudioDevice *psDevice)
+{
+    tAudioInstance *psInst;
+    tDeviceDescriptor *psDevDesc;
+
+    //
+    // Check parameter validity.
+    //
+    ASSERT(ulIndex == 0);
+    ASSERT(psDevice);
+    ASSERT(psDevice->ppStringDescriptors);
+    ASSERT(psDevice->psPrivateData);
+
+    //
+    // Initialize the workspace in the passed instance structure.
+    //
+    psInst = psDevice->psPrivateData;
+    psInst->psConfDescriptor = (tConfigDescriptor *)g_pAudioDescriptor;
+    psInst->psDevInfo = &g_sAudioDeviceInfo;
+    psInst->ulUSBBase = USB0_BASE;
+
+    //
+    // The Control interface is at index 0.
+    //
+    psInst->ucInterfaceControl = AUDIO_INTERFACE_CONTROL;
+
+    //
+    // The Audio interface is at index 1.
+    //
+    psInst->ucInterfaceAudio = AUDIO_INTERFACE_OUTPUT;
+
+    //
+    // Set the default Isochronous OUT endpoint.
+    //
+    psInst->ucOUTEndpoint = ISOC_OUT_ENDPOINT;
+    psInst->ucOUTDMA = ISOC_OUT_DMA_CHANNEL;
+
+    //
+    // Set the initial buffer to null.
+    //
+    psInst->sBuffer.pvData = 0;
+
+    //
+    // Save the volume settings.
+    //
+    psInst->sVolumeMax = psDevice->sVolumeMax;
+    psInst->sVolumeMin = psDevice->sVolumeMin;
+    psInst->sVolumeStep = psDevice->sVolumeStep;
+
+    //
+    // No update pending to any command.
+    //
+    psInst->usUpdate = 0;
+
+    //
+    // Fix up the device descriptor with the client-supplied values.
+    //
+    psDevDesc = (tDeviceDescriptor *)psInst->psDevInfo->pDeviceDescriptor;
+    psDevDesc->idVendor = psDevice->usVID;
+    psDevDesc->idProduct = psDevice->usPID;
+    //
+    // Fix up the configuration descriptor with client-supplied values.
+    //
+    psInst->psConfDescriptor->bmAttributes = psDevice->ucPwrAttributes;
+    psInst->psConfDescriptor->bMaxPower =
+        (unsigned char)(psDevice->usMaxPowermA / 2);
+
+    //
+    // Plug in the client's string stable to the device information
+    // structure.
+    //
+    psInst->psDevInfo->ppStringDescriptors = psDevice->ppStringDescriptors;
+    psInst->psDevInfo->ulNumStringDescriptors =
+        psDevice->ulNumStringDescriptors;
+    psInst->psDevInfo->pvInstance = (void *)psDevice;
+
+    //
+    // Return the pointer to the instance indicating that everything went well.
+    //
+    return((void *)psDevice);
+}
+
+//*****************************************************************************
+//
+//! Shuts down the audio device.
+//!
+//! \param pvInstance is the pointer to the device instance structure as
+//! returned by USBDAudioInit().
+//!
+//! This function terminates audio interface for the instance supplied.  This
+//! function should not be called if the audio device is part of a composite
+//! device and instead the USBDCompositeTerm() function should be called for
+//! the full composite device.
+//! Following this call, the \e pvInstance instance should not me used in any
+//! other calls.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDAudioTerm(void *pvInstance)
+{
+    ASSERT(pvInstance != 0);
+
+    //
+    // Cleanly exit device mode.
+    //
+    USBDCDTerm(0);
+}
+
+//*****************************************************************************
+//
+// This function is called by the USB device stack whenever a non-standard
+// request is received.
+//
+// \param pvInstance is the instance data for this request.
+// \param pUSBRequest points to the request received.
+//
+// This call parses the provided request structure to the type of request and
+// will respond to all commands that are understood by the class.
+//
+// \return None.
+//
+//*****************************************************************************
+static void
+HandleRequests(void *pvInstance, tUSBRequest *pUSBRequest)
+{
+    unsigned long ulControl;
+    unsigned long ulRecipient;
+    unsigned long ulStall;
+    tAudioInstance *psInst;
+    const tUSBDAudioDevice *psDevice;
+
+    ASSERT(pvInstance != 0);
+
+    //
+    // Create the instance pointer.
+    //
+    psDevice = (const tUSBDAudioDevice *)pvInstance;
+
+    //
+    // Make a copy of this pointer for ease of use in this function.
+    //
+    psInst = psDevice->psPrivateData;
+
+    //
+    // Make sure to acknowledge that the data was read, this will not send and
+    // ACK that has already been done at this point.  This just tells the
+    // hardware that the data was read.
+    //
+    MAP_USBDevEndpointDataAck(USB0_BASE, USB_EP_0, false);
+
+    //
+    // Don't stall by default.
+    //
+    ulStall = 0;
+
+    //
+    // Get the request type.
+    //
+    ulRecipient = pUSBRequest->bmRequestType & USB_RTYPE_RECIPIENT_M;
+
+    //
+    // Save the request type and request value.
+    //
+    psInst->usRequestType = pUSBRequest->bmRequestType;
+    psInst->ucRequest = pUSBRequest->bRequest;
+
+    //
+    // Check if this is an endpoint request to the audio streaming endpoint.
+    //
+    if((ulRecipient == USB_RTYPE_ENDPOINT) &&
+       (pUSBRequest->wIndex == USB_EP_TO_INDEX(psInst->ucOUTEndpoint)))
+    {
+        //
+        // Determine the type of request.
+        //
+        switch(psInst->ucRequest)
+        {
+            case USB_AC_SET_CUR:
+            {
+                //
+                // Handle retrieving the sample rate.
+                //
+                if(pUSBRequest->wValue == SAMPLING_FREQ_CONTROL)
+                {
+                    //
+                    // Retrieve the requested sample rate.
+                    //
+                    USBDCDRequestDataEP0(0,
+                                         (unsigned char *)&psInst->ulSampleRate,
+                                         3);
+
+                    //
+                    // Save what we are updating.
+                    //
+                    psInst->usUpdate = SAMPLING_FREQ_CONTROL;
+                }
+                break;
+            }
+            case USB_AC_GET_CUR:
+            {
+                //
+                // Handle retrieving the sample rate.
+                //
+                if(pUSBRequest->wValue == SAMPLING_FREQ_CONTROL)
+                {
+                    //
+                    // Send back the current sample rate.
+                    //
+                    USBDCDSendDataEP0(0,
+                                      (unsigned char *)&psInst->ulSampleRate,
+                                      3);
+                }
+                break;
+            }
+            default:
+            {
+                //
+                // Stall on unknown commands.
+                //
+                ulStall = 1;
+                break;
+            }
+        }
+    }
+    else if(ulRecipient == USB_RTYPE_INTERFACE)
+    {
+        //
+        // Make sure the request was for the control interface.
+        //
+        if((unsigned char)pUSBRequest->wIndex != psInst->ucInterfaceControl)
+        {
+            return;
+        }
+
+        //
+        // Extract the control value from the message.
+        //
+        ulControl = pUSBRequest->wValue & USB_CS_CONTROL_M;
+
+        //
+        // Handle an audio control request to the feature control unit.
+        //
+        if((AUDIO_CONTROL_ID << 8) == (pUSBRequest->wIndex & USB_CS_CONTROL_M))
+        {
+            //
+            // Determine the type of request.
+            //
+            switch(psInst->ucRequest)
+            {
+                case USB_AC_GET_MAX:
+                {
+                    if(ulControl == VOLUME_CONTROL)
+                    {
+                        //
+                        // Return the maximum volume setting.
+                        //
+                        USBDCDSendDataEP0(0,
+                                          (unsigned char *)&psInst->sVolumeMax,
+                                          2);
+                    }
+                    else
+                    {
+                        //
+                        // Stall on unknown commands.
+                        //
+                        ulStall = 1;
+                    }
+                    break;
+                }
+                case USB_AC_GET_MIN:
+                {
+                    if(ulControl == VOLUME_CONTROL)
+                    {
+                        //
+                        // Return the minimum volume setting.
+                        //
+                        USBDCDSendDataEP0(0,
+                                          (unsigned char *)&psInst->sVolumeMin,
+                                          2);
+                    }
+                    else
+                    {
+                        //
+                        // Stall on unknown commands.
+                        //
+                        ulStall = 1;
+                    }
+                    break;
+                }
+                case USB_AC_GET_RES:
+                {
+                    if(ulControl == VOLUME_CONTROL)
+                    {
+                        //
+                        // Return the volume step setting.
+                        //
+                        USBDCDSendDataEP0(0,
+                                          (unsigned char *)&psInst->sVolumeStep,
+                                          2);
+                    }
+                    else
+                    {
+                        //
+                        // Stall on unknown commands.
+                        //
+                        ulStall = 1;
+                    }
+                    break;
+                }
+                case USB_AC_GET_CUR:
+                {
+                    if(ulControl == VOLUME_CONTROL)
+                    {
+                        //
+                        // Send back the current volume level.
+                        //
+                        USBDCDSendDataEP0(0,
+                                          (unsigned char *)&psInst->sVolume,
+                                          2);
+                    }
+                    else if(ulControl == MUTE_CONTROL)
+                    {
+                        //
+                        // Send back the current mute value.
+                        //
+                        USBDCDSendDataEP0(0,
+                                          (unsigned char *)&psInst->ucMute, 1);
+                    }
+                    else
+                    {
+                        //
+                        // Stall on unknown commands.
+                        //
+                        ulStall = 1;
+                    }
+                    break;
+                }
+                case USB_AC_SET_CUR:
+                {
+                    if(ulControl == VOLUME_CONTROL)
+                    {
+                        //
+                        // Read the new volume level.
+                        //
+                        USBDCDRequestDataEP0(0,
+                                             (unsigned char *)&psInst->sVolume,
+                                             2);
+
+                        //
+                        // Save what we are updating.
+                        //
+                        psInst->usUpdate = VOLUME_CONTROL;
+                    }
+                    else if(ulControl == MUTE_CONTROL)
+                    {
+                        //
+                        // Read the new mute setting.
+                        //
+                        USBDCDRequestDataEP0(0,
+                                             (unsigned char *)&psInst->ucMute,
+                                             1);
+
+                        //
+                        // Save what we are updating.
+                        //
+                        psInst->usUpdate = MUTE_CONTROL;
+                    }
+                    else
+                    {
+                        //
+                        // Stall on unknown commands.
+                        //
+                        ulStall = 1;
+                    }
+                    break;
+                }
+                case USB_AC_SET_RES:
+                {
+                    if(ulControl == VOLUME_CONTROL)
+                    {
+                        //
+                        // Read the new volume step setting.
+                        //
+                        USBDCDRequestDataEP0(0,
+                            (unsigned char *)&psInst->sVolumeStep, 2);
+
+                        //
+                        // Save what we are updating.
+                        //
+                        psInst->usUpdate = VOLUME_CONTROL;
+                    }
+                    else
+                    {
+                        //
+                        // Stall on unknown commands.
+                        //
+                        ulStall = 1;
+                    }
+                    break;
+                }
+                default:
+                {
+                    //
+                    // Stall on unknown commands.
+                    //
+                    ulStall = 1;
+                    break;
+                }
+            }
+        }
+    }
+
+    //
+    // Stall on all unknown commands.
+    //
+    if(ulStall)
+    {
+        USBDCDStallEP0(0);
+    }
+}
+
+//*****************************************************************************
+//
+//! This function is used to supply buffers to the audio class to be filled
+//! from the USB host device.
+//!
+//! \param pvInstance is the pointer to the device instance structure as
+//! returned by USBDAudioInit() or USBDAudioInitComposite().
+//! \param pvBuffer is a pointer to the buffer to fill with audio data.
+//! \param ulSize is the size in bytes of the buffer pointed to by the pvBuffer
+//! parameter.
+//! \param pfnCallback is a callback that will provide notification when this
+//! buffer has valid data.
+//!
+//! This function fills the buffer pointed to by the \e pvBuffer parameter with
+//! at most \e ulSize one packet of data from the host controller.  The ulSize
+//! has a minimum value of \b ISOC_OUT_EP_MAX_SIZE since each USB packet can be
+//! at most \b ISOC_OUT_EP_MAX_SIZE bytes in size.  Since the audio data may
+//! not be received in amounts that evenly fit in the buffer provided, the
+//! buffer may not be completely filled.  The \e pfnCallback function will
+//! provide the amount of valid data that was actually stored in the buffer
+//! provided.  The function will return zero if the buffer could be scheduled
+//! to be filled, otherwise the function will return a non-zero value if there
+//! was some reason that the buffer could not be added.
+//!
+//! \return Returns 0 to indicate success any other value indicates that the
+//! buffer will not be filled.
+//
+//*****************************************************************************
+long
+USBAudioBufferOut(void *pvInstance, void *pvBuffer, unsigned long ulSize,
+                  tUSBAudioBufferCallback pfnCallback)
+{
+    tAudioInstance *psInst;
+    const tUSBDAudioDevice *psDevice;
+
+    //
+    // Make sure we were not passed NULL pointers.
+    //
+    ASSERT(pvInstance != 0);
+    ASSERT(pvBuffer != 0);
+
+    //
+    // Create the instance pointer.
+    //
+    psDevice = (const tUSBDAudioDevice *)pvInstance;
+
+    //
+    // Buffer must be at least one packet in size.
+    //
+    ASSERT(ulSize >= ISOC_OUT_EP_MAX_SIZE);
+    ASSERT(pfnCallback);
+
+    //
+    // Create a pointer of the correct type from the private pointer.
+    //
+    psInst = psDevice->psPrivateData;
+
+    //
+    // Initialize the buffer instance.
+    //
+    psInst->sBuffer.pvData = pvBuffer;
+    psInst->sBuffer.ulSize = ulSize;
+    psInst->sBuffer.ulNumBytes = 0;
+    psInst->sBuffer.pfnCallback = pfnCallback;
+
+    //
+    // Configure and enable DMA for the OUT transfer.
+    //
+    MAP_uDMAChannelTransferSet(psInst->ucOUTDMA, UDMA_MODE_BASIC,
+                               (void *)USBFIFOAddrGet(USB0_BASE,
+                                                      psInst->ucOUTEndpoint),
+                               psInst->sBuffer.pvData, ulSize >> 2);
+
+    //
+    // Start the DMA transfer.
+    //
+    MAP_uDMAChannelEnable(psInst->ucOUTDMA);
+
+    return(0);
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
diff --git a/src/platform/lm3s/usblib/device/usbdaudio.h b/src/platform/lm3s/usblib/device/usbdaudio.h
new file mode 100755
index 00000000..3c8ece53
--- /dev/null
+++ b/src/platform/lm3s/usblib/device/usbdaudio.h
@@ -0,0 +1,362 @@
+//*****************************************************************************
+//
+// usbdaudio.h - USB audio device class driver.
+//
+// Copyright (c) 2009-2011 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 7611 of the Stellaris USB Library.
+//
+//*****************************************************************************
+
+#ifndef __USBDAUDIO_H__
+#define __USBDAUDIO_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+//! \addtogroup audio_device_class_api
+//! @{
+//
+//*****************************************************************************
+
+typedef void (* tUSBAudioBufferCallback)(void *pvBuffer, unsigned long ulParam,
+                                         unsigned long ulEvent);
+
+//*****************************************************************************
+//
+// PRIVATE
+//
+// This structure defines the private instance data and state variables for the
+// audio device class.  The memory for this structure is pointed to by
+// the psPrivateData field in the tUSBDAudioDevice structure passed on
+// USBDAudioInit() and should not be modified by any code outside of the audio
+// device.
+//
+//*****************************************************************************
+typedef struct
+{
+    unsigned long ulUSBBase;
+    tDeviceInfo *psDevInfo;
+    tConfigDescriptor *psConfDescriptor;
+
+    //
+    // The maximum volume expressed as an 8.8 signed value.
+    //
+    short sVolumeMax;
+
+    //
+    // The minimum volume expressed as an 8.8 signed value.
+    //
+    short sVolumeMin;
+
+    //
+    // The minimum volume step expressed as an 8.8 signed value.
+    //
+    short sVolumeStep;
+
+    struct
+    {
+        //
+        // Pointer to a buffer provided by caller.
+        //
+        void *pvData;
+
+        //
+        // Size of the data area provided in pvData in bytes.
+        //
+        unsigned long ulSize;
+
+        //
+        // Number of valid bytes copied into the pvData area.
+        //
+        unsigned long ulNumBytes;
+
+        //
+        // The buffer callback for this function.
+        //
+        tUSBAudioBufferCallback pfnCallback;
+    } sBuffer;
+
+    //
+    // Pending request type.
+    //
+    unsigned short usRequestType;
+
+    //
+    // Pending request.
+    //
+    unsigned char ucRequest;
+
+    //
+    // Pending update value.
+    //
+    unsigned short usUpdate;
+
+    //
+    // Current Volume setting.
+    //
+    short sVolume;
+
+    //
+    // Current Mute setting.
+    //
+    unsigned char ucMute;
+
+    //
+    // Current Sample rate, this is not writable but the host will try.
+    //
+    unsigned long ulSampleRate;
+
+    //
+    // The OUT endpoint in use by this instance.
+    //
+    unsigned char ucOUTEndpoint;
+
+    //
+    // The OUT endpoint DMA channel in use by this instance.
+    //
+    unsigned char ucOUTDMA;
+
+    //
+    // The control interface number associated with this instance.
+    //
+    unsigned char ucInterfaceControl;
+
+    //
+    // The audio interface number associated with this instance.
+    //
+    unsigned char ucInterfaceAudio;
+}
+tAudioInstance;
+
+//*****************************************************************************
+//
+//! This is the size in bytes of the private data for the device audio class.
+//
+//*****************************************************************************
+#define USB_AUDIO_INSTANCE_SIZE sizeof(tAudioInstance);
+
+//*****************************************************************************
+//
+//! The size of the memory that should be allocated to create a configuration
+//! descriptor for a single instance of the USB Audio Device.
+//! This does not include the configuration descriptor which is automatically
+//! ignored by the composite device class.
+//
+// This value must be at least sizeof(g_pIADAudioDescriptor) +
+// sizeof(g_pAudioControlInterface) +
+// sizeof(g_sAudioStreamInterfaceSection)
+//
+//*****************************************************************************
+#define COMPOSITE_DAUDIO_SIZE   (8 + 52 + 52)
+
+//*****************************************************************************
+//
+//! The structure used by the application to define operating parameters for
+//! the device audio class.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! The vendor ID that this device is to present in the device descriptor.
+    //
+    unsigned short usVID;
+
+    //
+    //! The product ID that this device is to present in the device descriptor.
+    //
+    unsigned short usPID;
+
+    //
+    //! 8 byte vendor string.
+    //
+    unsigned char pucVendor[8];
+
+    //
+    //! 16 byte vendor string.
+    //
+    unsigned char pucProduct[16];
+
+    //
+    //! 4 byte vendor string.
+    //
+    unsigned char pucVersion[4];
+
+    //
+    //! The maximum power consumption of the device, expressed in mA.
+    //
+    unsigned short usMaxPowermA;
+
+    //
+    //! Indicates whether the device is self or bus-powered and whether or not
+    //! it supports remote wake up.  Valid values are USB_CONF_ATTR_SELF_PWR or
+    //! USB_CONF_ATTR_BUS_PWR, optionally ORed with USB_CONF_ATTR_RWAKE.
+    //
+    unsigned char ucPwrAttributes;
+
+    //
+    //! A pointer to the callback function which will be called to notify
+    //! the application of events relating to the operation of the audio
+    //! device.
+    //
+    tUSBCallback pfnCallback;
+
+    //
+    //! A pointer to the string descriptor array for this device.  This array
+    //! must contain the following string descriptor pointers in this order.
+    //! Language descriptor, Manufacturer name string (language 1), Product
+    //! name string (language 1), Serial number string (language 1), Audio
+    //! Interface description string (language 1), Configuration description
+    //! string (language 1).
+    //!
+    //! If supporting more than 1 language, the descriptor block (except for
+    //! string descriptor 0) must be repeated for each language defined in the
+    //! language descriptor.
+    //!
+    //
+    const unsigned char * const *ppStringDescriptors;
+
+    //
+    //! The number of descriptors provided in the ppStringDescriptors
+    //! array.  This must be 1 + ((5 + (number of strings)) *
+    //!                           (number of languages)).
+    //
+    unsigned long ulNumStringDescriptors;
+
+    //
+    //! The maximum volume expressed as an 8.8 signed value.
+    //
+    short sVolumeMax;
+
+    //
+    //! The minimum volume expressed as an 8.8 signed value.
+    //
+    short sVolumeMin;
+
+    //
+    //! The minimum volume step expressed as an 8.8 signed value.
+    //
+    short sVolumeStep;
+
+    //
+    //! A pointer to private instance data for the audio device.  This memory
+    //! must remain accessible for as long as the audio device is in use and
+    //! must not be modified by any code outside the audio class driver.
+    //
+    tAudioInstance *psPrivateData;
+}
+tUSBDAudioDevice;
+
+//*****************************************************************************
+//
+// Audio specific device class driver events
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! This USB audio event indicates that the device is connected but not active.
+//
+//*****************************************************************************
+#define USBD_AUDIO_EVENT_IDLE   (USBD_AUDIO_EVENT_BASE + 0)
+
+//*****************************************************************************
+//
+//! This USB audio event indicates that the device is connected and is now
+//! active.
+//
+//*****************************************************************************
+#define USBD_AUDIO_EVENT_ACTIVE (USBD_AUDIO_EVENT_BASE + 1)
+
+//*****************************************************************************
+//
+//! This USB audio event indicates that the device is returning a data buffer
+//! provided by the USBAudioBufferOut() function back to the application with
+//! valid audio data received from the USB host controller. The \e pvBuffer
+//! parameter holds the pointer to the buffer with the new audio data and
+//! the \e ulParam value holds the amount of valid data in bytes that are
+//! contained in the \e pvBuffer parameter.
+//
+//*****************************************************************************
+#define USBD_AUDIO_EVENT_DATAOUT (USBD_AUDIO_EVENT_BASE + 2)
+
+//*****************************************************************************
+//
+//! This USB audio event indicates that a volume change has occured.  The
+//! \e ulParam value contains a signed 8.8 fixed point value that represents
+//! the current volume gain/attenuation in decibels(dB).  The provided message
+//! handler should be prepared to handle negative and positive values with the
+//! value 0x8000 indicating maximum attenuation.  The \e pvBuffer parameter
+//! should be ignored.
+//
+//*****************************************************************************
+#define USBD_AUDIO_EVENT_VOLUME (USBD_AUDIO_EVENT_BASE + 4)
+
+//*****************************************************************************
+//
+//! This USB audio event indicates that a mute request has occured.  The
+//! \e ulParam value will either be a 1 to indicate that the audio is now
+//! muted, and a value of 0 indicates that the audio has been unmuted.
+//
+//*****************************************************************************
+#define USBD_AUDIO_EVENT_MUTE   (USBD_AUDIO_EVENT_BASE + 5)
+
+extern tDeviceInfo g_sAudioDeviceInfo;
+
+//*****************************************************************************
+//
+// API Function Prototypes
+//
+//*****************************************************************************
+extern void *USBDAudioInit(unsigned long ulIndex,
+                           const tUSBDAudioDevice *psAudioDevice);
+extern void *USBDAudioCompositeInit(unsigned long ulIndex,
+                                    const tUSBDAudioDevice *psAudioDevice);
+extern void USBDAudioTerm(void *pvInstance);
+extern long USBAudioBufferOut(void *pvInstance, void *pvBuffer,
+                              unsigned long ulSize,
+                              tUSBAudioBufferCallback pfnCallback);
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
diff --git a/src/platform/lm3s/usblib/device/usbdbulk.c b/src/platform/lm3s/usblib/device/usbdbulk.c
new file mode 100755
index 00000000..cd94cfb3
--- /dev/null
+++ b/src/platform/lm3s/usblib/device/usbdbulk.c
@@ -0,0 +1,1448 @@
+//*****************************************************************************
+//
+// usbdbulk.c - USB bulk device class driver.
+//
+// Copyright (c) 2008-2011 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 7611 of the Stellaris USB Library.
+//
+//*****************************************************************************
+
+#include "inc/hw_memmap.h"
+#include "inc/hw_types.h"
+#include "driverlib/debug.h"
+#include "driverlib/rom.h"
+#include "driverlib/rom_map.h"
+#include "driverlib/usb.h"
+#include "usblib/usblib.h"
+#include "usblib/device/usbdevice.h"
+#include "usblib/device/usbdbulk.h"
+#include "usblib/usblibpriv.h"
+
+//*****************************************************************************
+//
+//! \addtogroup bulk_device_class_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// The subset of endpoint status flags that we consider to be reception
+// errors.  These are passed to the client via USB_EVENT_ERROR if seen.
+//
+//*****************************************************************************
+#define USB_RX_ERROR_FLAGS      (USBERR_DEV_RX_DATA_ERROR |                   \
+                                 USBERR_DEV_RX_OVERRUN |                      \
+                                 USBERR_DEV_RX_FIFO_FULL)
+
+//*****************************************************************************
+//
+// Flags that may appear in usDeferredOpFlags to indicate some operation that
+// has been requested but could not be processed at the time it was received.
+// Each deferred operation is defined as the bit number that should be set in
+// tBulkInstance->usDeferredOpFlags to indicate that the operation is pending.
+//
+//*****************************************************************************
+#define BULK_DO_PACKET_RX           5
+
+//*****************************************************************************
+//
+// Macros to convert between USB controller base address and an index.  These
+// are currently trivial but are included to allow for the possibility of
+// supporting more than one controller in the future.
+//
+//*****************************************************************************
+#define USB_BASE_TO_INDEX(BaseAddr) (0)
+#define USB_INDEX_TO_BASE(Index) (USB0_BASE)
+
+//*****************************************************************************
+//
+// Endpoints to use for each of the required endpoints in the driver.
+//
+//*****************************************************************************
+#define DATA_IN_ENDPOINT        USB_EP_1
+#define DATA_OUT_ENDPOINT       USB_EP_1
+
+//*****************************************************************************
+//
+// Maximum packet size for the bulk endpoints used for serial data
+// transmission and reception and the associated FIFO sizes to set aside
+// for each endpoint.
+//
+//*****************************************************************************
+#define DATA_IN_EP_FIFO_SIZE    USB_FIFO_SZ_64
+#define DATA_OUT_EP_FIFO_SIZE   USB_FIFO_SZ_64
+
+#define DATA_IN_EP_MAX_SIZE     USB_FIFO_SZ_TO_BYTES(DATA_IN_EP_FIFO_SIZE)
+#define DATA_OUT_EP_MAX_SIZE    USB_FIFO_SZ_TO_BYTES(DATA_IN_EP_FIFO_SIZE)
+
+//*****************************************************************************
+//
+// Device Descriptor.  This is stored in RAM to allow several fields to be
+// changed at runtime based on the client's requirements.
+//
+//*****************************************************************************
+unsigned char g_pBulkDeviceDescriptor[] =
+{
+    18,                         // Size of this structure.
+    USB_DTYPE_DEVICE,           // Type of this structure.
+    USBShort(0x110),            // USB version 1.1 (if we say 2.0, hosts assume
+                                // high-speed - see USB 2.0 spec 9.2.6.6)
+    USB_CLASS_VEND_SPECIFIC,    // USB Device Class
+    0,                          // USB Device Sub-class
+    0,                          // USB Device protocol
+    64,                         // Maximum packet size for default pipe.
+    USBShort(0),                // Vendor ID (VID).
+    USBShort(0),                // Product ID (PID).
+    USBShort(0x100),            // Device Version BCD.
+    1,                          // Manufacturer string identifier.
+    2,                          // Product string identifier.
+    3,                          // Product serial number.
+    1                           // Number of configurations.
+};
+
+//*****************************************************************************
+//
+// Bulk device configuration descriptor.
+//
+// It is vital that the configuration descriptor bConfigurationValue field
+// (byte 6) is 1 for the first configuration and increments by 1 for each
+// additional configuration defined here.  This relationship is assumed in the
+// device stack for simplicity even though the USB 2.0 specification imposes
+// no such restriction on the bConfigurationValue values.
+//
+// Note that this structure is deliberately located in RAM since we need to
+// be able to patch some values in it based on client requirements.
+//
+//*****************************************************************************
+unsigned char g_pBulkDescriptor[] =
+{
+    //
+    // Configuration descriptor header.
+    //
+    9,                          // Size of the configuration descriptor.
+    USB_DTYPE_CONFIGURATION,    // Type of this descriptor.
+    USBShort(32),               // The total size of this full structure.
+    1,                          // The number of interfaces in this
+                                // configuration.
+    1,                          // The unique value for this configuration.
+    5,                          // The string identifier that describes this
+                                // configuration.
+    USB_CONF_ATTR_SELF_PWR,     // Bus Powered, Self Powered, remote wake up.
+    250,                        // The maximum power in 2mA increments.
+};
+
+//*****************************************************************************
+//
+// The remainder of the configuration descriptor is stored in flash since we
+// don't need to modify anything in it at runtime.
+//
+//*****************************************************************************
+const unsigned char g_pBulkInterface[] =
+{
+    //
+    // Vendor-specific Interface Descriptor.
+    //
+    9,                          // Size of the interface descriptor.
+    USB_DTYPE_INTERFACE,        // Type of this descriptor.
+    0,                          // The index for this interface.
+    0,                          // The alternate setting for this interface.
+    2,                          // The number of endpoints used by this
+                                // interface.
+    USB_CLASS_VEND_SPECIFIC,    // The interface class
+    0,                          // The interface sub-class.
+    0,                          // The interface protocol for the sub-class
+                                // specified above.
+    4,                          // The string index for this interface.
+
+    //
+    // Endpoint Descriptor
+    //
+    7,                               // The size of the endpoint descriptor.
+    USB_DTYPE_ENDPOINT,              // Descriptor type is an endpoint.
+    USB_EP_DESC_IN | USB_EP_TO_INDEX(DATA_IN_ENDPOINT),
+    USB_EP_ATTR_BULK,                // Endpoint is a bulk endpoint.
+    USBShort(DATA_IN_EP_MAX_SIZE),   // The maximum packet size.
+    0,                               // The polling interval for this endpoint.
+
+    //
+    // Endpoint Descriptor
+    //
+    7,                               // The size of the endpoint descriptor.
+    USB_DTYPE_ENDPOINT,              // Descriptor type is an endpoint.
+    USB_EP_DESC_OUT | USB_EP_TO_INDEX(DATA_OUT_ENDPOINT),
+    USB_EP_ATTR_BULK,                // Endpoint is a bulk endpoint.
+    USBShort(DATA_OUT_EP_MAX_SIZE),  // The maximum packet size.
+    0,                               // The polling interval for this endpoint.
+};
+
+//*****************************************************************************
+//
+// The serial config descriptor is defined as two sections, one containing
+// just the 9 byte USB configuration descriptor and the other containing
+// everything else that is sent to the host along with it.
+//
+//*****************************************************************************
+const tConfigSection g_sBulkConfigSection =
+{
+    sizeof(g_pBulkDescriptor),
+    g_pBulkDescriptor
+};
+
+const tConfigSection g_sBulkInterfaceSection =
+{
+    sizeof(g_pBulkInterface),
+    g_pBulkInterface
+};
+
+//*****************************************************************************
+//
+// This array lists all the sections that must be concatenated to make a
+// single, complete bulk device configuration descriptor.
+//
+//*****************************************************************************
+const tConfigSection *g_psBulkSections[] =
+{
+    &g_sBulkConfigSection,
+    &g_sBulkInterfaceSection
+};
+
+#define NUM_BULK_SECTIONS (sizeof(g_psBulkSections) /                         \
+                           sizeof(tConfigSection *))
+
+//*****************************************************************************
+//
+// The header for the single configuration we support.  This is the root of
+// the data structure that defines all the bits and pieces that are pulled
+// together to generate the configuration descriptor.
+//
+//*****************************************************************************
+const tConfigHeader g_sBulkConfigHeader =
+{
+    NUM_BULK_SECTIONS,
+    g_psBulkSections
+};
+
+//*****************************************************************************
+//
+// Configuration Descriptor.
+//
+//*****************************************************************************
+const tConfigHeader * const g_pBulkConfigDescriptors[] =
+{
+    &g_sBulkConfigHeader
+};
+
+//*****************************************************************************
+//
+// Forward references for device handler callbacks
+//
+//*****************************************************************************
+static void HandleConfigChange(void *pvInstance, unsigned long ulInfo);
+static void HandleDisconnect(void *pvInstance);
+static void HandleEndpoints(void *pvInstance, unsigned long ulStatus);
+static void HandleSuspend(void *pvInstance);
+static void HandleResume(void *pvInstance);
+static void HandleDevice(void *pvInstance, unsigned long ulRequest,
+                         void *pvRequestData);
+
+//*****************************************************************************
+//
+// The device information structure for the USB serial device.
+//
+//*****************************************************************************
+tDeviceInfo g_sBulkDeviceInfo =
+{
+    //
+    // Device event handler callbacks.
+    //
+    {
+        0,                     // GetDescriptor
+        0,                     // RequestHandler
+        0,                     // InterfaceChange
+        HandleConfigChange,    // ConfigChange
+        0,                     // DataReceived
+        0,                     // DataSentCallback
+        0,                     // ResetHandler
+        HandleSuspend,         // SuspendHandler
+        HandleResume,          // ResumeHandler
+        HandleDisconnect,      // DisconnectHandler
+        HandleEndpoints,       // EndpointHandler
+        HandleDevice           // Device handler.
+    },
+    g_pBulkDeviceDescriptor,
+    g_pBulkConfigDescriptors,
+    0,                         // Will be completed during USBDBulkInit().
+    0,                         // Will be completed during USBDBulkInit().
+    &g_sUSBDefaultFIFOConfig
+};
+
+//*****************************************************************************
+//
+// Set or clear deferred operation flags in an "atomic" manner.
+//
+// \param pusDeferredOp points to the flags variable which is to be modified.
+// \param usBit indicates which bit number is to be set or cleared.
+// \param bSet indicates the state that the flag must be set to.  If \b true,
+// the flag is set, if \b false, the flag is cleared.
+//
+// This function safely sets or clears a bit in a flag variable.  The operation
+// makes use of bitbanding to ensure that the operation is atomic (no read-
+// modify-write is required).
+//
+// \return None.
+//
+//*****************************************************************************
+static void
+SetDeferredOpFlag(volatile unsigned short *pusDeferredOp, unsigned short usBit,
+                  tBoolean bSet)
+{
+    //
+    // Set the flag bit to 1 or 0 using a bitband access.
+    //
+    HWREGBITH(pusDeferredOp, usBit) = bSet ? 1 : 0;
+}
+
+//*****************************************************************************
+//
+// Receives notifications related to data received from the host.
+//
+// \param psDevice is the device instance whose endpoint is to be processed.
+// \param ulStatus is the USB interrupt status that caused this function to
+// be called.
+//
+// This function is called from HandleEndpoints for all interrupts signaling
+// the arrival of data on the bulk OUT endpoint (in other words, whenever the
+// host has sent us a packet of data).  We inform the client that a packet
+// is available and, on return, check to see if the packet has been read.  If
+// not, we schedule another notification to the client for a later time.
+//
+// \return Returns \b true on success or \b false on failure.
+//
+//*****************************************************************************
+static tBoolean
+ProcessDataFromHost(const tUSBDBulkDevice *psDevice, unsigned long ulStatus)
+{
+    unsigned long ulEPStatus;
+    unsigned long ulSize;
+    tBulkInstance *psInst;
+
+    //
+    // Get a pointer to our instance data.
+    //
+    psInst = psDevice->psPrivateBulkData;
+
+    //
+    // Get the endpoint status to see why we were called.
+    //
+    ulEPStatus = MAP_USBEndpointStatus(USB0_BASE, psInst->ucOUTEndpoint);
+
+    //
+    // Clear the status bits.
+    //
+    MAP_USBDevEndpointStatusClear(USB0_BASE, psInst->ucOUTEndpoint, ulEPStatus);
+
+    //
+    // Has a packet been received?
+    //
+    if(ulEPStatus & USB_DEV_RX_PKT_RDY)
+    {
+        //
+        // Set the flag we use to indicate that a packet read is pending.  This
+        // will be cleared if the packet is read.  If the client doesn't read
+        // the packet in the context of the USB_EVENT_RX_AVAILABLE callback,
+        // the event will be signaled later during tick processing.
+        //
+        SetDeferredOpFlag(&psInst->usDeferredOpFlags, BULK_DO_PACKET_RX, true);
+
+        //
+        // How big is the packet we've just been sent?
+        //
+        ulSize = MAP_USBEndpointDataAvail(psInst->ulUSBBase,
+                                          psInst->ucOUTEndpoint);
+
+        //
+        // The receive channel is not blocked so let the caller know
+        // that a packet is waiting.  The parameters are set to indicate
+        // that the packet has not been read from the hardware FIFO yet.
+        //
+        psDevice->pfnRxCallback(psDevice->pvRxCBData,
+                                USB_EVENT_RX_AVAILABLE, ulSize,
+                                (void *)0);
+    }
+    else
+    {
+        //
+        // No packet was received.  Some error must have been reported.  Check
+        // and pass this on to the client if necessary.
+        //
+        if(ulEPStatus & USB_RX_ERROR_FLAGS)
+        {
+            //
+            // This is an error we report to the client so...
+            //
+            psDevice->pfnRxCallback(psDevice->pvRxCBData,
+                                    USB_EVENT_ERROR,
+                                    (ulEPStatus & USB_RX_ERROR_FLAGS),
+                                    (void *)0);
+        }
+        return(false);
+    }
+
+    return(true);
+}
+
+//*****************************************************************************
+//
+// Receives notifications related to data sent to the host.
+//
+// \param psDevice is the device instance whose endpoint is to be processed.
+// \param ulStatus is the USB interrupt status that caused this function to
+// be called.
+//
+// This function is called from HandleEndpoints for all interrupts originating
+// from the bulk IN endpoint (in other words, whenever data has been
+// transmitted to the USB host).  We examine the cause of the interrupt and,
+// if due to completion of a transmission, notify the client.
+//
+// \return Returns \b true on success or \b false on failure.
+//
+//*****************************************************************************
+static tBoolean
+ProcessDataToHost(const tUSBDBulkDevice *psDevice, unsigned long ulStatus)
+{
+    tBulkInstance *psInst;
+    unsigned long ulEPStatus;
+    unsigned long ulSize;
+
+    //
+    // Get a pointer to our instance data.
+    //
+    psInst = psDevice->psPrivateBulkData;
+
+    //
+    // Get the endpoint status to see why we were called.
+    //
+    ulEPStatus = MAP_USBEndpointStatus(psInst->ulUSBBase, psInst->ucINEndpoint);
+
+    //
+    // Clear the status bits.
+    //
+    MAP_USBDevEndpointStatusClear(psInst->ulUSBBase, psInst->ucINEndpoint,
+                                  ulEPStatus);
+
+    //
+    // Our last transmission completed.  Clear our state back to idle and
+    // see if we need to send any more data.
+    //
+    psInst->eBulkTxState = BULK_STATE_IDLE;
+
+    //
+    // Notify the client that the last transmission completed.
+    //
+    ulSize = psInst->usLastTxSize;
+    psInst->usLastTxSize = 0;
+    psDevice->pfnTxCallback(psDevice->pvTxCBData, USB_EVENT_TX_COMPLETE,
+                            ulSize, (void *)0);
+
+    return(true);
+}
+
+//*****************************************************************************
+//
+// Called by the USB stack for any activity involving one of our endpoints
+// other than EP0.  This function is a fan out that merely directs the call to
+// the correct handler depending upon the endpoint and transaction direction
+// signaled in ulStatus.
+//
+//*****************************************************************************
+static void
+HandleEndpoints(void *pvInstance, unsigned long ulStatus)
+{
+    const tUSBDBulkDevice *psBulkInst;
+    tBulkInstance *psInst;
+
+    ASSERT(pvInstance != 0);
+
+    //
+    // Determine if the serial device is in single or composite mode because
+    // the meaning of ulIndex is different in both cases.
+    //
+    psBulkInst = (const tUSBDBulkDevice *)pvInstance;
+    psInst = psBulkInst->psPrivateBulkData;
+
+    //
+    // Handler for the bulk OUT data endpoint.
+    //
+    if(ulStatus & (0x10000 << USB_EP_TO_INDEX(psInst->ucOUTEndpoint)))
+    {
+        //
+        // Data is being sent to us from the host.
+        //
+        ProcessDataFromHost(pvInstance, ulStatus);
+    }
+
+    //
+    // Handler for the bulk IN data endpoint.
+    //
+    if(ulStatus & (1 << USB_EP_TO_INDEX(psInst->ucINEndpoint)))
+    {
+        ProcessDataToHost(pvInstance, ulStatus);
+    }
+}
+
+//*****************************************************************************
+//
+// Called by the USB stack whenever a configuration change occurs.
+//
+//*****************************************************************************
+static void
+HandleConfigChange(void *pvInstance, unsigned long ulInfo)
+{
+    tBulkInstance *psInst;
+    const tUSBDBulkDevice *psDevice;
+
+    ASSERT(pvInstance != 0);
+
+    //
+    // Create a device instance pointer.
+    //
+    psDevice = (const tUSBDBulkDevice *)pvInstance;
+
+    //
+    // Get a pointer to our instance data.
+    //
+    psInst = psDevice->psPrivateBulkData;
+
+    //
+    // Set all our endpoints to idle state.
+    //
+    psInst->eBulkRxState = BULK_STATE_IDLE;
+    psInst->eBulkTxState = BULK_STATE_IDLE;
+
+    //
+    // If we have a control callback, let the client know we are open for
+    // business.
+    //
+    if(psDevice->pfnRxCallback)
+    {
+        //
+        // Pass the connected event to the client.
+        //
+        psDevice->pfnRxCallback(psDevice->pvRxCBData, USB_EVENT_CONNECTED, 0,
+                                (void *)0);
+    }
+
+    //
+    // Remember that we are connected.
+    //
+    psInst->bConnected = true;
+}
+
+//*****************************************************************************
+//
+// Device instance specific handler.
+//
+//*****************************************************************************
+static void
+HandleDevice(void *pvInstance, unsigned long ulRequest, void *pvRequestData)
+{
+    tBulkInstance *psInst;
+    unsigned char *pucData;
+
+    //
+    // Create the serial instance data.
+    //
+    psInst = ((tUSBDBulkDevice *)pvInstance)->psPrivateBulkData;
+
+    //
+    // Create the char array used by the events supported by the USB CDC
+    // serial class.
+    //
+    pucData = (unsigned char *)pvRequestData;
+
+    switch(ulRequest)
+    {
+        //
+        // This was an interface change event.
+        //
+        case USB_EVENT_COMP_IFACE_CHANGE:
+        {
+            psInst->ucInterface = pucData[1];
+            break;
+        }
+
+        //
+        // This was an endpoint change event.
+        //
+        case USB_EVENT_COMP_EP_CHANGE:
+        {
+            //
+            // Determine if this is an IN or OUT endpoint that has changed.
+            //
+            if(pucData[0] & USB_EP_DESC_IN)
+            {
+                psInst->ucINEndpoint = INDEX_TO_USB_EP((pucData[1] & 0x7f));
+            }
+            else
+            {
+                //
+                // Extract the new endpoint number.
+                //
+                psInst->ucOUTEndpoint = INDEX_TO_USB_EP(pucData[1] & 0x7f);
+            }
+            break;
+        }
+        default:
+        {
+            break;
+        }
+    }
+}
+
+//*****************************************************************************
+//
+// This function is called by the USB device stack whenever the device is
+// disconnected from the host.
+//
+//*****************************************************************************
+static void
+HandleDisconnect(void *pvInstance)
+{
+    const tUSBDBulkDevice *psBulkDevice;
+    tBulkInstance *psInst;
+
+    ASSERT(pvInstance != 0);
+
+    //
+    // Create the instance pointer.
+    //
+    psBulkDevice = (const tUSBDBulkDevice *)pvInstance;
+
+    //
+    // Get a pointer to our instance data.
+    //
+    psInst = psBulkDevice->psPrivateBulkData;
+
+    //
+    // If we are not currently connected so let the client know we are open
+    // for business.
+    //
+    if(psInst->bConnected)
+    {
+        //
+        // Pass the disconnected event to the client.
+        //
+        psBulkDevice->pfnRxCallback(psBulkDevice->pvRxCBData,
+                                    USB_EVENT_DISCONNECTED, 0, (void *)0);
+    }
+
+    //
+    // Remember that we are no longer connected.
+    //
+    psInst->bConnected = false;
+}
+
+//*****************************************************************************
+//
+// This function is called by the USB device stack whenever the bus is put into
+// suspend state.
+//
+//*****************************************************************************
+static void
+HandleSuspend(void *pvInstance)
+{
+    const tUSBDBulkDevice *psBulkDevice;
+
+    ASSERT(pvInstance != 0);
+
+    //
+    // Create the instance pointer.
+    //
+    psBulkDevice = (const tUSBDBulkDevice *)pvInstance;
+
+    //
+    // Pass the event on to the client.
+    //
+    psBulkDevice->pfnRxCallback(psBulkDevice->pvRxCBData, USB_EVENT_SUSPEND, 0,
+                                (void *)0);
+}
+
+//*****************************************************************************
+//
+// This function is called by the USB device stack whenever the bus is taken
+// out of suspend state.
+//
+//*****************************************************************************
+static void
+HandleResume(void *pvInstance)
+{
+    const tUSBDBulkDevice *psBulkDevice;
+
+    ASSERT(pvInstance != 0);
+
+    //
+    // Create the instance pointer.
+    //
+    psBulkDevice = (const tUSBDBulkDevice *)pvInstance;
+
+    //
+    // Pass the event on to the client.
+    //
+    psBulkDevice->pfnRxCallback(psBulkDevice->pvRxCBData, USB_EVENT_RESUME, 0,
+                                (void *)0);
+}
+
+//*****************************************************************************
+//
+// This function is called periodically and provides us with a time reference
+// and method of implementing delayed or time-dependent operations.
+//
+// \param ulIndex is the index of the USB controller for which this tick
+// is being generated.
+// \param ulTimemS is the elapsed time in milliseconds since the last call
+// to this function.
+//
+// \return None.
+//
+//*****************************************************************************
+static void
+BulkTickHandler(void *pvInstance, unsigned long ulTimemS)
+{
+    tBulkInstance *psInst;
+    unsigned long ulSize;
+    const tUSBDBulkDevice *psDevice;
+
+    ASSERT(pvInstance != 0);
+
+    //
+    // Create the instance pointer.
+    //
+    psDevice = (const tUSBDBulkDevice *)pvInstance;
+
+    //
+    // Get our instance data pointer.
+    //
+    psInst = psDevice->psPrivateBulkData;
+
+    //
+    // Do we have a deferred receive waiting
+    //
+    if(psInst->usDeferredOpFlags & (1 << BULK_DO_PACKET_RX))
+    {
+        //
+        // Yes - how big is the waiting packet?
+        //
+        ulSize = MAP_USBEndpointDataAvail(psInst->ulUSBBase,
+                                          psInst->ucOUTEndpoint);
+
+        //
+        // Tell the client that there is a packet waiting for it.
+        //
+        psDevice->pfnRxCallback(psDevice->pvRxCBData, USB_EVENT_RX_AVAILABLE,
+                                ulSize, (void *)0);
+    }
+
+    return;
+}
+
+//*****************************************************************************
+//
+//! Initializes bulk device operation for a given USB controller.
+//!
+//! \param ulIndex is the index of the USB controller which is to be
+//! initialized for bulk device operation.
+//! \param psDevice points to a structure containing parameters customizing
+//! the operation of the bulk device.
+//!
+//! An application wishing to make use of a USB bulk communication channel
+//! must call this function to initialize the USB controller and attach the
+//! device to the USB bus.  This function performs all required USB
+//! initialization.
+//!
+//! On successful completion, this function will return the \e psDevice pointer
+//! passed to it.  This must be passed on all future calls to the device driver
+//! related to this device.
+//!
+//! The USBDBulk interface offers packet-based transmit and receive operation.
+//! If the application would rather use block based communication with
+//! transmit and receive buffers, USB buffers may be used above the bulk
+//! transmit and receive channels to offer this functionality.
+//!
+//! Transmit Operation:
+//!
+//! Calls to USBDBulkPacketWrite must send no more than 64 bytes of data at a
+//! time and may only be made when no other transmission is currently
+//! outstanding.
+//!
+//! Once a packet of data has been acknowledged by the USB host, a
+//! USB_EVENT_TX_COMPLETE event is sent to the application callback to inform
+//! it that another packet may be transmitted.
+//!
+//! Receive Operation:
+//!
+//! An incoming USB data packet will result in a call to the application
+//! callback with event USBD_EVENT_RX_AVAILABLE.  The application must then
+//! call USBDBulkPacketRead(), passing a buffer capable of holding 64 bytes, to
+//! retrieve the data and acknowledge reception to the USB host.
+//!
+//! \note The application must not make any calls to the low level USB Device
+//! API if interacting with USB via the USB bulk device class API.  Doing so
+//! will cause unpredictable (though almost certainly unpleasant) behavior.
+//!
+//! \return Returns NULL on failure or the psDevice pointer on success.
+//
+//*****************************************************************************
+void *
+USBDBulkInit(unsigned long ulIndex, const tUSBDBulkDevice *psDevice)
+{
+    void *pvInstance;
+
+    //
+    // Check parameter validity.
+    //
+    ASSERT(ulIndex == 0);
+    ASSERT(psDevice);
+
+    pvInstance = USBDBulkCompositeInit(ulIndex, psDevice);
+
+    if(pvInstance)
+    {
+        //
+        // All is well so now pass the descriptors to the lower layer and put
+        // the bulk device on the bus.
+        //
+        USBDCDInit(ulIndex, psDevice->psPrivateBulkData->psDevInfo);
+    }
+
+    //
+    // Return the pointer to the instance indicating that everything went well.
+    //
+    return(pvInstance);
+}
+
+//*****************************************************************************
+//
+//! Initializes bulk device operation for a given USB controller.
+//!
+//! \param ulIndex is the index of the USB controller which is to be
+//! initialized for bulk device operation.
+//! \param psDevice points to a structure containing parameters customizing
+//! the operation of the bulk device.
+//!
+//! This call is very similar to USBDBulkInit() except that it is used for
+//! initializing an instance of the bulk device for use in a composite device.
+//!
+//! \return Returns zero on failure or a non-zero value that should be
+//! used with the remaining USB HID Bulk APIs.
+//
+//*****************************************************************************
+void *
+USBDBulkCompositeInit(unsigned long ulIndex, const tUSBDBulkDevice *psDevice)
+{
+    tBulkInstance *psInst;
+    tDeviceDescriptor *psDevDesc;
+
+    //
+    // Check parameter validity.
+    //
+    ASSERT(ulIndex == 0);
+    ASSERT(psDevice);
+    ASSERT(psDevice->ppStringDescriptors);
+    ASSERT(psDevice->psPrivateBulkData);
+    ASSERT(psDevice->pfnRxCallback);
+    ASSERT(psDevice->pfnTxCallback);
+
+    //
+    // Initialize the workspace in the passed instance structure.
+    //
+    psInst = psDevice->psPrivateBulkData;
+    psInst->psConfDescriptor = (tConfigDescriptor *)g_pBulkDescriptor;
+    psInst->psDevInfo = &g_sBulkDeviceInfo;
+    psInst->ulUSBBase = USB0_BASE;
+    psInst->eBulkRxState = BULK_STATE_UNCONFIGURED;
+    psInst->eBulkTxState = BULK_STATE_UNCONFIGURED;
+    psInst->usDeferredOpFlags = 0;
+    psInst->bConnected = false;
+
+    //
+    // Set the default endpoint and interface assignments.
+    //
+    psInst->ucINEndpoint = DATA_IN_ENDPOINT;
+    psInst->ucOUTEndpoint = DATA_OUT_ENDPOINT;
+    psInst->ucInterface = 0;
+
+    //
+    // Fix up the device descriptor with the client-supplied values.
+    //
+    psDevDesc = (tDeviceDescriptor *)psInst->psDevInfo->pDeviceDescriptor;
+    psDevDesc->idVendor = psDevice->usVID;
+    psDevDesc->idProduct = psDevice->usPID;
+
+    //
+    // Fix up the configuration descriptor with client-supplied values.
+    //
+    psInst->psConfDescriptor->bmAttributes = psDevice->ucPwrAttributes;
+    psInst->psConfDescriptor->bMaxPower =
+                        (unsigned char)(psDevice->usMaxPowermA / 2);
+
+    //
+    // Plug in the client's string stable to the device information
+    // structure.
+    //
+    psInst->psDevInfo->ppStringDescriptors = psDevice->ppStringDescriptors;
+    psInst->psDevInfo->ulNumStringDescriptors
+            = psDevice->ulNumStringDescriptors;
+
+    //
+    // Set the device instance.
+    //
+    psInst->psDevInfo->pvInstance = (void *)psDevice;
+
+    //
+    // Initialize the USB tick module, this will prevent it from being
+    // initialized later in the call to USBDCDInit();
+    //
+    InternalUSBTickInit();
+
+    //
+    // Register our tick handler (this must be done after USBDCDInit).
+    //
+    InternalUSBRegisterTickHandler(USB_TICK_HANDLER_DEVICE,
+                                   BulkTickHandler,
+                                   (void *)psDevice);
+
+    //
+    // Return the pointer to the instance indicating that everything went well.
+    //
+    return((void *)psDevice);
+}
+
+//*****************************************************************************
+//
+//! Shut down the bulk device.
+//!
+//! \param pvInstance is the pointer to the device instance structure as
+//! returned by USBDBulkInit().
+//!
+//! This function terminates device operation for the instance supplied and
+//! removes the device from the USB bus.  This function should not be called
+//! if the bulk device is part of a composite device and instead the
+//! USBDCompositeTerm() function should be called for the full composite
+//! device.
+//!
+//! Following this call, the \e pvInstance instance should not me used in any
+//! other calls.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDBulkTerm(void *pvInstance)
+{
+    tBulkInstance *psInst;
+
+    ASSERT(pvInstance);
+
+    //
+    // Get a pointer to our instance data.
+    //
+    psInst = ((tUSBDBulkDevice *)pvInstance)->psPrivateBulkData;
+
+    //
+    // Terminate the requested instance.
+    //
+    USBDCDTerm(USB_BASE_TO_INDEX(psInst->ulUSBBase));
+
+    psInst->ulUSBBase = 0;
+    psInst->psDevInfo = (tDeviceInfo *)0;
+    psInst->psConfDescriptor = (tConfigDescriptor *)0;
+
+    return;
+}
+
+//*****************************************************************************
+//
+//! Sets the client-specific pointer parameter for the receive channel
+//! callback.
+//!
+//! \param pvInstance is the pointer to the device instance structure as
+//! returned by USBDBulkInit().
+//! \param pvCBData is the pointer that client wishes to be provided on each
+//! event sent to the receive channel callback function.
+//!
+//! The client uses this function to change the callback pointer passed in
+//! the first parameter on all callbacks to the \e pfnRxCallback function
+//! passed on USBDBulkInit().
+//!
+//! If a client wants to make runtime changes in the callback pointer, it must
+//! ensure that the \e pvInstance structure passed to USBDBulkInit() resides in
+//! RAM.  If this structure is in flash, callback pointer changes will not be
+//! possible.
+//!
+//! \return Returns the previous callback pointer that was being used for
+//! this instance's receive callback.
+//
+//*****************************************************************************
+void *
+USBDBulkSetRxCBData(void *pvInstance, void *pvCBData)
+{
+    void *pvOldValue;
+
+    ASSERT(pvInstance);
+
+    //
+    // Set the callback data for the receive channel after remembering the
+    // previous value.
+    //
+    pvOldValue = ((tUSBDBulkDevice *)pvInstance)->pvRxCBData;
+    ((tUSBDBulkDevice *)pvInstance)->pvRxCBData = pvCBData;
+
+    //
+    // Return the previous callback pointer.
+    //
+    return(pvOldValue);
+}
+
+//*****************************************************************************
+//
+//! Sets the client-specific pointer parameter for the transmit callback.
+//!
+//! \param pvInstance is the pointer to the device instance structure as
+//! returned by USBDBulkInit().
+//! \param pvCBData is the pointer that client wishes to be provided on each
+//! event sent to the transmit channel callback function.
+//!
+//! The client uses this function to change the callback pointer passed in
+//! the first parameter on all callbacks to the \e pfnTxCallback function
+//! passed on USBDBulkInit().
+//!
+//! If a client wants to make runtime changes in the callback pointer, it must
+//! ensure that the \e pvInstance structure passed to USBDBulkInit() resides in
+//! RAM.  If this structure is in flash, callback pointer changes will not be
+//! possible.
+//!
+//! \return Returns the previous callback pointer that was being used for
+//! this instance's transmit callback.
+//
+//*****************************************************************************
+void *
+USBDBulkSetTxCBData(void *pvInstance, void *pvCBData)
+{
+    void *pvOldValue;
+
+    ASSERT(pvInstance);
+
+    //
+    // Set the callback pointer for the transmit channel after remembering the
+    // previous value.
+    //
+    pvOldValue = ((tUSBDBulkDevice *)pvInstance)->pvTxCBData;
+    ((tUSBDBulkDevice *)pvInstance)->pvTxCBData = pvCBData;
+
+    //
+    // Return the previous callback pointer value.
+    //
+    return(pvOldValue);
+}
+
+//*****************************************************************************
+//
+//! Transmits a packet of data to the USB host via the bulk data interface.
+//!
+//! \param pvInstance is the pointer to the device instance structure as
+//! returned by USBDBulkInit().
+//! \param pcData points to the first byte of data which is to be transmitted.
+//! \param ulLength is the number of bytes of data to transmit.
+//! \param bLast indicates whether more data is to be written before a packet
+//! should be scheduled for transmission.  If \b true, the client will make
+//! a further call to this function.  If \b false, no further call will be
+//! made and the driver should schedule transmission of a short packet.
+//!
+//! This function schedules the supplied data for transmission to the USB
+//! host in a single USB packet.  If no transmission is currently ongoing,
+//! the data is immediately copied to the relevant USB endpoint FIFO for
+//! transmission.  Whenever a USB packet is acknowledged by the host, a
+//! USB_EVENT_TX_COMPLETE event will be sent to the transmit channel callback
+//! indicating that more data can now be transmitted.
+//!
+//! The maximum value for \e ulLength is 64 bytes (the maximum USB packet size
+//! for the bulk endpoints in use by the device).  Attempts to send more data
+//! than this will result in a return code of 0 indicating that the data cannot
+//! be sent.
+//!
+//! The \e bLast parameter allows a client to make multiple calls to this
+//! function before scheduling transmission of the packet to the host.  This
+//! can be helpful if, for example, constructing a packet on the fly or
+//! writing a packet which spans the wrap point in a ring buffer.
+//!
+//! \return Returns the number of bytes actually sent.  At this level, this
+//! will either be the number of bytes passed (if less than or equal to the
+//! maximum packet size for the USB endpoint in use and no outstanding
+//! transmission ongoing) or 0 to indicate a failure.
+//
+//*****************************************************************************
+unsigned long
+USBDBulkPacketWrite(void *pvInstance, unsigned char *pcData,
+                    unsigned long ulLength, tBoolean bLast)
+{
+    tBulkInstance *psInst;
+    long lRetcode;
+
+    ASSERT(pvInstance);
+
+    //
+    // Get our instance data pointer
+    //
+    psInst = ((tUSBDBulkDevice *)pvInstance)->psPrivateBulkData;
+
+    //
+    // Can we send the data provided?
+    //
+    if((ulLength > DATA_IN_EP_MAX_SIZE) ||
+       (psInst->eBulkTxState != BULK_STATE_IDLE))
+    {
+        //
+        // Either the packet was too big or we are in the middle of sending
+        // another packet.  Return 0 to indicate that we can't send this data.
+        //
+        return(0);
+    }
+
+    //
+    // Copy the data into the USB endpoint FIFO.
+    //
+    lRetcode = MAP_USBEndpointDataPut(psInst->ulUSBBase, psInst->ucINEndpoint,
+                                      pcData, ulLength);
+
+    //
+    // Did we copy the data successfully?
+    //
+    if(lRetcode != -1)
+    {
+        //
+        // Remember how many bytes we sent.
+        //
+        psInst->usLastTxSize += (unsigned short)ulLength;
+
+        //
+        // If this is the last call for this packet, schedule transmission.
+        //
+        if(bLast)
+        {
+            //
+            // Send the packet to the host if we have received all the data we
+            // can expect for this packet.
+            //
+            psInst->eBulkTxState = BULK_STATE_WAIT_DATA;
+            lRetcode = MAP_USBEndpointDataSend(psInst->ulUSBBase,
+                                               psInst->ucINEndpoint,
+                                               USB_TRANS_IN);
+        }
+    }
+
+    //
+    // Did an error occur while trying to send the data?
+    //
+    if(lRetcode != -1)
+    {
+        //
+        // No - tell the caller we sent all the bytes provided.
+        //
+        return(ulLength);
+    }
+    else
+    {
+        //
+        // Yes - tell the caller we couldn't send the data.
+        //
+        return(0);
+    }
+}
+
+//*****************************************************************************
+//
+//! Reads a packet of data received from the USB host via the bulk data
+//! interface.
+//!
+//! \param pvInstance is the pointer to the device instance structure as
+//! returned by USBDBulkInit().
+//! \param pcData points to a buffer into which the received data will be
+//! written.
+//! \param ulLength is the size of the buffer pointed to by pcData.
+//! \param bLast indicates whether the client will make a further call to
+//! read additional data from the packet.
+//!
+//! This function reads up to \e ulLength bytes of data received from the USB
+//! host into the supplied application buffer.  If the driver detects that the
+//! entire packet has been read, it is acknowledged to the host.
+//!
+//! The \e bLast parameter is ignored in this implementation since the end of
+//! a packet can be determined without relying upon the client to provide
+//! this information.
+//!
+//! \return Returns the number of bytes of data read.
+//
+//*****************************************************************************
+unsigned long
+USBDBulkPacketRead(void *pvInstance, unsigned char *pcData,
+                   unsigned long ulLength, tBoolean bLast)
+{
+    unsigned long ulEPStatus, ulCount, ulPkt;
+    tBulkInstance *psInst;
+    long lRetcode;
+
+    ASSERT(pvInstance);
+
+    //
+    // Get our instance data pointer
+    //
+    psInst = ((tUSBDBulkDevice *)pvInstance)->psPrivateBulkData;
+
+    //
+    // Does the relevant endpoint FIFO have a packet waiting for us?
+    //
+    ulEPStatus = MAP_USBEndpointStatus(psInst->ulUSBBase,
+                                       psInst->ucOUTEndpoint);
+
+    if(ulEPStatus & USB_DEV_RX_PKT_RDY)
+    {
+        //
+        // How many bytes are available for us to receive?
+        //
+        ulPkt = MAP_USBEndpointDataAvail(psInst->ulUSBBase,
+                                         psInst->ucOUTEndpoint);
+
+        //
+        // Get as much data as we can.
+        //
+        ulCount = ulLength;
+        lRetcode = MAP_USBEndpointDataGet(psInst->ulUSBBase,
+                                          psInst->ucOUTEndpoint,
+                                          pcData, &ulCount);
+
+        //
+        // Did we read the last of the packet data?
+        //
+        if(ulCount == ulPkt)
+        {
+            //
+            // Clear the endpoint status so that we know no packet is
+            // waiting.
+            //
+            MAP_USBDevEndpointStatusClear(psInst->ulUSBBase,
+                                          psInst->ucOUTEndpoint,
+                                          ulEPStatus);
+
+            //
+            // Acknowledge the data, thus freeing the host to send the
+            // next packet.
+            //
+            MAP_USBDevEndpointDataAck(psInst->ulUSBBase, psInst->ucOUTEndpoint,
+                                      true);
+
+            //
+            // Clear the flag we set to indicate that a packet read is
+            // pending.
+            //
+            SetDeferredOpFlag(&psInst->usDeferredOpFlags, BULK_DO_PACKET_RX,
+                              false);
+        }
+
+        //
+        // If all went well, tell the caller how many bytes they got.
+        //
+        if(lRetcode != -1)
+        {
+            return(ulCount);
+        }
+    }
+
+    //
+    // No packet was available or an error occurred while reading so tell
+    // the caller no bytes were returned.
+    //
+    return(0);
+}
+
+//*****************************************************************************
+//
+//! Returns the number of free bytes in the transmit buffer.
+//!
+//! \param pvInstance is the pointer to the device instance structure as
+//! returned by USBDBulkInit().
+//!
+//! This function returns the maximum number of bytes that can be passed on a
+//! call to USBDBulkPacketWrite and accepted for transmission.  The value
+//! returned will be the maximum USB packet size (64) if no transmission is
+//! currently outstanding or 0 if a transmission is in progress.
+//!
+//! \return Returns the number of bytes available in the transmit buffer.
+//
+//*****************************************************************************
+unsigned long
+USBDBulkTxPacketAvailable(void *pvInstance)
+{
+    tBulkInstance *psInst;
+
+    ASSERT(pvInstance);
+
+    //
+    // Get our instance data pointer.
+    //
+    psInst = ((tUSBDBulkDevice *)pvInstance)->psPrivateBulkData;
+
+    //
+    // Do we have a packet transmission currently ongoing?
+    //
+    if(psInst->eBulkTxState != BULK_STATE_IDLE)
+    {
+        //
+        // We are not ready to receive a new packet so return 0.
+        //
+        return(0);
+    }
+    else
+    {
+        //
+        // We can receive a packet so return the max packet size for the
+        // relevant endpoint.
+        //
+        return(DATA_IN_EP_MAX_SIZE);
+    }
+}
+
+//*****************************************************************************
+//
+//! Determines whether a packet is available and, if so, the size of the
+//! buffer required to read it.
+//!
+//! \param pvInstance is the pointer to the device instance structure as
+//! returned by USBDBulkInit().
+//!
+//! This function may be used to determine if a received packet remains to be
+//! read and allows the application to determine the buffer size needed to
+//! read the data.
+//!
+//! \return Returns 0 if no received packet remains unprocessed or the
+//! size of the packet if a packet is waiting to be read.
+//
+//*****************************************************************************
+unsigned long
+USBDBulkRxPacketAvailable(void *pvInstance)
+{
+    unsigned long ulEPStatus;
+    unsigned long ulSize;
+    tBulkInstance *psInst;
+
+    ASSERT(pvInstance);
+
+    //
+    // Get our instance data pointer
+    //
+    psInst = ((tUSBDBulkDevice *)pvInstance)->psPrivateBulkData;
+
+    //
+    // Does the relevant endpoint FIFO have a packet waiting for us?
+    //
+    ulEPStatus = MAP_USBEndpointStatus(psInst->ulUSBBase,
+                                       psInst->ucOUTEndpoint);
+
+    if(ulEPStatus & USB_DEV_RX_PKT_RDY)
+    {
+        //
+        // Yes - a packet is waiting.  How big is it?
+        //
+        ulSize = MAP_USBEndpointDataAvail(psInst->ulUSBBase,
+                                          psInst->ucOUTEndpoint);
+
+        return(ulSize);
+    }
+    else
+    {
+        //
+        // There is no packet waiting to be received.
+        //
+        return(0);
+    }
+}
+
+//*****************************************************************************
+//
+//! Reports the device power status (bus- or self-powered) to the USB library.
+//!
+//! \param pvInstance is the pointer to the bulk device instance structure.
+//! \param ucPower indicates the current power status, either \b
+//! USB_STATUS_SELF_PWR or \b USB_STATUS_BUS_PWR.
+//!
+//! Applications which support switching between bus- or self-powered
+//! operation should call this function whenever the power source changes
+//! to indicate the current power status to the USB library.  This information
+//! is required by the USB library to allow correct responses to be provided
+//! when the host requests status from the device.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDBulkPowerStatusSet(void *pvInstance, unsigned char ucPower)
+{
+    ASSERT(pvInstance);
+
+    //
+    // Pass the request through to the lower layer.
+    //
+    USBDCDPowerStatusSet(0, ucPower);
+}
+
+//*****************************************************************************
+//
+//! Requests a remote wake up to resume communication when in suspended state.
+//!
+//! \param pvInstance is the pointer to the bulk device instance structure.
+//!
+//! When the bus is suspended, an application which supports remote wake up
+//! (advertised to the host via the configuration descriptor) may call this function
+//! to initiate remote wake up signaling to the host.  If the remote wake up
+//! feature has not been disabled by the host, this will cause the bus to
+//! resume operation within 20mS.  If the host has disabled remote wake up,
+//! \b false will be returned to indicate that the wake up request was not
+//! successful.
+//!
+//! \return Returns \b true if the remote wake up is not disabled and the
+//! signaling was started or \b false if remote wake up is disabled or if
+//! signaling is currently ongoing following a previous call to this function.
+//
+//*****************************************************************************
+tBoolean
+USBDBulkRemoteWakeupRequest(void *pvInstance)
+{
+    ASSERT(pvInstance);
+
+    //
+    // Pass the request through to the lower layer.
+    //
+    return(USBDCDRemoteWakeupRequest(0));
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/src/platform/lm3s/usblib/device/usbdbulk.h b/src/platform/lm3s/usblib/device/usbdbulk.h
new file mode 100755
index 00000000..9c7526b6
--- /dev/null
+++ b/src/platform/lm3s/usblib/device/usbdbulk.h
@@ -0,0 +1,269 @@
+//*****************************************************************************
+//
+// usbdcdc.h - USBLib support for a generic bulk device.
+//
+// Copyright (c) 2008-2011 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 7611 of the Stellaris USB Library.
+//
+//*****************************************************************************
+
+#ifndef __USBDBULK_H__
+#define __USBDBULK_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+//! \addtogroup bulk_device_class_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// PRIVATE
+//
+// The first few sections of this header are private defines that are used by
+// the USB Bulk example code and are here only to help with the application
+// allocating the correct amount of memory for the Bulk example device code.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// PRIVATE
+//
+// This enumeration holds the various states that the device can be in during
+// normal operation.
+//
+//*****************************************************************************
+typedef enum
+{
+    //
+    // Unconfigured.
+    //
+    BULK_STATE_UNCONFIGURED,
+
+    //
+    // No outstanding transaction remains to be completed.
+    //
+    BULK_STATE_IDLE,
+
+    //
+    // Waiting on completion of a send or receive transaction.
+    //
+    BULK_STATE_WAIT_DATA,
+
+    //
+    // Waiting for client to process data.
+    //
+    BULK_STATE_WAIT_CLIENT
+} tBulkState;
+
+//*****************************************************************************
+//
+// PRIVATE
+//
+// This structure defines the private instance data and state variables for the
+// Bulk only example device.  The memory for this structure is pointed to by
+// the psPrivateBulkData field in the tUSBDBulkDevice structure passed on
+// USBDBulkInit().
+//
+//*****************************************************************************
+typedef struct
+{
+    unsigned long ulUSBBase;
+    tDeviceInfo *psDevInfo;
+    tConfigDescriptor *psConfDescriptor;
+    volatile tBulkState eBulkRxState;
+    volatile tBulkState eBulkTxState;
+    volatile unsigned short usDeferredOpFlags;
+    unsigned short usLastTxSize;
+    volatile tBoolean bConnected;
+    unsigned char ucINEndpoint;
+    unsigned char ucOUTEndpoint;
+    unsigned char ucInterface;
+}
+tBulkInstance;
+
+#ifndef DEPRECATED
+//*****************************************************************************
+//
+// The number of bytes of workspace required by the bulk device class driver.
+// The client must provide a block of RAM of at least this size in the
+// tBulkInstance field of the tUSBBulkDevice structure passed on USBDBulkInit.
+//
+// This value is deprecated and should not be used, any new code should just
+// pass in a tBulkInstance structure in the psPrivateBulkData field.
+//
+//*****************************************************************************
+#define USB_BULK_WORKSPACE_SIZE (sizeof(tBulkInstance))
+#endif
+
+//*****************************************************************************
+//
+//! The size of the memory that should be allocated to create a configuration
+//! descriptor for a single instance of the USB Bulk Device.
+//! This does not include the configuration descriptor which is automatically
+//! ignored by the composite device class.
+//
+// For reference this is sizeof(g_sCDCSerIfaceHeaderSectionNOINT) +
+// sizeof(g_sCDCSerInterfaceSection) + sizeof(g_sCDCSerIfaceEndpointsNOINT)
+//
+//*****************************************************************************
+#define COMPOSITE_DBULK_SIZE     (23)
+
+//*****************************************************************************
+//
+//! The structure used by the application to define operating parameters for
+//! the bulk device.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! The vendor ID that this device is to present in the device descriptor.
+    //
+    unsigned short usVID;
+
+    //
+    //! The product ID that this device is to present in the device descriptor.
+    //
+    unsigned short usPID;
+
+    //
+    //! The maximum power consumption of the device, expressed in milliamps.
+    //
+    unsigned short usMaxPowermA;
+
+    //
+    //! Indicates whether the device is self- or bus-powered and whether or not
+    //! it supports remote wakeup.  Valid values are USB_CONF_ATTR_SELF_PWR or
+    //! USB_CONF_ATTR_BUS_PWR, optionally ORed with USB_CONF_ATTR_RWAKE.
+    //
+    unsigned char ucPwrAttributes;
+
+    //
+    //! A pointer to the callback function which will be called to notify
+    //! the application of events related to the device's data receive channel.
+    //
+    tUSBCallback pfnRxCallback;
+
+    //
+    //! A client-supplied pointer which will be sent as the first
+    //! parameter in all calls made to the receive channel callback,
+    //! pfnRxCallback.
+    //
+    void *pvRxCBData;
+
+    //
+    //! A pointer to the callback function which will be called to notify
+    //! the application of events related to the device's data transmit
+    //! channel.
+    //
+    tUSBCallback pfnTxCallback;
+
+    //
+    //! A client-supplied pointer which will be sent as the first
+    //! parameter in all calls made to the transmit channel callback,
+    //! pfnTxCallback.
+    //
+    void *pvTxCBData;
+
+    //
+    //! A pointer to the string descriptor array for this device.  This array
+    //! must contain pointers to the following string descriptors in this
+    //! order.  Language descriptor, Manufacturer name string (language 1),
+    //! Product name string (language 1), Serial number string (language 1),
+    //! Interface description string (language 1) and Configuration description
+    //! string (language 1).
+    //!
+    //! If supporting more than 1 language, the strings for indices 1 through 5
+    //! must be repeated for each of the other languages defined in the
+    //! language descriptor.
+    //
+    const unsigned char * const *ppStringDescriptors;
+
+    //
+    //! The number of descriptors provided in the ppStringDescriptors array.
+    //! This must be 1 + (5 * number of supported languages).
+    //
+    unsigned long ulNumStringDescriptors;
+
+    //
+    //! A pointer to private instance data for this device.  This memory must
+    //! remain accessible for as long as the bulk device is in use and must not
+    //! be modified by any code outside the bulk class driver.
+    //
+    tBulkInstance *psPrivateBulkData;
+}
+tUSBDBulkDevice;
+
+extern tDeviceInfo g_sBulkDeviceInfo;
+
+//*****************************************************************************
+//
+// API Function Prototypes
+//
+//*****************************************************************************
+extern void *USBDBulkInit(unsigned long ulIndex,
+                         const tUSBDBulkDevice *psDevice);
+extern void *USBDBulkCompositeInit(unsigned long ulIndex,
+                                   const tUSBDBulkDevice *psDevice);
+extern void USBDBulkTerm(void *pvInstance);
+extern void *USBDBulkSetRxCBData(void *pvInstance, void *pvCBData);
+extern void *USBDBulkSetTxCBData(void *pvInstance, void *pvCBData);
+extern unsigned long USBDBulkPacketWrite(void *pvInstance,
+                                         unsigned char *pcData,
+                                         unsigned long ulLength,
+                                         tBoolean bLast);
+extern unsigned long USBDBulkPacketRead(void *pvInstance,
+                                        unsigned char *pcData,
+                                        unsigned long ulLength,
+                                        tBoolean bLast);
+extern unsigned long USBDBulkTxPacketAvailable(void *pvInstance);
+extern unsigned long USBDBulkRxPacketAvailable(void *pvInstance);
+extern void USBDBulkPowerStatusSet(void *pvInstance, unsigned char ucPower);
+extern tBoolean USBDBulkRemoteWakeupRequest(void *pvInstance);
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __USBDBULK_H__
diff --git a/src/platform/lm3s/usblib/device/usbdcdc.c b/src/platform/lm3s/usblib/device/usbdcdc.c
new file mode 100755
index 00000000..7d82b014
--- /dev/null
+++ b/src/platform/lm3s/usblib/device/usbdcdc.c
@@ -0,0 +1,2973 @@
+//*****************************************************************************
+//
+// usbdcdc.c - USB CDC ACM (serial) device class driver.
+//
+// Copyright (c) 2008-2011 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 7611 of the Stellaris USB Library.
+//
+//*****************************************************************************
+
+#include "inc/hw_memmap.h"
+#include "inc/hw_types.h"
+#include "driverlib/debug.h"
+#include "driverlib/rom.h"
+#include "driverlib/rom_map.h"
+#include "driverlib/usb.h"
+#include "usblib/usblib.h"
+#include "usblib/usbcdc.h"
+#include "usblib/usblibpriv.h"
+#include "usblib/device/usbdevice.h"
+#include "usblib/device/usbdcomp.h"
+#include "usblib/device/usbdcdc.h"
+
+//*****************************************************************************
+//
+//! \addtogroup cdc_device_class_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Some assumptions and deviations from the CDC specification
+// ----------------------------------------------------------
+//
+// 1.  Although the CDC specification indicates that the following requests
+// should be supported by ACM CDC devices, these don't seem relevant to a
+// virtual COM port implementation and are never seen when connecting to a
+// Windows host and running either Hyperterminal or TeraTerm.  As a result,
+// this implementation does not support them and stalls endpoint 0 if they are
+// received.
+//          - SEND_ENCAPSULATED_COMMAND
+//          - GET_ENCAPSULATED_RESPONSE
+//          - SET_COMM_FEATURE
+//          - GET_COMM_FEATURE
+//          - CLEAR_COMM_FEATURE
+//
+// 2.  The CDC specification is very clear on the fact that an ACM device
+// should offer two interfaces - a control interface offering an interrupt IN
+// endpoint and a data interface offering bulk IN and OUT endpoints.  Using
+// this descriptor configuration, however, Windows insists on enumerating the
+// device as two separate entities resulting in two virtual COM ports or one
+// COM port and an Unknown Device (depending upon INF contents) appearing
+// in Device Manager.  This implementation, derived by experimentation and
+// examination of other virtual COM and CDC solutions, uses only a single
+// interface combining all three endpoints.  This appears to satisfy
+// Windows2000, XP and Vista and operates as intended using the Hyperterminal
+// and TeraTerm terminal emulators.  Your mileage may vary with other
+// (untested) operating systems!
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// The subset of endpoint status flags that we consider to be reception
+// errors.  These are passed to the client via USB_EVENT_ERROR if seen.
+//
+//*****************************************************************************
+#define USB_RX_ERROR_FLAGS      (USBERR_DEV_RX_DATA_ERROR | \
+                                 USBERR_DEV_RX_OVERRUN |    \
+                                 USBERR_DEV_RX_FIFO_FULL)
+
+//*****************************************************************************
+//
+// Size of the buffer to hold request-specific data read from the host.  This
+// must be sized to accommodate the largest request structure that we intend
+// processing.
+//
+//*****************************************************************************
+#define MAX_REQUEST_DATA_SIZE sizeof(tLineCoding)
+
+//*****************************************************************************
+//
+// Flags that may appear in usDeferredOpFlags to indicate some operation that
+// has been requested but could not be processed at the time it was received.
+//
+//*****************************************************************************
+#define CDC_DO_SERIAL_STATE_CHANGE 0
+#define CDC_DO_SEND_BREAK          1
+#define CDC_DO_CLEAR_BREAK         2
+#define CDC_DO_LINE_CODING_CHANGE  3
+#define CDC_DO_LINE_STATE_CHANGE   4
+#define CDC_DO_PACKET_RX           5
+
+//*****************************************************************************
+//
+// The subset of deferred operations which result in the receive channel
+// being blocked.
+//
+//*****************************************************************************
+#define RX_BLOCK_OPS ((1 << CDC_DO_SEND_BREAK) |                              \
+                      (1 << CDC_DO_LINE_CODING_CHANGE) |                      \
+                      (1 << CDC_DO_LINE_STATE_CHANGE))
+
+//*****************************************************************************
+//
+// Macros to convert between USB controller base address and an index.  These
+// are currently trivial but are included to allow for the possibility of
+// supporting more than one controller in the future.
+//
+//*****************************************************************************
+#define USB_BASE_TO_INDEX(BaseAddr) (0)
+#define USB_INDEX_TO_BASE(Index) (USB0_BASE)
+
+//*****************************************************************************
+//
+// Endpoints to use for each of the required endpoints in the driver.
+//
+//*****************************************************************************
+#define CONTROL_ENDPOINT        USB_EP_1
+#define DATA_IN_ENDPOINT        USB_EP_2
+#define DATA_OUT_ENDPOINT       USB_EP_1
+
+//*****************************************************************************
+//
+// The following are the USB interface numbers for the CDC serial device.
+//
+//*****************************************************************************
+#define SERIAL_INTERFACE_CONTROL    0
+#define SERIAL_INTERFACE_DATA       1
+
+//*****************************************************************************
+//
+// Maximum packet size for the bulk endpoints used for serial data
+// transmission and reception and the associated FIFO sizes to set aside
+// for each endpoint.
+//
+//*****************************************************************************
+#define DATA_IN_EP_FIFO_SIZE    USB_FIFO_SZ_64
+#define DATA_OUT_EP_FIFO_SIZE   USB_FIFO_SZ_64
+#define CTL_IN_EP_FIFO_SIZE     USB_FIFO_SZ_16
+
+#define DATA_IN_EP_MAX_SIZE     USB_FIFO_SZ_TO_BYTES(DATA_IN_EP_FIFO_SIZE)
+#define DATA_OUT_EP_MAX_SIZE    USB_FIFO_SZ_TO_BYTES(DATA_IN_EP_FIFO_SIZE)
+#define CTL_IN_EP_MAX_SIZE      USB_FIFO_SZ_TO_BYTES(CTL_IN_EP_FIFO_SIZE)
+
+//*****************************************************************************
+//
+// The collection of serial state flags indicating character errors.
+//
+//*****************************************************************************
+#define USB_CDC_SERIAL_ERRORS (USB_CDC_SERIAL_STATE_OVERRUN |                 \
+                               USB_CDC_SERIAL_STATE_PARITY |                  \
+                               USB_CDC_SERIAL_STATE_FRAMING)
+
+//*****************************************************************************
+//
+// Device Descriptor.  This is stored in RAM to allow several fields to be
+// changed at runtime based on the client's requirements.
+//
+//*****************************************************************************
+unsigned char g_pCDCSerDeviceDescriptor[] =
+{
+    18,                     // Size of this structure.
+    USB_DTYPE_DEVICE,       // Type of this structure.
+    USBShort(0x110),        // USB version 1.1 (if we say 2.0, hosts assume
+                            // high-speed - see USB 2.0 spec 9.2.6.6)
+    USB_CLASS_CDC,          // USB Device Class (spec 5.1.1)
+    0,                      // USB Device Sub-class (spec 5.1.1)
+    USB_CDC_PROTOCOL_NONE,  // USB Device protocol (spec 5.1.1)
+    64,                     // Maximum packet size for default pipe.
+    USBShort(0),            // Vendor ID (filled in during USBDCDCInit).
+    USBShort(0),            // Product ID (filled in during USBDCDCInit).
+    USBShort(0x100),        // Device Version BCD.
+    1,                      // Manufacturer string identifier.
+    2,                      // Product string identifier.
+    3,                      // Product serial number.
+    1                       // Number of configurations.
+};
+
+//*****************************************************************************
+//
+// CDC Serial configuration descriptor.
+//
+// It is vital that the configuration descriptor bConfigurationValue field
+// (byte 6) is 1 for the first configuration and increments by 1 for each
+// additional configuration defined here.  This relationship is assumed in the
+// device stack for simplicity even though the USB 2.0 specification imposes
+// no such restriction on the bConfigurationValue values.
+//
+// Note that this structure is deliberately located in RAM since we need to
+// be able to patch some values in it based on client requirements.
+//
+//*****************************************************************************
+unsigned char g_pCDCSerDescriptor[] =
+{
+    //
+    // Configuration descriptor header.
+    //
+    9,                          // Size of the configuration descriptor.
+    USB_DTYPE_CONFIGURATION,    // Type of this descriptor.
+    USBShort(9),                // The total size of this full structure, this
+                                // will be patched so it is just set to the
+                                // size of this structure.
+    2,                          // The number of interfaces in this
+                                // configuration.
+    1,                          // The unique value for this configuration.
+    5,                          // The string identifier that describes this
+                                // configuration.
+    USB_CONF_ATTR_SELF_PWR,     // Bus Powered, Self Powered, remote wake up.
+    250,                        // The maximum power in 2mA increments.
+};
+
+const tConfigSection g_sCDCSerConfigSection =
+{
+    sizeof(g_pCDCSerDescriptor),
+    g_pCDCSerDescriptor
+};
+
+//*****************************************************************************
+//
+// This is the Interface Association Descriptor for the serial device used in
+// composite devices.
+//
+//*****************************************************************************
+unsigned char g_pIADSerDescriptor[] =
+{
+
+    8,                          // Size of the interface descriptor.
+    USB_DTYPE_INTERFACE_ASC,    // Interface Association Type.
+    0x0,                        // Default starting interface is 0.
+    0x2,                        // Number of interfaces in this association.
+    USB_CLASS_CDC,              // The device class for this association.
+    USB_CDC_SUBCLASS_ABSTRACT_MODEL, // The device subclass for this
+                                     // association.
+    USB_CDC_PROTOCOL_V25TER,    // The protocol for this association.
+    0                           // The string index for this association.
+};
+
+const tConfigSection g_sIADSerConfigSection =
+{
+    sizeof(g_pIADSerDescriptor),
+    g_pIADSerDescriptor
+};
+
+//*****************************************************************************
+//
+// This is the control interface for the serial device.
+//
+//*****************************************************************************
+const unsigned char g_pCDCSerCommInterface[] =
+{
+    //
+    // Communication Class Interface Descriptor.
+    //
+    9,                          // Size of the interface descriptor.
+    USB_DTYPE_INTERFACE,        // Type of this descriptor.
+    SERIAL_INTERFACE_CONTROL,   // The index for this interface.
+    0,                          // The alternate setting for this interface.
+    1,                          // The number of endpoints used by this
+                                // interface.
+    USB_CLASS_CDC,              // The interface class constant defined by
+                                // USB-IF (spec 5.1.3).
+    USB_CDC_SUBCLASS_ABSTRACT_MODEL,    // The interface sub-class constant
+                                        // defined by USB-IF (spec 5.1.3).
+    USB_CDC_PROTOCOL_V25TER,    // The interface protocol for the sub-class
+                                // specified above.
+    4,                          // The string index for this interface.
+
+    //
+    // Communication Class Interface Functional Descriptor - Header
+    //
+    5,                          // Size of the functional descriptor.
+    USB_CDC_CS_INTERFACE,       // CDC interface descriptor
+    USB_CDC_FD_SUBTYPE_HEADER,  // Header functional descriptor
+    USBShort(0x110),            // Complies with CDC version 1.1
+
+    //
+    // Communication Class Interface Functional Descriptor - ACM
+    //
+    4,                          // Size of the functional descriptor.
+    USB_CDC_CS_INTERFACE,       // CDC interface descriptor
+    USB_CDC_FD_SUBTYPE_ABSTRACT_CTL_MGMT,
+    USB_CDC_ACM_SUPPORTS_LINE_PARAMS | USB_CDC_ACM_SUPPORTS_SEND_BREAK,
+
+    //
+    // Communication Class Interface Functional Descriptor - Unions
+    //
+    5,                          // Size of the functional descriptor.
+    USB_CDC_CS_INTERFACE,       // CDC interface descriptor
+    USB_CDC_FD_SUBTYPE_UNION,
+    SERIAL_INTERFACE_CONTROL,
+    SERIAL_INTERFACE_DATA,      // Data interface number
+
+    //
+    // Communication Class Interface Functional Descriptor - Call Management
+    //
+    5,                          // Size of the functional descriptor.
+    USB_CDC_CS_INTERFACE,       // CDC interface descriptor
+    USB_CDC_FD_SUBTYPE_CALL_MGMT,
+    USB_CDC_CALL_MGMT_HANDLED,
+    SERIAL_INTERFACE_DATA,      // Data interface number
+
+    //
+    // Endpoint Descriptor (interrupt, IN)
+    //
+    7,                              // The size of the endpoint descriptor.
+    USB_DTYPE_ENDPOINT,             // Descriptor type is an endpoint.
+    USB_EP_DESC_IN | USB_EP_TO_INDEX(CONTROL_ENDPOINT),
+    USB_EP_ATTR_INT,                // Endpoint is an interrupt endpoint.
+    USBShort(CTL_IN_EP_MAX_SIZE),   // The maximum packet size.
+    1                               // The polling interval for this endpoint.
+};
+
+const tConfigSection g_sCDCSerCommInterfaceSection =
+{
+    sizeof(g_pCDCSerCommInterface),
+    g_pCDCSerCommInterface
+};
+
+//*****************************************************************************
+//
+// This is the Data interface for the serial device.
+//
+//*****************************************************************************
+const unsigned char g_pCDCSerDataInterface[] =
+{
+    //
+    // Communication Class Data Interface Descriptor.
+    //
+    9,                          // Size of the interface descriptor.
+    USB_DTYPE_INTERFACE,        // Type of this descriptor.
+    SERIAL_INTERFACE_DATA,      // The index for this interface.
+    0,                          // The alternate setting for this interface.
+    2,                          // The number of endpoints used by this
+                                // interface.
+    USB_CLASS_CDC_DATA,         // The interface class constant defined by
+                                // USB-IF (spec 5.1.3).
+    0,                          // The interface sub-class constant
+                                // defined by USB-IF (spec 5.1.3).
+    USB_CDC_PROTOCOL_NONE,      // The interface protocol for the sub-class
+                                // specified above.
+    0,                          // The string index for this interface.
+
+    //
+    // Endpoint Descriptor
+    //
+    7,                              // The size of the endpoint descriptor.
+    USB_DTYPE_ENDPOINT,             // Descriptor type is an endpoint.
+    USB_EP_DESC_IN | USB_EP_TO_INDEX(DATA_IN_ENDPOINT),
+    USB_EP_ATTR_BULK,               // Endpoint is a bulk endpoint.
+    USBShort(DATA_IN_EP_MAX_SIZE),  // The maximum packet size.
+    0,                              // The polling interval for this endpoint.
+
+    //
+    // Endpoint Descriptor
+    //
+    7,                              // The size of the endpoint descriptor.
+    USB_DTYPE_ENDPOINT,             // Descriptor type is an endpoint.
+    USB_EP_DESC_OUT | USB_EP_TO_INDEX(DATA_OUT_ENDPOINT),
+    USB_EP_ATTR_BULK,               // Endpoint is a bulk endpoint.
+    USBShort(DATA_OUT_EP_MAX_SIZE), // The maximum packet size.
+    0,                              // The polling interval for this endpoint.
+};
+
+const tConfigSection g_sCDCSerDataInterfaceSection =
+{
+    sizeof(g_pCDCSerDataInterface),
+    g_pCDCSerDataInterface
+};
+
+//*****************************************************************************
+//
+// This array lists all the sections that must be concatenated to make a
+// single, complete CDC ACM configuration descriptor.
+//
+//*****************************************************************************
+const tConfigSection *g_psCDCSerSections[] =
+{
+    &g_sCDCSerConfigSection,
+    &g_sCDCSerCommInterfaceSection,
+    &g_sCDCSerDataInterfaceSection,
+};
+
+#define NUM_CDCSER_SECTIONS (sizeof(g_psCDCSerSections) /                     \
+                             sizeof(tConfigSection *))
+
+//*****************************************************************************
+//
+// The header for the single configuration.  This is the root of the data
+// structure that defines all the bits and pieces that are pulled together to
+// generate the configuration descriptor.
+//
+//*****************************************************************************
+const tConfigHeader g_sCDCSerConfigHeader =
+{
+    NUM_CDCSER_SECTIONS,
+    g_psCDCSerSections
+};
+
+//*****************************************************************************
+//
+// This array lists all the sections that must be concatenated to make a
+// single, complete CDC ACM configuration descriptor used in composite devices.
+// The only addition is the g_sIADSerConfigSection.
+//
+//*****************************************************************************
+const tConfigSection *g_psCDCCompSerSections[] =
+{
+    &g_sCDCSerConfigSection,
+    &g_sIADSerConfigSection,
+    &g_sCDCSerCommInterfaceSection,
+    &g_sCDCSerDataInterfaceSection,
+};
+
+#define NUM_COMP_CDCSER_SECTIONS (sizeof(g_psCDCCompSerSections) /                     \
+                                  sizeof(tConfigSection *))
+
+//*****************************************************************************
+//
+// The header for the composite configuration.  This is the root of the data
+// structure that defines all the bits and pieces that are pulled together to
+// generate the configuration descriptor.
+//
+//*****************************************************************************
+const tConfigHeader g_sCDCCompSerConfigHeader =
+{
+    NUM_COMP_CDCSER_SECTIONS,
+    g_psCDCCompSerSections
+};
+
+//*****************************************************************************
+//
+// Configuration Descriptor for the CDC serial class device.
+//
+//*****************************************************************************
+const tConfigHeader * const g_pCDCSerConfigDescriptors[] =
+{
+    &g_sCDCSerConfigHeader
+};
+
+//*****************************************************************************
+//
+// Configuration Descriptor for the CDC serial class device used in a composite
+// device.
+//
+//*****************************************************************************
+const tConfigHeader * const g_pCDCCompSerConfigDescriptors[] =
+{
+    &g_sCDCCompSerConfigHeader
+};
+
+//*****************************************************************************
+//
+// Forward references for device handler callbacks
+//
+//*****************************************************************************
+static void HandleRequests(void *pvInstance, tUSBRequest *pUSBRequest);
+static void HandleConfigChange(void *pvInstance, unsigned long ulInfo);
+static void HandleEP0Data(void *pvInstance, unsigned long ulDataSize);
+static void HandleDisconnect(void *pvInstance);
+static void HandleEndpoints(void *pvInstance, unsigned long ulStatus);
+static void HandleSuspend(void *pvInstance);
+static void HandleResume(void *pvInstance);
+static void HandleDevice(void *pvInstance, unsigned long ulRequest,
+                         void *pvRequestData);
+
+//*****************************************************************************
+//
+// The device information structure for the USB serial device.
+//
+//*****************************************************************************
+tDeviceInfo g_sCDCSerDeviceInfo =
+{
+    //
+    // Device event handler callbacks.
+    //
+    {
+        //
+        // GetDescriptor
+        //
+        0,
+
+        //
+        // RequestHandler
+        //
+        HandleRequests,
+
+        //
+        // InterfaceChange
+        //
+        0,
+
+        //
+        // ConfigChange
+        //
+        HandleConfigChange,
+
+        //
+        // DataReceived
+        //
+        HandleEP0Data,
+
+        //
+        // DataSentCallback
+        //
+        0,
+
+        //
+        // ResetHandler
+        //
+        0,
+
+        //
+        // SuspendHandler
+        //
+        HandleSuspend,
+
+        //
+        // ResumeHandler
+        //
+        HandleResume,
+
+        //
+        // DisconnectHandler
+        //
+        HandleDisconnect,
+
+        //
+        // EndpointHandler
+        //
+        HandleEndpoints,
+
+        //
+        // Device handler.
+        //
+        HandleDevice
+    },
+
+    //
+    // The common device descriptor.
+    //
+    g_pCDCSerDeviceDescriptor,
+
+    //
+    // Default to no interrupt endpoint.
+    //
+    g_pCDCCompSerConfigDescriptors,
+
+    //
+    // String descriptors will be passed in.
+    //
+    0,
+    0,
+
+    //
+    // Use the default USB FIFO configuration.
+    //
+    &g_sUSBDefaultFIFOConfig,
+
+    //
+    // Zero out the instance pointer by default.
+    //
+    0
+};
+
+//*****************************************************************************
+//
+// Set or clear deferred operation flags in an "atomic" manner.
+//
+// \param pusDeferredOp points to the flags variable which is to be modified.
+// \param usBit indicates which bit number is to be set or cleared.
+// \param bSet indicates the state that the flag must be set to.  If \b true,
+// the flag is set, if \b false, the flag is cleared.
+//
+// This function safely sets or clears a bit in a flag variable.  The operation
+// makes use of bitbanding to ensure that the operation is atomic (no read-
+// modify-write is required).
+//
+// \return None.
+//
+//*****************************************************************************
+static void
+SetDeferredOpFlag(volatile unsigned short *pusDeferredOp,
+                  unsigned short usBit, tBoolean bSet)
+{
+    //
+    // Set the flag bit to 1 or 0 using a bitband access.
+    //
+    HWREGBITH(pusDeferredOp, usBit) = bSet ? 1 : 0;
+}
+
+//*****************************************************************************
+//
+// Determines whether or not a client has consumed all received data previously
+// passed to it.
+//
+//! \param psDevice is the pointer to the device instance structure as returned
+//! by USBDCDCInit().
+//
+// This function is called to determine whether or not a device has consumed
+// all data previously passed to it via its receive callback.
+//
+// \return Returns \b true on success or \b false on failure.
+//
+//*****************************************************************************
+static tBoolean
+DeviceConsumedAllData(const tUSBDCDCDevice *psDevice)
+{
+    unsigned long ulRemaining;
+
+    //
+    // Send the device an event requesting that it tell us how many bytes
+    // of data it still has to process.
+    //
+    ulRemaining = psDevice->pfnRxCallback(psDevice->pvRxCBData,
+    USB_EVENT_DATA_REMAINING, 0, (void *)0);
+
+    //
+    // If any data remains to be processed, return false, else return true.
+    //
+    return(ulRemaining ? false : true);
+}
+
+//*****************************************************************************
+//
+// Notifies the client that it should set or clear a break condition.
+//
+// \param psDevice is the pointer to the device instance structure as returned
+// by USBDCDCInit().
+// \param bSend is \b true if a break condition is to be set or \b false if
+// it is to be cleared.
+//
+// This function is called to instruct the client to start or stop sending a
+// break condition on its serial transmit line.
+//
+// \return Returns \b true on success or \b false on failure.
+//
+//*****************************************************************************
+static void
+SendBreak(const tUSBDCDCDevice *psDevice, tBoolean bSend)
+{
+    tCDCSerInstance *psInst;
+
+    //
+    // Get our instance data pointer.
+    //
+    psInst = psDevice->psPrivateCDCSerData;
+
+    //
+    // Set the break state flags as necessary.  If we are turning the break on,
+    // set the flag to tell ourselves that we need to notify the client when
+    // it is time to turn it off again.
+    //
+    SetDeferredOpFlag(&psInst->usDeferredOpFlags, CDC_DO_SEND_BREAK, false);
+    SetDeferredOpFlag(&psInst->usDeferredOpFlags, CDC_DO_CLEAR_BREAK, bSend);
+
+    //
+    // Tell the client to start or stop sending the break.
+    //
+    psDevice->pfnControlCallback(psDevice->pvControlCBData,
+                                 (bSend ? USBD_CDC_EVENT_SEND_BREAK :
+                                          USBD_CDC_EVENT_CLEAR_BREAK), 0,
+                                 (void *)0);
+}
+
+//*****************************************************************************
+//
+// Notifies the client of a host request to set the serial communication
+// parameters.
+//
+// \param psDevice is the device instance whose communication parameters are to
+// be set.
+//
+// This function is called to notify the client when the host requests a change
+// in the serial communication parameters (baud rate, parity, number of bits
+// per character and number of stop bits) to use.
+//
+// \return None.
+//
+//*****************************************************************************
+static void
+SendLineCodingChange(const tUSBDCDCDevice *psDevice)
+{
+    tCDCSerInstance *psInst;
+
+    //
+    // Get our instance data pointer.
+    //
+    psInst = psDevice->psPrivateCDCSerData;
+
+    //
+    // Clear the flag we use to tell ourselves that the line coding change has
+    // yet to be notified to the client.
+    //
+    SetDeferredOpFlag(&psInst->usDeferredOpFlags, CDC_DO_LINE_CODING_CHANGE,
+                      false);
+
+    //
+    // Tell the client to update their serial line coding parameters.
+    //
+    psDevice->pfnControlCallback(psDevice->pvControlCBData,
+                                 USBD_CDC_EVENT_SET_LINE_CODING, 0,
+                                 &(psInst->sLineCoding));
+}
+
+//*****************************************************************************
+//
+// Notifies the client of a host request to set the RTS and DTR handshake line
+// states.
+//
+// \param psDevice is the device instance whose break condition is to be set or
+// cleared.
+//
+// This function is called to notify the client when the host requests a change
+// in the state of one or other of the RTS and DTR handshake lines.
+//
+// \return None.
+//
+//*****************************************************************************
+static void
+SendLineStateChange(const tUSBDCDCDevice *psDevice)
+{
+    tCDCSerInstance *psInst;
+
+    //
+    // Get our instance data pointer.
+    //
+    psInst = psDevice->psPrivateCDCSerData;
+
+    //
+    // Clear the flag we use to tell ourselves that the line coding change has
+    // yet to be notified to the client.
+    //
+    SetDeferredOpFlag(&psInst->usDeferredOpFlags, CDC_DO_LINE_STATE_CHANGE,
+                      false);
+
+    //
+    // Tell the client to update their serial line coding parameters.
+    //
+    psDevice->pfnControlCallback(psDevice->pvControlCBData,
+                                 USBD_CDC_EVENT_SET_CONTROL_LINE_STATE,
+                                 psInst->usControlLineState,
+                                 (void *)0);
+}
+
+//*****************************************************************************
+//
+// Notifies the client of a break request if no data remains to be processed.
+//
+// \param psDevice is the device instance that is to be commanded to send a
+// break condition.
+//
+// This function is called when the host requests that the device set a break
+// condition on the serial transmit line.  If no data received from the host
+// remains to be processed, the break request is passed to the control
+// callback.  If data is outstanding, the call is ignored (with the operation
+// being retried on the next timer tick).
+//
+// \return Returns \b true if the break notification was sent, \b false
+// otherwise.
+//
+//*****************************************************************************
+static tBoolean
+CheckAndSendBreak(const tUSBDCDCDevice *psDevice, unsigned short usDuration)
+{
+    tBoolean bCanSend;
+
+    //
+    // Has the client consumed all data received from the host yet?
+    //
+    bCanSend = DeviceConsumedAllData(psDevice);
+
+    //
+    // Can we send the break request?
+    //
+    if(bCanSend)
+    {
+        //
+        // Pass the break request on to the client since no data remains to be
+        // consumed.
+        //
+        SendBreak(psDevice, (usDuration ? true : false));
+    }
+
+    //
+    // Tell the caller whether or not we sent the notification.
+    //
+    return(bCanSend);
+}
+
+//*****************************************************************************
+//
+// Notifies the client of a request to change the serial line parameters if no
+// data remains to be processed.
+//
+// \param psDevice is the device instance whose line coding parameters are to
+// be changed.
+//
+// This function is called when the host requests that the device change the
+// serial line coding parameters.  If no data received from the host remains
+// to be processed, the request is passed to the control callback.  If data is
+// outstanding, the call is ignored (with the operation being retried on the
+// next timer tick).
+//
+// \return Returns \b true if the notification was sent, \b false otherwise.
+//
+//*****************************************************************************
+static tBoolean
+CheckAndSendLineCodingChange(const tUSBDCDCDevice *psDevice)
+{
+    tBoolean bCanSend;
+
+    //
+    // Has the client consumed all data received from the host yet?
+    //
+    bCanSend = DeviceConsumedAllData(psDevice);
+
+    //
+    // Can we send the break request?
+    //
+    if(bCanSend)
+    {
+        //
+        // Pass the request on to the client since no data remains to be
+        // consumed.
+        //
+        SendLineCodingChange(psDevice);
+    }
+
+    //
+    // Tell the caller whether or not we sent the notification.
+    //
+    return(bCanSend);
+}
+
+//*****************************************************************************
+//
+// Notifies the client of a request to change the handshake line states if no
+// data remains to be processed.
+//
+// \param psDevice is the device instance whose handshake line states are to
+// be changed.
+//
+// This function is called when the host requests that the device change the
+// state of one or other of the RTS or DTR handshake lines.  If no data
+// received from the host remains to be processed, the request is passed to
+// the control callback.  If data is outstanding, the call is ignored (with
+// the operation being retried on the next timer tick).
+//
+// \return Returns \b true if the notification was sent, \b false otherwise.
+//
+//*****************************************************************************
+static tBoolean
+CheckAndSendLineStateChange(const tUSBDCDCDevice *psDevice)
+{
+    tBoolean bCanSend;
+
+    //
+    // Has the client consumed all data received from the host yet?
+    //
+    bCanSend = DeviceConsumedAllData(psDevice);
+
+    //
+    // Can we send the break request?
+    //
+    if(bCanSend)
+    {
+        //
+        // Pass the request on to the client since no data remains to be
+        // consumed.
+        //
+        SendLineStateChange(psDevice);
+    }
+
+    //
+    // Tell the caller whether or not we sent the notification.
+    //
+    return(bCanSend);
+}
+
+//*****************************************************************************
+//
+// Notifies the client of a change in the serial line state.
+//
+// \param psInst is the instance whose serial state is to be reported.
+//
+// This function is called to send the current serial state information to
+// the host via the the interrupt IN endpoint.  This notification informs the
+// host of problems or conditions such as parity errors, breaks received,
+// framing errors, etc.
+//
+// \return Returns \b true on success or \b false on failure.
+//
+//*****************************************************************************
+static tBoolean
+SendSerialState(const tUSBDCDCDevice *psDevice)
+{
+    tUSBRequest sRequest;
+    unsigned short usSerialState;
+    tCDCSerInstance *psInst;
+    long lRetcode;
+
+    //
+    // Get a pointer to our instance data.
+    //
+    psInst = psDevice->psPrivateCDCSerData;
+
+    //
+    // Remember that we are in the middle of sending a notification.
+    //
+    psInst->eCDCInterruptState = CDC_STATE_WAIT_DATA;
+
+    //
+    // Clear the flag we use to indicate that a send is required.
+    //
+    SetDeferredOpFlag(&psInst->usDeferredOpFlags, CDC_DO_SERIAL_STATE_CHANGE,
+                      false);
+    //
+    // Take a snapshot of the serial state.
+    //
+    usSerialState = psInst->usSerialState;
+
+    //
+    // Build the request we will use to send the notification.
+    //
+    sRequest.bmRequestType = (USB_RTYPE_DIR_IN | USB_RTYPE_CLASS |
+    USB_RTYPE_INTERFACE);
+    sRequest.bRequest = USB_CDC_NOTIFY_SERIAL_STATE;
+    sRequest.wValue = 0;
+    sRequest.wIndex = 0;
+    sRequest.wLength = USB_CDC_NOTIFY_SERIAL_STATE_SIZE;
+
+    //
+    // Write the request structure to the USB FIFO.
+    //
+    lRetcode = MAP_USBEndpointDataPut(psInst->ulUSBBase,
+                                      psInst->ucControlEndpoint,
+                                      (unsigned char *)&sRequest,
+                                      sizeof(tUSBRequest));
+    lRetcode = MAP_USBEndpointDataPut(psInst->ulUSBBase, psInst->ucControlEndpoint,
+                                      (unsigned char *)&usSerialState,
+                                      USB_CDC_NOTIFY_SERIAL_STATE_SIZE);
+
+    //
+    // Did we correctly write the data to the endpoint FIFO?
+    //
+    if(lRetcode != -1)
+    {
+        //
+        // We put the data into the FIFO so now schedule it to be
+        // sent.
+        //
+        lRetcode = MAP_USBEndpointDataSend(psInst->ulUSBBase,
+                                           psInst->ucControlEndpoint,
+                                           USB_TRANS_IN);
+    }
+
+    //
+    // If an error occurred, mark the endpoint as idle (to prevent possible
+    // lockup) and return an error.
+    //
+    if(lRetcode == -1)
+    {
+        psInst->eCDCInterruptState = CDC_STATE_IDLE;
+        return(false);
+    }
+    else
+    {
+        //
+        // Everything went fine.  Clear the error bits that we just notified
+        // and return true.
+        //
+        psInst->usSerialState &= ~(usSerialState & USB_CDC_SERIAL_ERRORS);
+        return(true);
+    }
+}
+
+//*****************************************************************************
+//
+// Receives notifications related to data received from the host.
+//
+// \param psDevice is the device instance whose endpoint is to be processed.
+// \param ulStatus is the USB interrupt status that caused this function to
+// be called.
+//
+// This function is called from HandleEndpoints for all interrupts signaling
+// the arrival of data on the bulk OUT endpoint (in other words, whenever the
+// host has sent us a packet of data).  We inform the client that a packet
+// is available and, on return, check to see if the packet has been read.  If
+// not, we schedule another notification to the client for a later time.
+//
+// \return Returns \b true on success or \b false on failure.
+//
+//*****************************************************************************
+tBoolean
+ProcessDataFromHost(const tUSBDCDCDevice *psDevice, unsigned long ulStatus)
+{
+    unsigned long ulEPStatus;
+    unsigned long ulSize;
+    tCDCSerInstance *psInst;
+
+    //
+    // Get a pointer to our instance data.
+    //
+    psInst = psDevice->psPrivateCDCSerData;
+
+    //
+    // Get the endpoint status to see why we were called.
+    //
+    ulEPStatus = MAP_USBEndpointStatus(psInst->ulUSBBase,
+                                       psInst->ucBulkOUTEndpoint);
+
+    //
+    // Clear the status bits.
+    //
+    MAP_USBDevEndpointStatusClear(psInst->ulUSBBase, psInst->ucBulkOUTEndpoint,
+                                  ulEPStatus);
+
+    //
+    // Has a packet been received?
+    //
+    if(ulEPStatus & USB_DEV_RX_PKT_RDY)
+    {
+        //
+        // Set the flag we use to indicate that a packet read is pending.  This
+        // will be cleared if the packet is read.  If the client doesn't read
+        // the packet in the context of the USB_EVENT_RX_AVAILABLE callback,
+        // the event will be notified later during tick processing.
+        //
+        SetDeferredOpFlag(&psInst->usDeferredOpFlags, CDC_DO_PACKET_RX, true);
+
+        //
+        // Is the receive channel currently blocked?
+        //
+        if(!psInst->bControlBlocked && !psInst->bRxBlocked)
+        {
+            //
+            // How big is the packet we've just been sent?
+            //
+            ulSize = MAP_USBEndpointDataAvail(psInst->ulUSBBase,
+                                              psInst->ucBulkOUTEndpoint);
+
+            //
+            // The receive channel is not blocked so let the caller know
+            // that a packet is waiting.  The parameters are set to indicate
+            // that the packet has not been read from the hardware FIFO yet.
+            //
+            psDevice->pfnRxCallback(psDevice->pvRxCBData,
+                                    USB_EVENT_RX_AVAILABLE, ulSize,
+                                    (void *)0);
+        }
+    }
+    else
+    {
+        //
+        // No packet was received.  Some error must have been reported.  Check
+        // and pass this on to the client if necessary.
+        //
+        if(ulEPStatus & USB_RX_ERROR_FLAGS)
+        {
+            //
+            // This is an error we report to the client so...
+            //
+            psDevice->pfnRxCallback(psDevice->pvRxCBData,
+                                    USB_EVENT_ERROR,
+                                    (ulEPStatus & USB_RX_ERROR_FLAGS),
+                                    (void *)0);
+        }
+
+        return(false);
+    }
+
+    return(true);
+}
+
+//*****************************************************************************
+//
+// Receives notifications related to interrupt messages sent to the host.
+//
+// \param psDevice is the device instance whose endpoint is to be processed.
+// \param ulStatus is the USB interrupt status that caused this function to
+// be called.
+//
+// This function is called from HandleEndpoints for all interrupts originating
+// from the interrupt IN endpoint (in other words, whenever a notification has
+// been transmitted to the USB host).
+//
+// \return Returns \b true on success or \b false on failure.
+//
+//*****************************************************************************
+tBoolean
+ProcessNotificationToHost(const tUSBDCDCDevice *psDevice,
+                          unsigned long ulStatus)
+{
+    unsigned long ulEPStatus;
+    tCDCSerInstance *psInst;
+    tBoolean bRetcode;
+
+    //
+    // Assume all will go well until we have reason to believe otherwise.
+    //
+    bRetcode = true;
+
+    //
+    // Get a pointer to our instance data.
+    //
+    psInst = psDevice->psPrivateCDCSerData;
+
+    //
+    // Get the endpoint status to see why we were called.
+    //
+    ulEPStatus = MAP_USBEndpointStatus(psInst->ulUSBBase,
+                                       psInst->ucControlEndpoint);
+
+    //
+    // Clear the status bits.
+    //
+    MAP_USBDevEndpointStatusClear(psInst->ulUSBBase,
+                                  psInst->ucControlEndpoint, ulEPStatus);
+
+    //
+    // Did the state change while we were waiting for the previous notification
+    // to complete?
+    //
+    if(psInst->usDeferredOpFlags & (1 << CDC_DO_SERIAL_STATE_CHANGE))
+    {
+        //
+        // The state changed while we were waiting so we need to schedule
+        // another notification immediately.
+        //
+        bRetcode = SendSerialState(psDevice);
+    }
+    else
+    {
+        //
+        // Our last notification completed and we didn't have any new
+        // notifications to make so the interrupt channel is now idle again.
+        //
+        psInst->eCDCInterruptState = CDC_STATE_IDLE;
+    }
+
+    //
+    // Tell the caller how things went.
+    //
+    return(bRetcode);
+}
+
+//*****************************************************************************
+//
+// Receives notifications related to data sent to the host.
+//
+// \param psDevice is the device instance whose endpoint is to be processed.
+// \param ulStatus is the USB interrupt status that caused this function to
+// be called.
+//
+// This function is called from HandleEndpoints for all interrupts originating
+// from the bulk IN endpoint (in other words, whenever data has been
+// transmitted to the USB host).  We examine the cause of the interrupt and,
+// if due to completion of a transmission, notify the client.
+//
+// \return Returns \b true on success or \b false on failure.
+//
+//*****************************************************************************
+tBoolean
+ProcessDataToHost(const tUSBDCDCDevice *psDevice, unsigned long ulStatus)
+{
+    tCDCSerInstance *psInst;
+    unsigned long ulEPStatus, ulSize;
+    tBoolean bSentFullPacket;
+
+    //
+    // Get a pointer to our instance data.
+    //
+    psInst = psDevice->psPrivateCDCSerData;
+
+    //
+    // Get the endpoint status to see why we were called.
+    //
+    ulEPStatus = MAP_USBEndpointStatus(psInst->ulUSBBase,
+                                       psInst->ucBulkINEndpoint);
+
+    //
+    // Clear the status bits.
+    //
+    MAP_USBDevEndpointStatusClear(psInst->ulUSBBase,
+                                  psInst->ucBulkINEndpoint, ulEPStatus);
+
+    //
+    // Our last transmission completed.  Clear our state back to idle and
+    // see if we need to send any more data.
+    //
+    psInst->eCDCTxState = CDC_STATE_IDLE;
+
+    //
+    // If this notification isn't as a result of sending a zero-length packet,
+    // call back to the client to let it know we sent the last thing it passed
+    // us.
+    //
+    if(psInst->usLastTxSize)
+    {
+        //
+        // Have we just sent a 64 byte packet?
+        //
+        bSentFullPacket = (psInst->usLastTxSize == DATA_IN_EP_MAX_SIZE) ?
+                           true : false;
+
+        //
+        // Notify the client that the last transmission completed.
+        //
+        ulSize = (unsigned long)psInst->usLastTxSize;
+        psInst->usLastTxSize = 0;
+        psDevice->pfnTxCallback(psDevice->pvTxCBData, USB_EVENT_TX_COMPLETE,
+                                ulSize, (void *)0);
+
+        //
+        // If we had previously sent a full packet and the callback didn't
+        // schedule a new transmission, send a zero length packet to indicate
+        // the end of the transfer.
+        //
+        if(bSentFullPacket && !psInst->usLastTxSize)
+        {
+            //
+            // We can expect another transmit complete notification after doing
+            // this.
+            //
+            psInst->eCDCTxState = CDC_STATE_WAIT_DATA;
+
+            //
+            // Send the zero-length packet.
+            //
+            MAP_USBEndpointDataSend(psInst->ulUSBBase,
+                                    psInst->ucBulkINEndpoint,
+                                    USB_TRANS_IN);
+        }
+    }
+
+    return(true);
+}
+
+//*****************************************************************************
+//
+// Called by the USB stack for any activity involving one of our endpoints
+// other than EP0.  This function is a fan out that merely directs the call to
+// the correct handler depending upon the endpoint and transaction direction
+// signaled in ulStatus.
+//
+//*****************************************************************************
+static void
+HandleEndpoints(void *pvInstance, unsigned long ulStatus)
+{
+    const tUSBDCDCDevice *psDeviceInst;
+    tCDCSerInstance *psInst;
+
+    ASSERT(pvInstance != 0);
+
+    //
+    // Determine if the serial device is in single or composite mode because
+    // the meaning of ulIndex is different in both cases.
+    //
+    psDeviceInst = pvInstance;
+    psInst = psDeviceInst->psPrivateCDCSerData;
+
+    //
+    // Handler for the interrupt IN notification endpoint.
+    //
+    if(ulStatus & (1 << USB_EP_TO_INDEX(psInst->ucControlEndpoint)))
+    {
+        //
+        // We have sent an interrupt notification to the host.
+        //
+        ProcessNotificationToHost(psDeviceInst, ulStatus);
+    }
+
+    //
+    // Handler for the bulk OUT data endpoint.
+    //
+    if(ulStatus & (0x10000 << USB_EP_TO_INDEX(psInst->ucBulkOUTEndpoint)))
+    {
+        //
+        // Data is being sent to us from the host.
+        //
+        ProcessDataFromHost(psDeviceInst, ulStatus);
+    }
+
+    //
+    // Handler for the bulk IN data endpoint.
+    //
+    if(ulStatus & (1 << USB_EP_TO_INDEX(psInst->ucBulkINEndpoint)))
+    {
+        ProcessDataToHost(psDeviceInst, ulStatus);
+    }
+}
+
+//*****************************************************************************
+//
+// Called by the USB stack whenever a configuration change occurs.
+//
+//*****************************************************************************
+static void
+HandleConfigChange(void *pvInstance, unsigned long ulInfo)
+{
+    tCDCSerInstance *psInst;
+    const tUSBDCDCDevice *psDevice;
+
+    ASSERT(pvInstance != 0);
+
+    //
+    // Create a device instance pointer.
+    //
+    psDevice = (const tUSBDCDCDevice *)pvInstance;
+
+    //
+    // Get a pointer to our instance data.
+    //
+    psInst = psDevice->psPrivateCDCSerData;
+
+    //
+    // Set all our endpoints to idle state.
+    //
+    psInst->eCDCInterruptState = CDC_STATE_IDLE;
+    psInst->eCDCRequestState = CDC_STATE_IDLE;
+    psInst->eCDCRxState = CDC_STATE_IDLE;
+    psInst->eCDCTxState = CDC_STATE_IDLE;
+
+    //
+    // If we are not currently connected so let the client know we are open
+    // for business.
+    //
+    if(!psInst->bConnected)
+    {
+        //
+        // Pass the connected event to the client.
+        //
+        psDevice->pfnControlCallback(psDevice->pvControlCBData,
+                                     USB_EVENT_CONNECTED, 0, (void *)0);
+    }
+
+    //
+    // Remember that we are connected.
+    //
+    psInst->bConnected = true;
+}
+
+//*****************************************************************************
+//
+// USB data received callback.
+//
+// This function is called by the USB stack whenever any data requested from
+// EP0 is received.
+//
+//*****************************************************************************
+static void
+HandleEP0Data(void *pvInstance, unsigned long ulDataSize)
+{
+    const tUSBDCDCDevice *psDevice;
+    tCDCSerInstance *psInst;
+    tBoolean bRetcode;
+
+    ASSERT(pvInstance != 0);
+
+    //
+    // Create a device instance pointer.
+    //
+    psDevice = (const tUSBDCDCDevice *)pvInstance;
+
+    //
+    // If we were not passed any data, just return.
+    //
+    if(ulDataSize == 0)
+    {
+        return;
+    }
+
+    //
+    // Get our instance data pointer.
+    //
+    psInst = psDevice->psPrivateCDCSerData;
+
+    //
+    // Make sure we are actually expecting something.
+    //
+    if(psInst->eCDCRequestState != CDC_STATE_WAIT_DATA)
+    {
+        return;
+    }
+
+    //
+    // Process the data received.  This will be a request-specific data
+    // block associated with the last request received.
+    //
+    switch (psInst->ucPendingRequest)
+    {
+        //
+        // We just got the line coding structure.  Make sure the client has
+        // read all outstanding data then pass it back to initiate a change
+        // in the line state.
+        //
+        case USB_CDC_SET_LINE_CODING:
+        {
+            if(ulDataSize != sizeof(tLineCoding))
+            {
+                USBDCDStallEP0(0);
+            }
+            else
+            {
+                //
+                // Set the flag telling us that we need to send a line coding
+                // notification to the client.
+                //
+                SetDeferredOpFlag(&psInst->usDeferredOpFlags,
+                                  CDC_DO_LINE_CODING_CHANGE, true);
+
+                //
+                // See if we can send the notification immediately.
+                //
+                bRetcode = CheckAndSendLineCodingChange(psDevice);
+
+                //
+                // If we couldn't send the line coding change request to the
+                // client, block reception of more data from the host until
+                // previous data is processed and we send the change request.
+                //
+                if(!bRetcode)
+                {
+                    psInst->bRxBlocked = true;
+                }
+            }
+            break;
+        }
+
+            //
+            // Oops - we seem to be waiting on a request which has not yet been
+            // coded here.  Flag the error and stall EP0 anyway (even though
+            // this would indicate a coding error).
+            //
+        default:
+        {
+            USBDCDStallEP0(0);
+            ASSERT(0);
+            break;
+        }
+    }
+
+    //
+    // All is well.  Set the state back to IDLE.
+    //
+    psInst->eCDCRequestState = CDC_STATE_IDLE;
+}
+
+//*****************************************************************************
+//
+// Device instance specific handler.
+//
+//*****************************************************************************
+static void
+HandleDevice(void *pvInstance, unsigned long ulRequest, void *pvRequestData)
+{
+    tCDCSerInstance *psInst;
+    unsigned char *pucData;
+
+    //
+    // Create the serial instance data.
+    //
+    psInst = ((tUSBDCDCDevice *)pvInstance)->psPrivateCDCSerData;
+
+    //
+    // Create the char array used by the events supported by the USB CDC
+    // serial class.
+    //
+    pucData = (unsigned char *)pvRequestData;
+
+    switch(ulRequest)
+    {
+        //
+        // This was an interface change event.
+        //
+        case USB_EVENT_COMP_IFACE_CHANGE:
+        {
+            //
+            // Save the change to the appropriate interface number.
+            //
+            if(pucData[0] == SERIAL_INTERFACE_CONTROL)
+            {
+                psInst->ucInterfaceControl = pucData[1];
+            }
+            else if(pucData[0] == SERIAL_INTERFACE_DATA)
+            {
+                psInst->ucInterfaceData = pucData[1];
+            }
+            break;
+        }
+
+        //
+        // This was an endpoint change event.
+        //
+        case USB_EVENT_COMP_EP_CHANGE:
+        {
+            //
+            // Determine if this is an IN or OUT endpoint that has changed.
+            //
+            if(pucData[0] & USB_EP_DESC_IN)
+            {
+                //
+                // Determine which IN endpoint to modify.
+                //
+                if((pucData[0] & 0x7f) == USB_EP_TO_INDEX(CONTROL_ENDPOINT))
+                {
+                    psInst->ucControlEndpoint =
+                        INDEX_TO_USB_EP((pucData[1] & 0x7f));
+                }
+                else
+                {
+                    psInst->ucBulkINEndpoint =
+                        INDEX_TO_USB_EP((pucData[1] & 0x7f));
+                }
+            }
+            else
+            {
+                //
+                // Extract the new endpoint number.
+                //
+                psInst->ucBulkOUTEndpoint =
+                    INDEX_TO_USB_EP(pucData[1] & 0x7f);
+            }
+            break;
+        }
+
+        //
+        // Handle class specific reconfiguring of the configuration descriptor
+        // once the composite class has built the full descriptor.
+        //
+        case USB_EVENT_COMP_CONFIG:
+        {
+            //
+            // This sets the bFirstInterface of the Interface Association
+            // descriptor to the first interface which is the control
+            // interface used by this instance.
+            //
+            pucData[2] = psInst->ucInterfaceControl;
+
+            //
+            // This sets the bMasterInterface of the Union descriptor to the
+            // Control interface and the bSlaveInterface of the Union
+            // Descriptor to the Data interface used by this instance.
+            //
+            pucData[29] = psInst->ucInterfaceControl;
+            pucData[30] = psInst->ucInterfaceData;
+
+            //
+            // This sets the bDataInterface of the Union descriptor to the
+            // Data interface used by this instance.
+            pucData[35] = psInst->ucInterfaceData;
+            break;
+        }
+
+        default:
+        {
+            break;
+        }
+    }
+}
+
+//*****************************************************************************
+//
+// USB non-standard request callback.
+//
+// This function is called by the USB stack whenever any non-standard request
+// is made to the device.  The handler should process any requests that it
+// supports or stall EP0 in any unsupported cases.
+//
+//*****************************************************************************
+static void
+HandleRequests(void *pvInstance, tUSBRequest *pUSBRequest)
+{
+    const tUSBDCDCDevice *psDevice;
+    tCDCSerInstance *psInst;
+    tBoolean bRetcode;
+
+    ASSERT(pvInstance != 0);
+
+    //
+    // Create a device instance pointer.
+    //
+    psDevice = (const tUSBDCDCDevice *)pvInstance;
+
+    //
+    // Get our instance data pointer.
+    //
+    psInst = psDevice->psPrivateCDCSerData;
+
+    //
+    // Only handle requests meant for this interface.
+    //
+    if(pUSBRequest->wIndex != psInst->ucInterfaceControl)
+    {
+        return;
+    }
+
+    //
+    // Handle each of the requests that we expect from the host.
+    //
+    switch(pUSBRequest->bRequest)
+    {
+        case USB_CDC_SEND_ENCAPSULATED_COMMAND:
+        {
+            //
+            // This implementation makes use of no communication protocol so
+            // this request is meaningless.  We stall endpoint 0 if we receive
+            // it.
+            //
+            USBDCDStallEP0(0);
+            break;
+        }
+
+        case USB_CDC_GET_ENCAPSULATED_RESPONSE:
+        {
+            //
+            // This implementation makes use of no communication protocol so
+            // this request is meaningless.  We stall endpoint 0 if we receive
+            // it.
+            //
+            USBDCDStallEP0(0);
+            break;
+        }
+
+        case USB_CDC_SET_COMM_FEATURE:
+        {
+            //
+            // This request is apparently required by an ACM device but does
+            // not appear relevant to a virtual COM port and is never used by
+            // Windows (or, at least, is not seen when using Hyperterminal or
+            // TeraTerm via a Windows virtual COM port).  We stall endpoint 0
+            // to indicate that we do not support the request.
+            //
+            USBDCDStallEP0(0);
+            break;
+        }
+
+        case USB_CDC_GET_COMM_FEATURE:
+        {
+            //
+            // This request is apparently required by an ACM device but does
+            // not appear relevant to a virtual COM port and is never used by
+            // Windows (or, at least, is not seen when using Hyperterminal or
+            // TeraTerm via a Windows virtual COM port).  We stall endpoint 0
+            // to indicate that we do not support the request.
+            //
+            USBDCDStallEP0(0);
+            break;
+        }
+
+        case USB_CDC_CLEAR_COMM_FEATURE:
+        {
+            //
+            // This request is apparently required by an ACM device but does
+            // not appear relevant to a virtual COM port and is never used by
+            // Windows (or, at least, is not seen when using Hyperterminal or
+            // TeraTerm via a Windows virtual COM port).  We stall endpoint 0
+            // to indicate that we do not support the request.
+            //
+            USBDCDStallEP0(0);
+            break;
+        }
+
+        //
+        // Set the serial communication parameters.
+        //
+        case USB_CDC_SET_LINE_CODING:
+        {
+            //
+            // Remember the request we are processing.
+            //
+            psInst->ucPendingRequest = USB_CDC_SET_LINE_CODING;
+
+            //
+            // Set the state to indicate we are waiting for data.
+            //
+            psInst->eCDCRequestState = CDC_STATE_WAIT_DATA;
+
+            //
+            // Now read the payload of the request.  We handle the actual
+            // operation in the data callback once this data is received.
+            //
+            USBDCDRequestDataEP0(0, (unsigned char *)&psInst->sLineCoding,
+                                 sizeof(tLineCoding));
+
+            //
+            // ACK what we have already received.  We must do this after
+            // requesting the data or we get into a race condition where the
+            // data may return before we have set the stack state appropriately
+            // to receive it.
+            //
+            MAP_USBDevEndpointDataAck(psInst->ulUSBBase, USB_EP_0, false);
+
+            break;
+        }
+
+        //
+        // Return the serial communication parameters.
+        //
+        case USB_CDC_GET_LINE_CODING:
+        {
+            tLineCoding sLineCoding;
+
+            //
+            // ACK what we have already received
+            //
+            MAP_USBDevEndpointDataAck(psInst->ulUSBBase, USB_EP_0, false);
+
+            //
+            // Ask the client for the current line coding.
+            //
+            psDevice->pfnControlCallback(psDevice->pvControlCBData,
+                                         USBD_CDC_EVENT_GET_LINE_CODING, 0,
+                                         &sLineCoding);
+
+            //
+            // Send the line coding information back to the host.
+            //
+            USBDCDSendDataEP0(0, (unsigned char *)&sLineCoding,
+                              sizeof(tLineCoding));
+
+            break;
+        }
+
+        case USB_CDC_SET_CONTROL_LINE_STATE:
+        {
+            //
+            // ACK what we have already received
+            //
+            MAP_USBDevEndpointDataAck(psInst->ulUSBBase, USB_EP_0, false);
+
+            //
+            // Set the handshake lines as required.
+            //
+            psInst->usControlLineState = pUSBRequest->wValue;
+
+            //
+            // Remember that we are due to notify the client of a line
+            // state change.
+            //
+            SetDeferredOpFlag(&psInst->usDeferredOpFlags,
+                              CDC_DO_LINE_STATE_CHANGE, true);
+
+            //
+            // See if we can notify now.
+            //
+            bRetcode = CheckAndSendLineStateChange(psDevice);
+
+            //
+            // If we couldn't send the line state change request to the
+            // client, block reception of more data from the host until
+            // previous data is processed and we send the change request.
+            //
+            if(!bRetcode)
+            {
+                psInst->bRxBlocked = true;
+            }
+
+            break;
+        }
+
+        case USB_CDC_SEND_BREAK:
+        {
+            //
+            // ACK what we have already received
+            //
+            MAP_USBDevEndpointDataAck(psInst->ulUSBBase, USB_EP_0, false);
+
+            //
+            // Keep a copy of the requested break duration.
+            //
+            psInst->usBreakDuration = pUSBRequest->wValue;
+
+            //
+            // Remember that we need to send a break request.
+            //
+            SetDeferredOpFlag(&psInst->usDeferredOpFlags,
+                              CDC_DO_SEND_BREAK, true);
+
+            //
+            // Send the break request if all outstanding receive data has been
+            // processed.
+            //
+            bRetcode = CheckAndSendBreak(psDevice, pUSBRequest->wValue);
+
+            //
+            // If we couldn't send the line coding change request to the
+            // client, block reception of more data from the host until
+            // previous data is processed and we send the change request.
+            //
+            if(!bRetcode)
+            {
+                psInst->bRxBlocked = true;
+            }
+
+            break;
+        }
+
+        //
+        // These are valid CDC requests but not ones that an ACM device should
+        // receive.
+        //
+        case USB_CDC_SET_AUX_LINE_STATE:
+        case USB_CDC_SET_HOOK_STATE:
+        case USB_CDC_PULSE_SETUP:
+        case USB_CDC_SEND_PULSE:
+        case USB_CDC_SET_PULSE_TIME:
+        case USB_CDC_RING_AUX_JACK:
+        case USB_CDC_SET_RINGER_PARMS:
+        case USB_CDC_GET_RINGER_PARMS:
+        case USB_CDC_SET_OPERATION_PARMS:
+        case USB_CDC_GET_OPERATION_PARMS:
+        case USB_CDC_SET_LINE_PARMS:
+        case USB_CDC_GET_LINE_PARMS:
+        case USB_CDC_DIAL_DIGITS:
+        case USB_CDC_SET_UNIT_PARAMETER:
+        case USB_CDC_GET_UNIT_PARAMETER:
+        case USB_CDC_CLEAR_UNIT_PARAMETER:
+        case USB_CDC_GET_PROFILE:
+        case USB_CDC_SET_ETHERNET_MULTICAST_FILTERS:
+        case USB_CDC_SET_ETHERNET_POWER_MANAGEMENT_PATTERN_FILTER:
+        case USB_CDC_GET_ETHERNET_POWER_MANAGEMENT_PATTERN_FILTER:
+        case USB_CDC_SET_ETHERNET_PACKET_FILTER:
+        case USB_CDC_GET_ETHERNET_STATISTIC:
+        case USB_CDC_SET_ATM_DATA_FORMAT:
+        case USB_CDC_GET_ATM_DEVICE_STATISTICS:
+        case USB_CDC_SET_ATM_DEFAULT_VC:
+        case USB_CDC_GET_ATM_VC_STATISTICS:
+        {
+            USBDCDStallEP0(0);
+            break;
+        }
+
+        default:
+        {
+            //
+            // This request is not part of the CDC specification.
+            //
+            USBDCDStallEP0(0);
+            break;
+        }
+    }
+}
+
+//*****************************************************************************
+//
+// This function is called by the USB device stack whenever the device is
+// disconnected from the host.
+//
+//*****************************************************************************
+static void
+HandleDisconnect(void *pvInstance)
+{
+    const tUSBDCDCDevice *psCDCDevice;
+    tCDCSerInstance *psInst;
+
+    ASSERT(pvInstance != 0);
+
+    //
+    // Create the instance pointer.
+    //
+    psCDCDevice = (const tUSBDCDCDevice *)pvInstance;
+
+    //
+    // Get a pointer to our instance data.
+    //
+    psInst = psCDCDevice->psPrivateCDCSerData;
+
+    //
+    // If we are not currently connected and we have a control callback,
+    // let the client know we are open for business.
+    //
+    if(psInst->bConnected)
+    {
+        //
+        // Pass the disconnected event to the client.
+        //
+        psCDCDevice->pfnControlCallback(psCDCDevice->pvControlCBData,
+                                        USB_EVENT_DISCONNECTED, 0, (void *)0);
+    }
+
+    //
+    // Remember that we are no longer connected.
+    //
+    psInst->bConnected = false;
+}
+
+//*****************************************************************************
+//
+// This function is called by the USB device stack whenever the bus is put into
+// suspend state.
+//
+//*****************************************************************************
+static void
+HandleSuspend(void *pvInstance)
+{
+    const tUSBDCDCDevice *psCDCDevice;
+
+    ASSERT(pvInstance != 0);
+
+    //
+    // Create the instance pointer.
+    //
+    psCDCDevice = (const tUSBDCDCDevice *)pvInstance;
+
+    //
+    // Pass the event on to the client.
+    //
+    psCDCDevice->pfnControlCallback(psCDCDevice->pvControlCBData,
+                                    USB_EVENT_SUSPEND, 0, (void *)0);
+}
+
+//*****************************************************************************
+//
+// This function is called by the USB device stack whenever the bus is taken
+// out of suspend state.
+//
+//*****************************************************************************
+static void
+HandleResume(void *pvInstance)
+{
+    tUSBDCDCDevice *psCDCDevice;
+
+    ASSERT(pvInstance != 0);
+
+    //
+    // Create the instance pointer.
+    //
+    psCDCDevice = (tUSBDCDCDevice *)pvInstance;
+
+    //
+    // Pass the event on to the client.
+    //
+    psCDCDevice->pfnControlCallback(psCDCDevice->pvControlCBData,
+                                    USB_EVENT_RESUME, 0, (void *)0);
+}
+
+//*****************************************************************************
+//
+// This function is called periodically and provides us with a time reference
+// and method of implementing delayed or time-dependent operations.
+//
+// \param ulIndex is the index of the USB controller for which this tick
+// is being generated.
+// \param ulTimemS is the elapsed time in milliseconds since the last call
+// to this function.
+//
+// \return None.
+//
+//*****************************************************************************
+static void
+CDCTickHandler(void *pvInstance, unsigned long ulTimemS)
+{
+    tBoolean bCanSend;
+    const tUSBDCDCDevice *psDevice;
+    tCDCSerInstance *psInst;
+    unsigned long ulSize;
+
+    ASSERT(pvInstance != 0);
+
+    //
+    // Create the instance pointer.
+    //
+    psDevice = (const tUSBDCDCDevice *)pvInstance;
+
+    //
+    // Get our instance data pointer.
+    //
+    psInst = psDevice->psPrivateCDCSerData;
+
+    //
+    // Is there any outstanding operation that we should try to perform?
+    //
+    if(psInst->usDeferredOpFlags)
+    {
+        //
+        // Yes - we have at least one deferred operation pending.  First check
+        // to see if it is time to turn off a break condition.
+        //
+        if(psInst->usDeferredOpFlags & (1 << CDC_DO_CLEAR_BREAK))
+        {
+            //
+            // Will our break timer expire this time?
+            //
+            if(psInst->usBreakDuration <= ulTimemS)
+            {
+                //
+                // Yes - turn off the break condition.
+                //
+                SendBreak(psDevice, false);
+            }
+            else
+            {
+                //
+                // We have not timed out yet.  Decrement the break timer.
+                //
+                psInst->usBreakDuration -= (unsigned short)ulTimemS;
+            }
+        }
+
+        // Now check to see if the client has any data remaining to be
+        // processed.  This information is needed by the remaining deferred
+        // operations which are waiting for the receive pipe to be emptied
+        // before they can be carried out.
+        //
+        bCanSend = DeviceConsumedAllData(psDevice);
+
+        //
+        // Has all outstanding data been consumed?
+        //
+        if(bCanSend)
+        {
+            //
+            // Yes - go ahead and notify the client of the various things
+            // it has been asked to do while we waited for data to be
+            // consumed.
+            //
+
+            //
+            // Do we need to start sending a break condition?
+            //
+            if(psInst->usDeferredOpFlags & (1 << CDC_DO_SEND_BREAK))
+            {
+                SendBreak(psDevice, true);
+            }
+
+            //
+            // Do we need to set the RTS/DTR states?
+            //
+            if(psInst->usDeferredOpFlags & (1 << CDC_DO_LINE_STATE_CHANGE))
+            {
+                SendLineStateChange(psDevice);
+            }
+
+            //
+            // Do we need to change the line coding parameters?
+            //
+            if(psInst->usDeferredOpFlags & (1 << CDC_DO_LINE_CODING_CHANGE))
+            {
+                SendLineCodingChange(psDevice);
+            }
+
+            //
+            // NOTE: We do not need to handle CDC_DO_SERIAL_STATE_CHANGE here
+            // since this is handled in the transmission complete notification
+            // for the control IN endpoint (ProcessNotificationToHost()).
+            //
+
+            //
+            // If all the deferred operations which caused the receive channel
+            // to be blocked are now handled, we can unblock receive and handle
+            // any packet that is currently waiting to be received.
+            //
+            if(!(psInst->usDeferredOpFlags & RX_BLOCK_OPS))
+            {
+                //
+                // We can remove the receive block.
+                //
+                psInst->bRxBlocked = false;
+            }
+        }
+
+        //
+        // Is the receive channel unblocked?
+        //
+        if(!psInst->bRxBlocked)
+        {
+            //
+            // Do we have a deferred receive waiting
+            //
+            if(psInst->usDeferredOpFlags & (1 << CDC_DO_PACKET_RX))
+            {
+                //
+                // Yes - how big is the waiting packet?
+                //
+                ulSize = MAP_USBEndpointDataAvail(psInst->ulUSBBase,
+                                                  psInst->ucBulkOUTEndpoint);
+
+                // Tell the client that there is a packet waiting for it.
+                //
+                psDevice->pfnRxCallback(psDevice->pvRxCBData,
+                                        USB_EVENT_RX_AVAILABLE, ulSize,
+                                        (void *)0);
+            }
+        }
+    }
+
+    return;
+}
+
+//*****************************************************************************
+//
+//! Initializes CDC device operation when used with a composite device.
+//!
+//! \param ulIndex is the index of the USB controller in use.
+//! \param psCDCDevice points to a structure containing parameters customizing
+//! the operation of the CDC device.
+//!
+//! This call is very similar to USBDCDCInit() except that it is used for
+//! initializing an instance of the serial device for use in a composite device.
+//!
+//! \return Returns NULL on failure or the psCDCDevice pointer on success.
+//
+//*****************************************************************************
+void *
+USBDCDCCompositeInit(unsigned long ulIndex, const tUSBDCDCDevice *psCDCDevice)
+{
+    tCDCSerInstance *psInst;
+    tDeviceDescriptor *psDevDesc;
+
+    //
+    // Check parameter validity.
+    //
+    ASSERT(ulIndex == 0);
+    ASSERT(psCDCDevice);
+    ASSERT(psCDCDevice->psPrivateCDCSerData);
+    ASSERT(psCDCDevice->pfnControlCallback);
+    ASSERT(psCDCDevice->pfnRxCallback);
+    ASSERT(psCDCDevice->pfnTxCallback);
+
+    //
+    // Create an instance pointer to the private data area.
+    //
+    psInst = psCDCDevice->psPrivateCDCSerData;
+
+    //
+    // Set the default endpoint and interface assignments.
+    //
+    psInst->ucBulkINEndpoint = DATA_IN_ENDPOINT;
+    psInst->ucBulkOUTEndpoint = DATA_OUT_ENDPOINT;
+    psInst->ucInterfaceControl = SERIAL_INTERFACE_CONTROL;
+    psInst->ucInterfaceData = SERIAL_INTERFACE_DATA;
+
+    //
+    // By default do not use the interrupt control endpoint.  The single
+    // instance CDC serial device will turn this on in USBDCDCInit();
+    //
+    psInst->ucControlEndpoint = CONTROL_ENDPOINT;
+
+    //
+    // Initialize the workspace in the passed instance structure.
+    //
+    psInst->psConfDescriptor = (tConfigDescriptor *)g_pCDCSerDescriptor;
+    psInst->psDevInfo = &g_sCDCSerDeviceInfo;
+    psInst->ulUSBBase = USB0_BASE;
+    psInst->eCDCRxState = CDC_STATE_UNCONFIGURED;
+    psInst->eCDCTxState = CDC_STATE_UNCONFIGURED;
+    psInst->eCDCInterruptState = CDC_STATE_UNCONFIGURED;
+    psInst->eCDCRequestState = CDC_STATE_UNCONFIGURED;
+    psInst->ucPendingRequest = 0;
+    psInst->usBreakDuration = 0;
+    psInst->usSerialState = 0;
+    psInst->usDeferredOpFlags = 0;
+    psInst->usControlLineState = 0;
+    psInst->bRxBlocked = false;
+    psInst->bControlBlocked = false;
+    psInst->bConnected = false;
+
+    //
+    // Fix up the device descriptor with the client-supplied values.
+    //
+    psDevDesc = (tDeviceDescriptor *)psInst->psDevInfo->pDeviceDescriptor;
+    psDevDesc->idVendor = psCDCDevice->usVID;
+    psDevDesc->idProduct = psCDCDevice->usPID;
+
+    //
+    // Fix up the configuration descriptor with client-supplied values.
+    //
+    psInst->psConfDescriptor->bmAttributes = psCDCDevice->ucPwrAttributes;
+    psInst->psConfDescriptor->bMaxPower =
+                (unsigned char)(psCDCDevice->usMaxPowermA / 2);
+
+    //
+    // Plug in the client's string stable to the device information
+    // structure.
+    //
+    psInst->psDevInfo->ppStringDescriptors = psCDCDevice->ppStringDescriptors;
+    psInst->psDevInfo->ulNumStringDescriptors
+            = psCDCDevice->ulNumStringDescriptors;
+
+    //
+    // Initialize the USB tick module, this will prevent it from being
+    // initialized later in the call to USBDCDInit();
+    //
+    InternalUSBTickInit();
+
+    //
+    // Register our tick handler (this must be done after USBDCDInit).
+    //
+    InternalUSBRegisterTickHandler(USB_TICK_HANDLER_DEVICE,
+                                   CDCTickHandler,
+                                   (void *)psCDCDevice);
+
+    //
+    // Return the pointer to the instance indicating that everything went well.
+    //
+    return((void *)psCDCDevice);
+}
+
+//*****************************************************************************
+//
+//! Initializes CDC device operation for a given USB controller.
+//!
+//! \param ulIndex is the index of the USB controller which is to be
+//! initialized for CDC device operation.
+//! \param psCDCDevice points to a structure containing parameters customizing
+//! the operation of the CDC device.
+//!
+//! An application wishing to make use of a USB CDC communication channel and
+//! appear as a virtual serial port on the host system must call this function
+//! to initialize the USB controller and attach the device to the USB bus.
+//! This function performs all required USB initialization.
+//!
+//! The value returned by this function is the \e psCDCDevice pointer passed
+//! to it if successful.  This pointer must be passed to all later calls to the
+//! CDC class driver to identify the device instance.
+//!
+//! The USB CDC device class driver  offers packet-based transmit and receive
+//! operation.  If the application would rather use block based communication
+//! with transmit and receive buffers, USB buffers on the transmit and receive
+//! channels may be used to offer this functionality.
+//!
+//! Transmit Operation:
+//!
+//! Calls to USBDCDCPacketWrite() must send no more than 64 bytes of data at a
+//! time and may only be made when no other transmission is currently
+//! outstanding.
+//!
+//! Once a packet of data has been acknowledged by the USB host, a
+//! \b USB_EVENT_TX_COMPLETE event is sent to the application callback to
+//! inform it that another packet may be transmitted.
+//!
+//! Receive Operation:
+//!
+//! An incoming USB data packet will result in a call to the application
+//! callback with event \b USB_EVENT_RX_AVAILABLE.  The application must then
+//! call USBDCDCPacketRead(), passing a buffer capable of holding the received
+//! packet to retrieve the data and acknowledge reception to the USB host.  The
+//! size of the received packet may be queried by calling
+//! USBDCDCRxPacketAvailable().
+//!
+//! \note The application must not make any calls to the low level USB Device
+//! API if interacting with USB via the CDC device class API.  Doing so
+//! will cause unpredictable (though almost certainly unpleasant) behavior.
+//!
+//! \return Returns NULL on failure or the psCDCDevice pointer on success.
+//
+//*****************************************************************************
+void *
+USBDCDCInit(unsigned long ulIndex, const tUSBDCDCDevice *psCDCDevice)
+{
+    void *pvRet;
+    tCDCSerInstance *psInst;
+
+    //
+    // Initialize the internal state for this class.
+    //
+    pvRet = USBDCDCCompositeInit(ulIndex, psCDCDevice);
+
+    if(pvRet)
+    {
+        //
+        // Create an instance pointer to the private data area.
+        //
+        psInst = psCDCDevice->psPrivateCDCSerData;
+
+        //
+        // Set the instance data for this device so that USBDCDInit() call can
+        // have the instance data.
+        //
+        psInst->psDevInfo->pvInstance = (void *)psCDCDevice;
+
+        //
+        // Enable the default interrupt control endpoint if this class is not
+        // being used in a composite device.
+        //
+        psInst->ucControlEndpoint = CONTROL_ENDPOINT;
+
+        //
+        // Use the configuration descriptor with the interrupt control endpoint.
+        //
+        psInst->psDevInfo->ppConfigDescriptors = g_pCDCSerConfigDescriptors;
+
+        //
+        // All is well so now pass the descriptors to the lower layer and put
+        // the CDC device on the bus.
+        //
+        USBDCDInit(ulIndex, psInst->psDevInfo);
+    }
+
+    return(pvRet);
+}
+
+//*****************************************************************************
+//
+//! Shuts down the CDC device instance.
+//!
+//! \param pvInstance is the pointer to the device instance structure as returned
+//! by USBDCDCInit().
+//!
+//! This function terminates CDC operation for the instance supplied and
+//! removes the device from the USB bus.  This function should not be called
+//! if the CDC device is part of a composite device and instead the
+//! USBDCompositeTerm() function should be called for the full composite
+//! device.
+//!
+//! Following this call, the \e pvInstance instance should not me used in any
+//! other calls.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDCDCTerm(void *pvInstance)
+{
+    tCDCSerInstance *psInst;
+
+    ASSERT(pvInstance);
+
+    //
+    // Get a pointer to our instance data.
+    //
+    psInst = ((tUSBDCDCDevice *)pvInstance)->psPrivateCDCSerData;
+
+    //
+    // Terminate the requested instance.
+    //
+    USBDCDTerm(USB_BASE_TO_INDEX(psInst->ulUSBBase));
+
+    psInst->ulUSBBase = 0;
+    psInst->psDevInfo = (tDeviceInfo *)0;
+    psInst->psConfDescriptor = (tConfigDescriptor *)0;
+
+    return;
+}
+
+//*****************************************************************************
+//
+//! Sets the client-specific pointer for the control callback.
+//!
+//! \param pvInstance is the pointer to the device instance structure as
+//! returned by USBDCDCInit().
+//! \param pvCBData is the pointer that client wishes to be provided on each
+//! event sent to the control channel callback function.
+//!
+//! The client uses this function to change the callback pointer passed in
+//! the first parameter on all callbacks to the \e pfnControlCallback function
+//! passed on USBDCDCInit().
+//!
+//! If a client wants to make runtime changes in the callback pointer, it must
+//! ensure that the psCDCDevice structure passed to USBDCDCInit() resides in
+//! RAM.  If this structure is in flash, callback pointer changes will not be
+//! possible.
+//!
+//! \return Returns the previous callback pointer that was being used for
+//! this instance's control callback.
+//
+//*****************************************************************************
+void *
+USBDCDCSetControlCBData(void *pvInstance, void *pvCBData)
+{
+    void *pvOldValue;
+
+    ASSERT(pvInstance);
+
+    //
+    // Set the callback pointer for the control channel after remembering the
+    // previous value.
+    //
+    pvOldValue = ((tUSBDCDCDevice *)pvInstance)->pvControlCBData;
+    ((tUSBDCDCDevice *)pvInstance)->pvControlCBData = pvCBData;
+
+    //
+    // Return the previous callback data value.
+    //
+    return(pvOldValue);
+}
+
+//*****************************************************************************
+//
+//! Sets the client-specific data parameter for the receive channel callback.
+//!
+//! \param pvInstance is the pointer to the device instance structure as
+//! returned by USBDCDCInit().
+//! \param pvCBData is the pointer that client wishes to be provided on each
+//! event sent to the receive channel callback function.
+//!
+//! The client uses this function to change the callback pointer passed in
+//! the first parameter on all callbacks to the \e pfnRxCallback function
+//! passed on USBDCDCInit().
+//!
+//! If a client wants to make runtime changes in the callback pointer, it must
+//! ensure that the psCDCDevice structure passed to USBDCDCInit() resides in
+//! RAM.  If this structure is in flash, callback data changes will not be
+//! possible.
+//!
+//! \return Returns the previous callback pointer that was being used for
+//! this instance's receive callback.
+//
+//*****************************************************************************
+void *
+USBDCDCSetRxCBData(void *pvInstance, void *pvCBData)
+{
+    void *pvOldValue;
+
+    ASSERT(pvInstance);
+
+    //
+    // Set the callback data for the receive channel after remembering the
+    // previous value.
+    //
+    pvOldValue = ((tUSBDCDCDevice *)pvInstance)->pvRxCBData;
+    ((tUSBDCDCDevice *)pvInstance)->pvRxCBData = pvCBData;
+
+    //
+    // Return the previous callback pointer.
+    //
+    return(pvOldValue);
+}
+
+//*****************************************************************************
+//
+//! Sets the client-specific data parameter for the transmit callback.
+//!
+//! \param pvInstance is the pointer to the device instance structure as
+//! returned by USBDCDCInit().
+//! \param pvCBData is the pointer that client wishes to be provided on each
+//! event sent to the transmit channel callback function.
+//!
+//! The client uses this function to change the callback pointer passed in
+//! the first parameter on all callbacks to the \e pfnTxCallback function
+//! passed on USBDCDCInit().
+//!
+//! If a client wants to make runtime changes in the callback pointer, it must
+//! ensure that the psCDCDevice structure passed to USBDCDCInit() resides in
+//! RAM.  If this structure is in flash, callback data changes will not be
+//! possible.
+//!
+//! \return Returns the previous callback pointer that was being used for
+//! this instance's transmit callback.
+//
+//*****************************************************************************
+void *
+USBDCDCSetTxCBData(void *pvInstance, void *pvCBData)
+{
+    void *pvOldValue;
+
+    ASSERT(pvInstance);
+
+    //
+    // Set the callback data for the transmit channel after remembering the
+    // previous value.
+    //
+    pvOldValue = ((tUSBDCDCDevice *)pvInstance)->pvTxCBData;
+    ((tUSBDCDCDevice *)pvInstance)->pvTxCBData = pvCBData;
+
+    //
+    // Return the previous callback pointer.
+    //
+    return(pvOldValue);
+}
+
+//*****************************************************************************
+//
+//! Transmits a packet of data to the USB host via the CDC data interface.
+//!
+//! \param pvInstance is the pointer to the device instance structure as
+//! returned by USBDCDCInit().
+//! \param pcData points to the first byte of data which is to be transmitted.
+//! \param ulLength is the number of bytes of data to transmit.
+//! \param bLast indicates whether more data is to be written before a packet
+//! should be scheduled for transmission.  If \b true, the client will make
+//! a further call to this function.  If \b false, no further call will be
+//! made and the driver should schedule transmission of a short packet.
+//!
+//! This function schedules the supplied data for transmission to the USB
+//! host in a single USB packet.  If no transmission is currently ongoing
+//! the data is immediately copied to the relevant USB endpoint FIFO.  If the
+//! \e bLast parameter is \b true, the newly written packet is then scheduled
+//! for transmission.  Whenever a USB packet is acknowledged by the host, a
+//! USB_EVENT_TX_COMPLETE event will be sent to the application transmit
+//! callback indicating that more data can now be transmitted.
+//!
+//! The maximum value for ulLength is 64 bytes (the maximum USB packet size
+//! for the bulk endpoints in use by CDC).  Attempts to send more data than
+//! this will result in a return code of 0 indicating that the data cannot be
+//! sent.
+//!
+//! \return Returns the number of bytes actually sent.  At this level, this
+//! will either be the number of bytes passed (if less than or equal to the
+//! maximum packet size for the USB endpoint in use and no outstanding
+//! transmission ongoing) or 0 to indicate a failure.
+//
+//*****************************************************************************
+unsigned long
+USBDCDCPacketWrite(void *pvInstance, unsigned char *pcData,
+                   unsigned long ulLength, tBoolean bLast)
+{
+    tCDCSerInstance *psInst;
+    long lRetcode;
+
+    ASSERT(pvInstance);
+
+    //
+    // Get our instance data pointer
+    //
+    psInst = ((tUSBDCDCDevice *)pvInstance)->psPrivateCDCSerData;
+
+    //
+    // Can we send the data provided?
+    //
+    if((ulLength > DATA_IN_EP_MAX_SIZE) ||
+       (psInst->eCDCTxState != CDC_STATE_IDLE))
+    {
+        //
+        // Either the packet was too big or we are in the middle of sending
+        // another packet.  Return 0 to indicate that we can't send this data.
+        //
+        return(0);
+    }
+
+    //
+    // Copy the data into the USB endpoint FIFO.
+    //
+    lRetcode = MAP_USBEndpointDataPut(psInst->ulUSBBase,
+                                      psInst->ucBulkINEndpoint, pcData,
+                                      ulLength);
+
+    //
+    // Did we copy the data successfully?
+    //
+    if(lRetcode != -1)
+    {
+        //
+        // Remember how many bytes we sent.
+        //
+        psInst->usLastTxSize += (unsigned short)ulLength;
+
+        //
+        // If this is the last call for this packet, schedule transmission.
+        //
+        if(bLast)
+        {
+            //
+            // Send the packet to the host if we have received all the data we
+            // can expect for this packet.
+            //
+            psInst->eCDCTxState = CDC_STATE_WAIT_DATA;
+            lRetcode = MAP_USBEndpointDataSend(psInst->ulUSBBase,
+                                               psInst->ucBulkINEndpoint,
+                                               USB_TRANS_IN);
+        }
+    }
+
+    //
+    // Did an error occur while trying to send the data?
+    //
+    if(lRetcode != -1)
+    {
+        //
+        // No - tell the caller we sent all the bytes provided.
+        //
+        return(ulLength);
+    }
+    else
+    {
+        //
+        // Yes - tell the caller we couldn't send the data.
+        //
+        return(0);
+    }
+}
+
+//*****************************************************************************
+//
+//! Reads a packet of data received from the USB host via the CDC data
+//! interface.
+//!
+//! \param pvInstance is the pointer to the device instance structure as
+//! returned by USBDCDCInit().
+//! \param pcData points to a buffer into which the received data will be
+//! written.
+//! \param ulLength is the size of the buffer pointed to by pcData.
+//! \param bLast indicates whether the client will make a further call to
+//! read additional data from the packet.
+//!
+//! This function reads up to ulLength bytes of data received from the USB
+//! host into the supplied application buffer.
+//!
+//! \note The \e bLast parameter is ignored in this implementation since the
+//! end of a packet can be determined without relying upon the client to
+//! provide this information.
+//!
+//! \return Returns the number of bytes of data read.
+//
+//*****************************************************************************
+unsigned long
+USBDCDCPacketRead(void *pvInstance, unsigned char *pcData,
+                  unsigned long ulLength, tBoolean bLast)
+{
+    unsigned long ulEPStatus, ulCount, ulPkt;
+    tCDCSerInstance *psInst;
+    long lRetcode;
+
+    ASSERT(pvInstance);
+
+    //
+    // Get our instance data pointer
+    //
+    psInst = ((tUSBDCDCDevice *)pvInstance)->psPrivateCDCSerData;
+
+    //
+    // Does the relevant endpoint FIFO have a packet waiting for us?
+    //
+    ulEPStatus = MAP_USBEndpointStatus(psInst->ulUSBBase,
+                                       psInst->ucBulkOUTEndpoint);
+
+    if(ulEPStatus & USB_DEV_RX_PKT_RDY)
+    {
+        //
+        // If receive is currently blocked or the buffer we were passed is
+        // (potentially) too small, set the flag telling us that we have a
+        // packet waiting but return 0.
+        //
+        if(psInst->bRxBlocked || psInst->bControlBlocked)
+        {
+            SetDeferredOpFlag(&psInst->usDeferredOpFlags,
+                              CDC_DO_PACKET_RX, true);
+            return(0);
+        }
+        else
+        {
+            //
+            // It is OK to receive the new packet.  How many bytes are
+            // available for us to receive?
+            //
+            ulPkt = MAP_USBEndpointDataAvail(psInst->ulUSBBase,
+                                             psInst->ucBulkOUTEndpoint);
+
+            //
+            // Get as much data as we can.
+            //
+            ulCount = ulLength;
+            lRetcode = MAP_USBEndpointDataGet(psInst->ulUSBBase,
+                                              psInst->ucBulkOUTEndpoint,
+                                              pcData, &ulCount);
+
+            //
+            // Did we read the last of the packet data?
+            //
+            if(ulCount == ulPkt)
+            {
+                //
+                // Clear the endpoint status so that we know no packet is
+                // waiting.
+                //
+                MAP_USBDevEndpointStatusClear(psInst->ulUSBBase,
+                                              psInst->ucBulkOUTEndpoint,
+                                              ulEPStatus);
+
+                //
+                // Acknowledge the data, thus freeing the host to send the
+                // next packet.
+                //
+                MAP_USBDevEndpointDataAck(psInst->ulUSBBase,
+                                          psInst->ucBulkOUTEndpoint,
+                                          true);
+
+                //
+                // Clear the flag we set to indicate that a packet read is
+                // pending.
+                //
+                SetDeferredOpFlag(&psInst->usDeferredOpFlags,
+                                  CDC_DO_PACKET_RX, false);
+
+            }
+
+            //
+            // If all went well, tell the caller how many bytes they got.
+            //
+            if(lRetcode != -1)
+            {
+                return(ulCount);
+            }
+        }
+    }
+
+    //
+    // No packet was available or an error occurred while reading so tell
+    // the caller no bytes were returned.
+    //
+    return(0);
+}
+
+//*****************************************************************************
+//
+//! Returns the number of free bytes in the transmit buffer.
+//!
+//! \param pvInstance is the pointer to the device instance structure as
+//! returned by USBDCDCInit().
+//!
+//! This function returns the maximum number of bytes that can be passed on a
+//! call to USBDCDCPacketWrite and accepted for transmission.  The value
+//! returned will be the maximum USB packet size (64) if no transmission is
+//! currently outstanding or 0 if a transmission is in progress.
+//!
+//! \return Returns the number of bytes available in the transmit buffer.
+//
+//*****************************************************************************
+unsigned long
+USBDCDCTxPacketAvailable(void *pvInstance)
+{
+    tCDCSerInstance *psInst;
+
+    ASSERT(pvInstance);
+
+    //
+    // Get our instance data pointer.
+    //
+    psInst = ((tUSBDCDCDevice *)pvInstance)->psPrivateCDCSerData;
+
+    //
+    // Do we have a packet transmission currently ongoing?
+    //
+    if(psInst->eCDCTxState != CDC_STATE_IDLE)
+    {
+        //
+        // We are not ready to receive a new packet so return 0.
+        //
+        return(0);
+    }
+    else
+    {
+        //
+        // We can receive a packet so return the max packet size for the
+        // relevant endpoint.
+        //
+        return(DATA_IN_EP_MAX_SIZE);
+    }
+}
+
+//*****************************************************************************
+//
+//! Determines whether a packet is available and, if so, the size of the
+//! buffer required to read it.
+//!
+//! \param pvInstance is the pointer to the device instance structure as
+//! returned by USBDCDCInit().
+//!
+//! This function may be used to determine if a received packet remains to be
+//! read and allows the application to determine the buffer size needed to
+//! read the data.
+//!
+//! \return Returns 0 if no received packet remains unprocessed or the
+//! size of the packet if a packet is waiting to be read.
+//
+//*****************************************************************************
+unsigned long
+USBDCDCRxPacketAvailable(void *pvInstance)
+{
+    unsigned long ulEPStatus;
+    unsigned long ulSize;
+    tCDCSerInstance *psInst;
+
+    ASSERT(pvInstance);
+
+    //
+    // Get our instance data pointer
+    //
+    psInst = ((tUSBDCDCDevice *)pvInstance)->psPrivateCDCSerData;
+
+    //
+    // If receive is currently blocked, return 0.
+    //
+    if(psInst->bRxBlocked || psInst->bControlBlocked)
+    {
+        return(0);
+    }
+
+    //
+    // Does the relevant endpoint FIFO have a packet waiting for us?
+    //
+    ulEPStatus = MAP_USBEndpointStatus(psInst->ulUSBBase,
+                                       psInst->ucBulkOUTEndpoint);
+
+    if(ulEPStatus & USB_DEV_RX_PKT_RDY)
+    {
+        //
+        // Yes - a packet is waiting.  How big is it?
+        //
+        ulSize = MAP_USBEndpointDataAvail(psInst->ulUSBBase,
+                                          psInst->ucBulkOUTEndpoint);
+
+        return(ulSize);
+    }
+    else
+    {
+        //
+        // There is no packet waiting to be received.
+        //
+        return(0);
+    }
+}
+
+//*****************************************************************************
+//
+//! Informs the CDC module of changes in the serial control line states or
+//! receive error conditions.
+//!
+//! \param pvInstance is the pointer to the device instance structure as
+//! returned by USBDCDCInit().
+//! \param usState indicates the states of the various control lines and
+//! any receive errors detected.  Bit definitions are as for the USB CDC
+//! SerialState asynchronous notification and are defined in header file
+//! usbcdc.h.
+//!
+//! The application should call this function whenever the state of any of
+//! the incoming RS232 handshake signals changes or in response to a receive
+//! error or break condition.  The usState parameter is the ORed combination
+//! of the following flags with each flag indicating the presence of that
+//! condition.
+//!
+//! - USB_CDC_SERIAL_STATE_OVERRUN
+//! - USB_CDC_SERIAL_STATE_PARITY
+//! - USB_CDC_SERIAL_STATE_FRAMING
+//! - USB_CDC_SERIAL_STATE_RING_SIGNAL
+//! - USB_CDC_SERIAL_STATE_BREAK
+//! - USB_CDC_SERIAL_STATE_TXCARRIER
+//! - USB_CDC_SERIAL_STATE_RXCARRIER
+//!
+//! This function should be called only when the state of any flag changes.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDCDCSerialStateChange(void *pvInstance, unsigned short usState)
+{
+    tCDCSerInstance *psInst;
+
+    ASSERT(pvInstance);
+
+    //
+    // Get our instance data pointer
+    //
+    psInst = ((tUSBDCDCDevice *)pvInstance)->psPrivateCDCSerData;
+
+    //
+    // Add the newly reported state bits to the current collection.  We do this
+    // in case two state changes occur back-to-back before the first has been
+    // notified.  There are two distinct types of signals that we report here
+    // and we deal with them differently:
+    //
+    // 1.  Errors (overrun, parity, framing error) are ORed together so that
+    //     any reported error is sent on the next notification.
+    // 2.  Signal line states (RI, break, TX carrier, RX carrier) always
+    //     report the last state notified to us.  The implementation here will
+    //     send an interrupt showing the last state but, if two state changes
+    //     occur very quickly, the host may receive a notification containing
+    //     the same state that was last reported (in other words, a short pulse
+    //     will be lost).  It would be possible to reduce the likelihood of
+    //     this happening by building a queue of state changes and sending
+    //     these in order but you are left with exactly the same problem if the
+    //     queue fills up.  For now, therefore, we run the risk of missing very
+    //     short pulses on the "steady-state" signal lines.
+    //
+    psInst->usSerialState |= (usState & USB_CDC_SERIAL_ERRORS);
+    psInst->usSerialState &= ~USB_CDC_SERIAL_ERRORS;
+    psInst->usSerialState |= (usState & ~USB_CDC_SERIAL_ERRORS);
+
+    //
+    // Set the flag indicating that a serial state change is to be sent.
+    //
+    SetDeferredOpFlag(&psInst->usDeferredOpFlags, CDC_DO_SERIAL_STATE_CHANGE,
+                      true);
+
+    //
+    // Can we send the state change immediately?
+    //
+    if(psInst->eCDCInterruptState == CDC_STATE_IDLE)
+    {
+        //
+        // The interrupt channel is free so send the notification immediately.
+        // If we can't do this, the tick timer will catch this next time
+        // round.
+        //
+        psInst->eCDCInterruptState = CDC_STATE_WAIT_DATA;
+        SendSerialState(pvInstance);
+    }
+
+    return;
+}
+
+//*****************************************************************************
+//
+//! Reports the device power status (bus- or self-powered) to the USB library.
+//!
+//! \param pvInstance is the pointer to the CDC device instance structure.
+//! \param ucPower indicates the current power status, either \b
+//! USB_STATUS_SELF_PWR or \b USB_STATUS_BUS_PWR.
+//!
+//! Applications which support switching between bus- or self-powered
+//! operation should call this function whenever the power source changes
+//! to indicate the current power status to the USB library.  This information
+//! is required by the USB library to allow correct responses to be provided
+//! when the host requests status from the device.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDCDCPowerStatusSet(void *pvInstance, unsigned char ucPower)
+{
+    ASSERT(pvInstance);
+
+    //
+    // Pass the request through to the lower layer.
+    //
+    USBDCDPowerStatusSet(0, ucPower);
+}
+
+//*****************************************************************************
+//
+//! Requests a remote wakeup to resume communication when in suspended state.
+//!
+//! \param pvInstance is the pointer to the CDC device instance structure.
+//!
+//! When the bus is suspended, an application which supports remote wakeup
+//! (advertised to the host via the config descriptor) may call this function
+//! to initiate remote wakeup signaling to the host.  If the remote wakeup
+//! feature has not been disabled by the host, this will cause the bus to
+//! resume operation within 20mS.  If the host has disabled remote wakeup,
+//! \b false will be returned to indicate that the wakeup request was not
+//! successful.
+//!
+//! \return Returns \b true if the remote wakeup is not disabled and the
+//! signaling was started or \b false if remote wakeup is disabled or if
+//! signaling is currently ongoing following a previous call to this function.
+//
+//*****************************************************************************
+tBoolean
+USBDCDCRemoteWakeupRequest(void *pvInstance)
+{
+    ASSERT(pvInstance);
+
+    //
+    // Pass the request through to the lower layer.
+    //
+    return(USBDCDRemoteWakeupRequest(0));
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/src/platform/lm3s/usblib/device/usbdcdc.h b/src/platform/lm3s/usblib/device/usbdcdc.h
new file mode 100755
index 00000000..bc7b4582
--- /dev/null
+++ b/src/platform/lm3s/usblib/device/usbdcdc.h
@@ -0,0 +1,353 @@
+//*****************************************************************************
+//
+// usbdcdc.h - USBLib support for generic CDC ACM (serial) device.
+//
+// Copyright (c) 2008-2011 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 7611 of the Stellaris USB Library.
+//
+//*****************************************************************************
+
+#ifndef __USBDCDC_H__
+#define __USBDCDC_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+//! \addtogroup cdc_device_class_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// PRIVATE
+//
+// The first few sections of this header are private defines that are used by
+// the USB CDC Serial code and are here only to help with the application
+// allocating the correct amount of memory for the CDC Serial device code.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// PRIVATE
+//
+// This enumeration holds the various states that the device can be in during
+// normal operation.
+//
+//*****************************************************************************
+typedef enum
+{
+    //
+    // Unconfigured.
+    //
+    CDC_STATE_UNCONFIGURED,
+
+    //
+    // No outstanding transaction remains to be completed.
+    //
+    CDC_STATE_IDLE,
+
+    //
+    // Waiting on completion of a send or receive transaction.
+    //
+    CDC_STATE_WAIT_DATA,
+
+    //
+    // Waiting for client to process data.
+    //
+    CDC_STATE_WAIT_CLIENT
+}
+tCDCState;
+
+//*****************************************************************************
+//
+// PRIVATE
+//
+// This structure defines the private instance data and state variables for the
+// CDC Serial device.  The memory for this structure is pointed to by the
+// psPrivateCDCSerData field in the tUSBDCDCDevice structure passed on
+// USBDCDCInit().
+//
+//*****************************************************************************
+typedef struct
+{
+    unsigned long ulUSBBase;
+    tDeviceInfo *psDevInfo;
+    tConfigDescriptor *psConfDescriptor;
+    volatile tCDCState eCDCRxState;
+    volatile tCDCState eCDCTxState;
+    volatile tCDCState eCDCRequestState;
+    volatile tCDCState eCDCInterruptState;
+    volatile unsigned char ucPendingRequest;
+    unsigned short usBreakDuration;
+    unsigned short usControlLineState;
+    unsigned short usSerialState;
+    volatile unsigned short usDeferredOpFlags;
+    unsigned short usLastTxSize;
+    tLineCoding sLineCoding;
+    volatile tBoolean bRxBlocked;
+    volatile tBoolean bControlBlocked;
+    volatile tBoolean bConnected;
+    unsigned char ucControlEndpoint;
+    unsigned char ucBulkINEndpoint;
+    unsigned char ucBulkOUTEndpoint;
+    unsigned char ucInterfaceControl;
+    unsigned char ucInterfaceData;
+}
+tCDCSerInstance;
+
+
+#ifndef DEPRECATED
+//*****************************************************************************
+//
+// The number of bytes of workspace required by the CDC device class driver.
+// The client must provide a block of RAM of at least this size in the
+// psPrivateCDCSerData field of the tUSBCDCDevice structure passed on
+// USBDCDCInit().
+//
+// This value is deprecated and should not be used, any new code should just
+// pass in a tUSBCDCDevice structure in the psPrivateCDCSerData field.
+//
+//*****************************************************************************
+#define USB_CDCSER_WORKSPACE_SIZE (sizeof(tCDCSerInstance))
+#endif
+
+//*****************************************************************************
+//
+// The following defines are used when working with composite devices.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! The size of the memory that should be allocated to create a configuration
+//! descriptor for a single instance of the USB Serial CDC Device.
+//! This does not include the configuration descriptor which is automatically
+//! ignored by the composite device class.
+//
+// For reference this is sizeof(g_pIADSerDescriptor) +
+// sizeof(g_pCDCSerCommInterface) + sizeof(g_pCDCSerDataInterface)
+//
+//*****************************************************************************
+#define COMPOSITE_DCDC_SIZE     (8 + 35 + 23)
+
+//*****************************************************************************
+//
+// CDC-specific events These events are provided to the application in the
+// \e ulMsg parameter of the tUSBCallback function.
+//
+//*****************************************************************************
+
+//
+//! The host requests that the device send a BREAK condition on its
+//! serial communication channel.  The BREAK should remain active until
+//! a USBD_CDC_EVENT_CLEAR_BREAK event is received.
+//
+#define USBD_CDC_EVENT_SEND_BREAK (USBD_CDC_EVENT_BASE + 0)
+
+//
+//! The host requests that the device stop sending a BREAK condition on its
+//! serial communication channel.
+//
+#define USBD_CDC_EVENT_CLEAR_BREAK (USBD_CDC_EVENT_BASE + 1)
+
+//
+//! The host requests that the device set the RS232 signaling lines to
+//! a particular state.  The ulMsgValue parameter contains the RTS and
+//! DTR control line states as defined in table 51 of the USB CDC class
+//! definition and is a combination of the following values:
+//!
+//! (RTS) USB_CDC_DEACTIVATE_CARRIER or USB_CDC_ACTIVATE_CARRIER
+//! (DTR) USB_CDC_DTE_NOT_PRESENT or USB_CDC_DTE_PRESENT
+//
+#define USBD_CDC_EVENT_SET_CONTROL_LINE_STATE (USBD_CDC_EVENT_BASE + 2)
+
+//
+//! The host requests that the device set the RS232 communication
+//! parameters.  The pvMsgData parameter points to a tLineCoding structure
+//! defining the required number of bits per character, parity mode,
+//! number of stop bits and the baud rate.
+//
+#define USBD_CDC_EVENT_SET_LINE_CODING (USBD_CDC_EVENT_BASE + 3)
+
+//
+//! The host is querying the current RS232 communication parameters.  The
+//! pvMsgData parameter points to a tLineCoding structure that the
+//! application must fill with the current settings prior to returning
+//! from the callback.
+//
+#define USBD_CDC_EVENT_GET_LINE_CODING (USBD_CDC_EVENT_BASE + 4)
+
+//*****************************************************************************
+//
+//! The structure used by the application to define operating parameters for
+//! the CDC device.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! The vendor ID that this device is to present in the device descriptor.
+    //
+    unsigned short usVID;
+
+    //
+    //! The product ID that this device is to present in the device descriptor.
+    //
+    unsigned short usPID;
+
+    //
+    //! The maximum power consumption of the device, expressed in milliamps.
+    //
+    unsigned short usMaxPowermA;
+
+    //
+    //! Indicates whether the device is self- or bus-powered and whether or not
+    //! it supports remote wakeup.  Valid values are USB_CONF_ATTR_SELF_PWR or
+    //! USB_CONF_ATTR_BUS_PWR, optionally ORed with USB_CONF_ATTR_RWAKE.
+    //
+    unsigned char ucPwrAttributes;
+
+    //
+    //! A pointer to the callback function which will be called to notify
+    //! the application of all asynchronous control events related to the
+    //! operation of the device.
+    //
+    tUSBCallback pfnControlCallback;
+
+    //
+    //! A client-supplied pointer which will be sent as the first
+    //! parameter in all calls made to the control channel callback,
+    //! pfnControlCallback.
+    //
+    void *pvControlCBData;
+
+    //
+    //! A pointer to the callback function which will be called to notify
+    //! the application of events related to the device's data receive channel.
+    //
+    tUSBCallback pfnRxCallback;
+
+    //
+    //! A client-supplied pointer which will be sent as the first
+    //! parameter in all calls made to the receive channel callback,
+    //! pfnRxCallback.
+    //
+    void *pvRxCBData;
+
+    //
+    //! A pointer to the callback function which will be called to notify
+    //! the application of events related to the device's data transmit
+    //! channel.
+    //
+    tUSBCallback pfnTxCallback;
+
+    //
+    //! A client-supplied pointer which will be sent as the first
+    //! parameter in all calls made to the transmit channel callback,
+    //! pfnTxCallback.
+    //
+    void *pvTxCBData;
+
+    //
+    //! A pointer to the string descriptor array for this device.  This array
+    //! must contain the following string descriptor pointers in this order.
+    //! Language descriptor, Manufacturer name string (language 1), Product
+    //! name string (language 1), Serial number string (language 1),
+    //! Control interface description string (language 1), Configuration
+    //! description string (language 1).
+    //!
+    //! If supporting more than 1 language, the strings for indices 1 through 5
+    //! must be repeated for each of the other languages defined in the
+    //! language descriptor.
+    //
+    const unsigned char * const *ppStringDescriptors;
+
+    //
+    //! The number of descriptors provided in the ppStringDescriptors
+    //! array.  This must be 1 + (5 * number of supported languages).
+    //
+    unsigned long ulNumStringDescriptors;
+
+    //
+    //! A pointer to the private instance data for this device.  This memory
+    //! must remain accessible for as long as the CDC device is in use and must
+    //! not be modified by any code outside the CDC class driver.
+    //
+    tCDCSerInstance *psPrivateCDCSerData;
+}
+tUSBDCDCDevice;
+
+extern tDeviceInfo g_sCDCSerDeviceInfo;
+
+//*****************************************************************************
+//
+// API Function Prototypes
+//
+//*****************************************************************************
+extern void * USBDCDCCompositeInit(unsigned long ulIndex,
+                                   const tUSBDCDCDevice *psCDCDevice);
+extern void *USBDCDCInit(unsigned long ulIndex,
+                         const tUSBDCDCDevice *psCDCDevice);
+extern void USBDCDCTerm(void *pvInstance);
+extern void *USBDCDCSetControlCBData(void *pvInstance, void *pvCBData);
+extern void *USBDCDCSetRxCBData(void *pvInstance, void *pvCBData);
+extern void *USBDCDCSetTxCBData(void *pvInstance, void *pvCBData);
+extern unsigned long USBDCDCPacketWrite(void *pvInstance,
+                                        unsigned char *pcData,
+                                        unsigned long ulLength,
+                                        tBoolean bLast);
+extern unsigned long USBDCDCPacketRead(void *pvInstance,
+                                       unsigned char *pcData,
+                                       unsigned long ulLength,
+                                       tBoolean bLast);
+extern unsigned long USBDCDCTxPacketAvailable(void *pvInstance);
+extern unsigned long USBDCDCRxPacketAvailable(void *pvInstance);
+extern void USBDCDCSerialStateChange(void *pvInstance,
+                                     unsigned short usState);
+extern void USBDCDCPowerStatusSet(void *pvInstance, unsigned char ucPower);
+extern tBoolean USBDCDCRemoteWakeupRequest(void *pvInstance);
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __USBDCDC_H__
diff --git a/src/platform/lm3s/usblib/device/usbdcdesc.c b/src/platform/lm3s/usblib/device/usbdcdesc.c
new file mode 100755
index 00000000..a26a84d7
--- /dev/null
+++ b/src/platform/lm3s/usblib/device/usbdcdesc.c
@@ -0,0 +1,658 @@
+//*****************************************************************************
+//
+// usbcdesc.c - Config descriptor parsing functions.
+//
+// Copyright (c) 2007-2011 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 7611 of the Stellaris USB Library.
+//
+//*****************************************************************************
+
+#include "inc/hw_types.h"
+#include "driverlib/debug.h"
+#include "driverlib/usb.h"
+#include "usblib/usblib.h"
+#include "usblib/device/usbdevice.h"
+
+//*****************************************************************************
+//
+// The functions in this file mirror the descriptor parsing APIs available
+// in usblib.h but parse config descriptors defined in terms of a list of
+// sections rather than as a single block of descriptor data.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup device_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \internal
+//!
+//! Walk to the next descriptor after the supplied one within a section-based
+//! config descriptor.
+//!
+//! \param psConfig points to the header structure for the configuration
+//! descriptor which contains \e psDesc.
+//! \param pulSec points to a variable containing the section within \e
+//! psConfig which contains \e psDesc.
+//! \param psDesc points to the descriptor that we want to step past.
+//!
+//! This function walks forward one descriptor within a config descriptor.  The
+//! value returned is a pointer to the header of the next descriptor after the
+//! descriptor supplied in \e psDesc.  If the next descriptor is in the next
+//! section, \e *pulSec will be incremented accordlingly.
+//!
+//! \return Returns a pointer to the next descriptor in the config descrptor.
+//
+//*****************************************************************************
+static tDescriptorHeader *
+NextConfigDescGet(const tConfigHeader *psConfig, unsigned long *pulSec,
+                  tDescriptorHeader *psDesc)
+{
+    //
+    // Determine where the next descriptor after the supplied one should be
+    // assuming it is within the current section.
+    //
+    psDesc = NEXT_USB_DESCRIPTOR(psDesc);
+
+    //
+    // Did we run off the end of the section?
+    //
+    if((unsigned char *)psDesc >= (psConfig->psSections[*pulSec]->pucData +
+                                           psConfig->psSections[*pulSec]->ucSize))
+    {
+        //
+        // Yes - move to the next section.
+        //
+        (*pulSec)++;
+
+        //
+        // Are we still within the config descriptor?
+        //
+        if(*pulSec < psConfig->ucNumSections)
+        {
+            //
+            // Yes - the new descriptor is at the start of the new section.
+            //
+            psDesc =
+                (tDescriptorHeader *)psConfig->psSections[*pulSec]->pucData;
+        }
+        else
+        {
+            //
+            // No - we ran off the end of the descriptor so return NULL.
+            //
+            psDesc = (tDescriptorHeader *)0;
+        }
+    }
+
+    //
+    // Return the new descriptor pointer.
+    //
+    return(psDesc);
+}
+
+//*****************************************************************************
+//
+//! \internal
+//!
+//! Returns a pointer to the n-th interface descriptor in a config descriptor
+//! with the supplied interface number.
+//!
+//! \param psConfig points to the header structure for the config descriptor
+//! that is to be searched.
+//! \param ucInterfaceNumber is the interface number of the descriptor that is
+//! being queried.
+//! \param ulIndex is the zero based index of the descriptor to return.
+//! \param pulSection points to storage which will be written with the index
+//! of the section containing the returned descriptor.
+//!
+//! This function returns a pointer to the n-th interface descriptor in the
+//! supplied configuration which has the requested interface number.  It may be
+//! used by a client to retrieve the descriptors for each alternate setting
+//! of a given interface within the configuration passed.
+//!
+//! \return Returns a pointer to the n-th interface descriptor with interface
+//! number as specified or NULL of this descriptor does not exist.
+//
+//*****************************************************************************
+static tInterfaceDescriptor *
+ConfigAlternateInterfaceGet(const tConfigHeader *psConfig,
+                            unsigned char ucInterfaceNumber,
+                            unsigned long ulIndex,
+                            unsigned long *pulSection)
+{
+    tDescriptorHeader *psDescCheck;
+    unsigned long ulCount;
+    unsigned long ulSec;
+
+    //
+    // Set up for our descriptor counting loop.
+    //
+    psDescCheck = (tDescriptorHeader *)psConfig->psSections[0]->pucData;
+    ulCount = 0;
+    ulSec = 0;
+
+    //
+    // Keep looking through the supplied data until we reach the end.
+    //
+    while(psDescCheck)
+    {
+        //
+        // Does this descriptor match the type passed (if a specific type
+        // has been specified)?
+        //
+        if((psDescCheck->bDescriptorType == USB_DTYPE_INTERFACE) &&
+            (((tInterfaceDescriptor *)psDescCheck)->bInterfaceNumber ==
+             ucInterfaceNumber))
+        {
+            //
+            // This is an interface descriptor for interface ucInterfaceNumber.
+            // Determine if this is the n-th one we have found and, if so,
+            // return its pointer.
+            //
+            if(ulCount == ulIndex)
+            {
+                //
+                // Found it - return the pointer and section number.
+                //
+                *pulSection = ulSec;
+                return((tInterfaceDescriptor *)psDescCheck);
+            }
+
+            //
+            // Increment our count of matching descriptors found and go back
+            // to look for another since we have not yet reached the n-th
+            // match.
+            //
+            ulCount++;
+        }
+
+        //
+        // Move on to the next descriptor.
+        //
+        psDescCheck = NextConfigDescGet(psConfig, &ulSec, psDescCheck);
+    }
+
+    //
+    // If we drop out the end of the loop, we did not find the requested
+    // descriptor so return NULL.
+    //
+    return((tInterfaceDescriptor *)0);
+}
+
+//*****************************************************************************
+//
+//! \internal
+//!
+//! Determines the total length of a config descriptor defined in terms of a
+//! collection of concatenated sections.
+//!
+//! \param psConfig points to the header structure for the configuration
+//! descriptor whose size is to be determined.
+//!
+//! \return Returns the number of bytes in the config descriptor will result
+//! from concatenating the required sections.
+//
+//*****************************************************************************
+unsigned long
+USBDCDConfigDescGetSize(const tConfigHeader *psConfig)
+{
+    unsigned long ulLoop;
+    unsigned long ulLen;
+
+    ulLen = 0;
+
+    //
+    // Determine the size of the whole descriptor by adding the sizes of
+    // each section which will be concatenated to produce it.
+    //
+    for(ulLoop = 0; ulLoop < psConfig->ucNumSections; ulLoop++)
+    {
+        ulLen += psConfig->psSections[ulLoop]->ucSize;
+    }
+
+    return(ulLen);
+}
+
+//*****************************************************************************
+//
+//! \internal
+//!
+//! Determines the number of individual descriptors of a particular type within
+//! a supplied configuration descriptor.
+//!
+//! \param psConfig points to the header structure for the configuration
+//! descriptor that is to be searched.
+//! \param ulType identifies the type of descriptor that is to be counted.  If
+//! the value is \b USB_DESC_ANY, the function returns the total number of
+//! descriptors regardless of type.
+//!
+//! This function can be used to count the number of descriptors of a
+//! particular type within a configuration descriptor.  The caller can provide
+//! a specific type value which the function matches against the second byte
+//! of each descriptor or, alternatively, can specify \b USB_DESC_ANY to have
+//! the function count all descriptors regardless of their type.
+//!
+//! The search performed by this function traverses through the list of
+//! sections comprising the configuration descriptor.  Note that the similar
+//! top-level function, USBDescGetNum(), searches through a single, contiguous
+//! block of data to perform the same enumeration.
+//!
+//! \return Returns the number of descriptors found in the supplied block of
+//! data.
+//
+//*****************************************************************************
+unsigned long
+USBDCDConfigDescGetNum(const tConfigHeader *psConfig, unsigned long ulType)
+{
+    unsigned long ulSection;
+    unsigned long ulNumDescs;
+
+    //
+    // Initialize our counts.
+    //
+    ulNumDescs = 0;
+
+    //
+    // Determine the number of descriptors of the given type in each of the
+    // sections comprising the config descriptor.  Note that this assumes each
+    // section contains only whole descriptors!
+    //
+    for(ulSection = 0; ulSection < (unsigned long)psConfig->ucNumSections;
+        ulSection++)
+    {
+        ulNumDescs += USBDescGetNum(
+                (tDescriptorHeader *)psConfig->psSections[ulSection]->pucData,
+                psConfig->psSections[ulSection]->ucSize,
+                ulType);
+    }
+
+    return(ulNumDescs);
+}
+
+//*****************************************************************************
+//
+//! \internal
+//!
+//! Finds the n-th descriptor of a particular type within the supplied
+//! configuration descriptor.
+//!
+//! \param psConfig points to the header structure for the configuration
+//! descriptor that is to be searched.
+//! \param ulType identifies the type of descriptor that is to be found.  If
+//! the value is \b USB_DESC_ANY, the function returns a pointer to the n-th
+//! descriptor regardless of type.
+//! \param ulIndex is the zero based index of the descriptor whose pointer is
+//! to be returned.  For example, passing value 1 in \e ulIndex returns the
+//! second matching descriptor.
+//! \param pulSection points to storage which will receive the section index
+//! containing the requested descriptor.
+//!
+//! Return a pointer to the n-th descriptor of a particular type found in the
+//! configuration descriptor passed.
+//!
+//! The search performed by this function traverses through the list of
+//! sections comprising the configuration descriptor.  Note that the similar
+//! top-level function, USBDescGet(), searches through a single, contiguous
+//! block of data to perform the same enumeration.
+//!
+//! \return Returns a pointer to the header of the required descriptor if
+//! found or NULL otherwise.
+//
+//*****************************************************************************
+tDescriptorHeader *
+USBDCDConfigDescGet(const tConfigHeader *psConfig, unsigned long ulType,
+                    unsigned long ulIndex, unsigned long *pulSection)
+{
+    unsigned long ulSection;
+    unsigned long ulTotalDescs;
+    unsigned long ulNumDescs;
+
+    //
+    // Initialize our counts.
+    //
+    ulTotalDescs = 0;
+
+    //
+    // Determine the number of descriptors of the given type in each of the
+    // sections comprising the config descriptor.  This allows us to determine
+    // which section contains the descriptor we are being asked for.
+    //
+    for(ulSection = 0; ulSection < (unsigned long)psConfig->ucNumSections;
+        ulSection++)
+    {
+        //
+        // How many descriptors of the requested type exist in this section?
+        //
+        ulNumDescs = USBDescGetNum(
+                (tDescriptorHeader *)psConfig->psSections[ulSection]->pucData,
+                psConfig->psSections[ulSection]->ucSize,
+                ulType);
+
+        //
+        // Does this section contain the descriptor whose index we are looking
+        // for?
+        //
+        if((ulTotalDescs + ulNumDescs) > ulIndex)
+        {
+            //
+            // We know the requested descriptor exists in the current
+            // block so write the section number to the caller's storage.
+            //
+            *pulSection = ulSection;
+
+            //
+            // Now find the actual descriptor requested and return its pointer.
+            //
+            return(USBDescGet(
+                 (tDescriptorHeader *)psConfig->psSections[ulSection]->pucData,
+                 psConfig->psSections[ulSection]->ucSize,
+                 ulType,
+                 ulIndex - ulTotalDescs));
+        }
+
+        //
+        // We have not found the required descriptor yet.  Update our running
+        // count of the number of type matches found so far then move on to
+        // the next section.
+        //
+        ulTotalDescs += ulNumDescs;
+    }
+
+    //
+    // If we drop out of the loop, we can't find the requested descriptor
+    // so return NULL.
+    //
+    return((tDescriptorHeader *)0);
+}
+
+//*****************************************************************************
+//
+//! \internal
+//!
+//! Determines the number of different alternate configurations for a given
+//! interface within a config descriptor.
+//!
+//! \param psConfig points to the header structure for the configuration
+//! descriptor that is to be searched.
+//! \param ucInterfaceNumber is the interface number for which the number of
+//! alternate configurations is to be counted.
+//!
+//! This function can be used to count the number of alternate settings for a
+//! specific interface within a configuration.
+//!
+//! The search performed by this function traverses through the list of
+//! sections comprising the configuration descriptor.  Note that the similar
+//! top-level function, USBDescGetNumAlternateInterfaces(), searches through
+//! a single, contiguous block of data to perform the same enumeration.
+//!
+//! \return Returns the number of alternate versions of the specified interface
+//! or 0 if the interface number supplied cannot be found in the config
+//! descriptor.
+//
+//*****************************************************************************
+unsigned long
+USBDCDConfigGetNumAlternateInterfaces(const tConfigHeader *psConfig,
+                                      unsigned char ucInterfaceNumber)
+{
+    tDescriptorHeader *psDescCheck;
+    unsigned long ulCount;
+    unsigned long ulSec;
+
+    //
+    // Set up for our descriptor counting loop.
+    //
+    psDescCheck = (tDescriptorHeader *)psConfig->psSections[0]->pucData;
+    ulSec = 0;
+    ulCount = 0;
+
+    //
+    // Keep looking through the supplied data until we reach the end.
+    //
+    while(psDescCheck)
+    {
+        //
+        // Is this an interface descriptor with the required interface number?
+        //
+        if((psDescCheck->bDescriptorType == USB_DTYPE_INTERFACE) &&
+            (((tInterfaceDescriptor *)psDescCheck)->bInterfaceNumber ==
+             ucInterfaceNumber))
+        {
+            //
+            // Yes - increment our count.
+            //
+            ulCount++;
+        }
+
+        //
+        // Move on to the next descriptor.
+        //
+        psDescCheck = NextConfigDescGet(psConfig, &ulSec, psDescCheck);
+    }
+
+    //
+    // Return the descriptor count to the caller.
+    //
+    return(ulCount);
+}
+
+//*****************************************************************************
+//
+//! \internal
+//!
+//! Returns a pointer to the n-th interface descriptor in a configuration
+//! descriptor that applies to the supplied alternate setting number.
+//!
+//! \param psConfig points to the header structure for the configuration
+//! descriptor that is to be searched.
+//! \param ulIndex is the zero based index of the interface that is to be
+//! found.  If \e ulAlt is set to a value other than \b USB_DESC_ANY, this will
+//! be equivalent to the interface number being searched for.
+//! \param ulAlt is the alternate setting number which is to be
+//! searched for.  If this value is \b USB_DESC_ANY, the alternate setting
+//! is ignored and all interface descriptors are considered in the search.
+//! \param pulSection points to storage which will receive the index of the
+//! config descriptor section which contains the requested interface
+//! descriptor.
+//!
+//! Return a pointer to the n-th interface descriptor found in the supplied
+//! configuration descriptor.  If \e ulAlt is not \b USB_DESC_ANY, only
+//! interface descriptors which are part of the supplied alternate setting are
+//! considered in the search otherwise all interface descriptors are
+//! considered.
+//!
+//! Note that, although alternate settings can be applied on an interface-by-
+//! interface basis, the number of interfaces offered is fixed for a given
+//! config descriptor.  Hence, this function will correctly find the unique
+//! interface descriptor for that interface's alternate setting number \e
+//! ulAlt if \e ulIndex is set to the required interface number and \e ulAlt
+//! is set to a valid alternate setting number for that interface.
+//!
+//! The search performed by this function traverses through the list of
+//! sections comprising the configuration descriptor.  Note that the similar
+//! top-level function, USBDescGetInterface(), searches through a single,
+//! contiguous block of data to perform the same enumeration.
+//!
+//! \return Returns a pointer to the required interface descriptor if
+//! found or NULL otherwise.
+//
+//*****************************************************************************
+tInterfaceDescriptor *
+USBDCDConfigGetInterface(const tConfigHeader *psConfig, unsigned long ulIndex,
+                         unsigned long ulAlt, unsigned long *pulSection)
+{
+    //
+    // If we are being told to ignore the alternate configuration, this boils
+    // down to a very simple query.
+    //
+    if(ulAlt == USB_DESC_ANY)
+    {
+        //
+        // Return the ulIndex-th interface descriptor we find in the
+        // configuration descriptor.
+        //
+        return((tInterfaceDescriptor *)USBDCDConfigDescGet(psConfig,
+                                                           USB_DTYPE_INTERFACE,
+                                                           ulIndex,
+                                                           pulSection));
+    }
+    else
+    {
+        //
+        // In this case, a specific alternate setting number is required.
+        // Given that interface numbers are zero based indices, we can
+        // pass the supplied ulIndex parameter directly as the interface
+        // number to USBDescGetAlternateInterface to retrieve the requested
+        // interface descriptor pointer.
+        //
+        return(ConfigAlternateInterfaceGet(psConfig, ulIndex, ulAlt,
+                                           pulSection));
+    }
+}
+
+//*****************************************************************************
+//
+//! \internal
+//!
+//! Return a pointer to the n-th endpoint descriptor in a particular interface
+//! within a configuration descriptor.
+//!
+//! \param psConfig points to the header structure for the configuration
+//! descriptor that is to be searched.
+//! \param ulInterfaceNumber is the interface number whose endpoint is to be
+//! found.
+//! \param ulAltCfg is the alternate setting number which is to be searched
+//! for.  This must be a valid alternate setting number for the requested
+//! interface.
+//! \param ulIndex is the zero based index of the endpoint that is to be
+//! found within the appropriate alternate setting for the interface.
+//!
+//! Return a pointer to the n-th endpoint descriptor found in the supplied
+//! interface descriptor.  If the \e ulIndex parameter is invalid (greater
+//! than or equal to the bNumEndpoints field of the interface descriptor) or
+//! the endpoint cannot be found within \e ucSize bytes of the interface
+//! descriptor pointer, the function will return NULL.
+//!
+//! Note that, although the USB 2.0 specification states that endpoint
+//! descriptors must follow the interface descriptor that they relate to, it
+//! also states that device specific descriptors should follow any standard
+//! descriptor that they relate to.  As a result, we cannot assume that each
+//! interface descriptor will be followed by nothing but an ordered list of
+//! its own endpoints and, hence, the function needs to be provided ucSize to
+//! limit the search range.
+//!
+//! The search performed by this function traverses through the list of
+//! sections comprising the configuration descriptor.  Note that the similar
+//! top-level function, USBDescGetInterfaceEndpoint(), searches through a
+//! single, contiguous block of data to perform the same enumeration.
+//!
+//! \return Returns a pointer to the requested endpoint descriptor if
+//! found or NULL otherwise.
+//
+//*****************************************************************************
+tEndpointDescriptor *
+USBDCDConfigGetInterfaceEndpoint(const tConfigHeader *psConfig,
+                                 unsigned long ulInterfaceNumber,
+                                 unsigned long ulAltCfg, unsigned long ulIndex)
+{
+    tInterfaceDescriptor *psInterface;
+    tDescriptorHeader *psEndpoint;
+    unsigned long ulSection;
+    unsigned long ulCount;
+
+    //
+    // Find the requested interface descriptor.
+    //
+    psInterface = USBDCDConfigGetInterface(psConfig, ulInterfaceNumber,
+                                           ulAltCfg, &ulSection);
+
+    //
+    // Did we find the requested interface?
+    //
+    if(psInterface)
+    {
+        //
+        // Is the index passed valid?
+        //
+        if(ulIndex >= psInterface->bNumEndpoints)
+        {
+            //
+            // It's out of bounds so return a NULL.
+            //
+            return((tEndpointDescriptor *)0);
+        }
+        else
+        {
+            //
+            // Endpoint index is valid so find the descriptor.  We start from
+            // the interface descriptor and look for following endpoint
+            // descriptors.
+            //
+            ulCount = 0;
+            psEndpoint = (tDescriptorHeader *)psInterface;
+
+            while(psEndpoint)
+            {
+                if(psEndpoint->bDescriptorType == USB_DTYPE_ENDPOINT)
+                {
+                    //
+                    // We found an endpoint descriptor.  Have we reached the
+                    // one we want?
+                    //
+                    if(ulCount == ulIndex)
+                    {
+                        //
+                        // Yes - return the descriptor pointer to the caller.
+                        //
+                        return((tEndpointDescriptor *)psEndpoint);
+                    }
+
+                    //
+                    // Move on to look for the next endpoint.
+                    //
+                    ulCount++;
+                }
+
+                //
+                // Move to the next descriptor.
+                //
+                psEndpoint = NextConfigDescGet(psConfig, &ulSection,
+                                               psEndpoint);
+            }
+        }
+    }
+
+    //
+    // We couldn't find the requested interface or we got to the end of the
+    // descriptor without finding the requested endpoint.
+    //
+    return((tEndpointDescriptor *)0);
+
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/src/platform/lm3s/usblib/device/usbdcomp.c b/src/platform/lm3s/usblib/device/usbdcomp.c
new file mode 100755
index 00000000..e9feef3a
--- /dev/null
+++ b/src/platform/lm3s/usblib/device/usbdcomp.c
@@ -0,0 +1,1549 @@
+//****************************************************************************
+//
+// usbdcomp.c - USB composite device class driver.
+//
+// Copyright (c) 2010-2011 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 7611 of the Stellaris USB Library.
+//
+//****************************************************************************
+
+#include "inc/hw_memmap.h"
+#include "inc/hw_types.h"
+#include "driverlib/debug.h"
+#include "driverlib/sysctl.h"
+#include "driverlib/rom.h"
+#include "driverlib/rom_map.h"
+#include "driverlib/usb.h"
+#include "usblib/usblib.h"
+#include "usblib/usb-ids.h"
+#include "usblib/usbcdc.h"
+#include "usblib/device/usbdevice.h"
+#include "usblib/device/usbdcdc.h"
+#include "usblib/device/usbdcomp.h"
+#include "usblib/usblibpriv.h"
+
+//****************************************************************************
+//
+//! \addtogroup composite_device_class_api
+//! @{
+//
+//****************************************************************************
+
+//****************************************************************************
+//
+// Device Descriptor.  This is stored in RAM to allow several fields to be
+// changed at runtime based on the client's requirements.
+//
+//****************************************************************************
+static unsigned char g_pCompDeviceDescriptor[] =
+{
+    18,                     // Size of this structure.
+    USB_DTYPE_DEVICE,       // Type of this structure.
+    USBShort(0x110),        // USB version 1.1 (if we say 2.0, hosts assume
+                            // high-speed - see USB 2.0 spec 9.2.6.6)
+    USB_CLASS_MISC,         // USB Device Class (spec 5.1.1)
+    USB_MISC_SUBCLASS_COMMON, // USB Device Sub-class (spec 5.1.1)
+    USB_MISC_PROTOCOL_IAD,  // USB Device protocol (spec 5.1.1)
+    64,                     // Maximum packet size for default pipe.
+    USBShort(0),            // Vendor ID (filled in during USBDCompositeInit).
+    USBShort(0),            // Product ID (filled in during USBDCompositeInit).
+    USBShort(0x100),        // Device Version BCD.
+    1,                      // Manufacturer string identifier.
+    2,                      // Product string identifier.
+    3,                      // Product serial number.
+    1                       // Number of configurations.
+};
+
+//****************************************************************************
+//
+// Composite class device configuration descriptor.
+//
+// It is vital that the configuration descriptor bConfigurationValue field
+// (byte 6) is 1 for the first configuration and increments by 1 for each
+// additional configuration defined here.  This relationship is assumed in the
+// device stack for simplicity even though the USB 2.0 specification imposes
+// no such restriction on the bConfigurationValue values.
+//
+// Note that this structure is deliberately located in RAM since we need to
+// be able to patch some values in it based on client requirements.
+//
+//****************************************************************************
+static const unsigned char g_pCompConfigDescriptor[] =
+{
+    //
+    // Configuration descriptor header.
+    //
+    9,                          // Size of the configuration descriptor.
+    USB_DTYPE_CONFIGURATION,    // Type of this descriptor.
+    USBShort(0),                // The total size of this full structure.
+    0,                          // The number of interfaces in this
+                                // configuration, this will be filled by
+                                // the class as it discovers all classes
+                                // supported.
+    1,                          // The unique value for this configuration.
+    0,                          // The string identifier that describes this
+                                // configuration.
+    USB_CONF_ATTR_BUS_PWR,      // .
+    250,                        // The maximum power in 2mA increments.
+};
+
+//****************************************************************************
+//
+// Byte offsets used to access various fields in our index/interface/endpoint
+// lookup table (tUSBDCompositeDevice.pulDeviceWorkspace).  This workspace
+// contains one 4 byte entry per device. The LSB is the device index, next byte
+// is the number of the first interface not within this device, next byte is the
+// number of the first IN endpoint not within this device and the final byte is
+// the number of the first OUT endpoint not within this device.  Using this
+// simple table we can reasonably quickly cross-reference index with interface
+// and endpoint numbers.
+//
+//****************************************************************************
+#define LOOKUP_INDEX_BYTE       0
+#define LOOKUP_INTERFACE_BYTE   1
+#define LOOKUP_IN_END_BYTE      2
+#define LOOKUP_OUT_END_BYTE     3
+
+//****************************************************************************
+//
+// A marker used to indicate an invalid index into the device table.
+//
+//****************************************************************************
+#define INVALID_DEVICE_INDEX 0xFFFFFFFF
+
+//*****************************************************************************
+//
+// Macros to convert between USB controller base address and an index.  These
+// are currently trivial but are included to allow for the possibility of
+// supporting more than one controller in the future.
+//
+//*****************************************************************************
+#define USB_BASE_TO_INDEX(BaseAddr) (0)
+#define USB_INDEX_TO_BASE(Index)    (USB0_BASE)
+
+//****************************************************************************
+//
+// Various internal handlers needed by this class.
+//
+//****************************************************************************
+static void HandleDisconnect(void *pvInstance);
+static void InterfaceChange(void *pvInstance, unsigned char ucInterfaceNum,
+                            unsigned char ucAlternateSetting);
+static void ConfigChangeHandler(void *pvInstance, unsigned long ulValue);
+static void DataSent(void *pvInstance, unsigned long ulInfo);
+static void DataReceived(void *pvInstance, unsigned long ulInfo);
+static void HandleEndpoints(void *pvInstance, unsigned long ulStatus);
+static void HandleRequests(void *pvInstance, tUSBRequest *pUSBRequest);
+static void SuspendHandler(void *pvInstance);
+static void ResumeHandler(void *pvInstance);
+static void ResetHandler(void *pvInstance);
+static void GetDescriptor(void *pvInstance, tUSBRequest *pUSBRequest);
+
+//****************************************************************************
+//
+// Configuration Descriptor.
+//
+//****************************************************************************
+tConfigHeader *g_pCompConfigDescriptors[1];
+
+//****************************************************************************
+//
+// The FIFO configuration for USB mass storage class device.
+//
+//****************************************************************************
+tFIFOConfig g_sUSBCompositeFIFOConfig =
+{
+    //
+    // IN endpoints.
+    //
+    {
+        { 1, false, USB_EP_DEV_IN },
+        { 1, false, USB_EP_DEV_IN },
+        { 1, false, USB_EP_DEV_IN },
+        { 1, false, USB_EP_DEV_IN },
+        { 1, false, USB_EP_DEV_IN },
+        { 1, false, USB_EP_DEV_IN },
+        { 1, false, USB_EP_DEV_IN },
+        { 1, false, USB_EP_DEV_IN },
+        { 1, false, USB_EP_DEV_IN },
+        { 1, false, USB_EP_DEV_IN },
+        { 1, false, USB_EP_DEV_IN },
+        { 1, false, USB_EP_DEV_IN },
+        { 1, false, USB_EP_DEV_IN },
+        { 1, false, USB_EP_DEV_IN },
+        { 1, false, USB_EP_DEV_IN }
+    },
+    //
+    // OUT endpoints.
+    //
+    {
+        { 1, false, USB_EP_DEV_OUT },
+        { 1, false, USB_EP_DEV_OUT },
+        { 1, false, USB_EP_DEV_OUT },
+        { 1, false, USB_EP_DEV_OUT },
+        { 1, false, USB_EP_DEV_OUT },
+        { 1, false, USB_EP_DEV_OUT },
+        { 1, false, USB_EP_DEV_OUT },
+        { 1, false, USB_EP_DEV_OUT },
+        { 1, false, USB_EP_DEV_OUT },
+        { 1, false, USB_EP_DEV_OUT },
+        { 1, false, USB_EP_DEV_OUT },
+        { 1, false, USB_EP_DEV_OUT },
+        { 1, false, USB_EP_DEV_OUT },
+        { 1, false, USB_EP_DEV_OUT },
+        { 1, false, USB_EP_DEV_OUT }
+    },
+};
+
+//****************************************************************************
+//
+// The device information structure for the USB Composite device.
+//
+//****************************************************************************
+tDeviceInfo g_sCompositeDeviceInfo =
+{
+    //
+    // Device event handler callbacks.
+    //
+    {
+        //
+        // GetDescriptor
+        //
+        GetDescriptor,
+
+        //
+        // RequestHandler
+        //
+        HandleRequests,
+
+        //
+        // InterfaceChange
+        //
+        InterfaceChange,
+
+        //
+        // ConfigChange
+        //
+        ConfigChangeHandler,
+
+        //
+        // DataReceived
+        //
+        DataReceived,
+
+        //
+        // DataSentCallback
+        //
+        DataSent,
+
+        //
+        // ResetHandler
+        //
+        ResetHandler,
+
+        //
+        // SuspendHandler
+        //
+        SuspendHandler,
+
+        //
+        // ResumeHandler
+        //
+        ResumeHandler,
+
+        //
+        // DisconnectHandler
+        //
+        HandleDisconnect,
+
+        //
+        // EndpointHandler
+        //
+        HandleEndpoints
+    },
+    g_pCompDeviceDescriptor,
+    (const tConfigHeader **)g_pCompConfigDescriptors,
+    0,
+    0,
+    &g_sUSBCompositeFIFOConfig
+};
+
+//****************************************************************************
+//
+// Use the lookup table from the field pulDeviceWorkspace in the
+// tUSBDCompositeDevice structure to determine which device to call given a
+// particular composite device interface number.
+//
+// The returned value is the index into psDevice->tCompositeEntry indicating
+// the device which contains this interface or INVALID_DEVICE_INDEX if no
+// device contains the passed interface number.
+//
+//****************************************************************************
+static unsigned long
+InterfaceToIndex(tUSBDCompositeDevice *psDevice, unsigned long ulInterface)
+{
+    unsigned long ulLoop;
+    unsigned char *pucLookupEntry;
+
+    //
+    // Get a pointer to the lookup table.
+    //
+    pucLookupEntry = (unsigned char *)psDevice->pulDeviceWorkspace;
+
+    //
+    // Check each lookup entry in turn.
+    //
+    for(ulLoop = 0; ulLoop < psDevice->ulNumDevices; ulLoop++)
+    {
+        //
+        // If the desired interface number is lower than the value in the
+        // current lookup table entry, we have found the desired device so
+        // return its index.
+        //
+        if(ulInterface < (unsigned long)pucLookupEntry[LOOKUP_INTERFACE_BYTE])
+        {
+            return(ulLoop);
+        }
+
+        //
+        // Move to the next lookup table entry.
+        //
+        pucLookupEntry += sizeof(unsigned long);
+    }
+
+    //
+    // If we get here, an invalid interface number was passed so return a
+    // marker to indicate this.
+    //
+    return(INVALID_DEVICE_INDEX);
+}
+
+//****************************************************************************
+//
+// Use the lookup table from the field pulDeviceWorkspace in the
+// tUSBDCompositeDevice structure to determine which device to call given a
+// particular composite device endpoint number.
+//
+// The returned value is the index into psDevice->tCompositeEntry indicating
+// the device which contains this endpoint or INVALID_DEVICE_INDEX if no
+// device contains the passed endpoint number.
+//
+//****************************************************************************
+static unsigned long
+EndpointToIndex(tUSBDCompositeDevice *psDevice, unsigned long ulEndpoint,
+                tBoolean bInEndpoint)
+{
+    unsigned long ulLoop, ulEndpointByte;
+    unsigned char *pucLookupEntry;
+
+    //
+    // Get a pointer to the lookup table.
+    //
+    pucLookupEntry = (unsigned char *)psDevice->pulDeviceWorkspace;
+
+    //
+    // Are we considering an IN or OUT endpoint?
+    //
+    ulEndpointByte = bInEndpoint ? LOOKUP_IN_END_BYTE : LOOKUP_OUT_END_BYTE;
+
+    //
+    // Check each lookup entry in turn.
+    //
+    for(ulLoop = 0; ulLoop < psDevice->ulNumDevices; ulLoop++)
+    {
+        //
+        // If the desired endpoint number is lower than the value in the
+        // current lookup table entry, we have found the desired device so
+        // return its index.
+        //
+        if(ulEndpoint < (unsigned long)pucLookupEntry[ulEndpointByte])
+        {
+            return(ulLoop);
+        }
+
+        //
+        // Move to the next lookup table entry.
+        //
+        pucLookupEntry += sizeof(unsigned long);
+    }
+
+    //
+    // If we get here, an invalid endpoint number was passed so return a
+    // marker to indicate this.
+    //
+    return(INVALID_DEVICE_INDEX);
+}
+
+
+//****************************************************************************
+//
+// This function will check if any device classes need a get descriptor
+// handler called.
+//
+//****************************************************************************
+static void
+GetDescriptor(void *pvInstance, tUSBRequest *pUSBRequest)
+{
+    unsigned long ulIdx;
+    const tDeviceInfo *pDeviceInfo;
+    tUSBDCompositeDevice *psDevice;
+
+    //
+    // Create the device instance pointer.
+    //
+    psDevice = (tUSBDCompositeDevice *)pvInstance;
+
+    //
+    // Determine which device this request is intended for.  We have to be
+    // careful here to send this to the callback for the correct device
+    // depending upon whether it is a request sent to the device, the interface
+    // or the endpoint.
+    //
+    switch(pUSBRequest->bmRequestType & USB_RTYPE_RECIPIENT_M)
+    {
+        case USB_RTYPE_INTERFACE:
+        {
+            ulIdx = InterfaceToIndex(psDevice, (pUSBRequest->wIndex & 0xFF));
+            break;
+        }
+
+        case USB_RTYPE_ENDPOINT:
+        {
+            ulIdx = EndpointToIndex(psDevice, (pUSBRequest->wIndex & 0x0F),
+                             (pUSBRequest->wIndex & 0x80) ? true : false);
+            break;
+        }
+
+        //
+        // Requests sent to the device or any other recipient can't be
+        // handled here since we have no way of telling where they are
+        // supposed to be handled.  As a result, we just stall them.
+        //
+        // If your composite device has some device-specific descriptors,
+        // you should add code here to handle them.
+        //
+        case USB_RTYPE_DEVICE:
+        case USB_RTYPE_OTHER:
+        default:
+        {
+            ulIdx = INVALID_DEVICE_INDEX;
+            break;
+        }
+    }
+
+    //
+    // Did we find a device class to pass the request to?
+    //
+    if(ulIdx != INVALID_DEVICE_INDEX)
+    {
+        //
+        // Get a pointer to the individual device instance.
+        //
+        pDeviceInfo = psDevice->psDevices[ulIdx].psDevice;
+
+        //
+        // Does this device have a GetDescriptor callback?
+        //
+        if(pDeviceInfo->sCallbacks.pfnGetDescriptor)
+        {
+            //
+            // Remember this device index so that we can correctly route any
+            // data notification callbacks to it.
+            //
+            psDevice->psPrivateData->ulEP0Owner = ulIdx;
+
+            //
+            // Call the device to retrieve the descriptor.
+            //
+            pDeviceInfo->sCallbacks.pfnGetDescriptor(
+                    psDevice->psDevices[ulIdx].pvInstance, pUSBRequest);
+        }
+        else
+        {
+            //
+            // Oops - we can't satisfy the request so stall EP0 to indicate
+            // an error.
+            //
+            USBDCDStallEP0(
+                       USB_BASE_TO_INDEX(psDevice->psPrivateData->ulUSBBase));
+        }
+    }
+    else
+    {
+        //
+        // We are unable to satisfy the descriptor request so stall EP0 to
+        // indicate an error.
+        //
+        USBDCDStallEP0(USB_BASE_TO_INDEX(psDevice->psPrivateData->ulUSBBase));
+    }
+}
+
+//****************************************************************************
+//
+// This function will check if any device classes need an suspend handler
+// called.
+//
+//****************************************************************************
+static void
+SuspendHandler(void *pvInstance)
+{
+    unsigned long ulIdx;
+    tUSBDCompositeDevice *psDevice;
+    const tDeviceInfo *pDeviceInfo;
+    void *pvDeviceInst;
+
+    ASSERT(pvInstance != 0);
+
+    //
+    // Create the device instance pointer.
+    //
+    psDevice = (tUSBDCompositeDevice *)pvInstance;
+
+    //
+    // Inform the application that the device has resumed.
+    //
+    if(psDevice->pfnCallback)
+    {
+        psDevice->pfnCallback(pvInstance, USB_EVENT_SUSPEND, 0, 0);
+    }
+
+    for(ulIdx = 0; ulIdx < psDevice->ulNumDevices; ulIdx++)
+    {
+        pDeviceInfo = psDevice->psDevices[ulIdx].psDevice;
+        pvDeviceInst = psDevice->psDevices[ulIdx].pvInstance;
+
+        if(pDeviceInfo->sCallbacks.pfnSuspendHandler)
+        {
+            pDeviceInfo->sCallbacks.pfnSuspendHandler(pvDeviceInst);
+        }
+    }
+}
+
+//****************************************************************************
+//
+// This function will check if any device classes need an resume handler
+// called.
+//
+//****************************************************************************
+static void
+ResumeHandler(void *pvInstance)
+{
+    unsigned long ulIdx;
+    tUSBDCompositeDevice *psDevice;
+    const tDeviceInfo *pDeviceInfo;
+    void *pvDeviceInst;
+
+    ASSERT(pvInstance != 0);
+
+    //
+    // Create the device instance pointer.
+    //
+    psDevice = (tUSBDCompositeDevice *)pvInstance;
+
+    //
+    // Inform the application that the device has resumed.
+    //
+    if(psDevice->pfnCallback)
+    {
+        psDevice->pfnCallback(pvInstance, USB_EVENT_RESUME, 0, 0);
+    }
+
+    for(ulIdx = 0; ulIdx < psDevice->ulNumDevices; ulIdx++)
+    {
+        pDeviceInfo = psDevice->psDevices[ulIdx].psDevice;
+        pvDeviceInst = psDevice->psDevices[ulIdx].pvInstance;
+
+        if(pDeviceInfo->sCallbacks.pfnResumeHandler)
+        {
+            pDeviceInfo->sCallbacks.pfnResumeHandler(pvDeviceInst);
+        }
+    }
+}
+
+//****************************************************************************
+//
+// This function will check if any device classes need an reset handler
+// called.
+//
+//****************************************************************************
+static void
+ResetHandler(void *pvInstance)
+{
+    unsigned long ulIdx;
+    tUSBDCompositeDevice *psDevice;
+    const tDeviceInfo *pDeviceInfo;
+    void *pvDeviceInst;
+
+    ASSERT(pvInstance != 0);
+
+    //
+    // Create the device instance pointer.
+    //
+    psDevice = (tUSBDCompositeDevice *)pvInstance;
+
+    //
+    // Inform the application that the device has been connected.
+    //
+    if(psDevice->pfnCallback)
+    {
+        psDevice->pfnCallback(pvInstance, USB_EVENT_CONNECTED, 0, 0);
+    }
+
+    for(ulIdx = 0; ulIdx < psDevice->ulNumDevices; ulIdx++)
+    {
+        pDeviceInfo = psDevice->psDevices[ulIdx].psDevice;
+        pvDeviceInst = psDevice->psDevices[ulIdx].pvInstance;
+
+        if(pDeviceInfo->sCallbacks.pfnResetHandler)
+        {
+            pDeviceInfo->sCallbacks.pfnResetHandler(pvDeviceInst);
+        }
+    }
+}
+
+//****************************************************************************
+//
+// This function is called to handle data being set to the host so that the
+// application callback can be called when the data has been transferred.
+//
+//****************************************************************************
+static void
+DataSent(void *pvInstance, unsigned long ulInfo)
+{
+    unsigned long ulIdx;
+    const tDeviceInfo *pDeviceInfo;
+    tUSBDCompositeDevice *psDevice;
+
+    //
+    // Create the device instance pointer.
+    //
+    psDevice = (tUSBDCompositeDevice *)pvInstance;
+
+    //
+    // Pass this notification on to the device which last handled a
+    // transaction on endpoint 0 (assuming we know who that was).
+    //
+    ulIdx = psDevice->psPrivateData->ulEP0Owner;
+
+    if(ulIdx != INVALID_DEVICE_INDEX)
+    {
+        pDeviceInfo = psDevice->psDevices[ulIdx].psDevice;
+
+        if(pDeviceInfo->sCallbacks.pfnDataSent)
+        {
+            pDeviceInfo->sCallbacks.pfnDataSent(
+                psDevice->psDevices[ulIdx].pvInstance, ulInfo);
+        }
+    }
+}
+
+//****************************************************************************
+//
+// This function is called to handle data being received back from the host so
+// that the application callback can be called when the new data is ready.
+//
+//****************************************************************************
+static void
+DataReceived(void *pvInstance, unsigned long ulInfo)
+{
+    unsigned long ulIdx;
+    const tDeviceInfo *pDeviceInfo;
+    tUSBDCompositeDevice *psDevice;
+
+    //
+    // Create the device instance pointer.
+    //
+    psDevice = (tUSBDCompositeDevice *)pvInstance;
+
+    //
+    // Pass this notification on to the device which last handled a
+    // transaction on endpoint 0 (assuming we know who that was).
+    //
+    ulIdx = psDevice->psPrivateData->ulEP0Owner;
+
+    if(ulIdx != INVALID_DEVICE_INDEX)
+    {
+        pDeviceInfo = psDevice->psDevices[ulIdx].psDevice;
+
+        if(pDeviceInfo->sCallbacks.pfnDataReceived)
+        {
+            pDeviceInfo->sCallbacks.pfnDataReceived(
+                psDevice->psDevices[ulIdx].pvInstance, ulInfo);
+        }
+    }
+}
+
+//****************************************************************************
+//
+// This function will check if any device classes need an endpoint handler
+// called.
+//
+//****************************************************************************
+static void
+HandleEndpoints(void *pvInstance, unsigned long ulStatus){
+    unsigned long ulIdx;
+    const tDeviceInfo *pDeviceInfo;
+    tUSBDCompositeDevice *psDevice;
+
+    ASSERT(pvInstance != 0);
+
+    //
+    // Create the device instance pointer.
+    //
+    psDevice = (tUSBDCompositeDevice *)pvInstance;
+
+    //
+    // Call each of the endpoint handlers.  This may seem odd since we should
+    // only call the handler whose endpoint needs service.  Unfortunately, if
+    // the device class driver is using uDMA, we have no way of knowing which
+    // handler to call (since ulStatus will be 0).  Since the handlers are
+    // set up to ignore any callback that isn't for them, this is safe.
+    //
+    for(ulIdx = 0; ulIdx < psDevice->ulNumDevices; ulIdx++)
+    {
+        pDeviceInfo = psDevice->psDevices[ulIdx].psDevice;
+
+        if(pDeviceInfo->sCallbacks.pfnEndpointHandler)
+        {
+            pDeviceInfo->sCallbacks.pfnEndpointHandler(
+                psDevice->psDevices[ulIdx].pvInstance, ulStatus);
+        }
+    }
+}
+
+//****************************************************************************
+//
+// This function is called by the USB device stack whenever the device is
+// disconnected from the host.
+//
+//****************************************************************************
+static void
+HandleDisconnect(void *pvInstance)
+{
+    unsigned long ulIdx;
+    const tDeviceInfo *pDeviceInfo;
+    tUSBDCompositeDevice *psDevice;
+
+    ASSERT(pvInstance != 0);
+
+    //
+    // Create the device instance pointer.
+    //
+    psDevice = (tUSBDCompositeDevice *)pvInstance;
+
+    //
+    // Inform the application that the device has been disconnected.
+    //
+    if(psDevice->pfnCallback)
+    {
+        psDevice->pfnCallback(pvInstance, USB_EVENT_DISCONNECTED, 0, 0);
+    }
+
+    for(ulIdx = 0; ulIdx < psDevice->ulNumDevices; ulIdx++)
+    {
+        pDeviceInfo = psDevice->psDevices[ulIdx].psDevice;
+
+        if(pDeviceInfo->sCallbacks.pfnDisconnectHandler)
+        {
+            pDeviceInfo->sCallbacks.pfnDisconnectHandler(
+                psDevice->psDevices[ulIdx].pvInstance);
+        }
+    }
+}
+
+//****************************************************************************
+//
+// This function is called by the USB device stack whenever the device
+// interface changes.  It will be passed on to the device classes if they have
+// a handler for this function.
+//
+//****************************************************************************
+static void
+InterfaceChange(void *pvInstance, unsigned char ucInterfaceNum,
+                unsigned char ucAlternateSetting)
+{
+    unsigned long ulIdx;
+    const tDeviceInfo *pDeviceInfo;
+    tUSBDCompositeDevice *psDevice;
+
+    ASSERT(pvInstance != 0);
+
+    //
+    // Create the device instance pointer.
+    //
+    psDevice = (tUSBDCompositeDevice *)pvInstance;
+
+    for(ulIdx = 0; ulIdx < psDevice->ulNumDevices; ulIdx++)
+    {
+        pDeviceInfo = psDevice->psDevices[ulIdx].psDevice;
+
+        if(pDeviceInfo->sCallbacks.pfnInterfaceChange)
+        {
+            pDeviceInfo->sCallbacks.pfnInterfaceChange(
+                psDevice->psDevices[ulIdx].pvInstance, ucInterfaceNum,
+                ucAlternateSetting);
+        }
+    }
+}
+
+//****************************************************************************
+//
+// This function is called by the USB device stack whenever the device
+// configuration changes. It will be passed on to the device classes if they
+// have a handler for this function.
+//
+//****************************************************************************
+static void
+ConfigChangeHandler(void *pvInstance, unsigned long ulValue)
+{
+    unsigned long ulIdx;
+    const tDeviceInfo *pDeviceInfo;
+    tUSBDCompositeDevice *psDevice;
+
+    ASSERT(pvInstance != 0);
+
+    //
+    // Create the device instance pointer.
+    //
+    psDevice = (tUSBDCompositeDevice *)pvInstance;
+
+    for(ulIdx = 0; ulIdx < psDevice->ulNumDevices; ulIdx++)
+    {
+        pDeviceInfo = psDevice->psDevices[ulIdx].psDevice;
+
+        if(pDeviceInfo->sCallbacks.pfnConfigChange)
+        {
+            pDeviceInfo->sCallbacks.pfnConfigChange(
+                    psDevice->psDevices[ulIdx].pvInstance, ulValue);
+        }
+    }
+}
+
+//****************************************************************************
+//
+// This function is called by the USB device stack whenever a non-standard
+// request is received.
+//
+// \param pvInstance
+// \param pUSBRequest points to the request received.
+//
+// This call  will be passed on to the device classes if they have a handler
+// for this function.
+//
+// \return None.
+//
+//****************************************************************************
+static void
+HandleRequests(void *pvInstance, tUSBRequest *pUSBRequest)
+{
+    unsigned long ulIdx;
+    const tDeviceInfo *pDeviceInfo;
+    tUSBDCompositeDevice *psDevice;
+
+    //
+    // Create the device instance pointer.
+    //
+    psDevice = (tUSBDCompositeDevice *)pvInstance;
+
+    //
+    // Determine which device this request is intended for.  We have to be
+    // careful here to send this to the callback for the correct device
+    // depending upon whether it is a request sent to the device, the interface
+    // or the endpoint.
+    //
+    switch(pUSBRequest->bmRequestType & USB_RTYPE_RECIPIENT_M)
+    {
+        case USB_RTYPE_INTERFACE:
+        {
+            ulIdx = InterfaceToIndex(psDevice, (pUSBRequest->wIndex & 0xFF));
+            break;
+        }
+
+        case USB_RTYPE_ENDPOINT:
+        {
+            ulIdx = EndpointToIndex(psDevice, (pUSBRequest->wIndex & 0x0F),
+                             (pUSBRequest->wIndex & 0x80) ? true : false);
+            break;
+        }
+
+        //
+        // Requests sent to the device or any other recipient can't be
+        // handled here since we have no way of telling where they are
+        // supposed to be handled.  As a result, we just stall them.
+        //
+        // If your composite device has some device-specific requests that need
+        // to be handled at the device (rather than interface or endpoint)
+        // level, you should add code here to handle them.
+        //
+        case USB_RTYPE_DEVICE:
+        case USB_RTYPE_OTHER:
+        default:
+        {
+            ulIdx = INVALID_DEVICE_INDEX;
+            break;
+        }
+    }
+
+    //
+    // Did we find a device class to pass the request to?
+    //
+    if(ulIdx != INVALID_DEVICE_INDEX)
+    {
+        //
+        // Get a pointer to the individual device instance.
+        //
+        pDeviceInfo = psDevice->psDevices[ulIdx].psDevice;
+
+        //
+        // Does this device have a RequestHandler callback?
+        //
+        if(pDeviceInfo->sCallbacks.pfnRequestHandler)
+        {
+            //
+            // Remember this device index so that we can correctly route any
+            // data notification callbacks to it.
+            //
+            psDevice->psPrivateData->ulEP0Owner = ulIdx;
+
+            //
+            // Yes - call the device to retrieve the descriptor.
+            //
+            pDeviceInfo->sCallbacks.pfnRequestHandler(
+                    psDevice->psDevices[ulIdx].pvInstance, pUSBRequest);
+        }
+        else
+        {
+            //
+            // Oops - we can't satisfy the request so stall EP0 to indicate
+            // an error.
+            //
+            USBDCDStallEP0(
+                       USB_BASE_TO_INDEX(psDevice->psPrivateData->ulUSBBase));
+        }
+    }
+    else
+    {
+        //
+        // We are unable to satisfy the descriptor request so stall EP0 to
+        // indicate an error.
+        //
+        USBDCDStallEP0(USB_BASE_TO_INDEX(psDevice->psPrivateData->ulUSBBase));
+    }
+
+}
+
+//****************************************************************************
+//
+// This function handles sending interface number changes to device instances.
+//
+//****************************************************************************
+static void
+CompositeIfaceChange(tCompositeEntry *pCompDevice, unsigned char ucOld,
+                     unsigned char ucNew)
+{
+    unsigned char pucInterfaces[2];
+
+    if(pCompDevice->psDevice->sCallbacks.pfnDeviceHandler)
+    {
+        //
+        // Create the data to pass to the device handler.
+        //
+        pucInterfaces[0] = ucOld;
+        pucInterfaces[1] = ucNew;
+
+        //
+        // Call the device handler to inform the class of the interface number
+        // change.
+        //
+        pCompDevice->psDevice->sCallbacks.pfnDeviceHandler(
+            pCompDevice->pvInstance, USB_EVENT_COMP_IFACE_CHANGE,
+            (void *)pucInterfaces);
+    }
+}
+
+//****************************************************************************
+//
+// This function handles sending endpoint number changes to device instances.
+//
+//****************************************************************************
+static void
+CompositeEPChange(tCompositeEntry *pCompDevice, unsigned char ucOld,
+                     unsigned char ucNew)
+{
+    unsigned char pucInterfaces[2];
+    unsigned char ucIndex;
+
+    if(pCompDevice->psDevice->sCallbacks.pfnDeviceHandler)
+    {
+        //
+        // Create the data to pass to the device handler.
+        //
+        pucInterfaces[0] = ucOld;
+        pucInterfaces[1] = ucNew;
+
+        ucNew--;
+
+        if(ucOld & USB_RTYPE_DIR_IN)
+        {
+            ucIndex = (ucOld & ~USB_RTYPE_DIR_IN) - 1;
+
+            g_sUSBCompositeFIFOConfig.sIn[ucNew].bDoubleBuffer =
+                pCompDevice->psDevice->psFIFOConfig->sIn[ucIndex].bDoubleBuffer;
+
+            g_sUSBCompositeFIFOConfig.sIn[ucNew].cMultiplier =
+                pCompDevice->psDevice->psFIFOConfig->sIn[ucIndex].cMultiplier;
+
+            g_sUSBCompositeFIFOConfig.sIn[ucNew].usEPFlags =
+                pCompDevice->psDevice->psFIFOConfig->sIn[ucIndex].usEPFlags;
+        }
+        else
+        {
+            ucIndex = ucOld - 1;
+
+            g_sUSBCompositeFIFOConfig.sOut[ucNew].bDoubleBuffer =
+               pCompDevice->psDevice->psFIFOConfig->sOut[ucIndex].bDoubleBuffer;
+
+            g_sUSBCompositeFIFOConfig.sOut[ucNew].cMultiplier =
+                pCompDevice->psDevice->psFIFOConfig->sOut[ucIndex].cMultiplier;
+
+            g_sUSBCompositeFIFOConfig.sOut[ucNew].usEPFlags =
+                pCompDevice->psDevice->psFIFOConfig->sOut[ucIndex].usEPFlags;
+        }
+        //
+        // Call the device handler to inform the class of the interface number
+        // change.
+        //
+        pCompDevice->psDevice->sCallbacks.pfnDeviceHandler(
+            pCompDevice->pvInstance, USB_EVENT_COMP_EP_CHANGE,
+            (void *)pucInterfaces);
+    }
+}
+
+//****************************************************************************
+//
+// This function merges the configuration descriptors into a single multiple
+// instance device.
+//
+//****************************************************************************
+unsigned long
+BuildCompositeDescriptor(tUSBDCompositeDevice *psCompDevice)
+{
+    unsigned long ulIdx, ulOffset, ulCPIdx, ulFixINT, ulDev;
+    unsigned short usTotalLength, usBytes;
+    unsigned char ucInterface, ucINEndpoint, ucOUTEndpoint;
+    unsigned char *pucData, *pucConfig;
+    const tConfigHeader *pConfigHeader;
+    tDescriptorHeader *psHeader;
+    const unsigned char *pucDescriptor;
+    tInterfaceDescriptor *psInterface;
+    tEndpointDescriptor *psEndpoint;
+    const tDeviceInfo *psDevice;
+
+    //
+    // Save the number of devices to look through.
+    //
+    ulDev = 0;
+    ulIdx = 0;
+    ucInterface = 0;
+    ucINEndpoint = 1;
+    ucOUTEndpoint = 1;
+    ulOffset = 0;
+    ulFixINT = 0;
+
+    //
+    // This puts the first section pointer in the first entry in the list
+    // of sections.
+    //
+    psCompDevice->psPrivateData->ppsCompSections[0] =
+        &psCompDevice->psPrivateData->psCompSections[0];
+
+    //
+    // Put the pointer to this instances configuration descriptor into the
+    // front of the list.
+    //
+    psCompDevice->psPrivateData->ppsCompSections[0]->pucData =
+        (unsigned char *)&psCompDevice->psPrivateData->sConfigDescriptor;
+
+    psCompDevice->psPrivateData->ppsCompSections[0]->ucSize =
+        psCompDevice->psPrivateData->sConfigDescriptor.bLength;
+
+    //
+    // The configuration descriptor is 9 bytes so initialize the total length
+    // to 9 bytes.
+    //
+    usTotalLength = 9;
+
+    //
+    // Copy the section pointer into the section array for the composite
+    // device.  This is awkward but is required given the definition
+    // of the structures.
+    //
+    psCompDevice->psPrivateData->ppsCompSections[1] =
+        &psCompDevice->psPrivateData->psCompSections[1];
+
+    //
+    // Copy the pointer to the application supplied space into the section
+    // list.
+    //
+    psCompDevice->psPrivateData->ppsCompSections[1]->ucSize = 0;
+    psCompDevice->psPrivateData->ppsCompSections[1]->pucData =
+        psCompDevice->psPrivateData->pucData;
+
+    //
+    // Create a local pointer to the data that is used to copy data from
+    // the other devices into the composite descriptor.
+    //
+    pucData = psCompDevice->psPrivateData->pucData;
+
+    //
+    // Consider each device in turn.
+    //
+    while(ulDev < psCompDevice->ulNumDevices)
+    {
+        //
+        // Save the current starting address of this descriptor.
+        //
+        pucConfig = pucData + ulOffset;
+
+        //
+        // Create a local pointer to the configuration header.
+        //
+        psDevice = psCompDevice->psDevices[ulDev].psDevice;
+        pConfigHeader = psDevice->ppConfigDescriptors[0];
+
+        //
+        // Loop through each of the sections in this device's configuration
+        // descriptor.
+        //
+        for(ulIdx = 0; ulIdx < pConfigHeader->ucNumSections; ulIdx++)
+        {
+            //
+            // Initialize the local offset in this descriptor.  We include
+            // a special case here to ignore the initial 9 byte config
+            // descriptor since this has already been handled.
+            //
+            if(ulIdx)
+            {
+                //
+                // This is not the first section so we handle everything in
+                // it.
+                //
+                usBytes = 0;
+            }
+            else
+            {
+                //
+                // This is the first section for this device so skip the 9
+                // byte config descriptor since we've already handled this.
+                //
+                usBytes = 9;
+
+                //
+                // If this section includes only the config descriptor, skip
+                // it entirely.
+                //
+                if(pConfigHeader->psSections[ulIdx]->ucSize <= usBytes)
+                {
+                    continue;
+                }
+            }
+
+            //
+            // Get a pointer to the configuration descriptor.
+            //
+            pucDescriptor = pConfigHeader->psSections[ulIdx]->pucData;
+
+            //
+            // Bounds check the allocated space and return if there is not
+            // enough space.
+            //
+            if(ulOffset > psCompDevice->psPrivateData->ulDataSize)
+            {
+                return(1);
+            }
+
+            //
+            // Copy the descriptor from the device into the descriptor list.
+            //
+            for(ulCPIdx = 0;
+                ulCPIdx < pConfigHeader->psSections[ulIdx]->ucSize;
+                ulCPIdx++)
+            {
+                pucData[ulCPIdx + ulOffset] = pucDescriptor[ulCPIdx];
+            }
+
+            //
+            // Read out the descriptors in this section.
+            //
+            while(usBytes < pConfigHeader->psSections[ulIdx]->ucSize)
+            {
+                //
+                // Create a descriptor header pointer.
+                //
+                psHeader = (tDescriptorHeader *)&pucData[ulOffset + usBytes];
+
+                //
+                // Check for interface descriptors and modify the numbering to
+                // match the composite device.
+                //
+                if(psHeader->bDescriptorType == USB_DTYPE_INTERFACE)
+                {
+                    psInterface = (tInterfaceDescriptor *)psHeader;
+
+                    //
+                    // See if this is an alternate setting or the initial
+                    // setting.
+                    //
+                    if(psInterface->bAlternateSetting != 0)
+                    {
+                        //
+                        // If this is an alternate setting then use the
+                        // previous interface number because the current one
+                        // has already been incremented.
+                        //
+                        psInterface->bInterfaceNumber = ucInterface - 1;
+                    }
+                    else
+                    {
+                        //
+                        // Notify the class that it's interface number has
+                        // changed.
+                        //
+                        CompositeIfaceChange(&psCompDevice->psDevices[ulDev],
+                                             psInterface->bInterfaceNumber,
+                                             ucInterface);
+                        //
+                        // This was the non-alternate setting so save the
+                        // value and move to the next interface number.
+                        //
+                        psInterface->bInterfaceNumber = ucInterface;
+
+                        //
+                        // No strings allowed on interface descriptors for
+                        // composite devices.
+                        //
+                        psInterface->iInterface = 0;
+
+                        ucInterface++;
+                    }
+                }
+                //
+                // Check for endpoint descriptors and modify the numbering to
+                // match the composite device.
+                //
+                else if(psHeader->bDescriptorType == USB_DTYPE_ENDPOINT)
+                {
+                    psEndpoint = (tEndpointDescriptor *)psHeader;
+
+                    //
+                    // Check if this is an IN or OUT endpoint.
+                    //
+                    if(psEndpoint->bEndpointAddress & USB_RTYPE_DIR_IN)
+                    {
+                        //
+                        // Check if this is the special Fixed Interrupt class
+                        // and this is the interrupt endpoint.
+                        //
+                        if(((psEndpoint->bmAttributes & USB_EP_ATTR_TYPE_M) ==
+                                USB_EP_ATTR_INT) &&
+                           (psCompDevice->usPID == USB_PID_COMP_SERIAL))
+                        {
+                            //
+                            // Check if the Fixed Interrupt endpoint has been
+                            // set yet.
+                            //
+                            if(ulFixINT == 0)
+                            {
+                                //
+                                // Allocate the fixed interrupt endpoint and
+                                // save its number.
+                                //
+                                ulFixINT = ucINEndpoint++;
+                            }
+
+                            CompositeEPChange(&psCompDevice->psDevices[ulDev],
+                                              psEndpoint->bEndpointAddress,
+                                              ulFixINT);
+
+                            psEndpoint->bEndpointAddress = ulFixINT |
+                                                           USB_RTYPE_DIR_IN;
+                        }
+                        else
+                        {
+                            //
+                            // Notify the class that it's interface number has
+                            // changed.
+                            //
+                            CompositeEPChange(&psCompDevice->psDevices[ulDev],
+                                              psEndpoint->bEndpointAddress,
+                                              ucINEndpoint);
+
+                            psEndpoint->bEndpointAddress = ucINEndpoint++ |
+                                                           USB_RTYPE_DIR_IN;
+                        }
+                    }
+                    else
+                    {
+                        //
+                        // Notify the class that it's interface number has
+                        // changed.
+                        //
+                        CompositeEPChange(&psCompDevice->psDevices[ulDev],
+                                          psEndpoint->bEndpointAddress,
+                                          ucOUTEndpoint);
+                        psEndpoint->bEndpointAddress = ucOUTEndpoint++;
+                    }
+                }
+
+                //
+                // Move on to the next descriptor.
+                //
+                usBytes += psHeader->bLength;
+            }
+
+            ulOffset += pConfigHeader->psSections[ulIdx]->ucSize;
+
+            usTotalLength += usBytes;
+        }
+
+        //
+        // Allow the device class to make adjustments to the configuration
+        // descriptor.
+        //
+        psCompDevice->psDevices[ulDev].psDevice->sCallbacks.pfnDeviceHandler(
+                psCompDevice->psDevices[ulDev].pvInstance,
+                USB_EVENT_COMP_CONFIG, (void *)pucConfig);
+
+        //
+        // Add an entry into the device workspace array to allow us to quickly
+        // map interface and endpoint numbers to device instances later.
+        //
+        psCompDevice->pulDeviceWorkspace[ulDev] =
+            (ulDev << (LOOKUP_INDEX_BYTE * 8)) |
+            (ucInterface << (LOOKUP_INTERFACE_BYTE * 8)) |
+            (ucOUTEndpoint << (LOOKUP_OUT_END_BYTE * 8)) |
+            (ucINEndpoint << (LOOKUP_IN_END_BYTE * 8));
+
+        //
+        // Move on to the next device.
+        //
+        ulDev++;
+    }
+
+    //
+    // Modify the configuration descriptor to match the number of interfaces
+    // and the new total size.
+    //
+    psCompDevice->psPrivateData->sCompConfigHeader.ucNumSections = 2;
+    psCompDevice->psPrivateData->ppsCompSections[1]->ucSize = ulOffset;
+    psCompDevice->psPrivateData->sConfigDescriptor.bNumInterfaces =
+       ucInterface;
+    psCompDevice->psPrivateData->sConfigDescriptor.wTotalLength =
+       usTotalLength;
+
+
+    return(0);
+}
+
+//****************************************************************************
+//
+//! This function should be called once for the composite class device to
+//! initialize basic operation and prepare for enumeration.
+//!
+//! \param ulIndex is the index of the USB controller to initialize for
+//! composite device operation.
+//! \param psDevice points to a structure containing parameters customizing
+//! the operation of the composite device.
+//! \param ulSize is the size in bytes of the data pointed to by the
+//! \e pucData parameter.
+//! \param pucData is the data area that the composite class can use to build
+//! up descriptors.
+//!
+//! In order for an application to initialize the USB composite device class,
+//! it must first call this function with the a valid composite device class
+//! structure in the \e psDevice parameter.  This allows this function to
+//! initialize the USB controller and device code to be prepared to enumerate
+//! and function as a USB composite device.  The \e ulSize and \e pucData
+//! parameters should be large enough to hold all of the class instances
+//! passed in via the psDevice structure.  This is typically the full size of
+//! the configuration descriptor for a device minus its configuration
+//! header(9 bytes).
+//!
+//! This function returns a void pointer that must be passed in to all other
+//! APIs used by the composite class.
+//!
+//! See the documentation on the tUSBDCompositeDevice structure for more
+//! information on how to properly fill the structure members.
+//!
+//! \return This function returns 0 on failure or a non-zero void pointer on
+//! success.
+//
+//****************************************************************************
+void *
+USBDCompositeInit(unsigned long ulIndex, tUSBDCompositeDevice *psDevice,
+        unsigned long ulSize, unsigned char *pucData)
+{
+    tCompositeInstance *psInst;
+    long lIdx;
+    unsigned char *pucTemp;
+
+    //
+    // Check parameter validity.
+    //
+    ASSERT(ulIndex == 0);
+    ASSERT(psDevice);
+    ASSERT(psDevice->ppStringDescriptors);
+    ASSERT(psDevice->psPrivateData);
+
+    //
+    // Initialize the work space in the passed instance structure.
+    //
+    psInst = psDevice->psPrivateData;
+    psInst->ulDataSize = ulSize;
+    psInst->pucData = pucData;
+
+    //
+    // Save the base address of the USB controller.
+    //
+    psInst->ulUSBBase = USB_INDEX_TO_BASE(ulIndex);
+
+    //
+    // No device is currently transfering data on EP0.
+    //
+    psInst->ulEP0Owner = INVALID_DEVICE_INDEX;
+
+    //
+    // Set the device information for the composite device.
+    //
+    psInst->psDevInfo = &g_sCompositeDeviceInfo;
+
+    g_pCompConfigDescriptors[0] = &psInst->sCompConfigHeader;
+    g_pCompConfigDescriptors[0]->ucNumSections = 0;
+    g_pCompConfigDescriptors[0]->psSections =
+      (const tConfigSection * const *)psDevice->psPrivateData->ppsCompSections;
+
+    //
+    // Create a byte pointer to use with the copy.
+    //
+    pucTemp = (unsigned char *)&psInst->sConfigDescriptor;
+
+    //
+    // Copy the default configuration descriptor into the instance data.
+    //
+    for(lIdx = 0; lIdx < g_pCompConfigDescriptor[0]; lIdx++)
+    {
+        pucTemp[lIdx] = g_pCompConfigDescriptor[lIdx];
+    }
+
+    //
+    // Create a byte pointer to use with the copy.
+    //
+    pucTemp = (unsigned char *)&psInst->sDeviceDescriptor;
+
+    //
+    // Copy the default configuration descriptor into the instance data.
+    //
+    for(lIdx = 0; lIdx < g_pCompDeviceDescriptor[0]; lIdx++)
+    {
+        pucTemp[lIdx] = g_pCompDeviceDescriptor[lIdx];
+    }
+
+    //
+    // Fix up the device descriptor with the client-supplied values.
+    //
+    psInst->sDeviceDescriptor.idVendor = psDevice->usVID;
+    psInst->sDeviceDescriptor.idProduct = psDevice->usPID;
+
+    //
+    // Fix up the configuration descriptor with client-supplied values.
+    //
+    psInst->sConfigDescriptor.bmAttributes = psDevice->ucPwrAttributes;
+    psInst->sConfigDescriptor.bMaxPower =
+        (unsigned char)(psDevice->usMaxPowermA>>1);
+
+    g_sCompositeDeviceInfo.pDeviceDescriptor =
+        (const unsigned char *)&psInst->sDeviceDescriptor;
+
+    //
+    // Plug in the client's string table to the device information
+    // structure.
+    //
+    psInst->psDevInfo->ppStringDescriptors = psDevice->ppStringDescriptors;
+    psInst->psDevInfo->ulNumStringDescriptors =
+        psDevice->ulNumStringDescriptors;
+
+    //
+    // Enable Clocking to the USB controller so that changes to the USB
+    // controller can be made in the BuildCompositeDescriptor() function.
+    //
+    MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_USB0);
+
+    //
+    // Create the combined descriptors.
+    //
+    if(BuildCompositeDescriptor(psDevice))
+    {
+        return(0);
+    }
+
+    //
+    // Set the instance data for this device.
+    //
+    psInst->psDevInfo->pvInstance = (void *)psDevice;
+
+    //
+    // All is well so now pass the descriptors to the lower layer and put
+    // the bulk device on the bus.
+    //
+    USBDCDInit(ulIndex, psInst->psDevInfo);
+
+    //
+    // Return the pointer to the instance indicating that everything went
+    // well.
+    //
+    return((void *)psDevice);
+}
+
+//****************************************************************************
+//
+//! Shuts down the composite device.
+//!
+//! \param pvInstance is the pointer to the device instance structure as
+//! returned by USBDCompositeInit().
+//!
+//! This function terminates composite device interface for the instance
+//! supplied. Following this call, the \e pvInstance instance should not me
+//! used in any other calls.
+//!
+//! \return None.
+//
+//****************************************************************************
+void
+USBDCompositeTerm(void *pvInstance)
+{
+    ASSERT(pvInstance != 0);
+
+}
+
+//****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//****************************************************************************
+
diff --git a/src/platform/lm3s/usblib/device/usbdcomp.h b/src/platform/lm3s/usblib/device/usbdcomp.h
new file mode 100755
index 00000000..3f8d0144
--- /dev/null
+++ b/src/platform/lm3s/usblib/device/usbdcomp.h
@@ -0,0 +1,297 @@
+//*****************************************************************************
+//
+// usbdcomp.h - USB composite device class driver.
+//
+// Copyright (c) 2010-2011 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 7611 of the Stellaris USB Library.
+//
+//*****************************************************************************
+
+#ifndef __USBDCOMP_H__
+#define __USBDCOMP_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Return to default packing when using the IAR Embedded Workbench compiler.
+//
+//*****************************************************************************
+#ifdef ewarm
+#pragma pack()
+#endif
+
+//*****************************************************************************
+//
+//! \addtogroup composite_device_class_api
+//! @{
+//
+//*****************************************************************************
+
+//
+// Defines a single entry in a table of device types supported by the composite
+// device.
+//
+typedef struct
+{
+    //
+    // This is set internally by the composite class so it can be left
+    // uninitialized by the application.
+    //
+    const tDeviceInfo *pDeviceInfo;
+
+    //
+    // This should be the header to the configuration header for a class.
+    //
+    const tConfigHeader *psConfigHeader;
+
+    //
+    // The offset to this devices interface, filled in by the composite class.
+    //
+    unsigned char ucIfaceOffset;
+
+} tUSBDCompositeEntry;
+
+//*****************************************************************************
+//
+// PRIVATE
+//
+// This structure defines the private instance data and state variables for the
+// composite device class.  The memory for this structure is pointed to by
+// the psPrivateData field in the tUSBDCompositeDevice structure passed on
+// USBDCompositeInit() and should not be modified by any code outside of the
+// composite device code.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    // Saves which USB controller is in use.
+    //
+    unsigned long ulUSBBase;
+
+    //
+    // The device information pointer.
+    //
+    tDeviceInfo *psDevInfo;
+
+    //
+    // This is the configuration descriptor for this instance.
+    //
+    tConfigDescriptor sConfigDescriptor;
+
+    //
+    // This is the device descriptor for this instance.
+    //
+    tDeviceDescriptor sDeviceDescriptor;
+
+    //
+    // The configuration header for this instance.
+    //
+    tConfigHeader sCompConfigHeader;
+
+    //
+    // These are the configuration sections that will be built from the
+    // Configuration Descriptor header and the descriptors from the devices
+    // that are part of this composite device.
+    //
+    tConfigSection psCompSections[2];
+    tConfigSection *ppsCompSections[2];
+
+    //
+    // The size and pointer to the data used by the instance.
+    //
+    unsigned long ulDataSize;
+    unsigned char *pucData;
+
+    //
+    // The current "owner" of endpoint 0.  This is used to track the device
+    // class which is currently transfering data on EP0.
+    //
+    unsigned long ulEP0Owner;
+}
+tCompositeInstance;
+
+//*****************************************************************************
+//
+//! This type is used by an application to describe and instance of a device
+//! and an instance data pointer for that class.  The psDevice pointer should
+//! be a pointer to a valid device class to include in the composite device.
+//! The pvInstance pointer should be a pointer to an instance pointer for the
+//! device in the psDevice pointer.
+//!
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! This is the top level device information structure.
+    //
+    const tDeviceInfo *psDevice;
+
+    //
+    //! This is the instance data for the device structure.
+    //
+    void *pvInstance;
+}
+tCompositeEntry;
+
+//*****************************************************************************
+//
+//! The structure used by the application to define operating parameters for
+//! the composite device class.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! The vendor ID that this device is to present in the device descriptor.
+    //
+    unsigned short usVID;
+
+    //
+    //! The product ID that this device is to present in the device descriptor.
+    //
+    unsigned short usPID;
+
+    //
+    //! The maximum power consumption of the device, expressed in mA.
+    //
+    unsigned short usMaxPowermA;
+
+    //
+    //! Indicates whether the device is self or bus-powered and whether or not
+    //! it supports remote wake up.  Valid values are USB_CONF_ATTR_SELF_PWR or
+    //! USB_CONF_ATTR_BUS_PWR, optionally ORed with USB_CONF_ATTR_RWAKE.
+    //
+    unsigned char ucPwrAttributes;
+
+    //
+    //! A pointer to the callback function which will be called to notify
+    //! the application of events relating to the operation of the composite
+    //! device.
+    //
+    tUSBCallback pfnCallback;
+
+    //
+    //! A pointer to the string descriptor array for this device.  This array
+    //! must contain the following string descriptor pointers in this order.
+    //! Language descriptor, Manufacturer name string (language 1), Product
+    //! name string (language 1), Serial number string (language 1), Composite
+    //! device interface description string (language 1), Configuration
+    //! description string (language 1).
+    //!
+    //! If supporting more than 1 language, the descriptor block (except for
+    //! string descriptor 0) must be repeated for each language defined in the
+    //! language descriptor.
+    //!
+    //
+    const unsigned char * const *ppStringDescriptors;
+
+    //
+    //! The number of descriptors provided in the ppStringDescriptors
+    //! array.  This must be 1 + ((5 + (number of strings)) *
+    //!                           (number of languages)).
+    //
+    unsigned long ulNumStringDescriptors;
+
+    //
+    //! The number of devices in the psDevices array.
+    //
+    unsigned long ulNumDevices;
+
+    //
+    //! This application supplied array holds the the top level device class
+    //! information as well as the Instance data for that class.
+    //
+    tCompositeEntry *psDevices;
+
+    //
+    //! A pointer to per-device workspace used by the composite device.  This
+    //! buffer must be sized to contain at least ulNumDevices long integers
+    //! (or 4 * ulNumDevices bytes).  It must remain accessible for as long as
+    //! the composite device is in use and must not be modified by any code
+    //! outside the composite class driver.
+    //
+    unsigned long *pulDeviceWorkspace;
+
+    //
+    //! A pointer to RAM work space for this device instance.  The client
+    //! must fill in this field with a pointer to at least
+    //! sizeof(tCompositeInstance) bytes of read/write storage that the
+    //! library can use for driver work space.  This memory must remain
+    //! accessible for as long as the composite device is in use and must not
+    //! be modified by any code outside the composite class driver.
+    //
+    tCompositeInstance *psPrivateData;
+}
+tUSBDCompositeDevice;
+
+//*****************************************************************************
+//
+// Return to default packing when using the IAR Embedded Workbench compiler.
+//
+//*****************************************************************************
+#ifdef ewarm
+#pragma pack()
+#endif
+
+//*****************************************************************************
+//
+// Composite specific device class driver events
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// API Function Prototypes
+//
+//*****************************************************************************
+extern void *USBDCompositeInit(unsigned long ulIndex,
+                               tUSBDCompositeDevice *psCompDevice,
+                               unsigned long ulSize,
+                               unsigned char *pucData);
+extern void USBDCompositeTerm(void *pvInstance);
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
diff --git a/src/platform/lm3s/usblib/device/usbdconfig.c b/src/platform/lm3s/usblib/device/usbdconfig.c
new file mode 100755
index 00000000..3c2a8824
--- /dev/null
+++ b/src/platform/lm3s/usblib/device/usbdconfig.c
@@ -0,0 +1,669 @@
+//*****************************************************************************
+//
+// usbdconfig.c - High level USB device configuration function.
+//
+// Copyright (c) 2008-2011 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 7611 of the Stellaris USB Library.
+//
+//*****************************************************************************
+
+#include "inc/hw_memmap.h"
+#include "inc/hw_types.h"
+#include "driverlib/debug.h"
+#include "driverlib/usb.h"
+#include "usblib/usblib.h"
+#include "usblib/device/usbdevice.h"
+
+//*****************************************************************************
+//
+//! \addtogroup device_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Mask used to preserve various endpoint configuration flags.
+//
+//*****************************************************************************
+#define EP_FLAGS_MASK           (USB_EP_MODE_MASK | USB_EP_DEV_IN |           \
+                                 USB_EP_DEV_OUT)
+
+//*****************************************************************************
+//
+// Structure used in compiling FIFO size and endpoint properties from a
+// configuration descriptor.
+//
+//*****************************************************************************
+typedef struct
+{
+    unsigned long ulSize[2];
+    unsigned long ulType[2];
+}
+tUSBEndpointInfo;
+
+//*****************************************************************************
+//
+// Indices used when accessing the tUSBEndpointInfo structure.
+//
+//*****************************************************************************
+#define EP_INFO_IN              0
+#define EP_INFO_OUT             1
+
+//*****************************************************************************
+//
+// Given a maximum packet size and the user's FIFO scaling requirements,
+// determine the flags to use to configure the endpoint FIFO and the number
+// of bytes of FIFO space occupied.
+//
+//*****************************************************************************
+static unsigned long
+GetEndpointFIFOSize(unsigned long ulMaxPktSize, const tFIFOEntry *psFIFOParams,
+                    unsigned long *pupBytesUsed)
+{
+    unsigned long ulBytes;
+    unsigned long ulLoop;
+    unsigned long ulFIFOSize;
+
+    //
+    // A zero multiplier would not be a good thing.
+    //
+    ASSERT(psFIFOParams->cMultiplier);
+
+    //
+    // What is the basic size required for a single buffered FIFO entry
+    // containing the required number of packets?
+    //
+    ulBytes = ulMaxPktSize * (unsigned long)psFIFOParams->cMultiplier;
+
+    //
+    // Now we need to find the nearest supported size that accommodates the
+    // requested size.  Step through each of the supported sizes until we
+    // find one that will do.
+    //
+    for(ulLoop = USB_FIFO_SZ_8; ulLoop <= USB_FIFO_SZ_4096; ulLoop++)
+    {
+        //
+        // How many bytes does this FIFO value represent?
+        //
+        ulFIFOSize = USB_FIFO_SZ_TO_BYTES(ulLoop);
+
+        //
+        // Is this large enough to satisfy the request?
+        //
+        if(ulFIFOSize >= ulBytes)
+        {
+            //
+            // Yes - are we being asked to double-buffer the FIFO for this
+            // endpoint?
+            //
+            if(psFIFOParams->bDoubleBuffer)
+            {
+                //
+                // Yes - FIFO requirement is double in this case.
+                //
+                *pupBytesUsed = ulFIFOSize * 2;
+                return(ulLoop | USB_FIFO_SIZE_DB_FLAG);
+            }
+            else
+            {
+                //
+                // No double buffering so just return the size and associated
+                // flag.
+                //
+                *pupBytesUsed = ulFIFOSize;
+                return(ulLoop);
+            }
+        }
+    }
+
+    //
+    // If we drop out, we can't support the FIFO size requested.  Signal a
+    // problem by returning 0 in the pBytesUsed
+    //
+    *pupBytesUsed = 0;
+    return(USB_FIFO_SZ_8);
+}
+
+//*****************************************************************************
+//
+// Translate a USB endpoint descriptor into the values we need to pass to the
+// USBDevEndpointConfigSet() API.
+//
+//*****************************************************************************
+static void
+GetEPDescriptorType(tEndpointDescriptor *psEndpoint, unsigned long *pulEPIndex,
+                    unsigned long *pulMaxPktSize, unsigned long *pulFlags)
+{
+    //
+    // Get the endpoint index.
+    //
+    *pulEPIndex = psEndpoint->bEndpointAddress & USB_EP_DESC_NUM_M;
+
+    //
+    // Extract the maximum packet size.
+    //
+    *pulMaxPktSize = psEndpoint->wMaxPacketSize & USB_EP_MAX_PACKET_COUNT_M;
+
+    //
+    // Is this an IN or an OUT endpoint?
+    //
+    *pulFlags = (psEndpoint->bEndpointAddress & USB_EP_DESC_IN) ?
+                 USB_EP_DEV_IN : USB_EP_DEV_OUT;
+
+    //
+    // Set the endpoint mode.
+    //
+    switch(psEndpoint->bmAttributes & USB_EP_ATTR_TYPE_M)
+    {
+        case USB_EP_ATTR_CONTROL:
+            *pulFlags |= USB_EP_MODE_CTRL;
+            break;
+
+        case USB_EP_ATTR_BULK:
+            *pulFlags |= USB_EP_MODE_BULK;
+            break;
+
+        case USB_EP_ATTR_INT:
+            *pulFlags |= USB_EP_MODE_INT;
+            break;
+
+        case USB_EP_ATTR_ISOC:
+            *pulFlags |= USB_EP_MODE_ISOC;
+            break;
+    }
+}
+
+//*****************************************************************************
+//
+//! Configure the USB controller appropriately for the device whose config
+//! descriptor is passed.
+//!
+//! \param ulIndex is the zero-based index of the USB controller which is to
+//! be configured.
+//! \param psConfig is a pointer to the configuration descriptor that the
+//! USB controller is to be set up to support.
+//! \param psFIFOConfig is a pointer to an array of NUM_USB_EP tFIFOConfig
+//! structures detailing how the FIFOs are to be set up for each endpoint
+//! used by the configuration.
+//!
+//! This function may be used to initialize a USB controller to operate as
+//! the device whose configuration descriptor is passed.  The function
+//! enables the USB controller, partitions the FIFO appropriately and
+//! configures each endpoint required by the configuration.  If the supplied
+//! configuration supports multiple alternate settings for any interface,
+//! the USB FIFO is set up assuming the worst case use (largest packet size
+//! for a given endpoint in any alternate setting using that endpoint) to
+//! allow for on-the-fly alternate setting changes later.  On return from this
+//! function, the USB controller is configured for correct operation of
+//! the default configuration of the device described by the descriptor passed.
+//!
+//! The \e psFIFOConfig parameter allows the caller to provide additional
+//! information on USB FIFO configuration that cannot be determined merely
+//! by parsing the configuration descriptor.  The descriptor provides
+//! information on the endpoints that are to be used and the maximum packet
+//! size for each but cannot determine whether, for example, double buffering
+//! is to be used or how many packets the application wants to be able to
+//! store in a given endpoint's FIFO.
+//!
+//! USBDCDConfig() is an optional call and applications may chose to make
+//! direct calls to SysCtlPeripheralEnable(), SysCtlUSBPLLEnable(),
+//! USBDevEndpointConfigSet() and USBFIFOConfigSet() instead of using this
+//! function.  If this function is used, it must be called prior to
+//! USBDCDInit() since this call assumes that the low level hardware
+//! configuration has been completed before it is made.
+//!
+//! \return Returns \b true on success or \b false on failure.
+//
+//*****************************************************************************
+tBoolean
+USBDeviceConfig(unsigned long ulIndex, const tConfigHeader *psConfig,
+                const tFIFOConfig *psFIFOConfig)
+{
+    unsigned long ulLoop;
+    unsigned long ulCount;
+    unsigned long ulNumInterfaces;
+    unsigned long ulEpIndex;
+    unsigned long ulEpType;
+    unsigned long ulMaxPkt;
+    unsigned long ulNumEndpoints;
+    unsigned long ulFlags;
+    unsigned long ulBytesUsed;
+    unsigned long ulSection;
+    tInterfaceDescriptor *psInterface;
+    tEndpointDescriptor *psEndpoint;
+    tUSBEndpointInfo psEPInfo[NUM_USB_EP - 1];
+
+    //
+    // We only support 1 USB controller currently.
+    //
+    ASSERT(ulIndex == 0);
+
+    //
+    // Catch bad pointers in a debug build.
+    //
+    ASSERT(psConfig);
+    ASSERT(psFIFOConfig);
+
+    //
+    // Clear out our endpoint info.
+    //
+    for(ulLoop = 0; ulLoop < (NUM_USB_EP - 1); ulLoop++)
+    {
+        psEPInfo[ulLoop].ulSize[EP_INFO_IN] = 0;
+        psEPInfo[ulLoop].ulType[EP_INFO_IN] = 0;
+        psEPInfo[ulLoop].ulSize[EP_INFO_OUT] = 0;
+        psEPInfo[ulLoop].ulType[EP_INFO_OUT] = 0;
+    }
+
+    //
+    // How many (total) endpoints does this configuration describe?
+    //
+    ulNumEndpoints = USBDCDConfigDescGetNum(psConfig,
+                                            USB_DTYPE_ENDPOINT);
+
+    //
+    // How many interfaces are included?
+    //
+    ulNumInterfaces = USBDCDConfigDescGetNum(psConfig,
+                                             USB_DTYPE_INTERFACE);
+
+    //
+    // Look at each endpoint and determine the largest max packet size for
+    // each endpoint.  This will determine how we partition the USB FIFO.
+    //
+    for(ulLoop = 0; ulLoop < ulNumEndpoints; ulLoop++)
+    {
+        //
+        // Get a pointer to the endpoint descriptor.
+        //
+        psEndpoint = (tEndpointDescriptor *)USBDCDConfigDescGet(
+                                psConfig, USB_DTYPE_ENDPOINT, ulLoop,
+                                &ulSection);
+
+        //
+        // Extract the endpoint number and whether it is an IN or OUT
+        // endpoint.
+        //
+        ulEpIndex = (unsigned long)
+                        psEndpoint->bEndpointAddress & USB_EP_DESC_NUM_M;
+        ulEpType =  (psEndpoint->bEndpointAddress & USB_EP_DESC_IN) ?
+                     EP_INFO_IN : EP_INFO_OUT;
+
+        //
+        // Make sure the endpoint number is valid for our controller.  If not,
+        // return false to indicate an error.  Note that 0 is invalid since
+        // you shouldn't reference endpoint 0 in the config descriptor.
+        //
+        if((ulEpIndex >= NUM_USB_EP) || (ulEpIndex == 0))
+        {
+            return(false);
+        }
+
+        //
+        // Does this endpoint have a max packet size requirement larger than
+        // any previous use we have seen?
+        //
+        if(psEndpoint->wMaxPacketSize >
+           psEPInfo[ulEpIndex - 1].ulSize[ulEpType])
+        {
+            //
+            // Yes - remember the new maximum packet size.
+            //
+            psEPInfo[ulEpIndex - 1].ulSize[ulEpType] =
+                psEndpoint->wMaxPacketSize;
+        }
+    }
+
+    //
+    // At this point, we have determined the maximum packet size required
+    // for each endpoint by any possible alternate setting of any interface
+    // in this configuration.  Now determine the endpoint settings required
+    // for the interface setting we are actually going to use.
+    //
+    for(ulLoop = 0; ulLoop < ulNumInterfaces; ulLoop++)
+    {
+        //
+        // Get the next interface descriptor in the config descriptor.
+        //
+        psInterface = USBDCDConfigGetInterface(psConfig,
+                                               ulLoop,
+                                               USB_DESC_ANY,
+                                               &ulSection);
+
+        //
+        // Is this the default interface (bAlternateSetting set to 0)?
+        //
+        if(psInterface && (psInterface->bAlternateSetting == 0))
+        {
+            //
+            // This is an interface we are interested in so gather the
+            // information on its endpoints.
+            //
+            ulNumEndpoints = (unsigned long)psInterface->bNumEndpoints;
+
+            //
+            // Walk through each endpoint in this interface and configure
+            // it appropriately.
+            //
+            for(ulCount = 0; ulCount < ulNumEndpoints; ulCount++)
+            {
+                //
+                // Get a pointer to the endpoint descriptor.
+                //
+                psEndpoint = USBDCDConfigGetInterfaceEndpoint(psConfig,
+                                            psInterface->bInterfaceNumber,
+                                            psInterface->bAlternateSetting,
+                                            ulCount);
+
+                //
+                // Make sure we got a good pointer.
+                //
+                if(psEndpoint)
+                {
+                    //
+                    // Determine maximum packet size and flags from the
+                    // endpoint descriptor.
+                    //
+                    GetEPDescriptorType(psEndpoint, &ulEpIndex, &ulMaxPkt,
+                                        &ulFlags);
+
+                    //
+                    // Make sure no-one is trying to configure endpoint 0.
+                    //
+                    if(!ulEpIndex)
+                    {
+                        return(false);
+                    }
+
+                    //
+                    // Include any additional flags that the user wants.
+                    //
+                    if((ulFlags & (USB_EP_DEV_IN | USB_EP_DEV_OUT)) ==
+                        USB_EP_DEV_IN)
+                    {
+                        //
+                        // This is an IN endpoint.
+                        //
+                        ulFlags |= (unsigned long)(
+                                  psFIFOConfig->sIn[ulEpIndex - 1].usEPFlags);
+                        psEPInfo[ulEpIndex - 1].ulType[EP_INFO_IN] = ulFlags;
+                    }
+                    else
+                    {
+                        //
+                        // This is an OUT endpoint.
+                        //
+                        ulFlags |= (unsigned long)(
+                                  psFIFOConfig->sOut[ulEpIndex - 1].usEPFlags);
+                        psEPInfo[ulEpIndex - 1].ulType[EP_INFO_OUT] = ulFlags;
+                    }
+
+                    //
+                    // Set the endpoint configuration.
+                    //
+                    USBDevEndpointConfigSet(USB0_BASE,
+                                            INDEX_TO_USB_EP(ulEpIndex),
+                                            ulMaxPkt, ulFlags);
+                }
+            }
+        }
+    }
+
+    //
+    // At this point, we have configured all the endpoints that are to be
+    // used by this configuration's alternate setting 0.  Now we go on and
+    // partition the FIFO based on the maximum packet size information we
+    // extracted earlier.  Endpoint 0 is automatically configured to use the
+    // first MAX_PACKET_SIZE_EP0 bytes of the FIFO so we start from there.
+    //
+    ulCount = MAX_PACKET_SIZE_EP0;
+    for(ulLoop = 1; ulLoop < NUM_USB_EP; ulLoop++)
+    {
+        //
+        // Configure the IN endpoint at this index if it is referred to
+        // anywhere.
+        //
+        if(psEPInfo[ulLoop - 1].ulSize[EP_INFO_IN])
+        {
+            //
+            // What FIFO size flag do we use for this endpoint?
+            //
+            ulMaxPkt = GetEndpointFIFOSize(
+                                     psEPInfo[ulLoop - 1].ulSize[EP_INFO_IN],
+                                     &(psFIFOConfig->sIn[ulLoop - 1]),
+                                     &ulBytesUsed);
+
+            //
+            // If we are told that 0 bytes of FIFO will be used, this implies
+            // that there is an error in psFIFOConfig or the descriptor
+            // somewhere so return an error indicator to the caller.
+            //
+            if(!ulBytesUsed)
+            {
+                return(false);
+            }
+
+            //
+            // Now actually configure the FIFO for this endpoint.
+            //
+            USBFIFOConfigSet(USB0_BASE, INDEX_TO_USB_EP(ulLoop), ulCount,
+                             ulMaxPkt, USB_EP_DEV_IN);
+            ulCount += ulBytesUsed;
+        }
+
+        //
+        // Configure the OUT endpoint at this index.
+        //
+        if(psEPInfo[ulLoop - 1].ulSize[EP_INFO_OUT])
+        {
+            //
+            // What FIFO size flag do we use for this endpoint?
+            //
+            ulMaxPkt = GetEndpointFIFOSize(
+                                     psEPInfo[ulLoop - 1].ulSize[EP_INFO_OUT],
+                                     &(psFIFOConfig->sOut[ulLoop - 1]),
+                                     &ulBytesUsed);
+
+            //
+            // If we are told that 0 bytes of FIFO will be used, this implies
+            // that there is an error in psFIFOConfig or the descriptor
+            // somewhere so return an error indicator to the caller.
+            //
+            if(!ulBytesUsed)
+            {
+                return(false);
+            }
+
+            //
+            // Now actually configure the FIFO for this endpoint.
+            //
+            USBFIFOConfigSet(USB0_BASE, INDEX_TO_USB_EP(ulLoop), ulCount,
+                             ulMaxPkt, USB_EP_DEV_OUT);
+            ulCount += ulBytesUsed;
+        }
+
+    }
+
+    //
+    // If we get to the end, all is well.
+    //
+    return(true);
+}
+
+//*****************************************************************************
+//
+//! Configure the affected USB endpoints appropriately for one alternate
+//! interface setting.
+//!
+//! \param ulIndex is the zero-based index of the USB controller which is to
+//! be configured.
+//! \param psConfig is a pointer to the configuration descriptor that contains
+//! the interface whose alternate settings is to be configured.
+//! \param ucInterfaceNum is the number of the interface whose alternate
+//! setting is to be configured.  This number corresponds to the
+//! bInterfaceNumber field in the desired interface descriptor.
+//! \param ucAlternateSetting is the alternate setting number for the desired
+//! interface.  This number corresponds to the bAlternateSetting field in the
+//! desired interface descriptor.
+//!
+//! This function may be used to reconfigure the endpoints of an interface
+//! for operation in one of the interface's alternate settings.  Note that this
+//! function assumes that the endpoint FIFO settings will not need to change
+//! and only the endpoint mode is changed.  This assumption is valid if the
+//! USB controller was initialized using a previous call to USBDCDConfig().
+//!
+//! In reconfiguring the interface endpoints, any additional configuration
+//! bits set in the endpoint configuration other than the direction (\b
+//! USB_EP_DEV_IN or \b USB_EP_DEV_OUT) and mode (\b USB_EP_MODE_MASK) are
+//! preserved.
+//!
+//! \return Returns \b true on success or \b false on failure.
+//
+//*****************************************************************************
+tBoolean
+USBDeviceConfigAlternate(unsigned long ulIndex, const tConfigHeader *psConfig,
+                         unsigned char ucInterfaceNum,
+                         unsigned char ucAlternateSetting)
+{
+    unsigned long ulNumInterfaces;
+    unsigned long ulNumEndpoints;
+    unsigned long ulLoop;
+    unsigned long ulCount;
+    unsigned long ulMaxPkt;
+    unsigned long ulOldMaxPkt;
+    unsigned long ulFlags;
+    unsigned long ulOldFlags;
+    unsigned long ulSection;
+    unsigned long ulEpIndex;
+    tInterfaceDescriptor *psInterface;
+    tEndpointDescriptor *psEndpoint;
+
+    //
+    // How many interfaces are included in the descriptor?
+    //
+    ulNumInterfaces = USBDCDConfigDescGetNum(psConfig,
+                                             USB_DTYPE_INTERFACE);
+
+    //
+    // Find the interface descriptor for the supplied interface and alternate
+    // setting numbers.
+    //
+
+    for(ulLoop = 0; ulLoop < ulNumInterfaces; ulLoop++)
+    {
+        //
+        // Get the next interface descriptor in the config descriptor.
+        //
+        psInterface = USBDCDConfigGetInterface(psConfig, ulLoop, USB_DESC_ANY,
+                                               &ulSection);
+
+        //
+        // Is this the default interface (bAlternateSetting set to 0)?
+        //
+        if(psInterface &&
+           (psInterface->bInterfaceNumber == ucInterfaceNum) &&
+           (psInterface->bAlternateSetting == ucAlternateSetting))
+        {
+            //
+            // This is an interface we are interested in and the descriptor
+            // representing the alternate setting we want so go ahead and
+            // reconfigure the endpoints.
+            //
+
+            //
+            // How many endpoints does this interface have?
+            //
+            ulNumEndpoints = (unsigned long)psInterface->bNumEndpoints;
+
+            //
+            // Walk through each endpoint in turn.
+            //
+            for(ulCount = 0; ulCount < ulNumEndpoints; ulCount++)
+            {
+                //
+                // Get a pointer to the endpoint descriptor.
+                //
+                psEndpoint = USBDCDConfigGetInterfaceEndpoint(psConfig,
+                                              psInterface->bInterfaceNumber,
+                                              psInterface->bAlternateSetting,
+                                              ulCount);
+
+                //
+                // Make sure we got a good pointer.
+                //
+                if(psEndpoint)
+                {
+                    //
+                    // Determine maximum packet size and flags from the
+                    // endpoint descriptor.
+                    //
+                    GetEPDescriptorType(psEndpoint, &ulEpIndex, &ulMaxPkt,
+                                        &ulFlags);
+
+                    //
+                    // Make sure no-one is trying to configure endpoint 0.
+                    //
+                    if(!ulEpIndex)
+                    {
+                        return(false);
+                    }
+
+                    //
+                    // Get the existing endpoint configuration and mask in the
+                    // new mode and direction bits, leaving everything else
+                    // unchanged.
+                    //
+                    ulOldFlags = ulFlags;
+                    USBDevEndpointConfigGet(USB0_BASE,
+                                            INDEX_TO_USB_EP(ulEpIndex),
+                                            &ulOldMaxPkt,
+                                            &ulOldFlags);
+
+                    //
+                    // Mask in the previous DMA and auto-set bits.
+                    //
+                    ulFlags = (ulFlags & EP_FLAGS_MASK) |
+                              (ulOldFlags & ~EP_FLAGS_MASK);
+
+                    //
+                    // Set the endpoint configuration.
+                    //
+                    USBDevEndpointConfigSet(USB0_BASE,
+                                            INDEX_TO_USB_EP(ulEpIndex),
+                                            ulMaxPkt, ulFlags);
+                }
+            }
+
+            //
+            // At this point, we have reconfigured the desired interface so
+            // return indicating all is well.
+            //
+            return(true);
+        }
+    }
+
+    return(false);
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/src/platform/lm3s/usblib/device/usbddfu-rt.c b/src/platform/lm3s/usblib/device/usbddfu-rt.c
new file mode 100755
index 00000000..f06c7444
--- /dev/null
+++ b/src/platform/lm3s/usblib/device/usbddfu-rt.c
@@ -0,0 +1,589 @@
+//*****************************************************************************
+//
+// usbddfu-rt.c - USB Device Firmware Update runtime device class driver.
+//
+// Copyright (c) 2010-2011 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 7611 of the Stellaris USB Library.
+//
+//*****************************************************************************
+
+#include "inc/hw_memmap.h"
+#include "inc/hw_types.h"
+#include "inc/hw_nvic.h"
+#include "driverlib/debug.h"
+#include "driverlib/usb.h"
+#include "driverlib/sysctl.h"
+#include "driverlib/systick.h"
+#include "driverlib/interrupt.h"
+#include "driverlib/rom_map.h"
+#include "usblib/usblib.h"
+#include "usblib/usbdfu.h"
+#include "usblib/usb-ids.h"
+#include "usblib/device/usbdevice.h"
+#include "usblib/device/usbddfu-rt.h"
+#include "usblib/usblibpriv.h"
+
+//*****************************************************************************
+//
+//! \addtogroup dfu_device_class_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// DFU Device Descriptor.  This is a dummy structure since runtime DFU must be
+// a part of a composite device and cannot be instantiated on its own.
+//
+//*****************************************************************************
+const unsigned char g_pDFUDeviceDescriptor[] =
+{
+    18,                         // Size of this structure.
+    USB_DTYPE_DEVICE,           // Type of this structure.
+    USBShort(0x110),            // USB version 1.1 (if we say 2.0, hosts assume
+                                // high-speed - see USB 2.0 spec 9.2.6.6)
+    USB_CLASS_VEND_SPECIFIC,    // USB Device Class
+    0,                          // USB Device Sub-class
+    0,                          // USB Device protocol
+    64,                         // Maximum packet size for default pipe.
+    USBShort(0),                // Vendor ID (VID).
+    USBShort(0),                // Product ID (PID).
+    USBShort(0),                // Device Release Number BCD.
+    0,                          // Manufacturer string identifier.
+    0,                          // Product string indentifier.
+    0,                          // Product serial number.
+    1                           // Number of configurations.
+};
+
+//*****************************************************************************
+//
+// DFU device runtime configuration descriptor.  This is also a dummy structure
+// since the primary device class configuration will be used when DFU is added
+// to the composite device.
+//
+//*****************************************************************************
+unsigned char g_pDFUConfigDescriptor[] =
+{
+    //
+    // Configuration descriptor header.
+    //
+    9,                          // Size of the configuration descriptor.
+    USB_DTYPE_CONFIGURATION,    // Type of this descriptor.
+    USBShort(27),               // The total size of this full structure.
+    1,                          // The number of interfaces in this
+                                // configuration.
+    1,                          // The unique value for this configuration.
+    0,                          // The string identifier that describes this
+                                // configuration.
+    USB_CONF_ATTR_SELF_PWR,     // Bus Powered, Self Powered, remote wake up.
+    250,                        // The maximum power in 2mA increments.
+};
+
+//*****************************************************************************
+//
+// The DFU runtime interface descriptor.
+//
+//*****************************************************************************
+unsigned char g_pDFUInterface[] =
+{
+    //
+    // Interface descriptor for runtime DFU operation.
+    //
+    9,                          // Length of this descriptor.
+    USB_DTYPE_INTERFACE,        // This is an interface descriptor.
+    0,                          // Interface number .
+    0,                          // Alternate setting number.
+    0,                          // Number of endpoints (only endpoint 0 used)
+    USB_CLASS_APP_SPECIFIC,     // Application specific interface class
+    USB_DFU_SUBCLASS,           // Device Firmware Upgrade subclass
+    USB_DFU_RUNTIME_PROTOCOL,   // DFU runtime protocol
+    0,                          // No string descriptor for this interface.
+};
+
+//*****************************************************************************
+//
+// The DFU functional descriptor.
+//
+//*****************************************************************************
+unsigned char g_pDFUFunctionalDesc[] =
+{
+    //
+    // Device Firmware Upgrade functional descriptor.
+    //
+    9,                              // Length of this descriptor.
+    USB_DFU_FUNC_DESCRIPTOR_TYPE,   // DFU Functional descriptor type
+    (DFU_ATTR_CAN_DOWNLOAD |        // DFU attributes.
+     DFU_ATTR_CAN_UPLOAD |
+     DFU_ATTR_WILL_DETACH |
+     DFU_ATTR_MANIFEST_TOLERANT),
+    USBShort(0xFFFF),               // Detach timeout (set to maximum).
+    USBShort(DFU_TRANSFER_SIZE),    // Transfer size 1KB.
+    USBShort(0x0110)                // DFU Version 1.1
+};
+
+//*****************************************************************************
+//
+// The DFU runtime configuration descriptor is defined as two sections.
+// These sections are:
+//
+// 1.  The 9 byte configuration descriptor.
+// 2.  The interface descriptor + DFU functional descriptor.
+//
+//*****************************************************************************
+const tConfigSection g_sDFUConfigSection =
+{
+    sizeof(g_pDFUConfigDescriptor),
+    g_pDFUConfigDescriptor
+};
+
+const tConfigSection g_sDFUInterfaceSection =
+{
+    sizeof(g_pDFUInterface),
+    g_pDFUInterface
+};
+
+const tConfigSection g_sDFUFunctionalDescSection =
+{
+    sizeof(g_pDFUFunctionalDesc),
+    g_pDFUFunctionalDesc
+};
+
+//*****************************************************************************
+//
+// This array lists all the sections that must be concatenated to make a
+// single, complete DFU runtime configuration descriptor.
+//
+//*****************************************************************************
+const tConfigSection *g_psDFUSections[] =
+{
+    &g_sDFUConfigSection,
+    &g_sDFUInterfaceSection,
+    &g_sDFUFunctionalDescSection
+};
+
+#define NUM_DFU_SECTIONS (sizeof(g_psDFUSections) /                         \
+                          sizeof(tConfigSection *))
+
+//*****************************************************************************
+//
+// The header for the single configuration we support.  This is the root of
+// the data structure that defines all the bits and pieces that are pulled
+// together to generate the configuration descriptor.
+//
+//*****************************************************************************
+tConfigHeader g_sDFUConfigHeader =
+{
+    NUM_DFU_SECTIONS,
+    g_psDFUSections
+};
+
+//*****************************************************************************
+//
+// Configuration Descriptor.
+//
+//*****************************************************************************
+const tConfigHeader * const g_pDFUConfigDescriptors[] =
+{
+    &g_sDFUConfigHeader
+};
+
+//*****************************************************************************
+//
+// Forward references for device handler callbacks
+//
+//*****************************************************************************
+static void HandleGetDescriptor(void *pvInstance, tUSBRequest *pUSBRequest);
+static void HandleRequest(void *pvInstance, tUSBRequest *pUSBRequest);
+static void HandleDevice(void *pvInstance, unsigned long ulRequest,
+                         void *pvRequestData);
+
+//*****************************************************************************
+//
+// The device information structure for the USB DFU devices.
+//
+//*****************************************************************************
+tDeviceInfo g_sDFUDeviceInfo =
+{
+    //
+    // Device event handler callbacks.
+    //
+    {
+        HandleGetDescriptor,    // GetDescriptor
+        HandleRequest,          // RequestHandler
+        0,                      // InterfaceChange
+        0,                      // ConfigChange
+        0,                      // DataReceived
+        0,                      // DataSentCallback
+        0,                      // ResetHandler
+        0,                      // SuspendHandler
+        0,                      // ResumeHandler
+        0,                      // DisconnectHandler
+        0,                      // EndpointHandler
+        HandleDevice,           // Device handler.
+    },
+    0,                          // Device descriptor (unused - composite device)
+    g_pDFUConfigDescriptors,
+    0,                          // Completed during USBDDFUCompositeInit().
+    0,                          // Completed during USBDDFUCompositeInit().
+    &g_sUSBDefaultFIFOConfig,
+    0
+};
+
+//*****************************************************************************
+//
+// Device instance specific handler.  This callback received notifications of
+// events related to handling interface, endpoint and string identifiers when
+// a device is part of a composite device.  In this case, the only resource we
+// need which may be renumbered is the DFU runtime interface.
+//
+//*****************************************************************************
+static void
+HandleDevice(void *pvInstance, unsigned long ulRequest, void *pvRequestData)
+{
+    tDFUInstance *psInst;
+    unsigned char *pucData;
+
+    //
+    // Get a pointer to our instance data.
+    //
+    psInst = ((tUSBDDFUDevice *)pvInstance)->psPrivateDFUData;
+
+    //
+    // Get a byte pointer to the data.
+    //
+    pucData = (unsigned char *)pvRequestData;
+
+    //
+    // Which request event have we been passed?
+    //
+    switch(ulRequest)
+    {
+        //
+        // This was an interface change event.
+        //
+        case USB_EVENT_COMP_IFACE_CHANGE:
+        {
+            //
+            // Save the change to the interface number.
+            //
+            psInst->ucInterface = pucData[1];
+            break;
+        }
+
+        //
+        // We are not interested in any other event.
+        //
+        default:
+        {
+            break;
+        }
+    }
+}
+
+//*****************************************************************************
+//
+// This function is called by the USB device stack whenever a request for a
+// non-standard descriptor is received.
+//
+// \param pvInstance is the instance data for this request.
+// \param pUSBRequest points to the request received.
+//
+// This call parses the provided request structure and determines which
+// descriptor is being requested.  Assuming the descriptor can be found, it is
+// scheduled for transmission via endpoint zero.  If the descriptor cannot be
+// found, the endpoint is stalled to indicate an error to the host.
+//
+//*****************************************************************************
+static void
+HandleGetDescriptor(void *pvInstance, tUSBRequest *pUSBRequest)
+{
+    unsigned long ulSize;
+
+    ASSERT(pvInstance != 0);
+
+    //
+    // Which type of class descriptor are we being asked for?  We only support
+    // 1 type - the DFU functional descriptor.
+    //
+    if(((pUSBRequest->wValue >> 8) == USB_DFU_FUNC_DESCRIPTOR_TYPE) &&
+       ((pUSBRequest->wValue & 0xFF) == 0))
+    {
+        //
+        // If there is more data to send than the host requested then just
+        // send the requested amount of data.
+        //
+        if((unsigned short)g_pDFUFunctionalDesc[0] > pUSBRequest->wLength)
+        {
+            ulSize = (unsigned long)pUSBRequest->wLength;
+        }
+        else
+        {
+            ulSize = (unsigned long)g_pDFUFunctionalDesc[0];
+        }
+
+        //
+        // Send the data via endpoint 0.
+        //
+        USBDCDSendDataEP0(0, g_pDFUFunctionalDesc, ulSize);
+    }
+    else
+    {
+        //
+        // This was an unknown or invalid request so stall.
+        //
+        USBDCDStallEP0(0);
+    }
+}
+
+//*****************************************************************************
+//
+// This function is called by the USB device stack whenever a non-standard
+// request is received.
+//
+// \param pvInstance is the instance data for this HID device.
+// \param pUSBRequest points to the request received.
+//
+// This call parses the provided request structure.  Assuming the request is
+// understood, it is handled and any required response generated.  If the
+// request cannot be handled by this device class, endpoint zero is stalled to
+// indicate an error to the host.
+//
+//*****************************************************************************
+static void
+HandleRequest(void *pvInstance, tUSBRequest *pUSBRequest)
+{
+    tDFUInstance *psInst;
+    const tUSBDDFUDevice *psDevice;
+
+    ASSERT(pvInstance != 0);
+
+    //
+    // Which device are we dealing with?
+    //
+    psDevice = pvInstance;
+
+    //
+    // Get a pointer to our instance data.
+    //
+    psInst = psDevice->psPrivateDFUData;
+
+    //
+    // Make sure the request was for this interface.
+    //
+    if(pUSBRequest->wIndex != psInst->ucInterface)
+    {
+        return;
+    }
+
+    //
+    // Determine the type of request.
+    //
+    switch(pUSBRequest->bRequest)
+    {
+        //
+        // We have been asked to detach.  In this case, we call back to the
+        // application telling it to tidy up and re-enter the boot loader.  We
+        // rely upon it doing this on our behalf since this must be done from a
+        // non-interrupt context and this call is most likely in interrupt
+        // context.
+        //
+        case USBD_DFU_REQUEST_DETACH:
+        {
+            //
+            // Tell the application it's time to reenter the boot loader.
+            //
+            psDevice->pfnCallback(psDevice->pvCBData, USBD_DFU_EVENT_DETACH,
+                                  0, (void *)0);
+            break;
+        }
+
+        //
+        // This request was not recognized so stall.
+        //
+        default:
+        {
+            USBDCDStallEP0(0);
+            break;
+        }
+    }
+}
+
+//*****************************************************************************
+//
+//! Initializes DFU device operation for a given USB controller.
+//!
+//! \param ulIndex is the index of the USB controller which is to be
+//! initialized for DFU runtime device operation.
+//! \param psDevice points to a structure containing parameters customizing
+//! the operation of the DFU device.
+//!
+//! \return Returns NULL on failure or the \e psDevice pointer on success.
+//
+//*****************************************************************************
+void *
+USBDDFUCompositeInit(unsigned long ulIndex, const tUSBDDFUDevice *psDevice)
+{
+    tDFUInstance *psInst;
+
+    //
+    // Check parameter validity.
+    //
+    ASSERT(ulIndex == 0);
+    ASSERT(psDevice);
+    ASSERT(psDevice->psPrivateDFUData);
+
+    //
+    // Initialize the workspace in the passed instance structure.
+    //
+    psInst = psDevice->psPrivateDFUData;
+    psInst->psDevInfo = &g_sDFUDeviceInfo;
+    psInst->ulUSBBase = USB0_BASE;
+    psInst->bConnected = false;
+    psInst->ucInterface = 0;
+
+    //
+    // Tag the device information with our device data structure pointer.
+    //
+    psInst->psDevInfo->pvInstance = (void *)psDevice;
+
+    //
+    // Return the pointer to the instance indicating that everything went well.
+    //
+    return((void *)psDevice);
+}
+
+//*****************************************************************************
+//
+//! Shuts down the DFU device.
+//!
+//! \param pvInstance is the pointer to the device instance structure as
+//! returned by USBDDFUCompositeInit().
+//!
+//! This function terminates DFU operation for the instance supplied and
+//! removes the device from the USB bus.
+//!
+//! Following this call, the \e pvInstance instance should not me used in any
+//! other calls.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDDFUCompositeTerm(void *pvInstance)
+{
+    tDFUInstance *psInst;
+
+    ASSERT(pvInstance);
+
+    //
+    // Get a pointer to our instance data.
+    //
+    psInst = ((tUSBDDFUDevice *)pvInstance)->psPrivateDFUData;
+
+    //
+    // Terminate the requested instance.
+    //
+    USBDCDTerm(0);
+
+    psInst->ulUSBBase = 0;
+    psInst->psDevInfo = (tDeviceInfo *)0;
+}
+
+//*****************************************************************************
+//
+//! Removes the current USB device from the bus and transfers control to the
+//! DFU boot loader.
+//!
+//! This function should be called from the application's main loop (i.e. not
+//! in interrupt context) following a callback to the USB DFU callback function
+//! notifying the application of a DETACH request from the host.  The function
+//! will prepare the system to switch to DFU mode and transfer control to the
+//! boot loader in preparation for a firmware upgrade from the host.
+//!
+//! The application must ensure that it has completed all necessary shutdown
+//! activities (saved any required data, etc.) before making this call since
+//! the function will not return.
+//!
+//! \return This function does not return.
+//
+//*****************************************************************************
+void
+USBDDFUUpdateBegin(void)
+{
+    //
+    // Terminate the USB device and take us off the bus.
+    //
+    USBDCDTerm(0);
+
+    //
+    // Disable all interrupts.
+    //
+    MAP_IntMasterDisable();
+
+    //
+    // We must make sure we turn off SysTick and its interrupt
+    // before entering the boot loader!
+    //
+    MAP_SysTickIntDisable();
+    MAP_SysTickDisable();
+
+    //
+    // Disable all processor interrupts.  Instead of disabling them
+    // one at a time, a direct write to NVIC is done to disable all
+    // peripheral interrupts.
+    //
+    HWREG(NVIC_DIS0) = 0xffffffff;
+    HWREG(NVIC_DIS1) = 0xffffffff;
+
+    //
+    // Reset the USB peripheral
+    //
+    MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_USB0);
+    MAP_SysCtlPeripheralReset(SYSCTL_PERIPH_USB0);
+    MAP_SysCtlPeripheralDisable(SYSCTL_PERIPH_USB0);
+
+    //
+    // Wait for about a second.
+    //
+    MAP_SysCtlDelay(MAP_SysCtlClockGet() / 3);
+
+    //
+    // Re-enable interrupts at the NVIC level.
+    //
+    MAP_IntMasterEnable();
+
+    //
+    // Return control to the boot loader.  This is a call to the SVC
+    // handler in the boot loader.
+    //
+    (*((void (*)(void))(*(unsigned long *)0x2c)))();
+
+    //
+    // Should never get here, but just in case.
+    //
+    while(1)
+    {
+    }
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/src/platform/lm3s/usblib/device/usbddfu-rt.h b/src/platform/lm3s/usblib/device/usbddfu-rt.h
new file mode 100755
index 00000000..80862c98
--- /dev/null
+++ b/src/platform/lm3s/usblib/device/usbddfu-rt.h
@@ -0,0 +1,163 @@
+//*****************************************************************************
+//
+// usbddfu-rt.h - Definitions used by runtime DFU class devices.
+//
+// Copyright (c) 2010-2011 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 7611 of the Stellaris USB Library.
+//
+//*****************************************************************************
+
+#ifndef __USBDDFURT_H__
+#define __USBDDFURT_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+//! \addtogroup dfu_device_class_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! The size of the memory that should be allocated to create a configuration
+//! descriptor for a single instance of the DFU runtime device.  This does not
+//! include the configuration descriptor which is automatically ignored by the
+//! composite device class.
+//!
+//! This label is used to compute the value which will be passed to the
+//! USBDCompositeInit function in the ulSize parameter.
+//
+// For reference this is sizeof(g_pDFUInterface) + sizeof(g_pDFUFunctionalDesc)
+//
+//*****************************************************************************
+#define COMPOSITE_DDFU_SIZE     (9 + 9)
+
+//*****************************************************************************
+//
+//! This value is passed to the client via the callback function provided in
+//! the tUSBDDFUDevice structure and indicates that the host has sent a DETACH
+//! request to the DFU interface. This request indicates that the device detach
+//! from the USB bus and reattach in DFU mode in preparation for a firmware
+//! upgrade.  Currently, this is the only event that the DFU runtime class
+//! reports to the client.
+//!
+//! When this event is received, the client should call USBDDFUUpdateBegin()
+//! from a non-interrupt context at its earliest opportunity.
+//
+//*****************************************************************************
+#define USBD_DFU_EVENT_DETACH (USBD_DFU_EVENT_BASE + 0)
+
+//*****************************************************************************
+//
+// PRIVATE
+//
+// This structure defines the private instance data and state variables for
+// DFU devices.  The memory for this structure is pointed to by the
+// psPrivateDFUData field in the tUSBDDFUDevice structure passed in the
+// USBDDFUCompositeInit() function.
+//
+//*****************************************************************************
+typedef struct
+{
+    unsigned long ulUSBBase;
+    tDeviceInfo *psDevInfo;
+    unsigned char ucInterface;
+    tBoolean bConnected;
+}
+tDFUInstance;
+
+//*****************************************************************************
+//
+//! The structure used by the application to define operating parameters for
+//! the DFU device.  Note that, unlike all other devices, this structure does
+//! not contain any fields which configure the device descriptor sent back to
+//! the host.  The DFU runtime device class must be used as part of a composite
+//! device since all it provides is the capability to signal the device to
+//! switch into DFU mode in preparation for a firmware upgrade.  Creating a
+//! device with nothing but DFU runtime mode capability is rather pointless
+//! so this is not supported.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! A pointer to the callback function which will be called to notify
+    //! the application of DETACH requests.
+    //
+    tUSBCallback pfnCallback;
+
+    //
+    //! A client-supplied pointer which will be sent as the first
+    //! parameter in all calls made to the pfnCallback function.
+    //
+    void *pvCBData;
+
+    //
+    //! A pointer to private instance data for this device instance.  This
+    //! memory must remain accessible for as long as the DFU device is in use
+    //! and must not be modified by any code outside the DFU class driver.
+    //
+    tDFUInstance *psPrivateDFUData;
+}
+tUSBDDFUDevice;
+
+//*****************************************************************************
+//
+// Device information structure required to construct the composite device.
+//
+//*****************************************************************************
+extern tDeviceInfo g_sDFUDeviceInfo;
+
+//*****************************************************************************
+//
+// API Function Prototypes
+//
+//*****************************************************************************
+extern void *USBDDFUCompositeInit(unsigned long ulIndex,
+                                  const tUSBDDFUDevice *psDevice);
+extern void USBDDFUCompositeTerm(void *pvInstance);
+extern void USBDDFUUpdateBegin(void);
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __USBDDFURT_H__
diff --git a/src/platform/lm3s/usblib/device/usbdenum.c b/src/platform/lm3s/usblib/device/usbdenum.c
new file mode 100755
index 00000000..27d0fb7f
--- /dev/null
+++ b/src/platform/lm3s/usblib/device/usbdenum.c
@@ -0,0 +1,3021 @@
+//*****************************************************************************
+//
+// usbenum.c - Enumeration code to handle all endpoint zero traffic.
+//
+// Copyright (c) 2007-2011 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 7611 of the Stellaris USB Library.
+//
+//*****************************************************************************
+
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_types.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+#include "driverlib/rom.h"
+#include "driverlib/rom_map.h"
+#include "driverlib/sysctl.h"
+#include "driverlib/usb.h"
+#include "usblib/usblib.h"
+#include "usblib/device/usbdevice.h"
+#include "usblib/device/usbdevicepriv.h"
+#include "usblib/usblibpriv.h"
+
+//*****************************************************************************
+//
+// External prototypes.
+//
+//*****************************************************************************
+extern tUSBMode g_eUSBMode;
+
+//*****************************************************************************
+//
+// Local functions prototypes.
+//
+//*****************************************************************************
+static void USBDGetStatus(void *pvInstance, tUSBRequest *pUSBRequest);
+static void USBDClearFeature(void *pvInstance, tUSBRequest *pUSBRequest);
+static void USBDSetFeature(void *pvInstance, tUSBRequest *pUSBRequest);
+static void USBDSetAddress(void *pvInstance, tUSBRequest *pUSBRequest);
+static void USBDGetDescriptor(void *pvInstance, tUSBRequest *pUSBRequest);
+static void USBDSetDescriptor(void *pvInstance, tUSBRequest *pUSBRequest);
+static void USBDGetConfiguration(void *pvInstance,
+                                 tUSBRequest *pUSBRequest);
+static void USBDSetConfiguration(void *pvInstance,
+                                 tUSBRequest *pUSBRequest);
+static void USBDGetInterface(void *pvInstance, tUSBRequest *pUSBRequest);
+static void USBDSetInterface(void *pvInstance, tUSBRequest *pUSBRequest);
+static void USBDSyncFrame(void *pvInstance, tUSBRequest *pUSBRequest);
+static void USBDEP0StateTx(unsigned long ulIndex);
+static void USBDEP0StateTxConfig(unsigned long ulIndex);
+static long USBDStringIndexFromRequest(unsigned short usLang,
+                                       unsigned short usIndex);
+
+//*****************************************************************************
+//
+//! \addtogroup device_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! The default USB endpoint FIFO configuration structure.  This structure
+//! contains definitions to set all USB FIFOs into single buffered mode with
+//! no DMA use.  Each endpoint's FIFO is sized to hold the largest maximum
+//! packet size for any interface alternate setting in the current
+//! configuration descriptor.  A pointer to this structure may be passed in the
+//! psFIFOConfig field of the tDeviceInfo structure passed to USBCDCInit if the
+//! application does not require any special handling of the USB controller
+//! FIFO.
+//
+//*****************************************************************************
+const tFIFOConfig g_sUSBDefaultFIFOConfig =
+{
+    {
+        { 1, false, 0 },
+        { 1, false, 0 },
+        { 1, false, 0 },
+        { 1, false, 0 },
+        { 1, false, 0 },
+        { 1, false, 0 },
+        { 1, false, 0 },
+        { 1, false, 0 },
+        { 1, false, 0 },
+        { 1, false, 0 },
+        { 1, false, 0 },
+        { 1, false, 0 },
+        { 1, false, 0 },
+        { 1, false, 0 },
+        { 1, false, 0 }
+    },
+    {
+        { 1, false, 0 },
+        { 1, false, 0 },
+        { 1, false, 0 },
+        { 1, false, 0 },
+        { 1, false, 0 },
+        { 1, false, 0 },
+        { 1, false, 0 },
+        { 1, false, 0 },
+        { 1, false, 0 },
+        { 1, false, 0 },
+        { 1, false, 0 },
+        { 1, false, 0 },
+        { 1, false, 0 },
+        { 1, false, 0 },
+        { 1, false, 0 }
+    },
+};
+
+//*****************************************************************************
+//
+// Indices into the ucHalt array to select the IN or OUT endpoint group.
+//
+//*****************************************************************************
+#define HALT_EP_IN              0
+#define HALT_EP_OUT             1
+
+//*****************************************************************************
+//
+// The states for endpoint zero during enumeration.
+//
+//*****************************************************************************
+typedef enum
+{
+    //
+    // The USB device is waiting on a request from the host controller on
+    // endpoint zero.
+    //
+    USB_STATE_IDLE,
+
+    //
+    // The USB device is sending data back to the host due to an IN request.
+    //
+    USB_STATE_TX,
+
+    //
+    // The USB device is sending the configuration descriptor back to the host
+    // due to an IN request.
+    //
+    USB_STATE_TX_CONFIG,
+
+    //
+    // The USB device is receiving data from the host due to an OUT
+    // request from the host.
+    //
+    USB_STATE_RX,
+
+    //
+    // The USB device has completed the IN or OUT request and is now waiting
+    // for the host to acknowledge the end of the IN/OUT transaction.  This
+    // is the status phase for a USB control transaction.
+    //
+    USB_STATE_STATUS,
+
+    //
+    // This endpoint has signaled a stall condition and is waiting for the
+    // stall to be acknowledged by the host controller.
+    //
+    USB_STATE_STALL
+}
+tEP0State;
+
+//*****************************************************************************
+//
+// Define the max packet size for endpoint zero.
+//
+//*****************************************************************************
+#define EP0_MAX_PACKET_SIZE     64
+
+//*****************************************************************************
+//
+// This is a flag used with g_sUSBDeviceState.ulDevAddress to indicate that a
+// device address change is pending.
+//
+//*****************************************************************************
+#define DEV_ADDR_PENDING        0x80000000
+
+//*****************************************************************************
+//
+// This label defines the default configuration number to use after a bus
+// reset.  This may be overridden by calling USBDCDSetDefaultConfiguration()
+// during processing of the device reset handler if required.
+//
+//*****************************************************************************
+#define DEFAULT_CONFIG_ID       1
+
+//*****************************************************************************
+//
+// This label defines the number of milliseconds that the remote wake up signal
+// must remain asserted before removing it. Section 7.1.7.7 of the USB 2.0 spec
+// states that "the remote wake up device must hold the resume signaling for at
+// least 1ms but for no more than 15ms" so 10mS seems a reasonable choice.
+//
+//*****************************************************************************
+#define REMOTE_WAKEUP_PULSE_MS 10
+
+//*****************************************************************************
+//
+// This label defines the number of milliseconds between the point where we
+// assert the remote wake up signal and calling the client back to tell it that
+// bus operation has been resumed.  This value is based on the timings provided
+// in section 7.1.7.7 of the USB 2.0 specification which indicates that the host
+// (which takes over resume signaling when the device's initial signal is
+// detected) must hold the resume signaling for at least 20mS.
+//
+//*****************************************************************************
+#define REMOTE_WAKEUP_READY_MS 20
+
+//*****************************************************************************
+//
+// The buffer for reading data coming into EP0
+//
+//*****************************************************************************
+static unsigned char g_pucDataBufferIn[EP0_MAX_PACKET_SIZE];
+
+//*****************************************************************************
+//
+// The USB controller device information.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    // The device information for the USB device.
+    //
+    tDeviceInfo *psInfo;
+
+    //
+    // The instance data for the USB device.
+    //
+    void *pvInstance;
+
+    //
+    // The current state of endpoint zero.
+    //
+    volatile tEP0State eEP0State;
+
+    //
+    // The devices current address, this also has a change pending bit in the
+    // MSB of this value specified by DEV_ADDR_PENDING.
+    //
+    volatile unsigned long ulDevAddress;
+
+    //
+    // This holds the current active configuration for this device.
+    //
+    unsigned long ulConfiguration;
+
+    //
+    // This holds the configuration id that will take effect after a reset.
+    //
+    unsigned long ulDefaultConfiguration;
+
+    //
+    // This holds the current alternate interface for this device.
+    //
+    unsigned char pucAltSetting[USB_MAX_INTERFACES_PER_DEVICE];
+
+    //
+    // This is the pointer to the current data being sent out or received
+    // on endpoint zero.
+    //
+    unsigned char *pEP0Data;
+
+    //
+    // This is the number of bytes that remain to be sent from or received
+    // into the g_sUSBDeviceState.pEP0Data data buffer.
+    //
+    volatile unsigned long ulEP0DataRemain;
+
+    //
+    // The amount of data being sent/received due to a custom request.
+    //
+    unsigned long ulOUTDataSize;
+
+    //
+    // Holds the current device status.
+    //
+    unsigned char ucStatus;
+
+    //
+    // Holds the endpoint status for the HALT condition.  This array is sized
+    // to hold halt status for all IN and OUT endpoints.
+    //
+    unsigned char ucHalt[2][NUM_USB_EP - 1];
+
+    //
+    // Holds the configuration descriptor section number currently being sent
+    // to the host.
+    //
+    unsigned char ucConfigSection;
+
+    //
+    // Holds the offset within the configuration descriptor section currently
+    // being sent to the host.
+    //
+    unsigned char ucSectionOffset;
+
+    //
+    // Holds the index of the configuration that we are currently sending back
+    // to the host.
+    //
+    unsigned char ucConfigIndex;
+
+    //
+    // This flag is set to true if the client has called USBDPowerStatusSet
+    // and tells the USB library not to try to determine the current power
+    // status from the configuration descriptor.
+    //
+    tBoolean bPwrSrcSet;
+
+    //
+    // This flag indicates whether or not remote wake up signaling is in
+    // progress.
+    //
+    tBoolean bRemoteWakeup;
+
+    //
+    // During remote wake up signaling, this counter is used to track the
+    // number of milliseconds since the signaling was initiated.
+    //
+    unsigned char ucRemoteWakeupCount;
+}
+tDeviceInstance;
+
+tDeviceInstance g_psUSBDevice[1];
+
+//*****************************************************************************
+//
+// Function table to handle standard requests.
+//
+//*****************************************************************************
+static const tStdRequest g_psUSBDStdRequests[] =
+{
+    USBDGetStatus,
+    USBDClearFeature,
+    0,
+    USBDSetFeature,
+    0,
+    USBDSetAddress,
+    USBDGetDescriptor,
+    USBDSetDescriptor,
+    USBDGetConfiguration,
+    USBDSetConfiguration,
+    USBDGetInterface,
+    USBDSetInterface,
+    USBDSyncFrame
+};
+
+//*****************************************************************************
+//
+// Functions accessible by USBLIB clients.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! Initialize the USB library device control driver for a given hardware
+//! controller.
+//!
+//! \param ulIndex is the index of the USB controller which is to be
+//! initialized.
+//! \param psDevice is a pointer to a structure containing information that
+//! the USB library requires to support operation of this application's
+//! device.  The structure contains event handler callbacks and pointers to the
+//! various standard descriptors that the device wishes to publish to the
+//! host.
+//!
+//! This function must be called by any application which wishes to operate
+//! as a USB device.  It initializes the USB device control driver for the
+//! given controller and saves the device information for future use.  Prior to
+//! returning from this function, the device is connected to the USB bus.
+//! Following return, the caller can expect to receive a callback to the
+//! supplied pfnResetHandler function when a host connects to the
+//! device.
+//!
+//! The device information structure passed in \e psDevice must remain
+//! unchanged between this call and any matching call to USBDCDTerm() since
+//! it is not copied by the USB library.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDCDInit(unsigned long ulIndex, tDeviceInfo *psDevice)
+{
+    const tConfigHeader *psHdr;
+    const tConfigDescriptor *psDesc;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulIndex == 0);
+    ASSERT(psDevice != 0);
+
+    //
+    // Should not call this if the stack is in host mode.
+    //
+    ASSERT(g_eUSBMode != USB_MODE_HOST);
+
+    //
+    // Initialize a couple of fields in the device state structure.
+    //
+    g_psUSBDevice[0].ulConfiguration = DEFAULT_CONFIG_ID;
+    g_psUSBDevice[0].ulDefaultConfiguration = DEFAULT_CONFIG_ID;
+
+    //
+    // Remember the device information pointer.
+    //
+    g_psUSBDevice[0].psInfo = psDevice;
+    g_psUSBDevice[0].pvInstance = psDevice->pvInstance;
+    g_psUSBDevice[0].eEP0State = USB_STATE_IDLE;
+
+    //
+    // If no mode is set then make the mode become device mode.
+    //
+    if(g_eUSBMode == USB_MODE_NONE)
+    {
+        g_eUSBMode = USB_MODE_DEVICE;
+    }
+
+    //
+    // Only do hardware update if the stack is in Device mode, do not touch the
+    // hardware for OTG mode operation.
+    //
+    if(g_eUSBMode == USB_MODE_DEVICE)
+    {
+        //
+        // Reset the USB controller.
+        //
+        MAP_SysCtlPeripheralReset(SYSCTL_PERIPH_USB0);
+
+        //
+        // Enable Clocking to the USB controller.
+        //
+        MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_USB0);
+
+        //
+        // Turn on USB Phy clock.
+        //
+        MAP_SysCtlUSBPLLEnable();
+    }
+
+    //
+    // Initialize the USB tick module.
+    //
+    InternalUSBTickInit();
+
+    //
+    // Only do hardware update if the stack is in Device mode, do not touch the
+    // hardware for OTG mode operation.
+    //
+    if(g_eUSBMode == USB_MODE_DEVICE)
+    {
+        //
+        // Ask for the interrupt status.  As a side effect, this clears all
+        // pending USB interrupts.
+        //
+        MAP_USBIntStatusControl(USB0_BASE);
+        MAP_USBIntStatusEndpoint(USB0_BASE);
+
+        //
+        // Enable USB Interrupts.
+        //
+        MAP_USBIntEnableControl(USB0_BASE, USB_INTCTRL_RESET |
+                                           USB_INTCTRL_DISCONNECT |
+                                           USB_INTCTRL_RESUME |
+                                           USB_INTCTRL_SUSPEND |
+                                           USB_INTCTRL_SOF);
+        MAP_USBIntEnableEndpoint(USB0_BASE, USB_INTEP_ALL);
+    }
+
+    //
+    // Get a pointer to the default configuration descriptor.
+    //
+    psHdr = psDevice->ppConfigDescriptors[
+                g_psUSBDevice[0].ulDefaultConfiguration - 1];
+    psDesc = (const tConfigDescriptor *)(psHdr->psSections[0]->pucData);
+
+    //
+    // Default to the state where remote wake up is disabled.
+    //
+    g_psUSBDevice[0].ucStatus = 0;
+    g_psUSBDevice[0].bRemoteWakeup = false;
+
+    //
+    // Determine the self- or bus-powered state based on the flags the
+    // user provided.
+    //
+    g_psUSBDevice[0].bPwrSrcSet = false;
+
+    if((psDesc->bmAttributes & USB_CONF_ATTR_PWR_M) == USB_CONF_ATTR_SELF_PWR)
+    {
+        g_psUSBDevice[0].ucStatus |= USB_STATUS_SELF_PWR;
+    }
+    else
+    {
+        g_psUSBDevice[0].ucStatus &= ~USB_STATUS_SELF_PWR;
+    }
+
+    //
+    // Only do hardware update if the stack is in Device mode, do not touch the
+    // hardware for OTG mode operation.
+    //
+    if(g_eUSBMode == USB_MODE_DEVICE)
+    {
+        //
+        // Make sure we disconnect from the host for a while.  This ensures
+        // that the host will enumerate us even if we were previously
+        // connected to the bus.
+        //
+        MAP_USBDevDisconnect(USB0_BASE);
+
+        //
+        // Wait about 100mS.
+        //
+        MAP_SysCtlDelay(MAP_SysCtlClockGet() / 30);
+
+        //
+        // Attach the device using the soft connect.
+        //
+        MAP_USBDevConnect(USB0_BASE);
+
+        //
+        // Enable the USB interrupt.
+        //
+        MAP_IntEnable(INT_USB0);
+    }
+}
+
+//*****************************************************************************
+//
+//! Free the USB library device control driver for a given hardware controller.
+//!
+//! \param ulIndex is the index of the USB controller which is to be
+//! freed.
+//!
+//! This function should be called by an application if it no longer requires
+//! the use of a given USB controller to support its operation as a USB device.
+//! It frees the controller for use by another client.
+//!
+//! It is the caller's responsibility to remove its device from the USB bus
+//! prior to calling this function.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDCDTerm(unsigned long ulIndex)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulIndex == 0);
+
+    //
+    // Disable the USB interrupts.
+    //
+    MAP_IntDisable(INT_USB0);
+
+    g_psUSBDevice[0].psInfo = (tDeviceInfo *)0;
+    g_psUSBDevice[0].pvInstance = 0;
+
+    MAP_USBIntDisableControl(USB0_BASE, USB_INTCTRL_ALL);
+    MAP_USBIntDisableEndpoint(USB0_BASE, USB_INTEP_ALL);
+
+    //
+    // Detach the device using the soft connect.
+    //
+    MAP_USBDevDisconnect(USB0_BASE);
+
+    //
+    // Clear any pending interrupts.
+    //
+    MAP_USBIntStatusControl(USB0_BASE);
+    MAP_USBIntStatusEndpoint(USB0_BASE);
+
+    //
+    // Turn off USB Phy clock.
+    //
+    MAP_SysCtlUSBPLLDisable();
+
+    //
+    // Disable the USB peripheral
+    //
+    MAP_SysCtlPeripheralDisable(SYSCTL_PERIPH_USB0);
+}
+
+//*****************************************************************************
+//
+//! This function starts the request for data from the host on endpoint zero.
+//!
+//! \param ulIndex is the index of the USB controller from which the data
+//! is being requested.
+//! \param pucData is a pointer to the buffer to fill with data from the USB
+//! host.
+//! \param ulSize is the size of the buffer or data to return from the USB
+//! host.
+//!
+//! This function handles retrieving data from the host when a custom command
+//! has been issued on endpoint zero.  If the application needs notification
+//! when the data has been received,
+//! tDeviceInfo.sCallbacks.pfnDataReceived should contain valid
+//! function pointer.  In nearly all cases this is necessary because the caller
+//! of this function would likely need to know that the data requested was
+//! received.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDCDRequestDataEP0(unsigned long ulIndex, unsigned char *pucData,
+                     unsigned long ulSize)
+{
+    ASSERT(ulIndex == 0);
+
+    //
+    // Enter the RX state on end point 0.
+    //
+    g_psUSBDevice[0].eEP0State = USB_STATE_RX;
+
+    //
+    // Save the pointer to the data.
+    //
+    g_psUSBDevice[0].pEP0Data = pucData;
+
+    //
+    // Location to save the current number of bytes received.
+    //
+    g_psUSBDevice[0].ulOUTDataSize = ulSize;
+
+    //
+    // Bytes remaining to be received.
+    //
+    g_psUSBDevice[0].ulEP0DataRemain = ulSize;
+}
+
+//*****************************************************************************
+//
+//! This function requests transfer of data to the host on endpoint zero.
+//!
+//! \param ulIndex is the index of the USB controller which is to be used to
+//! send the data.
+//! \param pucData is a pointer to the buffer to send via endpoint zero.
+//! \param ulSize is the amount of data to send in bytes.
+//!
+//! This function handles sending data to the host when a custom command is
+//! issued or non-standard descriptor has been requested on endpoint zero.  If
+//! the application needs notification when this is complete,
+//! tDeviceInfo.sCallbacks.pfnDataSent should contain a valid function
+//! pointer.  This callback could be used to free up the buffer passed into
+//! this function in the \e pucData parameter.  The contents of the \e pucData
+//! buffer must remain unchanged until the pfnDataSent callback is
+//! received.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDCDSendDataEP0(unsigned long ulIndex, unsigned char *pucData,
+                  unsigned long ulSize)
+{
+    ASSERT(ulIndex == 0);
+
+    //
+    // Return the externally provided device descriptor.
+    //
+    g_psUSBDevice[0].pEP0Data = pucData;
+
+    //
+    // The size of the device descriptor is in the first byte.
+    //
+    g_psUSBDevice[0].ulEP0DataRemain = ulSize;
+
+    //
+    // Save the total size of the data sent.
+    //
+    g_psUSBDevice[0].ulOUTDataSize = ulSize;
+
+    //
+    // Now in the transmit data state.
+    //
+    USBDEP0StateTx(0);
+}
+
+//*****************************************************************************
+//
+//! This function sets the default configuration for the device.
+//!
+//! \param ulIndex is the index of the USB controller whose default
+//! configuration is to be set.
+//! \param ulDefaultConfig is the configuration identifier (byte 6 of the
+//! standard configuration descriptor) which is to be presented to the host
+//! as the default configuration in cases where the configuration descriptor is
+//! queried prior to any specific configuration being set.
+//!
+//! This function allows a device to override the default configuration
+//! descriptor that will be returned to a host whenever it is queried prior
+//! to a specific configuration having been set.  The parameter passed must
+//! equal one of the configuration identifiers found in the
+//! ppConfigDescriptors array for the device.
+//!
+//! If this function is not called, the USB library will return the first
+//! configuration in the ppConfigDescriptors array as the default
+//! configuration.
+//!
+//! \note The USB device stack assumes that the configuration IDs (byte 6 of
+//! the configuration descriptor, bConfigurationValue) stored within
+//! the configuration descriptor array, ppConfigDescriptors,
+//! are equal to the array index + 1.  In other words, the first entry in the
+//! array must contain a descriptor with bConfigurationValue 1, the
+//! second must have bConfigurationValue 2 and so on.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDCDSetDefaultConfiguration(unsigned long ulIndex,
+                              unsigned long ulDefaultConfig)
+{
+    ASSERT(ulIndex == 0);
+
+    g_psUSBDevice[0].ulDefaultConfiguration = ulDefaultConfig;
+}
+
+//*****************************************************************************
+//
+//! This function generates a stall condition on endpoint zero.
+//!
+//! \param ulIndex is the index of the USB controller whose endpoint zero is to
+//! be stalled.
+//!
+//! This function is typically called to signal an error condition to the host
+//! when an unsupported request is received by the device.  It should be
+//! called from within the callback itself (in interrupt context) and not
+//! deferred until later since it affects the operation of the endpoint zero
+//! state machine in the USB library.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDCDStallEP0(unsigned long ulIndex)
+{
+    ASSERT(ulIndex == 0);
+
+    //
+    // Stall the endpoint in question.
+    //
+    MAP_USBDevEndpointStall(USB0_BASE, USB_EP_0, USB_EP_DEV_OUT);
+
+    //
+    // Enter the stalled state.
+    //
+    g_psUSBDevice[0].eEP0State = USB_STATE_STALL;
+}
+
+//*****************************************************************************
+//
+//! Reports the device power status (bus- or self-powered) to the library.
+//!
+//! \param ulIndex is the index of the USB controller whose device power
+//! status is being reported.
+//! \param ucPower indicates the current power status, either \b
+//! USB_STATUS_SELF_PWR or \b USB_STATUS_BUS_PWR.
+//!
+//! Applications which support switching between bus- or self-powered
+//! operation should call this function whenever the power source changes
+//! to indicate the current power status to the USB library.  This information
+//! is required by the library to allow correct responses to be provided when
+//! the host requests status from the device.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDCDPowerStatusSet(unsigned long ulIndex, unsigned char ucPower)
+{
+    //
+    // Check for valid parameters.
+    //
+    ASSERT((ucPower == USB_STATUS_BUS_PWR) ||
+           (ucPower == USB_STATUS_SELF_PWR));
+    ASSERT(ulIndex == 0);
+
+    //
+    // Update the device status with the new power status flag.
+    //
+    g_psUSBDevice[0].bPwrSrcSet = true;
+    g_psUSBDevice[0].ucStatus &= ~USB_STATUS_PWR_M;
+    g_psUSBDevice[0].ucStatus |= ucPower;
+}
+
+//*****************************************************************************
+//
+//! Requests a remote wake up to resume communication when in suspended state.
+//!
+//! \param ulIndex is the index of the USB controller that will request
+//! a bus wake up.
+//!
+//! When the bus is suspended, an application which supports remote wake up
+//! (advertised to the host via the configuration descriptor) may call this
+//! function to initiate remote wake up signaling to the host.  If the remote
+//! wake up feature has not been disabled by the host, this will cause the bus
+//! to resume operation within 20mS.  If the host has disabled remote wake up,
+//! \b false will be returned to indicate that the wake up request was not
+//! successful.
+//!
+//! \return Returns \b true if the remote wake up is not disabled and the
+//! signaling was started or \b false if remote wake up is disabled or if
+//! signaling is currently ongoing following a previous call to this function.
+//
+//*****************************************************************************
+tBoolean
+USBDCDRemoteWakeupRequest(unsigned long ulIndex)
+{
+    //
+    // Check for parameter validity.
+    //
+    ASSERT(ulIndex == 0);
+
+    //
+    // Is remote wake up signaling currently enabled?
+    //
+    if(g_psUSBDevice[0].ucStatus & USB_STATUS_REMOTE_WAKE)
+    {
+        //
+        // The host has not disabled remote wake up. Are we still in the
+        // middle of a previous wake up sequence?
+        //
+        if(!g_psUSBDevice[0].bRemoteWakeup)
+        {
+            //
+            // No - we are not in the middle of a wake up sequence so start
+            // one here.
+            //
+            g_psUSBDevice[0].ucRemoteWakeupCount = 0;
+            g_psUSBDevice[0].bRemoteWakeup = true;
+            MAP_USBHostResume(USB0_BASE, true);
+            return(true);
+        }
+    }
+
+    //
+    // If we drop through to here, signaling was not initiated so return
+    // false.
+    return(false);
+}
+
+//*****************************************************************************
+//
+// Internal Functions, not to be called by applications
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// This internal function is called on the SOF interrupt to process any
+// outstanding remote wake up requests.
+//
+// \return None.
+//
+//*****************************************************************************
+void
+USBDeviceResumeTickHandler(unsigned long ulIndex)
+{
+    if(g_psUSBDevice[0].bRemoteWakeup)
+    {
+        //
+        // Increment the millisecond counter we use to time the resume
+        // signaling.
+        //
+        g_psUSBDevice[0].ucRemoteWakeupCount++;
+
+        //
+        // Have we reached the 10mS mark? If so, we need to turn the signaling
+        // off again.
+        //
+        if(g_psUSBDevice[0].ucRemoteWakeupCount == REMOTE_WAKEUP_PULSE_MS)
+        {
+            MAP_USBHostResume(USB0_BASE, false);
+        }
+
+        //
+        // Have we reached the point at which we can tell the client that the
+        // bus has resumed? The controller doesn't give us an interrupt if we
+        // initiated the wake up signaling so we just wait until 20mS have
+        // passed then tell the client all is well.
+        //
+        if(g_psUSBDevice[0].ucRemoteWakeupCount == REMOTE_WAKEUP_READY_MS)
+        {
+            //
+            // We are now finished with the remote wake up signaling.
+            //
+            g_psUSBDevice[0].bRemoteWakeup = false;
+
+            //
+            // If the client has registered a resume callback, call it.  In the
+            // case of a remote wake up request, we do not get a resume
+            // interrupt from the controller so we need to fake it here.
+            //
+            if(g_psUSBDevice[0].psInfo->sCallbacks.pfnResumeHandler)
+            {
+                g_psUSBDevice[0].psInfo->sCallbacks.pfnResumeHandler(
+                    g_psUSBDevice[0].pvInstance);
+            }
+        }
+    }
+}
+
+//*****************************************************************************
+//
+// This internal function reads a request data packet and dispatches it to
+// either a standard request handler or the registered device request
+// callback depending upon the request type.
+//
+// \return None.
+//
+//*****************************************************************************
+static void
+USBDReadAndDispatchRequest(unsigned long ulIndex)
+{
+    unsigned long ulSize;
+    tUSBRequest *pRequest;
+
+    //
+    // Cast the buffer to a request structure.
+    //
+    pRequest = (tUSBRequest *)g_pucDataBufferIn;
+
+    //
+    // Set the buffer size.
+    //
+    ulSize = EP0_MAX_PACKET_SIZE;
+
+    //
+    // Get the data from the USB controller end point 0.
+    //
+    MAP_USBEndpointDataGet(USB0_BASE,
+                           USB_EP_0,
+                           g_pucDataBufferIn,
+                           &ulSize);
+
+    //
+    // If there was a null setup packet then just return.
+    //
+    if(!ulSize)
+    {
+        return;
+    }
+
+    //
+    // See if this is a standard request or not.
+    //
+    if((pRequest->bmRequestType & USB_RTYPE_TYPE_M) != USB_RTYPE_STANDARD)
+    {
+        //
+        // Since this is not a standard request, see if there is
+        // an external handler present.
+        //
+        if(g_psUSBDevice[0].psInfo->sCallbacks.pfnRequestHandler)
+        {
+            g_psUSBDevice[0].psInfo->sCallbacks.pfnRequestHandler(
+                    g_psUSBDevice[0].pvInstance, pRequest);
+        }
+        else
+        {
+            //
+            // If there is no handler then stall this request.
+            //
+            USBDCDStallEP0(0);
+        }
+    }
+    else
+    {
+        //
+        // Assure that the jump table is not out of bounds.
+        //
+        if((pRequest->bRequest <
+           (sizeof(g_psUSBDStdRequests) / sizeof(tStdRequest))) &&
+           (g_psUSBDStdRequests[pRequest->bRequest] != 0))
+        {
+            //
+            // Jump table to the appropriate handler.
+            //
+            g_psUSBDStdRequests[pRequest->bRequest](&g_psUSBDevice[0],
+                                                    pRequest);
+        }
+        else
+        {
+            //
+            // If there is no handler then stall this request.
+            //
+            USBDCDStallEP0(0);
+        }
+    }
+}
+
+//*****************************************************************************
+//
+// This is interrupt handler for endpoint zero.
+//
+// This function handles all interrupts on endpoint zero in order to maintain
+// the state needed for the control endpoint on endpoint zero.  In order to
+// successfully enumerate and handle all USB standard requests, all requests
+// on endpoint zero must pass through this function.  The endpoint has the
+// following states: \b USB_STATE_IDLE, \b USB_STATE_TX, \b USB_STATE_RX,
+// \b USB_STATE_STALL, and \b USB_STATE_STATUS.  In the \b USB_STATE_IDLE
+// state the USB controller has not received the start of a request, and once
+// it does receive the data for the request it will either enter the
+// \b USB_STATE_TX, \b USB_STATE_RX, or \b USB_STATE_STALL depending on the
+// command.  If the controller enters the \b USB_STATE_TX or \b USB_STATE_RX
+// then once all data has been sent or received, it must pass through the
+// \b USB_STATE_STATUS state to allow the host to acknowledge completion of
+// the request.  The \b USB_STATE_STALL is entered from \b USB_STATE_IDLE in
+// the event that the USB request was not valid.  Both the \b USB_STATE_STALL
+// and \b USB_STATE_STATUS are transitional states that return to the
+// \b USB_STATE_IDLE state.
+//
+// \return None.
+//
+// USB_STATE_IDLE -*--> USB_STATE_TX -*-> USB_STATE_STATUS -*->USB_STATE_IDLE
+//                 |                  |                     |
+//                 |--> USB_STATE_RX -                      |
+//                 |                                        |
+//                 |--> USB_STATE_STALL ---------->---------
+//
+//  ----------------------------------------------------------------
+// | Current State       | State 0           | State 1              |
+// | --------------------|-------------------|----------------------
+// | USB_STATE_IDLE      | USB_STATE_TX/RX   | USB_STATE_STALL      |
+// | USB_STATE_TX        | USB_STATE_STATUS  |                      |
+// | USB_STATE_RX        | USB_STATE_STATUS  |                      |
+// | USB_STATE_STATUS    | USB_STATE_IDLE    |                      |
+// | USB_STATE_STALL     | USB_STATE_IDLE    |                      |
+//  ----------------------------------------------------------------
+//
+//*****************************************************************************
+void
+USBDeviceEnumHandler(tDeviceInstance *pDevInstance)
+{
+    unsigned long ulEPStatus;
+
+    //
+    // Get the end point 0 status.
+    //
+    ulEPStatus = MAP_USBEndpointStatus(USB0_BASE, USB_EP_0);
+
+    switch(pDevInstance->eEP0State)
+    {
+        //
+        // Handle the status state, this is a transitory state from
+        // USB_STATE_TX or USB_STATE_RX back to USB_STATE_IDLE.
+        //
+        case USB_STATE_STATUS:
+        {
+            //
+            // Just go back to the idle state.
+            //
+            pDevInstance->eEP0State = USB_STATE_IDLE;
+
+            //
+            // If there is a pending address change then set the address.
+            //
+            if(pDevInstance->ulDevAddress & DEV_ADDR_PENDING)
+            {
+                //
+                // Clear the pending address change and set the address.
+                //
+                pDevInstance->ulDevAddress &= ~DEV_ADDR_PENDING;
+                MAP_USBDevAddrSet(USB0_BASE, pDevInstance->ulDevAddress);
+            }
+
+            //
+            // If a new packet is already pending, we need to read it
+            // and handle whatever request it contains.
+            //
+            if(ulEPStatus & USB_DEV_EP0_OUT_PKTRDY)
+            {
+                //
+                // Process the newly arrived packet.
+                //
+                USBDReadAndDispatchRequest(0);
+            }
+            break;
+        }
+
+        //
+        // In the IDLE state the code is waiting to receive data from the host.
+        //
+        case USB_STATE_IDLE:
+        {
+            //
+            // Is there a packet waiting for us?
+            //
+            if(ulEPStatus & USB_DEV_EP0_OUT_PKTRDY)
+            {
+                //
+                // Yes - process it.
+                //
+                USBDReadAndDispatchRequest(0);
+            }
+            break;
+        }
+
+        //
+        // Data is still being sent to the host so handle this in the
+        // EP0StateTx() function.
+        //
+        case USB_STATE_TX:
+        {
+            USBDEP0StateTx(0);
+            break;
+        }
+
+        //
+        // We are still in the middle of sending the configuration descriptor
+        // so handle this in the EP0StateTxConfig() function.
+        //
+        case USB_STATE_TX_CONFIG:
+        {
+            USBDEP0StateTxConfig(0);
+            break;
+        }
+
+        //
+        // Handle the receive state for commands that are receiving data on
+        // endpoint zero.
+        //
+        case USB_STATE_RX:
+        {
+            unsigned long ulDataSize;
+
+            //
+            // Set the number of bytes to get out of this next packet.
+            //
+            if(pDevInstance->ulEP0DataRemain > EP0_MAX_PACKET_SIZE)
+            {
+                //
+                // Don't send more than EP0_MAX_PACKET_SIZE bytes.
+                //
+                ulDataSize = EP0_MAX_PACKET_SIZE;
+            }
+            else
+            {
+                //
+                // There was space so send the remaining bytes.
+                //
+                ulDataSize = pDevInstance->ulEP0DataRemain;
+            }
+
+            //
+            // Get the data from the USB controller end point 0.
+            //
+            MAP_USBEndpointDataGet(USB0_BASE, USB_EP_0, pDevInstance->pEP0Data,
+                                   &ulDataSize);
+
+            //
+            // If there we not more that EP0_MAX_PACKET_SIZE or more bytes
+            // remaining then this transfer is complete.  If there were exactly
+            // EP0_MAX_PACKET_SIZE remaining then there still needs to be
+            // null packet sent before this is complete.
+            //
+            if(pDevInstance->ulEP0DataRemain < EP0_MAX_PACKET_SIZE)
+            {
+                //
+                // Need to ACK the data on end point 0 in this case and set the
+                // data end as this is the last of the data.
+                //
+                MAP_USBDevEndpointDataAck(USB0_BASE, USB_EP_0, true);
+
+                //
+                // Return to the idle state.
+                //
+                pDevInstance->eEP0State =  USB_STATE_STATUS;
+
+                //
+                // If there is a receive callback then call it.
+                //
+                if((pDevInstance->psInfo->sCallbacks.pfnDataReceived) &&
+                   (pDevInstance->ulOUTDataSize != 0))
+                {
+                    //
+                    // Call the custom receive handler to handle the data
+                    // that was received.
+                    //
+                    pDevInstance->psInfo->sCallbacks.pfnDataReceived(
+                        pDevInstance->pvInstance,
+                        pDevInstance->ulOUTDataSize);
+
+                    //
+                    // Indicate that there is no longer any data being waited
+                    // on.
+                    //
+                    pDevInstance->ulOUTDataSize = 0;
+                }
+            }
+            else
+            {
+                //
+                // Need to ACK the data on end point 0 in this case
+                // without setting data end because more data is coming.
+                //
+                MAP_USBDevEndpointDataAck(USB0_BASE, USB_EP_0, false);
+            }
+
+            //
+            // Advance the pointer.
+            //
+            pDevInstance->pEP0Data += ulDataSize;
+
+            //
+            // Decrement the number of bytes that are being waited on.
+            //
+            pDevInstance->ulEP0DataRemain -= ulDataSize;
+
+            break;
+        }
+        //
+        // The device stalled endpoint zero so check if the stall needs to be
+        // cleared once it has been successfully sent.
+        //
+        case USB_STATE_STALL:
+        {
+            //
+            // If we sent a stall then acknowledge this interrupt.
+            //
+            if(ulEPStatus & USB_DEV_EP0_SENT_STALL)
+            {
+                //
+                // Clear the Setup End condition.
+                //
+                MAP_USBDevEndpointStatusClear(USB0_BASE, USB_EP_0,
+                                              USB_DEV_EP0_SENT_STALL);
+
+                //
+                // Reset the global end point 0 state to IDLE.
+                //
+                pDevInstance->eEP0State = USB_STATE_IDLE;
+
+            }
+            break;
+        }
+        //
+        // Halt on an unknown state, but only in DEBUG mode builds.
+        //
+        default:
+        {
+            ASSERT(0);
+        }
+    }
+}
+
+//*****************************************************************************
+//
+// This function handles bus reset notifications.
+//
+// This function is called from the low level USB interrupt handler whenever
+// a bus reset is detected.  It performs tidy-up as required and resets the
+// configuration back to defaults in preparation for descriptor queries from
+// the host.
+//
+// \return None.
+//
+//*****************************************************************************
+void
+USBDeviceEnumResetHandler(tDeviceInstance *pDevInstance)
+{
+    unsigned long ulLoop;
+
+    //
+    // Disable remote wake up signaling (as per USB 2.0 spec 9.1.1.6).
+    //
+    pDevInstance->ucStatus &= ~USB_STATUS_REMOTE_WAKE;
+    pDevInstance->bRemoteWakeup = false;
+
+    //
+    // Call the device dependent code to indicate a bus reset has occurred.
+    //
+    if(pDevInstance->psInfo->sCallbacks.pfnResetHandler)
+    {
+        pDevInstance->psInfo->sCallbacks.pfnResetHandler(
+            pDevInstance->pvInstance);
+    }
+
+    //
+    // Reset the default configuration identifier and alternate function
+    // selections.
+    //
+    pDevInstance->ulConfiguration = pDevInstance->ulDefaultConfiguration;
+
+    for(ulLoop = 0; ulLoop < USB_MAX_INTERFACES_PER_DEVICE; ulLoop++)
+    {
+        pDevInstance->pucAltSetting[ulLoop] = (unsigned char)0;
+    }
+}
+
+//*****************************************************************************
+//
+// This function handles the GET_STATUS standard USB request.
+//
+// \param pvInstance is the USB device controller instance data.
+// \param pUSBRequest holds the request type and endpoint number if endpoint
+// status is requested.
+//
+// This function handles responses to a Get Status request from the host
+// controller.  A status request can be for the device, an interface or an
+// endpoint.  If any other type of request is made this function will cause
+// a stall condition to indicate that the command is not supported.  The
+// \e pUSBRequest structure holds the type of the request in the
+// bmRequestType field.  If the type indicates that this is a request for an
+// endpoint's status, then the wIndex field holds the endpoint number.
+//
+// \return None.
+//
+//*****************************************************************************
+static void
+USBDGetStatus(void *pvInstance, tUSBRequest *pUSBRequest)
+{
+    unsigned short usData;
+    tDeviceInstance *psUSBControl;
+
+    ASSERT(pUSBRequest != 0);
+    ASSERT(pvInstance != 0);
+
+    //
+    // Create the device information pointer.
+    //
+    psUSBControl = (tDeviceInstance *)pvInstance;
+
+    //
+    // Need to ACK the data on end point 0 without setting last data as there
+    // will be a data phase.
+    //
+    MAP_USBDevEndpointDataAck(USB0_BASE, USB_EP_0, false);
+
+    //
+    // Determine what type of status was requested.
+    //
+    switch(pUSBRequest->bmRequestType & USB_RTYPE_RECIPIENT_M)
+    {
+        //
+        // This was a Device Status request.
+        //
+        case USB_RTYPE_DEVICE:
+        {
+            //
+            // Return the current status for the device.
+            //
+            usData = (unsigned short)psUSBControl->ucStatus;
+
+            break;
+        }
+
+        //
+        // This was a Interface status request.
+        //
+        case USB_RTYPE_INTERFACE:
+        {
+            //
+            // Interface status always returns 0.
+            //
+            usData = (unsigned short)0;
+
+            break;
+        }
+
+        //
+        // This was an endpoint status request.
+        //
+        case USB_RTYPE_ENDPOINT:
+        {
+            unsigned short usIndex;
+            unsigned long ulDir;
+
+            //
+            // Which endpoint are we dealing with?
+            //
+            usIndex = pUSBRequest->wIndex & USB_REQ_EP_NUM_M;
+
+            //
+            // Check if this was a valid endpoint request.
+            //
+            if((usIndex == 0) || (usIndex >= NUM_USB_EP))
+            {
+                USBDCDStallEP0(0);
+                return;
+            }
+            else
+            {
+                //
+                // Are we dealing with an IN or OUT endpoint?
+                //
+                ulDir = ((pUSBRequest->wIndex & USB_REQ_EP_DIR_M) ==
+                         USB_REQ_EP_DIR_IN) ? HALT_EP_IN : HALT_EP_OUT;
+
+                //
+                // Get the current halt status for this endpoint.
+                //
+                usData =
+                      (unsigned short)psUSBControl->ucHalt[ulDir][usIndex - 1];
+            }
+            break;
+        }
+
+        //
+        // This was an unknown request.
+        //
+        default:
+        {
+            //
+            // Anything else causes a stall condition to indicate that the
+            // command was not supported.
+            //
+            USBDCDStallEP0(0);
+            return;
+        }
+    }
+
+    //
+    // Send the two byte status response.
+    //
+    psUSBControl->ulEP0DataRemain = 2;
+    psUSBControl->pEP0Data = (unsigned char *)&usData;
+
+    //
+    // Send the response.
+    //
+    USBDEP0StateTx(0);
+}
+
+//*****************************************************************************
+//
+// This function handles the CLEAR_FEATURE standard USB request.
+//
+// \param pvInstance is the USB device controller instance data.
+// \param pUSBRequest holds the options for the Clear Feature USB request.
+//
+// This function handles device or endpoint clear feature requests.  The
+// \e pUSBRequest structure holds the type of the request in the bmRequestType
+// field and the feature is held in the wValue field.  The device can only
+// clear the Remote Wake feature.  This device request should only be made if
+// the descriptor indicates that Remote Wake is implemented by the device.
+// Endpoints can only clear a halt on a given endpoint.  If any other
+// requests are made, then the device will stall the request to indicate to
+// the host that the command was not supported.
+//
+// \return None.
+//
+//*****************************************************************************
+static void
+USBDClearFeature(void *pvInstance, tUSBRequest *pUSBRequest)
+{
+    tDeviceInstance *psUSBControl;
+
+    ASSERT(pUSBRequest != 0);
+    ASSERT(pvInstance != 0);
+
+    //
+    // Create the device information pointer.
+    //
+    psUSBControl = (tDeviceInstance *)pvInstance;
+
+    //
+    // Need to ACK the data on end point 0 with last data set as this has no
+    // data phase.
+    //
+    MAP_USBDevEndpointDataAck(USB0_BASE, USB_EP_0, true);
+
+    //
+    // Determine what type of status was requested.
+    //
+    switch(pUSBRequest->bmRequestType & USB_RTYPE_RECIPIENT_M)
+    {
+        //
+        // This is a clear feature request at the device level.
+        //
+        case USB_RTYPE_DEVICE:
+        {
+            //
+            // Only remote wake is can be cleared by this function.
+            //
+            if(USB_FEATURE_REMOTE_WAKE & pUSBRequest->wValue)
+            {
+                //
+                // Clear the remote wake up state.
+                //
+                psUSBControl->ucStatus &= ~USB_STATUS_REMOTE_WAKE;
+            }
+            else
+            {
+                USBDCDStallEP0(0);
+            }
+            break;
+        }
+
+        //
+        // This is a clear feature request at the endpoint level.
+        //
+        case USB_RTYPE_ENDPOINT:
+        {
+            unsigned long ulDir;
+            unsigned short usIndex;
+
+            //
+            // Which endpoint are we dealing with?
+            //
+            usIndex = pUSBRequest->wIndex & USB_REQ_EP_NUM_M;
+
+            //
+            // Not a valid endpoint.
+            //
+            if((usIndex == 0) || (usIndex > NUM_USB_EP))
+            {
+                USBDCDStallEP0(0);
+            }
+            else
+            {
+                //
+                // Only the halt feature is supported.
+                //
+                if(USB_FEATURE_EP_HALT == pUSBRequest->wValue)
+                {
+                    //
+                    // Are we dealing with an IN or OUT endpoint?
+                    //
+                    ulDir = ((pUSBRequest->wIndex & USB_REQ_EP_DIR_M) ==
+                             USB_REQ_EP_DIR_IN) ? HALT_EP_IN : HALT_EP_OUT;
+
+                    //
+                    // Clear the halt condition on this endpoint.
+                    //
+                    psUSBControl->ucHalt[ulDir][usIndex - 1] = 0;
+
+                    if(ulDir == HALT_EP_IN)
+                    {
+                        MAP_USBDevEndpointStallClear(USB0_BASE,
+                                                     INDEX_TO_USB_EP(usIndex),
+                                                     USB_EP_DEV_IN);
+                    }
+                    else
+                    {
+                        MAP_USBDevEndpointStallClear(USB0_BASE,
+                                                     INDEX_TO_USB_EP(usIndex),
+                                                     USB_EP_DEV_OUT);
+                    }
+                }
+                else
+                {
+                    //
+                    // If any other feature is requested, this is an error.
+                    //
+                    USBDCDStallEP0(0);
+                    return;
+                }
+            }
+            break;
+        }
+
+        //
+        // This is an unknown request.
+        //
+        default:
+        {
+            USBDCDStallEP0(0);
+            return;
+        }
+    }
+}
+
+//*****************************************************************************
+//
+// This function handles the SET_FEATURE standard USB request.
+//
+// \param pvInstance is the USB device controller instance data.
+// \param pUSBRequest holds the feature in the wValue field of the USB
+// request.
+//
+// This function handles device or endpoint set feature requests.  The
+// \e pUSBRequest structure holds the type of the request in the bmRequestType
+// field and the feature is held in the wValue field.  The device can only
+// set the Remote Wake feature.  This device request should only be made if the
+// descriptor indicates that Remote Wake is implemented by the device.
+// Endpoint requests can only issue a halt on a given endpoint.  If any other
+// requests are made, then the device will stall the request to indicate to the
+// host that the command was not supported.
+//
+// \return None.
+//
+//*****************************************************************************
+static void
+USBDSetFeature(void *pvInstance, tUSBRequest *pUSBRequest)
+{
+    tDeviceInstance *psUSBControl;
+
+    ASSERT(pUSBRequest != 0);
+    ASSERT(pvInstance != 0);
+
+    //
+    // Create the device information pointer.
+    //
+    psUSBControl = (tDeviceInstance *)pvInstance;
+
+    //
+    // Need to ACK the data on end point 0 with last data set as this has no
+    // data phase.
+    //
+    MAP_USBDevEndpointDataAck(USB0_BASE, USB_EP_0, true);
+
+    //
+    // Determine what type of status was requested.
+    //
+    switch(pUSBRequest->bmRequestType & USB_RTYPE_RECIPIENT_M)
+    {
+        //
+        // This is a set feature request at the device level.
+        //
+        case USB_RTYPE_DEVICE:
+        {
+            //
+            // Only remote wake is the only feature that can be set by this
+            // function.
+            //
+            if(USB_FEATURE_REMOTE_WAKE & pUSBRequest->wValue)
+            {
+                //
+                // Set the remote wake up state.
+                //
+                psUSBControl->ucStatus |= USB_STATUS_REMOTE_WAKE;
+            }
+            else
+            {
+                USBDCDStallEP0(0);
+            }
+            break;
+        }
+
+        //
+        // This is a set feature request at the endpoint level.
+        //
+        case USB_RTYPE_ENDPOINT:
+        {
+            unsigned short usIndex;
+            unsigned long ulDir;
+
+            //
+            // Which endpoint are we dealing with?
+            //
+            usIndex = pUSBRequest->wIndex & USB_REQ_EP_NUM_M;
+
+            //
+            // Not a valid endpoint?
+            //
+            if((usIndex == 0) || (usIndex >= NUM_USB_EP))
+            {
+                USBDCDStallEP0(0);
+            }
+            else
+            {
+                //
+                // Only the Halt feature can be set.
+                //
+                if(USB_FEATURE_EP_HALT == pUSBRequest->wValue)
+                {
+                    //
+                    // Are we dealing with an IN or OUT endpoint?
+                    //
+                    ulDir = ((pUSBRequest->wIndex & USB_REQ_EP_DIR_M) ==
+                             USB_REQ_EP_DIR_IN) ? HALT_EP_IN : HALT_EP_OUT;
+
+                    //
+                    // Clear the halt condition on this endpoint.
+                    //
+                    psUSBControl->ucHalt[ulDir][usIndex - 1] = 1;
+                }
+                else
+                {
+                    //
+                    // No other requests are supported.
+                    //
+                    USBDCDStallEP0(0);
+                    return;
+                }
+            }
+            break;
+        }
+
+        //
+        // This is an unknown request.
+        //
+        default:
+        {
+            USBDCDStallEP0(0);
+            return;
+        }
+    }
+}
+
+//*****************************************************************************
+//
+// This function handles the SET_ADDRESS standard USB request.
+//
+// \param pvInstance is the USB device controller instance data.
+// \param pUSBRequest holds the new address to use in the wValue field of the
+// USB request.
+//
+// This function is called to handle the change of address request from the
+// host controller.  This can only start the sequence as the host must
+// acknowledge that the device has changed address.  Thus this function sets
+// the address change as pending until the status phase of the request has
+// been completed successfully.  This prevents the devices address from
+// changing and not properly responding to the status phase.
+//
+// \return None.
+//
+//*****************************************************************************
+static void
+USBDSetAddress(void *pvInstance, tUSBRequest *pUSBRequest)
+{
+    tDeviceInstance *psUSBControl;
+
+    ASSERT(pUSBRequest != 0);
+    ASSERT(pvInstance != 0);
+
+    //
+    // Create the device information pointer.
+    //
+    psUSBControl = (tDeviceInstance *)pvInstance;
+
+    //
+    // Need to ACK the data on end point 0 with last data set as this has no
+    // data phase.
+    //
+    MAP_USBDevEndpointDataAck(USB0_BASE, USB_EP_0, true);
+
+    //
+    // Save the device address as we cannot change address until the status
+    // phase is complete.
+    //
+    psUSBControl->ulDevAddress = pUSBRequest->wValue | DEV_ADDR_PENDING;
+
+    //
+    // Transition directly to the status state since there is no data phase
+    // for this request.
+    //
+    psUSBControl->eEP0State = USB_STATE_STATUS;
+}
+
+//*****************************************************************************
+//
+// This function handles the GET_DESCRIPTOR standard USB request.
+//
+// \param pvInstance is the USB device controller instance data.
+// \param pUSBRequest holds the data for this request.
+//
+// This function will return most of the descriptors requested by the host
+// controller.  The descriptor specified by \e
+// pvInstance->psInfo->pDeviceDescriptor will be returned when the device
+// descriptor is requested.  If a request for a specific configuration
+// descriptor is made, then the appropriate descriptor from the \e
+// g_pConfigDescriptors will be returned.  When a request for a string
+// descriptor is made, the appropriate string from the
+// \e pvInstance->psInfo->pStringDescriptors will be returned.  If the \e
+// pvInstance->psInfo->sCallbacks.GetDescriptor is specified it will be
+// called to handle the request.  In this case it must call the
+// USBDCDSendDataEP0() function to send the data to the host controller.  If
+// the callback is not specified, and the descriptor request is not for a
+// device, configuration, or string descriptor then this function will stall
+// the request to indicate that the request was not supported by the device.
+//
+// \return None.
+//
+//*****************************************************************************
+static void
+USBDGetDescriptor(void *pvInstance, tUSBRequest *pUSBRequest)
+{
+    tBoolean bConfig;
+    tDeviceInstance *psUSBControl;
+    tDeviceInfo *psDevice;
+
+    ASSERT(pUSBRequest != 0);
+    ASSERT(pvInstance != 0);
+
+    //
+    // Create the device information pointer.
+    //
+    psUSBControl = (tDeviceInstance *)pvInstance;
+    psDevice = psUSBControl->psInfo;
+
+    //
+    // Need to ACK the data on end point 0 without setting last data as there
+    // will be a data phase.
+    //
+    MAP_USBDevEndpointDataAck(USB0_BASE, USB_EP_0, false);
+
+    //
+    // Assume we are not sending the configuration descriptor until we
+    // determine otherwise.
+    //
+    bConfig = false;
+
+    //
+    // Which descriptor are we being asked for?
+    //
+    switch(pUSBRequest->wValue >> 8)
+    {
+        //
+        // This request was for a device descriptor.
+        //
+        case USB_DTYPE_DEVICE:
+        {
+            //
+            // Return the externally provided device descriptor.
+            //
+            psUSBControl->pEP0Data =
+                (unsigned char *)psDevice->pDeviceDescriptor;
+
+            //
+            // The size of the device descriptor is in the first byte.
+            //
+            psUSBControl->ulEP0DataRemain = psDevice->pDeviceDescriptor[0];
+
+            break;
+        }
+
+        //
+        // This request was for a configuration descriptor.
+        //
+        case USB_DTYPE_CONFIGURATION:
+        {
+            const tConfigHeader *psConfig;
+            const tDeviceDescriptor *psDeviceDesc;
+            unsigned char ucIndex;
+
+            //
+            // Which configuration are we being asked for?
+            //
+            ucIndex = (unsigned char)(pUSBRequest->wValue & 0xFF);
+
+            //
+            // Is this valid?
+            //
+            psDeviceDesc =
+                (const tDeviceDescriptor *)psDevice->pDeviceDescriptor;
+
+            if(ucIndex >= psDeviceDesc->bNumConfigurations)
+            {
+                //
+                // This is an invalid configuration index.  Stall EP0 to
+                // indicate a request error.
+                //
+                USBDCDStallEP0(0);
+                psUSBControl->pEP0Data = 0;
+                psUSBControl->ulEP0DataRemain = 0;
+            }
+            else
+            {
+                //
+                // Return the externally specified configuration descriptor.
+                //
+                psConfig = psDevice->ppConfigDescriptors[ucIndex];
+
+                //
+                // Start by sending data from the beginning of the first
+                // descriptor.
+                //
+                psUSBControl->ucConfigSection = 0;
+                psUSBControl->ucSectionOffset = 0;
+                psUSBControl->pEP0Data = (unsigned char *)
+                                          psConfig->psSections[0]->pucData;
+
+                //
+                // Determine the total size of the configuration descriptor
+                // by counting the sizes of the sections comprising it.
+                //
+                psUSBControl->ulEP0DataRemain =
+                                            USBDCDConfigDescGetSize(psConfig);
+
+                //
+                // Remember that we need to send the configuration descriptor
+                // and which descriptor we need to send.
+                //
+                psUSBControl->ucConfigIndex = ucIndex;
+
+                bConfig = true;
+            }
+            break;
+        }
+
+        //
+        // This request was for a string descriptor.
+        //
+        case USB_DTYPE_STRING:
+        {
+            long lIndex;
+
+            //
+            // Determine the correct descriptor index based on the requested
+            // language ID and index.
+            //
+            lIndex = USBDStringIndexFromRequest(pUSBRequest->wIndex,
+                                                pUSBRequest->wValue & 0xFF);
+
+            //
+            // If the mapping function returned -1 then stall the request to
+            // indicate that the request was not valid.
+            //
+            if(lIndex == -1)
+            {
+                USBDCDStallEP0(0);
+                break;
+            }
+
+            //
+            // Return the externally specified configuration descriptor.
+            //
+            psUSBControl->pEP0Data =
+                (unsigned char *)psDevice->ppStringDescriptors[lIndex];
+
+            //
+            // The total size of a string descriptor is in byte 0.
+            //
+            psUSBControl->ulEP0DataRemain =
+                psDevice->ppStringDescriptors[lIndex][0];
+
+            break;
+        }
+
+        //
+        // Any other request is not handled by the default enumeration handler
+        // so see if it needs to be passed on to another handler.
+        //
+        default:
+        {
+            //
+            // If there is a handler for requests that are not handled then
+            // call it.
+            //
+            if(psDevice->sCallbacks.pfnGetDescriptor)
+            {
+                psDevice->sCallbacks.pfnGetDescriptor(psUSBControl->pvInstance,
+                                                      pUSBRequest);
+                return;
+            }
+            else
+            {
+                //
+                // Whatever this was this handler does not understand it so
+                // just stall the request.
+                //
+                USBDCDStallEP0(0);
+            }
+            break;
+        }
+    }
+
+    //
+    // If this request has data to send, then send it.
+    //
+    if(psUSBControl->pEP0Data)
+    {
+        //
+        // If there is more data to send than is requested then just
+        // send the requested amount of data.
+        //
+        if(psUSBControl->ulEP0DataRemain > pUSBRequest->wLength)
+        {
+            psUSBControl->ulEP0DataRemain = pUSBRequest->wLength;
+        }
+
+        //
+        // Now in the transmit data state.  Be careful to call the correct
+        // function since we need to handle the configuration descriptor
+        // differently from the others.
+        //
+        if(!bConfig)
+        {
+            USBDEP0StateTx(0);
+        }
+        else
+        {
+            USBDEP0StateTxConfig(0);
+        }
+    }
+}
+
+//*****************************************************************************
+//
+// This function determines which string descriptor to send to satisfy a
+// request for a given index and language.
+//
+// \param usLang is the requested string language ID.
+// \param usIndex is the requested string descriptor index.
+//
+// When a string descriptor is requested, the host provides a language ID and
+// index to identify the string ("give me string number 5 in French").  This
+// function maps these two parameters to an index within our device's string
+// descriptor array which is arranged as multiple groups of strings with
+// one group for each language advertised via string descriptor 0.
+//
+// We assume that there are an equal number of strings per language and
+// that the first descriptor is the language descriptor and use this fact to
+// perform the mapping.
+//
+// \return The index of the string descriptor to return or -1 if the string
+// could not be found.
+//
+//*****************************************************************************
+static long
+USBDStringIndexFromRequest(unsigned short usLang, unsigned short usIndex)
+{
+    tString0Descriptor *pLang;
+    unsigned long ulNumLangs;
+    unsigned long ulNumStringsPerLang;
+    unsigned long ulLoop;
+
+    //
+    // Make sure we have a string table at all.
+    //
+    if((g_psUSBDevice[0].psInfo == 0) ||
+       (g_psUSBDevice[0].psInfo->ppStringDescriptors == 0))
+    {
+        return(-1);
+    }
+
+    //
+    // First look for the trivial case where descriptor 0 is being
+    // requested.  This is the special case since descriptor 0 contains the
+    // language codes supported by the device.
+    //
+    if(usIndex == 0)
+    {
+        return(0);
+    }
+
+    //
+    // How many languages does this device support?  This is determined by
+    // looking at the length of the first descriptor in the string table,
+    // subtracting 2 for the header and dividing by two (the size of each
+    // language code).
+    //
+    ulNumLangs = (g_psUSBDevice[0].psInfo->ppStringDescriptors[0][0] - 2) / 2;
+
+    //
+    // We assume that the table includes the same number of strings for each
+    // supported language.  We know the number of entries in the string table,
+    // so how many are there for each language?  This may seem an odd way to
+    // do this (why not just have the application tell us in the device info
+    // structure?) but it's needed since we didn't want to change the API
+    // after the first release which did not support multiple languages.
+    //
+    ulNumStringsPerLang = ((g_psUSBDevice[0].psInfo->ulNumStringDescriptors - 1) /
+                           ulNumLangs);
+
+    //
+    // Just to be sure, make sure that the calculation indicates an equal
+    // number of strings per language.  We expect the string table to contain
+    // (1 + (strings_per_language * languages)) entries.
+    //
+    if((1 + (ulNumStringsPerLang * ulNumLangs)) !=
+       g_psUSBDevice[0].psInfo->ulNumStringDescriptors)
+    {
+        return(-1);
+    }
+
+    //
+    // Now determine which language we are looking for.  It is assumed that
+    // the order of the groups of strings per language in the table is the
+    // same as the order of the language IDs listed in the first descriptor.
+    //
+    pLang = (tString0Descriptor *)(g_psUSBDevice[0].psInfo->ppStringDescriptors[0]);
+
+    //
+    // Look through the supported languages looking for the one we were asked
+    // for.
+    //
+    for(ulLoop = 0; ulLoop < ulNumLangs; ulLoop++)
+    {
+        //
+        // Have we found the requested language?
+        //
+        if(pLang->wLANGID[ulLoop] == usLang)
+        {
+            //
+            // Yes - calculate the index of the descriptor to send.
+            //
+            return((ulNumStringsPerLang * ulLoop) + usIndex);
+        }
+    }
+
+    //
+    // If we drop out of the loop, the requested language was not found so
+    // return -1 to indicate the error.
+    //
+    return(-1);
+}
+
+//*****************************************************************************
+//
+// This function handles the SET_DESCRIPTOR standard USB request.
+//
+// \param pvInstance is the USB device controller instance data.
+// \param pUSBRequest holds the data for this request.
+//
+// This function currently is not supported and will respond with a Stall
+// to indicate that this command is not supported by the device.
+//
+// \return None.
+//
+//*****************************************************************************
+static void
+USBDSetDescriptor(void *pvInstance, tUSBRequest *pUSBRequest)
+{
+    //
+    // Need to ACK the data on end point 0 without setting last data as there
+    // will be a data phase.
+    //
+    MAP_USBDevEndpointDataAck(USB0_BASE, USB_EP_0, false);
+
+    //
+    // This function is not handled by default.
+    //
+    USBDCDStallEP0(0);
+}
+
+//*****************************************************************************
+//
+// This function handles the GET_CONFIGURATION standard USB request.
+//
+// \param pvInstance is the USB device controller instance data.
+// \param pUSBRequest holds the data for this request.
+//
+// This function responds to a host request to return the current
+// configuration of the USB device.  The function will send the configuration
+// response to the host and return.  This value will either be 0 or the last
+// value received from a call to SetConfiguration().
+//
+// \return None.
+//
+//*****************************************************************************
+static void
+USBDGetConfiguration(void *pvInstance, tUSBRequest *pUSBRequest)
+{
+    unsigned char ucValue;
+    tDeviceInstance *psUSBControl;
+
+    ASSERT(pUSBRequest != 0);
+    ASSERT(pvInstance != 0);
+
+    //
+    // Create the device information pointer.
+    //
+    psUSBControl = (tDeviceInstance *)pvInstance;
+
+    //
+    // Need to ACK the data on end point 0 without setting last data as there
+    // will be a data phase.
+    //
+    MAP_USBDevEndpointDataAck(USB0_BASE, USB_EP_0, false);
+
+    //
+    // If we still have an address pending then the device is still not
+    // configured.
+    //
+    if(psUSBControl->ulDevAddress & DEV_ADDR_PENDING)
+    {
+        ucValue = 0;
+    }
+    else
+    {
+        ucValue = (unsigned char)psUSBControl->ulConfiguration;
+    }
+
+    psUSBControl->ulEP0DataRemain = 1;
+    psUSBControl->pEP0Data = &ucValue;
+
+    //
+    // Send the single byte response.
+    //
+    USBDEP0StateTx(0);
+}
+
+//*****************************************************************************
+//
+// This function handles the SET_CONFIGURATION standard USB request.
+//
+// \param pvInstance is the USB device controller instance data.
+// \param pUSBRequest holds the data for this request.
+//
+// This function responds to a host request to change the current
+// configuration of the USB device.  The actual configuration number is taken
+// from the structure passed in via \e pUSBRequest.  This number should be one
+// of the configurations that was specified in the descriptors.  If the
+// \e ConfigChange callback is specified in \e pvInstance->psInfo->sCallbacks,
+// it will be called so that the application can respond to a change in
+// configuration.
+//
+// \return None.
+//
+//*****************************************************************************
+static void
+USBDSetConfiguration(void *pvInstance, tUSBRequest *pUSBRequest)
+{
+    tDeviceInstance *psUSBControl;
+    tDeviceInfo *psDevice;
+
+    //
+    // Create the device information pointer.
+    //
+    psUSBControl = (tDeviceInstance *)pvInstance;
+    psDevice = psUSBControl->psInfo;
+
+    //
+    // Need to ACK the data on end point 0 with last data set as this has no
+    // data phase.
+    //
+    MAP_USBDevEndpointDataAck(USB0_BASE, USB_EP_0, true);
+
+    //
+    // Cannot set the configuration to one that does not exist so check the
+    // enumeration structure to see how many valid configurations are present.
+    //
+    if(pUSBRequest->wValue > psUSBControl->psInfo->pDeviceDescriptor[17])
+    {
+        //
+        // The passed configuration number is not valid.  Stall the endpoint to
+        // signal the error to the host.
+        //
+        USBDCDStallEP0(0);
+    }
+    else
+    {
+        //
+        // Save the configuration.
+        //
+        psUSBControl->ulConfiguration = pUSBRequest->wValue;
+
+        //
+        // If passed a configuration other than 0 (which tells us that we are
+        // not currently configured), configure the endpoints (other than EP0)
+        // appropriately.
+        //
+        if(psUSBControl->ulConfiguration)
+        {
+            const tConfigHeader *psHdr;
+            const tConfigDescriptor *psDesc;
+
+            //
+            // Get a pointer to the configuration descriptor.  This will always
+            // be the first section in the current configuration.
+            //
+            psHdr = psDevice->ppConfigDescriptors[pUSBRequest->wValue - 1];
+            psDesc = (const tConfigDescriptor *)(psHdr->psSections[0]->pucData);
+
+            //
+            // Remember the new self- or bus-powered state if the user has not
+            // already called us to tell us the state to report.
+            //
+            if(!psUSBControl->bPwrSrcSet)
+            {
+                if((psDesc->bmAttributes & USB_CONF_ATTR_PWR_M) ==
+                    USB_CONF_ATTR_SELF_PWR)
+                {
+                    psUSBControl->ucStatus |= USB_STATUS_SELF_PWR;
+                }
+                else
+                {
+                    psUSBControl->ucStatus &= ~USB_STATUS_SELF_PWR;
+                }
+            }
+
+            //
+            // Configure endpoints for the new configuration.
+            //
+            USBDeviceConfig(0,
+                         psDevice->ppConfigDescriptors[pUSBRequest->wValue - 1],
+                         psDevice->psFIFOConfig);
+        }
+
+        //
+        // If there is a configuration change callback then call it.
+        //
+        if(psDevice->sCallbacks.pfnConfigChange)
+        {
+            psDevice->sCallbacks.pfnConfigChange(
+                psUSBControl->pvInstance, psUSBControl->ulConfiguration);
+        }
+    }
+}
+
+//*****************************************************************************
+//
+// This function handles the GET_INTERFACE standard USB request.
+//
+// \param pvInstance is the USB device controller instance data.
+// \param pUSBRequest holds the data for this request.
+//
+// This function is called when the host controller request the current
+// interface that is in use by the device.  This simply returns the value set
+// by the last call to SetInterface().
+//
+// \return None.
+//
+//*****************************************************************************
+static void
+USBDGetInterface(void *pvInstance, tUSBRequest *pUSBRequest)
+{
+    unsigned char ucValue;
+    tDeviceInstance *psUSBControl;
+
+    ASSERT(pUSBRequest != 0);
+    ASSERT(pvInstance != 0);
+
+    //
+    // Create the device information pointer.
+    //
+    psUSBControl = (tDeviceInstance *)pvInstance;
+
+    //
+    // Need to ACK the data on end point 0 without setting last data as there
+    // will be a data phase.
+    //
+    MAP_USBDevEndpointDataAck(USB0_BASE, USB_EP_0, false);
+
+    //
+    // If we still have an address pending then the device is still not
+    // configured.
+    //
+    if(psUSBControl->ulDevAddress & DEV_ADDR_PENDING)
+    {
+        ucValue = (unsigned char)0;
+    }
+    else
+    {
+        //
+        // Is the interface number valid?
+        //
+        if(pUSBRequest->wIndex < USB_MAX_INTERFACES_PER_DEVICE)
+        {
+            //
+            // Read the current alternate setting for the required interface.
+            //
+            ucValue = psUSBControl->pucAltSetting[pUSBRequest->wIndex];
+        }
+        else
+        {
+            //
+            // An invalid interface number was specified.
+            //
+            USBDCDStallEP0(0);
+            return;
+        }
+    }
+
+    //
+    // Send the single byte response.
+    //
+    psUSBControl->ulEP0DataRemain = 1;
+    psUSBControl->pEP0Data = &ucValue;
+
+    //
+    // Send the single byte response.
+    //
+    USBDEP0StateTx(0);
+}
+
+//*****************************************************************************
+//
+// This function handles the SET_INTERFACE standard USB request.
+//
+// \param pvInstance is the USB device controller instance data.
+// \param pUSBRequest holds the data for this request.
+//
+// This function is called when a standard request for changing the interface
+// is received from the host controller.  If this is a valid request the
+// function will call the function specified by the InterfaceChange in the
+// \e pvInstance->psInfo->sCallbacks variable to notify the application that the
+// interface has changed and will pass it the new alternate interface number.
+//
+// \return None.
+//
+//*****************************************************************************
+static void
+USBDSetInterface(void *pvInstance, tUSBRequest *pUSBRequest)
+{
+    const tConfigHeader *psConfig;
+    tInterfaceDescriptor *psInterface;
+    unsigned long ulLoop;
+    unsigned long ulSection;
+    unsigned long ulNumInterfaces;
+    unsigned char ucInterface;
+    tBoolean bRetcode;
+    tDeviceInstance *psUSBControl;
+    tDeviceInfo *psDevice;
+
+    ASSERT(pUSBRequest != 0);
+    ASSERT(pvInstance != 0);
+
+    //
+    // Create the device information pointer.
+    //
+    psUSBControl = (tDeviceInstance *)pvInstance;
+    psDevice = psUSBControl->psInfo;
+
+    //
+    // Need to ACK the data on end point 0 with last data set as this has no
+    // data phase.
+    //
+    MAP_USBDevEndpointDataAck(USB0_BASE, USB_EP_0, true);
+
+    //
+    // Use the current configuration.
+    //
+    psConfig = psDevice->ppConfigDescriptors[psUSBControl->ulConfiguration - 1];
+
+    //
+    // How many interfaces are included in the descriptor?
+    //
+    ulNumInterfaces = USBDCDConfigDescGetNum(psConfig,
+                                             USB_DTYPE_INTERFACE);
+
+    //
+    // Find the interface descriptor for the supplied interface and alternate
+    // setting numbers.
+    //
+    for(ulLoop = 0; ulLoop < ulNumInterfaces; ulLoop++)
+    {
+        //
+        // Get the next interface descriptor in the configuration descriptor.
+        //
+        psInterface = USBDCDConfigGetInterface(psConfig, ulLoop, USB_DESC_ANY,
+                                               &ulSection);
+
+        //
+        // Is this the required interface with the correct alternate setting?
+        //
+        if(psInterface &&
+           (psInterface->bInterfaceNumber == pUSBRequest->wIndex) &&
+           (psInterface->bAlternateSetting == pUSBRequest->wValue))
+        {
+            ucInterface = psInterface->bInterfaceNumber;
+
+            //
+            // Make sure we don't write outside the bounds of the pucAltSetting
+            // array (in a debug build, anyway, since this indicates an error
+            // in the device descriptor).
+            //
+            ASSERT(ucInterface < USB_MAX_INTERFACES_PER_DEVICE);
+
+            //
+            // This is the correct interface descriptor so save the
+            // setting.
+            //
+            psUSBControl->pucAltSetting[ucInterface] =
+                                            psInterface->bAlternateSetting;
+
+            //
+            // Reconfigure the endpoints to match the requirements of the
+            // new alternate setting for the interface.
+            //
+            bRetcode = USBDeviceConfigAlternate(0, psConfig, ucInterface,
+                                           psInterface->bAlternateSetting);
+
+            //
+            // If there is a callback then notify the application of the
+            // change to the alternate interface.
+            //
+            if(bRetcode && psDevice->sCallbacks.pfnInterfaceChange)
+            {
+                psDevice->sCallbacks.pfnInterfaceChange(
+                                                psUSBControl->pvInstance,
+                                                pUSBRequest->wIndex,
+                                                pUSBRequest->wValue);
+            }
+
+            //
+            // All done.
+            //
+            return;
+        }
+    }
+
+    //
+    // If we drop out of the loop, we didn't find an interface descriptor
+    // matching the requested number and alternate setting or there was an
+    // error while trying to set up for the new alternate setting.
+    //
+    USBDCDStallEP0(0);
+}
+
+//*****************************************************************************
+//
+// This function handles the SYNC_FRAME standard USB request.
+//
+// \param pvInstance is the USB device controller instance data.
+// \param pUSBRequest holds the data for this request.
+//
+// This is currently a stub function that will stall indicating that the
+// command is not supported.
+//
+// \return None.
+//
+//*****************************************************************************
+static void
+USBDSyncFrame(void *pvInstance, tUSBRequest *pUSBRequest)
+{
+    //
+    // Need to ACK the data on end point 0 with last data set as this has no
+    // data phase.
+    //
+    MAP_USBDevEndpointDataAck(USB0_BASE, USB_EP_0, true);
+
+    //
+    // Not handled yet so stall this request.
+    //
+    USBDCDStallEP0(0);
+}
+
+//*****************************************************************************
+//
+// This internal function handles sending data on endpoint zero.
+//
+// \param ulIndex is the index of the USB controller which is to be
+// initialized.
+//
+// \return None.
+//
+//*****************************************************************************
+static void
+USBDEP0StateTx(unsigned long ulIndex)
+{
+    unsigned long ulNumBytes;
+    unsigned char *pData;
+
+    ASSERT(ulIndex == 0);
+
+    //
+    // In the TX state on endpoint zero.
+    //
+    g_psUSBDevice[0].eEP0State = USB_STATE_TX;
+
+    //
+    // Set the number of bytes to send this iteration.
+    //
+    ulNumBytes = g_psUSBDevice[0].ulEP0DataRemain;
+
+    //
+    // Limit individual transfers to 64 bytes.
+    //
+    if(ulNumBytes > EP0_MAX_PACKET_SIZE)
+    {
+        ulNumBytes = EP0_MAX_PACKET_SIZE;
+    }
+
+    //
+    // Save the pointer so that it can be passed to the USBEndpointDataPut()
+    // function.
+    //
+    pData = (unsigned char *)g_psUSBDevice[0].pEP0Data;
+
+    //
+    // Advance the data pointer and counter to the next data to be sent.
+    //
+    g_psUSBDevice[0].ulEP0DataRemain -= ulNumBytes;
+    g_psUSBDevice[0].pEP0Data += ulNumBytes;
+
+    //
+    // Put the data in the correct FIFO.
+    //
+    MAP_USBEndpointDataPut(USB0_BASE, USB_EP_0, pData, ulNumBytes);
+
+    //
+    // If this is exactly 64 then don't set the last packet yet.
+    //
+    if(ulNumBytes == EP0_MAX_PACKET_SIZE)
+    {
+        //
+        // There is more data to send or exactly 64 bytes were sent, this
+        // means that there is either more data coming or a null packet needs
+        // to be sent to complete the transaction.
+        //
+        MAP_USBEndpointDataSend(USB0_BASE, USB_EP_0, USB_TRANS_IN);
+    }
+    else
+    {
+        //
+        // Now go to the status state and wait for the transmit to complete.
+        //
+        g_psUSBDevice[0].eEP0State = USB_STATE_STATUS;
+
+        //
+        // Send the last bit of data.
+        //
+        MAP_USBEndpointDataSend(USB0_BASE, USB_EP_0, USB_TRANS_IN_LAST);
+
+        //
+        // If there is a sent callback then call it.
+        //
+        if((g_psUSBDevice[0].psInfo->sCallbacks.pfnDataSent) &&
+           (g_psUSBDevice[0].ulOUTDataSize != 0))
+        {
+            //
+            // Call the custom handler.
+            //
+            g_psUSBDevice[0].psInfo->sCallbacks.pfnDataSent(
+                g_psUSBDevice[0].pvInstance, g_psUSBDevice[0].ulOUTDataSize);
+
+            //
+            // There is no longer any data pending to be sent.
+            //
+            g_psUSBDevice[0].ulOUTDataSize = 0;
+        }
+    }
+}
+
+//*****************************************************************************
+//
+// This internal function handles sending the configuration descriptor on
+// endpoint zero.
+//
+// \param ulIndex is the index of the USB controller which is to be used.
+//
+//
+// \return None.
+//
+//*****************************************************************************
+static void
+USBDEP0StateTxConfig(unsigned long ulIndex)
+{
+    unsigned long ulNumBytes;
+    unsigned long ulSecBytes;
+    unsigned long ulToSend;
+    unsigned char *pData;
+    tConfigDescriptor sConfDesc;
+    const tConfigHeader *psConfig;
+    const tConfigSection *psSection;
+
+    ASSERT(ulIndex == 0);
+
+    //
+    // In the TX state on endpoint zero.
+    //
+    g_psUSBDevice[0].eEP0State = USB_STATE_TX_CONFIG;
+
+    //
+    // Find the current configuration descriptor definition.
+    //
+    psConfig = g_psUSBDevice[0].psInfo->ppConfigDescriptors[
+               g_psUSBDevice[0].ucConfigIndex];
+
+    //
+    // Set the number of bytes to send this iteration.
+    //
+    ulNumBytes = g_psUSBDevice[0].ulEP0DataRemain;
+
+    //
+    // Limit individual transfers to 64 bytes.
+    //
+    if(ulNumBytes > EP0_MAX_PACKET_SIZE)
+    {
+        ulNumBytes = EP0_MAX_PACKET_SIZE;
+    }
+
+    //
+    // If this is the first call, we need to fix up the total length of the
+    // configuration descriptor.  This has already been determined and set in
+    // g_sUSBDeviceState.ulEP0DataRemain.
+    //
+    if((g_psUSBDevice[0].ucSectionOffset == 0) &&
+       (g_psUSBDevice[0].ucConfigSection == 0))
+    {
+        //
+        // Copy the USB configuration descriptor from the beginning of the
+        // first section of the current configuration.
+        //
+        sConfDesc = *(tConfigDescriptor *)g_psUSBDevice[0].pEP0Data;
+
+        //
+        // Update the total size.
+        //
+        sConfDesc.wTotalLength = (unsigned short)USBDCDConfigDescGetSize(
+                                                                   psConfig);
+
+        //
+        // Write the descriptor to the USB FIFO.
+        //
+        ulToSend = (ulNumBytes < sizeof(tConfigDescriptor)) ? ulNumBytes :
+                        sizeof(tConfigDescriptor);
+        MAP_USBEndpointDataPut(USB0_BASE, USB_EP_0, (unsigned char *)&sConfDesc,
+                           ulToSend);
+
+        //
+        // Did we reach the end of the first section?
+        //
+        if(psConfig->psSections[0]->ucSize == ulToSend)
+        {
+            //
+            // Update our tracking indices to point to the start of the next
+            // section.
+            //
+            g_psUSBDevice[0].ucSectionOffset = 0;
+            g_psUSBDevice[0].ucConfigSection = 1;
+        }
+        else
+        {
+            //
+            // Note that we have sent the first few bytes of the descriptor.
+            //
+            g_psUSBDevice[0].ucSectionOffset = (unsigned char)ulToSend;
+        }
+
+        //
+        // How many bytes do we have remaining to send on this iteration?
+        //
+        ulToSend = ulNumBytes - ulToSend;
+    }
+    else
+    {
+        //
+        // Set the number of bytes we still have to send on this call.
+        //
+        ulToSend = ulNumBytes;
+    }
+
+    //
+    // Add the relevant number of bytes to the USB FIFO
+    //
+    while(ulToSend)
+    {
+        //
+        // Get a pointer to the current configuration section.
+        //
+        psSection = psConfig->psSections[g_psUSBDevice[0].ucConfigSection];
+
+        //
+        // Calculate bytes are available in the current configuration section.
+        //
+        ulSecBytes = (unsigned long)(psSection->ucSize -
+                     g_psUSBDevice[0].ucSectionOffset);
+
+        //
+        // Save the pointer so that it can be passed to the
+        // USBEndpointDataPut() function.
+        //
+        pData = (unsigned char *)psSection->pucData +
+                g_psUSBDevice[0].ucSectionOffset;
+
+        //
+        // Are there more bytes in this section that we still have to send?
+        //
+        if(ulSecBytes > ulToSend)
+        {
+            //
+            // Yes - send only the remaining bytes in the transfer.
+            //
+            ulSecBytes = ulToSend;
+        }
+
+        //
+        // Put the data in the correct FIFO.
+        //
+        MAP_USBEndpointDataPut(USB0_BASE, USB_EP_0, pData, ulSecBytes);
+
+        //
+        // Fix up our pointers for the next iteration.
+        //
+        ulToSend -= ulSecBytes;
+        g_psUSBDevice[0].ucSectionOffset += (unsigned char)ulSecBytes;
+
+        //
+        // Have we reached the end of a section?
+        //
+        if(g_psUSBDevice[0].ucSectionOffset == psSection->ucSize)
+        {
+            //
+            // Yes - move to the next one.
+            //
+            g_psUSBDevice[0].ucConfigSection++;
+            g_psUSBDevice[0].ucSectionOffset = 0;
+        }
+    }
+
+    //
+    // Fix up the number of bytes remaining to be sent and the start pointer.
+    //
+    g_psUSBDevice[0].ulEP0DataRemain -= ulNumBytes;
+
+    //
+    // If we ran out of bytes in the configuration section, bail and just
+    // send out what we have.
+    //
+    if(psConfig->ucNumSections <= g_psUSBDevice[0].ucConfigSection)
+    {
+        g_psUSBDevice[0].ulEP0DataRemain = 0;
+    }
+
+    //
+    // If there is no more data don't keep looking or ucConfigSection might
+    // overrun the available space.
+    //
+    if(g_psUSBDevice[0].ulEP0DataRemain != 0)
+    {
+        pData =(unsigned char *)
+            psConfig->psSections[g_psUSBDevice[0].ucConfigSection]->pucData;
+        ulToSend = g_psUSBDevice[0].ucSectionOffset;
+        g_psUSBDevice[0].pEP0Data = (pData + ulToSend);
+    }
+
+    //
+    // If this is exactly 64 then don't set the last packet yet.
+    //
+    if(ulNumBytes == EP0_MAX_PACKET_SIZE)
+    {
+        //
+        // There is more data to send or exactly 64 bytes were sent, this
+        // means that there is either more data coming or a null packet needs
+        // to be sent to complete the transaction.
+        //
+        MAP_USBEndpointDataSend(USB0_BASE, USB_EP_0, USB_TRANS_IN);
+    }
+    else
+    {
+        //
+        // Send the last bit of data.
+        //
+        MAP_USBEndpointDataSend(USB0_BASE, USB_EP_0, USB_TRANS_IN_LAST);
+
+        //
+        // If there is a sent callback then call it.
+        //
+        if((g_psUSBDevice[0].psInfo->sCallbacks.pfnDataSent) &&
+           (g_psUSBDevice[0].ulOUTDataSize != 0))
+        {
+            //
+            // Call the custom handler.
+            //
+            g_psUSBDevice[0].psInfo->sCallbacks.pfnDataSent(
+                g_psUSBDevice[0].pvInstance, g_psUSBDevice[0].ulOUTDataSize);
+
+            //
+            // There is no longer any data pending to be sent.
+            //
+            g_psUSBDevice[0].ulOUTDataSize = 0;
+        }
+
+        //
+        // Now go to the status state and wait for the transmit to complete.
+        //
+        g_psUSBDevice[0].eEP0State = USB_STATE_STATUS;
+    }
+}
+
+//*****************************************************************************
+//
+// The internal USB device interrupt handler.
+//
+// \param ulIndex is the USB controller associated with this interrupt.
+// \param ulStatus is the current interrupt status as read via a call to
+// USBIntStatusControl().
+//
+// This function is called from either \e USB0DualModeIntHandler() or
+// \e USB0DeviceIntHandler() to process USB interrupts when in device mode.
+// This handler will branch the interrupt off to the appropriate application or
+// stack handlers depending on the current status of the USB controller.
+//
+// The two-tiered structure for the interrupt handler ensures that it is
+// possible to use the same handler code in both device and OTG modes and
+// means that host code can be excluded from applications that only require
+// support for USB device mode operation.
+//
+// \return None.
+//
+//*****************************************************************************
+void
+USBDeviceIntHandlerInternal(unsigned long ulIndex, unsigned long ulStatus)
+{
+    static unsigned long ulSOFDivide = 0;
+    tDeviceInfo *psInfo;
+    void *pvInstance;
+
+    //
+    // If device initialization has not been performed then just disconnect
+    // from the USB bus and return from the handler.
+    //
+    if(g_psUSBDevice[0].psInfo == 0)
+    {
+        MAP_USBDevDisconnect(USB0_BASE);
+        return;
+    }
+
+    psInfo = g_psUSBDevice[0].psInfo;
+    pvInstance = g_psUSBDevice[0].pvInstance;
+
+    //
+    // Received a reset from the host.
+    //
+    if(ulStatus & USB_INTCTRL_RESET)
+    {
+        USBDeviceEnumResetHandler(&g_psUSBDevice[0]);
+    }
+
+    //
+    // Suspend was signaled on the bus.
+    //
+    if(ulStatus & USB_INTCTRL_SUSPEND)
+    {
+        //
+        // Call the SuspendHandler() if it was specified.
+        //
+        if(psInfo->sCallbacks.pfnSuspendHandler)
+        {
+            psInfo->sCallbacks.pfnSuspendHandler(pvInstance);
+        }
+    }
+
+    //
+    // Resume was signaled on the bus.
+    //
+    if(ulStatus & USB_INTCTRL_RESUME)
+    {
+        //
+        // Call the ResumeHandler() if it was specified.
+        //
+        if(psInfo->sCallbacks.pfnResumeHandler)
+        {
+            psInfo->sCallbacks.pfnResumeHandler(pvInstance);
+        }
+    }
+
+    //
+    // USB device was disconnected.
+    //
+    if(ulStatus & USB_INTCTRL_DISCONNECT)
+    {
+        //
+        // Call the DisconnectHandler() if it was specified.
+        //
+        if(psInfo->sCallbacks.pfnDisconnectHandler)
+        {
+            psInfo->sCallbacks.pfnDisconnectHandler(pvInstance);
+        }
+    }
+
+    //
+    // Start of Frame was received.
+    //
+    if(ulStatus & USB_INTCTRL_SOF)
+    {
+        //
+        // Increment the global Start of Frame counter.
+        //
+        g_ulUSBSOFCount++;
+
+        //
+        // Increment our SOF divider.
+        //
+        ulSOFDivide++;
+
+        //
+        // Handle resume signaling if required.
+        //
+        USBDeviceResumeTickHandler(0);
+
+        //
+        // Have we counted enough SOFs to allow us to call the tick function?
+        //
+        if(ulSOFDivide == USB_SOF_TICK_DIVIDE)
+        {
+            //
+            // Yes - reset the divider and call the SOF tick handler.
+            //
+            ulSOFDivide = 0;
+            InternalUSBStartOfFrameTick(USB_SOF_TICK_DIVIDE);
+        }
+    }
+
+    //
+    // Get the controller interrupt status.
+    //
+    ulStatus = MAP_USBIntStatusEndpoint(USB0_BASE);
+
+    //
+    // Handle end point 0 interrupts.
+    //
+    if(ulStatus & USB_INTEP_0)
+    {
+        USBDeviceEnumHandler(&g_psUSBDevice[0]);
+    }
+
+    //
+    // Because there is no way to detect if a uDMA interrupt has occurred,
+    // check for an endpoint callback and call it if it is available.
+    //
+    if(psInfo->sCallbacks.pfnEndpointHandler)
+    {
+        psInfo->sCallbacks.pfnEndpointHandler(pvInstance, ulStatus);
+    }
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/src/platform/lm3s/usblib/device/usbdevice.h b/src/platform/lm3s/usblib/device/usbdevice.h
new file mode 100755
index 00000000..45e957ff
--- /dev/null
+++ b/src/platform/lm3s/usblib/device/usbdevice.h
@@ -0,0 +1,141 @@
+//*****************************************************************************
+//
+// usbdevice.h - types and definitions used during USB enumeration.
+//
+// Copyright (c) 2008-2011 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 7611 of the Stellaris USB Library.
+//
+//*****************************************************************************
+
+#ifndef __USBDEVICE_H__
+#define __USBDEVICE_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+//! \addtogroup device_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! The maximum number of independent interfaces that any single device
+//! implementation can support.  Independent interfaces means interface
+//! descriptors with different bInterfaceNumber values - several interface
+//! descriptors offering different alternative settings but the same interface
+//! number count as a single interface.
+//
+//*****************************************************************************
+#define USB_MAX_INTERFACES_PER_DEVICE 8
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// The default USB endpoint FIFO configuration structure.  This structure
+// contains definitions to set all USB FIFOs into single buffered mode with
+// no DMA use.  Each endpoint's FIFO is sized to hold the largest maximum
+// packet size for any interface alternate setting in the current config
+// descriptor.  A pointer to this structure may be passed in the psFIFOConfig
+// field of the tDeviceInfo structure passed to USBCDCInit if the application
+// does not require any special handling of the USB controller FIFO.
+//
+//*****************************************************************************
+extern const tFIFOConfig g_sUSBDefaultFIFOConfig;
+
+//*****************************************************************************
+//
+// Public APIs offered by the USB library device control driver.
+//
+//*****************************************************************************
+extern void USBDCDInit(unsigned long ulIndex, tDeviceInfo *psDevice);
+extern void USBDCDTerm(unsigned long ulIndex);
+extern void USBDCDStallEP0(unsigned long ulIndex);
+extern void USBDCDRequestDataEP0(unsigned long ulIndex, unsigned char *pucData,
+                                 unsigned long ulSize);
+extern void USBDCDSendDataEP0(unsigned long ulIndex, unsigned char *pucData,
+                              unsigned long ulSize);
+extern void USBDCDSetDefaultConfiguration(unsigned long ulIndex,
+                                          unsigned long ulDefaultConfig);
+extern unsigned long USBDCDConfigDescGetSize(const tConfigHeader *psConfig);
+extern unsigned long USBDCDConfigDescGetNum(const tConfigHeader *psConfig,
+                                            unsigned long ulType);
+extern tDescriptorHeader *USBDCDConfigDescGet(const tConfigHeader *psConfig,
+                                              unsigned long ulType,
+                                              unsigned long ulIndex,
+                                              unsigned long *pulSection);
+extern unsigned long
+       USBDCDConfigGetNumAlternateInterfaces(const tConfigHeader *psConfig,
+                                             unsigned char ucInterfaceNumber);
+extern tInterfaceDescriptor *
+       USBDCDConfigGetInterface(const tConfigHeader *psConfig,
+                                unsigned long ulIndex, unsigned long ulAltCfg,
+                                unsigned long *pulSection);
+extern tEndpointDescriptor *
+       USBDCDConfigGetInterfaceEndpoint(const tConfigHeader *psConfig,
+                                        unsigned long ulInterfaceNumber,
+                                        unsigned long ulAltCfg,
+                                        unsigned long ulIndex);
+extern void USBDCDPowerStatusSet(unsigned long ulIndex, unsigned char ucPower);
+extern tBoolean USBDCDRemoteWakeupRequest(unsigned long ulIndex);
+
+//*****************************************************************************
+//
+// Early releases of the USB library had the following function named
+// incorrectly.  This macro ensures that any code which used the previous name
+// will still operate as expected.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+#define USBCDCConfigGetInterfaceEndpoint(a, b, c, d)                          \
+            USBDCDConfigGetInterfaceEndpoint((a), (b), (c), (d))
+#endif
+
+//*****************************************************************************
+//
+// Device mode interrupt handler for controller index 0.
+//
+//*****************************************************************************
+extern void USB0DeviceIntHandler(void);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __USBENUM_H__
diff --git a/src/platform/lm3s/usblib/device/usbdevicepriv.h b/src/platform/lm3s/usblib/device/usbdevicepriv.h
new file mode 100755
index 00000000..ac7caa3d
--- /dev/null
+++ b/src/platform/lm3s/usblib/device/usbdevicepriv.h
@@ -0,0 +1,66 @@
+//*****************************************************************************
+//
+// usbdevicepriv.h - Private header file used to share internal variables and
+//                   function prototypes between the various device-related
+//                   modules in the USB library.  This header MUST NOT be
+//                   used by application code.
+//
+// Copyright (c) 2008-2011 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 7611 of the Stellaris USB Library.
+//
+//*****************************************************************************
+
+#ifndef __USBDEVICEPRIV_H__
+#define __USBDEVICEPRIV_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Device enumeration functions provided by device/usbenum.c and called from
+// the interrupt handler in device/usbhandler.c
+//
+//*****************************************************************************
+extern tBoolean USBDeviceConfig(unsigned long ulIndex,
+                                const tConfigHeader *psConfig,
+                                const tFIFOConfig *psFIFOConfig);
+extern tBoolean USBDeviceConfigAlternate(unsigned long ulIndex,
+                                         const tConfigHeader *psConfig,
+                                         unsigned char ucInterfaceNum,
+                                         unsigned char ucAlternateSetting);
+extern void USBDeviceResumeTickHandler(unsigned long ulIndex);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __USBDEVICEPRIV_H__
diff --git a/src/platform/lm3s/usblib/device/usbdhandler.c b/src/platform/lm3s/usblib/device/usbdhandler.c
new file mode 100755
index 00000000..bf44f732
--- /dev/null
+++ b/src/platform/lm3s/usblib/device/usbdhandler.c
@@ -0,0 +1,82 @@
+//*****************************************************************************
+//
+// usbhandler.c - General USB handling routines.
+//
+// Copyright (c) 2007-2011 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 7611 of the Stellaris USB Library.
+//
+//*****************************************************************************
+
+#include "inc/hw_memmap.h"
+#include "inc/hw_types.h"
+#include "driverlib/rom.h"
+#include "driverlib/rom_map.h"
+#include "driverlib/usb.h"
+#include "usblib/usblib.h"
+#include "usblib/device/usbdevice.h"
+#include "usblib/device/usbdevicepriv.h"
+#include "usblib/usblibpriv.h"
+
+//*****************************************************************************
+//
+//! \addtogroup device_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! The USB device interrupt handler.
+//!
+//! This the main USB interrupt handler entry point for use in USB device
+//! applications.  This top-level handler will branch the interrupt off to the
+//! appropriate application or stack handlers depending on the current status
+//! of the USB controller.
+//!
+//! Applications which operate purely as USB devices (rather than dual mode
+//! applications which can operate in either device or host mode at different
+//! times) must ensure that a pointer to this function is installed in the
+//! interrupt vector table entry for the USB0 interrupt.  For dual mode
+//! operation, the vector should be set to point to \e USB0DualModeIntHandler()
+//! instead.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USB0DeviceIntHandler(void)
+{
+    unsigned long ulStatus;
+
+    //
+    // Get the controller interrupt status.
+    //
+    ulStatus = MAP_USBIntStatusControl(USB0_BASE);
+
+    //
+    // Call the internal handler.
+    //
+    USBDeviceIntHandlerInternal(0, ulStatus);
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/src/platform/lm3s/usblib/device/usbdhid.c b/src/platform/lm3s/usblib/device/usbdhid.c
new file mode 100755
index 00000000..263dab99
--- /dev/null
+++ b/src/platform/lm3s/usblib/device/usbdhid.c
@@ -0,0 +1,2581 @@
+//*****************************************************************************
+//
+// usbdhid.c - USB HID device class driver.
+//
+// Copyright (c) 2008-2011 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 7611 of the Stellaris USB Library.
+//
+//*****************************************************************************
+
+#include "inc/hw_memmap.h"
+#include "inc/hw_types.h"
+#include "driverlib/debug.h"
+#include "driverlib/usb.h"
+#include "driverlib/rom.h"
+#include "driverlib/rom_map.h"
+#include "usblib/usblib.h"
+#include "usblib/usbhid.h"
+#include "usblib/device/usbdevice.h"
+#include "usblib/device/usbdhid.h"
+#include "usblib/usblibpriv.h"
+
+//*****************************************************************************
+//
+//! \addtogroup hid_device_class_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// The subset of endpoint status flags that we consider to be reception
+// errors.  These are passed to the client via USB_EVENT_ERROR if seen.
+//
+//*****************************************************************************
+#define USB_RX_ERROR_FLAGS      (USBERR_DEV_RX_DATA_ERROR |                   \
+                                 USBERR_DEV_RX_OVERRUN |                      \
+                                 USBERR_DEV_RX_FIFO_FULL)
+
+//*****************************************************************************
+//
+// Marker used to indicate that a given HID descriptor cannot be found in the
+// client-supplied list.
+//
+//*****************************************************************************
+#define HID_NOT_FOUND           0xFFFFFFFF
+
+//*****************************************************************************
+//
+// Flags that may appear in usDeferredOpFlags to indicate some operation that
+// has been requested but could not be processed at the time it was received.
+// Each deferred operation is defined as the bit number that should be set in
+// tHIDInstance->usDeferredOpFlags to indicate that the operation is pending.
+//
+//*****************************************************************************
+#define HID_DO_PACKET_RX        5
+#define HID_DO_SEND_IDLE_REPORT 6
+
+//*****************************************************************************
+//
+// Macros to convert between USB controller base address and an index.  These
+// are currently trivial but are included to allow for the possibility of
+// supporting more than one controller in the future.
+//
+//*****************************************************************************
+#define USB_BASE_TO_INDEX(BaseAddr) (0)
+#define USB_INDEX_TO_BASE(Index)    (USB0_BASE)
+
+//*****************************************************************************
+//
+// Endpoints to use for each of the required endpoints in the driver.
+//
+//*****************************************************************************
+#define INT_IN_ENDPOINT         USB_EP_3
+#define INT_OUT_ENDPOINT        USB_EP_3
+
+//*****************************************************************************
+//
+// Maximum packet size for the interrupt endpoints used for report transmission
+// and reception and the associated FIFO sizes to set aside for each endpoint.
+//
+//*****************************************************************************
+#define INT_IN_EP_FIFO_SIZE     USB_FIFO_SZ_64
+#define INT_OUT_EP_FIFO_SIZE    USB_FIFO_SZ_64
+
+#define INT_IN_EP_MAX_SIZE      USB_FIFO_SZ_TO_BYTES(INT_IN_EP_FIFO_SIZE)
+#define INT_OUT_EP_MAX_SIZE     USB_FIFO_SZ_TO_BYTES(INT_IN_EP_FIFO_SIZE)
+
+//*****************************************************************************
+//
+// Device Descriptor.  This is stored in RAM to allow several fields to be
+// changed at runtime based on the client's requirements.
+//
+//*****************************************************************************
+unsigned char g_pHIDDeviceDescriptor[] =
+{
+    18,                         // Size of this structure.
+    USB_DTYPE_DEVICE,           // Type of this structure.
+    USBShort(0x110),            // USB version 1.1 (if we say 2.0, hosts assume
+                                // high-speed - see USB 2.0 spec 9.2.6.6)
+    USB_CLASS_DEVICE,           // USB Device Class
+    0,                          // USB Device Sub-class
+    USB_HID_PROTOCOL_NONE,      // USB Device protocol
+    64,                         // Maximum packet size for default pipe.
+    USBShort(0),                // Vendor ID (VID).
+    USBShort(0),                // Product ID (PID).
+    USBShort(0x100),            // Device Version BCD.
+    1,                          // Manufacturer string identifier.
+    2,                          // Product string identifier.
+    3,                          // Product serial number.
+    1                           // Number of configurations.
+};
+
+//*****************************************************************************
+//
+// HID device configuration descriptor.
+//
+// It is vital that the configuration descriptor bConfigurationValue field
+// (byte 6) is 1 for the first configuration and increments by 1 for each
+// additional configuration defined here.  This relationship is assumed in the
+// device stack for simplicity even though the USB 2.0 specification imposes
+// no such restriction on the bConfigurationValue values.
+//
+// Note that this structure is deliberately located in RAM since we need to
+// be able to patch some values in it based on client requirements.
+//
+//*****************************************************************************
+unsigned char g_pHIDDescriptor[] =
+{
+    //
+    // Configuration descriptor header.
+    //
+    9,                          // Size of the configuration descriptor.
+    USB_DTYPE_CONFIGURATION,    // Type of this descriptor.
+    USBShort(34),               // The total size of this full structure.
+    1,                          // The number of interfaces in this
+                                // configuration.
+    1,                          // The unique value for this configuration.
+    5,                          // The string identifier that describes this
+                                // configuration.
+    USB_CONF_ATTR_SELF_PWR,     // Bus Powered, Self Powered, remote wake up.
+    250,                        // The maximum power in 2mA increments.
+};
+
+//*****************************************************************************
+//
+// The remainder of the configuration descriptor is stored in flash since we
+// don't need to modify anything in it at runtime.
+//
+//*****************************************************************************
+unsigned char g_pHIDInterface[] =
+{
+    //
+    // HID Device Class Interface Descriptor.
+    //
+    9,                          // Size of the interface descriptor.
+    USB_DTYPE_INTERFACE,        // Type of this descriptor.
+    0,                          // The index for this interface.
+    0,                          // The alternate setting for this interface.
+    2,                          // The number of endpoints used by this
+                                // interface.
+    USB_CLASS_HID,              // The interface class
+    0,                          // The interface sub-class.
+    0,                          // The interface protocol for the sub-class
+                                // specified above.
+    4,                          // The string index for this interface.
+};
+
+const unsigned char g_pHIDInEndpoint[] =
+{
+    //
+    // Interrupt IN endpoint descriptor
+    //
+    7,                          // The size of the endpoint descriptor.
+    USB_DTYPE_ENDPOINT,         // Descriptor type is an endpoint.
+    USB_EP_DESC_IN | USB_EP_TO_INDEX(INT_IN_ENDPOINT),
+    USB_EP_ATTR_INT,            // Endpoint is an interrupt endpoint.
+    USBShort(INT_IN_EP_MAX_SIZE), // The maximum packet size.
+    16,                         // The polling interval for this endpoint.
+};
+
+const unsigned char g_pHIDOutEndpoint[] =
+{
+    //
+    // Interrupt OUT endpoint descriptor
+    //
+    7,                          // The size of the endpoint descriptor.
+    USB_DTYPE_ENDPOINT,         // Descriptor type is an endpoint.
+    USB_EP_DESC_OUT | USB_EP_TO_INDEX(INT_OUT_ENDPOINT),
+    USB_EP_ATTR_INT,            // Endpoint is an interrupt endpoint.
+    USBShort(INT_OUT_EP_MAX_SIZE), // The maximum packet size.
+    16,                         // The polling interval for this endpoint.
+};
+
+//*****************************************************************************
+//
+// The HID configuration descriptor is defined as four or five sections
+// depending upon the client's configuration choice.  These sections are:
+//
+// 1.  The 9 byte configuration descriptor (RAM).
+// 2.  The interface descriptor (RAM).
+// 3.  The HID report and physical descriptors (provided by the client)
+//     (FLASH).
+// 4.  The mandatory interrupt IN endpoint descriptor (FLASH).
+// 5.  The optional interrupt OUT endpoint descriptor (FLASH).
+//
+//*****************************************************************************
+const tConfigSection g_sHIDConfigSection =
+{
+    sizeof(g_pHIDDescriptor),
+    g_pHIDDescriptor
+};
+
+const tConfigSection g_sHIDInterfaceSection =
+{
+    sizeof(g_pHIDInterface),
+    g_pHIDInterface
+};
+
+const tConfigSection g_sHIDInEndpointSection =
+{
+    sizeof(g_pHIDInEndpoint),
+    g_pHIDInEndpoint
+};
+
+const tConfigSection g_sHIDOutEndpointSection =
+{
+    sizeof(g_pHIDOutEndpoint),
+    g_pHIDOutEndpoint
+};
+
+//*****************************************************************************
+//
+// Place holder for the user's HID descriptor block.
+//
+//*****************************************************************************
+tConfigSection g_sHIDDescriptorSection =
+{
+   0, (void *)0
+};
+
+//*****************************************************************************
+//
+// This array lists all the sections that must be concatenated to make a
+// single, complete HID configuration descriptor.
+//
+//*****************************************************************************
+const tConfigSection *g_psHIDSections[] =
+{
+    &g_sHIDConfigSection,
+    &g_sHIDInterfaceSection,
+    &g_sHIDDescriptorSection,
+    &g_sHIDInEndpointSection,
+    &g_sHIDOutEndpointSection
+};
+
+#define NUM_HID_SECTIONS (sizeof(g_psHIDSections) /                         \
+                          sizeof(tConfigSection *))
+
+//*****************************************************************************
+//
+// The header for the single configuration we support.  This is the root of
+// the data structure that defines all the bits and pieces that are pulled
+// together to generate the configuration descriptor.  Note that this must be
+// in RAM since we need to include or exclude the final section based on
+// client supplied initialization parameters.
+//
+//*****************************************************************************
+tConfigHeader g_sHIDConfigHeader =
+{
+    NUM_HID_SECTIONS,
+    g_psHIDSections
+};
+
+//*****************************************************************************
+//
+// Configuration Descriptor.
+//
+//*****************************************************************************
+const tConfigHeader * const g_pHIDConfigDescriptors[] =
+{
+    &g_sHIDConfigHeader
+};
+
+//*****************************************************************************
+//
+// Forward references for device handler callbacks
+//
+//*****************************************************************************
+static void HandleGetDescriptor(void *pvInstance, tUSBRequest *pUSBRequest);
+static void HandleRequest(void *pvInstance, tUSBRequest *pUSBRequest);
+static void HandleConfigChange(void *pvInstance, unsigned long ulInfo);
+static void HandleEP0DataReceived(void *pvInstance, unsigned long ulInfo);
+static void HandleEP0DataSent(void *pvInstance, unsigned long ulInfo);
+static void HandleReset(void *pvInstance);
+static void HandleSuspend(void *pvInstance);
+static void HandleResume(void *pvInstance);
+static void HandleDisconnect(void *pvInstance);
+static void HandleEndpoints(void *pvInstance, unsigned long ulStatus);
+static void HandleDevice(void *pvInstance, unsigned long ulRequest,
+                         void *pvRequestData);
+
+//*****************************************************************************
+//
+// The device information structure for the USB HID devices.
+//
+//*****************************************************************************
+tDeviceInfo g_sHIDDeviceInfo =
+{
+    //
+    // Device event handler callbacks.
+    //
+    {
+        HandleGetDescriptor,   // GetDescriptor
+        HandleRequest,         // RequestHandler
+        0,                     // InterfaceChange
+        HandleConfigChange,    // ConfigChange
+        HandleEP0DataReceived, // DataReceived
+        HandleEP0DataSent,     // DataSentCallback
+        HandleReset,           // ResetHandler
+        HandleSuspend,         // SuspendHandler
+        HandleResume,          // ResumeHandler
+        HandleDisconnect,      // DisconnectHandler
+        HandleEndpoints,       // EndpointHandler
+        HandleDevice           // Device handler.
+    },
+    g_pHIDDeviceDescriptor,
+    g_pHIDConfigDescriptors,
+    0,                         // Will be completed during USBDHIDInit().
+    0,                         // Will be completed during USBDHIDInit().
+    &g_sUSBDefaultFIFOConfig
+};
+
+//*****************************************************************************
+//
+// Set or clear deferred operation flags in an "atomic" manner.
+//
+// \param pusDeferredOp points to the flags variable which is to be modified.
+// \param usBit indicates which bit number is to be set or cleared.
+// \param bSet indicates the state that the flag must be set to.  If \b true,
+// the flag is set, if \b false, the flag is cleared.
+//
+// This function safely sets or clears a bit in a flag variable.  The operation
+// makes use of bitbanding to ensure that the operation is atomic (no read-
+// modify-write is required).
+//
+// \return None.
+//
+//*****************************************************************************
+static void
+SetDeferredOpFlag(volatile unsigned short *pusDeferredOp,
+                  unsigned short usBit, tBoolean bSet)
+{
+    //
+    // Set the flag bit to 1 or 0 using a bitband access.
+    //
+    HWREGBITH(pusDeferredOp, usBit) = bSet ? 1 : 0;
+}
+
+//*****************************************************************************
+//
+// This function is called to clear the counter used to keep track of the time
+// elapsed since a given report was last sent.
+//
+// \param psDevice points to the HID device structure whose report timer is to
+// be cleared.
+// \param ucReportID is the first byte of the report to be sent.  If this
+// device offers more than one input report, this value is used to find the
+// relevant report timer structure in the psDevice structure.
+//
+// \return None.
+//
+//*****************************************************************************
+static void
+ClearReportTimer(const tUSBDHIDDevice *psDevice, unsigned char ucReportID)
+{
+    unsigned long ulLoop;
+
+    if(psDevice->ucNumInputReports > 1)
+    {
+        //
+        // We have more than 1 input report so the report must begin with a
+        // byte containing the report ID.  Scan the table we were provided
+        // when the device was initialized to find the entry for this report.
+        //
+        for(ulLoop = 0; ulLoop < psDevice->ucNumInputReports; ulLoop++)
+        {
+            if(psDevice->psReportIdle[ulLoop].ucReportID == ucReportID)
+            {
+                break;
+            }
+        }
+    }
+    else
+    {
+        ulLoop = 0;
+    }
+
+    //
+    // If we drop out of the loop with an index less than ucNumInputReports,
+    // we found the relevant report so clear its timer.
+    //
+    if(ulLoop < psDevice->ucNumInputReports)
+    {
+        psDevice->psReportIdle[ulLoop].ulTimeSinceReportmS = 0;
+    }
+}
+
+//*****************************************************************************
+//
+// This function is called to clear the idle period timers for each input
+// report supported by the device.
+//
+// \param psDevice points to the HID device structure whose timers are to be
+// cleared.
+// \param ulTimemS is the elapsed time in milliseconds since the last call
+// to this function.
+//
+// \return None.
+//
+//*****************************************************************************
+static void
+ClearIdleTimers(const tUSBDHIDDevice *psDevice)
+{
+    unsigned long ulLoop;
+
+    //
+    // Clear the "time till next report" counters for each input report.
+    //
+    for(ulLoop = 0; ulLoop < psDevice->ucNumInputReports; ulLoop++)
+    {
+        psDevice->psReportIdle[ulLoop].usTimeTillNextmS =
+            psDevice->psReportIdle[ulLoop].ucDuration4mS * 4;
+    }
+}
+
+//*****************************************************************************
+//
+// This function is called periodically to allow us to process the report idle
+// timers.
+//
+// \param psDevice points to the HID device structure whose timers are to be
+// updated.
+// \param ulElapsedmS indicates the number of milliseconds that have elapsed
+// since the last call to this function.
+//
+// \return None.
+//
+//*****************************************************************************
+static void
+ProcessIdleTimers(const tUSBDHIDDevice *psDevice, unsigned long ulElapsedmS)
+{
+    unsigned long ulLoop;
+    unsigned long ulSizeReport;
+    void *pvReport;
+    tHIDInstance *psInst;
+    tBoolean bDeferred;
+
+    //
+    // Get our instance data pointer
+    //
+    psInst = ((tUSBDHIDDevice *)psDevice)->psPrivateHIDData;
+
+    //
+    // We have not had to defer any report transmissions yet.
+    //
+    bDeferred = false;
+
+    //
+    // Look at each of the input report idle timers in turn.
+    //
+    for(ulLoop = 0; ulLoop < psDevice->ucNumInputReports; ulLoop++)
+    {
+        //
+        // Update the time since the last report was sent.
+        //
+        psDevice->psReportIdle[ulLoop].ulTimeSinceReportmS += ulElapsedmS;
+
+        //
+        // Is this timer running?
+        //
+        if(psDevice->psReportIdle[ulLoop].ucDuration4mS)
+        {
+            //
+            // Yes - is it about to expire?
+            //
+            if(psDevice->psReportIdle[ulLoop].usTimeTillNextmS <= ulElapsedmS)
+            {
+                //
+                // The timer is about to expire.  Can we send a report right
+                // now?
+                //
+                if((psInst->eHIDTxState == HID_STATE_IDLE) &&
+                   (psInst->bSendInProgress == false))
+                {
+                    //
+                    // We can send a report so send a message to the
+                    // application to retrieve its latest report for
+                    // transmission to the host.
+                    //
+                    ulSizeReport = psDevice->pfnRxCallback(
+                               psDevice->pvRxCBData,
+                               USBD_HID_EVENT_IDLE_TIMEOUT,
+                               psDevice->psReportIdle[ulLoop].ucReportID,
+                               &pvReport);
+
+                    //
+                    // Schedule the report for transmission.
+                    //
+                    USBDHIDReportWrite((void *)psDevice, pvReport,
+                                       ulSizeReport, true);
+
+                    //
+                    // Reload the timer for the next period.
+                    //
+                    psDevice->psReportIdle[ulLoop].usTimeTillNextmS =
+                        psDevice->psReportIdle[ulLoop].ucDuration4mS * 4;
+                }
+                else
+                {
+                    //
+                    // We can't send the report straight away so flag it for
+                    // transmission as soon as the previous transmission ends.
+                    //
+                    psDevice->psReportIdle[ulLoop].usTimeTillNextmS = 0;
+                    bDeferred = true;
+                }
+            }
+            else
+            {
+                //
+                // The timer is not about to expire.  Update the time till the
+                // next report transmission.
+                //
+                psDevice->psReportIdle[ulLoop].usTimeTillNextmS -= ulElapsedmS;
+            }
+        }
+    }
+
+    //
+    // If we had to defer transmission of any report, remember this so that we
+    // will process it as soon as possible.
+    //
+    SetDeferredOpFlag(&psInst->usDeferredOpFlags,
+                      HID_DO_SEND_IDLE_REPORT, bDeferred);
+}
+
+static void
+SetIdleTimeout(const tUSBDHIDDevice *psDevice, unsigned char ucReportID,
+               unsigned char ucTimeout4mS)
+{
+    unsigned long ulLoop;
+    tBoolean bReportNeeded;
+    tHIDReportIdle *psIdle;
+
+    //
+    // Remember that we have not found any report that needs to be sent
+    // immediately.
+    //
+    bReportNeeded = false;
+
+    //
+    // Search through all the input reports looking for ones that fit the
+    // requirements.
+    //
+    for(ulLoop = 0; ulLoop < psDevice->ucNumInputReports; ulLoop++)
+    {
+        psIdle = &psDevice->psReportIdle[ulLoop];
+
+        //
+        // If the report ID passed matches the report ID in the idle timer
+        // control structure or we were passed a report ID of zero, which
+        // indicates that all timers are to be set...
+        //
+        if(!ucReportID || (ucReportID == psIdle->ucReportID))
+        {
+            //
+            // Save the new duration for the idle timer.
+            //
+            psIdle->ucDuration4mS = ucTimeout4mS;
+
+            //
+            // Are we enabling the idle timer?  If so, fix up the time until it
+            // needs to fire.
+            //
+            if(ucTimeout4mS)
+            {
+                //
+                // Determine what the timeout is for this report given the time
+                // since the last report of this type was sent.
+                //
+                if(psIdle->ulTimeSinceReportmS >=
+                   ((unsigned long)ucTimeout4mS * 4))
+                {
+                    psIdle->usTimeTillNextmS = 0;
+                    bReportNeeded = true;
+                }
+                else
+                {
+                    psIdle->usTimeTillNextmS =
+                                        (((unsigned short)ucTimeout4mS * 4) -
+                                         psIdle->ulTimeSinceReportmS);
+                }
+            }
+        }
+    }
+
+    //
+    // If we get to here and bReportNeeded is true, this means we need to
+    // send back at least one of the input reports as soon as possible.  Try
+    // to do this immediately.
+    //
+    if(bReportNeeded)
+    {
+        ProcessIdleTimers(psDevice, 0);
+    }
+}
+
+//*****************************************************************************
+//
+// Find the idle timeout for a given HID input report.
+//
+// \param psDevice points to the HID device whose report idle timeout is to be
+// found.
+// \param ucReportID identifies the report whose timeout is requested.  If 0,
+// the timeout for the first report is returns, regardless of its ID (or
+// whether it has one).
+//
+// This function returns the current idle timeout for a given HID input report.
+// The value returned is expressed in terms of 4mS intervals.  Convert to
+// milliseconds by multiplying by 4.  If the return value is 0, this indicates
+// that an infinite timeout is currently set and the device will not send the
+// report unless a state change occurs.
+//
+// \return Returns the current idle timeout for the given report.
+//
+//*****************************************************************************
+static unsigned long
+GetIdleTimeout(const tUSBDHIDDevice *psDevice, unsigned char ucReportID)
+{
+    unsigned long ulLoop;
+    tHIDReportIdle *psIdle;
+
+    //
+    // Search through all the input reports looking for ones that fit the
+    // requirements.
+    //
+    for(ulLoop = 0; ulLoop < psDevice->ucNumInputReports; ulLoop++)
+    {
+        psIdle = &psDevice->psReportIdle[ulLoop];
+
+        //
+        // If the report ID passed matches the report ID in the idle timer
+        // control structure or we were passed a report ID of zero, which
+        // indicates that all timers are to be set...
+        //
+        if(!ucReportID || (ucReportID == psIdle->ucReportID))
+        {
+            //
+            // We found a report matching the required ID or we were not passed
+            // an ID and we are looking at the first report information.
+            //
+            return((unsigned long)psIdle->ucDuration4mS);
+        }
+    }
+
+    //
+    // If we drop out, the report couldn't be found so we need to indicate
+    // an error.
+    //
+    return(HID_NOT_FOUND);
+}
+
+//*****************************************************************************
+//
+// Find the n-th HID class descriptor of a given type in the client-provided
+// descriptor table.
+//
+// \param psDevice points to the HID device which is to be searched for the
+// required class descriptor.
+// \param ucType is the type of class descriptor being requested.  This will
+// be either USB_HID_DTYPE_REPORT or USB_HID_DTYPE_PHYSICAL.
+// \param ulIndex is the zero-based index of the descriptor that is being
+// requested.
+//
+// This function parses the supplied HID descriptor to find the index into the
+// sClassDescriptor array that corresponds to the requested descriptor.  If
+// a descriptor with the requested index does not exist, HID_NOT_FOUND will be
+// returned unless the request is for a physical descriptor and at least one
+// such descriptor exists.  In this case, the index returned will be for the
+// last physical descriptor (as required by the HID spec 7.1.1).
+//
+// \return Returns the index of the descriptor within the sClassDescriptor
+// of the tHIDDevice structure if found or HID_NOT_FOUND otherwise.
+//
+//*****************************************************************************
+static unsigned long
+FindHIDDescriptor(const tUSBDHIDDevice *psDevice, unsigned char ucType,
+                  unsigned long ulIndex, unsigned long *pulLen)
+{
+    tBoolean bFoundType;
+    unsigned long ulLoop;
+    unsigned long ulCount;
+    unsigned long ulLastFound;
+    const tHIDClassDescriptorInfo *psDesc;
+
+    //
+    // Remember that we have not found any descriptor with a matching type yet.
+    //
+    bFoundType = false;
+    ulCount = 0;
+    ulLastFound = 0;
+
+    //
+    // Walk through all the class descriptors looking for the one which
+    // matches the requested index and type.
+    //
+    for(ulLoop = 0; ulLoop < psDevice->psHIDDescriptor->bNumDescriptors;
+        ulLoop++)
+    {
+        psDesc = &(psDevice->psHIDDescriptor->sClassDescriptor[ulLoop]);
+        if(psDesc->bDescriptorType == ucType)
+        {
+            //
+            // We found a descriptor of the correct type.  Is this the
+            // correct index?
+            //
+            bFoundType = true;
+
+            //
+            // Is this the descriptor we are looking for?
+            //
+            if(ulCount == ulIndex)
+            {
+                //
+                // Yes - we found it so return the index and size to the
+                // caller.
+                //
+                *pulLen = (unsigned long)psDesc->wDescriptorLength;
+                return(ulLoop);
+            }
+            else
+            {
+                //
+                // Update our count and keep looking.  Remember where we were
+                // when we found this descriptor in case we need to return the
+                // last physical descriptor.
+                //
+                ulCount++;
+                ulLastFound = ulLoop;
+            }
+        }
+    }
+
+    //
+    // If we drop out, we didn't find the requested descriptor.  Now handle
+    // the special case of a physical descriptor - if we found any physical
+    // descriptors, return the last one.
+    //
+    if((ucType == USB_HID_DTYPE_PHYSICAL) && bFoundType)
+    {
+        //
+        // Get the length of the last descriptor we found.
+        //
+        psDesc = &(psDevice->psHIDDescriptor->sClassDescriptor[ulLastFound]);
+        *pulLen = (unsigned long)psDesc->wDescriptorLength;
+
+        //
+        // Return the index to the caller.
+        //
+        return(ulLastFound);
+    }
+    else
+    {
+        //
+        // We couldn't find the descriptor so return an appropriate error.
+        //
+        return(HID_NOT_FOUND);
+    }
+}
+
+//*****************************************************************************
+//
+// Schedule transmission of the next packet forming part of an input report.
+//
+// \param psInst points to the device instance whose input report is to be
+// sent.
+//
+// This function is called to transmit the next packet of an input report
+// passed to the driver via a call to USBDHIDReportWrite.  If any data remains
+// to be sent, a USB packet is written to the FIFO and scheduled for
+// transmission to the host.  The function ensures that reports are sent as
+// a sequence of full packets followed by either a single short packet or a
+// packet with no data to indicate the end of the transaction.
+//
+//*****************************************************************************
+static long
+ScheduleReportTransmission(tHIDInstance *psInst)
+{
+    unsigned long ulNumBytes;
+    unsigned char *pucData;
+    long lRetcode;
+
+    //
+    // Set the number of bytes to send this iteration.
+    //
+    ulNumBytes = (unsigned long)(psInst->usInReportSize -
+                                 psInst->usInReportIndex);
+
+    //
+    // Limit individual transfers to the maximum packet size for the endpoint.
+    //
+    if(ulNumBytes > INT_IN_EP_MAX_SIZE)
+    {
+        ulNumBytes = INT_IN_EP_MAX_SIZE;
+    }
+
+    //
+    // Where are we sending this data from?
+    //
+    pucData = psInst->pucInReportData + psInst->usInReportIndex;
+
+    //
+    // Put the data in the correct FIFO.
+    //
+    lRetcode = MAP_USBEndpointDataPut(psInst->ulUSBBase, psInst->ucINEndpoint,
+                                      pucData, ulNumBytes);
+
+    if(lRetcode != -1)
+    {
+        //
+        // Update the count and index ready for the next time round.
+        //
+        psInst->usInReportIndex += ulNumBytes;
+
+        //
+        // Send out the current data.
+        //
+        lRetcode = MAP_USBEndpointDataSend(psInst->ulUSBBase,
+                                           psInst->ucINEndpoint,
+                                           USB_TRANS_IN);
+    }
+
+    //
+    // Tell the caller how we got on.
+    //
+    return(lRetcode);
+}
+
+//*****************************************************************************
+//
+// Receives notifications related to data received from the host.
+//
+// \param psDevice is the device instance whose endpoint is to be processed.
+// \param ulStatus is the USB interrupt status that caused this function to
+// be called.
+//
+// This function is called from HandleEndpoints for all interrupts signaling
+// the arrival of data on the interrupt OUT endpoint (in other words, whenever
+// the host has sent us a packet of data).  We inform the client that a packet
+// is available and, on return, check to see if the packet has been read.  If
+// not, we schedule another notification to the client for a later time.
+//
+// \return Returns \b true on success or \b false on failure.
+//
+//*****************************************************************************
+static tBoolean
+ProcessDataFromHost(const tUSBDHIDDevice *psDevice, unsigned long ulStatus)
+{
+    unsigned long ulEPStatus;
+    unsigned long ulSize;
+    tHIDInstance *psInst;
+
+    //
+    // Get a pointer to our instance data.
+    //
+    psInst = psDevice->psPrivateHIDData;
+
+    //
+    // Get the endpoint status to see why we were called.
+    //
+    ulEPStatus = MAP_USBEndpointStatus(USB0_BASE, psInst->ucOUTEndpoint);
+
+    //
+    // Clear the status bits.
+    //
+    MAP_USBDevEndpointStatusClear(USB0_BASE, psInst->ucOUTEndpoint, ulEPStatus);
+
+    //
+    // Has a packet been received?
+    //
+    if(ulEPStatus & USB_DEV_RX_PKT_RDY)
+    {
+        //
+        // Set the flag we use to indicate that a packet read is pending.  This
+        // will be cleared if the packet is read.  If the client doesn't read
+        // the packet in the context of the USB_EVENT_RX_AVAILABLE callback,
+        // the event will be signaled later during tick processing.
+        //
+        SetDeferredOpFlag(&psInst->usDeferredOpFlags, HID_DO_PACKET_RX, true);
+
+        //
+        // How big is the packet we've just been sent?
+        //
+        ulSize = MAP_USBEndpointDataAvail(psInst->ulUSBBase,
+                                          psInst->ucOUTEndpoint);
+
+        //
+        // The receive channel is not blocked so let the caller know
+        // that a packet is waiting.  The parameters are set to indicate
+        // that the packet has not been read from the hardware FIFO yet.
+        //
+        psDevice->pfnRxCallback(psDevice->pvRxCBData,
+                                USB_EVENT_RX_AVAILABLE, ulSize,
+                                (void *)0);
+    }
+    else
+    {
+        //
+        // No packet was received.  Some error must have been reported.  Check
+        // and pass this on to the client if necessary.
+        //
+        if(ulEPStatus & USB_RX_ERROR_FLAGS)
+        {
+            //
+            // This is an error we report to the client so...
+            //
+            psDevice->pfnRxCallback(psDevice->pvRxCBData,
+                                    USB_EVENT_ERROR,
+                                    (ulEPStatus & USB_RX_ERROR_FLAGS),
+                                    (void *)0);
+        }
+        return(false);
+    }
+
+    return(true);
+}
+
+//*****************************************************************************
+//
+// Receives notifications related to data sent to the host.
+//
+// \param psDevice is the device instance whose endpoint is to be processed.
+// \param ulStatus is the USB interrupt status that caused this function to
+// be called.
+//
+// This function is called from HandleEndpoints for all interrupts originating
+// from the interrupt IN endpoint (in other words, whenever data has been
+// transmitted to the USB host).  We examine the cause of the interrupt and,
+// if due to completion of a transmission, notify the client.
+//
+// \return Returns \b true on success or \b false on failure.
+//
+//*****************************************************************************
+static tBoolean
+ProcessDataToHost(const tUSBDHIDDevice *psDevice, unsigned long ulStatus)
+{
+    tHIDInstance *psInst;
+    unsigned long ulEPStatus;
+
+    //
+    // Get a pointer to our instance data.
+    //
+    psInst = psDevice->psPrivateHIDData;
+
+    //
+    // Get the endpoint status to see why we were called.
+    //
+    ulEPStatus = MAP_USBEndpointStatus(psInst->ulUSBBase, psInst->ucINEndpoint);
+
+    //
+    // Clear the status bits.
+    //
+    MAP_USBDevEndpointStatusClear(psInst->ulUSBBase, psInst->ucINEndpoint,
+                                  ulEPStatus);
+
+    //
+    // Our last packet was transmitted successfully.  Is there any more data to
+    // send or have we finished sending the whole report?  We know we finished
+    // if the usInReportIndex has reached the usInReportSize value.
+    //
+    if(psInst->usInReportSize == psInst->usInReportIndex)
+    {
+        //
+        // We finished sending the last report so are idle once again.
+        //
+        psInst->eHIDTxState = HID_STATE_IDLE;
+
+        //
+        // Notify the client that the report transmission completed.
+        //
+        psDevice->pfnTxCallback(psDevice->pvTxCBData, USB_EVENT_TX_COMPLETE,
+                                psInst->usInReportSize, (void *)0);
+
+        //
+        // Do we have any reports to send as a result of idle timer timeouts?
+        //
+        if(psInst->usDeferredOpFlags & (1 << HID_DO_SEND_IDLE_REPORT))
+        {
+            //
+            // Yes - send reports for any timers that expired recently.
+            //
+            ProcessIdleTimers(psDevice, 0);
+        }
+    }
+    else
+    {
+        //
+        // There must be more data or a zero length packet waiting to be sent
+        // so go ahead and do this.
+        //
+        ScheduleReportTransmission(psInst);
+    }
+
+    return(true);
+}
+
+//*****************************************************************************
+//
+// Called by the USB stack for any activity involving one of our endpoints
+// other than EP0.  This function is a fan out that merely directs the call to
+// the correct handler depending upon the endpoint and transaction direction
+// signaled in ulStatus.
+//
+//*****************************************************************************
+static void
+HandleEndpoints(void *pvInstance, unsigned long ulStatus)
+{
+    const tUSBDHIDDevice *psHIDInst;
+    tHIDInstance *psInst;
+
+    ASSERT(pvInstance != 0);
+
+    //
+    // Determine if the serial device is in single or composite mode because
+    // the meaning of ulIndex is different in both cases.
+    //
+    psHIDInst = (const tUSBDHIDDevice *)pvInstance;
+    psInst = psHIDInst->psPrivateHIDData;
+
+    //
+    // Handler for the interrupt OUT data endpoint.
+    //
+    if(ulStatus & (0x10000 << USB_EP_TO_INDEX(psInst->ucOUTEndpoint)))
+    {
+        //
+        // Data is being sent to us from the host.
+        //
+        ProcessDataFromHost(pvInstance, ulStatus);
+    }
+
+    //
+    // Handler for the interrupt IN data endpoint.
+    //
+    if(ulStatus & (1 << USB_EP_TO_INDEX(psInst->ucINEndpoint)))
+    {
+        ProcessDataToHost(pvInstance, ulStatus);
+    }
+}
+
+//*****************************************************************************
+//
+// Called by the USB stack whenever a configuration change occurs.
+//
+//*****************************************************************************
+static void
+HandleConfigChange(void *pvInstance, unsigned long ulInfo)
+{
+    tHIDInstance *psInst;
+    const tUSBDHIDDevice *psDevice;
+
+    ASSERT(pvInstance != 0);
+
+    //
+    // Create the instance pointer.
+    //
+    psDevice = pvInstance;
+
+    //
+    // Get a pointer to our instance data.
+    //
+    psInst = psDevice->psPrivateHIDData;
+
+    //
+    // Set all our endpoints to idle state.
+    //
+    psInst->eHIDRxState = HID_STATE_IDLE;
+    psInst->eHIDTxState = HID_STATE_IDLE;
+
+    //
+    // If we are not currently connected let the client know we are open for
+    // business.
+    //
+    if(!psInst->bConnected)
+    {
+        //
+        // Pass the connected event to the client.
+        //
+        psDevice->pfnRxCallback(psDevice->pvRxCBData, USB_EVENT_CONNECTED, 0,
+                                (void *)0);
+    }
+
+    //
+    // Clear the idle timers for each input report.
+    //
+    ClearIdleTimers(psDevice);
+
+    //
+    // Remember that we are connected.
+    //
+    psInst->bConnected = true;
+}
+
+//*****************************************************************************
+//
+// Device instance specific handler.
+//
+//*****************************************************************************
+static void
+HandleDevice(void *pvInstance, unsigned long ulRequest, void *pvRequestData)
+{
+    tHIDInstance *psInst;
+    unsigned char *pucData;
+
+    //
+    // Create the serial instance data.
+    //
+    psInst = ((tUSBDHIDDevice *)pvInstance)->psPrivateHIDData;
+
+    //
+    // Create the char array used by the events supported by the USB CDC
+    // serial class.
+    //
+    pucData = (unsigned char *)pvRequestData;
+
+    switch(ulRequest)
+    {
+        //
+        // This was an interface change event.
+        //
+        case USB_EVENT_COMP_IFACE_CHANGE:
+        {
+            psInst->ucInterface = pucData[1];
+            break;
+        }
+
+        //
+        // This was an endpoint change event.
+        //
+        case USB_EVENT_COMP_EP_CHANGE:
+        {
+            //
+            // Determine if this is an IN or OUT endpoint that has changed.
+            //
+            if(pucData[0] & USB_EP_DESC_IN)
+            {
+                psInst->ucINEndpoint =
+                    INDEX_TO_USB_EP((pucData[1] & 0x7f));
+            }
+            else
+            {
+                //
+                // Extract the new endpoint number.
+                //
+                psInst->ucOUTEndpoint =
+                    INDEX_TO_USB_EP(pucData[1] & 0x7f);
+            }
+            break;
+        }
+        default:
+        {
+            break;
+        }
+    }
+}
+
+//*****************************************************************************
+//
+// This function is called by the USB device stack whenever the device is
+// disconnected from the host.
+//
+//*****************************************************************************
+static void
+HandleDisconnect(void *pvInstance)
+{
+    const tUSBDHIDDevice *psDevice;
+
+    ASSERT(pvInstance != 0);
+
+    //
+    // Create the instance pointer.
+    //
+    psDevice = (const tUSBDHIDDevice *)pvInstance;
+
+    //
+    // If we are not currently connected so let the client know we are open
+    // for business.
+    //
+    if(psDevice->psPrivateHIDData->bConnected)
+    {
+        //
+        // Pass the disconnected event to the client.
+        //
+        psDevice->pfnRxCallback(psDevice->pvRxCBData, USB_EVENT_DISCONNECTED,
+                                0, (void *)0);
+    }
+
+    //
+    // Remember that we are no longer connected.
+    //
+    psDevice->psPrivateHIDData->bConnected = false;
+}
+
+//*****************************************************************************
+//
+// This function is called by the USB device stack whenever a request for a
+// non-standard descriptor is received.
+//
+// \param pvInstance is the instance data for this request.
+// \param pUSBRequest points to the request received.
+//
+// This call parses the provided request structure and determines which
+// descriptor is being requested.  Assuming the descriptor can be found, it is
+// scheduled for transmission via endpoint zero.  If the descriptor cannot be
+// found, the endpoint is stalled to indicate an error to the host.
+//
+//*****************************************************************************
+static void
+HandleGetDescriptor(void *pvInstance, tUSBRequest *pUSBRequest)
+{
+    unsigned long ulSize;
+    unsigned long ulDesc;
+    const tUSBDHIDDevice *psDevice;
+
+    ASSERT(pvInstance != 0);
+
+    //
+    // Which device are we dealing with?
+    //
+    psDevice = pvInstance;
+
+    //
+    // Which type of class descriptor are we being asked for?
+    //
+    switch(pUSBRequest->wValue >> 8)
+    {
+        //
+        // This is a request for a HID report or physical descriptor.
+        //
+        case USB_HID_DTYPE_REPORT:
+        case USB_HID_DTYPE_PHYSICAL:
+        {
+            //
+            // Find the index to the descriptor that is being queried.
+            //
+            ulSize = 0;
+            ulDesc = FindHIDDescriptor(psDevice, pUSBRequest->wValue >> 8,
+                                       pUSBRequest->wValue & 0xFF,
+                                       &ulSize);
+
+            //
+            // Did we find the descriptor?
+            //
+            if(ulDesc == HID_NOT_FOUND)
+            {
+                //
+                // No - stall the endpoint and return.
+                //
+                USBDCDStallEP0(0);
+                return;
+            }
+
+            //
+            // If there is more data to send than the host requested then just
+            // send the requested amount of data.
+            //
+            if(ulSize > pUSBRequest->wLength)
+            {
+                ulSize = pUSBRequest->wLength;
+            }
+
+            //
+            // Send the data via endpoint 0.
+            //
+            USBDCDSendDataEP0(0,
+                (unsigned char *)psDevice->ppClassDescriptors[ulDesc], ulSize);
+
+            break;
+        }
+
+        //
+        // This is a request for the HID descriptor (as found in the
+        // configuration descriptor following the relevant interface).
+        //
+        case USB_HID_DTYPE_HID:
+        {
+            //
+            // How big is the HID descriptor?
+            //
+            ulSize = (unsigned long)psDevice->psHIDDescriptor->bLength;
+
+            //
+            // If there is more data to send than the host requested then just
+            // send the requested amount of data.
+            //
+            if(ulSize > pUSBRequest->wLength)
+            {
+                ulSize = pUSBRequest->wLength;
+            }
+
+            //
+            // Send the data via endpoint 0.
+            //
+            USBDCDSendDataEP0(0, (unsigned char *)psDevice->psHIDDescriptor,
+                              ulSize);
+            break;
+        }
+
+        //
+        // This was an unknown request so stall.
+        //
+        default:
+        {
+            USBDCDStallEP0(0);
+            break;
+        }
+    }
+}
+
+//*****************************************************************************
+//
+// This function is called by the USB device stack whenever a non-standard
+// request is received.
+//
+// \param pvInstance is the instance data for this HID device.
+// \param pUSBRequest points to the request received.
+//
+// This call parses the provided request structure.  Assuming the request is
+// understood, it is handled and any required response generated.  If the
+// request cannot be handled by this device class, endpoint zero is stalled to
+// indicate an error to the host.
+//
+//*****************************************************************************
+static void
+HandleRequest(void *pvInstance, tUSBRequest *pUSBRequest)
+{
+    tHIDInstance *psInst;
+    unsigned char ucProtocol;
+    const tUSBDHIDDevice *psDevice;
+
+    ASSERT(pvInstance != 0);
+
+    //
+    // Which device are we dealing with?
+    //
+    psDevice = pvInstance;
+
+    //
+    // Get a pointer to our instance data.
+    //
+    psInst = psDevice->psPrivateHIDData;
+
+    //
+    // Make sure the request was for this interface.
+    //
+    if(pUSBRequest->wIndex != psInst->ucInterface)
+    {
+        return;
+    }
+
+    //
+    // Determine the type of request.
+    //
+    switch(pUSBRequest->bRequest)
+    {
+        //
+        // A Set Report request is received from the host when it sends an
+        // Output report via endpoint 0.
+        //
+        case USBREQ_SET_REPORT:
+        {
+            //
+            // Ask the application for a buffer large enough to hold the
+            // report we are to be sent.
+            //
+            psInst->usOutReportSize = pUSBRequest->wLength;
+            psInst->pucOutReportData =
+                (unsigned char *)psDevice->pfnRxCallback(
+                               psDevice->pvRxCBData,
+                               USBD_HID_EVENT_GET_REPORT_BUFFER,
+                               pUSBRequest->wValue,
+                               (void *)(unsigned long)(pUSBRequest->wLength));
+
+            //
+            // Did the client provide us a buffer?
+            //
+            if(!psInst->pucOutReportData)
+            {
+                //
+                // The application couldn't provide us a buffer so stall the
+                // request.
+                //
+                USBDCDStallEP0(0);
+            }
+            else
+            {
+                //
+                // The client provided us a buffer to read the report into
+                // so request the data from the host.
+                //
+
+                //
+                // Set the state to indicate we are waiting for data.
+                //
+                psInst->eHIDRxState = HID_STATE_WAIT_DATA;
+
+                //
+                // Now read the payload of the request.  We handle the actual
+                // operation in the data callback once this data is received.
+                //
+                USBDCDRequestDataEP0(0, psInst->pucOutReportData,
+                                     (unsigned long)pUSBRequest->wLength);
+
+                //
+                // Need to ACK the data on end point 0 in this case.  Do this
+                // after requesting the data to prevent race conditions that
+                // occur if you acknowledge before setting up to receive the
+                // request data.
+                //
+                MAP_USBDevEndpointDataAck(psInst->ulUSBBase, USB_EP_0, true);
+            }
+
+            break;
+        }
+
+        //
+        // A Get Report request is used by the host to poll a device for its
+        // current state.
+        //
+        case USBREQ_GET_REPORT:
+        {
+            unsigned long ulSize;
+            unsigned char *pucReport;
+
+            //
+            // Get the latest report from the application.
+            //
+            ulSize = psDevice->pfnRxCallback(psDevice->pvRxCBData,
+                                             USBD_HID_EVENT_GET_REPORT,
+                                             pUSBRequest->wValue, &pucReport);
+
+            //
+            // Need to ACK the data on end point 0 in this case.
+            //
+            MAP_USBDevEndpointDataAck(psInst->ulUSBBase, USB_EP_0, true);
+
+            //
+            // ..then send back the requested report.
+            //
+            psInst->bGetRequestPending = true;
+            USBDCDSendDataEP0(0, pucReport, ulSize);
+
+            break;
+        }
+
+        //
+        // A set IDLE request has been made.  This indicates to us how often a
+        // given report should be sent back to the host in the absence of any
+        // change in state of the device.
+        //
+        case USBREQ_SET_IDLE:
+        {
+            //
+            // Set the idle timeout for the requested report(s).
+            //
+            SetIdleTimeout(psDevice, pUSBRequest->wValue & 0xFF,
+                           (pUSBRequest->wValue >> 8) & 0xFF);
+
+            //
+            // Need to ACK the data on end point 0 in this case.
+            //
+            MAP_USBDevEndpointDataAck(psInst->ulUSBBase, USB_EP_0, true);
+
+            break;
+        }
+
+        //
+        // A get IDLE request has been made.  This request queries the current
+        // idle timeout for a given report.
+        //
+        case USBREQ_GET_IDLE:
+        {
+            unsigned long ulTimeout;
+
+            //
+            // Determine the timeout for the requested report.
+            //
+            ulTimeout = GetIdleTimeout(psDevice, pUSBRequest->wValue);
+
+            if(ulTimeout != HID_NOT_FOUND)
+            {
+                //
+                // Need to ACK the data on end point 0 in this case.
+                //
+                MAP_USBDevEndpointDataAck(psInst->ulUSBBase, USB_EP_0, true);
+
+                //
+                // Send our response to the host.
+                //
+                USBDCDSendDataEP0(0, (unsigned char *)&ulTimeout, 1);
+            }
+            else
+            {
+                //
+                // The report ID was not found so stall the endpoint.
+                //
+                USBDCDStallEP0(0);
+            }
+            break;
+        }
+
+        //
+        // Set either boot or report protocol for reports sent from the device.
+        // This is only supported by devices in the boot subclass.
+        //
+        case USBREQ_SET_PROTOCOL:
+        {
+            if(psDevice->ucSubclass == USB_HID_SCLASS_BOOT)
+            {
+                //
+                // We need to ACK the data on end point 0 in this case.
+                //
+                MAP_USBDevEndpointDataAck(psInst->ulUSBBase, USB_EP_0, true);
+
+                //
+                // We are a boot subclass device so pass this on to the
+                // application.
+                //
+                psDevice->pfnRxCallback(psDevice->pvRxCBData,
+                                        USBD_HID_EVENT_SET_PROTOCOL,
+                                        pUSBRequest->wValue,
+                                        (void *)0);
+            }
+            else
+            {
+                //
+                // This is not a boot subclass device so stall the endpoint to
+                // show that we don't support this request.
+                //
+                USBDCDStallEP0(0);
+            }
+            break;
+        }
+
+        //
+        // Inform the host of the protocol, boot or report, that is currently
+        // in use.  This is only supported by devices in the boot subclass.
+        //
+        case USBREQ_GET_PROTOCOL:
+        {
+            if(psDevice->ucSubclass == USB_HID_SCLASS_BOOT)
+            {
+                //
+                // We need to ACK the data on end point 0 in this case.
+                //
+                MAP_USBDevEndpointDataAck(psInst->ulUSBBase, USB_EP_0, true);
+
+                //
+                // We are a boot subclass device so pass this on to the
+                // application callback to get the answer.
+                //
+                ucProtocol = (unsigned char)psDevice->pfnRxCallback(
+                    psDevice->pvRxCBData, USBD_HID_EVENT_GET_PROTOCOL, 0,
+                    (void *)0);
+
+                //
+                // Send our response to the host.
+                //
+                USBDCDSendDataEP0(0, (unsigned char *)&ucProtocol, 1);
+            }
+            else
+            {
+                //
+                // This is not a boot subclass device so stall the endpoint to
+                // show that we don't support this request.
+                //
+                USBDCDStallEP0(0);
+            }
+            break;
+        }
+
+        //
+        // This request was not recognized so stall.
+        //
+        default:
+        {
+            USBDCDStallEP0(0);
+            break;
+        }
+    }
+}
+
+//*****************************************************************************
+//
+// This function is called by the USB device stack whenever the data requested
+// on endpoint zero is received.
+//
+//*****************************************************************************
+static void
+HandleEP0DataReceived(void *pvInstance, unsigned long ulDataSize)
+{
+    tHIDInstance *psInst;
+    const tUSBDHIDDevice *psDevice;
+
+    ASSERT(pvInstance != 0);
+
+    //
+    // Which device are we dealing with?
+    //
+    psDevice = pvInstance;
+
+    //
+    // If we were not passed any data, just return.
+    //
+    if(ulDataSize == 0)
+    {
+        return;
+    }
+
+    //
+    // Get our instance data pointer.
+    //
+    psInst = psDevice->psPrivateHIDData;
+
+    //
+    // Make sure we are actually expecting something.
+    //
+    if(psInst->eHIDRxState != HID_STATE_WAIT_DATA)
+    {
+        return;
+    }
+
+    //
+    // Change the endpoint state back to idle now that we have been passed
+    // the data we were waiting for.
+    //
+    psInst->eHIDRxState = HID_STATE_IDLE;
+
+    //
+    // The only things we ever request via endpoint zero are reports sent to
+    // us via a Set_Report request.  Pass the newly received report on to
+    // the client.
+    //
+    psDevice->pfnRxCallback(psDevice->pvRxCBData, USBD_HID_EVENT_SET_REPORT,
+                            psInst->usOutReportSize,
+                            psInst->pucOutReportData);
+}
+
+//*****************************************************************************
+//
+// This function is called by the USB device stack whenever the data sent on
+// endpoint zero is received and acknowledged by the host.
+//
+//*****************************************************************************
+static void
+HandleEP0DataSent(void *pvInstance, unsigned long ulInfo)
+{
+    tHIDInstance *psInst;
+    const tUSBDHIDDevice *psDevice;
+
+    ASSERT(pvInstance != 0);
+
+    //
+    // Which device are we dealing with?
+    //
+    psDevice = pvInstance;
+
+    //
+    // Get our instance data pointer.
+    //
+    psInst = psDevice->psPrivateHIDData;
+
+    //
+    // If we just sent a report in response to a Get_Report request, send an
+    // event to the application telling it that the transmission completed.
+    //
+    if(psInst->bGetRequestPending)
+    {
+        //
+        // Clear the flag now that we are sending the application callback.
+        //
+        psInst->bGetRequestPending = false;
+
+        psDevice->pfnRxCallback(psDevice->pvRxCBData,
+                                USBD_HID_EVENT_REPORT_SENT, 0, (void *)0);
+    }
+
+    return;
+}
+
+//*****************************************************************************
+//
+// This function is called by the USB device stack whenever the device is
+// reset.  If we are currently connected, send a disconnect event at this
+// point.
+//
+//*****************************************************************************
+static void
+HandleReset(void *pvInstance)
+{
+    ASSERT(pvInstance != 0);
+
+    //
+    // Merely call the disconnect handler.  This causes a disconnect message to
+    // be sent to the client if we think we are currently connected.
+    //
+    HandleDisconnect(pvInstance);
+}
+
+//*****************************************************************************
+//
+// This function is called by the USB device stack whenever the bus is put into
+// suspend state.
+//
+//*****************************************************************************
+static void
+HandleSuspend(void *pvInstance)
+{
+    const tUSBDHIDDevice *psDevice;
+
+    ASSERT(pvInstance != 0);
+
+    //
+    // Create the instance pointer.
+    //
+    psDevice = (const tUSBDHIDDevice *)pvInstance;
+
+    //
+    // Pass the event on to the client.
+    //
+    psDevice->pfnRxCallback(psDevice->pvRxCBData, USB_EVENT_SUSPEND, 0,
+                            (void *)0);
+}
+
+//*****************************************************************************
+//
+// This function is called by the USB device stack whenever the bus is taken
+// out of suspend state.
+//
+//*****************************************************************************
+static void
+HandleResume(void *pvInstance)
+{
+    const tUSBDHIDDevice *psDevice;
+
+    ASSERT(pvInstance != 0);
+
+    //
+    // Create the instance pointer.
+    //
+    psDevice = (const tUSBDHIDDevice *)pvInstance;
+
+    //
+    // Pass the event on to the client.
+    //
+    psDevice->pfnRxCallback(psDevice->pvRxCBData,
+                            USB_EVENT_RESUME, 0, (void *)0);
+}
+
+//*****************************************************************************
+//
+// This function is called periodically and provides us with a time reference
+// and method of implementing delayed or time-dependent operations.
+//
+// \param pvInstance is the instance data for this request.
+// \param ulTimemS is the elapsed time in milliseconds since the last call
+// to this function.
+//
+// \return None.
+//
+//*****************************************************************************
+static void
+HIDTickHandler(void *pvInstance, unsigned long ulTimemS)
+{
+    tHIDInstance *psInst;
+    unsigned long ulSize;
+    const tUSBDHIDDevice *psDevice;
+
+    ASSERT(pvInstance != 0);
+
+    //
+    // Create the instance pointer.
+    //
+    psDevice = (const tUSBDHIDDevice *)pvInstance;
+
+    //
+    // Get our instance data pointer.
+    //
+    psInst = psDevice->psPrivateHIDData;
+
+    //
+    // If we are connected, process our idle timers.
+    //
+    if(psInst->bConnected)
+    {
+        ProcessIdleTimers(psDevice, ulTimemS);
+    }
+
+    //
+    // Do we have a deferred receive waiting
+    //
+    if(psInst->usDeferredOpFlags & (1 << HID_DO_PACKET_RX))
+    {
+        //
+        // Yes - how big is the waiting packet?
+        //
+        ulSize = MAP_USBEndpointDataAvail(USB0_BASE, psInst->ucOUTEndpoint);
+
+        //
+        // Tell the client that there is a packet waiting for it.
+        //
+        psDevice->pfnRxCallback(psDevice->pvRxCBData,
+                                USB_EVENT_RX_AVAILABLE, ulSize, (void *)0);
+    }
+
+    return;
+}
+
+//*****************************************************************************
+//
+//! Initializes HID device operation for a given USB controller.
+//!
+//! \param ulIndex is the index of the USB controller which is to be
+//! initialized for HID device operation.
+//! \param psDevice points to a structure containing parameters customizing
+//! the operation of the HID device.
+//!
+//! An application wishing to offer a USB HID interface to a host system
+//! must call this function to initialize the USB controller and attach the
+//! device to the USB bus.  This function performs all required USB
+//! initialization.
+//!
+//! On successful completion, this function will return the \e psDevice pointer
+//! passed to it.  This must be passed on all future calls from the application
+//! to the HID device class driver.
+//!
+//! The USB HID device class API offers the application a report-based transmit
+//! interface for Input reports.  Output reports may be received via the
+//! control endpoint or via a dedicated Interrupt OUT endpoint.  If using the
+//! dedicated endpoint, report data is delivered to the application packet-by-
+//! packet.  If the application uses reports longer than 64 bytes and would
+//! rather receive full reports, it may use a USB buffer above the receive
+//! channel to allow full reports to be read.
+//!
+//! Transmit Operation:
+//!
+//! Calls to USBDHIDReportWrite() pass complete reports to the driver for
+//! transmission.  These will be transmitted to the host using as many USB
+//! packets as are necessary to complete the transmission.
+//!
+//! Once a full Input report has been acknowledged by the USB host, a
+//! USB_EVENT_TX_COMPLETE event is sent to the application transmit callback to
+//! inform it that another report may be transmitted.
+//!
+//! Receive Operation (when using a dedicated interrupt OUT endpoint):
+//!
+//! An incoming USB data packet will result in a call to the application
+//! callback with event USB_EVENT_RX_AVAILABLE.  The application must then
+//! call USBDHIDPacketRead(), passing a buffer capable of holding the received
+//! packet.  The size of the packet may be determined by calling function
+//! USBDHIDRxPacketAvailable() prior to reading the packet.
+//!
+//! Receive Operation (when not using a dedicated OUT endpoint):
+//!
+//! If no dedicated OUT endpoint is used, Output and Feature reports are sent
+//! from the host using the control endpoint, endpoint zero.  When such a
+//! report is received, USBD_HID_EVENT_GET_REPORT_BUFFER is sent to the
+//! application which must respond with a buffer large enough to hold the
+//! report.  The device class driver will then copy the received report into
+//! the supplied buffer before sending USBD_HID_EVENT_SET_REPORT to indicate
+//! that the report is now available.
+//!
+//! \note The application must not make any calls to the low level USB device
+//! interface if interacting with USB via the USB HID device class API.  Doing
+//! so will cause unpredictable (though almost certainly unpleasant) behavior.
+//!
+//! \return Returns NULL on failure or the \e psDevice pointer on success.
+//
+//*****************************************************************************
+void *
+USBDHIDInit(unsigned long ulIndex, const tUSBDHIDDevice *psDevice)
+{
+    //
+    // Check parameter validity.
+    //
+    ASSERT(ulIndex == 0);
+    ASSERT(psDevice);
+    ASSERT(psDevice->ppStringDescriptors);
+    ASSERT(psDevice->psPrivateHIDData);
+    ASSERT(psDevice->pfnRxCallback);
+    ASSERT(psDevice->pfnTxCallback);
+    ASSERT(psDevice->ppClassDescriptors);
+    ASSERT(psDevice->psHIDDescriptor);
+    ASSERT((psDevice->ucNumInputReports == 0) || psDevice->psReportIdle);
+
+
+    USBDHIDCompositeInit(ulIndex, psDevice);
+
+    //
+    // All is well so now pass the descriptors to the lower layer and put
+    // the HID device on the bus.
+    //
+    USBDCDInit(ulIndex, psDevice->psPrivateHIDData->psDevInfo);
+
+    //
+    // Return the pointer to the instance indicating that everything went well.
+    //
+    return((void *)psDevice);
+}
+
+//*****************************************************************************
+//
+//! Initializes HID device operation for a given USB controller.
+//!
+//! \param ulIndex is the index of the USB controller which is to be
+//! initialized for HID device operation.
+//! \param psDevice points to a structure containing parameters customizing
+//! the operation of the HID device.
+//!
+//!
+//! \return Returns NULL on failure or the \e psDevice pointer on success.
+//
+//*****************************************************************************
+void *
+USBDHIDCompositeInit(unsigned long ulIndex, const tUSBDHIDDevice *psDevice)
+{
+    tHIDInstance *psInst;
+    tDeviceDescriptor *psDevDesc;
+    tInterfaceDescriptor *psDevIf;
+
+    //
+    // Check parameter validity.
+    //
+    ASSERT(ulIndex == 0);
+    ASSERT(psDevice);
+    ASSERT(psDevice->ppStringDescriptors);
+    ASSERT(psDevice->psPrivateHIDData);
+    ASSERT(psDevice->pfnRxCallback);
+    ASSERT(psDevice->pfnTxCallback);
+    ASSERT(psDevice->ppClassDescriptors);
+    ASSERT(psDevice->psHIDDescriptor);
+    ASSERT((psDevice->ucNumInputReports == 0) || psDevice->psReportIdle);
+
+    //
+    // Initialize the workspace in the passed instance structure.
+    //
+    psInst = psDevice->psPrivateHIDData;
+    psInst->psConfDescriptor = (tConfigDescriptor *)g_pHIDDescriptor;
+    psInst->psDevInfo = &g_sHIDDeviceInfo;
+    psInst->ulUSBBase = USB0_BASE;
+    psInst->eHIDRxState = HID_STATE_UNCONFIGURED;
+    psInst->eHIDTxState = HID_STATE_UNCONFIGURED;
+    psInst->usDeferredOpFlags = 0;
+    psInst->bConnected = false;
+    psInst->bGetRequestPending = false;
+    psInst->bSendInProgress = false;
+    psInst->usInReportIndex = 0;
+    psInst->usInReportSize = 0;
+    psInst->pucInReportData = (unsigned char *)0;
+    psInst->usOutReportSize = 0;
+    psInst->pucOutReportData = (unsigned char *)0;
+
+    //
+    // Set the default endpoint and interface assignments.
+    //
+    psInst->ucINEndpoint = INT_IN_ENDPOINT;
+    psInst->ucOUTEndpoint = INT_OUT_ENDPOINT;
+    psInst->ucInterface = 0;
+
+    //
+    // Fix up the device descriptor with the client-supplied values.
+    //
+    psDevDesc = (tDeviceDescriptor *)psInst->psDevInfo->pDeviceDescriptor;
+    psDevDesc->idVendor = psDevice->usVID;
+    psDevDesc->idProduct = psDevice->usPID;
+
+    //
+    // Fix up the configuration descriptor with client-supplied values.
+    //
+    psInst->psConfDescriptor->bmAttributes = psDevice->ucPwrAttributes;
+    psInst->psConfDescriptor->bMaxPower =
+                        (unsigned char)(psDevice->usMaxPowermA / 2);
+
+    //
+    // Slot the client's HID descriptor into our standard configuration
+    // descriptor.
+    //
+    g_sHIDDescriptorSection.ucSize = psDevice->psHIDDescriptor->bLength;
+    g_sHIDDescriptorSection.pucData =
+                                (unsigned char *)psDevice->psHIDDescriptor;
+
+    //
+    // Fix up the interface and endpoint descriptors depending upon client
+    // choices.
+    //
+    psDevIf = (tInterfaceDescriptor *)g_pHIDInterface;
+    psDevIf->bNumEndpoints = psDevice->bUseOutEndpoint ? 2 : 1;
+    psDevIf->bInterfaceSubClass = psDevice->ucSubclass;
+    psDevIf->bInterfaceProtocol = psDevice->ucProtocol;
+
+    //
+    // If necessary, remove the interrupt OUT endpoint from the configuration
+    // descriptor.
+    //
+    if(psDevice->bUseOutEndpoint == false)
+    {
+        g_sHIDConfigHeader.ucNumSections = (NUM_HID_SECTIONS - 1);
+    }
+    else
+    {
+        g_sHIDConfigHeader.ucNumSections = NUM_HID_SECTIONS;
+    }
+
+    //
+    // Plug in the client's string table to the device information
+    // structure.
+    //
+    psInst->psDevInfo->ppStringDescriptors = psDevice->ppStringDescriptors;
+    psInst->psDevInfo->ulNumStringDescriptors
+            = psDevice->ulNumStringDescriptors;
+    psInst->psDevInfo->pvInstance = (void *)psDevice;
+
+    //
+    // Initialize the input report idle timers if any input reports exist.
+    //
+    ClearIdleTimers(psDevice);
+
+    //
+    // Initialize the USB tick module, this will prevent it from being
+    // initialized later in the call to USBDCDInit();
+    //
+    InternalUSBTickInit();
+
+    //
+    // Register our tick handler (this must be done after USBDCDInit).
+    //
+    InternalUSBRegisterTickHandler(USB_TICK_HANDLER_DEVICE,
+                                   HIDTickHandler,
+                                   (void *)psDevice);
+
+    //
+    // Return the pointer to the instance indicating that everything went well.
+    //
+    return((void *)psDevice);
+}
+
+//*****************************************************************************
+//
+//! Shuts down the HID device.
+//!
+//! \param pvInstance is the pointer to the device instance structure as
+//! returned by USBDHIDInit().
+//!
+//! This function terminates HID operation for the instance supplied and
+//! removes the device from the USB bus.  This function should not be called
+//! if the HID device is part of a composite device and instead the
+//! USBDCompositeTerm() function should be called for the full composite
+//! device.
+//!
+//! Following this call, the \e pvInstance instance should not me used in any
+//! other calls.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDHIDTerm(void *pvInstance)
+{
+    tHIDInstance *psInst;
+
+    ASSERT(pvInstance);
+
+    //
+    // Get a pointer to our instance data.
+    //
+    psInst = ((tUSBDHIDDevice *)pvInstance)->psPrivateHIDData;
+
+    //
+    // Terminate the requested instance.
+    //
+    USBDCDTerm(USB_BASE_TO_INDEX(psInst->ulUSBBase));
+
+    psInst->ulUSBBase = 0;
+    psInst->psDevInfo = (tDeviceInfo *)0;
+    psInst->psConfDescriptor = (tConfigDescriptor *)0;
+}
+
+//*****************************************************************************
+//
+//! Sets the client-specific pointer parameter for the receive channel
+//! callback.
+//!
+//! \param pvInstance is the pointer to the device instance structure as
+//! returned by USBDHIDInit().
+//! \param pvCBData is the pointer that client wishes to be provided on each
+//! event sent to the receive channel callback function.
+//!
+//! The client uses this function to change the callback pointer passed in
+//! the first parameter on all callbacks to the \e pfnRxCallback function
+//! passed on USBDHIDInit().
+//!
+//! If a client wants to make runtime changes in the callback pointer, it must
+//! ensure that the pvInstance structure passed to USBDHIDInit() resides in
+//! RAM.  If this structure is in flash, callback data changes will not be
+//! possible.
+//!
+//! \return Returns the previous callback pointer that was being used for
+//! this instance's receive callback.
+//
+//*****************************************************************************
+void *
+USBDHIDSetRxCBData(void *pvInstance, void *pvCBData)
+{
+    void *pvOldValue;
+
+    ASSERT(pvInstance);
+
+    //
+    // Set the callback data for the receive channel after remembering the
+    // previous value.
+    //
+    pvOldValue = ((tUSBDHIDDevice *)pvInstance)->pvRxCBData;
+    ((tUSBDHIDDevice *)pvInstance)->pvRxCBData = pvCBData;
+
+    //
+    // Return the previous callback data value.
+    //
+    return(pvOldValue);
+}
+
+//*****************************************************************************
+//
+//! Sets the client-specific data pointer for the transmit callback.
+//!
+//! \param pvInstance is the pointer to the device instance structure as
+//! returned by USBDHIDInit().
+//! \param pvCBData is the pointer that client wishes to be provided on each
+//! event sent to the transmit channel callback function.
+//!
+//! The client uses this function to change the callback data pointer passed in
+//! the first parameter on all callbacks to the \e pfnTxCallback function
+//! passed on USBDHIDInit().
+//!
+//! If a client wants to make runtime changes in the callback data, it must
+//! ensure that the pvInstance structure passed to USBDHIDInit() resides in
+//! RAM.  If this structure is in flash, callback data changes will not be
+//! possible.
+//!
+//! \return Returns the previous callback data pointer that was being used for
+//! this instance's transmit callback.
+//
+//*****************************************************************************
+void *
+USBDHIDSetTxCBData(void *pvInstance, void *pvCBData)
+{
+    void *pvOldValue;
+
+    ASSERT(pvInstance);
+
+    //
+    // Set the callback data for the transmit channel after remembering the
+    // previous value.
+    //
+    pvOldValue = ((tUSBDHIDDevice *)pvInstance)->pvTxCBData;
+    ((tUSBDHIDDevice *)pvInstance)->pvTxCBData = pvCBData;
+
+    //
+    // Return the previous callback data value.
+    //
+    return(pvOldValue);
+}
+
+//*****************************************************************************
+//
+//! Transmits a HID device report to the USB host via the HID interrupt IN
+//! endpoint.
+//!
+//! \param pvInstance is the pointer to the device instance structure as
+//! returned by USBDHIDInit().
+//! \param pcData points to the first byte of data which is to be transmitted.
+//! \param ulLength is the number of bytes of data to transmit.
+//! \param bLast is ignored in this implementation.  This parameter is required
+//! to ensure compatibility with other device class drivers and USB buffers.
+//!
+//! This function schedules the supplied data for transmission to the USB
+//! host in a single USB transaction using as many packets as it takes to send
+//! all the data in the report.  If no transmission is currently ongoing,
+//! the first packet of data is immediately copied to the relevant USB endpoint
+//! FIFO for transmission.  Whenever all the report data has been acknowledged
+//! by the host, a \b USB_EVENT_TX_COMPLETE event will be sent to the
+//! application transmit callback indicating that another report can now be
+//! transmitted.
+//!
+//! The caller must ensure that the data pointed to by pucData remains
+//! accessible and unaltered until the \b USB_EVENT_TX_COMPLETE is received.
+//!
+//! \return Returns the number of bytes actually scheduled for transmission.
+//! At this level, this will either be the number of bytes passed or 0 to
+//! indicate a failure.
+//
+//*****************************************************************************
+unsigned long
+USBDHIDReportWrite(void *pvInstance, unsigned char *pcData,
+                   unsigned long ulLength, tBoolean bLast)
+{
+    tHIDInstance *psInst;
+    long lRetcode;
+
+    ASSERT(pvInstance);
+
+    //
+    // Get our instance data pointer
+    //
+    psInst = ((tUSBDHIDDevice *)pvInstance)->psPrivateHIDData;
+
+    //
+    // Set a flag indicating that we are currently in the process of sending
+    // a packet.
+    //
+    psInst->bSendInProgress = true;
+
+    //
+    // Can we send the data provided?
+    //
+    if(psInst->eHIDTxState != HID_STATE_IDLE)
+    {
+        //
+        // We are in the middle of sending another report.  Return 0 to
+        // indicate that we can't send this report until the previous one
+        // finishes.
+        //
+        psInst->bSendInProgress = false;
+        return(0);
+    }
+
+    //
+    // Clear the elapsed time since this report was last sent.
+    //
+    if(ulLength)
+    {
+        ClearReportTimer(pvInstance, *pcData);
+    }
+
+    //
+    // Keep track of the whereabouts of the report so that we can send it in
+    // multiple packets if necessary.
+    //
+    psInst->pucInReportData = pcData;
+    psInst->usInReportIndex = 0;
+    psInst->usInReportSize = ulLength;
+
+    //
+    // Schedule transmission of the first packet of the report.
+    //
+    psInst->eHIDTxState = HID_STATE_WAIT_DATA;
+    lRetcode = ScheduleReportTransmission(psInst);
+
+    //
+    // Clear the flag we use to indicate that we are in the midst of sending
+    // a packet.
+    //
+    psInst->bSendInProgress = false;
+
+    //
+    // Did an error occur while trying to send the data?
+    //
+    if(lRetcode != -1)
+    {
+        //
+        // No - tell the caller we sent all the bytes provided.
+        //
+        return(ulLength);
+    }
+    else
+    {
+        //
+        // Yes - tell the caller we couldn't send the data.
+        //
+        return(0);
+    }
+}
+
+//*****************************************************************************
+//
+//! Reads a packet of data received from the USB host via the interrupt OUT
+//! endpoint (if in use).
+//!
+//! \param pvInstance is the pointer to the device instance structure as
+//! returned by USBDHIDInit().
+//! \param pcData points to a buffer into which the received data will be
+//! written.
+//! \param ulLength is the size of the buffer pointed to by pcData.
+//! \param bLast indicates whether the client will make a further call to
+//! read additional data from the packet.
+//!
+//! This function reads up to ulLength bytes of data received from the USB
+//! host into the supplied application buffer.  If the driver detects that the
+//! entire packet has been read, it is acknowledged to the host.
+//!
+//! The \e bLast parameter is ignored in this implementation since the end of
+//! a packet can be determined without relying upon the client to provide
+//! this information.
+//!
+//! \return Returns the number of bytes of data read.
+//
+//*****************************************************************************
+unsigned long
+USBDHIDPacketRead(void *pvInstance, unsigned char *pcData,
+                  unsigned long ulLength, tBoolean bLast)
+{
+    unsigned long ulEPStatus, ulCount, ulPkt;
+    tHIDInstance *psInst;
+    long lRetcode;
+
+    ASSERT(pvInstance);
+
+    //
+    // Get our instance data pointer
+    //
+    psInst = ((tUSBDHIDDevice *)pvInstance)->psPrivateHIDData;
+
+    //
+    // Does the relevant endpoint FIFO have a packet waiting for us?
+    //
+    ulEPStatus = MAP_USBEndpointStatus(psInst->ulUSBBase,
+                                       psInst->ucOUTEndpoint);
+    if(ulEPStatus & USB_DEV_RX_PKT_RDY)
+    {
+        //
+        // How many bytes are available for us to receive?
+        //
+        ulPkt = MAP_USBEndpointDataAvail(psInst->ulUSBBase,
+                                         psInst->ucOUTEndpoint);
+
+        //
+        // Get as much data as we can.
+        //
+        ulCount = ulLength;
+        lRetcode = MAP_USBEndpointDataGet(psInst->ulUSBBase,
+                                          psInst->ucOUTEndpoint,
+                                          pcData, &ulCount);
+
+        //
+        // Did we read the last of the packet data?
+        //
+        if(ulCount == ulPkt)
+        {
+            //
+            // Clear the endpoint status so that we know no packet is
+            // waiting.
+            //
+            MAP_USBDevEndpointStatusClear(psInst->ulUSBBase,
+                                          psInst->ucOUTEndpoint,
+                                          ulEPStatus);
+
+            //
+            // Acknowledge the data, thus freeing the host to send the
+            // next packet.
+            //
+            MAP_USBDevEndpointDataAck(psInst->ulUSBBase, psInst->ucOUTEndpoint,
+                                      true);
+
+            //
+            // Clear the flag we set to indicate that a packet read is
+            // pending.
+            //
+            SetDeferredOpFlag(&psInst->usDeferredOpFlags,
+                              HID_DO_PACKET_RX, false);
+        }
+
+        //
+        // If all went well, tell the caller how many bytes they got.
+        //
+        if(lRetcode != -1)
+        {
+            return(ulCount);
+        }
+    }
+
+    //
+    // No packet was available or an error occurred while reading so tell
+    // the caller no bytes were returned.
+    //
+    return(0);
+}
+
+//*****************************************************************************
+//
+//! Returns the number of free bytes in the transmit buffer.
+//!
+//! \param pvInstance is the pointer to the device instance structure as
+//! returned by USBDHIDInit().
+//!
+//! This function indicates to the caller whether or not it is safe to send a
+//! new report using a call to USBDHIDReportWrite().  The value returned will
+//! be the maximum USB packet size (64) if no transmission is currently
+//! outstanding or 0 if a transmission is in progress.  Since the function
+//! USBDHIDReportWrite() can accept full reports longer than a single USB
+//! packet, the caller should be aware that the returned value from this
+//! class driver, unlike others, does not indicate the maximum size of report
+//! that can be written but is merely an indication that another report can be
+//! written.
+//!
+//! \return Returns 0 if an outgoing report is still being transmitted or 64
+//! if no transmission is currently in progress.
+//
+//*****************************************************************************
+unsigned long
+USBDHIDTxPacketAvailable(void *pvInstance)
+{
+    tHIDInstance *psInst;
+
+    ASSERT(pvInstance);
+
+    //
+    // Get our instance data pointer.
+    //
+    psInst = ((tUSBDHIDDevice *)pvInstance)->psPrivateHIDData;
+
+    //
+    // Do we have a packet transmission currently ongoing?
+    //
+    if(psInst->eHIDTxState != HID_STATE_IDLE)
+    {
+        //
+        // We are not ready to receive a new packet so return 0.
+        //
+        return(0);
+    }
+    else
+    {
+        //
+        // We can receive a packet so return the max packet size for the
+        // relevant endpoint.
+        //
+        return(INT_IN_EP_MAX_SIZE);
+    }
+}
+
+//*****************************************************************************
+//
+//! Determines whether a packet is available and, if so, the size of the
+//! buffer required to read it.
+//!
+//! \param pvInstance is the pointer to the device instance structure as
+//! returned by USBDHIDInit().
+//!
+//! This function may be used to determine if a received packet remains to be
+//! read and allows the application to determine the buffer size needed to
+//! read the data.
+//!
+//! \return Returns 0 if no received packet remains unprocessed or the
+//! size of the packet if a packet is waiting to be read.
+//
+//*****************************************************************************
+unsigned long
+USBDHIDRxPacketAvailable(void *pvInstance)
+{
+    unsigned long ulEPStatus;
+    unsigned long ulSize;
+    tHIDInstance *psInst;
+
+    ASSERT(pvInstance);
+
+    //
+    // Get our instance data pointer
+    //
+    psInst = ((tUSBDHIDDevice *)pvInstance)->psPrivateHIDData;
+
+    //
+    // Does the relevant endpoint FIFO have a packet waiting for us?
+    //
+    ulEPStatus = MAP_USBEndpointStatus(psInst->ulUSBBase,
+                                       psInst->ucOUTEndpoint);
+    if(ulEPStatus & USB_DEV_RX_PKT_RDY)
+    {
+        //
+        // Yes - a packet is waiting.  How big is it?
+        //
+        ulSize = MAP_USBEndpointDataAvail(psInst->ulUSBBase,
+                                          psInst->ucOUTEndpoint);
+
+        return(ulSize);
+    }
+    else
+    {
+        //
+        // There is no packet waiting to be received.
+        //
+        return(0);
+    }
+}
+
+//*****************************************************************************
+//
+//! Reports the device power status (bus- or self-powered) to the USB library.
+//!
+//! \param pvInstance is the pointer to the HID device instance structure.
+//! \param ucPower indicates the current power status, either \b
+//! USB_STATUS_SELF_PWR or \b USB_STATUS_BUS_PWR.
+//!
+//! Applications which support switching between bus- or self-powered
+//! operation should call this function whenever the power source changes
+//! to indicate the current power status to the USB library.  This information
+//! is required by the USB library to allow correct responses to be provided
+//! when the host requests status from the device.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDHIDPowerStatusSet(void *pvInstance, unsigned char ucPower)
+{
+    ASSERT(pvInstance);
+
+    //
+    // Pass the request through to the lower layer.
+    //
+    USBDCDPowerStatusSet(0, ucPower);
+}
+
+//*****************************************************************************
+//
+//! Requests a remote wake up to resume communication when in suspended state.
+//!
+//! \param pvInstance is the pointer to the HID device instance structure.
+//!
+//! When the bus is suspended, an application which supports remote wake up
+//! (advertised to the host via the configuration descriptor) may call this
+//! function to initiate remote wake up signaling to the host.  If the remote
+//! wake up feature has not been disabled by the host, this will cause the bus
+//! to resume operation within 20mS.  If the host has disabled remote wake up,
+//! \b false will be returned to indicate that the wake up request was not
+//! successful.
+//!
+//! \return Returns \b true if the remote wake up is not disabled and the
+//! signaling was started or \b false if remote wake up is disabled or if
+//! signaling is currently ongoing following a previous call to this function.
+//
+//*****************************************************************************
+tBoolean
+USBDHIDRemoteWakeupRequest(void *pvInstance)
+{
+    ASSERT(pvInstance);
+
+    //
+    // Pass the request through to the lower layer.
+    //
+    return(USBDCDRemoteWakeupRequest(0));
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/src/platform/lm3s/usblib/device/usbdhid.h b/src/platform/lm3s/usblib/device/usbdhid.h
new file mode 100755
index 00000000..e53fb5d9
--- /dev/null
+++ b/src/platform/lm3s/usblib/device/usbdhid.h
@@ -0,0 +1,974 @@
+//*****************************************************************************
+//
+// usbdhid.h - Definitions used by HID class devices.
+//
+// Copyright (c) 2008-2011 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 7611 of the Stellaris USB Library.
+//
+//*****************************************************************************
+
+#ifndef __USBDHID_H__
+#define __USBDHID_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+//! \addtogroup hid_device_class_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! The size of the memory that should be allocated to create a configuration
+//! descriptor for a single instance of the USB HID Device.
+//! This does not include the configuration descriptor which is automatically
+//! ignored by the composite device class.
+//
+// For reference this is
+// sizeof(g_sHIDInterfaceSection) +  sizeof(g_sHIDDescriptorSection) +
+// sizeof(g_sHIDInEndpointSection) + sizeof(g_sHIDOutEndpointSection)
+//
+//*****************************************************************************
+#define COMPOSITE_DHID_SIZE     (32)
+
+//*****************************************************************************
+//
+// Macros used to create the static Report Descriptors.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! This is a macro to assist adding Usage Page entries in HID report
+//! descriptors.
+//!
+//! \param ucValue is the Usage Page value.
+//!
+//! This macro takes a value and prepares it to be placed as a Usage Page entry
+//! into a HID report structure.  These are defined by the USB HID
+//! specification.
+//!
+//! \return Not a function.
+//
+//*****************************************************************************
+#define UsagePage(ucValue)      0x05, ((ucValue) & 0xff)
+
+//*****************************************************************************
+//
+//! This is a macro to assist adding Usage entries in HID report descriptors.
+//!
+//! \param ucValue is the Usage value.
+//!
+//! This macro takes a value and prepares it to be placed as a Usage entry into
+//! a HID report structure.  These are defined by the USB HID specification.
+//!
+//! \return Not a function.
+//
+//*****************************************************************************
+#define Usage(ucValue)          0x09, ((ucValue) & 0xff)
+
+//*****************************************************************************
+//
+//! This is a macro to assist adding Usage Minimum entries in HID report
+//! descriptors.
+//!
+//! \param ucValue is the Usage Minimum value.
+//!
+//! This macro takes a value and prepares it to be placed as a Usage Minimum
+//! entry into a HID report structure.  This is the first or minimum value
+//! associated with a usage value.
+//!
+//! \return Not a function.
+//
+//*****************************************************************************
+#define UsageMinimum(ucValue)   0x19, ((ucValue) & 0xff)
+
+//*****************************************************************************
+//
+//! This is a macro to assist adding Usage Maximum entries in HID report
+//! descriptors.
+//!
+//! \param ucValue is the Usage Maximum value.
+//!
+//! This macro takes a value and prepares it to be placed as a Usage Maximum
+//! entry into a HID report structure.  This is the last or maximum value
+//! associated with a usage value.
+//!
+//! \return Not a function.
+//
+//*****************************************************************************
+#define UsageMaximum(ucValue)   0x29, ((ucValue) & 0xff)
+
+//*****************************************************************************
+//
+//! This is a macro to assist adding Logical Minimum entries in HID report
+//! descriptors.
+//!
+//! \param cValue is the Logical Minimum value.
+//!
+//! This macro takes a value and prepares it to be placed as a Logical Minimum
+//! entry into a HID report structure.  This is the actual minimum value for a
+//! range of values associated with a field.
+//!
+//! \return Not a function.
+//
+//*****************************************************************************
+#define LogicalMinimum(cValue)  0x15, ((cValue) & 0xff)
+
+//*****************************************************************************
+//
+//! This is a macro to assist adding Logical Maximum entries in HID report
+//! descriptors.
+//!
+//! \param cValue is the Logical Maximum value.
+//!
+//! This macro takes a value and prepares it to be placed as a Logical Maximum
+//! entry into a HID report structure.  This is the actual maximum value for a
+//! range of values associated with a field.
+//!
+//! \return Not a function.
+//
+//*****************************************************************************
+#define LogicalMaximum(cValue)  0x25, ((cValue) & 0xff)
+
+//*****************************************************************************
+//
+//! This is a macro to assist adding Physical Minimum entries in HID report
+//! descriptors.
+//!
+//! \param sValue is the Physical Minimum value.  It is a signed, 16 bit
+//! number.
+//!
+//! This macro takes a value and prepares it to be placed as a Physical Minimum
+//! entry into a HID report structure.  This is value is used in conversion of
+//! the control logical value, as returned to the host in the relevant report,
+//! to a physical measurement in the appropriate units.
+//!
+//! \return Not a function.
+//
+//*****************************************************************************
+#define PhysicalMinimum(sValue) 0x36, ((sValue) & 0xFF),                      \
+                                (((sValue) >> 8) & 0xFF)
+
+//*****************************************************************************
+//
+//! This is a macro to assist adding Physical Maximum entries in HID report
+//! descriptors.
+//!
+//! \param sValue is the Physical Maximum value.  It is a signed, 16 bit
+//! number.
+//!
+//! This macro takes a value and prepares it to be placed as a Physical Maximum
+//! entry into a HID report structure.  This is value is used in conversion of
+//! the control logical value, as returned to the host in the relevant report,
+//! to a physical measurement in the appropriate units.
+//!
+//! \return Not a function.
+//
+//*****************************************************************************
+#define PhysicalMaximum(sValue) 0x46, ((sValue) & 0xFF),                      \
+                                (((sValue) >> 8) & 0xFF)
+
+//*****************************************************************************
+//
+//! This is a macro to assist adding Collection entries in HID report
+//! descriptors.
+//!
+//! \param ucValue is the type of Collection.
+//!
+//! This macro takes a value and prepares it to be placed as a Collection
+//! entry into a HID report structure.  This is the type of values that are
+//! being grouped together, for instance input, output or features can be
+//! grouped together as a collection.
+//!
+//! \return Not a function.
+//
+//*****************************************************************************
+#define Collection(ucValue)     0xa1, ((ucValue) & 0xff)
+
+//*****************************************************************************
+//
+//! This is a macro to assist adding End Collection entries in HID report
+//! descriptors.
+//!
+//! This macro can be used to place an End Collection entry into a HID report
+//! structure.  This is a tag to indicate that a collection of entries has
+//! ended in the HID report structure.  This terminates a previous Collection()
+//! entry.
+//!
+//! \return Not a function.
+//
+//*****************************************************************************
+#define EndCollection           0xc0
+
+//*****************************************************************************
+//
+//! This is a macro to assist adding Report Count entries in HID report
+//! descriptors.
+//!
+//! \param ucValue is the number of items in a report item.
+//!
+//! This macro takes a value and prepares it to be placed as a Report Count
+//! entry into a HID report structure.  This is number of entries of Report
+//! Size for a given item.
+//!
+//! \return Not a function.
+//
+//*****************************************************************************
+#define ReportCount(ucValue)    0x95, ((ucValue) & 0xff)
+
+//*****************************************************************************
+//
+//! This is a macro to assist adding Report ID entries in HID report
+//! descriptors.
+//!
+//! \param ucValue is the identifier prefix for the current report.
+//!
+//! This macro takes a value and prepares it to be placed as a Report ID
+//! entry into a HID report structure.  This value is used as a 1 byte prefix
+//! for the report it is contained within.
+//!
+//! \return Not a function.
+//
+//*****************************************************************************
+#define ReportID(ucValue)       0x85, ((ucValue) & 0xff)
+
+//*****************************************************************************
+//
+//! This is a macro to assist adding Report Size entries in HID report
+//! descriptors.
+//!
+//! \param ucValue is the size, in bits, of items in a report item.
+//!
+//! This macro takes a value and prepares it to be placed as a Report Size
+//! entry into a HID report structure.  This is size in bits of the entries of
+//! of a report entry.  The Report Count specifies how many entries of Report
+//! Size are in a given item.  These can be individual bits or bit fields.
+//!
+//! \return Not a function.
+//
+//*****************************************************************************
+#define ReportSize(ucValue)     0x75, ((ucValue) & 0xff)
+
+//*****************************************************************************
+//
+//! This is a macro to assist adding Input entries in HID report descriptors.
+//!
+//! \param ucValue is bit mask to specify the type of a set of input report
+//! items.  Note that if the USB_HID_INPUT_BITF flag is required, the Input2
+//! macro (which uses a 2 byte version of the Input item tag) must be used
+//! instead of this macro.
+//!
+//! This macro takes a value and prepares it to be placed as an Input entry
+//! into a HID report structure.  This specifies the type of an input item in
+//! a report structure.  These refer to a bit mask of flags that indicate the
+//! type of input for a set of items.
+//!
+//! \return Not a function.
+//
+//*****************************************************************************
+#define Input(ucValue)          0x81, ((ucValue) & 0xff)
+
+//*****************************************************************************
+//
+//! This is a macro to assist adding Input entries in HID report descriptors.
+//!
+//! \param usValue is bit mask to specify the type of a set of input report
+//! items.  Note that this macro uses a version of the Input item tag with a
+//! two byte payload and allows any of the 8 possible data bits for the tag to
+//! be used.  If USB_HID_INPUT_BITF (bit 8) is not required, the Input macro
+//! may be used instead.
+//!
+//! This macro takes a value and prepares it to be placed as an Input entry
+//! into a HID report structure.  This specifies the type of an input item in
+//! a report structure.  These refer to a bit mask of flags that indicate the
+//! type of input for a set of items.
+//!
+//! \return Not a function.
+//
+//*****************************************************************************
+#define Input2(usValue)         0x82, ((usValue) & 0xff),                     \
+                                (((usValue) >> 8) & 0xFF)
+
+//*****************************************************************************
+//
+//! This is a macro to assist adding Feature entries in HID report descriptors.
+//!
+//! \param ucValue is bit mask to specify the type of a set of feature report
+//! items.  Note that if the USB_HID_FEATURE_BITF flag is required, the
+//! Feature2 macro (which uses a 2 byte version of the Feature item tag) must
+//! be used instead of this macro.
+//!
+//! This macro takes a value and prepares it to be placed as a Feature entry
+//! into a HID report structure.  This specifies the type of a feature item in
+//! a report structure.  These refer to a bit mask of flags that indicate the
+//! type of feature for a set of items.
+//!
+//! \return Not a function.
+//
+//*****************************************************************************
+#define Feature(ucValue)        0xB1, ((ucValue) & 0xff)
+
+//*****************************************************************************
+//
+//! This is a macro to assist adding Feature entries in HID report descriptors.
+//!
+//! \param usValue is bit mask to specify the type of a set of feature report
+//! items.  Note that this macro uses a version of the Feature item tag with a
+//! two byte payload and allows any of the 8 possible data bits for the tag to
+//! be used.  If USB_HID_FEATURE_BITF (bit 8) is not required, the Feature
+//! macro may be used instead.
+//!
+//! This macro takes a value and prepares it to be placed as a Feature entry
+//! into a HID report structure.  This specifies the type of a feature item in
+//! a report structure.  These refer to a bit mask of flags that indicate the
+//! type of feature for a set of items.
+//!
+//! \return Not a function.
+//
+//*****************************************************************************
+#define Feature2(usValue)       0xB2, ((usValue) & 0xff),                     \
+                                (((usValue) >> 8) & 0xFF)
+
+//*****************************************************************************
+//
+//! This is a macro to assist adding Output entries in HID report descriptors.
+//!
+//! \param ucValue is bit mask to specify the type of a set of output report
+//! items.  Note that if the USB_HID_OUTPUT_BITF flag is required, the Output2
+//! macro (which uses a 2 byte version of the Output item tag) must be used
+//! instead of this macro.
+//!
+//! This macro takes a value and prepares it to be placed as an Output entry
+//! into a HID report structure.  This specifies the type of an output item in
+//! a report structure.  These refer to a bit mask of flags that indicate the
+//! type of output for a set of items.
+//!
+//! \return Not a function.
+//
+//*****************************************************************************
+#define Output(ucValue)         0x91, ((ucValue) & 0xff)
+
+//*****************************************************************************
+//
+//! This is a macro to assist adding Output entries in HID report descriptors.
+//!
+//! \param usValue is bit mask to specify the type of a set of output report
+//! items.  Note that this macro uses a version of the Output item tag with a
+//! two byte payload and allows any of the 8 possible data bits for the tag to
+//! be used.  If USB_HID_OUTPUT_BITF (bit 8) is not required, the Output macro
+//! may be used instead.
+//!
+//! This macro takes a value and prepares it to be placed as an Output entry
+//! into a HID report structure.  This specifies the type of an output item in
+//! a report structure.  These refer to a bit mask of flags that indicate the
+//! type of output for a set of items.
+//!
+//! \return Not a function.
+//
+//*****************************************************************************
+#define Output2(usValue)        0x92, ((usValue) & 0xff),                     \
+                                (((usValue) >> 8) & 0xFF)
+
+//*****************************************************************************
+//
+//! This is a macro to assist adding Unit Exponent entries in HID report
+//! descriptors.
+//!
+//! \param cValue is the required exponent in the range [-8, 7].
+//!
+//! This macro takes a value and prepares it to be placed as a Unit Exponent
+//! entry into a HID report structure.  This is the exponent applied to
+//! PhysicalMinimum and PhysicalMaximum when scaling and converting control
+//! values to "real" units.
+//!
+//! \return Not a function.
+//
+//*****************************************************************************
+#define UnitExponent(cValue)    0x55, ((cValue) & 0x0f)
+
+//*****************************************************************************
+//
+//! This is a macro to assist adding Unit entries for uncommon units in HID
+//! report descriptors.
+//!
+//! \param ulValue is the definition of the unit required as defined in section
+//! 6.2.2.7 of the USB HID device class definition document.
+//!
+//! This macro takes a value and prepares it to be placed as a Unit entry into
+//! a HID report structure.  Note that individual macros are defined for common
+//! units and this macro is intended for use when a complex or uncommon unit
+//! is needed.  It allows entry of a 5 nibble unit definition into the report
+//! descriptor.
+//!
+//! \return Not a function.
+//
+//*****************************************************************************
+#define Unit(ulValue)           0x67, (ulValue) & 0x0f),                      \
+                                (((ulValue) >> 8) & 0xFF),                    \
+                                (((ulValue) >> 16) & 0xFF),                   \
+                                (((ulValue) >> 24) & 0xFF)
+
+//*****************************************************************************
+//
+//! This macro inserts a Unit entry for centimeters into a report descriptor.
+//!
+//*****************************************************************************
+#define UnitDistance_cm         0x66, 0x11, 0x00
+
+//*****************************************************************************
+//
+//! This macro inserts a Unit entry for inches into a report descriptor.
+//!
+//*****************************************************************************
+#define UnitDistance_i          0x66, 0x13, 0x00
+
+//*****************************************************************************
+//
+//! This macro inserts a Unit entry for degrees into a report descriptor.
+//!
+//*****************************************************************************
+#define UnitRotation_deg        0x66, 0x14, 0x00
+
+//*****************************************************************************
+//
+//! This macro inserts a Unit entry for radians into a report descriptor.
+//!
+//*****************************************************************************
+#define UnitRotation_rad        0x66, 0x12, 0x00
+
+//*****************************************************************************
+//
+//! This macro inserts a Unit entry for grams into a report descriptor.
+//!
+//*****************************************************************************
+#define UnitMass_g              0x66, 0x01, 0x01
+
+//*****************************************************************************
+//
+//! This macro inserts a Unit entry for seconds into a report descriptor.
+//!
+//*****************************************************************************
+#define UnitTime_s              0x66, 0x01, 0x10
+
+//*****************************************************************************
+//
+//! This macro inserts a Unit entry for temperature in Kelvin into a report
+//! descriptor.
+//!
+//*****************************************************************************
+#define UnitTemp_K              0x67, 0x01, 0x00, 0x01, 0x00
+
+//*****************************************************************************
+//
+//! This macro inserts a Unit entry for temperature in Fahrenheit into a report
+//! descriptor.
+//!
+//*****************************************************************************
+#define UnitTemp_F              0x67, 0x03, 0x00, 0x01, 0x00
+
+//*****************************************************************************
+//
+//! This macro inserts a Unit entry for velocity in cm/s into a report
+//! descriptor.
+//!
+//*****************************************************************************
+#define UnitVelocitySI          0x66, 0x11, 0xF0
+
+//*****************************************************************************
+//
+//! This macro inserts a Unit entry for momentum in (grams * cm)/s into a
+//! report descriptor.
+//!
+//*****************************************************************************
+#define UnitMomentumSI          0x66, 0x11, 0xF1
+
+//*****************************************************************************
+//
+//! This macro inserts a Unit entry for acceleration in cm/s**2 into a
+//! report descriptor.
+//!
+//*****************************************************************************
+#define UnitAccelerationSI      0x66, 0x11, 0xE0
+
+//*****************************************************************************
+//
+//! This macro inserts a Unit entry for force in (cm * grams)/s**2 into a
+//! report descriptor.
+//!
+//*****************************************************************************
+#define UnitForceSI             0x66, 0x11, 0xE1
+
+//*****************************************************************************
+//
+//! This macro inserts a Unit entry for energy in (grams * cm**2)/s**2 into a
+//! report descriptor.
+//!
+//*****************************************************************************
+#define UnitEnergySI            0x66, 0x21, 0xE1
+
+//*****************************************************************************
+//
+//! This macro inserts a Unit entry for angular acceleration in degrees/s**2
+//! into a report descriptor.
+//!
+//*****************************************************************************
+#define UnitAngAccelerationSI   0x66, 0x12, 0xE0
+
+//*****************************************************************************
+//
+//! This macro inserts a Unit entry for voltage into a a report descriptor.
+//!
+//*****************************************************************************
+#define UnitVoltage             0x67, 0x21, 0xD1, 0xF0, 0x00
+
+//*****************************************************************************
+//
+//! This macro inserts a Unit entry for voltage into a a report descriptor.
+//!
+//*****************************************************************************
+#define UnitCurrent_A           0x67, 0x01, 0x00, 0x10, 0x00
+
+//*****************************************************************************
+//
+// PRIVATE
+//
+// The first few sections of this header are private defines that are used by
+// the USB HID code and are here only to help with the application
+// allocating the correct amount of memory for the HID device code.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// PRIVATE
+//
+// This enumeration holds the various states that the device can be in during
+// normal operation.
+//
+//*****************************************************************************
+typedef enum
+{
+    //
+    // Unconfigured.
+    //
+    HID_STATE_UNCONFIGURED,
+
+    //
+    // No outstanding transaction remains to be completed.
+    //
+    HID_STATE_IDLE,
+
+    //
+    // Waiting on completion of a send or receive transaction.
+    //
+    HID_STATE_WAIT_DATA
+}
+tHIDState;
+
+//*****************************************************************************
+//
+// PRIVATE
+//
+// This structure defines the private instance data and state variables for
+// HID devices.  The memory for this structure is pointed to by the
+// psPrivateHIDData field in the tUSBDHIDDevice structure passed in the
+// USBDHIDInit() function.
+//
+//*****************************************************************************
+typedef struct
+{
+    unsigned long ulUSBBase;
+    tDeviceInfo *psDevInfo;
+    tConfigDescriptor *psConfDescriptor;
+    volatile tHIDState eHIDRxState;
+    volatile tHIDState eHIDTxState;
+    volatile unsigned short usDeferredOpFlags;
+    unsigned short usInReportSize;
+    unsigned short usInReportIndex;
+    unsigned short usOutReportSize;
+    unsigned char *pucInReportData;
+    unsigned char *pucOutReportData;
+    volatile tBoolean bConnected;
+    volatile tBoolean bSendInProgress;
+    tBoolean bGetRequestPending;
+    unsigned char ucINEndpoint;
+    unsigned char ucOUTEndpoint;
+    unsigned char ucInterface;
+}
+tHIDInstance;
+
+#ifndef DEPRECATED
+//*****************************************************************************
+//
+// The number of bytes of workspace required by the HID device class driver.
+// The client must provide a block of RAM of at least this size in the
+// pvWorkspace field of the tUSBDHIDDevice structure passed on USBDHIDInit.
+//
+//*****************************************************************************
+#define USB_HID_WORKSPACE_SIZE  sizeof(tHIDInstance)
+#endif
+
+//*****************************************************************************
+//
+//! The structure used to track idle time for reports.  An array of these
+//! structures is passed to the HID device class driver during USBDHIDInit and
+//! is used to track automatic resending of each report (if not disabled by
+//! the host).
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! The idle duration for the report expressed in units of 4mS.  0
+    //! indicates infinite and informs the class driver not to send the report
+    //! unless a state change occurs.
+    //
+    unsigned char ucDuration4mS;
+
+    //
+    //! The ID of the report which this structure applies to.  This is the
+    //! report ID as specified using a ReportID tag in the report descriptor
+    //! rather than the index of the report in the HID class descriptor array.
+    //! If only a single Input report is supported and, thus, no ReportID tag
+    //! is present, this field should be set to 0.
+    //
+    unsigned char ucReportID;
+
+    //
+    //! The number of milliseconds before we need to send a copy of a given
+    //! report back to the host.  This field is updated by the HID driver and
+    //! used to time sending of USBD_HID_EVENT_IDLE_TIMEOUT.
+    //
+    unsigned short usTimeTillNextmS;
+
+    //
+    //! The number of milliseconds that have passed since the last time this
+    //! report was sent.  The HID class driver needs to track this since
+    //! Set_Idle requests are required to take effect as if issued immediately
+    //! after the last transmission of the report to which they refer.
+    //
+    unsigned long ulTimeSinceReportmS;
+}
+tHIDReportIdle;
+
+//*****************************************************************************
+//
+//! The structure used by the application to define operating parameters for
+//! the HID device.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! The vendor ID that this device is to present in the device descriptor.
+    //
+    unsigned short usVID;
+
+    //
+    //! The product ID that this device is to present in the device descriptor.
+    //
+    unsigned short usPID;
+
+    //
+    //! The maximum power consumption of the device, expressed in milliamps.
+    //
+    unsigned short usMaxPowermA;
+
+    //
+    //! Indicates whether the device is self- or bus-powered and whether or not
+    //! it supports remote wakeup.  Valid values are USB_CONF_ATTR_SELF_PWR or
+    //! USB_CONF_ATTR_BUS_PWR, optionally ORed with USB_CONF_ATTR_RWAKE.
+    //
+    unsigned char ucPwrAttributes;
+
+    //
+    //! The interface subclass to publish to the server for this HID device.
+    //
+    unsigned char ucSubclass;
+
+    //
+    //! The interface protocol to publish to the server for this HID device.
+    //
+    unsigned char ucProtocol;
+
+    //
+    //! The number of Input reports that this device supports.  This field
+    //! must equal the number of reports published in the HID class descriptors
+    //! for the device and also the number of entries in the array whose first
+    //! element is pointed to by field psReportIdle below.
+    //
+    unsigned char ucNumInputReports;
+
+    //
+    //! A pointer to the first element in an array of structures used to track
+    //! idle time for each Input report.  When USBDHIDInit is called, the
+    //! ucDuration4mS and ucReportID fields of each of these array members
+    //! should be initialized to indicate the default idle timeout for each
+    //! input report.  This array must be in RAM since the HID device class
+    //! driver will update values in it in response to requests from the host
+    //! and to track elapsed time.  The number of elements in the array must
+    //! match the number supplied in the ucNumInputReports field above.
+    //
+    tHIDReportIdle *psReportIdle;
+
+    //! A pointer to the callback function which will be called to notify
+    //! the application of general events, events related to report transfers
+    //! on endpoint zero and events related to reception of Output and Feature
+    //! reports via the (optional) interrupt OUT endpoint.
+    //
+    tUSBCallback pfnRxCallback;
+
+    //
+    //! A client-supplied pointer which will be sent as the first
+    //! parameter in all calls made to the receive channel callback,
+    //! pfnRxCallback.
+    //
+    void *pvRxCBData;
+
+    //
+    //! A pointer to the callback function which will be called to notify
+    //! the application of events related to transmission of Input reports
+    //! via the interrupt IN endpoint.
+    //
+    tUSBCallback pfnTxCallback;
+
+    //
+    //! A client-supplied pointer which will be sent as the first
+    //! parameter in all calls made to the transmit channel callback,
+    //! pfnTxCallback.
+    //
+    void *pvTxCBData;
+
+    //
+    //! If set to true, this field indicates that the device should use a
+    //! dedicated interrupt OUT endpoint to receive reports from the host.  In
+    //! this case, reports from the host are passed to the application via the
+    //! receive callback using USB_EVENT_RX_AVAILABLE events.  If false,
+    //! reports from the host are received via endpoint zero and passed to the
+    //! application via USBD_HID_EVENT_REPORT_SENT events.
+    //
+    tBoolean bUseOutEndpoint;
+
+    //
+    //! The HID descriptor that the device is to publish (following the
+    //! standard interface descriptor and prior to the endpoint descriptors for
+    //! the interface).
+    //
+    const tHIDDescriptor *psHIDDescriptor;
+
+    //
+    //! The HID class descriptors offered by the device are defined in an
+    //! array of byte pointers and this field points to that array.  The
+    //! order and number of elements in the array must match the associated
+    //! information provided in the HID descriptor in field by psHIDDescriptor.
+    //
+    const unsigned char * const *ppClassDescriptors;
+
+    //
+    //! A pointer to the string descriptor array for this device.  This array
+    //! must contain the following string descriptor pointers in this order.
+    //! Language descriptor, Manufacturer name string (language 1), Product
+    //! name string (language 1), Serial number string (language 1),HID
+    //! Interface description string (language 1), Configuration description
+    //! string (language 1), (optionally) First HID device-specific string
+    //! (language 1), (optionally) Second HID device-specific string (language
+    //! 1), etc.
+    //!
+    //! If supporting more than 1 language, the descriptor block (except for
+    //! string descriptor 0) must be repeated for each language defined in the
+    //! language descriptor.
+    //!
+    //! The number of HID device-specific strings is dependent upon the content
+    //! of the report descriptor passed to the interface and is, thus,
+    //! application controlled.
+    //
+    const unsigned char * const *ppStringDescriptors;
+
+    //
+    //! The number of descriptors provided in the ppStringDescriptors
+    //! array.  This must be 1 + ((5 + (num HID strings)) * (num languages)).
+    //
+    unsigned long ulNumStringDescriptors;
+
+    //
+    //! A pointer to private instance data for this device instance.  This
+    //! memory must remain accessible for as long as the HID device is in use
+    //! and must not be modified by any code outside the HID class driver.
+    //
+    tHIDInstance *psPrivateHIDData;
+}
+tUSBDHIDDevice;
+
+//*****************************************************************************
+//
+// HID-specific device class driver events
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! This event indicates that the host is requesting a particular report be
+//! returned via endpoint 0, the control endpoint.  The ulMsgValue parameter
+//! contains the requested report type in the high byte and report ID in the
+//! low byte (as passed in the wValue field of the USB request structure).
+//! The pvMsgData parameter contains a pointer which must be written with the
+//! address of the first byte of the requested report.  The callback must
+//! return the size in bytes of the report pointed to by *pvMsgData.  The
+//! memory returned in response to this event must remain unaltered until
+//! USBD_HID_EVENT_REPORT_SENT is sent.
+//
+//*****************************************************************************
+#define USBD_HID_EVENT_GET_REPORT                                             \
+                                (USBD_HID_EVENT_BASE + 0)
+
+//*****************************************************************************
+//
+//! This event indicates that a report previously requested via a
+//! USBD_HID_EVENT_GET_REPORT has been successfully transmitted to the host.
+//! The application may now free or reuse the report memory passed on the
+//! previous event.  Although this would seem to be an event that would be
+//! passed to the transmit channel callback, it is actually passed to the
+//! receive channel callback.  This ensures that all events related to the
+//! request and transmission of reports via endpoint zero can be handled in
+//! a single function.
+//
+//*****************************************************************************
+#define USBD_HID_EVENT_REPORT_SENT                                            \
+                                (USBD_HID_EVENT_BASE + 1)
+
+//*****************************************************************************
+//
+//! This event indicates that the host has sent a Set_Report request to
+//! the device and requests that the device provide a buffer into which the
+//! report can be written.  The ulMsgValue parameter contains the received
+//! report type in the high byte and report ID in the low byte (as passed in
+//! the wValue field of the USB request structure).  The pvMsgData parameter
+//! contains the length of buffer requested.  Note that this is the actual
+//! length value cast to a "void *" type and not a pointer in this case.
+//! The callback must return a pointer to a suitable buffer (cast to the
+//! standard "unsigned long" return type for the callback).
+//
+//*****************************************************************************
+#define USBD_HID_EVENT_GET_REPORT_BUFFER                                      \
+                                (USBD_HID_EVENT_BASE + 2)
+
+//*****************************************************************************
+//
+//! This event indicates that the host has sent the device a report via
+//! endpoint 0, the control endpoint.  The ulMsgValue field indicates the
+//! size of the report and pvMsgData points to the first byte of the report.
+//! The report buffer will previously have been returned in response to an
+//! earlier USBD_HID_EVENT_GET_REPORT_BUFFER callback.  The HID device class
+//! driver will not access the memory pointed to by pvMsgData after this
+//! callback is made so the application is free to reuse or free it at this
+//! point.
+//
+//*****************************************************************************
+#define USBD_HID_EVENT_SET_REPORT                                             \
+                                (USBD_HID_EVENT_BASE + 3)
+
+//*****************************************************************************
+//
+//! This event is sent in response to a Get_Protocol request from the host.
+//! The callback should provide the current protocol via the return code,
+//! USB_HID_PROTOCOL_BOOT or USB_HID_PROTOCOL_REPORT.
+//
+//*****************************************************************************
+#define USBD_HID_EVENT_GET_PROTOCOL                                           \
+                                (USBD_HID_EVENT_BASE + 4)
+
+//*****************************************************************************
+//
+//! This event is sent in response to a Set_Protocol request from the host.
+//! The ulMsgData value will contain the requested protocol,
+//! USB_HID_PROTOCOL_BOOT or USB_HID_PROTOCOL_REPORT.
+//
+//*****************************************************************************
+#define USBD_HID_EVENT_SET_PROTOCOL                                           \
+                                (USBD_HID_EVENT_BASE + 5)
+
+//*****************************************************************************
+//
+//! This event indicates to an application that a report idle timeout has
+//! occurred and requests a pointer to the report that must be sent back to
+//! the host.  The ulMsgData value will contain the requested report ID and
+//! pvMsgData contains a pointer that must be written with a pointer to the
+//! report data that is to be sent.  The callback must return the number of
+//! bytes in the report pointed to by *pvMsgData.
+//
+//*****************************************************************************
+#define USBD_HID_EVENT_IDLE_TIMEOUT                                           \
+                                (USBD_HID_EVENT_BASE + 6)
+
+extern tDeviceInfo g_sHIDDeviceInfo;
+
+//*****************************************************************************
+//
+// API Function Prototypes
+//
+//*****************************************************************************
+extern void *USBDHIDInit(unsigned long ulIndex,
+                         const tUSBDHIDDevice *psHIDDevice);
+extern void *USBDHIDCompositeInit(unsigned long ulIndex,
+                                  const tUSBDHIDDevice *psDevice);
+
+extern void USBDHIDTerm(void *pvInstance);
+extern void *USBDHIDSetRxCBData(void *pvInstance, void *pvCBData);
+extern void *USBDHIDSetTxCBData(void *pvInstance, void *pvCBData);
+extern unsigned long USBDHIDReportWrite(void *pvInstance,
+                                        unsigned char *pcData,
+                                        unsigned long ulLength,
+                                        tBoolean bLast);
+extern unsigned long USBDHIDPacketRead(void *pvInstance,
+                                       unsigned char *pcData,
+                                       unsigned long ulLength,
+                                       tBoolean bLast);
+extern unsigned long USBDHIDTxPacketAvailable(void *pvInstance);
+extern unsigned long USBDHIDRxPacketAvailable(void *pvInstance);
+extern void USBDHIDPowerStatusSet(void *pvInstance, unsigned char ucPower);
+extern tBoolean USBDHIDRemoteWakeupRequest(void *pvInstance);
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __USBDHID_H__
diff --git a/src/platform/lm3s/usblib/device/usbdhidkeyb.c b/src/platform/lm3s/usblib/device/usbdhidkeyb.c
new file mode 100755
index 00000000..c72a2c78
--- /dev/null
+++ b/src/platform/lm3s/usblib/device/usbdhidkeyb.c
@@ -0,0 +1,1119 @@
+//*****************************************************************************
+//
+// usbdhidkeyb.c - USB HID Keyboard device class driver.
+//
+// Copyright (c) 2008-2011 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 7611 of the Stellaris USB Library.
+//
+//*****************************************************************************
+
+#include "inc/hw_types.h"
+#include "driverlib/debug.h"
+#include "driverlib/usb.h"
+#include "usblib/usblib.h"
+#include "usblib/device/usbdevice.h"
+#include "usblib/usbhid.h"
+#include "usblib/device/usbdhid.h"
+#include "usblib/device/usbdhidkeyb.h"
+
+//*****************************************************************************
+//
+//! \addtogroup hid_keyboard_device_class_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// The following is the HID report structure definition that is passed back
+// to the host.
+//
+//*****************************************************************************
+static const unsigned char g_pucKeybReportDescriptor[]=
+{
+    UsagePage(USB_HID_GENERIC_DESKTOP),
+    Usage(USB_HID_KEYBOARD),
+    Collection(USB_HID_APPLICATION),
+
+        //
+        // Modifier keys.
+        // 8 - 1 bit values indicating the modifier keys (ctrl, shift...)
+        //
+        ReportSize(1),
+        ReportCount(8),
+        UsagePage(USB_HID_USAGE_KEYCODES),
+        UsageMinimum(224),
+        UsageMaximum(231),
+        LogicalMinimum(0),
+        LogicalMaximum(1),
+        Input(USB_HID_INPUT_DATA | USB_HID_INPUT_VARIABLE | USB_HID_INPUT_ABS),
+
+        //
+        // One byte of rsvd data required by HID spec.
+        //
+        ReportCount(1),
+        ReportSize(8),
+        Input(USB_HID_INPUT_CONSTANT),
+
+        //
+        // Keyboard LEDs.
+        // 5 - 1 bit values.
+        //
+        ReportCount(5),
+        ReportSize(1),
+        UsagePage(USB_HID_USAGE_LEDS),
+        UsageMinimum(1),
+        UsageMaximum(5),
+        Output(USB_HID_OUTPUT_DATA | USB_HID_OUTPUT_VARIABLE |
+               USB_HID_OUTPUT_ABS),
+        //
+        // 1 - 3 bit value to pad out to a full byte.
+        //
+        ReportCount(1),
+        ReportSize(3),
+        Output(USB_HID_OUTPUT_CONSTANT), //LED report padding
+
+        //
+        // The Key buffer.
+        // 6 - 8 bit values to store the current key state.
+        //
+        ReportCount(6),
+        ReportSize(8),
+        LogicalMinimum(0),
+        LogicalMaximum(101),
+        UsagePage(USB_HID_USAGE_KEYCODES),
+        UsageMinimum (0),
+        UsageMaximum (101),
+        Input(USB_HID_INPUT_DATA | USB_HID_INPUT_ARRAY),
+    EndCollection
+};
+
+//*****************************************************************************
+//
+// The HID class descriptor table.  For the keyboard class, we have only a
+// single report descriptor.
+//
+//*****************************************************************************
+static const unsigned char * const g_pKeybClassDescriptors[] =
+{
+    g_pucKeybReportDescriptor
+};
+
+//*****************************************************************************
+//
+// The HID descriptor for the keyboard device.
+//
+//*****************************************************************************
+static const tHIDDescriptor g_sKeybHIDDescriptor =
+{
+    9,                                     // bLength
+    USB_HID_DTYPE_HID,                     // bDescriptorType
+    0x111,                                 // bcdHID (version 1.11 compliant)
+    0,                                     // bCountryCode (not localized)
+    1,                                     // bNumDescriptors
+    {
+        {
+            USB_HID_DTYPE_REPORT,                  // Report descriptor
+            sizeof(g_pucKeybReportDescriptor)      // Size of report descriptor
+        }
+    }
+};
+
+//*****************************************************************************
+//
+// Forward references for keyboard device callback functions.
+//
+//*****************************************************************************
+static unsigned long HIDKeyboardRxHandler(void *pvCBData,
+                                          unsigned long ulEvent,
+                                          unsigned long ulMsgData,
+                                          void *pvMsgData);
+static unsigned long HIDKeyboardTxHandler(void *pvCBData,
+                                          unsigned long ulEvent,
+                                          unsigned long ulMsgData,
+                                          void *pvMsgData);
+
+//*****************************************************************************
+//
+// Main HID device class event handler function.
+//
+// \param pvCBData is the event callback pointer provided during USBDHIDInit().
+// This is a pointer to our HID device structure (&g_sHIDKeybDevice).
+// \param ulEvent identifies the event we are being called back for.
+// \param ulMsgData is an event-specific value.
+// \param pvMsgData is an event-specific pointer.
+//
+// This function is called by the HID device class driver to inform the
+// application of particular asynchronous events related to operation of the
+// keyboard HID device.
+//
+// \return Returns a value which is event-specific.
+//
+//*****************************************************************************
+static unsigned long
+HIDKeyboardRxHandler(void *pvCBData, unsigned long ulEvent,
+                     unsigned long ulMsgData, void *pvMsgData)
+{
+    tHIDKeyboardInstance *psInst;
+    tUSBDHIDKeyboardDevice *psDevice;
+
+    //
+    // Make sure we didn't get a NULL pointer.
+    //
+    ASSERT(pvCBData);
+
+    //
+    // Get a pointer to our instance data
+    //
+    psDevice = (tUSBDHIDKeyboardDevice *)pvCBData;
+    psInst = psDevice->psPrivateHIDKbdData;
+
+    //
+    // Which event were we sent?
+    //
+    switch (ulEvent)
+    {
+        //
+        // The host has connected to us and configured the device.
+        //
+        case USB_EVENT_CONNECTED:
+        {
+            psInst->ucUSBConfigured = true;
+
+            //
+            // Pass the information on to the client.
+            //
+            psDevice->pfnCallback(psDevice->pvCBData, USB_EVENT_CONNECTED,
+                                  0, (void *)0);
+
+            break;
+        }
+
+        //
+        // The host has disconnected from us.
+        //
+        case USB_EVENT_DISCONNECTED:
+        {
+            psInst->ucUSBConfigured = false;
+
+            //
+            // Pass the information on to the client.
+            //
+            psDevice->pfnCallback(psDevice->pvCBData, USB_EVENT_DISCONNECTED,
+                                  0, (void *)0);
+
+            break;
+        }
+
+        //
+        // The host is polling us for a particular report and the HID driver
+        // is asking for the latest version to transmit.
+        //
+        case USBD_HID_EVENT_IDLE_TIMEOUT:
+        case USBD_HID_EVENT_GET_REPORT:
+        {
+            //
+            // We only support a single input report so we don't need to check
+            // the ulMsgValue parameter in this case.  Set the report pointer
+            // in *pvMsgData and return the length of the report in bytes.
+            //
+            *(unsigned char **)pvMsgData = psInst->pucReport;
+            return(KEYB_IN_REPORT_SIZE);
+        }
+
+        //
+        // The device class driver has completed sending a report to the
+        // host in response to a Get_Report request.
+        //
+        case USBD_HID_EVENT_REPORT_SENT:
+        {
+            //
+            // We have nothing to do here.
+            //
+            break;
+        }
+
+        //
+        // This event is sent in response to a host Set_Report request.  We
+        // must return a pointer to a buffer large enough to receive the
+        // report into.
+        //
+        case USBD_HID_EVENT_GET_REPORT_BUFFER:
+        {
+            //
+            // Are we being asked for a report that is shorter than the storage
+            // we have set aside for this?  The only output report we define is
+            // 8 bits long so we really expect to see a length of 1 passed.
+            //
+            if((unsigned long)pvMsgData == KEYB_OUT_REPORT_SIZE )
+            {
+                //
+                // Yes - return our pointer.
+                //
+                return((unsigned long)psInst->pucDataBuffer);
+            }
+            else
+            {
+                //
+                // We are being passed a report that is longer than the
+                // only report we expect so return NULL.  This causes the
+                // device class driver to stall the request.
+                //
+                return(0);
+            }
+        }
+
+        //
+        // This event indicates that the host has sent us an Output or
+        // Feature report and that the report is now in the buffer we provided
+        // on the previous USBD_HID_EVENT_GET_REPORT_BUFFER callback.
+        //
+        case USBD_HID_EVENT_SET_REPORT:
+        {
+            //
+            // Inform the application if the keyboard LEDs have changed.
+            //
+            if(psInst->ucLEDStates != psInst->pucDataBuffer[0])
+            {
+                //
+                // Note the new LED states.
+                //
+                psInst->ucLEDStates = psInst->pucDataBuffer[0];
+
+                //
+                // Pass the information on to the client.
+                //
+                psDevice->pfnCallback(psDevice->pvCBData,
+                                      USBD_HID_KEYB_EVENT_SET_LEDS,
+                                      psInst->pucDataBuffer[0], (void *)0);
+            }
+            break;
+        }
+
+        //
+        // The host is asking us to set either boot or report protocol (not
+        // that it makes any difference to this particular mouse).
+        //
+        case USBD_HID_EVENT_SET_PROTOCOL:
+        {
+            psInst->ucProtocol = ulMsgData;
+            break;
+        }
+
+        //
+        // The host is asking us to tell it which protocol we are currently
+        // using, boot or request.
+        //
+        case USBD_HID_EVENT_GET_PROTOCOL:
+        {
+            return(psInst->ucProtocol);
+        }
+
+        //
+        // Pass ERROR, SUSPEND and RESUME to the client unchanged.
+        //
+        case USB_EVENT_ERROR:
+        case USB_EVENT_SUSPEND:
+        case USB_EVENT_RESUME:
+        {
+            return(psDevice->pfnCallback(psDevice->pvCBData, ulEvent,
+                                         ulMsgData, pvMsgData));
+        }
+
+        //
+        // We ignore all other events.
+        //
+        default:
+        {
+            break;
+        }
+    }
+    return(0);
+}
+
+//*****************************************************************************
+//
+// HID device class transmit channel event handler function.
+//
+// \param pvCBData is the event callback pointer provided during USBDHIDInit().
+// This is a pointer to our HID device structure (&g_sHIDKeybDevice).
+// \param ulEvent identifies the event we are being called back for.
+// \param ulMsgData is an event-specific value.
+// \param pvMsgData is an event-specific pointer.
+//
+// This function is called by the HID device class driver to inform the
+// application of particular asynchronous events related to report
+// transmissions made using the interrupt IN endpoint.
+//
+// \return Returns a value which is event-specific.
+//
+//*****************************************************************************
+static unsigned long
+HIDKeyboardTxHandler(void *pvCBData, unsigned long ulEvent,
+                     unsigned long ulMsgData, void *pvMsgData)
+{
+    tHIDKeyboardInstance *psInst;
+    tUSBDHIDKeyboardDevice *psDevice;
+    tUSBDHIDDevice *psHIDDevice;
+    unsigned long ulCount;
+
+    //
+    // Make sure we didn't get a NULL pointer.
+    //
+    ASSERT(pvCBData);
+
+    //
+    // Get a pointer to our instance data
+    //
+    psDevice = (tUSBDHIDKeyboardDevice *)pvCBData;
+    psInst = psDevice->psPrivateHIDKbdData;
+    psHIDDevice = &psDevice->psPrivateHIDKbdData->sHIDDevice;
+
+    //
+    // Which event were we sent?
+    //
+    switch (ulEvent)
+    {
+        //
+        // A report transmitted via the interrupt IN endpoint was acknowledged
+        // by the host.
+        //
+        case USB_EVENT_TX_COMPLETE:
+        {
+            //
+            // Do we have any pending changes needing transmitted?
+            //
+            if(psInst->bChangeMade)
+            {
+                //
+                // Yes - go ahead and send another report immediately.
+                //
+                ulCount = USBDHIDReportWrite((void *)psHIDDevice,
+                                             psInst->pucReport,
+                                             KEYB_IN_REPORT_SIZE, true);
+
+                //
+                // If we scheduled the report for transmission, clear the
+                // change flag.
+                //
+                if(ulCount != 0)
+                {
+                    psInst->bChangeMade = false;
+                }
+            }
+            else
+            {
+                //
+                // Our last transmission is complete and we have nothing more
+                // to send.
+                //
+                psInst->eKeyboardState = HID_KEYBOARD_STATE_IDLE;
+            }
+
+            //
+            // Pass the event on to the client.
+            //
+            psDevice->pfnCallback(psDevice->pvCBData, USB_EVENT_TX_COMPLETE,
+                                  ulMsgData, (void *)0);
+
+            break;
+        }
+
+        //
+        // We ignore all other events related to transmission of reports via
+        // the interrupt IN endpoint.
+        //
+        default:
+        {
+            break;
+        }
+    }
+
+    return(0);
+}
+
+//*****************************************************************************
+//
+// Add the supplied usage code to the list of keys currently in the pressed
+// state.
+//
+// \param ucUsageCode is the HID usage code of the newly pressed key.
+//
+// This function adds the supplied usage code to the global list of keys which
+// are currently pressed (assuming it is not already noted as pressed and that
+// there is space in the list to hold the new information).  The return code
+// indicates success if the list did not overflow and failure if the list
+// already contains as many pressed keys as can be reported.
+//
+// \return Returns \b true if the usage code was successfully added to the
+// list or \b false if there was insufficient space to hold the new key
+// press (in which case the caller should report a roll over error to the host).
+//
+//*****************************************************************************
+static tBoolean
+AddKeyToPressedList(tHIDKeyboardInstance *psInst, unsigned char ucUsageCode)
+{
+    unsigned long ulLoop;
+    tBoolean bRetcode;
+
+    //
+    // Assume all is well until we determine otherwise.
+    //
+    bRetcode = true;
+
+    //
+    // Look through the list of existing pressed keys to see if the new one
+    // is already there.
+    //
+    for(ulLoop = 0; ulLoop < (unsigned long)psInst->ucKeyCount; ulLoop++)
+    {
+        //
+        // Is this key already included in the list of keys in the pressed
+        // state?
+        //
+        if(ucUsageCode == psInst->pucKeysPressed[ulLoop])
+        {
+            //
+            // Yes - drop out.
+            //
+            break;
+        }
+    }
+
+    //
+    // If we exited the loop at the end of the existing key presses, this
+    // key does not exist already so add it if space exists.
+    //
+    if(ulLoop >= psInst->ucKeyCount)
+    {
+        if(psInst->ucKeyCount < KEYB_MAX_CHARS_PER_REPORT)
+        {
+            //
+            // We have room so store the new key press in the list.
+            //
+            psInst->pucKeysPressed[psInst->ucKeyCount] = ucUsageCode;
+            psInst->ucKeyCount++;
+            bRetcode = true;
+        }
+        else
+        {
+            //
+            // We have no room for the new key - declare a rollover error.
+            //
+            bRetcode = false;
+        }
+    }
+
+    return(bRetcode);
+}
+
+//*****************************************************************************
+//
+// Remove the supplied usage code from the list of keys currently in the
+// pressed state.
+//
+// \param ucUsageCode is the HID usage code of the newly released key.
+//
+// This function removes the supplied usage code from the global list of keys
+// which are currently pressed.  The return code indicates whether the key was
+// found in the list.  On exit, the list will have been cleaned up to ensure
+// that all key presses are contiguous starting at the first entry.
+//
+// \return Returns \b true if the usage code was found and removed from the
+// list or \b false if the code was not found.  The caller need not pass a new
+// report to the host if \b false is returned since the key list will not have
+// changed.
+//
+//*****************************************************************************
+static tBoolean
+RemoveKeyFromPressedList(tHIDKeyboardInstance *psInst,
+                         unsigned char ucUsageCode)
+{
+    unsigned long ulLoop;
+    unsigned long ulPos;
+
+    //
+    // Keep the compiler happy by setting ulPos to something.
+    //
+    ulPos = 0;
+
+    //
+    // Find the usage code in the current list.
+    //
+    for(ulLoop = 0; ulLoop < KEYB_MAX_CHARS_PER_REPORT; ulLoop++)
+    {
+        if(psInst->pucKeysPressed[ulLoop] == ucUsageCode)
+        {
+            ulPos = ulLoop;
+            break;
+        }
+    }
+
+    //
+    // If we dropped out at the end of the loop, we couldn't find the code so
+    // just return false.
+    //
+    if(ulLoop == KEYB_MAX_CHARS_PER_REPORT)
+    {
+        return(false);
+    }
+
+    //
+    // Now shuffle all the values to the right of the usage code we found
+    // down one position to fill the gap left by removing it.
+    //
+    for(ulLoop = (ulPos + 1); ulLoop < KEYB_MAX_CHARS_PER_REPORT; ulLoop++)
+    {
+        psInst->pucKeysPressed[ulLoop - 1] = psInst->pucKeysPressed[ulLoop];
+    }
+
+    //
+    // Clear the last entry in the array and adjust the number of keys in the
+    // array.
+    //
+    psInst->pucKeysPressed[KEYB_MAX_CHARS_PER_REPORT - 1] =
+        HID_KEYB_USAGE_RESERVED;
+    psInst->ucKeyCount--;
+
+    //
+    // Tell the caller we were successful.
+    //
+    return(true);
+}
+
+//*****************************************************************************
+//
+//! Initializes HID keyboard device operation for a given USB controller.
+//!
+//! \param ulIndex is the index of the USB controller which is to be
+//! initialized for HID keyboard device operation.
+//! \param psDevice points to a structure containing parameters customizing
+//! the operation of the HID keyboard device.
+//!
+//! An application wishing to offer a USB HID keyboard interface to a USB host
+//! must call this function to initialize the USB controller and attach the
+//! keyboard device to the USB bus.  This function performs all required USB
+//! initialization.
+//!
+//! On successful completion, this function will return the \e psDevice pointer
+//! passed to it.  This must be passed on all future calls to the HID keyboard
+//! device driver.
+//!
+//! When a host connects and configures the device, the application callback
+//! will receive \b USB_EVENT_CONNECTED after which calls can be made to
+//! USBDHIDKeyboardKeyStateChange() to report key presses and releases to the
+//! USB host.
+//!
+//! \note The application must not make any calls to the lower level USB device
+//! interfaces if interacting with USB via the USB HID keyboard device class
+//! API.  Doing so will cause unpredictable (though almost certainly
+//! unpleasant) behavior.
+//!
+//! \return Returns NULL on failure or the psDevice pointer on success.
+//
+//*****************************************************************************
+void *
+USBDHIDKeyboardInit(unsigned long ulIndex,
+                    const tUSBDHIDKeyboardDevice *psDevice)
+{
+    void *pvRetcode;
+    tUSBDHIDDevice *psHIDDevice;
+
+    //
+    // Check parameter validity.
+    //
+    ASSERT(psDevice);
+    ASSERT(psDevice->ppStringDescriptors);
+    ASSERT(psDevice->psPrivateHIDKbdData);
+    ASSERT(psDevice->pfnCallback);
+
+    //
+    // Get a pointer to the HID device data.
+    //
+    psHIDDevice = &psDevice->psPrivateHIDKbdData->sHIDDevice;
+
+    //
+    // Call the common initialization routine.
+    //
+    pvRetcode = USBDHIDKeyboardCompositeInit(ulIndex, psDevice);
+
+    //
+    // If we initialized the HID layer successfully, pass our device pointer
+    // back as the return code, otherwise return NULL to indicate an error.
+    //
+    if(pvRetcode)
+    {
+        //
+        // Initialize the lower layer HID driver and pass it the various
+        // structures and descriptors necessary to declare that we are a
+        // keyboard.
+        //
+        pvRetcode = USBDHIDInit(ulIndex, psHIDDevice);
+
+        return((void *)pvRetcode);
+    }
+    else
+    {
+        return((void *)0);
+    }
+}
+
+//*****************************************************************************
+//
+//! Initializes HID keyboard device operation for a given USB controller.
+//!
+//! \param ulIndex is the index of the USB controller which is to be
+//! initialized for HID keyboard device operation.
+//! \param psDevice points to a structure containing parameters customizing
+//! the operation of the HID keyboard device.
+//!
+//! This call is very similar to USBDKeyboardInit() except that it is used for
+//! initializing an instance of the HID keyboard device for use in a composite
+//! device.
+//!
+//! \return Returns zero on failure or a non-zero instance value that should be
+//! used with the remaining USB HID Keyboard APIs.
+//
+//*****************************************************************************
+void *
+USBDHIDKeyboardCompositeInit(unsigned long ulIndex,
+                             const tUSBDHIDKeyboardDevice *psDevice)
+{
+    tHIDKeyboardInstance *psInst;
+    unsigned long ulLoop;
+    tUSBDHIDDevice *psHIDDevice;
+
+    //
+    // Check parameter validity.
+    //
+    ASSERT(psDevice);
+    ASSERT(psDevice->ppStringDescriptors);
+    ASSERT(psDevice->psPrivateHIDKbdData);
+    ASSERT(psDevice->pfnCallback);
+
+    //
+    // Get a pointer to our instance data
+    //
+    psInst = psDevice->psPrivateHIDKbdData;
+
+    //
+    // Initialize the various fields in our instance structure.
+    //
+    psInst->ucUSBConfigured = 0;
+    psInst->ucProtocol = USB_HID_PROTOCOL_REPORT;
+    psInst->sReportIdle.ucDuration4mS = 125;
+    psInst->sReportIdle.ucReportID = 0;
+    psInst->sReportIdle.ulTimeSinceReportmS = 0;
+    psInst->sReportIdle.usTimeTillNextmS = 0;
+    psInst->ucLEDStates = 0;
+    psInst->ucKeyCount = 0;
+    for(ulLoop = 0; ulLoop < KEYB_MAX_CHARS_PER_REPORT; ulLoop++)
+    {
+        psInst->pucKeysPressed[ulLoop] = HID_KEYB_USAGE_RESERVED;
+    }
+
+    psInst->eKeyboardState = HID_KEYBOARD_STATE_UNCONFIGURED;
+
+    //
+    // Get a pointer to the HID device data.
+    //
+    psHIDDevice = &psDevice->psPrivateHIDKbdData->sHIDDevice;
+
+    //
+    // Initialize the HID device class instance structure based on input from
+    // the caller.
+    //
+    psHIDDevice->usPID = psDevice->usPID;
+    psHIDDevice->usVID = psDevice->usVID;
+    psHIDDevice->usMaxPowermA = psDevice->usMaxPowermA;
+    psHIDDevice->ucPwrAttributes = psDevice->ucPwrAttributes;
+    psHIDDevice->ucSubclass = USB_HID_SCLASS_BOOT;
+    psHIDDevice->ucProtocol = USB_HID_PROTOCOL_KEYB;
+    psHIDDevice->ucNumInputReports = 1;
+    psHIDDevice->psReportIdle = 0;
+    psHIDDevice->pfnRxCallback = HIDKeyboardRxHandler;
+    psHIDDevice->pvRxCBData = (void *)psDevice;
+    psHIDDevice->pfnTxCallback = HIDKeyboardTxHandler;
+    psHIDDevice->pvTxCBData = (void *)psDevice;
+    psHIDDevice->bUseOutEndpoint = false,
+    psHIDDevice->psHIDDescriptor = &g_sKeybHIDDescriptor;
+    psHIDDevice->ppClassDescriptors = g_pKeybClassDescriptors;
+    psHIDDevice->ppStringDescriptors = psDevice->ppStringDescriptors;
+    psHIDDevice->ulNumStringDescriptors = psDevice->ulNumStringDescriptors;
+    psHIDDevice->psPrivateHIDData = &psInst->sHIDInstance;
+    psHIDDevice->psReportIdle = &psInst->sReportIdle;
+
+    //
+    // Initialize the lower layer HID driver and pass it the various structures
+    // and descriptors necessary to declare that we are a keyboard.
+    //
+    return(USBDHIDCompositeInit(ulIndex, psHIDDevice));
+}
+
+//*****************************************************************************
+//
+//! Shuts down the HID keyboard device.
+//!
+//! \param pvInstance is the pointer to the device instance structure as
+//! returned by USBDHIDKeyboardInit().
+//!
+//! This function terminates HID keyboard operation for the instance supplied
+//! and removes the device from the USB bus.  Following this call, the \e
+//! pvInstance instance may not me used in any other call to the HID keyboard
+//! device other than USBDHIDKeyboardInit().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDHIDKeyboardTerm(void *pvInstance)
+{
+    tUSBDHIDKeyboardDevice *psDevice;
+    tUSBDHIDDevice *psHIDDevice;
+
+    ASSERT(pvInstance);
+
+    //
+    // Get a pointer to the device.
+    //
+    psDevice = (tUSBDHIDKeyboardDevice *)pvInstance;
+
+    //
+    // Get a pointer to the HID device data.
+    //
+    psHIDDevice = &psDevice->psPrivateHIDKbdData->sHIDDevice;
+
+    //
+    // Mark the device as no longer configured.
+    //
+    psDevice->psPrivateHIDKbdData->ucUSBConfigured = 0;
+
+    //
+    // Terminate the low level HID driver.
+    //
+    USBDHIDTerm(psHIDDevice);
+}
+
+//*****************************************************************************
+//
+//! Sets the client-specific pointer parameter for the keyboard callback.
+//!
+//! \param pvInstance is the pointer to the device instance structure as
+//! returned by USBDHIDKeyboardInit().
+//! \param pvCBData is the pointer that client wishes to be provided on each
+//! event sent to the keyboard callback function.
+//!
+//! The client uses this function to change the callback pointer passed in
+//! the first parameter on all callbacks to the \e pfnCallback function
+//! passed on USBDHIDKeyboardInit().
+//!
+//! If a client wants to make runtime changes in the callback pointer, it must
+//! ensure that the pvInstance structure passed to USBDHIDKeyboardInit() resides
+//! in RAM.  If this structure is in flash, callback data changes will not be
+//! possible.
+//!
+//! \return Returns the previous callback pointer that was set for this
+//! instance.
+//
+//*****************************************************************************
+void *
+USBDHIDKeyboardSetCBData(void *pvInstance, void *pvCBData)
+{
+    void *pvOldCBData;
+    tUSBDHIDKeyboardDevice *psKeyboard;
+
+    //
+    // Check for a NULL pointer in the device parameter.
+    //
+    ASSERT(pvInstance);
+
+    //
+    // Get a pointer to our keyboard device.
+    //
+    psKeyboard = (tUSBDHIDKeyboardDevice *)pvInstance;
+
+    //
+    // Save the old callback pointer and replace it with the new value.
+    //
+    pvOldCBData = psKeyboard->pvCBData;
+    psKeyboard->pvCBData = pvCBData;
+
+    //
+    // Pass the old callback pointer back to the caller.
+    //
+    return(pvOldCBData);
+}
+
+//*****************************************************************************
+//
+//! Reports a key state change to the USB host.
+//!
+//! \param pvInstance is the pointer to the device instance structure as
+//! returned by USBDHIDKeyboardInit().
+//! \param ucModifiers contains the states of each of the keyboard modifiers
+//! (left/right shift, ctrl, alt or GUI keys).  Valid values are logical OR
+//! combinations of the labels \b HID_KEYB_LEFT_CTRL, \b HID_KEYB_LEFT_SHIFT,
+//! \b HID_KEYB_LEFT_ALT, \b HID_KEYB_LEFT_GUI, \b HID_KEYB_RIGHT_CTRL, \b
+//! HID_KEYB_RIGHT_SHIFT, \b HID_KEYB_RIGHT_ALT and \b HID_KEYB_RIGHT_GUI.
+//! Presence of one of these bit flags indicates that the relevant modifier
+//! key is pressed and absence indicates that it is released.
+//! \param ucUsageCode is the usage code of the key whose state has changed.
+//! If only modifier keys have changed, \b HID_KEYB_USAGE_RESERVED should be
+//! passed in this parameter.
+//! \param bPress is \b true if the key has been pressed or \b false if it has
+//! been released.  If only modifier keys have changed state, this parameter is
+//! ignored.
+//!
+//! This function adds or removes a key usage code from the list of keys
+//! currently pressed and schedules a report transmission to the host to
+//! inform it of the new keyboard state.  If the maximum number of simultaneous
+//! key presses are already recorded, the report to the host will contain the
+//! rollover error code, HID_KEYB_USAGE_ROLLOVER instead of key usage codes
+//! and the caller will receive return code KEYB_ERR_TOO_MANY_KEYS.
+//!
+//! \return Returns \b KEYB_SUCCESS if the key usage code was added to or
+//! removed from the current list successfully.  \b KEYB_ERR_TOO_MANY_KEYS is
+//! returned if an attempt is made to press a 7th key (the BIOS keyboard
+//! protocol can report no more than 6 simultaneously pressed keys).  If called
+//! before the USB host has configured the device, \b KEYB_ERR_NOT_CONFIGURED
+//! is returned and, if an error is reported while attempting to transmit the
+//! report, \b KEYB_ERR_TX_ERROR is returned.  If an attempt is made to remove
+//! a key from the pressed list (by setting parameter \e bPressed to \b false)
+//! but the key usage code is not found, \b KEYB_ERR_NOT_FOUND is returned.
+//
+//*****************************************************************************
+unsigned long
+USBDHIDKeyboardKeyStateChange(void *pvInstance, unsigned char ucModifiers,
+                              unsigned char ucUsageCode, tBoolean bPress)
+{
+    tBoolean bRetcode;
+    unsigned long ulLoop;
+    unsigned long ulCount;
+    tHIDKeyboardInstance *psInst;
+    tUSBDHIDKeyboardDevice *psDevice;
+    tUSBDHIDDevice *psHIDDevice;
+
+    psDevice = (tUSBDHIDKeyboardDevice *)pvInstance;
+
+    //
+    // Get a pointer to the HID device data.
+    //
+    psHIDDevice = &psDevice->psPrivateHIDKbdData->sHIDDevice;
+
+    //
+    // Assume all is well until we determine otherwise.
+    //
+    bRetcode = true;
+
+    //
+    // Get a pointer to our instance data
+    //
+    psInst = psDevice->psPrivateHIDKbdData;
+
+    //
+    // Update the global keyboard report with the information passed.
+    //
+    psInst->pucReport[0] = ucModifiers;
+    psInst->pucReport[1] = 0;
+
+    //
+    // Were we passed a usage code for a new key press or release or was
+    // this call just telling us about a modifier change?
+    //
+    if(ucUsageCode != HID_KEYB_USAGE_RESERVED)
+    {
+        //
+        // Has a key been pressed or released?
+        //
+        if(bPress)
+        {
+            //
+            // A key has been pressed - add it to the list if there is space an
+            // and the key is not already in the list.
+            //
+            bRetcode = AddKeyToPressedList(psInst, ucUsageCode);
+        }
+        else
+        {
+            //
+            // A key has been released - remove it from the list.
+            //
+            bRetcode = RemoveKeyFromPressedList(psInst, ucUsageCode);
+
+            //
+            // The return code here indicates whether the key was found.  If it
+            // wasn't, the list has not changes so merely exit at this point
+            // without sending anything to the host.
+            //
+            if(!bRetcode)
+            {
+                return(KEYB_ERR_NOT_FOUND);
+            }
+        }
+
+        //
+        // Build the report from the current list of keys.  If we added a key
+        // and got a bad return code indicating a roll over error, we need to
+        // send a roll over report
+        //
+        for(ulLoop = 0; ulLoop < KEYB_MAX_CHARS_PER_REPORT; ulLoop++)
+        {
+            psInst->pucReport[2 + ulLoop] = (bRetcode ?
+                  psInst->pucKeysPressed[ulLoop] : HID_KEYB_USAGE_ROLLOVER);
+        }
+    }
+
+    //
+    // If we are not configured, return an error here before trying to send
+    // anything.
+    //
+    if(!psInst->ucUSBConfigured)
+    {
+        return(KEYB_ERR_NOT_CONFIGURED);
+    }
+
+    //
+    // Only send a report if the transmitter is currently free.
+    //
+    if(USBDHIDTxPacketAvailable((void *)psHIDDevice))
+    {
+        //
+        // Send the report to the host.
+        //
+        psInst->eKeyboardState = HID_KEYBOARD_STATE_SEND;
+        ulCount = USBDHIDReportWrite((void *)psHIDDevice,
+                                     psInst->pucReport, KEYB_IN_REPORT_SIZE,
+                                     true);
+
+        //
+        // Did we schedule a packet for transmission correctly?
+        //
+        if(!ulCount)
+        {
+            //
+            // No - report the error to the caller.
+            //
+            return(KEYB_ERR_TX_ERROR);
+        }
+    }
+    else
+    {
+        //
+        // We can't send the report immediately so mark the instance so that
+        // it is sent next time the transmitter is free.
+        //
+        psInst->bChangeMade = true;
+    }
+
+    //
+    // If we get this far, the key information was sent successfully.  Are
+    // too many keys currently pressed, though?
+    //
+    return(bRetcode ? KEYB_SUCCESS : KEYB_ERR_TOO_MANY_KEYS);
+}
+
+//*****************************************************************************
+//
+//! Reports the device power status (bus or self powered) to the USB library.
+//!
+//! \param pvInstance is the pointer to the keyboard device instance structure.
+//! \param ucPower indicates the current power status, either \b
+//! USB_STATUS_SELF_PWR or \b USB_STATUS_BUS_PWR.
+//!
+//! Applications which support switching between bus or self powered
+//! operation should call this function whenever the power source changes
+//! to indicate the current power status to the USB library.  This information
+//! is required by the USB library to allow correct responses to be provided
+//! when the host requests status from the device.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDHIDKeyboardPowerStatusSet(void *pvInstance, unsigned char ucPower)
+{
+    tUSBDHIDKeyboardDevice *psDevice;
+    tUSBDHIDDevice *psHIDDevice;
+
+    ASSERT(pvInstance);
+
+    //
+    // Get the keyboard device pointer.
+    //
+    psDevice = (tUSBDHIDKeyboardDevice *)pvInstance;
+
+    //
+    // Get a pointer to the HID device data.
+    //
+    psHIDDevice = &psDevice->psPrivateHIDKbdData->sHIDDevice;
+
+    //
+    // Pass the request through to the lower layer.
+    //
+    USBDHIDPowerStatusSet((void *)psHIDDevice, ucPower);
+}
+
+//*****************************************************************************
+//
+//! Requests a remote wake up to resume communication when in suspended state.
+//!
+//! \param pvInstance is the pointer to the keyboard device instance structure.
+//!
+//! When the bus is suspended, an application which supports remote wake up
+//! (advertised to the host via the configuration descriptor) may call this
+//! function to initiate remote wake up signaling to the host.  If the remote
+//! wake up feature has not been disabled by the host, this will cause the bus
+//! to resume operation within 20mS.  If the host has disabled remote wake up,
+//! \b false will be returned to indicate that the wake up request was not
+//! successful.
+//!
+//! \return Returns \b true if the remote wake up is not disabled and the
+//! signaling was started or \b false if remote wake up is disabled or if
+//! signaling is currently ongoing following a previous call to this function.
+//
+//*****************************************************************************
+tBoolean
+USBDHIDKeyboardRemoteWakeupRequest(void *pvInstance)
+{
+    tUSBDHIDKeyboardDevice *psDevice;
+    tUSBDHIDDevice *psHIDDevice;
+
+    ASSERT(pvInstance);
+
+    //
+    // Get the keyboard device pointer.
+    //
+    psDevice = (tUSBDHIDKeyboardDevice *)pvInstance;
+
+    //
+    // Get a pointer to the HID device data.
+    //
+    psHIDDevice = &psDevice->psPrivateHIDKbdData->sHIDDevice;
+
+    //
+    // Pass the request through to the lower layer.
+    //
+    return(USBDHIDRemoteWakeupRequest((void *)psHIDDevice));
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/src/platform/lm3s/usblib/device/usbdhidkeyb.h b/src/platform/lm3s/usblib/device/usbdhidkeyb.h
new file mode 100755
index 00000000..4670e017
--- /dev/null
+++ b/src/platform/lm3s/usblib/device/usbdhidkeyb.h
@@ -0,0 +1,382 @@
+//*****************************************************************************
+//
+// usbdhidkeyb.h - Definitions used by HID keyboard class devices.
+//
+// Copyright (c) 2008-2011 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 7611 of the Stellaris USB Library.
+//
+//*****************************************************************************
+
+#ifndef __USBDHIDKEYB_H__
+#define __USBDHIDKEYB_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+//! \addtogroup hid_keyboard_device_class_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! The maximum number of simultaneously-pressed, non-modifier keys that the
+//! HID BIOS keyboard protocol can send at once.  Attempts to send more pressed
+//! keys than this will result in a rollover error being reported to the host
+//! and KEYB_ERR_TOO_MANY_KEYS being returned from
+//! USBDHIDKeyboardKeyStateChange.
+//
+//*****************************************************************************
+#define KEYB_MAX_CHARS_PER_REPORT \
+                                6
+
+//*****************************************************************************
+//
+// PRIVATE
+//
+// The first few sections of this header are private defines that are used by
+// the USB HID keyboard code and are here only to help with the application
+// allocating the correct amount of memory for the USB HID Keyboard device
+// code.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// PRIVATE
+//
+// This enumeration holds the various states that the keyboard can be in during
+// normal operation.
+//
+//*****************************************************************************
+typedef enum
+{
+    //
+    // Unconfigured.
+    //
+    HID_KEYBOARD_STATE_UNCONFIGURED,
+
+    //
+    // No keys to send and not waiting on data.
+    //
+    HID_KEYBOARD_STATE_IDLE,
+
+    //
+    // Waiting on report data from the host.
+    //
+    HID_KEYBOARD_STATE_WAIT_DATA,
+
+    //
+    // Waiting on data to be sent out.
+    //
+    HID_KEYBOARD_STATE_SEND
+}
+tKeyboardState;
+
+//*****************************************************************************
+//
+// PRIVATE
+//
+// The size of the keyboard input and output reports.
+//
+//*****************************************************************************
+#define KEYB_IN_REPORT_SIZE 8
+#define KEYB_OUT_REPORT_SIZE 1
+
+//*****************************************************************************
+//
+// PRIVATE
+//
+// This structure defines the private instance data structure for the USB HID
+// keyboard device.  This structure forms the RAM workspace used by each
+// instance of the keyboard.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    // The USB configuration number set by the host or 0 of the device is
+    // currently unconfigured.
+    //
+    unsigned char ucUSBConfigured;
+
+    //
+    // The protocol requested by the host, USB_HID_PROTOCOL_BOOT or
+    // USB_HID_PROTOCOL_REPORT.
+    //
+    unsigned char ucProtocol;
+
+    //
+    // The current states that the keyboard LEDs are to be set to.
+    //
+    volatile unsigned char ucLEDStates;
+
+    //
+    // The total number of keys currently pressed.  This indicates the number
+    // of key press entries in the pucKeysPressed array.
+    //
+    unsigned char ucKeyCount;
+
+    //
+    // The current state of the keyboard interrupt IN endpoint.
+    //
+    volatile tKeyboardState eKeyboardState;
+
+    //
+    // A flag to indicate that the application pressed or released a key
+    // but that we couldn't send the report immediately.
+    //
+    volatile tBoolean bChangeMade;
+
+    //
+    // A buffer used to receive output reports from the host.
+    //
+    unsigned char pucDataBuffer[KEYB_OUT_REPORT_SIZE];
+
+    //
+    // A buffer used to hold the last input report sent to the host.
+    //
+    unsigned char pucReport[KEYB_IN_REPORT_SIZE];
+
+    //
+    // A buffer containing the usage codes of all non-modifier keys currently
+    // in the pressed state.
+    //
+    unsigned char pucKeysPressed[KEYB_MAX_CHARS_PER_REPORT];
+
+    //
+    // The idle timeout control structure for our input report.  This is
+    // required by the lower level HID driver.
+    //
+    tHIDReportIdle sReportIdle;
+
+    //
+    // The lower level HID driver's instance data.
+    //
+    tHIDInstance sHIDInstance;
+
+    //
+    // This is needed for the lower level HID driver.
+    //
+    tUSBDHIDDevice sHIDDevice;
+}
+tHIDKeyboardInstance;
+
+#ifndef DEPRECATED
+//*****************************************************************************
+//
+// The number of bytes of workspace required by the HID keyboard driver.
+// The client must provide a block of RAM of at least this size in the
+// psPrivateHIDKbdData field of the tUSBHIDKeyboardDevice structure passed on
+// USBDHIDKeyboardInit().
+//
+// This value is deprecated and should not be used, any new code should just
+// pass in a psPrivateHIDKbdData structure in the psPrivateHIDKbdData field.
+//
+//*****************************************************************************
+#define USB_HID_KEYB_WORKSPACE_SIZE (sizeof(tHIDKeyboardInstance))
+#endif
+
+//*****************************************************************************
+//
+//! This structure is used by the application to define operating parameters
+//! for the HID keyboard device.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! The vendor ID that this device is to present in the device descriptor.
+    //
+    unsigned short usVID;
+
+    //
+    //! The product ID that this device is to present in the device descriptor.
+    //
+    unsigned short usPID;
+
+    //
+    //! The maximum power consumption of the device, expressed in milliamps.
+    //
+    unsigned short usMaxPowermA;
+
+    //
+    //! Indicates whether the device is self- or bus-powered and whether or not
+    //! it supports remote wakeup.  Valid values are USB_CONF_ATTR_SELF_PWR or
+    //! USB_CONF_ATTR_BUS_PWR, optionally ORed with USB_CONF_ATTR_RWAKE.
+    //
+    unsigned char ucPwrAttributes;
+
+    //! A pointer to the callback function which will be called to notify
+    //! the application of general events and those related to reception of
+    //! Output and Feature reports via the (optional) interrupt OUT endpoint.
+    //
+    tUSBCallback pfnCallback;
+
+    //
+    //! A client-supplied pointer which will be sent as the first
+    //! parameter in all calls made to the keyboard callback,
+    //! pfnCallback.
+    //
+    void *pvCBData;
+
+    //
+    //! A pointer to the string descriptor array for this device.  This array
+    //! must contain the following string descriptor pointers in this order.
+    //! Language descriptor, Manufacturer name string (language 1), Product
+    //! name string (language 1), Serial number string (language 1),HID
+    //! Interface description string (language 1), Configuration description
+    //! string (language 1).
+    //!
+    //! If supporting more than 1 language, the descriptor block (except for
+    //! string descriptor 0) must be repeated for each language defined in the
+    //! language descriptor.
+    //
+    const unsigned char * const *ppStringDescriptors;
+
+    //
+    //! The number of descriptors provided in the ppStringDescriptors
+    //! array.  This must be (1 + (5 * (num languages))).
+    //
+    unsigned long ulNumStringDescriptors;
+
+    //
+    //! A pointer to private instance data for this device.  This memory must
+    //! remain accessible for as long as the keyboard device is in use and must
+    //! not be modified by any code outside the HID keyboard driver.
+    //
+    tHIDKeyboardInstance *psPrivateHIDKbdData;
+}
+tUSBDHIDKeyboardDevice;
+
+//*****************************************************************************
+//
+// Keyboard-specific device class driver events
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! This event indicates that the keyboard LED states are to be set.  The
+//! ulMsgValue parameter contains the requested state for each of the LEDs
+//! defined as a collection of ORed bits where a 1 indicates that the LED is
+//! to be turned on and a 0 indicates that it should be turned off.  The
+//! individual LED bits are defined using labels HID_KEYB_NUM_LOCK,
+//! HID_KEYB_CAPS_LOCK, HID_KEYB_SCROLL_LOCK, HID_KEYB_COMPOSE and
+//! HID_KEYB_KANA.
+//
+//*****************************************************************************
+#define USBD_HID_KEYB_EVENT_SET_LEDS                                          \
+                                USBD_HID_KEYB_EVENT_BASE
+
+//*****************************************************************************
+//
+//! This return code from USBDHIDKeyboardKeyStateChange indicates success.
+//
+//*****************************************************************************
+#define KEYB_SUCCESS            0
+
+//*****************************************************************************
+//
+//! This return code from USBDHIDKeyboardKeyStateChange indicates that an
+//! attempt has been made to record more than 6 simultaneously pressed,
+//! non-modifier keys.  The USB HID BIOS keyboard protocol allows no more than
+//! 6 pressed keys to be reported at one time.  Until at least one key is
+//! released, the device will report a roll over error to the host each time it
+//! is asked for the keyboard input report.
+//
+//*****************************************************************************
+#define KEYB_ERR_TOO_MANY_KEYS  1
+
+//*****************************************************************************
+//
+//! This return code from USBDHIDKeyboardKeyStateChange indicates that an
+//! error was reported while attempting to send a report to the host.  A client
+//! should assume that the host has disconnected if this return code is seen.
+//
+//*****************************************************************************
+#define KEYB_ERR_TX_ERROR       2
+
+//*****************************************************************************
+//
+//! USBDHIDKeyboardKeyStateChange returns this value if it is called with the
+//! bPress parameter set to false but with a ucUsageCode parameter which does
+//! does not indicate a key that is currently recorded as being pressed.  This
+//! may occur if an attempt was previously made to report more than 6 pressed
+//! keys and the earlier pressed keys are released before the later ones.  This
+//! condition is benign and should not be used to indicate a host disconnection
+//! or serious error.
+//
+//*****************************************************************************
+#define KEYB_ERR_NOT_FOUND      3
+
+//*****************************************************************************
+//
+//! USBDHIDKeyboardKeyStateChange returns this value if it is called before the
+//! USB host has connected and configured the device.  Any key usage code
+//! passed will be stored and passed to the host once configuration completes.
+//
+//*****************************************************************************
+#define KEYB_ERR_NOT_CONFIGURED 4
+
+//*****************************************************************************
+//
+// API Function Prototypes
+//
+//*****************************************************************************
+extern void *USBDHIDKeyboardInit(unsigned long ulIndex,
+                         const tUSBDHIDKeyboardDevice *psDevice);
+extern void *USBDHIDKeyboardCompositeInit(unsigned long ulIndex,
+                                          const tUSBDHIDKeyboardDevice *psDevice);
+extern void USBDHIDKeyboardTerm(void *pvInstance);
+extern void *USBDHIDKeyboardSetCBData(void *pvInstance, void *pvCBData);
+extern unsigned long USBDHIDKeyboardKeyStateChange(void *pvInstance,
+                                                   unsigned char ucModifiers,
+                                                   unsigned char ucUsageCode,
+                                                   tBoolean bPressed);
+extern void USBDHIDKeyboardPowerStatusSet(void *pvInstance,
+                                          unsigned char ucPower);
+extern tBoolean USBDHIDKeyboardRemoteWakeupRequest(void *pvInstance);
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __USBDHIDKEYB_H__
diff --git a/src/platform/lm3s/usblib/device/usbdhidmouse.c b/src/platform/lm3s/usblib/device/usbdhidmouse.c
new file mode 100755
index 00000000..4d57cdcb
--- /dev/null
+++ b/src/platform/lm3s/usblib/device/usbdhidmouse.c
@@ -0,0 +1,843 @@
+//*****************************************************************************
+//
+// usbdhidmouse.c - USB HID Mouse device class driver.
+//
+// Copyright (c) 2008-2011 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 7611 of the Stellaris USB Library.
+//
+//*****************************************************************************
+
+#include "inc/hw_types.h"
+#include "driverlib/debug.h"
+#include "driverlib/usb.h"
+#include "usblib/usblib.h"
+#include "usblib/device/usbdevice.h"
+#include "usblib/usbhid.h"
+#include "usblib/device/usbdhid.h"
+#include "usblib/device/usbdhidmouse.h"
+
+//*****************************************************************************
+//
+//! \addtogroup hid_mouse_device_class_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// The report descriptor for the mouse class device.
+//
+//*****************************************************************************
+static const unsigned char g_pucMouseReportDescriptor[]=
+{
+    UsagePage(USB_HID_GENERIC_DESKTOP),
+    Usage(USB_HID_MOUSE),
+    Collection(USB_HID_APPLICATION),
+        Usage(USB_HID_POINTER),
+        Collection(USB_HID_PHYSICAL),
+
+            //
+            // The buttons.
+            //
+            UsagePage(USB_HID_BUTTONS),
+            UsageMinimum(1),
+            UsageMaximum(3),
+            LogicalMinimum(0),
+            LogicalMaximum(1),
+
+            //
+            // 3 - 1 bit values for the buttons.
+            //
+            ReportSize(1),
+            ReportCount(3),
+            Input(USB_HID_INPUT_DATA | USB_HID_INPUT_VARIABLE |
+                  USB_HID_INPUT_ABS),
+
+            //
+            // 1 - 5 bit unused constant value to fill the 8 bits.
+            //
+            ReportSize(5),
+            ReportCount(1),
+            Input(USB_HID_INPUT_CONSTANT | USB_HID_INPUT_ARRAY |
+                  USB_HID_INPUT_ABS),
+
+            //
+            // The X and Y axis.
+            //
+            UsagePage(USB_HID_GENERIC_DESKTOP),
+            Usage(USB_HID_X),
+            Usage(USB_HID_Y),
+            LogicalMinimum(-127),
+            LogicalMaximum(127),
+
+            //
+            // 2 - 8 bit Values for x and y.
+            //
+            ReportSize(8),
+            ReportCount(2),
+            Input(USB_HID_INPUT_DATA | USB_HID_INPUT_VARIABLE |
+                  USB_HID_INPUT_RELATIVE),
+
+            //
+            // 2 - 8 bit Values for x and y.  // Padding
+            //
+            ReportSize(8),
+            ReportCount(MOUSE_REPORT_SIZE - 3),
+            Input(USB_HID_INPUT_CONSTANT | USB_HID_INPUT_ARRAY |
+                  USB_HID_INPUT_ABS),
+
+        EndCollection,
+    EndCollection,
+};
+
+//*****************************************************************************
+//
+// The HID class descriptor table.  For the mouse class, we have only a single
+// report descriptor.
+//
+//*****************************************************************************
+static const unsigned char * const g_pMouseClassDescriptors[] =
+{
+    g_pucMouseReportDescriptor
+};
+
+//*****************************************************************************
+//
+// The HID descriptor for the mouse device.
+//
+//*****************************************************************************
+static const tHIDDescriptor g_sMouseHIDDescriptor =
+{
+    9,                                 // bLength
+    USB_HID_DTYPE_HID,                 // bDescriptorType
+    0x111,                             // bcdHID (version 1.11 compliant)
+    0,                                 // bCountryCode (not localized)
+    1,                                 // bNumDescriptors
+    {
+        {
+            USB_HID_DTYPE_REPORT,                  // Report descriptor
+            sizeof(g_pucMouseReportDescriptor)     // Size of report descriptor
+        }
+    }
+};
+
+//*****************************************************************************
+//
+// Forward references for mouse device callback functions.
+//
+//*****************************************************************************
+static unsigned long HIDMouseRxHandler(void *pvCBData,
+                                          unsigned long ulEvent,
+                                          unsigned long ulMsgData,
+                                          void *pvMsgData);
+static unsigned long HIDMouseTxHandler(void *pvCBData,
+                                          unsigned long ulEvent,
+                                          unsigned long ulMsgData,
+                                          void *pvMsgData);
+
+//*****************************************************************************
+//
+// The HID mouse report offsets for this mouse application.
+//
+//*****************************************************************************
+#define HID_REPORT_BUTTONS      0
+#define HID_REPORT_X            1
+#define HID_REPORT_Y            2
+
+//*****************************************************************************
+//
+// Main HID device class event handler function.
+//
+// \param pvCBData is the event callback pointer provided during USBDHIDInit().
+// This is a pointer to our HID device structure (&g_sHIDMouseDevice).
+// \param ulEvent identifies the event we are being called back for.
+// \param ulMsgData is an event-specific value.
+// \param pvMsgData is an event-specific pointer.
+//
+// This function is called by the HID device class driver to inform the
+// application of particular asynchronous events related to operation of the
+// mouse HID device.
+//
+// \return Returns a value which is event-specific.
+//
+//*****************************************************************************
+static unsigned long
+HIDMouseRxHandler(void *pvCBData, unsigned long ulEvent,
+                  unsigned long ulMsgData, void *pvMsgData)
+{
+    tHIDMouseInstance *psInst;
+    tUSBDHIDMouseDevice *psDevice;
+
+    //
+    // Make sure we didn't get a NULL pointer.
+    //
+    ASSERT(pvCBData);
+
+    //
+    // Get a pointer to our instance data
+    //
+    psDevice = (tUSBDHIDMouseDevice *)pvCBData;
+    psInst = psDevice->psPrivateHIDMouseData;
+
+    //
+    // Which event were we sent?
+    //
+    switch (ulEvent)
+    {
+        //
+        // The host has connected to us and configured the device.
+        //
+        case USB_EVENT_CONNECTED:
+        {
+            psInst->ucUSBConfigured = true;
+
+            //
+            // Pass the information on to the client.
+            //
+            psDevice->pfnCallback(psDevice->pvCBData, USB_EVENT_CONNECTED,
+                                  0, (void *)0);
+
+            break;
+        }
+
+        //
+        // The host has disconnected from us.
+        //
+        case USB_EVENT_DISCONNECTED:
+        {
+            psInst->ucUSBConfigured = false;
+
+            //
+            // Pass the information on to the client.
+            //
+            psDevice->pfnCallback(psDevice->pvCBData, USB_EVENT_DISCONNECTED,
+                                  0, (void *)0);
+
+            break;
+        }
+
+        //
+        // The host is polling us for a particular report and the HID driver
+        // is asking for the latest version to transmit.
+        //
+        case USBD_HID_EVENT_IDLE_TIMEOUT:
+        case USBD_HID_EVENT_GET_REPORT:
+        {
+            //
+            // We only support a single input report so we don't need to check
+            // the ulMsgValue parameter in this case.  Set the report pointer
+            // in *pvMsgData and return the length of the report in bytes.
+            //
+            *(unsigned char **)pvMsgData = psInst->pucReport;
+            return(8);
+        }
+
+        //
+        // The device class driver has completed sending a report to the
+        // host in response to a Get_Report request.
+        //
+        case USBD_HID_EVENT_REPORT_SENT:
+        {
+            //
+            // We have nothing to do here.
+            //
+            break;
+        }
+
+        //
+        // This event is sent in response to a host Set_Report request.  The
+        // mouse device has no output reports so we return a NULL pointer and
+        // zero length to cause this request to be stalled.
+        //
+        case USBD_HID_EVENT_GET_REPORT_BUFFER:
+        {
+            //
+            // We are being asked for a report that does not exist for
+            // this device.
+            //
+            *(unsigned char **)pvMsgData = (void *)0;
+            return(0);
+        }
+
+        //
+        // The host is asking us to set either boot or report protocol (not
+        // that it makes any difference to this particular mouse).
+        //
+        case USBD_HID_EVENT_SET_PROTOCOL:
+        {
+            psInst->ucProtocol = ulMsgData;
+            break;
+        }
+
+        //
+        // The host is asking us to tell it which protocol we are currently
+        // using, boot or request.
+        //
+        case USBD_HID_EVENT_GET_PROTOCOL:
+        {
+            return(psInst->ucProtocol);
+        }
+
+        //
+        // Pass ERROR, SUSPEND and RESUME to the client unchanged.
+        //
+        case USB_EVENT_ERROR:
+        case USB_EVENT_SUSPEND:
+        case USB_EVENT_RESUME:
+        {
+            return(psDevice->pfnCallback(psDevice->pvCBData, ulEvent,
+                                         ulMsgData, pvMsgData));
+        }
+
+        //
+        // We ignore all other events.
+        //
+        default:
+        {
+            break;
+        }
+    }
+    return(0);
+}
+
+//*****************************************************************************
+//
+// HID device class transmit channel event handler function.
+//
+// \param pvCBData is the event callback pointer provided during USBDHIDInit().
+// This is a pointer to our HID device structure (&g_sHIDMouseDevice).
+// \param ulEvent identifies the event we are being called back for.
+// \param ulMsgData is an event-specific value.
+// \param pvMsgData is an event-specific pointer.
+//
+// This function is called by the HID device class driver to inform the
+// application of particular asynchronous events related to report
+// transmissions made using the interrupt IN endpoint.
+//
+// \return Returns a value which is event-specific.
+//
+//*****************************************************************************
+static unsigned long
+HIDMouseTxHandler(void *pvCBData, unsigned long ulEvent,
+                  unsigned long ulMsgData, void *pvMsgData)
+{
+    tHIDMouseInstance *psInst;
+    tUSBDHIDMouseDevice *psDevice;
+
+    //
+    // Make sure we didn't get a NULL pointer.
+    //
+    ASSERT(pvCBData);
+
+    //
+    // Get a pointer to our instance data
+    //
+    psDevice = (tUSBDHIDMouseDevice *)pvCBData;
+    psInst = psDevice->psPrivateHIDMouseData;
+
+    //
+    // Which event were we sent?
+    //
+    switch (ulEvent)
+    {
+        //
+        // A report transmitted via the interrupt IN endpoint was acknowledged
+        // by the host.
+        //
+        case USB_EVENT_TX_COMPLETE:
+        {
+            //
+            // Our last transmission is complete.
+            //
+            psInst->eMouseState = HID_MOUSE_STATE_IDLE;
+
+            //
+            // Pass the event on to the client.
+            //
+            psDevice->pfnCallback(psDevice->pvCBData, USB_EVENT_TX_COMPLETE,
+                                  ulMsgData, (void *)0);
+
+            break;
+        }
+
+        //
+        // We ignore all other events related to transmission of reports via
+        // the interrupt IN endpoint.
+        //
+        default:
+        {
+            break;
+        }
+    }
+
+    return(0);
+}
+
+//*****************************************************************************
+//
+//! Initializes HID mouse device operation for a given USB controller.
+//!
+//! \param ulIndex is the index of the USB controller which is to be
+//! initialized for HID mouse device operation.
+//! \param psDevice points to a structure containing parameters customizing
+//! the operation of the HID mouse device.
+//!
+//! An application wishing to offer a USB HID mouse interface to a USB host
+//! must call this function to initialize the USB controller and attach the
+//! mouse device to the USB bus.  This function performs all required USB
+//! initialization.
+//!
+//! On successful completion, this function will return the \e psDevice pointer
+//! passed to it.  This must be passed on all future calls to the HID mouse
+//! device driver.
+//!
+//! When a host connects and configures the device, the application callback
+//! will receive \b USB_EVENT_CONNECTED after which calls can be made to
+//! USBDHIDMouseStateChange() to report pointer movement and button presses
+//! to the host.
+//!
+//! \note The application must not make any calls to the lower level USB device
+//! interfaces if interacting with USB via the USB HID mouse device API.
+//! Doing so will cause unpredictable (though almost certainly unpleasant)
+//! behavior.
+//!
+//! \return Returns NULL on failure or the psDevice pointer on success.
+//
+//*****************************************************************************
+void *
+USBDHIDMouseInit(unsigned long ulIndex, const tUSBDHIDMouseDevice *psDevice)
+{
+    void *pvRetcode;
+    tUSBDHIDDevice *psHIDDevice;
+
+    //
+    // Check parameter validity.
+    //
+    ASSERT(psDevice);
+    ASSERT(psDevice->ppStringDescriptors);
+    ASSERT(psDevice->psPrivateHIDMouseData);
+    ASSERT(psDevice->pfnCallback);
+
+    //
+    // Get a pointer to the HID device data.
+    //
+    psHIDDevice = &psDevice->psPrivateHIDMouseData->sHIDDevice;
+
+    //
+    // Call the common initialization routine.
+    //
+    pvRetcode = USBDHIDMouseCompositeInit(ulIndex, psDevice);
+
+    //
+    // If we initialized the HID layer successfully, pass our device pointer
+    // back as the return code, otherwise return NULL to indicate an error.
+    //
+    if(pvRetcode)
+    {
+        //
+        // Initialize the lower layer HID driver and pass it the various
+        // structures and descriptors necessary to declare that we are a
+        // keyboard.
+        //
+        pvRetcode = USBDHIDInit(ulIndex, psHIDDevice);
+
+        return((void *)psDevice);
+    }
+    else
+    {
+        return((void *)0);
+    }
+}
+
+//*****************************************************************************
+//
+//! Initializes HID mouse device operation for a given USB controller.
+//!
+//! \param ulIndex is the index of the USB controller which is to be
+//! initialized for HID mouse device operation.
+//! \param psDevice points to a structure containing parameters customizing
+//! the operation of the HID mouse device.
+//!
+//! This call is very similar to USBDHIDMouseInit() except that it is used for
+//! initializing an instance of the HID mouse device for use in a composite
+//! device.
+//!
+//! \return Returns zero on failure or a non-zero instance value that should be
+//! used with the remaining USB HID Mouse APIs.
+//
+//*****************************************************************************
+void *
+USBDHIDMouseCompositeInit(unsigned long ulIndex,
+                          const tUSBDHIDMouseDevice *psDevice)
+{
+    tHIDMouseInstance *psInst;
+    tUSBDHIDDevice *psHIDDevice;
+
+
+    //
+    // Check parameter validity.
+    //
+    ASSERT(psDevice);
+    ASSERT(psDevice->ppStringDescriptors);
+    ASSERT(psDevice->psPrivateHIDMouseData);
+    ASSERT(psDevice->pfnCallback);
+
+    //
+    // Get a pointer to our instance data
+    //
+    psInst = psDevice->psPrivateHIDMouseData;
+
+    //
+    // Get a pointer to the HID device data.
+    //
+    psHIDDevice = &psDevice->psPrivateHIDMouseData->sHIDDevice;
+
+    //
+    // Initialize the various fields in our instance structure.
+    //
+    psInst->ucUSBConfigured = 0;
+    psInst->ucProtocol = USB_HID_PROTOCOL_REPORT;
+    psInst->sReportIdle.ucDuration4mS = 0;
+    psInst->sReportIdle.ucReportID = 0;
+    psInst->sReportIdle.ulTimeSinceReportmS = 0;
+    psInst->sReportIdle.usTimeTillNextmS = 0;
+    psInst->eMouseState = HID_MOUSE_STATE_UNCONFIGURED;
+
+    //
+    // Initialize the HID device class instance structure based on input from
+    // the caller.
+    //
+    psHIDDevice->usPID = psDevice->usPID;
+    psHIDDevice->usVID = psDevice->usVID;
+    psHIDDevice->usMaxPowermA = psDevice->usMaxPowermA;
+    psHIDDevice->ucPwrAttributes = psDevice->ucPwrAttributes;
+    psHIDDevice->ucSubclass = USB_HID_SCLASS_BOOT;
+    psHIDDevice->ucProtocol = USB_HID_PROTOCOL_MOUSE;
+    psHIDDevice->ucNumInputReports = 1;
+    psHIDDevice->psReportIdle = &psInst->sReportIdle;
+    psHIDDevice->pfnRxCallback = HIDMouseRxHandler;
+    psHIDDevice->pvRxCBData = (void *)psDevice;
+    psHIDDevice->pfnTxCallback = HIDMouseTxHandler;
+    psHIDDevice->pvTxCBData = (void *)psDevice;
+    psHIDDevice->bUseOutEndpoint = false;
+    psHIDDevice->psHIDDescriptor = &g_sMouseHIDDescriptor;
+    psHIDDevice->ppClassDescriptors= g_pMouseClassDescriptors;
+    psHIDDevice->ppStringDescriptors = psDevice->ppStringDescriptors;
+    psHIDDevice->ulNumStringDescriptors = psDevice->ulNumStringDescriptors;
+    psHIDDevice->psPrivateHIDData = &psInst->sHIDInstance;
+
+    //
+    // Initialize the lower layer HID driver and pass it the various structures
+    // and descriptors necessary to declare that we are a keyboard.
+    //
+    return(USBDHIDCompositeInit(ulIndex, psHIDDevice));
+}
+
+//*****************************************************************************
+//
+//! Shuts down the HID mouse device.
+//!
+//! \param pvInstance is the pointer to the device instance structure.
+//!
+//! This function terminates HID mouse operation for the instance supplied
+//! and removes the device from the USB bus.  Following this call, the \e
+//! pvInstance instance may not me used in any other call to the HID mouse
+//! device other than USBDHIDMouseInit().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDHIDMouseTerm(void *pvInstance)
+{
+    tUSBDHIDMouseDevice *psDevice;
+    tUSBDHIDDevice *psHIDDevice;
+
+    ASSERT(pvInstance);
+
+    //
+    // Get a pointer to the device.
+    //
+    psDevice = (tUSBDHIDMouseDevice *)pvInstance;
+
+    //
+    // Get a pointer to the HID device data.
+    //
+    psHIDDevice = &psDevice->psPrivateHIDMouseData->sHIDDevice;
+
+    //
+    // Mark our device as no longer configured.
+    //
+    psDevice->psPrivateHIDMouseData->ucUSBConfigured = 0;
+
+    //
+    // Terminate the low level HID driver.
+    //
+    USBDHIDTerm(psHIDDevice);
+}
+
+//*****************************************************************************
+//
+//! Sets the client-specific pointer parameter for the mouse callback.
+//!
+//! \param pvInstance is the pointer to the mouse device instance structure.
+//! \param pvCBData is the pointer that client wishes to be provided on each
+//! event sent to the mouse callback function.
+//!
+//! The client uses this function to change the callback pointer passed in
+//! the first parameter on all callbacks to the \e pfnCallback function
+//! passed on USBDHIDMouseInit().
+//!
+//! If a client wants to make runtime changes in the callback pointer, it must
+//! ensure that the pvInstance structure passed to USBDHIDMouseInit() resides
+//! in RAM.  If this structure is in flash, callback data changes will not be
+//! possible.
+//!
+//! \return Returns the previous callback pointer that was set for this
+//! instance.
+//
+//*****************************************************************************
+void *
+USBDHIDMouseSetCBData(void *pvInstance, void *pvCBData)
+{
+    void *pvOldCBData;
+    tUSBDHIDMouseDevice *psMouse;
+
+    //
+    // Check for a NULL pointer in the device parameter.
+    //
+    ASSERT(pvInstance);
+
+    //
+    // Get a pointer to our mouse device.
+    //
+    psMouse = (tUSBDHIDMouseDevice *)pvInstance;
+
+    //
+    // Save the old callback pointer and replace it with the new value.
+    //
+    pvOldCBData = psMouse->pvCBData;
+    psMouse->pvCBData = pvCBData;
+
+    //
+    // Pass the old callback pointer back to the caller.
+    //
+    return(pvOldCBData);
+}
+
+//*****************************************************************************
+//
+//! Reports a mouse state change, pointer movement or button press, to the USB
+//! host.
+//!
+//! \param pvInstance is the pointer to the mouse device instance structure.
+//! \param cDeltaX is the relative horizontal pointer movement that the
+//! application wishes to report.  Valid values are in the range [-127, 127]
+//! with positive values indicating movement to the right.
+//! \param cDeltaY is the relative vertical pointer movement that the
+//! application wishes to report.  Valid values are in the range [-127, 127]
+//! with positive values indicating downward movement.
+//! \param ucButtons is a bit mask indicating which (if any) of the three
+//! mouse buttons is pressed.  Valid values are logical OR combinations of
+//! \e MOUSE_REPORT_BUTTON_1, \e MOUSE_REPORT_BUTTON_2 and \e
+//! MOUSE_REPORT_BUTTON_3.
+//!
+//! This function is called to report changes in the mouse state to the USB
+//! host.  These changes can be movement of the pointer, reported relative to
+//! its previous position, or changes in the states of up to 3 buttons that
+//! the mouse may support.  The return code indicates whether or not the
+//! mouse report could be sent to the host.  In cases where a previous
+//! report is still being transmitted, \b MOUSE_ERR_TX_ERROR will be returned
+//! and the state change will be ignored.
+//!
+//! \return Returns \b MOUSE_SUCCESS on success, \b MOUSE_ERR_TX_ERROR if an
+//! error occurred while attempting to schedule transmission of the mouse
+//! report to the host (typically due to a previous report which has not yet
+//! completed transmission or due to disconnection of the host) or \b
+//! MOUSE_ERR_NOT_CONFIGURED if called before a host has connected to and
+//! configured the device.
+//
+//*****************************************************************************
+unsigned long
+USBDHIDMouseStateChange(void *pvInstance, char cDeltaX, char cDeltaY,
+                        unsigned char ucButtons)
+{
+    unsigned long ulRetcode;
+    unsigned long ulCount;
+    tHIDMouseInstance *psInst;
+    tUSBDHIDMouseDevice *psDevice;
+    tUSBDHIDDevice *psHIDDevice;
+
+    //
+    // Get a pointer to the device.
+    //
+    psDevice = (tUSBDHIDMouseDevice *)pvInstance;
+
+    //
+    // Get a pointer to the HID device data.
+    //
+    psHIDDevice = &psDevice->psPrivateHIDMouseData->sHIDDevice;
+
+    //
+    // Get a pointer to our instance data
+    //
+    psInst = psDevice->psPrivateHIDMouseData;
+
+    //
+    // Update the global mouse report with the information passed.
+    //
+    psInst->pucReport[HID_REPORT_BUTTONS] = ucButtons;
+    psInst->pucReport[HID_REPORT_X] = (unsigned char)cDeltaX;
+    psInst->pucReport[HID_REPORT_Y] = (unsigned char)cDeltaY;
+
+    //
+    // If we are not configured, return an error here before trying to send
+    // anything.
+    //
+    if(!psInst->ucUSBConfigured)
+    {
+        return(MOUSE_ERR_NOT_CONFIGURED);
+    }
+
+    //
+    // Only send a report if the transmitter is currently free.
+    //
+    if(USBDHIDTxPacketAvailable((void *)psHIDDevice))
+    {
+        //
+        // Send the report to the host.
+        //
+        psInst->eMouseState = HID_MOUSE_STATE_SEND;
+        ulCount = USBDHIDReportWrite((void *)psHIDDevice,
+                                     psInst->pucReport, MOUSE_REPORT_SIZE,
+                                     true);
+
+        //
+        // Did we schedule a packet for transmission correctly?
+        //
+        if(!ulCount)
+        {
+            //
+            // No - report the error to the caller.
+            //
+            ulRetcode = MOUSE_ERR_TX_ERROR;
+        }
+        else
+        {
+            ulRetcode = MOUSE_SUCCESS;
+        }
+    }
+    else
+    {
+        ulRetcode = MOUSE_ERR_TX_ERROR;
+    }
+    //
+    // Return the relevant error code to the caller.
+    //
+    return(ulRetcode);
+}
+
+//*****************************************************************************
+//
+//! Reports the device power status (bus- or self-powered) to the USB library.
+//!
+//! \param pvInstance is the pointer to the mouse device instance structure.
+//! \param ucPower indicates the current power status, either \b
+//! USB_STATUS_SELF_PWR or \b USB_STATUS_BUS_PWR.
+//!
+//! Applications which support switching between bus- or self-powered
+//! operation should call this function whenever the power source changes
+//! to indicate the current power status to the USB library.  This information
+//! is required by the USB library to allow correct responses to be provided
+//! when the host requests status from the device.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDHIDMousePowerStatusSet(void *pvInstance, unsigned char ucPower)
+{
+    tUSBDHIDMouseDevice *psDevice;
+    tUSBDHIDDevice *psHIDDevice;
+
+    ASSERT(pvInstance);
+
+    //
+    // Get the keyboard device pointer.
+    //
+    psDevice = (tUSBDHIDMouseDevice *)pvInstance;
+
+    //
+    // Get a pointer to the HID device data.
+    //
+    psHIDDevice = &psDevice->psPrivateHIDMouseData->sHIDDevice;
+
+    //
+    // Pass the request through to the lower layer.
+    //
+    USBDHIDPowerStatusSet((void *)psHIDDevice, ucPower);
+}
+
+//*****************************************************************************
+//
+//! Requests a remote wake up to resume communication when in suspended state.
+//!
+//! \param pvInstance is the pointer to the mouse device instance structure.
+//!
+//! When the bus is suspended, an application which supports remote wake up
+//! (advertised to the host via the configuration descriptor) may call this
+//! function to initiate remote wake up signaling to the host.  If the remote
+//! wake up feature has not been disabled by the host, this will cause the bus
+//! to resume operation within 20mS.  If the host has disabled remote wake up,
+//! \b false will be returned to indicate that the wake up request was not
+//! successful.
+//!
+//! \return Returns \b true if the remote wake up is not disabled and the
+//! signaling was started or \b false if remote wake up is disabled or if
+//! signaling is currently ongoing following a previous call to this function.
+//
+//*****************************************************************************
+tBoolean
+USBDHIDMouseRemoteWakeupRequest(void *pvInstance)
+{
+    tUSBDHIDMouseDevice *psDevice;
+    tUSBDHIDDevice *psHIDDevice;
+
+    ASSERT(pvInstance);
+
+    //
+    // Get the keyboard device pointer.
+    //
+    psDevice = (tUSBDHIDMouseDevice *)pvInstance;
+
+    //
+    // Get a pointer to the HID device data.
+    //
+    psHIDDevice = &psDevice->psPrivateHIDMouseData->sHIDDevice;
+
+    //
+    // Pass the request through to the lower layer.
+    //
+    return(USBDHIDRemoteWakeupRequest((void *)&psHIDDevice));
+}
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/src/platform/lm3s/usblib/device/usbdhidmouse.h b/src/platform/lm3s/usblib/device/usbdhidmouse.h
new file mode 100755
index 00000000..5980918f
--- /dev/null
+++ b/src/platform/lm3s/usblib/device/usbdhidmouse.h
@@ -0,0 +1,321 @@
+//*****************************************************************************
+//
+// usbdhidmouse.h - Public header file for the USB HID Mouse device class
+//                  driver
+//
+// Copyright (c) 2008-2011 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 7611 of the Stellaris USB Library.
+//
+//*****************************************************************************
+
+#ifndef __USBDHIDMOUSE_H__
+#define __USBDHIDMOUSE_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+//! \addtogroup hid_mouse_device_class_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// PRIVATE
+//
+// The first few sections of this header are private defines that are used by
+// the USB HID mouse code and are here only to help with the application
+// allocating the correct amount of memory for the HID mouse device code.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// PRIVATE
+//
+// The size of the mouse input report sent to the host.
+//
+//*****************************************************************************
+#define MOUSE_REPORT_SIZE       3
+
+//*****************************************************************************
+//
+// PRIVATE
+//
+// This enumeration holds the various states that the mouse can be in during
+// normal operation.
+//
+//*****************************************************************************
+typedef enum
+{
+    //
+    // Unconfigured.
+    //
+    HID_MOUSE_STATE_UNCONFIGURED,
+
+    //
+    // No keys to send and not waiting on data.
+    //
+    HID_MOUSE_STATE_IDLE,
+
+    //
+    // Waiting on report data from the host.
+    //
+    HID_MOUSE_STATE_WAIT_DATA,
+
+    //
+    // Waiting on data to be sent out.
+    //
+    HID_MOUSE_STATE_SEND
+}
+tMouseState;
+
+//*****************************************************************************
+//
+// PRIVATE
+//
+// This structure provides the private instance data structure for the USB
+// HID Mouse device.  This structure forms the RAM workspace used by each
+// instance of the mouse.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    // The USB configuration number set by the host or 0 of the device is
+    // currently unconfigured.
+    //
+    unsigned char ucUSBConfigured;
+
+    //
+    // The protocol requested by the host, USB_HID_PROTOCOL_BOOT or
+    // USB_HID_PROTOCOL_REPORT.
+    //
+    unsigned char ucProtocol;
+
+    //
+    // A buffer used to hold the last input report sent to the host.
+    //
+    unsigned char pucReport[MOUSE_REPORT_SIZE];
+
+    //
+    // The current state of the mouse interrupt IN endpoint.
+    //
+    volatile tMouseState eMouseState;
+
+    //
+    // The idle timeout control structure for our input report.  This is
+    // required by the lower level HID driver.
+    //
+    tHIDReportIdle sReportIdle;
+
+    //
+    // The lower level HID driver's instance data.
+    //
+    tHIDInstance sHIDInstance;
+
+    //
+    // This is needed for the lower level HID driver.
+    //
+    tUSBDHIDDevice sHIDDevice;
+}
+tHIDMouseInstance;
+
+#ifdef DEPRECATED
+//*****************************************************************************
+//
+// The number of bytes of workspace required by the HID mouse driver.
+// The client must provide a block of RAM of at least this size in the
+// tHIDMouseInstance field of the tUSBHIDMouseDevice structure passed on
+// USBDHIDMouseInit().  The HID mouse driver needs space for the generic HID
+// interface + the Mouse Report Buffer + HID mouse interface.
+//
+// This value is deprecated and should not be used, any new code should just
+// pass in a tHIDMouseInstance structure in the psPrivateHIDMouseData field.
+//
+//*****************************************************************************
+#define USB_HID_MOUSE_WORKSPACE_SIZE \
+                                 (sizeof(tHIDMouseInstance))
+#endif
+
+//*****************************************************************************
+//
+//! This structure is used by the application to define operating parameters
+//! for the HID mouse device.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! The vendor ID that this device is to present in the device descriptor.
+    //
+    unsigned short usVID;
+
+    //
+    //! The product ID that this device is to present in the device descriptor.
+    //
+    unsigned short usPID;
+
+    //
+    //! The maximum power consumption of the device, expressed in milliamps.
+    //
+    unsigned short usMaxPowermA;
+
+    //
+    //! Indicates whether the device is self- or bus-powered and whether or not
+    //! it supports remote wakeup.  Valid values are USB_CONF_ATTR_SELF_PWR or
+    //! USB_CONF_ATTR_BUS_PWR, optionally ORed with USB_CONF_ATTR_RWAKE.
+    //
+    unsigned char ucPwrAttributes;
+
+    //
+    //! A pointer to the callback function which will be called to notify
+    //! the application of events relating to the operation of the mouse.
+    //
+    tUSBCallback pfnCallback;
+
+    //
+    //! A client-supplied pointer which will be sent as the first
+    //! parameter in all calls made to the mouse callback, pfnCallback.
+    //
+    void *pvCBData;
+
+    //
+    //! A pointer to the string descriptor array for this device.  This array
+    //! must contain the following string descriptor pointers in this order.
+    //! Language descriptor, Manufacturer name string (language 1), Product
+    //! name string (language 1), Serial number string (language 1),HID
+    //! Interface description string (language 1), Configuration description
+    //! string (language 1).
+    //!
+    //! If supporting more than 1 language, the descriptor block (except for
+    //! string descriptor 0) must be repeated for each language defined in the
+    //! language descriptor.
+    //
+    const unsigned char * const *ppStringDescriptors;
+
+    //
+    //! The number of descriptors provided in the ppStringDescriptors
+    //! array.  This must be (1 + (5 * (num languages))).
+    //
+    unsigned long ulNumStringDescriptors;
+
+    //
+    //! A pointer to private instance data for this device.  This memory must
+    //! remain accessible for as long as the mouse device is in use and must
+    //! not be modified by any code outside the HID mouse driver.
+    //
+    tHIDMouseInstance *psPrivateHIDMouseData;
+}
+tUSBDHIDMouseDevice;
+
+//*****************************************************************************
+//
+//! This return code from USBDHIDMouseStateChange indicates success.
+//
+//*****************************************************************************
+#define MOUSE_SUCCESS           0
+
+//*****************************************************************************
+//
+//! This return code from USBDHIDMouseStateChange indicates that an error was
+//! reported while attempting to send a report to the host.  A client should
+//! assume that the host has disconnected if this return code is seen.
+//
+//*****************************************************************************
+#define MOUSE_ERR_TX_ERROR      2
+
+//*****************************************************************************
+//
+//! USBDHIDMouseStateChange returns this value if it is called before the
+//! USB host has connected and configured the device.  All mouse state
+//! information passed on the call will have been ignored.
+//
+//*****************************************************************************
+#define MOUSE_ERR_NOT_CONFIGURED \
+                                4
+
+//*****************************************************************************
+//
+//! Setting this bit in the ucButtons parameter to USBDHIDMouseStateChange
+//! indicates to the USB host that button 1 on the mouse is pressed.
+//
+//*****************************************************************************
+#define MOUSE_REPORT_BUTTON_1   0x01
+
+//*****************************************************************************
+//
+//! Setting this bit in the ucButtons parameter to USBDHIDMouseStateChange
+//! indicates to the USB host that button 2 on the mouse is pressed.
+//
+//*****************************************************************************
+#define MOUSE_REPORT_BUTTON_2   0x02
+
+//*****************************************************************************
+//
+//! Setting this bit in the ucButtons parameter to USBDHIDMouseStateChange
+//! indicates to the USB host that button 3 on the mouse is pressed.
+//
+//*****************************************************************************
+#define MOUSE_REPORT_BUTTON_3   0x04
+
+//*****************************************************************************
+//
+// API Function Prototypes
+//
+//*****************************************************************************
+extern void *USBDHIDMouseInit(unsigned long ulIndex,
+                              const tUSBDHIDMouseDevice *psDevice);
+extern void *USBDHIDMouseCompositeInit(unsigned long ulIndex,
+                                       const tUSBDHIDMouseDevice *psDevice);
+extern void USBDHIDMouseTerm(void *pvInstance);
+extern void *USBDHIDMouseSetCBData(void *pvInstance, void *pvCBData);
+extern unsigned long USBDHIDMouseStateChange(void *pvInstance, char cDeltaX,
+                                             char cDeltaY,
+                                             unsigned char ucButtons);
+extern void USBDHIDMousePowerStatusSet(void *pvInstance,
+                                       unsigned char ucPower);
+extern tBoolean USBDHIDMouseRemoteWakeupRequest(void *pvInstance);
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __USBDHIDMOUSE_H__
diff --git a/src/platform/lm3s/usblib/device/usbdmsc.c b/src/platform/lm3s/usblib/device/usbdmsc.c
new file mode 100755
index 00000000..2d51ccad
--- /dev/null
+++ b/src/platform/lm3s/usblib/device/usbdmsc.c
@@ -0,0 +1,2127 @@
+//*****************************************************************************
+//
+// usbdmsc.c - USB mass storage device class driver.
+//
+// Copyright (c) 2009-2011 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 7611 of the Stellaris USB Library.
+//
+//*****************************************************************************
+
+#include "inc/hw_memmap.h"
+#include "inc/hw_types.h"
+#include "driverlib/debug.h"
+#include "driverlib/rom.h"
+#include "driverlib/rom_map.h"
+#include "driverlib/sysctl.h"
+#include "driverlib/usb.h"
+#include "driverlib/udma.h"
+#include "usblib/usblib.h"
+#include "usblib/usbmsc.h"
+#include "usblib/device/usbdevice.h"
+#include "usblib/device/usbdmsc.h"
+#include "usblib/usblibpriv.h"
+
+//*****************************************************************************
+//
+//! \addtogroup msc_device_class_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// These are the internal flags used with the ulFlags member variable.
+//
+//*****************************************************************************
+#define USBD_FLAG_DMA_IN        0x00000001
+#define USBD_FLAG_DMA_OUT       0x00000002
+
+//*****************************************************************************
+//
+// The subset of endpoint status flags that we consider to be reception
+// errors.  These are passed to the client via USB_EVENT_ERROR if seen.
+//
+//*****************************************************************************
+#define USB_RX_ERROR_FLAGS      (USBERR_DEV_RX_DATA_ERROR |                   \
+                                 USBERR_DEV_RX_OVERRUN |                      \
+                                 USBERR_DEV_RX_FIFO_FULL)
+
+//*****************************************************************************
+//
+// These are fields that are used by the USB descriptors for the Mass Storage
+// Class.
+//
+//*****************************************************************************
+#define USB_MSC_SUBCLASS_SCSI   0x6
+#define USB_MSC_PROTO_BULKONLY  0x50
+
+//*****************************************************************************
+//
+// Endpoints to use for each of the required endpoints in the driver.
+//
+//*****************************************************************************
+#define DATA_IN_ENDPOINT        USB_EP_1
+#define DATA_IN_DMA_CHANNEL     UDMA_CHANNEL_USBEP1TX
+#define DATA_OUT_ENDPOINT       USB_EP_1
+#define DATA_OUT_DMA_CHANNEL    UDMA_CHANNEL_USBEP1RX
+
+//*****************************************************************************
+//
+// Maximum packet size for the bulk endpoints is 64 bytes.
+//
+//*****************************************************************************
+#define DATA_IN_EP_MAX_SIZE     64
+#define DATA_OUT_EP_MAX_SIZE    64
+
+//*****************************************************************************
+//
+// These defines control the sizes of USB transfers for data and commands.
+//
+//*****************************************************************************
+#define MAX_TRANSFER_SIZE       512
+#define COMMAND_BUFFER_SIZE     64
+
+//*****************************************************************************
+//
+// The local buffer used to read in commands and process them.
+//
+//*****************************************************************************
+static unsigned char g_pucCommand[COMMAND_BUFFER_SIZE];
+
+//*****************************************************************************
+//
+// The current transfer state is held in these variables.
+//
+//*****************************************************************************
+static tMSCCSW g_sSCSICSW;
+
+//*****************************************************************************
+//
+// The current state for the SCSI commands that are being handled and are
+// stored in the tMSCInstance.ucSCSIState structure member.
+//
+//*****************************************************************************
+
+//
+// No command in process.
+//
+#define STATE_SCSI_IDLE             0x00
+
+//
+// Sending and reading logical blocks.
+//
+#define STATE_SCSI_SEND_BLOCKS      0x01
+
+//
+// Receiving and writing logical blocks.
+//
+#define STATE_SCSI_RECEIVE_BLOCKS   0x02
+
+//
+// Send the status once the previous transfer is complete.
+//
+#define STATE_SCSI_SEND_STATUS      0x03
+
+//
+// Status was prepared to be sent and now waiting for it to have gone out.
+//
+#define STATE_SCSI_SENT_STATUS      0x04
+
+//*****************************************************************************
+//
+// Device Descriptor.  This is stored in RAM to allow several fields to be
+// changed at runtime based on the client's requirements.
+//
+//*****************************************************************************
+static unsigned char g_pMSCDeviceDescriptor[] =
+{
+    18,                     // Size of this structure.
+    USB_DTYPE_DEVICE,       // Type of this structure.
+    USBShort(0x110),        // USB version 1.1 (if we say 2.0, hosts assume
+                            // high-speed - see USB 2.0 spec 9.2.6.6)
+    0,                      // USB Device Class (spec 5.1.1)
+    0,                      // USB Device Sub-class (spec 5.1.1)
+    0,                      // USB Device protocol (spec 5.1.1)
+    64,                     // Maximum packet size for default pipe.
+    USBShort(0),            // Vendor ID (filled in during USBDCDCInit).
+    USBShort(0),            // Product ID (filled in during USBDCDCInit).
+    USBShort(0x100),        // Device Version BCD.
+    1,                      // Manufacturer string identifier.
+    2,                      // Product string identifier.
+    3,                      // Product serial number.
+    1                       // Number of configurations.
+};
+
+//*****************************************************************************
+//
+// Mass storage device configuration descriptor.
+//
+// It is vital that the configuration descriptor bConfigurationValue field
+// (byte 6) is 1 for the first configuration and increments by 1 for each
+// additional configuration defined here.  This relationship is assumed in the
+// device stack for simplicity even though the USB 2.0 specification imposes
+// no such restriction on the bConfigurationValue values.
+//
+// Note that this structure is deliberately located in RAM since we need to
+// be able to patch some values in it based on client requirements.
+//
+//*****************************************************************************
+static unsigned char g_pMSCDescriptor[] =
+{
+    //
+    // Configuration descriptor header.
+    //
+    9,                          // Size of the configuration descriptor.
+    USB_DTYPE_CONFIGURATION,    // Type of this descriptor.
+    USBShort(32),               // The total size of this full structure.
+    1,                          // The number of interfaces in this
+                                // configuration.
+    1,                          // The unique value for this configuration.
+    0,                          // The string identifier that describes this
+                                // configuration.
+    USB_CONF_ATTR_SELF_PWR,     // Bus Powered, Self Powered, remote wake up.
+    250,                        // The maximum power in 2mA increments.
+};
+
+//*****************************************************************************
+//
+// The remainder of the configuration descriptor is stored in flash since we
+// don't need to modify anything in it at runtime.
+//
+//*****************************************************************************
+const unsigned char g_pMSCInterface[] =
+{
+    //
+    // Vendor-specific Interface Descriptor.
+    //
+    9,                          // Size of the interface descriptor.
+    USB_DTYPE_INTERFACE,        // Type of this descriptor.
+    0,                          // The index for this interface.
+    0,                          // The alternate setting for this interface.
+    2,                          // The number of endpoints used by this
+                                // interface.
+    USB_CLASS_MASS_STORAGE,     // The interface class
+    USB_MSC_SUBCLASS_SCSI,      // The interface sub-class.
+    USB_MSC_PROTO_BULKONLY,     // The interface protocol for the sub-class
+                                // specified above.
+    0,                          // The string index for this interface.
+
+    //
+    // Endpoint Descriptor
+    //
+    7,                               // The size of the endpoint descriptor.
+    USB_DTYPE_ENDPOINT,              // Descriptor type is an endpoint.
+    USB_EP_DESC_IN | USB_EP_TO_INDEX(DATA_IN_ENDPOINT),
+    USB_EP_ATTR_BULK,                // Endpoint is a bulk endpoint.
+    USBShort(DATA_IN_EP_MAX_SIZE),   // The maximum packet size.
+    0,                               // The polling interval for this endpoint.
+
+    //
+    // Endpoint Descriptor
+    //
+    7,                               // The size of the endpoint descriptor.
+    USB_DTYPE_ENDPOINT,              // Descriptor type is an endpoint.
+    USB_EP_DESC_OUT | USB_EP_TO_INDEX(DATA_OUT_ENDPOINT),
+    USB_EP_ATTR_BULK,                // Endpoint is a bulk endpoint.
+    USBShort(DATA_OUT_EP_MAX_SIZE),  // The maximum packet size.
+    0,                               // The polling interval for this endpoint.
+};
+
+//*****************************************************************************
+//
+// The mass storage configuration descriptor is defined as two sections,
+// one containing just the 9 byte USB configuration descriptor and the other
+// containing everything else that is sent to the host along with it.
+//
+//*****************************************************************************
+const tConfigSection g_sMSCConfigSection =
+{
+    sizeof(g_pMSCDescriptor),
+    g_pMSCDescriptor
+};
+
+const tConfigSection g_sMSCInterfaceSection =
+{
+    sizeof(g_pMSCInterface),
+    g_pMSCInterface
+};
+
+//*****************************************************************************
+//
+// This array lists all the sections that must be concatenated to make a
+// single, complete bulk device configuration descriptor.
+//
+//*****************************************************************************
+const tConfigSection *g_psMSCSections[] =
+{
+    &g_sMSCConfigSection,
+    &g_sMSCInterfaceSection
+};
+
+#define NUM_MSC_SECTIONS (sizeof(g_psMSCSections) / sizeof(tConfigSection *))
+
+//*****************************************************************************
+//
+// The header for the single configuration we support.  This is the root of
+// the data structure that defines all the bits and pieces that are pulled
+// together to generate the configuration descriptor.
+//
+//*****************************************************************************
+const tConfigHeader g_sMSCConfigHeader =
+{
+    NUM_MSC_SECTIONS,
+    g_psMSCSections
+};
+
+//*****************************************************************************
+//
+// Configuration Descriptor.
+//
+//*****************************************************************************
+const tConfigHeader * const g_pMSCConfigDescriptors[] =
+{
+    &g_sMSCConfigHeader
+};
+
+//*****************************************************************************
+//
+// Various internal handlers needed by this class.
+//
+//*****************************************************************************
+static void HandleDisconnect(void *pvInstance);
+static void ConfigChangeHandler(void *pvInstance, unsigned long ulValue);
+static void HandleEndpoints(void *pvInstance, unsigned long ulStatus);
+static void HandleRequests(void *pvInstance, tUSBRequest *pUSBRequest);
+static void USBDSCSISendStatus(const tUSBDMSCDevice *psDevice);
+unsigned long USBDSCSICommand(const tUSBDMSCDevice *psDevice,
+                              tMSCCBW *pSCSICBW);
+static void HandleDevice(void *pvInstance, unsigned long ulRequest,
+                         void *pvRequestData);
+
+//*****************************************************************************
+//
+// The FIFO configuration for USB mass storage class device.
+//
+//*****************************************************************************
+const tFIFOConfig g_sUSBMSCFIFOConfig =
+{
+    //
+    // IN endpoints.
+    //
+    {
+        { 1, false, USB_EP_DEV_IN | USB_EP_DMA_MODE_1 | USB_EP_AUTO_SET },
+        { 1, false, USB_EP_DEV_IN },
+        { 1, false, USB_EP_DEV_IN },
+        { 1, false, USB_EP_DEV_IN },
+        { 1, false, USB_EP_DEV_IN },
+        { 1, false, USB_EP_DEV_IN },
+        { 1, false, USB_EP_DEV_IN },
+        { 1, false, USB_EP_DEV_IN },
+        { 1, false, USB_EP_DEV_IN },
+        { 1, false, USB_EP_DEV_IN },
+        { 1, false, USB_EP_DEV_IN },
+        { 1, false, USB_EP_DEV_IN },
+        { 1, false, USB_EP_DEV_IN },
+        { 1, false, USB_EP_DEV_IN },
+        { 1, false, USB_EP_DEV_IN }
+    },
+
+    //
+    // OUT endpoints.
+    //
+    {
+        { 1, false, USB_EP_DEV_OUT | USB_EP_DMA_MODE_1 | USB_EP_AUTO_CLEAR },
+        { 1, false, USB_EP_DEV_OUT },
+        { 1, false, USB_EP_DEV_OUT },
+        { 1, false, USB_EP_DEV_OUT },
+        { 1, false, USB_EP_DEV_OUT },
+        { 1, false, USB_EP_DEV_OUT },
+        { 1, false, USB_EP_DEV_OUT },
+        { 1, false, USB_EP_DEV_OUT },
+        { 1, false, USB_EP_DEV_OUT },
+        { 1, false, USB_EP_DEV_OUT },
+        { 1, false, USB_EP_DEV_OUT },
+        { 1, false, USB_EP_DEV_OUT },
+        { 1, false, USB_EP_DEV_OUT },
+        { 1, false, USB_EP_DEV_OUT },
+        { 1, false, USB_EP_DEV_OUT }
+    },
+};
+
+//*****************************************************************************
+//
+// The device information structure for the USB MSC device.
+//
+//*****************************************************************************
+tDeviceInfo g_sMSCDeviceInfo =
+{
+    //
+    // Device event handler callbacks.
+    //
+    {
+        //
+        // GetDescriptor
+        //
+        0,
+
+        //
+        // RequestHandler
+        //
+        HandleRequests,
+
+        //
+        // InterfaceChange
+        //
+        0,
+
+        //
+        // ConfigChange
+        //
+        ConfigChangeHandler,
+
+        //
+        // DataReceived
+        //
+        0,
+
+        //
+        // DataSentCallback
+        //
+        0,
+
+        //
+        // ResetHandler
+        //
+        0,
+
+        //
+        // SuspendHandler
+        //
+        0,
+
+        //
+        // ResumeHandler
+        //
+        0,
+
+        //
+        // DisconnectHandler
+        //
+        HandleDisconnect,
+
+        //
+        // EndpointHandler
+        //
+        HandleEndpoints,
+
+        //
+        // Device handler
+        //
+        HandleDevice
+    },
+    g_pMSCDeviceDescriptor,
+    g_pMSCConfigDescriptors,
+    0,
+    0,
+    &g_sUSBMSCFIFOConfig
+};
+
+//*****************************************************************************
+//
+//! This function is used by an application if it can detect insertion or
+//! removal of the media.
+//!
+//! \param pvInstance is the mass storage device instance that had a media
+//! change.
+//! \param eMediaStatus is the updated status for the media.
+//!
+//! This function should be called by an application when it detects a change
+//! in the status of the media in use by the USB mass storage class.  The
+//! \e eMediaStatus parameter will indicate the new status of the media and
+//! can also indicate that the application has no knowledge of the media state.
+//!
+//! There are currently the three following values for the \e eMediaStatus
+//! parameter:
+//! - USBDMSC_MEDIA_PRESENT indicates that the media is present or has been
+//! added.
+//! - USBDMSC_MEDIA_NOTPRESENT indicates that the media is not present or was
+//! removed.
+//! - USBDMSC_MEDIA_UNKNOWN indicates that the application has no knowledge of
+//! the media state and the USB mass storage class.
+//!
+//! It will be left up to the application to call this function whenever it
+//! detects a change or simply call it once with USBDMSC_MEDIA_UNKNOWN and
+//! allow the mass storage class to infer the state from the remaining device
+//! APIs.
+//!
+//! \note It is recommended that the application use this function to inform
+//! the mass storage class of media state changes as it will lead to a more
+//! responsive system.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDMSCMediaChange(void *pvInstance, tUSBDMSCMediaStatus eMediaStatus)
+{
+    const tUSBDMSCDevice *psDevice;
+
+    //
+    // Create a device instance pointer.
+    //
+    psDevice = pvInstance;
+
+    //
+    // Save the current media status.
+    //
+    psDevice->psPrivateData->eMediaStatus = eMediaStatus;
+}
+
+//*****************************************************************************
+//
+// This function is called to handle the interrupts on the Bulk endpoints for
+// the mass storage class.
+//
+//*****************************************************************************
+static void
+HandleEndpoints(void *pvInstance, unsigned long ulStatus)
+{
+    const tUSBDMSCDevice *psDevice;
+    tMSCInstance *psInst;
+    tMSCCBW *pSCSICBW;
+    unsigned long ulEPStatus;
+    unsigned long ulSize;
+
+    ASSERT(pvInstance != 0);
+
+    //
+    // Determine if the serial device is in single or composite mode because
+    // the meaning of ulIndex is different in both cases.
+    //
+    psDevice = pvInstance;
+
+    //
+    // Initialize the workspace in the passed instance structure.
+    //
+    psInst = psDevice->psPrivateData;
+
+    //
+    // Get the endpoints status.
+    //
+    ulEPStatus = MAP_USBEndpointStatus(USB0_BASE, psInst->ucOUTEndpoint);
+
+    //
+    // Handler for the bulk IN data endpoint.
+    //
+    if((ulStatus & (1 << USB_EP_TO_INDEX(psInst->ucINEndpoint))) ||
+       ((psInst->ulFlags & USBD_FLAG_DMA_IN) &&
+        (MAP_uDMAChannelModeGet(psInst->ucINDMA) == UDMA_MODE_STOP)))
+    {
+        switch(psInst->ucSCSIState)
+        {
+            //
+            // Handle the case where we are sending out data due to a read
+            // command.
+            //
+            case STATE_SCSI_SEND_BLOCKS:
+            {
+                //
+                // Decrement the number of bytes left to send.
+                //
+                psInst->ulBytesToTransfer -= MAX_TRANSFER_SIZE;
+
+                //
+                // If we are done then move on to the status phase.
+                //
+                if(psInst->ulBytesToTransfer == 0)
+                {
+                    //
+                    // Set the status so that it can be sent when this
+                    // response has has be successfully sent.
+                    //
+                    g_sSCSICSW.bCSWStatus = 0;
+                    g_sSCSICSW.dCSWDataResidue = 0;
+
+                    //
+                    // DMA has completed for the IN endpoint.
+                    //
+                    psInst->ulFlags &= ~USBD_FLAG_DMA_IN;
+
+                    //
+                    // Disable uDMA on the endpoint
+                    //
+                    MAP_USBEndpointDMADisable(USB0_BASE, psInst->ucINEndpoint,
+                                              USB_EP_DEV_IN);
+
+                    //
+                    // Send back the status once this transfer is complete.
+                    //
+                    psInst->ucSCSIState = STATE_SCSI_SEND_STATUS;
+
+                    if(psDevice->pfnEventCallback)
+                    {
+                        psDevice->pfnEventCallback(0, USBD_MSC_EVENT_IDLE, 0,
+                                                   0);
+                    }
+
+                    //
+                    // The transfer is complete so don't read anymore data.
+                    //
+                    break;
+                }
+
+                //
+                // Move on to the next Logical Block.
+                //
+                psInst->ulCurrentLBA++;
+
+                //
+                // Read the new data and send it out.
+                //
+                if(psDevice->sMediaFunctions.BlockRead(psInst->pvMedia,
+                        (unsigned char *)psInst->pulBuffer,
+                        psInst->ulCurrentLBA, 1) == 0)
+                {
+                }
+
+                //
+                // Reset the DMA transfer and enable the DMA channel.
+                //
+                MAP_uDMAChannelTransferSet(psInst->ucINDMA,
+                                           UDMA_MODE_BASIC,
+                                           psInst->pulBuffer,
+                                           (void *)USBFIFOAddrGet(USB0_BASE,
+                                               psInst->ucINEndpoint),
+                                           (MAX_TRANSFER_SIZE >> 2));
+                MAP_uDMAChannelEnable(psInst->ucINDMA);
+
+                break;
+            }
+
+            //
+            // Handle sending status.
+            //
+            case STATE_SCSI_SEND_STATUS:
+            {
+                //
+                // Indicate success and no extra data coming.
+                //
+                USBDSCSISendStatus(psDevice);
+
+                break;
+            }
+
+            //
+            // Handle completing sending status.
+            //
+            case STATE_SCSI_SENT_STATUS:
+            {
+                psInst->ucSCSIState = STATE_SCSI_IDLE;
+
+                break;
+            }
+
+            //
+            // These cases should not occur as the being in the IDLE state due
+            // to an IN interrupt is invalid.
+            //
+            case STATE_SCSI_IDLE:
+            default:
+            {
+                break;
+            }
+        }
+    }
+
+    //
+    // Handler for the bulk OUT data endpoint.
+    //
+    if((ulStatus & (0x10000 << USB_EP_TO_INDEX(psInst->ucOUTEndpoint))) ||
+        ((psInst->ulFlags & USBD_FLAG_DMA_OUT) &&
+         (MAP_uDMAChannelModeGet(psInst->ucOUTDMA) == UDMA_MODE_STOP)))
+    {
+        //
+        // Get the endpoint status to see why we were called.
+        //
+        ulEPStatus = MAP_USBEndpointStatus(USB0_BASE, psInst->ucOUTEndpoint);
+
+        switch(psInst->ucSCSIState)
+        {
+            //
+            // Receiving and writing bytes to the storage device.
+            //
+            case STATE_SCSI_RECEIVE_BLOCKS:
+            {
+                //
+                // Update the current status for the buffer.
+                //
+                psInst->ulBytesToTransfer -= MAX_TRANSFER_SIZE;
+
+                //
+                // Write the new data.
+                //
+                psDevice->sMediaFunctions.BlockWrite(psInst->pvMedia,
+                    (unsigned char *)psInst->pulBuffer,
+                    psInst->ulCurrentLBA, 1);
+
+                //
+                // Move on to the next Logical Block.
+                //
+                psInst->ulCurrentLBA++;
+
+                //
+                // Check if all bytes have been received.
+                //
+                if(psInst->ulBytesToTransfer == 0)
+                {
+                    //
+                    // Set the status so that it can be sent when this response
+                    // has be successfully sent.
+                    //
+                    g_sSCSICSW.bCSWStatus = 0;
+                    g_sSCSICSW.dCSWDataResidue = 0;
+
+                    //
+                    // DMA has completed for the OUT endpoint.
+                    //
+                    psInst->ulFlags &= ~USBD_FLAG_DMA_OUT;
+
+                    //
+                    // Indicate success and no extra data coming.
+                    //
+                    USBDSCSISendStatus(psDevice);
+
+                    //
+                    // Disable uDMA on the endpoint
+                    //
+                    MAP_USBEndpointDMADisable(USB0_BASE, psInst->ucOUTEndpoint,
+                                              USB_EP_DEV_OUT);
+
+                    //
+                    // If there is an event callback then call it to notify
+                    // that last operation has completed.
+                    //
+                    if(psDevice->pfnEventCallback)
+                    {
+                        psDevice->pfnEventCallback(0, USBD_MSC_EVENT_IDLE, 0,
+                                                   0);
+                    }
+                }
+                else
+                {
+                    //
+                    // Configure and enable DMA for the OUT transfer.
+                    //
+                    MAP_uDMAChannelTransferSet(psInst->ucOUTDMA,
+                                               UDMA_MODE_BASIC,
+                                               (void *)USBFIFOAddrGet(USB0_BASE,
+                                                   psInst->ucOUTEndpoint),
+                                               psInst->pulBuffer,
+                                               (MAX_TRANSFER_SIZE >> 2));
+
+                    //
+                    // Start the DMA transfer.
+                    //
+                    MAP_uDMAChannelEnable(psInst->ucOUTDMA);
+                }
+
+                break;
+            }
+
+            //
+            // If there is an OUT transfer in idle state then it was a new
+            // command.
+            //
+            case STATE_SCSI_IDLE:
+            {
+                //
+                // Attempt to handle the new command.
+                //
+
+                //
+                // Receive the command.
+                //
+                ulSize = COMMAND_BUFFER_SIZE;
+                MAP_USBEndpointDataGet(psInst->ulUSBBase, psInst->ucOUTEndpoint,
+                                       g_pucCommand, &ulSize);
+                pSCSICBW = (tMSCCBW *)g_pucCommand;
+
+                //
+                // Acknowledge the OUT data packet.
+                //
+                MAP_USBDevEndpointDataAck(psInst->ulUSBBase,
+                                          psInst->ucOUTEndpoint,
+                                          false);
+
+                //
+                // If this is a valid CBW then handle it.
+                //
+                if(pSCSICBW->dCBWSignature == CBW_SIGNATURE)
+                {
+                    g_sSCSICSW.dCSWSignature = CSW_SIGNATURE;
+                    g_sSCSICSW.dCSWTag = pSCSICBW->dCBWTag;
+                    g_sSCSICSW.dCSWDataResidue = 0;
+                    g_sSCSICSW.bCSWStatus = 0;
+
+                    USBDSCSICommand(psDevice, pSCSICBW);
+                }
+                else
+                {
+                    //
+                    // Just return to the idle state since we are now out of
+                    // sync with the host.  This should not happen, but this
+                    // should allow the device to synchronize with the host
+                    // controller.
+                    //
+                    psInst->ucSCSIState = STATE_SCSI_IDLE;
+                }
+
+                break;
+            }
+            default:
+            {
+                break;
+            }
+        }
+
+        //
+        // Clear the status bits.
+        //
+        MAP_USBDevEndpointStatusClear(USB0_BASE, psInst->ucOUTEndpoint,
+                                      ulEPStatus);
+    }
+}
+
+//*****************************************************************************
+//
+// Device instance specific handler.
+//
+//*****************************************************************************
+static void
+HandleDevice(void *pvInstance, unsigned long ulRequest, void *pvRequestData)
+{
+    tMSCInstance *psInst;
+    unsigned char *pucData;
+
+    //
+    // Create the serial instance data.
+    //
+    psInst = ((tUSBDMSCDevice *)pvInstance)->psPrivateData;
+
+    //
+    // Create the char array used by the events supported by the USB CDC
+    // serial class.
+    //
+    pucData = (unsigned char *)pvRequestData;
+
+    switch(ulRequest)
+    {
+        //
+        // This was an interface change event.
+        //
+        case USB_EVENT_COMP_IFACE_CHANGE:
+        {
+            psInst->ucInterface = pucData[1];
+            break;
+        }
+
+        //
+        // This was an endpoint change event.
+        //
+        case USB_EVENT_COMP_EP_CHANGE:
+        {
+            //
+            // Determine if this is an IN or OUT endpoint that has changed.
+            //
+            if(pucData[0] & USB_EP_DESC_IN)
+            {
+                psInst->ucINEndpoint = INDEX_TO_USB_EP((pucData[1] & 0x7f));
+                psInst->ucINDMA = UDMA_CHANNEL_USBEP1TX +
+                                  (((pucData[1] & 0x7f) - 1) * 2);
+
+                //
+                // Basic configuration for DMA on the IN endpoint.
+                //
+                MAP_uDMAChannelControlSet(psInst->ucINDMA,
+                                          (UDMA_SIZE_32 | UDMA_SRC_INC_32|
+                                           UDMA_DST_INC_NONE | UDMA_ARB_16));
+
+                //
+                // Select this channel for this endpoint, this only affects
+                // devices that have this feature.
+                //
+                MAP_USBEndpointDMAChannel(USB0_BASE, psInst->ucINEndpoint,
+                                          psInst->ucINDMA);
+            }
+            else
+            {
+                //
+                // Extract the new endpoint number.
+                //
+                psInst->ucOUTEndpoint = INDEX_TO_USB_EP(pucData[1] & 0x7f);
+                psInst->ucOUTDMA = UDMA_CHANNEL_USBEP1RX +
+                                   (((pucData[1] & 0x7f) - 1) * 2);
+
+                //
+                // Basic configuration for DMA on the OUT endpoint.
+                //
+                MAP_uDMAChannelControlSet(psInst->ucOUTDMA,
+                                          (UDMA_SIZE_32 | UDMA_SRC_INC_NONE|
+                                           UDMA_DST_INC_32 | UDMA_ARB_16));
+
+                //
+                // Select this channel for this endpoint, this only affects
+                // devices that have this feature.
+                //
+                MAP_USBEndpointDMAChannel(USB0_BASE, psInst->ucOUTEndpoint,
+                                          psInst->ucOUTDMA);
+            }
+            break;
+        }
+        default:
+        {
+            break;
+        }
+    }
+}
+
+//*****************************************************************************
+//
+// This function is called by the USB device stack whenever the device is
+// disconnected from the host.
+//
+//*****************************************************************************
+static void
+HandleDisconnect(void *pvInstance)
+{
+    const tUSBDMSCDevice *psDevice;
+
+    ASSERT(pvInstance != 0);
+
+    //
+    // Create the instance pointer.
+    //
+    psDevice = (const tUSBDMSCDevice *)pvInstance;
+
+    //
+    // Close the drive requested.
+    //
+    if(psDevice->psPrivateData->pvMedia != 0)
+    {
+        psDevice->psPrivateData->pvMedia = 0;
+        psDevice->sMediaFunctions.Close(0);
+    }
+
+    //
+    // If we have a control callback, let the client know we are open for
+    // business.
+    //
+    if(psDevice->pfnEventCallback)
+    {
+        //
+        // Pass the connected event to the client.
+        //
+        psDevice->pfnEventCallback(pvInstance, USB_EVENT_DISCONNECTED, 0, 0);
+    }
+}
+
+//*****************************************************************************
+//
+// This function is called by the USB device stack whenever the device
+// configuration changes.
+//
+//*****************************************************************************
+static void
+ConfigChangeHandler(void *pvInstance, unsigned long ulValue)
+{
+    tMSCInstance *psInst;
+    const tUSBDMSCDevice *psDevice;
+
+    ASSERT(pvInstance != 0);
+
+    //
+    // Create the instance pointer.
+    //
+    psDevice = (const tUSBDMSCDevice *)pvInstance;
+
+    //
+    // Create the serial instance data.
+    //
+    psInst = psDevice->psPrivateData;
+
+    //
+    // Insure that DMA is disable whenever the configuration is set.
+    //
+    MAP_USBEndpointDMADisable(USB0_BASE, psInst->ucINEndpoint, USB_EP_DEV_IN);
+    MAP_USBEndpointDMADisable(USB0_BASE, psInst->ucOUTEndpoint, USB_EP_DEV_OUT);
+
+    //
+    // Basic configuration for DMA on the OUT endpoint.
+    //
+    MAP_uDMAChannelControlSet(psInst->ucOUTDMA, UDMA_SIZE_32 |
+                                                UDMA_SRC_INC_NONE|
+                                                UDMA_DST_INC_32 |
+                                                UDMA_ARB_16);
+
+    //
+    // Select this channel for this endpoint, this only affects devices that
+    // have this feature.
+    //
+    MAP_USBEndpointDMAChannel(USB0_BASE, psInst->ucOUTEndpoint, psInst->ucOUTDMA);
+
+    //
+    // Basic configuration for DMA on the IN endpoint.
+    //
+    MAP_uDMAChannelControlSet(psInst->ucINDMA, UDMA_SIZE_32 | UDMA_SRC_INC_32|
+                                               UDMA_DST_INC_NONE | UDMA_ARB_16);
+
+    //
+    // Select this channel for this endpoint, this only affects devices that
+    // have this feature.
+    //
+    MAP_USBEndpointDMAChannel(USB0_BASE, psInst->ucINEndpoint, psInst->ucINDMA);
+
+    //
+    // If we have a control callback, let the client know we are open for
+    // business.
+    //
+    if(psDevice->pfnEventCallback)
+    {
+        //
+        // Pass the connected event to the client.
+        //
+        psDevice->pfnEventCallback(pvInstance, USB_EVENT_CONNECTED, 0, 0);
+    }
+}
+
+//*****************************************************************************
+//
+//! This function should be called once for the mass storage class device to
+//! initialized basic operation and prepare for enumeration.
+//!
+//! \param ulIndex is the index of the USB controller to initialize for
+//! mass storage class device operation.
+//! \param psDevice points to a structure containing parameters customizing
+//! the operation of the mass storage device.
+//!
+//! In order for an application to initialize the USB device mass storage
+//! class, it must first call this function with the a valid mass storage
+//! device class structure in the \e psDevice parameter.  This allows this
+//! function to initialize the USB controller and device code to be prepared to
+//! enumerate and function as a USB mass storage device.
+//!
+//! This function returns a void pointer that must be passed in to all other
+//! APIs used by the mass storage class.
+//!
+//! See the documentation on the tUSBDMSCDevice structure for more information
+//! on how to properly fill the structure members.
+//!
+//! \return Returns 0 on failure or a non-zero void pointer on success.
+//
+//*****************************************************************************
+void *
+USBDMSCInit(unsigned long ulIndex, const tUSBDMSCDevice *psDevice)
+{
+    //
+    // Check parameter validity.
+    //
+    ASSERT(ulIndex == 0);
+    ASSERT(psDevice);
+    ASSERT(psDevice->ppStringDescriptors);
+    ASSERT(psDevice->psPrivateData);
+
+    USBDMSCCompositeInit(ulIndex, psDevice);
+
+    //
+    // All is well so now pass the descriptors to the lower layer and put
+    // the bulk device on the bus.
+    //
+    USBDCDInit(ulIndex, psDevice->psPrivateData->psDevInfo);
+
+    //
+    // Return the pointer to the instance indicating that everything went well.
+    //
+    return((void *)psDevice);
+}
+
+//*****************************************************************************
+//
+//! This function should be called once for the mass storage class device to
+//! initialized basic operation and prepare for enumeration.
+//!
+//! \param ulIndex is the index of the USB controller to initialize for
+//! mass storage class device operation.
+//! \param psDevice points to a structure containing parameters customizing
+//! the operation of the mass storage device.
+//!
+//! In order for an application to initialize the USB device mass storage
+//! class, it must first call this function with the a valid mass storage
+//! device class structure in the \e psDevice parameter.  This allows this
+//! function to initialize the USB controller and device code to be prepared to
+//! enumerate and function as a USB mass storage device.
+//!
+//! This function returns a void pointer that must be passed in to all other
+//! APIs used by the mass storage class.
+//!
+//! See the documentation on the tUSBDMSCDevice structure for more information
+//! on how to properly fill the structure members.
+//!
+//! \return Returns 0 on failure or a non-zero void pointer on success.
+//
+//*****************************************************************************
+void *
+USBDMSCCompositeInit(unsigned long ulIndex, const tUSBDMSCDevice *psDevice)
+{
+    tMSCInstance *psInst;
+    tDeviceDescriptor *psDevDesc;
+
+    //
+    // Check parameter validity.
+    //
+    ASSERT(ulIndex == 0);
+    ASSERT(psDevice);
+    ASSERT(psDevice->ppStringDescriptors);
+    ASSERT(psDevice->psPrivateData);
+
+    //
+    // Initialize the workspace in the passed instance structure.
+    //
+    psInst = psDevice->psPrivateData;
+    psInst->psConfDescriptor = (tConfigDescriptor *)g_pMSCDescriptor;
+    psInst->psDevInfo = &g_sMSCDeviceInfo;
+    psInst->ulUSBBase = USB0_BASE;
+    psInst->bConnected = false;
+    psInst->eMediaStatus = USBDMSC_MEDIA_UNKNOWN;
+
+    //
+    // Set the initial interface and endpoints.
+    //
+    psInst->ucInterface = 0;
+    psInst->ucOUTEndpoint = DATA_OUT_ENDPOINT;
+    psInst->ucOUTDMA = DATA_OUT_DMA_CHANNEL;
+    psInst->ucINEndpoint = DATA_IN_ENDPOINT;
+    psInst->ucINDMA = DATA_IN_DMA_CHANNEL;
+
+    //
+    // Set the initial SCSI state to idle.
+    //
+    psInst->ucSCSIState = STATE_SCSI_IDLE;
+
+    //
+    // Fix up the device descriptor with the client-supplied values.
+    //
+    psDevDesc = (tDeviceDescriptor *)psInst->psDevInfo->pDeviceDescriptor;
+    psDevDesc->idVendor = psDevice->usVID;
+    psDevDesc->idProduct = psDevice->usPID;
+
+    //
+    // Fix up the configuration descriptor with client-supplied values.
+    //
+    psInst->psConfDescriptor->bmAttributes = psDevice->ucPwrAttributes;
+    psInst->psConfDescriptor->bMaxPower =
+                        (unsigned char)(psDevice->usMaxPowermA / 2);
+
+    //
+    // Plug in the client's string stable to the device information
+    // structure.
+    //
+    psInst->psDevInfo->ppStringDescriptors = psDevice->ppStringDescriptors;
+    psInst->psDevInfo->ulNumStringDescriptors
+        = psDevice->ulNumStringDescriptors;
+    psInst->psDevInfo->pvInstance = (void *)psDevice;
+
+    //
+    // If DMA is in use then clear all DMA attributes.
+    //
+    MAP_uDMAChannelAttributeDisable(psInst->ucINDMA, UDMA_ATTR_ALL);
+    MAP_uDMAChannelAttributeDisable(psInst->ucOUTDMA, UDMA_ATTR_ALL);
+
+    //
+    // Open the drive requested.
+    //
+    psInst->pvMedia = psDevice->sMediaFunctions.Open(0);
+
+    if(psInst->pvMedia == 0)
+    {
+        //
+        // There is no media currently present.
+        //
+        psInst->ucSenseKey = SCSI_RS_KEY_NOT_READY;
+        psInst->usAddSenseCode = SCSI_RS_MED_NOT_PRSNT;
+    }
+    else
+    {
+        //
+        // Media is now ready for use.
+        //
+        psInst->ucSenseKey = SCSI_RS_KEY_UNIT_ATTN;
+        psInst->usAddSenseCode = SCSI_RS_MED_NOTRDY2RDY;
+    }
+
+    //
+    // Enable Clocking to the USB controller.
+    //
+    MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_USB0);
+
+    //
+    // Turn on USB Phy clock.
+    //
+    MAP_SysCtlUSBPLLEnable();
+
+    //
+    // Return the pointer to the instance indicating that everything went well.
+    //
+    return((void *)psDevice);
+}
+
+//*****************************************************************************
+//
+//! Shuts down the mass storage device.
+//!
+//! \param pvInstance is the pointer to the device instance structure as
+//! returned by USBDMSCInit() or USBDMSCInitComposite().
+//!
+//! This function terminates mass storage operation for the instance supplied
+//! and removes the device from the USB bus.  Following this call, the
+//! \e psDevice instance may not me used in any other call to the mass storage
+//! device other than USBDMSCInit() or USBDMSCInitComposite().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDMSCTerm(void *pvInstance)
+{
+    const tUSBDMSCDevice *psDevice;
+
+    ASSERT(pvInstance != 0);
+
+    //
+    // Cleanly exit device mode.
+    //
+    USBDCDTerm(0);
+
+    //
+    // Create a device instance pointer.
+    //
+    psDevice = pvInstance;
+
+    //
+    // If the media was opened the close it out.
+    //
+    if(psDevice->psPrivateData->pvMedia != 0)
+    {
+        psDevice->psPrivateData->pvMedia = 0;
+        psDevice->sMediaFunctions.Close(0);
+    }
+}
+
+//*****************************************************************************
+//
+// This function is called by the USB device stack whenever a non-standard
+// request is received.
+//
+// \param pvInstance is instance data for this request.
+// \param pUSBRequest points to the request received.
+//
+// This call parses the provided request structure to determine the command.
+// The only mass storage command supported over endpoint 0 is the Get Max LUN
+// command.
+//
+// \return None.
+//
+//*****************************************************************************
+static void
+HandleRequests(void *pvInstance, tUSBRequest *pUSBRequest)
+{
+    //
+    // This class only support a single LUN.
+    //
+    const static unsigned char ucMaxLun = 0;
+
+    ASSERT(pvInstance != 0);
+
+    //
+    // Determine the type of request.
+    //
+    switch(pUSBRequest->bRequest)
+    {
+        //
+        // A Set Report request is received from the host when it sends an
+        // Output report via endpoint 0.
+        //
+        case USBREQ_GET_MAX_LUN:
+        {
+            //
+            // Send our response to the host.
+            //
+            USBDCDSendDataEP0(0, (unsigned char *)&ucMaxLun, 1);
+
+            break;
+        }
+
+        //
+        // This request was not recognized so stall.
+        //
+        default:
+        {
+            USBDCDStallEP0(0);
+            break;
+        }
+    }
+}
+
+//*****************************************************************************
+//
+// This function is used to handle the SCSI Inquiry command when it is received
+// from the host.
+//
+//*****************************************************************************
+static void
+USBDSCSIInquiry(const tUSBDMSCDevice *psDevice)
+{
+    long lIdx;
+    tMSCInstance *psInst;
+    unsigned long *pulData;
+
+    //
+    // Create a local unsigned long pointer to the command.
+    //
+    pulData = (unsigned long *)g_pucCommand;
+
+    //
+    // Create the serial instance data.
+    //
+    psInst = psDevice->psPrivateData;
+
+    //
+    // Direct Access device, Removable storage and SCSI 1 responses.
+    //
+    pulData[0] = SCSI_INQ_PDT_SBC | (SCSI_INQ_RMB << 8);
+
+    //
+    // Additional Length is fixed at 31 bytes.
+    //
+    pulData[1] = 31;
+
+    //
+    // Copy the Vendor string.
+    //
+    for(lIdx = 0; lIdx < 8; lIdx++)
+    {
+        g_pucCommand[lIdx + 8] = psDevice->pucVendor[lIdx];
+    }
+
+    //
+    // Copy the Product string.
+    //
+    for(lIdx = 0; lIdx < 16; lIdx++)
+    {
+        g_pucCommand[lIdx + 16] = psDevice->pucProduct[lIdx];
+    }
+
+    //
+    // Copy the Version string.
+    //
+    for(lIdx = 0; lIdx < 16; lIdx++)
+    {
+        g_pucCommand[lIdx + 32] = psDevice->pucVersion[lIdx];
+    }
+
+    //
+    // Send the SCSI Inquiry Response.
+    //
+    MAP_USBEndpointDataPut(USB0_BASE, psInst->ucINEndpoint, g_pucCommand, 36);
+
+    //
+    // Send the data to the host.
+    //
+    MAP_USBEndpointDataSend(USB0_BASE, psInst->ucINEndpoint, USB_TRANS_IN);
+
+    //
+    // Set the status so that it can be sent when this response has
+    // has be successfully sent.
+    //
+    g_sSCSICSW.bCSWStatus = 0;
+    g_sSCSICSW.dCSWDataResidue = 0;
+
+    psInst->ucSCSIState = STATE_SCSI_SEND_STATUS;
+}
+
+//*****************************************************************************
+//
+// This function is used to handle the SCSI Read Capacities command when it is
+// received from the host.
+//
+//*****************************************************************************
+static void
+USBDSCSIReadCapacities(const tUSBDMSCDevice *psDevice)
+{
+    unsigned long ulBlocks;
+    tMSCInstance *psInst;
+    unsigned long *pulData;
+
+    //
+    // Create a local unsigned long pointer to the command.
+    //
+    pulData = (unsigned long *)g_pucCommand;
+
+    //
+    // Get our instance data pointer.
+    //
+    psInst = psDevice->psPrivateData;
+
+    if(psInst->pvMedia != 0)
+    {
+        ulBlocks = psDevice->sMediaFunctions.NumBlocks(psInst->pvMedia);
+
+        pulData[0] = 0x08000000;
+
+        //
+        // Fill in the number of blocks, the bytes endianness must be changed.
+        //
+        g_pucCommand[4] = ulBlocks >> 24;
+        g_pucCommand[5] = 0xff & (ulBlocks >> 16);
+        g_pucCommand[6] = 0xff & (ulBlocks >> 8);
+        g_pucCommand[7] = 0xff & (ulBlocks);
+
+        //
+        // Current media capacity
+        //
+        g_pucCommand[8] = 0x2;
+
+        //
+        // Fill in the block size, which is fixed at DEVICE_BLOCK_SIZE.
+        //
+        g_pucCommand[9] = 0xff & (DEVICE_BLOCK_SIZE >> 16);
+        g_pucCommand[10] = 0xff & (DEVICE_BLOCK_SIZE >> 8);
+        g_pucCommand[11] = 0xff & DEVICE_BLOCK_SIZE;
+
+        //
+        // Send out the 12 bytes that are in this response.
+        //
+        MAP_USBEndpointDataPut(USB0_BASE, psInst->ucINEndpoint, g_pucCommand,
+                               12);
+        MAP_USBEndpointDataSend(USB0_BASE, psInst->ucINEndpoint, USB_TRANS_IN);
+
+        //
+        // Set the status so that it can be sent when this response has
+        // has be successfully sent.
+        //
+        g_sSCSICSW.bCSWStatus = 0;
+        g_sSCSICSW.dCSWDataResidue = 0;
+    }
+    else
+    {
+        //
+        // Set the status so that it can be sent when this response has
+        // has be successfully sent.
+        //
+        g_sSCSICSW.bCSWStatus = 1;
+        g_sSCSICSW.dCSWDataResidue = 0;
+
+        //
+        // Stall the IN endpoint
+        //
+        MAP_USBDevEndpointStall(USB0_BASE, psInst->ucINEndpoint, USB_EP_DEV_IN);
+
+        //
+        // Mark the sense code as valid and indicate that these is no media
+        // present.
+        //
+        psInst->ucErrorCode = SCSI_RS_VALID | SCSI_RS_CUR_ERRORS;
+        psInst->ucSenseKey = SCSI_RS_KEY_NOT_READY;
+        psInst->usAddSenseCode = SCSI_RS_MED_NOT_PRSNT;
+    }
+
+    psInst->ucSCSIState = STATE_SCSI_SEND_STATUS;
+}
+
+//*****************************************************************************
+//
+// This function is used to handle the SCSI Read Capacity command when it is
+// received from the host.
+//
+//*****************************************************************************
+static void
+USBDSCSIReadCapacity(const tUSBDMSCDevice *psDevice)
+{
+    unsigned long ulBlocks;
+    tMSCInstance *psInst;
+
+    //
+    // Get our instance data pointer.
+    //
+    psInst = psDevice->psPrivateData;
+
+    ulBlocks = psDevice->sMediaFunctions.NumBlocks(psInst->pvMedia);
+
+    //
+    // Only decrement if any blocks were found.
+    //
+    if(ulBlocks != 0)
+    {
+        //
+        // One less than the maximum number is the last addressable
+        // block.
+        //
+        ulBlocks--;
+    }
+
+    if(psInst->pvMedia != 0)
+    {
+        //
+        // Fill in the number of blocks, the bytes endianness must be changed.
+        //
+        g_pucCommand[0] = 0xff & (ulBlocks >> 24);
+        g_pucCommand[1] = 0xff & (ulBlocks >> 16);
+        g_pucCommand[2] = 0xff & (ulBlocks >> 8);
+        g_pucCommand[3] = 0xff & (ulBlocks);
+
+        g_pucCommand[4] = 0;
+
+        //
+        // Fill in the block size, which is fixed at DEVICE_BLOCK_SIZE.
+        //
+        g_pucCommand[5] = 0xff & (DEVICE_BLOCK_SIZE >> 16);
+        g_pucCommand[6] = 0xff & (DEVICE_BLOCK_SIZE >> 8);
+        g_pucCommand[7] = 0xff & DEVICE_BLOCK_SIZE;
+
+        //
+        // Send the SCSI Inquiry Response.
+        //
+        MAP_USBEndpointDataPut(USB0_BASE, psInst->ucINEndpoint, g_pucCommand,
+                               8);
+        MAP_USBEndpointDataSend(USB0_BASE, psInst->ucINEndpoint, USB_TRANS_IN);
+
+        //
+        // Set the status so that it can be sent when this response has
+        // has be successfully sent.
+        //
+        g_sSCSICSW.bCSWStatus = 0;
+        g_sSCSICSW.dCSWDataResidue = 0;
+    }
+    else
+    {
+        //
+        // Set the status so that it can be sent when this response has
+        // has be successfully sent.
+        //
+        g_sSCSICSW.bCSWStatus = 1;
+        g_sSCSICSW.dCSWDataResidue = 0;
+
+        //
+        // Stall the IN endpoint
+        //
+        MAP_USBDevEndpointStall(USB0_BASE, psInst->ucINEndpoint, USB_EP_DEV_IN);
+
+        //
+        // Mark the sense code as valid and indicate that these is no media
+        // present.
+        //
+        psInst->ucErrorCode = SCSI_RS_VALID | SCSI_RS_CUR_ERRORS;
+        psInst->ucSenseKey = SCSI_RS_KEY_NOT_READY;
+        psInst->usAddSenseCode = SCSI_RS_MED_NOT_PRSNT;
+    }
+
+    psInst->ucSCSIState = STATE_SCSI_SEND_STATUS;
+}
+
+//*****************************************************************************
+//
+// This function is used to handle the SCSI Request Sense command when it is
+// received from the host.
+//
+//*****************************************************************************
+static void
+USBDSCSIRequestSense(const tUSBDMSCDevice *psDevice)
+{
+    tMSCInstance *psInst;
+
+    //
+    // Get our instance data pointer.
+    //
+    psInst = psDevice->psPrivateData;
+
+    //
+    // The request sense response.
+    //
+    g_pucCommand[0] = psInst->ucErrorCode;
+    g_pucCommand[1] = 0;
+    g_pucCommand[2] = psInst->ucSenseKey;
+    *(unsigned long *)&g_pucCommand[3] = 0;
+
+    //
+    // There are 10 more bytes of data.
+    //
+    g_pucCommand[7] = 10;
+
+    *(unsigned long *)&g_pucCommand[8] = 0;
+
+    //
+    // Transition from not ready to ready.
+    //
+    *(unsigned short *)&g_pucCommand[12] = psInst->usAddSenseCode;
+    *(unsigned long *)&g_pucCommand[14] = 0;
+
+    //
+    // Send the SCSI Inquiry Response.
+    //
+    MAP_USBEndpointDataPut(USB0_BASE, psInst->ucINEndpoint, g_pucCommand, 18);
+    MAP_USBEndpointDataSend(USB0_BASE, psInst->ucINEndpoint, USB_TRANS_IN);
+
+    //
+    // Reset the valid flag on errors.
+    //
+    psInst->ucErrorCode = SCSI_RS_CUR_ERRORS;
+
+    //
+    // Set the status so that it can be sent when this response has
+    // has be successfully sent.
+    //
+    g_sSCSICSW.bCSWStatus = 0;
+    g_sSCSICSW.dCSWDataResidue = 0;
+
+    //
+    // Move on to the status phase.
+    //
+    psInst->ucSCSIState = STATE_SCSI_SEND_STATUS;
+}
+
+//*****************************************************************************
+//
+// This function is used to handle the SCSI Read 10 command when it is
+// received from the host.
+//
+//*****************************************************************************
+static void
+USBDSCSIRead10(const tUSBDMSCDevice *psDevice, tMSCCBW *pSCSICBW)
+{
+    unsigned short usNumBlocks;
+    tMSCInstance *psInst;
+
+    //
+    // Default the number of blocks.
+    //
+    usNumBlocks = 0;
+
+    //
+    // Get our instance data pointer.
+    //
+    psInst = psDevice->psPrivateData;
+
+    if(psInst->pvMedia != 0)
+    {
+        //
+        // Get the logical block from the CBW structure. This switching
+        // is required to convert from big to little endian.
+        //
+        psInst->ulCurrentLBA = (pSCSICBW->CBWCB[2] << 24) |
+                               (pSCSICBW->CBWCB[3] << 16) |
+                               (pSCSICBW->CBWCB[4] << 8) |
+                               (pSCSICBW->CBWCB[5] << 0);
+
+        //
+        // More bytes to read.
+        //
+        usNumBlocks = (pSCSICBW->CBWCB[7] << 8) | pSCSICBW->CBWCB[8];
+
+        //
+        // Read the next logical block from the storage device.
+        //
+        if(psDevice->sMediaFunctions.BlockRead(psInst->pvMedia,
+               (unsigned char *)psInst->pulBuffer,
+               psInst->ulCurrentLBA, 1) == 0)
+        {
+            psInst->pvMedia = 0;
+            psDevice->sMediaFunctions.Close(0);
+        }
+    }
+
+    //
+    // If there is media present then start transferring the data.
+    //
+    if(psInst->pvMedia != 0)
+    {
+        //
+        // Enable DMA on the endpoint
+        //
+        MAP_USBEndpointDMAEnable(USB0_BASE, psInst->ucINEndpoint,
+                                 USB_EP_DEV_IN);
+
+        //
+        // Configure the DMA transfer and enable the DMA channel.
+        //
+        MAP_uDMAChannelTransferSet(psInst->ucINDMA,
+                                   UDMA_MODE_BASIC,
+                                   psInst->pulBuffer,
+                                   (void *)USBFIFOAddrGet(USB0_BASE,
+                                                          psInst->ucINEndpoint),
+                                   (MAX_TRANSFER_SIZE >> 2));
+
+        //
+        // Remember that a DMA is in progress.
+        //
+        psInst->ulFlags |= USBD_FLAG_DMA_IN;
+
+        //
+        // Schedule the remaining bytes to send.
+        //
+        psInst->ulBytesToTransfer = (DEVICE_BLOCK_SIZE * usNumBlocks);
+
+        MAP_uDMAChannelEnable(psInst->ucINDMA);
+
+        //
+        // Move on and start sending blocks.
+        //
+        psInst->ucSCSIState = STATE_SCSI_SEND_BLOCKS;
+
+        if(psDevice->pfnEventCallback)
+        {
+            psDevice->pfnEventCallback(0, USBD_MSC_EVENT_READING, 0, 0);
+        }
+    }
+    else
+    {
+        //
+        // Set the status so that it can be sent when this response has
+        // has be successfully sent.
+        //
+        g_sSCSICSW.bCSWStatus = 1;
+        g_sSCSICSW.dCSWDataResidue = 0;
+
+        //
+        // Stall the IN endpoint
+        //
+        MAP_USBDevEndpointStall(USB0_BASE, psInst->ucINEndpoint, USB_EP_DEV_IN);
+
+        //
+        // Mark the sense code as valid and indicate that these is no media
+        // present.
+        //
+        psInst->ucErrorCode = SCSI_RS_VALID | SCSI_RS_CUR_ERRORS;
+        psInst->ucSenseKey = SCSI_RS_KEY_NOT_READY;
+        psInst->usAddSenseCode = SCSI_RS_MED_NOT_PRSNT;
+
+        psInst->ucSCSIState = STATE_SCSI_SEND_STATUS;
+    }
+}
+
+//*****************************************************************************
+//
+// This function is used to handle the SCSI Read 10 command when it is
+// received from the host.
+//
+//*****************************************************************************
+static void
+USBDSCSIWrite10(const tUSBDMSCDevice *psDevice, tMSCCBW *pSCSICBW)
+{
+    unsigned short usNumBlocks;
+    tMSCInstance *psInst;
+
+    //
+    // Get our instance data pointer.
+    //
+    psInst = psDevice->psPrivateData;
+
+    //
+    // If there is media present then start transferring the data.
+    //
+    if(psInst->pvMedia != 0)
+    {
+        //
+        // Get the logical block from the CBW structure. This switching
+        // is required to convert from big to little endian.
+        //
+        psInst->ulCurrentLBA = (pSCSICBW->CBWCB[2] << 24) |
+                         (pSCSICBW->CBWCB[3] << 16) |
+                         (pSCSICBW->CBWCB[4] << 8) |
+                         (pSCSICBW->CBWCB[5] << 0);
+
+        //
+        // More bytes to read.
+        //
+        usNumBlocks = (pSCSICBW->CBWCB[7] << 8) | pSCSICBW->CBWCB[8];
+
+        psInst->ulBytesToTransfer = DEVICE_BLOCK_SIZE * usNumBlocks;
+
+        //
+        // Start sending logical blocks, these are always multiples of
+        // DEVICE_BLOCK_SIZE bytes.
+        //
+        psInst->ucSCSIState = STATE_SCSI_RECEIVE_BLOCKS;
+
+        //
+        // Enable uDMA on the endpoint
+        //
+        MAP_USBEndpointDMAEnable(USB0_BASE, psInst->ucOUTEndpoint,
+                                 USB_EP_DEV_OUT);
+
+        //
+        // Configure the DMA for the OUT transfer.
+        //
+        MAP_uDMAChannelTransferSet(psInst->ucOUTDMA,
+                                   UDMA_MODE_BASIC,
+                                   (void *)USBFIFOAddrGet(USB0_BASE,
+                                                         psInst->ucOUTEndpoint),
+                                                         psInst->pulBuffer,
+                                   (MAX_TRANSFER_SIZE >> 2));
+
+        //
+        // Remember that a DMA is in progress.
+        //
+        psInst->ulFlags |= USBD_FLAG_DMA_OUT;
+
+        //
+        // Enable the OUT DMA transfer.
+        //
+        MAP_uDMAChannelEnable(psInst->ucOUTDMA);
+
+        //
+        // Notify the application of the write event.
+        //
+        if(psDevice->pfnEventCallback)
+        {
+            psDevice->pfnEventCallback(0, USBD_MSC_EVENT_WRITING, 0, 0);
+        }
+    }
+    else
+    {
+        //
+        // Set the status so that it can be sent when this response has
+        // has be successfully sent.
+        //
+        g_sSCSICSW.bCSWStatus = 1;
+        g_sSCSICSW.dCSWDataResidue = 0;
+
+        //
+        // Stall the IN endpoint
+        //
+        MAP_USBDevEndpointStall(USB0_BASE, psInst->ucOUTEndpoint,
+                                USB_EP_DEV_OUT);
+
+        //
+        // Mark the sense code as valid and indicate that these is no media
+        // present.
+        //
+        psInst->ucErrorCode = SCSI_RS_VALID | SCSI_RS_CUR_ERRORS;
+        psInst->ucSenseKey = SCSI_RS_KEY_NOT_READY;
+        psInst->usAddSenseCode = SCSI_RS_MED_NOT_PRSNT;
+
+        psInst->ucSCSIState = STATE_SCSI_SEND_STATUS;
+    }
+}
+
+//*****************************************************************************
+//
+// This function is used to handle the SCSI Mode Sense 6 command when it is
+// received from the host.
+//
+//*****************************************************************************
+static void
+USBDSCSIModeSense6(const tUSBDMSCDevice *psDevice, tMSCCBW *pSCSICBW)
+{
+    tMSCInstance *psInst;
+
+    //
+    // Get our instance data pointer.
+    //
+    psInst = psDevice->psPrivateData;
+
+    //
+    // If there is media present send the response.
+    //
+    if(psInst->pvMedia != 0)
+    {
+        //
+        // Three extra bytes in this response.
+        //
+        g_pucCommand[0] = 3;
+        g_pucCommand[1] = 0;
+        g_pucCommand[2] = 0;
+        g_pucCommand[3] = 0;
+
+        //
+        // Manually send the response back to the host.
+        //
+        MAP_USBEndpointDataPut(USB0_BASE, psInst->ucINEndpoint, g_pucCommand,
+                               4);
+        MAP_USBEndpointDataSend(USB0_BASE, psInst->ucINEndpoint, USB_TRANS_IN);
+
+        //
+        // Set the status so that it can be sent when this response has
+        // has be successfully sent.
+        //
+        g_sSCSICSW.bCSWStatus = 0;
+        g_sSCSICSW.dCSWDataResidue = pSCSICBW->dCBWDataTransferLength - 4;
+    }
+    else
+    {
+        //
+        // Set the status so that it can be sent when this response has
+        // has be successfully sent.
+        //
+        g_sSCSICSW.bCSWStatus = 1;
+        g_sSCSICSW.dCSWDataResidue = 0;
+
+        //
+        // Stall the IN endpoint
+        //
+        MAP_USBDevEndpointStall(USB0_BASE, psInst->ucINEndpoint, USB_EP_DEV_IN);
+
+        //
+        // Mark the sense code as valid and indicate that these is no media
+        // present.
+        //
+        psInst->ucErrorCode = SCSI_RS_VALID | SCSI_RS_CUR_ERRORS;
+        psInst->ucSenseKey = SCSI_RS_KEY_NOT_READY;
+        psInst->usAddSenseCode = SCSI_RS_MED_NOT_PRSNT;
+    }
+
+    psInst->ucSCSIState = STATE_SCSI_SEND_STATUS;
+}
+
+//*****************************************************************************
+//
+// This function is used to send out the response data based on the current
+// status of the mass storage class.
+//
+//*****************************************************************************
+static void
+USBDSCSISendStatus(const tUSBDMSCDevice *psDevice)
+{
+    tMSCInstance *psInst;
+
+    //
+    // Get our instance data pointer.
+    //
+    psInst = psDevice->psPrivateData;
+
+    //
+    // Respond with the requested status.
+    //
+    MAP_USBEndpointDataPut(USB0_BASE, psInst->ucINEndpoint,
+                           (unsigned char *)&g_sSCSICSW, 13);
+    MAP_USBEndpointDataSend(USB0_BASE, psInst->ucINEndpoint, USB_TRANS_IN);
+
+    //
+    // Move the state to status sent so that the next interrupt will move the
+    // statue to idle.
+    //
+    psInst->ucSCSIState = STATE_SCSI_SENT_STATUS;
+}
+
+//*****************************************************************************
+//
+// This function is used to handle all SCSI commands.
+//
+//*****************************************************************************
+unsigned long
+USBDSCSICommand(const tUSBDMSCDevice *psDevice, tMSCCBW *pSCSICBW)
+{
+    unsigned long ulRetCode;
+    unsigned long ulTransferLength;
+    tMSCInstance *psInst;
+
+    //
+    // Get our instance data pointer.
+    //
+    psInst = psDevice->psPrivateData;
+
+    //
+    // Initialize the return code.
+    //
+    ulRetCode = 1;
+
+    //
+    // Save the transfer length because it may be overwritten by some calls.
+    //
+    ulTransferLength = pSCSICBW->dCBWDataTransferLength;
+
+    switch(pSCSICBW->CBWCB[0])
+    {
+        //
+        // Respond to the SCSI Inquiry command.
+        //
+        case SCSI_INQUIRY_CMD:
+        {
+            USBDSCSIInquiry(psDevice);
+
+            break;
+        }
+
+        //
+        // Respond to the test unit ready command.
+        //
+        case SCSI_TEST_UNIT_READY:
+        {
+            g_sSCSICSW.dCSWDataResidue = 0;
+
+            if(psInst->pvMedia != 0)
+            {
+                //
+                // Set the status to success for now, this could be different
+                // if there is no media present.
+                //
+                g_sSCSICSW.bCSWStatus = 0;
+            }
+            else
+            {
+                //
+                // Since there was no media, check for media here.
+                //
+                psInst->pvMedia = psDevice->sMediaFunctions.Open(0);
+
+                //
+                // If it is still not present then fail this command.
+                //
+                if(psInst->pvMedia != 0)
+                {
+                    g_sSCSICSW.bCSWStatus = 0;
+                }
+                else
+                {
+                    g_sSCSICSW.bCSWStatus = 1;
+                }
+            }
+            break;
+        }
+
+        //
+        // Handle the Read Capacities command.
+        //
+        case SCSI_READ_CAPACITIES:
+        {
+            USBDSCSIReadCapacities(psDevice);
+
+            break;
+        }
+
+        //
+        // Handle the Read Capacity command.
+        //
+        case SCSI_READ_CAPACITY:
+        {
+            USBDSCSIReadCapacity(psDevice);
+
+            break;
+        }
+
+        //
+        // Handle the Request Sense command.
+        //
+        case SCSI_REQUEST_SENSE:
+        {
+            USBDSCSIRequestSense(psDevice);
+
+            break;
+        }
+
+        //
+        // Handle the Read 10 command.
+        //
+        case SCSI_READ_10:
+        {
+            USBDSCSIRead10(psDevice, pSCSICBW);
+
+            break;
+        }
+
+        //
+        // Handle the Write 10 command.
+        //
+        case SCSI_WRITE_10:
+        {
+            USBDSCSIWrite10(psDevice, pSCSICBW);
+
+            break;
+        }
+
+        //
+        // Handle the Mode Sense 6 command.
+        //
+        case SCSI_MODE_SENSE_6:
+        {
+            USBDSCSIModeSense6(psDevice, pSCSICBW);
+
+            break;
+        }
+        default:
+        {
+            //
+            // Set the status so that it can be sent when this response has
+            // has be successfully sent.
+            //
+            g_sSCSICSW.bCSWStatus = 1;
+            g_sSCSICSW.dCSWDataResidue = pSCSICBW->dCBWDataTransferLength;
+
+            //
+            // If there is data then there is more work to do.
+            //
+            if(pSCSICBW->dCBWDataTransferLength != 0)
+            {
+                if(pSCSICBW->bmCBWFlags & CBWFLAGS_DIR_IN)
+                {
+                    //
+                    // Stall the IN endpoint
+                    //
+                    MAP_USBDevEndpointStall(USB0_BASE, psInst->ucINEndpoint,
+                                            USB_EP_DEV_IN);
+                }
+                else
+                {
+                    //
+                    // Stall the OUT endpoint
+                    //
+                    MAP_USBDevEndpointStall(USB0_BASE, psInst->ucOUTEndpoint,
+                                            USB_EP_DEV_OUT);
+
+                }
+                //
+                // Send the status once the stall occurs.
+                //
+                psInst->ucSCSIState = STATE_SCSI_SEND_STATUS;
+            }
+
+            //
+            // Set the sense codes.
+            //
+            psInst->ucErrorCode = SCSI_RS_VALID | SCSI_RS_CUR_ERRORS;
+            psInst->ucSenseKey = SCSI_RS_KEY_ILGL_RQST;
+            psInst->usAddSenseCode = SCSI_RS_PV_INVALID;
+
+            break;
+        }
+    }
+
+    //
+    // If there is no data then send out the current status.
+    //
+    if(ulTransferLength == 0)
+    {
+        USBDSCSISendStatus(psDevice);
+    }
+    return(ulRetCode);
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/src/platform/lm3s/usblib/device/usbdmsc.h b/src/platform/lm3s/usblib/device/usbdmsc.h
new file mode 100755
index 00000000..fa9f4c2a
--- /dev/null
+++ b/src/platform/lm3s/usblib/device/usbdmsc.h
@@ -0,0 +1,391 @@
+//*****************************************************************************
+//
+// usbdmsc.h - USB mass storage device class driver.
+//
+// Copyright (c) 2009-2011 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 7611 of the Stellaris USB Library.
+//
+//*****************************************************************************
+
+#ifndef __USBDMSC_H__
+#define __USBDMSC_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+//! \addtogroup msc_device_class_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// USBDMSCMediaChange() ulStatus values.
+//
+//*****************************************************************************
+typedef enum
+{
+    USBDMSC_MEDIA_PRESENT,
+    USBDMSC_MEDIA_NOTPRESENT,
+    USBDMSC_MEDIA_UNKNOWN
+}
+tUSBDMSCMediaStatus;
+
+//*****************************************************************************
+//
+//! Media Access functions.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! This function is used to initialize and open the physical drive number
+    //! associated with the parameter ulDrive.  The function will return zero if
+    //! the drive could not be opened for some reason.  In the case of removable
+    //! device like an SD card this function should return zero if the SD card
+    //! is not present.
+    //! The function returns a pointer to data that should be passed to other
+    //! APIs or it will return 0 if no drive was found.
+    //
+    void *(* Open)(unsigned long ulDrive);
+
+    //*****************************************************************************
+    //
+    // This function close the drive number in use by the mass storage class device.
+    //
+    // /param pvDrive is the pointer that was returned from a call to
+    // USBDMSCStorageOpen().
+    //
+    // This function is used to close the physical drive number associated with the
+    // parameter /e pvDrive.  This function will return 0 if the drive was closed
+    // successfully and any other value will indicate a failure.
+    //
+    // /return Returns 0 if the drive was successfully closed or non-zero for a
+    // failure.
+    //
+    //*****************************************************************************
+    void (* Close)(void * pvDrive);
+
+    //*****************************************************************************
+    //
+    // This function will read a block from a device opened by the
+    // USBDMSCStorageOpen() call.
+    //
+    // /param pvDrive is the pointer that was returned from a call to
+    // USBDMSCStorageOpen().
+    // /param pucData is the buffer that data will be written into.
+    // /param ulSector is the block address to read.
+    // /param ulNumBlocks is the number of blocks to read.
+    //
+    // This function is use to read blocks from a physical device and return them
+    // in the /e pucData buffer.  The data area pointed to by /e pucData should be
+    // at least /e ulNumBlocks * Block Size bytes to prevent overwriting data.
+    //
+    // /return Returns the number of bytes that were read from the device.
+    //
+    //*****************************************************************************
+    unsigned long (* BlockRead)(void * pvDrive, unsigned char *pucData,
+                                unsigned long ulSector,
+                                unsigned long ulNumBlocks);
+
+    //*****************************************************************************
+    //
+    // This function will write a block to a device opened by the
+    // USBDMSCStorageOpen() call.
+    //
+    // /param pvDrive is the pointer that was returned from a call to
+    // USBDMSCStorageOpen().
+    // /param pucData is the buffer that data will be used for writing.
+    // /param ulNumBlocks is the number of blocks to write.
+    //
+    // This function is use to write blocks to a physical device from the buffer
+    // pointed to by the /e pucData buffer.  If the number of blocks is greater than
+    // one then the block address will increment and write to the next block until
+    // /e ulNumBlocks * Block Size bytes have been written.
+    //
+    // /return Returns the number of bytes that were written to the device.
+    //
+    //*****************************************************************************
+    unsigned long (* BlockWrite)(void * pvDrive, unsigned char *pucData,
+                                 unsigned long ulSector,
+                                 unsigned long ulNumBlocks);
+
+    //*****************************************************************************
+    //
+    // This function will return the number of blocks present on a device.
+    //
+    // /param pvDrive is the pointer that was returned from a call to
+    // USBDMSCStorageOpen().
+    //
+    // This function is used to return the total number of blocks on a physical
+    // device based on the /e pvDrive parameter.
+    //
+    // /return Returns the number of blocks that are present in a device.
+    //
+    //*****************************************************************************
+    unsigned long (* NumBlocks)(void * pvDrive);
+
+}
+tMSCDMedia;
+
+//*****************************************************************************
+//
+// These defines control the sizes of USB transfers for data and commands.
+//
+//*****************************************************************************
+#define DEVICE_BLOCK_SIZE       512
+
+//*****************************************************************************
+//
+// PRIVATE
+//
+// This structure defines the private instance data and state variables for the
+// mass storage class.  The memory for this structure is pointed to by
+// the psPrivateData field in the tUSBDMSCDevice structure passed on
+// USBDMSCInit() and should not be modified by any code outside of the mass
+// storage device code.
+//
+//*****************************************************************************
+typedef struct
+{
+    unsigned long ulUSBBase;
+    tDeviceInfo *psDevInfo;
+    tConfigDescriptor *psConfDescriptor;
+
+    //
+    // These three values are used to return the current sense data for an
+    // instance of the mass storage class.
+    //
+    unsigned char ucErrorCode;
+    unsigned char ucSenseKey;
+    unsigned short usAddSenseCode;
+
+    //
+    // The pointer to the instance returned from the Open call to the media.
+    //
+    void *pvMedia;
+
+    volatile tBoolean bConnected;
+
+    //
+    // Holds the flag settings for this instance.
+    //
+    unsigned long ulFlags;
+
+    tUSBDMSCMediaStatus eMediaStatus;
+
+    unsigned long pulBuffer[DEVICE_BLOCK_SIZE>>2];
+    unsigned long ulBytesToTransfer;
+    unsigned long ulCurrentLBA;
+
+    unsigned char ucINEndpoint;
+    unsigned char ucINDMA;
+    unsigned char ucOUTEndpoint;
+    unsigned char ucOUTDMA;
+    unsigned char ucInterface;
+    unsigned char ucSCSIState;
+}
+tMSCInstance;
+
+//*****************************************************************************
+//
+//
+//*****************************************************************************
+#ifdef DEPRECATED
+//*****************************************************************************
+//
+// This is the size in bytes of the private data for the mass storage class.
+//
+// This value is deprecated and should not be used, any new code should just
+// pass in a tMSCInstance structure in the psPrivateData field.
+//
+//*****************************************************************************
+#define USB_MSC_WORKSPACE_SIZE  sizeof(tMSCInstance);
+#endif
+
+//*****************************************************************************
+//
+//! The size of the memory that should be allocated to create a configuration
+//! descriptor for a single instance of the USB Audio Device.
+//! This does not include the configuration descriptor which is automatically
+//! ignored by the composite device class.
+//
+// For reference this is sizeof(g_pAudioControlInterface) +
+// sizeof(g_pAudioStreamInterface
+//
+//*****************************************************************************
+#define COMPOSITE_DMSC_SIZE   (23)
+
+//*****************************************************************************
+//
+//! The structure used by the application to define operating parameters for
+//! the mass storage device.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! The vendor ID that this device is to present in the device descriptor.
+    //
+    unsigned short usVID;
+
+    //
+    //! The product ID that this device is to present in the device descriptor.
+    //
+    unsigned short usPID;
+
+    //
+    //! 8 byte vendor string.
+    //
+    unsigned char pucVendor[8];
+
+    //
+    //! 16 byte vendor string.
+    //
+    unsigned char pucProduct[16];
+
+    //
+    //! 4 byte vendor string.
+    //
+    unsigned char pucVersion[4];
+
+    //
+    //! The maximum power consumption of the device, expressed in milliamps.
+    //
+    unsigned short usMaxPowermA;
+
+    //
+    //! Indicates whether the device is self or bus-powered and whether or not
+    //! it supports remote wakeup.  Valid values are USB_CONF_ATTR_SELF_PWR or
+    //! USB_CONF_ATTR_BUS_PWR, optionally ORed with USB_CONF_ATTR_RWAKE.
+    //
+    unsigned char ucPwrAttributes;
+
+    //
+    //! A pointer to the string descriptor array for this device.  This array
+    //! must contain the following string descriptor pointers in this order.
+    //! Language descriptor, Manufacturer name string (language 1), Product
+    //! name string (language 1), Serial number string (language 1), MSC
+    //! Interface description string (language 1), Configuration description
+    //! string (language 1).
+    //!
+    //! If supporting more than 1 language, the descriptor block (except for
+    //! string descriptor 0) must be repeated for each language defined in the
+    //! language descriptor.
+    //!
+    //
+    const unsigned char * const *ppStringDescriptors;
+
+    //
+    //! The number of descriptors provided in the ppStringDescriptors
+    //! array.  This must be 1 + ((5 + (num HID strings)) * (num languages)).
+    //
+    unsigned long ulNumStringDescriptors;
+
+    //
+    //! This structure holds the access functions for the media used by this
+    //! instance of the mass storage class device.  All of the functions in this
+    //! structure are required to be filled out with valid functions.
+    //
+    tMSCDMedia sMediaFunctions;
+
+    //
+    //! This is the callback function for various events that occur during
+    //! mass storage class operation.
+    //
+    tUSBCallback pfnEventCallback;
+
+    //
+    //! A pointer to the private instance data for this device.  This memory
+    //! must remain accessible for as long as the MSC device is in use and must
+    //! not be modified by any code outside the MSC class driver.
+    //
+    tMSCInstance *psPrivateData;
+}
+tUSBDMSCDevice;
+
+//*****************************************************************************
+//
+// MSC-specific device class driver events
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! This event indicates that the host has completed other operations and is
+//! no longer accessing the device.
+//
+//*****************************************************************************
+#define USBD_MSC_EVENT_IDLE     (USBD_MSC_EVENT_BASE + 0)
+
+//*****************************************************************************
+//
+//! This event indicates that the host is reading the storage media.
+//
+//*****************************************************************************
+#define USBD_MSC_EVENT_READING  (USBD_MSC_EVENT_BASE + 1)
+
+//*****************************************************************************
+//
+//! This event indicates that the host is writing to the storage media.
+//
+//*****************************************************************************
+#define USBD_MSC_EVENT_WRITING  (USBD_MSC_EVENT_BASE + 2)
+
+extern tDeviceInfo g_sMSCDeviceInfo;
+
+//*****************************************************************************
+//
+// API Function Prototypes
+//
+//*****************************************************************************
+extern void *USBDMSCInit(unsigned long ulIndex,
+                         const tUSBDMSCDevice *psMSCDevice);
+extern void *USBDMSCCompositeInit(unsigned long ulIndex,
+                                  const tUSBDMSCDevice *psMSCDevice);
+extern void USBDMSCTerm(void *pvInstance);
+extern void USBDMSCMediaChange(void *pvInstance,
+                               tUSBDMSCMediaStatus eMediaStatus);
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/platform/lm3s/usblib/host/usbhaudio.c b/src/platform/lm3s/usblib/host/usbhaudio.c
new file mode 100755
index 00000000..9927616a
--- /dev/null
+++ b/src/platform/lm3s/usblib/host/usbhaudio.c
@@ -0,0 +1,1519 @@
+//*****************************************************************************
+//
+// usbhaudio.c - USB host audio driver.
+//
+// Copyright (c) 2010-2011 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 7611 of the Stellaris USB Library.
+//
+//*****************************************************************************
+
+#include "inc/hw_types.h"
+#include "driverlib/usb.h"
+#include "usblib/usblib.h"
+#include "usblib/usbaudio.h"
+#include "usblib/host/usbhost.h"
+#include "usblib/host/usbhaudio.h"
+
+//*****************************************************************************
+//
+//! \addtogroup usblib_host_class
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// These defines are used with the USBHostAudioFormatSet()
+// USBHostAudioFormatGet() to parse out interface number and alternate
+// setting number for an interface.
+//
+//*****************************************************************************
+#define INTERFACE_NUM_M         0x000000FF
+#define INTERFACE_ALTSETTING_M  0x0000FF00
+#define INTERFACE_ALTSETTING_S  8
+
+//*****************************************************************************
+//
+// Used to indicate an invalid interface descriptor number.
+//
+//*****************************************************************************
+#define INVALID_INTERFACE       0xffffffff
+
+//*****************************************************************************
+//
+// Forward declarations for the driver open and close calls.
+//
+//*****************************************************************************
+static void *USBAudioOpen(tUSBHostDevice *pDevice);
+static void USBAudioClose(void *pvInstance);
+
+//*****************************************************************************
+//
+// This is the structure for an instance of a USB host audio driver.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    // Save the device instance.
+    //
+    tUSBHostDevice *pDevice;
+
+    //
+    // Used to save the call back.
+    //
+    tUSBHostAudioCallback pfnCallback;
+
+    //
+    // This is the control interface.
+    //
+    unsigned char ucIControl;
+
+    //
+    // This is the output streaming interface.
+    //
+    unsigned char ucOutInterface;
+
+    //
+    // This is the currently selected active output interface used with
+    // ucOutInterface interface.
+    //
+    unsigned char ucOutAltSetting;
+
+    //
+    // This is the streaming interface.
+    //
+    unsigned char ucInInterface;
+
+    //
+    // This is the currently selected active input interface used with
+    // ucInInterface interface.
+    //
+    unsigned char ucInAltSetting;
+
+    //
+    // The Isochronous endpoint addresses.
+    //
+    unsigned char ucIsochInAddress;
+    unsigned char ucIsochOutAddress;
+
+    tACInputTerminal *pInTerminal;
+    tACOutputTerminal *pOutTerminal;
+
+    //
+    // Holds the identifier for the Feature Unit for controlling volume.
+    //
+    unsigned char ucVolumeIDOut;
+    unsigned char ucVolumeIDIn;
+
+    //
+    // Holds what types of controls are enabled on the device.
+    //
+    unsigned short pusControls[3];
+
+    //
+    // Isochronous IN pipe.
+    //
+    unsigned long ulIsochInPipe;
+    unsigned short usPipeSizeIn;
+    tUSBHostAudioCallback pfnInCallback;
+    void *pvInBuffer;
+
+    //
+    // Isochronous OUT pipe.
+    //
+    unsigned long ulIsochOutPipe;
+    unsigned short usPipeSizeOut;
+    tUSBHostAudioCallback pfnOutCallback;
+    void *pvOutBuffer;
+
+    //
+    // State flags for this audio instance.
+    //
+    unsigned long ulFlags;
+}
+tUSBHostAudioInstance;
+
+//*****************************************************************************
+//
+// The internal flags for an audio interface.
+//
+//*****************************************************************************
+#define AUDIO_FLAG_OUT_ACTIVE   1   // Audio output is active.
+#define AUDIO_FLAG_IN_ACTIVE    2   // Audio input is active.
+
+//*****************************************************************************
+//
+// The USB Host audio instance.
+//
+//*****************************************************************************
+static tUSBHostAudioInstance g_AudioDevice =
+{
+    0
+};
+
+//*****************************************************************************
+//
+//! This constant global structure defines the Audio Class Driver that is
+//! provided with the USB library.
+//
+//*****************************************************************************
+const tUSBHostClassDriver g_USBHostAudioClassDriver =
+{
+    USB_CLASS_AUDIO,
+    USBAudioOpen,
+    USBAudioClose,
+    0
+};
+
+//*****************************************************************************
+//
+// This is the internal function that handles callbacks from the USB IN pipe.
+//
+//*****************************************************************************
+static void
+PipeCallbackIN(unsigned long ulPipe, unsigned long ulEvent)
+{
+    //
+    // Only handle the data available callback and pass it on to the
+    // application.
+    //
+    if(ulEvent == USB_EVENT_RX_AVAILABLE)
+    {
+        if(g_AudioDevice.pfnInCallback)
+        {
+            g_AudioDevice.pfnInCallback(
+                g_AudioDevice.pvInBuffer, 0, USB_EVENT_RX_AVAILABLE);
+        }
+    }
+}
+
+//*****************************************************************************
+//
+// This is the internal function that handles callbacks from the USB OUT pipe.
+//
+//*****************************************************************************
+static void
+PipeCallbackOUT(unsigned long ulPipe, unsigned long ulEvent)
+{
+    //
+    // Only handle the transmit complete callback and pass it on to the
+    // application.
+    //
+    if(ulEvent == USB_EVENT_TX_COMPLETE)
+    {
+        if(g_AudioDevice.pfnOutCallback)
+        {
+            g_AudioDevice.pfnOutCallback(
+                g_AudioDevice.pvOutBuffer, 0, USB_EVENT_TX_COMPLETE);
+        }
+    }
+}
+
+//*****************************************************************************
+//
+// Finds a given terminal and type in an audio configuration descriptor.
+//
+//*****************************************************************************
+static tDescriptorHeader *
+AudioTerminalGet(tConfigDescriptor *pConfigDesc, unsigned long ulTerminal,
+                 unsigned long ulTerminalType)
+{
+    tACOutputTerminal *pOutput;
+    tACFeatureUnit *pFeature;
+    tDescriptorHeader *pHeader;
+    long lBytesRemaining;
+
+    pHeader = (tDescriptorHeader *)pConfigDesc;
+    lBytesRemaining = pConfigDesc->wTotalLength;
+
+    while(lBytesRemaining > 0)
+    {
+        //
+        // Output and input terminals are the same past the bDescriptorSubtype
+        // and wTerminalType that are being searched for.
+        //
+        pOutput = (tACOutputTerminal *)pHeader;
+
+        //
+        // Only CS_INTERFACE descriptors can be a terminal.
+        //
+        if((pHeader->bDescriptorType == USB_DTYPE_CS_INTERFACE) &&
+           (ulTerminal == pOutput->bDescriptorSubtype))
+        {
+            if((pOutput->bDescriptorSubtype == USB_AI_OUTPUT_TERMINAL) ||
+               (pOutput->bDescriptorSubtype == USB_AI_INPUT_TERMINAL))
+
+            {
+                //
+                // If this was the terminal type that was requested, the
+                // return it.
+                //
+                if(pOutput->wTerminalType == ulTerminalType)
+                {
+                    return(pHeader);
+                }
+            }
+            else if(pOutput->bDescriptorSubtype == USB_AI_FEATURE_UNIT)
+            {
+                pFeature = (tACFeatureUnit *)pHeader;
+
+                if(pFeature->bUnitID == ulTerminalType)
+                {
+                    return(pHeader);
+                }
+            }
+        }
+
+        //
+        // Decrease the bytes remaining by the size of this descriptor.
+        //
+        lBytesRemaining -=  pHeader->bLength;
+
+        //
+        // Move the pointer to the next header.
+        //
+        pHeader = (tDescriptorHeader*)((unsigned long)pHeader +
+                                       pHeader->bLength);
+    }
+    return((tDescriptorHeader *)0);
+}
+
+//*****************************************************************************
+//
+// This function returns the interface number for the control interface
+// in the structure passed in the pConfigDesc.
+//
+// \param pConfigDescriptor is a pointer to the memory containing a valid
+//        configuration descriptor for a device.
+//
+// This function searches a configuration descriptor for a control interface
+// descriptor.  The function only search for the first descriptor and then
+// returns when it finds one.
+//
+// \return The first control interface descriptor number for an audio device
+//         or INVALID_INTERFACE if no control interface descriptor was found.
+//
+//*****************************************************************************
+static unsigned long
+AudioControlGet(tConfigDescriptor *pConfigDesc)
+{
+    tDescriptorHeader *pHeader;
+    tInterfaceDescriptor *pInterface;
+    unsigned long ulInterface;
+    long lBytes;
+
+    pHeader = (tDescriptorHeader *)pConfigDesc;
+    lBytes = pConfigDesc->wTotalLength;
+
+    //
+    // Initialize the interface number to an invalid value.
+    //
+    ulInterface = INVALID_INTERFACE;
+
+    //
+    // Search the whole configuration descriptor.
+    //
+    while(lBytes > 0)
+    {
+        //
+        // Find an interface descriptor and see if it is a control interface.
+        //
+        if(pHeader->bDescriptorType == USB_DTYPE_INTERFACE)
+        {
+            pInterface = (tInterfaceDescriptor *)pHeader;
+
+            //
+            // If this is the control interface then return the value to the
+            // caller.
+            //
+            if(pInterface->bInterfaceSubClass == USB_ASC_AUDIO_CONTROL)
+            {
+                ulInterface = pInterface->bInterfaceNumber;
+
+                break;
+            }
+        }
+
+        //
+        // Decrease the bytes remaining by the size of this descriptor.
+        //
+        lBytes -= pHeader->bLength;
+
+        //
+        // Move the pointer to the next header.
+        //
+        pHeader = (tDescriptorHeader*)((unsigned long)pHeader +
+                                       pHeader->bLength);
+    }
+    return(ulInterface);
+}
+
+//*****************************************************************************
+//
+// If it exists, finds the correct audio interface for a given audio format.
+//
+//*****************************************************************************
+static unsigned long
+AudioGetInterface(tUSBHostAudioInstance *pAudioDevice,
+                  unsigned short usFormat, unsigned long ulSampleRate,
+                  unsigned long ulBytes, unsigned long ulChannels,
+                  unsigned long ulFlags)
+{
+    tDescriptorHeader *pHeader;
+    tInterfaceDescriptor *pInterface;
+    tEndpointDescriptor *pINEndpoint, *pOUTEndpoint;
+    tACHeader *pACHeader;
+    tACGeneral *pGeneral;
+    tASFormat *pFormat;
+    tEndpointDescriptor *pEndpoint;
+    unsigned char *pucValue;
+    unsigned long ulValue;
+    long lBytes, lIdx;
+
+    //
+    // Initialize the Interface pointer to null.
+    //
+    pInterface = 0;
+    pINEndpoint = 0;
+    pOUTEndpoint = 0;
+
+    //
+    // Start at the top of the configuration descriptor.
+    //
+    pHeader = (tDescriptorHeader *)pAudioDevice->pDevice->pConfigDescriptor;
+
+    lBytes = pAudioDevice->pDevice->pConfigDescriptor->wTotalLength;
+
+    while(lBytes > 0)
+    {
+        if(pHeader->bDescriptorType == USB_DTYPE_INTERFACE)
+        {
+            //
+            // If a new interface was found and the last one satisfied all
+            // requirements then a valid interface was found so break out.
+            //
+            if(pInterface)
+            {
+                break;
+            }
+
+            //
+            // Get the new interface pointer.
+            //
+            pInterface = (tInterfaceDescriptor *)pHeader;
+
+            //
+            // Reset the endpoints on finding a new interface descriptor.
+            //
+            pINEndpoint = 0;
+            pOUTEndpoint = 0;
+
+            //
+            // If this is not a valid audio streaming interface then reset
+            // the interface pointer to null.
+            //
+            if((pInterface->bNumEndpoints == 0) ||
+               (pInterface->bInterfaceClass != USB_CLASS_AUDIO) ||
+               (pInterface->bInterfaceSubClass != USB_ASC_AUDIO_STREAMING))
+            {
+                pInterface = 0;
+            }
+        }
+        if((pInterface) && (pHeader->bDescriptorType == USB_DTYPE_CS_INTERFACE))
+        {
+            pACHeader = (tACHeader *)pHeader;
+
+            //
+            // If this is a General descriptor the check if the format matches.
+            //
+            if(pACHeader->bDescriptorSubtype == USB_AS_GENERAL)
+            {
+                //
+                // Just save the pointer to the format descriptor.
+                //
+                pGeneral = (tACGeneral *)pHeader;
+
+                //
+                // If this interface has the wrong format then set it to null
+                // so that the rest of this interface is ignored.
+                //
+                if(pGeneral->wFormatTag != usFormat)
+                {
+                    pInterface = 0;
+                }
+            }
+            else if(pACHeader->bDescriptorSubtype == USB_AS_FORMAT_TYPE)
+            {
+                pFormat = (tASFormat *)pHeader;
+
+                //
+                // If the number of bytes per sample and number of channels do
+                // not match then reset the interface pointer so that the rest
+                // of this interface is ignored.
+                //
+                if((pFormat->bNrChannels != ulChannels) ||
+                   (pFormat->bSubFrameSize != ulBytes))
+                {
+                    pInterface = 0;
+                }
+                else
+                {
+                    pucValue = &pFormat->tSamFreq;
+
+                    //
+                    // Attempt to find the sample rate in the sample rate
+                    // table for this interface.
+                    //
+                    for(lIdx = 0; lIdx < pFormat->bSamFreqType; lIdx++)
+                    {
+                        ulValue = (*((unsigned long *)&pucValue[lIdx * 3]) &
+                                   0xffffff);
+
+                        if(ulValue == ulSampleRate)
+                        {
+                            break;
+                        }
+                    }
+
+                    //
+                    // If the sample rate was not found then set the interface
+                    // pointer to null so that the rest of this interface is
+                    // ignored.
+                    //
+                    if(lIdx == pFormat->bSamFreqType)
+                    {
+                        pInterface = 0;
+                    }
+                }
+            }
+        }
+        else if((pInterface) &&
+                (pHeader->bDescriptorType == USB_DTYPE_ENDPOINT))
+        {
+            pEndpoint = (tEndpointDescriptor *)pHeader;
+
+            //
+            // See what direction is being requested.
+            //
+            if(ulFlags & USBH_AUDIO_FORMAT_IN)
+            {
+                //
+                // If this is an input endpoint and is just a feed back input
+                // then ignore it.
+                //
+                if(pEndpoint->bEndpointAddress & USB_EP_DESC_IN)
+                {
+                    if((pEndpoint->bmAttributes & USB_EP_ATTR_USAGE_M)
+                        == USB_EP_ATTR_USAGE_FEEDBACK)
+                    {
+                        pInterface = 0;
+                    }
+                    else
+                    {
+                        //
+                        // Save this endpoint as a possible valid endpoint
+                        //
+                        pINEndpoint = pEndpoint;
+                    }
+                }
+            }
+            else
+            {
+                //
+                // If this is an output endpoint and is just a feed back input
+                // then ignore it.
+                //
+                if((pEndpoint->bEndpointAddress & USB_EP_DESC_IN) == 0)
+                {
+                    if((pEndpoint->bmAttributes & USB_EP_ATTR_USAGE_M)
+                        == USB_EP_ATTR_USAGE_FEEDBACK)
+                    {
+                        pInterface = 0;
+                    }
+                    else
+                    {
+                        //
+                        // Save this endpoint as a possible valid endpoint;
+                        //
+                        pOUTEndpoint = pEndpoint;
+                    }
+                }
+            }
+        }
+
+        //
+        // Decrease the bytes remaining by the size of this descriptor.
+        //
+        lBytes -= pHeader->bLength;
+
+        //
+        // Move the pointer to the next header.
+        //
+        pHeader = (tDescriptorHeader*)((unsigned long)pHeader +
+                                       pHeader->bLength);
+    }
+
+    //
+    // If there is still a valid interface then return the values.
+    //
+    if(pInterface)
+    {
+        //
+        // Check a valid IN endpoint descriptor.
+        //
+        if(pINEndpoint)
+        {
+            //
+            // Save the endpoint address.
+            //
+            g_AudioDevice.ucIsochInAddress = pINEndpoint->bEndpointAddress &
+                                             USB_EP_DESC_NUM_M;
+
+            //
+            // If there is no current pipe then just allocate a new one with
+            // the settings for this interface.
+            //
+            if(g_AudioDevice.ulIsochInPipe == 0)
+            {
+                //
+                // Allocate the USB Pipe for this Isochronous IN end point.
+                //
+                g_AudioDevice.ulIsochInPipe =
+                    USBHCDPipeAllocSize(0, USBHCD_PIPE_ISOC_IN_DMA,
+                                        g_AudioDevice.pDevice->ulAddress,
+                                        pINEndpoint->wMaxPacketSize,
+                                        PipeCallbackIN);
+            }
+            else if(g_AudioDevice.usPipeSizeIn < pINEndpoint->wMaxPacketSize)
+            {
+                //
+                // Free the old endpoint and allocate a new one.
+                //
+                USBHCDPipeFree(g_AudioDevice.ulIsochInPipe);
+
+                //
+                // Allocate the USB Pipe for this Isochronous IN end point.
+                //
+                g_AudioDevice.ulIsochInPipe =
+                    USBHCDPipeAllocSize(0, USBHCD_PIPE_ISOC_IN_DMA,
+                                        g_AudioDevice.pDevice->ulAddress,
+                                        pINEndpoint->wMaxPacketSize,
+                                        PipeCallbackIN);
+
+                //
+                // Save the new size of the maximum packet size for this
+                // USB pipe.
+                //
+                g_AudioDevice.usPipeSizeIn = pINEndpoint->wMaxPacketSize;
+            }
+
+            //
+            // Configure the USB pipe as a Isochronous IN end point.
+            //
+            USBHCDPipeConfig(g_AudioDevice.ulIsochInPipe,
+                             pINEndpoint->wMaxPacketSize,
+                             0,
+                             g_AudioDevice.ucIsochInAddress);
+        }
+
+        //
+        // Check a valid OUT endpoint descriptor.
+        //
+        if(pOUTEndpoint)
+        {
+            //
+            // Save the endpoint address.
+            //
+            g_AudioDevice.ucIsochOutAddress = pOUTEndpoint->bEndpointAddress &
+                                              USB_EP_DESC_NUM_M;
+
+            //
+            // If there is no current pipe then just allocate a new one with
+            // the settings for this interface.
+            //
+            if(g_AudioDevice.ulIsochInPipe == 0)
+            {
+                //
+                // Allocate the USB Pipe for this Isochronous OUT end point.
+                //
+                g_AudioDevice.ulIsochOutPipe =
+                    USBHCDPipeAllocSize(0, USBHCD_PIPE_ISOC_OUT,
+                                        g_AudioDevice.pDevice->ulAddress,
+                                        pOUTEndpoint->wMaxPacketSize,
+                                        PipeCallbackOUT);
+            }
+            else if(g_AudioDevice.usPipeSizeOut < pOUTEndpoint->wMaxPacketSize)
+            {
+                //
+                // Free the old endpoint and allocate a new one.
+                //
+                USBHCDPipeFree(g_AudioDevice.ulIsochOutPipe);
+
+                //
+                // Allocate the USB Pipe for this Isochronous OUT end point.
+                //
+                g_AudioDevice.ulIsochOutPipe =
+                    USBHCDPipeAllocSize(0, USBHCD_PIPE_ISOC_OUT_DMA,
+                                        g_AudioDevice.pDevice->ulAddress,
+                                        pOUTEndpoint->wMaxPacketSize,
+                                        PipeCallbackOUT);
+
+                //
+                // Save the new size of the maximum packet size for this
+                // USB pipe.
+                //
+                g_AudioDevice.usPipeSizeOut = pOUTEndpoint->wMaxPacketSize;
+            }
+
+            //
+            // Configure the USB pipe as a Isochronous OUT end point.
+            //
+            USBHCDPipeConfig(g_AudioDevice.ulIsochOutPipe,
+                             pOUTEndpoint->wMaxPacketSize, 0,
+                             g_AudioDevice.ucIsochOutAddress);
+        }
+
+        return(pInterface->bInterfaceNumber |
+               (pInterface->bAlternateSetting << INTERFACE_ALTSETTING_S));
+    }
+    return(INVALID_INTERFACE);
+}
+
+//*****************************************************************************
+//
+// This function is used to open an instance of the USB host audio driver.
+//
+// \param pDevice is a pointer to the device information structure.
+//
+// This function attempts to open an instance of the USB host audio driver
+// based on the information contained in the pDevice structure.  This call
+// fails if there are not sufficient resources to open the device.  The
+// function returns a value that should be passed back into USBHostAudioClose()
+// when the driver is no longer needed.
+//
+// \return The function returns a pointer to a USB host audio driver
+// instance.
+//
+//*****************************************************************************
+static void *
+USBAudioOpen(tUSBHostDevice *pDevice)
+{
+    unsigned long ulTemp;
+    tConfigDescriptor *pConfigDesc;
+
+    //
+    // Don't allow the device to be opened without closing first.
+    //
+    if(g_AudioDevice.pDevice)
+    {
+        return(0);
+    }
+
+    g_AudioDevice.pDevice = pDevice;
+
+    //
+    // Save a shorter name for the configuration descriptor.
+    //
+    pConfigDesc = pDevice->pConfigDescriptor;
+
+    //
+    // Find the input terminal.
+    //
+    g_AudioDevice.pInTerminal =
+        (tACInputTerminal *)AudioTerminalGet(pConfigDesc,
+                                             USB_AI_INPUT_TERMINAL,
+                                             USB_TTYPE_STREAMING);
+
+    //
+    // Find the output terminal.
+    //
+    g_AudioDevice.pOutTerminal =
+        (tACOutputTerminal *)AudioTerminalGet(pConfigDesc,
+                                              USB_AI_OUTPUT_TERMINAL,
+                                              USB_TTYPE_STREAMING);
+
+    //
+    // Need some kind of terminal to send or receive audio from.
+    //
+    if((g_AudioDevice.pOutTerminal == 0) &&
+       (g_AudioDevice.pInTerminal == 0))
+    {
+        return(0);
+    }
+
+    //
+    // Find the Audio control interface.
+    //
+    ulTemp = AudioControlGet(pConfigDesc);
+
+    if(ulTemp == INVALID_INTERFACE)
+    {
+        return(0);
+    }
+
+    //
+    // Save the control interface index and increment the number
+    // of interfaces that have been found.
+    //
+    g_AudioDevice.ucIControl = (unsigned char)ulTemp;
+
+    //
+    // If the call back exists, call it with an Open event.
+    //
+    if(g_AudioDevice.pfnCallback != 0)
+    {
+        g_AudioDevice.pfnCallback((void *)&g_AudioDevice,
+                                         0, USBH_AUDIO_EVENT_OPEN);
+    }
+
+    //
+    // Save the device pointer.
+    //
+    g_AudioDevice.pDevice = pDevice;
+
+    //
+    // Allocate the USB Pipe for this Isochronous IN end point.
+    //
+    g_AudioDevice.ulIsochInPipe =
+        USBHCDPipeAllocSize(0, USBHCD_PIPE_ISOC_IN_DMA,
+                            g_AudioDevice.pDevice->ulAddress, 256,
+                            PipeCallbackIN);
+    g_AudioDevice.usPipeSizeIn = 256;
+
+    //
+    // Allocate the USB Pipe for this Isochronous OUT end point.
+    //
+    g_AudioDevice.ulIsochOutPipe =
+        USBHCDPipeAllocSize(0, USBHCD_PIPE_ISOC_OUT,
+                            g_AudioDevice.pDevice->ulAddress, 256,
+                            PipeCallbackOUT);
+    g_AudioDevice.usPipeSizeOut = 256;
+
+    //
+    // Clear the flags.
+    //
+    g_AudioDevice.ulFlags = 0;
+
+    //
+    // Return the only instance of this device.
+    //
+    return(&g_AudioDevice);
+}
+
+
+//*****************************************************************************
+//
+// This function is used to release an instance of the USB host audio driver.
+//
+// \param pvInstance is an instance pointer that needs to be released.
+//
+// This function frees up any resources in use by the USB host audio
+// driver instance that is passed in.  The \e pvInstance pointer should be a
+// valid value that was returned from a call to USBHostAudioOpen().
+//
+// \return None.
+//
+//*****************************************************************************
+static void
+USBAudioClose(void *pvInstance)
+{
+    //
+    // Do nothing if there is not a driver open.
+    //
+    if(g_AudioDevice.pDevice == 0)
+    {
+        return;
+    }
+
+    //
+    // Reset the device pointer.
+    //
+    g_AudioDevice.pDevice = 0;
+
+    //
+    // Free the Isochronous IN pipe.
+    //
+    if(g_AudioDevice.ulIsochInPipe != 0)
+    {
+        USBHCDPipeFree(g_AudioDevice.ulIsochInPipe);
+    }
+
+    //
+    // Free the Isochronous OUT pipe.
+    //
+    if(g_AudioDevice.ulIsochOutPipe != 0)
+    {
+        USBHCDPipeFree(g_AudioDevice.ulIsochOutPipe);
+    }
+
+    //
+    // If the call back exists then call it.
+    //
+    if(g_AudioDevice.pfnCallback != 0)
+    {
+        g_AudioDevice.pfnCallback((void *)&g_AudioDevice,
+                                         0, USBH_AUDIO_EVENT_CLOSE);
+    }
+}
+
+//*****************************************************************************
+//
+//! This function should be called before any devices are present to enable
+//! the host audio class driver.
+//!
+//! \param ulIndex is the audio device to open (currently only 0 is supported).
+//! \param pfnCallback is the driver call back for host audio events.
+//!
+//! This function is called to open an instance of a host audio device and
+//! should provide a valid callback function for host audio events in the
+//! \e pfnCallback parameter.  This function must be called before the USB
+//! host code can successfully enumerate an audio device.
+//!
+//! \return This function returns the driver instance to use for the other
+//! host audio functions.  If there is no instance available at the time of
+//! this call, this function returns zero.
+//
+//*****************************************************************************
+unsigned long
+USBHostAudioOpen(unsigned long ulIndex, tUSBHostAudioCallback pfnCallback)
+{
+    //
+    // Only one audio device is supported at this time and on one instance
+    // is supported so if there is already a call back then fail.
+    //
+    if((ulIndex != 0) || (g_AudioDevice.pfnCallback))
+    {
+        return(0);
+    }
+
+    //
+    // Save the call back.
+    //
+    g_AudioDevice.pfnCallback = pfnCallback;
+
+    //
+    // Return the requested device instance.
+    //
+    return((unsigned long)&g_AudioDevice);
+}
+
+//*****************************************************************************
+//
+//! This function should be called to release an audio device instance.
+//!
+//! \param ulInstance is the device instance that is to be released.
+//!
+//! This function is called when a host audio device needs to be released.
+//! This could be in preparation for shutdown or a switch to USB device mode,
+//! for example.  Following this call, the audio device is available and can
+//! be opened again using a call to USBHostAudioOpen().  After calling this
+//! function, the host audio driver will no longer provide any callbacks or
+//! accept calls to other audio driver APIs.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostAudioClose(unsigned long ulInstance)
+{
+    tUSBHostAudioInstance *pAudioDevice;
+
+    //
+    // Get a pointer to the device instance data from the handle.
+    //
+    pAudioDevice = (tUSBHostAudioInstance *)ulInstance;
+
+    //
+    // Close the audio device.
+    //
+    USBAudioClose((void *)pAudioDevice);
+
+    //
+    // Clear the call back indicating that the device is now closed.
+    //
+    pAudioDevice->pfnCallback = 0;
+}
+
+//*****************************************************************************
+//
+// This function is used to request settings from a given audio interface.
+//
+// \param ulInstance is an instance value for the audio device to access.
+// \param ulInterface is the interface to access.
+// \param ulChannel is the channel number to access.
+// \param ulRequest is the audio device request.
+//
+// This function is used to get volume control parameters from a given
+// interface and on a given channel.  The \e ulInterface is the interface to
+// make the request specified by \e ulChannel and \e ulRequest.  The
+// \e ulRequest parameter must be one of the USB_AC_GET_* values.
+//
+// \return This function returns the requested value.
+//
+//*****************************************************************************
+static unsigned long
+VolumeSettingGet(unsigned long ulInstance, unsigned long ulInterface,
+                 unsigned long ulChannel, unsigned long ulRequest)
+{
+    unsigned long ulValue;
+    tUSBHostAudioInstance *pAudioDevice;
+    tUSBRequest SetupPacket;
+
+    pAudioDevice = (tUSBHostAudioInstance *)ulInstance;
+
+    ulValue = 0;
+
+    //
+    // This is a Class specific Interface IN request.
+    //
+    SetupPacket.bmRequestType =
+        USB_RTYPE_DIR_IN | USB_RTYPE_CLASS | USB_RTYPE_INTERFACE;
+
+    //
+    // Request a Device Descriptor.
+    //
+    SetupPacket.bRequest = (ulRequest & 0xff);
+
+    //
+    // Request for a string descriptor.
+    //
+    SetupPacket.wValue = VOLUME_CONTROL | (ulChannel & 0xff);
+
+    //
+    // Set the language ID.
+    //
+    SetupPacket.wIndex = (pAudioDevice->ucVolumeIDOut << 8) |
+                         (ulInterface & 0xff);
+
+    //
+    // Only request the space available.
+    //
+    SetupPacket.wLength = 2;
+
+    //
+    // Put the setup packet in the buffer.
+    //
+    USBHCDControlTransfer(0, &SetupPacket, pAudioDevice->pDevice->ulAddress,
+                          (unsigned char *)&ulValue, 4,
+                          pAudioDevice->pDevice->DeviceDescriptor.bMaxPacketSize0);
+
+    return(ulValue);
+}
+
+//*****************************************************************************
+//
+//! This function is used to get the current volume setting for a given
+//! audio device.
+//!
+//! \param ulInstance is an instance of the USB audio device.
+//! \param ulInterface is the interface number to use to query the current
+//! volume setting.
+//! \param ulChannel is the 0 based channel number to query.
+//!
+//! The function is used to retrieve the current volume setting for an audio
+//! device on the channel specified by \e ulChannel.  The \e ulInterface is
+//! ignored for now and should be set to 0 to access the default audio control
+//! interface.  The \e ulChannel value starts with 0 which is the master audio
+//! volume control interface.  The remaining \e ulChannel values provide
+//! access to various other audio channels, with 1 and 2 being left and right
+//! audio channels.
+//!
+//! \note On devices that do not support volume control interfaces, this
+//! call returns 0, indicating a 0db setting.
+//!
+//! \return Returns the current volume setting for the requested interface.
+//
+//*****************************************************************************
+unsigned long
+USBHostAudioVolumeGet(unsigned long ulInstance, unsigned long ulInterface,
+                      unsigned long ulChannel)
+{
+    return(VolumeSettingGet(ulInstance, ulInterface, ulChannel,
+                            USB_AC_GET_CUR));
+}
+
+//*****************************************************************************
+//
+//! This function is used to get the maximum volume setting for a given
+//! audio device.
+//!
+//! \param ulInstance is an instance of the USB audio device.
+//! \param ulInterface is the interface number to use to query the maximum
+//! volume control value.
+//! \param ulChannel is the 0 based channel number to query.
+//!
+//! The function is used to retrieve the maximum volume setting for an audio
+//! device on the channel specified by \e ulChannel.  The \e ulInterface is
+//! ignored for now and should be set to 0 to access the default audio control
+//! interface.  The \e ulChannel value starts with 0 which is the master audio
+//! volume control interface.  The remaining \e ulChannel values provide
+//! access to various other audio channels, with 1 and 2 being left and right
+//! audio channels.
+//!
+//! \note On devices that do not support volume control interfaces, this
+//! call returns 0, indicating a 0db setting.
+//!
+//! \return Returns the maximum volume setting for the requested interface.
+//
+//*****************************************************************************
+unsigned long
+USBHostAudioVolumeMaxGet(unsigned long ulInstance, unsigned long ulInterface,
+                         unsigned long ulChannel)
+{
+    return(VolumeSettingGet(ulInstance, ulInterface, ulChannel,
+                            USB_AC_GET_MAX));
+}
+
+//*****************************************************************************
+//
+//! This function is used to get the minimum volume setting for a given
+//! audio device.
+//!
+//! \param ulInstance is an instance of the USB audio device.
+//! \param ulInterface is the interface number to use to query the minimum
+//! volume control value.
+//! \param ulChannel is the 0 based channel number to query.
+//!
+//! The function is used to retrieve the minimum volume setting for an audio
+//! device on the channel specified by \e ulChannel.  The \e ulInterface is
+//! ignored for now and should be set to 0 to access the default audio control
+//! interface.  The \e ulChannel value starts with 0 which is the master audio
+//! volume control interface.  The remaining \e ulChannel values provide
+//! access to various other audio channels, with 1 and 2 being left and right
+//! audio channels.
+//!
+//! \note On devices that do not support volume control interfaces, this
+//! call returns 0, indicating a 0db setting.
+//!
+//! \return Returns the minimum volume setting for the requested interface.
+//
+//*****************************************************************************
+unsigned long
+USBHostAudioVolumeMinGet(unsigned long ulInstance, unsigned long ulInterface,
+                         unsigned long ulChannel)
+{
+    return(VolumeSettingGet(ulInstance, ulInterface, ulChannel,
+                            USB_AC_GET_MIN));
+}
+
+//*****************************************************************************
+//
+//! This function is used to get the volume control resolution for a given
+//! audio device.
+//!
+//! \param ulInstance is an instance of the USB audio device.
+//! \param ulInterface is the interface number to use to query the resolution
+//! for the volume control.
+//! \param ulChannel is the 0 based channel number to query.
+//!
+//! The function is used to retrieve the volume control resolution for an audio
+//! device on the channel specified by \e ulChannel.  The \e ulInterface is
+//! ignored for now and should be set to 0 to access the default audio control
+//! interface.  The \e ulChannel value starts with 0 which is the master audio
+//! volume control interface.  The remaining \e ulChannel values provide
+//! access to various other audio channels, with 1 and 2 being left and right
+//! audio channels.
+//!
+//! \note On devices that do not support volume control interfaces, this
+//! call returns 0, indicating a 0db setting.
+//!
+//! \return Returns the volume control resolution for the requested interface.
+//
+//*****************************************************************************
+unsigned long
+USBHostAudioVolumeResGet(unsigned long ulInstance, unsigned long ulInterface,
+                         unsigned long ulChannel)
+{
+    return(VolumeSettingGet(ulInstance, ulInterface, ulChannel,
+                            USB_AC_GET_RES));
+}
+
+//*****************************************************************************
+//
+//! This function is used to set the current volume setting for a given
+//! audio device.
+//!
+//! \param ulInstance is an instance of the USB audio device.
+//! \param ulInterface is the interface number to use to set the current
+//! volume setting.
+//! \param ulChannel is the 0 based channel number to query.
+//! \param ulValue is the value to write to the USB audio device.
+//!
+//! The function is used to set the current volume setting for an audio
+//! device on the channel specified by \e ulChannel.  The \e ulInterface is
+//! ignored for now and should be set to 0 to access the default audio control
+//! interface.  The \e ulChannel value starts with 0 which is the master audio
+//! volume control interface.  The remaining \e ulChannel values provide
+//! access to various other audio channels, with 1 and 2 being left and right
+//! audio channels.
+//!
+//! \note On devices that do not support volume control interfaces, this
+//! call returns 0, indicating a 0db setting.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostAudioVolumeSet(unsigned long ulInstance, unsigned ulInterface,
+                      unsigned long ulChannel, unsigned long ulValue)
+{
+    tUSBHostAudioInstance *pAudioDevice;
+    tUSBRequest SetupPacket;
+
+    //
+    // Create an audio instance pointer.
+    //
+    pAudioDevice = (tUSBHostAudioInstance *)ulInstance;
+
+    //
+    // This is a Class specific Interface OUT request.
+    //
+    SetupPacket.bmRequestType =
+        USB_RTYPE_DIR_OUT | USB_RTYPE_CLASS | USB_RTYPE_INTERFACE;
+
+    //
+    // Request is to set the current value.
+    //
+    SetupPacket.bRequest = USB_AC_SET_CUR;
+
+    //
+    // Request the volume control.
+    //
+    SetupPacket.wValue = VOLUME_CONTROL | (ulChannel & 0xff);
+
+    //
+    // Set Volume control ID and interface to 0.
+    //
+    SetupPacket.wIndex = pAudioDevice->ucVolumeIDOut << 8;
+
+    //
+    // Only request the space available.
+    //
+    SetupPacket.wLength = 2;
+
+    //
+    // Put the setup packet in the buffer.
+    //
+    USBHCDControlTransfer(0, &SetupPacket, pAudioDevice->pDevice->ulAddress,
+                       (unsigned char *)&ulValue, 2,
+                       pAudioDevice->pDevice->DeviceDescriptor.bMaxPacketSize0);
+}
+
+//*****************************************************************************
+//
+//! This function is called to determine if an audio format is supported by the
+//! connected USB Audio device.
+//!
+//! \param ulInstance is the device instance for this call.
+//! \param ulSampleRate is the sample rate of the audio stream.
+//! \param ulBits is the number of bits per sample in the audio stream.
+//! \param ulChannels is the number of channels in the audio stream.
+//! \param ulFlags is a set of flags to determine what type of interface to
+//!        retrieve.
+//!
+//! This function is called when an application needs to determine which audio
+//! formats are supported by a USB audio device that has been connected.  The
+//! \e ulInstance value that is used with this call is the value that was
+//! returned from the USBHostAudioOpen() function.  This call checks the
+//! USB audio device to determine if it can support the values provided in the
+//! \e ulSampleRate, \e ulBits, and \e ulChannels values.  The \e ulFlags
+//! currently only supports either the \b USBH_AUDIO_FORMAT_IN or
+//! \b USBH_AUDIO_FORMAT_OUT values that indicates if a request is for an
+//! audio input and an audio output.  If the format is supported this
+//! function returns zero, and this function returns a non-zero value if the
+//! format is not supported.  This function does not set the current output or
+//! input format.
+//!
+//! \return A value of zero indicates the supplied format is supported and
+//! a non-zero value indicates that the format is not supported.
+//
+//*****************************************************************************
+unsigned long
+USBHostAudioFormatGet(unsigned long ulInstance, unsigned long ulSampleRate,
+                      unsigned long ulBits, unsigned long ulChannels,
+                      unsigned long ulFlags)
+{
+    tUSBHostAudioInstance *pAudioDevice;
+
+    //
+    // Get a pointer to the device instance data from the handle.
+    //
+    pAudioDevice = (tUSBHostAudioInstance *)ulInstance;
+
+    //
+    // Look for the requested format.
+    //
+    if(AudioGetInterface(pAudioDevice, USB_ADF_PCM, ulSampleRate, ulBits>>3,
+                         ulChannels, ulFlags) != INVALID_INTERFACE)
+    {
+        return(0);
+    }
+    return(1);
+}
+
+//*****************************************************************************
+//
+//! This function is called to set the current sample rate on an audio
+//! interface.
+//!
+//! \param ulInstance specifies the device instance for this call.
+//! \param ulSampleRate is the sample rate in Hz.
+//! \param ulBits is the number of bits per sample.
+//! \param ulChannels is then number of audio channels.
+//! \param ulFlags is a set of flags that determine the access type.
+//!
+//! This function is called when to set the current audio output or input format
+//! for a USB audio device.  The \e ulInstance value that is used with this
+//! call is the value that was returned from the USBHostAudioOpen() function.
+//! The application can use this call to insure that the audio format is
+//! supported and set the format at the same time.  If the application is
+//! just checking for supported rates, then it should call the
+//! USBHostAudioFormatGet().
+//!
+//! \note This function must be called before attempting to send or receive
+//! audio with the USBHostAudioPlay() or USBHostAudioRecord() functions.
+//!
+//! \return A non-zero value indicates the supplied format is not supported and
+//! a zero value indicates that the format was supported and has been
+//! configured.
+//
+//*****************************************************************************
+unsigned long
+USBHostAudioFormatSet(unsigned long ulInstance, unsigned long ulSampleRate,
+                      unsigned long ulBits, unsigned long ulChannels,
+                      unsigned long ulFlags)
+{
+    tUSBHostAudioInstance *pAudioDevice;
+    unsigned long ulInterface;
+
+    //
+    // Get a pointer to the device instance data from the handle.
+    //
+    pAudioDevice = (tUSBHostAudioInstance *)ulInstance;
+
+    //
+    // Look for the requested format.
+    //
+    ulInterface = AudioGetInterface(pAudioDevice, USB_ADF_PCM, ulSampleRate,
+                                    ulBits>>3, ulChannels, ulFlags);
+
+    if(ulInterface == INVALID_INTERFACE)
+    {
+        return(1);
+    }
+
+    //
+    // Determine if this is an input or output request.
+    //
+    if(ulFlags & USBH_AUDIO_FORMAT_IN)
+    {
+        //
+        // Get the active interface number and alternate setting for this
+        // format.
+        //
+        pAudioDevice->ucInInterface =
+            (unsigned char)(ulInterface & INTERFACE_NUM_M);
+        pAudioDevice->ucInAltSetting =
+            (unsigned char)((ulInterface & INTERFACE_ALTSETTING_M) >>
+                            INTERFACE_ALTSETTING_S);
+    }
+    else
+    {
+        //
+        // Get the active interface number and alternate setting for this
+        // format.
+        //
+        pAudioDevice->ucOutInterface =
+            (unsigned char)(ulInterface & INTERFACE_NUM_M);
+        pAudioDevice->ucOutAltSetting =
+            (unsigned char)((ulInterface & INTERFACE_ALTSETTING_M) >>
+                            INTERFACE_ALTSETTING_S);
+    }
+    return(0);
+}
+
+//*****************************************************************************
+//
+//! This function is called to send an audio buffer to the USB audio device.
+//!
+//! \param ulInstance specifies the device instance for this call.
+//! \param pvBuffer is the audio buffer to send.
+//! \param ulSize is the size of the buffer in bytes.
+//! \param pfnCallback is a pointer to a callback function that is called
+//! when the buffer can be used again.
+//!
+//! This function is called when an application needs to schedule a new buffer
+//! for output to the USB audio device.  Since this call schedules the transfer
+//! and returns immediately, the application should provide a \e pfnCallback
+//! function to be notified when the buffer can be used again by the
+//! application.  The \e pfnCallback function provided is called with the
+//! \e pvBuffer parameter set to the \e pvBuffer provided by this call, the
+//! \e ulParam can be ignored and the \e ulEvent parameter is
+//! \b USB_EVENT_TX_COMPLETE.
+//!
+//! \return This function returns the number of bytes that were scheduled
+//! to be sent.  If this function returns zero then there was no USB audio
+//! device present or the request could not be satisfied at this time.
+//
+//*****************************************************************************
+long
+USBHostAudioPlay(unsigned long ulInstance, void *pvBuffer,
+                 unsigned long ulSize, tUSBHostAudioCallback pfnCallback)
+{
+    tUSBHostAudioInstance *pAudioDevice;
+    unsigned long ulBytes;
+
+    //
+    // Make sure that there is a device present.
+    //
+    if(g_AudioDevice.pDevice == 0)
+    {
+        return(0);
+    }
+
+    //
+    // Get a pointer to the device instance data from the handle.
+    //
+    pAudioDevice = (tUSBHostAudioInstance *)ulInstance;
+
+    //
+    // If the audio output interface is not active then select the current
+    // active audio interface.
+    //
+    if(HWREGBITW(&pAudioDevice->ulFlags, AUDIO_FLAG_OUT_ACTIVE) == 0)
+    {
+        //
+        // Indicate the active audio interface has been selected.
+        //
+        HWREGBITW(&pAudioDevice->ulFlags, AUDIO_FLAG_OUT_ACTIVE) = 1;
+
+        //
+        // Configure the USB audio device to use the selected audio interface.
+        //
+        USBHCDSetInterface(0, (unsigned long)pAudioDevice->pDevice,
+                           pAudioDevice->ucOutInterface,
+                           pAudioDevice->ucOutAltSetting);
+    }
+
+    //
+    // Save the callback function and the buffer pointer.
+    //
+    pAudioDevice->pfnOutCallback = pfnCallback;
+    pAudioDevice->pvOutBuffer = (void *)pvBuffer;
+
+    //
+    // Schedule the data to be written out to the FIFO.
+    //
+    ulBytes = USBHCDPipeSchedule(pAudioDevice->ulIsochOutPipe, pvBuffer,
+                                 ulSize);
+
+    //
+    // Return the number of bytes scheduled to be sent.
+    //
+    return(ulBytes);
+}
+
+//*****************************************************************************
+//
+//! This function is called to provide an audio buffer to the USB audio device
+//! for audio input.
+//!
+//! \param ulInstance specifies the device instance for this call.
+//! \param pvBuffer is the audio buffer to send.
+//! \param ulSize is the size of the buffer in bytes.
+//! \param pfnCallback is a pointer to a callback function that is called
+//! when the buffer has been filled.
+//!
+//! This function is called when an application needs to schedule a new buffer
+//! for input from the USB audio device.  Since this call schedules the
+//! transfer and returns immediately, the application should provide a
+//! \e pfnCallback function to be notified when the buffer has been filled with
+//! audio data.  When the \e pfnCallback function is called, the \e pvBuffer
+//! parameter is set to \e pvBuffer provided in this call, the \e ulParam is
+//! the number of valid bytes in the pvBuffer and the \e ulEvent is set to
+//! \b USB_EVENT_RX_AVAILABLE.
+//!
+//! \return This function returns the number of bytes that were scheduled
+//! to be sent.  If this function returns zero then there was no USB audio
+//! device present or the device does not support audio input.
+//
+//*****************************************************************************
+long
+USBHostAudioRecord(unsigned long ulInstance, void *pvBuffer,
+                   unsigned long ulSize, tUSBHostAudioCallback pfnCallback)
+{
+    tUSBHostAudioInstance *pAudioDevice;
+    unsigned long ulBytes;
+
+    //
+    // Make sure that there is a device present.
+    //
+    if(g_AudioDevice.pDevice == 0)
+    {
+        return(0);
+    }
+
+    //
+    // Get a pointer to the device instance data from the handle.
+    //
+    pAudioDevice = (tUSBHostAudioInstance *)ulInstance;
+
+    //
+    // If the audio input interface is not active then select the current
+    // active audio interface.
+    //
+    if(HWREGBITW(&pAudioDevice->ulFlags, AUDIO_FLAG_IN_ACTIVE) == 0)
+    {
+        //
+        // Indicate the active audio interface has been selected.
+        //
+        HWREGBITW(&pAudioDevice->ulFlags, AUDIO_FLAG_IN_ACTIVE) = 1;
+
+        //
+        // Configure the USB audio device to use the selected audio interface.
+        //
+        USBHCDSetInterface(0, (unsigned long)pAudioDevice->pDevice,
+                           pAudioDevice->ucInInterface,
+                           pAudioDevice->ucInAltSetting);
+    }
+
+    //
+    // Save the callback function and the buffer pointer.
+    //
+    pAudioDevice->pfnInCallback = pfnCallback;
+    pAudioDevice->pvInBuffer = (void *)pvBuffer;
+
+    //
+    // Schedule the data to be written out to the FIFO.
+    //
+    ulBytes = USBHCDPipeSchedule(pAudioDevice->ulIsochInPipe, pvBuffer, ulSize);
+
+    //
+    // Return the number of bytes scheduled to be sent.
+    //
+    return(ulBytes);
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
diff --git a/src/platform/lm3s/usblib/host/usbhaudio.h b/src/platform/lm3s/usblib/host/usbhaudio.h
new file mode 100755
index 00000000..c9e35ed4
--- /dev/null
+++ b/src/platform/lm3s/usblib/host/usbhaudio.h
@@ -0,0 +1,162 @@
+//*****************************************************************************
+//
+// usbhaudio.h - USB host audio class driver.
+//
+// Copyright (c) 2010-2011 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 7611 of the Stellaris USB Library.
+//
+//*****************************************************************************
+
+#ifndef __USBHAUDIO_H__
+#define __USBHAUDIO_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+//! \addtogroup usblib_host_class
+//! @{
+//
+//*****************************************************************************
+
+typedef void (* tUSBHostAudioCallback)(void *pvBuffer,
+                                       unsigned long ulParam,
+                                       unsigned long ulEvent);
+
+//*****************************************************************************
+//
+//! This is the size in bytes of the private data for the host audio class.
+//
+//*****************************************************************************
+#define USB_HOST_AUDIO_INSTANCE_SIZE sizeof(tHostAudioInstance);
+
+//*****************************************************************************
+//
+// USB host audio specific events
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! This USB host audio event indicates that the device is connected and
+//! ready to send or receive buffers.  The \e pvBuffer and \e ulParam
+//! values are not used in this event.
+//
+//*****************************************************************************
+#define USBH_AUDIO_EVENT_OPEN   (USBH_AUDIO_EVENT_BASE + 0)
+
+//*****************************************************************************
+//
+//! This USB host audio event indicates that the previously connected device
+//! has been disconnected. The \e pvBuffer and \e ulParam values are not used
+//! in this event.
+//
+//*****************************************************************************
+#define USBH_AUDIO_EVENT_CLOSE  (USBH_AUDIO_EVENT_BASE + 1)
+
+//*****************************************************************************
+//
+// This definition is used with the USBHostAudioFormatGet() and
+// USBHostAudioFormatSet() API's to determine if the audio input is being
+// accesses(USBH_AUDIO_FORMAT_IN set) or audio output(USBH_AUDIO_FORMAT clear).
+//
+//*****************************************************************************
+#define USBH_AUDIO_FORMAT_IN    0x00000001
+#define USBH_AUDIO_FORMAT_OUT   0x00000000
+
+typedef struct
+{
+    unsigned char ucChannels;
+    unsigned char ucBits;
+    unsigned long ulSampleRate;
+} tUSBAudioFormat;
+
+//*****************************************************************************
+//
+// API Function Prototypes
+//
+//*****************************************************************************
+extern unsigned long USBHostAudioOpen(unsigned long ulIndex,
+                                      tUSBHostAudioCallback pfnCallback);
+extern void USBHostAudioClose(unsigned long ulInstance);
+extern long USBHostAudioPlay(unsigned long ulInstance, void *pvBuffer,
+                             unsigned long ulSize,
+                             tUSBHostAudioCallback pfnCallback);
+
+extern unsigned long USBHostAudioFormatGet(unsigned long ulInstance,
+                                           unsigned long ulSampleRate,
+                                           unsigned long ulBits,
+                                           unsigned long ulChannels,
+                                           unsigned long ulFlags);
+extern unsigned long USBHostAudioFormatSet(unsigned long ulInstance,
+                                           unsigned long ulSampleRate,
+                                           unsigned long ulBits,
+                                           unsigned long ulChannels,
+                                           unsigned long ulFlags);
+
+extern long USBHostAudioRecord(unsigned long ulInstance, void *pvBuffer,
+                               unsigned long ulSize,
+                               tUSBHostAudioCallback);
+
+extern unsigned long USBHostAudioVolumeGet(unsigned long ulInstance,
+                                           unsigned long ulInterface,
+                                           unsigned long ulChannel);
+
+extern void USBHostAudioVolumeSet(unsigned long ulInstance,
+                                  unsigned ulInterface,
+                                  unsigned long ulChannel,
+                                  unsigned long ulValue);
+
+extern unsigned long USBHostAudioVolumeMaxGet(unsigned long ulInstance,
+                                              unsigned long ulInterface,
+                                              unsigned long ulChannel);
+
+extern unsigned long USBHostAudioVolumeMinGet(unsigned long ulInstance,
+                                              unsigned long ulInterface,
+                                              unsigned long ulChannel);
+
+extern unsigned long USBHostAudioVolumeResGet(unsigned long ulInstance,
+                                              unsigned long ulInterface,
+                                              unsigned long ulChannel);
+
+//*****************************************************************************
+//
+//! @}
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
diff --git a/src/platform/lm3s/usblib/host/usbhhid.c b/src/platform/lm3s/usblib/host/usbhhid.c
new file mode 100755
index 00000000..68291dd3
--- /dev/null
+++ b/src/platform/lm3s/usblib/host/usbhhid.c
@@ -0,0 +1,686 @@
+//*****************************************************************************
+//
+// usbhhid.c - This file contains the host HID driver.
+//
+// Copyright (c) 2008-2011 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 7611 of the Stellaris USB Library.
+//
+//*****************************************************************************
+
+#include "inc/hw_types.h"
+#include "driverlib/usb.h"
+#include "usblib/usblib.h"
+#include "usblib/usbhid.h"
+#include "usblib/host/usbhost.h"
+#include "usblib/host/usbhhid.h"
+
+static void * HIDDriverOpen(tUSBHostDevice *pDevice);
+static void HIDDriverClose(void *pvInstance);
+
+//*****************************************************************************
+//
+//! \addtogroup usblib_host_class
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// This is the structure that holds all of the data for a given instance of
+// a HID device.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    // Save the device instance.
+    //
+    tUSBHostDevice *pDevice;
+
+    //
+    // Used to save the callback.
+    //
+    tUSBCallback pfnCallback;
+
+    //
+    // Callback data provided by caller.
+    //
+    unsigned long ulCBData;
+
+    //
+    // Used to remember what type of device was registered.
+    //
+    tHIDSubClassProtocol eDeviceType;
+
+    //
+    // Interrupt IN pipe.
+    //
+    unsigned long ulIntInPipe;
+}
+tHIDInstance;
+
+//*****************************************************************************
+//
+// The instance data storage for attached hid devices.
+//
+//*****************************************************************************
+static tHIDInstance g_HIDDevice =
+{
+    0,
+    0,
+    0,
+    USBH_HID_DEV_NONE,
+    0
+};
+
+//*****************************************************************************
+//
+//! This constant global structure defines the HID Class Driver that is
+//! provided with the USB library.
+//
+//*****************************************************************************
+const tUSBHostClassDriver g_USBHIDClassDriver =
+{
+    USB_CLASS_HID,
+    HIDDriverOpen,
+    HIDDriverClose,
+    0
+};
+
+//*****************************************************************************
+//
+//! This function is used to open an instance of a HID device.
+//!
+//! \param eDeviceType is the type of device that should be loaded for this
+//! instance of the HID device.
+//! \param pfnCallback is the function that will be called whenever changes
+//! are detected for this device.
+//! \param ulCBData is the data that will be returned in when the pfnCallback
+//! function is called.
+//!
+//! This function creates an instance of an specific type of HID device.  The
+//! \e eDeviceType parameter is one subclass/protocol values of the types
+//! specified in enumerated types tHIDSubClassProtocol.  Only devices that
+//! enumerate with this type will be called back via the \e pfnCallback
+//! function.  The \e pfnCallback parameter is the callback function for any
+//! events that occur for this device type.  The \e pfnCallback function must
+//! point to a valid function of type \e tUSBCallback for this call to complete
+//! successfully.  To release this device instance the caller of USBHHIDOpen()
+//! should call USBHHIDClose() and pass in the value returned from the
+//! USBHHIDOpen() call.
+//!
+//! \return This function returns and instance value that should be used with
+//! any other APIs that require an instance value.  If a value of 0 is returned
+//! then the device instance could not be created.
+//
+//*****************************************************************************
+unsigned long
+USBHHIDOpen(tHIDSubClassProtocol eDeviceType, tUSBCallback pfnCallback,
+            unsigned long ulCBData)
+{
+    //
+    // Only one callback is supported.
+    //
+    if(g_HIDDevice.pfnCallback)
+    {
+        return(0);
+    }
+
+    //
+    // Save the instance data for this device.
+    //
+    g_HIDDevice.pfnCallback = pfnCallback;
+    g_HIDDevice.eDeviceType = eDeviceType;
+    g_HIDDevice.ulCBData = ulCBData;
+
+    //
+    // Return the device instance pointer.
+    //
+    return((unsigned long)&g_HIDDevice);
+}
+
+//*****************************************************************************
+//
+//! This function is used to release an instance of a HID device.
+//!
+//! \param ulHIDInstance is the instance value for a HID device to release.
+//!
+//! This function releases an instance of a HID device that was created by a
+//! call to USBHHIDOpen().  This call is required to allow other HID devices
+//! to be enumerated after another HID device has been disconnected.  The
+//! \e ulHIDInstance parameter should hold the value that was returned from the
+//! previous call to USBHHIDOpen().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHHIDClose(unsigned long ulHIDInstance)
+{
+    //
+    // Disable any more notification from the HID layer.
+    //
+    g_HIDDevice.pfnCallback = 0;
+    g_HIDDevice.eDeviceType = USBH_HID_DEV_NONE;
+}
+
+//*****************************************************************************
+//
+// This function handles callbacks for the interrupt IN endpoint.
+//
+//*****************************************************************************
+static void
+HIDIntINCallback(unsigned long ulPipe, unsigned long ulEvent)
+{
+    switch (ulEvent)
+    {
+        //
+        // Handles a request to schedule a new request on the interrupt IN
+        // pipe.
+        //
+        case USB_EVENT_SCHEDULER:
+        {
+            USBHCDPipeSchedule(ulPipe, 0, 1);
+            break;
+        }
+        //
+        // Called when new data is available on the interrupt IN pipe.
+        //
+        case USB_EVENT_RX_AVAILABLE:
+        {
+            //
+            // Send the report data to the USB host HID device class driver.
+            //
+            g_HIDDevice.pfnCallback((void *)g_HIDDevice.ulCBData,
+                                    USB_EVENT_RX_AVAILABLE,
+                                    ulPipe,
+                                    0);
+            break;
+        }
+    }
+}
+
+//*****************************************************************************
+//
+//! This function is used to open an instance of the HID driver.
+//!
+//! \param pDevice is a pointer to the device information structure.
+//!
+//! This function will attempt to open an instance of the HID driver based on
+//! the information contained in the pDevice structure.  This call can fail if
+//! there are not sufficient resources to open the device.  The function will
+//! return a value that should be passed back into USBHIDClose() when the
+//! driver is no longer needed.
+//!
+//! \return The function will return a pointer to a HID driver instance.
+//
+//*****************************************************************************
+static void *
+HIDDriverOpen(tUSBHostDevice *pDevice)
+{
+    long lIdx;
+    tEndpointDescriptor *pEndpointDescriptor;
+    tInterfaceDescriptor *pInterface;
+
+    //
+    // Don't allow the device to be opened without closing first.
+    //
+    if(g_HIDDevice.pDevice)
+    {
+        return(0);
+    }
+
+    //
+    // Get the interface descriptor.
+    //
+    pInterface = USBDescGetInterface(pDevice->pConfigDescriptor, 0, 0);
+
+    if((pInterface->bInterfaceSubClass != USB_HID_SCLASS_BOOT) ||
+      (pInterface->bInterfaceProtocol != g_HIDDevice.eDeviceType))
+    {
+        return(0);
+    }
+
+    //
+    // Save the device pointer.
+    //
+    g_HIDDevice.pDevice = pDevice;
+
+    for(lIdx = 0; lIdx < 3; lIdx++)
+    {
+        //
+        // Get the first endpoint descriptor.
+        //
+        pEndpointDescriptor = USBDescGetInterfaceEndpoint(pInterface, lIdx,
+                                                          256);
+
+        //
+        // If no more endpoints then break out.
+        //
+        if(pEndpointDescriptor == 0)
+        {
+            break;
+        }
+
+        //
+        // Interrupt
+        //
+        if((pEndpointDescriptor->bmAttributes & USB_EP_ATTR_TYPE_M) ==
+           USB_EP_ATTR_INT)
+        {
+            //
+            // Interrupt IN.
+            //
+            if(pEndpointDescriptor->bEndpointAddress & USB_EP_DESC_IN)
+            {
+                g_HIDDevice.ulIntInPipe = USBHCDPipeAlloc(0,
+                                                          USBHCD_PIPE_INTR_IN,
+                                                          pDevice->ulAddress,
+                                                          HIDIntINCallback);
+                USBHCDPipeConfig(g_HIDDevice.ulIntInPipe,
+                                 pEndpointDescriptor->wMaxPacketSize,
+                                 pEndpointDescriptor->bInterval,
+                                 (pEndpointDescriptor->bEndpointAddress &
+                                  USB_EP_DESC_NUM_M));
+            }
+        }
+    }
+
+    //
+    // If there is a callback function call it to inform the application that
+    // the device has been enumerated.
+    //
+    if(g_HIDDevice.pfnCallback != 0)
+    {
+        g_HIDDevice.pfnCallback((void *)g_HIDDevice.ulCBData,
+                                USB_EVENT_CONNECTED,
+                                (unsigned long)&g_HIDDevice, 0);
+    }
+
+    //
+    // Save the device pointer.
+    //
+    g_HIDDevice.pDevice = pDevice;
+
+    return(&g_HIDDevice);
+}
+
+//*****************************************************************************
+//
+//! This function is used to release an instance of the HID driver.
+//!
+//! \param pvInstance is an instance pointer that needs to be released.
+//!
+//! This function will free up any resources in use by the HID driver instance
+//! that is passed in.  The \e pvInstance pointer should be a valid value that
+//! was returned from a call to USBHIDOpen().
+//!
+//! \return None.
+//
+//*****************************************************************************
+static void
+HIDDriverClose(void *pvInstance)
+{
+    //
+    // No device so just exit.
+    //
+    if(g_HIDDevice.pDevice == 0)
+    {
+        return;
+    }
+
+    //
+    // Reset the device pointer.
+    //
+    g_HIDDevice.pDevice = 0;
+
+    //
+    // Free the Interrupt IN pipe.
+    //
+    if(g_HIDDevice.ulIntInPipe != 0)
+    {
+        USBHCDPipeFree(g_HIDDevice.ulIntInPipe);
+    }
+
+    //
+    // If the callback exists, call it with an Open event.
+    //
+    if(g_HIDDevice.pfnCallback != 0)
+    {
+        g_HIDDevice.pfnCallback((void *)g_HIDDevice.ulCBData,
+                                USB_EVENT_DISCONNECTED,
+                                (unsigned long)&g_HIDDevice, 0);
+    }
+}
+
+//*****************************************************************************
+//
+//! This function is used to set the idle timeout for a HID device.
+//!
+//! \param ulInstance is the value that was returned from the call to
+//! USBHHIDOpen().
+//! \param ucDuration is the duration of the timeout in milliseconds.
+//! \param ucReportID is the report identifier to set the timeout on.
+//!
+//! This function will send the Set Idle command to a HID device to set the
+//! idle timeout for a given report.  The length of the timeout is specified
+//! by the \e ucDuration parameter and the report the timeout for is in the
+//! \e ucReportID value.
+//!
+//! \return Always returns 0.
+//
+//*****************************************************************************
+unsigned long
+USBHHIDSetIdle(unsigned long ulInstance, unsigned char ucDuration,
+               unsigned char ucReportID)
+{
+    tUSBRequest SetupPacket;
+    tHIDInstance *pHIDInstance;
+
+    pHIDInstance = (tHIDInstance *)ulInstance;
+
+    //
+    // This is a Class specific interface OUT request.
+    //
+    SetupPacket.bmRequestType = USB_RTYPE_DIR_OUT | USB_RTYPE_CLASS
+                    | USB_RTYPE_INTERFACE;
+
+    //
+    // Request a Device Descriptor.
+    //
+    SetupPacket.bRequest = USBREQ_SET_IDLE;
+    SetupPacket.wValue = (ucDuration << 8) | ucReportID;
+
+    //
+    // Set this on interface 1.
+    //
+    SetupPacket.wIndex = 0;
+
+    //
+    // This is always 0 for this request.
+    //
+    SetupPacket.wLength = 0;
+
+    //
+    // Put the setup packet in the buffer.
+    //
+    USBHCDControlTransfer(0,
+                          &SetupPacket,
+                          pHIDInstance->pDevice->ulAddress,
+                          0,
+                          0,
+                          MAX_PACKET_SIZE_EP0);
+
+    return(0);
+}
+
+//*****************************************************************************
+//
+//! This function can be used to retrieve the report descriptor for a given
+//! device instance.
+//!
+//! \param ulInstance is the value that was returned from the call to
+//! USBHHIDOpen().
+//! \param pucBuffer is the memory buffer to use to store the report
+//! descriptor.
+//! \param ulSize is the size in bytes of the buffer pointed to by
+//! \e pucBuffer.
+//!
+//! This function is used to return a report descriptor from a HID device
+//! instance so that it can determine how to interpret reports that are
+//! returned from the device indicated by the \e ulInstance parameter.
+//! This call is blocking and will return the number of bytes read into the
+//! \e pucBuffer.
+//!
+//! \return Returns the number of bytes read into the \e pucBuffer.
+//
+//*****************************************************************************
+unsigned long
+USBHHIDGetReportDescriptor(unsigned long ulInstance, unsigned char *pucBuffer,
+                           unsigned long ulSize)
+{
+    tUSBRequest SetupPacket;
+    unsigned long ulBytes;
+    tHIDInstance *pHIDInstance;
+
+    pHIDInstance = (tHIDInstance *)ulInstance;
+
+    //
+    // This is a Standard Device IN request.
+    //
+    SetupPacket.bmRequestType = USB_RTYPE_DIR_IN | USB_RTYPE_STANDARD
+                    | USB_RTYPE_INTERFACE;
+
+    //
+    // Request a Report Descriptor.
+    //
+    SetupPacket.bRequest = USBREQ_GET_DESCRIPTOR;
+    SetupPacket.wValue = USB_HID_DTYPE_REPORT << 8;
+
+    //
+    // Index is always 0 for device requests.
+    //
+    SetupPacket.wIndex = 0;
+
+    //
+    // All devices must have at least an 8 byte max packet size so just ask
+    // for 8 bytes to start with.
+    //
+    SetupPacket.wLength = ulSize;
+
+    //
+    // Now get the full descriptor now that the actual maximum packet size
+    // is known.
+    //
+    ulBytes = USBHCDControlTransfer(
+                0,
+                &SetupPacket,
+                pHIDInstance->pDevice->ulAddress,
+                pucBuffer,
+                ulSize,
+                pHIDInstance->pDevice->DeviceDescriptor.bMaxPacketSize0);
+
+    return(ulBytes);
+}
+
+//*****************************************************************************
+//
+//! This function is used to set or clear the boot protocol state of a device.
+//!
+//! \param ulInstance is the value that was returned from the call to
+//! USBHHIDOpen().
+//! \param ulBootProtocol is either zero or non-zero to indicate which protocol
+//! to use for the device.
+//!
+//! A USB host device can use this function to set the protocol for a connected
+//! HID device.  This is commonly used to set keyboards and mice into their
+//! simplified boot protocol modes to fix the report structure to a know
+//! state.
+//!
+//! \return This function returns 0.
+//
+//*****************************************************************************
+unsigned long
+USBHHIDSetProtocol(unsigned long ulInstance, unsigned long ulBootProtocol)
+{
+    tUSBRequest SetupPacket;
+    tHIDInstance *pHIDInstance;
+
+    pHIDInstance = (tHIDInstance *)ulInstance;
+
+    //
+    // This is a Standard Device IN request.
+    //
+    SetupPacket.bmRequestType = USB_RTYPE_DIR_OUT | USB_RTYPE_CLASS
+                    | USB_RTYPE_INTERFACE;
+
+    //
+    // Request a Report Descriptor.
+    //
+    SetupPacket.bRequest = USBREQ_SET_PROTOCOL;
+
+    if(ulBootProtocol)
+    {
+        //
+        // Boot Protocol.
+        //
+        SetupPacket.wValue = 0;
+    }
+    else
+    {
+        //
+        // Report Protocol.
+        //
+        SetupPacket.wValue = 1;
+    }
+
+    //
+    // Index is always 0 for device requests.
+    //
+    SetupPacket.wIndex = 0;
+
+    //
+    // Always 0.
+    //
+    SetupPacket.wLength = 0;
+
+    //
+    // Now get the full descriptor now that the actual maximum packet size
+    // is known.
+    //
+    USBHCDControlTransfer(
+        0,
+        &SetupPacket,
+        pHIDInstance->pDevice->ulAddress,
+        0,
+        0,
+        pHIDInstance->pDevice->DeviceDescriptor.bMaxPacketSize0);
+
+    return(0);
+}
+
+//*****************************************************************************
+//
+//! This function is used to retrieve a report from a HID device.
+//!
+//! \param ulInstance is the value that was returned from the call to
+//! USBHHIDOpen().
+//! \param ulInterface is the interface to retrieve the report from.
+//! \param pucData is the memory buffer to use to store the report.
+//! \param ulSize is the size in bytes of the buffer pointed to by
+//! \e pucBuffer.
+//!
+//! This function is used to retrieve a report from a USB pipe.  It is usually
+//! called when the USB HID layer has detected a new data available in a USB
+//! pipe.  The USB HID host device code will receive a
+//! \b USB_EVENT_RX_AVAILABLE event when data is available, allowing the
+//! callback function to retrieve the data.
+//!
+//! \return Returns the number of bytes read from report.
+//
+//*****************************************************************************
+unsigned long
+USBHHIDGetReport(unsigned long ulInstance,
+                 unsigned long ulInterface,
+                 unsigned char *pucData,
+                 unsigned long ulSize)
+{
+    tHIDInstance *pHIDInstance;
+
+    //
+    // Cast the instance pointer to the correct type for ease of use.
+    //
+    pHIDInstance = (tHIDInstance *)ulInstance;
+
+    //
+    // Read the Data out.
+    //
+    ulSize = USBHCDPipeReadNonBlocking(pHIDInstance->ulIntInPipe, pucData,
+                                       ulSize);
+
+    //
+    // Return the number of bytes read from the interrupt in pipe.
+    //
+    return(ulSize);
+}
+
+//*****************************************************************************
+//
+//! This function is used to send a report to a HID device.
+//!
+//! \param ulInstance is the value that was returned from the call to
+//! USBHHIDOpen().
+//! \param ulInterface is the interface to send the report to.
+//! \param pucData is the memory buffer to use to store the report.
+//! \param ulSize is the size in bytes of the buffer pointed to by
+//! \e pucBuffer.
+//!
+//! This function is used to send a report to a USB HID device.  It can be
+//! only be called from outside the callback context as this function will not
+//! return from the call until the data has been sent successfully.
+//!
+//! \return Returns the number of bytes sent to the device.
+//
+//*****************************************************************************
+unsigned long
+USBHHIDSetReport(unsigned long ulInstance, unsigned long ulInterface,
+                 unsigned char *pucData, unsigned long ulSize)
+{
+    tUSBRequest SetupPacket;
+    tHIDInstance *pHIDInstance;
+
+    pHIDInstance = (tHIDInstance *)ulInstance;
+
+    //
+    // This is a Standard Device IN request.
+    //
+    SetupPacket.bmRequestType = USB_RTYPE_DIR_OUT | USB_RTYPE_CLASS
+                    | USB_RTYPE_INTERFACE;
+
+    //
+    // Request a Report Descriptor.
+    //
+    SetupPacket.bRequest = USBREQ_SET_REPORT;
+    SetupPacket.wValue = USB_HID_REPORT_OUTPUT << 8;
+
+    //
+    // Index is always 0 for device requests.
+    //
+    SetupPacket.wIndex = (unsigned short)ulInterface;
+
+    //
+    // Always 0.
+    //
+    SetupPacket.wLength = ulSize;
+
+    //
+    // Now get the full descriptor now that the actual maximum packet size
+    // is known.
+    //
+    USBHCDControlTransfer(0, &SetupPacket, pHIDInstance->pDevice->ulAddress,
+                          pucData, ulSize,
+                      pHIDInstance->pDevice->DeviceDescriptor.bMaxPacketSize0);
+
+    return(ulSize);
+}
+
+//*****************************************************************************
+//
+//! @}
+//
+//*****************************************************************************
diff --git a/src/platform/lm3s/usblib/host/usbhhid.h b/src/platform/lm3s/usblib/host/usbhhid.h
new file mode 100755
index 00000000..a285107a
--- /dev/null
+++ b/src/platform/lm3s/usblib/host/usbhhid.h
@@ -0,0 +1,164 @@
+//*****************************************************************************
+//
+// usbhhid.h - This hold the host driver for hid class.
+//
+// Copyright (c) 2008-2011 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 7611 of the Stellaris USB Library.
+//
+//*****************************************************************************
+
+#ifndef __USBHHID_H__
+#define __USBHHID_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+//! \addtogroup usblib_host_class
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// These defines are the the events that will be passed in the ulEvent
+// parameter of the callback from the driver.
+//
+//*****************************************************************************
+#define USBH_EVENT_HID_SETRPT   USBH_HID_EVENT_BASE + 0
+#define USBH_EVENT_HID_REPORT   USBH_HID_EVENT_BASE + 1
+
+//
+//! The HID keyboard detected a key being pressed.
+//
+#define USBH_EVENT_HID_KB_PRESS USBH_HID_EVENT_BASE + 16
+
+//
+//! The HID keyboard detected a key being released.
+//
+#define USBH_EVENT_HID_KB_REL   USBH_HID_EVENT_BASE + 17
+
+//
+//! The HID keyboard detected one of the keyboard modifiers being pressed.
+//
+#define USBH_EVENT_HID_KB_MOD   USBH_HID_EVENT_BASE + 18
+
+//
+//! A button was pressed on a HID mouse.
+//
+#define USBH_EVENT_HID_MS_PRESS USBH_HID_EVENT_BASE + 32
+
+//
+//! A button was released on a HID mouse.
+//
+#define USBH_EVENT_HID_MS_REL   USBH_HID_EVENT_BASE + 33
+
+//
+//! The HID mouse detected movement in the X direction.
+//
+#define USBH_EVENT_HID_MS_X     USBH_HID_EVENT_BASE + 34
+
+//
+//! The HID mouse detected movement in the Y direction.
+//
+#define USBH_EVENT_HID_MS_Y     USBH_HID_EVENT_BASE + 35
+
+//*****************************************************************************
+//
+//! The following values are used to register callbacks to the USB HOST HID
+//! device class layer.
+//
+//*****************************************************************************
+typedef enum
+{
+    //
+    //! No device should be used.  This value should not be used by
+    //! applications.
+    //
+    USBH_HID_DEV_NONE =         0,
+
+    //
+    //! This is a keyboard device.
+    //
+    USBH_HID_DEV_KEYBOARD,
+
+    //
+    //! This is a mouse device.
+    //
+    USBH_HID_DEV_MOUSE,
+
+    //
+    //! This is a vendor specific device.
+    //
+    USBH_HID_DEV_VENDOR
+}
+tHIDSubClassProtocol;
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Prototypes.
+//
+//*****************************************************************************
+extern unsigned long USBHHIDOpen(tHIDSubClassProtocol eDeviceType,
+                                 tUSBCallback pfnCallback,
+                                 unsigned long ulCBData);
+extern void USBHHIDClose(unsigned long ulInstance);
+extern unsigned long USBHHIDGetReportDescriptor(unsigned long ulInstance,
+                                                unsigned char *pucBuffer,
+                                                unsigned long ulSize);
+extern unsigned long USBHHIDSetIdle(unsigned long ulInstance,
+                                    unsigned char ucDuration,
+                                    unsigned char ucReportID);
+extern unsigned long USBHHIDSetProtocol(unsigned long ulInstance,
+                                        unsigned long ulBootProtocol);
+extern unsigned long USBHHIDSetReport(unsigned long ulInstance,
+                                      unsigned long ulInterface,
+                                      unsigned char *pucData,
+                                      unsigned long ulSize);
+extern unsigned long USBHHIDGetReport(unsigned long ulInstance,
+                                      unsigned long ulInterface,
+                                      unsigned char *pucData,
+                                      unsigned long ulSize);
+extern const tUSBHostClassDriver g_USBHIDClassDriver;
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __USBHHID_H__
diff --git a/src/platform/lm3s/usblib/host/usbhhidkeyboard.c b/src/platform/lm3s/usblib/host/usbhhidkeyboard.c
new file mode 100755
index 00000000..4b8c653f
--- /dev/null
+++ b/src/platform/lm3s/usblib/host/usbhhidkeyboard.c
@@ -0,0 +1,719 @@
+//*****************************************************************************
+//
+// usbhhidkeyboard.c - This file holds the application interfaces for USB
+//                     keyboard devices.
+//
+// Copyright (c) 2008-2011 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 7611 of the Stellaris USB Library.
+//
+//*****************************************************************************
+
+#include "inc/hw_types.h"
+#include "usblib/usblib.h"
+#include "usblib/host/usbhost.h"
+#include "usblib/usbhid.h"
+#include "usblib/host/usbhhid.h"
+#include "usblib/host/usbhhidkeyboard.h"
+
+//*****************************************************************************
+//
+//! \addtogroup usblib_host_device
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Prototypes for local functions.
+//
+//*****************************************************************************
+static unsigned long USBHKeyboardCallback(void *pvCBData,
+                                          unsigned long ulEvent,
+                                          unsigned long ulMsgParam,
+                                          void *pvMsgData);
+
+//*****************************************************************************
+//
+// The size of a USB keyboard report.
+//
+//*****************************************************************************
+#define USBHKEYB_REPORT_SIZE    8
+
+//*****************************************************************************
+//
+// These are the flags for the tUSBHKeyboard.ulHIDFlags member variable.
+//
+//*****************************************************************************
+#define USBHKEYB_DEVICE_PRESENT 0x00000001
+
+//*****************************************************************************
+//
+// This is the structure definition for a keyboard device instance.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    // Global flags for an instance of a keyboard.
+    //
+    unsigned long ulHIDFlags;
+
+    //
+    // The applications registered callback.
+    //
+    tUSBCallback pfnCallback;
+
+    //
+    // The HID instance pointer for this keyboard instance.
+    //
+    unsigned long ulHIDInstance;
+
+    //
+    // NUM_LOCK, CAPS_LOCK, SCROLL_LOCK, COMPOSE or KANA keys.
+    //
+    unsigned char ucKeyModSticky;
+
+    //
+    // This is the current state of the keyboard modifier keys.
+    //
+    unsigned char ucKeyModState;
+
+    //
+    // This holds the keyboard usage codes for keys that are being held down.
+    //
+    unsigned char pucKeyState[6];
+
+    //
+    // This is a local buffer to hold the current HID report that comes up
+    // from the HID driver layer.
+    //
+    unsigned char pucBuffer[USBHKEYB_REPORT_SIZE];
+}
+tUSBHKeyboard;
+
+//*****************************************************************************
+//
+// This is the per instance information for a keyboard device.
+//
+//*****************************************************************************
+static tUSBHKeyboard g_sUSBHKeyboard =
+{
+    0
+};
+
+//*****************************************************************************
+//
+//! This function is used open an instance of a keyboard.
+//!
+//! \param pfnCallback is the callback function to call when new events occur
+//! with the keyboard returned.
+//! \param pucBuffer is the memory used by the keyboard to interact with the
+//! USB keyboard.
+//! \param ulSize is the size of the buffer provided by \e pucBuffer.
+//!
+//! This function is used to open an instance of the keyboard.  The value
+//! returned from this function should be used as the instance identifier for
+//! all other USBHKeyboard calls.  The \e pucBuffer memory buffer is used to
+//! access the keyboard.  The buffer size required is at least enough to hold
+//! a normal report descriptor for the device.  If there is not enough space
+//! only a partial report descriptor will be read out.
+//!
+//! \return Returns the instance identifier for the keyboard that is attached.
+//! If there is no keyboard present this will return 0.
+//
+//*****************************************************************************
+unsigned long
+USBHKeyboardOpen(tUSBCallback pfnCallback, unsigned char *pucBuffer,
+                 unsigned long ulSize)
+{
+    //
+    // Save the callback and data pointers.
+    //
+    g_sUSBHKeyboard.pfnCallback = pfnCallback;
+
+    //
+    // Save the instance pointer for the HID device that was opened.
+    //
+    g_sUSBHKeyboard.ulHIDInstance =
+        USBHHIDOpen(USBH_HID_DEV_KEYBOARD, USBHKeyboardCallback,
+                    (unsigned long)&g_sUSBHKeyboard);
+
+    return((unsigned long)&g_sUSBHKeyboard);
+}
+
+//*****************************************************************************
+//
+//! This function is used close an instance of a keyboard.
+//!
+//! \param ulInstance is the instance value for this keyboard.
+//!
+//! This function is used to close an instance of the keyboard that was opened
+//! with a call to USBHKeyboardOpen().  The \e ulInstance value is the value
+//! that was returned when the application called USBHKeyboardOpen().
+//!
+//! \return This function returns 0 to indicate success any non-zero value
+//! indicates an error condition.
+//
+//*****************************************************************************
+unsigned long
+USBHKeyboardClose(unsigned long ulInstance)
+{
+    tUSBHKeyboard *pUSBHKeyboard;
+
+    //
+    // Recover the pointer to the instance data.
+    //
+    pUSBHKeyboard = (tUSBHKeyboard *)ulInstance;
+
+    //
+    // Reset the callback to null.
+    //
+    pUSBHKeyboard->pfnCallback = 0;
+
+    //
+    // Call the HID driver layer to close out this instance.
+    //
+    USBHHIDClose(pUSBHKeyboard->ulHIDInstance);
+
+    return(0);
+}
+
+//*****************************************************************************
+//
+//! This function is used to map a USB usage ID to a printable character.
+//!
+//! \param ulInstance is the instance value for this keyboard.
+//! \param pTable is the table to use to map the usage ID to characters.
+//! \param ucUsageID is the USB usage ID to map to a character.
+//!
+//! This function is used to map a USB usage ID to a character.  The provided
+//! \e pTable is used to perform the mapping and is described by the
+//! tHIDKeyboardUsageTable type defined structure.  See the documentation on
+//! the tHIDKeyboardUsageTable structure for more details on the internals of
+//! this structure.  This function uses the current state of the shift keys
+//! and the Caps Lock key to modify the data returned by this function.  The
+//! pTable structure has values indicating which keys are modified by Caps Lock
+//! and alternate values for shifted cases.  The number of bytes returned from
+//! this function depends on the \e pTable structure passed in as it holds the
+//! number of bytes per character in the table.
+//!
+//! \return Returns the character value for the given usage id.
+//
+//*****************************************************************************
+unsigned long
+USBHKeyboardUsageToChar(unsigned long ulInstance,
+                        const tHIDKeyboardUsageTable *pTable,
+                        unsigned char ucUsageID)
+{
+    unsigned long ulValue;
+    const unsigned char *pucKeyBoardMap;
+    const unsigned short *pusKeyBoardMap;
+    unsigned long ulOffset;
+    unsigned long ulShift;
+    tUSBHKeyboard *pUSBHKeyboard;
+
+    //
+    // Recover the pointer to the instance data.
+    //
+    pUSBHKeyboard = (tUSBHKeyboard *)ulInstance;
+
+    //
+    // The added offset for the shifted character value.
+    //
+    ulShift = 0;
+
+    //
+    // Offset in the table for the character.
+    //
+    ulOffset = (ucUsageID * pTable->ucBytesPerChar * 2);
+
+    //
+    // Handle the case where CAPS lock has been set.
+    //
+    if(pUSBHKeyboard->ucKeyModSticky &= HID_KEYB_CAPS_LOCK)
+    {
+        //
+        // See if this usage ID is modified by Caps Lock by checking the packed
+        // bit array in the pulShiftState member of the pTable array.
+        //
+        if((pTable->pulCapsLock[ucUsageID >> 5]) >> (ucUsageID & 0x1f) & 1)
+        {
+            ulShift = pTable->ucBytesPerChar;
+        }
+    }
+
+    //
+    // Now handle if a shift key is being held.
+    //
+    if((pUSBHKeyboard->ucKeyModState & 0x22) != 0)
+    {
+        //
+        // Not shifted yet so we need to shift.
+        //
+        if(ulShift == 0)
+        {
+            ulShift = pTable->ucBytesPerChar;
+        }
+        else
+        {
+            //
+            // Unshift because CAPS LOCK and shift were presed.
+            //
+            ulShift = 0;
+        }
+    }
+
+    //
+    // One byte per character.
+    //
+    if(pTable->ucBytesPerChar == 1)
+    {
+        //
+        // Get the base address of the table.
+        //
+        pucKeyBoardMap = pTable->pCharMapping;
+
+        ulValue = pucKeyBoardMap[ulOffset + ulShift];
+    }
+    //
+    // Two bytes per character.
+    //
+    else if(pTable->ucBytesPerChar == 2)
+    {
+        //
+        // Get the base address of the table.
+        //
+        pusKeyBoardMap = (unsigned short *)pTable->pCharMapping;
+
+        ulValue = pusKeyBoardMap[ulOffset + ulShift];
+    }
+    //
+    // All other sizes are unsupported for now.
+    //
+    else
+    {
+        ulValue = 0;
+    }
+
+    return(ulValue);
+}
+
+//*****************************************************************************
+//
+//! This function is used to set one of the fixed modifier keys on a keyboard.
+//!
+//! \param ulInstance is the instance value for this keyboard.
+//! \param ulModifiers is a bit mask of the modifiers to set on the keyboard.
+//!
+//! This function is used to set the modifier key states on a keyboard.  The
+//! \e ulModifiers value is a bitmask of the following set of values:
+//! - HID_KEYB_NUM_LOCK
+//! - HID_KEYB_CAPS_LOCK
+//! - HID_KEYB_SCROLL_LOCK
+//! - HID_KEYB_COMPOSE
+//! - HID_KEYB_KANA
+//!
+//! Not all of these will be supported on all keyboards however setting values
+//! on a keyboard that does not have them should have no effect.  The
+//! \e ulInstance value is the value that was returned when the application
+//! called USBHKeyboardOpen().  If the value \b HID_KEYB_CAPS_LOCK is used it
+//! will modify the values returned from the USBHKeyboardUsageToChar()
+//! function.
+//!
+//! \return This function returns 0 to indicate success any non-zero value
+//! indicates an error condition.
+//
+//*****************************************************************************
+unsigned long
+USBHKeyboardModifierSet(unsigned long ulInstance, unsigned long ulModifiers)
+{
+    tUSBHKeyboard *pUSBHKeyboard;
+
+    //
+    // Recover the pointer to the instance data.
+    //
+    pUSBHKeyboard = (tUSBHKeyboard *)ulInstance;
+
+    //
+    // Remeber the fact that this is set.
+    //
+    pUSBHKeyboard->ucKeyModSticky = (unsigned char)ulModifiers;
+
+    //
+    // Set the LEDs on the keyboard.
+    //
+    USBHHIDSetReport(pUSBHKeyboard->ulHIDInstance, 0,
+                     (unsigned char *)&ulModifiers, 1);
+
+    return(0);
+}
+
+//*****************************************************************************
+//
+//! This function is used to initialize a keyboard interface after a keyboard
+//! has been detected.
+//!
+//! \param ulInstance is the instance value for this keyboard.
+//!
+//! This function should be called after receiving a \b USB_EVENT_CONNECTED
+//! event in the callback function provided by USBHKeyboardOpen(), however this
+//! function should only be called outside the callback function.  This will
+//! initialize the keyboard interface and determine the keyboard's
+//! layout and how it reports keys to the USB host controller.  The
+//! \e ulInstance value is the value that was returned when the application
+//! called USBHKeyboardOpen().  This function only needs to be called once
+//! per connection event but it should be called every time a
+//! \b USB_EVENT_CONNECTED event occurs.
+//!
+//! \return This function returns 0 to indicate success any non-zero value
+//! indicates an error condition.
+//
+//*****************************************************************************
+unsigned long
+USBHKeyboardInit(unsigned long ulInstance)
+{
+    unsigned char ucModData;
+    tUSBHKeyboard *pUSBHKeyboard;
+
+    //
+    // Recover the pointer to the instance data.
+    //
+    pUSBHKeyboard = (tUSBHKeyboard *)ulInstance;
+
+    //
+    // Set the initial rate to only update on keyboard state changes.
+    //
+    USBHHIDSetIdle(pUSBHKeyboard->ulHIDInstance, 0, 0);
+
+    //
+    // Read out the Report Descriptor from the keyboard and parse it for
+    // the format of the reports coming back from the keyboard.
+    //
+    USBHHIDGetReportDescriptor(pUSBHKeyboard->ulHIDInstance,
+                               pUSBHKeyboard->pucBuffer,
+                               USBHKEYB_REPORT_SIZE);
+
+    //
+    // Set the keyboard to boot protocol.
+    //
+    USBHHIDSetProtocol(pUSBHKeyboard->ulHIDInstance, 1);
+
+    //
+    // Used to clear the initial state of all on keyboard modifiers.
+    //
+    ucModData = 0;
+
+    //
+    // Update the keyboard LED state.
+    //
+    USBHHIDSetReport(pUSBHKeyboard->ulHIDInstance, 0, &ucModData, 1);
+
+    return(0);
+}
+
+//*****************************************************************************
+//
+//! This function is used to set the automatic poll rate of the keyboard.
+//!
+//! \param ulInstance is the instance value for this keyboard.
+//! \param ulPollRate is the rate in ms to cause the keyboard to update the
+//! host regardless of no change in key state.
+//!
+//! This function will allow an application to tell the keyboard how often it
+//! should send updates to the USB host controller regardless of any changes
+//! in keyboard state.  The \e ulInstance value is the value that was returned
+//! when the application called USBHKeyboardOpen().  The \e ulPollRate is the
+//! new value in ms for the update rate on the keyboard.  This value is
+//! initially set to 0 which indicates that the keyboard should only to update
+//! when the keyboard state changes.  Any value other than 0 can be used to
+//! force the keyboard to generate auto-repeat sequences for the application.
+//!
+//! \return This function returns 0 to indicate success any non-zero value
+//! indicates an error condition.
+//
+//*****************************************************************************
+unsigned long
+USBHKeyboardPollRateSet(unsigned long ulInstance, unsigned long ulPollRate)
+{
+    tUSBHKeyboard *pUSBHKeyboard;
+
+    //
+    // Recover the pointer to the instance data.
+    //
+    pUSBHKeyboard = (tUSBHKeyboard *)ulInstance;
+
+    //
+    // Send the Set Idle command to the USB keyboard.
+    //
+    USBHHIDSetIdle(pUSBHKeyboard->ulHIDInstance, ulPollRate, 0);
+
+    return(0);
+}
+
+//*****************************************************************************
+//
+// This is an internal function used to modify the current keyboard state.
+//
+// This function checks for changes in the keyboard state due to a new report
+// being received from the device.  It first checks if this is a "roll-over"
+// case by seeing if 0x01 is in the first position of the new keyboard report.
+// This indicates that too many keys were pressed to handle and to ignore this
+// report.  Next the keyboard modifier state is stored and if any changes are
+// detected a \b USBH_EVENT_HID_KB_MOD event is sent back to the application.
+// Then this function will check for any keys that have been released and send
+// a \b USBH_EVENT_HID_KB_REL even for each of these keys.  The last check is
+// for any new keys that are pressed and a \b USBH_EVENT_HID_KB_PRESS event
+// will be sent for each new key pressed.
+//
+// \return None.
+//
+//*****************************************************************************
+static void
+UpdateKeyboardState(tUSBHKeyboard *pUSBHKeyboard)
+{
+    long lNewKey, lOldKey;
+
+    //
+    // rollover code so ignore this buffer.
+    //
+    if(pUSBHKeyboard->pucBuffer[2] == 0x01)
+    {
+        return;
+    }
+
+    //
+    // Handle the keyboard modifier states.
+    //
+    if(pUSBHKeyboard->ucKeyModState != pUSBHKeyboard->pucBuffer[0])
+    {
+        //
+        // Notify the application of the event.
+        //
+        pUSBHKeyboard->pfnCallback(0, USBH_EVENT_HID_KB_MOD,
+                                   pUSBHKeyboard->pucBuffer[0], 0);
+
+        //
+        // Save the new state of the modifier keys.
+        //
+        pUSBHKeyboard->ucKeyModState = pUSBHKeyboard->pucBuffer[0];
+    }
+
+    //
+    // This loop checks for keys that have been released to make room for new
+    // ones that may have been pressed.
+    //
+    for(lOldKey = 2; lOldKey < 8; lOldKey++)
+    {
+        //
+        // If there is no old key pressed in this entry go to the next one.
+        //
+        if(pUSBHKeyboard->pucKeyState[lOldKey] == 0)
+        {
+            continue;
+        }
+
+        //
+        // Check if this old key is still in the list of currently pressed
+        // keys.
+        //
+        for(lNewKey = 2; lNewKey < 8; lNewKey++)
+        {
+            //
+            // Break out if the key is still present.
+            //
+            if(pUSBHKeyboard->pucBuffer[lNewKey]
+                            == pUSBHKeyboard->pucKeyState[lOldKey])
+            {
+                break;
+            }
+        }
+        //
+        // If the old key was no longer in the list of pressed keys then
+        // notify the application of the key release.
+        //
+        if(lNewKey == 8)
+        {
+            //
+            // Send the key release notification to the application.
+            //
+            pUSBHKeyboard->pfnCallback(0,
+                                       USBH_EVENT_HID_KB_REL,
+                                       pUSBHKeyboard->pucKeyState[lOldKey],
+                                       0);
+            //
+            // Remove the old key from the currently held key list.
+            //
+            pUSBHKeyboard->pucKeyState[lOldKey] = 0;
+
+        }
+    }
+
+    //
+    // This loop checks for new keys that have been pressed.
+    //
+    for(lNewKey = 2; lNewKey < 8; lNewKey++)
+    {
+        //
+        // The new list is empty so no new keys are pressed.
+        //
+        if(pUSBHKeyboard->pucBuffer[lNewKey] == 0)
+        {
+            break;
+        }
+
+        //
+        // This loop checks if the current key was already pressed.
+        //
+        for(lOldKey = 2; lOldKey < 8; lOldKey++)
+        {
+            //
+            // If it is in both lists then it was already pressed so ignore it.
+            //
+            if(pUSBHKeyboard->pucBuffer[lNewKey]
+                            == pUSBHKeyboard->pucKeyState[lOldKey])
+            {
+                break;
+            }
+        }
+        //
+        // The key in the new list was not found so it is new.
+        //
+        if(lOldKey == 8)
+        {
+            //
+            // Look for a free location to store this key usage code.
+            //
+            for(lOldKey = 2; lOldKey < 8; lOldKey++)
+            {
+                //
+                // If an empty location is found, store it and notify the
+                // application.
+                //
+                if(pUSBHKeyboard->pucKeyState[lOldKey] == 0)
+                {
+                    //
+                    // Save the newly pressed key.
+                    //
+                    pUSBHKeyboard->pucKeyState[lOldKey]
+                                    = pUSBHKeyboard->pucBuffer[lNewKey];
+
+                    //
+                    // Notify the application of the new key that has been
+                    // pressed.
+                    //
+                    pUSBHKeyboard->pfnCallback(
+                        0,
+                        USBH_EVENT_HID_KB_PRESS,
+                        pUSBHKeyboard->pucBuffer[lNewKey],
+                        0);
+
+                    break;
+                }
+            }
+        }
+    }
+}
+
+//*****************************************************************************
+//
+//! This function handles event callbacks from the USB HID driver layer.
+//!
+//! \param pvCBData is the pointer that was passed in to the USBHHIDOpen()
+//! call.
+//! \param ulEvent is the event that has been passed up from the HID driver.
+//! \param ulMsgParam has meaning related to the \e ulEvent that occurred.
+//! \param pvMsgData has meaning related to the \e ulEvent that occurred.
+//!
+//! This function will receive all event updates from the HID driver layer.
+//! The keyboard driver itself will mostly be concerned with report callbacks
+//! from the HID driver layer and parsing them into keystrokes for the
+//! application that has registered for callbacks with the USBHKeyboardOpen()
+//! call.
+//!
+//! \return Non-zero values should be assumed to indicate an error condition.
+//
+//*****************************************************************************
+unsigned long
+USBHKeyboardCallback(void *pvCBData, unsigned long ulEvent,
+                     unsigned long ulMsgParam, void *pvMsgData)
+{
+    tUSBHKeyboard *pUSBHKeyboard;
+
+    //
+    // Recover the pointer to the instance data.
+    //
+    pUSBHKeyboard = (tUSBHKeyboard *)pvCBData;
+
+    switch (ulEvent)
+    {
+        //
+        // New keyboard has been connected so notify the application.
+        //
+        case USB_EVENT_CONNECTED:
+        {
+            //
+            // Remember that a keyboard is present.
+            //
+            pUSBHKeyboard->ulHIDFlags |= USBHKEYB_DEVICE_PRESENT;
+
+            //
+            // Notify the application that a new keyboard was connected.
+            //
+            pUSBHKeyboard->pfnCallback(0, ulEvent, ulMsgParam, pvMsgData);
+
+            break;
+        }
+        case USB_EVENT_DISCONNECTED:
+        {
+            //
+            // No keyboard is present.
+            //
+            pUSBHKeyboard->ulHIDFlags &= ~USBHKEYB_DEVICE_PRESENT;
+
+            //
+            // Notify the application that the keyboard was disconnected.
+            //
+            pUSBHKeyboard->pfnCallback(0, ulEvent, ulMsgParam, pvMsgData);
+
+            break;
+        }
+        case USB_EVENT_RX_AVAILABLE:
+        {
+            //
+            // New keyboard report structure was received.
+            //
+            USBHHIDGetReport(pUSBHKeyboard->ulHIDInstance, 0,
+                             pUSBHKeyboard->pucBuffer,
+                             USBHKEYB_REPORT_SIZE);
+
+            //
+            // Update the application on the changes in the keyboard state.
+            //
+            UpdateKeyboardState(pUSBHKeyboard);
+
+            break;
+        }
+    }
+    return(0);
+}
+
+//*****************************************************************************
+//
+//! @}
+//
+//*****************************************************************************
diff --git a/src/platform/lm3s/usblib/host/usbhhidkeyboard.h b/src/platform/lm3s/usblib/host/usbhhidkeyboard.h
new file mode 100755
index 00000000..ea6e86c8
--- /dev/null
+++ b/src/platform/lm3s/usblib/host/usbhhidkeyboard.h
@@ -0,0 +1,77 @@
+//*****************************************************************************
+//
+// usbhhidkeyboard.h - This file holds the application interfaces for USB
+//                     keyboard devices.
+//
+// Copyright (c) 2008-2011 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 7611 of the Stellaris USB Library.
+//
+//*****************************************************************************
+
+#ifndef __USBHHIDKEYBOARD_H__
+#define __USBHHIDKEYBOARD_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+//! \addtogroup usblib_host_device
+//! @{
+//
+//*****************************************************************************
+
+extern unsigned long USBHKeyboardOpen(tUSBCallback pfnCallback,
+                                      unsigned char *pucBuffer,
+                                      unsigned long ulBufferSize);
+extern unsigned long USBHKeyboardClose(unsigned long ulInstance);
+extern unsigned long USBHKeyboardInit(unsigned long ulInstance);
+extern unsigned long USBHKeyboardModifierSet(unsigned long ulInstance,
+                                             unsigned long ulModifiers);
+extern unsigned long USBHKeyboardPollRateSet(unsigned long ulInstance,
+                                             unsigned long ulPollRate);
+
+extern unsigned long USBHKeyboardUsageToChar(
+    unsigned long ulInstance,
+    const tHIDKeyboardUsageTable *pTable,
+    unsigned char ucUsageID);
+
+//*****************************************************************************
+//
+//! @}
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/platform/lm3s/usblib/host/usbhhidmouse.c b/src/platform/lm3s/usblib/host/usbhhidmouse.c
new file mode 100755
index 00000000..f7f1c23c
--- /dev/null
+++ b/src/platform/lm3s/usblib/host/usbhhidmouse.c
@@ -0,0 +1,415 @@
+//*****************************************************************************
+//
+// usbhhidmouse.c - This file holds the application interfaces for USB
+//                  mouse devices.
+//
+// Copyright (c) 2008-2011 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 7611 of the Stellaris USB Library.
+//
+//*****************************************************************************
+
+#include "inc/hw_types.h"
+#include "usblib/usblib.h"
+#include "usblib/host/usbhost.h"
+#include "usblib/usbhid.h"
+#include "usblib/host/usbhhid.h"
+#include "usblib/host/usbhhidmouse.h"
+
+//*****************************************************************************
+//
+//! \addtogroup usblib_host_device
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Prototypes for local functions.
+//
+//*****************************************************************************
+static unsigned long USBHMouseCallback(void *pvCBData,
+                                       unsigned long ulEvent,
+                                       unsigned long ulMsgParam,
+                                       void *pvMsgData);
+
+//*****************************************************************************
+//
+// The size of a USB mouse report.
+//
+//*****************************************************************************
+#define USBHMS_REPORT_SIZE      4
+
+//*****************************************************************************
+//
+// These are the flags for the tUSBHMouse.ulHIDFlags member variable.
+//
+//*****************************************************************************
+#define USBHMS_DEVICE_PRESENT   0x00000001
+
+//*****************************************************************************
+//
+// This is the structure definition for a mouse device instance.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    // Global flags for an instance of a mouse.
+    //
+    unsigned long ulHIDFlags;
+
+    //
+    // The applications registered callback.
+    //
+    tUSBCallback pfnCallback;
+
+    //
+    // The current state of the buttons.
+    //
+    unsigned char ucButtons;
+
+    //
+    // This is a local buffer to hold the current HID report that comes up
+    // from the HID driver layer.
+    //
+    unsigned char pucBuffer[USBHMS_REPORT_SIZE];
+
+    //
+    // Heap data for the mouse currently used to read the HID Report
+    // Descriptor.
+    //
+    unsigned char *pucHeap;
+
+    //
+    // Size of the heap in bytes.
+    //
+    unsigned long ulHeapSize;
+
+    //
+    // This is the instance value for the HID device that will be used for the
+    // mouse.
+    //
+    unsigned long ulMouseInstance;
+}
+tUSBHMouse;
+
+//*****************************************************************************
+//
+// This is the per instance information for a mouse device.
+//
+//*****************************************************************************
+static tUSBHMouse g_sUSBHMouse =
+{
+    0
+};
+
+//*****************************************************************************
+//
+//! This function is used open an instance of a mouse.
+//!
+//! \param pfnCallback is the callback function to call when new events occur
+//! with the mouse returned.
+//! \param pucBuffer is the memory used by the driver to interact with the
+//! USB mouse.
+//! \param ulSize is the size of the buffer provided by \e pucBuffer.
+//!
+//! This function is used to open an instance of the mouse.  The value
+//! returned from this function should be used as the instance identifier for
+//! all other USBHMouse calls.  The \e pucBuffer memory buffer is used to
+//! access the mouse.  The buffer size required is at least enough to hold
+//! a normal report descriptor for the device.
+//!
+//! \return Returns the instance identifier for the mouse that is attached.
+//! If there is no mouse present this will return 0.
+//
+//*****************************************************************************
+unsigned long
+USBHMouseOpen(tUSBCallback pfnCallback, unsigned char *pucBuffer,
+              unsigned long ulSize)
+{
+    //
+    // Save the callback and data pointers.
+    //
+    g_sUSBHMouse.pfnCallback = pfnCallback;
+
+    //
+    // Save the instance pointer for the HID device that was opened.
+    //
+    g_sUSBHMouse.ulMouseInstance = USBHHIDOpen(USBH_HID_DEV_MOUSE,
+                                               USBHMouseCallback,
+                                               (unsigned long)&g_sUSBHMouse);
+
+    //
+    // Save the heap buffer and size.
+    //
+    g_sUSBHMouse.pucHeap = pucBuffer;
+    g_sUSBHMouse.ulHeapSize = ulSize;
+
+    return((unsigned long)&g_sUSBHMouse);
+}
+
+//*****************************************************************************
+//
+//! This function is used close an instance of a mouse.
+//!
+//! \param ulInstance is the instance value for this mouse.
+//!
+//! This function is used to close an instance of the mouse that was opened
+//! with a call to USBHMouseOpen().  The \e ulInstance value is the value
+//! that was returned when the application called USBHMouseOpen().
+//!
+//! \return Returns 0.
+//
+//*****************************************************************************
+unsigned long
+USBHMouseClose(unsigned long ulInstance)
+{
+    tUSBHMouse *pUSBHMouse;
+
+    //
+    // Recover the pointer to the instance data.
+    //
+    pUSBHMouse = (tUSBHMouse *)ulInstance;
+
+    //
+    // Reset the callback to null.
+    //
+    pUSBHMouse->pfnCallback = 0;
+
+    //
+    // Call the HID driver layer to close out this instance.
+    //
+    USBHHIDClose(pUSBHMouse->ulMouseInstance);
+
+    return(0);
+}
+
+//*****************************************************************************
+//
+//! This function is used to initialize a mouse interface after a mouse has
+//! been detected.
+//!
+//! \param ulInstance is the instance value for this mouse.
+//!
+//! This function should be called after receiving a \b USB_EVENT_CONNECTED
+//! event in the callback function provided by USBHMouseOpen(), however it
+//! should only be called outside of the callback function.  This will
+//! initialize the mouse interface and determine how it reports events to the
+//! USB host controller.  The \e ulInstance value is the value that was
+//! returned when the application called USBHMouseOpen().  This function only
+//! needs to be called once per connection event but it should be called every
+//! time a \b USB_EVENT_CONNECTED event occurs.
+//!
+//! \return Non-zero values should be assumed to indicate an error condition.
+//
+//*****************************************************************************
+unsigned long
+USBHMouseInit(unsigned long ulInstance)
+{
+    tUSBHMouse *pUSBHMouse;
+
+    //
+    // Recover the pointer to the instance data.
+    //
+    pUSBHMouse = (tUSBHMouse *)ulInstance;
+
+    //
+    // Set the initial rate to only update on mouse state changes.
+    //
+    USBHHIDSetIdle(pUSBHMouse->ulMouseInstance, 0, 0);
+
+    //
+    // Read out the Report Descriptor from the mouse and parse it for
+    // the format of the reports coming back from the mouse.
+    //
+    USBHHIDGetReportDescriptor(pUSBHMouse->ulMouseInstance,
+                               pUSBHMouse->pucHeap,
+                               pUSBHMouse->ulHeapSize);
+
+    //
+    // Set the mouse to boot protocol.
+    //
+    USBHHIDSetProtocol(pUSBHMouse->ulMouseInstance, 1);
+
+    return(0);
+}
+
+//*****************************************************************************
+//
+// This function handles updating the state of the mouse buttons and axis.
+//
+// \param pUSBHMouse is the pointer to an instance of the mouse data.
+//
+// This function will check for updates to buttons or X/Y movements and send
+// callbacks to the mouse callback function.
+//
+// \return None.
+//
+//*****************************************************************************
+static void
+UpdateMouseState(tUSBHMouse *pUSBHMouse)
+{
+    unsigned long ulButton;
+
+    if(pUSBHMouse->pucBuffer[0] != pUSBHMouse->ucButtons)
+    {
+        for(ulButton = 1; ulButton <= 0x4; ulButton <<= 1)
+        {
+            if(((pUSBHMouse->pucBuffer[0] & ulButton) != 0) &&
+               ((pUSBHMouse->ucButtons & ulButton) == 0))
+            {
+                //
+                // Send the mouse button press notification to the application.
+                //
+                pUSBHMouse->pfnCallback(0,
+                                        USBH_EVENT_HID_MS_PRESS,
+                                        ulButton,
+                                        0);
+            }
+            if(((pUSBHMouse->pucBuffer[0] & ulButton) == 0) &&
+               ((pUSBHMouse->ucButtons & ulButton) != 0))
+            {
+                //
+                // Send the mouse button release notification to the
+                // application.
+                //
+                pUSBHMouse->pfnCallback(0,
+                                        USBH_EVENT_HID_MS_REL,
+                                        ulButton,
+                                        0);
+            }
+        }
+
+        //
+        // Save the new state.
+        //
+        pUSBHMouse->ucButtons = pUSBHMouse->pucBuffer[0];
+    }
+    if(pUSBHMouse->pucBuffer[1] != 0)
+    {
+        //
+        // Send the mouse button release notification to the
+        // application.
+        //
+        pUSBHMouse->pfnCallback(0,
+                                USBH_EVENT_HID_MS_X,
+                                (unsigned long)pUSBHMouse->pucBuffer[1],
+                                0);
+    }
+    if(pUSBHMouse->pucBuffer[2] != 0)
+    {
+        //
+        // Send the mouse button release notification to the
+        // application.
+        //
+        pUSBHMouse->pfnCallback(0,
+                                USBH_EVENT_HID_MS_Y,
+                                (unsigned long)pUSBHMouse->pucBuffer[2],
+                                0);
+    }
+}
+
+//*****************************************************************************
+//
+//! This function handles event callbacks from the USB HID driver layer.
+//!
+//! \param pvCBData is the pointer that was passed in to the USBHHIDOpen()
+//! call.
+//! \param ulEvent is the event that has been passed up from the HID driver.
+//! \param ulMsgParam has meaning related to the \e ulEvent that occurred.
+//! \param pvMsgData has meaning related to the \e ulEvent that occurred.
+//!
+//! This function will receive all event updates from the HID driver layer.
+//! The mouse driver itself will mostly be concerned with report callbacks
+//! from the HID driver layer and parsing them into keystrokes for the
+//! application that has registered for callbacks with the USBHMouseOpen()
+//! call.
+//!
+//! \return Non-zero values should be assumed to indicate an error condition.
+//
+//*****************************************************************************
+unsigned long
+USBHMouseCallback(void *pvCBData, unsigned long ulEvent,
+                  unsigned long ulMsgParam, void *pvMsgData)
+{
+    tUSBHMouse *pUSBHMouse;
+
+    //
+    // Recover the pointer to the instance data.
+    //
+    pUSBHMouse = (tUSBHMouse *)pvCBData;
+
+    switch(ulEvent)
+    {
+        //
+        // New mouse has been connected so notify the application.
+        //
+        case USB_EVENT_CONNECTED:
+        {
+            //
+            // Remember that a mouse is present.
+            //
+            pUSBHMouse->ulHIDFlags |= USBHMS_DEVICE_PRESENT;
+
+            //
+            // Notify the application that a new mouse was connected.
+            //
+            pUSBHMouse->pfnCallback(0, ulEvent, ulMsgParam, pvMsgData);
+
+            break;
+        }
+        case USB_EVENT_DISCONNECTED:
+        {
+            //
+            // No mouse is present.
+            //
+            pUSBHMouse->ulHIDFlags &= ~USBHMS_DEVICE_PRESENT;
+
+            //
+            // Notify the application that the mouse was disconnected.
+            //
+            pUSBHMouse->pfnCallback(0, ulEvent, ulMsgParam, pvMsgData);
+
+            break;
+        }
+        case USB_EVENT_RX_AVAILABLE:
+        {
+            //
+            // New mouse report structure was received.
+            //
+            USBHHIDGetReport(pUSBHMouse->ulMouseInstance, 0,
+                             pUSBHMouse->pucBuffer,
+                             USBHMS_REPORT_SIZE);
+
+            //
+            // Update the current state of the mouse and notify the application
+            // of any changes.
+            //
+            UpdateMouseState(pUSBHMouse);
+
+            break;
+        }
+    }
+    return(0);
+}
+
+//*****************************************************************************
+//
+//! @}
+//
+//*****************************************************************************
diff --git a/src/platform/lm3s/usblib/host/usbhhidmouse.h b/src/platform/lm3s/usblib/host/usbhhidmouse.h
new file mode 100755
index 00000000..db952cb8
--- /dev/null
+++ b/src/platform/lm3s/usblib/host/usbhhidmouse.h
@@ -0,0 +1,68 @@
+//*****************************************************************************
+//
+// usbhhidmouse.h - This file holds the application interfaces for USB
+// mouse devices.
+//
+// Copyright (c) 2008-2011 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 7611 of the Stellaris USB Library.
+//
+//*****************************************************************************
+
+#ifndef __USBHHIDMOUSE_H__
+#define __USBHHIDMOUSE_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+//! \addtogroup usblib_host_device
+//! @{
+//
+//*****************************************************************************
+
+extern unsigned long USBHMouseOpen(tUSBCallback pfnCallback,
+                                   unsigned char *pucBuffer,
+                                   unsigned long ulBufferSize);
+extern unsigned long USBHMouseClose(unsigned long ulInstance);
+extern unsigned long USBHMouseInit(unsigned long ulInstance);
+
+//*****************************************************************************
+//
+//! @}
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/platform/lm3s/usblib/host/usbhmsc.c b/src/platform/lm3s/usblib/host/usbhmsc.c
new file mode 100755
index 00000000..4a0e23b8
--- /dev/null
+++ b/src/platform/lm3s/usblib/host/usbhmsc.c
@@ -0,0 +1,687 @@
+//*****************************************************************************
+//
+// usbhmsc.c - USB MSC host driver.
+//
+// Copyright (c) 2008-2011 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 7611 of the Stellaris USB Library.
+//
+//*****************************************************************************
+
+#include "inc/hw_types.h"
+#include "driverlib/usb.h"
+#include "usblib/usblib.h"
+#include "usblib/usbmsc.h"
+#include "usblib/host/usbhost.h"
+#include "usblib/host/usbhmsc.h"
+#include "usblib/host/usbhscsi.h"
+
+//*****************************************************************************
+//
+//! \addtogroup usblib_host_class
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Forward declarations for the driver open and close calls.
+//
+//*****************************************************************************
+static void *USBHMSCOpen(tUSBHostDevice *pDevice);
+static void USBHMSCClose(void *pvInstance);
+
+//*****************************************************************************
+//
+// This is the structure for an instance of a USB MSC host driver.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    // Save the device instance.
+    //
+    tUSBHostDevice *pDevice;
+
+    //
+    // Used to save the callback.
+    //
+    tUSBHMSCCallback pfnCallback;
+
+    //
+    // The Maximum LUNs
+    //
+    unsigned long ulMaxLUN;
+
+    //
+    // The total number of blocks associated with this device.
+    //
+    unsigned long ulNumBlocks;
+
+    //
+    // The size of the blocks associated with this device.
+    //
+    unsigned long ulBlockSize;
+
+    //
+    // Bulk IN pipe.
+    //
+    unsigned long ulBulkInPipe;
+
+    //
+    // Bulk OUT pipe.
+    //
+    unsigned long ulBulkOutPipe;
+}
+tUSBHMSCInstance;
+
+//*****************************************************************************
+//
+// The array of USB MSC host drivers.
+//
+//*****************************************************************************
+static tUSBHMSCInstance g_USBHMSCDevice =
+{
+    0
+};
+
+//*****************************************************************************
+//
+//! This constant global structure defines the Mass Storage Class Driver that
+//! is provided with the USB library.
+//
+//*****************************************************************************
+const tUSBHostClassDriver g_USBHostMSCClassDriver =
+{
+    USB_CLASS_MASS_STORAGE,
+    USBHMSCOpen,
+    USBHMSCClose,
+    0
+};
+
+//*****************************************************************************
+//
+//! This function is used to open an instance of the MSC driver.
+//!
+//! \param pDevice is a pointer to the device information structure.
+//!
+//! This function will attempt to open an instance of the MSC driver based on
+//! the information contained in the pDevice structure.  This call can fail if
+//! there are not sufficient resources to open the device.  The function will
+//! return a value that should be passed back into USBMSCClose() when the
+//! driver is no longer needed.
+//!
+//! \return The function will return a pointer to a MSC driver instance.
+//
+//*****************************************************************************
+static void *
+USBHMSCOpen(tUSBHostDevice *pDevice)
+{
+    long lIdx;
+    tEndpointDescriptor *pEndpointDescriptor;
+    tInterfaceDescriptor *pInterface;
+
+    //
+    // Don't allow the device to be opened without closing first.
+    //
+    if(g_USBHMSCDevice.pDevice)
+    {
+        return(0);
+    }
+
+    //
+    // Save the device pointer.
+    //
+    g_USBHMSCDevice.pDevice = pDevice;
+
+    //
+    // Get the interface descriptor.
+    //
+    pInterface = USBDescGetInterface(pDevice->pConfigDescriptor, 0, 0);
+
+    //
+    // Loop through the endpoints of the device.
+    //
+    for(lIdx = 0; lIdx < 3; lIdx++)
+    {
+        //
+        // Get the first endpoint descriptor.
+        //
+        pEndpointDescriptor =
+            USBDescGetInterfaceEndpoint(pInterface, lIdx,
+                                        pDevice->ulConfigDescriptorSize);
+
+        //
+        // If no more endpoints then break out.
+        //
+        if(pEndpointDescriptor == 0)
+        {
+            break;
+        }
+
+        //
+        // See if this is a bulk endpoint.
+        //
+        if((pEndpointDescriptor->bmAttributes & USB_EP_ATTR_TYPE_M) ==
+           USB_EP_ATTR_BULK)
+        {
+            //
+            // See if this is bulk IN or bulk OUT.
+            //
+            if(pEndpointDescriptor->bEndpointAddress & USB_EP_DESC_IN)
+            {
+                //
+                // Allocate the USB Pipe for this Bulk IN endpoint.
+                //
+                g_USBHMSCDevice.ulBulkInPipe =
+                    USBHCDPipeAllocSize(0, USBHCD_PIPE_BULK_IN_DMA,
+                                        pDevice->ulAddress,
+                                        pEndpointDescriptor->wMaxPacketSize,
+                                        0);
+                //
+                // Configure the USB pipe as a Bulk IN endpoint.
+                //
+                USBHCDPipeConfig(g_USBHMSCDevice.ulBulkInPipe,
+                                 pEndpointDescriptor->wMaxPacketSize,
+                                 0,
+                                 (pEndpointDescriptor->bEndpointAddress &
+                                  USB_EP_DESC_NUM_M));
+            }
+            else
+            {
+                //
+                // Allocate the USB Pipe for this Bulk OUT endpoint.
+                //
+                g_USBHMSCDevice.ulBulkOutPipe =
+                    USBHCDPipeAllocSize(0, USBHCD_PIPE_BULK_OUT_DMA,
+                                        pDevice->ulAddress,
+                                        pEndpointDescriptor->wMaxPacketSize,
+                                        0);
+                //
+                // Configure the USB pipe as a Bulk OUT endpoint.
+                //
+                USBHCDPipeConfig(g_USBHMSCDevice.ulBulkOutPipe,
+                                 pEndpointDescriptor->wMaxPacketSize,
+                                 0,
+                                 (pEndpointDescriptor->bEndpointAddress &
+                                  USB_EP_DESC_NUM_M));
+            }
+        }
+    }
+
+    //
+    // If the callback exists, call it with an Open event.
+    //
+    if(g_USBHMSCDevice.pfnCallback != 0)
+    {
+        g_USBHMSCDevice.pfnCallback((unsigned long)&g_USBHMSCDevice,
+                                    MSC_EVENT_OPEN, 0);
+    }
+
+    //
+    // Return the only instance of this device.
+    //
+    return(&g_USBHMSCDevice);
+}
+
+//*****************************************************************************
+//
+//! This function is used to release an instance of the MSC driver.
+//!
+//! \param pvInstance is an instance pointer that needs to be released.
+//!
+//! This function will free up any resources in use by the MSC driver instance
+//! that is passed in.  The \e pvInstance pointer should be a valid value that
+//! was returned from a call to USBMSCOpen().
+//!
+//! \return None.
+//
+//*****************************************************************************
+static void
+USBHMSCClose(void *pvInstance)
+{
+    //
+    // Do nothing if there is not a driver open.
+    //
+    if(g_USBHMSCDevice.pDevice == 0)
+    {
+        return;
+    }
+
+    //
+    // Reset the device pointer.
+    //
+    g_USBHMSCDevice.pDevice = 0;
+
+    //
+    // Free the Bulk IN pipe.
+    //
+    if(g_USBHMSCDevice.ulBulkInPipe != 0)
+    {
+        USBHCDPipeFree(g_USBHMSCDevice.ulBulkInPipe);
+    }
+
+    //
+    // Free the Bulk OUT pipe.
+    //
+    if(g_USBHMSCDevice.ulBulkOutPipe != 0)
+    {
+        USBHCDPipeFree(g_USBHMSCDevice.ulBulkOutPipe);
+    }
+
+    //
+    // If the callback exists then call it.
+    //
+    if(g_USBHMSCDevice.pfnCallback != 0)
+    {
+        g_USBHMSCDevice.pfnCallback((unsigned long)&g_USBHMSCDevice,
+                                    MSC_EVENT_CLOSE, 0);
+    }
+}
+
+//*****************************************************************************
+//
+//! This function retrieves the maximum number of the logical units on a
+//! mass storage device.
+//!
+//! \param ulAddress is the device address on the USB bus.
+//! \param ulInterface is the interface number on the device specified by the
+//! \e ulAddress parameter.
+//! \param pucMaxLUN is the byte value returned from the device for the
+//! device's maximum logical unit.
+//!
+//! The device will return one byte of data that contains the maximum LUN
+//! supported by the device.  For example, if the device supports four LUNs
+//! then the LUNs would be numbered from 0 to 3 and the return value would be
+//! 3.  If no LUN is associated with the device, the value returned shall be 0.
+//!
+//! \return None.
+//
+//*****************************************************************************
+static void
+USBHMSCGetMaxLUN(unsigned long ulAddress, unsigned long ulInterface,
+                 unsigned char *pucMaxLUN)
+{
+    tUSBRequest SetupPacket;
+
+    //
+    // This is a Class specific interface IN request.
+    //
+    SetupPacket.bmRequestType =
+        USB_RTYPE_DIR_IN | USB_RTYPE_CLASS | USB_RTYPE_INTERFACE;
+
+    //
+    // Request a the Max LUN for this interface.
+    //
+    SetupPacket.bRequest = USBREQ_GET_MAX_LUN;
+    SetupPacket.wValue = 0;
+
+    //
+    // Indicate the interface to use.
+    //
+    SetupPacket.wIndex = (unsigned short)ulInterface;
+
+    //
+    // Only request a single byte of data.
+    //
+    SetupPacket.wLength = 1;
+
+    //
+    // Put the setup packet in the buffer and send the command.
+    //
+    if(USBHCDControlTransfer(0, &SetupPacket, ulAddress, pucMaxLUN, 1,
+                             MAX_PACKET_SIZE_EP0) != 1)
+    {
+        *pucMaxLUN = 0;
+    }
+}
+
+//*****************************************************************************
+//
+//! This function checks if a drive is ready to be accessed.
+//!
+//! \param ulInstance is the device instance to use for this read.
+//!
+//! This function checks if the current device is ready to be accessed.
+//! It uses the \e ulInstance parameter to determine which device to check and
+//! will return zero when the device is ready.  Any non-zero return code
+//! indicates that the device was not ready.
+//!
+//! \return This function will return zero if the device is ready and it will
+//! return a other value if the device is not ready or if an error occurred.
+//
+//*****************************************************************************
+long
+USBHMSCDriveReady(unsigned long ulInstance)
+{
+    unsigned char ucMaxLUN, pBuffer[SCSI_INQUIRY_DATA_SZ];
+    unsigned long ulSize;
+    tUSBHMSCInstance *pMSCDevice;
+
+    //
+    // Get the instance pointer in a more usable form.
+    //
+    pMSCDevice = (tUSBHMSCInstance *)ulInstance;
+
+    //
+    // If there is no device present then return an error.
+    //
+    if(pMSCDevice->pDevice == 0)
+    {
+        return(-1);
+    }
+
+    //
+    // Get the Maximum LUNs on this device.
+    //
+    USBHMSCGetMaxLUN(g_USBHMSCDevice.pDevice->ulAddress,
+                     g_USBHMSCDevice.pDevice->ulInterface, &ucMaxLUN);
+
+    //
+    // Save the Maximum number of LUNs on this device.
+    //
+    g_USBHMSCDevice.ulMaxLUN = ucMaxLUN;
+
+    //
+    // Just return if the device is returning not present.
+    //
+    ulSize = SCSI_REQUEST_SENSE_SZ;
+    if(USBHSCSIRequestSense(pMSCDevice->ulBulkInPipe, pMSCDevice->ulBulkOutPipe,
+                            pBuffer, &ulSize) != SCSI_CMD_STATUS_PASS)
+    {
+        return(-1);
+    }
+
+    if((pBuffer[SCSI_RS_SKEY] == SCSI_RS_KEY_UNIT_ATTN) &&
+       (pBuffer[SCSI_RS_SKEY_AD_SKEY] == SCSI_RS_KEY_NOTPRSNT))
+    {
+        return(-1);
+    }
+
+    //
+    // Issue a SCSI Inquiry to get basic information on the device
+    //
+    ulSize = SCSI_INQUIRY_DATA_SZ;
+    if((USBHSCSIInquiry(pMSCDevice->ulBulkInPipe, pMSCDevice->ulBulkOutPipe,
+                        pBuffer, &ulSize) != SCSI_CMD_STATUS_PASS))
+    {
+        return(-1);
+    }
+
+    //
+    // Get the size of the drive.
+    //
+    ulSize = SCSI_INQUIRY_DATA_SZ;
+    if(USBHSCSIReadCapacity(pMSCDevice->ulBulkInPipe, pMSCDevice->ulBulkOutPipe,
+                            pBuffer, &ulSize) != SCSI_CMD_STATUS_PASS)
+    {
+        //
+        // Get the current sense data from the device to see why it failed
+        // the Read Capacity command.
+        //
+        ulSize = SCSI_REQUEST_SENSE_SZ;
+        USBHSCSIRequestSense(pMSCDevice->ulBulkInPipe,
+                             pMSCDevice->ulBulkOutPipe, pBuffer, &ulSize);
+        return(-1);
+    }
+    else
+    {
+        //
+        // Read the block size out, value is stored big endian.
+        //
+        pMSCDevice->ulBlockSize =
+            (pBuffer[7] | (pBuffer[6] << 8) | pBuffer[5] << 16 |
+             (pBuffer[4] << 24));
+
+        //
+        // Read the block size out.
+        //
+        pMSCDevice->ulNumBlocks =
+            (pBuffer[3] | (pBuffer[2] << 8) | pBuffer[1] << 16 |
+             (pBuffer[0] << 24));
+    }
+
+    //
+    // See if the drive is ready to use.
+    //
+    if(USBHSCSITestUnitReady(pMSCDevice->ulBulkInPipe,
+                             pMSCDevice->ulBulkOutPipe) != SCSI_CMD_STATUS_PASS)
+    {
+        //
+        // Get the current sense data from the device to see why it failed
+        // the Test Unit Ready command.
+        //
+        ulSize = SCSI_REQUEST_SENSE_SZ;
+        USBHSCSIRequestSense(pMSCDevice->ulBulkInPipe,
+                             pMSCDevice->ulBulkOutPipe, pBuffer, &ulSize);
+        return(-1);
+    }
+
+    //
+    // Success.
+    //
+    return(0);
+}
+
+//*****************************************************************************
+//
+//! This function should be called before any devices are present to enable
+//! the mass storage device class driver.
+//!
+//! \param ulDrive is the drive number to open.
+//! \param pfnCallback is the driver callback for any mass storage events.
+//!
+//! This function is called to open an instance of a mass storage device.  It
+//! should be called before any devices are connected to allow for proper
+//! notification of drive connection and disconnection.  The \e ulDrive
+//! parameter is a zero based index of the drives present in the system.
+//! There are a constant number of drives, and this number should only
+//! be greater than 0 if there is a USB hub present in the system.  The
+//! application should also provide the \e pfnCallback to be notified of mass
+//! storage related events like device enumeration and device removal.
+//!
+//! \return This function will return the driver instance to use for the other
+//! mass storage functions.  If there is no driver available at the time of
+//! this call, this function will return zero.
+//
+//*****************************************************************************
+unsigned long
+USBHMSCDriveOpen(unsigned long ulDrive, tUSBHMSCCallback pfnCallback)
+{
+    //
+    // Only the first drive is supported and only one callback is supported.
+    //
+    if((ulDrive != 0) || (g_USBHMSCDevice.pfnCallback))
+    {
+        return(0);
+    }
+
+    //
+    // Save the callback.
+    //
+    g_USBHMSCDevice.pfnCallback = pfnCallback;
+
+    //
+    // Return the requested device instance.
+    //
+    return((unsigned long)&g_USBHMSCDevice);
+}
+
+//*****************************************************************************
+//
+//! This function should be called to release a drive instance.
+//!
+//! \param ulInstance is the device instance that is to be released.
+//!
+//! This function is called when an MSC drive is to be released in preparation
+//! for shutdown or a switch to USB device mode, for example.  Following this
+//! call, the drive is available for other clients who may open it again using
+//! a call to USBHMSCDriveOpen().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHMSCDriveClose(unsigned long ulInstance)
+{
+    tUSBHMSCInstance *pMSCDevice;
+
+    //
+    // Get a pointer to the device instance data from the handle.
+    //
+    pMSCDevice = (tUSBHMSCInstance *)ulInstance;
+
+    //
+    // Close the drive (if it is already open)
+    //
+    USBHMSCClose((void *)pMSCDevice);
+
+    //
+    // Clear the callback indicating that the device is now closed.
+    //
+    pMSCDevice->pfnCallback = 0;
+}
+
+//*****************************************************************************
+//
+//! This function performs a block read to an MSC device.
+//!
+//! \param ulInstance is the device instance to use for this read.
+//! \param ulLBA is the logical block address to read on the device.
+//! \param pucData is a pointer to the returned data buffer.
+//! \param ulNumBlocks is the number of blocks to read from the device.
+//!
+//! This function will perform a block sized read from the device associated
+//! with the \e ulInstance parameter.  The \e ulLBA parameter specifies the
+//! logical block address to read on the device.  This function will only
+//! perform \e ulNumBlocks block sized reads.  In most cases this is a read
+//! of 512 bytes of data.  The \e *pucData buffer should be at least
+//! \e ulNumBlocks * 512 bytes in size.
+//!
+//! \return The function returns zero for success and any negative value
+//! indicates a failure.
+//
+//*****************************************************************************
+long
+USBHMSCBlockRead(unsigned long ulInstance, unsigned long ulLBA,
+                 unsigned char *pucData, unsigned long ulNumBlocks)
+{
+    tUSBHMSCInstance *pMSCDevice;
+    unsigned long ulSize;
+
+    //
+    // Get the instance pointer in a more usable form.
+    //
+    pMSCDevice = (tUSBHMSCInstance *)ulInstance;
+
+    //
+    // If there is no device present then return an error.
+    //
+    if(pMSCDevice->pDevice == 0)
+    {
+        return(-1);
+    }
+
+    //
+    // Calculate the actual byte size of the read.
+    //
+    ulSize = pMSCDevice->ulBlockSize * ulNumBlocks;
+
+    //
+    // Perform the SCSI read command.
+    //
+    if(USBHSCSIRead10(pMSCDevice->ulBulkInPipe, pMSCDevice->ulBulkOutPipe,
+                      ulLBA, pucData, &ulSize,
+                      ulNumBlocks) != SCSI_CMD_STATUS_PASS)
+    {
+        return(-1);
+    }
+
+    //
+    // Success.
+    //
+    return(0);
+}
+
+//*****************************************************************************
+//
+//! This function performs a block write to an MSC device.
+//!
+//! \param ulInstance is the device instance to use for this write.
+//! \param ulLBA is the logical block address to write on the device.
+//! \param pucData is a pointer to the data to write out.
+//! \param ulNumBlocks is the number of blocks to write to the device.
+//!
+//! This function will perform a block sized write to the device associated
+//! with the \e ulInstance parameter.  The \e ulLBA parameter specifies the
+//! logical block address to write on the device.  This function will only
+//! perform \e ulNumBlocks block sized writes.  In most cases this is a write
+//! of 512 bytes of data.  The \e *pucData buffer should contain at least
+//! \e ulNumBlocks * 512 bytes in size to prevent unwanted data being written
+//! to the device.
+//!
+//! \return The function returns zero for success and any negative value
+//! indicates a failure.
+//
+//*****************************************************************************
+long
+USBHMSCBlockWrite(unsigned long ulInstance, unsigned long ulLBA,
+                  unsigned char *pucData, unsigned long ulNumBlocks)
+{
+    tUSBHMSCInstance *pMSCDevice;
+    unsigned long ulSize;
+
+    //
+    // Get the instance pointer in a more usable form.
+    //
+    pMSCDevice = (tUSBHMSCInstance *)ulInstance;
+
+    //
+    // If there is no device present then return an error.
+    //
+    if(pMSCDevice->pDevice == 0)
+    {
+        return(-1);
+    }
+
+    //
+    // Calculate the actual byte size of the write.
+    //
+    ulSize = pMSCDevice->ulBlockSize * ulNumBlocks;
+
+    //
+    // Perform the SCSI write command.
+    //
+    if(USBHSCSIWrite10(pMSCDevice->ulBulkInPipe, pMSCDevice->ulBulkOutPipe,
+                       ulLBA, pucData, &ulSize,
+                       ulNumBlocks) != SCSI_CMD_STATUS_PASS)
+    {
+        return(-1);
+    }
+
+    //
+    // Success.
+    //
+    return(0);
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/src/platform/lm3s/usblib/host/usbhmsc.h b/src/platform/lm3s/usblib/host/usbhmsc.h
new file mode 100755
index 00000000..ee0f3082
--- /dev/null
+++ b/src/platform/lm3s/usblib/host/usbhmsc.h
@@ -0,0 +1,95 @@
+//*****************************************************************************
+//
+// usbhmsc.h - Definitions for the USB MSC host driver.
+//
+// Copyright (c) 2008-2011 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 7611 of the Stellaris USB Library.
+//
+//*****************************************************************************
+
+#ifndef __USBHMSC_H__
+#define __USBHMSC_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+//! \addtogroup usblib_host_class
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// These defines are the the events that will be passed in the \e ulEvent
+// parameter of the callback from the driver.
+//
+//*****************************************************************************
+#define MSC_EVENT_OPEN          1
+#define MSC_EVENT_CLOSE         2
+
+//*****************************************************************************
+//
+// The prototype for the USB MSC host driver callback function.
+//
+//*****************************************************************************
+typedef void (*tUSBHMSCCallback)(unsigned long ulInstance,
+                                 unsigned long ulEvent,
+                                 void *pvEventData);
+
+//*****************************************************************************
+//
+// Prototypes for the USB MSC host driver APIs.
+//
+//*****************************************************************************
+extern unsigned long USBHMSCDriveOpen(unsigned long ulDrive,
+                                      tUSBHMSCCallback pfnCallback);
+extern void USBHMSCDriveClose(unsigned long ulInstance);
+extern long USBHMSCDriveReady(unsigned long ulInstance);
+extern long USBHMSCBlockRead(unsigned long ulInstance, unsigned long ulLBA,
+                             unsigned char *pucData,
+                             unsigned long ulNumBlocks);
+extern long USBHMSCBlockWrite(unsigned long ulInstance, unsigned long ulLBA,
+                              unsigned char *pucData,
+                              unsigned long ulNumBlocks);
+
+//*****************************************************************************
+//
+//! @}
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __USBHMSC_H__
diff --git a/src/platform/lm3s/usblib/host/usbhost.h b/src/platform/lm3s/usblib/host/usbhost.h
new file mode 100755
index 00000000..deca7919
--- /dev/null
+++ b/src/platform/lm3s/usblib/host/usbhost.h
@@ -0,0 +1,312 @@
+//*****************************************************************************
+//
+// usbhost.h - Host specific definitions for the USB host library.
+//
+// Copyright (c) 2008-2011 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 7611 of the Stellaris USB Library.
+//
+//*****************************************************************************
+
+#ifndef __USBHOST_H__
+#define __USBHOST_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+//! \addtogroup usblib_hcd
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// This is the type used to identify what the pipe is currently in use for.
+//
+//*****************************************************************************
+#define USBHCD_PIPE_UNUSED          0x00100000
+#define USBHCD_PIPE_CONTROL         0x00130000
+#define USBHCD_PIPE_BULK_OUT        0x00210000
+#define USBHCD_PIPE_BULK_IN         0x00220000
+#define USBHCD_PIPE_INTR_OUT        0x00410000
+#define USBHCD_PIPE_INTR_IN         0x00420000
+#define USBHCD_PIPE_ISOC_OUT        0x00810000
+#define USBHCD_PIPE_ISOC_IN         0x00820000
+#define USBHCD_PIPE_ISOC_OUT_DMA    0x01810000
+#define USBHCD_PIPE_ISOC_IN_DMA     0x01820000
+#define USBHCD_PIPE_BULK_OUT_DMA    0x01210000
+#define USBHCD_PIPE_BULK_IN_DMA     0x01220000
+
+
+//*****************************************************************************
+//
+// These are the defines that are used with USBHCDPowerConfigInit().
+//
+//*****************************************************************************
+#define USBHCD_FAULT_LOW        0x00000010
+#define USBHCD_FAULT_HIGH       0x00000030
+#define USBHCD_FAULT_VBUS_NONE  0x00000000
+#define USBHCD_FAULT_VBUS_TRI   0x00000140
+#define USBHCD_FAULT_VBUS_DIS   0x00000400
+#define USBHCD_VBUS_MANUAL      0x00000004
+#define USBHCD_VBUS_AUTO_LOW    0x00000002
+#define USBHCD_VBUS_AUTO_HIGH   0x00000003
+#define USBHCD_VBUS_FILTER      0x00010000
+
+//*****************************************************************************
+//
+//! This macro is used to declare an instance of an Event driver for the USB
+//! library.
+//!
+//! \param VarName is the name of the variable.
+//! \param pfnOpen is the callback for the Open call to this driver.  This
+//! value is currently reserved and should be set to 0.
+//! \param pfnClose is the callback for the Close call to this driver.  This
+//! value is currently reserved and should be set to 0.
+//! \param pfnEvent is the callback that will be called for various USB events.
+//!
+//! The first parameter is the actual name of the variable that will
+//! be declared by this macro.  The second and third parameter are reserved
+//! for future functionality and are unused and should be set to zero.  The
+//! last parameter is the actual callback function and is specified as
+//! a function pointer of the type:
+//!
+//! void (*pfnEvent)(void *pvData);
+//!
+//! When the \e pfnEvent function is called the void pointer that is passed in
+//! as a parameter should be cast to a pointer to a structure of type
+//! tEventInfo.  This will contain the event that caused the pfnEvent function
+//! to be called.
+//
+//*****************************************************************************
+#define DECLARE_EVENT_DRIVER(VarName, pfnOpen, pfnClose, pfnEvent)          \
+void IntFn(void *pvData);                                                   \
+const tUSBHostClassDriver VarName =                                         \
+{                                                                           \
+    USB_CLASS_EVENTS,                                                       \
+    0,                                                                      \
+    0,                                                                      \
+    pfnEvent                                                                \
+}
+
+//*****************************************************************************
+//
+//! This structure is used to return generic event based information to an
+//! application.  The following events are currently supported:
+//! USB_EVENT_CONNECTED, USB_EVENT_DISCONNECTED, and USB_EVENT_POWER_FAULT.
+//
+//*****************************************************************************
+typedef struct
+{
+    unsigned long ulEvent;
+
+    unsigned long ulInstance;
+}
+tEventInfo;
+
+//*****************************************************************************
+//
+// This is the type definition a call back for events on USB Pipes allocated
+// by USBHCDPipeAlloc().
+//
+// \param ulPipe is well the pipe
+// \param ulEvent is well the event
+//
+// longer def thand may need more text in order to be recogized what should
+// this really say about ourselves.
+//
+// \return None.
+//
+//*****************************************************************************
+typedef void (* tHCDPipeCallback)(unsigned long ulPipe,
+                                  unsigned long ulEvent);
+
+//*****************************************************************************
+//
+//! This is the structure that holds all of the information for devices
+//! that are enumerated in the system.   It is passed in to Open function of
+//! USB host class drivers so that they can allocate any endpoints and parse
+//! out other information that the device class needs to complete enumeration.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! The current device address for this device.
+    //
+    unsigned long ulAddress;
+
+    //
+    //! The current interface for this device.
+    //
+    unsigned long ulInterface;
+
+    //
+    //! A pointer to the device descriptor for this device.
+    //
+    tDeviceDescriptor DeviceDescriptor;
+
+    //
+    //! A pointer to the configuration descriptor for this device.
+    //
+    tConfigDescriptor *pConfigDescriptor;
+
+    //
+    //! The size of the buffer allocated to pConfigDescriptor.
+    //
+    unsigned long ulConfigDescriptorSize;
+}
+tUSBHostDevice;
+
+//*****************************************************************************
+//
+//! This structure defines a USB host class driver interface, it is parsed to
+//! find a USB class driver once a USB device is enumerated.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! The interface class that this device class driver supports.
+    //
+    unsigned long ulInterfaceClass;
+
+    //
+    //! The function is called when this class of device has been detected.
+    //
+    void * (*pfnOpen)(tUSBHostDevice *pDevice);
+
+    //
+    //! The function is called when the device, originally opened with a call
+    //! to the pfnOpen function, is disconnected.
+    //
+    void (*pfnClose)(void *pvInstance);
+
+    //
+    //! This is the optional interrupt handler that will be called when an
+    //! endpoint associated with this device instance generates an interrupt.
+    //
+    void (*pfnIntHandler)(void *pvInstance);
+}
+tUSBHostClassDriver;
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// If the g_USBEventDriver is included in the host controller driver list then
+// this function must be provided by the application.
+//
+//*****************************************************************************
+void USBHCDEvents(void *pvData);
+
+//*****************************************************************************
+//
+// Prototypes for the USB Host controller APIs.
+//
+//*****************************************************************************
+extern void USBHCDMain(void);
+extern void USBHCDInit(unsigned long ulIndex, void *pData,
+                       unsigned long ulSize);
+extern void USBHCDPowerConfigInit(unsigned long ulIndex,
+                                  unsigned long ulFlags);
+extern unsigned long USBHCDPowerConfigGet(unsigned long ulIndex);
+extern unsigned long USBHCDPowerConfigSet(unsigned long ulIndex,
+                                          unsigned long ulConfig);
+extern unsigned long USBHCDPowerAutomatic(unsigned long ulIndex);
+extern void
+       USBHCDRegisterDrivers(unsigned long ulIndex,
+                             const tUSBHostClassDriver * const *ppHClassDrvrs,
+                             unsigned long ulNumDrivers);
+extern void USBHCDTerm(unsigned long ulIndex);
+extern void USBHCDSetConfig(unsigned long ulIndex, unsigned long ulDevice,
+                            unsigned long ulConfiguration);
+extern void USBHCDSetInterface(unsigned long ulIndex, unsigned long ulDevice,
+                               unsigned long ulInterface,
+                               unsigned ulAltSetting);
+
+extern void USBHCDSuspend(unsigned long ulIndex);
+extern void USBHCDResume(unsigned long ulIndex);
+extern void USBHCDReset(unsigned long ulIndex);
+extern void USBHCDPipeFree(unsigned long ulPipe);
+extern unsigned long USBHCDPipeAlloc(unsigned long ulIndex,
+                                     unsigned long ulEndpointType,
+                                     unsigned long ulDevAddr,
+                                     tHCDPipeCallback pCallback);
+extern unsigned long USBHCDPipeAllocSize(unsigned long ulIndex,
+                                     unsigned long ulEndpointType,
+                                     unsigned long ulDevAddr,
+                                     unsigned long ulFIFOSize,
+                                     tHCDPipeCallback pCallback);
+extern unsigned long USBHCDPipeConfig(unsigned long ulPipe,
+                                      unsigned long ulMaxPayload,
+                                      unsigned long ulInterval,
+                                      unsigned long ulTargetEndpoint);
+extern unsigned long USBHCDPipeStatus(unsigned long ulPipe);
+extern unsigned long USBHCDPipeWrite(unsigned long ulPipe,
+                                     unsigned char *pData,
+                                     unsigned long ulSize);
+extern unsigned long USBHCDPipeRead(unsigned long ulPipe, unsigned char *pData,
+                                    unsigned long ulSize);
+extern unsigned long USBHCDPipeSchedule(unsigned long ulPipe,
+                                        unsigned char *pucData,
+                                        unsigned long ulSize);
+extern unsigned long USBHCDPipeReadNonBlocking(unsigned long ulPipe,
+                                               unsigned char *pucData,
+                                               unsigned long ulSize);
+extern unsigned long USBHCDControlTransfer(unsigned long ulIndex,
+                                           tUSBRequest *pSetupPacket,
+                                           unsigned long ulAddress,
+                                           unsigned char *pData,
+                                           unsigned long ulSize,
+                                           unsigned long ulMaxPacketSize);
+extern void USB0HostIntHandler(void);
+
+//*****************************************************************************
+//
+// The host class drivers supported by the USB library.
+//
+//*****************************************************************************
+extern const tUSBHostClassDriver g_USBHostMSCClassDriver;
+extern const tUSBHostClassDriver g_USBHIDClassDriver;
+extern const tUSBHostClassDriver g_USBHostAudioClassDriver;
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __USBHOST_H__
diff --git a/src/platform/lm3s/usblib/host/usbhostenum.c b/src/platform/lm3s/usblib/host/usbhostenum.c
new file mode 100755
index 00000000..4eddc2ea
--- /dev/null
+++ b/src/platform/lm3s/usblib/host/usbhostenum.c
@@ -0,0 +1,4500 @@
+//*****************************************************************************
+//
+// usbhostenum.c - Device enumeration code for the USB host library.
+//
+// Copyright (c) 2008-2011 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 7611 of the Stellaris USB Library.
+//
+//*****************************************************************************
+
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_sysctl.h"
+#include "inc/hw_types.h"
+#include "driverlib/rom.h"
+#include "driverlib/rom_map.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+#include "driverlib/sysctl.h"
+#include "driverlib/udma.h"
+#include "driverlib/usb.h"
+#include "usblib/usblib.h"
+#include "usblib/usblibpriv.h"
+#include "usblib/host/usbhost.h"
+
+//*****************************************************************************
+//
+//! \addtogroup usblib_hcd
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// External prototypes.
+//
+//*****************************************************************************
+extern tUSBMode g_eUSBMode;
+
+extern void OTGDeviceDisconnect(unsigned long ulIndex);
+
+//*****************************************************************************
+//
+// Internal function prototypes.
+//
+//*****************************************************************************
+static void USBHCDEP0StateTx(void);
+static void USBHCDEnumHandler(void);
+static void USBHCDClearFeature(unsigned long ulDevAddress,
+                               unsigned long ulEndpoint,
+                               unsigned long ulFeature);
+
+//*****************************************************************************
+//
+// Automatic power enable.
+//
+//*****************************************************************************
+#define USB_HOST_PWREN_AUTO     0x00000002
+
+//*****************************************************************************
+//
+// Flags used to signal between the interrupt handler and USBHCDMain().
+//
+//*****************************************************************************
+#define INT_EVENT_VBUS_ERR      0x01
+#define INT_EVENT_CONNECT       0x02
+#define INT_EVENT_DISCONNECT    0x04
+#define INT_EVENT_POWER_FAULT   0x08
+
+volatile unsigned long g_ulUSBHIntEvents;
+
+//*****************************************************************************
+//
+// Flags used to indicate that a uDMA transfer is pending on a pipe.
+//
+//*****************************************************************************
+#define DMA_PEND_TRANSMIT_FLAG  0x10000
+#define DMA_PEND_RECEIVE_FLAG   0x1
+
+volatile unsigned long g_ulDMAPending = 0;
+
+//*****************************************************************************
+//
+// Flag used to indicate that a workaround should be applied when using
+// uDMA with USB.  The uDMA transfers must match the USB FIFO size when
+// with Rev A0 silicon.
+//
+//*****************************************************************************
+static unsigned long g_bUseDMAWA = 0;
+
+//*****************************************************************************
+//
+// This holds the current power configuration that is used when USBHCDInit()
+// is called.
+//
+//*****************************************************************************
+static unsigned long g_ulPowerConfig = USBHCD_VBUS_AUTO_HIGH;
+
+//*****************************************************************************
+//
+// The states for endpoint 0 during enumeration.
+//
+//*****************************************************************************
+typedef enum
+{
+    //
+    // The USB device is waiting on a request from the host controller on
+    // endpoint 0.
+    //
+    EP0_STATE_IDLE,
+
+    //
+    // Setup packet is expecting data IN.
+    //
+    EP0_STATE_SETUP_IN,
+
+    //
+    // Setup packet is sending data OUT.
+    //
+    EP0_STATE_SETUP_OUT,
+
+    //
+    // The USB device is receiving data from the device due to an SETUP IN
+    // request.
+    //
+    EP0_STATE_RX,
+
+    //
+    // The USB device has completed the IN or OUT request and is now waiting
+    // for the host to acknowledge the end of the IN/OUT transaction.  This
+    // is the status phase for a USB control transaction.
+    //
+    EP0_STATE_STATUS,
+
+    //
+    // This state is for when a response only has a status phase and no
+    // data phase.
+    //
+    EP0_STATE_STATUS_IN,
+
+    //
+    // This endpoint has signaled a stall condition and is waiting for the
+    // stall to be acknowledged by the host controller.
+    //
+    EP0_STATE_STALL,
+
+    //
+    // An error has occurred on endpoint 0.
+    //
+    EP0_STATE_ERROR
+}
+tEP0State;
+
+//*****************************************************************************
+//
+// This structure holds the full state for the device enumeration.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    // This is the pointer to the current data being sent out or received
+    // on endpoint 0.
+    //
+    unsigned char *pData;
+
+    //
+    // This is the number of bytes that remain to be sent from or received
+    // into the g_DeviceState.pEP0Data data buffer.
+    //
+    volatile unsigned long ulBytesRemaining;
+
+    //
+    // The amount of data being sent/received due to a request.
+    //
+    unsigned long ulDataSize;
+
+    //
+    // This is the current device address in use by endpoint 0.
+    //
+    unsigned long ulDevAddress;
+
+    //
+    // The maximum packet size for the device responding to the setup packet.
+    //
+    unsigned long ulMaxPacketSize;
+
+    //
+    // The host controller's state.
+    //
+    tEP0State eState;
+}
+tHostState;
+
+//*****************************************************************************
+//
+// This variable holds the current state of endpoint 0.
+//
+//*****************************************************************************
+static volatile tHostState g_sUSBHEP0State =
+{
+    0,                          // pData
+    0,                          // ulBytesRemaining
+    0,                          // ulDataSize
+    0,                          // ulDevAddress
+    0,                          // ulMaxPacketSize
+    EP0_STATE_IDLE              // eState
+};
+
+//*****************************************************************************
+//
+// The global delay time for use by SysCtlDelay() function.  This is
+// initialized to an appropriate value for a 50MHz clock.  The correct value
+// will be set in USBHCDInit().
+//
+//*****************************************************************************
+static unsigned long g_ulTickms = (50000000 / 3000);
+static volatile unsigned long g_ulCurrentTick = 0;
+
+//*****************************************************************************
+//
+// The current active driver.
+//
+//*****************************************************************************
+static long g_lUSBHActiveDriver = -1;
+static void *g_pvDriverInstance = 0;
+
+//*****************************************************************************
+//
+// This is the structure used to hold the information for a given USB pipe
+// that is attached to a device.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    // The current address for this pipe.
+    //
+    unsigned long ulDevAddr;
+
+    //
+    // The current address for this pipe.
+    //
+    unsigned char ucEPNumber;
+
+    //
+    // The DMA channel assigned to this endpoint.
+    //
+    unsigned char ucDMAChannel;
+
+    //
+    // The current type for this pipe.
+    //
+    unsigned long ulType;
+
+    //
+    // The millisecond interval for this pipe.
+    //
+    unsigned long ulInterval;
+
+    //
+    // The next tick value to trigger and event on this pipe.
+    //
+    unsigned long ulNextEventTick;
+
+    //
+    // The current call back for this pipe.
+    //
+    tHCDPipeCallback pfnCallback;
+
+    //
+    // The state of a given USB pipe.
+    //
+    volatile enum
+    {
+        PIPE_READING,
+        PIPE_DATA_READY,
+        PIPE_DATA_SENT,
+        PIPE_WRITING,
+        PIPE_STALLED,
+        PIPE_ERROR,
+        PIPE_IDLE,
+        PIPE_DISABLED
+    }
+    eState;
+
+    //
+    // The actual FIFO offset allocated to this endpoint.
+    //
+    unsigned short usFIFOAddr;
+
+    //
+    // The size of the FIFO entry based on the size parameter.  These are
+    // equivalent to the USB_FIFO_SZ_* values in usb.h.
+    //
+    unsigned char ucFIFOSize;
+
+    //
+    // The bit offset in the allocation structure.
+    //
+    unsigned char ucFIFOBitOffset;
+}
+tUSBHCDPipe;
+
+//*****************************************************************************
+//
+// The internal state of the device.
+//
+//*****************************************************************************
+typedef enum
+{
+    HCD_DEV_DISCONNECTED,
+    HCD_DEV_CONNECTED,
+    HCD_DEV_REQUEST,
+    HCD_DEV_RESET,
+    HCD_DEV_ADDRESSED,
+    HCD_DEV_CONFIGURED,
+    HCD_DEV_GETSTRINGS,
+    HCD_DEV_ERROR,
+    HCD_VBUS_ERROR,
+    HCD_POWER_FAULT,
+    HCD_IDLE
+}
+tUSBHDeviceState;
+
+//*****************************************************************************
+//
+// This is a fixed number as it relates to the maximum number of USB pipes
+// available on any USB controller.  The actual number on a given device may
+// be less than this number.
+//
+//*****************************************************************************
+#define MAX_NUM_PIPES           15
+
+//*****************************************************************************
+//
+// This is a fixed number as it relates to the number of USB pipes available
+// in the USB controller.
+//
+//*****************************************************************************
+#define MAX_NUM_DMA_CHANNELS    6
+
+//*****************************************************************************
+//
+// Marker for an unused DMA channel slot.
+//
+//*****************************************************************************
+#define USBHCD_DMA_UNUSED       0xff
+
+//*****************************************************************************
+//
+// These definitions are used to manipulate the values returned as allocated
+// USB pipes.
+//
+//*****************************************************************************
+#define EP_PIPE_USE_UDMA        0x01000000
+#define EP_PIPE_TYPE_ISOC       0x00800000
+#define EP_PIPE_TYPE_INTR       0x00400000
+#define EP_PIPE_TYPE_BULK       0x00200000
+#define EP_PIPE_TYPE_CONTROL    0x00100000
+#define EP_PIPE_TYPE_IN         0x00020000
+#define EP_PIPE_TYPE_OUT        0x00010000
+#define EP_PIPE_IDX_M           0x0000ffff
+
+//*****************************************************************************
+//
+// This creates a USB pipe handle from an index.
+//
+//*****************************************************************************
+#define OUT_PIPE_HANDLE(ulIdx)  (g_sUSBHCD.USBOUTPipes[ulIdx].ulType | ulIdx)
+#define IN_PIPE_HANDLE(ulIdx)   (g_sUSBHCD.USBINPipes[ulIdx].ulType | ulIdx)
+
+//*****************************************************************************
+//
+// Converts from an endpoint specifier to the offset of the endpoint's
+// control/status registers.
+//
+//*****************************************************************************
+#define EP_OFFSET(Endpoint)     (Endpoint - 0x10)
+
+//*****************************************************************************
+//
+// This structure holds the state information for a given host controller.
+//
+//*****************************************************************************
+typedef struct
+{
+    unsigned long ulUSBBase;
+
+    tUSBHCDPipe USBControlPipe;
+    tUSBHCDPipe USBOUTPipes[MAX_NUM_PIPES];
+    tUSBHCDPipe USBINPipes[MAX_NUM_PIPES];
+    unsigned char ucDMAChannels[MAX_NUM_DMA_CHANNELS];
+
+    //
+    // Each devices state.
+    //
+    tUSBHostDevice USBDevice[1];
+
+    //
+    // Holds the current state of the device.
+    //
+    volatile tUSBHDeviceState eDeviceState[1];
+
+    //
+    // Pointer to the memory pool for this controller.
+    //
+    void *pvPool;
+
+    //
+    // The pool size for this controller.
+    //
+    unsigned long ulPoolSize;
+
+    //
+    // The class drivers for this controller.
+    //
+    const tUSBHostClassDriver * const *pClassDrivers;
+
+    //
+    // The number of class drivers.
+    //
+    unsigned long ulNumClassDrivers;
+
+    //
+    // This is the index in the driver list of the event driver.
+    //
+    long lEventDriver;
+
+    //
+    // This is the generic event information used by the event driver.
+    //
+    tEventInfo EventInfo;
+
+    unsigned long ulClass;
+}
+tUSBHCD;
+
+//*****************************************************************************
+//
+// The global to hold all of the state information for a given host controller.
+//
+//*****************************************************************************
+static tUSBHCD g_sUSBHCD;
+
+//*****************************************************************************
+//
+// If there is an event driver this function will send out a generic connection
+// event USB_EVENT_CONNECTED indicating that an unknown connection event has
+// occurred.
+//
+//*****************************************************************************
+static void
+SendUnknownConnect(unsigned long ulClass, unsigned long ulInstance)
+{
+    if((g_sUSBHCD.lEventDriver != -1) &&
+       (g_sUSBHCD.pClassDrivers[g_sUSBHCD.lEventDriver]->pfnIntHandler))
+    {
+        //
+        // Send the generic connected event.
+        //
+        g_sUSBHCD.EventInfo.ulEvent = USB_EVENT_CONNECTED;
+
+        //
+        // Save the class for later incase and application needs it.
+        //
+        g_sUSBHCD.ulClass = ulClass;
+        g_sUSBHCD.EventInfo.ulInstance = ulInstance;
+
+        g_sUSBHCD.pClassDrivers[g_sUSBHCD.lEventDriver]->pfnIntHandler(
+           &g_sUSBHCD.EventInfo);
+    }
+}
+
+//*****************************************************************************
+//
+// Internal memory allocation space is two unsigned long values where each
+// bit represents a 64 byte block in the FIFO.  This requires 64 bits for
+// the 4096 bytes of FIFO available.
+//
+//*****************************************************************************
+static unsigned long g_ulAlloc[2];
+
+//*****************************************************************************
+//
+// This function handles freeing FIFO memory that has been allocated using the
+// FIFOAlloc() function.
+//
+//*****************************************************************************
+static void
+FIFOFree(tUSBHCDPipe *pUSBPipe)
+{
+    unsigned long ulMask;
+
+    //
+    // Calculate the mask value to use to clear off the allocated blocks used
+    // by the USB pipe specified by pUSBPipe.
+    //
+    ulMask = (1 << (pUSBPipe->ucFIFOSize - 2)) - 1;
+    ulMask = ulMask << pUSBPipe->ucFIFOBitOffset;
+
+    //
+    // Determine which 32 bit word to access based on the size.
+    //
+    if(pUSBPipe->ucFIFOSize > USB_FIFO_SZ_64)
+    {
+        //
+        // If the FIFO size is greater than 64 then use the upper 32 bits.
+        //
+        g_ulAlloc[1] &= ~ulMask;
+    }
+    else
+    {
+        //
+        // If the FIFO size is less than or equal to 64 then use the lower
+        // 32 bits.
+        //
+        g_ulAlloc[0] &= ~ulMask;
+    }
+}
+
+//*****************************************************************************
+//
+// This function is used to allocate FIFO memory to a given USB pipe.
+//
+// \param pUSBPipe is the USB pipe that needs FIFO memory allocated.
+// \param ulSize is the minimum size in bytes of the FIFO to allocate.
+//
+// This function will allocate \e ulSize bytes to the USB pipe in the
+// \e pUSBPipe parameter.  The function will fill the pUSBPipe structure
+// members ucFIFOSize and ucFIFOAddr with values that can be used with the
+// USBFIFOConfigSet() API.  This allocation uses a first fit algorithm.
+//
+// \return This function returns the size of the block allocated.
+//
+//*****************************************************************************
+static unsigned long
+FIFOAlloc(tUSBHCDPipe *pUSBPipe, unsigned long ulSize)
+{
+    unsigned long ulBlocks, ulStart, ulBlockSize;
+    unsigned short usFIFOAddr;
+    unsigned long ulTemp, ulIndex;
+
+    //
+    // Save which 32 bit value to access, the upper is for blocks greater
+    // than 64 and the lower is for block 64 or less.
+    //
+    if(ulSize > 64)
+    {
+        ulIndex = 1;
+    }
+    else
+    {
+        ulIndex = 0;
+    }
+
+    //
+    // Initial FIFO address is 0.
+    //
+    usFIFOAddr = 0;
+
+    //
+    // Initialize the bit pattern and bit location.
+    //
+    ulBlocks = 1;
+    ulStart = 0;
+
+    //
+    // The initial block size is always the minimum size of 64 bytes.
+    //
+    ulBlockSize = 64;
+
+    //
+    // The initial size and offset are 64 and 0.
+    //
+    pUSBPipe->ucFIFOBitOffset = 0;
+    pUSBPipe->ucFIFOSize = 3;
+
+    //
+    // Scan through 32 bits looking for a memory block large enough to fill
+    // the request.
+    //
+    while(usFIFOAddr <= 32)
+    {
+        //
+        // If the pattern is zero then it is a possible match.
+        //
+        if((g_ulAlloc[ulIndex] & ulBlocks) == 0)
+        {
+            //
+            // If the size is large enough then save it and break out of the
+            // loop.
+            //
+            if(ulBlockSize >= ulSize)
+            {
+                //
+                // Mark the memory as allocated.
+                //
+                g_ulAlloc[ulIndex] |= ulBlocks;
+
+                break;
+            }
+
+            //
+            // Increment the size of the FIFO block.
+            //
+            pUSBPipe->ucFIFOSize++;
+
+            //
+            // Add in a new bit to the size of the allocation.
+            //
+            ulBlocks = ulBlocks | (ulBlocks << 1) ;
+
+            //
+            // Double the current size.
+            //
+            ulBlockSize <<= 1;
+
+        }
+        else
+        {
+            //
+            // Need to start over looking because the last allocation match
+            // failed, so reset the bit offset to the current location and the
+            // size to 64 bytes.
+            //
+            pUSBPipe->ucFIFOBitOffset = usFIFOAddr;
+            pUSBPipe->ucFIFOSize = 3;
+
+            //
+            // Reset the block size to the minimum (64 bytes).
+            //
+            ulBlockSize = 64;
+
+            //
+            // Store the current starting bit location and set the block mask
+            // to this value.
+            //
+            ulStart = 1 << usFIFOAddr;
+            ulBlocks = ulStart;
+        }
+
+        //
+        // Increase the address of the FIFO offset.
+        //
+        usFIFOAddr++;
+    }
+
+    //
+    // If there was no block large enough then fail this call.
+    //
+    if(usFIFOAddr > 32)
+    {
+        ulBlockSize = 0;
+        pUSBPipe->usFIFOAddr = 0;
+        pUSBPipe->ucFIFOBitOffset = 0;
+        pUSBPipe->ucFIFOSize = 0;
+    }
+    else
+    {
+        //
+        // Calculate the offset in the FIFO.
+        //
+        ulTemp = pUSBPipe->ucFIFOBitOffset * 64;
+
+        //
+        // Sizes greater than 64 are allocated in the second half of the FIFO
+        // memory space.
+        //
+        if(ulSize > 64)
+        {
+            ulTemp += 2048;
+        }
+
+        //
+        // Convert this to the value that can be set in the USB controller.
+        //
+        pUSBPipe->usFIFOAddr = (unsigned short)ulTemp;
+    }
+    return(ulBlockSize);
+}
+
+//*****************************************************************************
+//
+//! This function is used to allocate a USB HCD pipe.
+//!
+//! \param ulIndex specifies which USB controller to use.
+//! \param ulEndpointType is the type of endpoint that this pipe will be
+//! communicating with.
+//! \param ulDevAddr is the device address to use for this endpoint.
+//! \param ulSize is the size of the FIFO in bytes.
+//! \param pfnCallback is the function that will be called when events occur on
+//! this USB Pipe.
+//!
+//! Since there are a limited number of USB HCD pipes that can be used in the
+//! host controller, this function is used to temporarily or permanently
+//! acquire one of the endpoints.  Unlike the USBHCDPipeAlloc() function this
+//! function allows the caller to specify the size of the FIFO allocated to
+//! this endpoint in the \e ulSize parameter.  This function also provides a
+//! method to register a callback for status changes on this endpoint.  If no
+//! callbacks are desired then the \e pfnCallback function should be set to 0.
+//! The callback should be used when using the USBHCDPipeSchedule() function
+//! so that the caller is notified when the action is complete.
+//!
+//! \return This function returns a value indicating which pipe was reserved.
+//! If the value is 0 then there were no pipes currently available.  This value
+//! should be passed to any USBHCDPipe APIs to indicate which pipe is being
+//! accessed.
+//
+//*****************************************************************************
+unsigned long
+USBHCDPipeAllocSize(unsigned long ulIndex, unsigned long ulEndpointType,
+                    unsigned long ulDevAddr, unsigned long ulSize,
+                    tHCDPipeCallback pfnCallback)
+{
+    long lIdx, lDMAIdx;
+
+    ASSERT(ulIndex == 0);
+
+    //
+    // Find a USB pipe that is free.
+    //
+    for(lIdx = 0; lIdx < MAX_NUM_PIPES; lIdx++)
+    {
+        //
+        // Handle OUT Pipes.
+        //
+        if(ulEndpointType & EP_PIPE_TYPE_OUT)
+        {
+            //
+            // A zero address indicates free.
+            //
+            if(g_sUSBHCD.USBOUTPipes[lIdx].ulDevAddr == 0)
+            {
+                //
+                // Set up uDMA for the pipe.
+                //
+                if(ulEndpointType & EP_PIPE_USE_UDMA)
+                {
+                    //
+                    // First three endpoints have fixed channels on some
+                    // parts so bias the pipes to match this as best is
+                    // possible.
+                    //
+                    if(lIdx < 3)
+                    {
+                        //
+                        // Check if the fixed channel is available for this
+                        // USB pipe.
+                        //
+                        if((g_sUSBHCD.ucDMAChannels[1 + (lIdx * 2)] ==
+                                      USBHCD_DMA_UNUSED))
+                        {
+                            //
+                            // The default channel was available so use it.
+                            //
+                            g_sUSBHCD.ucDMAChannels[1 + (lIdx * 2)] = lIdx;
+                            g_sUSBHCD.USBOUTPipes[lIdx].ucDMAChannel =
+                                1 + (lIdx * 2);
+                        }
+                        else
+                        {
+                            //
+                            // Go to the next USB pipe if the fixed one was not
+                            // available.
+                            //
+                            continue;
+                        }
+                    }
+                    else
+                    {
+                        //
+                        // Either the fixed channel was not available or the
+                        // pipe index was more than the first 3 pipes that are
+                        // available on all parts.
+                        //
+                        for(lDMAIdx = 1; lDMAIdx < MAX_NUM_DMA_CHANNELS;
+                            lDMAIdx += 2)
+                        {
+                            //
+                            // Find any available channel.
+                            //
+                            if(g_sUSBHCD.ucDMAChannels[lDMAIdx] ==
+                               USBHCD_DMA_UNUSED)
+                            {
+                                //
+                                // Save the index and the DMA channel
+                                // information.
+                                //
+                                g_sUSBHCD.ucDMAChannels[lDMAIdx] = lIdx;
+                                g_sUSBHCD.USBOUTPipes[lIdx].ucDMAChannel =
+                                    lDMAIdx;
+                            }
+                        }
+                    }
+
+                    //
+                    // If no DMA channel was available then just disable DMA
+                    // on this pipe.
+                    //
+                    if(g_sUSBHCD.USBOUTPipes[lIdx].ucDMAChannel ==
+                       USBHCD_DMA_UNUSED)
+                    {
+                        ulEndpointType &= ~EP_PIPE_USE_UDMA;
+                    }
+                    else
+                    {
+                        //
+                        // Set the DMA channel for this endpoint, this has no
+                        // effect on parts without configurable DMA.
+                        //
+                        MAP_USBEndpointDMAChannel(
+                            USB0_BASE, INDEX_TO_USB_EP(lIdx + 1),
+                            g_sUSBHCD.USBOUTPipes[lIdx].ucDMAChannel);
+
+                        //
+                        // Clear all the attributes for the channel
+                        //
+                        MAP_uDMAChannelAttributeDisable(
+                            g_sUSBHCD.USBOUTPipes[lIdx].ucDMAChannel,
+                            UDMA_ATTR_ALL);
+
+                        //
+                        // Configure the uDMA channel for the pipe
+                        //
+                        MAP_uDMAChannelControlSet(
+                            g_sUSBHCD.USBOUTPipes[lIdx].ucDMAChannel,
+                            (UDMA_SIZE_8 | UDMA_SRC_INC_8 | UDMA_DST_INC_NONE |
+                             UDMA_ARB_64));
+                    }
+                }
+
+                //
+                // Save the endpoint type and device address and callback
+                // function.
+                //
+                g_sUSBHCD.USBOUTPipes[lIdx].ulType = ulEndpointType;
+                g_sUSBHCD.USBOUTPipes[lIdx].ulDevAddr = ulDevAddr;
+                g_sUSBHCD.USBOUTPipes[lIdx].pfnCallback = pfnCallback;
+
+                //
+                // Clear out any pending status on this endpoint in case it
+                // was in use before a allowing a new device class to use it.
+                //
+                MAP_USBHostEndpointStatusClear(USB0_BASE,
+                                               INDEX_TO_USB_EP(lIdx + 1),
+                                               USB_HOST_OUT_STATUS);
+
+                //
+                // Initialize the endpoint as idle.
+                //
+                g_sUSBHCD.USBOUTPipes[lIdx].eState = PIPE_IDLE;
+
+                //
+                // Allocate space in the FIFO for this endpoint.
+                //
+                if(FIFOAlloc(&g_sUSBHCD.USBOUTPipes[lIdx], ulSize) != 0)
+                {
+                    //
+                    // Configure the FIFO.
+                    //
+                    MAP_USBFIFOConfigSet(USB0_BASE, INDEX_TO_USB_EP(lIdx + 1),
+                                         g_sUSBHCD.USBOUTPipes[lIdx].usFIFOAddr,
+                                         g_sUSBHCD.USBOUTPipes[lIdx].ucFIFOSize,
+                                         USB_EP_HOST_OUT);
+                }
+
+                //
+                // Set the function address for this endpoint.
+                //
+                MAP_USBHostAddrSet(USB0_BASE, INDEX_TO_USB_EP(lIdx + 1),
+                                   ulDevAddr, USB_EP_HOST_OUT);
+
+                break;
+            }
+        }
+        //
+        // Handle IN Pipes.
+        //
+        else if(ulEndpointType & EP_PIPE_TYPE_IN)
+        {
+            //
+            // A zero address indicates free.
+            //
+            if(g_sUSBHCD.USBINPipes[lIdx].ulDevAddr == 0)
+            {
+                //
+                // Set up uDMA for the pipe.
+                //
+                if(ulEndpointType & EP_PIPE_USE_UDMA)
+                {
+                    //
+                    // First three endpoints have fixed channels on some
+                    // parts so bias the pipes to match this as best is
+                    // possible.
+                    //
+                    if(lIdx < 3)
+                    {
+                        //
+                        // Check if the fixed channel is available for this
+                        // USB pipe.
+                        //
+                        if(g_sUSBHCD.ucDMAChannels[lIdx * 2] ==
+                           USBHCD_DMA_UNUSED)
+                        {
+                            //
+                            // The default channel was available so use it.
+                            //
+                            g_sUSBHCD.ucDMAChannels[lIdx * 2] = lIdx;
+                            g_sUSBHCD.USBINPipes[lIdx].ucDMAChannel = lIdx * 2;
+                        }
+                        else
+                        {
+                            //
+                            // Go to the next USB pipe if the fixed one was not
+                            // available.
+                            //
+                            continue;
+                        }
+                    }
+                    else
+                    {
+                        //
+                        // Either the fixed channel was not available or the
+                        // pipe index was more than the first 3 pipes that are
+                        // available on all parts.
+                        //
+                        for(lDMAIdx = 0; lDMAIdx < MAX_NUM_DMA_CHANNELS;
+                            lDMAIdx += 2)
+                        {
+                            //
+                            // Find any available channel.
+                            //
+                            if(g_sUSBHCD.ucDMAChannels[lDMAIdx] ==
+                               USBHCD_DMA_UNUSED)
+                            {
+                                //
+                                // Save the index and the DMA channel
+                                // information.
+                                //
+                                g_sUSBHCD.ucDMAChannels[lDMAIdx] = lIdx;
+                                g_sUSBHCD.USBINPipes[lIdx].ucDMAChannel =
+                                    lDMAIdx;
+                            }
+                        }
+                    }
+
+                    //
+                    // If no DMA channel was available then just disable DMA
+                    // on this pipe.
+                    //
+                    if(g_sUSBHCD.USBINPipes[lIdx].ucDMAChannel ==
+                       USBHCD_DMA_UNUSED)
+                    {
+                        ulEndpointType &= ~EP_PIPE_USE_UDMA;
+                    }
+                    else
+                    {
+                        //
+                        // Set the DMA channel for this endpoint, this has no
+                        // effect on parts without configurable DMA.
+                        //
+                        //
+                        MAP_USBEndpointDMAChannel(
+                            USB0_BASE, INDEX_TO_USB_EP(lIdx + 1),
+                            g_sUSBHCD.USBINPipes[lIdx].ucDMAChannel);
+
+                        //
+                        // Clear all the attributes for the channel
+                        //
+                        MAP_uDMAChannelAttributeDisable(
+                            g_sUSBHCD.USBINPipes[lIdx].ucDMAChannel,
+                            UDMA_ATTR_ALL);
+
+                        //
+                        // Configure the uDMA channel for the pipe
+                        //
+                        MAP_uDMAChannelControlSet(
+                            g_sUSBHCD.USBINPipes[lIdx].ucDMAChannel,
+                            (UDMA_SIZE_8 | UDMA_SRC_INC_NONE | UDMA_DST_INC_8 |
+                             UDMA_ARB_64));
+                    }
+                }
+
+                //
+                // Save the endpoint type and device address and callback
+                // function.
+                //
+                g_sUSBHCD.USBINPipes[lIdx].ulType = ulEndpointType;
+                g_sUSBHCD.USBINPipes[lIdx].ulDevAddr = ulDevAddr;
+                g_sUSBHCD.USBINPipes[lIdx].pfnCallback = pfnCallback;
+
+                //
+                // Clear out any pending status on this endpoint in case it
+                // was in use before a allowing a new device class to use it.
+                //
+                MAP_USBHostEndpointStatusClear(USB0_BASE,
+                                               INDEX_TO_USB_EP(lIdx + 1),
+                                               USB_HOST_IN_STATUS);
+
+                //
+                // Allocate space in the FIFO for this endpoint.
+                //
+                if(FIFOAlloc(&g_sUSBHCD.USBINPipes[lIdx], ulSize) != 0)
+                {
+                    //
+                    // Configure the FIFO.
+                    //
+                    MAP_USBFIFOConfigSet(USB0_BASE, INDEX_TO_USB_EP(lIdx + 1),
+                                         g_sUSBHCD.USBINPipes[lIdx].usFIFOAddr,
+                                         g_sUSBHCD.USBINPipes[lIdx].ucFIFOSize,
+                                         USB_EP_HOST_IN);
+                }
+
+                //
+                // Set the function address for this endpoint.
+                //
+                MAP_USBHostAddrSet(USB0_BASE, INDEX_TO_USB_EP(lIdx + 1),
+                                   ulDevAddr, USB_EP_HOST_IN);
+
+                //
+                // Reset the state of the pipe to idle.
+                //
+                g_sUSBHCD.USBINPipes[lIdx].eState = PIPE_IDLE;
+
+                break;
+            }
+        }
+    }
+
+    //
+    // Did not find a free pipe.
+    //
+    if(lIdx == MAX_NUM_PIPES)
+    {
+        return(0);
+    }
+
+    //
+    // Return the pipe index and type that was allocated.
+    //
+    return(ulEndpointType | lIdx);
+}
+
+//*****************************************************************************
+//
+//! This function is used to allocate a USB HCD pipe.
+//!
+//! \param ulIndex specifies which USB controller to use.
+//! \param ulEndpointType is the type of endpoint that this pipe will be
+//! communicating with.
+//! \param ulDevAddr is the device address to use for this endpoint.
+//! \param pfnCallback is the function that will be called when events occur on
+//! this USB Pipe.
+//!
+//! Since there are a limited number of USB HCD pipes that can be used in the
+//! host controller, this function is used to temporarily or permanently
+//! acquire one of the endpoints.  It also provides a method to register a
+//! callback for status changes on this endpoint.  If no callbacks are desired
+//! then the \e pfnCallback function should be set to 0.  The callback should
+//! be used when using the USBHCDPipeSchedule() function so that the caller is
+//! notified when the action is complete.
+//!
+//! \return This function returns a value indicating which pipe was reserved.
+//! If the value is 0 then there were no pipes currently available.  This value
+//! should be passed to any USBHCDPipe APIs to indicate which pipe is being
+//! accessed.
+//
+//*****************************************************************************
+unsigned long
+USBHCDPipeAlloc(unsigned long ulIndex, unsigned long ulEndpointType,
+                unsigned long ulDevAddr, tHCDPipeCallback pfnCallback)
+{
+    //
+    // The old API allocated only 64 bytes to each endpoint.
+    //
+    return(USBHCDPipeAllocSize(ulIndex, ulEndpointType, ulDevAddr, 64,
+                               pfnCallback));
+}
+
+//*****************************************************************************
+//
+//! This function is used to configure a USB HCD pipe.
+//!
+//! This should be called after allocating a USB pipe with a call to
+//! USBHCDPipeAlloc().  It is used to set the configuration associated with an
+//! endpoint like the max payload and target endpoint.  The \e ulMaxPayload
+//! parameter is typically read directly from the devices endpoint descriptor
+//! and is expressed in bytes.
+//!
+//! Setting the \e ulInterval parameter depends on the type of endpoint being
+//! configured.  For endpoints that do not need to use the \e ulInterval
+//! parameter \e ulInterval should be set to 0.  For Bulk \e ulInterval is a
+//! value from 2-16 and will set the NAK timeout value as 2^(\e ulInterval-1)
+//! frames.  For interrupt endpoints \e ulInterval is a value from 1-255 and
+//! is the count in frames between polling the endpoint.  For isochronous
+//! endpoints \e ulInterval ranges from 1-16 and is the polling interval in
+//! frames represented as 2^(\e ulInterval-1) frames.
+//!
+//! \param ulPipe is the allocated endpoint to modify.
+//! \param ulMaxPayload is maximum data that can be handled per transaction.
+//! \param ulInterval is the polling interval for data transfers expressed in
+//! frames.
+//! \param ulTargetEndpoint is the target endpoint on the device to communicate
+//! with.
+//!
+//! \return If the call was successful, this function returns zero any other
+//! value indicates an error.
+//
+//*****************************************************************************
+unsigned long
+USBHCDPipeConfig(unsigned long ulPipe, unsigned long ulMaxPayload,
+                 unsigned long ulInterval, unsigned long ulTargetEndpoint)
+{
+    unsigned long ulFlags;
+    unsigned long ulIndex;
+
+    //
+    // Get the index number from the allocated pipe.
+    //
+    ulIndex = (ulPipe & EP_PIPE_IDX_M);
+
+    //
+    // Set the direction.
+    //
+    if(ulPipe & EP_PIPE_TYPE_OUT)
+    {
+        //
+        // Set the mode for this endpoint.
+        //
+        if(g_sUSBHCD.USBOUTPipes[ulIndex].ulType & EP_PIPE_TYPE_BULK)
+        {
+            ulFlags = USB_EP_MODE_BULK;
+        }
+        else if(g_sUSBHCD.USBOUTPipes[ulIndex].ulType & EP_PIPE_TYPE_INTR)
+        {
+            ulFlags = USB_EP_MODE_INT;
+        }
+        else if(g_sUSBHCD.USBOUTPipes[ulIndex].ulType & EP_PIPE_TYPE_ISOC)
+        {
+            ulFlags = USB_EP_MODE_ISOC;
+        }
+        else
+        {
+            ulFlags = USB_EP_MODE_CTRL;
+        }
+
+        ulFlags |= USB_EP_HOST_OUT;
+
+        g_sUSBHCD.USBOUTPipes[ulIndex].ucEPNumber =
+            (unsigned char)ulTargetEndpoint;
+
+        //
+        // Save the interval and the next tick to trigger a scheduler event.
+        //
+        g_sUSBHCD.USBOUTPipes[ulIndex].ulInterval = ulInterval;
+        g_sUSBHCD.USBOUTPipes[ulIndex].ulNextEventTick =
+            ulInterval + g_ulCurrentTick;
+    }
+    else
+    {
+        //
+        // Set the mode for this endpoint.
+        //
+        if(g_sUSBHCD.USBINPipes[ulIndex].ulType & EP_PIPE_TYPE_BULK)
+        {
+            ulFlags = USB_EP_MODE_BULK;
+        }
+        else if(g_sUSBHCD.USBINPipes[ulIndex].ulType & EP_PIPE_TYPE_INTR)
+        {
+            ulFlags = USB_EP_MODE_INT;
+        }
+        else if(g_sUSBHCD.USBINPipes[ulIndex].ulType & EP_PIPE_TYPE_ISOC)
+        {
+            ulFlags = USB_EP_MODE_ISOC;
+        }
+        else
+        {
+            ulFlags = USB_EP_MODE_CTRL;
+        }
+        ulFlags |= USB_EP_HOST_IN;
+
+        g_sUSBHCD.USBINPipes[ulIndex].ucEPNumber =
+            (unsigned char)ulTargetEndpoint;
+
+        //
+        // Save the interval and the next tick to trigger a scheduler event.
+        //
+        g_sUSBHCD.USBINPipes[ulIndex].ulInterval = ulInterval;
+        g_sUSBHCD.USBINPipes[ulIndex].ulNextEventTick =
+            ulInterval + g_ulCurrentTick;
+    }
+
+    //
+    // Full speed by default but low speed will be selected if the device is
+    // low speed.
+    //
+    ulFlags |= USB_EP_SPEED_FULL;
+
+    //
+    // Set up the appropriate flags if uDMA is used.
+    //
+    if(ulPipe & EP_PIPE_USE_UDMA)
+    {
+        ulFlags |= USB_EP_DMA_MODE_0;
+    }
+
+    //
+    // Configure the endpoint according to the flags determined above.
+    //
+    USBHostEndpointConfig(USB0_BASE,
+                          INDEX_TO_USB_EP((ulPipe & EP_PIPE_IDX_M) + 1),
+                          ulMaxPayload, ulInterval, ulTargetEndpoint,
+                          ulFlags);
+
+    return(0);
+}
+
+//*****************************************************************************
+//
+//! This function is used to return the current status of a USB HCD pipe.
+//!
+//! This function will return the current status for a given USB pipe.  If
+//! there is no status to report this call will simply return
+//! \b USBHCD_PIPE_NO_CHANGE.
+//!
+//! \param ulPipe is the USB pipe for this status request.
+//!
+//! \return This function returns the current status for the given endpoint.
+//! This will be one of the \b USBHCD_PIPE_* values.
+//
+//*****************************************************************************
+unsigned long
+USBHCDPipeStatus(unsigned long ulPipe)
+{
+    return(0);
+}
+
+//*****************************************************************************
+//
+//! This function is used to write data to a USB HCD pipe.
+//!
+//! \param ulPipe is the USB pipe to put data into.
+//! \param pucData is a pointer to the data to send.
+//! \param ulSize is the amount of data to send.
+//!
+//! This function will block until it has sent as much data as was
+//! requested using the USB pipe's FIFO.  The caller should have registered a
+//! callback with the USBHCDPipeAlloc() call in order to be informed when the
+//! data has been transmitted.  The value returned by this function can be less
+//! than the \e ulSize requested if the USB pipe has less space available than
+//! this request is making.
+//!
+//! \return This function returns the number of bytes that were scheduled to
+//! be sent on the given USB pipe.
+//
+//*****************************************************************************
+unsigned long
+USBHCDPipeWrite(unsigned long ulPipe, unsigned char *pucData,
+                unsigned long ulSize)
+{
+    unsigned long ulEndpoint;
+    unsigned long ulRemainingBytes;
+    unsigned long ulByteToSend;
+    unsigned long ulPipeIdx;
+
+    //
+    // Determine which endpoint interface that this pipe is using.
+    //
+    ulEndpoint = INDEX_TO_USB_EP((EP_PIPE_IDX_M & ulPipe) + 1);
+
+    //
+    // Get index used for looking up pipe data
+    //
+    ulPipeIdx = ulPipe & EP_PIPE_IDX_M;
+
+    //
+    // Set the total number of bytes to send out.
+    //
+    ulRemainingBytes = ulSize;
+
+    if(ulSize > 64)
+    {
+        //
+        // Only send 64 bytes at a time.
+        //
+        ulByteToSend = 64;
+    }
+    else
+    {
+        //
+        // Send the requested number of bytes.
+        //
+        ulByteToSend = ulSize;
+    }
+
+    //
+    // Send all of the requested data.
+    //
+    while(ulRemainingBytes != 0)
+    {
+        //
+        // Start a write request.
+        //
+        g_sUSBHCD.USBOUTPipes[ulPipeIdx].eState = PIPE_WRITING;
+
+        //
+        // If uDMA is not enabled for this pipe, or if the uDMA workaround
+        // is applied, then don't use uDMA for this transfer.
+        //
+        if(!(ulPipe & EP_PIPE_USE_UDMA) ||
+           (g_bUseDMAWA && (ulByteToSend != 64)))
+        {
+            //
+            // Disable uDMA on the USB endpoint
+            //
+            MAP_USBEndpointDMADisable(USB0_BASE, ulEndpoint, USB_EP_HOST_OUT);
+
+            //
+            // Put the data in the buffer.
+            //
+            MAP_USBEndpointDataPut(USB0_BASE, ulEndpoint, pucData,
+                                   ulByteToSend);
+
+            //
+            // Schedule the data to be sent.
+            //
+            MAP_USBEndpointDataSend(USB0_BASE, ulEndpoint, USB_TRANS_OUT);
+        }
+
+        //
+        // Otherwise, uDMA should be used for this transfer
+        //
+        else
+        {
+            //
+            // Set up the uDMA transfer.
+            //
+            MAP_uDMAChannelTransferSet(UDMA_CHANNEL_USBEP1TX + (ulPipeIdx * 2),
+                                       UDMA_MODE_AUTO, pucData,
+                                       (void *)USBFIFOAddrGet(USB0_BASE,
+                                                              ulEndpoint),
+                                       ulByteToSend);
+
+            //
+            // Enable uDMA on the USB endpoint
+            //
+            MAP_USBEndpointDMAEnable(USB0_BASE, ulEndpoint, USB_EP_HOST_OUT);
+
+            //
+            // Set pending transmit DMA flag
+            //
+            g_ulDMAPending |= DMA_PEND_TRANSMIT_FLAG << ulPipeIdx;
+
+            //
+            // Enable the uDMA channel to start the transfer
+            //
+            MAP_uDMAChannelEnable(UDMA_CHANNEL_USBEP1TX + (ulPipeIdx * 2));
+        }
+
+        //
+        // Wait for a status change.
+        //
+        while(g_sUSBHCD.USBOUTPipes[ulPipeIdx].eState == PIPE_WRITING)
+        {
+        }
+
+        //
+        // If the data was successfully sent then decrement the count and
+        // continue.
+        //
+        if(g_sUSBHCD.USBOUTPipes[ulPipeIdx].eState == PIPE_DATA_SENT)
+        {
+            //
+            // Decrement the remaining data and advance the pointer.
+            //
+            ulRemainingBytes -= ulByteToSend;
+            pucData += ulByteToSend;
+        }
+        else if(g_sUSBHCD.USBOUTPipes[ulPipeIdx].eState == PIPE_STALLED)
+        {
+            //
+            // Zero out the size so that the caller knows that no data was
+            // written.
+            //
+            ulSize = 0;
+
+            //
+            // This is the actual endpoint number.
+            //
+            USBHCDClearFeature(1, ulPipe, USB_FEATURE_EP_HALT);
+
+            //
+            // If uDMA is being used, then disable the channel.
+            //
+            if(ulPipe & EP_PIPE_USE_UDMA)
+            {
+                MAP_uDMAChannelDisable(UDMA_CHANNEL_USBEP1TX + (ulPipeIdx * 2));
+            }
+
+            //
+            // If there was a stall, then no more data is coming so break out.
+            //
+            break;
+        }
+
+        //
+        // If there are less than 64 bytes to send then this is the last
+        // of the data to go out.
+        //
+        if(ulRemainingBytes < 64)
+        {
+            ulByteToSend = ulRemainingBytes;
+        }
+    }
+
+    //
+    // Go Idle once this state has been reached.
+    //
+    g_sUSBHCD.USBOUTPipes[ulPipeIdx].eState = PIPE_IDLE;
+
+    return(ulSize);
+}
+
+//*****************************************************************************
+//
+//! This function is used to schedule and IN transaction on a USB HCD pipe.
+//!
+//! \param ulPipe is the USB pipe to read data from.
+//! \param pucData is a pointer to store the data that is received.
+//! \param ulSize is the size in bytes of the buffer pointed to by pucData.
+//!
+//! This function will not block depending on the type of pipe passed in will
+//! schedule either a send of data to the device or a read of data from the
+//! device.  In either case the amount of data will be limited to what will
+//! fit in the FIFO for a given endpoint.
+//!
+//! \return This function returns the number of bytes that sent in the case
+//! of a transfer of data or it will return 0 for a request on a USB IN pipe.
+//
+//*****************************************************************************
+unsigned long
+USBHCDPipeSchedule(unsigned long ulPipe, unsigned char *pucData,
+                   unsigned long ulSize)
+{
+    unsigned long ulEndpoint;
+    unsigned long ulPipeIdx;
+
+    //
+    // Get index used for looking up pipe data
+    //
+    ulPipeIdx = ulPipe & EP_PIPE_IDX_M;
+
+    //
+    // Determine which endpoint interface that this pipe is using.
+    //
+    ulEndpoint = INDEX_TO_USB_EP((EP_PIPE_IDX_M & ulPipe) + 1);
+
+    if(ulPipe & EP_PIPE_TYPE_OUT)
+    {
+        //
+        // Start a write request.
+        //
+        g_sUSBHCD.USBOUTPipes[EP_PIPE_IDX_M & ulPipe].eState = PIPE_WRITING;
+
+        //
+        // Check if uDMA is enabled on this pipe.
+        //
+        if(ulPipe & EP_PIPE_USE_UDMA)
+        {
+            //
+            // Set up the uDMA transfer.
+            //
+            MAP_uDMAChannelTransferSet(UDMA_CHANNEL_USBEP1TX + (ulPipeIdx * 2),
+                                       UDMA_MODE_AUTO, pucData,
+                                       (void *)USBFIFOAddrGet(USB0_BASE,
+                                                              ulEndpoint),
+                                       ulSize);
+
+            //
+            // Enable uDMA on the USB endpoint
+            //
+            MAP_USBEndpointDMAEnable(USB0_BASE, ulEndpoint, USB_EP_HOST_OUT);
+
+            //
+            // Set pending transmit DMA flag
+            //
+            g_ulDMAPending |= DMA_PEND_TRANSMIT_FLAG << ulPipeIdx;
+
+            //
+            // Enable the uDMA channel to start the transfer
+            //
+            MAP_uDMAChannelEnable(UDMA_CHANNEL_USBEP1TX + (ulPipeIdx * 2));
+        }
+        else
+        {
+            //
+            // Put the data in the buffer.
+            //
+            MAP_USBEndpointDataPut(USB0_BASE, ulEndpoint, pucData, ulSize);
+
+            //
+            // Schedule the data to be sent.
+            //
+            MAP_USBEndpointDataSend(USB0_BASE, ulEndpoint, USB_TRANS_OUT);
+        }
+    }
+    else
+    {
+        //
+        // Start a read request.
+        //
+        g_sUSBHCD.USBINPipes[EP_PIPE_IDX_M & ulPipe].eState = PIPE_READING;
+
+        //
+        // If uDMA is not enabled for this pipe, or if the uDMA workaround
+        // is applied, then do not use uDMA for this transfer.
+        //
+        if((ulPipe & EP_PIPE_USE_UDMA) == 0)
+        {
+            //
+            // Disable uDMA on the endpoint
+            //
+            MAP_USBEndpointDMADisable(USB0_BASE, ulEndpoint, USB_EP_HOST_IN);
+        }
+        //
+        // Otherwise, uDMA should be used for this transfer, so set up
+        // the uDMA channel in advance of triggering the IN request.
+        //
+        else
+        {
+            //
+            // Compute bytes to transfer and set up transfer
+            //
+            MAP_uDMAChannelTransferSet(UDMA_CHANNEL_USBEP1RX + (ulPipeIdx * 2),
+                                       UDMA_MODE_AUTO,
+                                       (void *)USBFIFOAddrGet(USB0_BASE,
+                                                              ulEndpoint),
+                                       pucData, ulSize);
+
+            //
+            // Enable uDMA on the endpoint
+            //
+            MAP_USBEndpointDMAEnable(USB0_BASE, ulEndpoint, USB_EP_HOST_IN);
+
+            //
+            // Set pending DMA flag
+            //
+            g_ulDMAPending |= DMA_PEND_RECEIVE_FLAG << ulPipeIdx;
+
+            //
+            // Enable the uDMA channel to start the transfer
+            //
+            MAP_uDMAChannelEnable(UDMA_CHANNEL_USBEP1RX + (ulPipeIdx * 2));
+        }
+
+        //
+        // Trigger a request for data from the device.
+        //
+        MAP_USBHostRequestIN(USB0_BASE, ulEndpoint);
+
+        //
+        // No data was put into or read from the buffer.
+        //
+        ulSize = 0;
+    }
+    return(ulSize);
+}
+
+//*****************************************************************************
+//
+//! This function is used to read data from a USB HCD pipe.
+//!
+//! \param ulPipe is the USB pipe to read data from.
+//! \param pucData is a pointer to store the data that is received.
+//! \param ulSize is the size in bytes of the buffer pointed to by pucData.
+//!
+//! This function will not block and will only read as much data as requested
+//! or as much data is currently available from the USB pipe.  The caller
+//! should have registered a callback with the USBHCDPipeAlloc() call in order
+//! to be informed when the data has been received.  The value returned by this
+//! function can be less than the \e ulSize requested if the USB pipe has less
+//! data available than was requested.
+//!
+//! \return This function returns the number of bytes that were returned in the
+//! \e pucData buffer.
+//
+//*****************************************************************************
+unsigned long
+USBHCDPipeReadNonBlocking(unsigned long ulPipe, unsigned char *pucData,
+                          unsigned long ulSize)
+{
+    unsigned long ulEndpoint;
+
+    //
+    // Determine which endpoint interface that this pipe is using.
+    //
+    ulEndpoint = INDEX_TO_USB_EP((EP_PIPE_IDX_M & ulPipe) + 1);
+
+    //
+    // Read the data out of the USB endpoint interface.
+    //
+    MAP_USBEndpointDataGet(USB0_BASE, ulEndpoint, pucData, &ulSize);
+
+    //
+    // Acknowledge that the data was read from the endpoint.
+    //
+    MAP_USBHostEndpointDataAck(USB0_BASE, ulEndpoint);
+
+    //
+    // Go Idle once this state has been reached.
+    //
+    g_sUSBHCD.USBINPipes[EP_PIPE_IDX_M & ulPipe].eState = PIPE_IDLE;
+
+    return(ulSize);
+}
+
+//*****************************************************************************
+//
+//! This function is used to read data from a USB HCD pipe.
+//!
+//! \param ulPipe is the USB pipe to read data from.
+//! \param pucData is a pointer to store the data that is received.
+//! \param ulSize is the size in bytes of the buffer pointed to by pucData.
+//!
+//! This function will block and will only return when it has read as much data
+//! as requested from the USB pipe.  The caller should have registered a
+//! callback with the USBHCDPipeAlloc() call in order to be informed when the
+//! data has been received.  The value returned by this function can be less
+//! than the \e ulSize requested if the USB pipe has less data available than
+//! was requested.
+//!
+//! \return This function returns the number of bytes that were returned in the
+//! \e pucData buffer.
+//
+//*****************************************************************************
+unsigned long
+USBHCDPipeRead(unsigned long ulPipe, unsigned char *pucData,
+               unsigned long ulSize)
+{
+    unsigned long ulEndpoint;
+    unsigned long ulRemainingBytes;
+    unsigned long ulBytesRead;
+    unsigned long ulPipeIdx;
+
+    //
+    // Get index used for looking up pipe data
+    //
+    ulPipeIdx = ulPipe & EP_PIPE_IDX_M;
+
+    //
+    // Initialized the number of bytes read.
+    //
+    ulBytesRead = 0;
+
+    //
+    // Determine which endpoint interface that this pipe is using.
+    //
+    ulEndpoint = INDEX_TO_USB_EP(ulPipeIdx + 1);
+
+    //
+    // Set the remaining bytes to received.
+    //
+    ulRemainingBytes = ulSize;
+
+    //
+    // Continue until all data requested has been received.
+    //
+    while(ulRemainingBytes != 0)
+    {
+        //
+        // Start a read request.
+        //
+        g_sUSBHCD.USBINPipes[ulPipeIdx].eState = PIPE_READING;
+
+        //
+        // If uDMA is not enabled for this pipe, or if the uDMA workaround
+        // is applied, then do not use uDMA for this transfer.
+        //
+        if(!(ulPipe & EP_PIPE_USE_UDMA) ||
+            (g_bUseDMAWA && (ulRemainingBytes < 64)))
+        {
+            //
+            // Disable uDMA on the endpoint
+            //
+            MAP_USBEndpointDMADisable(USB0_BASE, ulEndpoint, USB_EP_HOST_IN);
+        }
+
+        //
+        // Otherwise, uDMA should be used for this transfer, so set up
+        // the uDMA channel in advance of triggering the IN request.
+        //
+        else
+        {
+            //
+            // Compute bytes to transfer and set up transfer
+            //
+            ulBytesRead = ulRemainingBytes > 64 ? 64 : ulRemainingBytes;
+            MAP_uDMAChannelTransferSet(UDMA_CHANNEL_USBEP1RX + (ulPipeIdx * 2),
+                                       UDMA_MODE_AUTO,
+                                       (void *)USBFIFOAddrGet(USB0_BASE,
+                                                              ulEndpoint),
+                                       pucData, ulBytesRead);
+
+            //
+            // Enable uDMA on the endpoint
+            //
+            MAP_USBEndpointDMAEnable(USB0_BASE, ulEndpoint, USB_EP_HOST_IN);
+
+            //
+            // Set pending DMA flag
+            //
+            g_ulDMAPending |= DMA_PEND_RECEIVE_FLAG << ulPipeIdx;
+
+            //
+            // Enable the uDMA channel to start the transfer
+            //
+            MAP_uDMAChannelEnable(UDMA_CHANNEL_USBEP1RX + (ulPipeIdx * 2));
+        }
+
+        //
+        // Trigger a request for data from the device.
+        //
+        MAP_USBHostRequestIN(USB0_BASE, ulEndpoint);
+
+        //
+        // Wait for a status change.
+        //
+        while(g_sUSBHCD.USBINPipes[ulPipeIdx].eState == PIPE_READING)
+        {
+        }
+
+        //
+        // If data is ready then return it.
+        //
+        if(g_sUSBHCD.USBINPipes[ulPipeIdx].eState == PIPE_DATA_READY)
+        {
+            //
+            // If not using uDMA then read the data from the USB.  Otherwise
+            // the data will already be in the buffer.
+            //
+            if(!(ulPipe & EP_PIPE_USE_UDMA) ||
+                (g_bUseDMAWA && (ulRemainingBytes < 64)))
+            {
+                //
+                // Request all of the remaining bytes.
+                //
+                ulBytesRead = ulRemainingBytes;
+
+                //
+                // Read the data out of the USB endpoint interface.
+                //
+                MAP_USBEndpointDataGet(USB0_BASE, ulEndpoint, pucData,
+                                       &ulBytesRead);
+
+                //
+                // Acknowledge that the data was read from the endpoint.
+                //
+                MAP_USBHostEndpointDataAck(USB0_BASE, ulEndpoint);
+            }
+
+            //
+            // Subtract the number of bytes read from the bytes remaining.
+            //
+            ulRemainingBytes -= ulBytesRead;
+
+            //
+            // If there were less than 64 bytes read, then this was a short
+            // packet and no more data will be returned.
+            //
+            if(ulBytesRead < 64)
+            {
+                //
+                // Subtract off the bytes that were not received and exit the
+                // loop.
+                //
+                ulSize = ulSize - ulRemainingBytes;
+                break;
+            }
+            else
+            {
+                //
+                // Move the buffer ahead to receive more data into the buffer.
+                //
+                pucData += 64;
+            }
+        }
+        else if(g_sUSBHCD.USBINPipes[ulPipeIdx].eState == PIPE_STALLED)
+        {
+            //
+            // Zero out the size so that the caller knows that no data was read.
+            //
+            ulSize = 0;
+
+            //
+            // This is the actual endpoint number.
+            //
+            USBHCDClearFeature(1, ulPipe, USB_FEATURE_EP_HALT);
+
+            //
+            // If uDMA is being used, then disable the channel.
+            //
+            if(ulPipe & EP_PIPE_USE_UDMA)
+            {
+                MAP_uDMAChannelDisable(UDMA_CHANNEL_USBEP1RX + (ulPipeIdx * 2));
+            }
+
+            //
+            // If there was a stall, then no more data is coming so break out.
+            //
+            break;
+        }
+    }
+
+    //
+    // Go Idle once this state has been reached.
+    //
+    g_sUSBHCD.USBINPipes[ulPipeIdx].eState = PIPE_IDLE;
+
+    return(ulSize);
+}
+
+//*****************************************************************************
+//
+//! This function is used to release a USB pipe.
+//!
+//! \param ulPipe is the allocated USB pipe to release.
+//!
+//! This function is used to release a USB pipe that was allocated by a call to
+//! USBHCDPipeAlloc() for use by some other device endpoint in the system.
+//! Freeing an unallocated or invalid pipe will not generate an error and will
+//! instead simply return.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHCDPipeFree(unsigned long ulPipe)
+{
+    long lDMAIdx;
+
+    if(ulPipe & EP_PIPE_TYPE_OUT)
+    {
+        //
+        // Clear the address and type for this endpoint to free it up.
+        //
+        g_sUSBHCD.USBOUTPipes[ulPipe & EP_PIPE_IDX_M].ulDevAddr = 0;
+        g_sUSBHCD.USBOUTPipes[ulPipe & EP_PIPE_IDX_M].ulType = 0;
+        g_sUSBHCD.USBOUTPipes[ulPipe & EP_PIPE_IDX_M].pfnCallback = 0;
+
+        //
+        // Get the dma channel used by this pipe.
+        //
+        lDMAIdx = g_sUSBHCD.USBOUTPipes[ulPipe & EP_PIPE_IDX_M].ucDMAChannel;
+
+        //
+        // Mark the channel as free for use.
+        //
+        g_sUSBHCD.ucDMAChannels[lDMAIdx] = USBHCD_DMA_UNUSED;
+
+        //
+        // Clear out the current channel in use by this pipe.
+        //
+        g_sUSBHCD.USBOUTPipes[ulPipe & EP_PIPE_IDX_M].ucDMAChannel =
+            USBHCD_DMA_UNUSED;
+
+        //
+        // Free up the FIFO memory used by this endpoint.
+        //
+        if(g_sUSBHCD.USBOUTPipes[ulPipe & EP_PIPE_IDX_M].ucFIFOSize)
+        {
+            FIFOFree(&g_sUSBHCD.USBOUTPipes[ulPipe & EP_PIPE_IDX_M]);
+        }
+    }
+    else if(ulPipe & EP_PIPE_TYPE_IN)
+    {
+        //
+        // Clear the address and type for this endpoint to free it up.
+        //
+        g_sUSBHCD.USBINPipes[ulPipe & EP_PIPE_IDX_M].ulDevAddr = 0;
+        g_sUSBHCD.USBINPipes[ulPipe & EP_PIPE_IDX_M].ulType = 0;
+        g_sUSBHCD.USBINPipes[ulPipe & EP_PIPE_IDX_M].pfnCallback = 0;
+
+        //
+        // Get the DMA channel used by this pipe.
+        //
+        lDMAIdx = g_sUSBHCD.USBINPipes[ulPipe & EP_PIPE_IDX_M].ucDMAChannel;
+
+        //
+        // This is a debug check that will prevent accessing beyond the
+        // buffer allocated to the DMA channels.
+        //
+        ASSERT(lDMAIdx < MAX_NUM_DMA_CHANNELS);
+
+        //
+        // Make sure that the DMA index was actually valid because the value
+        // could be USBHCD_DMA_UNUSED.
+        //
+        if(lDMAIdx != USBHCD_DMA_UNUSED)
+        {
+            //
+            // Mark the channel as free for use.
+            //
+            g_sUSBHCD.ucDMAChannels[lDMAIdx] = USBHCD_DMA_UNUSED;
+        }
+
+        //
+        // Clear out the current channel in use by this pipe.
+        //
+        g_sUSBHCD.USBINPipes[ulPipe & EP_PIPE_IDX_M].ucDMAChannel =
+            USBHCD_DMA_UNUSED;
+
+        //
+        // Free up the FIFO memory used by this endpoint.
+        //
+        if(g_sUSBHCD.USBINPipes[ulPipe & EP_PIPE_IDX_M].ucFIFOSize)
+        {
+            FIFOFree(&g_sUSBHCD.USBINPipes[ulPipe & EP_PIPE_IDX_M]);
+        }
+    }
+}
+
+//*****************************************************************************
+//
+// This internal function initializes the HCD code.
+//
+// \param ulIndex specifies which USB controller to use.
+// \param pvPool is a pointer to the data to use as a memory pool for this
+// controller.
+// \param ulPoolSize is the size in bytes of the buffer passed in as pvPool.
+//
+// This function will perform all the necessary operations to allow the USB
+// host controller to begin enumeration and communication with a device.  This
+// function should typically be called once at the start of an application
+// before any other calls are made to the host controller.
+//
+// \return None.
+//
+//*****************************************************************************
+static void
+USBHCDInitInternal(unsigned long ulIndex, void *pvPool,
+                   unsigned long ulPoolSize)
+{
+    long lIdx;
+
+    ASSERT(ulIndex == 0);
+
+    //
+    // The first 64 Bytes are allocated to endpoint 0.
+    //
+    g_ulAlloc[0] = 1;
+    g_ulAlloc[1] = 0;
+
+    //
+    // Save the base address for this controller.
+    //
+    g_sUSBHCD.ulUSBBase = USB0_BASE;
+
+    //
+    // All Pipes are unused at start.
+    //
+    for(lIdx = 0; lIdx < MAX_NUM_PIPES; lIdx++)
+    {
+        g_sUSBHCD.USBINPipes[lIdx].ulDevAddr = 0;
+        g_sUSBHCD.USBINPipes[lIdx].ulType = USBHCD_PIPE_UNUSED;
+        g_sUSBHCD.USBINPipes[lIdx].ucDMAChannel = USBHCD_DMA_UNUSED;
+        g_sUSBHCD.USBOUTPipes[lIdx].ulDevAddr = 0;
+        g_sUSBHCD.USBOUTPipes[lIdx].ulType = USBHCD_PIPE_UNUSED;
+        g_sUSBHCD.USBOUTPipes[lIdx].ucDMAChannel = USBHCD_DMA_UNUSED;
+    }
+
+    //
+    // All DMA channels are unused at start.
+    //
+    for(lIdx = 0; lIdx < MAX_NUM_DMA_CHANNELS; lIdx++)
+    {
+        g_sUSBHCD.ucDMAChannels[lIdx] = USBHCD_DMA_UNUSED;
+    }
+
+    //
+    // Initialized the device structure.
+    //
+    g_sUSBHCD.eDeviceState[0] = HCD_IDLE;
+    g_sUSBHCD.USBDevice[0].pConfigDescriptor = 0;
+
+    //
+    // Initialize the device descriptor.
+    //
+    g_sUSBHCD.USBDevice[0].DeviceDescriptor.bLength = 0;
+    g_sUSBHCD.USBDevice[0].DeviceDescriptor.bMaxPacketSize0 = 0;
+
+    //
+    // Initialize the device address.
+    //
+    g_sUSBHCD.USBDevice[0].ulAddress = 0;
+
+    //
+    // Set the current interface to 0.
+    //
+    g_sUSBHCD.USBDevice[0].ulInterface = 0;
+
+    //
+    // Allocate the memory needed for reading descriptors.
+    //
+    g_sUSBHCD.pvPool = pvPool;
+    g_sUSBHCD.ulPoolSize = ulPoolSize;
+
+    //
+    // Initialize the device class.
+    //
+    g_sUSBHCD.ulClass = USB_CLASS_EVENTS;
+
+    //
+    // Initialize the USB tick module.
+    //
+    InternalUSBTickInit();
+
+    //
+    // Only do hardware update if the stack is in Host mode, do not touch the
+    // hardware for OTG mode operation.
+    //
+    if(g_eUSBMode == USB_MODE_HOST)
+    {
+        //
+        // Configure the End point 0.
+        //
+        USBHostEndpointConfig(USB0_BASE, USB_EP_0, 64, 0, 0,
+                              (USB_EP_MODE_CTRL | USB_EP_SPEED_FULL |
+                               USB_EP_HOST_OUT));
+
+        //
+        // Enable USB Interrupts.
+        //
+        MAP_USBIntEnableControl(USB0_BASE, USB_INTCTRL_RESET |
+                                           USB_INTCTRL_DISCONNECT |
+                                           USB_INTCTRL_SOF |
+                                           USB_INTCTRL_SESSION |
+                                           USB_INTCTRL_BABBLE |
+                                           USB_INTCTRL_CONNECT |
+                                           USB_INTCTRL_RESUME |
+                                           USB_INTCTRL_SUSPEND |
+                                           USB_INTCTRL_VBUS_ERR |
+                                           USB_INTCTRL_POWER_FAULT);
+
+        MAP_USBIntEnableEndpoint(USB0_BASE, USB_INTEP_ALL);
+
+        //
+        // Enable the USB interrupt.
+        //
+        MAP_IntEnable(INT_USB0);
+
+        //
+        // There is no automatic power in pure host mode.
+        //
+        USBHCDPowerConfigSet(ulIndex, g_ulPowerConfig & ~USB_HOST_PWREN_AUTO);
+
+        //
+        // Force the power on as well as this point.
+        //
+        MAP_USBHostPwrEnable(USB0_BASE);
+
+        //
+        // This is required to get into host mode on some parts.
+        //
+        USBOTGSessionRequest(USB0_BASE, true);
+    }
+}
+
+//*****************************************************************************
+//
+//! This function is used to set the power pin and power fault configuration.
+//!
+//! \param ulIndex specifies which USB controller to use.
+//! \param ulPwrConfig is the power configuration to use for the application.
+//!
+//! This function must be called before HCDInit() is called so that the power
+//! pin configuration can be set before power is enabled.  The \e ulPwrConfig
+//! flags specify the power fault level sensitivity, the power fault action,
+//! and the power enable pin level and source.
+//!
+//! One of the following can be selected as the power fault level sensitivity:
+//!
+//! - \b USBHCD_FAULT_LOW - An external power fault is indicated by the pin
+//!                         being driven low.
+//! - \b USBHCD_FAULT_HIGH - An external power fault is indicated by the pin
+//!                          being driven high.
+//!
+//! One of the following can be selected as the power fault action:
+//!
+//! - \b USBHCD_FAULT_VBUS_NONE - No automatic action when power fault
+//!   detected.
+//! - \b USBHCD_FAULT_VBUS_TRI - Automatically Tri-state the USBnEPEN pin on a
+//!                              power fault.
+//! - \b USBHCD_FAULT_VBUS_DIS - Automatically drive the USBnEPEN pin to it's
+//!                              inactive state on a power fault.
+//!
+//! One of the following can be selected as the power enable level and source:
+//!
+//! - \b USBHCD_VBUS_MANUAL - Power control is completely managed by the
+//!                           application, the USB library will provide a
+//!                           power callback to request power state changes.
+//! - \b USBHCD_VBUS_AUTO_LOW - USBEPEN is driven low by the USB controller
+//!                             automatically if USBOTGSessionRequest() has
+//!                             enabled a session.
+//! - \b USBHCD_VBUS_AUTO_HIGH - USBEPEN is driven high by the USB controller
+//!                              automatically if USBOTGSessionRequest() has
+//!                              enabled a session.
+//!
+//! If USBHCD_VBUS_MANUAL is used then the application must provide an
+//! event driver to receive the USB_EVENT_POWER_ENABLE and
+//! USB_EVENT_POWER_DISABLE events and enable and disable power to VBUS when
+//! requested by the USB library.  The application should respond to a power
+//! control callback by enabling or disabling VBUS as soon as possible and
+//! before returning from the callback function.
+//!
+//! \note The following values should no longer be used with the USB library:
+//! USB_HOST_PWRFLT_LOW, USB_HOST_PWRFLT_HIGH, USB_HOST_PWRFLT_EP_NONE,
+//! USB_HOST_PWRFLT_EP_TRI, USB_HOST_PWRFLT_EP_LOW, USB_HOST_PWRFLT_EP_HIGH,
+//! USB_HOST_PWREN_LOW, USB_HOST_PWREN_HIGH, USB_HOST_PWREN_VBLOW, and
+//! USB_HOST_PWREN_VBHIGH.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHCDPowerConfigInit(unsigned long ulIndex, unsigned long ulPwrConfig)
+{
+    ASSERT(ulIndex == 0);
+
+    //
+    // Save the value as it will be used later.
+    //
+    g_ulPowerConfig = ulPwrConfig;
+}
+
+//*****************************************************************************
+//
+//! This function is used to get the power pin and power fault configuration.
+//!
+//! \param ulIndex specifies which USB controller to use.
+//!
+//! This function will return the current power control pin configuration as
+//! set by the USBHCDPowerConfigInit() function or the defaults if not yet set.
+//! See the USBHCDPowerConfigInit() documentation for the meaning of the bits
+//! that are returned by this function.
+//!
+//! \return The configuration of the power control pins.
+//!
+//*****************************************************************************
+unsigned long
+USBHCDPowerConfigGet(unsigned long ulIndex)
+{
+    ASSERT(ulIndex == 0);
+
+    //
+    // Save the value as it will be used later.
+    //
+    return(g_ulPowerConfig);
+}
+
+//*****************************************************************************
+//
+//! This function is used to set the power pin and power fault configuration.
+//!
+//! \param ulIndex specifies which USB controller to use.
+//! \param ulConfig specifies which USB power configuration to use.
+//!
+//! This function will set the current power control pin configuration as
+//! set by the USBHCDPowerConfigInit() function or the defaults if not yet set.
+//! See the USBHCDPowerConfigInit() documentation for the meaning of the bits
+//! that are set by this function.
+//!
+//! \return Returns zero to indicate the power setting is now active.
+//!
+//*****************************************************************************
+unsigned long
+USBHCDPowerConfigSet(unsigned long ulIndex, unsigned long ulConfig)
+{
+    ASSERT(ulIndex == 0);
+
+    //
+    // Remember the current setting.
+    //
+    g_ulPowerConfig = ulConfig;
+
+    //
+    // Clear out the two flag bits.
+    //
+    ulConfig = g_ulPowerConfig & ~(USBHCD_VBUS_MANUAL | USBHCD_FAULT_VBUS_DIS);
+
+    //
+    // If there is an automatic disable power action specified then set the
+    // polarity of the signal to match EPEN.
+    //
+    if(g_ulPowerConfig & USBHCD_FAULT_VBUS_DIS)
+    {
+        //
+        // Insure that the assumption below is true.
+        //
+        ASSERT((USBHCD_VBUS_AUTO_HIGH & 1) == 1);
+        ASSERT((USBHCD_VBUS_AUTO_LOW & 1) == 0);
+
+        //
+        // This is taking advantage of the difference between
+        // USBHCD_VBUS_AUTO_LOW and USBHCD_VBUS_AUTO_HIGH being that bit
+        // one is set when EPEN is active high.
+        //
+        if(g_ulPowerConfig & 1)
+        {
+            g_ulPowerConfig |= USB_HOST_PWRFLT_EP_HIGH;
+        }
+        else
+        {
+            g_ulPowerConfig |= USB_HOST_PWRFLT_EP_LOW;
+        }
+    }
+
+    //
+    // Initialize the power configuration.
+    //
+    MAP_USBHostPwrConfig(USB0_BASE, ulConfig);
+
+    //
+    // If not in manual mode then just turn on power.
+    //
+    if((g_ulPowerConfig & USBHCD_VBUS_MANUAL) == 0)
+    {
+        //
+        // Power the USB bus.
+        //
+        MAP_USBHostPwrEnable(USB0_BASE);
+    }
+
+    //
+    // Return success.
+    //
+    return(0);
+}
+
+//*****************************************************************************
+//
+//! This function returns if the current power settings will automatically
+//! handle enabling and disabling VBUS power.
+//!
+//! \param ulIndex specifies which USB controller to query.
+//!
+//! This function returns if the current power control pin configuration will
+//! automatically apply power or whether it will be left to the application
+//! to turn on power when it is notified.
+//!
+//! \return A non-zero value indicates that power is automatically applied and
+//! a value of zero indicates that the application must manually apply power.
+//!
+//*****************************************************************************
+unsigned long
+USBHCDPowerAutomatic(unsigned long ulIndex)
+{
+    //
+    // Check if the controller is automatically applying power or not.
+    //
+    if(g_ulPowerConfig & USBHCD_VBUS_MANUAL)
+    {
+        return(0);
+    }
+    return(1);
+}
+
+//*****************************************************************************
+//
+//! This function is used to initialize the HCD code.
+//!
+//! \param ulIndex specifies which USB controller to use.
+//! \param pvPool is a pointer to the data to use as a memory pool for this
+//! controller.
+//! \param ulPoolSize is the size in bytes of the buffer passed in as pvPool.
+//!
+//! This function will perform all the necessary operations to allow the USB
+//! host controller to begin enumeration and communication with devices.  This
+//! function should typically be called once at the start of an application
+//! once all of the device and class drivers are ready for normal operation.
+//! This call will start up the USB host controller and any connected device
+//! will immediately start the enumeration sequence.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHCDInit(unsigned long ulIndex, void *pvPool, unsigned long ulPoolSize)
+{
+    long lDriver;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulIndex == 0);
+
+    //
+    // Make sure there is at least enough to read the configuration descriptor.
+    //
+    ASSERT(ulPoolSize >= sizeof(tConfigDescriptor));
+
+    //
+    // Should not call this if the stack is in device mode.
+    //
+    ASSERT(g_eUSBMode != USB_MODE_DEVICE)
+
+    //
+    // If no mode is set then make the mode become host mode.
+    //
+    if(g_eUSBMode == USB_MODE_NONE)
+    {
+        g_eUSBMode = USB_MODE_HOST;
+    }
+
+    //
+    // Only do hardware update if the stack is in Host mode, do not touch the
+    // hardware for OTG mode operation.
+    //
+    if(g_eUSBMode == USB_MODE_HOST)
+    {
+        //
+        // Reset the USB controller.
+        //
+        MAP_SysCtlPeripheralReset(SYSCTL_PERIPH_USB0);
+
+        //
+        // Enable Clocking to the USB controller.
+        //
+        MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_USB0);
+
+        //
+        // Turn on USB Phy clock.
+        //
+        MAP_SysCtlUSBPLLEnable();
+    }
+
+    //
+    // Call our internal function to perform the initialization.
+    //
+    USBHCDInitInternal(ulIndex, pvPool, ulPoolSize);
+
+    //
+    // No event driver is present by default.
+    //
+    g_sUSBHCD.lEventDriver = -1;
+
+    //
+    // Search through the Host Class driver list for the devices class.
+    //
+    for(lDriver = 0; lDriver < g_sUSBHCD.ulNumClassDrivers; lDriver++)
+    {
+        if(g_sUSBHCD.pClassDrivers[lDriver]->ulInterfaceClass ==
+           USB_CLASS_EVENTS)
+        {
+            //
+            // Event driver was found so remember it.
+            //
+            g_sUSBHCD.lEventDriver = lDriver;
+        }
+    }
+
+    //
+    // Get the number of ticks per millisecond, this is only used by blocking
+    // delays using the SysCtlDelay() function.
+    //
+    g_ulTickms = MAP_SysCtlClockGet() / 3000;
+
+    //
+    // Check to see if uDMA workaround is needed.
+    //
+    if(CLASS_IS_DUSTDEVIL && REVISION_IS_A0)
+    {
+        g_bUseDMAWA = 1;
+    }
+}
+
+//*****************************************************************************
+//
+//! This function is used to initialize the HCD class driver list.
+//!
+//! \param ulIndex specifies which USB controller to use.
+//! \param ppHClassDrvs is an array of host class drivers that are
+//! supported on this controller.
+//! \param ulNumDrivers is the number of entries in the \e pHostClassDrivers
+//! array.
+//!
+//! This function will set the host classes supported by the host controller
+//! specified by the \e ulIndex parameter.  This function should be called
+//! before enabling the host controller driver with the USBHCDInit() function.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHCDRegisterDrivers(unsigned long ulIndex,
+                      const tUSBHostClassDriver * const *ppHClassDrvs,
+                      unsigned long ulNumDrivers)
+{
+    ASSERT(ulIndex == 0);
+
+    //
+    // Save the class drivers.
+    //
+    g_sUSBHCD.pClassDrivers = ppHClassDrvs;
+
+    //
+    // Save the number of class drivers.
+    //
+    g_sUSBHCD.ulNumClassDrivers = ulNumDrivers;
+}
+
+//*****************************************************************************
+//
+//! This function is used to terminate the HCD code.
+//!
+//! \param ulIndex specifies which USB controller to release.
+//!
+//! This function will clean up the USB host controller and disable it in
+//! preparation for shutdown or a switch to USB device mode.  Once this call is
+//! made, \e USBHCDInit() may be called to reinitialize the controller and
+//! prepare for host mode operation.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHCDTerm(unsigned long ulIndex)
+{
+    ASSERT(ulIndex == 0);
+
+    //
+    // End the session.
+    //
+    USBOTGSessionRequest(USB0_BASE, false);
+
+    //
+    // Remove power from the USB bus.
+    //
+    MAP_USBHostPwrDisable(USB0_BASE);
+
+    //
+    // Disable USB interrupts.
+    //
+    MAP_IntDisable(INT_USB0);
+
+    MAP_USBIntDisableControl(USB0_BASE, USB_INTCTRL_ALL);
+
+    MAP_USBIntDisableEndpoint(USB0_BASE, USB_INTEP_ALL);
+
+    //
+    // Set the host controller state back to it's initial values.
+    //
+    g_sUSBHCD.USBINPipes[0].ulType = USBHCD_PIPE_UNUSED;
+    g_sUSBHCD.USBINPipes[1].ulType = USBHCD_PIPE_UNUSED;
+    g_sUSBHCD.USBINPipes[2].ulType = USBHCD_PIPE_UNUSED;
+    g_sUSBHCD.USBOUTPipes[0].ulType = USBHCD_PIPE_UNUSED;
+    g_sUSBHCD.USBOUTPipes[1].ulType = USBHCD_PIPE_UNUSED;
+    g_sUSBHCD.USBOUTPipes[2].ulType = USBHCD_PIPE_UNUSED;
+    g_sUSBHCD.eDeviceState[0] = HCD_IDLE;
+    g_sUSBHCD.USBDevice[0].pConfigDescriptor = 0;
+    g_sUSBHCD.USBDevice[0].DeviceDescriptor.bLength = 0;
+    g_sUSBHCD.USBDevice[0].DeviceDescriptor.bMaxPacketSize0 = 0;
+    g_sUSBHCD.USBDevice[0].ulAddress = 0;
+    g_sUSBHCD.USBDevice[0].ulInterface = 0;
+    g_sUSBHCD.pvPool = 0;
+    g_sUSBHCD.ulPoolSize = 0;
+}
+
+//*****************************************************************************
+//
+//! This function generates reset signaling on the USB bus.
+//!
+//! \param ulIndex specifies which USB controller to use.
+//!
+//! This function handles sending out reset signaling on the USB bus.  After
+//! returning from this function, any attached device on the USB bus should
+//! have returned to it's reset state.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHCDReset(unsigned long ulIndex)
+{
+    ASSERT(ulIndex == 0);
+
+    //
+    // Start the reset signaling.
+    //
+    MAP_USBHostReset(USB0_BASE, 1);
+
+    //
+    // Wait 20ms
+    //
+    MAP_SysCtlDelay(g_ulTickms * 20);
+
+    //
+    // End reset signaling on the bus.
+    //
+    MAP_USBHostReset(USB0_BASE, 0);
+
+    //
+    // Need to wait at least 10ms to let the device recover from
+    // the reset.  This is the delay specified in the USB 2.0 spec.
+    // We will hold the reset for 20ms.
+    //
+    MAP_SysCtlDelay(g_ulTickms * 20);
+}
+
+//*****************************************************************************
+//
+//! This function will generate suspend signaling on the USB bus.
+//!
+//! \param ulIndex specifies which USB controller to use.
+//!
+//! This function is used to generate suspend signaling on the USB bus.  In
+//! order to leave the suspended state, the application should call
+//! USBHCDResume().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHCDSuspend(unsigned long ulIndex)
+{
+    ASSERT(ulIndex == 0);
+
+    //
+    // Start the suspend signaling.
+    //
+    MAP_USBHostSuspend(USB0_BASE);
+}
+
+//*****************************************************************************
+//
+//! This function will generate resume signaling on the USB bus.
+//!
+//! \param ulIndex specifies which USB controller to use.
+//!
+//! This function is used to generate resume signaling on the USB bus in order
+//! to cause  USB devices to leave their suspended state.  This call should
+//! not be made unless a preceding call to USBHCDSuspend() has been made.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHCDResume(unsigned long ulIndex)
+{
+    ASSERT(ulIndex == 0);
+
+    //
+    // Start the resume signaling.
+    //
+    MAP_USBHostResume(USB0_BASE, 1);
+
+    //
+    // Wait 100ms
+    //
+    MAP_SysCtlDelay(g_ulTickms * 100);
+
+    //
+    // End reset signaling on the bus.
+    //
+    MAP_USBHostResume(USB0_BASE, 0);
+}
+
+//*****************************************************************************
+//
+//! This function issues a request for the current configuration descriptor
+//! from a device.
+//!
+//! \param ulIndex specifies which USB controller to use.
+//! \param pDevice is a pointer to the device structure that holds the buffer
+//! to store the configuration descriptor.
+//!
+//! This function will request the configuration descriptor from the device.
+//! The \e pDevice->ConfigDescriptor member variable is used to hold the data
+//! for this request.  This buffer will be allocated from the pool provided by
+//! the HCDInit() function.  \e pDevice->DeviceDescriptor.bMaxPacketSize0
+//! should be valid prior to this call in order to correctly receive the
+//! configuration descriptor.  If this variable is not valid then this call
+//! will not return accurate data.
+//!
+//! \return The number of bytes returned due to the request.  This value can be
+//! zero if the device did not respond.
+//
+//*****************************************************************************
+static unsigned long
+USBHCDGetConfigDescriptor(unsigned long ulIndex, tUSBHostDevice *pDevice)
+{
+    tUSBRequest SetupPacket;
+    unsigned long ulBytes;
+
+    ASSERT(ulIndex == 0);
+
+    ulBytes = 0;
+
+    //
+    // This is a Standard Device IN request.
+    //
+    SetupPacket.bmRequestType =
+        USB_RTYPE_DIR_IN | USB_RTYPE_STANDARD | USB_RTYPE_DEVICE;
+
+    //
+    // Request a Device Descriptor.
+    //
+    SetupPacket.bRequest = USBREQ_GET_DESCRIPTOR;
+    SetupPacket.wValue = USB_DTYPE_CONFIGURATION << 8;
+
+    //
+    // Index is always 0 for device configurations requests.
+    //
+    SetupPacket.wIndex = 0;
+
+    //
+    // Only ask for the configuration header first to see how big the
+    // whole thing is.
+    //
+    if(g_sUSBHCD.USBDevice[0].pConfigDescriptor == 0)
+    {
+        //
+        // Only request the space available.
+        //
+        SetupPacket.wLength = sizeof(tConfigDescriptor);
+
+        //
+        // Set the memory to use for the config descriptor and save the size.
+        //
+        g_sUSBHCD.USBDevice[0].pConfigDescriptor = g_sUSBHCD.pvPool;
+        g_sUSBHCD.USBDevice[0].ulConfigDescriptorSize = g_sUSBHCD.ulPoolSize;
+
+        //
+        // Put the setup packet in the buffer.
+        //
+        ulBytes =
+            USBHCDControlTransfer(0, &SetupPacket, pDevice->ulAddress,
+                                  (unsigned char *)pDevice->pConfigDescriptor,
+                                  sizeof(tConfigDescriptor),
+                                  pDevice->DeviceDescriptor.bMaxPacketSize0);
+    }
+
+    //
+    // If the Configuration header was successfully returned then get the
+    // full configuration descriptor.
+    //
+    if(ulBytes == sizeof(tConfigDescriptor))
+    {
+        //
+        // Save the total size and request the full configuration descriptor.
+        //
+        SetupPacket.wLength =
+            g_sUSBHCD.USBDevice[0].pConfigDescriptor->wTotalLength;
+
+        //
+        // Don't allow the buffer to be larger than was allocated.
+        //
+        if(SetupPacket.wLength > g_sUSBHCD.ulPoolSize)
+        {
+            SetupPacket.wLength = g_sUSBHCD.ulPoolSize;
+        }
+
+        //
+        // Put the setup packet in the buffer.
+        //
+        ulBytes =
+            USBHCDControlTransfer(0, &SetupPacket, pDevice->ulAddress,
+                                  (unsigned char *)pDevice->pConfigDescriptor,
+                                  SetupPacket.wLength,
+                                  pDevice->DeviceDescriptor.bMaxPacketSize0);
+    }
+
+    return(ulBytes);
+}
+
+//*****************************************************************************
+//
+//! This function issues a request for a device descriptor from a device.
+//!
+//! \param ulIndex specifies which USB controller to use.
+//! \param pDevice is a pointer to the device structure that holds the buffer
+//! to store the device descriptor into.
+//!
+//! This function will request the device descriptor from the device.  The
+//! \e pDevice->DeviceDescriptor descriptor is used to hold the data for this
+//! request.  \e pDevice->DeviceDescriptor.bMaxPacketSize0 should be
+//! initialized to zero or to the valid maximum packet size if it is known.  If
+//! this variable is not set to zero, then this call will determine the maximum
+//! packet size for endpoint 0 and save it in the structure member
+//! bMaxPacketSize0.
+//!
+//! \return The number of bytes returned due to the request.  This value can be
+//! zero if the device did not respond.
+//
+//*****************************************************************************
+static unsigned long
+USBHCDGetDeviceDescriptor(unsigned long ulIndex, tUSBHostDevice *pDevice)
+{
+    tUSBRequest SetupPacket;
+    unsigned long ulBytes;
+
+    ASSERT(ulIndex == 0);
+
+    //
+    // This is a Standard Device IN request.
+    //
+    SetupPacket.bmRequestType =
+        USB_RTYPE_DIR_IN | USB_RTYPE_STANDARD | USB_RTYPE_DEVICE;
+
+    //
+    // Request a Device Descriptor.
+    //
+    SetupPacket.bRequest = USBREQ_GET_DESCRIPTOR;
+    SetupPacket.wValue = USB_DTYPE_DEVICE << 8;
+
+    //
+    // Index is always 0 for device requests.
+    //
+    SetupPacket.wIndex = 0;
+
+    //
+    // All devices must have at least an 8 byte max packet size so just ask
+    // for 8 bytes to start with.
+    //
+    SetupPacket.wLength = 8;
+
+    ulBytes = 0;
+
+    //
+    // Discover the max packet size for endpoint 0.
+    //
+    if(pDevice->DeviceDescriptor.bMaxPacketSize0 == 0)
+    {
+        //
+        // Put the setup packet in the buffer.
+        //
+        ulBytes =
+            USBHCDControlTransfer(ulIndex, &SetupPacket, pDevice->ulAddress,
+                                  (unsigned char *)&(pDevice->DeviceDescriptor),
+                                  sizeof(tDeviceDescriptor),
+                                  MAX_PACKET_SIZE_EP0);
+    }
+
+    //
+    // Now get the full descriptor now that the actual maximum packet size
+    // is known.
+    //
+    if(ulBytes < sizeof(tDeviceDescriptor))
+    {
+        SetupPacket.wLength = (unsigned short)sizeof(tDeviceDescriptor);
+
+        ulBytes =
+            USBHCDControlTransfer(ulIndex, &SetupPacket, pDevice->ulAddress,
+                                  (unsigned char *)&(pDevice->DeviceDescriptor),
+                                  sizeof(tDeviceDescriptor),
+                                  pDevice->DeviceDescriptor.bMaxPacketSize0);
+    }
+
+    return(ulBytes);
+}
+
+//*****************************************************************************
+//
+//! This function is used to send the set address command to a device.
+//!
+//! \param ulDevAddress is the new device address to use for a device.
+//!
+//! The USBHCDSetAddress() function is used to set the USB device address, once
+//! a device has been discovered on the bus.  This is typically issued
+//! following a USB reset which is triggered by a call the USBHCDReset().  The
+//! address passed into this function via the \e ulDevAddress parameter should
+//! be used for all further communications with the device once this function
+//! returns.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHCDSetAddress(unsigned long ulDevAddress)
+{
+    tUSBRequest SetupPacket;
+
+    //
+    // This is a Standard Device OUT request.
+    //
+    SetupPacket.bmRequestType =
+        USB_RTYPE_DIR_OUT | USB_RTYPE_STANDARD | USB_RTYPE_DEVICE;
+
+    //
+    // Request a Device Descriptor.
+    //
+    SetupPacket.bRequest = USBREQ_SET_ADDRESS;
+    SetupPacket.wValue = ulDevAddress;
+
+    //
+    // Index is always 0 for device requests.
+    //
+    SetupPacket.wIndex = 0;
+
+    //
+    // Only request the space available.
+    //
+    SetupPacket.wLength = 0;
+
+    //
+    // Put the setup packet in the buffer.
+    //
+    USBHCDControlTransfer(0, &SetupPacket, 0, 0, 0, MAX_PACKET_SIZE_EP0);
+
+    //
+    // Must delay 2ms after setting the address.
+    //
+    MAP_SysCtlDelay(g_ulTickms * 2);
+}
+
+//*****************************************************************************
+//
+//! This function is used to send a Clear Feature request to a device.
+//!
+//! \param ulDevAddress is the USB bus address of the device that will receive
+//! this request.
+//! \param ulPipe is the pipe that will be used to send the request.
+//! \param ulFeature is one of the USB_FEATURE_* definitions.
+//!
+//! This function will issue a Clear Feature request to the device indicated
+//! by the \e ulDevAddress parameter.  The \e ulPipe parameter is the USB pipe
+//! that should be used to send this request.  The \e ulFeature parameter
+//! should be one of the following values:
+//!
+//! * \b USB_FEATURE_EP_HALT is used to end a HALT condition on a devices
+//!   endpoint.
+//! * \b USB_FEATURE_REMOTE_WAKE is used to disable a device's remote wake
+//!   feature.
+//! * \b USB_FEATURE_TEST_MODE is used take the USB device out of test mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHCDClearFeature(unsigned long ulDevAddress, unsigned long ulPipe,
+                   unsigned long ulFeature)
+{
+    tUSBRequest SetupPacket;
+    unsigned long ulIndex;
+
+    //
+    // Get the index number from the allocated pipe.
+    //
+    ulIndex = (ulPipe & EP_PIPE_IDX_M);
+
+    //
+    // This is a Standard Device OUT request.
+    //
+    SetupPacket.bmRequestType =
+        USB_RTYPE_DIR_OUT | USB_RTYPE_STANDARD | USB_RTYPE_ENDPOINT;
+
+    //
+    // Request a Device Descriptor.
+    //
+    SetupPacket.bRequest = USBREQ_CLEAR_FEATURE;
+    SetupPacket.wValue = ulFeature;
+
+    //
+    // Set the endpoint to access.
+    //
+    if(ulPipe & EP_PIPE_TYPE_IN)
+    {
+        SetupPacket.wIndex = g_sUSBHCD.USBINPipes[ulIndex].ucEPNumber | 0x80;
+    }
+    else
+    {
+        SetupPacket.wIndex = g_sUSBHCD.USBOUTPipes[ulIndex].ucEPNumber;
+    }
+
+    //
+    // This is always 0.
+    //
+    SetupPacket.wLength = 0;
+
+    //
+    // Put the setup packet in the buffer.
+    //
+    USBHCDControlTransfer(0, &SetupPacket, ulDevAddress, 0, 0,
+                          MAX_PACKET_SIZE_EP0);
+
+    //
+    // Set the endpoint to access.
+    //
+    if(ulPipe & EP_PIPE_TYPE_IN)
+    {
+        MAP_USBEndpointDataToggleClear(USB0_BASE, INDEX_TO_USB_EP(ulIndex + 1),
+                                       USB_EP_HOST_IN);
+    }
+    else
+    {
+        MAP_USBEndpointDataToggleClear(USB0_BASE, INDEX_TO_USB_EP(ulIndex + 1),
+                                       USB_EP_HOST_OUT);
+    }
+
+    //
+    // Must delay 2ms after clearing the feature.
+    //
+    MAP_SysCtlDelay(g_ulTickms * 2);
+}
+
+//*****************************************************************************
+//
+//! This function is used to set the current configuration for a device.
+//!
+//! \param ulIndex specifies which USB controller to use.
+//! \param ulDevice is the USB device for this function.
+//! \param ulConfiguration is one of the devices valid configurations.
+//!
+//! This function is used to set the current device configuration for a USB
+//! device.  The \e ulConfiguration value must be one of the configuration
+//! indexes that was returned in the configuration descriptor from the device,
+//! or a value of 0.  If 0 is passed in, the device will return to it's
+//! addressed state and no longer be in a configured state.  If the value is
+//! non-zero then the device will change to the requested configuration.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHCDSetConfig(unsigned long ulIndex, unsigned long ulDevice,
+                unsigned long ulConfiguration)
+{
+    tUSBRequest SetupPacket;
+    tUSBHostDevice *pDevice;
+
+    ASSERT(ulIndex == 0);
+
+    pDevice = (tUSBHostDevice *)ulDevice;
+
+    //
+    // This is a Standard Device OUT request.
+    //
+    SetupPacket.bmRequestType =
+        USB_RTYPE_DIR_OUT | USB_RTYPE_STANDARD | USB_RTYPE_DEVICE;
+
+    //
+    // Request a Device Descriptor.
+    //
+    SetupPacket.bRequest = USBREQ_SET_CONFIG;
+    SetupPacket.wValue = ulConfiguration;
+
+    //
+    // Index is always 0 for device requests.
+    //
+    SetupPacket.wIndex = 0;
+
+    //
+    // Only request the space available.
+    //
+    SetupPacket.wLength = 0;
+
+    //
+    // Put the setup packet in the buffer.
+    //
+    USBHCDControlTransfer(0, &SetupPacket, pDevice->ulAddress, 0, 0,
+                          MAX_PACKET_SIZE_EP0);
+}
+
+//*****************************************************************************
+//
+//! This function is used to set the current interface and alternate setting
+//! for an interface on a device.
+//!
+//! \param ulIndex specifies which USB controller to use.
+//! \param ulDevice is the USB device for this function.
+//! \param ulInterface is one of the valid interface numbers for a device.
+//! \param ulAltSetting is one of the valid alternate interfaces for the
+//! ulInterface number.
+//!
+//! This function is used to change the alternate setting for one of the valid
+//! interfaces on a USB device.  The \e ulDevice specifies the device instance
+//! that was returned when the device was connected.  This call will set the
+//! USB device's interface based on the \e ulInterface and \e ulAltSetting.
+//!
+//! \b Example: Set the USB device interface 2 to alternate setting 1.
+//!
+//! \verbatim
+//! USBHCDSetInterface(0, ulDevice, 2, 1);
+//! \endverbatim
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHCDSetInterface(unsigned long ulIndex, unsigned long ulDevice,
+                   unsigned long ulInterface, unsigned ulAltSetting)
+{
+    tUSBRequest SetupPacket;
+    tUSBHostDevice *pDevice;
+
+    ASSERT(ulIndex == 0);
+
+    pDevice = (tUSBHostDevice *)ulDevice;
+
+    //
+    // This is a Standard Device OUT request.
+    //
+    SetupPacket.bmRequestType =
+        USB_RTYPE_DIR_OUT | USB_RTYPE_STANDARD | USB_RTYPE_INTERFACE;
+
+    //
+    // Request a Device Descriptor.
+    //
+    SetupPacket.bRequest = USBREQ_SET_INTERFACE;
+
+    //
+    // Index is the interface to access.
+    //
+    SetupPacket.wIndex = ulInterface;
+
+    //
+    // wValue is the alternate setting.
+    //
+    SetupPacket.wValue = ulAltSetting;
+
+
+    //
+    // Only request the space available.
+    //
+    SetupPacket.wLength = 0;
+
+    //
+    // Put the setup packet in the buffer.
+    //
+    USBHCDControlTransfer(0, &SetupPacket, pDevice->ulAddress, 0, 0,
+                          MAX_PACKET_SIZE_EP0);
+}
+
+//*****************************************************************************
+//
+// The internal function to see if a new schedule event should occur.
+//
+// This function is called by the main interrupt handler due to start of frame
+// interrupts to determine if a new scheduler event should be sent to the USB
+// pipe.
+//
+// \return None.
+//
+//*****************************************************************************
+void
+USBHostCheckPipes(void)
+{
+    long lIdx;
+
+    for(lIdx = 0; lIdx < 3; lIdx++)
+    {
+        //
+        // Skip unused pipes.
+        //
+        if(g_sUSBHCD.USBINPipes[lIdx].ulType == USBHCD_PIPE_UNUSED)
+        {
+            continue;
+        }
+
+        //
+        // If the tick has expired and it has an interval then update it.
+        //
+        if((g_sUSBHCD.USBINPipes[lIdx].ulInterval != 0) &&
+           (g_sUSBHCD.USBINPipes[lIdx].ulNextEventTick == g_ulCurrentTick))
+        {
+            //
+            // Schedule the next event.
+            //
+            g_sUSBHCD.USBINPipes[lIdx].ulNextEventTick +=
+                g_sUSBHCD.USBINPipes[lIdx].ulInterval;
+
+            //
+            // If the pipe is IDLE and there is a callback, let the higher
+            // level drivers know that a new transfer can be scheduled.
+            //
+            if((g_sUSBHCD.USBINPipes[lIdx].eState == PIPE_IDLE) &&
+               (g_sUSBHCD.USBINPipes[lIdx].pfnCallback))
+            {
+                g_sUSBHCD.USBINPipes[lIdx].pfnCallback(IN_PIPE_HANDLE(lIdx),
+                                                       USB_EVENT_SCHEDULER);
+            }
+        }
+    }
+}
+
+//*****************************************************************************
+//
+// The internal USB host mode interrupt handler.
+//
+// \param ulIndex is the USB controller associated with this interrupt.
+// \param ulStatus is the current interrupt status as read via a call to
+// \e USBIntStatusControl().
+//
+// This the main USB interrupt handler called when operating in host mode.
+// This handler will branch the interrupt off to the appropriate handlers
+// depending on the current status of the USB controller.
+//
+// The two-tiered structure for the interrupt handler ensures that it is
+// possible to use the same handler code in both host and OTG modes and
+// means that device code can be excluded from applications that only require
+// support for USB host mode operation.
+//
+// \return None.
+//
+//*****************************************************************************
+void
+USBHostIntHandlerInternal(unsigned long ulIndex, unsigned long ulStatus)
+{
+    unsigned long ulEPStatus;
+    static unsigned long ulSOFDivide = 0;
+    unsigned long ulEvent;
+    unsigned long ulIdx;
+
+    if(ulStatus & USB_INTCTRL_SOF)
+    {
+        g_ulCurrentTick++;
+
+        USBHostCheckPipes();
+    }
+
+    //
+    // A power fault has occurred so notify the application.
+    //
+    if(ulStatus & USB_INTCTRL_POWER_FAULT)
+    {
+        //
+        // Indicate that a power fault has occurred.
+        //
+        g_ulUSBHIntEvents |= INT_EVENT_POWER_FAULT;
+
+        //
+        // Turn off power to the bus.
+        //
+        MAP_USBHostPwrDisable(USB0_BASE);
+
+        //
+        // Disable USB interrupts.
+        //
+        MAP_IntDisable(INT_USB0);
+
+        return;
+    }
+
+    //
+    // In the event of a USB VBUS error, end the session and remove power to
+    // the device.
+    //
+    if(ulStatus & USB_INTCTRL_VBUS_ERR)
+    {
+        //
+        // Set the VBUS error event.  We deliberately clear all other events
+        // since this one means anything else that is outstanding is
+        // irrelevant.
+        //
+        g_ulUSBHIntEvents = INT_EVENT_VBUS_ERR;
+        return;
+    }
+
+    //
+    // Received a reset from the host.
+    //
+    if(ulStatus & USB_INTCTRL_RESET)
+    {
+    }
+
+    //
+    // Suspend was signaled on the bus.
+    //
+    if(ulStatus & USB_INTCTRL_SUSPEND)
+    {
+    }
+
+    //
+    // Start the session.
+    //
+    if(ulStatus & USB_INTCTRL_SESSION)
+    {
+        //
+        // Power the USB bus.
+        //
+        MAP_USBHostPwrEnable(USB0_BASE);
+
+        USBOTGSessionRequest(USB0_BASE, true);
+    }
+
+    //
+    // Resume was signaled on the bus.
+    //
+    if(ulStatus & USB_INTCTRL_RESUME)
+    {
+    }
+
+    //
+    // Device connected so tell the main routine to issue a reset.
+    //
+    if(ulStatus & USB_INTCTRL_CONNECT)
+    {
+        //
+        // Set the connect flag and clear disconnect if it happens to be set.
+        //
+        g_ulUSBHIntEvents |= INT_EVENT_CONNECT;
+        g_ulUSBHIntEvents &= ~INT_EVENT_DISCONNECT;
+
+        //
+        // Power the USB bus.
+        //
+        MAP_USBHostPwrEnable(USB0_BASE);
+    }
+
+    //
+    // Device was unplugged.
+    //
+    if(ulStatus & USB_INTCTRL_DISCONNECT)
+    {
+        //
+        // Set the disconnect flag and clear connect if it happens to be set.
+        //
+        g_ulUSBHIntEvents |= INT_EVENT_DISCONNECT;
+        g_ulUSBHIntEvents &= ~INT_EVENT_CONNECT;
+    }
+
+    //
+    // Start of Frame was received.
+    //
+    if(ulStatus & USB_INTCTRL_SOF)
+    {
+        //
+        // Increment the global Start of Frame counter.
+        //
+        g_ulUSBSOFCount++;
+
+        //
+        // Increment our SOF divider.
+        //
+        ulSOFDivide++;
+
+        //
+        // Have we counted enough SOFs to allow us to call the tick function?
+        //
+        if(ulSOFDivide == USB_SOF_TICK_DIVIDE)
+        {
+            //
+            // Yes - reset the divider and call the SOF tick handler.
+            //
+            ulSOFDivide = 0;
+            InternalUSBStartOfFrameTick(USB_SOF_TICK_DIVIDE);
+        }
+    }
+
+    //
+    // Get the current endpoint interrupt status.
+    //
+    ulStatus = MAP_USBIntStatusEndpoint(USB0_BASE);
+
+    //
+    // Handle end point 0 interrupts.
+    //
+    if(ulStatus & USB_INTEP_0)
+    {
+        USBHCDEnumHandler();
+    }
+
+    //
+    // Check to see if any uDMA transfers are pending
+    //
+    for(ulIdx = 0; ulIdx < MAX_NUM_PIPES; ulIdx++)
+    {
+        if((g_ulDMAPending == 0) && (ulStatus == 0))
+        {
+            break;
+        }
+
+        //
+        // Check each pipe to see if uDMA is pending
+        //
+        if(g_ulDMAPending & (DMA_PEND_RECEIVE_FLAG << ulIdx))
+        {
+            //
+            // Handle the case where the pipe is reading
+            //
+            if(g_sUSBHCD.USBINPipes[ulIdx].eState == PIPE_READING)
+            {
+                //
+                // If the uDMA channel transfer is complete, send an ack.
+                //
+                if(uDMAChannelModeGet(UDMA_CHANNEL_USBEP1RX + (ulIdx * 2))
+                        == UDMA_MODE_STOP)
+                {
+                    MAP_USBHostEndpointDataAck(USB0_BASE,
+                                               INDEX_TO_USB_EP(ulIdx + 1));
+                    g_ulDMAPending &= ~(DMA_PEND_RECEIVE_FLAG << ulIdx);
+
+                    //
+                    // If using uDMA then the endpoint status int will not
+                    // occur.  So process the data ready event here.
+                    //
+                    g_sUSBHCD.USBINPipes[ulIdx].eState = PIPE_DATA_READY;
+                    ulEvent = USB_EVENT_RX_AVAILABLE;
+
+                    //
+                    // Only call a handler if one is present.
+                    //
+                    if(g_sUSBHCD.USBINPipes[ulIdx].pfnCallback)
+                    {
+                        g_sUSBHCD.USBINPipes[ulIdx].pfnCallback(
+                            IN_PIPE_HANDLE(ulIdx), ulEvent);
+                    }
+                }
+            }
+        }
+
+        //
+        // Check for a pending DMA transmit transaction.
+        //
+        if(g_ulDMAPending & (DMA_PEND_TRANSMIT_FLAG << ulIdx))
+        {
+            //
+            // Handle the case where the pipe is writing
+            //
+            if(g_sUSBHCD.USBOUTPipes[ulIdx].eState == PIPE_WRITING)
+            {
+                //
+                // If the uDMA channel transfer is complete, then tell
+                // the USB controller to go ahead and send the data
+                //
+                if(uDMAChannelModeGet(UDMA_CHANNEL_USBEP1TX + (ulIdx * 2))
+                        == UDMA_MODE_STOP)
+                {
+                    MAP_USBEndpointDataSend(USB0_BASE,
+                                            INDEX_TO_USB_EP(ulIdx + 1),
+                                            USB_TRANS_OUT);
+                    g_ulDMAPending &= ~(DMA_PEND_TRANSMIT_FLAG << ulIdx);
+                }
+            }
+        }
+
+        //
+        // Check the next pipe, the first time through this will clear out
+        // any interrupts dealing with endpoint zero since it was handled above.
+        //
+        ulStatus >>= 1;
+
+        //
+        // Check the status of the transmit(OUT) pipes.
+        //
+        if(ulStatus & 1)
+        {
+            //
+            // Read the status of the endpoint connected to this pipe.
+            //
+            ulEPStatus = MAP_USBEndpointStatus(USB0_BASE,
+                                               INDEX_TO_USB_EP(ulIdx + 1));
+
+            //
+            // Check if the device stalled the request.
+            //
+            if(ulEPStatus & USB_HOST_OUT_STALL)
+            {
+                //
+                // Clear the stall condition on this endpoint pipe.
+                //
+                MAP_USBHostEndpointStatusClear(USB0_BASE,
+                                               INDEX_TO_USB_EP(ulIdx + 1),
+                                               USB_HOST_OUT_STALL);
+
+                //
+                // Save the STALLED state.
+                //
+                g_sUSBHCD.USBOUTPipes[ulIdx].eState = PIPE_STALLED;
+
+                //
+                // Notify the pipe that it was stalled.
+                //
+                ulEvent = USB_EVENT_STALL;
+            }
+            else
+            {
+                //
+                // Data was transmitted successfully.
+                //
+                g_sUSBHCD.USBOUTPipes[ulIdx].eState = PIPE_DATA_SENT;
+
+                //
+                // Notify the pipe that its last transaction was completed.
+                //
+                ulEvent = USB_EVENT_TX_COMPLETE;
+            }
+
+            //
+            // Only call a handler if one is present.
+            //
+            if(g_sUSBHCD.USBOUTPipes[ulIdx].pfnCallback)
+            {
+                g_sUSBHCD.USBOUTPipes[ulIdx].pfnCallback(OUT_PIPE_HANDLE(ulIdx),
+                                                         ulEvent);
+            }
+        }
+
+        //
+        // Check the status of the receive(IN) pipes.
+        //
+        if(ulStatus & 0x10000)
+        {
+            //
+            // Clear the status flag for the IN Pipe.
+            //
+            ulStatus &= ~0x10000;
+
+            //
+            // Read the status of the endpoint connected to this pipe.
+            //
+            ulEPStatus = MAP_USBEndpointStatus(USB0_BASE,
+                                               INDEX_TO_USB_EP(ulIdx + 1));
+
+            //
+            // Check if the device stalled the request.
+            //
+            if(ulEPStatus & USB_HOST_IN_STALL)
+            {
+                //
+                // Clear the stall condition on this endpoint pipe.
+                //
+                MAP_USBHostEndpointStatusClear(USB0_BASE,
+                                               INDEX_TO_USB_EP(ulIdx + 1),
+                                               USB_HOST_IN_STALL);
+
+                //
+                // Save the STALLED state.
+                //
+                g_sUSBHCD.USBINPipes[ulIdx].eState = PIPE_STALLED;
+
+                //
+                // Notify the pipe that it was stalled.
+                //
+                ulEvent = USB_EVENT_STALL;
+            }
+            else
+            {
+                //
+                // Data is available.
+                //
+                g_sUSBHCD.USBINPipes[ulIdx].eState = PIPE_DATA_READY;
+
+                //
+                // Notify the pipe that its last transaction was completed.
+                //
+                ulEvent = USB_EVENT_RX_AVAILABLE;
+            }
+
+            //
+            // Only call a handler if one is present.
+            //
+            if(g_sUSBHCD.USBINPipes[ulIdx].pfnCallback)
+            {
+                g_sUSBHCD.USBINPipes[ulIdx].pfnCallback(IN_PIPE_HANDLE(ulIdx),
+                                                        ulEvent);
+            }
+        }
+    }
+
+    //
+    // If there is an active driver and it has a call back then call it.
+    //
+    if((g_lUSBHActiveDriver >= 0) &&
+       (g_sUSBHCD.pClassDrivers[g_lUSBHActiveDriver]->pfnIntHandler))
+    {
+        g_sUSBHCD.pClassDrivers[g_lUSBHActiveDriver]->
+            pfnIntHandler(g_pvDriverInstance);
+    }
+}
+
+//*****************************************************************************
+//
+//! The USB host mode interrupt handler for controller index 0.
+//!
+//! This the main USB interrupt handler entry point.  This handler will branch
+//! the interrupt off to the appropriate handlers depending on the current
+//! status of the USB controller.   This function must be placed in the
+//! interrupt table in order for the USB Library host stack to function.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USB0HostIntHandler(void)
+{
+    unsigned long ulStatus;
+
+    //
+    // Get the control interrupt status.
+    //
+    ulStatus = MAP_USBIntStatusControl(USB0_BASE);
+
+    //
+    // Call the internal handler to process the interrupts.
+    //
+    USBHostIntHandlerInternal(0, ulStatus);
+}
+
+//*****************************************************************************
+//
+//! This function opens the class driver.
+//!
+//! \param ulIndex specifies which USB controller to use.
+//! \param ulDeviceNum is the device number for the driver to load.
+//!
+//! This function opens the driver needed based on the class value found in
+//! the device's interface descriptor.
+//!
+//! \return This function returns -1 if no driver is found, or it returns the
+//! index of the driver found in the list of host class drivers.
+//
+//*****************************************************************************
+static long
+USBHCDOpenDriver(unsigned long ulIndex, unsigned long ulDeviceNum)
+{
+    long lDriver;
+    unsigned long ulClass;
+    tInterfaceDescriptor *pInterface;
+
+    ASSERT(ulIndex == 0);
+
+    //
+    // Get the interface descriptor.
+    //
+    pInterface = USBDescGetInterface(g_sUSBHCD.USBDevice[0].pConfigDescriptor,
+                                     g_sUSBHCD.USBDevice[0].ulInterface,
+                                     USB_DESC_ANY);
+
+    //
+    // Read the interface class.
+    //
+    ulClass = pInterface->bInterfaceClass;
+
+    //
+    // Search through the Host Class driver list for the devices class.
+    //
+    for(lDriver = 0; lDriver < g_sUSBHCD.ulNumClassDrivers; lDriver++)
+    {
+        //
+        // If a driver was found call the open for this driver and save which
+        // driver is in use.
+        //
+        if(g_sUSBHCD.pClassDrivers[lDriver]->ulInterfaceClass == ulClass)
+        {
+            //
+            // Call the open function for the class driver.
+            //
+            g_pvDriverInstance = g_sUSBHCD.pClassDrivers[lDriver]->pfnOpen(
+                &g_sUSBHCD.USBDevice[0]);
+
+            //
+            // If the driver was successfully loaded then break out of the
+            // loop.
+            //
+            if(g_pvDriverInstance != 0)
+            {
+                break;
+            }
+        }
+    }
+
+    //
+    // If no drivers were found then return -1 to indicate an invalid
+    // driver instance.
+    //
+    if(lDriver == g_sUSBHCD.ulNumClassDrivers)
+    {
+        //
+        // Send an unknown connection event.
+        //
+        SendUnknownConnect(ulClass, 1);
+
+        //
+        // Indicate that no driver was found.
+        //
+        lDriver = -1;
+    }
+
+    return(lDriver);
+}
+
+//*****************************************************************************
+//
+// This function will send an event to a registered event driver.
+//
+// \param ulIndex is one of the USB_EVENT_* values.
+//
+// This function is only used internally to the USB library and will check
+// if an event driver is registered and send on the event.
+//
+// Note: This function should not be called outside of the USB library.
+//
+// \return None.
+//
+//*****************************************************************************
+void
+InternalUSBHCDSendEvent(unsigned long ulEvent)
+{
+    //
+    // Make sure that an event driver has been registered.
+    //
+    if((g_sUSBHCD.lEventDriver != -1) &&
+       (g_sUSBHCD.pClassDrivers[g_sUSBHCD.lEventDriver]->pfnIntHandler))
+    {
+        //
+        // Send an event to the application.
+        //
+        g_sUSBHCD.EventInfo.ulEvent = ulEvent;
+
+        g_sUSBHCD.pClassDrivers[g_sUSBHCD.lEventDriver]->pfnIntHandler(
+           &g_sUSBHCD.EventInfo);
+    }
+}
+
+
+//*****************************************************************************
+//
+// This function handles the necessary clean up for device disconnect.
+//
+// \param ulIndex is the device number for the device that was disconnected.
+//
+// This function handles all of the necessary clean up after a device
+// disconnect has been detected by the stack.  This includes calling back the
+// appropriate driver if necessary.
+//
+// \return None.
+//
+//*****************************************************************************
+static void
+USBHCDDeviceDisconnected(unsigned long ulIndex)
+{
+    ASSERT(ulIndex == 0);
+
+    if(g_sUSBHCD.USBDevice[0].pConfigDescriptor)
+    {
+        //
+        // Invalidate the configuration descriptor.
+        //
+        g_sUSBHCD.USBDevice[0].pConfigDescriptor = 0;
+    }
+
+    //
+    // Reset the max packet size so that this will be re-read from new devices.
+    //
+    g_sUSBHCD.USBDevice[0].DeviceDescriptor.bMaxPacketSize0 = 0;
+
+    //
+    // No longer have a device descriptor.
+    //
+    g_sUSBHCD.USBDevice[0].DeviceDescriptor.bLength = 0;
+
+    //
+    // No longer addressed.
+    //
+    g_sUSBHCD.USBDevice[0].ulAddress = 0;
+
+    //
+    // If this was an active driver then close it out.
+    //
+    if(g_lUSBHActiveDriver >= 0)
+    {
+        //
+        // Call the driver Close entry point.
+        //
+        g_sUSBHCD.pClassDrivers[g_lUSBHActiveDriver]->
+            pfnClose(&g_sUSBHCD.USBDevice[0]);
+
+        //
+        // No active driver now present.
+        //
+        g_lUSBHActiveDriver = -1;
+        g_pvDriverInstance = 0;
+    }
+    else
+    {
+        if((g_sUSBHCD.lEventDriver != -1) &&
+           (g_sUSBHCD.pClassDrivers[g_sUSBHCD.lEventDriver]->pfnIntHandler))
+        {
+            //
+            // Send the generic disconnect event.
+            //
+            g_sUSBHCD.EventInfo.ulEvent = USB_EVENT_DISCONNECTED;
+
+            g_sUSBHCD.pClassDrivers[g_sUSBHCD.lEventDriver]->pfnIntHandler(
+               &g_sUSBHCD.EventInfo);
+
+            //
+            // Reset the class and the instance.
+            //
+            g_sUSBHCD.ulClass = USB_CLASS_EVENTS;
+            g_sUSBHCD.EventInfo.ulInstance = 0;
+        }
+    }
+
+    //
+    // This call is necessary for OTG controllers to know that the host
+    // stack has completed handling the disconnect of the device before
+    // removing power and returning to a state that can allow OTG
+    // negotiations once again.
+    //
+    if(g_eUSBMode == USB_MODE_OTG)
+    {
+        OTGDeviceDisconnect(0);
+    }
+}
+
+//*****************************************************************************
+//
+//! This function is the main routine for the Host Controller Driver.
+//!
+//! This function is the main routine for the host controller driver, and must
+//! be called periodically by the main application outside of a callback
+//! context.  This allows for a simple cooperative system to access the the
+//! host controller driver interface without the need for an RTOS.  All time
+//! critical operations are handled in interrupt context but all blocking
+//! operations are run from the this function to allow them to block and wait
+//! for completion without holding off other interrupts.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHCDMain(void)
+{
+    unsigned long ulIntState;
+    tUSBHDeviceState eOldState;
+
+    //
+    // Save the old state to detect changes properly.
+    //
+    eOldState = g_sUSBHCD.eDeviceState[0];
+
+    //
+    // Fix up the state if any important interrupt events occurred.
+    //
+    if(g_ulUSBHIntEvents)
+    {
+        //
+        // Perform this fixup with interrupts disabled to prevent race
+        // conditions related to g_ulUSBHIntEvents.
+        //
+        ulIntState = MAP_IntMasterDisable();
+
+        if(g_ulUSBHIntEvents & INT_EVENT_POWER_FAULT)
+        {
+            //
+            // A power fault has occurred so notify the application.
+            //
+            if((g_sUSBHCD.lEventDriver != -1) &&
+               (g_sUSBHCD.pClassDrivers[g_sUSBHCD.lEventDriver]->pfnIntHandler))
+            {
+                //
+                // Send the generic power fault event.
+                //
+                g_sUSBHCD.EventInfo.ulEvent = USB_EVENT_POWER_FAULT;
+
+                g_sUSBHCD.pClassDrivers[g_sUSBHCD.lEventDriver]->pfnIntHandler(
+                   &g_sUSBHCD.EventInfo);
+            }
+
+            g_sUSBHCD.eDeviceState[0] = HCD_POWER_FAULT;
+        }
+        else if(g_ulUSBHIntEvents & INT_EVENT_VBUS_ERR)
+        {
+            //
+            // A VBUS error has occurred.  This event trumps connect and
+            // disconnect since it will cause a controller reset.
+            //
+            g_sUSBHCD.eDeviceState[0] = HCD_VBUS_ERROR;
+        }
+        else
+        {
+            //
+            // Has a device connected?
+            //
+            if(g_ulUSBHIntEvents & INT_EVENT_CONNECT)
+            {
+                g_sUSBHCD.eDeviceState[0] = HCD_DEV_RESET;
+            }
+            else
+            {
+                //
+                // Has a device disconnected?
+                //
+                if(g_ulUSBHIntEvents & INT_EVENT_DISCONNECT)
+                {
+                    g_sUSBHCD.eDeviceState[0] = HCD_DEV_DISCONNECTED;
+                }
+            }
+        }
+
+        //
+        // Clear the flags.
+        //
+        g_ulUSBHIntEvents = 0;
+
+        //
+        // Turn interrupts back on if they were on when we were called.
+        //
+        if(!ulIntState)
+        {
+            MAP_IntMasterEnable();
+        }
+    }
+
+    switch(g_sUSBHCD.eDeviceState[0])
+    {
+        //
+        // There was a power fault condition so shut down and wait for the
+        // application to re-initialized the system.
+        //
+        case HCD_POWER_FAULT:
+        {
+            break;
+        }
+
+        //
+        // There was a VBUS error so handle it.
+        //
+        case HCD_VBUS_ERROR:
+        {
+            //
+            // Disable USB interrupts.
+            //
+            MAP_IntDisable(INT_USB0);
+
+            //
+            // If there was a device in any state of connection then indicate
+            // that it has been disconnected.
+            //
+            if((eOldState != HCD_IDLE) && (eOldState != HCD_POWER_FAULT))
+            {
+                //
+                // Handle device disconnect.
+                //
+                USBHCDDeviceDisconnected(0);
+            }
+
+            //
+            // Reset the controller.
+            //
+            MAP_SysCtlPeripheralReset(SYSCTL_PERIPH_USB0);
+
+            //
+            // Wait for 100ms before trying to re-power the device.
+            //
+            MAP_SysCtlDelay(g_ulTickms * 100);
+
+            //
+            // Re-initialize the HCD.
+            //
+            USBHCDInitInternal(0, g_sUSBHCD.pvPool, g_sUSBHCD.ulPoolSize);
+
+            break;
+        }
+        //
+        // Trigger a reset to the connected device.
+        //
+        case HCD_DEV_RESET:
+        {
+            //
+            // Trigger a Reset.
+            //
+            USBHCDReset(0);
+
+            //
+            // The state moves to connected but not configured.
+            //
+            g_sUSBHCD.eDeviceState[0] = HCD_DEV_CONNECTED;
+
+            break;
+        }
+        //
+        // Device connection has been established now start enumerating
+        // the device.
+        //
+        case HCD_DEV_CONNECTED:
+        {
+            //
+            // First check if we have read the device descriptor at all
+            // before proceeding.
+            //
+            if(g_sUSBHCD.USBDevice[0].DeviceDescriptor.bLength == 0)
+            {
+                //
+                // Initialize a request for the device descriptor.
+                //
+                if(USBHCDGetDeviceDescriptor(0, &g_sUSBHCD.USBDevice[0]) == 0)
+                {
+                    //
+                    // If the device descriptor cannot be read then the device
+                    // will be treated as unknown.
+                    //
+                    g_sUSBHCD.eDeviceState[0] = HCD_DEV_ERROR;
+
+                    //
+                    // Send an unknown connection event.
+                    //
+                    SendUnknownConnect(0, 1);
+                }
+            }
+            //
+            // If we have the device descriptor then move on to setting
+            // the address of the device.
+            //
+            else if(g_sUSBHCD.USBDevice[0].ulAddress == 0)
+            {
+                //
+                // Send the set address command.
+                //
+                USBHCDSetAddress(1);
+
+                //
+                // Save the address.
+                //
+                g_sUSBHCD.USBDevice[0].ulAddress = 1;
+
+                //
+                // Move on to the addressed state.
+                //
+                g_sUSBHCD.eDeviceState[0] = HCD_DEV_ADDRESSED;
+            }
+            break;
+        }
+        case HCD_DEV_ADDRESSED:
+        {
+            //
+            // First check if we have read the configuration descriptor.
+            //
+            if (g_sUSBHCD.USBDevice[0].pConfigDescriptor == 0)
+            {
+                //
+                // Initialize a request for the device descriptor.
+                //
+                if(USBHCDGetConfigDescriptor(0, &g_sUSBHCD.USBDevice[0]) == 0)
+                {
+                    //
+                    // If the device descriptor cannot be read then the device
+                    // will be treated as unknown.
+                    //
+                    g_sUSBHCD.eDeviceState[0] = HCD_DEV_ERROR;
+
+                    //
+                    // Send an unknown connection event.
+                    //
+                    SendUnknownConnect(0, 1);
+                }
+            }
+            //
+            // Now have addressed and received the device configuration,
+            // so get ready to set the device configuration.
+            //
+            else
+            {
+                //
+                // Use the first configuration to set the device
+                // configuration.
+                //
+                USBHCDSetConfig(0, (unsigned long)&g_sUSBHCD.USBDevice[0], 1);
+
+                //
+                // Move on to the configured state.
+                //
+                g_sUSBHCD.eDeviceState[0] = HCD_DEV_CONFIGURED;
+
+                //
+                // Open the driver for device 0.
+                //
+                g_lUSBHActiveDriver = USBHCDOpenDriver(0, 0);
+            }
+            break;
+        }
+        //
+        // The device was making a request and is now complete.
+        //
+        case HCD_DEV_REQUEST:
+        {
+            g_sUSBHCD.eDeviceState[0] = HCD_DEV_CONNECTED;
+            break;
+        }
+        //
+        // The strings are currently not accessed.
+        //
+        case HCD_DEV_GETSTRINGS:
+        {
+            break;
+        }
+        //
+        // Basically Idle at this point.
+        //
+        case HCD_DEV_DISCONNECTED:
+        {
+            //
+            // Handle device disconnect.
+            //
+            USBHCDDeviceDisconnected(0);
+
+            //
+            // Return to the Idle state.
+            //
+            g_sUSBHCD.eDeviceState[0] = HCD_IDLE;
+            break;
+        }
+
+        //
+        // Connection and enumeration is complete so allow this function
+        // to exit.
+        //
+        case HCD_DEV_CONFIGURED:
+        {
+            break;
+        }
+
+        //
+        // Poorly behaving device are in limbo in this state until removed.
+        //
+        case HCD_DEV_ERROR:
+        {
+            g_ulUSBHIntEvents |= INT_EVENT_DISCONNECT;
+            g_sUSBHCD.eDeviceState[0] = HCD_IDLE;
+            break;
+        }
+        default:
+        {
+            break;
+        }
+    }
+}
+
+//*****************************************************************************
+//
+//! This function completes a control transaction to a device.
+//!
+//! \param ulIndex is the controller index to use for this transfer.
+//! \param pSetupPacket is the setup request to be sent.
+//! \param ulDevAddress is the address of the device for this request.
+//! \param pData is the data to send for OUT requests or the receive buffer
+//! for IN requests.
+//! \param ulSize is the size of the buffer in pData.
+//! \param ulMaxPacketSize is the maximum packet size for the device for this
+//! request.
+//!
+//! This function handles the state changes necessary to send a control
+//! transaction to a device.  This function should not be called from within
+//! an interrupt callback as it is a blocking function.
+//!
+//! \return The number of bytes of data that were sent or received as a result
+//! of this request.
+//
+//*****************************************************************************
+unsigned long
+USBHCDControlTransfer(unsigned long ulIndex, tUSBRequest *pSetupPacket,
+                      unsigned long ulDevAddress, unsigned char *pData,
+                      unsigned long ulSize, unsigned long ulMaxPacketSize)
+{
+    unsigned long ulRemaining;
+    unsigned long ulDataSize;
+
+    ASSERT(g_sUSBHEP0State.eState == EP0_STATE_IDLE);
+    ASSERT(ulIndex == 0);
+
+    //
+    // Initialize the state of the data for this request.
+    //
+    g_sUSBHEP0State.pData = pData;
+    g_sUSBHEP0State.ulBytesRemaining = ulSize;
+    g_sUSBHEP0State.ulDataSize = ulSize;
+
+    //
+    // Set the maximum packet size.
+    //
+    g_sUSBHEP0State.ulMaxPacketSize = ulMaxPacketSize;
+
+    //
+    // Save the current address.
+    //
+    g_sUSBHEP0State.ulDevAddress = ulDevAddress;
+
+    //
+    // Set the address the host will used to communicate with the device.
+    //
+    MAP_USBHostAddrSet(USB0_BASE, USB_EP_0, g_sUSBHEP0State.ulDevAddress,
+                       USB_EP_HOST_OUT);
+
+    //
+    // Put the data in the correct FIFO.
+    //
+    MAP_USBEndpointDataPut(USB0_BASE, USB_EP_0, (unsigned char *)pSetupPacket,
+                           sizeof(tUSBRequest));
+
+    //
+    // If this is an IN request, change to that state.
+    //
+    if(pSetupPacket->bmRequestType & USB_RTYPE_DIR_IN)
+    {
+        g_sUSBHEP0State.eState = EP0_STATE_SETUP_IN;
+    }
+    else
+    {
+        //
+        // If there is no data then this is not an OUT request.
+        //
+        if(ulSize != 0)
+        {
+            //
+            // Since there is data, this is an OUT request.
+            //
+            g_sUSBHEP0State.eState = EP0_STATE_SETUP_OUT;
+        }
+        else
+        {
+            //
+            // Otherwise this request has no data and just a status phase.
+            //
+            g_sUSBHEP0State.eState = EP0_STATE_STATUS_IN;
+        }
+    }
+
+    //
+    // Send the Setup packet.
+    //
+    MAP_USBEndpointDataSend(USB0_BASE, USB_EP_0, USB_TRANS_SETUP);
+
+    //
+    // Block until endpoint 0 returns to the IDLE state.
+    //
+    while(g_sUSBHEP0State.eState != EP0_STATE_IDLE)
+    {
+        if(g_sUSBHEP0State.eState == EP0_STATE_ERROR)
+        {
+            return(0);
+        }
+
+        //
+        // If we aborted the transfer due to an error, tell the caller
+        // that no bytes were transferred.
+        //
+        if(g_ulUSBHIntEvents & (INT_EVENT_VBUS_ERR | INT_EVENT_DISCONNECT))
+        {
+            return(0);
+        }
+    }
+
+    //
+    // Calculate and return the number of bytes that were sent or received.
+    // The extra copy into local variables is required to prevent some
+    // compilers from warning about undefined order of volatile access.
+    //
+    ulDataSize = g_sUSBHEP0State.ulDataSize;
+    ulRemaining = g_sUSBHEP0State.ulBytesRemaining;
+
+    return(ulDataSize - ulRemaining);
+}
+
+//*****************************************************************************
+//
+// This is the endpoint 0 interrupt handler.
+//
+// \return None.
+//
+//*****************************************************************************
+static void
+USBHCDEnumHandler(void)
+{
+    unsigned long ulEPStatus;
+    unsigned long ulDataSize;
+
+    //
+    // Get the end point 0 status.
+    //
+    ulEPStatus = MAP_USBEndpointStatus(USB0_BASE, USB_EP_0);
+
+    //
+    // If there was an error then go to the error state.
+    //
+    if(ulEPStatus == USB_HOST_EP0_ERROR)
+    {
+        //
+        // Clear this status indicating that the status packet was
+        // received.
+        //
+        MAP_USBHostEndpointStatusClear(USB0_BASE, USB_EP_0, USB_HOST_EP0_ERROR);
+        MAP_USBFIFOFlush(USB0_BASE, USB_EP_0, 0);
+
+        //
+        // Just go back to the idle state.
+        //
+        g_sUSBHEP0State.eState = EP0_STATE_ERROR;
+
+        return;
+    }
+
+    switch(g_sUSBHEP0State.eState)
+    {
+        //
+        // Handle the status state, this is a transitory state from
+        // USB_STATE_TX or USB_STATE_RX back to USB_STATE_IDLE.
+        //
+        case EP0_STATE_STATUS:
+        {
+            //
+            // Handle the case of a received status packet.
+            //
+            if(ulEPStatus & (USB_HOST_EP0_RXPKTRDY | USB_HOST_EP0_STATUS))
+            {
+                //
+                // Clear this status indicating that the status packet was
+                // received.
+                //
+                MAP_USBHostEndpointStatusClear(USB0_BASE, USB_EP_0,
+                                               (USB_HOST_EP0_RXPKTRDY |
+                                                USB_HOST_EP0_STATUS));
+            }
+
+            //
+            // Just go back to the idle state.
+            //
+            g_sUSBHEP0State.eState = EP0_STATE_IDLE;
+
+            break;
+        }
+
+        //
+        // This state triggers a STATUS IN request from the device.
+        //
+        case EP0_STATE_STATUS_IN:
+        {
+            //
+            // Generate an IN request from the device.
+            //
+            MAP_USBHostRequestStatus(USB0_BASE);
+
+            //
+            // Change to the status phase and wait for the response.
+            //
+            g_sUSBHEP0State.eState =  EP0_STATE_STATUS;
+
+            break;
+        }
+
+        //
+        // In the IDLE state the code is waiting to receive data from the host.
+        //
+        case EP0_STATE_IDLE:
+        {
+            break;
+        }
+
+        //
+        // Data is still being sent to the host so handle this in the
+        // EP0StateTx() function.
+        //
+        case EP0_STATE_SETUP_OUT:
+        {
+            //
+            // Send remaining data if necessary.
+            //
+            USBHCDEP0StateTx();
+
+            break;
+        }
+
+        //
+        // Handle the receive state for commands that are receiving data on
+        // endpoint 0.
+        //
+        case EP0_STATE_SETUP_IN:
+        {
+            //
+            // Generate a new IN request to the device.
+            //
+            MAP_USBHostRequestIN(USB0_BASE, USB_EP_0);
+
+            //
+            // Proceed to the RX state to receive the requested data.
+            //
+            g_sUSBHEP0State.eState =  EP0_STATE_RX;
+
+            break;
+        }
+
+        //
+        // The endpoint remains in this state until all requested data has
+        // been received.
+        //
+        case EP0_STATE_RX:
+        {
+            //
+            // There was a stall on endpoint 0 so go back to the idle state
+            // as this command has been terminated.
+            //
+            if(ulEPStatus & USB_HOST_EP0_RX_STALL)
+            {
+                g_sUSBHEP0State.eState = EP0_STATE_IDLE;
+
+                //
+                // Clear the stalled state on endpoint 0.
+                //
+                MAP_USBHostEndpointStatusClear(USB0_BASE, USB_EP_0, ulEPStatus);
+                break;
+            }
+            //
+            // Set the number of bytes to get out of this next packet.
+            //
+            if(g_sUSBHEP0State.ulBytesRemaining > MAX_PACKET_SIZE_EP0)
+            {
+                //
+                // Don't send more than EP0_MAX_PACKET_SIZE bytes.
+                //
+                ulDataSize = MAX_PACKET_SIZE_EP0;
+            }
+            else
+            {
+                //
+                // There was space so send the remaining bytes.
+                //
+                ulDataSize = g_sUSBHEP0State.ulBytesRemaining;
+            }
+
+            if(ulDataSize != 0)
+            {
+                //
+                // Get the data from the USB controller end point 0.
+                //
+                MAP_USBEndpointDataGet(USB0_BASE, USB_EP_0,
+                                       g_sUSBHEP0State.pData,
+                                       &ulDataSize);
+            }
+
+            //
+            // Advance the pointer.
+            //
+            g_sUSBHEP0State.pData += ulDataSize;
+
+            //
+            // Decrement the number of bytes that are being waited on.
+            //
+            g_sUSBHEP0State.ulBytesRemaining -= ulDataSize;
+
+            //
+            // Need to ack the data on end point 0 in this case
+            // without setting data end.
+            //
+            MAP_USBHostEndpointDataAck(USB0_BASE, USB_EP_0);
+
+            //
+            // If there was not more than the maximum packet size bytes of data
+            // the this was a short packet and indicates that this transfer is
+            // complete.  If there were exactly g_sUSBHEP0State.ulMaxPacketSize
+            // remaining then there still needs to be null packet sent before
+            // this transfer is complete.
+            //
+            if((ulDataSize < g_sUSBHEP0State.ulMaxPacketSize) ||
+               (g_sUSBHEP0State.ulBytesRemaining == 0))
+            {
+                //
+                // Return to the idle state.
+                //
+                g_sUSBHEP0State.eState =  EP0_STATE_STATUS;
+
+                //
+                // No more data.
+                //
+                g_sUSBHEP0State.pData = 0;
+
+                //
+                // Send a null packet to acknowledge that all data was received.
+                //
+                MAP_USBEndpointDataSend(USB0_BASE, USB_EP_0, USB_TRANS_STATUS);
+            }
+            else
+            {
+                //
+                // Request more data.
+                //
+                MAP_USBHostRequestIN(USB0_BASE, USB_EP_0);
+            }
+            break;
+        }
+
+        //
+        // The device stalled endpoint zero so check if the stall needs to be
+        // cleared once it has been successfully sent.
+        //
+        case EP0_STATE_STALL:
+        {
+            //
+            // Reset the global end point 0 state to IDLE.
+            //
+            g_sUSBHEP0State.eState = EP0_STATE_IDLE;
+
+            break;
+        }
+
+        //
+        // Halt on an unknown state, but only in DEBUG builds.
+        //
+        default:
+        {
+            ASSERT(0);
+            break;
+        }
+    }
+}
+
+//*****************************************************************************
+//
+// This internal function handles sending data on endpoint 0.
+//
+// \return None.
+//
+//*****************************************************************************
+static void
+USBHCDEP0StateTx(void)
+{
+    unsigned long ulNumBytes;
+    unsigned char *pData;
+
+    //
+    // In the TX state on endpoint 0.
+    //
+    g_sUSBHEP0State.eState = EP0_STATE_SETUP_OUT;
+
+    //
+    // Set the number of bytes to send this iteration.
+    //
+    ulNumBytes = g_sUSBHEP0State.ulBytesRemaining;
+
+    //
+    // Limit individual transfers to 64 bytes.
+    //
+    if(ulNumBytes > 64)
+    {
+        ulNumBytes = 64;
+    }
+
+    //
+    // Save the pointer so that it can be passed to the USBEndpointDataPut()
+    // function.
+    //
+    pData = (unsigned char *)g_sUSBHEP0State.pData;
+
+    //
+    // Advance the data pointer and counter to the next data to be sent.
+    //
+    g_sUSBHEP0State.ulBytesRemaining -= ulNumBytes;
+    g_sUSBHEP0State.pData += ulNumBytes;
+
+    //
+    // Put the data in the correct FIFO.
+    //
+    MAP_USBEndpointDataPut(USB0_BASE, USB_EP_0, pData, ulNumBytes);
+
+    //
+    // If this is exactly 64 then don't set the last packet yet.
+    //
+    if(ulNumBytes == 64)
+    {
+        //
+        // There is more data to send or exactly 64 bytes were sent, this
+        // means that there is either more data coming or a null packet needs
+        // to be sent to complete the transaction.
+        //
+        MAP_USBEndpointDataSend(USB0_BASE, USB_EP_0, USB_TRANS_OUT);
+    }
+    else
+    {
+        //
+        // Send the last bit of data.
+        //
+        MAP_USBEndpointDataSend(USB0_BASE, USB_EP_0, USB_TRANS_OUT);
+
+        //
+        // Now go to the status state and wait for the transmit to complete.
+        //
+        g_sUSBHEP0State.eState = EP0_STATE_STATUS_IN;
+    }
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/src/platform/lm3s/usblib/host/usbhscsi.c b/src/platform/lm3s/usblib/host/usbhscsi.c
new file mode 100755
index 00000000..fc0acba5
--- /dev/null
+++ b/src/platform/lm3s/usblib/host/usbhscsi.c
@@ -0,0 +1,778 @@
+//*****************************************************************************
+//
+// usbhscsi.c - USB host SCSI layer used by the USB host MSC driver.
+//
+// Copyright (c) 2008-2011 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 7611 of the Stellaris USB Library.
+//
+//*****************************************************************************
+
+#include "inc/hw_types.h"
+#include "usblib/usblib.h"
+#include "usblib/usbmsc.h"
+#include "usblib/host/usbhost.h"
+#include "usblib/host/usbhmsc.h"
+#include "usblib/host/usbhscsi.h"
+
+//*****************************************************************************
+//
+//! \addtogroup usblib_host_class
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// This is the data verify tag passed between requests.
+//
+//*****************************************************************************
+#define CBW_TAG_VALUE           0x54231990
+
+//*****************************************************************************
+//
+//! This function is used to issue SCSI commands via USB.
+//!
+//! \param ulInPipe is the USB IN pipe to use for this command.
+//! \param ulOutPipe is the USB OUT pipe to use for this command.
+//! \param pSCSICmd is the SCSI command structure to send.
+//! \param pucData is pointer to the command data to be sent.
+//! \param pulSize is the number of bytes is the number of bytes expected or
+//! sent by the command.
+//!
+//! This internal function is used to handle SCSI commands sent by other
+//! functions.  It serves as a layer between the SCSI command and the USB
+//! interface being used to send the command.  The \e pSCSI parameter contains
+//! the SCSI command to send.  For commands that expect data back, the
+//! \e pucData is the buffer to store the data into and \e pulSize is used to
+//! store the amount of data to request as well as used to indicate how many
+//! bytes were filled into the \e pucData buffer on return.  For commands that
+//! are sending data, \e pucData is the data to be sent and \e pulSize is the
+//! number of bytes to send.
+//!
+//! \return This function returns the SCSI status from the command.  The value
+//! will be either \b SCSI_CMD_STATUS_PASS or \b SCSI_CMD_STATUS_FAIL.
+//
+//*****************************************************************************
+static unsigned long
+USBHSCSISendCommand(unsigned long ulInPipe, unsigned long ulOutPipe,
+                    tMSCCBW *pSCSICmd, unsigned char *pucData,
+                    unsigned long *pulSize)
+{
+    tMSCCSW CmdStatus;
+    unsigned long ulBytes;
+
+    //
+    // Initialize the command status.
+    //
+    CmdStatus.dCSWSignature = 0;
+    CmdStatus.dCSWTag = 0;
+    CmdStatus.bCSWStatus = SCSI_CMD_STATUS_FAIL;
+
+    //
+    // Set the CBW signature and tag.
+    //
+    pSCSICmd->dCBWSignature = CBW_SIGNATURE;
+    pSCSICmd->dCBWTag = CBW_TAG_VALUE;
+
+    //
+    // Set the size of the data to be returned by the device.
+    //
+    pSCSICmd->dCBWDataTransferLength = *pulSize;
+
+    //
+    // Send the command.
+    //
+    ulBytes = USBHCDPipeWrite(ulOutPipe,
+                              (unsigned char*)pSCSICmd, sizeof(tMSCCBW));
+
+    //
+    // If no bytes went out then the command failed.
+    //
+    if(ulBytes == 0)
+    {
+        return(SCSI_CMD_STATUS_FAIL);
+    }
+
+    //
+    // Only request data if there is data to request.
+    //
+    if(pSCSICmd->dCBWDataTransferLength != 0)
+    {
+        //
+        // See if this is a read or a write.
+        //
+        if(pSCSICmd->bmCBWFlags & CBWFLAGS_DIR_IN)
+        {
+            //
+            // Read the data back.
+            //
+            *pulSize = USBHCDPipeRead(ulInPipe, pucData, *pulSize);
+        }
+        else
+        {
+            //
+            // Write the data out.
+            //
+            *pulSize = USBHCDPipeWrite(ulOutPipe, pucData, *pulSize);
+        }
+    }
+
+    //
+    // Get the status of the command.
+    //
+    ulBytes = USBHCDPipeRead(ulInPipe, (unsigned char *)&CmdStatus,
+                             sizeof(tMSCCSW));
+
+
+    //
+    // If the status was invalid or did not have the correct signature then
+    // indicate a failure.
+    //
+    if((ulBytes == 0) || (CmdStatus.dCSWSignature != CSW_SIGNATURE) ||
+       (CmdStatus.dCSWTag != CBW_TAG_VALUE))
+    {
+        return(SCSI_CMD_STATUS_FAIL);
+    }
+
+    //
+    // Return the status.
+    //
+    return((unsigned long)CmdStatus.bCSWStatus);
+}
+
+//*****************************************************************************
+//
+//! This will issue the SCSI inquiry command to a device.
+//!
+//! \param ulInPipe is the USB IN pipe to use for this command.
+//! \param ulOutPipe is the USB OUT pipe to use for this command.
+//! \param pucData is the data buffer to return the results into.
+//! \param pulSize is the size of buffer that was passed in on entry and the
+//! number of bytes returned.
+//!
+//! This function should be used to issue a SCSI Inquiry command to a mass
+//! storage device.  To allow for multiple devices, the \e ulInPipe and
+//! \e ulOutPipe parameters indicate which USB pipes to use for this call.
+//!
+//! \note The \e pucData buffer pointer should have at least
+//! \b SCSI_INQUIRY_DATA_SZ bytes of data or this function will overflow the
+//! buffer.
+//!
+//! \return This function returns the SCSI status from the command.  The value
+//! will be either \b SCSI_CMD_STATUS_PASS or \b SCSI_CMD_STATUS_FAIL.
+//
+//*****************************************************************************
+unsigned long
+USBHSCSIInquiry(unsigned long ulInPipe, unsigned long ulOutPipe,
+                unsigned char *pucData, unsigned long *pulSize)
+{
+    tMSCCBW SCSICmd;
+    unsigned long *pulData;
+
+    //
+    // Create a local unsigned long pointer to the command.
+    //
+    pulData = (unsigned long *)SCSICmd.CBWCB;
+
+    //
+    // The number of bytes of data that the host expects to transfer on the
+    // Bulk-In or Bulk-Out endpoint (as indicated by the Direction bit) during
+    // the execution of this command.  If this field is zero, the device and
+    // the host shall transfer no data between the CBW and the associated CSW,
+    // and the device shall ignore the value of the Direction bit in
+    // bmCBWFlags.
+    //
+    *pulSize = SCSI_INQUIRY_DATA_SZ;
+
+    //
+    // This is an IN request.
+    //
+    SCSICmd.bmCBWFlags = CBWFLAGS_DIR_IN;
+
+    //
+    // Only handle LUN 0.
+    //
+    SCSICmd.bCBWLUN = 0;
+
+    //
+    // This is the length of the command itself.
+    //
+    SCSICmd.bCBWCBLength = 6;
+
+    //
+    // Send Inquiry command with no request for vital product data.
+    //
+    pulData[0] = SCSI_INQUIRY_CMD;
+
+    //
+    // Allocation length.
+    //
+    pulData[1] = SCSI_INQUIRY_DATA_SZ;
+    pulData[2] = 0;
+    pulData[3] = 0;
+
+    //
+    // Send the command and get the results.
+    //
+    return(USBHSCSISendCommand(ulInPipe, ulOutPipe, &SCSICmd, pucData,
+                               pulSize));
+}
+
+//*****************************************************************************
+//
+//! This will issue the SCSI read capacity command to a device.
+//!
+//! \param ulInPipe is the USB IN pipe to use for this command.
+//! \param ulOutPipe is the USB OUT pipe to use for this command.
+//! \param pucData is the data buffer to return the results into.
+//! \param pulSize is the size of buffer that was passed in on entry and the
+//! number of bytes returned.
+//!
+//! This function should be used to issue a SCSI Read Capacity command
+//! to a mass storage device that is connected.  To allow for multiple devices,
+//! the \e ulInPipe and \e ulOutPipe parameters indicate which USB pipes to
+//! use for this call.
+//!
+//! \note The \e pucData buffer pointer should have at least
+//! \b SCSI_READ_CAPACITY_SZ bytes of data or this function will overflow the
+//! buffer.
+//!
+//! \return This function returns the SCSI status from the command.  The value
+//! will be either \b SCSI_CMD_STATUS_PASS or \b SCSI_CMD_STATUS_FAIL.
+//
+//*****************************************************************************
+unsigned long
+USBHSCSIReadCapacity(unsigned long ulInPipe, unsigned long ulOutPipe,
+                     unsigned char *pucData, unsigned long *pulSize)
+{
+    tMSCCBW SCSICmd;
+    unsigned long *pulData;
+
+    //
+    // Create a local unsigned long pointer to the command.
+    //
+    pulData = (unsigned long *)SCSICmd.CBWCB;
+
+    //
+    // Set the size of the command data.
+    //
+    *pulSize = SCSI_READ_CAPACITY_SZ;
+
+    //
+    // This is an IN request.
+    //
+    SCSICmd.bmCBWFlags = CBWFLAGS_DIR_IN;
+
+    //
+    // Only handle LUN 0.
+    //
+    SCSICmd.bCBWLUN = 0;
+
+    //
+    // Set the length of the command itself.
+    //
+    SCSICmd.bCBWCBLength = 12;
+
+    //
+    // Only use the first byte and set it to the Read Capacity command.  The
+    // rest are set to 0.
+    //
+    pulData[0] = SCSI_READ_CAPACITY;
+    pulData[1] = 0;
+    pulData[2] = 0;
+    pulData[3] = 0;
+
+    //
+    // Send the command and get the results.
+    //
+    return(USBHSCSISendCommand(ulInPipe, ulOutPipe, &SCSICmd, pucData,
+                               pulSize));
+}
+
+//*****************************************************************************
+//
+//! This will issue the SCSI read capacities command to a device.
+//!
+//! \param ulInPipe is the USB IN pipe to use for this command.
+//! \param ulOutPipe is the USB OUT pipe to use for this command.
+//! \param pucData is the data buffer to return the results into.
+//! \param pulSize is the size of buffer that was passed in on entry and the
+//! number of bytes returned.
+//!
+//! This function should be used to issue a SCSI Read Capacities command
+//! to a mass storage device that is connected.  To allow for multiple devices,
+//! the \e ulInPipe and \e ulOutPipe parameters indicate which USB pipes to
+//! use for this call.
+//!
+//! \return This function returns the SCSI status from the command.  The value
+//! will be either \b SCSI_CMD_STATUS_PASS or \b SCSI_CMD_STATUS_FAIL.
+//
+//*****************************************************************************
+unsigned long
+USBHSCSIReadCapacities(unsigned long ulInPipe, unsigned long ulOutPipe,
+                       unsigned char *pucData, unsigned long *pulSize)
+{
+    tMSCCBW SCSICmd;
+    unsigned long *pulData;
+
+    //
+    // Create a local unsigned long pointer to the command.
+    //
+    pulData = (unsigned long *)SCSICmd.CBWCB;
+
+    //
+    // This is an IN request.
+    //
+    SCSICmd.bmCBWFlags = CBWFLAGS_DIR_IN;
+
+    //
+    // Only handle LUN 0.
+    //
+    SCSICmd.bCBWLUN = 0;
+
+    //
+    // Set the length of the command itself.
+    //
+    SCSICmd.bCBWCBLength = 12;
+
+    //
+    // Only use the first byte and set it to the Read Capacity command.  The
+    // rest are set to 0.
+    //
+    pulData[0] = SCSI_READ_CAPACITIES;
+    pulData[1] = 0;
+    pulData[2] = 0;
+    pulData[3] = 0;
+
+    //
+    // Send the command and get the results.
+    //
+    return(USBHSCSISendCommand(ulInPipe, ulOutPipe, &SCSICmd, pucData,
+                               pulSize));
+}
+
+//*****************************************************************************
+//
+//! This will issue the SCSI Mode Sense(6) command to a device.
+//!
+//! \param ulInPipe is the USB IN pipe to use for this command.
+//! \param ulOutPipe is the USB OUT pipe to use for this command.
+//! \param ulFlags is a combination of flags defining the exact query that is
+//! to be made.
+//! \param pucData is the data buffer to return the results into.
+//! \param pulSize is the size of the buffer on entry and number of bytes read
+//! on exit.
+//!
+//! This function should be used to issue a SCSI Mode Sense(6) command
+//! to a mass storage device.  To allow for multiple devices,the \e ulInPipe
+//! and \e ulOutPipe parameters indicate which USB pipes to use for this call.
+//! The call will return at most the number of bytes in the \e pulSize
+//! parameter, however it can return less and change the \e pulSize parameter
+//! to the number of valid bytes in the \e *pulSize buffer.
+//!
+//! The \e ulFlags parameter is a combination of the following three sets of
+//! definitions:
+//!
+//! One of the following values must be specified:
+//!
+//! - \b SCSI_MS_PC_CURRENT request for current settings.
+//! - \b SCSI_MS_PC_CHANGEABLE request for changeable settings.
+//! - \b SCSI_MS_PC_DEFAULT request for default settings.
+//! - \b SCSI_MS_PC_SAVED request for the saved values.
+//!
+//! One of these following values must also be specified to determine the page
+//! code for the request:
+//!
+//! - \b SCSI_MS_PC_VENDOR is the vendor specific page code.
+//! - \b SCSI_MS_PC_DISCO is the disconnect/reconnect page code.
+//! - \b SCSI_MS_PC_CONTROL is the control page code.
+//! - \b SCSI_MS_PC_LUN is the protocol specific LUN page code.
+//! - \b SCSI_MS_PC_PORT is the protocol specific port page code.
+//! - \b SCSI_MS_PC_POWER is the power condition page code.
+//! - \b SCSI_MS_PC_INFORM is the informational exceptions page code.
+//! - \b SCSI_MS_PC_ALL will request all pages codes supported by the device.
+//!
+//! The last value is optional and supports the following global flag:
+//! - \b SCSI_MS_DBD disables returning block descriptors.
+//!
+//! Example: Request for all current settings.
+//!
+//! \verbatim
+//! SCSIModeSense6(ulInPipe, ulOutPipe,
+//!                SCSI_MS_PC_CURRENT | SCSI_MS_PC_ALL,
+//!                pucData, pulSize);
+//! \endverbatim
+//!
+//! \return This function returns the SCSI status from the command.  The value
+//! will be either \b SCSI_CMD_STATUS_PASS or \b SCSI_CMD_STATUS_FAIL.
+//
+//*****************************************************************************
+unsigned long
+USBHSCSIModeSense6(unsigned long ulInPipe, unsigned long ulOutPipe,
+                   unsigned long ulFlags, unsigned char *pucData,
+                   unsigned long *pulSize)
+{
+    tMSCCBW SCSICmd;
+    unsigned long *pulData;
+
+    //
+    // Create a local unsigned long pointer to the command.
+    //
+    pulData = (unsigned long *)SCSICmd.CBWCB;
+
+    //
+    // This is an IN request.
+    //
+    SCSICmd.bmCBWFlags = CBWFLAGS_DIR_IN;
+
+    //
+    // Only handle LUN 0.
+    //
+    SCSICmd.bCBWLUN = 0;
+
+    //
+    // Set the size of the command data.
+    //
+    SCSICmd.bCBWCBLength = 6;
+
+    //
+    // Set the options for the Mode Sense Command (6).
+    //
+    pulData[0] = (SCSI_MODE_SENSE_6 | ulFlags);
+    pulData[1] = (unsigned char)*pulSize;
+    pulData[2] = 0;
+    pulData[3] = 0;
+
+    //
+    // Send the command and get the results.
+    //
+    return(USBHSCSISendCommand(ulInPipe, ulOutPipe, &SCSICmd, pucData,
+                               pulSize));
+}
+
+//*****************************************************************************
+//
+//! This function issues a SCSI Test Unit Ready command to a device.
+//!
+//! \param ulInPipe is the USB IN pipe to use for this command.
+//! \param ulOutPipe is the USB OUT pipe to use for this command.
+//!
+//! This function is used to issue a SCSI Test Unit Ready command to a device.
+//! This call will simply return the results of issuing this command.
+//!
+//! \return This function returns the results of the SCSI Test Unit Ready
+//! command.  The value will be either \b SCSI_CMD_STATUS_PASS or
+//! \b SCSI_CMD_STATUS_FAIL.
+//
+//*****************************************************************************
+unsigned long
+USBHSCSITestUnitReady(unsigned long ulInPipe, unsigned long ulOutPipe)
+{
+    tMSCCBW SCSICmd;
+    unsigned long ulSize;
+    unsigned long *pulData;
+
+    //
+    // Create a local unsigned long pointer to the command.
+    //
+    pulData = (unsigned long *)SCSICmd.CBWCB;
+
+    //
+    // No data in this command.
+    //
+    ulSize = 0;
+
+    //
+    // This is an IN request.
+    //
+    SCSICmd.bmCBWFlags = CBWFLAGS_DIR_IN;
+
+    //
+    // Only handle LUN 0.
+    //
+    SCSICmd.bCBWLUN = 0;
+
+    //
+    // Set the size of the command data.
+    //
+    SCSICmd.bCBWCBLength = 6;
+
+    //
+    // Set the parameter options.
+    //
+    pulData[0] = SCSI_TEST_UNIT_READY;
+    pulData[1] = 0;
+    pulData[2] = 0;
+    pulData[3] = 0;
+
+    //
+    // Send the command and get the results.
+    //
+    return(USBHSCSISendCommand(ulInPipe, ulOutPipe, &SCSICmd, 0, &ulSize));
+}
+
+//*****************************************************************************
+//
+//! This function issues a SCSI Request Sense command to a device.
+//!
+//! \param ulInPipe is the USB IN pipe to use for this command.
+//! \param ulOutPipe is the USB OUT pipe to use for this command.
+//! \param pucData is the data buffer to return the results into.
+//! \param pulSize is the size of the buffer on entry and number of bytes read
+//! on exit.
+//!
+//! This function is used to issue a SCSI Request Sense command to a device.
+//! It will return the data in the buffer pointed to by \e pucData.  The
+//! parameter \e pulSize should have the allocation size in bytes of the buffer
+//! pointed to by pucData.
+//!
+//! \return This function returns the results of the SCSI Request Sense
+//! command.  The value will be either \b SCSI_CMD_STATUS_PASS or
+//! \b SCSI_CMD_STATUS_FAIL.
+//
+//*****************************************************************************
+unsigned long
+USBHSCSIRequestSense(unsigned long ulInPipe, unsigned long ulOutPipe,
+                     unsigned char *pucData, unsigned long *pulSize)
+{
+    tMSCCBW SCSICmd;
+    unsigned long *pulData;
+
+    //
+    // Create a local unsigned long pointer to the command.
+    //
+    pulData = (unsigned long *)SCSICmd.CBWCB;
+
+    //
+    // This is an IN request.
+    //
+    SCSICmd.bmCBWFlags = CBWFLAGS_DIR_IN;
+
+    //
+    // Only handle LUN 0.
+    //
+    SCSICmd.bCBWLUN = 0;
+
+    //
+    // Set the size of the command data.
+    //
+    SCSICmd.bCBWCBLength = 12;
+
+    //
+    // Set the parameter options.
+    //
+    pulData[0] = SCSI_REQUEST_SENSE;
+    pulData[1] = 18;
+    pulData[2] = 0;
+    pulData[3] = 0;
+
+    //
+    // Send the command and get the results.
+    //
+    return(USBHSCSISendCommand(ulInPipe, ulOutPipe, &SCSICmd, pucData,
+                               pulSize));
+}
+
+//*****************************************************************************
+//
+//! This function issues a SCSI Read(10) command to a device.
+//!
+//! \param ulInPipe is the USB IN pipe to use for this command.
+//! \param ulOutPipe is the USB OUT pipe to use for this command.
+//! \param ulLBA is the logical block address to read.
+//! \param pucData is the data buffer to return the data.
+//! \param pulSize is the size of the buffer on entry and number of bytes read
+//! on exit.
+//! \param ulNumBlocks is the number of contiguous blocks to read from the
+//! device.
+//!
+//! This function is used to issue a SCSI Read(10) command to a device.  The
+//! \e ulLBA parameter specifies the logical block address to read from the
+//! device.  The data from this block will be returned in the buffer pointed to
+//! by \e pucData.  The parameter \e pulSize should indicate enough space to
+//! hold a full block size, or only the first pulSize bytes of the LBA will
+//! be returned.
+//!
+//! \return This function returns the results of the SCSI Read(10) command.
+//! The value will be either \b SCSI_CMD_STATUS_PASS or
+//! \b SCSI_CMD_STATUS_FAIL.
+//
+//*****************************************************************************
+unsigned long
+USBHSCSIRead10(unsigned long ulInPipe, unsigned long ulOutPipe,
+               unsigned long ulLBA, unsigned char *pucData,
+               unsigned long *pulSize, unsigned long ulNumBlocks)
+{
+    tMSCCBW SCSICmd;
+
+    //
+    // This is an IN request.
+    //
+    SCSICmd.bmCBWFlags = CBWFLAGS_DIR_IN;
+
+    //
+    // Only handle LUN 0.
+    //
+    SCSICmd.bCBWLUN = 0;
+
+    //
+    // Set the size of the command data.
+    //
+    SCSICmd.bCBWCBLength = 10;
+
+    //
+    // Set the parameter options.
+    //
+    SCSICmd.CBWCB[0] = SCSI_READ_10;
+
+    //
+    // Clear the reserved field.
+    //
+    SCSICmd.CBWCB[1] = 0;
+
+    //
+    // LBA starts at offset 2.
+    //
+    SCSICmd.CBWCB[2] = (unsigned char)(ulLBA >> 24);
+    SCSICmd.CBWCB[3] = (unsigned char)(ulLBA >> 16);
+    SCSICmd.CBWCB[4] = (unsigned char)(ulLBA >> 8);
+    SCSICmd.CBWCB[5] = (unsigned char)ulLBA;
+
+    //
+    // Clear the reserved field.
+    //
+    SCSICmd.CBWCB[6] = 0;
+
+    //
+    // Transfer length in blocks starts at offset 2.
+    // This also sets the Control value to 0 at offset 9.
+    //
+    SCSICmd.CBWCB[7] = (ulNumBlocks & 0xFF00) >> 8;
+    *((unsigned long *)&SCSICmd.CBWCB[8]) = (ulNumBlocks & 0xFF);
+    *((unsigned long *)&SCSICmd.CBWCB[12]) = 0;
+
+    //
+    // Send the command and get the results.
+    //
+    return(USBHSCSISendCommand(ulInPipe, ulOutPipe, &SCSICmd, pucData,
+                               pulSize));
+}
+
+//*****************************************************************************
+//
+//! This function issues a SCSI Write(10) command to a device.
+//!
+//! This function is used to issue a SCSI Write(10) command to a device.  The
+//! \e ulLBA parameter specifies the logical block address on the device.  The
+//! data to write to this block should be in the buffer pointed to by
+//! \e pucData parameter.  The parameter \e pulSize should indicate the amount
+//! of data to write to the specified LBA.
+//!
+//! \param ulInPipe is the USB IN pipe to use for this command.
+//! \param ulOutPipe is the USB OUT pipe to use for this command.
+//! \param ulLBA is the logical block address to read.
+//! \param pucData is the data buffer to write out.
+//! \param pulSize is the size of the buffer.
+//! \param ulNumBlocks is the number of contiguous blocks to write to the
+//! device.
+//!
+//! \return This function returns the results of the SCSI Write(10) command.
+//! The value will be either \b SCSI_CMD_STATUS_PASS or
+//! \b SCSI_CMD_STATUS_FAIL.
+//
+//*****************************************************************************
+unsigned long
+USBHSCSIWrite10(unsigned long ulInPipe, unsigned long ulOutPipe,
+                unsigned long ulLBA, unsigned char *pucData,
+                unsigned long *pulSize, unsigned long ulNumBlocks)
+{
+    tMSCCBW SCSICmd;
+    unsigned long *pulData;
+
+    //
+    // Create a local unsigned long pointer to the command.
+    //
+    pulData = (unsigned long *)SCSICmd.CBWCB;
+
+    //
+    // This is an IN request.
+    //
+    SCSICmd.bmCBWFlags = CBWFLAGS_DIR_OUT;
+
+    //
+    // Only handle LUN 0.
+    //
+    SCSICmd.bCBWLUN = 0;
+
+    //
+    // Set the size of the command data.
+    //
+    SCSICmd.bCBWCBLength = 10;
+
+    //
+    // Set the parameter options.
+    //
+    SCSICmd.CBWCB[0] = SCSI_WRITE_10;
+
+    //
+    // Clear the reserved field.
+    //
+    SCSICmd.CBWCB[1] = 0;
+
+    //
+    // LBA starts at offset 2.
+    //
+    SCSICmd.CBWCB[2] = (unsigned char)(ulLBA >> 24);
+    SCSICmd.CBWCB[3] = (unsigned char)(ulLBA >> 16);
+    SCSICmd.CBWCB[4] = (unsigned char)(ulLBA >> 8);
+    SCSICmd.CBWCB[5] = (unsigned char)ulLBA;
+
+    //
+    // Clear the reserved field.
+    //
+    SCSICmd.CBWCB[6] = 0;
+
+    //
+    // Set the transfer length in blocks.
+    // This also sets the Control value to 0 at offset 9.
+    //
+    SCSICmd.CBWCB[7] = (ulNumBlocks & 0xFF00) >> 8;
+
+    //
+    // The blocks go into is byte offset 8 or word address 2.
+    //
+    pulData[2] = (ulNumBlocks & 0xFF);
+
+    //
+    // The blocks go into is byte offset 12 or word address 3.
+    //
+    pulData[3] = 0;
+
+    //
+    // Send the command and get the results.
+    //
+    return(USBHSCSISendCommand(ulInPipe, ulOutPipe, &SCSICmd, pucData,
+                               pulSize));
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/src/platform/lm3s/usblib/host/usbhscsi.h b/src/platform/lm3s/usblib/host/usbhscsi.h
new file mode 100755
index 00000000..fa65ef13
--- /dev/null
+++ b/src/platform/lm3s/usblib/host/usbhscsi.h
@@ -0,0 +1,102 @@
+//*****************************************************************************
+//
+// usbhscsi.h - Definitions for the USB host SCSI layer.
+//
+// Copyright (c) 2008-2011 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 7611 of the Stellaris USB Library.
+//
+//*****************************************************************************
+
+#ifndef __USBHSCSI_H__
+#define __USBHSCSI_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+//! \addtogroup usblib_host_class
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Prototypes for the APIs exported by the USB SCSI layer.
+//
+//*****************************************************************************
+extern unsigned long USBHSCSIInquiry(unsigned long ulInPipe,
+                                     unsigned long ulOutPipe,
+                                     unsigned char *pucBuffer,
+                                     unsigned long *pulSize);
+extern unsigned long USBHSCSIReadCapacity(unsigned long ulInPipe,
+                                          unsigned long ulOutPipe,
+                                          unsigned char *pData,
+                                          unsigned long *pulSize);
+extern unsigned long USBHSCSIReadCapacities(unsigned long ulInPipe,
+                                            unsigned long ulOutPipe,
+                                            unsigned char *pData,
+                                            unsigned long *pulSize);
+extern unsigned long USBHSCSIModeSense6(unsigned long ulInPipe,
+                                        unsigned long ulOutPipe,
+                                        unsigned long ulFlags,
+                                        unsigned char *pData,
+                                        unsigned long *pulSize);
+extern unsigned long USBHSCSITestUnitReady(unsigned long ulInPipe,
+                                           unsigned long ulOutPipe);
+extern unsigned long USBHSCSIRequestSense(unsigned long ulInPipe,
+                                          unsigned long ulOutPipe,
+                                          unsigned char *pucData,
+                                          unsigned long *pulSize);
+extern unsigned long USBHSCSIRead10(unsigned long ulInPipe,
+                                    unsigned long ulOutPipe,
+                                    unsigned long ulLBA,
+                                    unsigned char *pucData,
+                                    unsigned long *pulSize,
+                                    unsigned long ulNumBlocks);
+extern unsigned long USBHSCSIWrite10(unsigned long ulInPipe,
+                                     unsigned long ulOutPipe,
+                                     unsigned long ulLBA,
+                                     unsigned char *pucData,
+                                     unsigned long *pulSize,
+                                     unsigned long ulNumBlocks);
+
+//*****************************************************************************
+//
+//! @}
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __USBHSCSI_H__
diff --git a/src/platform/lm3s/usblib/usb-ids.h b/src/platform/lm3s/usblib/usb-ids.h
new file mode 100755
index 00000000..97144278
--- /dev/null
+++ b/src/platform/lm3s/usblib/usb-ids.h
@@ -0,0 +1,62 @@
+//*****************************************************************************
+//
+// usb-ids.h - Definitions of VIDs and PIDs used by Stellaris USB examples.
+//
+// Copyright (c) 2008-2011 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 7611 of the Stellaris USB Library.
+//
+//*****************************************************************************
+
+#ifndef __USBIDS_H__
+#define __USBIDS_H__
+
+//*****************************************************************************
+//
+// TI Stellaris Vendor ID.
+//
+//*****************************************************************************
+#define USB_VID_STELLARIS       0x1cbe
+
+//*****************************************************************************
+//
+// Product IDs.
+//
+//*****************************************************************************
+#define USB_PID_MOUSE           0x0000
+#define USB_PID_KEYBOARD        0x0001
+#define USB_PID_SERIAL          0x0002
+#define USB_PID_BULK            0x0003
+#define USB_PID_SCOPE           0x0004
+#define USB_PID_MSC             0x0005
+#define USB_PID_AUDIO           0x0006
+#define USB_PID_COMP_SERIAL     0x0007
+#define USB_PID_COMP_AUDIO_HID  0x0008
+#define USB_PID_COMP_HID_SER    0x0009
+#define USB_PID_COMP_HID_DFU    0x000A
+#define USB_PID_DFU             0x00FF
+
+#ifndef DEPRECATED
+//*****************************************************************************
+//
+// Deprecated definitions.
+//
+//*****************************************************************************
+#define USB_VID_LUMINARY        USB_VID_STELLARIS
+#endif
+
+#endif /* __USBIDS_H__ */
diff --git a/src/platform/lm3s/usblib/usbaudio.h b/src/platform/lm3s/usblib/usbaudio.h
new file mode 100755
index 00000000..34f9019c
--- /dev/null
+++ b/src/platform/lm3s/usblib/usbaudio.h
@@ -0,0 +1,717 @@
+//*****************************************************************************
+//
+// usbaudio.h - Definitions used by Audio Class devices.
+//
+// Copyright (c) 2009-2011 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 7611 of the Stellaris USB Library.
+//
+//*****************************************************************************
+
+#ifndef __USBAUDIO_H__
+#define __USBAUDIO_H__
+
+
+//*****************************************************************************
+//
+// Standard Audio descriptor sub types.
+//
+//*****************************************************************************
+#define USB_AI_UNDEFINED        0
+#define USB_AI_HEADER           1
+#define USB_AI_INPUT_TERMINAL   2
+#define USB_AI_OUTPUT_TERMINAL  3
+#define USB_AI_MIXER_UNIT       4
+#define USB_AI_SELECTOR_UNIT    5
+#define USB_AI_FEATURE_UNIT     6
+#define USB_AI_PROCESSING_UNIT  7
+#define USB_AI_EXTENSION_UNIT   8
+
+//*****************************************************************************
+//
+// Standard Audio Streaming Interface descriptor types.
+//
+//*****************************************************************************
+#define USB_AS_UNDEFINED        0
+#define USB_AS_GENERAL          1
+#define USB_AS_FORMAT_TYPE      2
+#define USB_AS_FORMAT_SPECIFIC  3
+
+//*****************************************************************************
+//
+// Standard USB terminal types used with audio terminal descriptors.  These
+// are defined in the "Universal Serial Bus Device Class Definition for
+// Terminal Types" version 1.0 released March 18, 1998.
+//
+//*****************************************************************************
+#define USB_TTYPE_UNDEFINED     0x0100
+#define USB_TTYPE_STREAMING     0x0101
+#define USB_TTYPE_VENDOR        0x01ff
+
+#define USB_TTYPE_OUT_UNDEF     0x0300
+#define USB_TTYPE_OUT_SPEAKER   0x0301
+#define USB_TTYPE_OUT_HEADPHONE 0x0302
+#define USB_TTYPE_OUT_DESK_SPKR 0x0304
+#define USB_TTYPE_OUT_ROOM_SPKR 0x0305
+#define USB_TTYPE_OUT_COMM_SPKR 0x0306
+#define USB_TTYPE_OUT_LFE       0x0307
+
+#define USB_TTYPE_EXT_UNDEF     0x0600
+#define USB_TTYPE_EXT_ANALOG    0x0601
+#define USB_TTYPE_EXT_DIGITAL   0x0602
+#define USB_TTYPE_EXT_LINE      0x0603
+#define USB_TTYPE_EXT_LEGACY    0x0604
+#define USB_TTYPE_EXT_SPDIF     0x0605
+#define USB_TTYPE_EXT_1394_DA   0x0606
+#define USB_TTYPE_EXT_1394_DV   0x0607
+
+//*****************************************************************************
+//
+// Audio Interface Subclass Codes
+//
+//*****************************************************************************
+#define USB_ASC_UNDEFINED       0x00
+#define USB_ASC_AUDIO_CONTROL   0x01
+#define USB_ASC_AUDIO_STREAMING 0x02
+#define USB_ASC_MIDI_STREAMING  0x03
+
+//*****************************************************************************
+//
+// Audio Class-Specific Descriptor Types
+// (Table A-4)
+//
+//*****************************************************************************
+#define USB_ACSDT_UNDEFINED     0x20
+#define USB_ACSDT_DEVICE        0x21
+#define USB_ACSDT_CONFIGURATION 0x22
+#define USB_ACSDT_STRING        0x23
+#define USB_ACSDT_INTERFACE     0x24
+#define USB_ACSDT_ENDPOINT      0x25
+
+//*****************************************************************************
+//
+// Audio Class-Specific AC Interface Descriptor Subtypes
+// (Table A-5)
+//
+//*****************************************************************************
+#define USB_ACDSTYPE_UNDEFINED       0x00
+#define USB_ACDSTYPE_HEADER          0x01
+#define USB_ACDSTYPE_IN_TERMINAL     0x02
+#define USB_ACDSTYPE_OUT_TERMINAL    0x03
+#define USB_ACDSTYPE_MIXER_UNIT      0x04
+#define USB_ACDSTYPE_SELECTOR_UNIT   0x05
+#define USB_ACDSTYPE_FEATURE_UNIT    0x06
+#define USB_ACDSTYPE_PROCESSING_UNIT 0x07
+#define USB_ACDSTYPE_EXTENSION_UNIT  0x08
+
+//*****************************************************************************
+//
+// Audio Class-Specific AS Interface Descriptor Subtypes
+// (Table A-6)
+//
+//*****************************************************************************
+#define USB_ASDSTYPE_UNDEFINED          0x00
+#define USB_ASDSTYPE_GENERAL            0x01
+#define USB_ASDSTYPE_FORMAT_TYPE        0x02
+#define USB_ASDSTYPE_FORMAT_SPECIFIC    0x03
+
+//*****************************************************************************
+//
+// Audio Data Format Type I Codes.
+//
+//*****************************************************************************
+#define USB_ADF_UNDEFINED       0x0000
+#define USB_ADF_PCM             0x0001
+#define USB_ADF_PCM8            0x0002
+#define USB_ADF_IEEE_FLOAT      0x0003
+#define USB_ADF_ALAW            0x0004
+#define USB_ADF_MULAW           0x0005
+
+//*****************************************************************************
+//
+// Audio Format Type Codes
+//
+//*****************************************************************************
+#define USB_AF_TYPE_UNDEFINED   0x00
+#define USB_AF_TYPE_TYPE_I      0x01
+#define USB_AF_TYPE_TYPE_II     0x02
+#define USB_AF_TYPE_TYPE_III    0x03
+
+//*****************************************************************************
+//
+// Audio Class-Specific controls used with bmaControls values.
+//
+//*****************************************************************************
+#define USB_ACONTROL_MUTE       0x0001  // Mute
+#define USB_ACONTROL_VOLUME     0x0002  // Volume
+#define USB_ACONTROL_BASS       0x0004  // Bass
+#define USB_ACONTROL_MID        0x0008  // Mid
+#define USB_ACONTROL_TREBLE     0x0010  // Treble
+#define USB_ACONTROL_EQ         0x0020  // Graphic Equalizer
+#define USB_ACONTROL_AGC        0x0040  // Automatic Gain
+#define USB_ACONTROL_DELAY      0x0080  // Delay
+#define USB_ACONTROL_BASS_BOOST 0x0100  // Bass Boost
+#define USB_ACONTROL_LOUD       0x0200  // Loudness
+
+//*****************************************************************************
+//
+// Audio Class-Specific Output terminal types.
+//
+//*****************************************************************************
+#define USB_ATTYPE_UNDEFINED    0x0300  // Output Terminal, undefined Type.
+#define USB_ATTYPE_SPEAKER      0x0301  // A generic speaker.
+#define USB_ATTYPE_HEADPHONES   0x0302  // A head-mounted audio output device.
+#define USB_ATTYPE_HMD          0x0303  // The audio part of a VR head mounted
+                                        // display.
+#define USB_ATTYPE_SPEAKER_DT   0x0304  // Desktop or Monitor speaker(s).
+#define USB_ATTYPE_SPEAKER_RM   0x0305  // Larger room speaker(s).
+#define USB_ATTYPE_SPEAKER_COM  0x0306  // Communications Speaker (phone).
+#define USB_ATTYPE_SPEAKER_LFE  0x0307  // Speaker designed for low frequencies.
+
+//*****************************************************************************
+//
+// USB Audio channel configuration bits for wChannelConfig values.
+// wChannelConfig: a bit field that indicates which spatial locations are
+// present in the cluster. The bit allocations are as follows:
+//
+//*****************************************************************************
+#define USB_CHANNEL_L           0x0001  // Left Front (L)
+#define USB_CHANNEL_R           0x0002  // Right Front (R)
+#define USB_CHANNEL_C           0x0004  // Center Front (C)
+#define USB_CHANNEL_LFE         0x0008  // Low Frequency Enhancement (LFE)
+#define USB_CHANNEL_LS          0x0010  // Left Surround (LS)
+#define USB_CHANNEL_RS          0x0020  // Right Surround (RS)
+#define USB_CHANNEL_LC          0x0040  // Left of Center (LC)
+#define USB_CHANNEL_RC          0x0080  // Right of Center (RC)
+#define USB_CHANNEL_S           0x0100  // Surround (S)
+#define USB_CHANNEL_SL          0x0200  // Side Left (SL)
+#define USB_CHANNEL_SR          0x0400  // Side Right (SR)
+#define USB_CHANNEL_T           0x0800  // Top (T)
+
+//*****************************************************************************
+//
+// Endpoint attributes for Audio Class General type.
+//
+//*****************************************************************************
+#define USB_EP_ATTR_ACG_SAMPLING    0x01    // Sampling Frequency
+#define USB_EP_ATTR_ACG_PITCH       0x02    // Pitch
+#define USB_EP_ATTR_ACG_MAXPACKET   0x80    // MaxPacketsOnly
+
+//*****************************************************************************
+//
+// Indicates the units used for the wLockDelay field for Audio Class General
+// type.
+//
+//*****************************************************************************
+#define USB_EP_LOCKDELAY_UNDEF  0x00    // Undefined
+#define USB_EP_LOCKDELAY_MS     0x01    // Milliseconds
+#define USB_EP_LOCKDELAY_PCM    0x02    // Decoded PCM samples
+
+//*****************************************************************************
+//
+// Audio Class-Specific Request Codes
+//
+//*****************************************************************************
+#define USB_AC_SET_CUR          0x01
+#define USB_AC_SET_MIN          0x02
+#define USB_AC_SET_MAX          0x03
+#define USB_AC_SET_RES          0x04
+#define USB_AC_SET_MEM          0x05
+#define USB_AC_GET_CUR          0x81
+#define USB_AC_GET_MIN          0x82
+#define USB_AC_GET_MAX          0x83
+#define USB_AC_GET_RES          0x84
+#define USB_AC_GET_MEM          0x85
+#define USB_AC_GET_STAT         0xff
+
+#define USB_CS_CONTROL_M        0xff00
+#define USB_CS_CHANNEL_M        0x00ff
+
+//*****************************************************************************
+//
+// Endpoint Control Selectors
+//
+//*****************************************************************************
+#define EP_CONTROL_UNDEFINED    0x0000
+#define SAMPLING_FREQ_CONTROL   0x0100
+#define PITCH_CONTROL           0x0200
+
+//*****************************************************************************
+//
+// Feature Unit Control Selectors
+//
+//*****************************************************************************
+#define FU_CONTROL_UNDEFINED    0x0000
+#define MUTE_CONTROL            0x0100
+#define VOLUME_CONTROL          0x0200
+#define BASS_CONTROL            0x0300
+#define MID_CONTROL             0x0400
+#define TREBLE_CONTROL          0x0500
+#define EQUALIZER_CONTROL       0x0600
+#define AUTOMATIC_GAIN_CONTROL  0x0700
+#define DELAY_CONTROL           0x0800
+#define BASS_BOOST_CONTROL      0x0900
+#define LOUDNESS_CONTROL        0x0A00
+
+//*****************************************************************************
+//
+// All structures defined in this section of the header require byte packing of
+// fields.  This is usually accomplished using the PACKED macro but, for IAR
+// Embedded Workbench, this requires a pragma.
+//
+//*****************************************************************************
+#ifdef ewarm
+#pragma pack(1)
+#endif
+
+//*****************************************************************************
+//
+//! This structure describes the Class-Specific Audio Class Interface Header
+//! Descriptor as defined in Universal Serial Bus Device Class Definition
+//! for Audio Devices Release 1.0.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! The length of this descriptor in bytes.
+    //
+    unsigned char bLength;
+
+    //
+    //! The type of the descriptor.  For an interface descriptor, this will
+    //! be USB_DTYPE_CS_INTERFACE (36).
+    //
+    unsigned char bDescriptorType;
+
+    //
+    //! This will be USB_DSUBTYPE_HEADER for the header.
+    //
+    unsigned char bDescriptorSubtype;
+
+    //
+    //! Audio Device Class Specification Release Number in Binary-Coded
+    //! Decimal.
+    //
+    unsigned short bcdADC;
+
+    //
+    //! Total number of bytes returned for the class-specific AudioControl
+    //! interface descriptor. Includes the combined length of this descriptor
+    //! header and all Unit and Terminal descriptors.
+    //
+    unsigned short wTotalLength;
+
+    //
+    //! The number of AudioStreaming and MIDIStreaming interfaces in the Audio
+    //! Interface Collection to which this AudioControl interface belongs.
+    //
+    unsigned char bInCollection;
+
+    //
+    //! Interface number of the first AudioStreaming or MIDIStreaming interface
+    //! in the Collection.
+    //
+    unsigned char baInterfaceNr;
+}
+PACKED tACHeader;
+
+//*****************************************************************************
+//
+// These are the possible bits set in the tACInputTerminal.wChannelConfig
+// value.
+//
+//*****************************************************************************
+#define USB_AC_CC_LEFT          0x0001
+#define USB_AC_CC_RIGHT         0x0002
+#define USB_AC_CC_CENTER        0x0004
+#define USB_AC_CC_LFE           0x0008
+#define USB_AC_CC_LEFTSURROUND  0x0010
+#define USB_AC_CC_RIGHTSURROUND 0x0020
+#define USB_AC_CC_LEFT_CENTER   0x0040
+#define USB_AC_CC_RIGHT_CENTER  0x0080
+#define USB_AC_CC_SURROUND      0x0100
+#define USB_AC_CC_SIDE_LEFT     0x0200
+#define USB_AC_CC_SIDE_RIGHT    0x0400
+#define USB_AC_CC_TOP           0x0800
+
+//*****************************************************************************
+//
+//! This structure describes the Feature Unit Descriptor as defined in
+//! Universal Serial Bus Device Class Definition for Audio Devices Release 1.0.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! The length of this descriptor in bytes.
+    //
+    unsigned char bLength;
+
+    //
+    //! The type of the descriptor.  For an interface descriptor, this will
+    //! be USB_DTYPE_CS_INTERFACE (36).
+    //
+    unsigned char bDescriptorType;
+
+    //
+    //! This will be USB_DSUBTYPE_IN_TERM for the header.
+    //
+    unsigned char bDescriptorSubtype;
+
+    //
+    //! Constant uniquely identifying the Unit within the audio function. This
+    //! value is used in all requests to address this Unit.
+    //
+    unsigned char bUnitID;
+
+    //
+    //! ID of the Unit or Terminal to which this Feature Unit is connected.
+    //
+    unsigned char bSourceID;
+
+    //
+    //! ID of the Output Terminal to which this Input Terminal is associated.
+    //
+    unsigned char bControlSize;
+
+    //
+    //! A bit set to 1 indicates that the mentioned Control is supported for
+    //! a given channel.  See the USB_FU_* defines for the bit definitions.
+    //! This actually an array of elements of size bControlSize so be
+    //! careful when using this value directly.
+    //
+    unsigned short bmaControls;
+}
+PACKED tACFeatureUnit;
+
+//*****************************************************************************
+//
+//! This structure describes the Output Terminal Descriptor as defined in
+//! Universal Serial Bus Device Class Definition for Audio Devices Release 1.0.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! The length of this descriptor in bytes.
+    //
+    unsigned char bLength;
+
+    //
+    //! The type of the descriptor.  For an interface descriptor, this will
+    //! be USB_DTYPE_CS_INTERFACE (36).
+    //
+    unsigned char bDescriptorType;
+
+    //
+    //! This will be USB_DSUBTYPE_OUT_TERM for the header.
+    //
+    unsigned char bDescriptorSubtype;
+
+    //
+    //! Constant uniquely identifying the Terminal within the audio function.
+    //! This value is used in all requests to address this Terminal.
+    //
+    unsigned char bTerminalID;
+
+    //
+    //! Constant characterizing the type of Terminal. See USB Audio Terminal
+    //! Types.
+    //
+    unsigned short wTerminalType;
+
+    //
+    //! Constant, identifying the Input Terminal to which this Output Terminal
+    //! is associated.
+    //
+    unsigned char bAssocTerminal;
+
+    //
+    //! ID of the Unit or Terminal to which this Terminal is connected.
+    //
+    unsigned char bSourceID;
+
+    //
+    //! Index of a string descriptor, describing the Output Terminal.
+    //
+    unsigned char iTerminal;
+}
+PACKED tACOutputTerminal;
+
+//*****************************************************************************
+//
+//! This structure describes the Input Terminal Descriptor as defined in
+//! Universal Serial Bus Device Class Definition for Audio Devices Release 1.0.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! The length of this descriptor in bytes.
+    //
+    unsigned char bLength;
+
+    //
+    //! The type of the descriptor.  For an interface descriptor, this will
+    //! be USB_DTYPE_CS_INTERFACE (36).
+    //
+    unsigned char bDescriptorType;
+
+    //
+    //! This will be USB_DSUBTYPE_OUT_TERM for the header.
+    //
+    unsigned char bDescriptorSubtype;
+
+    //
+    //! Constant uniquely identifying the Terminal within the audio function.
+    //! This value is used in all requests to address this Terminal.
+    //
+    unsigned char bTerminalID;
+
+    //
+    //! Constant characterizing the type of Terminal. See USB Audio Terminal
+    //! Types.
+    //
+    unsigned short wTerminalType;
+
+    //
+    //! Constant, identifying the Input Terminal to which this Output Terminal
+    //! is associated.
+    //
+    unsigned char bAssocTerminal;
+
+    //
+    //! Number of logical output channels in the Terminal’s output audio
+    //! channel cluster.
+    //
+    unsigned char bNrChannels;
+
+    //
+    //! Describes the spatial location of the logical channels.
+    //
+    unsigned short wChannelConfig;
+
+    //
+    //! Index of a string descriptor, describing the name of the first logical
+    //! channel.
+    //
+    unsigned char iChannelNames;
+
+    //
+    //! Index of a string descriptor, describing the Output Terminal.
+    //
+    unsigned char iTerminal;
+}
+PACKED tACInputTerminal;
+
+//*****************************************************************************
+//
+//! This structure describes the Mixer Descriptor as defined in Universal
+//! Serial Bus Device Class Definition for Audio Devices Release 1.0.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! The length of this descriptor in bytes.
+    //
+    unsigned char bLength;
+
+    //
+    //! The type of the descriptor.  For an interface descriptor, this will
+    //! be USB_DTYPE_CS_INTERFACE (36).
+    //
+    unsigned char bDescriptorType;
+
+    //
+    //! This will be USB_AI_MIXER_UNIT for the header.
+    //
+    unsigned char bDescriptorSubtype;
+
+    //
+    //! Constant uniquely identifying the Unit within the audio function. This
+    //! value is used in all requests to address this Unit.
+    //
+    unsigned char bUnitID;
+
+    //
+    //! Number of Input Pins of this Unit.
+    //
+    unsigned char bNrInPins;
+
+    //
+    //! ID of the Unit or Terminal to which the first Input Pin of this Mixer Unit is
+    //! connected.
+    //
+    unsigned char baSourceID;
+}
+PACKED tACMixer;
+
+//*****************************************************************************
+//
+//! This structure describes the Selector Descriptor as defined in Universal
+//! Serial Bus Device Class Definition for Audio Devices Release 1.0.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! The length of this descriptor in bytes.
+    //
+    unsigned char bLength;
+
+    //
+    //! The type of the descriptor.  For an interface descriptor, this will
+    //! be USB_DTYPE_CS_INTERFACE (36).
+    //
+    unsigned char bDescriptorType;
+
+    //
+    //! This will be USB_AI_MIXER_UNIT for the header.
+    //
+    unsigned char bDescriptorSubtype;
+
+    //
+    //! Constant uniquely identifying the Unit within the audio function. This
+    //! value is used in all requests to address this Unit.
+    //
+    unsigned char bUnitID;
+
+    //
+    //! Number of Input Pins of this Unit.
+    //
+    unsigned char bNrInPins;
+
+    //
+    //! ID of the Unit or Terminal to which the first Input Pin of this Mixer Unit is
+    //! connected.
+    //
+    unsigned char baSourceID;
+}
+PACKED tACSelector;
+
+//*****************************************************************************
+//
+//! This structure describes the Output Terminal Descriptor as defined in
+//! Universal Serial Bus Device Class Definition for Audio Devices Release 1.0.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! The length of this descriptor in bytes.
+    //
+    unsigned char bLength;
+
+    //
+    //! The type of the descriptor.  For an interface descriptor, this will
+    //! be USB_DTYPE_CS_INTERFACE (36).
+    //
+    unsigned char bDescriptorType;
+
+    //
+    //! This will be USB_DSUBTYPE_GENERAL for the header.
+    //
+    unsigned char bDescriptorSubtype;
+
+    //
+    //! The Terminal ID of the Terminal to which the endpoint of this
+    //! interface is connected.
+    //
+    unsigned char bTerminalLink;
+
+    //
+    //! Delay introduced by the data path. Expressed in number of frames.
+    //
+    unsigned char bDelay;
+
+    //
+    //! The Audio Data Format that has to be used to communicate with this
+    //! interface.
+    //
+    unsigned short wFormatTag;
+}
+PACKED tACGeneral;
+
+//*****************************************************************************
+//
+//! This structure describes the Type I Audio format descriptors defined in
+//! USB Audio Devices Release 1.0.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! The length of this descriptor in bytes.
+    //
+    unsigned char bLength;
+
+    //
+    //! The type of the descriptor.  For an interface descriptor, this will
+    //! be USB_DTYPE_CS_INTERFACE (36).
+    //
+    unsigned char bDescriptorType;
+
+    //
+    //! This will be USB_AS_FORMAT_TYPE.
+    //
+    unsigned char bDescriptorSubtype;
+
+    //
+    //! This will be USB_AS_FORMAT_TYPE_I.
+    //
+    unsigned char bFormatType;
+
+    //
+    //! Number of channels on this streaming interface.
+    //
+    unsigned char bNrChannels;
+
+    //
+    //! Number of bytes per audio sub-frame or channel.
+    //
+    unsigned char bSubFrameSize;
+
+    //
+    //! Number of bits per sample.
+    //
+    unsigned char bBitResolution;
+
+    //
+    //! Number of sample rates that are supported.
+    //
+    unsigned char bSamFreqType;
+
+    //
+    //! Number of bits per sample.
+    //
+    unsigned char tSamFreq;
+}
+PACKED tASFormat;
+
+//*****************************************************************************
+//
+// Return to default packing when using the IAR Embedded Workbench compiler.
+//
+//*****************************************************************************
+#ifdef ewarm
+#pragma pack()
+#endif
+
+#endif
+
diff --git a/src/platform/lm3s/usblib/usbbuffer.c b/src/platform/lm3s/usblib/usbbuffer.c
new file mode 100755
index 00000000..d854711e
--- /dev/null
+++ b/src/platform/lm3s/usblib/usbbuffer.c
@@ -0,0 +1,1089 @@
+//*****************************************************************************
+//
+// usbbuffer.c - USB buffer object.
+//
+// Copyright (c) 2008-2011 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 7611 of the Stellaris USB Library.
+//
+//*****************************************************************************
+
+#include "inc/hw_types.h"
+#include "driverlib/debug.h"
+#include "usblib/usblib.h"
+#include "usblib/usblibpriv.h"
+
+//*****************************************************************************
+//
+//! \addtogroup usblib_buffer_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Workspace variables required by each buffer instance.  This structure is
+// overlaid on the pvWorkspace memory provided in the tUSBBuffer structure
+// passed to USBBufferInit().
+//
+//*****************************************************************************
+typedef struct
+{
+    tUSBRingBufObject sRingBuf;
+}
+tUSBBufferVars;
+
+//*****************************************************************************
+//
+// Schedule the next packet transmission to the host if data remains to be
+// sent.
+//
+// \param psBuffer points to the buffer from which a packet transmission is
+// to be scheduled.
+//
+// This function checks to determine whether the lower layer is capable of
+// accepting a new packet for transmission and, if so, schedules the next
+// packet transmission if data remains in the buffer.
+//
+// \return None.
+//
+//*****************************************************************************
+static void
+ScheduleNextTransmission(const tUSBBuffer *psBuffer)
+{
+    tUSBBufferVars *psVars;
+    unsigned long ulPacket, ulSpace, ulTotal;
+
+    //
+    // Get a pointer to our workspace variables.
+    //
+    psVars = psBuffer->pvWorkspace;
+
+    //
+    // Ask the lower layer if it has space to accept another packet of data.
+    //
+    ulPacket = psBuffer->pfnAvailable(psBuffer->pvHandle);
+
+    //
+    // If we were returned something other than zero, we can write that number
+    // of bytes to the lower layer.
+    //
+    if(ulPacket)
+    {
+        //
+        // How much contiguous data do we have in the buffer?
+        //
+        ulSpace = USBRingBufContigUsed(&psVars->sRingBuf);
+
+        //
+        // How much total data do we have in the buffer?
+        //
+        ulTotal = USBRingBufUsed(&psVars->sRingBuf);
+
+        //
+        // Write the contiguous bytes to the lower layer assuming there is
+        // something to send.
+        //
+        if(ulSpace)
+        {
+            //
+            // Determine the maximum sized block we can send in this transfer.
+            //
+            ulSpace = (ulSpace < ulPacket) ? ulSpace : ulPacket;
+            //
+            // Call the lower layer to send the new packet.  If the current
+            // data spans the buffer wrap, tell the lower layer that it can
+            // expect a second call to fill the whole packet before it
+            // transmits it.
+            //
+            psBuffer->pfnTransfer(psBuffer->pvHandle,
+                                 (psVars->sRingBuf.pucBuf +
+                                  psVars->sRingBuf.ulReadIndex), ulSpace,
+                                  (((ulSpace < ulPacket) &&
+                                    (ulSpace < ulTotal)) ? false : true));
+
+            //
+            // Do we need to send a second part to fill out the packet?  This
+            // will occur if the current packet spans the buffer wrap.
+            //
+            if((ulSpace < ulPacket) && (ulSpace < ulTotal))
+            {
+                //
+                // The packet straddled the wrap.  How much space remains in
+                // the packet?
+                //
+                ulPacket -= ulSpace;
+
+                //
+                // How much data can we actually send?
+                //
+                ulSpace = ulTotal - ulSpace;
+                ulSpace = (ulSpace > ulPacket) ? ulPacket : ulSpace;
+
+                psBuffer->pfnTransfer(psBuffer->pvHandle,
+                                      psVars->sRingBuf.pucBuf, ulSpace, true);
+            }
+        }
+
+        //
+        // Don't update the ring buffer read index yet.  We do this once we are
+        // sure the packet was correctly transmitted.
+        //
+    }
+}
+
+//*****************************************************************************
+//
+// Handles USB_EVENT_RX_AVAILABLE for a receive buffer.
+//
+// \param psBuffer points to the buffer which is receiving the event.
+// \param ulSize is the size reported in the event.
+// \param pucData is the pointer provided in the event.
+//
+// This function is responsible for reading data from the lower layer into
+// the buffer or, if we had previously passed a section of the buffer to the
+// lower layer for it to write into directly, updating the buffer write pointer
+// to add the new data to the buffer.
+//
+// If the pointer provided is NULL, we call the low level pfnTransfer function
+// to get the new data.  If the pointer is not NULL and not within the existing
+// ring buffer, we copy the data directly from the pointer to the buffer and
+// return the number of bytes read.
+//
+// \return Returns the number of bytes read from the lower layer.
+//
+//*****************************************************************************
+static unsigned long
+HandleRxAvailable(tUSBBuffer *psBuffer, unsigned long ulSize,
+                  unsigned char *pucData)
+{
+    tUSBBufferVars *psVars;
+    unsigned long ulAvail, ulRead, ulPacket, ulRetCount;
+
+    //
+    // Get a pointer to our workspace variables.
+    //
+    psVars = psBuffer->pvWorkspace;
+
+    //
+    // Has the data already been read into memory?
+    //
+    if(pucData)
+    {
+        //
+        // Yes - is it already in our ring buffer?
+        //
+        if((pucData >= psBuffer->pcBuffer) &&
+           (pucData < psBuffer->pcBuffer + psBuffer->ulBufferSize))
+        {
+            //
+            // The data is already in our ring buffer so merely update the
+            // write pointer to add the new data.
+            //
+            USBRingBufAdvanceWrite(&psVars->sRingBuf, ulSize);
+
+            //
+            // In this case, we pass back 0 to indicate that the lower layer
+            // doesn't need to make any buffer pointer updates.
+            //
+            ulRetCount = 0;
+        }
+        else
+        {
+            //
+            // The data is not within our buffer so we need to copy it into
+            // the buffer.
+            //
+            // How much space does the buffer have available?
+            //
+            ulAvail = USBRingBufFree(&psVars->sRingBuf);
+
+            //
+            // How much should we copy?
+            //
+            ulRead = (ulAvail < ulSize) ? ulAvail : ulSize;
+
+            //
+            // Copy the data into the buffer.
+            //
+            USBRingBufWrite(&psVars->sRingBuf, pucData, ulRead);
+
+            //
+            // We need to return the number of bytes we read in this case
+            // since the buffer supplied to us was owned by the lower layer and
+            // it may need to update its read pointer.
+            //
+            ulRetCount = ulRead;
+        }
+    }
+    else
+    {
+        //
+        // We were passed a NULL pointer so the low level driver has not read
+        // the data into memory yet.  We need to call the transfer function to
+        // get the packet.
+        //
+        // How big is the packet that we need to receive?
+        //
+        ulPacket = psBuffer->pfnAvailable(psBuffer->pvHandle);
+
+        //
+        // How much contiguous space do we have in the buffer?
+        //
+        ulAvail = USBRingBufContigFree(&psVars->sRingBuf);
+
+        //
+        // Get as much of the packet as we can in the available space.
+        //
+        ulRead = psBuffer->pfnTransfer(psBuffer->pvHandle,
+                                       (psVars->sRingBuf.pucBuf +
+                                        psVars->sRingBuf.ulWriteIndex),
+                                       ulAvail, true);
+
+        //
+        // Advance the ring buffer write pointer to add our new data.
+        //
+        if(ulRead)
+        {
+            USBRingBufAdvanceWrite(&psVars->sRingBuf, ulRead);
+        }
+
+        //
+        // Did we get the whole packet?
+        //
+        if(ulRead < ulPacket)
+        {
+            //
+            // No - how much space do we have in the buffer?
+            //
+            ulAvail = USBRingBufContigFree(&psVars->sRingBuf);
+
+            //
+            // If there is any space left, read as much of the remainder of
+            // the packet as we can.
+            //
+            if(ulAvail)
+            {
+                ulPacket =
+                    psBuffer->pfnTransfer(psBuffer->pvHandle,
+                                          (psVars->sRingBuf.pucBuf +
+                                           psVars->sRingBuf.ulWriteIndex),
+                                          ulAvail, true);
+
+                //
+                // Update the write pointer after we read more data into the
+                // buffer.
+                //
+                if(ulPacket)
+                {
+                    USBRingBufAdvanceWrite(&psVars->sRingBuf, ulPacket);
+                }
+            }
+        }
+
+        //
+        // We need to return 0 in this case to indicate that the lower layer
+        // need not perform any buffer maintenance as a result of the callback.
+        //
+        ulRetCount = 0;
+    }
+
+    //
+    // How much data do we have in the buffer?
+    //
+    ulAvail = USBRingBufUsed(&psVars->sRingBuf);
+
+    //
+    // Pass the event on to the client with the current read pointer and
+    // available data size.  The client is expected to understand the ring
+    // structure and be able to deal with wrap if it wants to read the data
+    // directly from the buffer.
+    //
+    ulRead = psBuffer->pfnCallback(psBuffer->pvCBData,
+                                   USB_EVENT_RX_AVAILABLE,
+                                   ulAvail,
+                                   (psVars->sRingBuf.pucBuf +
+                                    psVars->sRingBuf.ulReadIndex));
+
+    //
+    // If the client read anything from the buffer, update the read pointer.
+    //
+    USBRingBufAdvanceRead(&psVars->sRingBuf, ulRead);
+
+    //
+    // Return the correct value to the low level driver.
+    //
+    return(ulRetCount);
+}
+
+//*****************************************************************************
+//
+// Handles USB_EVENT_DATA_REMAINING for a receive buffer.
+//
+// \param psBuffer points to the buffer which is receiving the event.
+//
+// This function determines the total number of bytes of data that remain
+// unprocessed in the client and buffer and reports this back to the caller.
+//
+// \return Returns the number of bytes remaining to be processed.
+//
+//*****************************************************************************
+static unsigned long
+HandleDataRemaining(tUSBBuffer *psBuffer)
+{
+    unsigned long ulBufData, ulClientData;
+    tUSBBufferVars *psVars;
+
+    //
+    // Get a pointer to our workspace variables.
+    //
+    psVars = psBuffer->pvWorkspace;
+
+    //
+    // How much data does the client currently have buffered?
+    //
+    ulClientData = psBuffer->pfnCallback(psBuffer->pvCBData,
+                                         USB_EVENT_DATA_REMAINING, 0,
+                                         (void *)0);
+
+    //
+    // How much data do we have in the buffer?
+    //
+    ulBufData = USBRingBufUsed(&psVars->sRingBuf);
+
+    //
+    // Return the total number of bytes of unprocessed data to the lower layer.
+    //
+    return(ulBufData + ulClientData);
+}
+
+//*****************************************************************************
+//
+// Handles USB_EVENT_TX_COMPLETE for a transmit buffer.
+//
+// \param psBuffer points to the buffer which is receiving the event.
+// \param ulSize is the number of bytes that have been transmitted and
+// acknowledged.
+//
+// This function informs us that data written to the lower layer from a
+// transmit buffer has been successfully transmitted.  We use this to update
+// the buffer read pointer and attempt to schedule the next transmission if
+// data remains in the buffer.
+//
+// \return Returns the number of bytes remaining to be processed.
+//
+//*****************************************************************************
+static unsigned long
+HandleTxComplete(tUSBBuffer *psBuffer, unsigned long ulSize)
+{
+    tUSBBufferVars *psVars;
+
+    //
+    // Get a pointer to our workspace variables.
+    //
+    psVars = psBuffer->pvWorkspace;
+
+    //
+    // Update the transmit buffer read pointer to remove the data that has
+    // now been transmitted.
+    //
+    USBRingBufAdvanceRead(&psVars->sRingBuf, ulSize);
+
+    //
+    // Try to schedule the next packet transmission if data remains to be
+    // sent.
+    //
+    ScheduleNextTransmission(psBuffer);
+
+    //
+    // The return code from this event is ignored.
+    //
+    return(0);
+}
+
+//*****************************************************************************
+//
+// Handles USB_EVENT_REQUEST_BUFFER for a receive buffer.
+//
+// \param psBuffer points to the buffer which is receiving the event.
+// \param ulSize is the size of the buffer requested.
+// \param ppucBuffer is a pointer which is to be written with a pointer to
+// the returned buffer.
+//
+// This function is called by a low level driver that wishes to receive data
+// automatically and write it directly to a memory buffer, either using
+// software or DMA prior to issuing USB_EVENT_RX_AVAILABLE.  The event is sent
+// in advance of receiving data to provide storage for whatever is received
+// next.
+//
+// If we have a contiguous block of space in the buffer of at least ulSize
+// bytes immediately in front of the current write pointer, we pass this back
+// otherwise we send NULL indicating that the next packet should be notified
+// using a standard USB_EVENT_RX_AVAILABLE event without being received
+// automatically.  Note that the USB_EVENT_REQUEST_BUFFER protocol allows us to
+// return less than \e ulSize bytes if we know how much data is expected next
+// but this is not possible here since the USBBuffer knows nothing about the
+// protocol whose data it is handling.
+//
+// \return Returns the number of bytes remaining to be processed.
+//
+//*****************************************************************************
+static unsigned long
+HandleRequestBuffer(tUSBBuffer *psBuffer, unsigned long ulSize,
+                    unsigned char **ppucBuffer)
+{
+    tUSBBufferVars *psVars;
+    unsigned long ulSpace;
+
+    //
+    // Get a pointer to our workspace variables.
+    //
+    psVars = psBuffer->pvWorkspace;
+
+    //
+    // How much contiguous space do we have available?
+    //
+    ulSpace = USBRingBufContigFree(&psVars->sRingBuf);
+
+    //
+    // Is there enough space available to satisfy the request?
+    //
+    if(ulSpace >= ulSize)
+    {
+        //
+        // Yes - return the current write pointer
+        //
+        *ppucBuffer = psVars->sRingBuf.pucBuf + psVars->sRingBuf.ulWriteIndex;
+        return(ulSize);
+    }
+    else
+    {
+        //
+        // We do not have enough contiguous space following the current write
+        // pointer to satisfy the request so do not provide a buffer.
+        //
+        *ppucBuffer = (unsigned char *)0;
+        return(0);
+    }
+}
+
+//*****************************************************************************
+//
+//! Initializes a USB buffer object to be used with a given USB controller and
+//! device or host class driver.
+//!
+//! \param psBuffer points to a structure containing information on the buffer
+//! memory to be used and the underlying device or host class driver whose data
+//! is to be buffered.  This structure must remain accessible for as long as
+//! the buffer is in use.
+//!
+//! This function is used to initialize a USB buffer object and insert it
+//! into the function and callback interfaces between an underlying driver
+//! and the application.  The caller supplies information on both the RAM
+//! to be used to buffer data, the type of buffer to be created (transmit or
+//! receive) and the functions to be called in the lower layer to transfer
+//! data to or from the USB controller.
+//!
+//! \return Returns the original buffer structure pointer if successful or
+//! NULL if an error is detected.
+//
+//*****************************************************************************
+const tUSBBuffer *
+USBBufferInit(const tUSBBuffer *psBuffer)
+{
+    tUSBBufferVars *psVars;
+
+    //
+    // Check parameter validity.
+    //
+    ASSERT(psBuffer && psBuffer->pvWorkspace && psBuffer->pcBuffer &&
+           psBuffer->ulBufferSize && psBuffer->pfnAvailable &&
+           psBuffer->pfnTransfer && psBuffer->pfnCallback);
+
+    //
+    // Get a pointer to the buffer workspace and inttialize the variables it
+    // contains.
+    //
+    psVars = psBuffer->pvWorkspace;
+    USBRingBufInit(&psVars->sRingBuf, psBuffer->pcBuffer,
+                   psBuffer->ulBufferSize);
+
+    //
+    // If all is well, return the same pointer we were originally passed.
+    //
+    return(psBuffer);
+}
+
+//*****************************************************************************
+//
+//! Returns the current ring buffer indices for this USB buffer.
+//!
+//! \param psBuffer is the pointer to the buffer instance whose information
+//! is being queried.
+//! \param psRingBuf is a pointer to storage that will be written with the
+//! current ring buffer control structure for this USB buffer.
+//!
+//! This function is provided to aid a client wishing to write data directly
+//! into the USB buffer rather than using the USBBufferWrite() function.  This
+//! may be necessary to control when the USBBuffer starts transmission of a
+//! large block of data, for example.
+//!
+//! A transmit buffer will immediately send a new packet on any call to
+//! USBBufferWrite() if the underlying layer indicates that a transmission can
+//! be started.  In some cases this is not desirable and a client may wish to
+//! wishes to write more data to the buffer in advance of starting transmission
+//! to the lower layer.  In such cases, this function may be called to retrieve
+//! the current ring buffer indices and the buffer accessed directly.  Once the
+//! client has written all data it wishes to send, it should call function
+//! USBBufferDataWritten() to indicate that transmission may begin.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBBufferInfoGet(const tUSBBuffer *psBuffer, tUSBRingBufObject *psRingBuf)
+{
+    tUSBBufferVars *psVars;
+
+    //
+    // Check parameter validity.
+    //
+    ASSERT(psBuffer && psRingBuf);
+
+    //
+    // Get our workspace variables.
+    //
+    psVars = psBuffer->pvWorkspace;
+
+    //
+    // Copy the current ring buffer settings to the clients storage.
+    //
+    *psRingBuf = psVars->sRingBuf;
+}
+
+//*****************************************************************************
+//
+//! Indicates that a client has written data directly into the buffer and
+//! wishes to start transmission.
+//!
+//! \param psBuffer is the pointer to the buffer instance into which data has
+//! been written.
+//! \param ulLength is the number of bytes of data that the client has written.
+//!
+//! This function updates the USB buffer write pointer and starts transmission
+//! of the data in the buffer assuming the lower layer is ready to receive a
+//! new packet.  The function is provided to aid a client wishing to write
+//! data directly into the USB buffer rather than using the USBBufferWrite()
+//! function.  This may be necessary to control when the USB buffer starts
+//! transmission of a large block of data, for example.
+//!
+//! A transmit buffer will immediately send a new packet on any call to
+//! USBBufferWrite() if the underlying layer indicates that a transmission can
+//! be started.  In some cases this is not desirable and a client may wish to
+//! write more data to the buffer in advance of starting transmission
+//! to the lower layer.  In such cases, USBBufferInfoGet() may be called to
+//! retrieve the current ring buffer indices and the buffer accessed directly.
+//! Once the client has written all data it wishes to send (taking care to
+//! handle the ring buffer wrap), it should call this function to indicate that
+//! transmission may begin.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBBufferDataWritten(const tUSBBuffer *psBuffer, unsigned long ulLength)
+{
+    tUSBBufferVars *psVars;
+
+    //
+    // Check parameter validity.
+    //
+    ASSERT(psBuffer);
+
+    //
+    // Get our workspace variables.
+    //
+    psVars = psBuffer->pvWorkspace;
+
+    //
+    // Advance the ring buffer write pointer to include the newly written
+    // data.
+    //
+    if(ulLength)
+    {
+        USBRingBufAdvanceWrite(&psVars->sRingBuf, ulLength);
+    }
+
+    //
+    // Try to schedule a new packet transmission.
+    //
+    ScheduleNextTransmission(psBuffer);
+}
+
+//*****************************************************************************
+//
+//! Indicates that a client has read data directly out of the buffer.
+//!
+//! \param psBuffer is the pointer to the buffer instance from which data has
+//! been read.
+//! \param ulLength is the number of bytes of data that the client has read.
+//!
+//! This function updates the USB buffer read pointer to remove data that
+//! the client has read directly rather than via a call to USBBufferRead().
+//! The function is provided to aid a client wishing to minimize data copying.
+//! To read directly from the buffer, a client must call USBBufferInfoGet() to
+//! retrieve the current buffer indices.  With this information, the data
+//! following the current read index can be read.  Once the client has
+//! processed much data as it needs, USBBufferDataRemoved() must be called to
+//! advance the read pointer past the data that has been read and free up that
+//! section of the buffer.  The client must take care to correctly handle the
+//! wrap point if accessing the buffer directly.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBBufferDataRemoved(const tUSBBuffer *psBuffer, unsigned long ulLength)
+{
+    tUSBBufferVars *psVars;
+
+    //
+    // Check parameter validity.
+    //
+    ASSERT(psBuffer);
+
+    //
+    // Get our workspace variables.
+    //
+    psVars = psBuffer->pvWorkspace;
+
+    //
+    // Advance the ring buffer write pointer to include the newly written
+    // data.
+    //
+    if(ulLength)
+    {
+        USBRingBufAdvanceRead(&psVars->sRingBuf, ulLength);
+    }
+}
+
+//*****************************************************************************
+//
+//! Sets the callback pointer supplied to clients of this buffer.
+//!
+//! \param psBuffer is the pointer to the buffer instance whose callback data
+//! is to be changed.
+//! \param pvCBData is the pointer the client wishes to receive on all future
+//! callbacks from this buffer.
+//!
+//! This function sets the callback pointer which this buffer will supply
+//! to clients as the \e pvCBData parameter in all future calls to the
+//! event callback.
+//!
+//! \note If this function is to be used, the application must ensure that the
+//! tUSBBuffer structure used to describe this buffer is held in RAM rather
+//! than flash.  The \e pvCBData value passed is written directly into this
+//! structure.
+//!
+//! \return Returns the previous callback pointer set for the buffer.
+//
+//*****************************************************************************
+void *
+USBBufferCallbackDataSet(tUSBBuffer *psBuffer, void *pvCBData)
+{
+    void *pvOldData;
+
+    //
+    // Keep a copy of the old callback data.
+    //
+    pvOldData = psBuffer->pvCBData;
+
+    //
+    // Replace the callback data with the new value.
+    //
+    psBuffer->pvCBData = pvCBData;
+
+    //
+    // Give the caller the old value back.
+    //
+    return(pvOldData);
+}
+
+//*****************************************************************************
+//
+//! Writes a block of data to the transmit buffer and queues it for
+//! transmission to the USB controller.
+//!
+//! \param psBuffer points to the pointer instance into which data is to be
+//! written.
+//! \param pucData points to the first byte of data which is to be written.
+//! \param ulLength is the number of bytes of data to write to the buffer.
+//!
+//! This function copies the supplied data into the transmit buffer.  The
+//! transmit buffer data will be packetized according to the constraints
+//! imposed by the lower layer in use and sent to the USB controller as soon as
+//! possible.  Once a packet is transmitted and acknowledged, a
+//! \b USB_EVENT_TX_COMPLETE event will be sent to the application callback
+//! indicating the number of bytes that have been sent from the buffer.
+//!
+//! Attempts to send more data than there is space for in the transmit buffer
+//! will result in fewer bytes than expected being written.  The value returned
+//! by the function indicates the actual number of bytes copied to the buffer.
+//!
+//! \return Returns the number of bytes actually written.
+//
+//*****************************************************************************
+unsigned long
+USBBufferWrite(const tUSBBuffer *psBuffer, const unsigned char *pucData,
+               unsigned long ulLength)
+{
+    unsigned long ulSpace;
+    tUSBBufferVars *psVars;
+
+    //
+    // Check parameter validity.
+    //
+    ASSERT(psBuffer && pucData);
+    ASSERT(psBuffer->bTransmitBuffer == true);
+
+    //
+    // Get our workspace variables.
+    //
+    psVars = psBuffer->pvWorkspace;
+
+    //
+    // How much space is left in the buffer?
+    //
+    ulSpace = USBRingBufFree(&psVars->sRingBuf);
+
+    //
+    // How many bytes will we write?
+    //
+    ulLength = (ulLength > ulSpace) ? ulSpace : ulLength;
+
+    //
+    // Write the data to the buffer.
+    //
+    if(ulLength)
+    {
+        USBRingBufWrite(&psVars->sRingBuf, pucData, ulLength);
+    }
+
+    //
+    // Try to transmit the next packet to the host.
+    //
+    ScheduleNextTransmission(psBuffer);
+
+    //
+    // Tell the caller how many bytes we wrote to the buffer.
+    //
+    return(ulLength);
+}
+
+//*****************************************************************************
+//
+//! Flushes a USB buffer, discarding any data that it contains.
+//!
+//! \param psBuffer is the pointer to the buffer instance which is to be
+//! flushed.
+//!
+//! This function discards all data currently in the supplied buffer without
+//! processing (transmitting it via the USB controller or passing it to the
+//! client depending upon the buffer mode).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBBufferFlush(const tUSBBuffer *psBuffer)
+{
+    tUSBBufferVars *psVars;
+
+    //
+    // Check parameter validity.
+    //
+    ASSERT(psBuffer);
+
+    //
+    // Get our workspace variables.
+    //
+    psVars = psBuffer->pvWorkspace;
+
+    //
+    // Flush the ring buffer.
+    //
+    USBRingBufFlush(&psVars->sRingBuf);
+}
+
+//*****************************************************************************
+//
+//! Reads a block of data from a USB receive buffer into storage supplied by
+//! the caller.
+//!
+//! \param psBuffer is the pointer to the buffer instance from which data is
+//! to be read.
+//! \param pucData points to a buffer into which the received data will be
+//! written.
+//! \param ulLength is the size of the buffer pointed to by pucData.
+//!
+//! This function reads up to ulLength bytes of data received from the USB
+//! host into the supplied application buffer.  If the receive buffer
+//! contains fewer than \e ulLength bytes of data, the data that is present
+//! will be copied and the return code will indicate the actual number of bytes
+//! copied to \e pucData.
+//!
+//! \return Returns the number of bytes of data read.
+//
+//*****************************************************************************
+unsigned long
+USBBufferRead(const tUSBBuffer *psBuffer, unsigned char *pucData,
+              unsigned long ulLength)
+{
+    tUSBBufferVars *psVars;
+    unsigned long ulAvail, ulRead;
+
+    //
+    // Check parameter validity.
+    //
+    ASSERT(psBuffer && pucData && ulLength);
+
+    //
+    // Get our workspace variables.
+    //
+    psVars = psBuffer->pvWorkspace;
+
+    //
+    // How much data is in the buffer?
+    //
+    ulAvail = USBRingBufUsed(&psVars->sRingBuf);
+
+    //
+    // Determine how many bytes we can actually read.
+    //
+    ulRead = (ulAvail < ulLength) ? ulAvail : ulLength;
+
+    //
+    // Read the data from the buffer assuming there is some to read.
+    //
+    if(ulRead)
+    {
+        USBRingBufRead(&psVars->sRingBuf, pucData, ulRead);
+    }
+
+    //
+    // Tell the caller how many bytes we wrote to their buffer.
+    //
+    return(ulRead);
+}
+
+//*****************************************************************************
+//
+//! Returns the number of bytes of data available in the buffer.
+//!
+//! \param psBuffer is the pointer to the buffer instance which is to be
+//! queried.
+//!
+//! This function may be used to determine the number of bytes of data in a
+//! buffer.  For a receive buffer, this indicates the number of bytes that the
+//! client can read from the buffer using USBBufferRead().  For a transmit
+//! buffer, this indicates the amount of data that remains to be sent to the
+//! USB controller.
+//!
+//! \return Returns the number of bytes of data in the buffer.
+//
+//*****************************************************************************
+unsigned long
+USBBufferDataAvailable(const tUSBBuffer *psBuffer)
+{
+    tUSBBufferVars *psVars;
+
+    //
+    // Check parameter validity.
+    //
+    ASSERT(psBuffer);
+
+    //
+    // Get our workspace variables.
+    //
+    psVars = psBuffer->pvWorkspace;
+
+    //
+    // Return the amount of data in the buffer.
+    //
+    return(USBRingBufUsed(&psVars->sRingBuf));
+}
+
+//*****************************************************************************
+//
+//! Returns the number of free bytes in the buffer.
+//!
+//! \param psBuffer is the pointer to the buffer instance which is to be
+//! queried.
+//!
+//! This function returns the number of free bytes in the buffer.  For a
+//! transmit buffer, this indicates the maximum number of bytes that can be
+//! passed on a call to USBBufferWrite() and accepted for transmission.  For a
+//! receive buffer, it indicates the number of bytes that can be read from the
+//! USB controller before the buffer will be full.
+//!
+//! \return Returns the number of free bytes in the buffer.
+//
+//*****************************************************************************
+unsigned long
+USBBufferSpaceAvailable(const tUSBBuffer *psBuffer)
+{
+    tUSBBufferVars *psVars;
+
+    //
+    // Check parameter validity.
+    //
+    ASSERT(psBuffer);
+
+    //
+    // Get our workspace variables.
+    //
+    psVars = psBuffer->pvWorkspace;
+
+    //
+    // Return the amount of space available in the buffer.
+    //
+    return(USBRingBufFree(&psVars->sRingBuf));
+}
+
+//*****************************************************************************
+//
+//! Called by the USB buffer to notify the client of asynchronous events.
+//!
+//! \param pvCBData is the client-supplied callback pointer associated with
+//! this buffer instance.
+//! \param ulEvent is the identifier of the event being sent.  This will be
+//! a general event identifier of the form USBD_EVENT_xxxx or a device
+//! class-dependent event of the form USBD_CDC_EVENT_xxx or
+//! USBD_HID_EVENT_xxx.
+//! \param ulMsgValue is an event-specific parameter value.
+//! \param pvMsgData is an event-specific data pointer.
+//!
+//! This function is the USB buffer event handler that applications should
+//! register with the USB device class driver as the callback for the channel
+//! which is to be buffered using this buffer.
+//!
+//! \note This function will never be called by an application.  It is the
+//! handler that allows the USB buffer to be inserted above the device class
+//! driver or host pipe driver and below the application to offer buffering
+//! support.
+//!
+//! \return The return value is dependent upon the event being processed.
+//
+//*****************************************************************************
+unsigned long
+USBBufferEventCallback(void *pvCBData, unsigned long ulEvent,
+                       unsigned long ulMsgValue, void *pvMsgData)
+{
+    tUSBBuffer *psBuffer;
+
+    //
+    // Get our instance data pointers from the callback data.
+    //
+    psBuffer = (tUSBBuffer *)pvCBData;
+    ASSERT(psBuffer);
+
+    //
+    // Which event have we been sent?
+    //
+    switch(ulEvent)
+    {
+        //
+        // Data is available from the lower layer.
+        //
+        case USB_EVENT_RX_AVAILABLE:
+        {
+            //
+            // This event is only relevant to us if we are a receive buffer.
+            //
+            if(!psBuffer->bTransmitBuffer)
+            {
+                return(HandleRxAvailable(psBuffer, ulMsgValue, pvMsgData));
+            }
+            break;
+        }
+
+        //
+        // We are being asked how much data remains to be processed.
+        //
+        case USB_EVENT_DATA_REMAINING:
+        {
+            return(HandleDataRemaining(psBuffer));
+        }
+
+        //
+        // A previous transmission has completed.
+        //
+        case USB_EVENT_TX_COMPLETE:
+        {
+            //
+            // This event is only relevant to us if we are a transmit buffer.
+            //
+            if(psBuffer->bTransmitBuffer)
+            {
+                //
+                // Handle the message then drop out of the switch so that the
+                // event is echoed to the layer above.
+                //
+                HandleTxComplete(psBuffer, ulMsgValue);
+            }
+            break;
+        }
+
+        //
+        // We are being asked to provide a buffer into which the next packet
+        // can be received.
+        //
+        case USB_EVENT_REQUEST_BUFFER:
+        {
+            //
+            // This event is only relevant to us if we are a receive buffer.
+            //
+            if(!psBuffer->bTransmitBuffer)
+            {
+                return(HandleRequestBuffer(psBuffer, ulMsgValue, pvMsgData));
+            }
+            break;
+        }
+
+        //
+        // All other events are merely passed through to the client.
+        //
+        default:
+        {
+            break;
+        }
+    }
+
+    //
+    // If we drop out of the switch, we need to pass the event on to the client
+    // unmodified and return the relevant return code back to the lower layer.
+    //
+    return(psBuffer->pfnCallback(psBuffer->pvCBData, ulEvent, ulMsgValue,
+                                 pvMsgData));
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/src/platform/lm3s/usblib/usbcdc.h b/src/platform/lm3s/usblib/usbcdc.h
new file mode 100755
index 00000000..d0d43de6
--- /dev/null
+++ b/src/platform/lm3s/usblib/usbcdc.h
@@ -0,0 +1,789 @@
+//*****************************************************************************
+//
+// usbhid.h - Definitions used by Communication Device Class devices.
+//
+// Copyright (c) 2007-2011 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 7611 of the Stellaris USB Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Note: This header contains definitions related to the USB Communication
+//       Device Class specification.  The header is complete for ACM model
+//       devices but request and notification definitions specific to other
+//       modem types, ISDN, ATM and Ethernet are currently incomplete or
+//       omitted.
+//
+//*****************************************************************************
+
+#ifndef __USBCDC_H__
+#define __USBCDC_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+//! \addtogroup cdc_device_class_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Generic macros to read a byte, word or long from a character pointer.
+//
+//*****************************************************************************
+#define BYTE(pucData)           (*(unsigned char *)(pucData))
+#define SHORT(pucData)          (*(unsigned short *)(pucData))
+#define LONG(pucData)           (*(unsigned long *)(pucData))
+
+//*****************************************************************************
+//
+// USB CDC subclass codes.  Used in interface descriptor, bInterfaceClass
+//
+//*****************************************************************************
+#define USB_CDC_SUBCLASS_DIRECT_LINE_MODEL          0x01
+#define USB_CDC_SUBCLASS_ABSTRACT_MODEL             0x02
+#define USB_CDC_SUBCLASS_TELEPHONE_MODEL            0x03
+#define USB_CDC_SUBCLASS_MULTI_CHANNEL_MODEL        0x04
+#define USB_CDC_SUBCLASS_CAPI_MODEL                 0x05
+#define USB_CDC_SUBCLASS_ETHERNET_MODEL             0x06
+#define USB_CDC_SUBCLASS_ATM_MODEL                  0x07
+
+//*****************************************************************************
+//
+// USB CDC control interface protocols.  Used in control interface descriptor,
+// bInterfaceProtocol
+//
+//*****************************************************************************
+#define USB_CDC_PROTOCOL_NONE                       0x00
+#define USB_CDC_PROTOCOL_V25TER                     0x01
+#define USB_CDC_PROTOCOL_VENDOR                     0xFF
+
+//*****************************************************************************
+//
+// USB CDC data interface protocols.  Used in data interface descriptor,
+// bInterfaceProtocol
+//
+//*****************************************************************************
+//      USB_CDC_PROTOCOL_NONE                       0x00
+#define USB_CDC_PROTOCOL_I420                       0x30
+#define USB_CDC_PROTOCOL_TRANSPARENT                0x32
+#define USB_CDC_PROTOCOL_Q921M                      0x50
+#define USB_CDC_PROTOCOL_Q921                       0x51
+#define USB_CDC_PROTOCOL_Q921TM                     0x52
+#define USB_CDC_PROTOCOL_V42BIS                     0x90
+#define USB_CDC_PROTOCOL_Q921EURO                   0x91
+#define USB_CDC_PROTOCOL_V120                       0x92
+#define USB_CDC_PROTOCOL_CAPI20                     0x93
+#define USB_CDC_PROTOCOL_HOST_DRIVER                0xFD
+#define USB_CDC_PROTOCOL_CDC_SPEC                   0xFE
+//      USB_CDC_PROTOCOL_VENDOR                     0xFF
+
+//*****************************************************************************
+//
+// Functional descriptor definitions
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Functional descriptor types
+//
+//*****************************************************************************
+#define USB_CDC_CS_INTERFACE                    0x24
+#define USB_CDC_CS_ENDPOINT                     0x25
+
+//*****************************************************************************
+//
+// Functional descriptor subtypes
+//
+//*****************************************************************************
+#define USB_CDC_FD_SUBTYPE_HEADER               0x00
+#define USB_CDC_FD_SUBTYPE_CALL_MGMT            0x01
+#define USB_CDC_FD_SUBTYPE_ABSTRACT_CTL_MGMT    0x02
+#define USB_CDC_FD_SUBTYPE_DIRECT_LINE_MGMT     0x03
+#define USB_CDC_FD_SUBTYPE_TELEPHONE_RINGER     0x04
+#define USB_CDC_FD_SUBTYPE_LINE_STATE_CAPS      0x05
+#define USB_CDC_FD_SUBTYPE_UNION                0x06
+#define USB_CDC_FD_SUBTYPE_COUNTRY              0x07
+#define USB_CDC_FD_SUBTYPE_TELEPHONE_MODES      0x08
+#define USB_CDC_FD_SUBTYPE_USB_TERMINAL         0x09
+#define USB_CDC_FD_SUBTYPE_NETWORK_TERMINAL     0x0A
+#define USB_CDC_FD_SUBTYPE_PROTOCOL_UNIT        0x0B
+#define USB_CDC_FD_SUBTYPE_EXTENSION_UNIT       0x0C
+#define USB_CDC_FD_SUBTYPE_MULTI_CHANNEL_MGMT   0x0D
+#define USB_CDC_FD_SUBTYPE_CAPI_MGMT            0x0E
+#define USB_CDC_FD_SUBTYPE_ETHERNET             0x0F
+#define USB_CDC_FD_SUBTYPE_ATM                  0x10
+
+//*****************************************************************************
+//
+// USB_CDC_FD_SUBTYPE_CALL_MGMT, Header functional descriptor, bmCapabilities
+//
+//*****************************************************************************
+#define USB_CDC_CALL_MGMT_VIA_DATA              0x02
+#define USB_CDC_CALL_MGMT_HANDLED               0x01
+
+//*****************************************************************************
+//
+// USB_CDC_FD_SUBTYPE_ABSTRACT_CTL_MGMT, Abstract Control Management functional
+// descriptor, bmCapabilities
+//
+//*****************************************************************************
+#define USB_CDC_ACM_SUPPORTS_NETWORK_CONNECTION 0x08
+#define USB_CDC_ACM_SUPPORTS_SEND_BREAK         0x04
+#define USB_CDC_ACM_SUPPORTS_LINE_PARAMS        0x02
+#define USB_CDC_ACM_SUPPORTS_COMM_FEATURE       0x01
+
+//*****************************************************************************
+//
+// USB_CDC_FD_SUBTYPE_DIRECT_LINE_MGMT, Direct Line Management functional
+// descriptor, bmCapabilities
+//
+//*****************************************************************************
+#define USB_CDC_DLM_NEEDS_EXTRA_PULSE_SETUP     0x04
+#define USB_CDC_DLM_SUPPORTS_AUX                0x02
+#define USB_CDC_DLM_SUPPORTS_PULSE              0x01
+
+//*****************************************************************************
+//
+// USB_CDC_FD_SUBTYPE_TELEPHONE_MODES, Telephone Operational Modes functional
+// descriptor, bmCapabilities
+//
+//*****************************************************************************
+#define USB_CDC_TELEPHONE_SUPPORTS_COMPUTER     0x04
+#define USB_CDC_TELEPHONE_SUPPORTS_STANDALONE   0x02
+#define USB_CDC_TELEPHONE_SUPPORTS_SIMPLE       0x01
+
+//*****************************************************************************
+//
+// USB_CDC_FD_SUBTYPE_LINE_STATE_CAPS, Telephone Call and Line State Reporting
+// Capabilities descriptor
+//
+//*****************************************************************************
+#define USB_CDC_LINE_STATE_CHANGES_NOTIFIED     0x20
+#define USB_CDC_LINE_STATE_REPORTS_DTMF         0x10
+#define USB_CDC_LINE_STATE_REPORTS_DIST_RING    0x08
+#define USB_CDC_LINE_STATE_REPORTS_CALLERID     0x04
+#define USB_CDC_LINE_STATE_REPORTS_BUSY         0x02
+#define USB_CDC_LINE_STATE_REPORTS_INT_DIALTONE 0x01
+
+//*****************************************************************************
+//
+// USB_CDC_FD_SUBTYPE_USB_TERMINAL, USB Terminal functional descriptor,
+// bmOptions
+//
+//*****************************************************************************
+#define USB_CDC_TERMINAL_NO_WRAPPER_USED        0x00
+#define USB_CDC_TERMINAL_WRAPPER_USED           0x01
+
+//*****************************************************************************
+//
+// USB_CDC_FD_SUBTYPE_MULTI_CHANNEL_MGMT, Multi-Channel Management functional
+// descriptor, bmCapabilities
+//
+//*****************************************************************************
+#define USB_CDC_MCM_SUPPORTS_SET_UNIT_PARAM     0x04
+#define USB_CDC_MCM_SUPPORTS_CLEAR_UNIT_PARAM   0x02
+#define USB_CDC_MCM_UNIT_PARAMS_NON_VOLATILE    0x01
+
+//*****************************************************************************
+//
+// USB_CDC_FD_SUBTYPE_CAPI_MGMT, CAPI Control Management functional descriptor,
+// bmCapabilities
+//
+//*****************************************************************************
+#define USB_CDC_CAPI_INTELLIGENT                0x01
+#define USB_CDC_CAPI_SIMPLE                     0x00
+
+//*****************************************************************************
+//
+// USB_CDC_FD_SUBTYPE_ETHERNET, Ethernet Networking functional descriptor,
+// bmEthernetStatistics
+//
+//*****************************************************************************
+#define USB_CDC_ETHERNET_XMIT_OK                0x01000000
+#define USB_CDC_ETHERNET_RCV_OK                 0x02000000
+#define USB_CDC_ETHERNET_XMIT_ERROR             0x04000000
+#define USB_CDC_ETHERNET_RCV_ERROR              0x08000000
+#define USB_CDC_ETHERNET_RCV_NO_BUFFER          0x10000000
+#define USB_CDC_ETHERNET_DIRECTED_BYTES_XMIT    0x20000000
+#define USB_CDC_ETHERNET_DIRECTED_FRAMES_XMIT   0x40000000
+#define USB_CDC_ETHERNET_MULTICAST_BYTES_XMIT   0x80000000
+#define USB_CDC_ETHERNET_MULTICAST_FRAMES_XMIT  0x00010000
+#define USB_CDC_ETHERNET_BROADCAST_BYTES_XMIT   0x00020000
+#define USB_CDC_ETHERNET_BROADCAST_FRAMES_XMIT  0x00040000
+#define USB_CDC_ETHERNET_DIRECTED_BYTES_RCV     0x00080000
+#define USB_CDC_ETHERNET_DIRECTED_FRAMES_RCV    0x00100000
+#define USB_CDC_ETHERNET_MULTICAST_BYTES_RCV    0x00200000
+#define USB_CDC_ETHERNET_MULTICAST_FRAMES_RCV   0x00400000
+#define USB_CDC_ETHERNET_BROADCAST_BYTES_RCV    0x00800000
+#define USB_CDC_ETHERNET_BROADCAST_FRAMES_RCV   0x00000100
+#define USB_CDC_ETHERNET_RCV_CRC_ERROR          0x00000200
+#define USB_CDC_ETHERNET_TRANSMIT_QUEUE_LENGTH  0x00000400
+#define USB_CDC_ETHERNET_RCV_ERROR_ALIGNMENT    0x00000800
+#define USB_CDC_ETHERNET_XMIT_ONE_COLLISION     0x00001000
+#define USB_CDC_ETHERNET_XMIT_MORE_COLLISIONS   0x00002000
+#define USB_CDC_ETHERNET_XMIT_DEFERRED          0x00004000
+#define USB_CDC_ETHERNET_XMIT_MAX_COLLISIONS    0x00008000
+#define USB_CDC_ETHERNET_RCV_OVERRUN            0x00000001
+#define USB_CDC_ETHERNET_XMIT_UNDERRUN          0x00000002
+#define USB_CDC_ETHERNET_XMIT_HEARTBEAT_FAILURE 0x00000004
+#define USB_CDC_ETHERNET_XMIT_TIMES_CRS_LOST    0x00000008
+#define USB_CDC_ETHERNET_XMIT_LATE_COLLISIONS   0x00000010
+
+//*****************************************************************************
+//
+// USB_CDC_FD_SUBTYPE_ATM, ATM Networking functional descriptor,
+// bmDataCapabilities
+//
+//*****************************************************************************
+#define USB_CDC_ATM_TYPE_3                      0x08
+#define USB_CDC_ATM_TYPE_2                      0x04
+#define USB_CDC_ATM_TYPE_1                      0x02
+
+//*****************************************************************************
+//
+// bmATMDeviceStatistics
+//
+//*****************************************************************************
+#define USB_CDC_ATM_VC_US_CELLS_SENT            0x10
+#define USB_CDC_ATM_VC_US_CELLS_RECEIVED        0x08
+#define USB_CDC_ATM_DS_CELLS_HEC_ERR_CORRECTED  0x04
+#define USB_CDC_ATM_US_CELLS_SENT               0x02
+#define USB_CDC_ATM_US_CELLS_RECEIVED           0x01
+
+//*****************************************************************************
+//
+// Management Element Requests (provided in tUSBRequest.ucRequest)
+//
+//*****************************************************************************
+#define USB_CDC_SEND_ENCAPSULATED_COMMAND                       0x00
+#define USB_CDC_GET_ENCAPSULATED_RESPONSE                       0x01
+#define USB_CDC_SET_COMM_FEATURE                                0x02
+#define USB_CDC_GET_COMM_FEATURE                                0x03
+#define USB_CDC_CLEAR_COMM_FEATURE                              0x04
+#define USB_CDC_SET_AUX_LINE_STATE                              0x10
+#define USB_CDC_SET_HOOK_STATE                                  0x11
+#define USB_CDC_PULSE_SETUP                                     0x12
+#define USB_CDC_SEND_PULSE                                      0x13
+#define USB_CDC_SET_PULSE_TIME                                  0x14
+#define USB_CDC_RING_AUX_JACK                                   0x15
+#define USB_CDC_SET_LINE_CODING                                 0x20
+#define USB_CDC_GET_LINE_CODING                                 0x21
+#define USB_CDC_SET_CONTROL_LINE_STATE                          0x22
+#define USB_CDC_SEND_BREAK                                      0x23
+#define USB_CDC_SET_RINGER_PARMS                                0x30
+#define USB_CDC_GET_RINGER_PARMS                                0x31
+#define USB_CDC_SET_OPERATION_PARMS                             0x32
+#define USB_CDC_GET_OPERATION_PARMS                             0x33
+#define USB_CDC_SET_LINE_PARMS                                  0x34
+#define USB_CDC_GET_LINE_PARMS                                  0x35
+#define USB_CDC_DIAL_DIGITS                                     0x36
+#define USB_CDC_SET_UNIT_PARAMETER                              0x37
+#define USB_CDC_GET_UNIT_PARAMETER                              0x38
+#define USB_CDC_CLEAR_UNIT_PARAMETER                            0x39
+#define USB_CDC_GET_PROFILE                                     0x3A
+#define USB_CDC_SET_ETHERNET_MULTICAST_FILTERS                  0x40
+#define USB_CDC_SET_ETHERNET_POWER_MANAGEMENT_PATTERN_FILTER    0x41
+#define USB_CDC_GET_ETHERNET_POWER_MANAGEMENT_PATTERN_FILTER    0x42
+#define USB_CDC_SET_ETHERNET_PACKET_FILTER                      0x43
+#define USB_CDC_GET_ETHERNET_STATISTIC                          0x44
+#define USB_CDC_SET_ATM_DATA_FORMAT                             0x50
+#define USB_CDC_GET_ATM_DEVICE_STATISTICS                       0x51
+#define USB_CDC_SET_ATM_DEFAULT_VC                              0x52
+#define USB_CDC_GET_ATM_VC_STATISTICS                           0x53
+
+//*****************************************************************************
+//
+// In cases where a request defined above results in the return of a fixed size
+// data block, the following group of labels define the size of that block.  In
+// each of these cases, an access macro is also provided to write the response
+// data into an appropriately-sized array of unsigned characters.
+//
+//*****************************************************************************
+#define USB_CDC_SIZE_COMM_FEATURE                                2
+#define USB_CDC_SIZE_LINE_CODING                                 7
+#define USB_CDC_SIZE_RINGER_PARMS                                4
+#define USB_CDC_SIZE_OPERATION_PARMS                             2
+#define USB_CDC_SIZE_UNIT_PARAMETER                              2
+#define USB_CDC_SIZE_PROFILE                                     64
+#define USB_CDC_SIZE_ETHERNET_POWER_MANAGEMENT_PATTERN_FILTER    2
+#define USB_CDC_SIZE_ETHERNET_STATISTIC                          4
+#define USB_CDC_SIZE_ATM_DEVICE_STATISTICS                       4
+#define USB_CDC_SIZE_ATM_VC_STATISTICS                           4
+#define USB_CDC_SIZE_LINE_PARMS                                  10
+
+//*****************************************************************************
+//
+// NB: USB_CDC_SIZE_LINE_PARAMS assumes only a single call.  For multiple
+// calls, add 4 bytes per additional call.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// USB_CDC_GET_COMM_FEATURE & USB_CDC_SET_COMM_FEATURE
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// wValue (Feature Selector)
+//
+//*****************************************************************************
+#define USB_CDC_ABSTRACT_STATE                  0x0001
+#define USB_CDC_COUNTRY_SETTING                 0x0002
+
+//*****************************************************************************
+//
+// Data when feature selector is USB_DCD_ABSTRACT_STATE
+//
+//*****************************************************************************
+#define USB_CDC_ABSTRACT_CALL_DATA_MULTIPLEXED  0x0002
+#define USB_CDC_ABSTRACT_ENDPOINTS_IDLE         0x0001
+
+//*****************************************************************************
+//
+// Macros to populate the response data buffer (whose size in bytes is defined
+// by USB_CDC_SIZE_COMM_FEATURE).
+//
+//*****************************************************************************
+#define SetResponseCommFeature(pcBuf, usData)        \
+        do                                           \
+        {                                            \
+            (*(unsigned short *)(pcBuf)) = (usData); \
+        }                                            \
+        while(0)
+
+//*****************************************************************************
+//
+// USB_CDC_SET_AUX_LINE_STATE, wValue
+//
+//*****************************************************************************
+#define USB_CDC_AUX_DISCONNECT                  0x0000
+#define USB_CDC_AUX_CONNECT                     0x0001
+
+//*****************************************************************************
+//
+// USB_CDC_SET_HOOK_STATE, wValue
+//
+//*****************************************************************************
+#define USB_CDC_ON_HOOK                         0x0000
+#define USB_CDC_OFF_HOOK                        0x0001
+#define USB_CDC_SNOOPING                        0x0002
+
+//*****************************************************************************
+//
+// USB_CDC_GET_LINE_CODING
+//
+//*****************************************************************************
+#define USB_CDC_STOP_BITS_1                     0x00
+#define USB_CDC_STOP_BITS_1_5                   0x01
+#define USB_CDC_STOP_BITS_2                     0x02
+
+#define USB_CDC_PARITY_NONE                     0x00
+#define USB_CDC_PARITY_ODD                      0x01
+#define USB_CDC_PARITY_EVEN                     0x02
+#define USB_CDC_PARITY_MARK                     0x03
+#define USB_CDC_PARITY_SPACE                    0x04
+
+//*****************************************************************************
+//
+// Macro to populate the response data buffer (whose size in bytes is defined
+// by USB_CDC_SIZE_LINE_CODING).
+//
+//*****************************************************************************
+#define SetResponseLineCoding(pcBuf, ucRate, ucStop, ucParity, ucDatabits) \
+        do                                                                 \
+        {                                                                  \
+            (*(unsigned long *)(pcBuf)) = (ucRate);                        \
+            (*((unsigned char *)(pcBuf) + 4)) = (ucStop);                  \
+            (*((unsigned char *)(pcBuf) + 5)) = (ucParity);                \
+            (*((unsigned char *)(pcBuf) + 6)) = (ucDatabits);              \
+        }                                                                  \
+        while(0)
+
+//*****************************************************************************
+//
+// USB_CDC_SET_CONTROL_LINE_STATE, wValue
+//
+//*****************************************************************************
+#define USB_CDC_DEACTIVATE_CARRIER              0x00
+#define USB_CDC_ACTIVATE_CARRIER                0x02
+#define USB_CDC_DTE_NOT_PRESENT                 0x00
+#define USB_CDC_DTE_PRESENT                     0x01
+
+//*****************************************************************************
+//
+// USB_CDC_SET_RINGER_PARMS, USB_CDC_GET_RINGER_PARMS and
+// USB_CDC_GET_LINE_PARMS (ulRingerBmp)
+//
+//*****************************************************************************
+#define USB_CDC_RINGER_EXISTS                   0x80000000
+#define USB_CDC_RINGER_DOES_NOT_EXIST           0x00000000
+
+//*****************************************************************************
+//
+// Macro to populate the response data buffer to USB_CDC_GET_RINGER_PARMS.
+// Parameter buf points to a buffer of size USB_CDC_SIZE_RINGER_PARMS bytes.
+//
+//*****************************************************************************
+#define SetResponseRingerParms(pcBuf, ucPattern, ucVolume, ulExists)          \
+        do                                                                    \
+        {                                                                     \
+            *(unsigned long *)(pcBuf) = ((ucPattern) +                        \
+                                         ((ucVolume & 0xFF) << 8) +           \
+                                         (ulExists & USB_CDC_RINGER_EXISTS)); \
+        }                                                                     \
+        while(0)
+
+//*****************************************************************************
+//
+// Macros to extract fields from the USB_CDC_SET_RINGER_PARMS data
+//
+//*****************************************************************************
+#define GetRingerVolume(pcData)  (BYTE((pcData)+1))
+#define GetRingerPattern(pcData) (BYTE(pcData))
+#define GetRingerExists(pcData)  ((LONG(pcData)) & USB_CDC_RINGER_EXISTS)
+
+//*****************************************************************************
+//
+// USB_CDC_SET_OPERATION_PARMS, wValue
+//
+//*****************************************************************************
+#define USB_CDC_SIMPLE_MODE                     0x0000
+#define USB_CDC_STANDALONE_MODE                 0x0001
+#define USB_CDC_HOST_CENTRIC_MODE               0x0002
+
+//*****************************************************************************
+//
+// Macro to populate the response data buffer to USB_CDC_GET_OPERATION_PARMS.
+// Parameter buf points to a buffer of size USB_CDC_SIZE_OPERATION_PARMS
+// bytes.
+//
+//*****************************************************************************
+#define SetResponseOperationParms(pBbuf, usData) \
+        do                                       \
+        {                                        \
+            WORD(pcBuf) = (usData);              \
+        }                                        \
+        while(0)
+
+//*****************************************************************************
+//
+// USB_CDC_SET_LINE_PARMS, wParam - Line State Change
+//
+//*****************************************************************************
+#define USB_CDC_DROP_ACTIVE_CALL                0x0000
+#define USB_CDC_START_NEW_CALL                  0x0001
+#define USB_CDC_APPLY_RINGING                   0x0002
+#define USB_CDC_REMOVE_RINGING                  0x0003
+#define USB_CDC_SWITCH_CALL                     0x0004
+
+//*****************************************************************************
+//
+// Line state bitmap in USB_CDC_GET_LINE_PARMS response
+//
+//*****************************************************************************
+#define USB_CDC_LINE_IS_ACTIVE                  0x80000000
+#define USB_CDC_LINE_IS_IDLE                    0x00000000
+#define USB_CDC_LINE_NO_ACTIVE_CALL             0x000000FF
+
+#define USB_CDC_CALL_ACTIVE                     0x80000000
+
+//*****************************************************************************
+//
+// Call state value definitions
+//
+//*****************************************************************************
+#define USB_CDC_CALL_IDLE                       0x00000000
+#define USB_CDC_CALL_TYPICAL_DIALTONE           0x00000001
+#define USB_CDC_CALL_INTERRUPTED_DIALTONE       0x00000002
+#define USB_CDC_CALL_DIALING                    0x00000003
+#define USB_CDC_CALL_RINGBACK                   0x00000004
+#define USB_CDC_CALL_CONNECTED                  0x00000005
+#define USB_CDC_CALL_INCOMING                   0x00000006
+
+//*****************************************************************************
+//
+// Call state change value definitions
+//
+//*****************************************************************************
+#define USB_CDC_CALL_STATE_IDLE                 0x01
+#define USB_CDC_CALL_STATE_DIALING              0x02
+#define USB_CDC_CALL_STATE_RINGBACK             0x03
+#define USB_CDC_CALL_STATE_CONNECTED            0x04
+#define USB_CDC_CALL_STATE_INCOMING             0x05
+
+//*****************************************************************************
+//
+// Extra byte of data describing the connection type for
+// USB_CDC_CALL_STATE_CONNECTED.
+//
+//*****************************************************************************
+#define USB_CDC_VOICE                           0x00
+#define USB_CDC_ANSWERING_MACHINE               0x01
+#define USB_CDC_FAX                             0x02
+#define USB_CDC_MODEM                           0x03
+#define USB_CDC_UNKNOWN                         0xFF
+
+//*****************************************************************************
+//
+// Macro to extract call index from request in cases where wParam is
+// USB_CDC_SWITCH_CALL.
+//
+//*****************************************************************************
+#define GetCallIndex(pcData) (BYTE(pcData))
+
+//*****************************************************************************
+//
+// Macro to populate the CallState entries in response to request
+// USB_CDC_GET_LINE_PARMS.  The ucIndex parameter is a zero based index
+// indicating which call entry in the pcBuf response buffer to fill in.  Note
+// that pcBuf points to the first byte of the buffer (the wLength field).
+//
+//*****************************************************************************
+#define SetResponseCallState(pcBuf, ucIndex, ulActive, ucStateChange,   \
+                             ucState)                                   \
+        do                                                              \
+        {                                                               \
+            (LONG((unsigned char *)(pcBuf) + (10 + (4 * (ucIndex))))) = \
+                (((ulActive) & USB_CDC_CALL_IS_ACTIVE) +                \
+                 (((ucStateChange) & 0xFF) << 8) +                      \
+                 ((ucState) & 0xFF));                                   \
+        }                                                               \
+        while(0)
+
+//*****************************************************************************
+//
+// Macro to populate the response data buffer (whose size in bytes is defined
+// by USB_CDC_SIZE_LINE_PARMS).  Note that this macro only populates fields for
+// a single call.  If multiple calls are being managed, additional 4 byte
+// fields must be appended to provide call state for each call after the first.
+// This may be done using the SetResponseCallState macro with the appropriate
+// call index supplied.
+//
+//*****************************************************************************
+#define SetResponseLineParms(pcBuf, usLength,                              \
+                             ucRingPattern, ucRingVolume, ulRingExists,    \
+                             ulLineActive, ucLineCallIndex,                \
+                             ulCallActive, ucCallStateChange, ucCallState) \
+        do                                                                 \
+        {                                                                  \
+            (WORD(pcBuf)) = (usLength);                                    \
+            SetResponseRingerParams(((unsigned char *)(pcBuf) + 2),        \
+                                    (ucRingPattern), (ucRingVolume),       \
+                                    (ulRingExists));                       \
+            (LONG((unsigned char *)(pcBuf) + 6)) =                         \
+                (((ulLineActive) & USB_CDC_LINE_IS_ACTIVE) +               \
+                 ((ucLineCallIndex) & 0xFF)) ;                             \
+            SetResponseCallState((pcBuf), 0, (ulCallActive),               \
+                                 (ucCallStateChange), (ucCallState));      \
+        }                                                                  \
+        while(0)
+
+//*****************************************************************************
+//
+// Notification Element definitions
+//
+//*****************************************************************************
+#define USB_CDC_NOTIFY_NETWORK_CONNECTION               0x00
+#define USB_CDC_NOTIFY_RESPONSE_AVAILABLE               0x01
+#define USB_CDC_NOTIFY_AUX_JACK_HOOK_STATE              0x08
+#define USB_CDC_NOTIFY_RING_DETECT                      0x09
+#define USB_CDC_NOTIFY_SERIAL_STATE                     0x20
+#define USB_CDC_NOTIFY_CALL_STATE_CHANGE                0x28
+#define USB_CDC_NOTIFY_LINE_STATE_CHANGE                0x29
+#define USB_CDC_NOTIFY_CONNECTION_SPEED_CHANGE          0x2A
+
+//*****************************************************************************
+//
+// USB_CDC_NOTIFY_NETWORK_CONNECTION, wValue
+//
+//*****************************************************************************
+#define USB_CDC_NETWORK_DISCONNECTED                    0x0000
+#define USB_CDC_NETWORK_CONNECTED                       0x0001
+
+//*****************************************************************************
+//
+// USB_CDC_NOTIFY_AUX_JACK_HOOK_STATE, wValue
+//
+//*****************************************************************************
+#define USB_CDC_AUX_JACK_ON_HOOK                        0x0000
+#define USB_CDC_AUX_JACK_OFF_HOOK                       0x0001
+
+//*****************************************************************************
+//
+// USB_CDC_NOTIFY_SERIAL_STATE, Data
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Number of bytes of data returned alongside this notification.
+//
+//*****************************************************************************
+#define USB_CDC_NOTIFY_SERIAL_STATE_SIZE                2
+
+#define USB_CDC_SERIAL_STATE_OVERRUN                    0x0040
+#define USB_CDC_SERIAL_STATE_PARITY                     0x0020
+#define USB_CDC_SERIAL_STATE_FRAMING                    0x0010
+#define USB_CDC_SERIAL_STATE_RING_SIGNAL                0x0008
+#define USB_CDC_SERIAL_STATE_BREAK                      0x0004
+#define USB_CDC_SERIAL_STATE_TXCARRIER                  0x0002
+#define USB_CDC_SERIAL_STATE_RXCARRIER                  0x0001
+
+//*****************************************************************************
+//
+// USB_CDC_NOTIFY_CALL_STATE_CHANGE, wValue
+//
+// Call state values are defined above in the group beginning
+// USB_CDC_CALL_STATE_IDLE.  Note that the data returned alongside this
+// notification are heavily dependent upon the call state being reported so no
+// specific lengths or access macros are provided here.
+//
+// Macro to construct the correct wValue for this notification given a state
+// and call index.
+//
+//*****************************************************************************
+#define SetNotifyCallStatewValue(psResult, ucCallState, ucIndex) \
+        do                                                       \
+        {                                                        \
+            (WORD(psResult)) = (((ucCallState) & 0xFF) +         \
+                                (((ucIndex) & 0xFF) << 8));      \
+        }                                                        \
+        while(0)
+
+//*****************************************************************************
+//
+// USB_CDC_NOTIFY_LINE_STATE_CHANGE, wValue
+//
+// Note that the data returned alongside this notification are heavily
+// dependent upon the call state being reported so no specific lengths or
+// access macros are provided here.
+//
+//*****************************************************************************
+#define USB_CDC_LINE_STATE_IDLE                         0x0000
+#define USB_CDC_LINE_STATE_HOLD                         0x0001
+#define USB_CDC_LINE_STATE_OFF_HOOK                     0x0002
+#define USB_CDC_LINE_STATE_ON_HOOK                      0x0003
+
+//*****************************************************************************
+//
+// USB_CDC_NOTIFY_CONNECTION_SPEED_CHANGE, Data
+//
+// Macro to populate the 8 byte data structure returned alongside this
+// notification.
+//
+//*****************************************************************************
+#define SetNotifyConnectionSpeedChange(pcBuf, ulUSBitRate, ulDSBitRate) \
+        do                                                              \
+        {                                                               \
+            LONG(pcBuf) = ulUSBitRate;                                  \
+            LONG((unsigned char *)(pcBuf) + 4) = ulDSBitRate;           \
+        }                                                               \
+        while(0)
+
+//*****************************************************************************
+//
+// Packed structure definitions for request/response data blocks
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// All structures defined in this section of the header require byte packing of
+// fields.  This is usually accomplished using the PACKED macro but, for IAR
+// Embedded Workbench, this requires a pragma.
+//
+//*****************************************************************************
+#ifdef ewarm
+#pragma pack(1)
+#endif
+
+//*****************************************************************************
+//
+//! USB_CDC_GET/SET_LINE_CODING request-specific data.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! The data terminal rate in bits per second.
+    //
+    unsigned long ulRate;
+
+    //
+    //! The number of stop bits.  Valid values are USB_CDC_STOP_BITS_1,
+    //! USB_CDC_STOP_BITS_1_5 or USB_CDC_STOP_BITS_2
+    //
+    unsigned char ucStop;
+
+    //
+    //! The parity setting.  Valid values are USB_CDC_PARITY_NONE,
+    //! USB_CDC_PARITY_ODD, USB_CDC_PARITY_EVEN, USB_CDC_PARITY_MARK and
+    //! USB_CDC_PARITY_SPACE.
+    //
+    unsigned char ucParity;
+
+    //
+    //! The number of data bits per character.  Valid values are 5, 6, 7 and 8
+    //! in this implementation.
+    //
+    unsigned char ucDatabits;
+}
+PACKED tLineCoding;
+
+//*****************************************************************************
+//
+// Return to default packing when using the IAR Embedded Workbench compiler.
+//
+//*****************************************************************************
+#ifdef ewarm
+#pragma pack()
+#endif
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __USBCDC_H__
diff --git a/src/platform/lm3s/usblib/usbdesc.c b/src/platform/lm3s/usblib/usbdesc.c
new file mode 100755
index 00000000..777703c3
--- /dev/null
+++ b/src/platform/lm3s/usblib/usbdesc.c
@@ -0,0 +1,478 @@
+//*****************************************************************************
+//
+// usbdesc.c - USB descriptor parsing functions.
+//
+// Copyright (c) 2008-2011 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 7611 of the Stellaris USB Library.
+//
+//*****************************************************************************
+
+#include "inc/hw_types.h"
+#include "usblib/usblib.h"
+
+//*****************************************************************************
+//
+// Assumptions:
+// ------------
+//
+// The following assumptions are made in this module.  From reading chapter 9
+// of the USB 2.0 specification, these appear to be perfectly valid.
+//
+// 1.  The interface number, bInterfaceNumber in the interface descriptor, is
+//     a zero based index and takes values between 0 and
+//     (pConfigDescriptor->bNumInterfaces - 1) inclusive.
+// 2.  Similarly, the alternate setting number, bAlternateSetting in the
+//     interface descriptor, is a zero based index.
+// 3.  Interface descriptors are ordered by interface number in the
+//     configuration descriptor.
+// 4.  If alternate settings are available for an interface, the interface
+//     descriptors are ordered by alternate setting value bAlternateSetting.
+// 5.  Although the endpoints associated with a given interface must follow
+//     their associated interface descriptor, it is possible for other,
+//     device specific descriptors to be found between an interface descriptor
+//     and its endpoints or between endpoint descriptors for the same
+//     interface.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup general_usblib_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! Determines the number of individual descriptors of a particular type within
+//! a supplied buffer.
+//!
+//! \param psDesc points to the first byte of a block of standard USB
+//! descriptors.
+//! \param ulSize is the number of bytes of descriptor data found at pointer
+//! \e psDesc.
+//! \param ulType identifies the type of descriptor that is to be counted.  If
+//! the value is \b USB_DESC_ANY, the function returns the total number of
+//! descriptors regardless of type.
+//!
+//! This function can be used to count the number of descriptors of a
+//! particular type within a block of descriptors.  The caller can provide a
+//! specific type value which the function matches against the second byte of
+//! each descriptor or, alternatively, can specify \b USB_DESC_ANY to have the
+//! function count all descriptors regardless of their type.
+//!
+//! \return Returns the number of descriptors found in the supplied block of
+//! data.
+//
+//*****************************************************************************
+unsigned long
+USBDescGetNum(tDescriptorHeader *psDesc,  unsigned long ulSize,
+              unsigned long ulType)
+{
+    tDescriptorHeader *psDescCheck;
+    unsigned long ulTotLength;
+    unsigned long ulCount;
+
+    //
+    // Set up for our descriptor counting loop.
+    //
+    psDescCheck = psDesc;
+    ulTotLength = 0;
+    ulCount = 0;
+
+    //
+    // Keep looking through the supplied data until we reach the end.
+    //
+    while(ulTotLength < ulSize)
+    {
+        //
+        // Does this descriptor match the type passed (if a specific type
+        // has been specified)?
+        //
+        if((ulType == USB_DESC_ANY) ||
+           (psDescCheck->bDescriptorType == (unsigned char)(ulType & 0xFF)))
+        {
+            ulCount++;
+        }
+
+        //
+        // Move on to the next descriptor.
+        //
+        ulTotLength += (unsigned long)psDescCheck->bLength;
+        psDescCheck = NEXT_USB_DESCRIPTOR(psDescCheck);
+    }
+
+    //
+    // Return the descriptor count to the caller.
+    //
+    return(ulCount);
+}
+
+//*****************************************************************************
+//
+//! Determines the number of individual descriptors of a particular type within
+//! a supplied buffer.
+//!
+//! \param psDesc points to the first byte of a block of standard USB
+//! descriptors.
+//! \param ulSize is the number of bytes of descriptor data found at pointer
+//! \e psDesc.
+//! \param ulType identifies the type of descriptor that is to be found.  If
+//! the value is \b USB_DESC_ANY, the function returns a pointer to the n-th
+//! descriptor regardless of type.
+//! \param ulIndex is the zero based index of the descriptor whose pointer is
+//! to be returned.  For example, passing value 1 in \e ulIndex returns the
+//! second matching descriptor.
+//!
+//! Return a pointer to the n-th descriptor of a particular type found in the
+//! block of \e ulSize bytes starting at \e psDesc.
+//!
+//! \return Returns a pointer to the header of the required descriptor if
+//! found or NULL otherwise.
+//
+//*****************************************************************************
+tDescriptorHeader *
+USBDescGet(tDescriptorHeader *psDesc,  unsigned long ulSize,
+           unsigned long ulType, unsigned long ulIndex)
+{
+    tDescriptorHeader *psDescCheck;
+    unsigned long ulTotLength;
+    unsigned long ulCount;
+
+    //
+    // Set up for our descriptor counting loop.
+    //
+    psDescCheck = psDesc;
+    ulTotLength = 0;
+    ulCount = 0;
+
+    //
+    // Keep looking through the supplied data until we reach the end.
+    //
+    while(ulTotLength < ulSize)
+    {
+        //
+        // Does this descriptor match the type passed (if a specific type
+        // has been specified)?
+        //
+        if((ulType == USB_DESC_ANY) ||
+           (psDescCheck->bDescriptorType == (unsigned char)(ulType & 0xFF)))
+        {
+            //
+            // We found a matching descriptor.  If our count matches the
+            // supplied index, we are done so return the pointer.
+            //
+            if(ulCount == ulIndex)
+            {
+                return(psDescCheck);
+            }
+
+            //
+            // We have not found enough descriptors yet to satisfy the supplied
+            // index so increment our count and continue.
+            //
+            ulCount++;
+        }
+
+        //
+        // Move on to the next descriptor.
+        //
+        ulTotLength += (unsigned long)psDescCheck->bLength;
+        psDescCheck = NEXT_USB_DESCRIPTOR(psDescCheck);
+    }
+
+    //
+    // If we get here, we reached the end of the data without finding the
+    // required descriptor.  Return NULL.
+    //
+    return((tDescriptorHeader *)0);
+}
+
+//*****************************************************************************
+//
+//! Determines the number of different alternate configurations for a given
+//! interface within a configuration descriptor.
+//!
+//! \param psConfig points to the first byte of a standard USB configuration
+//! descriptor.
+//! \param ucInterfaceNumber is the interface number for which the number of
+//! alternate configurations is to be counted.
+//!
+//! This function can be used to count the number of alternate settings for a
+//! specific interface within a configuration.
+//!
+//! \return Returns the number of alternate versions of the specified interface
+//! or 0 if the interface number supplied cannot be found in the config
+//! descriptor.
+//
+//*****************************************************************************
+unsigned long
+USBDescGetNumAlternateInterfaces(tConfigDescriptor *psConfig,
+                                 unsigned char ucInterfaceNumber)
+{
+    tDescriptorHeader *psDescCheck;
+    unsigned long ulTotLength;
+    unsigned long ulCount;
+
+    //
+    // Set up for our descriptor counting loop.
+    //
+    psDescCheck = (tDescriptorHeader *)psConfig;
+    ulTotLength = 0;
+    ulCount = 0;
+
+    //
+    // Keep looking through the supplied data until we reach the end.
+    //
+    while(ulTotLength < (unsigned long)psConfig->wTotalLength)
+    {
+        //
+        // Is this an interface descriptor with the required interface number?
+        //
+        if((psDescCheck->bDescriptorType == USB_DTYPE_INTERFACE) &&
+            (((tInterfaceDescriptor *)psDescCheck)->bInterfaceNumber ==
+             ucInterfaceNumber))
+        {
+            //
+            // Yes - increment our count.
+            //
+            ulCount++;
+        }
+
+        //
+        // Move on to the next descriptor.
+        //
+        ulTotLength += (unsigned long)psDescCheck->bLength;
+        psDescCheck = NEXT_USB_DESCRIPTOR(psDescCheck);
+    }
+
+    //
+    // Return the descriptor count to the caller.
+    //
+    return(ulCount);
+}
+
+//*****************************************************************************
+//
+//! Returns a pointer to the n-th interface descriptor in a config descriptor
+//! with the supplied interface number.
+//!
+//! \param psConfig points to the first byte of a standard USB configuration
+//! descriptor.
+//! \param ucInterfaceNumber is the interface number of the descriptor that is
+//! being queried.
+//! \param ulIndex is the zero based index of the descriptor to return.
+//!
+//! This function returns a pointer to the n-th interface descriptor in the
+//! supplied configuration which has the requested interface number.  It may be
+//! used by a client to retrieve the descriptors for each alternate setting
+//! of a given interface within the configuration passed.
+//!
+//! \return Returns a pointer to the n-th interface descriptor with interface
+//! number as specified or NULL of this descriptor does not exist.
+//
+//*****************************************************************************
+static tInterfaceDescriptor *
+USBDescGetAlternateInterface(tConfigDescriptor *psConfig,
+                             unsigned char ucInterfaceNumber,
+                             unsigned long ulIndex)
+{
+    tDescriptorHeader *psDescCheck;
+    unsigned long ulTotLength;
+    unsigned long ulCount;
+
+    //
+    // Set up for our descriptor counting loop.
+    //
+    psDescCheck = (tDescriptorHeader *)psConfig;
+    ulTotLength = 0;
+    ulCount = 0;
+
+    //
+    // Keep looking through the supplied data until we reach the end.
+    //
+    while(ulTotLength < (unsigned long)psConfig->wTotalLength)
+    {
+        //
+        // Does this descriptor match the type passed (if a specific type
+        // has been specified)?
+        //
+        if((psDescCheck->bDescriptorType == USB_DTYPE_INTERFACE) &&
+            (((tInterfaceDescriptor *)psDescCheck)->bInterfaceNumber ==
+             ucInterfaceNumber))
+        {
+            //
+            // This is an interface descriptor for interface ucInterfaceNumber.
+            // Determine if this is the n-th one we have found and, if so,
+            // return its pointer.
+            //
+            if(ulCount == ulIndex)
+            {
+                //
+                // Found it - return the pointer.
+                //
+                return((tInterfaceDescriptor *)psDescCheck);
+            }
+
+            //
+            // Increment our count of matching descriptors found and go back
+            // to look for another since we have not yet reached the n-th
+            // match.
+            //
+            ulCount++;
+        }
+
+        //
+        // Move on to the next descriptor.
+        //
+        ulTotLength += (unsigned long)psDescCheck->bLength;
+        psDescCheck = NEXT_USB_DESCRIPTOR(psDescCheck);
+    }
+
+    //
+    // If we drop out the end of the loop, we did not find the requested
+    // descriptor so return NULL.
+    //
+    return((tInterfaceDescriptor *)0);
+}
+
+//*****************************************************************************
+//
+//! Returns a pointer to the n-th interface descriptor in a configuration
+//! descriptor that applies to the supplied alternate setting number.
+//!
+//! \param psConfig points to the first byte of a standard USB configuration
+//! descriptor.
+//! \param ulIndex is the zero based index of the interface that is to be
+//! found.  If ulAlt is set to a value other than \b USB_DESC_ANY, this will be
+//! equivalent to the interface number being searched for.
+//! \param ulAlt is the alternate setting number which is to be
+//! searched for.  If this value is \b USB_DESC_ANY, the alternate setting
+//! is ignored and all interface descriptors are considered in the search.
+//!
+//! Return a pointer to the n-th interface descriptor found in the supplied
+//! configuration descriptor.  If \e ulAlt is not \b USB_DESC_ANY, only
+//! interface descriptors which are part of the supplied alternate setting are
+//! considered in the search otherwise all interface descriptors are
+//! considered.
+//!
+//! Note that, although alternate settings can be applied on an interface-by-
+//! interface basis, the number of interfaces offered is fixed for a given
+//! config descriptor.  Hence, this function will correctly find the unique
+//! interface descriptor for that interface's alternate setting number ulAlt
+//! if ulIndex is set to the required interface number and ulAlt is set to a
+//! valid alternate setting number for that interface.
+//!
+//! \return Returns a pointer to the required interface descriptor if
+//! found or NULL otherwise.
+//
+//*****************************************************************************
+tInterfaceDescriptor *
+USBDescGetInterface(tConfigDescriptor *psConfig, unsigned long ulIndex,
+                    unsigned long ulAlt)
+{
+    //
+    // If we are being told to ignore the alternate configuration, this boils
+    // down to a very simple query.
+    //
+    if(ulAlt == USB_DESC_ANY)
+    {
+        //
+        // Return the ulIndex-th interface descriptor we find in the
+        // configuration descriptor.
+        //
+        return((tInterfaceDescriptor *)USBDescGet(
+                          (tDescriptorHeader *)psConfig,
+                          (unsigned long)psConfig->wTotalLength,
+                          USB_DTYPE_INTERFACE, ulIndex));
+    }
+    else
+    {
+        //
+        // In this case, a specific alternate setting number is required.
+        // Given that interface numbers are zero based indices, we can
+        // pass the supplied ulIndex parameter directly as the interface
+        // number to USBDescGetAlternateInterface to retrieve the requested
+        // interface descriptor pointer.
+        //
+        return(USBDescGetAlternateInterface(psConfig, ulIndex, ulAlt));
+    }
+}
+
+//*****************************************************************************
+//
+//! Return a pointer to the n-th endpoint descriptor in the supplied
+//! interface descriptor.
+//!
+//! \param psInterface points to the first byte of a standard USB interface
+//! descriptor.
+//! \param ulIndex is the zero based index of the endpoint that is to be
+//! found.
+//! \param ulSize contains the maximum number of bytes that the function may
+//! search beyond \e psInterface while looking for the requested endpoint
+//! descriptor.
+//!
+//! Return a pointer to the n-th endpoint descriptor found in the supplied
+//! interface descriptor.  If the \e ulIndex parameter is invalid (greater
+//! than or equal to the bNumEndpoints field of the interface descriptor) or
+//! the endpoint cannot be found within \e ulSize bytes of the interface
+//! descriptor pointer, the function will return NULL.
+//!
+//! Note that, although the USB 2.0 specification states that endpoint
+//! descriptors must follow the interface descriptor that they relate to, it
+//! also states that device specific descriptors should follow any standard
+//! descriptor that they relate to.  As a result, we cannot assume that each
+//! interface descriptor will be followed by nothing but an ordered list of
+//! its own endpoints and, hence, the function needs to be provided ulSize to
+//! limit the search range.
+//!
+//! \return Returns a pointer to the requested endpoint descriptor if
+//! found or NULL otherwise.
+//
+//*****************************************************************************
+tEndpointDescriptor *
+USBDescGetInterfaceEndpoint(tInterfaceDescriptor *psInterface,
+                            unsigned long ulIndex, unsigned long ulSize)
+{
+    //
+    // Is the index passed valid?
+    //
+    if(ulIndex >= psInterface->bNumEndpoints)
+    {
+        //
+        // It's out of bounds so return a NULL.
+        //
+        return((tEndpointDescriptor *)0);
+    }
+    else
+    {
+        //
+        // Endpoint index is valid so find the descriptor.
+        //
+        return((tEndpointDescriptor *)USBDescGet(
+                         (tDescriptorHeader *)psInterface,
+                          ulSize, USB_DTYPE_ENDPOINT, ulIndex));
+    }
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/src/platform/lm3s/usblib/usbdfu.h b/src/platform/lm3s/usblib/usbdfu.h
new file mode 100755
index 00000000..c1be0939
--- /dev/null
+++ b/src/platform/lm3s/usblib/usbdfu.h
@@ -0,0 +1,430 @@
+//*****************************************************************************
+//
+// usbdfu.h - Definitions related to the USB Device Firmware Upgrade class.
+//
+// Copyright (c) 2008-2011 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 7611 of the Stellaris USB Library.
+//
+//*****************************************************************************
+
+#ifndef __USBDFU_H__
+#define __USBDFU_H__
+
+//*****************************************************************************
+//
+// DFU attributes as published in the functional descriptor.
+//
+//*****************************************************************************
+#define DFU_ATTR_WILL_DETACH        0x08
+#define DFU_ATTR_MANIFEST_TOLERANT  0x04
+#define DFU_ATTR_CAN_UPLOAD         0x02
+#define DFU_ATTR_CAN_DOWNLOAD       0x01
+
+//*****************************************************************************
+//
+// The states that the DFU device can be in.  These values are reported to
+// the host in response to a USBD_DFU_REQUEST_GETSTATE request.
+//
+//*****************************************************************************
+typedef enum
+{
+   STATE_APP_IDLE = 0,
+   STATE_APP_DETACH,
+   STATE_IDLE,
+   STATE_DNLOAD_SYNC,
+   STATE_DNBUSY,
+   STATE_DNLOAD_IDLE,
+   STATE_MANIFEST_SYNC,
+   STATE_MANIFEST,
+   STATE_MANIFEST_WAIT_RESET,
+   STATE_UPLOAD_IDLE,
+   STATE_ERROR
+}
+tDFUState;
+
+//*****************************************************************************
+//
+// The current error status of the DFU device.  These values are reported to
+// the host in response to a USBD_DFU_REQUEST_GETSTATUS request.
+//
+//*****************************************************************************
+typedef enum
+{
+   STATUS_OK = 0,
+   STATUS_ERR_TARGET,
+   STATUS_ERR_FILE,
+   STATUS_ERR_WRITE,
+   STATUS_ERR_ERASE,
+   STATUS_ERR_CHECK_ERASED,
+   STATUS_ERR_PROG,
+   STATUS_ERR_VERIFY,
+   STATUS_ERR_ADDRESS,
+   STATUS_ERR_NOTDONE,
+   STATUS_ERR_FIRMWARE,
+   STATUS_ERR_VENDOR,
+   STATUS_ERR_USBR,
+   STATUS_ERR_POR,
+   STATUS_ERR_UNKNOWN,
+   STATUS_ERR_STALLEDPKT
+}
+tDFUStatus;
+
+//*****************************************************************************
+//
+// The descriptor type for the DFU functional descriptor.
+//
+//*****************************************************************************
+#define USB_DFU_FUNC_DESCRIPTOR_TYPE   0x21
+
+//*****************************************************************************
+//
+// The subclass identifier for DFU as reported to the host in the
+// bInterfaceSubClass field of the DFU interface descriptor.
+//
+//*****************************************************************************
+#define USB_DFU_SUBCLASS                0x01
+
+//*****************************************************************************
+//
+// The protocol identifier for DFU as reported to the host in the
+// bInterfaceProtocol field of the DFU interface descriptor.
+//
+//*****************************************************************************
+#define USB_DFU_PROTOCOL                0x02
+#define USB_DFU_RUNTIME_PROTOCOL        0x01
+
+//*****************************************************************************
+//
+// DFU class-specific request identifiers.
+//
+//*****************************************************************************
+#define USBD_DFU_REQUEST_DETACH         0
+#define USBD_DFU_REQUEST_DNLOAD         1
+#define USBD_DFU_REQUEST_UPLOAD         2
+#define USBD_DFU_REQUEST_GETSTATUS      3
+#define USBD_DFU_REQUEST_CLRSTATUS      4
+#define USBD_DFU_REQUEST_GETSTATE       5
+#define USBD_DFU_REQUEST_ABORT          6
+
+//*****************************************************************************
+//
+// Request 1KB blocks from the host.  This value is published in the USB
+// functional descriptor.
+//
+//*****************************************************************************
+#define DFU_TRANSFER_SIZE       1024
+
+//*****************************************************************************
+//
+// Stellaris-specific request identifier.  This is used to determine whether
+// the target device supports our DFU command protocol.  It is expected that
+// a device not supporting our extensions will stall this request.  This
+// request is only supported while the DFU device is in STATE_IDLE.
+//
+// An IN request containing the following parameters will result in the device
+// sending back a tDFUQueryStellarisProtocol structure indicating that Stellaris
+// extensions are supported.  The actual values in wValue and wIndex have no
+// meaning other than to act as markers in the unlikely event that another
+// DFU device also choses to use request ID 0x42 for some other purpose.
+//
+// wValue        - 0x23(REQUEST_STELLARIS_VALUE)
+// wIndex        - Interface number
+// wLength       - sizeof(tDFUQueryStellarisProtocol)
+//
+//*****************************************************************************
+#define USBD_DFU_REQUEST_STELLARIS    0x42
+
+#define REQUEST_STELLARIS_VALUE 0x23
+
+#define LM_DFU_PROTOCOL_MARKER    0x4C4D
+#define LM_DFU_PROTOCOL_VERSION_1 0x0001
+
+#ifdef ewarm
+#pragma pack(1)
+#endif
+
+//*****************************************************************************
+//
+// The structure sent to the host when a valid USBD_DFU_REQUEST_STELLARIS is
+// received while the DFU device is in idle state.
+//
+//*****************************************************************************
+typedef struct
+{
+    unsigned short usMarker;        // LM_DFU_PROTOCOL_MARKER
+    unsigned short usVersion;       // LM_DFU_PROTOCOL_VERSION_1
+}
+PACKED tDFUQueryStellarisProtocol;
+
+//*****************************************************************************
+//
+// Structure sent to the host in response to USBD_DFU_REQUEST_GETSTATUS.
+//
+//*****************************************************************************
+typedef struct
+{
+    unsigned char bStatus;
+    unsigned char bwPollTimeout[3];
+    unsigned char bState;
+    unsigned char iString;
+}
+PACKED tDFUGetStatusResponse;
+
+//*****************************************************************************
+//
+// Firmware Download Commands
+//
+// The data passed on a USBD_DFU_REQUEST_DNLOAD request is comprised of a
+// header which instructs the boot loader how to interpret the block and
+// block-specific data.  The following definitions relate to the download
+// block headers.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Supported command identifiers
+//
+//*****************************************************************************
+#define DFU_CMD_PROG  0x01
+#define DFU_CMD_READ  0x02
+#define DFU_CMD_CHECK 0x03
+#define DFU_CMD_ERASE 0x04
+#define DFU_CMD_INFO  0x05
+#define DFU_CMD_BIN   0x06
+#define DFU_CMD_RESET 0x07
+
+//*****************************************************************************
+//
+// Generic download command header.
+//
+//*****************************************************************************
+typedef struct
+{
+    unsigned char ucCommand;     // Command identifier.
+    unsigned char ucData[7];     // Command-specific data elements.
+}
+PACKED tDFUDownloadHeader;
+
+//*****************************************************************************
+//
+// Header for the DFU_CMD_PROG command.
+//
+// This command is used to program a section of the flash with the binary data
+// which immediately follows the header. The start address of the data is
+// expressed as a 1KB block number so 0 would represent the bottom of flash
+// (which, incidentally, the USB boot loader will not let you program) and 0x10
+// would represent address 16KB or 16384 (0x4000).  The usLength field contains
+// the total number of bytes of data in the following programming operation.
+// The DFU device will not look for any command header on following
+// USBD_DFU_REQUEST_DNLOAD requests until the operation is completed or
+// aborted.
+//
+// By using this protocol, the DFU_CMD_PROG command header may be used as a
+// simple header on the binary files to be sent to the DFU device for
+// programming.  If we enforce the requirement that the DFU_CMD_PROG header is
+// applied to each USBD_DFU_REQUEST_DNLOAD (one per block), this means that the
+// host-side DFU application must be aware of the underlying protocol and
+// insert these headers dynamically during programming operations.  This could
+// be handled by post processing the binary to insert the headers at the
+// appropriate points but this would then tie the binary structure to the
+// chosen transfer size and break the operation if the transfer size were to
+// change in the future.
+//
+//*****************************************************************************
+typedef struct
+{
+    unsigned char  ucCommand;   // DFU_CMD_PROG
+    unsigned char  ucReserved;  // Reserved - set to 0x00.
+    unsigned short usStartAddr; // Block start address / 1024
+    unsigned long  ulLength;    // Total length, in bytes, of following data
+                                // for the complete download operation.
+}
+PACKED tDFUDownloadProgHeader;
+
+//*****************************************************************************
+//
+// Header for the DFU_CMD_READ and DFU_CMD_CHECK commands.
+//
+// This command may be used to set the address range whose content will be
+// returned on subsequent USBD_DFU_REQUEST_UPLOAD requests from the host.
+//
+// To read back a the contents of a region of flash, the host should send
+// USBD_DFU_REQUEST_DNLOAD with ucCommand DFU_CMD_READ, usStartAddr set to the
+// 1KB block start address and ulLength set to the number of bytes to read.
+// The host should then send one or more USBD_DFU_REQUEST_UPLOAD requests
+// to receive the current flash contents from the configured addresses.  Data
+// returned will include an 8 byte DFU_CMD_PROG prefix structure unless
+// the prefix has been disabled by sending a DFU_CMD_BIN command with the
+// bBinary parameter set to 1.
+//
+// To check that a region of flash is erased, the DFU_CMD_CHECK command should
+// be sent with usStartAddr and ulLength set to describe the region to check.
+// The host should then send a USBD_DFU_REQUEST_GETSTATUS.  If the erase check
+// was successful, the returned bStatus value will be STATUS_OK, otherwise it
+// will be STATUS_ERR_CHECK_ERASED. Note that ulLength passed must be a
+// a multiple of 4.  If this is not the case, the value will be truncated before
+// the check is performed.
+//
+//*****************************************************************************
+typedef struct
+{
+    unsigned char  ucCommand;    // DFU_CMD_READ or DFU_CMD_CHECK
+    unsigned char  ucReserved;   // Reserved - write to 0
+    unsigned short usStartAddr;  // Block start address / 1024
+    unsigned long  ulLength;     // The number of bytes of data to read back or
+                                 // check.
+}                                                       
+PACKED tDFUDownloadReadCheckHeader;
+
+//*****************************************************************************
+//
+// Header for the DFU_CMD_ERASE command.
+//
+// This command may be used to erase a number of flash blocks.  The address of
+// the first block to be erased is passed in usStartAddr with usNumBlocks
+// containing the number of blocks to be erased from this address.  The block
+// size of the device may be determined using the DFU_CMD_INFO command.
+//
+//*****************************************************************************
+typedef struct
+{
+    unsigned char  ucCommand;      // DFU_CMD_ERASE
+    unsigned char  ucReserved;     // Reserved - set to 0.
+    unsigned short usStartAddr;    // Block start address / 1024
+    unsigned short usNumBlocks;    // The number of blocks to erase.
+    unsigned char  ucReserved2[2]; // Reserved - set to 0.
+}
+PACKED tDFUDownloadEraseHeader;
+
+//*****************************************************************************
+//
+// Header for the DFU_CMD_INFO command.
+//
+// This command may be used to query information about the connected device.
+// After sending the command, the information is returned on the next
+// USBD_DFU_REQUEST_UPLOAD request.
+//
+//*****************************************************************************
+typedef struct
+{
+    unsigned char ucCommand;     // DFU_CMD_INFO
+    unsigned char ucReserved[7]; // Reserved - set to 0.
+}
+PACKED tDFUDownloadInfoHeader;
+
+
+//*****************************************************************************
+//
+// Header for the DFU_CMD_BIN command.
+//
+// This command may be used to set the format of uploaded data.  By default,
+// images read using USBD_DFU_REQUEST_UPLOAD are formatted with the appropriate
+// header to allow the same image to be flashed back to the device and have it
+// located at the address from which it originated.  This is a requirement of
+// the DFU class specification (section 6.2 "the uploaded image must be
+// usable in a subsequent download") but may not be helpful in some cases where
+// the application wishes to receive only the binary image from flash.  To
+// instruct the DFU device to omit the position and size header, send this
+// command with the bBinary field set to \b true prior to issuing a
+// USBD_DFU_REQUEST_UPLOAD for image data.  The format choice remains in effect
+// until the command is sent once again with bBinary set to \b false.
+//
+// Note that the format choice affects only image data sent and not responses
+// read via USBD_DFU_REQUEST_UPLOAD following Stellaris-specific commands such
+// as DFU_CMD_INFO.
+//
+//*****************************************************************************
+typedef struct
+{
+    unsigned char ucCommand;     // DFU_CMD_BIN
+    unsigned char bBinary;       // Set to true to omit image header or false
+                                 // to include it (the default).
+    unsigned char ucReserved[6]; // Reserved - set to 0.
+}
+PACKED tDFUDownloadBinHeader;
+
+//*****************************************************************************
+//
+// The DFU_CMD_RESET command uses a tDFUDownloadHeader structure since
+// only the ucCommand field is important.  This command causes an immediate
+// reset of the the target board.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! Payload returned in response to the DFU_CMD_INFO command.
+//!
+//! This is structure is returned in response to the first
+//! USBD_DFU_REQUEST_UPLOAD request following a DFU_CMD_INFO command.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! The size of a flash block in bytes.
+    //
+    unsigned short usFlashBlockSize;
+
+    //
+    //! The number of blocks of flash in the  device.  Total flash size is
+    //! usNumFlashBlocks * usFlashBlockSize.
+    //
+    unsigned short usNumFlashBlocks;
+
+    //
+    //! Information on the part number, family, version and package as
+    //! read from SYSCTL register DID1.
+    //
+    unsigned long ulPartInfo;
+
+    //
+    //! Information on the part class and revision as read from SYSCTL DID0.
+    //
+    unsigned long ulClassInfo;
+
+    //
+    //! Address 1 byte above the highest location the boot loader can access.
+    //
+    unsigned long ulFlashTop;
+
+    //
+    //! Lowest address the boot loader can write or erase.
+    //
+    unsigned long ulAppStartAddr;
+}
+PACKED tDFUDeviceInfo;
+
+#ifndef DEPRECATED
+//*****************************************************************************
+//
+// Various deprecated definitions.  These are included to ensure backwards
+// compatibility.
+//
+//*****************************************************************************
+#define USBD_DFU_REQUEST_LUMINARY USBD_DFU_REQUEST_STELLARIS
+#define REQUEST_LUMINARY_VALUE REQUEST_STELLARIS_VALUE
+#define tDFUQueryLuminaryProtocol uDFUQueryStellarisProtocol
+#endif
+
+#ifdef ewarm
+#pragma pack()
+#endif
+
+#endif // __USBDFU_H__
diff --git a/src/platform/lm3s/usblib/usbhid.h b/src/platform/lm3s/usblib/usbhid.h
new file mode 100755
index 00000000..c598c57b
--- /dev/null
+++ b/src/platform/lm3s/usblib/usbhid.h
@@ -0,0 +1,654 @@
+//*****************************************************************************
+//
+// usbhid.h - Definitions used by HID class devices and hosts.
+//
+// Copyright (c) 2008-2011 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 7611 of the Stellaris USB Library.
+//
+//*****************************************************************************
+
+#ifndef __USBHID_H__
+#define __USBHID_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+//! \addtogroup hid_device_class_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// HID Interface descriptor Subclasses.
+//
+//*****************************************************************************
+#define USB_HID_SCLASS_NONE     0x00
+#define USB_HID_SCLASS_BOOT     0x01
+
+//*****************************************************************************
+//
+// USB Interface descriptor HID protocols.
+//
+//*****************************************************************************
+#define USB_HID_PROTOCOL_NONE   0
+#define USB_HID_PROTOCOL_KEYB   1
+#define USB_HID_PROTOCOL_MOUSE  2
+
+//*****************************************************************************
+//
+// HID Class descriptor types.
+//
+//*****************************************************************************
+#define USB_HID_DTYPE_HID       0x21
+#define USB_HID_DTYPE_REPORT    0x22
+#define USB_HID_DTYPE_PHYSICAL  0x23
+
+//*****************************************************************************
+//
+// HID USB requests.
+//
+//*****************************************************************************
+#define USBREQ_GET_REPORT       0x01
+#define USBREQ_GET_IDLE         0x02
+#define USBREQ_GET_PROTOCOL     0x03
+#define USBREQ_SET_REPORT       0x09
+#define USBREQ_SET_IDLE         0x0a
+#define USBREQ_SET_PROTOCOL     0x0b
+
+//*****************************************************************************
+//
+// GET_REPORT or SET_REPORT Definitions.
+//
+//*****************************************************************************
+#define USB_HID_REPORT_IN       0x01
+#define USB_HID_REPORT_OUTPUT   0x02
+#define USB_HID_REPORT_FEATURE  0x03
+
+//*****************************************************************************
+//
+// GET_PROTOCOL or SET_PROTOCOL Definitions.
+//
+//*****************************************************************************
+#define USB_HID_PROTOCOL_BOOT   0
+#define USB_HID_PROTOCOL_REPORT 1
+
+//*****************************************************************************
+//
+// Report Values used with the Report macros.
+//
+//*****************************************************************************
+#define USB_HID_GENERIC_DESKTOP 0x01
+#define USB_HID_BUTTONS         0x09
+#define USB_HID_X               0x30
+#define USB_HID_Y               0x31
+
+#define USB_HID_POINTER         0x01
+#define USB_HID_MOUSE           0x02
+#define USB_HID_KEYBOARD        0x06
+
+#define USB_HID_PHYSICAL        0x00
+#define USB_HID_APPLICATION     0x01
+
+#define USB_HID_USAGE_POINTER   0x0109
+#define USB_HID_USAGE_BUTTONS   0x0509
+#define USB_HID_USAGE_LEDS      0x0508
+#define USB_HID_USAGE_KEYCODES  0x0507
+
+//*****************************************************************************
+//
+// HID mouse button definitions as used in the first byte of the output report
+// used in the BIOS mouse protocol.
+//
+//*****************************************************************************
+#define HID_MOUSE_BUTTON_1      0x01
+#define HID_MOUSE_BUTTON_2      0x02
+#define HID_MOUSE_BUTTON_3      0x04
+
+//*****************************************************************************
+//
+// HID Keyboard LED definitions as used in the first byte of the output report
+// used in the BIOS keyboard protocol.
+//
+//*****************************************************************************
+#define HID_KEYB_NUM_LOCK       0x01
+#define HID_KEYB_CAPS_LOCK      0x02
+#define HID_KEYB_SCROLL_LOCK    0x04
+#define HID_KEYB_COMPOSE        0x08
+#define HID_KEYB_KANA           0x10
+
+//*****************************************************************************
+//
+// HID Keyboard key modifiers as provided in the first byte of the input report
+// used in the BIOS keyboard protocol.
+//
+//*****************************************************************************
+#define HID_KEYB_LEFT_CTRL      0x01
+#define HID_KEYB_LEFT_SHIFT     0x02
+#define HID_KEYB_LEFT_ALT       0x04
+#define HID_KEYB_LEFT_GUI       0x08
+#define HID_KEYB_RIGHT_CTRL     0x10
+#define HID_KEYB_RIGHT_SHIFT    0x20
+#define HID_KEYB_RIGHT_ALT      0x40
+#define HID_KEYB_RIGHT_GUI      0x80
+
+//*****************************************************************************
+//
+// A subset of the HID keyboard usage IDs.
+//
+//*****************************************************************************
+#define HID_KEYB_USAGE_RESERVED 0x00
+#define HID_KEYB_USAGE_ROLLOVER 0x01
+#define HID_KEYB_USAGE_A        0x04
+#define HID_KEYB_USAGE_B        0x05
+#define HID_KEYB_USAGE_C        0x06
+#define HID_KEYB_USAGE_D        0x07
+#define HID_KEYB_USAGE_E        0x08
+#define HID_KEYB_USAGE_F        0x09
+#define HID_KEYB_USAGE_G        0x0A
+#define HID_KEYB_USAGE_H        0x0B
+#define HID_KEYB_USAGE_I        0x0C
+#define HID_KEYB_USAGE_J        0x0D
+#define HID_KEYB_USAGE_K        0x0E
+#define HID_KEYB_USAGE_L        0x0F
+#define HID_KEYB_USAGE_M        0x10
+#define HID_KEYB_USAGE_N        0x11
+#define HID_KEYB_USAGE_O        0x12
+#define HID_KEYB_USAGE_P        0x13
+#define HID_KEYB_USAGE_Q        0x14
+#define HID_KEYB_USAGE_R        0x15
+#define HID_KEYB_USAGE_S        0x16
+#define HID_KEYB_USAGE_T        0x17
+#define HID_KEYB_USAGE_U        0x18
+#define HID_KEYB_USAGE_V        0x19
+#define HID_KEYB_USAGE_W        0x1A
+#define HID_KEYB_USAGE_X        0x1B
+#define HID_KEYB_USAGE_Y        0x1C
+#define HID_KEYB_USAGE_Z        0x1D
+#define HID_KEYB_USAGE_1        0x1E
+#define HID_KEYB_USAGE_2        0x1F
+#define HID_KEYB_USAGE_3        0x20
+#define HID_KEYB_USAGE_4        0x21
+#define HID_KEYB_USAGE_5        0x22
+#define HID_KEYB_USAGE_6        0x23
+#define HID_KEYB_USAGE_7        0x24
+#define HID_KEYB_USAGE_8        0x25
+#define HID_KEYB_USAGE_9        0x26
+#define HID_KEYB_USAGE_0        0x27
+#define HID_KEYB_USAGE_ENTER    0x28
+#define HID_KEYB_USAGE_ESCAPE   0x29
+#define HID_KEYB_USAGE_BACKSPACE \
+                                0x2A
+#define HID_KEYB_USAGE_TAB      0x2B
+#define HID_KEYB_USAGE_SPACE    0x2C
+#define HID_KEYB_USAGE_MINUS    0x2D
+#define HID_KEYB_USAGE_EQUAL    0x2E
+#define HID_KEYB_USAGE_LBRACKET 0x2F
+#define HID_KEYB_USAGE_RBRACKET 0x30
+#define HID_KEYB_USAGE_BSLASH   0x31
+#define HID_KEYB_USAGE_SEMICOLON \
+                                0x33
+#define HID_KEYB_USAGE_FQUOTE   0x34
+#define HID_KEYB_USAGE_BQUOTE   0x35
+#define HID_KEYB_USAGE_COMMA    0x36
+#define HID_KEYB_USAGE_PERIOD   0x37
+#define HID_KEYB_USAGE_FSLASH   0x38
+#define HID_KEYB_USAGE_CAPSLOCK 0x39
+#define HID_KEYB_USAGE_F1       0x3A
+#define HID_KEYB_USAGE_F2       0x3B
+#define HID_KEYB_USAGE_F3       0x3C
+#define HID_KEYB_USAGE_F4       0x3D
+#define HID_KEYB_USAGE_F5       0x3E
+#define HID_KEYB_USAGE_F6       0x3F
+#define HID_KEYB_USAGE_F7       0x40
+#define HID_KEYB_USAGE_F8       0x41
+#define HID_KEYB_USAGE_F9       0x42
+#define HID_KEYB_USAGE_F10      0x43
+#define HID_KEYB_USAGE_F11      0x44
+#define HID_KEYB_USAGE_F12      0x45
+#define HID_KEYB_USAGE_RIGHT_ARROW \
+                                0x4F
+#define HID_KEYB_USAGE_LEFT_ARROW \
+                                0x50
+#define HID_KEYB_USAGE_DOWN_ARROW \
+                                0x51
+#define HID_KEYB_USAGE_UP_ARROW 0x52
+#define HID_KEYB_USAGE_KEYPAD_SLASH \
+                                0x54
+#define HID_KEYB_USAGE_KEYPAD_STAR \
+                                0x55
+#define HID_KEYB_USAGE_KEYPAD_MINUS \
+                                0x56
+#define HID_KEYB_USAGE_KEYPAD_PLUS \
+                                0x57
+#define HID_KEYB_USAGE_KEPAD_ENTER \
+                                0x58
+#define HID_KEYB_USAGE_KEYPAD_1 0x59
+#define HID_KEYB_USAGE_KEYPAD_2 0x5A
+#define HID_KEYB_USAGE_KEYPAD_3 0x5B
+#define HID_KEYB_USAGE_KEYPAD_4 0x5C
+#define HID_KEYB_USAGE_KEYPAD_5 0x5D
+#define HID_KEYB_USAGE_KEYPAD_6 0x5E
+#define HID_KEYB_USAGE_KEYPAD_7 0x5F
+#define HID_KEYB_USAGE_KEYPAD_8 0x60
+#define HID_KEYB_USAGE_KEYPAD_9 0x61
+#define HID_KEYB_USAGE_KEYPAD_0 0x62
+#define HID_KEYB_USAGE_KEPAD_PERIOD \
+                                0x63
+
+//*****************************************************************************
+//
+// HID descriptor country codes (most of these are described as "countries" in
+// the HID specification even though they are really languages).
+//
+//*****************************************************************************
+#define USB_HID_COUNTRY_NONE    0x00
+#define USB_HID_COUNTRY_ARABIC  0x01
+#define USB_HID_COUNTRY_BELGIAN 0x02
+#define USB_HID_COUNTRY_CANADA_BI \
+                                0x03
+#define USB_HID_COUNTRY_CANADA_FR \
+                                0x04
+#define USB_HID_COUNTRY_CZECH_REPUBLIC \
+                                0x05
+#define USB_HID_COUNTRY_DANISH  0x06
+#define USB_HID_COUNTRY_FINNISH 0x07
+#define USB_HID_COUNTRY_FRENCH  0x08
+#define USB_HID_COUNTRY_GERMAN  0x09
+#define USB_HID_COUNTRY_GREEK   0x0A
+#define USB_HID_COUNTRY_HEBREW  0x0B
+#define USB_HID_COUNTRY_HUNGARY 0x0C
+#define USB_HID_COUNTRY_INTERNATIONAL_ISO \
+                                0x0D
+#define USB_HID_COUNTRY_ITALIAN 0x0E
+#define USB_HID_COUNTRY_JAPAN_KATAKANA \
+                                0x0F
+#define USB_HID_COUNTRY_KOREAN  0x10
+#define USB_HID_COUNTRY_LATIN_AMERICAN \
+                                0x11
+#define USB_HID_COUNTRY_NETHERLANDS \
+                                0x12
+#define USB_HID_COUNTRY_NORWEGIAN \
+                                0x13
+#define USB_HID_COUNTRY_PERSIAN 0x14
+#define USB_HID_COUNTRY_POLAND  0x15
+#define USB_HID_COUNTRY_PORTUGUESE \
+                                0x16
+#define USB_HID_COUNTRY_RUSSIA  0x17
+#define USB_HID_COUNTRY_SLOVAKIA \
+                                0x18
+#define USB_HID_COUNTRY_SPANISH 0x19
+#define USB_HID_COUNTRY_SWEDISH 0x1A
+#define USB_HID_COUNTRY_SWISS_FRENCH \
+                                0x1B
+#define USB_HID_COUNTRY_SWISS_GERMAN \
+                                0x1C
+#define USB_HID_COUNTRY_SWITZERLAND \
+                                0x1D
+#define USB_HID_COUNTRY_TAIWAN  0x1E
+#define USB_HID_COUNTRY_TURKISH_Q \
+                                0x1F
+#define USB_HID_COUNTRY_UK      0x20
+#define USB_HID_COUNTRY_US      0x21
+#define USB_HID_COUNTRY_YUGOSLAVIA \
+                                0x22
+#define USB_HID_COUNTRY_TURKISH_F \
+                                0x23
+
+//*****************************************************************************
+//
+// Data flags used in Input item tags within report descriptors.
+//
+//*****************************************************************************
+#define USB_HID_INPUT_DATA      0x0000
+#define USB_HID_INPUT_CONSTANT  0x0001
+#define USB_HID_INPUT_ARRAY     0x0000
+#define USB_HID_INPUT_VARIABLE  0x0002
+#define USB_HID_INPUT_ABS       0x0000
+#define USB_HID_INPUT_RELATIVE  0x0004
+#define USB_HID_INPUT_NOWRAP    0x0000
+#define USB_HID_INPUT_WRAP      0x0008
+#define USB_HID_INPUT_LINEAR    0x0000
+#define USB_HID_INPUT_NONLINEAR 0x0010
+#define USB_HID_INPUT_PREFER    0x0000
+#define USB_HID_INPUT_NONPREFER 0x0020
+#define USB_HID_INPUT_NONULL    0x0000
+#define USB_HID_INPUT_NULL      0x0040
+#define USB_HID_INPUT_BITF      0x0100
+#define USB_HID_INPUT_BYTES     0x0000
+
+//*****************************************************************************
+//
+// Data flags used in Feature item tags within report descriptors.
+//
+//*****************************************************************************
+#define USB_HID_FEATURE_DATA    0x0000
+#define USB_HID_FEATURE_CONSTANT \
+                                0x0001
+#define USB_HID_FEATURE_ARRAY   0x0000
+#define USB_HID_FEATURE_VARIABLE \
+                                0x0002
+#define USB_HID_FEATURE_ABS     0x0000
+#define USB_HID_FEATURE_RELATIVE \
+                                0x0004
+#define USB_HID_FEATURE_NOWRAP  0x0000
+#define USB_HID_FEATURE_WRAP    0x0008
+#define USB_HID_FEATURE_LINEAR  0x0000
+#define USB_HID_FEATURE_NONLINEAR \
+                                0x0010
+#define USB_HID_FEATURE_PREFER  0x0000
+#define USB_HID_FEATURE_NONPREFER \
+                                0x0020
+#define USB_HID_FEATURE_NONULL  0x0000
+#define USB_HID_FEATURE_NULL    0x0040
+#define USB_HID_FEATURE_BITF    0x0100
+#define USB_HID_FEATURE_BYTES   0x0000
+
+//*****************************************************************************
+//
+// Data flags used in Output item tags within report descriptors.
+//
+//*****************************************************************************
+#define USB_HID_OUTPUT_DATA     0x0000
+#define USB_HID_OUTPUT_CONSTANT 0x0001
+#define USB_HID_OUTPUT_ARRAY    0x0000
+#define USB_HID_OUTPUT_VARIABLE 0x0002
+#define USB_HID_OUTPUT_ABS      0x0000
+#define USB_HID_OUTPUT_RELATIVE 0x0004
+#define USB_HID_OUTPUT_NOWRAP   0x0000
+#define USB_HID_OUTPUT_WRAP     0x0008
+#define USB_HID_OUTPUT_LINEAR   0x0000
+#define USB_HID_OUTPUT_NONLINEAR \
+                                0x0010
+#define USB_HID_OUTPUT_PREFER   0x0000
+#define USB_HID_OUTPUT_NONPREFER \
+                                0x0020
+#define USB_HID_OUTPUT_NONULL   0x0000
+#define USB_HID_OUTPUT_NULL     0x0040
+#define USB_HID_OUTPUT_BITF     0x0100
+#define USB_HID_OUTPUT_BYTES    0x0000
+
+//*****************************************************************************
+//
+// Physical descriptor bias values.
+//
+//*****************************************************************************
+#define USB_HID_BIAS_NOT_APPLICABLE \
+                                0x00
+#define USB_HID_BIAS_RIGHT_HAND 0x01
+#define USB_HID_BIAS_LEFT_HAND  0x02
+#define USB_HID_BIAS_BOTH_HANDS 0x03
+#define USB_HID_BIAS_EITHER_HAND \
+                                0x04
+
+//*****************************************************************************
+//
+// Physical descriptor designator values.
+//
+//*****************************************************************************
+#define USB_HID_DESIGNATOR_NONE 0x00
+#define USB_HID_DESIGNATOR_HAND 0x01
+#define USB_HID_DESIGNATOR_EYEBALL \
+                                0x02
+#define USB_HID_DESIGNATOR_EYEBROW \
+                                0x03
+#define USB_HID_DESIGNATOR_EYELID \
+                                0x04
+#define USB_HID_DESIGNATOR_EAR  0x05
+#define USB_HID_DESIGNATOR_NOSE 0x06
+#define USB_HID_DESIGNATOR_MOUTH \
+                                0x07
+#define USB_HID_DESIGNATOR_UPPER_LIP \
+                                0x08
+#define USB_HID_DESIGNATOR_LOWER_LIP \
+                                0x09
+#define USB_HID_DESIGNATOR_JAW  0x0A
+#define USB_HID_DESIGNATOR_NECK 0x0B
+#define USB_HID_DESIGNATOR_UPPER_ARM \
+                                0x0C
+#define USB_HID_DESIGNATOR_ELBOW \
+                                0x0D
+#define USB_HID_DESIGNATOR_FOREARM \
+                                0x0E
+#define USB_HID_DESIGNATOR_WRIST \
+                                0x0F
+#define USB_HID_DESIGNATOR_PALM 0x10
+#define USB_HID_DESIGNATOR_THUMB \
+                                0x11
+#define USB_HID_DESIGNATOR_INDEX_FINGER \
+                                0x12
+#define USB_HID_DESIGNATOR_MIDDLE_FINGER \
+                                0x13
+#define USB_HID_DESIGNATOR_RING_FINGER \
+                                0x14
+#define USB_HID_DESIGNATOR_LITTLE_FINGER \
+                                0x15
+#define USB_HID_DESIGNATOR_HEAD 0x16
+#define USB_HID_DESIGNATOR_SHOULDER \
+                                0x17
+#define USB_HID_DESIGNATOR_HIP  0x18
+#define USB_HID_DESIGNATOR_WAIST \
+                                0x19
+#define USB_HID_DESIGNATOR_THIGH \
+                                0x1A
+#define USB_HID_DESIGNATOR_KNEE 0x1B
+#define USB_HID_DESIGNATOR_CALF 0x1C
+#define USB_HID_DESIGNATOR_ANKLE \
+                                0x1D
+#define USB_HID_DESIGNATOR_FOOT 0x1E
+#define USB_HID_DESIGNATOR_HEEL 0x1F
+#define USB_HID_DESIGNATOR_BALL_OF_FOOT \
+                                0x20
+#define USB_HID_DESIGNATOR_BIG_TOE \
+                                0x21
+#define USB_HID_DESIGNATOR_SECOND_TOE \
+                                0x22
+#define USB_HID_DESIGNATOR_THIRD_TOE \
+                                0x23
+#define USB_HID_DESIGNATOR_FOURTH_TOE \
+                                0x24
+#define USB_HID_DESIGNATOR_LITTLE_TOE \
+                                0x25
+#define USB_HID_DESIGNATOR_BROW 0x26
+#define USB_HID_DESIGNATOR_CHEEK \
+                                0x27
+
+//*****************************************************************************
+//
+// Physical descriptor qualifier values.
+//
+//*****************************************************************************
+#define USB_HID_QUALIFIER_NOT_APPLICABLE    \
+                                (0x00 << 5)
+#define USB_HID_QUALIFIER_RIGHT (0x01 << 5)
+#define USB_HID_QUALIFIER_LEFT  (0x02 << 5)
+#define USB_HID_QUALIFIER_BOTH  (0x03 << 5)
+#define USB_HID_QUALIFIER_EITHER \
+                                (0x04 << 5)
+#define USB_HID_QUALIFIER_CENTER \
+                                (0x05 << 5)
+
+//*****************************************************************************
+//
+// This is the maximum value for a usage code.
+//
+//*****************************************************************************
+#define USBH_HID_MAX_USAGE      256
+#define USBH_HID_CAPS_ARRAY_SZ  (USBH_HID_MAX_USAGE/sizeof(unsigned long))
+
+//*****************************************************************************
+//
+// All structures defined in this section of the header require byte packing of
+// fields.  This is usually a ccomplished using the PACKED macro but, for IAR
+// Embedded Workbench, this requires a pragma.
+//
+//*****************************************************************************
+#ifdef ewarm
+#pragma pack(1)
+#endif
+
+//*****************************************************************************
+//
+//! The class descriptor information structure is used to announce the presence
+//! of HID-specific class descriptors within the HID descriptor.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! The type of HID class descriptor.  This will be USB_HID_DTYPE_REPORT or
+    //! USB_HID_DTYPE_PHYSICAL.
+    //
+    unsigned char bDescriptorType;
+
+    //
+    //! The total length of the HID class descriptor.
+    //
+    unsigned short wDescriptorLength;
+}
+PACKED tHIDClassDescriptorInfo;
+
+//*****************************************************************************
+//
+//! The HID descriptor is inserted following the interface descriptor and
+//! before the endpoint descriptors for a HID class device.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! The length of this descriptor in bytes.
+    //
+    unsigned char bLength;
+
+    //
+    //! The type of the descriptor.  For a HID descriptor, this will be
+    //! USB_HID_DTYPE_HID (0x21).
+    //
+    unsigned char bDescriptorType;
+
+    //
+    //! A BCD value identifying the HID Class specification release supported
+    //! by the device.  For version 1.11, for example, this value would be
+    //! 0x0111.
+    //
+    unsigned short bcdHID;
+
+    //
+    //! The country code for which this hardware is localized or 0 if no
+    //! localization has been performed.  Valid country (or language) codes are
+    //! in labels of the form USB_HID_COUNTRY_xxx.
+    unsigned char bCountryCode;
+
+    //
+    //! The number of class-specific descriptors that exist for this device.
+    //! This indicates the number of class descriptor information structures
+    //! that are appended to this structure and must be at least 1 (since all
+    //! HID devices must publish at least 1 report descriptor).
+    //
+    unsigned char bNumDescriptors;
+
+    //
+    //! A table announcing each of the class-specific descriptors that this
+    //! device publishes.  The actual number of entries in the array is given
+    //! by the bNumDescriptors field.
+    //
+    tHIDClassDescriptorInfo sClassDescriptor[1];
+}
+PACKED tHIDDescriptor;
+
+//*****************************************************************************
+//
+// Return to default packing when using the IAR Embedded Workbench compiler.
+//
+//*****************************************************************************
+#ifdef ewarm
+#pragma pack()
+#endif
+
+//*****************************************************************************
+//
+//! This structure defines the mapping of USB usage identifiers to printable
+//! characters.  The structure has three members that hold this information.
+//! The ucBytesPerChar, indicates the number of bytes per character in
+//! the table.  The pulCapsLock array holds a packed bit array of usage
+//! identifiers that can be modified by the Caps Lock key.  The pCharMapping
+//! array is treated as a double indexed array with two "columns".  In the case
+//! of a single byte character it is treated as pairs of 8 bit values for
+//! unshifted and shifted values.  In the case of a double byte characters it is
+//! treated as pairs of 16 bit values.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! Number of bytes per character in the pCharMapping table of this
+    //! structure.
+    //
+    unsigned char ucBytesPerChar;
+
+    //
+    //! This is a packed bitmasked structure with a one bit flags that
+    //! indicates if the corresponding Usage ID is affected by the Caps Lock
+    //! key.
+    //
+    unsigned long pulCapsLock[USBH_HID_CAPS_ARRAY_SZ];
+
+    //
+    //! This is the indexed table of Usage ID to character value.  It must be
+    //! at least ucBytesPerChar * 2 * USBH_HID_MAX_USAGE bytes in size as it
+    //! is treated as a double indexed array.
+    //
+    void *pCharMapping;
+}
+tHIDKeyboardUsageTable;
+
+//*****************************************************************************
+//
+// The US Keyboard mapping used by USB keyboard usage ID to character mapping.
+//
+//*****************************************************************************
+extern const tHIDKeyboardUsageTable g_sUSKeyboardMap;
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __USBHID_H__
diff --git a/src/platform/lm3s/usblib/usbkeyboardmap.c b/src/platform/lm3s/usblib/usbkeyboardmap.c
new file mode 100755
index 00000000..418d992c
--- /dev/null
+++ b/src/platform/lm3s/usblib/usbkeyboardmap.c
@@ -0,0 +1,143 @@
+//*****************************************************************************
+//
+// usbkeyboardmap.c - This file holds the table to enable USB keyboard usage
+// identifiers to be mapped to printable characters.
+//
+// Copyright (c) 2008-2011 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 7611 of the Stellaris USB Library.
+//
+//*****************************************************************************
+
+#include "inc/hw_types.h"
+#include "usblib/usblib.h"
+#include "usblib/usbhid.h"
+
+//*****************************************************************************
+//
+// This is the array that hold the unshifted and shifted ASCII character for
+// each usage ID.
+//
+//*****************************************************************************
+const unsigned char g_pucKeyBoardMap[USBH_HID_MAX_USAGE][2] =
+{
+//
+//  Usage ID to character mapping                      Usage ID     CAPS Lock
+//
+    {0, 0},     {0, 0},     {0, 0},     {0, 0},     // 0 - 3        0
+    {'a', 'A'}, {'b', 'B'}, {'c', 'C'}, {'d', 'D'}, // 4 - 7        f
+    {'e', 'E'}, {'f', 'F'}, {'g', 'G'}, {'h', 'H'}, // 8 - 11       f
+    {'i', 'I'}, {'j', 'J'}, {'k', 'K'}, {'l', 'L'}, // 12 - 15      f
+    {'m', 'M'}, {'n', 'N'}, {'o', 'O'}, {'p', 'P'}, // 16 - 19      f
+    {'q', 'Q'}, {'r', 'R'}, {'s', 'S'}, {'t', 'T'}, // 20 - 23      f
+    {'u', 'U'}, {'v', 'V'}, {'w', 'W'}, {'x', 'X'}, // 24 - 27      f
+    {'y', 'Y'}, {'z', 'Z'}, {'1', '!'}, {'2', '@'}, // 28 - 31      3
+
+    {'3', '#'}, {'4', '$'}, {'5', '%'}, {'6', '^'}, // 32 - 35      0
+    {'7', '&'}, {'8', '*'}, {'9', '('}, {'0', ')'}, // 36 - 39      0
+    {'\n', '\n'}, {0, 0},   {0, 0},   {'\t', '\t'}, // 40 - 43      0
+    {' ', ' '}, {'-', '_'}, {'=', '+'}, {'[', '{'}, // 44 - 47      0
+    {']', '}'}, {'\\', '|'},{'`', '~'}, {';', ':'}, // 48 - 51      0
+    {'\'', '"'}, {'`', '~'}, {',', '<'}, {'.', '>'},// 52 - 55      0
+    {'/', '?'}, {0, 0},     {0, 0},     {0, 0},     // 56 - 59      0
+    {0, 0},     {0, 0},     {0, 0},     {0, 0},     // 60 - 63      0
+
+    {0, 0},     {0, 0},     {0, 0},     {0, 0},     // 64 - 67      0
+    {0, 0},     {0, 0},     {0, 0},     {0, 0},     // 68 - 71      0
+    {0, 0},     {0, 0},     {0, 0},     {0, 0},     // 72 - 75      0
+    {0, 0},     {0, 0},     {0, 0},     {0, 0},     // 76 - 79      0
+    {0, 0},     {0, 0},     {0, 0},     {0, 0},     // 80 - 83      0
+    {'/', '/'}, {'*', '*'}, {'-', '-'}, {'+', '+'}, // 84 - 87      0
+    {'\n', '\n'}, {'1', 0}, {'2', 0},   {'3', 0},   // 88 - 91      0
+    {'4', 0},   {'5', 0},   {'6', 0},   {'7', 0},   // 92 - 95      0
+
+    {'8', 0},   {'9', 0},   {'0', 0},   {'.', 0},   // 96 - 99      0
+    {'\\', '|'},{0, 0},     {0, 0},     {'=', '+'}, // 100 - 103    0
+    {0, 0},     {0, 0},     {0, 0},     {0, 0},     // 104 - 107    0
+    {0, 0},     {0, 0},     {0, 0},     {0, 0},     // 108 - 111    0
+    {0, 0},     {0, 0},     {0, 0},     {0, 0},     // 112 - 115    0
+    {0, 0},     {0, 0},     {0, 0},     {0, 0},     // 116 - 119    0
+    {0, 0},     {0, 0},     {0, 0},     {0, 0},     // 120 - 123    0
+    {0, 0},     {0, 0},     {0, 0},     {0, 0},     // 124 - 127    0
+    {0, 0},     {0, 0},     {0, 0},     {0, 0},     // 128 - 131    0
+
+    {0, 0},     {',', ','}, {'=', '='}, {0, 0},     // 132 - 135    0
+    {0, 0},     {0, 0},     {0, 0},     {0, 0},     // 136 - 139    0
+    {0, 0},     {0, 0},     {0, 0},     {0, 0},     // 140 - 143    0
+    {0, 0},     {0, 0},     {0, 0},     {0, 0},     // 144 - 147    0
+    {0, 0},     {0, 0},     {0, 0},     {0, 0},     // 148 - 151    0
+    {0, 0},     {0, 0},     {0, 0},     {0, 0},     // 152 - 155    0
+    {0, 0},     {0, 0},     {0, 0},     {0, 0},     // 156 - 159    0
+    {0, 0},     {0, 0},     {0, 0},     {0, 0},     // 160 - 163    0
+
+    {0, 0},     {0, 0},     {0, 0},     {0, 0},     // 164 - 167    0
+    {0, 0},     {0, 0},     {0, 0},     {0, 0},     // 168 - 171    0
+    {0, 0},     {0, 0},     {0, 0},     {0, 0},     // 172 - 175    0
+    {0, 0},     {0, 0},     {0, 0},     {0, 0},     // 174 - 179    0
+    {0, 0},     {0, 0},     {'(', '('}, {')', ')'}, // 180 - 183    0
+    {'{', '{'}, {'}', '}'}, {'\t', '\t'}, {0, 0},   // 184 - 187    0
+    {'A', 'A'}, {'B', 'B'}, {'C', 'C'}, {'D', 'D'}, // 188 - 191    0
+    {'E', 'E'}, {'F', 'F'}, {0, 0},     {'^', '^'}, // 192 - 195    0
+
+    {'%', '%'}, {'<', '<'}, {'>', '>'}, {'&', '&'}, // 196 - 199    0
+    {'&', '&'}, {'|', '|'}, {'|', '|'}, {':', ':'}, // 200 - 203    0
+    {'#', '#'}, {' ', ' '}, {'@', '@'}, {'!', '!'}, // 204 - 207    0
+    {0, 0},     {0, 0},     {0, 0},     {0, 0},     // 208 - 211    0
+    {0, 0},     {0, 0},     {0, 0},     {0, 0},     // 212 - 215    0
+    {0, 0},     {0, 0},     {0, 0},     {0, 0},     // 216 - 219    0
+    {0, 0},     {0, 0},     {0, 0},     {0, 0},     // 220 - 223    0
+
+    {0, 0},     {0, 0},     {0, 0},     {0, 0},     // 224 - 227    0
+    {0, 0},     {0, 0},     {0, 0},     {0, 0},     // 228 - 231    0
+    {0, 0},     {0, 0},     {0, 0},     {0, 0},     // 232 - 235    0
+    {0, 0},     {0, 0},     {0, 0},     {0, 0},     // 236 - 239    0
+    {0, 0},     {0, 0},     {0, 0},     {0, 0},     // 240 - 243    0
+    {0, 0},     {0, 0},     {0, 0},     {0, 0},     // 244 - 247    0
+    {0, 0},     {0, 0},     {0, 0},     {0, 0},     // 248 - 251    0
+    {0, 0},     {0, 0},     {0, 0},     {0, 0},     // 252 - 255    0
+};
+
+//*****************************************************************************
+//
+// This is the structure that defines the mapping of USB usage IDs to ASCII
+// values for printing.
+//
+//*****************************************************************************
+const tHIDKeyboardUsageTable g_sUSKeyboardMap =
+{
+    //
+    // One byte per character.
+    //
+    1,
+    //
+    // Packed bit array of usages codes that are effected by Caps Lock state.
+    //
+    {
+        0x3ffffff0,     // Alpha characters are only one affected by CAPS LOCK
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+    },
+    //
+    // The large table of the direct mapping of usage id's to ascii characters.
+    //
+    (void *)g_pucKeyBoardMap
+};
diff --git a/src/platform/lm3s/usblib/usblib.h b/src/platform/lm3s/usblib/usblib.h
new file mode 100755
index 00000000..61df6571
--- /dev/null
+++ b/src/platform/lm3s/usblib/usblib.h
@@ -0,0 +1,1836 @@
+//*****************************************************************************
+//
+// usblib.h - Main header file for the USB Library.
+//
+// Copyright (c) 2008-2011 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 7611 of the Stellaris USB Library.
+//
+//*****************************************************************************
+
+#ifndef __USBLIB_H__
+#define __USBLIB_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// This is the maximum number of endpoints supported by the usblib.
+//
+//*****************************************************************************
+#define USBLIB_NUM_EP           16   // Number of supported endpoints.
+
+//*****************************************************************************
+//
+// The following macro allows compiler-independent syntax to be used to
+// define packed structures.  A typical structure definition using these
+// macros will look similar to the following example:
+//
+//   #ifdef ewarm
+//   #pragma pack(1)
+//   #endif
+//
+//   typedef struct _PackedStructName
+//   {
+//      unsigned long ulFirstField;
+//      char cCharMember;
+//      unsigned short usShort;
+//   }
+//   PACKED tPackedStructName;
+//
+//   #ifdef ewarm
+//   #pragma pack()
+//   #endif
+//
+// The conditional blocks related to ewarm include the #pragma pack() lines
+// only if the IAR Embedded Workbench compiler is being used.  Unfortunately,
+// it is not possible to emit a #pragma from within a macro definition so this
+// must be done explicitly.
+//
+//*****************************************************************************
+#if defined(ccs) ||             \
+    defined(codered) ||         \
+    defined(gcc) ||             \
+    defined(rvmdk) ||           \
+    defined(__ARMCC_VERSION) || \
+    defined(sourcerygxx)
+#define PACKED __attribute__ ((packed))
+#elif defined(ewarm)
+#define PACKED
+#else
+#error Unrecognized COMPILER!
+#endif
+//*****************************************************************************
+//
+// Assorted language IDs from the document "USB_LANGIDs.pdf" provided by the
+// USB Implementers' Forum (Version 1.0).
+//
+//*****************************************************************************
+#define USB_LANG_CHINESE_PRC    0x0804      // Chinese (PRC)
+#define USB_LANG_CHINESE_TAIWAN 0x0404      // Chinese (Taiwan)
+#define USB_LANG_EN_US          0x0409      // English (United States)
+#define USB_LANG_EN_UK          0x0809      // English (United Kingdom)
+#define USB_LANG_EN_AUS         0x0C09      // English (Australia)
+#define USB_LANG_EN_CA          0x1009      // English (Canada)
+#define USB_LANG_EN_NZ          0x1409      // English (New Zealand)
+#define USB_LANG_FRENCH         0x040C      // French (Standard)
+#define USB_LANG_GERMAN         0x0407      // German (Standard)
+#define USB_LANG_HINDI          0x0439      // Hindi
+#define USB_LANG_ITALIAN        0x0410      // Italian (Standard)
+#define USB_LANG_JAPANESE       0x0411      // Japanese
+#define USB_LANG_KOREAN         0x0412      // Korean
+#define USB_LANG_ES_TRAD        0x040A      // Spanish (Traditional)
+#define USB_LANG_ES_MODERN      0x0C0A      // Spanish (Modern)
+#define USB_LANG_SWAHILI        0x0441      // Swahili (Kenya)
+#define USB_LANG_URDU_IN        0x0820      // Urdu (India)
+#define USB_LANG_URDU_PK        0x0420      // Urdu (Pakistan)
+
+//*****************************************************************************
+//
+//! \addtogroup usbchap9_src
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Note:
+//
+// Structure definitions which are derived directly from the USB specification
+// use field names from the specification.  Since a somewhat different version
+// of Hungarian prefix notation is used from the Stellaris standard, beware of
+// making assumptions about field sizes based on the field prefix when using
+// these structures.  Of particular note is the difference in the meaning of
+// the 'i' prefix.  In USB structures, this indicates a single byte index
+// whereas in Stellaris code, this is a 32 bit integer.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// All structures defined in this section of the header require byte packing of
+// fields.  This is usually accomplished using the PACKED macro but, for IAR
+// Embedded Workbench, this requires a pragma.
+//
+//*****************************************************************************
+#ifdef ewarm
+#pragma pack(1)
+#endif
+
+//*****************************************************************************
+//
+// Definitions related to standard USB device requests (sections 9.3 & 9.4)
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! The standard USB request header as defined in section 9.3 of the USB 2.0
+//! specification.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! Determines the type and direction of the request.
+    //
+    unsigned char bmRequestType;
+
+    //
+    //! Identifies the specific request being made.
+    //
+    unsigned char bRequest;
+
+    //
+    //! Word-sized field that varies according to the request.
+    //
+    unsigned short wValue;
+
+    //
+    //! Word-sized field that varies according to the request; typically used
+    //! to pass an index or offset.
+    //
+    unsigned short wIndex;
+
+    //
+    //! The number of bytes to transfer if there is a data stage to the
+    //! request.
+    //
+    unsigned short wLength;
+
+}
+PACKED tUSBRequest;
+
+//*****************************************************************************
+//
+// The following defines are used with the bmRequestType member of tUSBRequest.
+//
+// Request types have 3 bit fields:
+// 4:0 - Is the recipient type.
+// 6:5 - Is the request type.
+// 7 - Is the direction of the request.
+//
+//*****************************************************************************
+#define USB_RTYPE_DIR_IN        0x80
+#define USB_RTYPE_DIR_OUT       0x00
+
+#define USB_RTYPE_TYPE_M        0x60
+#define USB_RTYPE_VENDOR        0x40
+#define USB_RTYPE_CLASS         0x20
+#define USB_RTYPE_STANDARD      0x00
+
+#define USB_RTYPE_RECIPIENT_M   0x1f
+#define USB_RTYPE_OTHER         0x03
+#define USB_RTYPE_ENDPOINT      0x02
+#define USB_RTYPE_INTERFACE     0x01
+#define USB_RTYPE_DEVICE        0x00
+
+//*****************************************************************************
+//
+// Standard USB requests IDs used in the bRequest field of tUSBRequest.
+//
+//*****************************************************************************
+#define USBREQ_GET_STATUS       0x00
+#define USBREQ_CLEAR_FEATURE    0x01
+#define USBREQ_SET_FEATURE      0x03
+#define USBREQ_SET_ADDRESS      0x05
+#define USBREQ_GET_DESCRIPTOR   0x06
+#define USBREQ_SET_DESCRIPTOR   0x07
+#define USBREQ_GET_CONFIG       0x08
+#define USBREQ_SET_CONFIG       0x09
+#define USBREQ_GET_INTERFACE    0x0a
+#define USBREQ_SET_INTERFACE    0x0b
+#define USBREQ_SYNC_FRAME       0x0c
+
+//*****************************************************************************
+//
+// Data returned from a USBREQ_GET_STATUS request to a device.
+//
+//*****************************************************************************
+#define USB_STATUS_SELF_PWR     0x0001  // Currently self powered.
+#define USB_STATUS_BUS_PWR      0x0000  // Currently bus-powered.
+#define USB_STATUS_PWR_M        0x0001  // Mask for power mode.
+#define USB_STATUS_REMOTE_WAKE  0x0002  // Remote wake-up is currently enabled.
+
+//*****************************************************************************
+//
+// Feature Selectors (tUSBRequest.wValue) passed on USBREQ_CLEAR_FEATURE and
+// USBREQ_SET_FEATURE.
+//
+//*****************************************************************************
+#define USB_FEATURE_EP_HALT     0x0000  // Endpoint halt feature.
+#define USB_FEATURE_REMOTE_WAKE 0x0001  // Remote wake feature, device only.
+#define USB_FEATURE_TEST_MODE   0x0002  // Test mode
+
+//*****************************************************************************
+//
+// Endpoint Selectors (tUSBRequest.wIndex) passed on USBREQ_CLEAR_FEATURE,
+// USBREQ_SET_FEATURE and USBREQ_GET_STATUS.
+//
+//*****************************************************************************
+#define USB_REQ_EP_NUM_M   0x007F
+#define USB_REQ_EP_DIR_M   0x0080
+#define USB_REQ_EP_DIR_IN  0x0080
+#define USB_REQ_EP_DIR_OUT 0x0000
+
+//*****************************************************************************
+//
+// Standard USB descriptor types.  These values are passed in the upper bytes
+// of tUSBRequest.wValue on USBREQ_GET_DESCRIPTOR and also appear in the
+// bDescriptorType field of standard USB descriptors.
+//
+//*****************************************************************************
+#define USB_DTYPE_DEVICE        1
+#define USB_DTYPE_CONFIGURATION 2
+#define USB_DTYPE_STRING        3
+#define USB_DTYPE_INTERFACE     4
+#define USB_DTYPE_ENDPOINT      5
+#define USB_DTYPE_DEVICE_QUAL   6
+#define USB_DTYPE_OSPEED_CONF   7
+#define USB_DTYPE_INTERFACE_PWR 8
+#define USB_DTYPE_OTG           9
+#define USB_DTYPE_INTERFACE_ASC 11
+#define USB_DTYPE_CS_INTERFACE  36
+
+//*****************************************************************************
+//
+// Definitions related to USB descriptors (sections 9.5 & 9.6)
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! This structure describes a generic descriptor header.  These fields are to
+//! be found at the beginning of all valid USB descriptors.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! The length of this descriptor (including this length byte) expressed
+    //! in bytes.
+    //
+    unsigned char bLength;
+
+    //
+    //! The type identifier of the descriptor whose information follows.  For
+    //! standard descriptors, this field could contain, for example,
+    //! USB_DTYPE_DEVICE to identify a device descriptor or USB_DTYPE_ENDPOINT
+    //! to identify an endpoint descriptor.
+    //
+    unsigned char bDescriptorType;
+}
+PACKED tDescriptorHeader;
+
+//*****************************************************************************
+//
+//! This structure describes the USB device descriptor as defined in USB
+//! 2.0 specification section 9.6.1.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! The length of this descriptor in bytes.  All device descriptors are
+    //! 18 bytes long.
+    //
+    unsigned char bLength;
+
+    //
+    //! The type of the descriptor.  For a device descriptor, this will be
+    //! USB_DTYPE_DEVICE (1).
+    //
+    unsigned char bDescriptorType;
+
+    //
+    //! The USB Specification Release Number in BCD format.  For USB 2.0, this
+    //! will be 0x0200.
+    //
+    unsigned short bcdUSB;
+
+    //
+    //! The device class code.
+    //
+    unsigned char bDeviceClass;
+
+    //
+    //! The device subclass code.  This value qualifies the value found in the
+    //! bDeviceClass field.
+    //
+    unsigned char bDeviceSubClass;
+
+    //
+    //! The device protocol code.  This value is qualified by the values of
+    //! bDeviceClass and bDeviceSubClass.
+    //
+    unsigned char bDeviceProtocol;
+
+    //
+    //! The maximum packet size for endpoint zero.  Valid values are 8, 16, 32
+    //! and 64.
+    //
+    unsigned char bMaxPacketSize0;
+
+    //
+    //! The device Vendor ID (VID) as assigned by the USB-IF.
+    //
+    unsigned short idVendor;
+
+    //
+    //! The device Product ID (PID) as assigned by the manufacturer.
+    //
+    unsigned short idProduct;
+
+    //
+    //! The device release number in BCD format.
+    //
+    unsigned short bcdDevice;
+
+    //
+    //! The index of a string descriptor describing the manufacturer.
+    //
+    unsigned char iManufacturer;
+
+    //
+    //! The index of a string descriptor describing the product.
+    //
+    unsigned char iProduct;
+
+    //
+    //! The index of a string descriptor describing the device's serial
+    //! number.
+    //
+    unsigned char iSerialNumber;
+
+    //
+    //! The number of possible configurations offered by the device.  This
+    //! field indicates the number of distinct configuration descriptors that
+    //! the device offers.
+    //
+    unsigned char bNumConfigurations;
+}
+PACKED tDeviceDescriptor;
+
+//*****************************************************************************
+//
+// USB Device Class codes used in the tDeviceDescriptor.bDeviceClass field.
+// Definitions for the bDeviceSubClass and bDeviceProtocol fields are device
+// specific and can be found in the appropriate device class header files.
+//
+//*****************************************************************************
+#define USB_CLASS_DEVICE        0x00
+#define USB_CLASS_AUDIO         0x01
+#define USB_CLASS_CDC           0x02
+#define USB_CLASS_HID           0x03
+#define USB_CLASS_PHYSICAL      0x05
+#define USB_CLASS_IMAGE         0x06
+#define USB_CLASS_PRINTER       0x07
+#define USB_CLASS_MASS_STORAGE  0x08
+#define USB_CLASS_HUB           0x09
+#define USB_CLASS_CDC_DATA      0x0a
+#define USB_CLASS_SMART_CARD    0x0b
+#define USB_CLASS_SECURITY      0x0d
+#define USB_CLASS_VIDEO         0x0e
+#define USB_CLASS_HEALTHCARE    0x0f
+#define USB_CLASS_DIAG_DEVICE   0xdc
+#define USB_CLASS_WIRELESS      0xe0
+#define USB_CLASS_MISC          0xef
+#define USB_CLASS_APP_SPECIFIC  0xfe
+#define USB_CLASS_VEND_SPECIFIC 0xff
+#define USB_CLASS_EVENTS        0xffffffff
+
+//*****************************************************************************
+//
+// Generic values for undefined subclass and protocol.
+//
+//*****************************************************************************
+#define USB_SUBCLASS_UNDEFINED  0x00
+#define USB_PROTOCOL_UNDEFINED  0x00
+
+//*****************************************************************************
+//
+// The following are the miscellaneous subclass values.
+//
+//*****************************************************************************
+#define USB_MISC_SUBCLASS_SYNC      0x01
+#define USB_MISC_SUBCLASS_COMMON    0x02
+
+//*****************************************************************************
+//
+// These following are miscellaneous protocol values.
+//
+//*****************************************************************************
+#define USB_MISC_PROTOCOL_IAD   0x01
+
+//*****************************************************************************
+//
+//! This structure describes the USB device qualifier descriptor as defined in
+//! the USB 2.0 specification, section 9.6.2.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! The length of this descriptor in bytes.  All device qualifier
+    //! descriptors are 10 bytes long.
+    //
+    unsigned char bLength;
+
+    //
+    //! The type of the descriptor.  For a device descriptor, this will be
+    //! USB_DTYPE_DEVICE_QUAL (6).
+    //
+    unsigned char bDescriptorType;
+
+    //
+    //! The USB Specification Release Number in BCD format.  For USB 2.0, this
+    //! will be 0x0200.
+    //
+    unsigned short bcdUSB;
+
+    //
+    //! The device class code.
+    //
+    unsigned char bDeviceClass;
+
+    //
+    //! The device subclass code.  This value qualifies the value found in the
+    //! bDeviceClass field.
+    //
+    unsigned char bDeviceSubClass;
+
+    //
+    //! The device protocol code.  This value is qualified by the values of
+    //! bDeviceClass and bDeviceSubClass.
+    //
+    unsigned char bDeviceProtocol;
+
+    //
+    //! The maximum packet size for endpoint zero when operating at a speed
+    //! other than high speed.
+    //
+    unsigned char bMaxPacketSize0;
+
+    //
+    //! The number of other-speed configurations supported.
+    //
+    unsigned char bNumConfigurations;
+
+    //
+    //! Reserved for future use.  Must be set to zero.
+    //
+    unsigned char bReserved;
+}
+PACKED tDeviceQualifierDescriptor;
+
+//*****************************************************************************
+//
+//! This structure describes the USB configuration descriptor as defined in
+//! USB 2.0 specification section 9.6.3.  This structure also applies to the
+//! USB other speed configuration descriptor defined in section 9.6.4.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! The length of this descriptor in bytes.  All configuration descriptors
+    //! are 9 bytes long.
+    //
+    unsigned char bLength;
+
+    //
+    //! The type of the descriptor.  For a configuration descriptor, this will
+    //! be USB_DTYPE_CONFIGURATION (2).
+    //
+    unsigned char bDescriptorType;
+
+    //
+    //! The total length of data returned for this configuration.  This
+    //! includes the combined length of all descriptors (configuration,
+    //! interface, endpoint and class- or vendor-specific) returned for this
+    //! configuration.
+    //
+    unsigned short wTotalLength;
+
+    //
+    //! The number of interface supported by this configuration.
+    //
+    unsigned char bNumInterfaces;
+
+    //
+    //! The value used as an argument to the SetConfiguration standard request
+    //! to select this configuration.
+    //
+    unsigned char bConfigurationValue;
+
+    //
+    //! The index of a string descriptor describing this configuration.
+    //
+    unsigned char iConfiguration;
+
+    //
+    //! Attributes of this configuration.
+    //
+    unsigned char bmAttributes;
+
+    //
+    //! The maximum power consumption of the USB device from the bus in this
+    //! configuration when the device is fully operational.  This is expressed
+    //! in units of 2mA so, for example, 100 represents 200mA.
+    //
+    unsigned char bMaxPower;
+}
+PACKED tConfigDescriptor;
+
+//*****************************************************************************
+//
+// Flags used in constructing the value assigned to the field
+// tConfigDescriptor.bmAttributes.  Note that bit 7 is reserved and must be set
+// to 1.
+//
+//*****************************************************************************
+#define USB_CONF_ATTR_PWR_M     0xC0
+
+#define USB_CONF_ATTR_SELF_PWR  0xC0
+#define USB_CONF_ATTR_BUS_PWR   0x80
+#define USB_CONF_ATTR_RWAKE     0xA0
+
+//*****************************************************************************
+//
+//! This structure describes the USB interface descriptor as defined in USB
+//! 2.0 specification section 9.6.5.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! The length of this descriptor in bytes.  All interface descriptors
+    //! are 9 bytes long.
+    //
+    unsigned char bLength;
+
+    //
+    //! The type of the descriptor.  For an interface descriptor, this will
+    //! be USB_DTYPE_INTERFACE (4).
+    //
+    unsigned char bDescriptorType;
+
+    //
+    //! The number of this interface.  This is a zero based index into the
+    //! array of concurrent interfaces supported by this configuration.
+    //
+    unsigned char bInterfaceNumber;
+
+    //
+    //! The value used to select this alternate setting for the interface
+    //! defined in bInterfaceNumber.
+    //
+    unsigned char bAlternateSetting;
+
+    //
+    //! The number of endpoints used by this interface (excluding endpoint
+    //! zero).
+    //
+    unsigned char bNumEndpoints;
+
+    //
+    //! The interface class code as assigned by the USB-IF.
+    //
+    unsigned char bInterfaceClass;
+
+    //
+    //! The interface subclass code as assigned by the USB-IF.
+    //
+    unsigned char bInterfaceSubClass;
+
+    //
+    //! The interface protocol code as assigned by the USB-IF.
+    //
+    unsigned char bInterfaceProtocol;
+
+    //
+    //! The index of a string descriptor describing this interface.
+    //
+    unsigned char iInterface;
+}
+PACKED tInterfaceDescriptor;
+
+//*****************************************************************************
+//
+//! This structure describes the USB endpoint descriptor as defined in USB
+//! 2.0 specification section 9.6.6.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! The length of this descriptor in bytes.  All endpoint descriptors
+    //! are 7 bytes long.
+    //
+    unsigned char bLength;
+
+    //
+    //! The type of the descriptor.  For an endpoint descriptor, this will
+    //! be USB_DTYPE_ENDPOINT (5).
+    //
+    unsigned char bDescriptorType;
+
+    //
+    //! The address of the endpoint.  This field contains the endpoint number
+    //! ORed with flag USB_EP_DESC_OUT or USB_EP_DESC_IN to indicate the
+    //! endpoint direction.
+    //
+    unsigned char bEndpointAddress;
+
+    //
+    //! The endpoint transfer type, USB_EP_ATTR_CONTROL, USB_EP_ATTR_ISOC,
+    //! USB_EP_ATTR_BULK or USB_EP_ATTR_INT and, if isochronous, additional
+    //! flags indicating usage type and synchronization method.
+    //
+    unsigned char bmAttributes;
+
+    //
+    //! The maximum packet size this endpoint is capable of sending or
+    //! receiving when this configuration is selected.  For high speed
+    //! isochronous or interrupt endpoints, bits 11 and 12 are used to
+    //! pass additional information.
+    //
+    unsigned short wMaxPacketSize;
+
+    //
+    //! The polling interval for data transfers expressed in frames or
+    //! micro frames depending upon the operating speed.
+    //
+    unsigned char bInterval;
+}
+PACKED tEndpointDescriptor;
+
+//*****************************************************************************
+//
+// Flags used in constructing the value assigned to the field
+// tEndpointDescriptor.bEndpointAddress.
+//
+//*****************************************************************************
+#define USB_EP_DESC_OUT                 0x00
+#define USB_EP_DESC_IN                  0x80
+#define USB_EP_DESC_NUM_M               0x0f
+
+//*****************************************************************************
+//
+// Mask used to extract the maximum packet size (in bytes) from the
+// wMaxPacketSize field of the endpoint descriptor.
+//
+//*****************************************************************************
+#define USB_EP_MAX_PACKET_COUNT_M       0x07FF
+
+//*****************************************************************************
+//
+// Endpoint attributes used in tEndpointDescriptor.bmAttributes.
+//
+//*****************************************************************************
+#define USB_EP_ATTR_CONTROL             0x00
+#define USB_EP_ATTR_ISOC                0x01
+#define USB_EP_ATTR_BULK                0x02
+#define USB_EP_ATTR_INT                 0x03
+#define USB_EP_ATTR_TYPE_M              0x03
+
+#define USB_EP_ATTR_ISOC_M              0x0c
+#define USB_EP_ATTR_ISOC_NOSYNC         0x00
+#define USB_EP_ATTR_ISOC_ASYNC          0x04
+#define USB_EP_ATTR_ISOC_ADAPT          0x08
+#define USB_EP_ATTR_ISOC_SYNC           0x0c
+#define USB_EP_ATTR_USAGE_M             0x30
+#define USB_EP_ATTR_USAGE_DATA          0x00
+#define USB_EP_ATTR_USAGE_FEEDBACK      0x10
+#define USB_EP_ATTR_USAGE_IMPFEEDBACK   0x20
+
+//*****************************************************************************
+//
+//! This structure describes the USB string descriptor for index 0 as defined
+//! in USB 2.0 specification section 9.6.7.  Note that the number of language
+//! IDs is variable and can be determined by examining bLength.  The number of
+//! language IDs present in the descriptor is given by ((bLength - 2) / 2).
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! The length of this descriptor in bytes.  This value will vary
+    //! depending upon the number of language codes provided in the descriptor.
+    //
+    unsigned char bLength;
+
+    //
+    //! The type of the descriptor.  For a string descriptor, this will be
+    //! USB_DTYPE_STRING (3).
+    //
+    unsigned char bDescriptorType;
+
+    //
+    //! The language code (LANGID) for the first supported language.  Note that
+    //! this descriptor may support multiple languages, in which case, the
+    //! number of elements in the wLANGID array will increase and bLength will
+    //! be updated accordingly.
+    //
+    unsigned short wLANGID[1];
+}
+PACKED tString0Descriptor;
+
+//*****************************************************************************
+//
+//! This structure describes the USB string descriptor for all string indexes
+//! other than 0 as defined in USB 2.0 specification section 9.6.7.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! The length of this descriptor in bytes.  This value will be 2 greater
+    //! than the number of bytes comprising the UNICODE string that the
+    //! descriptor contains.
+    //
+    unsigned char bLength;
+
+    //
+    //! The type of the descriptor.  For a string descriptor, this will be
+    //! USB_DTYPE_STRING (3).
+    //
+    unsigned char bDescriptorType;
+
+    //
+    //! The first byte of the UNICODE string.  This string is not NULL
+    //! terminated.  Its length (in bytes) can be computed by subtracting 2
+    //! from the value in the bLength field.
+    //
+    unsigned char bString;
+}
+PACKED tStringDescriptor;
+
+//*****************************************************************************
+//
+//! Write a 2 byte unsigned short value to a USB descriptor block.
+//!
+//! \param usValue is the two byte unsigned short that is to be written to
+//! the descriptor.
+//!
+//! This helper macro is used in descriptor definitions to write two-byte
+//! values.  Since the configuration descriptor contains all interface and
+//! endpoint descriptors in a contiguous block of memory, these descriptors are
+//! typically defined using an array of bytes rather than as packed structures.
+//!
+//! \return Not a function.
+//
+//*****************************************************************************
+#define USBShort(usValue)       (usValue & 0xff), (usValue >> 8)
+
+//*****************************************************************************
+//
+//! Write a 3 byte unsigned long value to a USB descriptor block.
+//!
+//! \param ulValue is the three byte unsigned value that is to be written to the
+//! descriptor.
+//!
+//! This helper macro is used in descriptor definitions to write three-byte
+//! values.  Since the configuration descriptor contains all interface and
+//! endpoint descriptors in a contiguous block of memory, these descriptors are
+//! typically defined using an array of bytes rather than as packed structures.
+//!
+//! \return Not a function.
+//
+//*****************************************************************************
+#define USB3Byte(ulValue)       (ulValue & 0xff),              \
+                                ((ulValue >> 8) & 0xff),       \
+                                ((ulValue >> 16) & 0xff)
+
+//*****************************************************************************
+//
+//! Write a 4 byte unsigned long value to a USB descriptor block.
+//!
+//! \param ulValue is the four byte unsigned long that is to be written to the
+//! descriptor.
+//!
+//! This helper macro is used in descriptor definitions to write four-byte
+//! values.  Since the configuration descriptor contains all interface and
+//! endpoint descriptors in a contiguous block of memory, these descriptors are
+//! typically defined using an array of bytes rather than as packed structures.
+//!
+//! \return Not a function.
+//
+//*****************************************************************************
+#define USBLong(ulValue)        (ulValue & 0xff),              \
+                                ((ulValue >> 8) & 0xff),       \
+                                ((ulValue >> 16) & 0xff),      \
+                                ((ulValue >> 24) & 0xff)
+
+//*****************************************************************************
+//
+//! Traverse to the next USB descriptor in a block.
+//!
+//! \param ptr points to the first byte of a descriptor in a block of
+//! USB descriptors.
+//!
+//! This macro aids in traversing lists of descriptors by returning a pointer
+//! to the next descriptor in the list given a pointer to the current one.
+//!
+//! \return Returns a pointer to the next descriptor in the block following
+//! \e ptr.
+//!
+//*****************************************************************************
+#define NEXT_USB_DESCRIPTOR(ptr)                         \
+        (tDescriptorHeader *)(((unsigned char *)(ptr)) + \
+                              *((unsigned char *)(ptr)))
+
+//*****************************************************************************
+//
+// Return to default packing when using the IAR Embedded Workbench compiler.
+//
+//*****************************************************************************
+#ifdef ewarm
+#pragma pack()
+#endif
+
+//*****************************************************************************
+//
+// Close the usbchap9_src Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup device_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Function prototype for any standard USB request.
+//
+//*****************************************************************************
+typedef void (* tStdRequest)(void *pvInstance, tUSBRequest *pUSBRequest);
+
+//*****************************************************************************
+//
+// Data callback for receiving data from an endpoint.
+//
+//*****************************************************************************
+typedef void (* tInfoCallback)(void *pvInstance, unsigned long ulInfo);
+
+//*****************************************************************************
+//
+// Callback made to indicate that an interface alternate setting change has
+// occurred.
+//
+//*****************************************************************************
+typedef void (* tInterfaceCallback)(void *pvInstance,
+                                    unsigned char ucInterfaceNum,
+                                    unsigned char ucAlternateSetting);
+
+//*****************************************************************************
+//
+// Generic interrupt handler callbacks.
+//
+//*****************************************************************************
+typedef void (* tUSBIntHandler)(void *pvInstance);
+
+//*****************************************************************************
+//
+// Interrupt handler callbacks that have status information.
+//
+//*****************************************************************************
+typedef void (* tUSBEPIntHandler)(void *pvInstance,
+                                  unsigned long ulStatus);
+
+//*****************************************************************************
+//
+// Generic handler callbacks that are used when the callers needs to call into
+// an instance of class.
+//
+//*****************************************************************************
+typedef void (* tUSBDeviceHandler)(void *pvInstance,
+                                   unsigned long ulRequest,
+                                   void *pvRequestData);
+
+//*****************************************************************************
+//
+//! USB event handler functions used during enumeration and operation of the
+//! device stack.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! This callback is made whenever the USB host requests a non-standard
+    //! descriptor from the device.
+    //
+    tStdRequest pfnGetDescriptor;
+
+    //
+    //! This callback is made whenever the USB host makes a non-standard
+    //! request.
+    //
+    tStdRequest pfnRequestHandler;
+
+    //
+    //! This callback is made in response to a SetInterface request from the
+    //! host.
+    //
+    tInterfaceCallback pfnInterfaceChange;
+
+    //
+    //! This callback is made in response to a SetConfiguration request from
+    //! the host.
+    //
+    tInfoCallback pfnConfigChange;
+
+    //
+    //! This callback is made when data has been received following to a call
+    //! to USBDCDRequestDataEP0.
+    //
+    tInfoCallback pfnDataReceived;
+
+    //
+    //! This callback is made when data has been transmitted following a call
+    //! to USBDCDSendDataEP0.
+    //
+    tInfoCallback pfnDataSent;
+
+    //
+    //! This callback is made when a USB reset is detected.
+    //
+    tUSBIntHandler pfnResetHandler;
+
+    //
+    //! This callback is made when the bus has been inactive long enough to
+    //! trigger a suspend condition.
+    //
+    tUSBIntHandler pfnSuspendHandler;
+
+    //
+    //! This is called when resume signaling is detected.
+    //
+    tUSBIntHandler pfnResumeHandler;
+
+    //
+    //! This callback is made when the device is disconnected from the USB bus.
+    //
+    tUSBIntHandler pfnDisconnectHandler;
+
+    //
+    //! This callback is made to inform the device of activity on all endpoints
+    //! other than endpoint zero.
+    //
+    tUSBEPIntHandler pfnEndpointHandler;
+
+    //
+    //! This generic handler is provided to allow requests based on
+    //! a given instance to be passed into a device.  This is commonly used
+    //! by a top level composite device that is using multiple instances of
+    //! a class.
+    //
+    tUSBDeviceHandler pfnDeviceHandler;
+}
+tCustomHandlers;
+
+//*****************************************************************************
+//
+//! This structure defines how a given endpoint's FIFO is configured in
+//! relation to the maximum packet size for the endpoint as specified in the
+//! endpoint descriptor.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! The multiplier to apply to an endpoint's maximum packet size when
+    //! configuring the FIFO for that endpoint.  For example, setting this
+    //! value to 2 will result in a 128 byte FIFO being configured if
+    //! bDoubleBuffer is false and the associated endpoint is set to use a 64
+    //! byte maximum packet size.
+    //
+    unsigned char cMultiplier;
+
+    //
+    //! This field indicates whether to configure an endpoint's FIFO to be
+    //! double- or single-buffered.  If true, a double-buffered FIFO is
+    //! created and the amount of required FIFO storage is multiplied by two.
+    //
+    tBoolean bDoubleBuffer;
+
+    //
+    //! This field defines endpoint mode flags which cannot be deduced from
+    //! the configuration descriptor, namely any in the set USB_EP_AUTO_xxx or
+    //! USB_EP_DMA_MODE_x.  USBDCDConfig adds these flags to the endpoint
+    //! mode and direction determined from the config descriptor before it
+    //! configures the endpoint using a call to USBDevEndpointConfigSet().
+    //
+    unsigned short usEPFlags;
+}
+tFIFOEntry;
+
+//*****************************************************************************
+//
+//! This structure defines endpoint and FIFO configuration information for
+//! all endpoints that the device wishes to use.  This information cannot be
+//! determined by examining the USB configuration descriptor and is
+//! provided to USBDCDConfig by the application to allow the USB controller
+//! endpoints to be correctly configured.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! An array containing one FIFO entry for each of the IN endpoints.
+    //! Note that endpoint 0 is configured and managed by the USB device stack
+    //! so is excluded from this array.  The index 0 entry of the array
+    //! corresponds to endpoint 1, index 1 to endpoint 2, etc.
+    //
+    tFIFOEntry sIn[USBLIB_NUM_EP - 1];
+
+    //
+    //! An array containing one FIFO entry for each of the OUT endpoints.
+    //! Note that endpoint 0 is configured and managed by the USB device stack
+    //! so is excluded from this array.  The index 0 entry of the array
+    //! corresponds to endpoint 1, index 1 to endpoint 2, etc.
+    //
+    tFIFOEntry sOut[USBLIB_NUM_EP - 1];
+}
+tFIFOConfig;
+
+//*****************************************************************************
+//
+//! This structure defines a contiguous block of data which contains a group
+//! of descriptors that form part of a configuration descriptor for a device.
+//! It is assumed that a config section contains only whole descriptors.  It is
+//! not valid to split a single descriptor across multiple sections.
+//!
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! The number of bytes of descriptor data pointed to by pucData.
+    //
+    unsigned char ucSize;
+
+    //
+    //! A pointer to a block of data containing an integral number of
+    //! USB descriptors which form part of a larger configuration descriptor.
+    //
+    const unsigned char *pucData;
+}
+tConfigSection;
+
+//*****************************************************************************
+//
+//! This is the top level structure defining a USB device configuration
+//! descriptor.  A configuration descriptor contains a collection of device-
+//! specific descriptors in addition to the basic config, interface and
+//! endpoint descriptors.  To allow flexibility in constructing the
+//! configuration, the descriptor is described in terms of a list of data
+//! blocks.  The first block must contain the configuration descriptor itself
+//! and the following blocks are appended to this in order to produce the
+//! full descriptor sent to the host in response to a GetDescriptor request
+//! for the configuration descriptor.
+//!
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! The number of sections comprising the full descriptor for this
+    //! configuration.
+    //
+    unsigned char ucNumSections;
+
+    //
+    //! A pointer to an array of ucNumSections section pointers which must
+    //! be concatenated to form the configuration descriptor.
+    //
+    const tConfigSection * const *psSections;
+}
+tConfigHeader;
+
+//*****************************************************************************
+//
+//! This structure is passed to the USB library on a call to USBDCDInit and
+//! provides the library with information about the device that the
+//! application is implementing.  It contains functions pointers for the
+//! various USB event handlers and pointers to each of the standard device
+//! descriptors.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! A pointer to a structure containing pointers to event handler functions
+    //! provided by the client to support the operation of this device.
+    //
+    tCustomHandlers sCallbacks;
+
+    //
+    //! A pointer to the device descriptor for this device.
+    //
+    const unsigned char *pDeviceDescriptor;
+
+    //
+    //! A pointer to an array of configuration descriptor pointers.  Each entry
+    //! in the array corresponds to one configuration that the device may be set
+    //! to use by the USB host.  The number of entries in the array must
+    //! match the bNumConfigurations value in the device descriptor
+    //! array, pDeviceDescriptor.
+    //
+    const tConfigHeader * const *ppConfigDescriptors;
+
+    //
+    //! A pointer to the string descriptor array for this device.  This array
+    //! must be arranged as follows:
+    //!
+    //!   - [0]   - Standard descriptor containing supported language codes.
+    //!   - [1]   - String 1 for the first language listed in descriptor 0.
+    //!   - [2]   - String 2 for the first language listed in descriptor 0.
+    //!   - ...
+    //!   - [n]   - String n for the first language listed in descriptor 0.
+    //!   - [n+1] - String 1 for the second language listed in descriptor 0.
+    //!   - ...
+    //!   - [2n]  - String n for the second language listed in descriptor 0.
+    //!   - [2n+1]- String 1 for the third language listed in descriptor 0.
+    //!   - ...
+    //!   - [3n]  - String n for the third language listed in descriptor 0.
+    //!
+    //! and so on.
+    //
+    const unsigned char * const *ppStringDescriptors;
+
+    //
+    //! The total number of descriptors provided in the ppStringDescriptors
+    //! array.
+    //
+    unsigned long ulNumStringDescriptors;
+
+    //
+    //! A structure defining how the USB controller FIFO is to be partitioned
+    //! between the various endpoints.  This member can be set to point to
+    //! g_sUSBDefaultFIFOConfig if the default FIFO configuration is acceptable
+    //! This configuration sets each endpoint FIFO to be single buffered and
+    //! sized to hold the maximum packet size for the endpoint.
+    //
+    const tFIFOConfig *psFIFOConfig;
+
+    //
+    //! This value will be passed back to all call back functions so that
+    //! they have access to individual instance data based on the this pointer.
+    //
+    void *pvInstance;
+}
+tDeviceInfo;
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup general_usblib_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// USB descriptor parsing functions found in usbdesc.c
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! The USB_DESC_ANY label is used as a wild card in several of the descriptor
+//! parsing APIs to determine whether or not particular search criteria should
+//! be ignored.
+//
+//*****************************************************************************
+#define USB_DESC_ANY 0xFFFFFFFF
+
+extern unsigned long USBDescGetNum(tDescriptorHeader *psDesc,
+                                   unsigned long ulSize, unsigned long ulType);
+extern tDescriptorHeader *USBDescGet(tDescriptorHeader *psDesc,
+                                     unsigned long ulSize,
+                                     unsigned long ulType,
+                                     unsigned long ulIndex);
+extern unsigned long
+       USBDescGetNumAlternateInterfaces(tConfigDescriptor *psConfig,
+                                        unsigned char ucInterfaceNumber);
+extern tInterfaceDescriptor *USBDescGetInterface(tConfigDescriptor *psConfig,
+                                                 unsigned long ulIndex,
+                                                 unsigned long ulAltCfg);
+extern tEndpointDescriptor *
+       USBDescGetInterfaceEndpoint(tInterfaceDescriptor *psInterface,
+                                   unsigned long ulIndex,
+                                   unsigned long ulSize);
+
+//*****************************************************************************
+//
+//! The operating mode required by the USB library client.  This type is used
+//! by applications which wish to be able to switch between host and device
+//! modes by calling the USBStackModeSet() API.
+//
+//*****************************************************************************
+typedef enum
+{
+    //
+    //! The application wishes to operate as a USB device.
+    //
+    USB_MODE_DEVICE = 0,
+
+    //
+    //! The application wishes to operate as a USB host.
+    //
+    USB_MODE_HOST,
+
+    //
+    //! The application wishes to operate as both a host and device using
+    //! On-The-Go protocols to negotiate.
+    //
+    USB_MODE_OTG,
+
+    //
+    //! A marker indicating that no USB mode has yet been set by the
+    //! application.
+    //
+    USB_MODE_NONE
+} tUSBMode;
+
+//*****************************************************************************
+//
+// A pointer to a USB mode callback function.  This function is called by the
+// USB library to indicate to the application which operating mode it should
+// use, host or device.
+//
+//*****************************************************************************
+typedef void (*tUSBModeCallback)(unsigned long ulIndex, tUSBMode eMode);
+
+//*****************************************************************************
+//
+// Mode selection and dual mode interrupt steering functions.
+//
+//*****************************************************************************
+extern void USBStackModeSet(unsigned long ulIndex, tUSBMode eUSBMode,
+                            tUSBModeCallback pfnCallback);
+extern void USBDualModeInit(unsigned long ulIndex);
+extern void USBDualModeTerm(unsigned long ulIndex);
+extern void USBOTGMain(unsigned long ulMsTicks);
+extern void USBOTGPollRate(unsigned long ulIndex, unsigned long ulPollRate);
+extern void USBOTGModeInit(unsigned long ulIndex, unsigned long ulPollRate,
+                           void *pHostData, unsigned long ulHostDataSize);
+extern void USBOTGModeTerm(unsigned long ulIndex);
+extern void USB0OTGModeIntHandler(void);
+extern void USB0DualModeIntHandler(void);
+
+//*****************************************************************************
+//
+//! USB callback function.
+//!
+//! \param pvCBData is the callback pointer associated with the instance
+//!  generating the callback.  This is a value provided by the client during
+//! initialization of the instance making the callback.
+//! \param ulEvent is the identifier of the asynchronous event which is being
+//! notified to the client.
+//! \param ulMsgParam is an event-specific parameter.
+//! \param pvMsgData is an event-specific data pointer.
+//!
+//! A function pointer provided to the USB layer by the application
+//! which will be called to notify it of all asynchronous events relating to
+//! data transmission or reception.  This callback is used by device class
+//! drivers and host pipe functions.
+//!
+//! \return Returns an event-dependent value.
+//
+//*****************************************************************************
+typedef unsigned long (* tUSBCallback)(void *pvCBData, unsigned long ulEvent,
+                                       unsigned long ulMsgParam,
+                                       void *pvMsgData);
+
+//*****************************************************************************
+//
+// Base identifiers for groups of USB events.  These are used by both the
+// device class drivers and host layer.
+//
+// USB_CLASS_EVENT_BASE is the lowest identifier that should be used for
+// a class-specific event.  Individual event bases are defined for each
+// of the supported device class drivers.  Events with IDs between
+// USB_EVENT_BASE and USB_CLASS_EVENT_BASE are reserved for stack use.
+//
+//*****************************************************************************
+#define USB_EVENT_BASE          0x0000
+#define USB_CLASS_EVENT_BASE    0x8000
+
+//*****************************************************************************
+//
+// Event base identifiers for the various device classes supported in host
+// and device modes.
+// The first 0x800 values of a range are reserved for the device specific
+// messages and the second 0x800 values of a range are used for the host
+// specific messages for a given class.
+//
+//*****************************************************************************
+#define USBD_CDC_EVENT_BASE      (USB_CLASS_EVENT_BASE + 0)
+#define USBD_HID_EVENT_BASE      (USB_CLASS_EVENT_BASE + 0x1000)
+#define USBD_HID_KEYB_EVENT_BASE (USBD_HID_EVENT_BASE + 0x100)
+#define USBD_BULK_EVENT_BASE     (USB_CLASS_EVENT_BASE + 0x2000)
+#define USBD_MSC_EVENT_BASE      (USB_CLASS_EVENT_BASE + 0x3000)
+#define USBD_AUDIO_EVENT_BASE    (USB_CLASS_EVENT_BASE + 0x4000)
+#define USBD_DFU_EVENT_BASE      (USB_CLASS_EVENT_BASE + 0x5000)
+
+#define USBH_CDC_EVENT_BASE   (USBD_CDC_EVENT_BASE  + 0x800)
+#define USBH_HID_EVENT_BASE   (USBD_HID_EVENT_BASE  + 0x800)
+#define USBH_BULK_EVENT_BASE  (USBD_BULK_EVENT_BASE + 0x800)
+#define USBH_MSC_EVENT_BASE   (USBD_MSC_EVENT_BASE  + 0x800)
+#define USBH_AUDIO_EVENT_BASE (USBD_AUDIO_EVENT_BASE  + 0x800)
+
+//*****************************************************************************
+//
+// General events supported by device classes and host pipes.
+//
+//*****************************************************************************
+
+//
+//! The device is now attached to a USB host and ready to begin sending
+//! and receiving data (used by device classes only).
+//
+#define USB_EVENT_CONNECTED (USB_EVENT_BASE + 0)
+
+//
+//! The device has been disconnected from the USB host (used by device classes
+//! only).
+//!
+//! \note In device mode, the USB_EVENT_DISCONNECTED will not be reported if the
+//! MCU's PB1/USB0VBUS pin is connected to a fixed +5 Volts rather than
+//! directly to the VBUS pin on the USB connector.
+//
+#define USB_EVENT_DISCONNECTED (USB_EVENT_BASE + 1)
+
+//
+//! Data has been received and is in the buffer provided.
+//
+#define USB_EVENT_RX_AVAILABLE (USB_EVENT_BASE + 2)
+
+//
+//! This event is sent by a lower layer to inquire about the amount of
+//! unprocessed data buffered in the layers above.  It is used in cases
+//! where a low level driver needs to ensure that all preceding data has
+//! been processed prior to performing some action or making some notification.
+//! Clients receiving this event should return the number of bytes of data
+//! that are unprocessed or 0 if no outstanding data remains.
+//
+#define USB_EVENT_DATA_REMAINING (USB_EVENT_BASE + 3)
+
+//
+//! This event is sent by a lower layer supporting DMA to request a buffer in
+//! which the next received packet may be stored.  The \e ulMsgValue parameter
+//! indicates the maximum size of packet that can be received in this channel
+//! and \e pvMsgData points to storage which should be written with the
+//! returned buffer pointer.  The return value from the callback should be the
+//! size of the buffer allocated (which may be less than the maximum size
+//! passed in \e ulMsgValue if the client knows that fewer bytes are expected
+//! to be received) or 0 if no buffer is being returned.
+//
+#define USB_EVENT_REQUEST_BUFFER (USB_EVENT_BASE + 4)
+
+//
+//! Data has been sent and acknowledged.  If this event is received via the
+//! USB buffer callback, the \e ulMsgValue parameter indicates the number of
+//! bytes from the transmit buffer that have been successfully transmitted
+//! and acknowledged.
+//
+#define USB_EVENT_TX_COMPLETE (USB_EVENT_BASE + 5)
+
+//
+//! An error has been reported on the channel or pipe.  The \e ulMsgValue
+//! parameter indicates the source(s) of the error and is the logical OR
+//! combination of "USBERR_" flags defined below.
+//
+#define USB_EVENT_ERROR (USB_EVENT_BASE + 6)
+
+//
+//! The bus has entered suspend state.
+//
+#define USB_EVENT_SUSPEND (USB_EVENT_BASE + 7)
+
+//
+//! The bus has left suspend state.
+//
+#define USB_EVENT_RESUME (USB_EVENT_BASE + 8)
+
+//
+//! A scheduler event has occurred.
+//
+#define USB_EVENT_SCHEDULER     (USB_EVENT_BASE + 9)
+//
+//! A device or host has detected a stall condition.
+//
+#define USB_EVENT_STALL         (USB_EVENT_BASE + 10)
+
+//
+//! The host detected a power fault condition.
+//
+#define USB_EVENT_POWER_FAULT   (USB_EVENT_BASE + 11)
+
+//
+//! The controller has detected a A-Side cable and needs power applied  This is
+//! only generated on OTG parts if automatic power control is disabled.
+//
+#define USB_EVENT_POWER_ENABLE  (USB_EVENT_BASE + 12)
+
+//
+//! The controller needs power removed,  This is only generated on OTG parts
+//! if automatic power control is disabled.
+//
+#define USB_EVENT_POWER_DISABLE (USB_EVENT_BASE + 13)
+
+//
+//! This define is used with a device class's pfnDeviceHandler handler function
+//! to indicate that the USB library has changed the interface number.  This
+//! event is typically due to the class being included in a composite device.
+//!
+//! The \e pvInstance is a pointer to an instance of the device being accessed.
+//!
+//! The \e ulRequest is USB_EVENT_COMP_IFACE_CHANGE.
+//!
+//! The \e pvRequestData is a pointer to a two byte array where the first value
+//! is the old interface number and the second is the new interface number.
+//
+#define USB_EVENT_COMP_IFACE_CHANGE (USB_EVENT_BASE + 14)
+
+//
+//! This define is used with a device class's pfnDeviceHandler handler function
+//! to indicate that the USB library has changed the endpoint number.  This
+//! event is typically due to the class being included in a composite device.
+//!
+//! The \e pvInstance is a pointer to an instance of the device being accessed.
+//!
+//! The \e ulRequest is USB_EVENT_COMP_EP_CHANGE.
+//!
+//! The \e pvRequestData is a pointer to a two byte array where the first value
+//! is the old endpoint number and the second is the new endpoint number.  The
+//! endpoint numbers should be exactly as USB specification defines them and
+//! bit 7 set indicates an IN endpoint and bit 7 clear indicates an OUT
+//! endpoint.
+//
+#define USB_EVENT_COMP_EP_CHANGE    (USB_EVENT_BASE + 15)
+
+//
+//! This define is used with a device class's pfnDeviceHandler handler function
+//! to indicate that the USB library has changed the string index number for a
+//! string.  This event is typically due to the class being included in a
+//! composite device.
+//!
+//! The \e pvInstance is a pointer to an instance of the device being accessed.
+//!
+//! The \e ulRequest is USB_EVENT_COMP_STR_CHANGE.
+//!
+//! The \e pvRequestData is a pointer to a two byte array where the first value
+//! is the old string index and the second is the new string index.
+//
+#define USB_EVENT_COMP_STR_CHANGE    (USB_EVENT_BASE + 16)
+
+//
+//! This define is used with a device class's pfnDeviceHandler handler function
+//! to indicate that the USB library has changed the configuration descriptor.
+//! This allows the class to make final adjustments to the configuration
+//! descriptor.  This event is typically due to the class being included in a
+//! composite device.
+//!
+//! The \e pvInstance is a pointer to an instance of the device being accessed.
+//!
+//! The \e ulRequest is USB_EVENT_COMP_CONFIG.
+//!
+//! The \e pvRequestData is a pointer to the beginning of the configuration
+//! descriptor for the device instance.
+//
+#define USB_EVENT_COMP_CONFIG        (USB_EVENT_BASE + 17)
+
+//*****************************************************************************
+//
+// Error sources reported via USB_EVENT_ERROR.
+//
+//*****************************************************************************
+
+//
+//! The host received an invalid PID in a transaction.
+//
+#define USBERR_HOST_IN_PID_ERROR   0x01000000
+
+//
+//! The host did not receive a response from a device.
+//
+#define USBERR_HOST_IN_NOT_COMP    0x00100000
+
+//
+//! The host received a stall on an IN endpoint.
+//
+#define USBERR_HOST_IN_STALL       0x00400000
+
+//
+//! The host detected a CRC or bit-stuffing error (isochronous mode).
+//
+#define USBERR_HOST_IN_DATA_ERROR  0x00080000
+
+//
+//! The host received NAK on an IN endpoint for longer than the specified
+//! timeout period (interrupt, bulk and control modes).
+//
+#define USBERR_HOST_IN_NAK_TO      0x00080000
+
+//
+//! The host failed to communicate with a device via an IN endpoint.
+//
+#define USBERR_HOST_IN_ERROR       0x00040000
+
+//
+//! The host receive FIFO is full.
+//
+#define USBERR_HOST_IN_FIFO_FULL   0x00020000  // RX FIFO full
+//
+//! The host received NAK on an OUT endpoint for longer than the specified
+//! timeout period (bulk, interrupt and control modes).
+//
+#define USBERR_HOST_OUT_NAK_TO     0x00000080
+
+//
+//! The host did not receive a response from a device (isochronous mode).
+//
+#define USBERR_HOST_OUT_NOT_COMP   0x00000080
+
+//
+//! The host received a stall on an OUT endpoint.
+//
+#define USBERR_HOST_OUT_STALL      0x00000020
+
+//
+//! The host failed to communicate with a device via an OUT endpoint.
+//
+#define USBERR_HOST_OUT_ERROR      0x00000004
+
+//
+//! The host received NAK on endpoint 0 for longer than the configured
+//! timeout.
+//
+#define USBERR_HOST_EP0_NAK_TO     0x00000080
+
+//
+//! The host failed to communicate with a device via an endpoint zero.
+//
+#define USBERR_HOST_EP0_ERROR      0x00000010
+
+//
+//! The device detected a CRC error in received data.
+//
+#define USBERR_DEV_RX_DATA_ERROR   0x00080000
+
+//
+//! The device was unable to receive a packet from the host since the receive
+//! FIFO is full.
+//
+#define USBERR_DEV_RX_OVERRUN      0x00040000
+
+//
+//! The device receive FIFO is full.
+//
+#define USBERR_DEV_RX_FIFO_FULL    0x00020000  // RX FIFO full
+
+//*****************************************************************************
+//
+// Close the general_usblib_api Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup usblib_buffer_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! A function pointer type which describes either a class driver packet read
+//! or packet write function (both have the same prototype) to the USB
+//! buffer object.
+//
+//*****************************************************************************
+typedef unsigned long (* tUSBPacketTransfer)(void *pvHandle,
+                                             unsigned char *pcData,
+                                             unsigned long ulLength,
+                                             tBoolean bLast);
+
+//*****************************************************************************
+//
+//! A function pointer type which describes either a class driver transmit
+//! or receive packet available function (both have the same prototype) to the
+//! USB buffer object.
+//
+//*****************************************************************************
+typedef unsigned long (* tUSBPacketAvailable)(void *pvHandle);
+
+//*****************************************************************************
+//
+//! The number of bytes of workspace that each USB buffer object requires.
+//! This workspace memory is provided to the buffer on USBBufferInit() in
+//! the \e pvWorkspace field of the \e tUSBBuffer structure.
+//
+//*****************************************************************************
+#define USB_BUFFER_WORKSPACE_SIZE 16
+
+//*****************************************************************************
+//
+//! The structure used by the application to initialize a buffer object that
+//! will provide buffered access to either a transmit or receive channel.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! This field sets the mode of the buffer.  If true, the buffer
+    //! operates as a transmit buffer and supports calls to USBBufferWrite
+    //! by the client.  If false, the buffer operates as a receive buffer
+    //! and supports calls to USBBufferRead.
+    //
+    tBoolean bTransmitBuffer;
+
+    //
+    //! A pointer to the callback function which will be called to notify
+    //! the application of all asynchronous events related to the operation
+    //! of the buffer.
+    //
+    tUSBCallback pfnCallback;
+
+    //
+    //! A pointer that the buffer will pass back to the client in the
+    //! first parameter of all callbacks related to this instance.
+    //
+    void *pvCBData;
+
+    //
+    //! The function which should be called to transmit a packet of data
+    //! in transmit mode or receive a packet in receive mode.
+    //
+    tUSBPacketTransfer pfnTransfer;
+
+    //
+    //! The function which should be called to determine if the endpoint is
+    //! ready to accept a new packet for transmission in transmit mode or
+    //! to determine the size of the buffer required to read a packet in
+    //! receive mode.
+    //
+    tUSBPacketAvailable pfnAvailable;
+
+    //
+    //! The handle to pass to the low level function pointers
+    //! provided in the pfnTransfer and pfnAvailable members.  For USB device
+    //! use, this is the psDevice parameter required by the relevant device
+    //! class driver APIs.  For USB host use, this is the pipe identifier
+    //! returned by USBHCDPipeAlloc.
+    //
+    void *pvHandle;
+
+    //
+    //! A pointer to memory to be used as the ring buffer for this
+    //! instance.
+    //
+    unsigned char *pcBuffer;
+
+    //
+    //! The size, in bytes, of the buffer pointed to by pcBuffer.
+    //
+    unsigned long ulBufferSize;
+
+    //
+    //! A pointer to USB_BUFFER_WORKSPACE_SIZE bytes of RAM that the buffer
+    //! object can use for workspace.
+    //
+    void *pvWorkspace;
+}
+tUSBBuffer;
+
+//*****************************************************************************
+//
+//! The structure used for encapsulating all the items associated with a
+//! ring buffer.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! The ring buffer size.
+    //
+    unsigned long ulSize;
+
+    //
+    //! The ring buffer write index.
+    //
+    volatile unsigned long ulWriteIndex;
+
+    //
+    //! The ring buffer read index.
+    //
+    volatile unsigned long ulReadIndex;
+
+    //
+    //! The ring buffer.
+    //
+    unsigned char *pucBuf;
+}
+tUSBRingBufObject;
+
+//*****************************************************************************
+//
+// USB buffer API function prototypes.
+//
+//*****************************************************************************
+extern const tUSBBuffer *USBBufferInit(const tUSBBuffer *psBuffer);
+extern void USBBufferInfoGet(const tUSBBuffer *psBuffer,
+                             tUSBRingBufObject *psRingBuf);
+extern void *USBBufferCallbackDataSet(tUSBBuffer *psBuffer, void *pvCBData);
+extern unsigned long USBBufferWrite(const tUSBBuffer *psBuffer,
+                                    const unsigned char *pucData,
+                                    unsigned long ulLength);
+extern void USBBufferDataWritten(const tUSBBuffer *psBuffer,
+                                 unsigned long ulLength);
+extern void USBBufferDataRemoved(const tUSBBuffer *psBuffer,
+                                 unsigned long ulLength);
+extern void USBBufferFlush(const tUSBBuffer *psBuffer);
+extern unsigned long USBBufferRead(const tUSBBuffer *psBuffer,
+                                   unsigned char *pucData,
+                                   unsigned long ulLength);
+extern unsigned long USBBufferDataAvailable(const tUSBBuffer *psBuffer);
+extern unsigned long USBBufferSpaceAvailable(const tUSBBuffer *psBuffer);
+extern unsigned long USBBufferEventCallback(void *pvCBData,
+                                            unsigned long ulEvent,
+                                            unsigned long ulMsgValue,
+                                            void *pvMsgData);
+extern tBoolean USBRingBufFull(tUSBRingBufObject *ptUSBRingBuf);
+extern tBoolean USBRingBufEmpty(tUSBRingBufObject *ptUSBRingBuf);
+extern void USBRingBufFlush(tUSBRingBufObject *ptUSBRingBuf);
+extern unsigned long USBRingBufUsed(tUSBRingBufObject *ptUSBRingBuf);
+extern unsigned long USBRingBufFree(tUSBRingBufObject *ptUSBRingBuf);
+extern unsigned long USBRingBufContigUsed(tUSBRingBufObject *ptUSBRingBuf);
+extern unsigned long USBRingBufContigFree(tUSBRingBufObject *ptUSBRingBuf);
+extern unsigned long USBRingBufSize(tUSBRingBufObject *ptUSBRingBuf);
+extern unsigned char USBRingBufReadOne(tUSBRingBufObject *ptUSBRingBuf);
+extern void USBRingBufRead(tUSBRingBufObject *ptUSBRingBuf,
+                           unsigned char *pucData, unsigned long ulLength);
+extern void USBRingBufWriteOne(tUSBRingBufObject *ptUSBRingBuf,
+                               unsigned char ucData);
+extern void USBRingBufWrite(tUSBRingBufObject *ptUSBRingBuf,
+                            const unsigned char *pucData,
+                            unsigned long ulLength);
+extern void USBRingBufAdvanceWrite(tUSBRingBufObject *ptUSBRingBuf,
+                                   unsigned long ulNumBytes);
+extern void USBRingBufAdvanceRead(tUSBRingBufObject *ptUSBRingBuf,
+                                  unsigned long ulNumBytes);
+extern void USBRingBufInit(tUSBRingBufObject *ptUSBRingBuf,
+                           unsigned char *pucBuf, unsigned long ulSize);
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __USBLIB_H__
diff --git a/src/platform/lm3s/usblib/usblibpriv.h b/src/platform/lm3s/usblib/usblibpriv.h
new file mode 100755
index 00000000..44ea818e
--- /dev/null
+++ b/src/platform/lm3s/usblib/usblibpriv.h
@@ -0,0 +1,133 @@
+//*****************************************************************************
+//
+// usblibpriv.h - Private header file used to share internal variables and
+//                function prototypes between the various modules in the USB
+//                library.  This header MUST NOT be used by application code.
+//
+// Copyright (c) 2008-2011 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 7611 of the Stellaris USB Library.
+//
+//*****************************************************************************
+
+#ifndef __USBLIBPRIV_H__
+#define __USBLIBPRIV_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Internal interrupt handlers called from the main vectors in device and
+// host mode.
+//
+//*****************************************************************************
+extern void USBDeviceIntHandlerInternal(unsigned long ulIndex,
+                                        unsigned long ulStatus);
+extern void USBHostIntHandlerInternal(unsigned long ulIndex,
+                                      unsigned long ulStatus);
+
+//*****************************************************************************
+//
+// These defines are used to register the tick handlers used by the stack.
+// These handlers are internal to the stack and should never be called directly
+// by an application.
+//
+//*****************************************************************************
+#define USB_TICK_HANDLER_OTG        0   // OTG mode tick handler.
+#define USB_TICK_HANDLER_DEVICE     1   // Device mode tick handler.
+#define USB_TICK_HANDLER_HOST       2   // Host mode tick handler.
+#define USB_TICK_HANDLER_NUM        3   // Total number of tick handlers.
+
+//*****************************************************************************
+//
+// This value defines the number of SOF ticks that must pass before a call
+// is made to InternalUSBStartOfFrameTick.  The value 5 ensures that the
+// function is called every 5 milliseconds assuming that SOF interrupts are
+// enabled and SOF is present.
+//
+//*****************************************************************************
+#define USB_SOF_TICK_DIVIDE 5
+
+//*****************************************************************************
+//
+// Tick handler function pointer type.
+//
+//*****************************************************************************
+typedef void(* tUSBTickHandler)(void *pvInstance, unsigned long ulTicksmS);
+
+//*****************************************************************************
+//
+// Internal functions use to initialize the tick handler and register tick
+// callbacks.
+//
+//*****************************************************************************
+extern void InternalUSBTickInit(void);
+extern void InternalUSBRegisterTickHandler(unsigned long ulHandler,
+                                           tUSBTickHandler pfHandler,
+                                           void *pvInstance);
+extern void InternalUSBStartOfFrameTick(unsigned long ulTicksmS);
+extern void InternalUSBHCDSendEvent(unsigned long ulEvent);
+
+//*****************************************************************************
+//
+// g_ulCurrentUSBTick holds the elapsed time in milliseconds since the
+// tick module was first initialized based on calls to the function
+// InternalUSBStartOfFrameTick.  The granularity is USB_SOF_TICK_DIVIDE
+// milliseconds.
+//
+//*****************************************************************************
+extern unsigned long g_ulCurrentUSBTick;
+
+//*****************************************************************************
+//
+// g_ulUSBSOFCount is a global counter for Start of Frame interrupts.  It is
+// incremented by the low level device- or host-mode interrupt handlers.
+//
+//*****************************************************************************
+extern unsigned long g_ulUSBSOFCount;
+
+//*****************************************************************************
+//
+// InternalUSBGetTime is a macro which will return the system time in
+// milliseconds as calculated based on calls to the function
+// InternalUSBStartOfFrameTick.  The granularity is USB_SOF_TICK_DIVIDE
+// milliseconds.
+//
+// Currently, this merely returns the value of a global variable.
+//
+//*****************************************************************************
+#define InternalUSBGetTime() g_ulCurrentUSBTick
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __USBLIBPRIV_H__
diff --git a/src/platform/lm3s/usblib/usbmode.c b/src/platform/lm3s/usblib/usbmode.c
new file mode 100755
index 00000000..6526b1be
--- /dev/null
+++ b/src/platform/lm3s/usblib/usbmode.c
@@ -0,0 +1,1080 @@
+//*****************************************************************************
+//
+// usbmode.c - Functions related to dual mode USB device/host operation.
+//
+// Copyright (c) 2008-2011 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 7611 of the Stellaris USB Library.
+//
+//*****************************************************************************
+
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_types.h"
+#include "inc/hw_usb.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+#include "driverlib/rom.h"
+#include "driverlib/rom_map.h"
+#include "driverlib/sysctl.h"
+#include "driverlib/usb.h"
+#include "usblib/usblib.h"
+#include "usblib/device/usbdevice.h"
+#include "usblib/host/usbhost.h"
+#include "usblib/usblibpriv.h"
+
+//*****************************************************************************
+//
+//! \addtogroup general_usblib_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// The following label defines interrupts that we will always pass to the host
+// interrupt handler even if we are in dual mode and not yet sure of which
+// mode we are operating in.
+//
+//*****************************************************************************
+#define USB_HOST_INTS           (USB_INTCTRL_VBUS_ERR)
+
+//*****************************************************************************
+//
+// Global variable indicating which mode of operation the application has
+// requested.
+//
+//*****************************************************************************
+volatile tUSBMode g_eUSBMode = USB_MODE_NONE;
+
+//*****************************************************************************
+//
+// The default and the current polling rate for the USB OTG library.
+//
+//*****************************************************************************
+volatile unsigned long g_ulPollRate;
+
+//*****************************************************************************
+//
+// The current time remaining in milliseconds before checking the cable
+// connection.
+//
+//*****************************************************************************
+volatile unsigned long g_ulWaitTicks = 0;
+
+//*****************************************************************************
+//
+// This enum holds the various states that we can be in while performing
+// USB mode checking. This involves use of the OTG session request to poll
+// the USB ID pin to determine whether a device or a host is connected.
+//
+//*****************************************************************************
+typedef enum
+{
+    //
+    // No checking is currently pending.
+    //
+    USB_OTG_MODE_IDLE,
+
+    //
+    // Waiting on ID mode detection.
+    //
+    USB_OTG_MODE_WAITID,
+
+    //
+    // Waiting for next poll interval.
+    //
+    USB_OTG_MODE_WAIT,
+
+    //
+    // Now in B-side wait for connect.
+    //
+    USB_OTG_MODE_B_WAITCON,
+
+    //
+    // Now in A-side device mode.
+    //
+    USB_OTG_MODE_B_DEVICE,
+
+    //
+    // Now in A-side host mode.
+    //
+    USB_OTG_MODE_A_HOST,
+}
+tUSBOTGState;
+
+volatile tUSBOTGState g_eOTGModeState;
+
+//*****************************************************************************
+//
+// Global variable indicating whether we are currently operating in host or
+// device mode if the user has requested Dual mode operation.
+//
+//*****************************************************************************
+static volatile tUSBMode g_eDualMode = USB_MODE_NONE;
+
+static void USBOTGRemovePower(unsigned long ulIndex);
+
+//*****************************************************************************
+//
+// Global variable holding a pointer to the callback function which will be
+// called when the USB mode changes between device and host.
+//
+//*****************************************************************************
+static tUSBModeCallback g_pfnUSBModeCallback;
+
+//*****************************************************************************
+//
+// This function is used to handle switching between host, device and
+// unconfigured modes.
+//
+// /param eUSBMode is one of USB_MODE_HOST, USB_MODE_DEVICE, or USB_MODE_NONE.
+//
+// Based on the current state held in g_eDualMode variable this function will
+// handle the transistion of the mode of operation in OTG mode and calling
+// the callback function if it is present.
+//
+// /return None.
+//
+//*****************************************************************************
+static void
+USBOTGSetMode(tUSBMode eUSBMode)
+{
+    if((g_eDualMode != eUSBMode) || (g_eDualMode == USB_MODE_NONE))
+    {
+        //
+        // If going from host mode to unconfigured mode then remove power.
+        //
+        if((g_eDualMode == USB_MODE_HOST) && (eUSBMode == USB_MODE_NONE))
+        {
+            //
+            // Take the steps to remove power in the of host mode OTG.
+            //
+            USBOTGRemovePower(0);
+        }
+
+        //
+        // If going from device mode to unconfigured mode then end the current
+        // session.
+        //
+        if((g_eDualMode == USB_MODE_DEVICE) && (eUSBMode == USB_MODE_NONE))
+        {
+            //
+            // End the current session.
+            //
+            USBOTGSessionRequest(USB0_BASE, false);
+        }
+
+        //
+        // Reset the delay whenever returning ot USB_MODE_NONE.
+        //
+        if(eUSBMode == USB_MODE_NONE)
+        {
+            g_ulWaitTicks = g_ulPollRate;
+        }
+
+        //
+        // Do we have a mode change callback installed?
+        //
+        if((g_pfnUSBModeCallback) && (g_eDualMode != eUSBMode))
+        {
+            //
+            // Inform the callback of the new operating mode.
+            //
+            g_pfnUSBModeCallback(0, eUSBMode);
+        }
+
+        //
+        // Save the new mode.
+        //
+        g_eDualMode = eUSBMode;
+    }
+}
+
+//*****************************************************************************
+//
+//! Allows a dual-mode application to switch between USB device and host modes.
+//!
+//! \param ulIndex specifies the USB controller whose mode of operation is to
+//! be set.  This parameter must be set to 0.
+//! \param eUSBMode indicates the mode that the application wishes to operate
+//! in.  Valid values are \b USB_MODE_DEVICE to operate as a USB device and
+//! \b USB_MODE_HOST to operate as a USB host.
+//! \param pfnCallback is a pointer to a function which the USB library will
+//! call each time the mode is changed to indicate the new operating mode.  In
+//! cases where \e eUSBMode is set to either \b USB_MODE_DEVICE or
+//! \b USB_MODE_HOST, the callback will be made immediately to allow the
+//! application to perform any host or device specific initialization.
+//!
+//! This function allows a USB application, which can operate in host
+//! or device mode, to indicate to the USB stack the mode that it wishes to
+//! use.  The caller is responsible for cleaning up the interface and removing
+//! itself from the bus prior to making this call and reconfiguring afterwards.
+//!
+//! For successful dual mode mode operation, an application must register
+//! USB0DualModeIntHandler() as the interrupt handler for the USB0 interrupt.
+//! This handler is responsible for steering interrupts to the device or host
+//! stack depending upon the chosen mode.  Devices which do not require dual
+//! mode capability should register either \e USB0DeviceIntHandler() or
+//! \e USB0HostIntHandler() instead.  Registering \e USB0DualModeIntHandler()
+//! for a single mode application will result in an application binary larger
+//! than required since library functions for both USB operating modes will be
+//! included even though only one mode is required.
+//!
+//! Single mode applications (those offering exclusively USB device or USB
+//! host functionality) need not call this function since no interrupt
+//! steering is required if the appropriate single mode interrupt handler is
+//! installed.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBStackModeSet(unsigned long ulIndex, tUSBMode eUSBMode,
+                tUSBModeCallback pfnCallback)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulIndex == 0);
+    ASSERT(eUSBMode < USB_MODE_NONE)
+    ASSERT(pfnCallback);
+
+    //
+    // Remember the mode so that we can steer the interrupts appropriately.
+    //
+    g_eUSBMode = eUSBMode;
+
+    //
+    // Remember the callback pointer.
+    //
+    g_pfnUSBModeCallback = pfnCallback;
+
+    //
+    // If we are being asked to be either a host or device, we will not be
+    // trying to auto-detect the mode so make the callback immediately.
+    //
+    if((eUSBMode == USB_MODE_DEVICE) || (eUSBMode == USB_MODE_HOST))
+    {
+        g_pfnUSBModeCallback(0, eUSBMode);
+    }
+}
+
+//*****************************************************************************
+//
+//! Steers USB interrupts from controller to the correct handler in the USB
+//! stack.
+//!
+//! This interrupt handler is used in applications which require to operate
+//! in both host and device mode.  It steers the USB hardware interrupt to the
+//! correct handler in the USB stack depending upon the current operating mode
+//! of the application, USB device or host.
+//!
+//! For successful dual mode operation, an application must register
+//! USB0DualModeIntHandler() in the CPU vector table as the interrupt handler
+//! for the USB0 interrupt.  This handler is responsible for steering
+//! interrupts to the device or host stack depending upon the chosen mode.
+//!
+//! \note Devices which do not require dual mode capability should register
+//! either USB0DeviceIntHandler() or USB0HostIntHandler() instead.  Registering
+//! USB0DualModeIntHandler() for a single mode application will result in an
+//! application binary larger than required since library functions for both
+//! USB operating modes will be included even though only one mode is actually
+//! required.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USB0DualModeIntHandler(void)
+{
+    unsigned long ulStatus;
+
+    //
+    // Read the USB interrupt status.
+    //
+    ulStatus = USBIntStatusControl(USB0_BASE);
+
+    //
+    // Pass through the subset of interrupts that we always want
+    // the host stack to see regardless of whether or not we
+    // are actually in host mode at this point.
+    //
+    if(ulStatus & USB_HOST_INTS)
+    {
+        //
+        // Call the host's interrupt handler.
+        //
+        USBHostIntHandlerInternal(0, ulStatus & USB_HOST_INTS);
+
+        //
+        // We have already processed these interrupts so clear them
+        // from the status.
+        //
+        ulStatus &= ~USB_HOST_INTS;
+    }
+
+    //
+    // Steer the interrupt to the appropriate handler within the stack
+    // depending upon our current operating mode.  Note that we need to pass
+    // the ulStatus parameter since the USB interrupt register is
+    // clear-on-read.
+    //
+    switch(g_eUSBMode)
+    {
+        case USB_MODE_NONE:
+        {
+            //
+            // No mode is set yet so we have no idea what to do.  Just ignore
+            // the interrupt.
+            //
+            break;
+        }
+
+        //
+        // Operating in pure host mode.
+        //
+        case USB_MODE_HOST:
+        {
+            //
+            // Call the host interrupt handler if there is anything still to
+            // process.
+            //
+            USBHostIntHandlerInternal(0, ulStatus);
+
+            break;
+        }
+
+        //
+        // Operating in pure device mode.
+        //
+        case USB_MODE_DEVICE:
+        {
+            //
+            // Call the device interrupt handler.
+            //
+            USBDeviceIntHandlerInternal(0, ulStatus);
+
+            break;
+        }
+
+        default:
+        {
+        }
+    }
+}
+
+//*****************************************************************************
+//
+//! Initializes the USB controller for dual mode operation.
+//!
+//! \param ulIndex specifies the USB controller that is to be initialized for
+//! dual mode operation.  This parameter must be set to 0.
+//!
+//! This function initializes the USB controller hardware into a state
+//! suitable for dual mode operation.  Applications may use this function to
+//! ensure that the controller is in a neutral state and able to receive
+//! appropriate interrupts before host or device mode is chosen using a call
+//! to USBStackModeSet().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDualModeInit(unsigned long ulIndex)
+{
+    //
+    // We only support a single USB controller.
+    //
+    ASSERT(ulIndex == 0);
+
+    //
+    // Configure the End point 0.
+    //
+    USBHostEndpointConfig(USB0_BASE, USB_EP_0, 64, 0, 0,
+                          (USB_EP_MODE_CTRL | USB_EP_SPEED_FULL |
+                           USB_EP_HOST_OUT));
+
+    //
+    // Enable USB Interrupts.
+    //
+    MAP_USBIntEnableControl(USB0_BASE, USB_INTCTRL_RESET |
+                                       USB_INTCTRL_DISCONNECT |
+                                       USB_INTCTRL_SESSION |
+                                       USB_INTCTRL_BABBLE |
+                                       USB_INTCTRL_CONNECT |
+                                       USB_INTCTRL_RESUME |
+                                       USB_INTCTRL_SUSPEND |
+                                       USB_INTCTRL_VBUS_ERR);
+
+    //
+    // Enable all endpoint interrupts.
+    //
+    MAP_USBIntEnableEndpoint(USB0_BASE, USB_INTEP_ALL);
+
+    //
+    // Initialize the USB tick module.
+    //
+    InternalUSBTickInit();
+
+    //
+    // Enable the USB interrupt.
+    //
+    MAP_IntEnable(INT_USB0);
+
+    //
+    // Turn on session request to enable ID pin checking.
+    //
+    USBOTGSessionRequest(USB0_BASE, true);
+
+    //
+    // Initialize the power configuration.
+    //
+    USBHostPwrConfig(USB0_BASE, USBHCDPowerConfigGet(ulIndex));
+
+    //
+    // If power enable is automatic then then USBHostPwrEnable() has to be
+    // called to allow the USB controller to control the power enable pin.
+    //
+    if(USBHCDPowerAutomatic(ulIndex))
+    {
+        //
+        // This will not turn on power but instead will allow the USB
+        // controller to turn on power when needed.
+        //
+        USBHostPwrEnable(USB0_BASE);
+    }
+}
+
+//*****************************************************************************
+//
+//! Returns the USB controller to the default mode when in dual mode operation.
+//!
+//! \param ulIndex specifies the USB controller whose dual mode operation is to
+//! be ended.  This parameter must be set to 0.
+//!
+//! Applications using both host and device modes may call this function to
+//! disable interrupts in preparation for shutdown or a change of operating
+//! mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDualModeTerm(unsigned long ulIndex)
+{
+    //
+    // We only support a single USB controller.
+    //
+    ASSERT(ulIndex == 0);
+
+    //
+    // Disable the USB interrupt.
+    //
+    MAP_IntDisable(INT_USB0);
+
+    MAP_USBIntDisableControl(USB0_BASE, USB_INTCTRL_ALL);
+
+    MAP_USBIntDisableEndpoint(USB0_BASE, USB_INTEP_ALL);
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+//*****************************************************************************
+//
+//! \addtogroup usblib_otg
+//! @{
+//
+//*****************************************************************************
+
+
+//*****************************************************************************
+//
+//! Returns the USB controller to and inactive state when in OTG mode operation.
+//!
+//! \param ulIndex specifies the USB controller to end OTG mode operations.
+//!
+//! Applications using OTG mode may call this function to disable interrupts
+//! in preparation for shutdown or a change of operating mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBOTGModeTerm(unsigned long ulIndex)
+{
+    //
+    // We only support a single USB controller.
+    //
+    ASSERT(ulIndex == 0);
+
+    //
+    // Disable the USB interrupt.
+    //
+    MAP_IntDisable(INT_USB0);
+
+    //
+    // Disable all control interrupts.
+    //
+    MAP_USBIntDisableControl(USB0_BASE, USB_INTCTRL_ALL);
+
+    //
+    // Disable all endpoint interrupts.
+    //
+    MAP_USBIntDisableEndpoint(USB0_BASE, USB_INTEP_ALL);
+
+    //
+    // Set the mode to none if it is not already.
+    //
+    USBOTGSetMode(USB_MODE_NONE);
+}
+
+//*****************************************************************************
+//
+//! Initializes the USB controller for OTG mode operation.
+//!
+//! \param ulIndex specifies the USB controller that is to be initialized for
+//! OTG mode operation.
+//! \param ulPollingRate is the rate in milliseconds to poll the controller
+//! for changes in mode.
+//! \param pvPool is a pointer to the data to use as a memory pool for this
+//! controller.
+//! \param ulPoolSize is the size in bytes of the buffer passed in as pvPool.
+//!
+//! This function initializes the USB controller hardware into a state
+//! suitable for OTG mode operation.  Applications must use this function to
+//! ensure that the controller is in a neutral state and able to receive
+//! appropriate interrupts before host or device mode is chosen by OTG
+//! negotiation.  The \e ulPollingRate parameter is used to set the rate at
+//! which the USB library will poll the controller to determine the mode.  This
+//! has the most effect on how quickly the USB library will detect changes when
+//! going to host mode.  The parameters \e pvPool and \e ulPoolSize are passed
+//! on to the USB host library functions to provide memory for the USB library
+//! when it is acting as a  host. Any device and host initialization should have
+//! been called before calling this function to prevent the USB library from
+//! attempting to run in device or host mode before the USB library is
+//! fully configured.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBOTGModeInit(unsigned long ulIndex, unsigned long ulPollingRate,
+               void *pvPool, unsigned long ulPoolSize)
+{
+    //
+    // We only support a single USB controller.
+    //
+    ASSERT(ulIndex == 0);
+
+    //
+    // Remember that we have not yet determined whether we are device or
+    // host.
+    //
+    g_eUSBMode = USB_MODE_OTG;
+    g_eDualMode = USB_MODE_NONE;
+
+    //
+    // Set the default polling rate.
+    //
+    g_ulPollRate = ulPollingRate;
+
+    //
+    // Enable the USB controller.
+    //
+    MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_USB0);
+
+    //
+    // Turn on USB Phy clock.
+    //
+    MAP_SysCtlUSBPLLEnable();
+
+    //
+    // Initialize the host controller stack.
+    //
+    USBHCDInit(ulIndex, pvPool, ulPoolSize);
+
+    //
+    // Configure the End point 0.
+    //
+    USBHostEndpointConfig(USB0_BASE, USB_EP_0, 64, 0, 0,
+                          (USB_EP_MODE_CTRL | USB_EP_SPEED_FULL |
+                           USB_EP_HOST_OUT));
+
+    //
+    // Enable control interrupts.
+    //
+    MAP_USBIntEnableControl(USB0_BASE, USB_INTCTRL_RESET |
+                                       USB_INTCTRL_DISCONNECT |
+                                       USB_INTCTRL_SESSION |
+                                       USB_INTCTRL_BABBLE |
+                                       USB_INTCTRL_CONNECT |
+                                       USB_INTCTRL_RESUME |
+                                       USB_INTCTRL_SUSPEND |
+                                       USB_INTCTRL_VBUS_ERR |
+                                       USB_INTCTRL_MODE_DETECT |
+                                       USB_INTCTRL_SOF);
+
+    //
+    // Make sure the mode OTG mode and not forced device or host.
+    //
+    USBOTGMode(USB0_BASE);
+
+    //
+    // Enable all endpoint interrupts.
+    //
+    MAP_USBIntEnableEndpoint(USB0_BASE, USB_INTEP_ALL);
+
+    //
+    // Initialize the power configuration.
+    //
+    USBHCDPowerConfigSet(ulIndex, USBHCDPowerConfigGet(ulIndex));
+
+    //
+    // If power enable is automatic then then USBHostPwrEnable() has to be
+    // called to allow the USB controller to control the power enable pin.
+    //
+    if(USBHCDPowerAutomatic(ulIndex))
+    {
+        //
+        // This will not turn on power but instead will allow the USB
+        // controller to turn on power when needed.
+        //
+        USBHostPwrEnable(USB0_BASE);
+    }
+
+    //
+    // Enable the USB interrupt.
+    //
+    MAP_IntEnable(INT_USB0);
+}
+
+//*****************************************************************************
+//
+// This function handles the steps required to remove power in OTG mode.
+//
+// \param ulIndex specifies which USB controller should remove power.
+//
+// This function will perform the steps required to remove power from the USB
+// bus as required by the OTG specification.  This call will first issue a
+// bus suspend followed by clearing the current session and then removing power.
+//
+// /return None.
+//
+//*****************************************************************************
+static void
+USBOTGRemovePower(unsigned long ulIndex)
+{
+    //
+    // Do suspend signaling.
+    //
+    USBHostSuspend(USB0_BASE);
+
+    //
+    // End the session in either device or host mode.
+    //
+    USBOTGSessionRequest(USB0_BASE, false);
+
+    //
+    // Check if the controller is automatically applying power or not.
+    //
+    if(USBHCDPowerAutomatic(ulIndex) == 0)
+    {
+        //
+        // Call the registered event driver to allow it to disable power.
+        //
+        InternalUSBHCDSendEvent(USB_EVENT_POWER_DISABLE);
+    }
+}
+
+//*****************************************************************************
+//
+//! This call sets the USB OTG controllers poll rate when checking for the mode
+//! of the controller.
+//!
+//! \param ulIndex specifies which USB controller to set the polling rate.
+//! \param ulPollRate is the rate in milliseconds to poll for changes in the
+//! controller mode.
+//!
+//! This function is called to set the USB OTG libraries polling rate when
+//! checking the status of the cable.  The \e ulPollRate value used sets the
+//! rate in milliseconds that the USB OTG library will poll the cable to see
+//! if the controller should enter host mode.  This value has no effect on
+//! device detection rate as the controller will detect being connected to a
+//! host controller automatically.  The \e ulPollRate can be set to 0 to
+//! disable polling.  The USB OTG library can still function with the polling
+//! rate set to zero, however it will fail to detect host mode properly when no
+//! device is present at the end of the USB OTG B side of the cable.
+//!
+//! \note This function should only be called on devices that support OTG
+//! functionality.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBOTGPollRate(unsigned long ulIndex, unsigned long ulPollRate)
+{
+    //
+    // Save the timeout.
+    //
+    g_ulPollRate = ulPollRate;
+}
+
+//*****************************************************************************
+//
+//! Handles OTG mode changes and also steers other USB interrupts from
+//! the controller to the correct handler in the USB stack.
+//!
+//! This interrupt handler is used in applications which require to operate
+//! in both host and device mode using OTG.  When in host or device mode, it
+//! steers the USB hardware interrupt to the correct handler in the USB stack
+//! depending upon the current operating mode.  It also handles other OTG
+//! related interrupt events.
+//!
+//! For successful OTG mode operation, an application must register
+//! USB0OTGModeIntHandler() in the CPU vector table as the interrupt handler
+//! for the USB0 interrupt.
+//!
+//! \note This interrupt handler should only be used on controllers that support
+//! OTG functionality.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USB0OTGModeIntHandler(void)
+{
+    unsigned long ulStatus;
+
+    //
+    // Read the USB interrupt status.
+    //
+    ulStatus = USBIntStatusControl(USB0_BASE);
+
+    //
+    // Check if this was an mode detect interrupt and under manual power
+    // control.
+    //
+    if((ulStatus & USB_INTCTRL_MODE_DETECT) &&
+       (USBHCDPowerAutomatic(0) == 0))
+    {
+        unsigned long ulMode;
+
+        ulMode = USBModeGet(USB0_BASE);
+
+        switch(ulMode)
+        {
+            //
+            // Device is on the A side of the cable and power needs to be
+            // applied.
+            //
+            case USB_OTG_MODE_ASIDE_NPWR:
+            case USB_OTG_MODE_ASIDE_SESS:
+            case USB_OTG_MODE_ASIDE_AVAL:
+            {
+                //
+                // Since power is not automatically enabled, call the
+                // registered event handler to allow the application to turn
+                // on power.
+                //
+                InternalUSBHCDSendEvent(USB_EVENT_POWER_ENABLE);
+
+                break;
+            }
+
+            //
+            // Device is on the B side of the cable and powered.
+            //
+            case USB_OTG_MODE_BSIDE_DEV:
+            {
+                //
+                // Now in device mode on the B side of the cable and will wait
+                // for a connect before becoming a device.
+                //
+                g_eOTGModeState = USB_OTG_MODE_B_WAITCON;
+
+                break;
+            }
+
+            //
+            // Any other mode detect indicates USB_MODE_NONE.
+            //
+            default:
+            {
+                //
+                // Just inform the application that the mode was not device
+                // or host.
+                //
+                USBOTGSetMode(USB_MODE_NONE);
+
+                break;
+            }
+        }
+    }
+
+    //
+    // If there was a VBUS error then the power should be shut off and the system
+    // is reset to waiting for detection again.
+    //
+    if(ulStatus & USB_INTCTRL_VBUS_ERR)
+    {
+        //
+        // Just inform the application that the mode was not device
+        // or host.
+        //
+        USBOTGSetMode(USB_MODE_NONE);
+
+        //
+        // Return to idle mode.
+        //
+        g_eOTGModeState = USB_OTG_MODE_WAIT;
+    }
+
+    //
+    // If there is a disconnect interrupt and the controller was on the B side
+    // cable as a device then go back to the IDLE state.
+    //
+    if((ulStatus & USB_INTCTRL_DISCONNECT) &&
+       (g_eOTGModeState == USB_OTG_MODE_B_DEVICE))
+    {
+        //
+        // No longer a device so switch to unconfigured mode.
+        //
+        USBOTGSetMode(USB_MODE_NONE);
+
+        //
+        // Return to idle mode.
+        //
+        g_eOTGModeState = USB_OTG_MODE_WAIT;
+
+        return;
+    }
+
+    //
+    // Handle receiving a reset.
+    //
+    if((ulStatus & USB_INTCTRL_RESET)&&
+       (g_eOTGModeState != USB_OTG_MODE_B_DEVICE))
+    {
+        //
+        // Getting a reset interrupt when not already a b side device indicates
+        // that a host is resetting the device and the controller should
+        // move to device mode.
+        //
+        g_eOTGModeState = USB_OTG_MODE_B_DEVICE;
+
+        //
+        // Save the new mode.
+        //
+        USBOTGSetMode(USB_MODE_DEVICE);
+    }
+
+    //
+    // If there is a connect interrupt while the library is waiting for
+    // one then move to full host mode state.
+    //
+    if(ulStatus & USB_INTCTRL_CONNECT)
+    {
+        //
+        // Move to A side host state.
+        //
+        g_eOTGModeState = USB_OTG_MODE_A_HOST;
+
+        //
+        // Inform the application that controller is in host mode.
+        //
+        USBOTGSetMode(USB_MODE_HOST);
+    }
+
+    //
+    // Call the correct device or host interrupt handler based on the current
+    // mode of operation.
+    //
+    switch(g_eOTGModeState)
+    {
+        case USB_OTG_MODE_A_HOST:
+        {
+            //
+            // Call the host interrupt handler if there is anything still to
+            // process.
+            //
+            USBHostIntHandlerInternal(0, ulStatus);
+
+            break;
+        }
+
+        //
+        // Operating in pure device mode.
+        //
+        case USB_OTG_MODE_B_DEVICE:
+        {
+            //
+            // Call the device interrupt handler.
+            //
+            USBDeviceIntHandlerInternal(0, ulStatus);
+
+            break;
+        }
+        default:
+        {
+            break;
+        }
+    }
+}
+
+//*****************************************************************************
+//
+// This function is called by the USB host stack code to indicated that it
+// has compeleted handing the device disconnection.
+//
+// \param ulIndex specifies the USB controller that has completed disconnect.
+//
+// This internal library function is used when the hsot controller has completed
+// any deferred handling when it has detected a device has been disconnected.
+// The functions main purpose is to return the OTG controller to a state that
+// allows for resuming normal OTG cable detection and negotiation.
+//
+// \note This function should not be called outside the library.
+//
+//*****************************************************************************
+void
+OTGDeviceDisconnect(unsigned long ulIndex)
+{
+    //
+    // This function is only valid when called in host mode.
+    //
+    if(g_eOTGModeState == USB_OTG_MODE_A_HOST)
+    {
+        //
+        // No longer a host so switch to unconfigured mode.
+        //
+        USBOTGSetMode(USB_MODE_NONE);
+
+        g_eOTGModeState = USB_OTG_MODE_WAIT;
+    }
+}
+
+//*****************************************************************************
+//
+//! This function is the main routine for the OTG Controller Driver.
+//!
+//! \param ulMsTicks is the number of milliseconds that have passed since the
+//! last time this function was called.
+//!
+//! This function is the main routine for the USB controller when using the
+//! library in OTG mode.  This routine must be called periodically by the main
+//! application outside of a callback context.  The \e ulMsTicks value is used
+//! for basic timing needed by the USB library when operating in OTG mode.  This
+//! allows for a simple cooperative system to access the the OTG controller
+//! driver interface without the need for an RTOS.  All time critical operations
+//! are handled in interrupt context but all longer operations are run from
+//! the this function to allow them to block and wait for completion without
+//! holding off other interrupts.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBOTGMain(unsigned long ulMsTicks)
+{
+    if(ulMsTicks > g_ulWaitTicks)
+    {
+        g_ulWaitTicks = 0;
+    }
+    else
+    {
+        g_ulWaitTicks -= ulMsTicks;
+    }
+
+    switch(g_eOTGModeState)
+    {
+        case USB_OTG_MODE_IDLE:
+        {
+            g_eOTGModeState = USB_OTG_MODE_WAITID;
+
+            //
+            // Initiate a session request and check the ID pin.
+            //
+            USBOTGSessionRequest(USB0_BASE, true);
+            break;
+        }
+        case USB_OTG_MODE_WAIT:
+        case USB_OTG_MODE_WAITID:
+        {
+            //
+            // If reached the timeout and polling is enabled then look again.
+            //
+            if((g_ulWaitTicks == 0) && (g_ulPollRate != 0))
+            {
+                //
+                // Remove the session request.
+                //
+                USBOTGSessionRequest(USB0_BASE, false);
+
+                //
+                // Return to idle mode.
+                //
+                USBOTGSetMode(USB_MODE_NONE);
+
+                //
+                // Check if the controller is automatically applying power or
+                // not.
+                //
+                if(USBHCDPowerAutomatic(0) == 0)
+                {
+                    //
+                    // Call the registered event driver to allow it to disable
+                    // power.
+                    //
+                    InternalUSBHCDSendEvent(USB_EVENT_POWER_DISABLE);
+                }
+
+                //
+                // Go back to the idle state.
+                //
+                g_eOTGModeState = USB_OTG_MODE_IDLE;
+            }
+            break;
+        }
+        case USB_OTG_MODE_A_HOST:
+        {
+            //
+            // Call the host main routine when acting as a host.
+            //
+            USBHCDMain();
+            break;
+        }
+        case USB_OTG_MODE_B_WAITCON:
+        case USB_OTG_MODE_B_DEVICE:
+        default:
+        {
+            break;
+        }
+    }
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/src/platform/lm3s/usblib/usbmsc.h b/src/platform/lm3s/usblib/usbmsc.h
new file mode 100755
index 00000000..06d55d8a
--- /dev/null
+++ b/src/platform/lm3s/usblib/usbmsc.h
@@ -0,0 +1,393 @@
+//*****************************************************************************
+//
+// usbmsc.h - Generic types and defines use by the mass storage class.
+//
+// Copyright (c) 2008-2011 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 7611 of the Stellaris USB Library.
+//
+//*****************************************************************************
+
+#ifndef __USBMSC_H__
+#define __USBMSC_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// The request for the maximum number of logical units on a mass storage
+// device.
+//
+//*****************************************************************************
+#define USBREQ_GET_MAX_LUN      0xfe
+
+//*****************************************************************************
+//
+// The signatures defined by USB MSC class specification.
+//
+//*****************************************************************************
+#define CBW_SIGNATURE           0x43425355
+#define CSW_SIGNATURE           0x53425355
+
+//*****************************************************************************
+//
+// Flag for the bmCBWFlags member of tMSCCBW
+//
+//*****************************************************************************
+#define CBWFLAGS_DIR_M          0x80
+#define CBWFLAGS_DIR_IN         0x80
+#define CBWFLAGS_DIR_OUT        0x00
+
+//*****************************************************************************
+//
+// All structures defined in this section of the header require byte packing of
+// fields.  This is usually accomplished using the PACKED macro but, for IAR
+// Embedded Workbench, this requries a pragma.
+//
+//*****************************************************************************
+#ifdef ewarm
+#pragma pack(1)
+#endif
+
+//*****************************************************************************
+//
+// The following packed structure is used to access the Command Block Wrapper
+// (CBW) data structure that is used when communicating with USB Mass Storage
+// Class devices.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    // Signature that helps identify this data packet as a CBW.  The signature
+    // field shall contain the value 0x43425355 (little endian), indicating a
+    // CBW.
+    //
+    unsigned long dCBWSignature;
+
+    //
+    // The Command Block Tag sent by the host controller.  The device shall
+    // echo the contents of this field back to the host in the dCSWTag field
+    // of the associated CSW.  The dCSWTag positively associates a CSW with the
+    // corresponding CBW.
+    //
+    unsigned long dCBWTag;
+
+    //
+    // The number of bytes of data that the host expects to transfer on the
+    // Bulk-In or Bulk-Out endpoint (as indicated by the Direction bit) during
+    // the execution of this command.  If this field is zero, the device and
+    // the host will not transfer data between the CBW and the associated CSW,
+    // and the device will ignore the value of the Direction bit in
+    // bmCBWFlags.
+    //
+    unsigned long dCBWDataTransferLength;
+
+    //
+    // The device will ignore these bits if the dCBWDataTransferLength value
+    // is set to 0.
+    //
+    // The bits of this field are defined as follows:
+    // Bit 7 Direction
+    //   0 = Data-Out from host to the device,
+    //   1 = Data-In from the device to the host.
+    // Bit 6 Obsolete - The host shall set this bit to zero.
+    // Bits 5..0 Reserved - the host shall set these bits to zero.
+    //
+    unsigned char bmCBWFlags;
+
+    //
+    // The device Logical Unit Number (LUN) to which the command block is being
+    // sent.  For devices that support multiple LUNs, the host shall place into
+    // this field the LUN to which this command block is addressed.  Otherwise,
+    // the host shall set this field to zero.
+    //
+    unsigned char bCBWLUN;
+
+    //
+    // The valid length of the CBWCB in bytes.  This defines the valid length
+    // of the command block.  The only legal values are 1 through 16.  All
+    // other values are reserved.
+    //
+    unsigned char bCBWCBLength;
+
+    //
+    // This array holds the command block to be executed by the device.  The
+    // MSC device will interpret the first bCBWCBLength bytes in this field as
+    // a command block as defined by the command set identified by
+    // bInterfaceSubClass.  If the command set supported by the device uses
+    // command blocks of fewer than 16 bytes in length, the significant bytes
+    // shall be transferred first, beginning with the byte at offset 15.  The
+    // device will ignore the content of the CBWCB field past the byte at
+    // offset (15 + bCBWCBLength - 1).
+    //
+    unsigned char CBWCB[16];
+}
+PACKED tMSCCBW;
+
+//*****************************************************************************
+//
+// Flags for the bCSWStatus member of tMSCCSW
+//
+//*****************************************************************************
+#define CSWSTATUS_CMD_SUCCESS   0
+#define CSWSTATUS_CMD_FAILED    1
+#define CSWSTATUS_PHASE_ERROR   2
+
+//*****************************************************************************
+//
+// This structure encapsulates the Command Status Word (CSW) structure that is
+// sent in response to all CBW commands.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    // Signature that identifies this data packet as a CSW.  The signature
+    // field must contain the value 53425355h (little endian) to indicate CSW.
+    //
+    unsigned long dCSWSignature;
+
+    //
+    // The device will set this field to the value received in the dCBWTag of
+    // the associated CBW.
+    //
+    unsigned long dCSWTag;
+
+    //
+    // For OUT transactions the device will fill the dCSWDataResidue field with
+    // the difference between the amount of data expected as stated in the
+    // dCBWDataTransferLength, and the actual amount of data processed by the
+    // device.  For IN transactions the device will fill the dCSWDataResidue
+    // field with the difference between the amount of data expected as stated
+    // in the dCBWDataTransferLength and the actual amount of relevant data
+    // sent by the device.  The dCSWDataResidue will not exceed the value sent
+    // in the dCBWDataTransferLength.
+    //
+    unsigned long dCSWDataResidue;
+
+    //
+    // The bCSWStatus field indicates the success or failure of the command.
+    // The device shall set this byte to zero if the command completed
+    // successfully.  A non-zero value shall indicate a failure during command
+    // execution.
+    //
+    unsigned char bCSWStatus;
+}
+PACKED tMSCCSW;
+
+//*****************************************************************************
+//
+// Return to default packing when using the IAR Embedded Workbench compiler.
+//
+//*****************************************************************************
+#ifdef ewarm
+#pragma pack()
+#endif
+
+//*****************************************************************************
+//
+// SCSI Command return codes.
+//
+//*****************************************************************************
+#define SCSI_CMD_STATUS_PASS        0x00
+#define SCSI_CMD_STATUS_FAIL        0x01
+
+//*****************************************************************************
+//
+// SCSI commands.
+//
+//*****************************************************************************
+#define SCSI_TEST_UNIT_READY        0x00
+#define SCSI_REQUEST_SENSE          0x03
+#define SCSI_INQUIRY_CMD            0x12
+#define SCSI_MODE_SENSE_6           0x1a
+#define SCSI_READ_CAPACITIES        0x23
+#define SCSI_READ_CAPACITY          0x25
+#define SCSI_READ_10                0x28
+#define SCSI_WRITE_10               0x2a
+
+//*****************************************************************************
+//
+// SCSI Test Unit Ready definitions.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// SCSI Inquiry command definitions.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Size of the SCSI inquiry response data.
+//
+//*****************************************************************************
+#define SCSI_INQUIRY_DATA_SZ    36
+
+//*****************************************************************************
+//
+// Offset 0 of the Inquiry Data.
+//
+//*****************************************************************************
+#define SCSI_INQ_PQ_M           0xe0  // Peripheral Qualifier Mask.
+#define SCSI_INQ_PQ_CNCT        0x00  // Device connected.
+#define SCSI_INQ_PQ_DISC        0x20  // Device disconnected.
+#define SCSI_INQ_PDT_M          0x1f  // Peripheral Device Type Mask.
+#define SCSI_INQ_PDT_SBC        0x00  // Direct Access device.
+
+//*****************************************************************************
+//
+// Offset 1 of the Inquiry Data.
+//
+//*****************************************************************************
+#define SCSI_INQ_RMB            0x80  // Device is removable.
+
+//*****************************************************************************
+//
+// Macro to check if removeable.
+//
+//*****************************************************************************
+#define SCSIIsRemovable(pData)                       \
+        (((unsigned char *)pData)[1] & SCSI_INQ_RMB)
+
+//*****************************************************************************
+//
+// SCSI Read Capacity definitions.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Size of the SCSI Read Capacity response data.
+//
+//*****************************************************************************
+#define SCSI_READ_CAPACITY_SZ   0x08
+
+//*****************************************************************************
+//
+// SCSI Mode Sense definitions, these are passed in via the ulFlags parameter
+// of the SCSIModeSense() function call.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Disable block descriptors.
+//
+//*****************************************************************************
+#define SCSI_MS_DBD             0x00000800
+
+//*****************************************************************************
+//
+// Page Code values, used in combination with Page Control values.
+//
+//*****************************************************************************
+#define SCSI_MS_PC_VENDOR       0x00000000
+#define SCSI_MS_PC_DISCO        0x00020000
+#define SCSI_MS_PC_CONTROL      0x000a0000
+#define SCSI_MS_PC_LUN          0x00180000
+#define SCSI_MS_PC_PORT         0x00190000
+#define SCSI_MS_PC_POWER        0x001a0000
+#define SCSI_MS_PC_INFORM       0x001c0000
+#define SCSI_MS_PC_ALL          0x003f0000
+
+//*****************************************************************************
+//
+// Page Control values.
+//
+//*****************************************************************************
+#define SCSI_MS_PC_CURRENT      0x00000000
+#define SCSI_MS_PC_CHANGEABLE   0x00400000
+#define SCSI_MS_PC_DEFAULT      0x00800000
+#define SCSI_MS_PC_SAVED        0x00c00000
+
+//*****************************************************************************
+//
+// Request Sense Definitions.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Size of the data returned by the Request Sense command.
+//
+//*****************************************************************************
+#define SCSI_REQUEST_SENSE_SZ   18
+
+#define SCSI_RS_SKEY            2     // Sense Key offset.
+#define SCSI_RS_SKEY_AD_SKEY    12    // Additional Sense Key offset.
+
+//*****************************************************************************
+//
+// Offset 0 in the Request Sense response.
+//
+//*****************************************************************************
+#define SCSI_RS_VALID           0x80  // Response is valid.
+#define SCSI_RS_CUR_ERRORS      0x70  // Current errors returned.
+#define SCSI_RS_DEFER_ERRORS    0x71  // Deferred errors returned.
+
+//*****************************************************************************
+//
+// Offset 2 in the Request Sense response.
+//
+//*****************************************************************************
+#define SCSI_RS_KEY_M           0x0f  // Sense Key.
+#define SCSI_RS_KEY_NO_SENSE    0x00  // No Sense Data.
+#define SCSI_RS_KEY_RECOVRD_ERR 0x01  // Recovered Error.
+#define SCSI_RS_KEY_NOT_READY   0x02  // Not Ready.
+#define SCSI_RS_KEY_MEDIUM_ERR  0x03  // Error in the media.
+#define SCSI_RS_KEY_HW_ERR      0x04  // Hardware Error, non recoverable.
+#define SCSI_RS_KEY_ILGL_RQST   0x05  // Illegal request.
+#define SCSI_RS_KEY_UNIT_ATTN   0x06  // Unit changed or reset.
+#define SCSI_RS_KEY_DATA_PROT   0x07  // Write Protect error.
+#define SCSI_RS_KEY_BLANK_CHK   0x07  // Write once error, block not clear.
+#define SCSI_RS_KEY_ABORT       0x0b  // Last command was aborted.
+#define SCSI_RS_ILI             0x20  // Incorrect length indicator.
+#define SCSI_RS_EOM             0x40  // End of medium condition.
+#define SCSI_RS_FILEMARK        0x80  // Command has read a filemark/setmark.
+#define SCSI_RS_MED_NOT_PRSNT   0x003a  // Medium not present.
+#define SCSI_RS_MED_NOTRDY2RDY  0x0028  // Not ready to ready transition.
+#define SCSI_RS_PV_INVALID      0x0226  // Parameter Value Invalid.
+
+//*****************************************************************************
+//
+// Additional information for SCSI_RS_KEY_NOT_READY
+//
+//*****************************************************************************
+#define SCSI_RS_KEY_NOTPRSNT    0x3A  // Media Not Present.
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __USBMSC_H__
diff --git a/src/platform/lm3s/usblib/usbringbuf.c b/src/platform/lm3s/usblib/usbringbuf.c
new file mode 100755
index 00000000..c49f8b5c
--- /dev/null
+++ b/src/platform/lm3s/usblib/usbringbuf.c
@@ -0,0 +1,712 @@
+//*****************************************************************************
+//
+// usbringbuf.c - USB library ring buffer management utilities.
+//
+// Copyright (c) 2008-2011 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 7611 of the Stellaris USB Library.
+//
+//*****************************************************************************
+
+#include "inc/hw_types.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+#include "usblib/usblib.h"
+
+//*****************************************************************************
+//
+//! \addtogroup usblib_buffer_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Define NULL, if not already defined.
+//
+//*****************************************************************************
+#ifndef NULL
+#define NULL                    ((void *)0)
+#endif
+
+//*****************************************************************************
+//
+// Change the value of a variable atomically.
+//
+// \param pulVal points to the index whose value is to be modified.
+// \param ulDelta is the number of bytes to increment the index by.
+// \param ulSize is the size of the buffer the index refers to.
+//
+// This function is used to increment a read or write buffer index that may be
+// written in various different contexts.  It ensures that the
+// read/modify/write sequence is not interrupted and, hence, guards against
+// corruption of the variable.  The new value is adjusted for buffer wrap.
+//
+// \return None.
+//
+//*****************************************************************************
+static void
+UpdateIndexAtomic(volatile unsigned long *pulVal, unsigned long ulDelta,
+                  unsigned long ulSize)
+{
+    tBoolean bIntsOff;
+
+    //
+    // Turn interrupts off temporarily.
+    //
+    bIntsOff = IntMasterDisable();
+
+    //
+    // Update the variable value.
+    //
+    *pulVal += ulDelta;
+
+    //
+    // Correct for wrap.  We use a loop here since we don't want to use a
+    // modulus operation with interrupts off but we don't want to fail in
+    // case ulDelta is greater than ulSize (which is extremely unlikely but...)
+    //
+    while(*pulVal >= ulSize)
+    {
+        *pulVal -= ulSize;
+    }
+
+    //
+    // Restore the interrupt state
+    //
+    if(!bIntsOff)
+    {
+        IntMasterEnable();
+    }
+}
+
+//*****************************************************************************
+//
+//! Determines whether a ring buffer is full or not.
+//!
+//! \param ptUSBRingBuf is the ring buffer object to empty.
+//!
+//! This function is used to determine whether or not a given ring buffer is
+//! full.  The structure is specifically to ensure that we do not see
+//! warnings from the compiler related to the order of volatile accesses
+//! being undefined.
+//!
+//! \return Returns \b true if the buffer is full or \b false otherwise.
+//
+//*****************************************************************************
+tBoolean
+USBRingBufFull(tUSBRingBufObject *ptUSBRingBuf)
+{
+    unsigned long ulWrite;
+    unsigned long ulRead;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ptUSBRingBuf != NULL);
+
+    //
+    // Copy the Read/Write indices for calculation.
+    //
+    ulWrite = ptUSBRingBuf->ulWriteIndex;
+    ulRead = ptUSBRingBuf->ulReadIndex;
+
+    //
+    // Return the full status of the buffer.
+    //
+    return((((ulWrite + 1) % ptUSBRingBuf->ulSize) == ulRead) ? true : false);
+}
+
+//*****************************************************************************
+//
+//! Determines whether a ring buffer is empty or not.
+//!
+//! \param ptUSBRingBuf is the ring buffer object to empty.
+//!
+//! This function is used to determine whether or not a given ring buffer is
+//! empty.  The structure is specifically to ensure that we do not see
+//! warnings from the compiler related to the order of volatile accesses
+//! being undefined.
+//!
+//! \return Returns \b true if the buffer is empty or \b false otherwise.
+//
+//*****************************************************************************
+tBoolean
+USBRingBufEmpty(tUSBRingBufObject *ptUSBRingBuf)
+{
+    unsigned long ulWrite;
+    unsigned long ulRead;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ptUSBRingBuf != NULL);
+
+    //
+    // Copy the Read/Write indices for calculation.
+    //
+    ulWrite = ptUSBRingBuf->ulWriteIndex;
+    ulRead = ptUSBRingBuf->ulReadIndex;
+
+    //
+    // Return the empty status of the buffer.
+    //
+    return((ulWrite == ulRead) ? true : false);
+}
+
+//*****************************************************************************
+//
+//! Empties the ring buffer.
+//!
+//! \param ptUSBRingBuf is the ring buffer object to empty.
+//!
+//! Discards all data from the ring buffer.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBRingBufFlush(tUSBRingBufObject *ptUSBRingBuf)
+{
+    tBoolean bIntsOff;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ptUSBRingBuf != NULL);
+
+    //
+    // Set the Read/Write pointers to be the same.  Do this with interrupts
+    // disabled to prevent the possibility of corruption of the read index.
+    //
+    bIntsOff = IntMasterDisable();
+    ptUSBRingBuf->ulReadIndex = ptUSBRingBuf->ulWriteIndex;
+    if(!bIntsOff)
+    {
+        IntMasterEnable();
+    }
+}
+
+//*****************************************************************************
+//
+//! Returns number of bytes stored in ring buffer.
+//!
+//! \param ptUSBRingBuf is the ring buffer object to check.
+//!
+//! This function returns the number of bytes stored in the ring buffer.
+//!
+//! \return Returns the number of bytes stored in the ring buffer.
+//
+//*****************************************************************************
+unsigned long
+USBRingBufUsed(tUSBRingBufObject *ptUSBRingBuf)
+{
+    unsigned long ulWrite;
+    unsigned long ulRead;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ptUSBRingBuf != NULL);
+
+    //
+    // Copy the Read/Write indices for calculation.
+    //
+    ulWrite = ptUSBRingBuf->ulWriteIndex;
+    ulRead = ptUSBRingBuf->ulReadIndex;
+
+    //
+    // Return the number of bytes contained in the ring buffer.
+    //
+    return((ulWrite >= ulRead) ? (ulWrite - ulRead) :
+           (ptUSBRingBuf->ulSize - (ulRead - ulWrite)));
+}
+
+//*****************************************************************************
+//
+//! Returns number of bytes available in a ring buffer.
+//!
+//! \param ptUSBRingBuf is the ring buffer object to check.
+//!
+//! This function returns the number of bytes available in the ring buffer.
+//!
+//! \return Returns the number of bytes available in the ring buffer.
+//
+//*****************************************************************************
+unsigned long
+USBRingBufFree(tUSBRingBufObject *ptUSBRingBuf)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ptUSBRingBuf != NULL);
+
+    //
+    // Return the number of bytes available in the ring buffer.
+    //
+    return((ptUSBRingBuf->ulSize - 1) - USBRingBufUsed(ptUSBRingBuf));
+}
+
+//*****************************************************************************
+//
+//! Returns number of contiguous bytes of data stored in ring buffer ahead of
+//! the current read pointer.
+//!
+//! \param ptUSBRingBuf is the ring buffer object to check.
+//!
+//! This function returns the number of contiguous bytes of data available in
+//! the ring buffer ahead of the current read pointer.  This represents the
+//! largest block of data which does not straddle the buffer wrap.
+//!
+//! \return Returns the number of contiguous bytes available.
+//
+//*****************************************************************************
+unsigned long
+USBRingBufContigUsed(tUSBRingBufObject *ptUSBRingBuf)
+{
+    unsigned long ulWrite;
+    unsigned long ulRead;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ptUSBRingBuf != NULL);
+
+    //
+    // Copy the Read/Write indices for calculation.
+    //
+    ulWrite = ptUSBRingBuf->ulWriteIndex;
+    ulRead = ptUSBRingBuf->ulReadIndex;
+
+    //
+    // Return the number of contiguous bytes available.
+    //
+    return((ulWrite >= ulRead) ? (ulWrite - ulRead) :
+           (ptUSBRingBuf->ulSize - ulRead));
+}
+
+//*****************************************************************************
+//
+//! Returns number of contiguous free bytes available in a ring buffer.
+//!
+//! \param ptUSBRingBuf is the ring buffer object to check.
+//!
+//! This function returns the number of contiguous free bytes ahead of the
+//! current write pointer in the ring buffer.
+//!
+//! \return Returns the number of contiguous bytes available in the ring
+//! buffer.
+//
+//*****************************************************************************
+unsigned long
+USBRingBufContigFree(tUSBRingBufObject *ptUSBRingBuf)
+{
+    unsigned long ulWrite;
+    unsigned long ulRead;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ptUSBRingBuf != NULL);
+
+    //
+    // Copy the Read/Write indices for calculation.
+    //
+    ulWrite = ptUSBRingBuf->ulWriteIndex;
+    ulRead = ptUSBRingBuf->ulReadIndex;
+
+    //
+    // Return the number of contiguous bytes available.
+    //
+    if(ulRead > ulWrite)
+    {
+        //
+        // The read pointer is above the write pointer so the amount of free
+        // space is the difference between the two indices minus 1 to account
+        // for the buffer full condition (write index one behind read index).
+        //
+        return((ulRead - ulWrite) - 1);
+    }
+    else
+    {
+        //
+        // If the write pointer is above the read pointer, the amount of free
+        // space is the size of the buffer minus the write index.  We need to
+        // add a special-case adjustment if the read index is 0 since we need
+        // to leave 1 byte empty to ensure we can tell the difference between
+        // the buffer being full and empty.
+        //
+        return(ptUSBRingBuf->ulSize - ulWrite - ((ulRead == 0) ? 1 : 0));
+    }
+}
+
+//*****************************************************************************
+//
+//! Returns the size in bytes of a ring buffer.
+//!
+//! \param ptUSBRingBuf is the ring buffer object to check.
+//!
+//! This function returns the size of the ring buffer.
+//!
+//! \return Returns the size in bytes of the ring buffer.
+//
+//*****************************************************************************
+unsigned long
+USBRingBufSize(tUSBRingBufObject *ptUSBRingBuf)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ptUSBRingBuf != NULL);
+
+    //
+    // Return the number of bytes available in the ring buffer.
+    //
+    return(ptUSBRingBuf->ulSize);
+}
+
+//*****************************************************************************
+//
+//! Reads a single byte of data from a ring buffer.
+//!
+//! \param ptUSBRingBuf points to the ring buffer to be written to.
+//!
+//! This function reads a single byte of data from a ring buffer.
+//!
+//! \return The byte read from the ring buffer.
+//
+//*****************************************************************************
+unsigned char
+USBRingBufReadOne(tUSBRingBufObject *ptUSBRingBuf)
+{
+    unsigned char ucTemp;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ptUSBRingBuf != NULL);
+
+    //
+    // Verify that space is available in the buffer.
+    //
+    ASSERT(USBRingBufUsed(ptUSBRingBuf) != 0);
+
+    //
+    // Write the data byte.
+    //
+    ucTemp = ptUSBRingBuf->pucBuf[ptUSBRingBuf->ulReadIndex];
+
+    //
+    // Increment the read index.
+    //
+    UpdateIndexAtomic(&ptUSBRingBuf->ulReadIndex, 1, ptUSBRingBuf->ulSize);
+
+    //
+    // Return the character read.
+    //
+    return(ucTemp);
+}
+
+//*****************************************************************************
+//
+//! Reads data from a ring buffer.
+//!
+//! \param ptUSBRingBuf points to the ring buffer to be read from.
+//! \param pucData points to where the data should be stored.
+//! \param ulLength is the number of bytes to be read.
+//!
+//! This function reads a sequence of bytes from a ring buffer.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBRingBufRead(tUSBRingBufObject *ptUSBRingBuf, unsigned char *pucData,
+               unsigned long ulLength)
+{
+    unsigned long ulTemp;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ptUSBRingBuf != NULL);
+    ASSERT(pucData != NULL);
+    ASSERT(ulLength != 0);
+
+    //
+    // Verify that data is available in the buffer.
+    //
+    ASSERT(ulLength <= USBRingBufUsed(ptUSBRingBuf));
+
+    //
+    // Read the data from the ring buffer.
+    //
+    for(ulTemp = 0; ulTemp < ulLength; ulTemp++)
+    {
+        pucData[ulTemp] = USBRingBufReadOne(ptUSBRingBuf);
+    }
+}
+
+//*****************************************************************************
+//
+//! Removes bytes from the ring buffer by advancing the read index.
+//!
+//! \param ptUSBRingBuf points to the ring buffer from which bytes are to be
+//! removed.
+//! \param ulNumBytes is the number of bytes to be removed from the buffer.
+//!
+//! This function advances the ring buffer read index by a given number of
+//! bytes, removing that number of bytes of data from the buffer.  If \e
+//! ulNumBytes is larger than the number of bytes currently in the buffer, the
+//! buffer is emptied.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBRingBufAdvanceRead(tUSBRingBufObject *ptUSBRingBuf,
+                      unsigned long ulNumBytes)
+{
+    unsigned long ulCount;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ptUSBRingBuf != NULL);
+
+    //
+    // Make sure that we are not being asked to remove more data than is
+    // there to be removed.
+    //
+    ulCount = USBRingBufUsed(ptUSBRingBuf);
+    ulCount =  (ulCount < ulNumBytes) ? ulCount : ulNumBytes;
+
+    //
+    // Advance the buffer read index by the required number of bytes.
+    //
+    UpdateIndexAtomic(&ptUSBRingBuf->ulReadIndex, ulCount,
+                      ptUSBRingBuf->ulSize);
+}
+
+//*****************************************************************************
+//
+//! Adds bytes to the ring buffer by advancing the write index.
+//!
+//! \param ptUSBRingBuf points to the ring buffer to which bytes have been
+//! added.
+//! \param ulNumBytes is the number of bytes added to the buffer.
+//!
+//! This function should be used by clients who wish to add data to the buffer
+//! directly rather than via calls to USBRingBufWrite() or
+//! USBRingBufWriteOne().  It advances the write index by a given number of
+//! bytes.
+//!
+//! \note It is considered an error if the \e ulNumBytes parameter is larger
+//! than the amount of free space in the buffer and a debug build of this
+//! function will fail (ASSERT) if this condition is detected.  In a release
+//! build, the buffer read pointer will be advanced if too much data is written
+//! but this will, of course, result in some of the oldest data in the buffer
+//! being discarded and also, depending upon how data is being read from
+//! the buffer, may result in a race condition which could corrupt the read
+//! pointer.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBRingBufAdvanceWrite(tUSBRingBufObject *ptUSBRingBuf,
+                       unsigned long ulNumBytes)
+{
+    unsigned long ulCount;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ptUSBRingBuf != NULL);
+
+    //
+    // Make sure we were not asked to add a silly number of bytes.
+    //
+    ASSERT(ulNumBytes <= ptUSBRingBuf->ulSize);
+
+    //
+    // Determine how much free space we currently think the buffer has.
+    //
+    ulCount = USBRingBufFree(ptUSBRingBuf);
+
+    //
+    // Check that the client has not added more data to the buffer than there
+    // is space for.  In this case, corruption may have occurred since the
+    // buffer may have been read under interrupt context while the writer was
+    // busy trashing the area around the read pointer.
+    //
+    ASSERT(ulCount >= ulNumBytes);
+
+    //
+    // Update the write pointer.
+    //
+    ptUSBRingBuf->ulWriteIndex += ulNumBytes;
+
+    //
+    // Check and correct for wrap.
+    //
+    if(ptUSBRingBuf->ulWriteIndex >= ptUSBRingBuf->ulSize)
+    {
+        ptUSBRingBuf->ulWriteIndex -= ptUSBRingBuf->ulSize;
+    }
+
+    //
+    // Did the client add more bytes than the buffer had free space for?  This
+    // should be considered a bug since, unless this function is called in
+    // the same context as the code which is reading from the buffer, writing
+    // over the earliest data can cause corrupted data to be read.  The
+    // ASSERT above catches this in debug builds but, in release builds, we
+    // go ahead and try to fix up the read pointer appropriately.
+    //
+    if(ulCount < ulNumBytes)
+    {
+        //
+        // Yes - we need to advance the read pointer to ahead of the write
+        // pointer to discard some of the oldest data.
+        //
+        ptUSBRingBuf->ulReadIndex = ptUSBRingBuf->ulWriteIndex + 1;
+
+        //
+        // Correct for buffer wrap if necessary.
+        //
+        if(ptUSBRingBuf->ulReadIndex >= ptUSBRingBuf->ulSize)
+        {
+            ptUSBRingBuf->ulReadIndex -= ptUSBRingBuf->ulSize;
+        }
+    }
+
+}
+
+//*****************************************************************************
+//
+//! Writes a single byte of data to a ring buffer.
+//!
+//! \param ptUSBRingBuf points to the ring buffer to be written to.
+//! \param ucData is the byte to be written.
+//!
+//! This function writes a single byte of data into a ring buffer.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBRingBufWriteOne(tUSBRingBufObject *ptUSBRingBuf, unsigned char ucData)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ptUSBRingBuf != NULL);
+
+    //
+    // Verify that space is available in the buffer.
+    //
+    ASSERT(USBRingBufFree(ptUSBRingBuf) != 0);
+
+    //
+    // Write the data byte.
+    //
+    ptUSBRingBuf->pucBuf[ptUSBRingBuf->ulWriteIndex] = ucData;
+
+    //
+    // Increment the write index.
+    //
+    UpdateIndexAtomic(&ptUSBRingBuf->ulWriteIndex, 1, ptUSBRingBuf->ulSize);
+}
+
+//*****************************************************************************
+//
+//! Writes data to a ring buffer.
+//!
+//! \param ptUSBRingBuf points to the ring buffer to be written to.
+//! \param pucData points to the data to be written.
+//! \param ulLength is the number of bytes to be written.
+//!
+//! This function write a sequence of bytes into a ring buffer.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBRingBufWrite(tUSBRingBufObject *ptUSBRingBuf, const unsigned char *pucData,
+                unsigned long ulLength)
+{
+    unsigned long ulTemp;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ptUSBRingBuf != NULL);
+    ASSERT(pucData != NULL);
+    ASSERT(ulLength != 0);
+
+    //
+    // Verify that space is available in the buffer.
+    //
+    ASSERT(ulLength <= USBRingBufFree(ptUSBRingBuf));
+
+    //
+    // Write the data into the ring buffer.
+    //
+    for(ulTemp = 0; ulTemp < ulLength; ulTemp++)
+    {
+        USBRingBufWriteOne(ptUSBRingBuf, pucData[ulTemp]);
+    }
+}
+
+//*****************************************************************************
+//
+//! Initializes a ring buffer object.
+//!
+//! \param ptUSBRingBuf points to the ring buffer to be initialized.
+//! \param pucBuf points to the data buffer to be used for the ring buffer.
+//! \param ulSize is the size of the buffer in bytes.
+//!
+//! This function initializes a ring buffer object, preparing it to store data.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBRingBufInit(tUSBRingBufObject *ptUSBRingBuf, unsigned char *pucBuf,
+               unsigned long ulSize)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ptUSBRingBuf != NULL);
+    ASSERT(pucBuf != NULL);
+    ASSERT(ulSize != 0);
+
+    //
+    // Initialize the ring buffer object.
+    //
+    ptUSBRingBuf->ulSize = ulSize;
+    ptUSBRingBuf->pucBuf = pucBuf;
+    ptUSBRingBuf->ulWriteIndex = ptUSBRingBuf->ulReadIndex = 0;
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/src/platform/lm3s/usblib/usbtick.c b/src/platform/lm3s/usblib/usbtick.c
new file mode 100755
index 00000000..2620d0ad
--- /dev/null
+++ b/src/platform/lm3s/usblib/usbtick.c
@@ -0,0 +1,182 @@
+//*****************************************************************************
+//
+// usbtick.c - Functions related to USB stack tick timer handling.
+//
+// Copyright (c) 2008-2011 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 7611 of the Stellaris USB Library.
+//
+//*****************************************************************************
+
+#include "inc/hw_types.h"
+#include "driverlib/debug.h"
+#include "usblib/usblib.h"
+#include "usblib/usblibpriv.h"
+
+//*****************************************************************************
+//
+//! \addtogroup general_usblib_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// These are the internal timer tick handlers used by the USB stack.  Handlers
+// in g_pfTickHandlers are called in the context of the USB SOF interrupt
+// every USB_SOF_TICK_DIVIDE milliseconds.
+//
+//*****************************************************************************
+tUSBTickHandler g_pfTickHandlers[USB_TICK_HANDLER_NUM];
+void *g_pvTickInstance[USB_TICK_HANDLER_NUM];
+
+//*****************************************************************************
+//
+// Flag to indicate whether or not we have been initialized.
+//
+//*****************************************************************************
+tBoolean g_bUSBTimerInitialized = false;
+
+//*****************************************************************************
+//
+// This is the current tick value in ms for the system.  This is used for all
+// instances of USB controllers and for all timer tick handlers.
+//
+//*****************************************************************************
+unsigned long g_ulCurrentUSBTick = 0;
+
+//*****************************************************************************
+//
+// This is the total number of SOF interrupts received since the system
+// booted.  The value is incremented by the low level device- or host-interrupt
+// handler functions.
+//
+//*****************************************************************************
+unsigned long g_ulUSBSOFCount = 0;
+
+//*****************************************************************************
+//
+// This internal function initializes the variables used in processing timer
+// ticks.
+//
+// This function should only be called from within the USB library.  It is set
+// up to ensure that it can be called multiple times if necessary without
+// the previous configuration being erased (to cater for OTG mode switching).
+//
+// \return None.
+//
+//*****************************************************************************
+void
+InternalUSBTickInit(void)
+{
+    unsigned long ulLoop;
+
+    if(!g_bUSBTimerInitialized)
+    {
+        for(ulLoop = 0; ulLoop < USB_TICK_HANDLER_NUM; ulLoop++)
+        {
+            g_pfTickHandlers[ulLoop] = (tUSBTickHandler)0;
+            g_pvTickInstance[ulLoop] = 0;
+        }
+
+        g_bUSBTimerInitialized = true;
+    }
+}
+
+//*****************************************************************************
+//
+// This internal function handles registering OTG, Host, or Device SOF timer
+// handler functions.
+//
+// \param ulHandler specifies which type of handler to register.
+// \param pfHandler specifies the handler to call for the given type of
+// handler.
+//
+// This function should only be called inside the USB library and only as a
+// result to a call to reinitialize the stack in a new mode.  Currently the
+// following 3 types of timer tick handlers can be registered:
+// TICK_HANDLER_OTG, TICK_HANDLER_HOST, or TICK_HANDLER_DEVICE.  Handlers
+// registered via this function are called in the context of the SOF interrupt.
+//
+// \return None.
+//
+//*****************************************************************************
+void
+InternalUSBRegisterTickHandler(unsigned long ulHandler,
+                               tUSBTickHandler pfHandler,
+                               void *pvInstance)
+{
+    ASSERT(ulHandler < USB_TICK_HANDLER_NUM);
+
+    //
+    // Save the handler.
+    //
+    g_pfTickHandlers[ulHandler] = pfHandler;
+
+    //
+    // Save the instance data.
+    //
+    g_pvTickInstance[ulHandler] = pvInstance;
+}
+
+//*****************************************************************************
+//
+//! \internal
+//!
+//! Calls internal handlers in response to a tick based on the start of frame
+//! interrupt.
+//!
+//! \param ulTicksmS specifies how many milliseconds have passed since the last
+//! call to this function.
+//!
+//! This function is called every 5mS in the context of the Start of Frame
+//! (SOF) interrupt.  It is used to call any registered internal tick
+//! functions.
+//!
+//! This function should only be called from within the USB library.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+InternalUSBStartOfFrameTick(unsigned long ulTicksmS)
+{
+    long lIdx;
+
+    //
+    // Advance time.
+    //
+    g_ulCurrentUSBTick += ulTicksmS;
+
+    //
+    // Call any registered SOF tick handlers.
+    //
+    for(lIdx = 0; lIdx < USB_TICK_HANDLER_NUM; lIdx++)
+    {
+        if(g_pfTickHandlers[lIdx])
+        {
+            g_pfTickHandlers[lIdx](g_pvTickInstance[lIdx], ulTicksmS);
+        }
+    }
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/src/platform/lpc17xx/platform.c b/src/platform/lpc17xx/platform.c
index 6c3c79eb..ed8ca0c4 100644
--- a/src/platform/lpc17xx/platform.c
+++ b/src/platform/lpc17xx/platform.c
@@ -28,6 +28,8 @@
 #include "lpc17xx_pwm.h"
 #include "lpc17xx_adc.h"
 
+#define SYSTICKHZ             10
+
 // ****************************************************************************
 // Platform initialization
 
@@ -43,13 +45,13 @@ int platform_init()
   // DeInit NVIC and SCBNVIC
   NVIC_DeInit();
   NVIC_SCBDeInit();
-	
+
   // Configure the NVIC Preemption Priority Bits:
   // two (2) bits of preemption priority, six (6) bits of sub-priority.
   // Since the Number of Bits used for Priority Levels is five (5), so the
   // actual bit number of sub-priority is three (3)
   NVIC_SetPriorityGrouping(0x05);
-	
+
   //  Set Vector table offset value
 #if (__RAM_MODE__==1)
   NVIC_SetVTOR(0x10000000);
@@ -66,12 +68,35 @@ int platform_init()
   platform_setup_adcs();
 #endif
 
+  // System timer setup
+  cmn_systimer_set_base_freq( mbed_get_cpu_frequency() );
+  cmn_systimer_set_interrupt_freq( SYSTICKHZ );
+
+  // Enable SysTick
+  SysTick_Config( mbed_get_cpu_frequency() / SYSTICKHZ );
+
   // Common platform initialization code
   cmn_platform_init();
 
   return PLATFORM_OK;
 } 
 
+extern u32 SystemCoreClock;
+u32 mbed_get_cpu_frequency()
+{
+  return SystemCoreClock;
+}
+
+// SysTick interrupt handler
+void SysTick_Handler()
+{
+  // Handle virtual timers
+  cmn_virtual_timer_cb();
+
+  // Handle system timer call
+  cmn_systimer_periodic();
+}
+
 // ****************************************************************************
 // PIO section
    
@@ -79,7 +104,6 @@ int platform_init()
 pio_type platform_pio_op( unsigned port, pio_type pinmask, int op )
 {
   pio_type retval = 1;
-  u32 idx = 0;
   
   switch( op )
   {
@@ -134,18 +158,17 @@ pio_type platform_pio_op( unsigned port, pio_type pinmask, int op )
 // The other UARTs have assignable Rx/Tx pins and thus have to be configured
 // by the user
 
-static LPC_UART_TypeDef *uart[] = { LPC_UART0, LPC_UART1, LPC_UART2, LPC_UART3 };
+static LPC_UART_TypeDef* const uart[] = { LPC_UART0, LPC_UART1, LPC_UART2, LPC_UART3 };
 
 u32 platform_uart_setup( unsigned id, u32 baud, int databits, int parity, int stopbits )
 {
-  u32 temp;
   // UART Configuration structure variable
   UART_CFG_Type UARTConfigStruct;
   // UART FIFO configuration Struct variable
   UART_FIFO_CFG_Type UARTFIFOConfigStruct;
   // Pin configuration for UART0
   PINSEL_CFG_Type PinCfg;
-	
+
   // UART0 Pin Config
   PinCfg.Funcnum = 1;
   PinCfg.OpenDrain = 0;
@@ -155,7 +178,7 @@ u32 platform_uart_setup( unsigned id, u32 baud, int databits, int parity, int st
   PINSEL_ConfigPin(&PinCfg);
   PinCfg.Pinnum = 3;
   PINSEL_ConfigPin(&PinCfg);
-	
+
   UARTConfigStruct.Baud_rate = ( uint32_t )baud;
   
   switch( databits )
@@ -196,9 +219,9 @@ u32 platform_uart_setup( unsigned id, u32 baud, int databits, int parity, int st
       UARTConfigStruct.Parity = UART_PARITY_EVEN;
       break;
   }
-	
+
   UART_Init(uart[ id ], &UARTConfigStruct);
-	
+
   // Get default FIFO config and initialize
   UART_FIFOConfigStructInit(&UARTFIFOConfigStruct);
   UART_FIFOConfig(uart[ id ], &UARTFIFOConfigStruct);
@@ -214,7 +237,7 @@ void platform_s_uart_send( unsigned id, u8 data )
   UART_Send(uart[ id ], &data, 1, BLOCKING);
 }
 
-int platform_s_uart_recv( unsigned id, s32 timeout )
+int platform_s_uart_recv( unsigned id, timer_data_type timeout )
 {
   u8 buffer;
   
@@ -256,8 +279,8 @@ static u32 platform_timer_set_clock( unsigned id, u32 clock )
 
   // Initialize timer 0, prescale count time of 1uS
   TIM_ConfigStruct.PrescaleOption = TIM_PRESCALE_USVAL;
-  TIM_ConfigStruct.PrescaleValue	= 1000000ULL / clock;
-	
+  TIM_ConfigStruct.PrescaleValue  = 1000000ULL / clock;
+
   TIM_Init( tmr[ id ], TIM_TIMER_MODE, &TIM_ConfigStruct );
   TIM_Cmd( tmr[ id ], ENABLE );
   TIM_ResetCounter( tmr[ id ] );
@@ -279,7 +302,7 @@ static void platform_setup_timers()
     platform_timer_set_clock( i, 1000000ULL );
 }
 
-void platform_s_timer_delay( unsigned id, u32 delay_us )
+void platform_s_timer_delay( unsigned id, timer_data_type delay_us )
 {
   u32 last;
 
@@ -289,7 +312,7 @@ void platform_s_timer_delay( unsigned id, u32 delay_us )
   while( tmr[ id ]->TC < last );
 }
       
-u32 platform_s_timer_op( unsigned id, int op, u32 data )
+timer_data_type platform_s_timer_op( unsigned id, int op, timer_data_type data )
 {
   u32 res = 0;
 
@@ -304,14 +327,6 @@ u32 platform_s_timer_op( unsigned id, int op, u32 data )
       res = tmr[ id ]->TC;
       break;
 
-    case PLATFORM_TIMER_OP_GET_MAX_DELAY:
-      res = platform_timer_get_diff_us( id, 0, 0xFFFFFFFF );
-      break;
-      
-    case PLATFORM_TIMER_OP_GET_MIN_DELAY:
-      res = platform_timer_get_diff_us( id, 0, 1 );
-      break;      
-      
     case PLATFORM_TIMER_OP_SET_CLOCK:
       res = platform_timer_set_clock( id, data );
       break;
@@ -319,10 +334,34 @@ u32 platform_s_timer_op( unsigned id, int op, u32 data )
     case PLATFORM_TIMER_OP_GET_CLOCK:
       res = platform_timer_get_clock( id );
       break;
+
+    case PLATFORM_TIMER_OP_GET_MAX_CNT:
+      res = 0xFFFFFFFF;
+      break;
   }
   return res;
 }
 
+u64 platform_timer_sys_raw_read()
+{
+  return SysTick->LOAD - SysTick->VAL;
+}
+
+void platform_timer_sys_disable_int()
+{
+  SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
+}
+
+void platform_timer_sys_enable_int()
+{
+  SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
+}
+
+timer_data_type platform_timer_read_sys()
+{
+  return cmn_systimer_get();
+}
+
 // *****************************************************************************
 // ADC specific functions and variables
 
@@ -427,12 +466,12 @@ static void platform_setup_adcs()
   // Default enables ADC interrupt only on global, switch to per-channel
   ADC_IntConfig( LPC_ADC, ADC_ADGINTEN, DISABLE );
     
-  platform_adc_setclock( 0, 0 );
+  platform_adc_set_clock( 0, 0 );
 }
 
 
 // NOTE: On this platform, there is only one ADC, clock settings apply to the whole device
-u32 platform_adc_setclock( unsigned id, u32 frequency )
+u32 platform_adc_set_clock( unsigned id, u32 frequency )
 {
   TIM_TIMERCFG_Type TIM_ConfigStruct;
   TIM_MATCHCFG_Type TIM_MatchConfigStruct ;
@@ -448,7 +487,7 @@ u32 platform_adc_setclock( unsigned id, u32 frequency )
         
     // Run timer at 1MHz
     TIM_ConfigStruct.PrescaleOption = TIM_PRESCALE_USVAL;
-    TIM_ConfigStruct.PrescaleValue	= 1;
+    TIM_ConfigStruct.PrescaleValue     = 1;
     
     TIM_MatchConfigStruct.MatchChannel = 1;
     TIM_MatchConfigStruct.IntOnMatch   = FALSE;
@@ -459,7 +498,7 @@ u32 platform_adc_setclock( unsigned id, u32 frequency )
     TIM_MatchConfigStruct.MatchValue   = ( 1000000ULL / ( frequency * 2 ) ) - 1;
         
     frequency = 1000000ULL / (TIM_MatchConfigStruct.MatchValue + 1);
-  	
+  
     // Set configuration for Tim_config and Tim_MatchConfig
     TIM_Init( tmr[ d->timer_id ], TIM_TIMER_MODE, &TIM_ConfigStruct );
     TIM_ConfigMatch( tmr[ d->timer_id ], &TIM_MatchConfigStruct );
@@ -538,20 +577,20 @@ int platform_adc_start_sequence()
 
 
 // Helper function: get timer clock
-static u32 platform_pwm_get_clock( unsigned id )
+u32 platform_pwm_get_clock( unsigned id )
 {
   return CLKPWR_GetPCLK( CLKPWR_PCLKSEL_PWM1 ) / ( LPC_PWM1->PR + 1 );
 }
 
 // Helper function: set timer clock
-static u32 platform_pwm_set_clock( unsigned id, u32 clock )
+u32 platform_pwm_set_clock( unsigned id, u32 clock )
 {
   PWM_TIMERCFG_Type PWMCfgDat;
   
   PWMCfgDat.PrescaleOption = PWM_TIMER_PRESCALE_USVAL;
   PWMCfgDat.PrescaleValue = 1000000ULL / clock;
   PWM_Init( LPC_PWM1, PWM_MODE_TIMER, &PWMCfgDat );
-	
+
   return clock;
 }
 
@@ -599,30 +638,14 @@ u32 platform_pwm_setup( unsigned id, u32 frequency, unsigned duty )
   return platform_pwm_get_clock( id ) / divisor;
 }
 
-u32 platform_pwm_op( unsigned id, int op, u32 data )
+void platform_pwm_start( unsigned id )
 {
-  u32 res = 0;
+  PWM_Cmd(LPC_PWM1, ENABLE);
+}
 
-  switch( op )
-  {
-    case PLATFORM_PWM_OP_START:
-      PWM_Cmd(LPC_PWM1, ENABLE);
-      break;
-
-    case PLATFORM_PWM_OP_STOP:
-      PWM_Cmd(LPC_PWM1, DISABLE);
-      break;
-
-    case PLATFORM_PWM_OP_SET_CLOCK:
-      res = platform_pwm_set_clock( id, data );
-      break;
-
-    case PLATFORM_PWM_OP_GET_CLOCK:
-      res = platform_pwm_get_clock( id );
-      break;
-  }
-
-  return res;
+void platform_pwm_stop( unsigned id )
+{
+  PWM_Cmd(LPC_PWM1, DISABLE);
 }
 
 // ****************************************************************************
diff --git a/src/platform/lpc17xx/platform_conf.h b/src/platform/lpc17xx/platform_conf.h
index 0cd935be..1e96b75a 100644
--- a/src/platform/lpc17xx/platform_conf.h
+++ b/src/platform/lpc17xx/platform_conf.h
@@ -5,6 +5,7 @@
 
 #include "auxmods.h"
 #include "stacks.h"
+#include "type.h"
 
 // *****************************************************************************
 // Define here what components you want for this platform
@@ -18,12 +19,13 @@
 #define BUILD_SEMIFS
 #define BUILD_RPC
 
+#define PLATFORM_HAS_SYSTIMER
+
 // *****************************************************************************
 // UART/Timer IDs configuration data (used in main.c)
 
 #define CON_UART_ID           0
 #define CON_UART_SPEED        115200
-#define CON_TIMER_ID          0
 #define TERM_LINES            25
 #define TERM_COLS             80
 
@@ -102,10 +104,10 @@
 
 // RPC  
 #define RPC_UART_ID           CON_UART_ID
-#define RPC_TIMER_ID          CON_TIMER_ID
 
 // CPU frequency (needed by the CPU module, 0 if not used)
-#define CPU_FREQUENCY         100000000
+u32 mbed_get_cpu_frequency();
+#define CPU_FREQUENCY         mbed_get_cpu_frequency()
 
 // PIO prefix ('0' for P0, P1, ... or 'A' for PA, PB, ...)
 #define PIO_PREFIX            '0'
diff --git a/src/platform/lpc24xx/platform.c b/src/platform/lpc24xx/platform.c
index 935be487..41b265de 100644
--- a/src/platform/lpc24xx/platform.c
+++ b/src/platform/lpc24xx/platform.c
@@ -73,8 +73,8 @@ static void platform_setup_extmem()
   volatile unsigned int i;
   volatile DWORD wtemp;
 
-  EMC_CTRL = 0x00000001;		/*Disable Address mirror*/
-  PCONP   |= 0x00000800;		/* Turn On EMC PCLK */
+  EMC_CTRL = 0x00000001;                /*Disable Address mirror*/
+  PCONP   |= 0x00000800;                /* Turn On EMC PCLK */
   PINSEL4  = 0x50000000;
   PINSEL5  = 0x05050555;
   PINSEL6  = 0x55555555;
@@ -387,7 +387,7 @@ void platform_s_uart_send( unsigned id, u8 data )
   *UxTHR = data;
 }
 
-int platform_s_uart_recv( unsigned id, s32 timeout )
+int platform_s_uart_recv( unsigned id, timer_data_type timeout )
 {
   PREG UxLSR = ( PREG )uart_lsr[ id ];
   PREG UxRBR = ( PREG )uart_rbr[ id ];
@@ -452,14 +452,13 @@ static u32 platform_timer_set_clock( unsigned id, u32 clock )
   return Fpclk / div;
 }
 
-#if VTMR_NUM_TIMERS > 0
 static void int_handler_tmr()
 {
   T3IR = 1; // clear interrupt
-  cmn_virtual_timer_cb();
+  cmn_virtual_timer_cb(); // handle virtual timers if they're present
+  cmn_systimer_periodic(); // handle the system timer
   VICVectAddr = 0; // ACK interrupt
 }
-#endif
 
 // Helper function: setup timers
 static void platform_setup_timers()
@@ -474,9 +473,13 @@ static void platform_setup_timers()
     *TxTCR = 0;
     platform_timer_set_clock( i, 1000000ULL );
   }
-#if VTMR_NUM_TIMERS > 0
-  // Setup virtual timers here
-  // Timer 3 is allocated for virtual timers and nothing else in this case
+
+  // Setup system timer
+  cmn_systimer_set_base_freq( 1000000 );
+  cmn_systimer_set_interrupt_freq( VTMR_FREQ_HZ );
+
+  // Setup virtual timers / system timer here
+  // Timer 3 is allocated for virtual timers and the system timer, nothing else
   T3TCR = TMR_RESET;
   T3MR0 = 1000000ULL / VTMR_FREQ_HZ - 1;
   T3IR = 0xFF;
@@ -486,10 +489,9 @@ static void platform_setup_timers()
   platform_cpu_set_global_interrupts( PLATFORM_CPU_ENABLE );
   // Start timer
   T3TCR = TMR_ENABLE;
-#endif
 }
 
-void platform_s_timer_delay( unsigned id, u32 delay_us )
+void platform_s_timer_delay( unsigned id, timer_data_type delay_us )
 {
   PREG TxTCR = ( PREG )tmr_tcr[ id ];
   PREG TxTC = ( PREG )tmr_tc[ id ];
@@ -501,7 +503,7 @@ void platform_s_timer_delay( unsigned id, u32 delay_us )
   while( *TxTC < last );
 }
       
-u32 platform_s_timer_op( unsigned id, int op, u32 data )
+timer_data_type platform_s_timer_op( unsigned id, int op, timer_data_type data )
 {
   u32 res = 0;
   PREG TxTCR = ( PREG )tmr_tcr[ id ];
@@ -518,14 +520,6 @@ u32 platform_s_timer_op( unsigned id, int op, u32 data )
       res = *TxTC;
       break;
 
-    case PLATFORM_TIMER_OP_GET_MAX_DELAY:
-      res = platform_timer_get_diff_us( id, 0, 0xFFFFFFFF );
-      break;
-      
-    case PLATFORM_TIMER_OP_GET_MIN_DELAY:
-      res = platform_timer_get_diff_us( id, 0, 1 );
-      break;      
-      
     case PLATFORM_TIMER_OP_SET_CLOCK:
       res = platform_timer_set_clock( id, data );
       break;
@@ -533,15 +527,39 @@ u32 platform_s_timer_op( unsigned id, int op, u32 data )
     case PLATFORM_TIMER_OP_GET_CLOCK:
       res = platform_timer_get_clock( id );
       break;
+
+    case PLATFORM_TIMER_OP_GET_MAX_CNT:
+      res = 0xFFFFFFFF;
+      break;
   }
   return res;
 }
 
-int platform_s_timer_set_match_int( unsigned id, u32 period_us, int type )
+int platform_s_timer_set_match_int( unsigned id, timer_data_type period_us, int type )
 {
   return PLATFORM_TIMER_INT_INVALID_ID;
 }
 
+u64 platform_timer_sys_raw_read()
+{
+  return T3TC;
+}
+
+void platform_timer_sys_disable_int()
+{
+  T3MCR = 0x02; // clear on match, no interrupt
+}
+
+void platform_timer_sys_enable_int()
+{
+  T3MCR = 0x03; // interrupt on match with MR0 and clear on match
+}
+
+timer_data_type platform_timer_read_sys()
+{
+  return cmn_systimer_get();
+}
+
 // *****************************************************************************
 // ADC specific functions and variables
 
@@ -590,7 +608,7 @@ static void adc_int_handler()
   if ( dreg_t & ( 1UL << 31 ) )
   { 
     d->sample_buf[ d->seq_ctr ] = ( u16 )( ( dreg_t >> 6 ) & 0x3FF );
-    AD0CR &= 0xF8FFFF00;	// stop ADC, disable channels
+    AD0CR &= 0xF8FFFF00;        // stop ADC, disable channels
     s->value_fresh = 1;
             
     if ( s->logsmoothlen > 0 && s->smooth_ready == 0)
@@ -663,7 +681,7 @@ static void platform_setup_adcs()
 
 
 // NOTE: On this platform, there is only one ADC, clock settings apply to the whole device
-u32 platform_adc_setclock( unsigned id, u32 frequency )
+u32 platform_adc_set_clock( unsigned id, u32 frequency )
 {
   elua_adc_dev_state *d = adc_get_dev_state( 0 );
 
@@ -799,8 +817,8 @@ enum
   PWM_ENABLE_6 = 1 << 14,
 };
 
-// Helper function: get timer clock
-static u32 platform_pwm_get_clock( unsigned id )
+// Get timer clock
+u32 platform_pwm_get_clock( unsigned id )
 {
   unsigned pwmid = id / 6;
   PREG PWMxPR = ( PREG )pwm_pr[ pwmid ];
@@ -808,8 +826,8 @@ static u32 platform_pwm_get_clock( unsigned id )
   return Fpclk / ( *PWMxPR + 1 );
 }
 
-// Helper function: set timer clock
-static u32 platform_pwm_set_clock( unsigned id, u32 clock )
+// Set timer clock
+u32 platform_pwm_set_clock( unsigned id, u32 clock )
 {
   u32 div = Fpclk / clock, prevtc;
   unsigned pwmid = id / 6;
@@ -860,34 +878,22 @@ u32 platform_pwm_setup( unsigned id, u32 frequency, unsigned duty )
   return platform_pwm_get_clock( id ) / divisor;
 }
 
-u32 platform_pwm_op( unsigned id, int op, u32 data )
+void platform_pwm_start( unsigned id )
 {
-  u32 res = 0;
   unsigned pwmid = id / 6;
   PREG PWMxTCR = ( PREG )pwm_tcr[ pwmid ];
   PREG PWMxPCR = ( PREG )pwm_pcr[ pwmid ];
 
-  switch( op )
-  {
-    case PLATFORM_PWM_OP_START:
-      *PWMxPCR = PWM_ENABLE_1 | PWM_ENABLE_2 | PWM_ENABLE_3 | PWM_ENABLE_4 | PWM_ENABLE_5 | PWM_ENABLE_6;
-      *PWMxTCR = PWM_ENABLE | PWM_MODE;
-      break;
-
-    case PLATFORM_PWM_OP_STOP:
-      *PWMxPCR = 0;   
-      *PWMxTCR = PWM_RESET;
-      break;
-
-    case PLATFORM_PWM_OP_SET_CLOCK:
-      res = platform_pwm_set_clock( id, data );
-      break;
-
-    case PLATFORM_PWM_OP_GET_CLOCK:
-      res = platform_pwm_get_clock( id );
-      break;
-  }
-
-  return res;
+  *PWMxPCR = PWM_ENABLE_1 | PWM_ENABLE_2 | PWM_ENABLE_3 | PWM_ENABLE_4 | PWM_ENABLE_5 | PWM_ENABLE_6;
+  *PWMxTCR = PWM_ENABLE | PWM_MODE;
 }
 
+void platform_pwm_stop( unsigned id )
+{
+  unsigned pwmid = id / 6;
+  PREG PWMxTCR = ( PREG )pwm_tcr[ pwmid ];
+  PREG PWMxPCR = ( PREG )pwm_pcr[ pwmid ];
+
+  *PWMxPCR = 0;   
+  *PWMxTCR = PWM_RESET;
+}
diff --git a/src/platform/lpc24xx/platform_conf.h b/src/platform/lpc24xx/platform_conf.h
index 7c46ef39..d39eab91 100644
--- a/src/platform/lpc24xx/platform_conf.h
+++ b/src/platform/lpc24xx/platform_conf.h
@@ -20,18 +20,19 @@
 #define BUILD_CON_GENERIC
 #define BUILD_ADC
 #define BUILD_RPC
-#define BUILD_RFS
-#define BUILD_SERMUX
+//#define BUILD_RFS
+//#define BUILD_SERMUX
 #define BUILD_LUA_INT_HANDLERS
 #define BUILD_C_INT_HANDLERS
 
+#define PLATFORM_HAS_SYSTIMER
+
 // *****************************************************************************
 // UART/Timer IDs configuration data (used in main.c)
 
-#define CON_UART_ID           ( SERMUX_SERVICE_ID_FIRST + 1 )
-//#define CON_UART_ID           0
+//#define CON_UART_ID           ( SERMUX_SERVICE_ID_FIRST + 1 )
+#define CON_UART_ID           0
 #define CON_UART_SPEED        115200
-#define CON_TIMER_ID          0
 #define TERM_LINES            25
 #define TERM_COLS             80
 
@@ -75,6 +76,7 @@
 
 // Virtual timers (0 if not used)
 #define VTMR_NUM_TIMERS       4
+// NOTE: DON'T define VTMR_FREQ_HZ as 0!
 #define VTMR_FREQ_HZ          4
 
 // Number of resources (0 if not available/not implemented)
@@ -108,10 +110,9 @@
 
 // RPC boot options
 #define RPC_UART_ID           CON_UART_ID
-#define RPC_TIMER_ID          CON_TIMER_ID
 #define RPC_UART_SPEED        CON_UART_SPEED
 
-// CPU frequency (needed by the CPU module, 0 if not used)
+// CPU frequency (needed by the CPU module and MMCFS code, 0 if not used)
 #define CPU_FREQUENCY         Fcclk
 
 // PIO prefix ('0' for P0, P1, ... or 'A' for PA, PB, ...)
@@ -123,9 +124,9 @@
 #define PIO_PINS_PER_PORT     32
 
 // Remote file system data
+/*
 #define RFS_BUFFER_SIZE       BUF_SIZE_512
 #define RFS_UART_ID           ( SERMUX_SERVICE_ID_FIRST )
-#define RFS_TIMER_ID          0
 #define RFS_TIMEOUT           100000
 #define RFS_UART_SPEED        115200
 
@@ -133,6 +134,7 @@
 #define SERMUX_PHYS_SPEED     115200
 #define SERMUX_NUM_VUART      2
 #define SERMUX_BUFFER_SIZES   { RFS_BUFFER_SIZE, CON_BUF_SIZE }
+*/
 
 // Allocator data: define your free memory zones here in two arrays
 // (start address and end address)
@@ -154,7 +156,7 @@
 // *****************************************************************************
 // CPU constants that should be exposed to the eLua "cpu" module
 
-#define PINSEL_BASE_ADDR	      0xE002C000
+#define PINSEL_BASE_ADDR      0xE002C000
 #define IO_PINSEL0            ( PINSEL_BASE_ADDR + 0x00 )
 #define IO_PINSEL1            ( PINSEL_BASE_ADDR + 0x04 )
 #define IO_PINSEL2            ( PINSEL_BASE_ADDR + 0x08 )
diff --git a/src/platform/lpc288x/platform.c b/src/platform/lpc288x/platform.c
index c65a037a..e9944570 100644
--- a/src/platform/lpc288x/platform.c
+++ b/src/platform/lpc288x/platform.c
@@ -118,7 +118,7 @@ void platform_s_uart_send( unsigned id, u8 data )
   uart_write( data );
 }
 
-int platform_s_uart_recv( unsigned id, s32 timeout )
+int platform_s_uart_recv( unsigned id, timer_data_type timeout )
 {
   if( timeout == 0 )
   {
@@ -160,7 +160,7 @@ static u32 platform_timer_set_clock( unsigned id, u32 clock )
   return MAIN_CLOCK / tmr_prescale[ mini ];
 }
 
-void platform_s_timer_delay( unsigned id, u32 delay_us )
+void platform_s_timer_delay( unsigned id, timer_data_type delay_us )
 {
   u32 freq;
   u64 final;
@@ -177,7 +177,7 @@ void platform_s_timer_delay( unsigned id, u32 delay_us )
   while( ( INT_PENDING & mask ) == 0 );
 }
       
-u32 platform_s_timer_op( unsigned id, int op, u32 data )
+timer_data_type platform_s_timer_op( unsigned id, int op, timer_data_type data )
 {
   u32 res = 0;
   
@@ -194,14 +194,6 @@ u32 platform_s_timer_op( unsigned id, int op, u32 data )
       res = *tmr_value[ id ];
       break;
       
-    case PLATFORM_TIMER_OP_GET_MAX_DELAY:
-      res = platform_timer_get_diff_us( id, 0, 0xFFFFFFFF );
-      break;
-      
-    case PLATFORM_TIMER_OP_GET_MIN_DELAY:
-      res = platform_timer_get_diff_us( id, 0, 1 );
-      break;      
-      
     case PLATFORM_TIMER_OP_SET_CLOCK:
       res = platform_timer_set_clock( id, data );
       break;
@@ -209,6 +201,10 @@ u32 platform_s_timer_op( unsigned id, int op, u32 data )
     case PLATFORM_TIMER_OP_GET_CLOCK:
       res = platform_timer_get_clock( id );
       break;
+
+    case PLATFORM_TIMER_OP_GET_MAX_CNT:
+      res = 0xFFFFFFFF;
+      break;
   }
   return res;
 }
diff --git a/src/platform/lpc288x/platform_conf.h b/src/platform/lpc288x/platform_conf.h
index 773fb22c..a559c1bc 100644
--- a/src/platform/lpc288x/platform_conf.h
+++ b/src/platform/lpc288x/platform_conf.h
@@ -46,7 +46,7 @@
 #define RPC_TIMER_ID          CON_TIMER_ID
 #define RPC_UART_SPEED        CON_UART_SPEED
 
-// CPU frequency (needed by the CPU module, 0 if not used)
+// CPU frequency (needed by the CPU module and MMCFS code, 0 if not used)
 #define CPU_FREQUENCY         Fcclk
 
 // PIO prefix ('0' for P0, P1, ... or 'A' for PA, PB, ...)
diff --git a/src/platform/sim/host.c b/src/platform/sim/host.c
index 561c784c..85403ff0 100644
--- a/src/platform/sim/host.c
+++ b/src/platform/sim/host.c
@@ -1,11 +1,12 @@
 #include "host.h"
 
-#define __NR_read     3
-#define __NR_write    4
-#define __NR_mmap2    192
-#define __NR_exit     1
-#define __NR_open     5 
-#define __NR_close    6
+#define __NR_read             3
+#define __NR_write            4
+#define __NR_mmap2            192
+#define __NR_exit             1
+#define __NR_open             5
+#define __NR_close            6
+#define __NR_gettimeofday     78
 
 int host_errno = 0;
 
@@ -27,6 +28,16 @@ __asm__ volatile ("int $0x80" \
 __syscall_return(type,__res); \
 }
 
+#define _syscall2(type,name,type1,arg1,type2,arg2) \
+type host_##name(type1 arg1,type2 arg2) \
+{ \
+long __res; \
+__asm__ volatile ("int $0x80" \
+        : "=a" (__res) \
+        : "0" (__NR_##name),"b" ((long)(arg1)),"c" ((long)(arg2))); \
+__syscall_return(type,__res); \
+}
+
 
 #define _syscall3(type,name,type1,arg1,type2,arg2,type3,arg3) \
 type host_##name(type1 arg1,type2 arg2,type3 arg3) \
@@ -58,4 +69,5 @@ _syscall3(int, open, const char*, pathname, int, flags, mode_t, mode);
 _syscall6(void *,mmap2, void *,addr, size_t, length, int, prot, int, flags, int, fd, off_t, offset);
 _syscall1(void, exit, int, status);
 _syscall1(int, close, int, status);
+_syscall2(int, gettimeofday, struct timeval*, tv, struct timezone*, tz);
 
diff --git a/src/platform/sim/host.h b/src/platform/sim/host.h
index 7913677d..62369136 100644
--- a/src/platform/sim/host.h
+++ b/src/platform/sim/host.h
@@ -5,6 +5,7 @@
 
 #include 
 #include 
+#include 
 
 extern int host_errno;
 
@@ -30,6 +31,7 @@ int host_close( int fd );
 #define MAP_FAILED (void *)(-1)
 
 void *host_mmap2(void *addr, size_t length, int prot, int flags, int fd, off_t pgoffset);
+int host_gettimeofday( struct timeval *tv, struct timezone *tz );
 void host_exit(int status);
 
 #endif // _HOST_H
diff --git a/src/platform/sim/hostif.h b/src/platform/sim/hostif.h
index 9b0d0e45..8397748e 100644
--- a/src/platform/sim/hostif.h
+++ b/src/platform/sim/hostif.h
@@ -3,6 +3,8 @@
 #ifndef __HOSTIO_H__
 #define __HOSTIO_H__
 
+#include "type.h"
+
 // Write a single character out to the screen.
 void hostif_putc(char c);
 
@@ -30,5 +32,8 @@ int hostif_write( int fd, const void *buf, unsigned count );
 // Close
 int hostif_close( int fd );
 
+// Get time
+s64 hostif_gettime();
+
 #endif // __HOSTIO_H__
 
diff --git a/src/platform/sim/hostif_linux.c b/src/platform/sim/hostif_linux.c
index 2b385f2a..d12f7907 100644
--- a/src/platform/sim/hostif_linux.c
+++ b/src/platform/sim/hostif_linux.c
@@ -3,6 +3,7 @@
 #include 
 #include 
 #include 
+#include 
 #include "term.h"
 #include "host.h"
 #include "hostif.h"
@@ -64,3 +65,11 @@ int hostif_close( int fd )
   return host_close( fd );
 }
 
+s64 hostif_gettime()
+{
+  struct timeval tv;
+
+  host_gettimeofday( &tv, NULL );
+  return ( s64 )tv.tv_sec * 1000000 + tv.tv_usec;
+}
+
diff --git a/src/platform/sim/platform.c b/src/platform/sim/platform.c
index 2b03c729..fee8f3c8 100644
--- a/src/platform/sim/platform.c
+++ b/src/platform/sim/platform.c
@@ -69,7 +69,7 @@ static void scr_write( int fd, char c )
   hostif_putc( c );
 }
 
-static int kb_read( s32 to )
+static int kb_read( timer_data_type to )
 {
   int res;
 
@@ -90,18 +90,18 @@ void *memory_end_address = 0;
 
 void platform_ll_init()
 {
-	// Initialise heap memory region.
-	memory_start_address = hostif_getmem( MEM_LENGTH ); 
-	memory_end_address = memory_start_address + MEM_LENGTH;
+  // Initialise heap memory region.
+  memory_start_address = hostif_getmem( MEM_LENGTH ); 
+  memory_end_address = memory_start_address + MEM_LENGTH;
 }
 
 int platform_init()
 { 
-	if( memory_start_address == NULL ) 
+  if( memory_start_address == NULL ) 
   {
     hostif_putstr( "platform_init(): mmap failed\n" );
-		return PLATFORM_ERR;
-	}
+    return PLATFORM_ERR;
+  }
 
   // Set the std input/output functions
   // Set the send/recv functions                          
@@ -132,7 +132,7 @@ void platform_s_uart_send( unsigned id, u8 data )
 {
 }
 
-int platform_s_uart_recv( unsigned id, s32 timeout )
+int platform_s_uart_recv( unsigned id, timer_data_type timeout )
 {
   return -1;
 }
@@ -145,15 +145,20 @@ int platform_s_uart_set_flow_control( unsigned id, int type )
 // ****************************************************************************
 // "Dummy" timer functions
 
-void platform_s_timer_delay( unsigned id, u32 delay_us )
+void platform_s_timer_delay( unsigned id, timer_data_type delay_us )
 {
 }
 
-u32 platform_s_timer_op( unsigned id, int op, u32 data )
+timer_data_type platform_s_timer_op( unsigned id, int op, timer_data_type data )
 {
   return 0;
 }
 
+timer_data_type platform_timer_read_sys()
+{
+  return hostif_gettime();
+}
+
 // ****************************************************************************
 // "Dummy" CPU functions
 
diff --git a/src/platform/sim/platform_conf.h b/src/platform/sim/platform_conf.h
index ba85a67c..d1531285 100644
--- a/src/platform/sim/platform_conf.h
+++ b/src/platform/sim/platform_conf.h
@@ -20,6 +20,8 @@
 #define TERM_LINES    25
 #define TERM_COLS     80
 
+#define PLATFORM_HAS_SYSTIMER
+
 // *****************************************************************************
 // Auxiliary libraries that will be compiled for this platform
 
@@ -27,12 +29,12 @@
   _ROM( AUXLIB_PD, luaopen_pd, pd_map )\
   _ROM( LUA_MATHLIBNAME, luaopen_math, math_map )\
   _ROM( AUXLIB_TERM, luaopen_term, term_map )\
-  _ROM( AUXLIB_ELUA, luaopen_elua, elua_map )
+  _ROM( AUXLIB_ELUA, luaopen_elua, elua_map )\
+  _ROM( AUXLIB_TMR, luaopen_tmr, tmr_map )\
 
 // Bogus defines for common.c
 #define CON_UART_ID           0
 #define CON_UART_SPEED        0
-#define CON_TIMER_ID          0
 
 // *****************************************************************************
 // Configuration data
@@ -49,7 +51,7 @@
 #define NUM_ADC               0
 #define NUM_CAN               0
 
-// CPU frequency (needed by the CPU module, 0 if not used)
+// CPU frequency (needed by the CPU module and MMCFS code, 0 if not used)
 #define CPU_FREQUENCY         0
 
 // PIO prefix ('0' for P0, P1, ... or 'A' for PA, PB, ...)
diff --git a/src/platform/stm32/lua_lcd.c b/src/platform/stm32/lua_lcd.c
index 498d96b7..cc8add7a 100644
--- a/src/platform/stm32/lua_lcd.c
+++ b/src/platform/stm32/lua_lcd.c
@@ -17,60 +17,60 @@
 
 static int lcd_init(lua_State * L)
 {
-	STM3210E_LCD_Init();
+  STM3210E_LCD_Init();
 
-	return 0;
+  return 0;
 }
 
 static int lcd_setforecolor(lua_State * L)
 {
-	u16 color = luaL_checkint(L, 1);
+  u16 color = luaL_checkint(L, 1);
 
-	LCD_SetTextColor(color);
+  LCD_SetTextColor(color);
 
-	return 0;
+  return 0;
 }
 
 static int lcd_setbackcolor(lua_State * L)
 {
-	u16 color = luaL_checkint(L, 1);
+  u16 color = luaL_checkint(L, 1);
 
-	LCD_SetBackColor(color);
+  LCD_SetBackColor(color);
 
-	return 0;
+  return 0;
 }
 
 static int lcd_clear(lua_State * L)
 {
-	u16 color;
+  u16 color;
 
-	if (lua_gettop(L) == 0)
-		color = 0x0000;
-	else
-		color = luaL_checkint(L, 1);
+  if (lua_gettop(L) == 0)
+    color = 0x0000;
+  else
+    color = luaL_checkint(L, 1);
 
-	LCD_Clear(color);
+  LCD_Clear(color);
 
-	return 0;
+  return 0;
 }
 
 static int lcd_clearline(lua_State * L)
 {
-	u8 line = luaL_checkint(L, 1);
+  u8 line = luaL_checkint(L, 1);
 
-	LCD_ClearLine(line);
+  LCD_ClearLine(line);
 
-	return 0;
+  return 0;
 }
 
 static int lcd_print(lua_State * L)
 {
-	u8   line = luaL_checkint(L, 1);
-	u8 * text = (u8 *)luaL_checkstring(L, 2);
+  u8   line = luaL_checkint(L, 1);
+  u8 * text = (u8 *)luaL_checkstring(L, 2);
 
-	LCD_DisplayStringLine(line, text);
+  LCD_DisplayStringLine(line, text);
 
-	return 0;
+  return 0;
 }
 
 static int lcd_mt_index( lua_State *L )
@@ -88,17 +88,17 @@ static int lcd_mt_index( lua_State *L )
 #include "lrodefs.h"
 const LUA_REG_TYPE lcd_map[] =
 {
-	{ LSTRKEY( "init" ), LFUNCVAL( lcd_init ) },
-	{ LSTRKEY( "setforecolor" ), LFUNCVAL( lcd_setforecolor ) },
-	{ LSTRKEY( "setbackcolor" ), LFUNCVAL( lcd_setbackcolor ) },
-	{ LSTRKEY( "clear" ), LFUNCVAL( lcd_clear ) },
-	{ LSTRKEY( "clearline" ), LFUNCVAL( lcd_clearline ) },
-	{ LSTRKEY( "print" ), LFUNCVAL( lcd_print ) },
+  { LSTRKEY( "init" ), LFUNCVAL( lcd_init ) },
+  { LSTRKEY( "setforecolor" ), LFUNCVAL( lcd_setforecolor ) },
+  { LSTRKEY( "setbackcolor" ), LFUNCVAL( lcd_setbackcolor ) },
+  { LSTRKEY( "clear" ), LFUNCVAL( lcd_clear ) },
+  { LSTRKEY( "clearline" ), LFUNCVAL( lcd_clearline ) },
+  { LSTRKEY( "print" ), LFUNCVAL( lcd_print ) },
 #if LUA_OPTIMIZE_MEMORY > 0
   { LSTRKEY( "__metatable" ), LROVAL( lcd_map ) },
 #endif
   { LSTRKEY( "__index" ), LFUNCVAL( lcd_mt_index ) },
-	{ LNILKEY, LNILVAL }
+  { LNILKEY, LNILVAL }
 };
 
 LUALIB_API int luaopen_lcd(lua_State * L)
diff --git a/src/platform/stm32/platform.c b/src/platform/stm32/platform.c
index cea769d8..06d49e5e 100755
--- a/src/platform/stm32/platform.c
+++ b/src/platform/stm32/platform.c
@@ -82,6 +82,10 @@ int platform_init()
 
   // Setup CANs
   cans_init();
+
+  // Setup system timer
+  cmn_systimer_set_base_freq( HCLK );
+  cmn_systimer_set_interrupt_freq( SYSTICKHZ );
   
   // Enable SysTick
   if ( SysTick_Config( HCLK / SYSTICKHZ ) )
@@ -638,7 +642,7 @@ void platform_s_uart_send( unsigned id, u8 data )
   USART_SendData(stm32_usart[id], data);
 }
 
-int platform_s_uart_recv( unsigned id, s32 timeout )
+int platform_s_uart_recv( unsigned id, timer_data_type timeout )
 {
   if( timeout == 0 )
   {
@@ -692,22 +696,23 @@ int platform_s_uart_set_flow_control( unsigned id, int type )
 // ****************************************************************************
 // Timers
 
+u8 stm32_timer_int_periodic_flag[ NUM_PHYS_TIMER ];
+
 // We leave out TIM6/TIM for now, as they are dedicated
-static TIM_TypeDef * const timer[] = { TIM1, TIM2, TIM3, TIM4, TIM5 };
+TIM_TypeDef * const timer[] = { TIM1, TIM2, TIM3, TIM4, TIM5 };
 #define TIM_GET_PRESCALE( id ) ( ( id ) == 0 || ( id ) == 5 ? ( PCLK2_DIV ) : ( PCLK1_DIV ) )
 #define TIM_GET_BASE_CLK( id ) ( TIM_GET_PRESCALE( id ) == 1 ? ( HCLK / TIM_GET_PRESCALE( id ) ) : ( HCLK / ( TIM_GET_PRESCALE( id ) / 2 ) ) )
 #define TIM_STARTUP_CLOCK       50000
 
-static u32 timer_set_clock( unsigned id, u32 clock );
+static u32 platform_timer_set_clock( unsigned id, u32 clock );
 
 void SysTick_Handler( void )
 {
   // Handle virtual timers
   cmn_virtual_timer_cb();
 
-#ifdef BUILD_MMCFS
-  disk_timerproc();
-#endif
+  // Handle system timer call
+  cmn_systimer_periodic();
 }
 
 static void timers_init()
@@ -723,17 +728,17 @@ static void timers_init()
 
   // Configure timers
   for( i = 0; i < NUM_TIMER; i ++ )
-    timer_set_clock( i, TIM_STARTUP_CLOCK );
+    platform_timer_set_clock( i, TIM_STARTUP_CLOCK );
 }
 
-static u32 timer_get_clock( unsigned id )
+static u32 platform_timer_get_clock( unsigned id )
 {
   TIM_TypeDef* ptimer = timer[ id ];
 
   return TIM_GET_BASE_CLK( id ) / ( TIM_GetPrescaler( ptimer ) + 1 );
 }
 
-static u32 timer_set_clock( unsigned id, u32 clock )
+static u32 platform_timer_set_clock( unsigned id, u32 clock )
 {
   TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
   TIM_TypeDef *ptimer = timer[ id ];
@@ -750,19 +755,19 @@ static u32 timer_set_clock( unsigned id, u32 clock )
   return TIM_GET_BASE_CLK( id ) / ( pre + 1 );
 }
 
-void platform_s_timer_delay( unsigned id, u32 delay_us )
+void platform_s_timer_delay( unsigned id, timer_data_type delay_us )
 {
   TIM_TypeDef *ptimer = timer[ id ];
   volatile unsigned dummy;
   timer_data_type final;
 
-  final = ( ( u64 )delay_us * timer_get_clock( id ) ) / 1000000;
+  final = ( ( u64 )delay_us * platform_timer_get_clock( id ) ) / 1000000;
   TIM_SetCounter( ptimer, 0 );
   for( dummy = 0; dummy < 200; dummy ++ );
   while( TIM_GetCounter( ptimer ) < final );
 }
 
-u32 platform_s_timer_op( unsigned id, int op, u32 data )
+timer_data_type platform_s_timer_op( unsigned id, int op, timer_data_type data )
 {
   u32 res = 0;
   TIM_TypeDef *ptimer = timer[ id ];
@@ -780,29 +785,91 @@ u32 platform_s_timer_op( unsigned id, int op, u32 data )
       res = TIM_GetCounter( ptimer );
       break;
 
-    case PLATFORM_TIMER_OP_GET_MAX_DELAY:
-      res = platform_timer_get_diff_us( id, 0, 0xFFFF );
-      break;
-
-    case PLATFORM_TIMER_OP_GET_MIN_DELAY:
-      res = platform_timer_get_diff_us( id, 0, 1 );
-      break;
-
     case PLATFORM_TIMER_OP_SET_CLOCK:
-      res = timer_set_clock( id, data );
+      res = platform_timer_set_clock( id, data );
       break;
 
     case PLATFORM_TIMER_OP_GET_CLOCK:
-      res = timer_get_clock( id );
+      res = platform_timer_get_clock( id );
       break;
 
+    case PLATFORM_TIMER_OP_GET_MAX_CNT:
+      res = 0xFFFF;
+      break;
   }
   return res;
 }
 
-int platform_s_timer_set_match_int( unsigned id, u32 period_us, int type )
+int platform_s_timer_set_match_int( unsigned id, timer_data_type period_us, int type )
 {
-  return PLATFORM_TIMER_INT_INVALID_ID;
+  TIM_TypeDef* base = ( TIM_TypeDef* )timer[ id ];
+  u32 period, prescaler, freq;
+  timer_data_type final;
+  TIM_OCInitTypeDef  TIM_OCInitStructure;
+
+  if( period_us == 0 )
+  {
+    TIM_ITConfig( base, TIM_IT_CC1, DISABLE );
+    base->CR1 = 0; // Why are we doing this?
+    base->CR2 = 0;
+    return PLATFORM_TIMER_INT_OK;
+  }
+
+  period = ( ( u64 )TIM_GET_BASE_CLK( id ) * period_us ) / 1000000;
+    
+  prescaler = ( period / 0x10000 ) + 1;
+  period /= prescaler;
+
+  platform_timer_set_clock( id, TIM_GET_BASE_CLK( id  ) / prescaler );
+  freq = platform_timer_get_clock( id );
+  final = ( ( u64 )period_us * freq ) / 1000000;
+
+  if( final == 0 )
+    return PLATFORM_TIMER_INT_TOO_SHORT;
+  if( final > 0xFFFF )
+    return PLATFORM_TIMER_INT_TOO_LONG;
+
+  TIM_Cmd( base, DISABLE );
+
+  TIM_OCStructInit( &TIM_OCInitStructure );
+  TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_Timing;
+  TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
+  TIM_OCInitStructure.TIM_Pulse = final;
+  TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;
+  TIM_OC1Init( base, &TIM_OCInitStructure );
+  
+  // Patch timer configuration to reload when period is reached
+  TIM_SetAutoreload( base, final );
+
+  TIM_OC1PreloadConfig( base, TIM_OCPreload_Enable );
+
+  stm32_timer_int_periodic_flag[ id ] = type;
+  
+  TIM_SetCounter( base, 0 );
+  TIM_Cmd( base, ENABLE );
+  //TIM_ITConfig( base, TIM_IT_CC1, ENABLE );
+
+  return PLATFORM_TIMER_INT_OK;
+}
+
+u64 platform_timer_sys_raw_read()
+{
+  return SysTick->LOAD - SysTick->VAL;
+}
+
+void platform_timer_sys_disable_int()
+{
+  SysTick->CTRL &= ~( 1 << SYSTICK_TICKINT );
+}
+
+void platform_timer_sys_enable_int()
+{
+  SysTick->CTRL |= 1 << SYSTICK_TICKINT;
+}
+
+timer_data_type platform_timer_read_sys()
+{
+  return cmn_systimer_get();
 }
 
 // ****************************************************************************
@@ -844,16 +911,17 @@ static void pwms_init()
   // 
 }
 
-// Helper function: return the PWM clock
-// NOTE: Can't find a function to query for the period set for the timer, therefore using the struct.
-//       This may require adjustment if driver libraries are updated.
-static u32 platform_pwm_get_clock()
+// Return the PWM clock
+// NOTE: Can't find a function to query for the period set for the timer,
+// therefore using the struct.
+// This may require adjustment if driver libraries are updated.
+u32 platform_pwm_get_clock( unsigned id )
 {
   return ( ( TIM_GET_BASE_CLK( PWM_TIMER_ID ) / ( TIM_GetPrescaler( PWM_TIMER_NAME ) + 1 ) ) / ( PWM_TIMER_NAME->ARR + 1 ) );
 }
 
-// Helper function: set the PWM clock
-static u32 platform_pwm_set_clock( u32 clock )
+// Set the PWM clock
+u32 platform_pwm_set_clock( unsigned id, u32 clock )
 {
   TIM_TimeBaseInitTypeDef  TIM_TimeBaseStructure;
   TIM_TypeDef* ptimer = PWM_TIMER_NAME;
@@ -872,7 +940,7 @@ static u32 platform_pwm_set_clock( u32 clock )
   TIM_TimeBaseStructure.TIM_RepetitionCounter = 0x0000;
   TIM_TimeBaseInit( ptimer, &TIM_TimeBaseStructure );
     
-  return platform_pwm_get_clock();
+  return platform_pwm_get_clock( id );
 }
 
 u32 platform_pwm_setup( unsigned id, u32 frequency, unsigned duty )
@@ -891,7 +959,7 @@ u32 platform_pwm_setup( unsigned id, u32 frequency, unsigned duty )
   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
   GPIO_Init(GPIOC, &GPIO_InitStructure);
   
-  clock = platform_pwm_set_clock( frequency );
+  clock = platform_pwm_set_clock( id, frequency );
   TIM_ARRPreloadConfig( ptimer, ENABLE );
   
   /* PWM Mode configuration */  
@@ -931,30 +999,14 @@ u32 platform_pwm_setup( unsigned id, u32 frequency, unsigned duty )
   return clock;
 }
 
-u32 platform_pwm_op( unsigned id, int op, u32 data )
+void platform_pwm_start( unsigned id )
 {
-  u32 res = 0;
+  PWM_TIMER_NAME->CCER |= ( ( u16 )1 << 4 * id );
+}
 
-  switch( op )
-  {
-    case PLATFORM_PWM_OP_SET_CLOCK:
-      res = platform_pwm_set_clock( data );
-      break;
-
-    case PLATFORM_PWM_OP_GET_CLOCK:
-      res = platform_pwm_get_clock();
-      break;
-
-    case PLATFORM_PWM_OP_START:
-      PWM_TIMER_NAME->CCER |= ( ( u16 )1 << 4 * id );
-      break;
-
-    case PLATFORM_PWM_OP_STOP:
-      PWM_TIMER_NAME->CCER &= ~( ( u16 )1 << 4 * id );
-      break;
-  }
-
-  return res;
+void platform_pwm_stop( unsigned id )
+{
+  PWM_TIMER_NAME->CCER &= ~( ( u16 )1 << 4 * id );
 }
 
 // *****************************************************************************
@@ -1098,7 +1150,7 @@ static void adcs_init()
   
   for( id = 0; id < NUM_ADC; id ++ )
     adc_init_ch_state( id );
-	
+
   RCC_APB2PeriphClockCmd( RCC_APB2Periph_ADC1, ENABLE );
   RCC_ADCCLKConfig( RCC_PCLK2_Div8 );
   
@@ -1148,10 +1200,10 @@ static void adcs_init()
   DMA_Cmd( DMA1_Channel1, ENABLE );
   DMA_ITConfig( DMA1_Channel1, DMA1_IT_TC1 , ENABLE ); 
   
-  platform_adc_setclock( 0, 0 );
+  platform_adc_set_clock( 0, 0 );
 }
 
-u32 platform_adc_setclock( unsigned id, u32 frequency )
+u32 platform_adc_set_clock( unsigned id, u32 frequency )
 {
   TIM_TimeBaseInitTypeDef timer_base_struct;
   elua_adc_dev_state *d = adc_get_dev_state( 0 );
diff --git a/src/platform/stm32/platform_conf.h b/src/platform/stm32/platform_conf.h
index b89dc485..198141cc 100755
--- a/src/platform/stm32/platform_conf.h
+++ b/src/platform/stm32/platform_conf.h
@@ -31,12 +31,13 @@
 #define BUILD_LUA_INT_HANDLERS
 #define ENABLE_ENC
 
+#define PLATFORM_HAS_SYSTIMER
+
 // *****************************************************************************
 // UART/Timer IDs configuration data (used in main.c)
 
 #define CON_UART_ID           0
 #define CON_UART_SPEED        115200
-#define CON_TIMER_ID          0
 #define TERM_LINES            25
 #define TERM_COLS             80
 
@@ -112,6 +113,7 @@
 #define NUM_SPI               2
 #define NUM_UART              5
 #define NUM_TIMER             5
+#define NUM_PHYS_TIMER        5
 #define NUM_PWM               4
 #define NUM_ADC               16
 #define NUM_CAN               1
@@ -131,7 +133,6 @@
 
 // RPC boot options
 #define RPC_UART_ID           CON_UART_ID
-#define RPC_TIMER_ID          CON_TIMER_ID
 #define RPC_UART_SPEED        CON_UART_SPEED
 
 
@@ -139,8 +140,6 @@
 
 // MMCFS Support (FatFs on SD/MMC)
 // For STM32F103RET6 - PA5 = CLK, PA6 = MISO, PA7 = MOSI, PA8 = CS
-#define MMCFS_TICK_HZ                10
-#define MMCFS_TICK_MS                ( 1000 / MMCFS_TICK_HZ )
 #define MMCFS_CS_PORT                0
 #define MMCFS_CS_PIN                 8
 #define MMCFS_SPI_NUM                0
@@ -160,7 +159,6 @@ u32 platform_s_cpu_get_frequency();
 // Remote file system data
 #define RFS_BUFFER_SIZE       BUF_SIZE_512
 #define RFS_UART_ID           0
-#define RFS_TIMER_ID          0
 #define RFS_TIMEOUT           100000
 #define RFS_UART_SPEED        115200
 
diff --git a/src/platform/stm32/platform_int.c b/src/platform/stm32/platform_int.c
index 7172891e..30771125 100644
--- a/src/platform/stm32/platform_int.c
+++ b/src/platform/stm32/platform_int.c
@@ -9,6 +9,10 @@
 // Platform-specific headers
 #include "stm32f10x.h"
 
+#ifndef VTMR_TIMER_ID
+#define VTMR_TIMER_ID         ( -1 )
+#endif
+
 // ****************************************************************************
 // Interrupt handlers
 
@@ -71,7 +75,7 @@ static void all_exti_irqhandler( int line )
 {
   u16 v, port, pin;
   
-  v = exti_line_to_gpio( line );	
+  v = exti_line_to_gpio( line );
   port = PLATFORM_IO_GET_PORT( v );
   pin = PLATFORM_IO_GET_PIN( v );
 
@@ -128,6 +132,61 @@ void EXTI15_10_IRQHandler()
   }
 }
 
+// ----------------------------------------------------------------------------
+// Timer interrupt handlers
+
+const TIM_TypeDef * const timer[] = { TIM1, TIM2, TIM3, TIM4, TIM5 };
+extern u8 stm32_timer_int_periodic_flag[ NUM_PHYS_TIMER ];
+
+static void tmr_int_handler( int id )
+{
+  TIM_TypeDef *base = ( TIM_TypeDef* )timer[ id ];
+
+  if (TIM_GetITStatus( base, TIM_IT_CC1) != RESET)
+  {
+    TIM_ClearITPendingBit( base, TIM_IT_CC1 );
+
+    if( id == VTMR_TIMER_ID )
+      cmn_virtual_timer_cb();
+    else
+      cmn_int_handler( INT_TMR_MATCH, id );
+
+    if( stm32_timer_int_periodic_flag[ id ] != PLATFORM_TIMER_INT_CYCLIC )
+      TIM_ITConfig( base, TIM_IT_CC1, DISABLE );
+  }
+}
+
+
+void TIM1_CC_IRQHandler(void)
+{
+  tmr_int_handler( 0 );
+}
+
+void TIM2_IRQHandler(void)
+{
+  tmr_int_handler( 1 );
+}
+
+void TIM3_IRQHandler(void)
+{
+  tmr_int_handler( 2 );
+}
+
+void TIM4_IRQHandler(void)
+{
+  tmr_int_handler( 3 );
+}
+
+void TIM5_IRQHandler(void)
+{
+  tmr_int_handler( 4 );
+}
+
+void TIM8_CC_IRQHandler(void)
+{
+  tmr_int_handler( 7 );
+}
+
 // ****************************************************************************
 // GPIO helper functions
 
@@ -154,7 +213,7 @@ static int gpioh_set_int_status( elua_int_id id, elua_int_resnum resnum, int sta
     exti_init_struct.EXTI_Line = exti_line[ exint_gpio_to_src( resnum ) ];
     exti_init_struct.EXTI_Mode = EXTI_Mode_Interrupt;
     if( ( ( ( EXTI->RTSR & mask ) != 0 ) && ( id == INT_GPIO_NEGEDGE ) ) ||
-	( ( ( EXTI->FTSR & mask ) != 0 ) && ( id == INT_GPIO_POSEDGE ) ) )
+        ( ( ( EXTI->FTSR & mask ) != 0 ) && ( id == INT_GPIO_POSEDGE ) ) )
       exti_init_struct.EXTI_Trigger = EXTI_Trigger_Rising_Falling;
     else
       exti_init_struct.EXTI_Trigger = id == INT_GPIO_POSEDGE ? EXTI_Trigger_Rising : EXTI_Trigger_Falling;
@@ -234,19 +293,30 @@ static int int_gpio_negedge_get_flag( elua_int_resnum resnum, int clear )
 // ****************************************************************************
 // Interrupt: INT_TMR_MATCH
 
-static int int_tmr_match_set_status( elua_int_resnum resnum, int status )
-{
-  return PLATFORM_INT_NOT_HANDLED;
-}
-
 static int int_tmr_match_get_status( elua_int_resnum resnum )
 {
-  return PLATFORM_INT_NOT_HANDLED;
+  TIM_TypeDef *base = ( TIM_TypeDef* )timer[ resnum ];
+
+  return ( base->DIER & TIM_IT_CC1 ) != 0;
+}
+
+static int int_tmr_match_set_status( elua_int_resnum resnum, int status )
+{
+  int previous = int_tmr_match_get_status( resnum );
+  TIM_TypeDef *base = ( TIM_TypeDef* )timer[ resnum ];
+  
+  TIM_ITConfig( base, TIM_IT_CC1, status == PLATFORM_CPU_ENABLE ? ENABLE : DISABLE );
+  return previous;
 }
 
 static int int_tmr_match_get_flag( elua_int_resnum resnum, int clear )
 {
-  return PLATFORM_INT_NOT_HANDLED;
+  TIM_TypeDef *base = ( TIM_TypeDef* )timer[ resnum ];
+  int status = TIM_GetFlagStatus( base, TIM_FLAG_CC1 );
+
+  if( clear )
+    TIM_ClearFlag( base, TIM_FLAG_CC1 );
+  return status;
 }
 
 // ****************************************************************************
@@ -287,6 +357,15 @@ static const u8 uart_irq_table[] = { USART1_IRQn, USART2_IRQn, USART3_IRQn, UART
 // EXTI IRQ table
 static const u8 exti_irq_table[] = { EXTI0_IRQn, EXTI1_IRQn, EXTI2_IRQn, EXTI3_IRQn, EXTI4_IRQn, EXTI9_5_IRQn, EXTI15_10_IRQn };
 
+// EXTI IRQ table
+#if defined( STM32F10X_LD )
+static const u8 timer_irq_table[] = { TIM1_CC_IRQn, TIM2_IRQn, TIM3_IRQn };
+#elseif defined( STM32F10X_MD )
+static const u8 timer_irq_table[] = { TIM1_CC_IRQn, TIM2_IRQn, TIM3_IRQn, TIM4_IRQn };
+#else
+static const u8 timer_irq_table[] = { TIM1_CC_IRQn, TIM2_IRQn, TIM3_IRQn, TIM4_IRQn, TIM5_IRQn };
+#endif
+
 void platform_int_init()
 {
   NVIC_InitTypeDef nvic_init_structure;
@@ -295,7 +374,8 @@ void platform_int_init()
   // Enable all USART interrupts in the NVIC
   nvic_init_structure.NVIC_IRQChannelPreemptionPriority = 0;
   nvic_init_structure.NVIC_IRQChannelSubPriority = 0;
-  nvic_init_structure.NVIC_IRQChannelCmd = ENABLE;  
+  nvic_init_structure.NVIC_IRQChannelCmd = ENABLE;
+
   for( i = 0; i < sizeof( uart_irq_table ) / sizeof( u8 ); i ++ )
   {
     nvic_init_structure.NVIC_IRQChannel = uart_irq_table[ i ];
@@ -309,6 +389,15 @@ void platform_int_init()
     NVIC_Init( &nvic_init_structure );
   }
 
+#ifdef INT_TMR_MATCH
+  for( i = 0; i < sizeof( timer_irq_table ) / sizeof( u8 ); i ++ )
+  {
+    nvic_init_structure.NVIC_IRQChannel = timer_irq_table[ i ];
+      nvic_init_structure.NVIC_IRQChannelSubPriority = 1;
+    NVIC_Init( &nvic_init_structure );
+  }
+#endif  
+
 }
 
 // ****************************************************************************
diff --git a/src/platform/stm32/uip-conf.h b/src/platform/stm32/uip-conf.h
index 79a14929..32dcb927 100755
--- a/src/platform/stm32/uip-conf.h
+++ b/src/platform/stm32/uip-conf.h
@@ -150,8 +150,6 @@ typedef struct dhcpc_state uip_udp_appstate_t;
 #define UIP_UDP_APPCALL             elua_uip_udp_appcall
 #endif
 
-// Added for eLua: DHCP TIMER ID
-#define ELUA_DHCP_TIMER_ID          1
 #define CLOCK_SECOND                1000000UL
 
 #endif // __UIP_CONF_H_
diff --git a/src/platform/str7/platform.c b/src/platform/str7/platform.c
index 0bebcb62..19d96610 100644
--- a/src/platform/str7/platform.c
+++ b/src/platform/str7/platform.c
@@ -180,7 +180,7 @@ void platform_s_uart_send( unsigned id, u8 data )
   UART_ByteSend( pport, &data );
 }
 
-int platform_s_uart_recv( unsigned id, s32 timeout )
+int platform_s_uart_recv( unsigned id, timer_data_type timeout )
 {
   UART_TypeDef* pport = ( UART_TypeDef* )uart_periph[ id ];    
   
@@ -232,7 +232,7 @@ static u32 platform_timer_set_clock( unsigned id, u32 clock )
   return baseclk / bestdiv;
 }
 
-void platform_s_timer_delay( unsigned id, u32 delay_us )
+void platform_s_timer_delay( unsigned id, timer_data_type delay_us )
 {
   TIM_TypeDef* ptimer = ( TIM_TypeDef* )tim_periph[ id ];  
   u32 freq;
@@ -253,7 +253,7 @@ void platform_s_timer_delay( unsigned id, u32 delay_us )
   while( TIM_CounterValue( ptimer ) < final );  
 }
       
-u32 platform_s_timer_op( unsigned id, int op, u32 data )
+timer_data_type platform_s_timer_op( unsigned id, int op, timer_data_type data )
 {
   u32 res = 0;
   TIM_TypeDef* ptimer = ( TIM_TypeDef* )tim_periph[ id ];  
@@ -275,14 +275,6 @@ u32 platform_s_timer_op( unsigned id, int op, u32 data )
       res = TIM_CounterValue( ptimer );
       break;
       
-    case PLATFORM_TIMER_OP_GET_MAX_DELAY:
-      res = platform_timer_get_diff_us( id, 0, 0xFFFF );
-      break;
-      
-    case PLATFORM_TIMER_OP_GET_MIN_DELAY:
-      res = platform_timer_get_diff_us( id, 0, 1 );
-      break;      
-      
     case PLATFORM_TIMER_OP_SET_CLOCK:
       res = platform_timer_set_clock( id, data );
       break;
@@ -290,6 +282,10 @@ u32 platform_s_timer_op( unsigned id, int op, u32 data )
     case PLATFORM_TIMER_OP_GET_CLOCK:
       res = platform_timer_get_clock( id );
       break;
+
+    case PLATFORM_TIMER_OP_GET_MAX_CNT:
+      res = 0xFFFF;
+      break;
   }
   return res;
 }
@@ -319,31 +315,24 @@ u32 platform_pwm_setup( unsigned id, u32 frequency, unsigned duty )
   return pwmclk / period;
 }
 
-u32 platform_pwm_op( unsigned id, int op, u32 data )
+u32 platform_pwm_set_clock( unsigned id, u32 clock )
 {
-  u32 res = 0;
-  TIM_TypeDef *ptimer = ( TIM_TypeDef* )tim_periph[ id + 1 ];
-  
-  switch( op )
-  {
-    case PLATFORM_PWM_OP_SET_CLOCK:
-      res = platform_timer_set_clock( id + 1, data );
-      break;
-      
-    case PLATFORM_PWM_OP_GET_CLOCK:
-      res = platform_timer_get_clock( id + 1 );
-      break;
-      
-    case PLATFORM_PWM_OP_START:
-      TIM_CounterConfig( ptimer, TIM_START );
-      break;
-      
-    case PLATFORM_PWM_OP_STOP:
-      TIM_CounterConfig( ptimer, TIM_STOP );
-      platform_pio_op( pwm_ports[ id ], pwm_pins[ id ], PLATFORM_IO_PIN_DIR_INPUT );
-      break;
-  }
-  
-  return res;
+  return platform_timer_set_clock( id + 1, clock );
 }
 
+u32 platform_pwm_get_clock( unsigned id )
+{
+  return platform_timer_get_clock( id + 1 );
+}
+
+void platform_pwm_start( unsigned id )
+{
+  TIM_TypeDef *ptimer = ( TIM_TypeDef* )tim_periph[ id + 1 ];
+
+  TIM_CounterConfig( ptimer, TIM_START );
+}
+
+void platform_pwm_stop( unsigned id )
+{
+  platform_pio_op( pwm_ports[ id ], pwm_pins[ id ], PLATFORM_IO_PIN_DIR_INPUT );
+}
diff --git a/src/platform/str7/platform_conf.h b/src/platform/str7/platform_conf.h
index e40bffc8..fd095e94 100644
--- a/src/platform/str7/platform_conf.h
+++ b/src/platform/str7/platform_conf.h
@@ -73,7 +73,7 @@
 #define RPC_TIMER_ID          CON_TIMER_ID
 #define RPC_UART_SPEED        CON_UART_SPEED
 
-// CPU frequency (needed by the CPU module, 0 if not used)
+// CPU frequency (needed by the CPU module and MMCFS code, 0 if not used)
 #define CPU_FREQUENCY         0
 
 // PIO prefix ('0' for P0, P1, ... or 'A' for PA, PB, ...)
diff --git a/src/platform/str9/interrupt.c b/src/platform/str9/interrupt.c
index c37bd52e..f64fd354 100644
--- a/src/platform/str9/interrupt.c
+++ b/src/platform/str9/interrupt.c
@@ -93,6 +93,8 @@ void ARMRX_IRQHandler(void)
 void ARMTX_IRQHandler(void)
 {
 }
+
+#if 0
 /*******************************************************************************
 * Function Name  : TIM0_IRQHandler
 * Description    : This function handles the TIM0 interrupt request
@@ -121,6 +123,8 @@ void TIM2_IRQHandler(void)
 void TIM3_IRQHandler(void)
 {
 }
+#endif
+
 /*******************************************************************************
 * Function Name  : USBHP_IRQHandler
 * Description    : This function handles the USBHP interrupt request
@@ -243,37 +247,38 @@ void RTC_IRQHandler(void)
 * Function Name  : WIU_IRQHandler
 * Description    : This function handles the WIU interrupt request
 *******************************************************************************/
-void WIU_IRQHandler(void)
+/*void WIU_IRQHandler(void)
 {
-}
+}*/
+
 /*******************************************************************************
 * Function Name  : EXTIT0_IRQHandler
 * Description    : This function handles the EXTIT0 interrupt request
 *******************************************************************************/
-/*void EXTIT0_IRQHandler(void)
+void EXTIT0_IRQHandler(void)
 {
-}*/
+}
 /*******************************************************************************
 * Function Name  : EXTIT1_IRQHandler
 * Description    : This function handles the EXTIT1 interrupt request
 *******************************************************************************/
-/*void EXTIT1_IRQHandler(void)
+void EXTIT1_IRQHandler(void)
 {
-}*/
+}
 /*******************************************************************************
 * Function Name  : EXTIT2_IRQHandler
 * Description    : This function handles the EXTIT2 interrupt request
 *******************************************************************************/
-/*void EXTIT2_IRQHandler(void)
+void EXTIT2_IRQHandler(void)
 {
-}*/
+}
 /*******************************************************************************
 * Function Name  : EXTIT3_IRQHandler
 * Description    : This function handles the EXTIT3 interrupt request
 *******************************************************************************/
-/*void EXTIT3_IRQHandler(void)
+void EXTIT3_IRQHandler(void)
 {
-}*/
+}
 /*******************************************************************************
 * Function Name  : USBWU_IRQHandler
 * Description    : This function handles the USBWU interrupt request
diff --git a/src/platform/str9/platform.c b/src/platform/str9/platform.c
index 7c809bb2..17a587f3 100644
--- a/src/platform/str9/platform.c
+++ b/src/platform/str9/platform.c
@@ -30,8 +30,16 @@
 // ****************************************************************************
 // Platform initialization
 const GPIO_TypeDef* port_data[] = { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7, GPIO8, GPIO9 };
+#ifndef VTMR_TIMER_ID
+#error Define VTMR_TIMER_ID to the ID of the timer used for the system timer
+#endif
 const TIM_TypeDef* str9_timer_data[] = { TIM0, TIM1, TIM2, TIM3 };
 
+// System timer implementation on STR9 uses one of the physical timers (defined by
+// VTMR_TIMER_ID). This is the same timer used for VTMR implementation. Its base
+// frequency is set to 1MHz in platform_s_timer_set_match_int. It runs at 16Hz
+// since this gives an exact number of microseconds (62500) before its overflow.
+
 static void platform_setup_adcs();
 
 static void platform_config_scu()
@@ -158,10 +166,11 @@ int platform_init()
   // Setup ADCs
   platform_setup_adcs();
 #endif
- 
-#ifdef VTMR_TIMER_ID
+
+  // Initialize system timer
+  cmn_systimer_set_base_freq( 1000000 );
+  cmn_systimer_set_interrupt_freq( VTMR_FREQ_HZ );
   platform_s_timer_set_match_int( VTMR_TIMER_ID, 1000000 / VTMR_FREQ_HZ, PLATFORM_TIMER_INT_CYCLIC );
-#endif
   return PLATFORM_OK;
 }
 
@@ -280,7 +289,7 @@ void platform_s_uart_send( unsigned id, u8 data )
   while( UART_GetFlagStatus( p_uart, UART_FLAG_TxFIFOFull ) != RESET );  
 }
 
-int platform_s_uart_recv( unsigned id, s32 timeout )
+int platform_s_uart_recv( unsigned id, timer_data_type timeout )
 {
   UART_TypeDef* p_uart = ( UART_TypeDef* )uarts[ id ];
 
@@ -329,7 +338,7 @@ static u32 platform_timer_set_clock( unsigned id, u32 clock )
   return baseclk / bestdiv;
 }
 
-void platform_s_timer_delay( unsigned id, u32 delay_us )
+void platform_s_timer_delay( unsigned id, timer_data_type delay_us )
 {
   TIM_TypeDef* base = ( TIM_TypeDef* )str9_timer_data[ id ];  
   u32 freq;
@@ -350,7 +359,7 @@ void platform_s_timer_delay( unsigned id, u32 delay_us )
   while( TIM_GetCounterValue( base ) < final );  
 }
       
-u32 platform_s_timer_op( unsigned id, int op, u32 data )
+timer_data_type platform_s_timer_op( unsigned id, int op, timer_data_type data )
 {
   u32 res = 0;
   TIM_TypeDef* base = ( TIM_TypeDef* )str9_timer_data[ id ];  
@@ -368,14 +377,6 @@ u32 platform_s_timer_op( unsigned id, int op, u32 data )
       res = TIM_GetCounterValue( base );
       break;
       
-    case PLATFORM_TIMER_OP_GET_MAX_DELAY:
-      res = platform_timer_get_diff_us( id, 0, 0xFFFF );
-      break;
-      
-    case PLATFORM_TIMER_OP_GET_MIN_DELAY:
-      res = platform_timer_get_diff_us( id, 0, 1 );
-      break;      
-      
     case PLATFORM_TIMER_OP_SET_CLOCK:
       res = platform_timer_set_clock( id, data );
       break;
@@ -383,11 +384,15 @@ u32 platform_s_timer_op( unsigned id, int op, u32 data )
     case PLATFORM_TIMER_OP_GET_CLOCK:
       res = platform_timer_get_clock( id );
       break;
+
+    case PLATFORM_TIMER_OP_GET_MAX_CNT:
+      res = 0xFFFF;
+      break;
   }
   return res;
 }
 
-int platform_s_timer_set_match_int( unsigned id, u32 period_us, int type )
+int platform_s_timer_set_match_int( unsigned id, timer_data_type period_us, int type )
 {
   TIM_TypeDef* base = ( TIM_TypeDef* )str9_timer_data[ id ];  
   u32 freq;
@@ -428,6 +433,32 @@ int platform_s_timer_set_match_int( unsigned id, u32 period_us, int type )
   return PLATFORM_TIMER_INT_OK;
 }
 
+u64 platform_timer_sys_raw_read()
+{
+  TIM_TypeDef* base = ( TIM_TypeDef* )str9_timer_data[ VTMR_TIMER_ID ];
+
+  return TIM_GetCounterValue( base );
+}
+
+void platform_timer_sys_enable_int()
+{
+  TIM_TypeDef* base = ( TIM_TypeDef* )str9_timer_data[ VTMR_TIMER_ID ];
+
+  TIM_ITConfig( base, TIM_IT_OC1, ENABLE );
+}
+
+void platform_timer_sys_disable_int()
+{
+  TIM_TypeDef* base = ( TIM_TypeDef* )str9_timer_data[ VTMR_TIMER_ID ];
+
+  TIM_ITConfig( base, TIM_IT_OC1, DISABLE );
+}
+
+timer_data_type platform_timer_read_sys()
+{
+  return cmn_systimer_get();
+}
+
 // *****************************************************************************
 // ADC specific functions and variables
 
@@ -470,18 +501,18 @@ void ADC_IRQHandler( void )
     
       // Fill in smoothing buffer until warmed up
       if ( s->logsmoothlen > 0 && s->smooth_ready == 0)
-	adc_smooth_data( s->id );
+        adc_smooth_data( s->id );
 #if defined( BUF_ENABLE_ADC )
       else if ( s->reqsamples > 1 )
       {
-	buf_write( BUF_ID_ADC, s->id, ( t_buf_data* )s->value_ptr );
-	s->value_fresh = 0;
+        buf_write( BUF_ID_ADC, s->id, ( t_buf_data* )s->value_ptr );
+        s->value_fresh = 0;
       }
 #endif
 
       // If we have the number of requested samples, stop sampling
       if ( adc_samples_available( s->id ) >= s->reqsamples && s->freerunning == 0 )
-	platform_adc_stop( s->id );
+        platform_adc_stop( s->id );
 
       d->seq_ctr++;
     }
@@ -524,12 +555,12 @@ static void platform_setup_adcs()
 
   ADC_ITConfig(ADC_IT_ECV, ENABLE);
 
-  platform_adc_setclock( 0, 0 );
+  platform_adc_set_clock( 0, 0 );
 }
 
 
 // NOTE: On this platform, there is only one ADC, clock settings apply to the whole device
-u32 platform_adc_setclock( unsigned id, u32 frequency )
+u32 platform_adc_set_clock( unsigned id, u32 frequency )
 {
   elua_adc_dev_state *d = adc_get_dev_state( 0 );
   
@@ -658,7 +689,7 @@ u32 platform_pwm_setup( unsigned id, u32 frequency, unsigned duty )
   return base / div;
 }
 
-static u32 platform_pwm_set_clock( unsigned id, u32 clock )
+u32 platform_pwm_set_clock( unsigned id, u32 clock )
 {
   TIM_TypeDef* p_timer = ( TIM_TypeDef* )str9_timer_data[ id ];
   u32 base = ( SCU_GetPCLKFreqValue() * 1000 );
@@ -668,31 +699,25 @@ static u32 platform_pwm_set_clock( unsigned id, u32 clock )
   return base / div;
 }
 
-u32 platform_pwm_op( unsigned id, int op, u32 data )
+u32 platform_pwm_get_clock( unsigned id )
 {
-  u32 res = 0;
   TIM_TypeDef* p_timer = ( TIM_TypeDef* )str9_timer_data[ id ];
 
-  switch( op )
-  {
-    case PLATFORM_PWM_OP_START:
-      TIM_CounterCmd( p_timer, TIM_START );
-      break;
+  return ( SCU_GetPCLKFreqValue() * 1000 ) / ( TIM_GetPrescalerValue( p_timer ) + 1 );
+}
 
-    case PLATFORM_PWM_OP_STOP:
-      TIM_CounterCmd( p_timer, TIM_STOP );
-      break;
+void platform_pwm_start( unsigned id )
+{
+  TIM_TypeDef* p_timer = ( TIM_TypeDef* )str9_timer_data[ id ];
 
-    case PLATFORM_PWM_OP_SET_CLOCK:
-      res = platform_pwm_set_clock( id, data );
-      break;
+  TIM_CounterCmd( p_timer, TIM_START );
+}
 
-    case PLATFORM_PWM_OP_GET_CLOCK:
-      res = ( SCU_GetPCLKFreqValue() * 1000 ) / ( TIM_GetPrescalerValue( p_timer ) + 1 );
-      break;
-  }
+void platform_pwm_stop( unsigned id )
+{
+  TIM_TypeDef* p_timer = ( TIM_TypeDef* )str9_timer_data[ id ];
 
-  return res;
+  TIM_CounterCmd( p_timer, TIM_STOP );
 }
 
 // ****************************************************************************
@@ -836,36 +861,79 @@ u32 platform_spi_setup( unsigned id, int mode, u32 clock, unsigned cpol, unsigne
     divider = temp / prescaler;
   }
 
-  // GPIO setup
-  // Fixed assignment:
-  // P5.4 - SCLK
-  // P5.5 - MOSI
-  // P5.6 - MISO
-  // P5.7 - CS (not explicitly handled by the SPI module)
-  GPIO_InitStructure.GPIO_Direction = GPIO_PinOutput;
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 | GPIO_Pin_5;
-  GPIO_InitStructure.GPIO_Type = GPIO_Type_PushPull ;
-  GPIO_InitStructure.GPIO_Alternate = GPIO_OutputAlt2  ;
-  GPIO_Init(GPIO5, &GPIO_InitStructure);
-  GPIO_InitStructure.GPIO_Direction = GPIO_PinInput;
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
-  GPIO_InitStructure.GPIO_IPConnected = GPIO_IPConnected_Enable;
-  GPIO_InitStructure.GPIO_Alternate = GPIO_InputAlt1  ;
-  GPIO_Init(GPIO5, &GPIO_InitStructure);
+  if ( id == 0 )
+  {
+    // GPIO setup
+    // Fixed assignment:
+    // P5.4 - SCLK
+    // P5.5 - MOSI
+    // P5.6 - MISO
+    // P5.7 - CS
+    GPIO_InitStructure.GPIO_Direction = GPIO_PinOutput;
+    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_7;
+    GPIO_InitStructure.GPIO_Type = GPIO_Type_PushPull;
+    GPIO_InitStructure.GPIO_Alternate = GPIO_OutputAlt2;
+    GPIO_Init(GPIO5, &GPIO_InitStructure);
+    GPIO_InitStructure.GPIO_Direction = GPIO_PinInput;
+    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
+    GPIO_InitStructure.GPIO_IPConnected = GPIO_IPConnected_Enable;
+    GPIO_InitStructure.GPIO_Alternate = GPIO_InputAlt1  ;
+    GPIO_Init(GPIO5, &GPIO_InitStructure);
 
-  // Actual SPI setup
-  SSP_DeInit(SSP0);
-  SSP_InitStructure.SSP_FrameFormat = SSP_FrameFormat_Motorola;
-  SSP_InitStructure.SSP_Mode = SSP_Mode_Master;
-  SSP_InitStructure.SSP_CPOL = cpol == 0 ? SSP_CPOL_Low : SSP_CPOL_High;
-  SSP_InitStructure.SSP_CPHA = cpha == 0 ? SSP_CPHA_1Edge : SSP_CPHA_2Edge;
-  SSP_InitStructure.SSP_DataSize = databits - 1;
-  SSP_InitStructure.SSP_ClockRate = divider - 1;
-  SSP_InitStructure.SSP_ClockPrescaler = prescaler;
-  SSP_Init(SSP0, &SSP_InitStructure);
+    // Actual SPI setup
+    SSP_DeInit(SSP0);
+    SSP_InitStructure.SSP_FrameFormat = SSP_FrameFormat_Motorola;
+    SSP_InitStructure.SSP_Mode = SSP_Mode_Master;
+    SSP_InitStructure.SSP_CPOL = cpol == 0 ? SSP_CPOL_Low : SSP_CPOL_High;
+    SSP_InitStructure.SSP_CPHA = cpha == 0 ? SSP_CPHA_1Edge : SSP_CPHA_2Edge;
+    SSP_InitStructure.SSP_DataSize = databits - 1;
+    SSP_InitStructure.SSP_ClockRate = divider - 1;
+    SSP_InitStructure.SSP_ClockPrescaler = prescaler;
+    SSP_Init(SSP0, &SSP_InitStructure);
 
-  // Enable peripheral   
-  SSP_Cmd(SSP0, ENABLE);
+    // Enable peripheral   
+    SSP_Cmd(SSP0, ENABLE);
+  }
+  else if ( id == 1 )
+  {
+    // GPIO setup
+    // Fixed assignment:
+    // P1.0 - SCLK
+    // P1.1 - MOSI
+    // P1.2 - MISO
+    // P1.3 - CS
+    GPIO_InitStructure.GPIO_Direction = GPIO_PinOutput;
+    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;
+    GPIO_InitStructure.GPIO_Type = GPIO_Type_PushPull;
+    GPIO_InitStructure.GPIO_Alternate = GPIO_OutputAlt3;
+    GPIO_Init(GPIO1, &GPIO_InitStructure);
+	
+    GPIO_InitStructure.GPIO_Direction = GPIO_PinOutput;
+    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_3;
+    GPIO_InitStructure.GPIO_Type = GPIO_Type_PushPull;
+    GPIO_InitStructure.GPIO_Alternate = GPIO_OutputAlt3;
+    GPIO_Init(GPIO1, &GPIO_InitStructure);
+	
+    GPIO_InitStructure.GPIO_Direction = GPIO_PinInput;
+    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
+    GPIO_InitStructure.GPIO_IPConnected = GPIO_IPConnected_Enable;
+    GPIO_InitStructure.GPIO_Alternate = GPIO_InputAlt1;
+    GPIO_Init(GPIO1, &GPIO_InitStructure);
+
+    // Actual SPI setup
+    SSP_DeInit(SSP1);
+    SSP_InitStructure.SSP_FrameFormat = SSP_FrameFormat_Motorola;
+    SSP_InitStructure.SSP_Mode = SSP_Mode_Master;
+    SSP_InitStructure.SSP_CPOL = cpol == 0 ? SSP_CPOL_Low : SSP_CPOL_High;
+    SSP_InitStructure.SSP_CPHA = cpha == 0 ? SSP_CPHA_1Edge : SSP_CPHA_2Edge;
+    SSP_InitStructure.SSP_DataSize = databits - 1;
+    SSP_InitStructure.SSP_ClockRate = divider - 1;
+    SSP_InitStructure.SSP_ClockPrescaler = prescaler;
+    SSP_Init(SSP1, &SSP_InitStructure);
+
+    // Enable peripheral   
+    SSP_Cmd(SSP1, ENABLE);
+  }
   
   // All done
   return basefreq / ( prescaler * divider );
@@ -873,14 +941,28 @@ u32 platform_spi_setup( unsigned id, int mode, u32 clock, unsigned cpol, unsigne
 
 spi_data_type platform_spi_send_recv( unsigned id, spi_data_type data )
 {
-  // Send byte through the SSP0 peripheral
-  SSP0->DR = data;
-  // Loop while Transmit FIFO is full
-  while(SSP_GetFlagStatus(SSP0, SSP_FLAG_TxFifoEmpty) == RESET);
-  // Loop while Receive FIFO is empty
-  while(SSP_GetFlagStatus(SSP0, SSP_FLAG_RxFifoNotEmpty) == RESET); 
-  // Return the byte read from the SSP bus
-  return SSP0->DR;
+  if (id == 0)
+  {
+    // Send byte through the SSP0 peripheral
+    SSP0->DR = data;
+    // Loop while Transmit FIFO is full
+    while(SSP_GetFlagStatus(SSP0, SSP_FLAG_TxFifoEmpty) == RESET);
+    // Loop while Receive FIFO is empty
+    while(SSP_GetFlagStatus(SSP0, SSP_FLAG_RxFifoNotEmpty) == RESET); 
+    // Return the byte read from the SSP bus
+    return SSP0->DR;  
+  }
+  else
+  {
+    // Send byte through the SSP1 peripheral
+    SSP1->DR = data;
+    // Loop while Transmit FIFO is full
+    while(SSP_GetFlagStatus(SSP1, SSP_FLAG_TxFifoEmpty) == RESET);
+    // Loop while Receive FIFO is empty
+    while(SSP_GetFlagStatus(SSP1, SSP_FLAG_RxFifoNotEmpty) == RESET); 
+    // Return the byte read from the SSP bus
+    return SSP1->DR;  
+  }
 }
 
 void platform_spi_select( unsigned id, int is_select )
diff --git a/src/platform/str9/platform_conf.h b/src/platform/str9/platform_conf.h
index 3c02dd47..ab1e4937 100644
--- a/src/platform/str9/platform_conf.h
+++ b/src/platform/str9/platform_conf.h
@@ -22,6 +22,8 @@
 #define BUILD_LUA_INT_HANDLERS
 #define BUILD_C_INT_HANDLERS
 
+#define PLATFORM_HAS_SYSTIMER
+
 // *****************************************************************************
 // UART/Timer IDs configuration data (used in main.c)
 
@@ -32,7 +34,6 @@
 #endif
 
 #define CON_UART_SPEED        115200
-#define CON_TIMER_ID          0
 #define TERM_LINES            25
 #define TERM_COLS             80
 
@@ -41,23 +42,20 @@
 
 // Virtual timers (0 if not used)
 #define VTMR_NUM_TIMERS       4
-#define VTMR_FREQ_HZ          10
-#define VTMR_TIMER_ID         2
+#define VTMR_FREQ_HZ          16
+#define VTMR_TIMER_ID         3
 
 // Number of resources (0 if not available/not implemented)
 #define NUM_PIO               10
-#define NUM_SPI               1
+#define NUM_SPI               2
 #define NUM_UART              3
 #define NUM_PWM               4
 #define NUM_ADC               8
 #define NUM_CAN               0
 #define NUM_I2C               2
 
-#ifdef VTMR_TIMER_ID
+// One timer is reserved for the system timer / vtimers
 #define NUM_TIMER             3
-#else
-#define NUM_TIMER             4
-#endif
 #define NUM_PHYS_TIMER        4
 
 // ADC Configuration Params
@@ -71,13 +69,12 @@
 
 // RPC boot options
 #define RPC_UART_ID           CON_UART_ID
-#define RPC_TIMER_ID          CON_TIMER_ID
 #define RPC_UART_SPEED        CON_UART_SPEED
 
 // Interrupt queue configuration
 #define PLATFORM_INT_QUEUE_LOG_SIZE   BUF_SIZE_32
 
-// CPU frequency (needed by the CPU module, 0 if not used)
+// CPU frequency (needed by the CPU module and MMCFS code, 0 if not used)
 u32 SCU_GetMCLKFreqValue();
 #define CPU_FREQUENCY         ( SCU_GetMCLKFreqValue() * 1000 )
 
diff --git a/src/platform/str9/platform_int.c b/src/platform/str9/platform_int.c
index a1aca1b6..f9591147 100644
--- a/src/platform/str9/platform_int.c
+++ b/src/platform/str9/platform_int.c
@@ -55,31 +55,23 @@ static int exint_gpio_to_src( pio_type piodata )
 // ----------------------------------------------------------------------------
 // External interrupt handlers
 
-static void exint_irq_handler( int group )
+void WIU_IRQHandler(void)
 {
   u32 bmask;
   u32 pr = WIU->PR;
   u32 mr = WIU->MR;
   u32 tr = WIU->TR;
-  u32 shift = group << 3;
   unsigned i;
 
-  // Check interrupt mask
-  if( ( ( pr >> shift ) & 0xFF ) == 0 )
-  {
-    VIC1->VAR = 0xFF;
-    return;
-  }
-
   // Iterate through all the bits in the mask, queueing interrupts as needed
-  for( i = 0, bmask = 1 << shift; i < 8; i ++, bmask <<= 1 )
+  for( i = 2, bmask = 4; i < 32; i ++, bmask <<= 1 )
     if( ( pr & bmask ) && ( mr & bmask ) )
     {
       // Enqueue interrupt
       if( tr & bmask )
-        cmn_int_handler( INT_GPIO_POSEDGE, exint_src_to_gpio( shift + i ) );
+        cmn_int_handler( INT_GPIO_POSEDGE, exint_src_to_gpio( i ) );
       else
-        cmn_int_handler( INT_GPIO_NEGEDGE, exint_src_to_gpio( shift + i ) );
+        cmn_int_handler( INT_GPIO_NEGEDGE, exint_src_to_gpio( i ) );
       // Then clear it
       WIU->PR  = bmask;
     }
@@ -88,26 +80,6 @@ static void exint_irq_handler( int group )
   VIC1->VAR = 0xFF;
 }
 
-void EXTIT0_IRQHandler()
-{
-  exint_irq_handler( 0 );
-}
-
-void EXTIT1_IRQHandler()
-{
-  exint_irq_handler( 1 );
-}
-
-void EXTIT2_IRQHandler()
-{
-  exint_irq_handler( 2 );
-}
-
-void EXTIT3_IRQHandler()
-{
-  exint_irq_handler( 3 );
-}
-
 // ----------------------------------------------------------------------------
 // Timer interrupt handlers
 
@@ -121,7 +93,10 @@ static void tmr_int_handler( int id )
   TIM_ClearFlag( base, TIM_FLAG_OC1 );
   TIM_CounterCmd( base, TIM_CLEAR );
   if( id == VTMR_TIMER_ID )
+  {
     cmn_virtual_timer_cb();
+    cmn_systimer_periodic();
+  }
   else
     cmn_int_handler( INT_TMR_MATCH, id );
   if( str9_timer_int_periodic_flag[ id ] != PLATFORM_TIMER_INT_CYCLIC )
@@ -289,6 +264,8 @@ static int int_tmr_match_get_flag( elua_int_resnum resnum, int clear )
 
 void platform_int_init()
 {
+  int p = 1;
+
   // Initialize VIC
   VIC_DeInit();
   VIC0->DVAR = ( u32 )dummy_int_handler;
@@ -297,19 +274,14 @@ void platform_int_init()
   // Enablue WIU
   WIU_DeInit();
   
-  // Initialize all external interrupts
-  VIC_Config( EXTIT0_ITLine, VIC_IRQ, 1 );
-  VIC_Config( EXTIT1_ITLine, VIC_IRQ, 2 );
-  VIC_Config( EXTIT2_ITLine, VIC_IRQ, 3 );
-  VIC_Config( EXTIT3_ITLine, VIC_IRQ, 4 );
-  VIC_ITCmd( EXTIT0_ITLine, ENABLE );
-  VIC_ITCmd( EXTIT1_ITLine, ENABLE );
-  VIC_ITCmd( EXTIT2_ITLine, ENABLE );
-  VIC_ITCmd( EXTIT3_ITLine, ENABLE );
-
+  // Initialize the WIU interrupt
+  VIC_Config( WIU_ITLine, VIC_IRQ, p ++ );
+  VIC_ITCmd( WIU_ITLine, ENABLE );
   // Enable interrupt generation on WIU
+  WIU->PR = 0xFFFFFFFF;
   WIU->CTRL |= 2; 
 
+
 #ifdef INT_TMR_MATCH
   VIC_Config( TIM0_ITLine, VIC_IRQ, 5 );
   VIC_Config( TIM1_ITLine, VIC_IRQ, 6 );
diff --git a/src/platform/str9/str9_pio.c b/src/platform/str9/str9_pio.c
index 234d5ea7..1814266b 100644
--- a/src/platform/str9/str9_pio.c
+++ b/src/platform/str9/str9_pio.c
@@ -71,22 +71,3 @@ const LUA_REG_TYPE str9_pio_map[] =
   { LSTRKEY( "setpin" ),  LFUNCVAL( setpin) },
   { LNILKEY, LNILVAL }
 };
-
-LUALIB_API int luaopen_disp( lua_State *L )
-{
-#if LUA_OPTIMIZE_MEMORY > 0
-  return 0;
-#else
-  luaL_register( L, PS_LIB_TABLE_NAME, str9_pio_map );
-  MOD_REG_NUMBER( L, "INPUT", GPIO_DIR_INPUT );
-  MOD_REG_NUMBER( L, "OUTPUT", GPIO_DIR_OUTPUT );
-  MOD_REG_NUMBER( L, "ALT_INPUT", GPIO_ALT_INPUT );
-  MOD_REG_NUMBER( L, "ALT_OUTPUT1", GPIO_ALT_OUTPUT1 );
-  MOD_REG_NUMBER( L, "ALT_OUTPUT2", GPIO_ALT_OUTPUT2 );
-  MOD_REG_NUMBER( L, "ALT_OUTPUT3", GPIO_ALT_OUTPUT3 );
-  MOD_REG_NUMBER( L, "OUTPUT_PUSHPULL", GPIO_OUTPUT_PP );
-  MOD_REG_NUMBER( L, "OUTPUT_OC", GPIO_OUTPUT_OC );
-  return 1;  
-#endif
-}  
-
diff --git a/src/remotefs/client.c b/src/remotefs/client.c
index 210014d3..3bf03c64 100644
--- a/src/remotefs/client.c
+++ b/src/remotefs/client.c
@@ -5,7 +5,7 @@
 #include "client.h"
 #include "os_io.h"
 #include "eluarpc.h"
-
+#include "platform.h"
 #include 
 #include "platform_conf.h"
 #include "buf.h"
@@ -26,7 +26,7 @@ void RFSDEBUG( const char* dummy, ... )
 static u8 *rfsc_buffer;
 static p_rfsc_send rfsc_send;
 static p_rfsc_recv rfsc_recv;
-static u32 rfsc_timeout;
+static timer_data_type rfsc_timeout;
 
 // ****************************************************************************
 // Client helpers
@@ -76,7 +76,7 @@ static int rfsch_send_request_read_response()
 // ****************************************************************************
 // Client public interface
 
-void rfsc_setup( u8 *pbuf, p_rfsc_send rfsc_send_func, p_rfsc_recv rfsc_recv_func, u32 timeout )
+void rfsc_setup( u8 *pbuf, p_rfsc_send rfsc_send_func, p_rfsc_recv rfsc_recv_func, timer_data_type timeout )
 {
   rfsc_buffer = pbuf;
   rfsc_send = rfsc_send_func;
@@ -84,7 +84,7 @@ void rfsc_setup( u8 *pbuf, p_rfsc_send rfsc_send_func, p_rfsc_recv rfsc_recv_fun
   rfsc_timeout = timeout;
 }
 
-void rfsc_set_timeout( u32 timeout )
+void rfsc_set_timeout( timer_data_type timeout )
 {
   rfsc_timeout = timeout;
 }
diff --git a/src/remotefs/elua_rfs.c b/src/remotefs/elua_rfs.c
index bf511814..38a6a170 100644
--- a/src/remotefs/elua_rfs.c
+++ b/src/remotefs/elua_rfs.c
@@ -19,7 +19,11 @@
 
 // [TODO] the new builder should automatically do this
 #ifndef RFS_FLOW_TYPE
-#define RFS_FLOW_TYPE        PLATFORM_UART_FLOW_NONE
+#define RFS_FLOW_TYPE         PLATFORM_UART_FLOW_NONE
+#endif
+
+#ifndef RFS_TIMER_ID
+#define RFS_TIMER_ID          PLATFORM_TIMER_SYS_ID
 #endif
 
 // Our RFS buffer
@@ -131,7 +135,7 @@ static u32 rfs_send( const u8 *p, u32 size )
   return size;
 }
 
-static u32 rfs_recv( u8 *p, u32 size, s32 timeout )
+static u32 rfs_recv( u8 *p, u32 size, timer_data_type timeout )
 {
   u32 cnt = 0;
   int data;
@@ -157,7 +161,7 @@ static u32 rfs_send( const u8 *p, u32 size )
   return ( u32 )hostif_write( rfs_write_fd, p, size );
 }
 
-static u32 rfs_recv( u8 *p, u32 size, s32 timeout )
+static u32 rfs_recv( u8 *p, u32 size, timer_data_type timeout )
 {
   timeout = timeout;
   return ( u32 )hostif_read( rfs_read_fd, p, size );
diff --git a/src/semifs.c b/src/semifs.c
index 4e8add8e..3b512eba 100644
--- a/src/semifs.c
+++ b/src/semifs.c
@@ -39,7 +39,7 @@ __semihost(int reason, void * arg)
        : "=r" (value) /* Outputs */
        : "r" (reason), "r" (arg), "i" (AngelSWI) /* Inputs */
        : "r0", "r1", "r2", "r3", "ip", "lr", "memory", "cc"
-		/* Clobbers r0 and r1, and lr if in supervisor mode */);
+                /* Clobbers r0 and r1, and lr if in supervisor mode */);
                 /* Accordingly to page 13-77 of ARM DUI 0040D other registers
                    can also be clobbered.  Some memory positions may also be
                    changed by a system call, so they should not be kept in
@@ -168,7 +168,7 @@ static off_t semifs_lseek_r( struct _reent *r, int fd, off_t off, int whence )
     case SEEK_CUR:
       // seek from current position
       if (fd == SEMIFS_MAX_FDS)
-	return -1;
+        return -1;
       off  += semifs_fd_table[ fd ].pos;
       whence = SEEK_SET;
       break;
diff --git a/src/serial/serial_win32.c b/src/serial/serial_win32.c
index 4f712b85..749eaeb0 100644
--- a/src/serial/serial_win32.c
+++ b/src/serial/serial_win32.c
@@ -13,7 +13,7 @@ static int ser_win32_set_timeouts( HANDLE hComm, DWORD ri, DWORD rtm, DWORD rtc,
 {   
   COMMTIMEOUTS timeouts;
   
-  if( GetCommTimeouts( hComm, &timeouts ) == FALSE )
+  if( !GetCommTimeouts( hComm, &timeouts ) )
   {
     CloseHandle( hComm );
     return SER_ERR;
@@ -23,10 +23,10 @@ static int ser_win32_set_timeouts( HANDLE hComm, DWORD ri, DWORD rtm, DWORD rtc,
   timeouts.ReadTotalTimeoutMultiplier = rtc;
   timeouts.WriteTotalTimeoutConstant = wtm;
   timeouts.WriteTotalTimeoutMultiplier = wtc;
-	if( SetCommTimeouts( hComm, &timeouts ) == FALSE )
-	{
-	  CloseHandle( hComm );
-	  return SER_ERR;
+  if( !SetCommTimeouts( hComm, &timeouts ) )
+  {
+    CloseHandle( hComm );
+    return SER_ERR;
   }               
   
   return SER_OK;
@@ -45,6 +45,11 @@ ser_handler ser_open( const char* sername )
     return WIN_ERROR;
   if( !SetupComm( hComm, 2048, 2048 ) )
     return WIN_ERROR;
+  if( !FlushFileBuffers( hComm ) || 
+      !PurgeComm( hComm, PURGE_TXABORT | PURGE_RXABORT |
+                         PURGE_TXCLEAR | PURGE_RXCLEAR ) )
+    return WIN_ERROR; 
+  
   return hComm;
 }
 
@@ -77,11 +82,12 @@ int ser_setup( ser_handler id, u32 baud, int databits, int parity, int stopbits
   /**/ dcb.fAbortOnError = FALSE;
   dcb.fOutxCtsFlow = FALSE;
   dcb.fOutxDsrFlow = FALSE;
-  dcb.fDtrControl = DTR_CONTROL_DISABLE;
+  // dcb.fDtrControl = DTR_CONTROL_DISABLE; -- prevents data being read with LM3S eval board
   dcb.fDsrSensitivity = FALSE;
   dcb.fRtsControl = RTS_CONTROL_DISABLE;
   dcb.fOutxCtsFlow = FALSE;
-  if( SetCommState( hComm, &dcb ) == 0 )
+
+  if( !SetCommState( hComm, &dcb ) )
   {
     CloseHandle( hComm );
     return SER_ERR;
@@ -103,7 +109,7 @@ u32 ser_read( ser_handler id, u8* dest, u32 maxsize )
   HANDLE hComm = ( HANDLE )id;
   DWORD readbytes;
   
-  if( ReadFile( hComm, dest, maxsize, &readbytes, NULL ) == FALSE )
+  if( !ReadFile( hComm, dest, maxsize, &readbytes, NULL ) )
     return 0;
   return readbytes;
 }
@@ -123,8 +129,8 @@ u32 ser_write( ser_handler id, const u8 *src, u32 size )
 {
   HANDLE hComm = ( HANDLE )id;
   DWORD written;
-	
-  if( WriteFile( hComm, src, size, &written, NULL ) == FALSE )
+
+  if( !WriteFile( hComm, src, size, &written, NULL ) )
     return 0;
   return written;
 }
@@ -153,7 +159,8 @@ int ser_readable( ser_handler id )
   DWORD   dwErrors;
   HANDLE hComm = ( HANDLE )id;
   
-  ClearCommError(hComm, &dwErrors, &comStat);
+  if( !ClearCommError(hComm, &dwErrors, &comStat) )
+    return 0;
   
   return ( comStat.cbInQue > 0 );
 }
diff --git a/src/shell.c b/src/shell.c
index 11384241..8647dcfc 100644
--- a/src/shell.c
+++ b/src/shell.c
@@ -56,7 +56,8 @@ static void shell_help( char* args )
   printf( "  ls or dir   - lists filesystems files and sizes\n" );
   printf( "  cat or type - lists file contents\n" );
   printf( "  lua [args]  - run Lua with the given arguments\n" );
-  printf( "  recv        - receive a file via XMODEM and execute it\n" );
+  printf( "  recv [path] - receive a file via XMODEM, if there is a path, save"
+          "                there, otherwise run it.");
   printf( "  cp   - copy source file 'src' to 'dst'\n" );
   printf( "  ver         - print eLua version\n" );
 }
@@ -144,21 +145,41 @@ static void shell_recv( char* args )
   p ++;
   printf( "done, got %u bytes\n", ( unsigned )( p - shell_prog ) );          
   
-  // Execute
-  if( ( L = lua_open() ) == NULL )
+  // we've received an argument, try saving it to a file
+  if( strcmp( args, "") != 0 )
   {
-    printf( "Unable to create Lua state\n" );
-    free( shell_prog );
-    shell_prog = NULL;
-    return;
+    FILE *foutput = fopen( args, "w" );
+    size_t file_sz = p - shell_prog;
+    if( foutput == NULL )
+    {
+      printf( "unable to open file %s\n", args);
+      free( shell_prog );
+      shell_prog = NULL;
+      return;
+    }
+    if( fwrite( shell_prog, sizeof( char ), file_sz, foutput ) == file_sz )
+      printf( "received and saved as %s\n", args );
+    else
+      printf( "disk full, unable to save file %s\n", args );
+    fclose( foutput );
   }
-  luaL_openlibs( L );
-  if( luaL_loadbuffer( L, shell_prog, p - shell_prog, "xmodem" ) != 0 )
-    printf( "Error: %s\n", lua_tostring( L, -1 ) );
-  else
-    if( lua_pcall( L, 0, LUA_MULTRET, 0 ) != 0 )
+  else // no arg, running the file with lua.
+  {
+    if( ( L = lua_open() ) == NULL )
+    {
+      printf( "Unable to create Lua state\n" );
+      free( shell_prog );
+      shell_prog = NULL;
+      return;
+    }
+    luaL_openlibs( L );
+    if( luaL_loadbuffer( L, shell_prog, p - shell_prog, "xmodem" ) != 0 )
       printf( "Error: %s\n", lua_tostring( L, -1 ) );
-  lua_close( L );
+    else
+      if( lua_pcall( L, 0, LUA_MULTRET, 0 ) != 0 )
+        printf( "Error: %s\n", lua_tostring( L, -1 ) );
+    lua_close( L );
+  }
   free( shell_prog );
   shell_prog = NULL;
 #endif // #ifndef BUILD_XMODEM
diff --git a/src/uip/dhcpc.c b/src/uip/dhcpc.c
index 1436b626..e92b4d91 100644
--- a/src/uip/dhcpc.c
+++ b/src/uip/dhcpc.c
@@ -30,7 +30,7 @@
  *
  * This file is part of the uIP TCP/IP stack
  *
- * @(#)$Id: dhcpc.c,v 1.2 2006/06/11 21:46:37 adam Exp $
+ * @(#)$Id: dhcpc.c,v 1.1 2007/01/04 11:06:35 adamdunkels Exp $
  */
 
 #include 
@@ -48,6 +48,10 @@
 
 #define HOSTNAME "elua"
 
+#ifndef ELUA_DHCP_TIMER_ID
+#define ELUA_DHCP_TIMER_ID    PLATFORM_TIMER_SYS_ID
+#endif
+
 static struct dhcpc_state s;
 
 struct __attribute((packed)) dhcp_msg {
@@ -273,31 +277,31 @@ PT_THREAD(handle_dhcp(void))
 
   do {
     send_discover();
-    s.timer_init = platform_timer_op( ELUA_DHCP_TIMER_ID, PLATFORM_TIMER_OP_START, 0 );
-    PT_WAIT_UNTIL(&s.pt, uip_newdata() || platform_timer_get_diff_us( ELUA_DHCP_TIMER_ID, s.timer_init, platform_timer_op( ELUA_DHCP_TIMER_ID, PLATFORM_TIMER_OP_READ, 0 ) ) >= s.ticks );
+    s.timer_init = platform_timer_start( ELUA_DHCP_TIMER_ID );
+    PT_YIELD_UNTIL(&s.pt, uip_newdata() || platform_timer_get_diff_crt( ELUA_DHCP_TIMER_ID, s.timer_init ) >= s.ticks );
     if(uip_newdata() && parse_msg() == DHCPOFFER) {
-	  uip_flags &= ~UIP_NEWDATA;
+      uip_flags &= ~UIP_NEWDATA;
       s.state = STATE_OFFER_RECEIVED;
       break;
     }
-	uip_flags &= ~UIP_NEWDATA;
+    uip_flags &= ~UIP_NEWDATA;
     if(s.ticks < CLOCK_SECOND * 60) {
       s.ticks *= 2;
     } else {
-	  s.ipaddr[0] = 0;
-	  goto dhcp_failed;
-	  }
+      s.ipaddr[0] = 0;
+      goto dhcp_failed;
+    }
   } while(s.state != STATE_OFFER_RECEIVED);
   
   s.ticks = CLOCK_SECOND;
 
   do {
     send_request();
-    s.timer_init = platform_timer_op( ELUA_DHCP_TIMER_ID, PLATFORM_TIMER_OP_START, 0 );    
-    PT_WAIT_UNTIL(&s.pt, uip_newdata() || platform_timer_get_diff_us( ELUA_DHCP_TIMER_ID, s.timer_init, platform_timer_op( ELUA_DHCP_TIMER_ID, PLATFORM_TIMER_OP_READ, 0 ) ) >= s.ticks );
+    s.timer_init = platform_timer_start( ELUA_DHCP_TIMER_ID );
+    PT_YIELD_UNTIL(&s.pt, uip_newdata() || platform_timer_get_diff_crt( ELUA_DHCP_TIMER_ID, s.timer_init ) >= s.ticks );
     
     if(uip_newdata() && parse_msg() == DHCPACK) {
-	  uip_flags &= ~UIP_NEWDATA;
+      uip_flags &= ~UIP_NEWDATA;
       s.state = STATE_CONFIG_RECEIVED;
       break;
     }
diff --git a/src/uip/dhcpc.h b/src/uip/dhcpc.h
index aa8629f5..ee6febff 100644
--- a/src/uip/dhcpc.h
+++ b/src/uip/dhcpc.h
@@ -40,7 +40,7 @@ struct dhcpc_state {
   struct pt pt;
   char state;
   struct uip_udp_conn *conn;
-  u32 timer_init, ticks;
+  u64 timer_init, ticks;
   const void *mac_addr;
   int mac_len;
   
diff --git a/src/uip/lc-switch.h b/src/uip/lc-switch.h
index f32885fd..90e22bd0 100644
--- a/src/uip/lc-switch.h
+++ b/src/uip/lc-switch.h
@@ -55,7 +55,7 @@
  */
 
 #ifndef __LC_SWITCH_H__
-#define __LC_SWTICH_H__
+#define __LC_SWITCH_H__
 
 /* WARNING! lc implementation using switch() does not work if an
    LC_SET() is done within another switch() statement! */
diff --git a/src/uip/psock.c b/src/uip/psock.c
index 35d3e9bf..5633386c 100644
--- a/src/uip/psock.c
+++ b/src/uip/psock.c
@@ -76,7 +76,7 @@
 /*---------------------------------------------------------------------------*/
 static void
 buf_setup(struct psock_buf *buf,
-	  u8_t *bufptr, u16_t bufsize)
+          u8_t *bufptr, u16_t bufsize)
 {
   buf->ptr = bufptr;
   buf->left = bufsize;
@@ -84,7 +84,7 @@ buf_setup(struct psock_buf *buf,
 /*---------------------------------------------------------------------------*/
 static u8_t
 buf_bufdata(struct psock_buf *buf, u16_t len,
-	    u8_t **dataptr, u16_t *datalen)
+            u8_t **dataptr, u16_t *datalen)
 {
   if(*datalen < buf->left) {
     memcpy(buf->ptr, *dataptr, *datalen);
@@ -112,7 +112,7 @@ buf_bufdata(struct psock_buf *buf, u16_t len,
 /*---------------------------------------------------------------------------*/
 static u8_t
 buf_bufto(register struct psock_buf *buf, u8_t endmarker,
-	  register u8_t **dataptr, register u16_t *datalen)
+          register u8_t **dataptr, register u16_t *datalen)
 {
   u8_t c;
   while(buf->left > 0 && *datalen > 0) {
@@ -177,7 +177,7 @@ data_acked(register struct psock *s)
 }
 /*---------------------------------------------------------------------------*/
 PT_THREAD(psock_send(register struct psock *s, const char *buf,
-		     unsigned int len))
+                     unsigned int len))
 {
   PT_BEGIN(&s->psockpt);
 
@@ -188,7 +188,7 @@ PT_THREAD(psock_send(register struct psock *s, const char *buf,
 
   /* Save the length of and a pointer to the data that is to be
      sent. */
-  s->sendptr = buf;
+  s->sendptr = (u8_t *)buf;
   s->sendlen = len;
 
   s->state = STATE_NONE;
@@ -216,7 +216,7 @@ PT_THREAD(psock_send(register struct psock *s, const char *buf,
 }
 /*---------------------------------------------------------------------------*/
 PT_THREAD(psock_generator_send(register struct psock *s,
-			       unsigned short (*generate)(void *), void *arg))
+                               unsigned short (*generate)(void *), void *arg))
 {
   PT_BEGIN(&s->psockpt);
 
@@ -276,7 +276,7 @@ PT_THREAD(psock_readto(register struct psock *psock, unsigned char c))
 {
   PT_BEGIN(&psock->psockpt);
 
-  buf_setup(&psock->buf, psock->bufptr, psock->bufsize);
+  buf_setup(&psock->buf, (u8_t *)psock->bufptr, psock->bufsize);
   
   /* XXX: Should add buf_checkmarker() before do{} loop, if
      incoming data has been handled while waiting for a write. */
@@ -289,8 +289,8 @@ PT_THREAD(psock_readto(register struct psock *psock, unsigned char c))
       psock->readlen = uip_datalen();
     }
   } while((buf_bufto(&psock->buf, c,
-		     &psock->readptr,
-		     &psock->readlen) & BUF_FOUND) == 0);
+                     &psock->readptr,
+                     &psock->readlen) & BUF_FOUND) == 0);
   
   if(psock_datalen(psock) == 0) {
     psock->state = STATE_NONE;
@@ -303,7 +303,7 @@ PT_THREAD(psock_readbuf(register struct psock *psock))
 {
   PT_BEGIN(&psock->psockpt);
 
-  buf_setup(&psock->buf, psock->bufptr, psock->bufsize);
+  buf_setup(&psock->buf, (u8_t *)psock->bufptr, psock->bufsize);
   
   /* XXX: Should add buf_checkmarker() before do{} loop, if
      incoming data has been handled while waiting for a write. */
@@ -317,8 +317,8 @@ PT_THREAD(psock_readbuf(register struct psock *psock))
       psock->readlen = uip_datalen();
     }
   } while(buf_bufdata(&psock->buf, psock->bufsize,
-			 &psock->readptr,
-			 &psock->readlen) != BUF_FULL);
+                      &psock->readptr,
+                      &psock->readlen) != BUF_FULL);
 
   if(psock_datalen(psock) == 0) {
     psock->state = STATE_NONE;
@@ -334,7 +334,7 @@ psock_init(register struct psock *psock, char *buffer, unsigned int buffersize)
   psock->readlen = 0;
   psock->bufptr = buffer;
   psock->bufsize = buffersize;
-  buf_setup(&psock->buf, buffer, buffersize);
+  buf_setup(&psock->buf, (u8_t *)buffer, buffersize);
   PT_INIT(&psock->pt);
   PT_INIT(&psock->psockpt);
 }
diff --git a/src/uip/psock.h b/src/uip/psock.h
index 3dffa735..54906dd6 100644
--- a/src/uip/psock.h
+++ b/src/uip/psock.h
@@ -105,19 +105,19 @@ struct psock_buf {
  */
 struct psock {
   struct pt pt, psockpt; /* Protothreads - one that's using the psock
-			    functions, and one that runs inside the
-			    psock functions. */
+                            functions, and one that runs inside the
+                            psock functions. */
   const u8_t *sendptr;   /* Pointer to the next data to be sent. */
   u8_t *readptr;         /* Pointer to the next data to be read. */
   
   char *bufptr;          /* Pointer to the buffer used for buffering
-			    incoming data. */
+                            incoming data. */
   
   u16_t sendlen;         /* The number of bytes left to be sent. */
   u16_t readlen;         /* The number of bytes left to be read. */
 
   struct psock_buf buf;  /* The structure holding the state of the
-			    input buffer. */
+                            input buffer. */
   unsigned int bufsize;  /* The size of the input buffer. */
   
   unsigned char state;   /* The state of the protosocket. */
@@ -175,7 +175,7 @@ PT_THREAD(psock_send(struct psock *psock, const char *buf, unsigned int len));
  *
  * \hideinitializer
  */
-#define PSOCK_SEND(psock, data, datalen)		\
+#define PSOCK_SEND(psock, data, datalen) \
     PT_WAIT_THREAD(&((psock)->pt), psock_send(psock, data, datalen))
 
 /**
@@ -188,11 +188,11 @@ PT_THREAD(psock_send(struct psock *psock, const char *buf, unsigned int len));
  *
  * \hideinitializer
  */
-#define PSOCK_SEND_STR(psock, str)      		\
+#define PSOCK_SEND_STR(psock, str) \
     PT_WAIT_THREAD(&((psock)->pt), psock_send(psock, str, strlen(str)))
 
 PT_THREAD(psock_generator_send(struct psock *psock,
-				unsigned short (*f)(void *), void *arg));
+                               unsigned short (*f)(void *), void *arg));
 
 /**
  * \brief      Generate data with a function and send it
@@ -216,9 +216,9 @@ PT_THREAD(psock_generator_send(struct psock *psock,
  *
  * \hideinitializer
  */
-#define PSOCK_GENERATOR_SEND(psock, generator, arg)     \
-    PT_WAIT_THREAD(&((psock)->pt),					\
-		   psock_generator_send(psock, generator, arg))
+#define PSOCK_GENERATOR_SEND(psock, generator, arg) \
+    PT_WAIT_THREAD(&((psock)->pt),                  \
+    psock_generator_send(psock, generator, arg))
 
 
 /**
@@ -247,7 +247,7 @@ PT_THREAD(psock_readbuf(struct psock *psock));
  *
  * \hideinitializer
  */
-#define PSOCK_READBUF(psock)				\
+#define PSOCK_READBUF(psock) \
   PT_WAIT_THREAD(&((psock)->pt), psock_readbuf(psock))
 
 PT_THREAD(psock_readto(struct psock *psock, unsigned char c));
@@ -265,7 +265,7 @@ PT_THREAD(psock_readto(struct psock *psock, unsigned char c));
  *
  * \hideinitializer
  */
-#define PSOCK_READTO(psock, c)				\
+#define PSOCK_READTO(psock, c) \
   PT_WAIT_THREAD(&((psock)->pt), psock_readto(psock, c))
 
 /**
@@ -305,10 +305,10 @@ u16_t psock_datalen(struct psock *psock);
  *
  * \hideinitializer
  */
-#define PSOCK_CLOSE_EXIT(psock)		\
-  do {						\
-    PSOCK_CLOSE(psock);			\
-    PSOCK_EXIT(psock);			\
+#define PSOCK_CLOSE_EXIT(psock) \
+  do {                          \
+    PSOCK_CLOSE(psock);         \
+    PSOCK_EXIT(psock);          \
   } while(0)
 
 /**
diff --git a/src/uip/pt.h b/src/uip/pt.h
index 9f1f64da..f1e8b66c 100644
--- a/src/uip/pt.h
+++ b/src/uip/pt.h
@@ -145,12 +145,12 @@ struct pt {
  *
  * \hideinitializer
  */
-#define PT_WAIT_UNTIL(pt, condition)	        \
-  do {						\
-    LC_SET((pt)->lc);				\
-    if(!(condition)) {				\
-      return PT_WAITING;			\
-    }						\
+#define PT_WAIT_UNTIL(pt, condition)            \
+  do {                                          \
+    LC_SET((pt)->lc);                           \
+    if(!(condition)) {                          \
+      return PT_WAITING;                        \
+    }                                           \
   } while(0)
 
 /**
@@ -203,10 +203,10 @@ struct pt {
  *
  * \hideinitializer
  */
-#define PT_SPAWN(pt, child, thread)		\
-  do {						\
-    PT_INIT((child));				\
-    PT_WAIT_THREAD((pt), (thread));		\
+#define PT_SPAWN(pt, child, thread)             \
+  do {                                          \
+    PT_INIT((child));                           \
+    PT_WAIT_THREAD((pt), (thread));             \
   } while(0)
 
 /** @} */
@@ -226,10 +226,10 @@ struct pt {
  *
  * \hideinitializer
  */
-#define PT_RESTART(pt)				\
-  do {						\
-    PT_INIT(pt);				\
-    return PT_WAITING;			\
+#define PT_RESTART(pt)                          \
+  do {                                          \
+    PT_INIT(pt);                                \
+    return PT_WAITING;                          \
   } while(0)
 
 /**
@@ -243,10 +243,10 @@ struct pt {
  *
  * \hideinitializer
  */
-#define PT_EXIT(pt)				\
-  do {						\
-    PT_INIT(pt);				\
-    return PT_EXITED;			\
+#define PT_EXIT(pt)                             \
+  do {                                          \
+    PT_INIT(pt);                                \
+    return PT_EXITED;                           \
   } while(0)
 
 /** @} */
@@ -287,13 +287,13 @@ struct pt {
  *
  * \hideinitializer
  */
-#define PT_YIELD(pt)				\
-  do {						\
-    PT_YIELD_FLAG = 0;				\
-    LC_SET((pt)->lc);				\
-    if(PT_YIELD_FLAG == 0) {			\
-      return PT_YIELDED;			\
-    }						\
+#define PT_YIELD(pt)                            \
+  do {                                          \
+    PT_YIELD_FLAG = 0;                          \
+    LC_SET((pt)->lc);                           \
+    if(PT_YIELD_FLAG == 0) {                    \
+      return PT_YIELDED;                        \
+    }                                           \
   } while(0)
 
 /**
@@ -307,13 +307,13 @@ struct pt {
  *
  * \hideinitializer
  */
-#define PT_YIELD_UNTIL(pt, cond)		\
-  do {						\
-    PT_YIELD_FLAG = 0;				\
-    LC_SET((pt)->lc);				\
-    if((PT_YIELD_FLAG == 0) || !(cond)) {	\
-      return PT_YIELDED;			\
-    }						\
+#define PT_YIELD_UNTIL(pt, cond)                \
+  do {                                          \
+    PT_YIELD_FLAG = 0;                          \
+    LC_SET((pt)->lc);                           \
+    if((PT_YIELD_FLAG == 0) || !(cond)) {       \
+      return PT_YIELDED;                        \
+    }                                           \
   } while(0)
 
 /** @} */
diff --git a/src/uip/resolv.c b/src/uip/resolv.c
index eeeff9f8..2e1fad25 100644
--- a/src/uip/resolv.c
+++ b/src/uip/resolv.c
@@ -181,23 +181,23 @@ check_entries(void)
     if(namemapptr->state == STATE_NEW ||
        namemapptr->state == STATE_ASKING) {
       if(namemapptr->state == STATE_ASKING) {
-	if(--namemapptr->tmr == 0) {
-	  if(++namemapptr->retries == MAX_RETRIES) {
-	    namemapptr->state = STATE_ERROR;
-	    resolv_found(namemapptr->name, NULL);
-	    continue;
-	  }
-	  namemapptr->tmr = namemapptr->retries;
-	} else {
-	  /*	  printf("Timer %d\n", namemapptr->tmr);*/
-	  /* Its timer has not run out, so we move on to next
-	     entry. */
-	  continue;
-	}
+        if(--namemapptr->tmr == 0) {
+          if(++namemapptr->retries == MAX_RETRIES) {
+            namemapptr->state = STATE_ERROR;
+            resolv_found(namemapptr->name, NULL);
+            continue;
+          }
+          namemapptr->tmr = namemapptr->retries;
+        } else {
+          /*      printf("Timer %d\n", namemapptr->tmr);*/
+          /* Its timer has not run out, so we move on to next
+             entry. */
+          continue;
+        }
       } else {
-	namemapptr->state = STATE_ASKING;
-	namemapptr->tmr = 1;
-	namemapptr->retries = 0;
+        namemapptr->state = STATE_ASKING;
+        namemapptr->tmr = 1;
+        namemapptr->retries = 0;
       }
       hdr = (struct dns_hdr *)uip_appdata;
       memset(hdr, 0, sizeof(struct dns_hdr));
@@ -209,20 +209,20 @@ check_entries(void)
       --nameptr;
       /* Convert hostname into suitable query format. */
       do {
-	++nameptr;
-	nptr = query;
-	++query;
-	for(n = 0; *nameptr != '.' && *nameptr != 0; ++nameptr) {
-	  *query = *nameptr;
-	  ++query;
-	  ++n;
-	}
-	*nptr = n;
+        ++nameptr;
+        nptr = query;
+        ++query;
+        for(n = 0; *nameptr != '.' && *nameptr != 0; ++nameptr) {
+          *query = *nameptr;
+          ++query;
+          ++n;
+        }
+        *nptr = n;
       } while(*nameptr != 0);
       {
-	static unsigned char endquery[] =
-	  {0,0,1,0,1};
-	memcpy(query, endquery, 5);
+        static unsigned char endquery[] =
+          {0,0,1,0,1};
+        memcpy(query, endquery, 5);
       }
       uip_udp_send((unsigned char)(query + 5 - (char *)uip_appdata));
       break;
@@ -237,7 +237,7 @@ check_entries(void)
 static void
 newdata(void)
 {
-  char *nameptr;
+  unsigned char *nameptr;
   struct dns_answer *ans;
   struct dns_hdr *hdr;
   static u8_t nquestions, nanswers;
@@ -281,44 +281,44 @@ newdata(void)
     /* Skip the name in the question. XXX: This should really be
        checked agains the name in the question, to be sure that they
        match. */
-    nameptr = parse_name((char *)uip_appdata + 12) + 4;
+    nameptr = parse_name((unsigned char *)uip_appdata + 12) + 4;
 
     while(nanswers > 0) {
       /* The first byte in the answer resource record determines if it
-	 is a compressed record or a normal one. */
+         is a compressed record or a normal one. */
       if(*nameptr & 0xc0) {
-	/* Compressed name. */
-	nameptr +=2;
-	/*	printf("Compressed anwser\n");*/
+        /* Compressed name. */
+        nameptr +=2;
+        /* printf("Compressed anwser\n");*/
       } else {
-	/* Not compressed name. */
-	nameptr = parse_name((char *)nameptr);
+        /* Not compressed name. */
+        nameptr = parse_name(nameptr);
       }
 
       ans = (struct dns_answer *)nameptr;
       /*      printf("Answer: type %x, class %x, ttl %x, length %x\n",
-	     htons(ans->type), htons(ans->class), (htons(ans->ttl[0])
-	     << 16) | htons(ans->ttl[1]), htons(ans->len));*/
+             htons(ans->type), htons(ans->class), (htons(ans->ttl[0])
+             << 16) | htons(ans->ttl[1]), htons(ans->len));*/
 
       /* Check for IP address type and Internet class. Others are
-	 discarded. */
+         discarded. */
       if(ans->type == HTONS(1) &&
-	 ans->class == HTONS(1) &&
-	 ans->len == HTONS(4)) {
-	/*	printf("IP address %d.%d.%d.%d\n",
-	       htons(ans->ipaddr[0]) >> 8,
-	       htons(ans->ipaddr[0]) & 0xff,
-	       htons(ans->ipaddr[1]) >> 8,
-	       htons(ans->ipaddr[1]) & 0xff);*/
-	/* XXX: we should really check that this IP address is the one
-	   we want. */
-	namemapptr->ipaddr[0] = ans->ipaddr[0];
-	namemapptr->ipaddr[1] = ans->ipaddr[1];
-	
-	resolv_found(namemapptr->name, namemapptr->ipaddr);
-	return;
+         ans->class == HTONS(1) &&
+         ans->len == HTONS(4)) {
+        /* printf("IP address %d.%d.%d.%d\n",
+               htons(ans->ipaddr[0]) >> 8,
+               htons(ans->ipaddr[0]) & 0xff,
+               htons(ans->ipaddr[1]) >> 8,
+               htons(ans->ipaddr[1]) & 0xff);*/
+        /* XXX: we should really check that this IP address is the one
+           we want. */
+        namemapptr->ipaddr[0] = ans->ipaddr[0];
+        namemapptr->ipaddr[1] = ans->ipaddr[1];
+        
+        resolv_found(namemapptr->name, namemapptr->ipaddr);
+        return;
       } else {
-	nameptr = nameptr + 10 + htons(ans->len);
+        nameptr = nameptr + 10 + htons(ans->len);
       }
       --nanswers;
     }
diff --git a/src/uip/uip-fw.c b/src/uip/uip-fw.c
index a7884d11..205f5a2e 100644
--- a/src/uip/uip-fw.c
+++ b/src/uip/uip-fw.c
@@ -331,7 +331,7 @@ find_netif(void)
   /* Walk through every network interface to check for a match. */
   for(netif = netifs; netif != NULL; netif = netif->next) {
     if(ipaddr_maskcmp(BUF->destipaddr, netif->ipaddr,
-		      netif->netmask)) {
+                      netif->netmask)) {
       /* If there was a match, we break the loop. */
       return netif;
     }
@@ -385,8 +385,8 @@ uip_fw_output(void)
   
   netif = find_netif();
   /*  printf("uip_fw_output: netif %p ->output %p len %d\n", netif,
-	 netif->output,
-	 uip_len);*/
+         netif->output,
+         uip_len);*/
 
   if(netif == NULL) {
     return UIP_FW_NOROUTE;
diff --git a/src/uip/uip-fw.h b/src/uip/uip-fw.h
index 90338509..bb00a98a 100644
--- a/src/uip/uip-fw.h
+++ b/src/uip/uip-fw.h
@@ -53,12 +53,12 @@
  */
 struct uip_fw_netif {
   struct uip_fw_netif *next;  /**< Pointer to the next interface when
-				 linked in a list. */
+                                 linked in a list. */
   u16_t ipaddr[2];            /**< The IP address of this interface. */
   u16_t netmask[2];           /**< The netmask of the interface. */
   u8_t (* output)(void);
                               /**< A pointer to the function that
-				 sends a packet. */
+                                 sends a packet. */
 };
 
 /**
@@ -79,8 +79,8 @@ struct uip_fw_netif {
  */
 #define UIP_FW_NETIF(ip1,ip2,ip3,ip4, nm1,nm2,nm3,nm4, outputfunc) \
         NULL, \
-	{HTONS((ip1 << 8) | ip2), HTONS((ip3 << 8) | ip4)}, \
-	{HTONS((nm1 << 8) | nm2), HTONS((nm3 << 8) | nm4)}, \
+        {HTONS((ip1 << 8) | ip2), HTONS((ip3 << 8) | ip4)}, \
+        {HTONS((nm1 << 8) | nm2), HTONS((nm3 << 8) | nm4)}, \
         outputfunc
 
 /**
diff --git a/src/uip/uip-neighbor.c b/src/uip/uip-neighbor.c
index 0c278cb3..93ad9a6a 100644
--- a/src/uip/uip-neighbor.c
+++ b/src/uip/uip-neighbor.c
@@ -91,8 +91,8 @@ uip_neighbor_add(uip_ipaddr_t ipaddr, struct uip_neighbor_addr *addr)
   u8_t oldest_time;
 
   /*printf("Adding neighbor with link address %02x:%02x:%02x:%02x:%02x:%02x\n",
-	 addr->addr.addr[0], addr->addr.addr[1], addr->addr.addr[2], addr->addr.addr[3],
-	 addr->addr.addr[4], addr->addr.addr[5]);*/
+         addr->addr.addr[0], addr->addr.addr[1], addr->addr.addr[2], addr->addr.addr[3],
+         addr->addr.addr[4], addr->addr.addr[5]);*/
   
   /* Find the first unused entry or the oldest used entry. */
   oldest_time = 0;
@@ -151,8 +151,8 @@ uip_neighbor_lookup(uip_ipaddr_t ipaddr)
   e = find_entry(ipaddr);
   if(e != NULL) {
     /*    printf("Lookup neighbor with link address %02x:%02x:%02x:%02x:%02x:%02x\n",
-	   e->addr.addr.addr[0], e->addr.addr.addr[1], e->addr.addr.addr[2], e->addr.addr.addr[3],
-	   e->addr.addr.addr[4], e->addr.addr.addr[5]);*/
+           e->addr.addr.addr[0], e->addr.addr.addr[1], e->addr.addr.addr[2], e->addr.addr.addr[3],
+           e->addr.addr.addr[4], e->addr.addr.addr[5]);*/
 
     return &e->addr;
   }
diff --git a/src/uip/uip.c b/src/uip/uip.c
index 40785106..1971372a 100644
--- a/src/uip/uip.c
+++ b/src/uip/uip.c
@@ -129,52 +129,51 @@ static const uip_ipaddr_t all_zeroes_addr =
 
 #if UIP_FIXEDETHADDR
 const struct uip_eth_addr uip_ethaddr = {{UIP_ETHADDR0,
-					  UIP_ETHADDR1,
-					  UIP_ETHADDR2,
-					  UIP_ETHADDR3,
-					  UIP_ETHADDR4,
-					  UIP_ETHADDR5}};
+                                          UIP_ETHADDR1,
+                                          UIP_ETHADDR2,
+                                          UIP_ETHADDR3,
+                                          UIP_ETHADDR4,
+                                          UIP_ETHADDR5}};
 #else
 struct uip_eth_addr uip_ethaddr = {{0,0,0,0,0,0}};
 #endif
 
 #ifndef UIP_CONF_EXTERNAL_BUFFER
 u8_t uip_buf[UIP_BUFSIZE + 2];   /* The packet buffer that contains
-				    incoming packets. */
+                                    incoming packets. */
 #endif /* UIP_CONF_EXTERNAL_BUFFER */
 
 void *uip_appdata;               /* The uip_appdata pointer points to
-				    application data. */
+                                    application data. */
 void *uip_sappdata;              /* The uip_appdata pointer points to
-				    the application data which is to
-				    be sent. */
+                                    the application data which is to
+                                    be sent. */
 #if UIP_URGDATA > 0
 void *uip_urgdata;               /* The uip_urgdata pointer points to
-   				    urgent data (out-of-band data), if
-   				    present. */
+                                    urgent data (out-of-band data), if
+                                    present. */
 u16_t uip_urglen, uip_surglen;
 #endif /* UIP_URGDATA > 0 */
 
-u16_t uip_len, uip_slen;
-                             /* The uip_len is either 8 or 16 bits,
-				depending on the maximum packet
-				size. */
+u16_t uip_len, uip_slen;     /* The uip_len is either 8 or 16 bits,
+                                depending on the maximum packet
+                                size. */
 
-u8_t uip_flags;     /* The uip_flags variable is used for
-				communication between the TCP/IP stack
-				and the application program. */
+u8_t uip_flags;              /* The uip_flags variable is used for
+                                communication between the TCP/IP stack
+                                and the application program. */
 
 #if UIP_TCP
 struct uip_conn *uip_conn;   /* uip_conn always points to the current
-				connection. */
+                                connection. */
 
 struct uip_conn uip_conns[UIP_CONNS];
                              /* The uip_conns array holds all TCP
-				connections. */
+                                connections. */
 u16_t uip_listenports[UIP_LISTENPORTS];
                              /* The uip_listenports list all currently
-				listning ports. */
-				
+                                listning ports. */
+                                
 u8_t uip_forced_poll;   // 1 if forcing the polling, 0 if the polling is not forced
 #endif /* UIP_TCP */
 
@@ -184,19 +183,19 @@ struct uip_udp_conn uip_udp_conns[UIP_UDP_CONNS];
 #endif /* UIP_UDP */
 
 static u16_t ipid;           /* Ths ipid variable is an increasing
-				number that is used for the IP ID
-				field. */
+                                number that is used for the IP ID
+                                field. */
 
 void uip_setipid(u16_t id) { ipid = id; }
 
 #if UIP_TCP
 static u8_t iss[4];          /* The iss variable is used for the TCP
-				initial sequence number. */
+                                initial sequence number. */
 #endif /* UIP_TCP */
 
 #if UIP_ACTIVE_OPEN
 static u16_t lastport;       /* Keeps track of the last port used for
-				a new connection. */
+                                a new connection. */
 #endif /* UIP_ACTIVE_OPEN */
 
 /* Temporary variables. */
@@ -290,7 +289,7 @@ uip_add32(u8_t *op32, u16_t op16)
     if(uip_acc32[2] == 0) {
       ++uip_acc32[1];
       if(uip_acc32[1] == 0) {
-	++uip_acc32[0];
+        ++uip_acc32[0];
       }
     }
   }
@@ -310,11 +309,11 @@ chksum(u16_t sum, const u8_t *data, u16_t len)
   dataptr = data;
   last_byte = data + len - 1;
   
-  while(dataptr < last_byte) {	/* At least two more bytes */
+  while(dataptr < last_byte) {  /* At least two more bytes */
     t = (dataptr[0] << 8) + dataptr[1];
     sum += t;
     if(sum < t) {
-      sum++;		/* carry */
+      sum++;            /* carry */
     }
     dataptr += 2;
   }
@@ -323,7 +322,7 @@ chksum(u16_t sum, const u8_t *data, u16_t len)
     t = (dataptr[0] << 8) + 0;
     sum += t;
     if(sum < t) {
-      sum++;		/* carry */
+      sum++;            /* carry */
     }
   }
 
@@ -371,7 +370,7 @@ upper_layer_chksum(u8_t proto)
 
   /* Sum TCP header and data. */
   sum = chksum(sum, &uip_buf[UIP_IPH_LEN + UIP_LLH_LEN],
-	       upper_layer_len);
+               upper_layer_len);
     
   return (sum == 0) ? 0xffff : htons(sum);
 }
@@ -496,8 +495,8 @@ uip_connect(uip_ipaddr_t *ripaddr, u16_t rport)
     }
     if(cconn->tcpstateflags == UIP_TIME_WAIT) {
       if(conn == 0 ||
-	 cconn->timer > conn->timer) {
-	conn = cconn;
+         cconn->timer > conn->timer) {
+        conn = cconn;
       }
     }
   }
@@ -606,7 +605,7 @@ uip_listen(u16_t port)
 static u8_t uip_reassbuf[UIP_REASS_BUFSIZE];
 static u8_t uip_reassbitmap[UIP_REASS_BUFSIZE / (8 * 8)];
 static const u8_t bitmap_bits[8] = {0xff, 0x7f, 0x3f, 0x1f,
-				    0x0f, 0x07, 0x03, 0x01};
+                                    0x0f, 0x07, 0x03, 0x01};
 static u16_t uip_reasslen;
 static u8_t uip_reassflags;
 #define UIP_REASS_FLAG_LASTFRAG 0x01
@@ -655,28 +654,28 @@ uip_reass(void)
     /* Copy the fragment into the reassembly buffer, at the right
        offset. */
     memcpy(&uip_reassbuf[UIP_IPH_LEN + offset],
-	   (char *)BUF + (int)((BUF->vhl & 0x0f) * 4),
-	   len);
+           (char *)BUF + (int)((BUF->vhl & 0x0f) * 4),
+           len);
       
     /* Update the bitmap. */
     if(offset / (8 * 8) == (offset + len) / (8 * 8)) {
       /* If the two endpoints are in the same byte, we only update
-	 that byte. */
-	     
+         that byte. */
+             
       uip_reassbitmap[offset / (8 * 8)] |=
-	     bitmap_bits[(offset / 8 ) & 7] &
-	     ~bitmap_bits[((offset + len) / 8 ) & 7];
+             bitmap_bits[(offset / 8 ) & 7] &
+             ~bitmap_bits[((offset + len) / 8 ) & 7];
     } else {
       /* If the two endpoints are in different bytes, we update the
-	 bytes in the endpoints and fill the stuff inbetween with
-	 0xff. */
+         bytes in the endpoints and fill the stuff inbetween with
+         0xff. */
       uip_reassbitmap[offset / (8 * 8)] |=
-	bitmap_bits[(offset / 8 ) & 7];
+        bitmap_bits[(offset / 8 ) & 7];
       for(i = 1 + offset / (8 * 8); i < (offset + len) / (8 * 8); ++i) {
-	uip_reassbitmap[i] = 0xff;
+        uip_reassbitmap[i] = 0xff;
       }
       uip_reassbitmap[(offset + len) / (8 * 8)] |=
-	~bitmap_bits[((offset + len) / 8 ) & 7];
+        ~bitmap_bits[((offset + len) / 8 ) & 7];
     }
     
     /* If this fragment has the More Fragments flag set to zero, we
@@ -695,27 +694,27 @@ uip_reass(void)
        in the bitmap are set. */
     if(uip_reassflags & UIP_REASS_FLAG_LASTFRAG) {
       /* Check all bytes up to and including all but the last byte in
-	 the bitmap. */
+         the bitmap. */
       for(i = 0; i < uip_reasslen / (8 * 8) - 1; ++i) {
-	if(uip_reassbitmap[i] != 0xff) {
-	  goto nullreturn;
-	}
+        if(uip_reassbitmap[i] != 0xff) {
+          goto nullreturn;
+        }
       }
       /* Check the last byte in the bitmap. It should contain just the
-	 right amount of bits. */
+         right amount of bits. */
       if(uip_reassbitmap[uip_reasslen / (8 * 8)] !=
-	 (u8_t)~bitmap_bits[uip_reasslen / 8 & 7]) {
-	goto nullreturn;
+         (u8_t)~bitmap_bits[uip_reasslen / 8 & 7]) {
+        goto nullreturn;
       }
 
       /* If we have come this far, we have a full packet in the
-	 buffer, so we allocate a pbuf and copy the packet into it. We
-	 also reset the timer. */
+         buffer, so we allocate a pbuf and copy the packet into it. We
+         also reset the timer. */
       uip_reasstmr = 0;
       memcpy(BUF, FBUF, uip_reasslen);
 
       /* Pretend to be a "normal" (i.e., not fragmented) IP packet
-	 from now on. */
+         from now on. */
       BUF->ipoffset[0] = BUF->ipoffset[1] = 0;
       BUF->len[0] = uip_reasslen >> 8;
       BUF->len[1] = uip_reasslen & 0xff;
@@ -764,9 +763,10 @@ uip_process(u8_t flag)
   if(flag == UIP_POLL_REQUEST) {
     if((uip_connr->tcpstateflags & UIP_TS_MASK) == UIP_ESTABLISHED &&
        !uip_outstanding(uip_connr)) {
-	uip_flags = UIP_POLL;
-	UIP_APPCALL();
-	goto appsend;
+        uip_flags = UIP_POLL;
+        uip_len = uip_slen = 0;
+        UIP_APPCALL();
+        goto appsend;
     }
     goto drop;
     
@@ -780,9 +780,9 @@ uip_process(u8_t flag)
     /* Increase the initial sequence number. */
     if(++iss[3] == 0) {
       if(++iss[2] == 0) {
-	if(++iss[1] == 0) {
-	  ++iss[0];
-	}
+        if(++iss[1] == 0) {
+          ++iss[0];
+        }
       }
     }
 
@@ -798,80 +798,80 @@ uip_process(u8_t flag)
        uip_connr->tcpstateflags == UIP_FIN_WAIT_2)) {
       ++(uip_connr->timer);
       if(uip_connr->timer == UIP_TIME_WAIT_TIMEOUT) {
-	uip_connr->tcpstateflags = UIP_CLOSED;
+        uip_connr->tcpstateflags = UIP_CLOSED;
       }
     } else if(uip_connr->tcpstateflags != UIP_CLOSED && uip_connr->tcpstateflags != UIP_RESERVED) {
       /* If the connection has outstanding data, we increase the
-	 connection's timer and see if it has reached the RTO value
-	 in which case we retransmit. */
+         connection's timer and see if it has reached the RTO value
+         in which case we retransmit. */
       if(uip_outstanding(uip_connr) && !uip_forced_poll) {
-	if(uip_connr->timer-- == 0) {
-	  if(uip_connr->nrtx == UIP_MAXRTX ||
-	     ((uip_connr->tcpstateflags == UIP_SYN_SENT ||
-	       uip_connr->tcpstateflags == UIP_SYN_RCVD) &&
-	      uip_connr->nrtx == UIP_MAXSYNRTX)) {
-	    uip_connr->tcpstateflags = UIP_CLOSED;
+        if(uip_connr->timer-- == 0) {
+          if(uip_connr->nrtx == UIP_MAXRTX ||
+             ((uip_connr->tcpstateflags == UIP_SYN_SENT ||
+               uip_connr->tcpstateflags == UIP_SYN_RCVD) &&
+              uip_connr->nrtx == UIP_MAXSYNRTX)) {
+            uip_connr->tcpstateflags = UIP_CLOSED;
 
-	    /* We call UIP_APPCALL() with uip_flags set to
-	       UIP_TIMEDOUT to inform the application that the
-	       connection has timed out. */
-	    uip_flags = UIP_TIMEDOUT;
-	    UIP_APPCALL();
+            /* We call UIP_APPCALL() with uip_flags set to
+               UIP_TIMEDOUT to inform the application that the
+               connection has timed out. */
+            uip_flags = UIP_TIMEDOUT;
+            UIP_APPCALL();
 
-	    /* We also send a reset packet to the remote host. */
-	    BUF->flags = TCP_RST | TCP_ACK;
-	    goto tcp_send_nodata;
-	  }
+            /* We also send a reset packet to the remote host. */
+            BUF->flags = TCP_RST | TCP_ACK;
+            goto tcp_send_nodata;
+          }
 
-	  /* Exponential backoff. */
-	  uip_connr->timer = UIP_RTO << (uip_connr->nrtx > 4?
-					 4:
-					 uip_connr->nrtx);
-	  ++(uip_connr->nrtx);
-	  
-	  /* Ok, so we need to retransmit. We do this differently
-	     depending on which state we are in. In ESTABLISHED, we
-	     call upon the application so that it may prepare the
-	     data for the retransmit. In SYN_RCVD, we resend the
-	     SYNACK that we sent earlier and in LAST_ACK we have to
-	     retransmit our FINACK. */
-	  UIP_STAT(++uip_stat.tcp.rexmit);
-	  switch(uip_connr->tcpstateflags & UIP_TS_MASK) {
-	  case UIP_SYN_RCVD:
-	    /* In the SYN_RCVD state, we should retransmit our
+          /* Exponential backoff. */
+          uip_connr->timer = UIP_RTO << (uip_connr->nrtx > 4?
+                                         4:
+                                         uip_connr->nrtx);
+          ++(uip_connr->nrtx);
+          
+          /* Ok, so we need to retransmit. We do this differently
+             depending on which state we are in. In ESTABLISHED, we
+             call upon the application so that it may prepare the
+             data for the retransmit. In SYN_RCVD, we resend the
+             SYNACK that we sent earlier and in LAST_ACK we have to
+             retransmit our FINACK. */
+          UIP_STAT(++uip_stat.tcp.rexmit);
+          switch(uip_connr->tcpstateflags & UIP_TS_MASK) {
+          case UIP_SYN_RCVD:
+            /* In the SYN_RCVD state, we should retransmit our
                SYNACK. */
-	    goto tcp_send_synack;
-	    
+            goto tcp_send_synack;
+            
 #if UIP_ACTIVE_OPEN
-	  case UIP_SYN_SENT:
-	    /* In the SYN_SENT state, we retransmit out SYN. */
-	    BUF->flags = 0;
-	    goto tcp_send_syn;
+          case UIP_SYN_SENT:
+            /* In the SYN_SENT state, we retransmit out SYN. */
+            BUF->flags = 0;
+            goto tcp_send_syn;
 #endif /* UIP_ACTIVE_OPEN */
-	    
-	  case UIP_ESTABLISHED:
-	    /* In the ESTABLISHED state, we call upon the application
+            
+          case UIP_ESTABLISHED:
+            /* In the ESTABLISHED state, we call upon the application
                to do the actual retransmit after which we jump into
                the code for sending out the packet (the apprexmit
                label). */
-	    uip_flags = UIP_REXMIT;
-	    UIP_APPCALL();
-	    goto apprexmit;
-	    
-	  case UIP_FIN_WAIT_1:
-	  case UIP_CLOSING:
-	  case UIP_LAST_ACK:
-	    /* In all these states we should retransmit a FINACK. */
-	    goto tcp_send_finack;
-	    
-	  }
-	}
+            uip_flags = UIP_REXMIT;
+            UIP_APPCALL();
+            goto apprexmit;
+            
+          case UIP_FIN_WAIT_1:
+          case UIP_CLOSING:
+          case UIP_LAST_ACK:
+            /* In all these states we should retransmit a FINACK. */
+            goto tcp_send_finack;
+            
+          }
+        }
       } else if((uip_connr->tcpstateflags & UIP_TS_MASK) == UIP_ESTABLISHED) {
-	/* If there was no need for a retransmission, we poll the
+        /* If there was no need for a retransmission, we poll the
            application for new data. */
-	uip_flags = UIP_POLL;
-	UIP_APPCALL();
-	goto appsend;
+        uip_flags = UIP_POLL;
+        UIP_APPCALL();
+        goto appsend;
       }
     }
     goto drop;
@@ -928,14 +928,14 @@ uip_process(u8_t flag)
     uip_len = (BUF->len[0] << 8) + BUF->len[1];
 #if UIP_CONF_IPV6
     uip_len += 40; /* The length reported in the IPv6 header is the
-		      length of the payload that follows the
-		      header. However, uIP uses the uip_len variable
-		      for holding the size of the entire packet,
-		      including the IP header. For IPv4 this is not a
-		      problem as the length field in the IPv4 header
-		      contains the length of the entire packet. But
-		      for IPv6 we need to add the size of the IPv6
-		      header (40 bytes). */
+                      length of the payload that follows the
+                      header. However, uIP uses the uip_len variable
+                      for holding the size of the entire packet,
+                      including the IP header. For IPv4 this is not a
+                      problem as the length field in the IPv4 header
+                      contains the length of the entire packet. But
+                      for IPv6 we need to add the size of the IPv6
+                      header (40 bytes). */
 #endif /* UIP_CONF_IPV6 */
   } else {
     UIP_LOG("ip: packet shorter than reported in IP header.");
@@ -982,7 +982,7 @@ uip_process(u8_t flag)
     if(BUF->proto == UIP_PROTO_UDP &&
        uip_ipaddr_cmp(BUF->destipaddr, all_ones_addr)
        /*&&
-	 uip_ipchksum() == 0xffff*/) {
+         uip_ipchksum() == 0xffff*/) {
       goto udp_input;
     }
 #endif /* UIP_BROADCAST */
@@ -1009,7 +1009,7 @@ uip_process(u8_t flag)
 
 #if !UIP_CONF_IPV6
   if(uip_ipchksum() != 0xffff) { /* Compute and check the IP header
-				    checksum. */
+                                    checksum. */
     UIP_STAT(++uip_stat.ip.drop);
     UIP_STAT(++uip_stat.ip.chkerr);
     UIP_LOG("ip: bad checksum.");
@@ -1019,8 +1019,8 @@ uip_process(u8_t flag)
 
 #if UIP_TCP
   if(BUF->proto == UIP_PROTO_TCP) { /* Check for TCP packet. If so,
-				       proceed with TCP input
-				       processing. */
+                                       proceed with TCP input
+                                       processing. */
     goto tcp_input;
   }
 #endif /* UIP_TCP */
@@ -1034,7 +1034,7 @@ uip_process(u8_t flag)
 #if !UIP_CONF_IPV6
   /* ICMPv4 processing code follows. */
   if(BUF->proto != UIP_PROTO_ICMP) { /* We only allow ICMP packets from
-					here. */
+                                        here. */
     UIP_STAT(++uip_stat.ip.drop);
     UIP_STAT(++uip_stat.ip.protoerr);
     UIP_LOG("ip: neither tcp nor icmp.");
@@ -1088,7 +1088,7 @@ uip_process(u8_t flag)
   DEBUG_PRINTF("icmp6_input: length %d\n", uip_len);
 
   if(BUF->proto != UIP_PROTO_ICMP6) { /* We only allow ICMPv6 packets from
-					 here. */
+                                         here. */
     UIP_STAT(++uip_stat.ip.drop);
     UIP_STAT(++uip_stat.ip.protoerr);
     UIP_LOG("ip: neither tcp nor icmp6.");
@@ -1103,12 +1103,12 @@ uip_process(u8_t flag)
     if(uip_ipaddr_cmp(ICMPBUF->icmp6data, uip_hostaddr)) {
 
       if(ICMPBUF->options[0] == ICMP6_OPTION_SOURCE_LINK_ADDRESS) {
-	/* Save the sender's address in our neighbor list. */
-	uip_neighbor_add(ICMPBUF->srcipaddr, &(ICMPBUF->options[2]));
+        /* Save the sender's address in our neighbor list. */
+        uip_neighbor_add(ICMPBUF->srcipaddr, &(ICMPBUF->options[2]));
       }
       
       /* We should now send a neighbor advertisement back to where the
-	 neighbor solicication came from. */
+         neighbor solicication came from. */
       ICMPBUF->type = ICMP6_NEIGHBOR_ADVERTISEMENT;
       ICMPBUF->flags = ICMP6_FLAG_S; /* Solicited flag. */
       
@@ -1188,8 +1188,8 @@ uip_process(u8_t flag)
         UDPBUF->srcport == uip_udp_conn->rport ||
         uip_udp_conn->rport == HTONS(69)) &&
        (uip_ipaddr_cmp(uip_udp_conn->ripaddr, all_zeroes_addr) ||
-	uip_ipaddr_cmp(uip_udp_conn->ripaddr, all_ones_addr) ||
-	uip_ipaddr_cmp(BUF->srcipaddr, uip_udp_conn->ripaddr))) {
+        uip_ipaddr_cmp(uip_udp_conn->ripaddr, all_ones_addr) ||
+        uip_ipaddr_cmp(BUF->srcipaddr, uip_udp_conn->ripaddr))) {
       goto udp_found;
     }
   }
@@ -1197,6 +1197,7 @@ uip_process(u8_t flag)
   goto drop;
   
  udp_found:
+  UIP_STAT(++uip_stat.udp.recv);
 #if UIP_TCP
   uip_conn = NULL;
 #endif /* UIP_TCP */
@@ -1232,7 +1233,7 @@ uip_process(u8_t flag)
   uip_ipaddr_copy(BUF->srcipaddr, uip_hostaddr);
   uip_ipaddr_copy(BUF->destipaddr, uip_udp_conn->ripaddr);
    
-  uip_appdata = &uip_buf[UIP_LLH_LEN + UIP_IPTCPH_LEN];
+  uip_appdata = &uip_buf[UIP_LLH_LEN + UIP_IPUDPH_LEN];
 
 #if UIP_UDP_CHECKSUMS
   /* Calculate UDP checksum. */
@@ -1242,6 +1243,7 @@ uip_process(u8_t flag)
   }
 #endif /* UIP_UDP_CHECKSUMS */
   
+  UIP_STAT(++uip_stat.udp.sent);
   goto ip_send_nolen;
 #endif /* UIP_UDP */
   
@@ -1253,7 +1255,7 @@ uip_process(u8_t flag)
   /* Start of TCP input header processing code. */
   
   if(uip_tcpchksum() != 0xffff) {   /* Compute and check the TCP
-				       checksum. */
+                                       checksum. */
     UIP_STAT(++uip_stat.tcp.drop);
     UIP_STAT(++uip_stat.tcp.chkerr);
     UIP_LOG("tcp: bad checksum.");
@@ -1269,6 +1271,10 @@ uip_process(u8_t flag)
        BUF->destport == uip_connr->lport &&
        BUF->srcport == uip_connr->rport &&
        uip_ipaddr_cmp(BUF->srcipaddr, uip_connr->ripaddr)) {
+      if ((uip_connr->tcpstateflags != UIP_SYN_RCVD) &&
+          (BUF->flags & TCP_CTL) == TCP_SYN) {
+        goto reset;
+      }
       goto found;
     }
   }
@@ -1326,7 +1332,7 @@ uip_process(u8_t flag)
   if(++BUF->ackno[3] == 0) {
     if(++BUF->ackno[2] == 0) {
       if(++BUF->ackno[1] == 0) {
-	++BUF->ackno[0];
+        ++BUF->ackno[0];
       }
     }
   }
@@ -1361,8 +1367,8 @@ uip_process(u8_t flag)
     }
     if(uip_conns[c].tcpstateflags == UIP_TIME_WAIT) {
       if(uip_connr == 0 ||
-	 uip_conns[c].timer > uip_connr->timer) {
-	uip_connr = &uip_conns[c];
+         uip_conns[c].timer > uip_connr->timer) {
+        uip_connr = &uip_conns[c];
       }
     }
   }
@@ -1405,30 +1411,30 @@ uip_process(u8_t flag)
     for(c = 0; c < ((BUF->tcpoffset >> 4) - 5) << 2 ;) {
       opt = uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + c];
       if(opt == TCP_OPT_END) {
-	/* End of options. */
-	break;
+        /* End of options. */
+        break;
       } else if(opt == TCP_OPT_NOOP) {
-	++c;
-	/* NOP option. */
+        ++c;
+        /* NOP option. */
       } else if(opt == TCP_OPT_MSS &&
-		uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == TCP_OPT_MSS_LEN) {
-	/* An MSS option with the right option length. */
-	tmp16 = ((u16_t)uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 2 + c] << 8) |
-	  (u16_t)uip_buf[UIP_IPTCPH_LEN + UIP_LLH_LEN + 3 + c];
-	uip_connr->initialmss = uip_connr->mss =
-	  tmp16 > UIP_TCP_MSS? UIP_TCP_MSS: tmp16;
-	
-	/* And we are done processing options. */
-	break;
+                uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == TCP_OPT_MSS_LEN) {
+        /* An MSS option with the right option length. */
+        tmp16 = ((u16_t)uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 2 + c] << 8) |
+          (u16_t)uip_buf[UIP_IPTCPH_LEN + UIP_LLH_LEN + 3 + c];
+        uip_connr->initialmss = uip_connr->mss =
+          tmp16 > UIP_TCP_MSS? UIP_TCP_MSS: tmp16;
+        
+        /* And we are done processing options. */
+        break;
       } else {
-	/* All other options have a length field, so that we easily
-	   can skip past them. */
-	if(uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0) {
-	  /* If the length field is zero, the options are malformed
-	     and we don't process them further. */
-	  break;
-	}
-	c += uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c];
+        /* All other options have a length field, so that we easily
+           can skip past them. */
+        if(uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0) {
+          /* If the length field is zero, the options are malformed
+             and we don't process them further. */
+          break;
+        }
+        c += uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c];
       }
     }
   }
@@ -1480,14 +1486,18 @@ uip_process(u8_t flag)
 
   /* First, check if the sequence number of the incoming packet is
      what we're expecting next. If not, we send out an ACK with the
-     correct numbers in. */
-  if(!(((uip_connr->tcpstateflags & UIP_TS_MASK) == UIP_SYN_SENT) &&
-       ((BUF->flags & TCP_CTL) == (TCP_SYN | TCP_ACK)))) {
+     correct numbers in, unless we are in the SYN_RCVD state and
+     receive a SYN, in which case we should retransmit our SYNACK
+     (which is done futher down). */
+  if(!((((uip_connr->tcpstateflags & UIP_TS_MASK) == UIP_SYN_SENT) &&
+        ((BUF->flags & TCP_CTL) == (TCP_SYN | TCP_ACK))) ||
+       (((uip_connr->tcpstateflags & UIP_TS_MASK) == UIP_SYN_RCVD) &&
+        ((BUF->flags & TCP_CTL) == TCP_SYN)))) {
     if((uip_len > 0 || ((BUF->flags & (TCP_SYN | TCP_FIN)) != 0)) &&
        (BUF->seqno[0] != uip_connr->rcv_nxt[0] ||
-	BUF->seqno[1] != uip_connr->rcv_nxt[1] ||
-	BUF->seqno[2] != uip_connr->rcv_nxt[2] ||
-	BUF->seqno[3] != uip_connr->rcv_nxt[3])) {
+        BUF->seqno[1] != uip_connr->rcv_nxt[1] ||
+        BUF->seqno[2] != uip_connr->rcv_nxt[2] ||
+        BUF->seqno[3] != uip_connr->rcv_nxt[3])) {
       goto tcp_send_ack;
     }
   }
@@ -1508,21 +1518,21 @@ uip_process(u8_t flag)
       uip_connr->snd_nxt[1] = uip_acc32[1];
       uip_connr->snd_nxt[2] = uip_acc32[2];
       uip_connr->snd_nxt[3] = uip_acc32[3];
-	
+        
 
       /* Do RTT estimation, unless we have done retransmissions. */
       if(uip_connr->nrtx == 0) {
-	signed char m;
-	m = uip_connr->rto - uip_connr->timer;
-	/* This is taken directly from VJs original code in his paper */
-	m = m - (uip_connr->sa >> 3);
-	uip_connr->sa += m;
-	if(m < 0) {
-	  m = -m;
-	}
-	m = m - (uip_connr->sv >> 2);
-	uip_connr->sv += m;
-	uip_connr->rto = (uip_connr->sa >> 3) + uip_connr->sv;
+        signed char m;
+        m = uip_connr->rto - uip_connr->timer;
+        /* This is taken directly from VJs original code in his paper */
+        m = m - (uip_connr->sa >> 3);
+        uip_connr->sa += m;
+        if(m < 0) {
+          m = -m;
+        }
+        m = m - (uip_connr->sv >> 2);
+        uip_connr->sv += m;
+        uip_connr->rto = (uip_connr->sa >> 3) + uip_connr->sv;
 
       }
       /* Set the acknowledged flag. */
@@ -1539,9 +1549,9 @@ uip_process(u8_t flag)
   /* Do different things depending on in what state the connection is. */
   switch(uip_connr->tcpstateflags & UIP_TS_MASK) {
     /* CLOSED and LISTEN are not handled here. CLOSE_WAIT is not
-	implemented, since we force the application to close when the
-	peer sends a FIN (hence the application goes directly from
-	ESTABLISHED to LAST_ACK). */
+        implemented, since we force the application to close when the
+        peer sends a FIN (hence the application goes directly from
+        ESTABLISHED to LAST_ACK). */
   case UIP_SYN_RCVD:
     /* In SYN_RCVD we have sent out a SYNACK in response to a SYN, and
        we are waiting for an ACK that acknowledges the data we sent
@@ -1559,6 +1569,10 @@ uip_process(u8_t flag)
       UIP_APPCALL();
       goto appsend;
     }
+    /* We need to retransmit the SYNACK */
+    if((BUF->flags & TCP_CTL) == TCP_SYN) {
+      goto tcp_send_synack;
+    }
     goto drop;
 #if UIP_ACTIVE_OPEN
   case UIP_SYN_SENT:
@@ -1571,35 +1585,35 @@ uip_process(u8_t flag)
 
       /* Parse the TCP MSS option, if present. */
       if((BUF->tcpoffset & 0xf0) > 0x50) {
-	for(c = 0; c < ((BUF->tcpoffset >> 4) - 5) << 2 ;) {
-	  opt = uip_buf[UIP_IPTCPH_LEN + UIP_LLH_LEN + c];
-	  if(opt == TCP_OPT_END) {
-	    /* End of options. */
-	    break;
-	  } else if(opt == TCP_OPT_NOOP) {
-	    ++c;
-	    /* NOP option. */
-	  } else if(opt == TCP_OPT_MSS &&
-		    uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == TCP_OPT_MSS_LEN) {
-	    /* An MSS option with the right option length. */
-	    tmp16 = (uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 2 + c] << 8) |
-	      uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 3 + c];
-	    uip_connr->initialmss =
-	      uip_connr->mss = tmp16 > UIP_TCP_MSS? UIP_TCP_MSS: tmp16;
+        for(c = 0; c < ((BUF->tcpoffset >> 4) - 5) << 2 ;) {
+          opt = uip_buf[UIP_IPTCPH_LEN + UIP_LLH_LEN + c];
+          if(opt == TCP_OPT_END) {
+            /* End of options. */
+            break;
+          } else if(opt == TCP_OPT_NOOP) {
+            ++c;
+            /* NOP option. */
+          } else if(opt == TCP_OPT_MSS &&
+                    uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == TCP_OPT_MSS_LEN) {
+            /* An MSS option with the right option length. */
+            tmp16 = (uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 2 + c] << 8) |
+              uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 3 + c];
+            uip_connr->initialmss =
+              uip_connr->mss = tmp16 > UIP_TCP_MSS? UIP_TCP_MSS: tmp16;
 
-	    /* And we are done processing options. */
-	    break;
-	  } else {
-	    /* All other options have a length field, so that we easily
-	       can skip past them. */
-	    if(uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0) {
-	      /* If the length field is zero, the options are malformed
-		 and we don't process them further. */
-	      break;
-	    }
-	    c += uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c];
-	  }
-	}
+            /* And we are done processing options. */
+            break;
+          } else {
+            /* All other options have a length field, so that we easily
+               can skip past them. */
+            if(uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0) {
+              /* If the length field is zero, the options are malformed
+                 and we don't process them further. */
+              break;
+            }
+            c += uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c];
+          }
+        }
       }
       uip_connr->tcpstateflags = UIP_ESTABLISHED;
       uip_connr->rcv_nxt[0] = BUF->seqno[0];
@@ -1636,12 +1650,12 @@ uip_process(u8_t flag)
 
     if(BUF->flags & TCP_FIN && !(uip_connr->tcpstateflags & UIP_STOPPED)) {
       if(uip_outstanding(uip_connr)) {
-	goto drop;
+        goto drop;
       }
       uip_add_rcv_nxt(1 + uip_len);
       uip_flags |= UIP_CLOSE;
       if(uip_len > 0) {
-	uip_flags |= UIP_NEWDATA;
+        uip_flags |= UIP_NEWDATA;
       }
       UIP_APPCALL();
       uip_connr->len = 1;
@@ -1658,8 +1672,8 @@ uip_process(u8_t flag)
 #if UIP_URGDATA > 0
       uip_urglen = (BUF->urgp[0] << 8) | BUF->urgp[1];
       if(uip_urglen > uip_len) {
-	/* There is more urgent data in the next segment to come. */
-	uip_urglen = uip_len;
+        /* There is more urgent data in the next segment to come. */
+        uip_urglen = uip_len;
       }
       uip_add_rcv_nxt(uip_urglen);
       uip_len -= uip_urglen;
@@ -1725,52 +1739,52 @@ uip_process(u8_t flag)
     appsend:
       
       if(uip_flags & UIP_ABORT) {
-	uip_slen = 0;
-	uip_connr->tcpstateflags = UIP_CLOSED;
-	BUF->flags = TCP_RST | TCP_ACK;
-	goto tcp_send_nodata;
+        uip_slen = 0;
+        uip_connr->tcpstateflags = UIP_CLOSED;
+        BUF->flags = TCP_RST | TCP_ACK;
+        goto tcp_send_nodata;
       }
 
       if(uip_flags & UIP_CLOSE) {
-	uip_slen = 0;
-	uip_connr->len = 1;
-	uip_connr->tcpstateflags = UIP_FIN_WAIT_1;
-	uip_connr->nrtx = 0;
-	BUF->flags = TCP_FIN | TCP_ACK;
-	goto tcp_send_nodata;
+        uip_slen = 0;
+        uip_connr->len = 1;
+        uip_connr->tcpstateflags = UIP_FIN_WAIT_1;
+        uip_connr->nrtx = 0;
+        BUF->flags = TCP_FIN | TCP_ACK;
+        goto tcp_send_nodata;
       }
 
       /* If uip_slen > 0, the application has data to be sent. */
       if(uip_slen > 0) {
 
-	/* If the connection has acknowledged data, the contents of
-	   the ->len variable should be discarded. */
-	if((uip_flags & UIP_ACKDATA) != 0) {
-	  uip_connr->len = 0;
-	}
+        /* If the connection has acknowledged data, the contents of
+           the ->len variable should be discarded. */
+        if((uip_flags & UIP_ACKDATA) != 0) {
+          uip_connr->len = 0;
+        }
 
-	/* If the ->len variable is non-zero the connection has
-	   already data in transit and cannot send anymore right
-	   now. */
-	if(uip_connr->len == 0) {
+        /* If the ->len variable is non-zero the connection has
+           already data in transit and cannot send anymore right
+           now. */
+        if(uip_connr->len == 0) {
 
-	  /* The application cannot send more than what is allowed by
-	     the mss (the minumum of the MSS and the available
-	     window). */
-	  if(uip_slen > uip_connr->mss) {
-	    uip_slen = uip_connr->mss;
-	  }
+          /* The application cannot send more than what is allowed by
+             the mss (the minumum of the MSS and the available
+             window). */
+          if(uip_slen > uip_connr->mss) {
+            uip_slen = uip_connr->mss;
+          }
 
-	  /* Remember how much data we send out now so that we know
-	     when everything has been acknowledged. */
-	  uip_connr->len = uip_slen;
-	} else {
+          /* Remember how much data we send out now so that we know
+             when everything has been acknowledged. */
+          uip_connr->len = uip_slen;
+        } else {
 
-	  /* If the application already had unacknowledged data, we
-	     make sure that the application does not send (i.e.,
-	     retransmit) out more than it previously sent out. */
-	  uip_slen = uip_connr->len;
-	}
+          /* If the application already had unacknowledged data, we
+             make sure that the application does not send (i.e.,
+             retransmit) out more than it previously sent out. */
+          uip_slen = uip_connr->len;
+        }
       }
       uip_connr->nrtx = 0;
     apprexmit:
@@ -1779,19 +1793,19 @@ uip_process(u8_t flag)
       /* If the application has data to be sent, or if the incoming
          packet had new data in it, we must send out a packet. */
       if(uip_slen > 0 && uip_connr->len > 0) {
-	/* Add the length of the IP and TCP headers. */
-	uip_len = uip_connr->len + UIP_TCPIP_HLEN;
-	/* We always set the ACK flag in response packets. */
-	BUF->flags = TCP_ACK | TCP_PSH;
-	/* Send the packet. */
-	goto tcp_send_noopts;
+        /* Add the length of the IP and TCP headers. */
+        uip_len = uip_connr->len + UIP_TCPIP_HLEN;
+        /* We always set the ACK flag in response packets. */
+        BUF->flags = TCP_ACK | TCP_PSH;
+        /* Send the packet. */
+        goto tcp_send_noopts;
       }
       /* If there is no data to send, just send out a pure ACK if
-	 there is newdata. */
+         there is newdata. */
       if(uip_flags & UIP_NEWDATA) {
-	uip_len = UIP_TCPIP_HLEN;
-	BUF->flags = TCP_ACK;
-	goto tcp_send_noopts;
+        uip_len = UIP_TCPIP_HLEN;
+        BUF->flags = TCP_ACK;
+        goto tcp_send_noopts;
       }
     }
     goto drop;
@@ -1814,11 +1828,11 @@ uip_process(u8_t flag)
     }
     if(BUF->flags & TCP_FIN) {
       if(uip_flags & UIP_ACKDATA) {
-	uip_connr->tcpstateflags = UIP_TIME_WAIT;
-	uip_connr->timer = 0;
-	uip_connr->len = 0;
+        uip_connr->tcpstateflags = UIP_TIME_WAIT;
+        uip_connr->timer = 0;
+        uip_connr->len = 0;
       } else {
-	uip_connr->tcpstateflags = UIP_CLOSING;
+        uip_connr->tcpstateflags = UIP_CLOSING;
       }
       uip_add_rcv_nxt(1);
       uip_flags = UIP_CLOSE;
@@ -1944,7 +1958,7 @@ uip_process(u8_t flag)
   UIP_STAT(++uip_stat.tcp.sent);
  send:
   DEBUG_PRINTF("Sending packet with length %d (%d)\n", uip_len,
-	       (BUF->len[0] << 8) | BUF->len[1]);
+               (BUF->len[0] << 8) | BUF->len[1]);
   
   UIP_STAT(++uip_stat.ip.sent);
   /* Return and let the caller do the actual transmission. */
diff --git a/src/uip/uip.h b/src/uip/uip.h
index 3a9e2e7b..cd65b4ab 100644
--- a/src/uip/uip.h
+++ b/src/uip/uip.h
@@ -242,12 +242,12 @@ void uip_setipid(u16_t id);
       uip_input();
       if(uip_len > 0) {
         uip_arp_out();
-	ethernet_devicedriver_send();
+        ethernet_devicedriver_send();
       }
     } else if(BUF->type == HTONS(UIP_ETHTYPE_ARP)) {
       uip_arp_arpin();
       if(uip_len > 0) {
-	ethernet_devicedriver_send();
+        ethernet_devicedriver_send();
       }
     }
  \endcode
@@ -926,7 +926,7 @@ struct uip_udp_conn *uip_udp_new(uip_ipaddr_t *ripaddr, u16_t rport);
  */
 #if !UIP_CONF_IPV6
 #define uip_ipaddr_cmp(addr1, addr2) (((u16_t *)addr1)[0] == ((u16_t *)addr2)[0] && \
-				      ((u16_t *)addr1)[1] == ((u16_t *)addr2)[1])
+                                      ((u16_t *)addr1)[1] == ((u16_t *)addr2)[1])
 #else /* !UIP_CONF_IPV6 */
 #define uip_ipaddr_cmp(addr1, addr2) (memcmp(addr1, addr2, sizeof(uip_ip6addr_t)) == 0)
 #endif /* !UIP_CONF_IPV6 */
@@ -1173,26 +1173,26 @@ struct uip_conn {
   
   u16_t lport;        /**< The local TCP port, in network byte order. */
   u16_t rport;        /**< The local remote TCP port, in network byte
-			 order. */
+                         order. */
   
   u8_t rcv_nxt[4];    /**< The sequence number that we expect to
-			 receive next. */
+                         receive next. */
   u8_t snd_nxt[4];    /**< The sequence number that was last sent by
                          us. */
   u16_t len;          /**< Length of the data that was previously sent. */
   u16_t mss;          /**< Current maximum segment size for the
-			 connection. */
+                         connection. */
   u16_t initialmss;   /**< Initial maximum segment size for the
-			 connection. */
+                         connection. */
   u8_t sa;            /**< Retransmission time-out calculation state
-			 variable. */
+                         variable. */
   u8_t sv;            /**< Retransmission time-out calculation state
-			 variable. */
+                         variable. */
   u8_t rto;           /**< Retransmission time-out. */
   u8_t tcpstateflags; /**< TCP state and flags. */
   u8_t timer;         /**< The retransmission timer. */
   u8_t nrtx;          /**< The number of retransmissions for the last
-			 segment sent. */
+                         segment sent. */
 
   /** The application state. */
   uip_tcp_appstate_t appstate;
@@ -1253,30 +1253,30 @@ extern struct uip_udp_conn uip_udp_conns[UIP_UDP_CONNS];
 struct uip_stats {
   struct {
     uip_stats_t drop;     /**< Number of dropped packets at the IP
-			     layer. */
+                             layer. */
     uip_stats_t recv;     /**< Number of received packets at the IP
-			     layer. */
+                             layer. */
     uip_stats_t sent;     /**< Number of sent packets at the IP
-			     layer. */
+                             layer. */
     uip_stats_t vhlerr;   /**< Number of packets dropped due to wrong
-			     IP version or header length. */
+                             IP version or header length. */
     uip_stats_t hblenerr; /**< Number of packets dropped due to wrong
-			     IP length, high byte. */
+                             IP length, high byte. */
     uip_stats_t lblenerr; /**< Number of packets dropped due to wrong
-			     IP length, low byte. */
+                             IP length, low byte. */
     uip_stats_t fragerr;  /**< Number of packets dropped since they
-			     were IP fragments. */
+                             were IP fragments. */
     uip_stats_t chkerr;   /**< Number of packets dropped due to IP
-			     checksum errors. */
+                             checksum errors. */
     uip_stats_t protoerr; /**< Number of packets dropped since they
-			     were neither ICMP, UDP nor TCP. */
+                             were neither ICMP, UDP nor TCP. */
   } ip;                   /**< IP statistics. */
   struct {
     uip_stats_t drop;     /**< Number of dropped ICMP packets. */
     uip_stats_t recv;     /**< Number of received ICMP packets. */
     uip_stats_t sent;     /**< Number of sent ICMP packets. */
     uip_stats_t typeerr;  /**< Number of ICMP packets with a wrong
-			     type. */
+                             type. */
   } icmp;                 /**< ICMP statistics. */
 #if UIP_TCP
   struct {
@@ -1284,15 +1284,15 @@ struct uip_stats {
     uip_stats_t recv;     /**< Number of recived TCP segments. */
     uip_stats_t sent;     /**< Number of sent TCP segments. */
     uip_stats_t chkerr;   /**< Number of TCP segments with a bad
-			     checksum. */
+                             checksum. */
     uip_stats_t ackerr;   /**< Number of TCP segments with a bad ACK
-			     number. */
+                             number. */
     uip_stats_t rst;      /**< Number of recevied TCP RST (reset) segments. */
     uip_stats_t rexmit;   /**< Number of retransmitted TCP segments. */
     uip_stats_t syndrop;  /**< Number of dropped SYNs due to too few
-			     connections was avaliable. */
+                             connections was avaliable. */
     uip_stats_t synrst;   /**< Number of SYNs for closed ports,
-			     triggering a RST. */
+                             triggering a RST. */
   } tcp;                  /**< TCP statistics. */
 #endif /* UIP_TCP */
 #if UIP_UDP
@@ -1301,7 +1301,7 @@ struct uip_stats {
     uip_stats_t recv;     /**< Number of recived UDP segments. */
     uip_stats_t sent;     /**< Number of sent UDP segments. */
     uip_stats_t chkerr;   /**< Number of UDP segments with a bad
-			     checksum. */
+                             checksum. */
   } udp;                  /**< UDP statistics. */
 #endif /* UIP_UDP */
 };
@@ -1335,33 +1335,33 @@ extern u8_t uip_flags;
    functions/macros. */
 
 #define UIP_ACKDATA   1     /* Signifies that the outstanding data was
-			       acked and the application should send
-			       out new data instead of retransmitting
-			       the last data. */
+                               acked and the application should send
+                               out new data instead of retransmitting
+                               the last data. */
 #define UIP_NEWDATA   2     /* Flags the fact that the peer has sent
-			       us new data. */
+                               us new data. */
 #define UIP_REXMIT    4     /* Tells the application to retransmit the
-			       data that was last sent. */
+                               data that was last sent. */
 #define UIP_POLL      8     /* Used for polling the application, to
-			       check if the application has data that
-			       it wants to send. */
+                               check if the application has data that
+                               it wants to send. */
 #define UIP_CLOSE     16    /* The remote host has closed the
-			       connection, thus the connection has
-			       gone away. Or the application signals
-			       that it wants to close the
-			       connection. */
+                               connection, thus the connection has
+                               gone away. Or the application signals
+                               that it wants to close the
+                               connection. */
 #define UIP_ABORT     32    /* The remote host has aborted the
-			       connection, thus the connection has
-			       gone away. Or the application signals
-			       that it wants to abort the
-			       connection. */
+                               connection, thus the connection has
+                               gone away. Or the application signals
+                               that it wants to abort the
+                               connection. */
 #define UIP_CONNECTED 64    /* We have got a connection from a remote
                                host and have set up a new connection
                                for it, or an active connection has
                                been successfully established. */
 
 #define UIP_TIMEDOUT  128   /* The connection has been aborted due to
-			       too many retransmissions. */
+                               too many retransmissions. */
 
 /* uip_process(flag):
  *
@@ -1377,16 +1377,16 @@ void uip_process(u8_t flag);
    the macrose defined in this file. */
  
 #define UIP_DATA          1     /* Tells uIP that there is incoming
-				   data in the uip_buf buffer. The
-				   length of the data is stored in the
-				   global variable uip_len. */
+                                   data in the uip_buf buffer. The
+                                   length of the data is stored in the
+                                   global variable uip_len. */
 #define UIP_TIMER         2     /* Tells uIP that the periodic timer
-				   has fired. */
+                                   has fired. */
 #define UIP_POLL_REQUEST  3     /* Tells uIP that a connection should
-				   be polled. */
+                                   be polled. */
 #define UIP_UDP_SEND_CONN 4     /* Tells uIP that a UDP datagram
-				   should be constructed in the
-				   uip_buf buffer. */
+                                   should be constructed in the
+                                   uip_buf buffer. */
 #if UIP_UDP
 #define UIP_UDP_TIMER     5
 #endif /* UIP_UDP */
@@ -1544,11 +1544,11 @@ struct uip_udpip_hdr {
 #define UIP_UDPH_LEN    8    /* Size of UDP header */
 #define UIP_TCPH_LEN   20    /* Size of TCP header */
 #define UIP_IPUDPH_LEN (UIP_UDPH_LEN + UIP_IPH_LEN)    /* Size of IP +
-							  UDP
-							  header */
+                                                          UDP
+                                                          header */
 #define UIP_IPTCPH_LEN (UIP_TCPH_LEN + UIP_IPH_LEN)    /* Size of IP +
-							  TCP
-							  header */
+                                                          TCP
+                                                          header */
 #define UIP_TCPIP_HLEN UIP_IPTCPH_LEN
 
 
diff --git a/src/uip/uip_arp.c b/src/uip/uip_arp.c
index 58a052bd..5732e78b 100644
--- a/src/uip/uip_arp.c
+++ b/src/uip/uip_arp.c
@@ -174,13 +174,13 @@ uip_arp_update(u16_t *ipaddr, struct uip_eth_addr *ethaddr)
       /* Check if the source IP address of the incoming packet matches
          the IP address in this ARP table entry. */
       if(ipaddr[0] == tabptr->ipaddr[0] &&
-	 ipaddr[1] == tabptr->ipaddr[1]) {
-	 
-	/* An old entry found, update this and return. */
-	memcpy(tabptr->ethaddr.addr, ethaddr->addr, 6);
-	tabptr->time = arptime;
+         ipaddr[1] == tabptr->ipaddr[1]) {
+ 
+        /* An old entry found, update this and return. */
+        memcpy(tabptr->ethaddr.addr, ethaddr->addr, 6);
+        tabptr->time = arptime;
 
-	return;
+        return;
       }
     }
   }
@@ -205,8 +205,8 @@ uip_arp_update(u16_t *ipaddr, struct uip_eth_addr *ethaddr)
     for(i = 0; i < UIP_ARPTAB_SIZE; ++i) {
       tabptr = &arp_table[i];
       if(arptime - tabptr->time > tmpage) {
-	tmpage = arptime - tabptr->time;
-	c = i;
+        tmpage = arptime - tabptr->time;
+        c = i;
       }
     }
     i = c;
@@ -238,7 +238,7 @@ void
 uip_arp_ipin(void)
 {
   uip_len -= sizeof(struct uip_eth_hdr);
-	
+
   /* Only insert/update an entry if the source IP address of the
      incoming IP packet comes from a host on the local network. */
   if((IPBUF->srcipaddr[0] & uip_netmask[0]) !=
@@ -293,8 +293,8 @@ uip_arp_arpin(void)
        reply. */
     if(uip_ipaddr_cmp(BUF->dipaddr, uip_hostaddr)) {
       /* First, we register the one who made the request in our ARP
-	 table, since it is likely that we will do more communication
-	 with this host in the future. */
+         table, since it is likely that we will do more communication
+         with this host in the future. */
       uip_arp_update(BUF->sipaddr, &BUF->shwaddr);
       
       /* The reply opcode is 2. */
@@ -372,8 +372,8 @@ uip_arp_out(void)
     /* Check if the destination address is on the local network. */
     if(!uip_ipaddr_maskcmp(IPBUF->destipaddr, uip_hostaddr, uip_netmask)) {
       /* Destination address was not on the local network, so we need to
-	 use the default router's IP address instead of the destination
-	 address when determining the MAC address. */
+         use the default router's IP address instead of the destination
+         address when determining the MAC address. */
       uip_ipaddr_copy(ipaddr, uip_draddr);
     } else {
       /* Else, we use the destination IP address. */
@@ -383,13 +383,13 @@ uip_arp_out(void)
     for(i = 0; i < UIP_ARPTAB_SIZE; ++i) {
       tabptr = &arp_table[i];
       if(uip_ipaddr_cmp(ipaddr, tabptr->ipaddr)) {
-	break;
+        break;
       }
     }
 
     if(i == UIP_ARPTAB_SIZE) {
       /* The destination address was not in our ARP table, so we
-	 overwrite the IP packet with an ARP request. */
+         overwrite the IP packet with an ARP request. */
 
       memset(BUF->ethhdr.dest.addr, 0xff, 6);
       memset(BUF->dhwaddr.addr, 0x00, 6);
diff --git a/src/uip/uiplib.c b/src/uip/uiplib.c
index 3cb4beef..cbf02e00 100644
--- a/src/uip/uiplib.c
+++ b/src/uip/uiplib.c
@@ -57,16 +57,16 @@ uiplib_ipaddrconv(char *addrstr, unsigned char *ipaddr)
       c = *addrstr;
       ++j;
       if(j > 4) {
-	return 0;
+        return 0;
       }
       if(c == '.' || c == 0) {
-	*ipaddr = tmp;
-	++ipaddr;
-	tmp = 0;
+        *ipaddr = tmp;
+        ++ipaddr;
+        tmp = 0;
       } else if(c >= '0' && c <= '9') {
-	tmp = (tmp * 10) + (c - '0');
+        tmp = (tmp * 10) + (c - '0');
       } else {
-	return 0;
+        return 0;
       }
       ++addrstr;
     } while(c != '.' && c != 0);
diff --git a/utils/build.lua b/utils/build.lua
index 1bc6f519..cd9e2c81 100644
--- a/utils/build.lua
+++ b/utils/build.lua
@@ -660,62 +660,40 @@ builder.read_depends = function( self, ftable )
   return dtable
 end
 
--- Build and interpret dependencies for the given source files
--- "flable" is either a space-separated string with all the source files or an array
-builder.make_depends = function( self, ftable )
-  if type( ftable ) == 'string' then ftable = utils.string_to_table( ftable ) end
-
-  -- Start with initial dependency data (this might be nil when generated initially)
-  local initdep = self:read_depends( ftable )
-
-  -- Build dependencies for all targets
-  self.dtable = {}
-  for i = 1, #ftable do
-    local isasm = ftable[ i ]:find( "%.c$" ) == nil
-    -- Skip assembler targets if 'asm_dep_cmd' is set to 'false'
-    -- Skip C targets if 'c_dep_cmd' is set to 'false'
-    local skip = isasm and self.asm_dep_cmd == false
-    skip = skip or ( not isasm and self.c_dep_cmd == false )
-    if not skip then
-      local cmd = isasm and self._asm_cmd or self.comp_cmd
-      local depcmd = cmd:gsub( "-c ", "-E -MM " )
-      if isasm and self.asm_dep_cmd then depcmd = self.asm_dep_cmd end
-      if not isasm and self.c_dep_cmd then depcmd = self.c_dep_cmd end
-      local target = self:dep_target( ftable[ i ], initdep[ ftable[ i ] ], depcmd )
-      -- The post build function will read the generated dependencies and save
-      -- them into an instance-related field (dtable)
-      target:set_post_build_function( function( t, _ ) 
-        if not self.clean_mode then
-          local tname = t.dep[ 1 ]:target_name()
-          if tname then
-            local fres = self:read_depends( tname )
-            self.dtable[ tname ] = fres[ tname ] 
-          end
-        end
-      end )
-    end
-  end
-end
-
 -- Create and return compile targets for the given sources
 builder.create_compile_targets = function( self, ftable, res )
   if type( ftable ) == 'string' then ftable = utils.string_to_table( ftable ) end
   res = res or {}
   -- Build dependencies for all targets
   for i = 1, #ftable do
-    local target 
+    local isasm = ftable[ i ]:find( "%.c$" ) == nil
+    -- Skip assembler targets if 'asm_dep_cmd' is set to 'false'
+    -- Skip C targets if 'c_dep_cmd' is set to 'false'
+    local skip = isasm and self.asm_dep_cmd == false
+    skip = skip or ( not isasm and self.c_dep_cmd == false )
     local deps = self:get_dep_filename( ftable[ i ] )
-    if ftable[ i ]:find( "%.c$" ) then
-      target = self:c_target( self:obj_name( ftable[ i ] ), { self:get_registered_target( deps ) or ftable[ i ] } )
+    local target
+    if not isasm then
+      local depcmd = skip and self.comp_cmd or ( self.c_dep_cmd or self.comp_cmd:gsub( "-c ", sf( "-c -MD -MF %s ", deps ) ) )
+      target = self:c_target( self:obj_name( ftable[ i ] ), { self:get_registered_target( deps ) or ftable[ i ] }, depcmd )
     else
-      target = self:asm_target( self:obj_name( ftable[ i ] ), { self:get_registered_target( deps ) or ftable[ i ] } )
+      local depcmd = skip and self._asm_cmd or ( self.asm_dep_cmd or self._asm_cmd:gsub( "-c ", sf( "-c -MD -MF %s ", deps ) ) )
+      target = self:asm_target( self:obj_name( ftable[ i ] ), { self:get_registered_target( deps ) or ftable[ i ] }, depcmd )
+    end
+    -- Pre build step: replace dependencies with the ones from the compiler generated dependency file
+    if not skip then
+      target:set_pre_build_function( function( t, _ )
+        if not self.clean_mode then
+          local fres = self:read_depends( ftable[ i ] )
+          local fdeps = fres[ ftable[ i ] ]
+          if #fdeps:gsub( "%s+", "" ) == 0 then fdeps = ftable[ i ] end
+          t:set_dependencies( fdeps )
+        else
+          io.write( sf( "[builder] Removing %s ... ", deps ) )
+          if os.remove( deps ) then print "done." else print "failed!" end
+        end
+      end )
     end
-    -- Post build step: replace dependencies with the ones generated by 'make_depends'
-    target:set_pre_build_function( function( t, _ ) 
-      if not self.clean_mode then
-        t:set_dependencies( self.dtable[ ftable[ i ] ] or ftable[ i ] )
-      end
-    end )
     table.insert( res, target )
   end
   return res
@@ -778,7 +756,6 @@ end
 
 -- Create dependencies, create object files, link final object
 builder.make_exe_target = function( self, target, file_list )
-  self:make_depends( file_list )
   local odeps = self:create_compile_targets( file_list )
   local exetarget = self:link_target( target, odeps )
   self:default( self:add_target( exetarget ) )