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preliminary support for str9-comstick

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Bogdan Marinescu 2008-08-02 18:00:05 +00:00
parent 8ad0f6f31c
commit cc38de7724
22 changed files with 5940 additions and 0 deletions
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src/platform/str9/91x_conf.h Normal file
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/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
* File Name : 91x_conf.h
* Author : MCD Application Team
* Date First Issued : 05/18/2006 : Version 1.0
* Description : Library configuration.
********************************************************************************
* History:
* 05/24/2006 : Version 1.1
* 05/18/2006 : Version 1.0
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
#ifndef __91x_CONF_H
#define __91x_CONF_H
/* To work in buffered mode just decomment the following line */
//#define Buffered
/* Comment the line below to put the library in release mode */
//#define DEBUG
/************************* AHBAPB *************************/
//#define _AHBAPB
//#define _AHBAPB0
//#define _AHBAPB1
/************************* VIC *************************/
#define _VIC
#define _VIC0
#define _VIC1
/************************* DMA *************************/
//#define _DMA
//#define _DMA_Channel0
//#define _DMA_Channel1
//#define _DMA_Channel2
//#define _DMA_Channel3
//#define _DMA_Channel4
//#define _DMA_Channel5
//#define _DMA_Channel6
//#define _DMA_Channel7
/************************* EMI *************************/
//#define _EMI
//#define _EMI_Bank0
//#define _EMI_Bank1
//#define _EMI_Bank2
//#define _EMI_Bank3
/************************* FMI *************************/
#define _FMI
/************************* WIU *************************/
//#define _WIU
/************************* TIM *************************/
#define _TIM
#define _TIM0
#define _TIM1
#define _TIM2
#define _TIM3
/************************* GPIO ************************/
#define _GPIO
#define _GPIO0
#define _GPIO1
#define _GPIO2
#define _GPIO3
#define _GPIO4
#define _GPIO5
#define _GPIO6
#define _GPIO7
#define _GPIO8
#define _GPIO9
/************************* RTC *************************/
//#define _RTC
/************************* SCU *************************/
#define _SCU
/************************* MC **************************/
//#define _MC
/************************* UART ************************/
#define _UART
#define _UART0
#define _UART1
#define _UART2
/************************* SSP *************************/
//#define _SSP
//#define _SSP0
//#define _SSP1
/************************* CAN *************************/
//#define _CAN
/************************* ADC *************************/
//#define _ADC
/************************* WDG *************************/
//#define _WDG
/************************* I2C *************************/
//#define _I2C
//#define _I2C0
//#define _I2C1
/************************ ENET *************************/
//#define _ENET
/************************ USB *************************/
//#define _USB
/*---------------------------- _Main_Crystal frequency value (KHz)------------*/
#ifndef _Main_Crystal
#define _Main_Crystal 25000
#endif
/*------------------------------------------------------------------------------*/
#endif /* __91x_CONF_H */
/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/

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src/platform/str9/91x_fmi.c Normal file
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/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
* File Name : 91x_fmi.c
* Author : MCD Application Team
* Date First Issued : 05/18/2006 : Version 1.0
* Description : This file provides all the FMI software functions.
********************************************************************************
* History:
* 05/24/2006 : Version 1.1
* 05/18/2006 : Version 1.0
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Standard include ----------------------------------------------------------*/
#include "91x_fmi.h"
/* Include of other module interface headers ---------------------------------*/
/* Local includes ------------------------------------------------------------*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define TIMEOUT 0xFFFFFF /* Timeout value */
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Interface functions -------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/*******************************************************************************
* Function Name : FMI_BankRemapConfig
* Description : Configure the addresses and sizes of bank 0 and bank 1.
* Input1 : FMI_BootBankSize: specifies the boot bank size.
* This parameter can be one of the following values:
* - 0x0: 32KBytes.
* - 0x1: 64KBytes.
* - 0x2: 128KBytes.
* - 0x3: 256KBytes.
* - 0x4: 512KBytes.
* ....
* - 0xB: 64MBytes.
* Input2 : FMI_NonBootBankSize: specifies the non boot bank size.
* This parameter can be one of the following values:
* - 0x0: 8KBytes.
* - 0x1: 16KBytes.
* - 0x2: 32KBytes.
* - 0x3: 64KBytes.
* ....
* - 0xD: 64MBytes.
* Input3 : FMI_BootBankAddress: specifies the address of the boot bank.
* Input4 : FMI_NonBootBankAddress: specifies the address of the non
* boot bank.
* Output : None
* Return : None
*******************************************************************************/
void FMI_BankRemapConfig(u8 FMI_BootBankSize, u8 FMI_NonBootBankSize, \
u32 FMI_BootBankAddress, u32 FMI_NonBootBankAddress)
{
FMI->BBSR = FMI_BootBankSize;
FMI->NBBSR = FMI_NonBootBankSize;
FMI->BBADR = (FMI_BootBankAddress >> 2);
FMI->NBBADR = (FMI_NonBootBankAddress >> 2);
FMI->CR |= 0x18; /* Enable bank 1 */
}
/*******************************************************************************
* Function Name : FMI_Config
* Description : Configure the FMI.
* Input1 : FMI_ReadWaitState: specifies the needed read wait states.
* This parameter can be one of the following values:
* - FMI_READ_WAIT_STATE_1: One read wait state.
* - FMI_READ_WAIT_STATE_2: Two read wait states.
* - FMI_READ_WAIT_STATE_3: Three read wait states.
* Input2 : FMI_WriteWaitState: specifies the needed write wait states.
* This parameter can be one of the following values:
* - FMI_WRITE_WAIT_STATE_1: One write wait state.
* - FMI_WRITE_WAIT_STATE_2: Two write wait states.
* Input3 : FMI_PWD: specifies the power down mode status.
* This parameter can be one of the following values:
* - FMI_PWD_ENABLE: Enable the PWD.
* - FMI_PWD_DISABLE: Disable the PWD.
* Input4 : FMI_LVDEN: specifies the low voltage detector status.
* This parameter can be one of the following values:
* - FMI_LVD_ENABLE: Enable the LVD.
* - FMI_LVD_DISABLE: Disable the LVD.
* Input5 : FMI_FreqRange: specifies the working frequency range.
* This parameter can be one of the following values:
* - FMI_FREQ_LOW: Low working frequency (up to 66MHz).
* - FMI_FREQ_HIGH: High working frequency (above 66MHz) .
* Output : None
* Return : None
*******************************************************************************/
void FMI_Config(u16 FMI_ReadWaitState, u32 FMI_WriteWaitState, u16 FMI_PWD,\
u16 FMI_LVDEN, u16 FMI_FreqRange)
{
/* Configure the write wait state value */
if (FMI_WriteWaitState == FMI_WRITE_WAIT_STATE_1)
{
FMI->CR |= FMI_WRITE_WAIT_STATE_1;
}
else
{
FMI->CR &= FMI_WRITE_WAIT_STATE_0;
}
/* Write a write flash configuration register command */
*(vu16 *)FMI_BANK_1 = 0x60;
/* Configure the flash configuration register */
*(vu16 *)(FMI_BANK_1|FMI_ReadWaitState|FMI_PWD|FMI_LVDEN|FMI_FreqRange) = 0x03;
}
/*******************************************************************************
* Function Name : FMI_EraseSector
* Description : Erase the needed sector.
* Input : FMI_Sector: specifies the sector to be erased.
* This parameter can be one of the following values:
* - FMI_B0S0: FMI bank 0 sector 0.
* - FMI_B0S1: FMI bank 0 sector 1.
* - FMI_B0S2: FMI bank 0 sector 2.
* - FMI_B0S3: FMI bank 0 sector 3.
* - FMI_B0S4: FMI bank 0 sector 4.
* - FMI_B0S5: FMI bank 0 sector 5.
* - FMI_B0S6: FMI bank 0 sector 6.
* - FMI_B0S7: FMI bank 0 sector 7.
* - FMI_B1S0: FMI bank 1 sector 0.
* - FMI_B1S1: FMI bank 1 sector 1.
* - FMI_B1S2: FMI bank 1 sector 2.
* - FMI_B1S3: FMI bank 1 sector 3.
* Output : None
* Return : None
*******************************************************************************/
void FMI_EraseSector(vu32 FMI_Sector)
{
/* Write an erase set-up command to the sector */
*(vu16 *)FMI_Sector = 0x20;
/* Write an erase confirm command to the sector */
*(vu16 *)FMI_Sector = 0xD0;
}
/*******************************************************************************
* Function Name : FMI_EraseBank
* Description : Erase the needed bank.
* Input : FMI_Bank: specifies the bank to be erased.
* This parameter can be one of the following values:
* - FMI_BANK_0: FMI bank 0.
* - FMI_BANK_1: FMI bank 1.
* Output : None
* Return : None
*******************************************************************************/
void FMI_EraseBank(vu32 FMI_Bank)
{
/* Write a bank erase set-up command to the bank */
*(vu16 *)FMI_Bank = 0x80;
/* Write an erase confirm command to the sector */
*(vu16 *)FMI_Bank = 0xD0;
}
/*******************************************************************************
* Function Name : FMI_WriteHalfWord
* Description : Write a halfword to the needed Flash memory address.
* Input 1 : FMI_Address: specifies the address offset where the data will
* be written.
* Input 2 : FMI_Data: the needed data.
* Output : None
* Return : None
*******************************************************************************/
void FMI_WriteHalfWord(u32 FMI_Address, u16 FMI_Data)
{
/* Write a program command to the sector to be written */
*(vu16 *)(FMI_Address & 0xFFFFFFFC) = 0x40;
/* Write the halfword to the destination address */
*(vu16 *)FMI_Address = FMI_Data;
}
/*******************************************************************************
* Function Name : FMI_WriteOTPHalfWord
* Description : Write a halfword to the needed OTP sector address.
* Input 1 : FMI_OTPHWAddress: specifies the halfword address offset
* where the data will be written.
* This parameter can be one of the following values:
* - FMI_OTP_LOW_HALFWORD_0: OTP Low halfword 0.
* - FMI_OTP_HIGH_HALFWORD_0: OTP High halfword 0.
* - FMI_OTP_LOW_HALFWORD_1: OTP Low halfword 1.
* - FMI_OTP_HIGH_HALFWORD_1: OTP High halfword 1.
* - FMI_OTP_LOW_HALFWORD_2: OTP Low halfword 2.
* - FMI_OTP_HIGH_HALFWORD_2: OTP High halfword 2.
* - FMI_OTP_LOW_HALFWORD_3: OTP Low halfword 3.
* - FMI_OTP_HIGH_HALFWORD_3: OTP High halfword 3.
* - FMI_OTP_LOW_HALFWORD_4: OTP Low halfword 4.
* - FMI_OTP_HIGH_HALFWORD_4: OTP High halfword 4.
* - FMI_OTP_LOW_HALFWORD_5: OTP Low halfword 5.
* - FMI_OTP_HIGH_HALFWORD_5: OTP High halfword 5.
* - FMI_OTP_LOW_HALFWORD_6: OTP Low halfword 6.
* - FMI_OTP_HIGH_HALFWORD_6: OTP High halfword 6.
* - FMI_OTP_LOW_HALFWORD_7: OTP Low halfword 7.
* - FMI_OTP_HIGH_HALFWORD_7: OTP High halfword 7.
* Input 2 : FMI_OTPData: The needed OTP data.
* Output : None
* Return : None
*******************************************************************************/
void FMI_WriteOTPHalfWord(u8 FMI_OTPHWAddress, u16 FMI_OTPData)
{
/* Write a write OTP command to the needed address */
*(vu16 *)(FMI_BANK_1) = 0xC0;
/* Write the halfword to the destination address */
*(vu16 *)(FMI_BANK_1 + FMI_OTPHWAddress) = FMI_OTPData;
}
/*******************************************************************************
* Function Name : FMI_ReadWord
* Description : Read the correspondent data.
* Input : FMI_Address: specifies the needed address.
* Output : None
* Return : The data contained in the specified address.
*******************************************************************************/
u32 FMI_ReadWord(u32 FMI_Address)
{
return(*(u32*)FMI_Address);
}
/*******************************************************************************
* Function Name : FMI_ReadOTPData
* Description : Read data from the OTP sector.
* Input : FMI_OTPAddress: specifies the address of the data to be read.
* This parameter can be one of the following values:
* - FMI_OTP_WORD_0: FMI bank 0 sector 0.
* - FMI_OTP_WORD_1: FMI bank 0 sector 1.
* - FMI_OTP_WORD_2: FMI bank 0 sector 2.
* - FMI_OTP_WORD_3: FMI bank 0 sector 3.
* - FMI_OTP_WORD_4: FMI bank 0 sector 4.
* - FMI_OTP_WORD_5: FMI bank 0 sector 5.
* - FMI_OTP_WORD_6: FMI bank 0 sector 6.
* - FMI_OTP_WORD_7: FMI bank 0 sector 7.
* Output : None
* Return : The needed OTP words.
*******************************************************************************/
u32 FMI_ReadOTPData(u8 FMI_OTPAddress)
{
u32 OTP_Data = 0x0;
/* write a read OTP sector command */
*(vu16 *)(FMI_BANK_1) = 0x98;
/* Read the correspondent data */
OTP_Data = (*(vu32*)(FMI_BANK_1 + FMI_OTPAddress));
/* Write a read array command */
*(vu16 *)(FMI_BANK_1) = 0xFF;
return OTP_Data;
}
/*******************************************************************************
* Function Name : FMI_GetFlagStatus
* Description : Check whether the specified FMI flag is set or not.
* Input1 : FMI_Flag: flag to check.
* This parameter can be one of the following values:
* - FMI_FLAG_SPS: Sector Protection Status Flag.
* - FMI_FLAG_PSS: Program Suspend Status Flag.
* - FMI_FLAG_PS: Program Status Flag.
* - FMI_FLAG_ES: Erase Status Flag.
* - FMI_FLAG_ESS: Erase Suspend Status Flag.
* - FMI_FLAG_PECS: FPEC Status Flag.
* Input2 : FMI_Bank: specifies the needed bank.
* This parameter can be one of the following values:
* - FMI_BANK_0: FMI bank 0.
* - FMI_BANK_1: FMI bank 1.
* Output : None
* Return : None
*******************************************************************************/
FlagStatus FMI_GetFlagStatus(u8 FMI_Flag, vu32 FMI_Bank)
{
u16 FMI_Status_Register = 0;
/* Write a read status register command */
*(vu16 *)FMI_Bank = 0x70;
/* Wait until operation completion */
while(!((*(vu16 *)FMI_Bank) & 0x80));
/* Read the status register */
FMI_Status_Register = *(vu16 *)FMI_Bank;
/* Write a read array command */
*(vu16 *)FMI_Bank = 0xFF;
if((FMI_Status_Register & FMI_Flag) != RESET)
{
return SET;
}
else
{
return RESET;
}
}
/*******************************************************************************
* Function Name : FMI_GetReadWaitStateValue
* Description : Get the current Read wait state value.
* Input : None
* Output : None
* Return : The current read wait states value.
*******************************************************************************/
u16 FMI_GetReadWaitStateValue(void)
{
u16 FMI_Configuration_Register = 0;
/* Write a read flash configuration register command */
*(vu16 *)FMI_BANK_1 = 0x90;
/* Read the flash configuration register */
FMI_Configuration_Register = *(vu16 *)(FMI_BANK_1 + 0x14);
/* Write a read array command */
*(vu16 *)FMI_BANK_1 = 0xFF;
FMI_Configuration_Register = ((FMI_Configuration_Register>>11) + 1) & 0x3;
/* Return the wait states value */
return FMI_Configuration_Register;
}
/*******************************************************************************
* Function Name : FMI_GetWriteWaitStateValue
* Description : Get the current write wait state value.
* Input : None
* Output : None
* Return : The current write wait states value.
*******************************************************************************/
u16 FMI_GetWriteWaitStateValue(void)
{
return ((u16)((FMI->CR & 0x100) >> 8));
}
/*******************************************************************************
* Function Name : FMI_SuspendEnable
* Description : Suspend command enable.
* Input : FMI_Bank: specifies the bank to be suspended.
* This parameter can be one of the following values:
* - FMI_BANK_0: FMI bank 0.
* - FMI_BANK_1: FMI bank 1.
* Output : None
* Return : None
*******************************************************************************/
void FMI_SuspendEnable(vu32 FMI_Bank)
{
/* Write a suspend command to the bank */
*(vu16 *)FMI_Bank = 0xB0;
}
/*******************************************************************************
* Function Name : FMI_ResumeEnable
* Description : Resume the suspended command.
* Input : FMI_Bank: specifies the suspended bank.
* This parameter can be one of the following values:
* - FMI_BANK_0: FMI bank 0.
* - FMI_BANK_1: FMI bank 1.
* Output : None
* Return : None
*******************************************************************************/
void FMI_ResumeEnable(vu32 FMI_Bank)
{
/* Write a resume command to the bank */
*(vu16 *)FMI_Bank = 0xD0;
}
/*******************************************************************************
* Function Name : FMI_ClearFlag
* Description : Clear the FMI Flags on the correspondent bank.
* Input : FMI_Bank: specifies the needed bank.
* This parameter can be one of the following values:
* - FMI_BANK_0: FMI bank 0.
* - FMI_BANK_1: FMI bank 1.
* Output : None
* Return : None
*******************************************************************************/
void FMI_ClearFlag(vu32 FMI_Bank)
{
/* Write a clear status register command */
*(vu16 *)FMI_Bank = 0x50;
}
/*******************************************************************************
* Function Name : FMI_WriteProtectionCmd
* Description : Enable or disable the write protection for the needed sector.
* Input1 : FMI_Sector: specifies the sector to be protected or
* unprotected.
* This parameter can be one of the following values:
* - FMI_B0S0: FMI bank 0 sector 0.
* - FMI_B0S1: FMI bank 0 sector 1.
* - FMI_B0S2: FMI bank 0 sector 2.
* - FMI_B0S3: FMI bank 0 sector 3.
* - FMI_B0S4: FMI bank 0 sector 4.
* - FMI_B0S5: FMI bank 0 sector 5.
* - FMI_B0S6: FMI bank 0 sector 6.
* - FMI_B0S7: FMI bank 0 sector 7.
* - FMI_B1S0: FMI bank 1 sector 0.
* - FMI_B1S1: FMI bank 1 sector 1.
* - FMI_B1S2: FMI bank 1 sector 2.
* - FMI_B1S3: FMI bank 1 sector 3.
* Input2 : FMI_NewState: specifies the protection status.
* This parameter can be one of the following values:
* - ENABLE: Enable the protection.
* - DISABLE: Disable the protection.
* Output : None
* Return : None
*******************************************************************************/
void FMI_WriteProtectionCmd(vu32 FMI_Sector, FunctionalState FMI_NewState)
{
if (FMI_NewState == ENABLE)
{
*(vu16*)FMI_Sector = 0x60;
*(vu16*)FMI_Sector = 0x01;
*(vu16*)FMI_Sector = 0xFF;
}
else /* DISABLE */
{
*(vu16*)FMI_Sector = 0x60;
*(vu16*)FMI_Sector = 0xD0;
*(vu16*)FMI_Sector = 0xFF;
}
}
/*******************************************************************************
* Function Name : FMI_GetWriteProtectionStatus
* Description : Get the write protection status for the needed sector.
* Input : FMI_Sector_Mask: specifies the needed sector mask.
* This parameter can be one of the following values:
* - FMI_B0S0_MASK: FMI bank 0 sector 0.
* - FMI_B0S1_MASK: FMI bank 0 sector 1.
* - FMI_B0S2_MASK: FMI bank 0 sector 2.
* - FMI_B0S3_MASK: FMI bank 0 sector 3.
* - FMI_B0S4_MASK: FMI bank 0 sector 4.
* - FMI_B0S5_MASK: FMI bank 0 sector 5.
* - FMI_B0S6_MASK: FMI bank 0 sector 6.
* - FMI_B0S7_MASK: FMI bank 0 sector 7.
* - FMI_B1S0_MASK: FMI bank 1 sector 0.
* - FMI_B1S1_MASK: FMI bank 1 sector 1.
* - FMI_B1S2_MASK: FMI bank 1 sector 2.
* - FMI_B1S3_MASK: FMI bank 1 sector 3.
* Output : None
* Return : The Protection Status of the needed sector.
* - RESET: The needed sector is not write protected.
* - SET : The needed sector is write protected.
*******************************************************************************/
FlagStatus FMI_GetWriteProtectionStatus(u32 FMI_Sector_Mask)
{
u16 Protection_Level_1_Register = 0;
/* Write a read flash protection level 1 register command */
*(vu16 *)FMI_BANK_1 = 0x90;
/* Read the flash protection level 1 register */
Protection_Level_1_Register = *(vu16 *)(FMI_BANK_1 + 0x10);
/* Write a read array command */
*(vu16 *)FMI_BANK_1 = 0xFF;
if (Protection_Level_1_Register &= FMI_Sector_Mask)
{
return SET;
}
else
{
return RESET;
}
}
/*******************************************************************************
* Function Name : FMI_WaitForLastOperation
* Description : Wait until the last operation (Write halfword, Write OTP
* halfword, Erase sector and Erase bank) completion.
* Input : FMI_Bank: specifies the bank where the operation is on going.
* This parameter can be one of the following values:
* - FMI_BANK_0: FMI bank 0.
* - FMI_BANK_1: FMI bank 1.
* Output : None
* Return : The timeout status.
* This parameter can be one of the following values:
* - FMI_TIME_OUT_ERROR: Timeout error occurred.
* - FMI_NO_TIME_OUT_ERROR: No timeout error.
*******************************************************************************/
u8 FMI_WaitForLastOperation(vu32 FMI_Bank)
{
u32 Time_Out = 0;
/* Write a read status register command */
*(vu16 *)(FMI_Bank) = 0x70;
/* Wait until operation compeletion */
while((!((*(vu16 *)FMI_Bank) & 0x80))&&(Time_Out < TIMEOUT ))
{
Time_Out ++; /* Time Out */
}
/* Write a read array command */
*(vu16 *)FMI_Bank = 0xFF;
if (Time_Out == TIMEOUT)
{
return FMI_TIME_OUT_ERROR;
}
else
{
return FMI_NO_TIME_OUT_ERROR;
}
}
/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/

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/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
* File Name : 91x_fmi.h
* Author : MCD Application Team
* Date First Issued : 05/18/2006 : Version 1.0
* Description : This file contains all the functions prototypes for the
* FMI software library.
********************************************************************************
* History:
* 05/24/2006 : Version 1.1
* 05/18/2006 : Version 1.0
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion ------------------------------------ */
#ifndef __91x_FMI_H
#define __91x_FMI_H
/* ========================================================================== */
/* When bank 1 is remapped at address 0x0, decomment the following line */
/* ========================================================================== */
//#define Remap_Bank_1
/* Includes ------------------------------------------------------------------*/
#include "91x_map.h"
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* FMI banks */
#ifdef Remap_Bank_1
#define FMI_BANK_0 ((*(vu32*)0x54000010) << 2) /* FMI Bank 0 */
#define FMI_BANK_1 ((*(vu32*)0x5400000C) << 2) /* FMI Bank 1 */
#else /* Remap Bank 0 */
#define FMI_BANK_0 ((*(vu32*)0x5400000C) << 2) /* FMI Bank 0 */
#define FMI_BANK_1 ((*(vu32*)0x54000010) << 2) /* FMI Bank 1 */
#endif
/* FMI sectors */
#define FMI_B0S0 0x00000000 + FMI_BANK_0 /* Bank 0 sector 0 */
#define FMI_B0S1 0x00010000 + FMI_BANK_0 /* Bank 0 sector 1 */
#define FMI_B0S2 0x00020000 + FMI_BANK_0 /* Bank 0 sector 2 */
#define FMI_B0S3 0x00030000 + FMI_BANK_0 /* Bank 0 sector 3 */
#define FMI_B0S4 0x00040000 + FMI_BANK_0 /* Bank 0 sector 4 */
#define FMI_B0S5 0x00050000 + FMI_BANK_0 /* Bank 0 sector 5 */
#define FMI_B0S6 0x00060000 + FMI_BANK_0 /* Bank 0 sector 6 */
#define FMI_B0S7 0x00070000 + FMI_BANK_0 /* Bank 0 sector 7 */
#define FMI_B1S0 0x00000000 + FMI_BANK_1 /* Bank 1 sector 0 */
#define FMI_B1S1 0x00002000 + FMI_BANK_1 /* Bank 1 sector 1 */
#define FMI_B1S2 0x00004000 + FMI_BANK_1 /* Bank 1 sector 2 */
#define FMI_B1S3 0x00006000 + FMI_BANK_1 /* Bank 1 sector 3 */
/* FMI Flags */
#define FMI_FLAG_SPS 0x02 /* Sector Protection Status Flag */
#define FMI_FLAG_PSS 0x04 /* Program Suspend Status Flag */
#define FMI_FLAG_PS 0x10 /* Program Status Flag */
#define FMI_FLAG_ES 0x20 /* Erase Status Flag */
#define FMI_FLAG_ESS 0x40 /* Erase Suspend Status Flag */
#define FMI_FLAG_PECS 0x80 /* FPEC Status Flag */
/* FMI read wait states */
#define FMI_READ_WAIT_STATE_1 0x0000 /* One read wait state */
#define FMI_READ_WAIT_STATE_2 0x2000 /* Two read wait states */
#define FMI_READ_WAIT_STATE_3 0x4000 /* Three read wait states */
/* FMI write wait states */
#define FMI_WRITE_WAIT_STATE_0 0xFFFFFEFF /* Zero wait state */
#define FMI_WRITE_WAIT_STATE_1 0x00000100 /* One wait state */
/* FMI power down configuration */
#define FMI_PWD_ENABLE 0x1000 /* FMI Power Down Enable */
#define FMI_PWD_DISABLE 0x0000 /* FMI Power Down Disable */
/* FMI low voltage detector */
#define FMI_LVD_ENABLE 0x0000 /* FMI Low Voltage Detector Enable */
#define FMI_LVD_DISABLE 0x0800 /* FMI Low Voltage Detector Disable */
/* FMI frequency range */
#define FMI_FREQ_LOW 0x0000 /* FMI Low bus working frequency */
#define FMI_FREQ_HIGH 0x0040 /* FMI High bus working gfrequency */
/* Above 66 MHz*/
/* FMI OTP word addresses */
#define FMI_OTP_WORD_0 0x00 /* OTP word 0 */
#define FMI_OTP_WORD_1 0x04 /* OTP word 1 */
#define FMI_OTP_WORD_2 0x08 /* OTP word 2 */
#define FMI_OTP_WORD_3 0x0C /* OTP word 3 */
#define FMI_OTP_WORD_4 0x10 /* OTP word 4 */
#define FMI_OTP_WORD_5 0x14 /* OTP word 5 */
#define FMI_OTP_WORD_6 0x18 /* OTP word 6 */
#define FMI_OTP_WORD_7 0x1C /* OTP word 7 */
/* FMI OTP halfword addresses */
#define FMI_OTP_LOW_HALFWORD_0 0x00 /* OTP Low halfword 0 */
#define FMI_OTP_HIGH_HALFWORD_0 0x02 /* OTP High halfword 0 */
#define FMI_OTP_LOW_HALFWORD_1 0x04 /* OTP Low halfword 1 */
#define FMI_OTP_HIGH_HALFWORD_1 0x06 /* OTP High halfword 1 */
#define FMI_OTP_LOW_HALFWORD_2 0x08 /* OTP Low halfword 2 */
#define FMI_OTP_HIGH_HALFWORD_2 0x0A /* OTP High halfword 2 */
#define FMI_OTP_LOW_HALFWORD_3 0x0C /* OTP Low halfword 3 */
#define FMI_OTP_HIGH_HALFWORD_3 0x0E /* OTP High halfword 3 */
#define FMI_OTP_LOW_HALFWORD_4 0x10 /* OTP Low halfword 4 */
#define FMI_OTP_HIGH_HALFWORD_4 0x12 /* OTP High halfword 4 */
#define FMI_OTP_LOW_HALFWORD_5 0x14 /* OTP Low halfword 5 */
#define FMI_OTP_HIGH_HALFWORD_5 0x16 /* OTP High halfword 5 */
#define FMI_OTP_LOW_HALFWORD_6 0x18 /* OTP Low halfword 6 */
#define FMI_OTP_HIGH_HALFWORD_6 0x1A /* OTP High halfword 6 */
#define FMI_OTP_LOW_HALFWORD_7 0x1C /* OTP Low halfword 7 */
#define FMI_OTP_HIGH_HALFWORD_7 0x1E /* OTP High halfword 7 */
/* FMI sectors Masks */
#define FMI_B0S0_MASK 0x0001 /* FMI B0S0 mask */
#define FMI_B0S1_MASK 0x0002 /* FMI B0S1 mask */
#define FMI_B0S2_MASK 0x0004 /* FMI B0S2 mask */
#define FMI_B0S3_MASK 0x0008 /* FMI B0S3 mask */
#define FMI_B0S4_MASK 0x0010 /* FMI B0S4 mask */
#define FMI_B0S5_MASK 0x0020 /* FMI B0S5 mask */
#define FMI_B0S6_MASK 0x0040 /* FMI B0S6 mask */
#define FMI_B0S7_MASK 0x0080 /* FMI B0S7 mask */
#define FMI_B1S0_MASK 0x0100 /* FMI B1S0 mask */
#define FMI_B1S1_MASK 0x0200 /* FMI B1S1 mask */
#define FMI_B1S2_MASK 0x0400 /* FMI B1S2 mask */
#define FMI_B1S3_MASK 0x0800 /* FMI B1S3 mask */
/* Timeout error */
#define FMI_TIME_OUT_ERROR 0x00 /* Timeout error */
#define FMI_NO_TIME_OUT_ERROR 0x01 /* No Timeout error */
/* Module private variables --------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void FMI_BankRemapConfig(u8 FMI_BootBankSize, u8 FMI_NonBootBankSize, \
u32 FMI_BootBankAddress, u32 FMI_NonBootBankAddress);
void FMI_Config(u16 FMI_ReadWaitState, u32 FMI_WriteWaitState, u16 FMI_PWD,\
u16 FMI_LVDEN, u16 FMI_FreqRange);
void FMI_EraseSector(vu32 FMI_Sector);
void FMI_EraseBank(vu32 FMI_Bank);
void FMI_WriteHalfWord(u32 FMI_Address, u16 FMI_Data);
void FMI_WriteOTPHalfWord(u8 FMI_OTPHWAddress, u16 FMI_OTPData);
u32 FMI_ReadWord(u32 FMI_Address);
u32 FMI_ReadOTPData(u8 FMI_OTPAddress);
FlagStatus FMI_GetFlagStatus(u8 FMI_Flag, vu32 FMI_Bank);
u16 FMI_GetReadWaitStateValue(void);
u16 FMI_GetWriteWaitStateValue(void);
void FMI_SuspendEnable(vu32 FMI_Bank);
void FMI_ResumeEnable(vu32 FMI_Bank);
void FMI_ClearFlag(vu32 FMI_Bank);
void FMI_WriteProtectionCmd(vu32 FMI_Sector, FunctionalState FMI_NewState);
FlagStatus FMI_GetWriteProtectionStatus(u32 FMI_Sector_Protection);
u8 FMI_WaitForLastOperation(vu32 FMI_Bank);
#endif /* __91x_FMI_H */
/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/

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/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
* File Name : 91x_gpio.c
* Author : MCD Application Team
* Date First Issued : 05/18/2006 : Version 1.0
* Description : This file provides all the GPIO software functions.
********************************************************************************
* History:
* 05/24/2006 : Version 1.1
* 05/18/2006 : Version 1.0
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Includes ------------------------------------------------------------------*/
#include "91x_gpio.h"
#include "91x_scu.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
static u8 GPIO_GetGPIONumber(GPIO_TypeDef* GPIOx);
/* Private functions ---------------------------------------------------------*/
/*******************************************************************************
* Function Name : GPIO_DeInit
* Description : Deinitializes the GPIOx peripheral registers to their default
* reset values.
* Input : GPIOx: where x can be (0..9) to select the GPIO peripheral.
* Output : None
* Return : None
*******************************************************************************/
void GPIO_DeInit(GPIO_TypeDef* GPIOx)
{
/* Reset the GPIO registers values */
if(GPIOx == GPIO0)
{
SCU_APBPeriphReset(__GPIO0,ENABLE);
SCU_APBPeriphReset(__GPIO0,DISABLE);
SCU->GPIOTYPE[0x00] = 0x0000 ;
SCU->GPIOOUT[0x00] = 0x0000;
SCU->GPIOIN[0x00] = 0x0000;
}
if(GPIOx == GPIO1)
{
SCU_APBPeriphReset(__GPIO1,ENABLE);
SCU_APBPeriphReset(__GPIO1,DISABLE);
SCU->GPIOTYPE[0x01] = 0x0000 ;
SCU->GPIOOUT[0x01] = 0x0000;
SCU->GPIOIN[0x01] = 0x0000;
}
if(GPIOx == GPIO2)
{
SCU_APBPeriphReset(__GPIO2,ENABLE);
SCU_APBPeriphReset(__GPIO2,DISABLE);
SCU->GPIOTYPE[0x02] = 0x0000 ;
SCU->GPIOOUT[0x02] = 0x0000;
SCU->GPIOIN[0x02] = 0x0000;
}
if(GPIOx == GPIO3)
{
SCU_APBPeriphReset(__GPIO3,ENABLE);
SCU_APBPeriphReset(__GPIO3,DISABLE);
SCU->GPIOTYPE[0x03] = 0x0000 ;
SCU->GPIOOUT[0x03] = 0x0000;
SCU->GPIOIN[0x03] = 0x0000;
}
if(GPIOx == GPIO4)
{
SCU_APBPeriphReset(__GPIO4,ENABLE);
SCU_APBPeriphReset(__GPIO4,DISABLE);
SCU->GPIOTYPE[0x04] = 0x0000 ;
SCU->GPIOOUT[0x04] = 0x0000;
SCU->GPIOIN[0x04] = 0x0000;
SCU->GPIOANA = 0x00;
}
if(GPIOx == GPIO5)
{
SCU_APBPeriphReset(__GPIO5,ENABLE);
SCU_APBPeriphReset(__GPIO5,DISABLE);
SCU->GPIOTYPE[0x05] = 0x0000 ;
SCU->GPIOOUT[0x05] = 0x0000;
SCU->GPIOIN[0x05] = 0x0000;
}
if(GPIOx == GPIO6)
{
SCU_APBPeriphReset(__GPIO6,ENABLE);
SCU_APBPeriphReset(__GPIO6,DISABLE);
SCU->GPIOTYPE[0x06] = 0x0000 ;
SCU->GPIOOUT[0x06] = 0x0000;
SCU->GPIOIN[0x06] = 0x0000;
}
if(GPIOx == GPIO7)
{
SCU_APBPeriphReset(__GPIO7,ENABLE);
SCU_APBPeriphReset(__GPIO7,DISABLE);
SCU->GPIOOUT[0x07] = 0xAAAA;
SCU->GPIOOUT[0x07] = 0x0000;
SCU->GPIOIN[0x07] = 0x0000;
}
if(GPIOx == GPIO8)
{
SCU_APBPeriphReset(__GPIO8,ENABLE);
SCU_APBPeriphReset(__GPIO8,DISABLE);
SCU->GPIOEMI = 0x00;
}
if(GPIOx == GPIO9)
{
SCU_APBPeriphReset(__GPIO9,ENABLE);
SCU_APBPeriphReset(__GPIO9,DISABLE);
SCU->GPIOEMI = 0x00;
}
}
/*******************************************************************************
* Function Name : GPIO_Init
* Description : Initializes the GPIOx peripheral according to the specified
* parameters in the GPIO_InitStruct .
* Input :- GPIOx: where x can be (0..9) to select the GPIO peripheral.
* - GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that
* contains the configuration information for the specified GPIO
* peripheral.
* Output : None
* Return : None
*******************************************************************************/
void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
{
/* Select pin direction */
u8 PinNumber = 0;
u8 Counter = 0;
u8 GPIO_Number = 0;
GPIO_Number = GPIO_GetGPIONumber(GPIOx);
if(GPIO_InitStruct->GPIO_Direction == GPIO_PinOutput)
{
GPIOx->DDR |= GPIO_InitStruct->GPIO_Pin;
}
else
{
GPIOx->DDR &= ~GPIO_InitStruct->GPIO_Pin;
}
for (Counter = 0; Counter < 8;Counter++)
{
/*Search pin number*/
PinNumber = (GPIO_InitStruct->GPIO_Pin & (1 <<Counter));
if((PinNumber >> Counter) == 1)
{
/*Output ALternate 0*/
SCU->GPIOOUT[GPIO_Number] &= ~(0x3 <<(Counter *2));
if(GPIO_InitStruct->GPIO_Alternate == GPIO_OutputAlt1)
{
/*Output ALternate 1*/
SCU->GPIOOUT[GPIO_Number] |= 1 << (Counter *2);
}
if(GPIO_InitStruct->GPIO_Alternate == GPIO_OutputAlt2)
{
/*Output ALternate 2*/
SCU->GPIOOUT[GPIO_Number] |= 0x2 << (Counter *2);
}
if(GPIO_InitStruct->GPIO_Alternate == GPIO_OutputAlt3)
{
/*Output ALternate 3*/
SCU->GPIOOUT[GPIO_Number] |= 0x3 << (Counter *2);
}
/*Type configuration: PushPull or Open Collector*/
SCU->GPIOTYPE[GPIO_Number] &= ~(0x1 << Counter) ;
if(GPIO_InitStruct->GPIO_Type == GPIO_Type_OpenCollector)
{
/*Open Drain configuration*/
SCU->GPIOTYPE[GPIO_Number] |= 0x1 << Counter;
}
/*IP Connected disable*/
SCU->GPIOIN[GPIO_Number] &= ~(0x1 << Counter) ;
if(GPIO_InitStruct->GPIO_IPConnected == GPIO_IPConnected_Enable)
{
/*IP Connected enable*/
SCU->GPIOIN[GPIO_Number] |= 0x1 << Counter;
}
}
}
}
/*******************************************************************************
* Function Name : GPIO_StructInit
* Description : Initialize the GPIO Init Structure parameters
* Input : GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure
* which will be initialized.
* Output : None
* Return : None
*******************************************************************************/
void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
{
/* Reset GPIO init structure parameters values */
GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;
GPIO_InitStruct->GPIO_Direction = GPIO_PinInput;
GPIO_InitStruct->GPIO_Type = GPIO_Type_PushPull;
GPIO_InitStruct->GPIO_IPConnected = GPIO_IPConnected_Disable;
GPIO_InitStruct->GPIO_Alternate = GPIO_InputAlt1;
}
/*******************************************************************************
* Function Name : GPIO_ReadBit
* Description : Reads the specified port pin
* Input : - GPIOx: where x can be (0..9) to select the GPIO peripheral.
* : - GPIO_Pin: the Pin number. This parameter can be GPIO_Pin_x
* where x can be (0..7).
* Output : None
* Return : The port pin value
*******************************************************************************/
u8 GPIO_ReadBit(GPIO_TypeDef* GPIOx, u8 GPIO_Pin)
{
if ((((GPIOx->DR[GPIO_Pin<<2])) & GPIO_Pin) != Bit_RESET )
{
return Bit_SET;
}
else
{
return Bit_RESET;
}
}
/*******************************************************************************
* Function Name : GPIO_Read
* Description : Reads the specified GPIO data port
* Input : - GPIOx: where x can be (0..9) to select the GPIO peripheral.
* Output : None
* Return : GPIO data port word value.
*******************************************************************************/
u8 GPIO_Read(GPIO_TypeDef* GPIOx)
{
return (GPIOx->DR[0x3FC]);
}
/*******************************************************************************
* Function Name : GPIO_WriteBit
* Description : Sets or clears the selected data port bit.
* Input : - GPIOx: where x can be (0..9) to select the GPIO peripheral.
* - GPIO_Pin: the Pin number. This parameter can be GPIO_Pin_x
* where x can be (0..7).
* - BitVal: this parameter specifies the value to be written
* to the selected bit.
* BitVal must be one of the BitAction enum values:
* - Bit_RESET: to clear the port pin
* - Bit_SET: to set the port pin
* Output : None
* Return : None
*******************************************************************************/
void GPIO_WriteBit(GPIO_TypeDef* GPIOx, u8 GPIO_Pin, BitAction BitVal)
{
if(BitVal == Bit_SET)
{
GPIOx->DR[GPIO_Pin <<2] = GPIO_Pin;
}
else
{
GPIOx->DR[GPIO_Pin <<2] = 0x00;
}
}
/*******************************************************************************
* Function Name : GPIO_Write
* Description : Writes the passed value in the selected data GPIOx port
* register.
* Input :- GPIOx: where x can be (0..9) to select the GPIO peripheral.
* - PortVal: the value to be written to the data port register.
* Output : None
* Return : None
*******************************************************************************/
void GPIO_Write(GPIO_TypeDef* GPIOx, u8 PortVal)
{
GPIOx->DR[0x3FC] = PortVal;
}
/*******************************************************************************
* Function Name : GPIO_EMIConfig
* Description : Enables or disables GPIO 8 and 9 in EMI mode.
* Input : - NewState: new state of the EMI.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void GPIO_EMIConfig(FunctionalState NewState)
{
if(NewState == ENABLE)
{
SCU->GPIOEMI = 0x01;
}
else
{
SCU->GPIOEMI = 0x00;
}
}
/*******************************************************************************
* Function Name : GPIO_ANAPinConfig
* Description : Enables or disables pins from GPIO 4 in Analogue mode.
* Input :- GPIO_ANAChannel: selects the ADC channel pin.
* This parameter can be one of the following values:
* GPIO_ANAChannel0
* GPIO_ANAChannel1
* GPIO_ANAChannel2
* GPIO_ANAChannel3
* GPIO_ANAChannel4
* GPIO_ANAChannel5
* GPIO_ANAChannel6
* GPIO_ANAChannel7
* GPIO_ANAChannelALL
* - NewState: new state of the port pin.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void GPIO_ANAPinConfig(u8 GPIO_ANAChannel, FunctionalState NewState)
{
if(NewState == ENABLE)
{
if(GPIO_ANAChannel == GPIO_ANAChannelALL)
{
SCU->GPIOOUT[4] = 0x0000;
SCU->GPIOIN[4] = 0x00;
}
else
{
SCU->GPIOOUT[4] &= ~(0x3<<(GPIO_ANAChannel-1));
SCU->GPIOIN[4] &= ~GPIO_ANAChannel;
}
SCU->GPIOANA |= GPIO_ANAChannel;
}
else
{
SCU->GPIOANA &= ~GPIO_ANAChannel;
}
}
/*******************************************************************************
* Function Name : GPIO_GetGPIONumber
* Description : searche the GPIO number.
* Input : GPIOx: where x can be (0..9) to select the GPIO peripheral.
* Output : None
* Return : GPIO number
*******************************************************************************/
u8 GPIO_GetGPIONumber(GPIO_TypeDef* GPIOx)
{
if(GPIOx == GPIO1)
{
return 1;
}
if(GPIOx == GPIO2)
{
return 2;
}
if(GPIOx == GPIO3)
{
return 3;
}
if(GPIOx == GPIO4)
{
return 4;
}
if(GPIOx == GPIO5)
{
return 5;
}
if(GPIOx == GPIO6)
{
return 6;
}
if(GPIOx == GPIO7)
{
return 7;
}
if(GPIOx == GPIO8)
{
return 8;
}
if(GPIOx == GPIO9)
{
return 9;
}
return 0;
}
/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/

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/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
* File Name : 91x_gpio.h
* Author : MCD Application Team
* Date First Issued : 05/18/2006 : Version 1.0
* Description : This file contains all the functions prototypes for the
* GPIO software library.
********************************************************************************
* History:
* 05/24/2006 : Version 1.1
* 05/18/2006 : Version 1.0
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion ------------------------------------ */
#ifndef _91x_GPIO_H
#define _91x_GPIO_H
/* Includes ------------------------------------------------------------------*/
#include "91x_map.h"
/* GPIO Init structure definition */
typedef struct
{
u8 GPIO_Pin;
u8 GPIO_Direction;
u8 GPIO_Type;
u8 GPIO_IPConnected;
u16 GPIO_Alternate;
}GPIO_InitTypeDef;
/* Bit_SET and Bit_RESET enumeration */
typedef enum
{ Bit_RESET = 0,
Bit_SET
}BitAction;
/* Exported constants --------------------------------------------------------*/
#define GPIO_Pin_None 0x00
#define GPIO_Pin_0 0x01
#define GPIO_Pin_1 0x02
#define GPIO_Pin_2 0x04
#define GPIO_Pin_3 0x08
#define GPIO_Pin_4 0x10
#define GPIO_Pin_5 0x20
#define GPIO_Pin_6 0x40
#define GPIO_Pin_7 0x80
#define GPIO_Pin_All 0xFF
#define GPIO_PinInput 0x00
#define GPIO_PinOutput 0x01
#define GPIO_Type_PushPull 0x00
#define GPIO_Type_OpenCollector 0x01
#define GPIO_IPConnected_Disable 0x00
#define GPIO_IPConnected_Enable 0x01
#define GPIO_InputAlt1 0x00
#define GPIO_OutputAlt1 0x01
#define GPIO_OutputAlt2 0x02
#define GPIO_OutputAlt3 0x03
#define GPIO_ANAChannel0 0x01
#define GPIO_ANAChannel1 0x02
#define GPIO_ANAChannel2 0x04
#define GPIO_ANAChannel3 0x08
#define GPIO_ANAChannel4 0x10
#define GPIO_ANAChannel5 0x20
#define GPIO_ANAChannel6 0x40
#define GPIO_ANAChannel7 0x80
#define GPIO_ANAChannelALL 0xFF
void GPIO_DeInit(GPIO_TypeDef* GPIOx);
void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
u8 GPIO_ReadBit(GPIO_TypeDef* GPIOx, u8 GPIO_Pin);
u8 GPIO_Read(GPIO_TypeDef* GPIOx);
void GPIO_WriteBit(GPIO_TypeDef* GPIOx, u8 GPIO_Pin, BitAction BitVal);
void GPIO_Write(GPIO_TypeDef* GPIOx, u8 PortVal);
void GPIO_EMIConfig(FunctionalState NewState);
void GPIO_ANAPinConfig(u8 GPIO_ANAChannel, FunctionalState NewState);
#endif /* _91x_GPIO_H */
/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/

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/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
* File Name : 91x_map.h
* Author : MCD Application Team
* Date First Issued : 05/18/2006 : Version 1.0
* Description : Peripherals registers definition and memory mapping.
********************************************************************************
* History:
* 05/24/2006 : Version 1.1
* 05/18/2006 : Version 1.0
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion ------------------------------------ */
#ifndef __91x_MAP_H
#define __91x_MAP_H
#ifndef EXT
#define EXT extern
#endif /* EXT */
/* Includes ------------------------------------------------------------------*/
#include "91x_conf.h"
#include "91x_type.h"
/******************************************************************************/
/* IP registers structures */
/******************************************************************************/
/*------------------------------------ FMI -----------------------------------*/
typedef struct
{
vu32 BBSR; /* Boot Bank Size Register */
vu32 NBBSR; /* Non-Boot Bank Size Register */
vu32 EMPTY1;
vu32 BBADR; /* Boot Bank Base Address Register */
vu32 NBBADR; /* Non-Boot Bank Base Address Register */
vu32 EMPTY2;
vu32 CR; /* Control Register */
vu32 SR; /* Status Register */
vu32 BCE5ADDR; /* BC Fifth Entry Target Address Register */
} FMI_TypeDef;
/*---------------------- Analog to Digital Convertor ------------------------*/
typedef struct
{
vu16 CR; /* Control Register */
vu16 EMPTY1;
vu16 CCR; /* Channel Configuration Register */
vu16 EMPTY2;
vu16 HTR; /* Higher Threshold Register */
vu16 EMPTY3;
vu16 LTR; /* Lower Threshold Register */
vu16 EMPTY4;
vu16 CRR; /* Compare Result Register */
vu16 EMPTY5;
vu16 DR0; /* Data Register for Channel 0 */
vu16 EMPTY6;
vu16 DR1; /* Data Register for Channel 1 */
vu16 EMPTY7;
vu16 DR2; /* Data Register for Channel 2 */
vu16 EMPTY8;
vu16 DR3; /* Data Register for Channel 3 */
vu16 EMPTY9;
vu16 DR4; /* Data Register for Channel 4 */
vu16 EMPTY10;
vu16 DR5; /* Data Register for Channel 5 */
vu16 EMPTY11;
vu16 DR6; /* Data Register for Channel 6 */
vu16 EMPTY12;
vu16 DR7; /* Data Register for Channel 7 */
vu16 EMPTY13;
vu16 PRS; /* Prescaler Value Register */
vu16 EMPTY14;
} ADC_TypeDef;
/*--------------------- AHB APB BRIDGE registers strcture --------------------*/
typedef struct
{
vu32 BSR; /* Bridge Status Register */
vu32 BCR; /* Bridge Configuration Register */
vu32 PAER; /* Peripheral Address Error register */
} AHBAPB_TypeDef;
/*--------------- Controller Area Network Interface Register -----------------*/
typedef struct
{
vu16 CRR; /* IFn Command request Register */
vu16 EMPTY1;
vu16 CMR; /* IFn Command Mask Register */
vu16 EMPTY2;
vu16 M1R; /* IFn Message Mask 1 Register */
vu16 EMPTY3;
vu16 M2R; /* IFn Message Mask 2 Register */
vu16 EMPTY4;
vu16 A1R; /* IFn Message Arbitration 1 Register */
vu16 EMPTY5;
vu16 A2R; /* IFn Message Arbitration 2 Register */
vu16 EMPTY6;
vu16 MCR; /* IFn Message Control Register */
vu16 EMPTY7;
vu16 DA1R; /* IFn DATA A 1 Register */
vu16 EMPTY8;
vu16 DA2R; /* IFn DATA A 2 Register */
vu16 EMPTY9;
vu16 DB1R; /* IFn DATA B 1 Register */
vu16 EMPTY10;
vu16 DB2R; /* IFn DATA B 2 Register */
vu16 EMPTY11[27];
} CAN_MsgObj_TypeDef;
typedef struct
{
vu16 CR; /* Control Register */
vu16 EMPTY1;
vu16 SR; /* Status Register */
vu16 EMPTY2;
vu16 ERR; /* Error counter Register */
vu16 EMPTY3;
vu16 BTR; /* Bit Timing Register */
vu16 EMPTY4;
vu16 IDR; /* Interrupt Identifier Register */
vu16 EMPTY5;
vu16 TESTR; /* Test Register */
vu16 EMPTY6;
vu16 BRPR; /* BRP Extension Register */
vu16 EMPTY7[3];
CAN_MsgObj_TypeDef sMsgObj[2];
vu16 EMPTY8[16];
vu16 TXR1R; /* Transmission request 1 Register */
vu16 EMPTY9;
vu16 TXR2R; /* Transmission Request 2 Register */
vu16 EMPTY10[13];
vu16 ND1R; /* New Data 1 Register */
vu16 EMPTY11;
vu16 ND2R; /* New Data 2 Register */
vu16 EMPTY12[13];
vu16 IP1R; /* Interrupt Pending 1 Register */
vu16 EMPTY13;
vu16 IP2R; /* Interrupt Pending 2 Register */
vu16 EMPTY14[13];
vu16 MV1R; /* Message Valid 1 Register */
vu16 EMPTY15;
vu16 MV2R; /* Message VAlid 2 Register */
vu16 EMPTY16;
} CAN_TypeDef;
/*----------------------- System Control Unit---------------------------------*/
typedef struct
{
vu32 CLKCNTR; /* Clock Control Register */
vu32 PLLCONF; /* PLL Configuration Register */
vu32 SYSSTATUS; /* System Status Register */
vu32 PWRMNG; /* Power Management Register */
vu32 ITCMSK; /* Interrupt Mask Register */
vu32 PCGRO; /* Peripheral Clock Gating Register 0 */
vu32 PCGR1; /* Peripheral Clock Gating Register 1 */
vu32 PRR0; /* Peripheral Reset Register 0 */
vu32 PRR1; /* Peripheral Reset Register 1 */
vu32 MGR0; /* Idle Mode Mask Gating Register 0 */
vu32 MGR1; /* Idle Mode Mask Gating Register 1 */
vu32 PECGR0; /* Peripheral Emulation Clock Gating Register 0 */
vu32 PECGR1; /* Peripheral Emulation Clock Gating Register 1 */
vu32 SCR0; /* System Configuration Register 0 */
vu32 SCR1; /* System Configuration Register 1 */
vu32 SCR2; /* System Configuration Register 2 */
u32 EMPTY1;
vu32 GPIOOUT[8]; /* GPIO Output Registers */
vu32 GPIOIN[8]; /* GPIO Input Registers */
vu32 GPIOTYPE[10];/* GPIO Type Registers */
vu32 GPIOEMI; /* GPIO EMI Selector Register */
vu32 WKUPSEL; /* Wake-Up Selection Register */
u32 EMPTY2[2];
vu32 GPIOANA; /* GPIO Analag mode Register */
} SCU_TypeDef;
/*------------------------- DMA Channelx Registers ---------------------------*/
typedef struct
{
vu32 SRC; /* Channelx Source Address Register */
vu32 DES; /* Channelx Destination Address Register */
vu32 LLI; /* Channelx Lincked List Item Register */
vu32 CC; /* Channelx Contol Register */
vu32 CCNF; /* Channelx Configuration Register */
} DMA_Channel_TypeDef;
/* x can be ,0,1,2,3,4,5,6 or 7. There are eight Channels AHB BUS Master */
/*----------------------------- DMA Controller -------------------------------*/
typedef struct
{
vu32 ISR; /* Interrupt Status Register */
vu32 TCISR; /* Terminal Count Interrupt Status Register */
vu32 TCICR; /* Terminal CountInterrupt Clear Register */
vu32 EISR; /* Error Interrupt Status Register */
vu32 EICR; /* Error Interrupt Clear Register */
vu32 TCRISR; /* Terminal Count Raw Interrupt Status Register */
vu32 ERISR; /* Raw Error Interrupt Status Register */
vu32 ENCSR; /* Enabled Channel Status Register */
vu32 SBRR; /* Software Burst Request Register */
vu32 SSRR; /* Software Single Request Register */
vu32 SLBRR; /* Software Last Burst Request Register */
vu32 SLSRR; /* Software Last Single Request Register */
vu32 CNFR; /* Configuration Register */
vu32 SYNR; /* Syncronization Register */
} DMA_TypeDef;
/*--------------------------------- TIM Timer --------------------------------*/
typedef struct
{
vu16 IC1R; /* Input Capture 1 Register */
vu16 EMPTY1;
vu16 IC2R; /* Input Capture 2 Register */
vu16 EMPTY2;
vu16 OC1R; /* Output Compare 1 Register */
vu16 EMPTY3;
vu16 OC2R; /* Output Compare 2 Register */
vu16 EMPTY4;
vu16 CNTR; /* Counter Register */
vu16 EMPTY5;
vu16 CR1; /* Control Register 1 */
vu16 EMPTY6;
vu16 CR2; /* Control Register 2 */
vu16 EMPTY7;
vu16 SR; /* Status Register */
vu16 EMPTY8;
} TIM_TypeDef;
/*---------------------------- EMI Bankx Registers ---------------------------*/
typedef struct
{
vu32 ICR; /* Bankx Idle Cycle Control Register */
vu32 RCR; /* Bankx Read Wait State Control Register */
vu32 WCR; /* Bankx Write Wait State Control Register */
vu32 OECR; /* Bankx Output Enable Assertion Delay Control Register */
vu32 WECR; /* Bankx Write Enable Assertion Delay Control Register */
vu32 BCR; /* Bankx Control Register */
} EMI_Bank_TypeDef;
/*---------------------------- Ethernet Controller ---------------------------*/
/* MAC Registers */
typedef struct
{
vu32 MCR; /* ENET Control Register */
vu32 MAH; /* ENET Address High Register */
vu32 MAL; /* ENET Address Low Register */
vu32 MCHA; /* Multicast Address High Register */
vu32 MCLA; /* Multicast Address Low Register */
vu32 MIIA; /* MII Address Register */
vu32 MIID; /* MII Data Register */
vu32 MCF; /* ENET Control Frame Register */
vu32 VL1; /* VLAN1 Register */
vu32 VL2; /* VLAN2 register */
vu32 MTS; /* ENET Transmission Status Register */
vu32 MRS; /* ENET Reception Status Register */
} ENET_MAC_TypeDef;
/* DMA Registers */
typedef struct
{
vu32 SCR; /* DMA Status and Control Register */
vu32 IER; /* DMA Interrupt Sources Enable Register */
vu32 ISR; /* DMA Interrupt Status Register */
vu32 CCR; /* Clock Control Relation : HCLK, PCLK and
ENET_CLK phase relations */
vu32 RXSTR; /* Rx DMA start Register */
vu32 RXCR; /* Rx DMA Control Register */
vu32 RXSAR; /* Rx DMA Base Address Register */
vu32 RXNDAR; /* Rx DMA Next Descriptor Address Register */
vu32 RXCAR; /* Rx DMA Current Address Register */
vu32 RXCTCR; /* Rx DMA Current Transfer Count Register */
vu32 RXTOR; /* Rx DMA FIFO Time Out Register */
vu32 RXSR; /* Rx DMA FIFO Status Register */
vu32 TXSTR; /* Tx DMA start Register */
vu32 TXCR; /* Tx DMA Control Register */
vu32 TXSAR; /* Tx DMA Base Address Register */
vu32 TXNDAR; /* Tx DMA Next Descriptor Address Register */
vu32 TXCAR; /* Tx DMA Current Address Register */
vu32 TXTCR; /* Tx DMA Current Transfer Count Register */
vu32 TXTOR; /* Tx DMA FIFO Time Out Register */
vu32 TXSR; /* Tx DMA FIFO Status Register */
} ENET_DMA_TypeDef;
/*------------------------------------- GPIO ---------------------------------*/
typedef struct
{
vu8 DR[1021]; /* Data Register */
vu32 DDR; /* Data Direction Register */
} GPIO_TypeDef;
/*-------------------------------- I2C interface -----------------------------*/
typedef struct
{
vu8 CR; /* Control Register */
vu8 EMPTY1[3];
vu8 SR1; /* Status Register 1 */
vu8 EMPTY2[3];
vu8 SR2; /* Status Register 2 */
vu8 EMPTY3[3];
vu8 CCR; /* Clock Control Register */
vu8 EMPTY4[3];
vu8 OAR1; /* Own Address Register 1 */
vu8 EMPTY5[3];
vu8 OAR2; /* Own Address Register 2 */
vu8 EMPTY6[3];
vu8 DR; /* Data Register */
vu8 EMPTY7[3];
vu8 ECCR; /* Extended Clock Control Register */
vu8 EMPTY8[3];
} I2C_TypeDef;
/*------------------------------------- VIC ----------------------------------*/
typedef struct
{
vu32 ISR; /* IRQ Status Register */
vu32 FSR; /* FIQ Status Register */
vu32 RINTSR; /* Raw Interrupt Status Register */
vu32 INTSR; /* Interrupt Select Register */
vu32 INTER; /* Interrupt Enable Register */
vu32 INTECR; /* Interrupt Enable Clear Register */
vu32 SWINTR; /* Software Interrupt Register */
vu32 SWINTCR; /* Software Interrupt clear Register */
vu32 PER; /* Protection Enable Register */
vu32 EMPTY1[3];
vu32 VAR; /* Vector Address Register */
vu32 DVAR; /* Default Vector Address Register */
vu32 EMPTY2[50];
vu32 VAiR[16]; /* Vector Address 0-15 Register */
vu32 EMPTY3[48];
vu32 VCiR[16]; /* Vector Control 0-15 Register */
} VIC_TypeDef;
/*-------------------------------- Motor Control -----------------------------*/
typedef struct
{
vu16 TCPT; /* Tacho Capture Register */
vu16 EMPTY1;
vu16 TCMP; /* Tacho Compare Register */
vu16 EMPTY2;
vu16 IPR; /* Input Pending Register */
vu16 EMPTY3;
vu16 TPRS; /* Tacho Prescaler Register */
vu16 EMPTY4;
vu16 CPRS; /* PWM Counter Prescaler Register */
vu16 EMPTY5;
vu16 REP; /* Repetition Counter Register */
vu16 EMPTY6;
vu16 CMPW; /* Compare Phase W Preload Register */
vu16 EMPTY7;
vu16 CMPV; /* Compare Phase V Preload Register */
vu16 EMPTY8;
vu16 CMPU; /* Compare Phase U Preload Register */
vu16 EMPTY9;
vu16 CMP0; /* Compare 0 Preload Register */
vu16 EMPTY10;
vu16 PCR0; /* Peripheral Control Register 0 */
vu16 EMPTY11;
vu16 PCR1; /* Peripheral Control Register 1 */
vu16 EMPTY12;
vu16 PCR2; /* Peripheral Control Register 2 */
vu16 EMPTY13;
vu16 PSR; /* Polarity Selection Register */
vu16 EMPTY14;
vu16 OPR; /* Output Peripheral Register */
vu16 EMPTY15;
vu16 IMR; /* Interrupt Mask Register */
vu16 EMPTY16;
vu16 DTG; /* Dead Time Generator Register */
vu16 EMPTY17;
vu16 ESC; /* Emergency Stop Clear Register */
vu16 EMPTY18;
}MC_TypeDef;
/*------------------------------------- RTC ----------------------------------*/
typedef struct
{
vu32 TR; /* Time Register */
vu32 DTR; /* Date Register */
vu32 ATR; /* Alarm time Register */
vu32 CR; /* Control Register */
vu32 SR; /* Status Register */
vu32 MILR; /* Millisec Register */
}RTC_TypeDef;
/*------------------------------------- SSP ----------------------------------*/
typedef struct
{
vu16 CR0; /* Control Register 1 */
vu16 EMPTY1;
vu16 CR1; /* Control Register 2 */
vu16 EMPTY2;
vu16 DR; /* Data Register */
vu16 EMPTY3;
vu16 SR; /* Status Register */
vu16 EMPTY4;
vu16 PR; /* Clock Prescale Register */
vu16 EMPTY5;
vu16 IMSCR; /* Interrupt Mask Set or Clear Register */
vu16 EMPTY6;
vu16 RISR; /* Raw Interrupt Status Register */
vu16 EMPTY7;
vu16 MISR; /* Masked Interrupt Status Register */
vu16 EMPTY8;
vu16 ICR; /* Interrupt Clear Register */
vu16 EMPTY9;
vu16 DMACR; /* DMA Control Register */
vu16 EMPTY10;
}SSP_TypeDef;
/*------------------------------------ UART ----------------------------------*/
typedef struct
{
vu16 DR; /* Data Register */
vu16 EMPTY1;
vu16 RSECR; /* Receive Status Register (read)/Error Clear Register (write) */
vu16 EMPTY2[9];
vu16 FR; /* Flag Register */
vu16 EMPTY3[3];
vu16 ILPR; /* IrDA Low-Power counter Register */
vu16 EMPTY4;
vu16 IBRD; /* Integer Baud Rate Divisor Register */
vu16 EMPTY5;
vu16 FBRD; /* Fractional Baud Rate Divisor Register */
vu16 EMPTY6;
vu16 LCR; /* Line Control Register, High byte */
vu16 EMPTY7;
vu16 CR; /* Control Register */
vu16 EMPTY8;
vu16 IFLS; /* Interrupt FIFO Level Select Register */
vu16 EMPTY9;
vu16 IMSC; /* Interrupt Mask Set/Clear Register */
vu16 EMPTY10;
vu16 RIS; /* Raw Interrupt Status Register */
vu16 EMPTY11;
vu16 MIS; /* Masked Interrupt Status Register */
vu16 EMPTY12;
vu16 ICR; /* Interrupt Clear Register */
vu16 EMPTY13;
vu16 DMACR; /* DMA Control Register */
vu16 EMPTY14;
}UART_TypeDef;
/*------------------------------- Wake-up System -----------------------------*/
typedef struct
{
vu32 CTRL; /* Control Register */
vu32 MR; /* Mask Register */
vu32 TR; /* Trigger Register */
vu32 PR; /* Pending Register */
vu32 INTR; /* Software Interrupt Register */
} WIU_TypeDef;
/*------------------------------- WatchDog Timer -----------------------------*/
typedef struct
{
vu16 CR; /* Control Register */
vu16 EMPTY1;
vu16 PR; /* Presclar Register */
vu16 EMPTY2;
vu16 VR; /* Pre-load Value Register */
vu16 EMPTY3;
vu16 CNT; /* Counter Register */
vu16 EMPTY4;
vu16 SR; /* Status Register */
vu16 EMPTY5;
vu16 MR; /* Mask Register */
vu16 EMPTY6;
vu16 KR; /* Key Register */
vu16 EMPTY7;
} WDG_TypeDef;
/*******************************************************************************
* Memory Mapping of STR91x *
*******************************************************************************/
#define AHB_APB_BRDG0_U (0x58000000) /* AHB/APB Bridge 0 UnBuffered Space */
#define AHB_APB_BRDG0_B (0x48000000) /* AHB/APB Bridge 0 Buffered Space */
#define AHB_APB_BRDG1_U (0x5C000000) /* AHB/APB Bridge 1 UnBuffered Space */
#define AHB_APB_BRDG1_B (0x4C000000) /* AHB/APB Bridge 1 Buffered Space */
#define AHB_EMI_U (0x74000000) /* EMI UnBuffered Space */
#define AHB_EMI_B (0x64000000) /* EMI Buffered Space */
#define AHB_DMA_U (0x78000000) /* DMA UnBuffered Space */
#define AHB_DMA_B (0x68000000) /* DMA Buffered Space */
#define AHB_ENET_MAC_U (0x7C000400) /* ENET_MAC UnBuffered Space */
#define AHB_ENET_MAC_B (0x6C000000) /* ENET_MAC Buffered Space */
#define AHB_ENET_DMA_U (0x7C000000) /* ENET_DMA Unbuffered Space */
#define AHB_ENET_DMA_B (0x6C000400) /* ENET_DMA Buffered Space */
#define AHB_VIC1_U (0xFC000000) /* Secondary VIC1 UnBuffered Space */
#define AHB_VIC0_U (0xFFFFF000) /* Primary VIC0 UnBuffered Space */
#define AHB_FMI_U (0x54000000) /* FMI Unbuffered Space */
#define AHB_FMI_B (0x44000000) /* FMI buffered Space */
/*******************************************************************************
* Addresses related to the VICs' peripherals *
*******************************************************************************/
#define VIC0_BASE (AHB_VIC0_U)
#define VIC1_BASE (AHB_VIC1_U)
/*******************************************************************************
* Addresses related to the EMI banks *
*******************************************************************************/
#define AHB_EMIB3_OFST (0x00000040) /* Offset of EMI bank3 */
#define AHB_EMIB2_OFST (0x00000020) /* Offset of EMI bank2 */
#define AHB_EMIB1_OFST (0x00000000) /* Offset of EMI bank1 */
#define AHB_EMIB0_OFST (0x000000E0) /* Offset of EMI bank0 */
/*******************************************************************************
* Addresses related to the DMA peripheral *
*******************************************************************************/
#define AHB_DMA_Channel0_OFST (0x00000100) /* Offset of Channel 0 */
#define AHB_DMA_Channel1_OFST (0x00000120) /* Offset of Channel 1 */
#define AHB_DMA_Channel2_OFST (0x00000140) /* Offset of Channel 2 */
#define AHB_DMA_Channel3_OFST (0x00000160) /* Offset of Channel 3 */
#define AHB_DMA_Channel4_OFST (0x00000180) /* Offset of Channel 4 */
#define AHB_DMA_Channel5_OFST (0x000001A0) /* Offset of Channel 5 */
#define AHB_DMA_Channel6_OFST (0x000001C0) /* Offset of Channel 6 */
#define AHB_DMA_Channel7_OFST (0x000001E0) /* Offset of Channel 7 */
/*******************************************************************************
* Addresses related to the APB0 sub-system *
*******************************************************************************/
#define APB_WIU_OFST (0x00001000) /* Offset of WIU */
#define APB_TIM0_OFST (0x00002000) /* Offset of TIM0 */
#define APB_TIM1_OFST (0x00003000) /* Offset of TIM1 */
#define APB_TIM2_OFST (0x00004000) /* Offset of TIM2 */
#define APB_TIM3_OFST (0x00005000) /* Offset of TIM3 */
#define APB_GPIO0_OFST (0x00006000) /* Offset of GPIO0 */
#define APB_GPIO1_OFST (0x00007000) /* Offset of GPIO1 */
#define APB_GPIO2_OFST (0x00008000) /* Offset of GPIO2 */
#define APB_GPIO3_OFST (0x00009000) /* Offset of GPIO3 */
#define APB_GPIO4_OFST (0x0000A000) /* Offset of GPIO4 */
#define APB_GPIO5_OFST (0x0000B000) /* Offset of GPIO5 */
#define APB_GPIO6_OFST (0x0000C000) /* Offset of GPIO6 */
#define APB_GPIO7_OFST (0x0000D000) /* Offset of GPIO7 */
#define APB_GPIO8_OFST (0x0000E000) /* Offset of GPIO8 */
#define APB_GPIO9_OFST (0x0000F000) /* Offset of GPIO9 */
/*******************************************************************************
* Addresses related to the APB1 sub-system *
*******************************************************************************/
#define APB_RTC_OFST (0x00001000) /* Offset of RTC */
#define APB_SCU_OFST (0x00002000) /* Offset of System Controller */
#define APB_MC_OFST (0x00003000) /* Offset of Motor Control */
#define APB_UART0_OFST (0x00004000) /* Offset of UART0 */
#define APB_UART1_OFST (0x00005000) /* Offset of UART1 */
#define APB_UART2_OFST (0x00006000) /* Offset of UART2 */
#define APB_SSP0_OFST (0x00007000) /* Offset of SSP0 */
#define APB_SSP1_OFST (0x00008000) /* Offset of SSPI */
#define APB_CAN_OFST (0x00009000) /* Offset of CAN */
#define APB_ADC_OFST (0x0000A000) /* Offset of ADC */
#define APB_WDG_OFST (0x0000B000) /* Offset of WDG */
#define APB_I2C0_OFST (0x0000C000) /* Offset of I2C0 */
#define APB_I2C1_OFST (0x0000D000) /* Offset of I2C1 */
/*----------------------------------------------------------------------------*/
/*----------------------------- Unbuffered Mode ------------------------------*/
/*----------------------------------------------------------------------------*/
#ifndef Buffered
/*******************************************************************************
* AHBAPB peripheral Unbuffered Base Address *
*******************************************************************************/
#define AHBAPB0_BASE (AHB_APB_BRDG0_U)
#define AHBAPB1_BASE (AHB_APB_BRDG1_U)
/*******************************************************************************
* ENET peripheral Unbuffered Base Address *
*******************************************************************************/
#define ENET_MAC_BASE (AHB_ENET_MAC_U)
#define ENET_DMA_BASE (AHB_ENET_DMA_U)
/*******************************************************************************
* DMA peripheral Unbuffered Base Address *
*******************************************************************************/
#define DMA_BASE (AHB_DMA_U)
/*******************************************************************************
* EMI peripheral Unbuffered Base Address *
*******************************************************************************/
#define EMI_BASE (AHB_EMI_U)
/*******************************************************************************
* FMI peripheral Unbuffered Base Address *
*******************************************************************************/
#define FMI_BASE (AHB_FMI_U)
#else /* Buffered */
/*----------------------------------------------------------------------------*/
/*------------------------------ Buffered Mode -------------------------------*/
/*----------------------------------------------------------------------------*/
/*******************************************************************************
* AHBAPB peripheral Buffered Base Address *
*******************************************************************************/
#define AHBAPB0_BASE (AHB_APB_BRDG0_B)
#define AHBAPB1_BASE (AHB_APB_BRDG1_B)
/*******************************************************************************
* ENET peripheral Unbuffered Base Address *
*******************************************************************************/
#define ENET_MAC_BASE (AHB_ENET_MAC_B)
#define ENET_DMA_BASE (AHB_ENET_DMA_B)
/*******************************************************************************
* DMA peripheral Buffered Base Address *
*******************************************************************************/
#define DMA_BASE (AHB_DMA_B)
/*******************************************************************************
* EMI peripheral Buffered Base Address *
*******************************************************************************/
#define EMI_BASE (AHB_EMI_B)
/*******************************************************************************
* FMI peripheral Buffered Base Address *
*******************************************************************************/
#define FMI_BASE (AHB_FMI_B)
#endif /* Buffered */
/*******************************************************************************
* DMA channels Base Address *
*******************************************************************************/
#define DMA_Channel0_BASE (DMA_BASE + AHB_DMA_Channel0_OFST)
#define DMA_Channel1_BASE (DMA_BASE + AHB_DMA_Channel1_OFST)
#define DMA_Channel2_BASE (DMA_BASE + AHB_DMA_Channel2_OFST)
#define DMA_Channel3_BASE (DMA_BASE + AHB_DMA_Channel3_OFST)
#define DMA_Channel4_BASE (DMA_BASE + AHB_DMA_Channel4_OFST)
#define DMA_Channel5_BASE (DMA_BASE + AHB_DMA_Channel5_OFST)
#define DMA_Channel6_BASE (DMA_BASE + AHB_DMA_Channel6_OFST)
#define DMA_Channel7_BASE (DMA_BASE + AHB_DMA_Channel7_OFST)
/*******************************************************************************
* EMI Banks peripheral Base Address *
*******************************************************************************/
#define EMI_Bank0_BASE (EMI_BASE + AHB_EMIB0_OFST)
#define EMI_Bank1_BASE (EMI_BASE + AHB_EMIB1_OFST)
#define EMI_Bank2_BASE (EMI_BASE + AHB_EMIB2_OFST)
#define EMI_Bank3_BASE (EMI_BASE + AHB_EMIB3_OFST)
/*******************************************************************************
* APB0 Peripherals' Base addresses *
*******************************************************************************/
#define WIU_BASE (AHBAPB0_BASE + APB_WIU_OFST)
#define TIM0_BASE (AHBAPB0_BASE + APB_TIM0_OFST)
#define TIM1_BASE (AHBAPB0_BASE + APB_TIM1_OFST)
#define TIM2_BASE (AHBAPB0_BASE + APB_TIM2_OFST)
#define TIM3_BASE (AHBAPB0_BASE + APB_TIM3_OFST)
#define GPIO0_BASE (AHBAPB0_BASE + APB_GPIO0_OFST)
#define GPIO1_BASE (AHBAPB0_BASE + APB_GPIO1_OFST)
#define GPIO2_BASE (AHBAPB0_BASE + APB_GPIO2_OFST)
#define GPIO3_BASE (AHBAPB0_BASE + APB_GPIO3_OFST)
#define GPIO4_BASE (AHBAPB0_BASE + APB_GPIO4_OFST)
#define GPIO5_BASE (AHBAPB0_BASE + APB_GPIO5_OFST)
#define GPIO6_BASE (AHBAPB0_BASE + APB_GPIO6_OFST)
#define GPIO7_BASE (AHBAPB0_BASE + APB_GPIO7_OFST)
#define GPIO8_BASE (AHBAPB0_BASE + APB_GPIO8_OFST)
#define GPIO9_BASE (AHBAPB0_BASE + APB_GPIO9_OFST)
/*******************************************************************************
* APB1 Peripherals' Base addresses *
*******************************************************************************/
#define RTC_BASE (AHBAPB1_BASE + APB_RTC_OFST)
#define SCU_BASE (AHBAPB1_BASE + APB_SCU_OFST)
#define MC_BASE (AHBAPB1_BASE + APB_MC_OFST)
#define UART0_BASE (AHBAPB1_BASE + APB_UART0_OFST)
#define UART1_BASE (AHBAPB1_BASE + APB_UART1_OFST)
#define UART2_BASE (AHBAPB1_BASE + APB_UART2_OFST)
#define SSP0_BASE (AHBAPB1_BASE + APB_SSP0_OFST)
#define SSP1_BASE (AHBAPB1_BASE + APB_SSP1_OFST)
#define CAN_BASE (AHBAPB1_BASE + APB_CAN_OFST)
#define ADC_BASE (AHBAPB1_BASE + APB_ADC_OFST)
#define WDG_BASE (AHBAPB1_BASE + APB_WDG_OFST)
#define I2C0_BASE (AHBAPB1_BASE + APB_I2C0_OFST)
#define I2C1_BASE (AHBAPB1_BASE + APB_I2C1_OFST)
/*******************************************************************************
* IPs' declaration *
*******************************************************************************/
/*------------------------------ Non Debug Mode ------------------------------*/
#undef DEBUG
#ifndef DEBUG
/*********************************** AHBAPB ***********************************/
#define AHBAPB0 ((AHBAPB_TypeDef *)AHBAPB0_BASE)
#define AHBAPB1 ((AHBAPB_TypeDef *)AHBAPB1_BASE)
/************************************* EMI ************************************/
#define EMI ((EMI_TypeDef *)EMI_BASE)
/************************************* DMA ************************************/
#define DMA ((DMA_TypeDef *)DMA_BASE)
#define DMA_Channel0 ((DMA_Channel_TypeDef *)DMA_Channel0_BASE)
#define DMA_Channel1 ((DMA_Channel_TypeDef *)DMA_Channel1_BASE)
#define DMA_Channel2 ((DMA_Channel_TypeDef *)DMA_Channel2_BASE)
#define DMA_Channel3 ((DMA_Channel_TypeDef *)DMA_Channel3_BASE)
#define DMA_Channel4 ((DMA_Channel_TypeDef *)DMA_Channel4_BASE)
#define DMA_Channel5 ((DMA_Channel_TypeDef *)DMA_Channel5_BASE)
#define DMA_Channel6 ((DMA_Channel_TypeDef *)DMA_Channel6_BASE)
#define DMA_Channel7 ((DMA_Channel_TypeDef *)DMA_Channel7_BASE)
/************************************* EMI ************************************/
#define EMI_Bank0 ((EMI_Bank_TypeDef *)EMI_Bank0_BASE)
#define EMI_Bank1 ((EMI_Bank_TypeDef *)EMI_Bank1_BASE)
#define EMI_Bank2 ((EMI_Bank_TypeDef *)EMI_Bank2_BASE)
#define EMI_Bank3 ((EMI_Bank_TypeDef *)EMI_Bank3_BASE)
/************************************* ENET_MAC ************************************/
#define ENET_MAC ((ENET_MAC_TypeDef *)ENET_MAC_BASE)
/************************************* ENET_DMA ************************************/
#define ENET_DMA ((ENET_DMA_TypeDef *)ENET_DMA_BASE)
/************************************* FMI ************************************/
#define FMI ((FMI_TypeDef *)FMI_BASE)
/************************************* VIC ************************************/
#define VIC0 ((VIC_TypeDef *)VIC0_BASE)
#define VIC1 ((VIC_TypeDef *)VIC1_BASE)
/*******************************************************************************
* APB0 Peripherals' *
*******************************************************************************/
#define WIU ((WIU_TypeDef *)WIU_BASE)
#define TIM0 ((TIM_TypeDef *)TIM0_BASE)
#define TIM1 ((TIM_TypeDef *)TIM1_BASE)
#define TIM2 ((TIM_TypeDef *)TIM2_BASE)
#define TIM3 ((TIM_TypeDef *)TIM3_BASE)
#define GPIO0 ((GPIO_TypeDef *)GPIO0_BASE)
#define GPIO1 ((GPIO_TypeDef *)GPIO1_BASE)
#define GPIO2 ((GPIO_TypeDef *)GPIO2_BASE)
#define GPIO3 ((GPIO_TypeDef *)GPIO3_BASE)
#define GPIO4 ((GPIO_TypeDef *)GPIO4_BASE)
#define GPIO5 ((GPIO_TypeDef *)GPIO5_BASE)
#define GPIO6 ((GPIO_TypeDef *)GPIO6_BASE)
#define GPIO7 ((GPIO_TypeDef *)GPIO7_BASE)
#define GPIO8 ((GPIO_TypeDef *)GPIO8_BASE)
#define GPIO9 ((GPIO_TypeDef *)GPIO9_BASE)
/*******************************************************************************
* APB1 Peripherals' *
*******************************************************************************/
#define RTC ((RTC_TypeDef *)RTC_BASE)
#define SCU ((SCU_TypeDef *)SCU_BASE)
#define MC ((MC_TypeDef *)MC_BASE)
#define UART0 ((UART_TypeDef *)UART0_BASE)
#define UART1 ((UART_TypeDef *)UART1_BASE)
#define UART2 ((UART_TypeDef *)UART2_BASE)
#define SSP0 ((SSP_TypeDef *)SSP0_BASE)
#define SSP1 ((SSP_TypeDef *)SSP1_BASE)
#define CAN ((CAN_TypeDef *)CAN_BASE)
#define ADC ((ADC_TypeDef *)ADC_BASE)
#define WDG ((WDG_TypeDef *)WDG_BASE)
#define I2C0 ((I2C_TypeDef *)I2C0_BASE)
#define I2C1 ((I2C_TypeDef *)I2C1_BASE)
#define ENET_MAC ((ENET_MAC_TypeDef *)ENET_MAC_BASE)
#define ENET_DMA ((ENET_DMA_TypeDef *)ENET_DMA_BASE)
#else /* DEBUG */
/*-------------------------------- Debug Mode --------------------------------*/
EXT AHBAPB_TypeDef *AHBAPB0;
EXT AHBAPB_TypeDef *AHBAPB1;
EXT DMA_TypeDef *DMA;
EXT DMA_Channel_TypeDef *DMA_Channel0;
EXT DMA_Channel_TypeDef *DMA_Channel1;
EXT DMA_Channel_TypeDef *DMA_Channel2;
EXT DMA_Channel_TypeDef *DMA_Channel3;
EXT DMA_Channel_TypeDef *DMA_Channel4;
EXT DMA_Channel_TypeDef *DMA_Channel5;
EXT DMA_Channel_TypeDef *DMA_Channel6;
EXT DMA_Channel_TypeDef *DMA_Channel7;
EXT EMI_Bank_TypeDef *EMI_Bank0;
EXT EMI_Bank_TypeDef *EMI_Bank1;
EXT EMI_Bank_TypeDef *EMI_Bank2;
EXT EMI_Bank_TypeDef *EMI_Bank3;
EXT FMI_TypeDef *FMI;
EXT VIC_TypeDef *VIC0;
EXT VIC_TypeDef *VIC1;
EXT WIU_TypeDef *WIU;
EXT TIM_TypeDef *TIM0;
EXT TIM_TypeDef *TIM1;
EXT TIM_TypeDef *TIM2;
EXT TIM_TypeDef *TIM3;
EXT GPIO_TypeDef *GPIO0;
EXT GPIO_TypeDef *GPIO1;
EXT GPIO_TypeDef *GPIO2;
EXT GPIO_TypeDef *GPIO3;
EXT GPIO_TypeDef *GPIO4;
EXT GPIO_TypeDef *GPIO5;
EXT GPIO_TypeDef *GPIO6;
EXT GPIO_TypeDef *GPIO7;
EXT GPIO_TypeDef *GPIO8;
EXT GPIO_TypeDef *GPIO9;
EXT RTC_TypeDef *RTC;
EXT SCU_TypeDef *SCU;
EXT MC_TypeDef *MC;
EXT UART_TypeDef *UART0;
EXT UART_TypeDef *UART1;
EXT UART_TypeDef *UART2;
EXT SSP_TypeDef *SSP0;
EXT SSP_TypeDef *SSP1;
EXT CAN_TypeDef *CAN;
EXT ADC_TypeDef *ADC;
EXT WDG_TypeDef *WDG;
EXT I2C_TypeDef *I2C0;
EXT I2C_TypeDef *I2C1;
EXT ENET_MAC_TypeDef *ENET_MAC;
EXT ENET_DMA_TypeDef *ENET_DMA;
#endif /* DEBUG */
#endif /* __91x_MAP_H*/
/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/

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/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
* File Name : 91x_scu.c
* Author : MCD Application Team
* Date First Issued : 05/18/2006 : Version 1.0
* Description : This file provides the SCU library software functions
********************************************************************************
* History:
* 05/24/2006 : Version 1.1
* 05/18/2006 : Version 1.0
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Includes ------------------------------------------------------------------*/
#include "91x_scu.h"
/* Include of other module interface headers ---------------------------------*/
/* Local includes ------------------------------------------------------------*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define SCU_PLLEN 0x80000
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Interface functions -------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/*******************************************************************************
* Function Name : SCU_MCLKSourceConfig
* Description : Configures the MCLK source clock
* Input : MCLK_Source = SCU_MCLK_OSC, SCU_MCLK_PLL or SCU_MCLK_RTC
* Output : None
* Return : ErrorStatus: SUCCESS or ERROR
* Note : this function returns ERROR if trying to select the PLL as
* clock source while the PLL is disabled or not locked.
*******************************************************************************/
ErrorStatus SCU_MCLKSourceConfig(u32 MCLK_Source)
{
u32 CLKCNTR_Value;
CLKCNTR_Value = SCU->CLKCNTR; /*get CLKCNTR register value*/
CLKCNTR_Value &=~0x3; /*clear field MCLKSEL*/
if (MCLK_Source == SCU_MCLK_PLL) /*PLL selected as clock source*/
{
/*check if PLL enabled & locked*/
if (!((SCU->PLLCONF&SCU_PLLEN)&&(SCU->SYSSTATUS&SCU_FLAG_LOCK)))
return ERROR;
}
else CLKCNTR_Value |=MCLK_Source; /*OSC or RTC selected as clock source*/
SCU->CLKCNTR = CLKCNTR_Value; /*Update CLKCNTR register value*/
return SUCCESS;
}
/*******************************************************************************
* Function Name : SCU_PLLFactorsConfig
* Description : Sets the PLL factors
* Input : PLLN, PLLM and PLLP
* Output : None
* Return : ErrorStatus: ERROR or SUCCESS
* Notes : -The PLL factors must respect the PLL specification requirements
* -The function returns ERROR if trying to change PLL
* factors while PLL is selected as Main Clock source (MCLK)
* -This function disables the PLL, to enable the PLL use
* function" SCU_PLLCmd(ENABLE)" after setting the PLL factors
******************************************************************************/
ErrorStatus SCU_PLLFactorsConfig(u8 PLLN, u8 PLLM, u8 PLLP)
{
if (SCU_PLLCmd(DISABLE)==SUCCESS) /*Disable PLL*/
{
SCU->PLLCONF =0; /*clear PLLCONF register*/
SCU->PLLCONF |=(PLLN<<8); /*update PLLN field*/
SCU->PLLCONF |=PLLM; /*update PLLM field*/
SCU->PLLCONF |=PLLP<<16; /*update PLLP field*/
return SUCCESS;
}
return ERROR;
}
/*******************************************************************************
* Function Name : SCU_PLLCmd
* Description : Enable or Disable the PLL
* Input : NewState = ENABLE or DISABLE
* Output : None
* Return : ErrorStatus: SUCCESS or ERROR
* Note : -The function returns ERROR if:
* *trying to disable the PLL while it is selected as the MCLK
* *trying to enable the PLL while it is already enabled and
* locked
*******************************************************************************/
ErrorStatus SCU_PLLCmd(FunctionalState NewState)
{
vu32 i;
if (NewState==ENABLE)
{
if (!((SCU->PLLCONF&SCU_PLLEN)&&(SCU->SYSSTATUS&SCU_FLAG_LOCK)))
{
SCU->SYSSTATUS|=SCU_FLAG_LOCK; /*clear LOCK bit*/
SCU->PLLCONF |=SCU_PLLEN; /*PLL Enable*/
while(!SCU->SYSSTATUS&SCU_FLAG_LOCK); /*Wait PLL to lock*/
return SUCCESS;
}
else return ERROR;
}
else /*NewState = DISABLE*/
{
if(SCU->CLKCNTR&0x3) /*check if PLL not sys CLK*/
{
for(i=10;i>0;i--); /*delay before PLL disabling*/
SCU->PLLCONF &=~SCU_PLLEN; /*PLL Disable*/
return SUCCESS;
}
else return ERROR;
}
}
/*******************************************************************************
* Function Name : SCU_RCLKDivisorConfig
* Description : Sets the RCLK divisor value
* Input : RCLK_Divisor
* Output : None
* Return : None
*******************************************************************************/
void SCU_RCLKDivisorConfig(u32 RCLK_Divisor)
{
SCU->CLKCNTR &=SCU_RCLK_Div1; /*clear RCLKDIV[2:0] field*/
if (RCLK_Divisor!=SCU_RCLK_Div1)
SCU->CLKCNTR |= RCLK_Divisor; /*update field with RCLK divisor*/
}
/*******************************************************************************
* Function Name : SCU_HCLKDivisorConfig
* Description : Sets the HCLK divisor value
* Input : HCLK_Divisor
* Output : None
* Return : None
*******************************************************************************/
void SCU_HCLKDivisorConfig(u32 HCLK_Divisor)
{
SCU->CLKCNTR &=SCU_HCLK_Div1; /*clear AHBDIV[1:0] field*/
if (HCLK_Divisor!=SCU_HCLK_Div1)
SCU->CLKCNTR |= HCLK_Divisor; /*update field with HCLK divisor*/
}
/*******************************************************************************
* Function Name : SCU_PCLKDivisorConfig
* Description : Sets the PCLK divisor value
* Input : PCLK_Divisor
* Output : None
* Return : None
*******************************************************************************/
void SCU_PCLKDivisorConfig(u32 PCLK_Divisor)
{
SCU->CLKCNTR &=SCU_PCLK_Div1; /*clear APBDIV[1:0] field*/
if (PCLK_Divisor!=SCU_PCLK_Div1)
SCU->CLKCNTR |= PCLK_Divisor; /*update field with PCLK Divisor*/
}
/*******************************************************************************
* Function Name : SCU_APBPeriphClockConfig
* Description : Enable the clock for an APB peripheral
* Input : -APBPerip : APB peripherals(__RTC, __ADC ,...)
* -NewState : ENABLE or DISABLE
* Output : None
* Return : None
*******************************************************************************/
void SCU_APBPeriphClockConfig(u32 APBPeriph, FunctionalState NewState)
{
if (NewState==ENABLE) /*Enable clock for APB peripheral*/
SCU->PCGR1 |=APBPeriph;
else
SCU->PCGR1 &=~APBPeriph; /*Disable clock for APB peripheral*/
}
/*******************************************************************************
* Function Name : SCU_AHBPeriphClockConfig
* Description : Enable the clock for an AHB peripheral
* Input : -AHBPerip: AHB peripherals(__USB, __DMA,...)
* -NewState : ENABLE or DISABLE
* Output : None
* Return : None
*******************************************************************************/
void SCU_AHBPeriphClockConfig(u32 AHBPeriph, FunctionalState NewState)
{
if (NewState==ENABLE) /*Enable clock for AHB peripheral*/
SCU->PCGRO |=AHBPeriph;
else
SCU->PCGRO &=~AHBPeriph; /*Disable clock for AHB peripheral*/
}
/*******************************************************************************
* Function Name : SCU_APBPeriphReset
* Description : Assert or deassert Reset on APB peripheral
* Input : -APBPeriph: APB peripherals(__RTC, __ADC,...)
-NewState : ENABLE or DISABLE
* Output : None
* Return : None
*******************************************************************************/
void SCU_APBPeriphReset(u32 APBPeriph, FunctionalState NewState)
{
if (NewState==DISABLE) /*APB peripheral not held in Reset*/
SCU->PRR1 |=APBPeriph;
else
SCU->PRR1 &=~APBPeriph; /*APB peripheral held in Reset*/
}
/*******************************************************************************
* Function Name : SCU_AHBPeriphReset
* Description : Assert or deassert Reset on AHB peripheral
* Input : -AHBPeriph: AHB peripherals(__USB, __DMA,...)
-NewState : ENABLE or DISABLE
* Output : None
* Return : None
*******************************************************************************/
void SCU_AHBPeriphReset(u32 AHBPeriph, FunctionalState NewState)
{
if (NewState==DISABLE)
SCU->PRR0 |=AHBPeriph; /*AHB peripheral not held in Reset*/
else
SCU->PRR0 &=~AHBPeriph; /*AHB peripheral held in Reset*/
}
/*******************************************************************************
* Function Name : SCU_APBPeriphIdleConfig
* Description : Enable or Disable Periph Clock during Idle mode
* Input : -APBPeriph: APB peripherals(__RTC, __ADC,...)
-NewState : ENABLE or DISABLE
* Output : None
* Return : None
*******************************************************************************/
void SCU_APBPeriphIdleConfig(u32 APBPeriph, FunctionalState NewState)
{
if (NewState==ENABLE)
SCU->MGR1 |=APBPeriph; /*APB peripheral clock enabled during Idle mode*/
else
SCU->MGR1 &=~APBPeriph; /*APB peripheral clock disabled during Idle mode*/
}
/*******************************************************************************
* Function Name : SCU_AHBPeriphIdleConfig
* Description : Enable or Disable Periph Clock during Idle mode
* Input : -AHBPeriph: AHB peripherals(__USB, __DMA,...)
-NewState : ENABLE or DISABLE
* Output : None
* Return : None
*******************************************************************************/
void SCU_AHBPeriphIdleConfig(u32 AHBPeriph, FunctionalState NewState)
{
if (NewState==ENABLE)
SCU->MGR0 |=AHBPeriph; /*AHB peripheral clock enabled during Idle mode*/
else
SCU->MGR0 &=~AHBPeriph; /*AHB peripheral clock disabled during Idle mode*/
}
/*******************************************************************************
* Function Name : SCU_APBPeriphDebugConfig
* Description : Enable or Disable Periph Clock during ARM debug state
* Input : -APBPeriph: APB peripherals(__RTC, __ADC,...)
-NewState : ENABLE or DISABLE
* Output : None
* Return : None
*******************************************************************************/
void SCU_APBPeriphDebugConfig(u32 APBPeriph, FunctionalState NewState)
{
if (NewState==ENABLE)
SCU->PECGR1 |=APBPeriph; /*APB peripheral clock enabled during ARM debug state*/
else
SCU->PECGR1 &=~APBPeriph; /*APB peripheral clock disabled during ARM debug state*/
}
/*******************************************************************************
* Function Name : SCU_AHBPeriphDebugConfig
* Description : Enable or Disable Periph Clock during ARM debug state
* Input : -AHBPeriph: AHB peripherals(__USB, __DMA,...)
-NewState : ENABLE or DISABLE
* Output : None
* Return : None
*******************************************************************************/
void SCU_AHBPeriphDebugConfig(u32 AHBPeriph, FunctionalState NewState)
{
if (NewState==ENABLE)
SCU->PECGR0 |=AHBPeriph; /*AHB peripheral clock enabled during ARM debug state*/
else
SCU->PECGR0 &=~AHBPeriph; /*AHB peripheral clock disabled during ARM debug state*/
}
/*******************************************************************************
* Function Name : SCU_BRCLKDivisorConfig
* Description : Sets the BRCLK divisor value
* Input : BRCLK_Divisor
* Output : None
* Return : None
*******************************************************************************/
void SCU_BRCLKDivisorConfig(u32 BRCLK_Divisor)
{
SCU->CLKCNTR &=SCU_BRCLK_Div1; /*Clear BRSEL bit*/
if (BRCLK_Divisor!=SCU_BRCLK_Div1)
SCU->CLKCNTR |= SCU_BRCLK_Div2; /*set bit BRSEL*/
}
/*******************************************************************************
* Function Name : SCU_TIMCLKSourceConfig
* Description : Sets the TIMx clock source
* Input : - TIMx : SCU_TIM01 or SCU_TIM23
* - TIMCLK_Source = SCU_TIMCLK_EXT or SCU_TIMCLK_INT
* Output : None
* Return : None
*******************************************************************************/
void SCU_TIMCLKSourceConfig(u8 TIMx, u32 TIMCLK_Source)
{
if (TIMx== SCU_TIM01) /*TIM01 clock source configuration*/
{
SCU->CLKCNTR &=0xFFFFDFFF;
if (TIMCLK_Source == SCU_TIMCLK_EXT)
SCU->CLKCNTR |=0x2000;
}
else
{
SCU->CLKCNTR &=0xFFFFBFFF; /*TIM23 clock source configuration*/
if (TIMCLK_Source == SCU_TIMCLK_EXT)
SCU->CLKCNTR |=0x4000;
}
}
/*******************************************************************************
* Function Name : SCU_TIMPresConfig
* Description : Sets the TIMx Prescaler Value
* Input : - TIMx : SCU_TIM01 or SCU_TIM23
* - Prescaler (16 bit value)
* Output : None
* Return : None
*******************************************************************************/
void SCU_TIMPresConfig(u8 TIMx, u16 Prescaler)
{
if (TIMx==SCU_TIM01) /*TIM01 Prescaler configuration*/
SCU->SCR1 = Prescaler&0xFFFF;
else
SCU->SCR2 = Prescaler&0xFFFF; /*TIM23 Prescaler configuration*/
}
/*******************************************************************************
* Function Name : SCU_USBCLKConfig
* Description : Configures the clock source for the 48MHz USBCLK
* Input : USBCLK_Source: SCU_USBCLK_MCLK,SCU_USBCLK_MCLK2 or SCU_USBCLK_EXT
* Output : None
* Return : None
*******************************************************************************/
void SCU_USBCLKConfig(u32 USBCLK_Source)
{
SCU->CLKCNTR &=SCU_USBCLK_MCLK; /*clear USBSEL[1:0] field*/
if (USBCLK_Source!=SCU_USBCLK_MCLK)
SCU->CLKCNTR |= USBCLK_Source; /*update field with USBCLK_Source*/
}
/*******************************************************************************
* Function Name : SCU_PHYCLKConfig
* Description : Enable or Disable PHY clock output
* Input : NewState : ENABLE or DISABLE
* Output : None
* Return : None
*******************************************************************************/
void SCU_PHYCLKConfig(FunctionalState NewState)
{
if (NewState==ENABLE)
SCU->CLKCNTR |= 0x1000; /*enable MIIPHY clock*/
else
SCU->CLKCNTR &=~0x1000; /*disable MIIPHY clock*/
}
/*******************************************************************************
* Function Name : SCU_FMICLKDivisorConfig
* Description : Set the FMI clock divisor
* Input : FMICLK_Divisor: SCU_FMICLK_Div1 or SCU_FMICLK_DIV2
* Output : None
* Return : None
*******************************************************************************/
void SCU_FMICLKDivisorConfig(u32 FMICLK_Divisor)
{
SCU->CLKCNTR &=SCU_FMICLK_Div1; /*FMICLK = RCLK*/
if (FMICLK_Divisor!=SCU_FMICLK_Div1)
SCU->CLKCNTR |=SCU_FMICLK_Div2; /*FMICLK = RCLK/2 */
}
/*******************************************************************************
* Function Name : SCU_EMIBCLKDivisorConfig
* Description : Set the EMI Bus clock divisor: EMIBCLK = HCLK or HCLK/2
* Input : SCU_EMICLK: SCU_EMIBCLK_Div1 , SCU_EMIBCLK_Div2
* Output : None
* Return : None
*******************************************************************************/
void SCU_EMIBCLKDivisorConfig(u32 SCU_EMIBCLK)
{
SCU->CLKCNTR &=SCU_EMIBCLK_Div1; /*EMIBCLK = HCLK */
if (SCU_EMIBCLK!=SCU_EMIBCLK_Div1)
SCU->CLKCNTR |= SCU_EMIBCLK_Div2; /*EMIBCLK = HCLK/2 */
}
/*******************************************************************************
* Function Name : SCU_EMIModeConfig
* Description : Configure the EMI as Multiplexed or Demultiplexed
* Input : SCU_EMIMODE : SCU_EMI_MUX or SCU_EMI_DEMUX
* Output : None
* Return : None
*******************************************************************************/
void SCU_EMIModeConfig(u32 SCU_EMIMODE)
{
SCU->SCR0 &=SCU_EMI_MUX; /*EMI mode = Multiplexed*/
if (SCU_EMIMODE!=SCU_EMI_MUX)
SCU->SCR0 |= SCU_EMI_DEMUX; /*EMI mode = Demultiplexed*/
}
/*******************************************************************************
* Function Name : SCU_EMIALEConfig
* Description : Configure the ALE signal (length & polarity)
* Input : -SCU_EMIALE_LEN : SCU_EMIALE_LEN1 or SCU_EMIALE_LEN2
* -SCU_EMIALE_POL : SCU_EMIALE_POLLow or SCU_EMI_POLHigh
* Output : None
* Return : None
*******************************************************************************/
void SCU_EMIALEConfig(u32 SCU_EMIALE_LEN, u32 SCU_EMIALE_POL)
{
/*Configure EMI ALE Length*/
SCU->SCR0 &=SCU_EMIALE_LEN1;
if (SCU_EMIALE_LEN!=SCU_EMIALE_LEN1)
SCU->SCR0 |= SCU_EMIALE_LEN2;
/*Configure EMI ALE POL*/
SCU->SCR0 &=SCU_EMIALE_POLLow;
if (SCU_EMIALE_POL!=SCU_EMIALE_POLLow)
SCU->SCR0 |= SCU_EMIALE_POLHigh;
}
/*******************************************************************************
* Function Name : SCU_ITConfig
* Description : ENBALE or DISABLE an SCU interrupt
* Input : -SCU_IT: interrupt mask
* -NewState: ENABLE or DISABLE
* Output : None
* Return : None
*******************************************************************************/
void SCU_ITConfig(u32 SCU_IT, FunctionalState NewState)
{
if (NewState==ENABLE)
SCU->ITCMSK&=~SCU_IT; /*IT enable */
else
SCU->ITCMSK|=SCU_IT; /*IT disable( mask)*/
}
/*******************************************************************************
* Function Name : SCU_GetFlagStatus
* Description : Returns flag status
* Input : SCU_Flag
* Output : NONE
* Return : SET or RESET
*******************************************************************************/
FlagStatus SCU_GetFlagStatus(u32 SCU_Flag)
{
if (SCU->SYSSTATUS&SCU_Flag)
return SET;
else return RESET;
}
/*******************************************************************************
* Function Name : SCU_ClearFlag
* Description : Clears a SYSTATUS Flag
* Input : SCU_Flag
* Output : None
* Return : None
*******************************************************************************/
void SCU_ClearFlag(u32 SCU_Flag)
{
SCU->SYSSTATUS = SCU_Flag;
}
/*******************************************************************************
* Function Name : SCU_GetPLLfreqValue
* Description : Gets the current PLL frequency
* Input : None
* Output : None
* Return : PLL frequency (KHz)
*******************************************************************************/
u32 SCU_GetPLLFreqValue(void)
{
u8 PLL_M;
u8 PLL_N;
u8 PLL_P;
PLL_M = SCU->PLLCONF&0xFF;
PLL_N = (SCU->PLLCONF&0xFF00)>>8;
PLL_P = (SCU->PLLCONF&0x70000)>>16;
if ((PLL_M>0)&&(PLL_N>0))
return (u32)(((_Main_Crystal*2)*PLL_N)/(PLL_M<<PLL_P));
else return 0;
}
/*******************************************************************************
* Function Name : SCU_GetMCLKFreqValue
* Description : Gets the current MCLK frequency
* Input : None
* Output : None
* Return : MCLK frequency (KHz)
*******************************************************************************/
u32 SCU_GetMCLKFreqValue(void)
{
if ((SCU->CLKCNTR&0x3) == 0x2) return (u32)(_Main_Crystal);
if ((SCU->CLKCNTR&0x3) == 0x1) return (u32)(32);
else return (SCU_GetPLLFreqValue());
}
/*******************************************************************************
* Function Name : SCU_GetRCLKFreqValue
* Description : Gets the current RCLK frequency
* Input : None
* Output : None
* Return : RCLK frequency (KHz)
*******************************************************************************/
u32 SCU_GetRCLKFreqValue(void)
{
u8 RCLK_Div;
RCLK_Div = (SCU->CLKCNTR&0x1C)>>2;
if (RCLK_Div==0x5) RCLK_Div=10;
return (u32)(SCU_GetMCLKFreqValue() >>RCLK_Div);
}
/*******************************************************************************
* Function Name : SCU_GetHCLKFreqValue
* Description : Gets the current PCLK frequency
* Input : None
* Output : None
* Return : HCLK frequency (KHz)
*******************************************************************************/
u32 SCU_GetHCLKFreqValue(void)
{
u8 HCLK_Div;
HCLK_Div = (SCU->CLKCNTR&0x60)>>5;
return (u32)(SCU_GetRCLKFreqValue() >>HCLK_Div);
}
/*******************************************************************************
* Function Name : SCU_GetPCLKFreqValue
* Description : Gets the current HCLK frequency
* Input : None
* Output : None
* Return : PCLK frequency (KHz)
*******************************************************************************/
u32 SCU_GetPCLKFreqValue(void)
{
u8 PCLK_Div;
PCLK_Div = (SCU->CLKCNTR&0x180)>>7;
return (u32)(SCU_GetRCLKFreqValue() >>PCLK_Div);
}
/*******************************************************************************
* Function Name : SCU_WakeUpLineConfig
* Description : Configures an External interrupt as WakeUp line
* Input : EXTint : 0 -> 31
* Output : None
* Return : None
*******************************************************************************/
void SCU_WakeUpLineConfig(u8 EXTint)
{
if (EXTint < 8)
{
SCU->WKUPSEL&=~0x7;
SCU->WKUPSEL|=EXTint;
}
else if (EXTint<16)
{
SCU->WKUPSEL&=~0x38;
SCU->WKUPSEL|=(EXTint-8)<<3;
}
else if (EXTint<24)
{
SCU->WKUPSEL&=~0x1C0;
SCU->WKUPSEL|=(EXTint-16)<<6;
}
else
{
SCU->WKUPSEL&=~0xE00;
SCU->WKUPSEL|=(EXTint-24)<<9;
}
}
/*******************************************************************************
* Function Name : SCU_SpecIntRunModeConfig
* Description : Enables or Disables the Special Run mode
* Input : newstate = ENABLE or DISABLE
* Output : None
* Return : None
*******************************************************************************/
void SCU_SpecIntRunModeConfig(FunctionalState NewState)
{
if (NewState == ENABLE)
SCU->PWRMNG |=0x8;
else
SCU->PWRMNG &=~0x8;
}
/*******************************************************************************
* Function Name : SCU_EnterIdleMode
* Description : Enters in Idle mode
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void SCU_EnterIdleMode(void)
{
SCU->PWRMNG |=0x1;
}
/*******************************************************************************
* Function Name : SCU_EnterSleepMode
* Description : Enters in Sleep mode
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void SCU_EnterSleepMode(void)
{
SCU->PWRMNG |=0x2;
}
/*******************************************************************************
* Function Name : SCU_UARTIrDAConfig
* Description : Enable or Disable the Irda mode for UARTx
* Input : - UARTx :x=0,1 or 2
* - UART_IrDA_Mode : SCU_UARTMode_IrDA or SCU_UARTMode_UART
* Output : None
* Return : None
*******************************************************************************/
void SCU_UARTIrDASelect(UART_TypeDef * UARTx, u8 UART_IrDA_Mode)
{
if (UART_IrDA_Mode == SCU_UARTMode_IrDA)
{
if (UARTx== UART0) SCU->SCR0 |=0x400;
else if (UARTx==UART1) SCU->SCR0 |=0x800;
else SCU->SCR0 |=0x1000;
}
else
{
if (UARTx== UART0) SCU->SCR0 &=~0x400;
else if (UARTx==UART1) SCU->SCR0 &=~0x800;
else SCU->SCR0 &=~0x1000;
}
}
/*******************************************************************************
* Function Name : SCU_PFQBCCmd
* Description : Enable or Disable PFQBC
* Input : NewState : ENABLE or DISABLE
* Output : None
* Return : None
*******************************************************************************/
void SCU_PFQBCCmd(FunctionalState NewState)
{
if (NewState==ENABLE)
SCU->SCR0 |=0x1;
else SCU->SCR0 &=~0x1;
}
/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/

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/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
* File Name : 91x_scu.h
* Author : MCD Application Team
* Date First Issued : 05/18/2006 : Version 1.0
* Description : This file provides the SCU library software functions
* prototypes & definitions
********************************************************************************
* History:
* 05/24/2006 : Version 1.1
* 05/18/2006 : Version 1.0
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __91x_SCU_H
#define __91x_SCU_H
/* Includes ------------------------------------------------------------------*/
#include "91x_map.h"
/* Exported constants --------------------------------------------------------*/
/*MCLK_Source*/
#define SCU_MCLK_PLL 0x0
#define SCU_MCLK_RTC 0x1
#define SCU_MCLK_OSC 0x2
/*RCLK_Divisor*/
#define SCU_RCLK_Div1 0xFFFFFFE3
#define SCU_RCLK_Div2 0x4
#define SCU_RCLK_Div4 0x8
#define SCU_RCLK_Div8 0xC
#define SCU_RCLK_Div16 0x10
#define SCU_RCLK_Div1024 0x14
/*HCLK_Divisor*/
#define SCU_HCLK_Div1 0xFFFFFF9F
#define SCU_HCLK_Div2 0x20
#define SCU_HCLK_Div4 0x40
/*PCLK_Divisor*/
#define SCU_PCLK_Div1 0xFFFFFE7F
#define SCU_PCLK_Div2 0x80
#define SCU_PCLK_Div4 0x100
#define SCU_PCLK_Div8 0x180
/*FMICLK_Divisor*/
#define SCU_FMICLK_Div1 0xFFFEFFFF
#define SCU_FMICLK_Div2 0x10000
/*BRCLK_Divisor*/
#define SCU_BRCLK_Div1 0xFFFFFDFF
#define SCU_BRCLK_Div2 0x200
/*TIMCLK_Source*/
#define SCU_TIMCLK_EXT 0x1
#define SCU_TIMCLK_INT 0x0
/*TIMx*/
#define SCU_TIM01 0x0
#define SCU_TIM23 0x1
/*USBCLK_Source*/
#define SCU_USBCLK_MCLK 0xFFFFF3FF
#define SCU_USBCLK_MCLK2 0x400
#define SCU_USBCLK_EXT 0x800
/*SCU_EMIBCLK*/
#define SCU_EMIBCLK_Div1 0xFFF9FFFF
#define SCU_EMIBCLK_Div2 0x20000
/*SCU_EMIMODE*/
#define SCU_EMI_MUX 0xFFFFFFBF
#define SCU_EMI_DEMUX 0x40
/*SCU_EMIALE_LEN*/
#define SCU_EMIALE_LEN1 0xFFFFFEFF
#define SCU_EMIALE_LEN2 0x100
/*SCU_EMIALE_POL*/
#define SCU_EMIALE_POLLow 0xFFFFFF7F
#define SCU_EMIALE_POLHigh 0x80
/*UART_IrDA_Mode*/
#define SCU_UARTMode_IrDA 0x1
#define SCU_UARTMode_UART 0x0
/*APBPeriph*/
#define __TIM01 0x1
#define __TIM23 0x2
#define __MC 0x4
#define __UART0 0x8
#define __UART1 0x10
#define __UART2 0x20
#define __UART_ALL (__UART0|__UART1|__UART2)
#define __I2C0 0x40
#define __I2C1 0x80
#define __SSP0 0x100
#define __SSP1 0x200
#define __CAN 0x400
#define __ADC 0x800
#define __WDG 0x1000
#define __WIU 0x2000
#define __GPIO0 0x4000
#define __GPIO1 0x8000
#define __GPIO2 0x10000
#define __GPIO3 0x20000
#define __GPIO4 0x40000
#define __GPIO5 0x80000
#define __GPIO6 0x100000
#define __GPIO7 0x200000
#define __GPIO8 0x400000
#define __GPIO9 0x800000
#define __GPIO_ALL (__GPIO0|__GPIO1|__GPIO2|__GPIO3|__GPIO4|__GPIO5|__GPIO6|__GPIO7|__GPIO8|__GPIO9)
#define __RTC 0x1000000
/*AHBPeriph*/
#define __FMI 0x1
#define __FPQBC 0x2
#define __SRAM 0x8
#define __SRAM_ARBITER 0x10
#define __VIC 0x20
#define __EMI 0x40
#define __EMI_MEM_CLK 0x80
#define __DMA 0x100
#define __USB 0x200
#define __USB48M 0x400
#define __ENET 0x800
#define __PFQBC_AHB 0x1000
/*SCU_IT*/
#define SCU_IT_LVD_RST 0x10
#define SCU_IT_SRAM_ERROR 0x8
#define SCU_IT_ACK_PFQBC 0x4
#define SCU_IT_LOCK_LOST 0x2
#define SCU_IT_LOCK 0x1
/*SCU_FLAG*/
#define SCU_FLAG_SRAM_ERROR 0x20
#define SCU_FLAG_ACK_PFQBC 0x10
#define SCU_FLAG_LVD_RESET 0x8
#define SCU_FLAG_WDG_RST 0x4
#define SCU_FLAG_LOCK_LOST 0x2
#define SCU_FLAG_LOCK 0x1
/* Module private variables --------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
ErrorStatus SCU_MCLKSourceConfig(u32 MCLK_Source);
ErrorStatus SCU_PLLFactorsConfig(u8 PLLN, u8 PLLM, u8 PLLP);
ErrorStatus SCU_PLLCmd(FunctionalState NewState);
void SCU_RCLKDivisorConfig(u32 RCLK_Divisor);
void SCU_HCLKDivisorConfig(u32 HCLK_Divisor);
void SCU_PCLKDivisorConfig(u32 PCLK_Divisor);
void SCU_APBPeriphClockConfig(u32 APBPeriph, FunctionalState NewState);
void SCU_AHBPeriphClockConfig(u32 AHBPeriph, FunctionalState NewState);
void SCU_APBPeriphReset(u32 APBPeriph, FunctionalState NewState);
void SCU_AHBPeriphReset(u32 AHBPeriph, FunctionalState NewState);
void SCU_APBPeriphIdleConfig(u32 APBPeriph, FunctionalState NewState);
void SCU_AHBPeriphIdleConfig(u32 AHBPeriph, FunctionalState NewState);
void SCU_APBPeriphDebugConfig(u32 APBPeriph, FunctionalState NewState);
void SCU_AHBPeriphDebugConfig(u32 AHBPeriph, FunctionalState NewState);
void SCU_BRCLKDivisorConfig(u32 BRCLK_Divisor);
void SCU_TIMCLKSourceConfig(u8 TIMx, u32 TIMCLK_Source);
void SCU_TIMPresConfig(u8 TIMx, u16 Prescaler);
void SCU_USBCLKConfig(u32 USBCLK_Source);
void SCU_PHYCLKConfig(FunctionalState NewState);
void SCU_FMICLKDivisorConfig(u32 FMICLK_Divisor);
void SCU_EMIBCLKDivisorConfig(u32 SCU_EMIBCLK);
void SCU_EMIModeConfig(u32 SCU_EMIMODE);
void SCU_EMIALEConfig(u32 SCU_EMIALE_LEN, u32 SCU_EMIALE_POL);
void SCU_ITConfig(u32 SCU_IT, FunctionalState NewState);
FlagStatus SCU_GetFlagStatus(u32 SCU_Flag);
void SCU_ClearFlag(u32 SCU_Flag);
u32 SCU_GetPLLFreqValue(void);
u32 SCU_GetMCLKFreqValue(void);
u32 SCU_GetRCLKFreqValue(void);
u32 SCU_GetHCLKFreqValue(void);
u32 SCU_GetPCLKFreqValue(void);
void SCU_WakeUpLineConfig(u8 EXTint);
void SCU_SpecIntRunModeConfig(FunctionalState NewState);
void SCU_EnterIdleMode(void);
void SCU_EnterSleepMode(void);
void SCU_UARTIrDASelect(UART_TypeDef * UARTx, u8 UART_IrDA_Mode);
void SCU_PFQBCCmd(FunctionalState NewState);
#endif /*__91x_SCU_H*/
/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/

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/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
* File Name : 91x_tim.c
* Author : MCD Application Team
* Date First Issued : 05/18/2006 : Version 1.0
* Description : This file provides all the TIM software functions.
********************************************************************************
* History:
* 05/24/2006 : Version 1.1
* 05/18/2006 : Version 1.0
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Includes ------------------------------------------------------------------*/
#include "91x_tim.h"
/* Include of other module interface headers ---------------------------------*/
/* Local includes ------------------------------------------------------------*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* TIM Bits Masks */
#define TIM_PWM_MASK 0x0010
#define TIM_OPM_MASK 0x0020
#define TIM_OC1_ENABLE_MASK 0x0040
#define TIM_OC1_DISABLE_MASK 0xFFBF
#define TIM_OC2_ENABLE_MASK 0x0080
#define TIM_OC2_DISABLE_MASK 0xFF7F
#define TIM_OLVL1_SET_MASK 0x0100
#define TIM_OLVL1_RESET_MASK 0xFEFF
#define TIM_OLVL2_SET_MASK 0x0200
#define TIM_OLVL2_RESET_MASK 0xFDFF
#define TIM_ENABLE_MASK 0x8000
#define TIM_DISABLE_MASK 0x7FFF
#define TIM_DMA_CLEAR_MASK 0xCFFF
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Interface functions -------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/*******************************************************************************
* Function Name : TIM_DeInit
* Description : Initializes TIM peripheral control and registers to their
* : default reset values.
* Input : TIMx: where x can be from 0 to 3 to select the TIM
* peripheral.
* Output : None
* Return : None
*******************************************************************************/
void TIM_DeInit(TIM_TypeDef *TIMx)
{
if((TIMx == TIM0)||(TIMx == TIM1))
{
SCU_APBPeriphReset(__TIM01, DISABLE); /* TIM0 & TIM1 Reset's off */
}
else
{
SCU_APBPeriphReset(__TIM23, DISABLE); /* TIM2 & TIM3 Reset's off */
}
/* Set all the TIMx registers to thier default values */
TIMx->OC1R = 0x8000;
TIMx->OC2R = 0x8000;
TIMx->CR1 = 0x0;
TIMx->CR2 = 0x1;
TIMx->CNTR = 0x1234;
TIMx->SR = 0x0;
}
/*******************************************************************************
* Function Name : TIM_StructInit
* Description : Fills in a TIM_InitTypeDef structure with the reset value of
* each parameter.
* Input : TIM_InitStruct : pointer to a TIM_InitTypeDef structure
which will be initialized.
* Output : None
* Return : None.
*******************************************************************************/
void TIM_StructInit(TIM_InitTypeDef *TIM_InitStruct)
{
TIM_InitStruct->TIM_Mode = 0x0000;
TIM_InitStruct->TIM_OC1_Modes = 0x0000;
TIM_InitStruct->TIM_OC2_Modes = 0x0000;
TIM_InitStruct->TIM_Clock_Source = 0x0000;
TIM_InitStruct->TIM_Clock_Edge = 0x0000;
TIM_InitStruct->TIM_OPM_INPUT_Edge = 0x0000;
TIM_InitStruct->TIM_ICAP1_Edge = 0x0000;
TIM_InitStruct->TIM_ICAP2_Edge = 0x0000;
TIM_InitStruct->TIM_Prescaler = 0x0000;
TIM_InitStruct->TIM_Pulse_Level_1 = 0x0000;
TIM_InitStruct->TIM_Pulse_Level_2 = 0x0000;
TIM_InitStruct->TIM_Period_Level = 0x0000;
TIM_InitStruct->TIM_Pulse_Length_1 = 0x0000;
TIM_InitStruct->TIM_Pulse_Length_2 = 0x0000;
TIM_InitStruct->TIM_Full_Period = 0x0000;
}
/*******************************************************************************
* Function Name : TIM_Init
* Description : Initializes TIM peripheral according to the specified
* parameters in the TIM_InitTypeDef structure.
* Input1 : TIMx: where x can be from 0 to 3 to select the TIM
* peripheral.
* Input2 : TIM_InitStruct: pointer to a TIM_InitTypeDef structure that
* contains the configuration information for the specified
* TIM peripheral.
* Output : None
* Return : None
*******************************************************************************/
void TIM_Init(TIM_TypeDef *TIMx, TIM_InitTypeDef *TIM_InitStruct)
{
/***************************** Clock configuration ****************************/
if (TIM_InitStruct->TIM_Clock_Source == TIM_CLK_APB)
{
/* APB clock */
TIMx->CR1 &= TIM_CLK_APB;
}
else
{
/* External/SCU clock */
TIMx->CR1 |= TIM_CLK_EXTERNAL;
if (TIM_InitStruct->TIM_Clock_Edge == TIM_CLK_EDGE_RISING)
{
/* Clock rising edge */
TIMx->CR1 |= TIM_CLK_EDGE_RISING;
}
else
{
/* Clock falling edge */
TIMx->CR1 &= TIM_CLK_EDGE_FALLING;
}
}
/************************** Prescaler configuration ***************************/
TIMx->CR2 =( TIMx->CR2 & 0xFF00 )|TIM_InitStruct->TIM_Prescaler ;
/********************************** TIM Modes *********************************/
switch ( TIM_InitStruct->TIM_Mode)
{
/******************************* PWM Input mode *******************************/
case TIM_PWMI:
/* Set the PWMI Bit */
TIMx->CR1 |= TIM_PWMI;
/* Set the first edge Level */
if ( TIM_InitStruct->TIM_ICAP1_Edge == TIM_ICAP1_EDGE_RISING)
{
TIMx->CR1 |= TIM_ICAP1_EDGE_RISING;
}
else
{
TIMx->CR1 &= TIM_ICAP1_EDGE_FALLING;
}
/* Set the Second edge Level ( Opposite of the first level ) */
if ( TIM_InitStruct->TIM_ICAP1_Edge == TIM_ICAP1_EDGE_RISING)
{
TIMx->CR1 &= TIM_ICAP2_EDGE_FALLING;
}
else
{
TIMx->CR1 |= TIM_ICAP2_EDGE_RISING;
}
break;
/************************** Output compare channel 1 **************************/
case TIM_OCM_CHANNEL_1:
if (TIM_InitStruct->TIM_Pulse_Level_1 == TIM_HIGH)
{
TIMx->CR1 |= TIM_OLVL1_SET_MASK;
}
else
{
TIMx->CR1 &= TIM_OLVL1_RESET_MASK;
}
TIMx->OC1R = TIM_InitStruct->TIM_Pulse_Length_1;
if (TIM_InitStruct->TIM_OC1_Modes == TIM_TIMING)
{
TIMx->CR1 &= TIM_OC1_DISABLE_MASK;
}
else
{
TIMx->CR1 |= TIM_OC1_ENABLE_MASK;
}
break;
/************************** Output compare channel 2 **************************/
case TIM_OCM_CHANNEL_2:
if (TIM_InitStruct->TIM_Pulse_Level_2 == TIM_HIGH)
{
TIMx->CR1 |= TIM_OLVL2_SET_MASK;
}
else
{
TIMx->CR1 &= TIM_OLVL2_RESET_MASK;
}
TIMx->OC2R = TIM_InitStruct->TIM_Pulse_Length_2;
if (TIM_InitStruct->TIM_OC2_Modes == TIM_TIMING)
{
TIMx->CR1 &= TIM_OC2_DISABLE_MASK;
}
else
{
TIMx->CR1 |= TIM_OC2_ENABLE_MASK;
}
break;
/************************ Output compare channel 1 & 2 ************************/
case TIM_OCM_CHANNEL_12:
TIMx->OC2R = TIM_InitStruct->TIM_Pulse_Length_2;
TIMx->OC1R = TIM_InitStruct->TIM_Pulse_Length_1;
if (TIM_InitStruct->TIM_OC2_Modes == TIM_TIMING)
{
TIMx->CR1 &= TIM_OC2_DISABLE_MASK;
}
else
{
TIMx->CR1 |= TIM_OC2_ENABLE_MASK;
}
if (TIM_InitStruct->TIM_OC1_Modes == TIM_TIMING)
{
TIMx->CR1 &= TIM_OC1_DISABLE_MASK;
}
else
{
TIMx->CR1 |= TIM_OC1_ENABLE_MASK;
}
if (TIM_InitStruct->TIM_Pulse_Level_1 == TIM_HIGH)
{
TIMx->CR1 |= TIM_OLVL1_SET_MASK;
}
else
{
TIMx->CR1 &= TIM_OLVL1_RESET_MASK;
}
if (TIM_InitStruct->TIM_Pulse_Level_2 == TIM_HIGH)
{
TIMx->CR1 |= TIM_OLVL2_SET_MASK;
}
else
{
TIMx->CR1 &= TIM_OLVL2_RESET_MASK;
}
break;
/********************************** PWM mode **********************************/
case TIM_PWM:
/* Set the Level During the pulse */
if ( TIM_InitStruct->TIM_Pulse_Level_1 == TIM_HIGH)
{
TIMx->CR1 |= TIM_OLVL2_SET_MASK;
}
else
{
TIMx->CR1 &= TIM_OLVL2_RESET_MASK;
}
/* Set the Level after the pulse */
if (TIM_InitStruct->TIM_Period_Level == TIM_HIGH)
{
TIMx->CR1 |= TIM_OLVL1_SET_MASK;
}
else
{
TIMx->CR1 &= TIM_OLVL1_RESET_MASK;
}
/* Set the OCAE */
TIMx->CR1 |= TIM_OC1_ENABLE_MASK;
/* Set the PWM Bit */
TIMx->CR1 |= TIM_PWM_MASK;
/* Set the Duty Cycle value */
if ( TIM_InitStruct->TIM_Pulse_Length_1 < 5 )
{
TIM_InitStruct->TIM_Pulse_Length_1 = 4;
}
TIMx->OC1R = TIM_InitStruct->TIM_Pulse_Length_1 - 4;
/* Set the Full Period */
TIMx->OC2R = TIM_InitStruct->TIM_Full_Period - 4;
break;
/******************************* One pulse mode *******************************/
case TIM_OPM:
/* Set the Level During the pulse */
if (TIM_InitStruct->TIM_Pulse_Level_1 == TIM_HIGH)
{
TIMx->CR1 |= TIM_OLVL2_SET_MASK;
}
/* Set the Level after the pulse */
if (TIM_InitStruct->TIM_Period_Level == TIM_HIGH)
{
TIMx->CR1 |= TIM_OLVL1_SET_MASK;
}
/* Set the Activation Edge on the ICAP 1 */
if (TIM_InitStruct->TIM_OPM_INPUT_Edge == TIM_OPM_EDGE_RISING)
{
TIMx->CR1 |= TIM_OPM_EDGE_RISING;
}
/* Set the Output Compare Function */
TIMx->CR1 |= TIM_OC1_ENABLE_MASK;
/* Set the One pulse mode */
TIMx->CR1 |= TIM_OPM_MASK;
/* Set the Pulse length */
TIMx->OC1R = TIM_InitStruct->TIM_Pulse_Length_1;
break;
/*************************** Input capture channel 1 **************************/
case TIM_ICAP_CHANNEL_1:
if (TIM_InitStruct->TIM_ICAP1_Edge == TIM_ICAP1_EDGE_RISING)
{
TIMx->CR1 |= TIM_ICAP1_EDGE_RISING;
}
else
{
TIMx->CR1 &= TIM_ICAP1_EDGE_FALLING;
}
break;
/*************************** Input capture channel 2 **************************/
case TIM_ICAP_CHANNEL_2:
if (TIM_InitStruct->TIM_ICAP2_Edge == TIM_ICAP2_EDGE_RISING)
{
TIMx->CR1 |= TIM_ICAP2_EDGE_RISING;
}
else
{
TIMx->CR1 &= TIM_ICAP2_EDGE_FALLING;
}
break;
/************************* Input capture channel 1 & 2 ************************/
case TIM_ICAP_CHANNEL_12:
if (TIM_InitStruct->TIM_ICAP2_Edge == TIM_ICAP2_EDGE_RISING)
{
TIMx->CR1 |= TIM_ICAP2_EDGE_RISING;
}
else
{
TIMx->CR1 &= TIM_ICAP2_EDGE_FALLING;
}
if (TIM_InitStruct->TIM_ICAP1_Edge == TIM_ICAP1_EDGE_RISING)
{
TIMx->CR1 |= TIM_ICAP1_EDGE_RISING;
}
else
{
TIMx->CR1 &= TIM_ICAP1_EDGE_FALLING;
}
break;
default:
break;
}
}
/*******************************************************************************
* Function Name : TIM_CounterCmd
* Description : Enables or disables TIMx Counter peripheral.
* Input1 : TIMx: where x can be from 0 to 3 to select the TIM
* peripheral.
* Input2 : TIM_operation: specifies the new state of the TIMx Counter.
* This parameter can be one of the following values:
* - TIM_START: Start the timer counter.
* - TIM_STOP : Stop the timer counter.
* - TIM_CLEAR: Clear the timer counter.
* Output : None
* Return : None
*******************************************************************************/
void TIM_CounterCmd(TIM_TypeDef *TIMx, TIM_CounterOperations TIM_operation)
{
switch (TIM_operation)
{
case TIM_START:
TIMx->CR1 |= TIM_ENABLE_MASK;
break;
case TIM_STOP:
TIMx->CR1 &= TIM_DISABLE_MASK;
break;
case TIM_CLEAR:
TIMx->CNTR = 0x1234;
break;
default:
break;
}
}
/*******************************************************************************
* Function Name : TIM_PrescalerConfig
* Description : This routine is used to configure the TIMx prescaler value
* (when using the APB clock).
* Input1 : TIMx: where x can be from 0 to 3 to select the TIM
* peripheral.
* Input2 : TIM_Prescaler: specifies the prescaler value. This parameter
* can be a value from 0x0 to 0xFF.
* Output : None
* Return : None
*******************************************************************************/
void TIM_PrescalerConfig(TIM_TypeDef *TIMx, u8 TIM_Prescaler)
{
TIMx->CR2 &= 0xFF00;
TIMx->CR2 |= TIM_Prescaler;
}
/*******************************************************************************
* Function Name : TIM_GetPrescalerValue
* Description : This routine is used to get the TIMx prescaler value
* (when using the APB clock).
* Input : TIMx: where x can be from 0 to 3 to select the TIM
* peripheral.
* Output : None
* Return : The prescaler value.
*******************************************************************************/
u8 TIM_GetPrescalerValue(TIM_TypeDef *TIMx)
{
return TIMx->CR2 & 0x00FF;
}
/*******************************************************************************
* Function Name : TIM_GetCounterValue
* Description : This routine is used to get the TIMx counter value.
* Input : TIMx: where x can be from 0 to 3 to select the TIM
* peripheral.
* Output : None
* Return : The counter value.
*******************************************************************************/
u16 TIM_GetCounterValue(TIM_TypeDef *TIMx)
{
return TIMx->CNTR;
}
/*******************************************************************************
* Function Name : TIM_GetICAP1Value
* Description : This routine is used to get the Input Capture 1 value.
* Input : TIMx: where x can be from 0 to 3 to select the TIM
* peripheral.
* Output : None
* Return : The Input Capture 1 value.
*******************************************************************************/
u16 TIM_GetICAP1Value(TIM_TypeDef *TIMx)
{
return TIMx->IC1R;
}
/*******************************************************************************
* Function Name : TIM_GetICAP2Value
* Description : This routine is used to get the Input Capture 2 value.
* Input : TIMx: where x can be from 0 to 3 to select the TIM
* peripheral.
* Output : None
* Return : The Input Capture 2 value.
*******************************************************************************/
u16 TIM_GetICAP2Value(TIM_TypeDef *TIMx)
{
return TIMx->IC2R;
}
/*******************************************************************************
* Function Name : TIM_SetPulse
* Description : This routine is used to set the pulse value.
* Input1 : TIMx: where x can be from 0 to 3 to select the TIM
* peripheral.
* Input2 : TIM_Channel: specifies the needed channel.
* This parameter can be one of the following values:
* - TIM_PWM_OC1_Channel: PWM/Output Compare 1 Channel
* - TIM_OC2_Channel : Output Compare 2 Channel
* Input3 : TIM_Pulse: specifies the new pulse value.
* Output : None
* Return : None
*******************************************************************************/
void TIM_SetPulse(TIM_TypeDef *TIMx,u16 TIM_Channel ,u16 TIM_Pulse)
{
if (TIM_Channel == TIM_PWM_OC1_Channel)
{
TIMx->OC1R = TIM_Pulse;
}
else
{
TIMx->OC2R = TIM_Pulse;
}
}
/*******************************************************************************
* Function Name : TIM_GetFlagStatus
* Description : Checks whether the specified TIMx flag is set or not.
* Input1 : TIMx: where x can be from 0 to 3 to select the TIM
* peripheral.
* Input2 : TIM_Flag: specifies the flag to check.
* This parameter can be one of the following values:
* - TIM_FLAG_IC1: Input Capture Channel 1 Flag
* - TIM_FLAG_IC2: Input Capture Channel 2 Flag
* - TIM_FLAG_TO : Timer Overflow Flag
* - TIM_FLAG_OC1: Output Compare Channel 1 Flag
* - TIM_FLAG_OC2: Output Compare Channel 2 Flag
* Output : None
* Return : The NewState of the TIM_Flag (SET or RESET).
*******************************************************************************/
FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, u16 TIM_Flag)
{
if((TIMx->SR & TIM_Flag) == RESET)
{
return RESET;
}
else
{
return SET;
}
}
/*******************************************************************************
* Function Name : TIM_ClearFlag
* Description : Clears the TIM Flag passed as a parameter.
* Input1 : TIMx: where x can be from 0 to 3 to select the TIM
* peripheral.
* Input2 : TIM_Flag: specifies the flag to clear.
* This parameter can be one of the following values:
* - TIM_FLAG_IC1: Input Capture Channel 1 Flag
* - TIM_FLAG_IC2: Input Capture Channel 2 Flag
* - TIM_FLAG_TO : Timer Overflow Flag
* - TIM_FLAG_OC1: Output Compare Channel 1 Flag
* - TIM_FLAG_OC2: Output Compare Channel 2 Flag
* Output : None
* Return : None
*******************************************************************************/
void TIM_ClearFlag(TIM_TypeDef *TIMx, u16 TIM_Flag)
{
/* Clear TIM_Flag */
TIMx->SR &= ~TIM_Flag;
}
/*******************************************************************************
* Function Name : TIM_GetPWMIPulse
* Description : This routine is used to get the Pulse value in PWMI Mode.
* Input : TIMx: where x can be from 0 to 3 to select the TIM
* peripheral.
* Output : None
* Return : The pulse value.
*******************************************************************************/
u16 TIM_GetPWMIPulse(TIM_TypeDef *TIMx)
{
return TIMx->IC2R;
}
/*******************************************************************************
* Function Name : TIM_GetPWMIPeriod
* Description : This routine is used to get the Period value in PWMI Mode.
* Input : TIMx: where x can be from 0 to 3 to select the TIM
* peripheral.
* Output : None
* Return : The period value.
*******************************************************************************/
u16 TIM_GetPWMIPeriod(TIM_TypeDef *TIMx)
{
return TIMx->IC1R;
}
/*******************************************************************************
* Function Name : TIM_ITConfig
* Description : Configures the Timer interrupt source.
* Input1 : TIMx: where x can be from 0 to 3 to select the TIM
* peripheral.
* Input2 : TIM_IT: specifies the TIM interrupt source to be enabled.
* This parameter can be one of the following values:
* - TIM_IT_IC1: Input Capture 1 Interrupt source.
* - TIM_IT_OC1: Output Compare 1 Interrupt source.
* - TIM_IT_TO : Timer Overflow Interrupt source.
* - TIM_IT_IC2: Input Capture 2 Interrupt source.
* - TIM_IT_OC2: Output Compare 2 Interrupt source.
* Input3 : TIM_Newstate: specifies the new state of the TIMx IT.
* This parameter can be one of the following values:
* - ENABLE : Enable the needed interrupt.
* - DISABLE: Disable the needed interrupt.
* Output : None
* Return : None
*******************************************************************************/
void TIM_ITConfig(TIM_TypeDef *TIMx, u16 TIM_IT, FunctionalState TIM_Newstate)
{
if(TIM_Newstate == ENABLE)
{
TIMx->CR2 = (TIMx->CR2 & 0x00FF) | TIM_IT;
}
else
{
TIMx->CR2 &= ~TIM_IT;
}
}
/*******************************************************************************
* Function Name : TIM_DMAConfig
* Description : Configures the Timer DMA source.
* Input1 : TIMx: where x can be from 0 to 3 to select the TIM
* peripheral.
* Input2 : TIM_DMA_Souces: specifies the TIM DMA source to be selected.
* This parameter can be one of the following values:
* - TIM_DMA_IC1: Input Capture 1 DMA source.
* - TIM_DMA_OCA1 Output Compare 1 DMA source.
* - TIM_DMA_TO: Timer Overflow DMA source.
* - TIM_DMA_IC2: Input Capture 2 DMA source.
* - TIM_DMA_OC2: Output Compare 2 DMA source.
* Output : None
* Return : None
*******************************************************************************/
void TIM_DMAConfig(TIM_TypeDef *TIMx, u16 TIM_DMA_Sources)
{
/* Reset the DMAS[1:0] bits */
TIMx->CR1 &= TIM_DMA_CLEAR_MASK;
/* Set the DMAS[1:0] bits according to TIM_DMA_Sources parameter */
TIMx->CR1 |= TIM_DMA_Sources;
}
/*******************************************************************************
* Function Name : TIM_DMACmd
* Description : Enables or disables TIMx DMA peripheral.
* Input1 : TIMx: where x can be from 0 to 3 to select the TIM
* peripheral.
* Input2 : TIM_Newstate: new state of the TIMx DMA peripheral
* This parameter can be one of the following values:
* - ENABLE : Enable the TIMx DMA.
* - DISABLE: Disable the TIMx DMA.
* Output : None
* Return : None
*******************************************************************************/
void TIM_DMACmd(TIM_TypeDef *TIMx, FunctionalState TIM_Newstate)
{
if (TIM_Newstate == ENABLE)
{
TIMx->CR2 |= TIM_DMA_ENABLE;
}
else
{
TIMx->CR2 &= TIM_DMA_DISABLE;
}
}
/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/

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/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
* File Name : 91x_tim.h
* Author : MCD Application Team
* Date First Issued : 05/18/2006 : Version 1.0
* Description : This file contains all the functions prototypes for the
* TIM software library.
********************************************************************************
* History:
* 05/24/2006 : Version 1.1
* 05/18/2006 : Version 1.0
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __91x_TIM_H
#define __91x_TIM_H
/* Includes ------------------------------------------------------------------*/
#include "91x_map.h"
#include "91x_scu.h"
/* Exported types ----------------------------------------------------------- */
/* TIM Init structure define */
typedef struct
{
u16 TIM_Mode; /* Timer mode */
u16 TIM_OC1_Modes; /* Output Compare 1 Mode: Timing or Wave */
u16 TIM_OC2_Modes; /* Output Compare 2 Mode: Timing or Wave */
u16 TIM_Clock_Source; /* Timer Clock source APB/SCU/EXTERNAL */
u16 TIM_Clock_Edge; /* Timer Clock Edge: Rising or Falling Edge */
u16 TIM_OPM_INPUT_Edge; /* Timer Input Capture 1 Edge used in OPM Mode */
u16 TIM_ICAP1_Edge; /* Timer Input Capture 1 Edge used in ICAP1 Mode */
u16 TIM_ICAP2_Edge; /* Timer Input Capture 2 Edge used in ICAP2 Mode */
u8 TIM_Prescaler; /* Timer Prescaler factor */
u16 TIM_Pulse_Level_1; /* Level applied on the Output Compare Pin 1 */
u16 TIM_Pulse_Level_2; /* Level applied on the Output Compare Pin 2 */
u16 TIM_Period_Level; /* Level applied during the Period of a PWM Mode */
u16 TIM_Pulse_Length_1; /* Pulse 1 Length used in Output Compare 1 Mode */
u16 TIM_Pulse_Length_2; /* Pulse 2 Length used in Output Compare 2 Mode */
u16 TIM_Full_Period; /* Period Length used in PWM Mode */
} TIM_InitTypeDef;
typedef enum
{
TIM_START,
TIM_STOP,
TIM_CLEAR
} TIM_CounterOperations;
/* Exported constants --------------------------------------------------------*/
/* TIM MODE */
#define TIM_PWMI 0x4000 /* PWM INPUT Mode */
#define TIM_OCM_CHANNEL_1 0x0040 /* OUTPUT COMPARE CHANNEL 1 Mode */
#define TIM_OCM_CHANNEL_2 0x0080 /* OUTPUT COMPARE CHANNEL 2 Mode */
#define TIM_OCM_CHANNEL_12 0x00C0 /* OUTPUT COMPARE CHANNEL 1 & 2 Mode */
#define TIM_PWM 0x0010 /* PWM Mode */
#define TIM_OPM 0x0020 /* ONE PULSE Mode */
#define TIM_ICAP_CHANNEL_1 0x0400 /* INPUT CAPTURE 1 Mode */
#define TIM_ICAP_CHANNEL_2 0x0500 /* INPUT CAPTURE 2 Mode */
#define TIM_ICAP_CHANNEL_12 0x0600 /* INPUT CAPTURE 1 & 2 Mode */
/* TIM OUTPUT COMPARE MODE */
#define TIM_WAVE 0x0001
#define TIM_TIMING 0x0002
/* TIM CLOCK SOURCE */
#define TIM_CLK_APB 0xFFFE
#define TIM_CLK_EXTERNAL 0x0001
#define TIM_CLK_SCU 0x0001
/* TIM CLOCK EDGE */
#define TIM_CLK_EDGE_FALLING 0xFFFD
#define TIM_CLK_EDGE_RISING 0x0002
/* TIM OPM INPUT EDGE */
#define TIM_OPM_EDGE_FALLING 0xFFFB
#define TIM_OPM_EDGE_RISING 0x0004
/* TIM ICAPA INPUT EDGE */
#define TIM_ICAP1_EDGE_FALLING 0xFFFB
#define TIM_ICAP1_EDGE_RISING 0x0004
/* TIM ICAPB INPUT EDGE */
#define TIM_ICAP2_EDGE_FALLING 0xFFF7
#define TIM_ICAP2_EDGE_RISING 0x0008
/* TIM OUTPUT LEVEL */
#define TIM_HIGH 0x0200
#define TIM_LOW 0x0300
/* TIM OUTPUT EDGE */
#define TIM_OUTPUT_EDGE_RISING 0x8000
#define TIM_OUTPUT_EDGE_FALLING 0x0800
/* TIM channels */
#define TIM_PWM_OC1_Channel 0x1 /* PWM/Output Compare 1 Channel */
#define TIM_OC2_Channel 0x2 /* Output Compare 2 Channel */
/* TIM DMA SOURCE */
#define TIM_DMA_IC1 0x0000 /* Input Capture Channel 1 DMA Source */
#define TIM_DMA_OC1 0x1000 /* OUTPUT Compare Channel 1 DMA Source */
#define TIM_DMA_IC2 0x2000 /* Input Capture Channel 2 DMA Source */
#define TIM_DMA_OC2 0x3000 /* OUTPUT Compare Channel 2 DMA Source */
/* TIM DMA ENABLE or DISABLE */
#define TIM_DMA_ENABLE 0x0400 /* DMA Enable */
#define TIM_DMA_DISABLE 0xFBFF /* DMA Disable */
/* TIM Interruption Sources*/
#define TIM_IT_IC1 0x8000 /* Input Capture Channel 1 Interrupt Source */
#define TIM_IT_OC1 0x4000 /* Output Compare Channel 1 Interrupt Source */
#define TIM_IT_TO 0x2000 /* Timer OverFlow Interrupt Source */
#define TIM_IT_IC2 0x1000 /* Input Capture Channel 2 Interrupt Source */
#define TIM_IT_OC2 0x0800 /* Output Compare Channel 2 Interrupt Source */
/* TIM Flags */
#define TIM_FLAG_IC1 0x8000 /* Input Capture Channel 1 Flag */
#define TIM_FLAG_OC1 0x4000 /* Output Compare Channel 1 Flag */
#define TIM_FLAG_TO 0x2000 /* Timer OverFlow Flag */
#define TIM_FLAG_IC2 0x1000 /* Input Capture Channel 2 Flag */
#define TIM_FLAG_OC2 0x0800 /* Output Compare Channel 2 Flag */
/* Module private variables --------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void TIM_Init(TIM_TypeDef *TIMx, TIM_InitTypeDef *TIM_InitStruct);
void TIM_DeInit(TIM_TypeDef *TIMx);
void TIM_StructInit(TIM_InitTypeDef *TIM_InitStruct);
void TIM_CounterCmd(TIM_TypeDef *TIMx, TIM_CounterOperations TIM_operation);
void TIM_PrescalerConfig(TIM_TypeDef *TIMx, u8 TIM_Prescaler);
u8 TIM_GetPrescalerValue(TIM_TypeDef *TIMx);
u16 TIM_GetCounterValue(TIM_TypeDef *TIMx);
u16 TIM_GetICAP1Value(TIM_TypeDef *TIMx);
u16 TIM_GetICAP2Value(TIM_TypeDef *TIMx);
void TIM_SetPulse(TIM_TypeDef *TIMx,u16 TIM_Channel ,u16 TIM_Pulse);
FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, u16 TIM_Flag);
void TIM_ClearFlag(TIM_TypeDef *TIMx, u16 TIM_Flag);
u16 TIM_GetPWMIPulse(TIM_TypeDef *TIMx);
u16 TIM_GetPWMIPeriod(TIM_TypeDef *TIMx);
void TIM_ITConfig(TIM_TypeDef *TIMx, u16 TIM_IT, FunctionalState TIM_Newstate);
void TIM_DMAConfig(TIM_TypeDef *TIMx, u16 TIM_DMA_Sources);
void TIM_DMACmd(TIM_TypeDef *TIMx, FunctionalState TIM_Newstate);
#endif /* __91x_TIM_H */
/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/

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/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
* File Name : 91x_type.h
* Author : MCD Application Team
* Date First Issued : 05/18/2006 : Version 1.0
* Description : It contains common types and constants used in all the
* peripherals' drivers.
********************************************************************************
* History:
* 05/24/2006 : Version 1.1
* 05/18/2006 : Version 1.0
**********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*********************************************************************************/
#ifndef __91x_type_H
#define __91x_type_H
#include "type.h"
typedef volatile unsigned long vu32;
typedef volatile unsigned short vu16;
typedef volatile unsigned char vu8;
typedef volatile signed long vs32;
typedef volatile signed short vs16;
typedef volatile signed char vs8;
#ifndef _TIME48_C_
typedef enum { FALSE = 0, TRUE = !FALSE } bool;
#endif
typedef enum { RESET = 0, SET = !RESET } FlagStatus, ITStatus;
typedef enum { DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
typedef enum { ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
#endif /* __91x_type_H */
/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/

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/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
* File Name : 91x_uart.c
* Author : MCD Application Team
* Date First Issued : 05/18/2006 : Version 1.0
* Description : This file provides all the UART software functions.
********************************************************************************
* History:
* 05/24/2006 : Version 1.1
* 05/18/2006 : Version 1.0
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Includes ------------------------------------------------------------------*/
#include "91x_uart.h"
#include "91x_scu.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* UART IrDA Mask */
#define UART_IrDA_Disable_Mask 0xFFFD /* IrDA Disable Mask */
#define UART_IrDA_Enable_Mask 0x0002 /* IrDA Enable Mask */
#define IrDA_LowPower_Enable_Mask 0x0004 /*IrDA lower power mode enable*/
#define IrDA_LowPower_Disable_Mask 0xFFFB /*IrDA lower power mode enable*/
/* UART Mask */
#define UART_Enable_Mask 0x0001 /* UART Enable Mask */
#define UART_Disable_Mask 0xFFFE /* UART Disable Mask */
/* UART LoopBack */
#define UART_LoopBack_Disable_Mask 0xFF7F /* LoopBack Disable Mask */
#define UART_LoopBack_Enable_Mask 0x0080 /* LoopBack Enable Mask */
#define UART_WordLength_Mask 0xFF9F /* UART Word Length Mask */
#define UART_Parity_Mask 0xFF79 /* UART Parity Mask */
#define UART_HardwareFlowControl_Mask 0x3FFF /* UART Hardware Flow Control Mask */
#define UART_TxRxFIFOLevel_Mask 0xFFC0 /* UART Tx Rx FIFO Level Mask */
#define UART_BreakChar_Mask 0x0001 /* UART Break Character send Mask*/
#define UART_FLAG_Mask 0x1F /* UART Flag Mask */
#define UART_Mode_Mask 0xFCFF /* UART Mode Mask */
#define UART_RTS_LowLevel_Mask 0x0800 /* RTS signal is low */
#define UART_RTS_HighLevel_Mask 0xF7FF /* RTS signal is High */
#define UART_DTR_LowLevel_Mask 0x0400 /* DTR signal is low */
#define UART_DTR_HighLevel_Mask 0xFBFF /* DTR signal is High */
#define UART_ClearFlag_Mask 0xAA /* Clear Flag Mask */
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/*******************************************************************************
* Function Name : UART_DeInit
* Description : Deinitializes the UARTx peripheral registers
* to their default reset values.
* Input : UARTx: where x can be 0,1 or 2 to select the UART peripheral.
* Output : None
* Return : None
*******************************************************************************/
void UART_DeInit(UART_TypeDef* UARTx)
{
/* Reset the UARTx registers values */
if(UARTx == UART0)
{
SCU_APBPeriphReset(__UART0,ENABLE);
SCU_APBPeriphReset(__UART0,DISABLE);
}
else if(UARTx == UART1)
{
SCU_APBPeriphReset(__UART1,ENABLE);
SCU_APBPeriphReset(__UART1,DISABLE);
}
else if(UARTx == UART2)
{
SCU_APBPeriphReset(__UART2,ENABLE);
SCU_APBPeriphReset(__UART2,DISABLE);
}
}
/*******************************************************************************
* Function Name : UART_Init
* Description : Initializes the UARTx peripheral according to the specified
* parameters in the UART_InitStruct .
* Input : - UARTx: where x can be 0,1or 2 to select the UART peripheral.
* - UART_InitStruct: pointer to a UART_InitTypeDef structure
* that contains the configuration information for the
* specified UART peripheral.
* Output : None
* Return : None
*******************************************************************************/
void UART_Init(UART_TypeDef* UARTx, UART_InitTypeDef* UART_InitStruct)
{
u64 UART_MainClock = 0;
u32 IntegerDivider = 0;
u32 FractionalDivider = 0;
/* Clear the LCR[6:5] bits */
UARTx->LCR &= UART_WordLength_Mask;
/* Set the LCR[6:5] bits according to UART_WordLength value */
UARTx->LCR |= UART_InitStruct->UART_WordLength;
/* Choose Stop Bits */
if(UART_InitStruct->UART_StopBits == UART_StopBits_2)
{
/* 2 Stop Bit */
UARTx->LCR |= UART_StopBits_2;
}
else
{
/* One Stop Bits */
UARTx->LCR &= UART_StopBits_1;
}
/* Configure the Parity */
/* Clear the LCR[7]and LCR[2:1] bits */
UARTx->LCR &= UART_Parity_Mask;
/* Set the LCR[7]and LCR[2:1] bits according to UART_Parity value */
UARTx->LCR |= UART_InitStruct->UART_Parity;
/* Configure the BaudRate */
UART_MainClock = (SCU_GetMCLKFreqValue())*1000;
if((SCU->CLKCNTR & 0x200) != 0x200)
{
UART_MainClock = UART_MainClock/2;
}
/* Determine the integer part */
IntegerDivider = ((100) * (UART_MainClock) / (16 * (UART_InitStruct->UART_BaudRate)));
UARTx->IBRD = IntegerDivider / 100;
/* Determine the fractional part */
FractionalDivider = IntegerDivider - (100 * (UARTx->IBRD));
UARTx->FBRD = ((((FractionalDivider * 64) + 50) / 100));
/* Choose the Hardware Flow Control */
/* Clear the CR[15:14] bits */
UARTx->CR &= UART_HardwareFlowControl_Mask;
/* Set the CR[15:14] bits according to UART_HardwareFlowControl value */
UARTx->CR |= UART_InitStruct->UART_HardwareFlowControl;
/* Configure the UART mode */
/* Clear the CR[9:8] bits */
UARTx->CR &= UART_Mode_Mask;
/* Set the CR[9:8] bits according to UART_Mode value */
UARTx->CR |= UART_InitStruct->UART_Mode;
/* Enable or disable the FIFOs */
/* Set the FIFOs Levels */
if(UART_InitStruct->UART_FIFO == UART_FIFO_Enable)
{
/* Enable the FIFOs */
UARTx->LCR |= UART_FIFO_Enable;
/* Clear TXIFLSEL and RXIFLSEL bits */
UARTx->IFLS &= UART_TxRxFIFOLevel_Mask;
/* Set RXIFLSEL bits according to UART_RxFIFOLevel value */
UARTx->IFLS |= (UART_InitStruct->UART_RxFIFOLevel << 3);
/* Set TXIFLSEL bits according to UART_TxFIFOLevel value */
UARTx->IFLS |= UART_InitStruct->UART_TxFIFOLevel;
}
else
{
/* Disable the FIFOs */
UARTx->LCR &= UART_FIFO_Disable;
}
}
/*******************************************************************************
* Function Name : UART_StructInit
* Description : Fills each UART_InitStruct member with its reset value.
* Input : UART_InitStruct: pointer to a UART_InitTypeDef structure which
* will be initialized.
* Output : None
* Return : None
*******************************************************************************/
void UART_StructInit(UART_InitTypeDef* UART_InitStruct)
{
/* Reset the UART_InitStruct members */
UART_InitStruct->UART_WordLength = UART_WordLength_8D;
UART_InitStruct->UART_StopBits = UART_StopBits_1;
UART_InitStruct->UART_Parity = UART_Parity_Odd ;
UART_InitStruct->UART_BaudRate = 9600;
UART_InitStruct->UART_HardwareFlowControl = UART_HardwareFlowControl_None;
UART_InitStruct->UART_Mode = UART_Mode_Tx_Rx;
UART_InitStruct->UART_FIFO = UART_FIFO_Enable;
UART_InitStruct->UART_TxFIFOLevel = UART_FIFOLevel_1_2;
UART_InitStruct->UART_RxFIFOLevel = UART_FIFOLevel_1_2;
}
/*******************************************************************************
* Function Name : UART_Cmd
* Description : Enables or disables the specified UART peripheral.
* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral
* - NewState: new state of the UARTx peripheral.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void UART_Cmd(UART_TypeDef* UARTx, FunctionalState NewState)
{
if (NewState == ENABLE)
{
/* Enable the selected UART by setting the UARTEN bit in the CR register */
UARTx->CR |= UART_Enable_Mask;
}
else
{
/* Disable the selected UART by clearing the UARTEN bit in the CR register */
UARTx->CR &= UART_Disable_Mask;
}
}
/*******************************************************************************
* Function Name : UART_ITConfig
* Description : Enables or disables the specified UART interrupts.
* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral
* - UART_IT: specifies the UART interrupts sources to be
* enabled or disabled. This parameter can be any combination
* of the following values:
* - UART_IT_OverrunError: Overrun Error interrupt
* - UART_IT_BreakError: Break Error interrupt
* - UART_IT_ParityError: Parity Error interrupt
* - UART_IT_FrameError: Frame Error interrupt
* - UART_IT_ReceiveTimeOut: Receive Time Out interrupt
* - UART_IT_Transmit: Transmit interrupt
* - UART_IT_Receive: Receive interrupt
* - UART_IT_DSR: DSR interrupt
* - UART_IT_DCD: DCD interrupt
* - UART_IT_CTS: CTS interrupt
* - UART_IT_RI: RI interrupt
* - NewState: new state of the UARTx peripheral.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void UART_ITConfig(UART_TypeDef* UARTx, u16 UART_IT, FunctionalState NewState)
{
if(NewState == ENABLE)
{
/* Enables the selected interrupts */
UARTx->IMSC |= UART_IT;
}
else
{
/* Disables the selected interrupts */
UARTx->IMSC &= ~UART_IT;
}
}
/*******************************************************************************
* Function Name : UART_DMAConfig
* Description : Configures the UARTx's DMA interface.
* Input : - UARTx: where x can be 1 or 2 to select the UART peripheral
* - UART_DMAOnError: specifies the DMA on error request.
* This parameter can be:
* - UART_DMAOnError_Enable: DMA receive request enabled
* when the UART error interrupt is asserted.
* - UART_DMAOnError_Disable: DMA receive request disabled
* when the UART error interrupt is asserted.
* Output : None
* Return : None
*******************************************************************************/
void UART_DMAConfig(UART_TypeDef* UARTx, u16 UART_DMAOnError)
{
if(UART_DMAOnError == UART_DMAOnError_Enable)
{
UARTx->DMACR &= UART_DMAOnError_Enable;
}
else
{
UARTx->DMACR |= UART_DMAOnError_Disable;
}
}
/*******************************************************************************
* Function Name : UART_DMACmd
* Description : Enables or disables the UARTx's DMA interface.
* Input : - UARTx: where x can be 1 or 2 to select the UART peripheral
* - UART_DMAReq: enables or disables the request of DMA from UART.
* This parameter can be:
* - UART_DMAReq_Tx: Transmit DMA Enable
* - UART_DMAReq_Rx: Receive DMA Enable
* - NewState: new state of the UARTx peripheral.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void UART_DMACmd(UART_TypeDef* UARTx, u8 UART_DMAReq, FunctionalState NewState)
{
if(UART_DMAReq == UART_DMAReq_Tx)
{
if(NewState == ENABLE)
{
UARTx->DMACR |= UART_DMAReq_Tx;
}
else
{
UARTx->DMACR &= ~UART_DMAReq_Tx;
}
}
if(UART_DMAReq == UART_DMAReq_Rx)
{
if(NewState == ENABLE)
{
UARTx->DMACR |= UART_DMAReq_Rx;
}
else
{
UARTx->DMACR &= ~UART_DMAReq_Rx;
}
}
}
/*******************************************************************************
* Function Name : UART_LoopBackConfig
* Description : Enables or disables the LoopBack mode.
* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral
* - NewState: new state of the UARTx peripheral.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void UART_LoopBackConfig(UART_TypeDef* UARTx, FunctionalState NewState)
{
if (NewState == ENABLE)
{
/* Enable the LoopBack mode of the specified UART */
UARTx->CR |= UART_LoopBack_Enable_Mask;
}
else
{
/* Disable the LoopBack mode of the specified UART */
UARTx->CR &= UART_LoopBack_Disable_Mask;
}
}
/*******************************************************************************
* Function Name : UART_GetFlagStatus
* Description : Checks whether the specified UART flag is set or not.
* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral
* - UART_FLAG: specifies the flag to check.
* This parameter can be one of the following values:
* - UART_FLAG_OverrunError: Overrun error flag
* - UART_FLAG_Break: break error flag
* - UART_FLAG_ParityError: parity error flag
* - UART_FLAG_FrameError: frame error flag
* - UART_FLAG_RI: RI flag
* - UART_FLAG_TxFIFOEmpty: Transmit FIFO Empty flag
* - UART_FLAG_RxFIFOFull: Receive FIFO Full flag
* - UART_FLAG_TxFIFOFull: Transmit FIFO Full flag
* - UART_FLAG_RxFIFOEmpty: Receive FIFO Empty flag
* - UART_FLAG_Busy: UART Busy flag
* - UART_FLAG_CTS: CTS flag
* - UART_FLAG_DCD: DCD flag
* - UART_FLAG_DSR: DSR flag
* - UART_RawIT_OverrunError: Overrun Error interrupt flag
* - UART_RawIT_BreakError: Break Error interrupt flag
* - UART_RawIT_ParityError: Parity Error interrupt flag
* - UART_RawIT_FrameError: Frame Error interrupt flag
* - UART_RawIT_ReceiveTimeOut: ReceiveTimeOut interrupt flag
* - UART_RawIT_Transmit: Transmit interrupt flag
* - UART_RawIT_Receive: Receive interrupt flag
* - UART_RawIT_DSR: DSR interrupt flag
* - UART_RawIT_DCD: DCD interrupt flag
* - UART_RawIT_CTS: CTS interrupt flag
* - UART_RawIT_RI: RI interrupt flag
* Output : None
* Return : The new state of UART_FLAG (SET or RESET).
*******************************************************************************/
FlagStatus UART_GetFlagStatus(UART_TypeDef* UARTx, u16 UART_FLAG)
{
u32 UARTReg = 0, FlagPos = 0;
u32 StatusReg = 0;
/* Get the UART register index */
UARTReg = UART_FLAG >> 5;
/* Get the flag position */
FlagPos = UART_FLAG & UART_FLAG_Mask;
if(UARTReg == 1) /* The flag to check is in RSR register */
{
StatusReg = UARTx->RSECR;
}
else if (UARTReg == 2) /* The flag to check is in FR register */
{
StatusReg = UARTx->FR;
}
else if(UARTReg == 3) /* The flag to check is in RIS register */
{
StatusReg = UARTx->RIS;
}
if((StatusReg & (1 << FlagPos))!= RESET)
{
return SET;
}
else
{
return RESET;
}
}
/*******************************************************************************
* Function Name : UART_ClearFlag
* Description : Clears the UARTx's flags(Frame, Parity, Break, Overrun error).
* Input : - UARTx: where x can be 0,1or 2 to select the UART peripheral.
* Output : None
* Return : None
*******************************************************************************/
void UART_ClearFlag(UART_TypeDef* UARTx)
{
/* Clear the flag */
UARTx->RSECR = UART_ClearFlag_Mask;
}
/*******************************************************************************
* Function Name : UART_GetITStatus
* Description : Checks whether the specified UART interrupt has occured or not.
* Input : - UARTx: where x can be 0,1or 2 to select the UART peripheral.
* - UART_IT: specifies the interrupt pending bit to be checked.
* This parameter can be one of the following values:
* - UART_IT_OverrunError: Overrun Error interrupt
* - UART_IT_BreakError: Break Error interrupt
* - UART_IT_ParityError: Parity Error interrupt
* - UART_IT_FrameError: Frame Error interrupt
* - UART_IT_ReceiveTimeOut: Receive Time Out interrupt
* - UART_IT_Transmit: Transmit interrupt
* - UART_IT_Receive: Receive interrupt
* - UART_IT_DSR: DSR interrupt
* - UART_IT_DCD: DCD interrupt
* - UART_IT_CTS: CTS interrupt
* - UART_IT_RI: RI interrupt
* Output : None
* Return : The new state of UART_IT (SET or RESET).
*******************************************************************************/
ITStatus UART_GetITStatus(UART_TypeDef* UARTx, u16 UART_IT)
{
if((UARTx->MIS & UART_IT) != RESET)
{
return SET;
}
else
{
return RESET;
}
}
/*******************************************************************************
* Function Name : UART_ClearITPendingBit
* Description : Clears the UARTx's interrupt pending bits.
* Input : - UARTx: where x can be 0,1or 2 to select the UART peripheral.
* - UART_IT: specifies the interrupt pending bit to clear.
* This parameter can be:
* - UART_IT_OverrunError: Overrun Error interrupt
* - UART_IT_BreakError: Break Error interrupt
* - UART_IT_ParityError: Parity Error interrupt
* - UART_IT_FrameError: Frame Error interrupt
* - UART_IT_ReceiveTimeOut: Receive Time Out interrupt
* - UART_IT_Transmit: Transmit interrupt
* - UART_IT_Receive: Receive interrupt
* - UART_IT_DSR: DSR interrupt
* - UART_IT_DCD: DCD interrupt
* - UART_IT_CTS: CTS interrupt
* - UART_IT_RI: RI interrupt
* Output : None
* Return : None
*******************************************************************************/
void UART_ClearITPendingBit(UART_TypeDef* UARTx, u16 UART_IT)
{
/* Clear the specified interrupt */
UARTx->ICR &= UART_IT;
}
/*******************************************************************************
* Function Name : UART_IrDALowPowerConfig
* Description : Sets the IrDA low power mode
* Input : - IrDAx: where x can be 0,1 or 2 to select the UART/IrDA peripheral.
* - NewState: new state of the UARTIrDA peripheral.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void UART_IrDALowPowerConfig(u8 IrDAx, FunctionalState NewState)
{
UART_TypeDef* UARTx = UART0;
switch(IrDAx)
{
case IrDA0: UARTx = UART0;
break;
case IrDA1: UARTx = UART1;
break;
case IrDA2: UARTx = UART2;
break;
}
if (NewState == ENABLE)
{
UARTx->CR |= IrDA_LowPower_Enable_Mask;
}
else
{
UARTx->CR &= IrDA_LowPower_Disable_Mask;
}
}
/*******************************************************************************
* Function Name : UART_IrDASetCounter
* Description : Sets the IrDA counter divisor value.
* Input : - UARTx: where x can be 0,1 or 2 to select the UART/IrDA peripheral.
* - IrDA_Counter: IrDA counter divisor new value n low power mode(Hz).
* Output : None
* Return : None
*******************************************************************************/
void UART_IrDASetCounter(u8 IrDAx, u32 IrDA_Counter)
{
UART_TypeDef* UARTx = UART0;
u32 APBClock;
switch(IrDAx)
{
case IrDA0: UARTx = UART0;
break;
case IrDA1: UARTx = UART1;
break;
case IrDA2: UARTx = UART2;
break;
}
/* Get the APB frequency */
APBClock = (SCU_GetPCLKFreqValue())*1000;
/* Determine the Counter Divisor part */
UARTx->ILPR = (((APBClock*10) / ( IrDA_Counter)) + 5 )/10;
}
/*******************************************************************************
* Function Name : UART_IrDACmd
* Description : Enables or disables the UARTx's IrDA interface.
* Input : - IrDAx: where x can be 0,1 or 2 to select the UART/IrDA peripheral
* - NewState: new state of the UARTx peripheral.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void UART_IrDACmd(u8 IrDAx, FunctionalState NewState)
{
UART_TypeDef* UARTx = UART0;
switch(IrDAx)
{
case IrDA0: UARTx = UART0;
break;
case IrDA1: UARTx = UART1;
break;
case IrDA2: UARTx = UART2;
break;
}
if(NewState == ENABLE)
{
/* Enable the IrDA mode of the specified UART */
UARTx->CR |= UART_IrDA_Enable_Mask;
}
else
{
/* Disable the IrDA mode of the specified UART */
UARTx->CR &= UART_IrDA_Disable_Mask;
}
}
/*******************************************************************************
* Function Name : UART_SendData
* Description : Transmits signle Byte of data through the UARTx peripheral.
* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral.
* - Data: the byte to transmit
* Output : None
* Return : None
*******************************************************************************/
void UART_SendData(UART_TypeDef* UARTx, u8 Data)
{
/* Transmit one byte */
UARTx->DR = Data;
}
/*******************************************************************************
* Function Name : UART_ReceiveData
* Description : Returns the most recent received Byte by the UARTx peripheral.
* Input : UARTx: where x can be 0,1 or 2 to select the UART peripheral.
* Output : None
* Return : The received data
*******************************************************************************/
u8 UART_ReceiveData(UART_TypeDef* UARTx)
{
/* Receive one byte */
return ((u8)UARTx->DR);
}
/*******************************************************************************
* Function Name : UART_SendBreak
* Description : Transmits break characters.
* Input : UARTx: where x can be 0,1 or 2 to select the UART peripheral.
* Output : None
* Return : None
*******************************************************************************/
void UART_SendBreak(UART_TypeDef* UARTx)
{
/* Send break characters */
UARTx->LCR |= UART_BreakChar_Mask;
}
/*******************************************************************************
* Function Name : UART_RTSConfig
* Description : Sets or Resets the RTS signal
* Input : - LevelState: new state of the RTS signal for UART0 only.
* This parameter can be: LowLevel or HighLevel
* Output : None
* Return : None
*******************************************************************************/
void UART_RTSConfig(UART_LevelTypeDef LevelState)
{
if(LevelState == LowLevel)
{
UART0->CR |= UART_RTS_LowLevel_Mask;
}
else
{
UART0->CR &= UART_RTS_HighLevel_Mask;
}
}
/*******************************************************************************
* Function Name : UART_DTRConfig
* Description : Sets or Resets the DTR signal for UART0 only
* Input : - LevelState: new state of the DTR signal.
* This parameter can be: LowLevel or HighLevel
* Output : None
* Return : None
*******************************************************************************/
void UART_DTRConfig(UART_LevelTypeDef LevelState)
{
if(LevelState == LowLevel)
{
UART0->CR |= UART_DTR_LowLevel_Mask;
}
else
{
UART0->CR &= UART_DTR_HighLevel_Mask;
}
}
/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/

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/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
* File Name : 91x_uart.h
* Author : MCD Application Team
* Date First Issued : 05/18/2006 : Version 1.0
* Description : This file contains all the functions prototypes for the
* UART software library.
********************************************************************************
* History:
* 05/24/2006 : Version 1.1
* 05/18/2006 : Version 1.0
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __91x_UART_H
#define __91x_UART_H
/* Includes ------------------------------------------------------------------*/
#include <91x_map.h>
/* Exported types ------------------------------------------------------------*/
/* UART FIFO Level enumeration */
typedef enum
{
UART_FIFOLevel_1_8 = 0x0000, /* FIFO size 16 bytes, FIFO level 2 bytes */
UART_FIFOLevel_1_4 = 0x0001, /* FIFO size 16 bytes, FIFO level 4 bytes */
UART_FIFOLevel_1_2 = 0x0002, /* FIFO size 16 bytes, FIFO level 8 bytes */
UART_FIFOLevel_3_4 = 0x0003, /* FIFO size 16 bytes, FIFO level 12 bytes */
UART_FIFOLevel_7_8 = 0x0004 /* FIFO size 16 bytes, FIFO level 14 bytes */
}UART_FIFOLevel;
/* UART Init Structure definition */
typedef struct
{
u16 UART_WordLength;
u16 UART_StopBits;
u16 UART_Parity;
u32 UART_BaudRate;
u16 UART_HardwareFlowControl;
u16 UART_Mode;
u16 UART_FIFO;
UART_FIFOLevel UART_TxFIFOLevel;
UART_FIFOLevel UART_RxFIFOLevel;
}UART_InitTypeDef;
/* UART RTS enumeration */
typedef enum
{
LowLevel = 0,
HighLevel
}UART_LevelTypeDef;
/* Exported constants --------------------------------------------------------*/
/* UART Data Length */
#define UART_WordLength_5D 0x0000 /* 5 bits Data */
#define UART_WordLength_6D 0x0020 /* 6 bits Data */
#define UART_WordLength_7D 0x0040 /* 7 bits Data */
#define UART_WordLength_8D 0x0060 /* 8 bits Data */
/* UART Stop Bits */
#define UART_StopBits_1 0xFFF7 /* Disable two stop bit is transmitted
at the end of frame */
#define UART_StopBits_2 0x0008 /* Enable Two stop bits are transmitted
at the end of frame */
/* UART Parity */
#define UART_Parity_No 0x0000 /* Parity Disable */
#define UART_Parity_Even 0x0006 /* Even Parity */
#define UART_Parity_Odd 0x0002 /* Odd Parity */
#define UART_Parity_OddStick 0x0082 /* 1 is transmitted as bit parity */
#define UART_Parity_EvenStick 0x0086 /* 0 is transmitted as bit parity */
/* UART Hardware Flow Control */
#define UART_HardwareFlowControl_None 0x0000 /* HFC Disable */
#define UART_HardwareFlowControl_RTS 0x4000 /* RTS Enable */
#define UART_HardwareFlowControl_CTS 0x8000 /* CTS Enable */
#define UART_HardwareFlowControl_RTS_CTS 0xC000 /* CTS and RTS Enable */
/* UART Mode */
#define UART_Mode_Rx 0x0200 /* UART Rx Enabled */
#define UART_Mode_Tx 0x0100 /* UART Tx Enbled */
#define UART_Mode_Tx_Rx 0x0300 /* UART Tx and Rx Enabled */
/* UART FIFO */
#define UART_FIFO_Disable 0xFFEF /* FIFOs Disable */
#define UART_FIFO_Enable 0x0010 /* FIFOs Enable */
/* UART Interrupt definition */
#define UART_IT_OverrunError 0x0400 /* Overrun Error interrupt mask */
#define UART_IT_BreakError 0x0200 /* Break Error interrupt mask */
#define UART_IT_ParityError 0x0100 /* Parity Error interrupt mask */
#define UART_IT_FrameError 0x0080 /* Frame Error interrupt mask */
#define UART_IT_ReceiveTimeOut 0x0040 /* Receive Time Out interrupt mask */
#define UART_IT_Transmit 0x0020 /* Transmit interrupt mask */
#define UART_IT_Receive 0x0010 /* Receive interrupt mask */
#define UART_IT_DSR 0x0008 /* DSR interrupt mask */
#define UART_IT_DCD 0x0004 /* DCD interrupt mask */
#define UART_IT_CTS 0x0002 /* CTS interrupt mask */
#define UART_IT_RI 0x0001 /* RI interrupt mask */
/* UART DMA On Error */
#define UART_DMAOnError_Enable 0xFFFB /* DMA receive request enabled
when the UART error interrupt
is asserted. */
#define UART_DMAOnError_Disable 0x0004 /* DMA receive request disabled
when the UART error interrupt
is asserted. */
/* UART DMA Request */
#define UART_DMAReq_Tx 0x02 /* Transmit DMA Enable */
#define UART_DMAReq_Rx 0x01 /* Receive DMA Enable */
/* UART FLAG */
#define UART_FLAG_OverrunError 0x23 /* Overrun error flag */
#define UART_FLAG_Break 0x22 /* break error flag */
#define UART_FLAG_ParityError 0x21 /* parity error flag */
#define UART_FLAG_FrameError 0x20 /* frame error flag */
#define UART_FLAG_RI 0x48 /* RI flag */
#define UART_FLAG_TxFIFOEmpty 0x47 /* Transmit FIFO Empty flag */
#define UART_FLAG_RxFIFOFull 0x46 /* Receive FIFO Full flag */
#define UART_FLAG_TxFIFOFull 0x45 /* Transmit FIFO Full flag */
#define UART_FLAG_RxFIFOEmpty 0x44 /* Receive FIFO Empty flag */
#define UART_FLAG_Busy 0x43 /* UART Busy flag */
#define UART_FLAG_DCD 0x42 /* DCD flag */
#define UART_FLAG_DSR 0x41 /* DSR flag */
#define UART_FLAG_CTS 0x40 /* CTS flag */
#define UART_RawIT_OverrunError 0x6A /* Overrun Error Raw IT flag */
#define UART_RawIT_BreakError 0x69 /* Break Error Raw IT flag */
#define UART_RawIT_ParityError 0x68 /* Parity Error Raw IT flag */
#define UART_RawIT_FrameError 0x67 /* Frame Error Raw IT flag */
#define UART_RawIT_ReceiveTimeOut 0x66 /* ReceiveTimeOut Raw IT flag */
#define UART_RawIT_Transmit 0x65 /* Transmit Raw IT flag */
#define UART_RawIT_Receive 0x64 /* Receive Raw IT flag */
#define UART_RawIT_DSR 0x63 /* DSR Raw IT flag */
#define UART_RawIT_DCD 0x62 /* DCD Raw IT flag */
#define UART_RawIT_CTS 0x61 /* CTS Raw IT flag */
#define UART_RawIT_RI 0x60 /* RI Raw IT flag */
/*IrDAx select*/
#define IrDA0 0x01 /*IrDA0 select*/
#define IrDA1 0x02 /*IrDA0 select*/
#define IrDA2 0x03 /*IrDA0 select*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void UART_DeInit(UART_TypeDef* UARTx);
void UART_Init(UART_TypeDef* UARTx, UART_InitTypeDef* UART_InitStruct);
void UART_StructInit(UART_InitTypeDef* UART_InitStruct);
void UART_Cmd(UART_TypeDef* UARTx, FunctionalState NewState);
void UART_ITConfig(UART_TypeDef* UARTx, u16 UART_IT, FunctionalState NewState);
void UART_DMAConfig(UART_TypeDef* UARTx, u16 UART_DMAOnError);
void UART_DMACmd(UART_TypeDef* UARTx, u8 UART_DMAReq, FunctionalState NewState);
void UART_LoopBackConfig(UART_TypeDef* UARTx, FunctionalState NewState);
FlagStatus UART_GetFlagStatus(UART_TypeDef* UARTx, u16 UART_FLAG);
void UART_ClearFlag(UART_TypeDef* UARTx);
void UART_ClearITPendingBit(UART_TypeDef* UARTx, u16 UART_IT);
void UART_IrDALowPowerConfig(u8 IrDAx, FunctionalState NewState);
void UART_IrDACmd(u8 IrDAx, FunctionalState NewState);
void UART_IrDASetCounter(u8 IrDAx, u32 IrDA_Counter);
void UART_SendData(UART_TypeDef* UARTx, u8 Data);
u8 UART_ReceiveData(UART_TypeDef* UARTx);
void UART_SendBreak(UART_TypeDef* UARTx);
void UART_DTRConfig(UART_LevelTypeDef LevelState);
void UART_RTSConfig(UART_LevelTypeDef LevelState);
ITStatus UART_GetITStatus(UART_TypeDef* UARTx, u16 UART_IT);
#endif /* __91x_UART_H */
/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/

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# Configuration file for the STR9 backend
cpumode = ARGUMENTS.get( 'cpumode', 'arm' ).lower()
specific_files = "startup912.s startup_generic.s platform.c 91x_scu.c 91x_fmi.c 91x_gpio.c 91x_uart.c 91x_tim.c"
# Check CPU
if cputype == 'str912fw44':
ldscript = "str912fw44.lds"
else:
print "Invalid STR9 CPU %s", samtype
sys.exit( -1 )
# Check CPU mode
if cpumode == 'arm':
modeflag = ''
elif cpumode == 'thumb':
modeflag = '-mthumb'
else:
print "Invalid CPU mode %s", cpumode
sys.exit( -1 )
# Prepend with path
specific_files = " ".join( [ "src/platform/%s/%s" % ( platform, f ) for f in specific_files.split() ] )
ldscript = "src/platform/%s/%s" % ( platform, ldscript )
# Toolset data
tools[ 'str9' ] = {}
tools[ 'str9' ][ 'cccom' ] = "arm-elf-gcc -mcpu=arm966e-s -mfpu=fpa %s %s %s -ffunction-sections -fdata-sections %s -Wall -c $SOURCE -o $TARGET" % ( opt, local_include, modeflag, cdefs )
tools[ 'str9' ][ 'linkcom' ] = "arm-elf-gcc -mcpu=arm966e-s -mfpu=fpa -nostartfiles -nostdlib %s -T %s -Wl,--gc-sections -Wl,-e,_startup -Wl,--allow-multiple-definition -o $TARGET $SOURCES %s -lc -lgcc -lm" % ( modeflag, ldscript, local_libs )
tools[ 'str9' ][ 'ascom' ] = "arm-elf-gcc -x assembler-with-cpp %s -mcpu=arm966e-s -mfpu=fpa %s %s -Wall -c $SOURCE -o $TARGET" % ( local_include, modeflag, cdefs )
# Programming function for LPC2888
def progfunc_str9( target, source, env ):
outname = output + ".elf"
os.system( "arm-elf-size %s" % outname )
print "Generating binary image..."
os.system( "arm-elf-objcopy -O binary %s %s.bin" % ( outname, output ) )
tools[ 'str9' ][ 'progfunc' ] = progfunc_str9

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/********************************************************************
* Project: STR9-comStick GNU (UART)
* File: main.c
*
* System: ARM9TDMI 32 Bit (STR912FW44X)
* Compiler: GCC 4.0.3
*
* Date: 2006-12-20
* Author: Applications@Hitex.de
*
* Rights: Hitex Development Tools GmbH
* Greschbachstr. 12
* D-76229 Karlsruhe
********************************************************************
* Description:
*
* This file is part of the GNU Example chain
* The code is bassed on usage of the STmicro library functions
* This is a small implementation of UART1 feature echoing external input
* The application runs in ARM mode with high optimization level.
*
********************************************************************
* History:
*
* Revision 1.0 2006/12/20 Gn
* Initial revision
********************************************************************
* This is a preliminary version.
*
* WARRANTY: HITEX warrants that the media on which the SOFTWARE is
* furnished is free from defects in materials and workmanship under
* normal use and service for a period of ninety (90) days. HITEX entire
* liability and your exclusive remedy shall be the replacement of the
* SOFTWARE if the media is defective. This Warranty is void if failure
* of the media resulted from unauthorized modification, accident, abuse,
* or misapplication.
*
* DISCLAIMER: OTHER THAN THE ABOVE WARRANTY, THE SOFTWARE IS FURNISHED
* "AS IS" WITHOUT WARRANTY OF ANY KIND. HITEX DISCLAIMS ALL OTHER WARRANTIES,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*
* NEITHER HITEX NOR ITS AFFILIATES SHALL BE LIABLE FOR ANY DAMAGES ARISING
* OUT OF THE USE OF OR INABILITY TO USE THE SOFTWARE, INCLUDING DAMAGES FOR
* LOSS OF PROFITS, BUSINESS INTERRUPTION, OR ANY SPECIAL, INCIDENTAL, INDIRECT
* OR CONSEQUENTIAL DAMAGES EVEN IF HITEX HAS BEEN ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGES.
********************************************************************/
#include "defines.h"
#define global extern /* to declare external variables and functions */
#include "91x_lib.h"
#include "main.h"
#define GPIO_Alt1 0x01
#define TxBufferSize (countof(TxBuffer) - 1)
#define RxBufferSize 0xFF
/* Private macro -------------------------------------------------------------*/
#define countof(a) (sizeof(a) / sizeof(*(a)))
/* Private variables ---------------------------------------------------------*/
UART_InitTypeDef UART_InitStructure;
u8 TxBuffer[] = "UART1 - 1,8,N,1@115.2k communication without flow control\n\r";
u8 RxBuffer[RxBufferSize];
u8 NbrOfDataToTransfer = TxBufferSize;
u8 TxCounter = 0;
u8 RxCounter = 0;
GPIO_InitTypeDef GPIO_InitStructure;
TIM_InitTypeDef TIM_InitStructure;
/* Private function prototypes -----------------------------------------------*/
void SCU_Configuration(void);
void GPIO_Configuration(void);
void UART1_Configuration(void);
static void Delay(u32 nCount);
int main (void)
{
/* Configure the system clocks */
SCU_Configuration();
/* Configure the GPIOs */
GPIO_Configuration();
/* Configure and start the UART1 */
UART1_Configuration();
/* endless loop */
while (1)
{
{
if((UART_GetFlagStatus(UART1, UART_FLAG_RxFIFOEmpty) != SET)&&(RxCounter < RxBufferSize))
{
RxBuffer[0] = UART1->DR;
UART_SendData(UART1, RxBuffer[0]);
}
}
/* Turn OFF leds connected to P9.0, P9.1 pins */
GPIO_WriteBit(GPIO8, GPIO_Pin_0, Bit_SET);
/* Insert delay */
Delay(0x1FFFF);
/* Turn ON leds connected to P9.0, P9.1 pins */
GPIO_WriteBit(GPIO8, GPIO_Pin_0, Bit_RESET);
/* Insert delay */
Delay(0x1FFFF);
}
}
void SCU_Configuration(void)
{
SCU_MCLKSourceConfig(SCU_MCLK_OSC);
SCU_PLLFactorsConfig(192,25,2); /* PLL = 96 MHz */
SCU_PLLCmd(ENABLE); /* PLL Enabled */
SCU_MCLKSourceConfig(SCU_MCLK_PLL); /* MCLK = PLL */
FMI_BankRemapConfig(4, 2, 0, 0x80000); /* Set Flash banks size & address */
FMI_Config(FMI_READ_WAIT_STATE_2, FMI_WRITE_WAIT_STATE_0, FMI_PWD_ENABLE,\
FMI_LVD_ENABLE, FMI_FREQ_HIGH); /* FMI Waite States */
/* Enable VIC clock */
SCU_AHBPeriphClockConfig(__VIC, ENABLE);
SCU_AHBPeriphReset(__VIC, DISABLE);
/* Set the PCLK Clock to MCLK/2 */
SCU_PCLKDivisorConfig(SCU_PCLK_Div1);
/* Enable the UART0 Clock */
SCU_APBPeriphClockConfig(__UART1, ENABLE);
/* Enable the clock for TIM0 and TIM1 */
SCU_APBPeriphClockConfig(__TIM01, ENABLE);
SCU_APBPeriphReset(__TIM01, DISABLE);
SCU_APBPeriphClockConfig(__TIM23, ENABLE);
SCU_APBPeriphReset(__TIM23, DISABLE);
/* Enable the GPIO3 Clock */
SCU_APBPeriphClockConfig(__GPIO3, ENABLE);
SCU_APBPeriphClockConfig(__GPIO4, ENABLE); /* Enable the clock for the GPIO4 */
/* Enable the __GPIO8 */
SCU_APBPeriphClockConfig(__GPIO8 ,ENABLE);
/* Enable the __GPIO9 */
SCU_APBPeriphClockConfig(__GPIO9 ,ENABLE);
}
/* GPIO Configuration --------------------------------------------------------*/
void GPIO_Configuration(void)
{
GPIO_DeInit(GPIO3);
GPIO_DeInit(GPIO4); /* GPIO4 Deinitialization */
GPIO_DeInit(GPIO9);
/* IOs */
GPIO_InitStructure.GPIO_Direction = GPIO_PinOutput;
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_All;
GPIO_InitStructure.GPIO_Type = GPIO_Type_PushPull ;
GPIO_Init (GPIO4, &GPIO_InitStructure);
/* onboard LED */
GPIO_InitStructure.GPIO_Direction = GPIO_PinOutput;
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;
GPIO_InitStructure.GPIO_Type = GPIO_Type_PushPull ;
GPIO_Init (GPIO9, &GPIO_InitStructure);
GPIO_WriteBit(GPIO9, GPIO_Pin_0, Bit_RESET);
/* configure UART1_Rx pin GPIO3.2*/
GPIO_InitStructure.GPIO_Direction = GPIO_PinInput;
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
GPIO_InitStructure.GPIO_Type = GPIO_Type_PushPull ;
GPIO_InitStructure.GPIO_IPConnected = GPIO_IPConnected_Enable;
GPIO_InitStructure.GPIO_Alternate = GPIO_InputAlt1 ;
GPIO_Init (GPIO3, &GPIO_InitStructure);
/*Gonfigure UART1_Tx pin GPIO3.3*/
GPIO_InitStructure.GPIO_Direction = GPIO_PinInput;
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3;
GPIO_InitStructure.GPIO_Type = GPIO_Type_PushPull ;
GPIO_InitStructure.GPIO_Alternate = GPIO_OutputAlt2 ;
GPIO_Init (GPIO3, &GPIO_InitStructure);
}
/* UART1 configuration -------------------------------------------------------*/
void UART1_Configuration(void)
{
/* UART1 configured as follow:
- Word Length = 8 Bits
- One Stop Bit
- No parity
- BaudRate = 115200 baud
- no Hardware flow control enabled (RTS and CTS signals)
- Receive and transmit enabled
- Receive and transmit FIFOs are enabled
- Transmit and Receive FIFOs levels have 8 bytes depth
*/
UART_InitStructure.UART_WordLength = UART_WordLength_8D;
UART_InitStructure.UART_StopBits = UART_StopBits_1;
UART_InitStructure.UART_Parity = UART_Parity_No ;
UART_InitStructure.UART_BaudRate = 115200;
UART_InitStructure.UART_HardwareFlowControl = UART_HardwareFlowControl_None;
UART_InitStructure.UART_Mode = UART_Mode_Tx_Rx;
UART_InitStructure.UART_FIFO = UART_FIFO_Enable;//UART_FIFO_Enable;
UART_InitStructure.UART_TxFIFOLevel = UART_FIFOLevel_1_2; /* FIFO size 16 bytes, FIFO level 8 bytes */
UART_InitStructure.UART_RxFIFOLevel = UART_FIFOLevel_1_2; /* FIFO size 16 bytes, FIFO level 8 bytes */
UART_DeInit(UART1);
UART_Init(UART1, &UART_InitStructure);
/* Enable the UART0 */
UART_Cmd(UART1, ENABLE);
while(NbrOfDataToTransfer--)
{
UART_SendData(UART1, TxBuffer[TxCounter++]);
while(UART_GetFlagStatus(UART1, UART_FLAG_TxFIFOFull) != RESET);
}
}
/*******************************************************************************
* Function Name : Delay
* Description : Inserts a delay time.
* Input : nCount: specifies the delay time length.
*******************************************************************************/
static void Delay(u32 nCount)
{
u32 j = 0;
for(j = nCount; j != 0; j--);
}
/************************************** EOF *********************************/

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// Platform-dependent functions
#include "platform.h"
#include "type.h"
#include "devman.h"
#include "genstd.h"
#include "stacks.h"
#include <reent.h>
#include <errno.h>
#include <string.h>
#include <ctype.h>
#include <stdio.h>
#include "91x_scu.h"
#include "91x_fmi.h"
#include "91x_gpio.h"
#include "91x_uart.h"
#include "91x_tim.h"
// We define here the UART used by this porting layer
#define STR9_UART UART1
// *****************************************************************************
// std functions
static void uart_send( int fd, char c )
{
fd = fd;
platform_uart_send( 0, c );
}
static int uart_recv()
{
return platform_uart_recv( 0, 0, PLATFORM_UART_INFINITE_TIMEOUT );
}
// ****************************************************************************
// Platform initialization
static const GPIO_TypeDef* port_data[] = { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7, GPIO8, GPIO9 };
static const TIM_TypeDef* timer_data[] = { TIM0, TIM1, TIM2, TIM3 };
static void platform_config_scu()
{
FMI_BankRemapConfig(4, 2, 0, 0x80000); /* Set Flash banks size & address */
FMI_Config(FMI_READ_WAIT_STATE_2, FMI_WRITE_WAIT_STATE_0, FMI_PWD_ENABLE,
FMI_LVD_ENABLE, FMI_FREQ_HIGH); /* FMI Waite States */
volatile u16 i = 0xFFFF;
while (i-- > 0);
// SCU initialization
SCU_MCLKSourceConfig(SCU_MCLK_OSC);
SCU_PLLFactorsConfig(192,25,2); /* PLL = 96 MHz */
SCU_PLLCmd(ENABLE); /* PLL Enabled */
SCU_MCLKSourceConfig(SCU_MCLK_PLL); /* MCLK = PLL */
/* Set the RCLK Clock divider to max speed*/
SCU_RCLKDivisorConfig(SCU_RCLK_Div1);
/* Set the PCLK Clock to MCLK/8 */
SCU_PCLKDivisorConfig(SCU_PCLK_Div8);
/* Set the HCLK Clock to MCLK/2 */
SCU_HCLKDivisorConfig(SCU_HCLK_Div2);
// Enable the UART clocks
SCU_APBPeriphClockConfig(__UART_ALL, ENABLE);
// Enable the timer clocks
SCU_APBPeriphClockConfig(__TIM01, ENABLE);
SCU_APBPeriphReset(__TIM01, DISABLE);
SCU_APBPeriphClockConfig(__TIM23, ENABLE);
SCU_APBPeriphReset(__TIM23, DISABLE);
// Enable the GPIO clocks
SCU_APBPeriphClockConfig(__GPIO_ALL, ENABLE);
}
int platform_init()
{
unsigned i;
TIM_InitTypeDef tim;
TIM_TypeDef* base;
// System configuration
platform_config_scu();
// PIO setup
for( i = 0; i < 10; i ++ )
GPIO_DeInit( ( GPIO_TypeDef* )port_data[ i ] );
// UART setup (only STR9_UART is used in this example)
platform_uart_setup( 0, 115200, 8, PLATFORM_UART_PARITY_NONE, PLATFORM_UART_STOPBITS_1 );
// Initialize timers
for( i = 0; i < 4; i ++ )
{
base = ( TIM_TypeDef* )timer_data[ i ];
TIM_DeInit( base );
TIM_StructInit( &tim );
tim.TIM_Clock_Source = TIM_CLK_APB;
tim.TIM_Prescaler = 255;
TIM_Init( base, &tim );
TIM_CounterCmd( base, TIM_START );
}
// Set the send/recv functions
std_set_send_func( uart_send );
std_set_get_func( uart_recv );
return PLATFORM_OK;
}
// ****************************************************************************
// PIO functions
int platform_pio_has_port( unsigned port )
{
return port < 10;
}
const char* platform_pio_get_prefix( unsigned port )
{
static char c[ 3 ];
sprintf( c, "P%d", port );
return c;
}
int platform_pio_has_pin( unsigned port, unsigned pin )
{
return port < 10 && pin < 8;
}
pio_type platform_pio_op( unsigned port, pio_type pinmask, int op )
{
GPIO_TypeDef* base = ( GPIO_TypeDef* )port_data[ port ];
GPIO_InitTypeDef data;
pio_type retval = 0;
GPIO_StructInit( &data );
switch( op )
{
case PLATFORM_IO_PORT_SET_VALUE:
GPIO_Write( base, ( u8 )pinmask );
break;
case PLATFORM_IO_PIN_SET:
GPIO_WriteBit( base, ( u8 )pinmask, Bit_SET );
break;
case PLATFORM_IO_PIN_CLEAR:
GPIO_WriteBit( base, ( u8 )pinmask, Bit_RESET );
break;
case PLATFORM_IO_PORT_DIR_OUTPUT:
pinmask = 0xFF;
case PLATFORM_IO_PIN_DIR_OUTPUT:
data.GPIO_Direction = GPIO_PinOutput;
data.GPIO_Type = GPIO_Type_PushPull ;
data.GPIO_Alternate=GPIO_OutputAlt1;
data.GPIO_Pin = ( u8 )pinmask;
GPIO_Init(base, &data);
break;
case PLATFORM_IO_PORT_DIR_INPUT:
pinmask = 0xFF;
case PLATFORM_IO_PIN_DIR_INPUT:
data.GPIO_Pin = ( u8 )pinmask;
GPIO_Init(base, &data);
break;
case PLATFORM_IO_PORT_GET_VALUE:
retval = GPIO_Read( base );
break;
case PLATFORM_IO_PIN_GET:
retval = GPIO_ReadBit( base, ( u8 )pinmask );
break;
}
return retval;
}
// ****************************************************************************
// UART
int platform_uart_exists( unsigned id )
{
return id < 1;
}
u32 platform_uart_setup( unsigned id, u32 baud, int databits, int parity, int stopbits )
{
UART_InitTypeDef UART_InitStructure;
GPIO_InitTypeDef GPIO_InitStructure;
id = id;
// First configure GPIO
// RX: GPIO3.2
GPIO_InitStructure.GPIO_Direction = GPIO_PinInput;
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
GPIO_InitStructure.GPIO_Type = GPIO_Type_PushPull ;
GPIO_InitStructure.GPIO_IPConnected = GPIO_IPConnected_Enable;
GPIO_InitStructure.GPIO_Alternate = GPIO_InputAlt1 ;
GPIO_Init (GPIO3, &GPIO_InitStructure);
// TX: GPIO3.3
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3;
GPIO_InitStructure.GPIO_Alternate = GPIO_OutputAlt2 ;
GPIO_Init (GPIO3, &GPIO_InitStructure);
// Then configure UART parameters
switch( databits )
{
case 5:
UART_InitStructure.UART_WordLength = UART_WordLength_5D;
break;
case 6:
UART_InitStructure.UART_WordLength = UART_WordLength_6D;
break;
case 7:
UART_InitStructure.UART_WordLength = UART_WordLength_7D;
break;
case 8:
UART_InitStructure.UART_WordLength = UART_WordLength_8D;
break;
}
if( stopbits == PLATFORM_UART_STOPBITS_1 )
UART_InitStructure.UART_StopBits = UART_StopBits_1;
else
UART_InitStructure.UART_StopBits = UART_StopBits_2;
if( parity == PLATFORM_UART_PARITY_EVEN )
UART_InitStructure.UART_Parity = UART_Parity_Even;
else if( parity == PLATFORM_UART_PARITY_ODD )
UART_InitStructure.UART_Parity = UART_Parity_Odd;
else
UART_InitStructure.UART_Parity = UART_Parity_No;
UART_InitStructure.UART_BaudRate = baud;
UART_InitStructure.UART_HardwareFlowControl = UART_HardwareFlowControl_None;
UART_InitStructure.UART_Mode = UART_Mode_Tx_Rx;
UART_InitStructure.UART_FIFO = UART_FIFO_Enable; //UART_FIFO_Enable;
UART_InitStructure.UART_TxFIFOLevel = UART_FIFOLevel_1_2; /* FIFO size 16 bytes, FIFO level 8 bytes */
UART_InitStructure.UART_RxFIFOLevel = UART_FIFOLevel_1_2; /* FIFO size 16 bytes, FIFO level 8 bytes */
UART_DeInit(STR9_UART);
UART_Init(STR9_UART, &UART_InitStructure);
UART_Cmd(STR9_UART, ENABLE);
return baud;
}
void platform_uart_send( unsigned id, u8 data )
{
id = id;
while( UART_GetFlagStatus(STR9_UART, UART_FLAG_TxFIFOFull) == SET );
UART_SendData( STR9_UART, data );
}
int platform_uart_recv( unsigned id, unsigned timer_id, int timeout )
{
timer_data_type tmr_start, tmr_crt;
int res;
if( timeout == 0 )
{
// Return data only if already available
if( UART_GetFlagStatus(STR9_UART, UART_FLAG_RxFIFOEmpty) != SET )
return UART_ReceiveData( STR9_UART );
else
return -1;
}
else if( timeout == PLATFORM_UART_INFINITE_TIMEOUT )
{
// Wait for data
while( UART_GetFlagStatus(STR9_UART, UART_FLAG_RxFIFOEmpty) == SET );
return UART_ReceiveData( STR9_UART );
}
else
{
// Receive char with the specified timeout
tmr_start = platform_timer_op( timer_id, PLATFORM_TIMER_OP_START,0 );
while( 1 )
{
if( UART_GetFlagStatus(STR9_UART, UART_FLAG_RxFIFOEmpty) != SET )
{
res = UART_ReceiveData( STR9_UART );
break;
}
else
res = -1;
tmr_crt = platform_timer_op( timer_id, PLATFORM_TIMER_OP_READ, 0 );
if( platform_timer_get_diff_us( timer_id, tmr_crt, tmr_start ) >= timeout )
break;
}
return res;
}
}
// ****************************************************************************
// Timer
int platform_timer_exists( unsigned id )
{
return id < 4;
}
// Helper: get timer clock
static u32 platform_timer_get_clock( unsigned id )
{
return ( SCU_GetPCLKFreqValue() * 1000 ) / ( TIM_GetPrescalerValue( ( TIM_TypeDef* )timer_data[ id ] ) + 1 );
}
// Helper: set timer clock
static u32 platform_timer_set_clock( unsigned id, u32 clock )
{
u32 baseclk = SCU_GetPCLKFreqValue() * 1000;
TIM_TypeDef* base = ( TIM_TypeDef* )timer_data[ id ];
u64 bestdiv;
bestdiv = ( ( u64 )baseclk << 16 ) / clock;
if( bestdiv & 0x8000 )
bestdiv += 0x10000;
bestdiv >>= 16;
if( bestdiv > 256 )
bestdiv = 256;
TIM_PrescalerConfig( base, bestdiv - 1 );
return baseclk / bestdiv;
}
void platform_timer_delay( unsigned id, u32 delay_us )
{
TIM_TypeDef* base = ( TIM_TypeDef* )timer_data[ id ];
u32 freq;
timer_data_type final;
freq = platform_timer_get_clock( id );
final = ( ( u64 )delay_us * freq ) / 1000000;
if( final > 2 )
final -= 2;
else
final = 0;
if( final > 0xFFFF )
final = 0xFFFF;
TIM_CounterCmd( base, TIM_STOP );
TIM_CounterCmd( base, TIM_CLEAR );
TIM_CounterCmd( base, TIM_START );
while( TIM_GetCounterValue( base ) >= 0xFFFC );
while( TIM_GetCounterValue( base ) < final );
}
u32 platform_timer_op( unsigned id, int op, u32 data )
{
u32 res = 0;
TIM_TypeDef* base = ( TIM_TypeDef* )timer_data[ id ];
switch( op )
{
case PLATFORM_TIMER_OP_START:
TIM_CounterCmd( base, TIM_STOP );
TIM_CounterCmd( base, TIM_CLEAR );
TIM_CounterCmd( base, TIM_START );
while( TIM_GetCounterValue( base ) >= 0xFFFC );
break;
case PLATFORM_TIMER_OP_READ:
res = TIM_GetCounterValue( base );
break;
case PLATFORM_TIMER_OP_GET_MAX_DELAY:
res = platform_timer_get_diff_us( id, 0, 0xFFFF );
break;
case PLATFORM_TIMER_OP_GET_MIN_DELAY:
res = platform_timer_get_diff_us( id, 0, 1 );
break;
case PLATFORM_TIMER_OP_SET_CLOCK:
res = platform_timer_set_clock( id, data );
break;
case PLATFORM_TIMER_OP_GET_CLOCK:
res = platform_timer_get_clock( id );
break;
}
return res;
}
u32 platform_timer_get_diff_us( unsigned id, timer_data_type end, timer_data_type start )
{
timer_data_type temp;
u32 freq;
freq = platform_timer_get_clock( id );
if( start < end )
{
temp = end;
end = start;
start = temp;
}
return ( ( u64 )( start - end ) * 1000000 ) / freq;
}
// ****************************************************************************
// Platform data functions
const char* platform_pd_get_name()
{
return "STR9";
}
const char* platform_pd_cpu_name()
{
return "STR912FW44X";
}
u32 platform_pd_get_cpu_frequency()
{
return SCU_GetMCLKFreqValue() * 1000;
}
// ****************************************************************************
// Allocator support
extern char end[];
void* platform_get_first_free_ram()
{
return ( void* )end;
}
#define SRAM_ORIGIN 0x40000000
#define SRAM_SIZE 0x18000
void* platform_get_last_free_ram()
{
return ( void* )( SRAM_ORIGIN + SRAM_SIZE - STACK_SIZE_TOTAL );
}

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// Auxiliary libraries that will be compiled for this platform
#ifndef __PLATFORM_LIBS_H__
#define __PLATFORM_LIBS_H__
#include "auxmods.h"
#define LUA_PLATFORM_LIBS\
{ AUXLIB_PIO, luaopen_pio},\
{ AUXLIB_TMR, luaopen_tmr },\
{ AUXLIB_PD, luaopen_pd },\
{ AUXLIB_UART, luaopen_uart }
#endif

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// Stack size definitions
#ifndef __STACKS_H__
#define __STACKS_H__
#define STACK_SIZE_USR 512
#define STACK_SIZE_IRQ 64
#define STACK_SIZE_TOTAL ( STACK_SIZE_USR + STACK_SIZE_IRQ )
#endif

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#*************************************************************************
# *** STR912 Startup Code For GNU Tools (executed after Reset) ***
#
# (C) Hitex (UK) Ltd. 2006
#
# Disclaimer: Whilst every effort has been made to ensure the correctness
# of this code, Hitex (UK) Ltd. cannot be held responsible for the consequences
# of its use. Users should therefore verify its operation before including it
# in any program.
#*************************************************************************
#
#
# ---------------------------------------------
# Include startup macros
# ---------------------------------------------
#include "stacks.h"
.include "startup_generic.s"
#
# Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs
#
.equ RAM_Size, 0x00018000 /* 96K */
.equ RAM_Base, 0x40000000
#*************************************************************************
# Control Startup Code Operation
#*************************************************************************
.equ SRAM_SETUP , 1 /* Enable setup of SRAM */
#*************************************************************************
# Hardware Definitions
#*************************************************************************
# Flash Memory Interface (FMI) definitions (Flash banks sizes and addresses)
.equ FMI_BASE , 0x54000000 /* FMI Base Address (non-buffered) */
.equ FMI_BBSR_OFS , 0x00 /* Boot Bank Size Register */
.equ FMI_NBBSR_OFS , 0x04 /* Non-boot Bank Size Register */
.equ FMI_BBADR_OFS , 0x0C /* Boot Bank Base Address Register #!!! Documentation page 30,*/
.equ FMI_NBBADR_OFS , 0x10 /* Non-boot Bank Base Address Register #!!! adresseses do not correspond*/
.equ FMI_CR_OFS , 0x18 /* Control Register */
.equ FMI_SR_OFS , 0x1C /* Status Register */
.equ FMI_CR_Val , 0x00000018
.equ FMI_BBSR_Val , 0x00000004
.equ FMI_BBADR_Val , 0x00000000
.equ FMI_NBBSR_Val , 0x00000002
.equ FMI_NBBADR_Val , 0x00080000
.equ FLASH_CFG_Val , 0x00001010
.equ FMI_SR_Val , 0x00000003 /* Clear status errors (register not in STR912 manual! */
# System Control Unit (SCU) definitions
.equ SCU_BASE , 0x5C002000 /* SCU Base Address (non-buffered) */
.equ SCU_CLKCNTR_OFS , 0x00 /* Clock Control register Offset */
.equ SCU_PLLCONF_OFS , 0x04 /* PLL Configuration register Offset */
.equ SCU_SYSTAT_OFS , 0x08 /* SCU status register offset */
.equ SCU_PCGR0_OFS , 0x14 /* Peripheral Clock Gating Register 0 Offset */
.equ SCU_PCGR1_OFS , 0x18 /* Peripheral Clock Gating Register 1 Offset */
.equ SCU_SCR0_OFS , 0x34 /* System Configuration Register 0 Offset */
.equ SCU_CLKCNTR_Val , 0x00030000 /* Use PLL, external memory ratio/2 */
.equ SCU_PLLCONF_Val , 0x000AC019
.equ SCU_PCGR0_Val , 0x000000DB /* Setup ext mem clock, EMI, SRAM, Prefetch Queue/Branch cache, FMI */
.equ SCU_PCGR1_Val , 0x00C40000 /* Setup GPIO8, 9 & 4 */
.equ SCU_SCR0_Val , 0x00000196 /* Disable Prefetch Queue and Branch cache, SRAM = 96kb */
.equ SCU_SYSSTAT_LOCK , 0x01 /* Check for PLL locked */
# APB Bridge 1 & 2 definitions (Peripherals)
.equ APB0_BUF_BASE , 0x48001802 /* APB Bridge 0 Buffered Base Address */
.equ APB0_NBUF_BASE , 0x58000000 /* APB Bridge 0 Non-buffered Base Address */
.equ APB1_BUF_BASE , 0x4C000000 /* APB Bridge 1 Buffered Base Address */
.equ APB1_NBUF_BASE , 0x5C000000 /* APB Bridge 1 Non-buffered Base Address */
#*************************************************************************
# Stack definitions
#*************************************************************************
.equ Top_Stack, RAM_Base + RAM_Size
# NOTE: Startup Code must be linked first at Address at which it expects to run.
#*************************************************************************
# STARTUP EXECUTABLE CODE
#*************************************************************************
.text
.arm
.extern main
.global _startup
_startup:
#*************************************************************************
# Exception Vectors
#*************************************************************************
Vectors:
LDR PC, Reset_Addr /* 0x0000 */
LDR PC, Undef_Addr /* 0x0004 */
LDR PC, SWI_Addr /* 0x0008 */
LDR PC, PAbt_Addr /* 0x000C */
LDR PC, DAbt_Addr /* 0x0010 */
NOP /* 0x0014 Reserved Vector */
LDR PC, [PC, #-0xFF0] /* 0x0018 wraps around address space to 0xFFFFFF030. Vector from VicVECAddr */
LDR PC, FIQ_Addr /* 0x001C FIQ has no VIC vector slot! */
#*************************************************************************
# Interrupt Vectors
#*************************************************************************
Reset_Addr: .word Hard_Reset /* CPU reset vector and entry point */
Undef_Addr: .word Undef_Handler
SWI_Addr: .word SWI_Handler
PAbt_Addr: .word PAbt_Handler
DAbt_Addr: .word DAbt_Handler
.word 0 /* Reserved Address */
IRQ_Addr: .word IRQ_Handler /* Does not get used due to "LDR PC, [PC, #-0xFF0]" above */
FIQ_Addr: .word FIQ_Handler
# Dummy Interrupt Vector Table (real service routines in INTERRUPT.C)
Undef_Handler: B Undef_Handler
SWI_Handler: B SWI_Handler
PAbt_Handler: B PAbt_Handler
DAbt_Handler: B DAbt_Handler
IRQ_Handler: B IRQ_Handler /* should never get here as IRQ is via VIC slot... */
FIQ_Handler: B FIQ_Handler
#*************************************************************************
# Reset Handler Entry Point
#*************************************************************************
Hard_Reset:
#*************************************************************************
# Setup SRAM Size
.IF SRAM_SETUP == 1
LDR R0, =SCU_BASE
LDR R1, =SCU_SCR0_Val
STR R1, [R0, #SCU_SCR0_OFS]
.ENDIF
#*************************************************************************
# Compiler Runtime Environment Setup
#*************************************************************************
# Note: R13 = SP
# Setup Stack for each mode
LDR R0, =Top_Stack
# Set up Interrupt Mode and set IRQ Mode Stack
msr CPSR_c, #Mode_IRQ|I_BIT|F_BIT
mov r13, r0
sub r0, r0, #STACK_SIZE_IRQ
# Set up User Mode and set User Mode Stack
msr CPSR_c, #Mode_USR /* Leave interrupts enabled in user mode */
mov r13, r0 /* Note: interrupts will not happen until VIC is enabled */
#*************************************************************************
# Initialise RAM For Compiler Variables
#*************************************************************************
copy_section2 data, _efixed, _srelocate, _erelocate
#*************************************************************************
# Clear .bss section
#*************************************************************************
clear_section bss, _szero, _ezero
#*************************************************************************
# Enter the C code
#*************************************************************************
# Jump to main()
ldr r0, =main
mov lr, pc
bx r0
forever:
B forever
#*************************************************************************
# END
#*************************************************************************
.end

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#*****************************************************************************
#*
#* Project: Generic include file for ARM startup
#* Filename: startup.inc
#* Date: 11.05.2004
#* Rights: Hitex Development Tools GmbH
#* Greschbachstr. 12
#* 76229 Karlsruhe
#*
#****************************************************************************
# *** Startup Code (executed after Reset) ***
# Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs
.equ Mode_USR, 0x10
.equ Mode_FIQ, 0x11
.equ Mode_IRQ, 0x12
.equ Mode_SVC, 0x13
.equ Mode_ABT, 0x17
.equ Mode_UND, 0x1B
.equ Mode_SYS, 0x1F
.equ T_BIT, 0x20 /* when T bit is set, thumb mode active */
.equ I_BIT, 0x80 /* when I bit is set, IRQ is disabled */
.equ F_BIT, 0x40 /* when F bit is set, FIQ is disabled */
# ---------------------------------------------
# macro definition for stack memory reservation
# ---------------------------------------------
# use this macro to setup the stack
.macro setup_stack label1, size, mode_bits
.lcomm __range_\label1, (\size - 1) * 4
.global \label1
.lcomm \label1, 4
ldr r0, adr_\label1
msr CPSR_c, \mode_bits
mov r13, r0
.endm
# use this macro to define the label for the setup_stack mcaro!
.macro stack_adr label1
adr_\label1:
.word \label1
.endm
# ---------------------------------------------
# copy section
# use this macro to copy a section
# parameters:
# - individual name, used to create labels
# - source pointer
# - destination pointer
# - source pointer + length > end address of source
# ---------------------------------------------
.macro copy_section sec_name, source, destination, source_end
ldr R1, =\source
ldr R2, =\destination
ldr R3, =\source_end
_cplp_\sec_name:
cmp R1, R3
ldrlo R0, [R1], #4
strlo R0, [R2], #4
blo _cplp_\sec_name
.endm
# ---------------------------------------------
# copy section 2
# use this macro to copy a section
# parameters:
# - individual name, used to create labels
# - source pointer
# - destination pointer
# - destination pointer + length > end address of destination
# ---------------------------------------------
.macro copy_section2 sec_name, source, destination, destination_end
ldr R1, =\source
ldr R2, =\destination
ldr R3, =\destination_end
_cplp_\sec_name:
cmp R2, R3
ldrlo R0, [R1], #4
strlo R0, [R2], #4
blo _cplp_\sec_name
.endm
# ---------------------------------------------
# clear section
# use this macro to clear bss sections
# ---------------------------------------------
.macro clear_section sec_name, source, source_end
mov R0, #0
ldr R1, =\source
ldr R2, =\source_end
_cllp_\sec_name:
cmp R1, R2
strlo R0, [R1], #4
blo _cllp_\sec_name
.endm
# ---------------------------------------------
# examples how to use the macros
# ---------------------------------------------
# Setup stacks for the operating modes
# ---------------------------------------------
# setup_stack UND_Stack, UND_Stack_Size, #Mode_UND|I_BIT|F_BIT
# setup_stack SVC_Stack, SVC_Stack_Size, #Mode_SVC|I_BIT|F_BIT
# setup_stack ABT_Stack, ABT_Stack_Size, #Mode_ABT|I_BIT|F_BIT
# setup_stack FIQ_Stack, FIQ_Stack_Size, #Mode_FIQ|I_BIT|F_BIT
# setup_stack IRQ_Stack, IRQ_Stack_Size, #Mode_IRQ|I_BIT|F_BIT
# setup_stack USR_Stack, USR_Stack_Size, #Mode_USR
# ---------------------------------------------
# copy sections
# ---------------------------------------------
# copy code into internal ram
# copy_section code, __code_start__, RAM_Base_Boot, __code_end__
# Relocate .data section (Copy from ROM to RAM)
# copy_section data, __data_start__, __data_start__+RAM_Base_Boot, __data_end__
# ---------------------------------------------
# Clear .bss section
# ---------------------------------------------
# Clear .bss section (Zero init)
# clear_section bss, __bss_start__, __bss_end__
# ---------------------------------------------
# startup delay
# use this macro if you are working with an debugger
# the startup delay avoid problems while
# the application start before the debug interface
# becomes controled by the debugger
# ---------------------------------------------
# a goodf choice for the delay value is
# cpu clock / 100 with ATMEL controllers
# cpu clock / 40 with Philips controllers
.macro StartupDelay delay_value
ldr R1, =\delay_value
ldr R2, =0
__StartDelay:
sub R1, R1, #1
cmp R1, R2
bhi __StartDelay
.endm
# ---------------------------------------------

47
src/platform/str9/str912fw44.lds Normal file
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OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
MEMORY
{
sram (W!RX) : ORIGIN = 0x40000000, LENGTH = 96k
flash (RX) : ORIGIN = 0x0, LENGTH = 512k
}
SECTIONS
{
.fixed :
{
. = ALIGN(4);
_sfixed = .;
*(.text .text.*)
*(.rodata .rodata.*)
*(.gnu.linkonce.t.*)
*(.glue_7)
*(.glue_7t)
*(.gcc_except_table)
*(.gnu.linkonce.r.*)
. = ALIGN(4);
_efixed = .;
PROVIDE(etext = .);
} >flash
.relocate : AT (_efixed)
{
. = ALIGN(4);
_srelocate = .;
*(.data .data.*)
*(.gnu.linkonce.d.*)
. = ALIGN(4);
_erelocate = .;
} >sram
.bss (NOLOAD) : {
_szero = .;
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
_ezero = .;
} >sram
end = .;
}

18
src/platform/str9/type.h Normal file
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#ifndef __TYPE_H__
#define __TYPE_H__
typedef unsigned char BYTE;
typedef unsigned short WORD;
typedef unsigned long DWORD;
typedef unsigned int BOOL;
typedef unsigned char u8;
typedef signed char s8;
typedef unsigned short u16;
typedef signed short s16;
typedef unsigned long u32;
typedef signed long s32;
typedef unsigned long long u64;
typedef signed long long s64;
#endif