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Merge pull request #158 from ramangopalan/master

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XMC4200 Hexagon kit: Import system files
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Bogdan Marinescu 2019-02-13 18:33:11 +02:00 committed by GitHub
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src/platform/xmc4000/XMC4200.h Normal file
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src/platform/xmc4000/startup_XMC4200.S Normal file
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/*********************************************************************************************************************
* @file startup_XMC4200.S
* @brief CMSIS Core Device Startup File for Infineon XMC4200 Device Series
* @version V1.0
* @date 01 June 2016
*
* @cond
*********************************************************************************************************************
* Copyright (c) 2012-2016, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
**************************** Change history ********************************
* V0.1,Sep, 13, 2012 ES : initial version
* V0.2,Oct, 12, 2012 PKB: C++ support
* V0.3,Jan, 26, 2013 PKB: Workaround for prefetch bug
* V0.4,Jul, 29, 2013 PKB: AAPCS violation in V0.3 fixed
* V0.5,Feb, 05, 2014 PKB: Removed redundant alignment code from copy+clear funcs
* V0.6,May, 05, 2014 JFT: Added ram_code section
* V0.7,Nov, 25, 2014 JFT: CPU workaround disabled. Single default handler.
* Removed DAVE3 dependency
* V0.8,Jan, 05, 2016 JFT: Fix .reset section attributes
* V0.9,March,04,2016 JFT: Fix weak definition of Veneers.
* Only relevant for AA, which needs ENABLE_PMU_CM_001_WORKAROUND
* V1.0,June ,01,2016 JFT: Rename ENABLE_CPU_CM_001_WORKAROUND to ENABLE_PMU_CM_001_WORKAROUND
* Action required: If using AA step, use ENABLE_PMU_CM_001_WORKAROUND instead of ENABLE_CPU_CM_001_WORKAROUND
* @endcond
*/
/* ===========START : MACRO DEFINITION MACRO DEFINITION ================== */
.macro Entry Handler
#if defined(ENABLE_PMU_CM_001_WORKAROUND)
.long \Handler\()_Veneer
#else
.long \Handler
#endif
.endm
.macro Insert_ExceptionHandler Handler_Func
.weak \Handler_Func
.thumb_set \Handler_Func, Default_Handler
#if defined(ENABLE_PMU_CM_001_WORKAROUND)
.weak \Handler_Func\()_Veneer
.type \Handler_Func\()_Veneer, %function
\Handler_Func\()_Veneer:
push {r0, lr}
ldr r0, =\Handler_Func
blx r0
pop {r0, pc}
.size \Handler_Func\()_Veneer, . - \Handler_Func\()_Veneer
#endif
.endm
/* =============END : MACRO DEFINITION MACRO DEFINITION ================== */
/* ================== START OF VECTOR TABLE DEFINITION ====================== */
/* Vector Table - This gets programed into VTOR register by onchip BootROM */
.syntax unified
.section .reset, "a", %progbits
.align 2
.globl __Vectors
.type __Vectors, %object
__Vectors:
.long __initial_sp /* Top of Stack */
.long Reset_Handler /* Reset Handler */
Entry NMI_Handler /* NMI Handler */
Entry HardFault_Handler /* Hard Fault Handler */
Entry MemManage_Handler /* MPU Fault Handler */
Entry BusFault_Handler /* Bus Fault Handler */
Entry UsageFault_Handler /* Usage Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
Entry SVC_Handler /* SVCall Handler */
Entry DebugMon_Handler /* Debug Monitor Handler */
.long 0 /* Reserved */
Entry PendSV_Handler /* PendSV Handler */
Entry SysTick_Handler /* SysTick Handler */
/* Interrupt Handlers for Service Requests (SR) from XMC4200 Peripherals */
Entry SCU_0_IRQHandler /* Handler name for SR SCU_0 */
Entry ERU0_0_IRQHandler /* Handler name for SR ERU0_0 */
Entry ERU0_1_IRQHandler /* Handler name for SR ERU0_1 */
Entry ERU0_2_IRQHandler /* Handler name for SR ERU0_2 */
Entry ERU0_3_IRQHandler /* Handler name for SR ERU0_3 */
Entry ERU1_0_IRQHandler /* Handler name for SR ERU1_0 */
Entry ERU1_1_IRQHandler /* Handler name for SR ERU1_1 */
Entry ERU1_2_IRQHandler /* Handler name for SR ERU1_2 */
Entry ERU1_3_IRQHandler /* Handler name for SR ERU1_3 */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
Entry PMU0_0_IRQHandler /* Handler name for SR PMU0_0 */
.long 0 /* Not Available */
Entry VADC0_C0_0_IRQHandler /* Handler name for SR VADC0_C0_0 */
Entry VADC0_C0_1_IRQHandler /* Handler name for SR VADC0_C0_1 */
Entry VADC0_C0_2_IRQHandler /* Handler name for SR VADC0_C0_1 */
Entry VADC0_C0_3_IRQHandler /* Handler name for SR VADC0_C0_3 */
Entry VADC0_G0_0_IRQHandler /* Handler name for SR VADC0_G0_0 */
Entry VADC0_G0_1_IRQHandler /* Handler name for SR VADC0_G0_1 */
Entry VADC0_G0_2_IRQHandler /* Handler name for SR VADC0_G0_2 */
Entry VADC0_G0_3_IRQHandler /* Handler name for SR VADC0_G0_3 */
Entry VADC0_G1_0_IRQHandler /* Handler name for SR VADC0_G1_0 */
Entry VADC0_G1_1_IRQHandler /* Handler name for SR VADC0_G1_1 */
Entry VADC0_G1_2_IRQHandler /* Handler name for SR VADC0_G1_2 */
Entry VADC0_G1_3_IRQHandler /* Handler name for SR VADC0_G1_3 */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
Entry DAC0_0_IRQHandler /* Handler name for SR DAC0_0 */
Entry DAC0_1_IRQHandler /* Handler name for SR DAC0_1 */
Entry CCU40_0_IRQHandler /* Handler name for SR CCU40_0 */
Entry CCU40_1_IRQHandler /* Handler name for SR CCU40_1 */
Entry CCU40_2_IRQHandler /* Handler name for SR CCU40_2 */
Entry CCU40_3_IRQHandler /* Handler name for SR CCU40_3 */
Entry CCU41_0_IRQHandler /* Handler name for SR CCU41_0 */
Entry CCU41_1_IRQHandler /* Handler name for SR CCU41_1 */
Entry CCU41_2_IRQHandler /* Handler name for SR CCU41_2 */
Entry CCU41_3_IRQHandler /* Handler name for SR CCU41_3 */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
Entry CCU80_0_IRQHandler /* Handler name for SR CCU80_0 */
Entry CCU80_1_IRQHandler /* Handler name for SR CCU80_1 */
Entry CCU80_2_IRQHandler /* Handler name for SR CCU80_2 */
Entry CCU80_3_IRQHandler /* Handler name for SR CCU80_3 */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
Entry POSIF0_0_IRQHandler /* Handler name for SR POSIF0_0 */
Entry POSIF0_1_IRQHandler /* Handler name for SR POSIF0_1 */
.long 0 /* Not Available */
.long 0 /* Not Available */
Entry HRPWM_0_IRQHandler /* Handler name for SR HRPWM_0 */
Entry HRPWM_1_IRQHandler /* Handler name for SR HRPWM_1 */
Entry HRPWM_2_IRQHandler /* Handler name for SR HRPWM_2 */
Entry HRPWM_3_IRQHandler /* Handler name for SR HRPWM_3 */
Entry CAN0_0_IRQHandler /* Handler name for SR CAN0_0 */
Entry CAN0_1_IRQHandler /* Handler name for SR CAN0_1 */
Entry CAN0_2_IRQHandler /* Handler name for SR CAN0_2 */
Entry CAN0_3_IRQHandler /* Handler name for SR CAN0_3 */
Entry CAN0_4_IRQHandler /* Handler name for SR CAN0_4 */
Entry CAN0_5_IRQHandler /* Handler name for SR CAN0_5 */
Entry CAN0_6_IRQHandler /* Handler name for SR CAN0_6 */
Entry CAN0_7_IRQHandler /* Handler name for SR CAN0_7 */
Entry USIC0_0_IRQHandler /* Handler name for SR USIC0_0 */
Entry USIC0_1_IRQHandler /* Handler name for SR USIC0_1 */
Entry USIC0_2_IRQHandler /* Handler name for SR USIC0_2 */
Entry USIC0_3_IRQHandler /* Handler name for SR USIC0_3 */
Entry USIC0_4_IRQHandler /* Handler name for SR USIC0_4 */
Entry USIC0_5_IRQHandler /* Handler name for SR USIC0_5 */
Entry USIC1_0_IRQHandler /* Handler name for SR USIC1_0 */
Entry USIC1_1_IRQHandler /* Handler name for SR USIC1_1 */
Entry USIC1_2_IRQHandler /* Handler name for SR USIC1_2 */
Entry USIC1_3_IRQHandler /* Handler name for SR USIC1_3 */
Entry USIC1_4_IRQHandler /* Handler name for SR USIC1_4 */
Entry USIC1_5_IRQHandler /* Handler name for SR USIC1_5 */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
Entry LEDTS0_0_IRQHandler /* Handler name for SR LEDTS0_0 */
.long 0 /* Not Available */
Entry FCE0_0_IRQHandler /* Handler name for SR FCE0_0 */
Entry GPDMA0_0_IRQHandler /* Handler name for SR GPDMA0_0 */
.long 0 /* Not Available */
Entry USB0_0_IRQHandler /* Handler name for SR USB0_0 */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
.size __Vectors, . - __Vectors
/* ================== END OF VECTOR TABLE DEFINITION ======================= */
/* ================== START OF VECTOR ROUTINES ============================= */
.align 1
.thumb
/* Reset Handler */
.thumb_func
.globl Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp,=__initial_sp
#ifndef __SKIP_SYSTEM_INIT
ldr r0, =SystemInit
blx r0
#endif
/* Initialize data
*
* Between symbol address __copy_table_start__ and __copy_table_end__,
* there are array of triplets, each of which specify:
* offset 0: LMA of start of a section to copy from
* offset 4: VMA of start of a section to copy to
* offset 8: size of the section to copy. Must be multiply of 4
*
* All addresses must be aligned to 4 bytes boundary.
*/
ldr r4, =__copy_table_start__
ldr r5, =__copy_table_end__
.L_loop0:
cmp r4, r5
bge .L_loop0_done
ldr r1, [r4]
ldr r2, [r4, #4]
ldr r3, [r4, #8]
.L_loop0_0:
subs r3, #4
ittt ge
ldrge r0, [r1, r3]
strge r0, [r2, r3]
bge .L_loop0_0
adds r4, #12
b .L_loop0
.L_loop0_done:
/* Zero initialized data
* Between symbol address __zero_table_start__ and __zero_table_end__,
* there are array of tuples specifying:
* offset 0: Start of a BSS section
* offset 4: Size of this BSS section. Must be multiply of 4
*
* Define __SKIP_BSS_CLEAR to disable zeroing uninitialzed data in startup.
*/
#ifndef __SKIP_BSS_CLEAR
ldr r3, =__zero_table_start__
ldr r4, =__zero_table_end__
.L_loop2:
cmp r3, r4
bge .L_loop2_done
ldr r1, [r3]
ldr r2, [r3, #4]
movs r0, 0
.L_loop2_0:
subs r2, #4
itt ge
strge r0, [r1, r2]
bge .L_loop2_0
adds r3, #8
b .L_loop2
.L_loop2_done:
#endif /* __SKIP_BSS_CLEAR */
#ifndef __SKIP_LIBC_INIT_ARRAY
ldr r0, =__libc_init_array
blx r0
#endif
ldr r0, =main
blx r0
.align 2
__copy_table_start__:
.long __data_load, __data_start, __data_size
.long __ram_code_load, __ram_code_start, __ram_code_size
__copy_table_end__:
__zero_table_start__:
.long __bss_start, __bss_size
.long USB_RAM_start, USB_RAM_size
__zero_table_end__:
.pool
.size Reset_Handler,.-Reset_Handler
/* ======================================================================== */
/* ========== START OF EXCEPTION HANDLER DEFINITION ======================== */
/* Default exception Handlers - Users may override this default functionality by
defining handlers of the same name in their C code */
.align 1
.thumb_func
.weak Default_Handler
.type Default_Handler, %function
Default_Handler:
b .
.size Default_Handler, . - Default_Handler
Insert_ExceptionHandler NMI_Handler
Insert_ExceptionHandler HardFault_Handler
Insert_ExceptionHandler MemManage_Handler
Insert_ExceptionHandler BusFault_Handler
Insert_ExceptionHandler UsageFault_Handler
Insert_ExceptionHandler SVC_Handler
Insert_ExceptionHandler DebugMon_Handler
Insert_ExceptionHandler PendSV_Handler
Insert_ExceptionHandler SysTick_Handler
Insert_ExceptionHandler SCU_0_IRQHandler
Insert_ExceptionHandler ERU0_0_IRQHandler
Insert_ExceptionHandler ERU0_1_IRQHandler
Insert_ExceptionHandler ERU0_2_IRQHandler
Insert_ExceptionHandler ERU0_3_IRQHandler
Insert_ExceptionHandler ERU1_0_IRQHandler
Insert_ExceptionHandler ERU1_1_IRQHandler
Insert_ExceptionHandler ERU1_2_IRQHandler
Insert_ExceptionHandler ERU1_3_IRQHandler
Insert_ExceptionHandler PMU0_0_IRQHandler
Insert_ExceptionHandler VADC0_C0_0_IRQHandler
Insert_ExceptionHandler VADC0_C0_1_IRQHandler
Insert_ExceptionHandler VADC0_C0_2_IRQHandler
Insert_ExceptionHandler VADC0_C0_3_IRQHandler
Insert_ExceptionHandler VADC0_G0_0_IRQHandler
Insert_ExceptionHandler VADC0_G0_1_IRQHandler
Insert_ExceptionHandler VADC0_G0_2_IRQHandler
Insert_ExceptionHandler VADC0_G0_3_IRQHandler
Insert_ExceptionHandler VADC0_G1_0_IRQHandler
Insert_ExceptionHandler VADC0_G1_1_IRQHandler
Insert_ExceptionHandler VADC0_G1_2_IRQHandler
Insert_ExceptionHandler VADC0_G1_3_IRQHandler
Insert_ExceptionHandler DAC0_0_IRQHandler
Insert_ExceptionHandler DAC0_1_IRQHandler
Insert_ExceptionHandler CCU40_0_IRQHandler
Insert_ExceptionHandler CCU40_1_IRQHandler
Insert_ExceptionHandler CCU40_2_IRQHandler
Insert_ExceptionHandler CCU40_3_IRQHandler
Insert_ExceptionHandler CCU41_0_IRQHandler
Insert_ExceptionHandler CCU41_1_IRQHandler
Insert_ExceptionHandler CCU41_2_IRQHandler
Insert_ExceptionHandler CCU41_3_IRQHandler
Insert_ExceptionHandler CCU80_0_IRQHandler
Insert_ExceptionHandler CCU80_1_IRQHandler
Insert_ExceptionHandler CCU80_2_IRQHandler
Insert_ExceptionHandler CCU80_3_IRQHandler
Insert_ExceptionHandler POSIF0_0_IRQHandler
Insert_ExceptionHandler POSIF0_1_IRQHandler
Insert_ExceptionHandler HRPWM_0_IRQHandler
Insert_ExceptionHandler HRPWM_1_IRQHandler
Insert_ExceptionHandler HRPWM_2_IRQHandler
Insert_ExceptionHandler HRPWM_3_IRQHandler
Insert_ExceptionHandler CAN0_0_IRQHandler
Insert_ExceptionHandler CAN0_1_IRQHandler
Insert_ExceptionHandler CAN0_2_IRQHandler
Insert_ExceptionHandler CAN0_3_IRQHandler
Insert_ExceptionHandler CAN0_4_IRQHandler
Insert_ExceptionHandler CAN0_5_IRQHandler
Insert_ExceptionHandler CAN0_6_IRQHandler
Insert_ExceptionHandler CAN0_7_IRQHandler
Insert_ExceptionHandler USIC0_0_IRQHandler
Insert_ExceptionHandler USIC0_1_IRQHandler
Insert_ExceptionHandler USIC0_2_IRQHandler
Insert_ExceptionHandler USIC0_3_IRQHandler
Insert_ExceptionHandler USIC0_4_IRQHandler
Insert_ExceptionHandler USIC0_5_IRQHandler
Insert_ExceptionHandler USIC1_0_IRQHandler
Insert_ExceptionHandler USIC1_1_IRQHandler
Insert_ExceptionHandler USIC1_2_IRQHandler
Insert_ExceptionHandler USIC1_3_IRQHandler
Insert_ExceptionHandler USIC1_4_IRQHandler
Insert_ExceptionHandler USIC1_5_IRQHandler
Insert_ExceptionHandler LEDTS0_0_IRQHandler
Insert_ExceptionHandler FCE0_0_IRQHandler
Insert_ExceptionHandler GPDMA0_0_IRQHandler
Insert_ExceptionHandler USB0_0_IRQHandler
/* ============= END OF INTERRUPT HANDLER DEFINITION ====================== */
.end

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/*********************************************************************************************************************
* @file system_XMC4200.c
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File for the Infineon XMC4200 Device Series
* @version V3.1.3
* @date 26. Sep 2017
*
* @cond
*********************************************************************************************************************
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
********************** Version History ***************************************
* V3.1.0, Dec 2014, Added options to configure clock settings
* V3.1.1, 01. Jun 2016, Fix masking of OSCHPCTRL value
* V3.1.2, 19. Jun 2017, Rely on cmsis_compiler.h instead of defining __WEAK
* Added support for ARM Compiler 6 (armclang)
* V3.1.3, 26. Sep 2017, Disable FPU if FPU_USED is zero
******************************************************************************
* @endcond
*/
/*******************************************************************************
* HEADER FILES
*******************************************************************************/
#include <string.h>
#include <XMC4200.h>
#include "system_XMC4200.h"
/*******************************************************************************
* MACROS
*******************************************************************************/
#define CHIPID_LOC ((uint8_t *)0x20000000UL)
#define HRPWM_CHARDATA_LOC ((uint8_t *)0x20000084UL)
#define PMU_FLASH_WS (0x2U)
#define FPLL_FREQUENCY (80000000U)
#define FOSCREF (2500000U)
#define DELAY_CNT_50US_50MHZ (2500UL)
#define DELAY_CNT_150US_50MHZ (7500UL)
#define DELAY_CNT_50US_60MHZ (3000UL)
#define DELAY_CNT_50US_80MHZ (4000UL)
#define SCU_PLL_PLLSTAT_OSC_USABLE (SCU_PLL_PLLSTAT_PLLHV_Msk | \
SCU_PLL_PLLSTAT_PLLLV_Msk | \
SCU_PLL_PLLSTAT_PLLSP_Msk)
/*
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
*/
/*
// <h> Clock configuration
*/
/*
// <o> External crystal frequency [Hz]
// <8000000=> 8MHz
// <12000000=> 12MHz
// <16000000=> 16MHz
// <i> Defines external crystal frequency
// <i> Default: 8MHz
*/
#define OSCHP_FREQUENCY (12000000U)
#if OSCHP_FREQUENCY == 8000000U
#define USB_PDIV (1U)
#define USB_NDIV (95U)
#define USB_DIV (3U)
#elif OSCHP_FREQUENCY == 12000000U
#define USB_PDIV (1U)
#define USB_NDIV (63U)
#define USB_DIV (3U)
#elif OSCHP_FREQUENCY == 16000000U
#define USB_PDIV (1U)
#define USB_NDIV (47U)
#define USB_DIV (3U)
#else
#error "External crystal frequency not supported"
#endif
/*
// <o> System clock (fSYS) source selection
// <0=> Backup clock (24MHz)
// <1=> Maximum clock frequency using PLL (80MHz)
// <i> Default: Maximum clock frequency using PLL (80MHz)
*/
#define SYS_CLOCK_SRC 1
#define SYS_CLOCK_SRC_OFI 0
#define SYS_CLOCK_SRC_PLL 1
/*
// <o> Backup clock calibration mode
// <0=> Factory calibration
// <1=> Automatic calibration
// <i> Default: Automatic calibration
*/
#define FOFI_CALIBRATION_MODE 1
#define FOFI_CALIBRATION_MODE_FACTORY 0
#define FOFI_CALIBRATION_MODE_AUTOMATIC 1
/*
// <o> Standby clock (fSTDBY) source selection
// <0=> Internal slow oscillator (32768Hz)
// <1=> External crystal (32768Hz)
// <i> Default: Internal slow oscillator (32768Hz)
*/
#define STDBY_CLOCK_SRC 0
#define STDBY_CLOCK_SRC_OSI 0
#define STDBY_CLOCK_SRC_OSCULP 1
/*
// <o> PLL clock source selection
// <0=> External crystal
// <1=> External direct input
// <2=> Internal fast oscillator
// <i> Default: External crystal
*/
#define PLL_CLOCK_SRC 0
#define PLL_CLOCK_SRC_EXT_XTAL 0
#define PLL_CLOCK_SRC_EXT_DIRECT 1
#define PLL_CLOCK_SRC_OFI 2
#if PLL_CLOCK_SRC == PLL_CLOCK_SRC_EXT_XTAL
#if OSCHP_FREQUENCY == 8000000U
#define PLL_PDIV (1U)
#define PLL_NDIV (79U)
#define PLL_K2DIV (3U)
#elif OSCHP_FREQUENCY == 12000000U
#define PLL_PDIV (2U)
#define PLL_NDIV (79U)
#define PLL_K2DIV (3U)
#elif OSCHP_FREQUENCY == 16000000U
#define PLL_PDIV (1U)
#define PLL_NDIV (39U)
#define PLL_K2DIV (3U)
#else
#error "External crystal frequency not supported"
#endif
#define VCO ((OSCHP_FREQUENCY / (PLL_PDIV + 1UL)) * (PLL_NDIV + 1UL))
#else /* PLL_CLOCK_SRC == PLL_CLOCK_SRC_EXT_XTAL */
#define PLL_PDIV (5U)
#define PLL_NDIV (79U)
#define PLL_K2DIV (3U)
#define VCO ((OFI_FREQUENCY / (PLL_PDIV + 1UL)) * (PLL_NDIV + 1UL))
#endif /* PLL_CLOCK_SRC == PLL_CLOCK_SRC_OFI */
#define PLL_K2DIV_0 ((VCO / OFI_FREQUENCY) - 1UL)
#define PLL_K2DIV_1 ((VCO / 60000000U) - 1UL)
#define SCU_CLK_CLKCLR_ENABLE_USBCLK SCU_CLK_CLKCLR_USBCDI_Msk
#define SCU_CLK_CLKCLR_ENABLE_CCUCLK SCU_CLK_CLKCLR_CCUCDI_Msk
#define SCU_CLK_CLKCLR_ENABLE_WDTCLK SCU_CLK_CLKCLR_WDTCDI_Msk
#define SCU_CLK_USBCLKCR_USBSEL_USBPLL (0U << SCU_CLK_USBCLKCR_USBSEL_Pos)
#define SCU_CLK_USBCLKCR_USBSEL_PLL (1U << SCU_CLK_USBCLKCR_USBSEL_Pos)
#define SCU_CLK_WDTCLKCR_WDTSEL_OFI (0U << SCU_CLK_WDTCLKCR_WDTSEL_Pos)
#define SCU_CLK_WDTCLKCR_WDTSEL_STANDBY (1U << SCU_CLK_WDTCLKCR_WDTSEL_Pos)
#define SCU_CLK_WDTCLKCR_WDTSEL_PLL (2U << SCU_CLK_WDTCLKCR_WDTSEL_Pos)
#define SCU_CLK_EXTCLKCR_ECKSEL_SYS (0U << SCU_CLK_EXTCLKCR_ECKSEL_Pos)
#define SCU_CLK_EXTCLKCR_ECKSEL_USBPLL (2U << SCU_CLK_EXTCLKCR_ECKSEL_Pos)
#define SCU_CLK_EXTCLKCR_ECKSEL_PLL (3U << SCU_CLK_EXTCLKCR_ECKSEL_Pos)
#define SCU_CLK_EXTCLKCR_ECKSEL_STANDBY (4U << SCU_CLK_EXTCLKCR_ECKSEL_Pos)
#define EXTCLK_PIN_P0_8 (0)
#define EXTCLK_PIN_P1_15 (1)
/*
// <h> Clock tree
// <o1.0> CPU clock divider
// <0=> fCPU = fSYS
// <1=> fCPU = fSYS / 2
// <o2.0> Peripheral clock divider
// <0=> fPB = fCPU
// <1=> fPB = fCPU / 2
// <e.4> Enable CCU clock
// <o3.0> CCU clock divider
// <0=> fCCU = fCPU
// <1=> fCCU = fCPU / 2
// </e>
// <e.5> Enable WDT clock
// <o4.0..7> WDT clock divider <1-256><#-1>
// <o4.16..17> WDT clock source <0=> fOFI
// <1=> fSTDBY
// <2=> fPLL
// </e>
// <e.0> Enable USB clock
// <o5.16> USB clock source <0=> USBPLL
// <1=> PLL
// </e>
// <e6> External Clock configuration
// <o7.0..2> External clock source selection
// <0=> System clock
// <2=> USB PLL clock
// <3=> PLL clock
// <4=> Standby clock
// <o7.16..24> External clock divider <1-512><#-1>
// <i> Only valid for USB PLL and PLL clocks
// <o8.0> External Pin Selection
// <0=> P0.8
// <1=> P1.15
// </e>
// </h>
*/
#define ENABLE_SCUCLK (0U)
#define CPUCLKDIV (0U)
#define PBCLKDIV (0U)
#define CCUCLKDIV (0U)
#define WDTCLKDIV (0U | SCU_CLK_WDTCLKCR_WDTSEL_OFI)
#define USBCLKDIV (0U | SCU_CLK_USBCLKCR_USBSEL_USBPLL | USB_DIV)
#define ENABLE_EXTCLK (0U)
#define EXTCLKDIV (0U | SCU_CLK_EXTCLKCR_ECKSEL_SYS)
#define EXTCLK_PIN (0U)
#define ENABLE_PLL \
(SYS_CLOCK_SRC == SYS_CLOCK_SRC_PLL) || \
(((ENABLE_SCUCLK & SCU_CLK_CLKSET_USBCEN_Msk) != 0) && ((USBCLKDIV & SCU_CLK_USBCLKCR_USBSEL_Msk) == SCU_CLK_USBCLKCR_USBSEL_PLL)) || \
(((ENABLE_SCUCLK & SCU_CLK_CLKSET_WDTCEN_Msk) != 0) && ((WDTCLKDIV & SCU_CLK_WDTCLKCR_WDTSEL_Msk) == SCU_CLK_WDTCLKCR_WDTSEL_PLL))
/*
// </h>
*/
/*
//-------- <<< end of configuration section >>> ------------------
*/
/*******************************************************************************
* GLOBAL VARIABLES
*******************************************************************************/
#if defined ( __CC_ARM )
uint32_t SystemCoreClock __attribute__((at(0x20005FC0)));
uint8_t g_chipid[16] __attribute__((at(0x20005FC4)));
uint32_t g_hrpwm_char_data[3] __attribute__((at(0x20005FD4)));
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
uint32_t SystemCoreClock __attribute__((section(".ARM.__at_0x20005FC0")));
uint8_t g_chipid[16] __attribute__((section(".ARM.__at_0x20005FC4")));
uint32_t g_hrpwm_char_data[3] __attribute__((section(".ARM.__at_0x20005FD4")));
#elif defined ( __ICCARM__ )
__no_init uint32_t SystemCoreClock;
__no_init uint8_t g_chipid[16];
__no_init uint32_t g_hrpwm_char_data[3];
#elif defined ( __GNUC__ )
uint32_t SystemCoreClock __attribute__((section(".no_init")));
uint8_t g_chipid[16] __attribute__((section(".no_init")));
uint32_t g_hrpwm_char_data[3] __attribute__((section(".no_init")));
#elif defined ( __TASKING__ )
uint32_t SystemCoreClock __at( 0x20005FC0 );
uint8_t g_chipid[16] __at( 0x20005FC4 );
uint32_t g_hrpwm_char_data[3] __at( 0x20005FD4 );
#endif
extern uint32_t __Vectors;
/*******************************************************************************
* LOCAL FUNCTIONS
*******************************************************************************/
static void delay(uint32_t cycles)
{
volatile uint32_t i;
for(i = 0UL; i < cycles ;++i)
{
__NOP();
}
}
/*******************************************************************************
* API IMPLEMENTATION
*******************************************************************************/
__WEAK void SystemInit(void)
{
memcpy(g_chipid, CHIPID_LOC, 16);
memcpy(g_hrpwm_char_data, HRPWM_CHARDATA_LOC, 12);
SystemCoreSetup();
SystemCoreClockSetup();
}
__WEAK void SystemCoreSetup(void)
{
uint32_t temp;
/* relocate vector table */
__disable_irq();
SCB->VTOR = (uint32_t)(&__Vectors);
__DSB();
__enable_irq();
/* __FPU_PRESENT = 1 in device header file */
/* __FPU_USED value depends on compiler options. */
/* __FPU_USED = 0 if -mfloat-abi=soft is selected */
/* __FPU_USED = 0 if -mfloat-abi=softfp or –mfloat-abi=hard */
#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */
(3UL << 11*2) ); /* set CP11 Full Access */
#else
SCB->CPACR = 0;
#endif
/* Enable unaligned memory access - SCB_CCR.UNALIGN_TRP = 0 */
SCB->CCR &= ~(SCB_CCR_UNALIGN_TRP_Msk);
temp = FLASH0->FCON;
temp &= ~FLASH_FCON_WSPFLASH_Msk;
temp |= PMU_FLASH_WS;
FLASH0->FCON = temp;
}
__WEAK void SystemCoreClockSetup(void)
{
#if FOFI_CALIBRATION_MODE == FOFI_CALIBRATION_MODE_FACTORY
/* Enable factory calibration */
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FOTR_Msk;
#else
/* Automatic calibration uses the fSTDBY */
/* Enable HIB domain */
/* Power up HIB domain if and only if it is currently powered down */
if((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0)
{
SCU_POWER->PWRSET |= SCU_POWER_PWRSET_HIB_Msk;
while((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0)
{
/* wait until HIB domain is enabled */
}
}
/* Remove the reset only if HIB domain were in a state of reset */
if((SCU_RESET->RSTSTAT) & SCU_RESET_RSTSTAT_HIBRS_Msk)
{
SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_HIBRS_Msk;
delay(DELAY_CNT_150US_50MHZ);
}
#if STDBY_CLOCK_SRC == STDBY_CLOCK_SRC_OSCULP
/* Enable OSC_ULP */
if ((SCU_HIBERNATE->OSCULCTRL & SCU_HIBERNATE_OSCULCTRL_MODE_Msk) != 0UL)
{
/*enable OSC_ULP*/
while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk)
{
/* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */
}
SCU_HIBERNATE->OSCULCTRL &= ~SCU_HIBERNATE_OSCULCTRL_MODE_Msk;
/* Check if the clock is OK using OSCULP Oscillator Watchdog*/
while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk)
{
/* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */
}
SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_ULPWDGEN_Msk;
/* wait till clock is stable */
do
{
while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk)
{
/* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */
}
SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk;
delay(DELAY_CNT_50US_50MHZ);
} while ((SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_ULPWDG_Msk) != 0UL);
}
/* now OSC_ULP is running and can be used*/
/* Select OSC_ULP as the clock source for RTC and STDBY*/
while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk)
{
/* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */
}
SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_RCS_Msk | SCU_HIBERNATE_HDCR_STDBYSEL_Msk;
#endif /* STDBY_CLOCK_SRC == STDBY_CLOCK_SRC_OSCULP */
/* Enable automatic calibration of internal fast oscillator */
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk;
#endif /* FOFI_CALIBRATION_MODE == FOFI_CALIBRATION_MODE_AUTOMATIC */
delay(DELAY_CNT_50US_50MHZ);
#if ENABLE_PLL
/* enable PLL */
SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);
#if PLL_CLOCK_SRC != PLL_CLOCK_SRC_OFI
/* enable OSC_HP */
if ((SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk) != 0U)
{
SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_OSCHPCTRL_MODE_Msk | SCU_OSC_OSCHPCTRL_OSCVAL_Msk);
SCU_OSC->OSCHPCTRL |= ((OSCHP_GetFrequency() / FOSCREF) - 1UL) << SCU_OSC_OSCHPCTRL_OSCVAL_Pos;
/* select OSC_HP clock as PLL input */
SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk;
/* restart OSC Watchdog */
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;
while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_OSC_USABLE) != SCU_PLL_PLLSTAT_OSC_USABLE)
{
/* wait till OSC_HP output frequency is usable */
}
}
#else /* PLL_CLOCK_SRC != PLL_CLOCK_SRC_OFI */
/* select backup clock as PLL input */
SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk;
#endif
/* Go to bypass the Main PLL */
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk;
/* disconnect Oscillator from PLL */
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk;
/* Setup divider settings for main PLL */
SCU_PLL->PLLCON1 = ((PLL_NDIV << SCU_PLL_PLLCON1_NDIV_Pos) |
(PLL_K2DIV_0 << SCU_PLL_PLLCON1_K2DIV_Pos) |
(PLL_PDIV << SCU_PLL_PLLCON1_PDIV_Pos));
/* Set OSCDISCDIS */
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk;
/* connect Oscillator to PLL */
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk;
/* restart PLL Lock detection */
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk;
while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk) == 0U)
{
/* wait for PLL Lock */
}
/* Disable bypass- put PLL clock back */
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk;
while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOBYST_Msk) != 0U)
{
/* wait for normal mode */
}
#endif /* ENABLE_PLL */
#if (SYS_CLOCK_SRC == SYS_CLOCK_SRC_PLL)
/* Switch system clock to PLL */
SCU_CLK->SYSCLKCR |= SCU_CLK_SYSCLKCR_SYSSEL_Msk;
#else
/* Switch system clock to backup clock */
SCU_CLK->SYSCLKCR &= ~SCU_CLK_SYSCLKCR_SYSSEL_Msk;
#endif
/* Before scaling to final frequency we need to setup the clock dividers */
SCU_CLK->PBCLKCR = PBCLKDIV;
SCU_CLK->CPUCLKCR = CPUCLKDIV;
SCU_CLK->CCUCLKCR = CCUCLKDIV;
SCU_CLK->WDTCLKCR = WDTCLKDIV;
SCU_CLK->USBCLKCR = USBCLKDIV;
#if ENABLE_PLL
/* PLL frequency stepping...*/
/* Reset OSCDISCDIS */
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCDISCDIS_Msk;
SCU_PLL->PLLCON1 = ((PLL_NDIV << SCU_PLL_PLLCON1_NDIV_Pos) |
(PLL_K2DIV_1 << SCU_PLL_PLLCON1_K2DIV_Pos) |
(PLL_PDIV << SCU_PLL_PLLCON1_PDIV_Pos));
delay(DELAY_CNT_50US_60MHZ);
while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk) == 0U)
{
/* wait for PLL Lock */
}
SCU_PLL->PLLCON1 = ((PLL_NDIV << SCU_PLL_PLLCON1_NDIV_Pos) |
(PLL_K2DIV << SCU_PLL_PLLCON1_K2DIV_Pos) |
(PLL_PDIV << SCU_PLL_PLLCON1_PDIV_Pos));
delay(DELAY_CNT_50US_80MHZ);
while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk) == 0U)
{
/* wait for PLL Lock */
}
SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk;
#endif /* ENABLE_PLL */
#if (((ENABLE_SCUCLK & SCU_CLK_CLKSET_USBCEN_Msk) != 0) && ((USBCLKDIV & SCU_CLK_USBCLKCR_USBSEL_Msk) == SCU_CLK_USBCLKCR_USBSEL_USBPLL))
/* enable USB PLL first */
SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk);
/* USB PLL uses as clock input the OSC_HP */
/* check and if not already running enable OSC_HP */
if ((SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk) != 0U)
{
/* check if Main PLL is switched on for OSC WDG*/
if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0UL)
{
/* enable PLL first */
SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);
}
SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_OSCHPCTRL_MODE_Msk | SCU_OSC_OSCHPCTRL_OSCVAL_Msk);
SCU_OSC->OSCHPCTRL |= ((OSCHP_GetFrequency() / FOSCREF) - 1UL) << SCU_OSC_OSCHPCTRL_OSCVAL_Pos;
/* restart OSC Watchdog */
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;
while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_OSC_USABLE) != SCU_PLL_PLLSTAT_OSC_USABLE)
{
/* wait till OSC_HP output frequency is usable */
}
}
/* Setup USB PLL */
/* Go to bypass the USB PLL */
SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_VCOBYP_Msk;
/* disconnect Oscillator from USB PLL */
SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_FINDIS_Msk;
/* Setup Divider settings for USB PLL */
SCU_PLL->USBPLLCON = ((USB_NDIV << SCU_PLL_USBPLLCON_NDIV_Pos) |
(USB_PDIV << SCU_PLL_USBPLLCON_PDIV_Pos));
/* Set OSCDISCDIS */
SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_OSCDISCDIS_Msk;
/* connect Oscillator to USB PLL */
SCU_PLL->USBPLLCON &= ~SCU_PLL_USBPLLCON_FINDIS_Msk;
/* restart PLL Lock detection */
SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_RESLD_Msk;
while ((SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk) == 0U)
{
/* wait for PLL Lock */
}
#endif /* (USBCLKDIV & SCU_CLK_USBCLKCR_USBSEL_Msk) */
/* Enable selected clocks */
SCU_CLK->CLKSET = ENABLE_SCUCLK;
#if ENABLE_EXTCLK == 1
/* Configure external clock */
SCU_CLK->EXTCLKCR = EXTCLKDIV;
#if EXTCLK_PIN == EXTCLK_PIN_P1_15
/* P1.15 */
PORT1->PDR1 &= ~PORT1_PDR1_PD15_Msk;
PORT1->IOCR12 = (PORT1->IOCR12 & ~PORT0_IOCR12_PC15_Msk) | (0x11U << PORT0_IOCR12_PC15_Pos);
#else
/* P0.8 */
PORT0->HWSEL &= ~PORT0_HWSEL_HW8_Msk;
PORT0->PDR1 &= ~PORT0_PDR1_PD8_Msk;
PORT0->IOCR8 = (PORT0->IOCR8 & ~PORT0_IOCR8_PC8_Msk) | (0x11U << PORT0_IOCR8_PC8_Pos);
#endif
#endif /* ENABLE_EXTCLK == 1 */
SystemCoreClockUpdate();
}
__WEAK void SystemCoreClockUpdate(void)
{
uint32_t pdiv;
uint32_t ndiv;
uint32_t kdiv;
uint32_t temp;
if (SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSSEL_Msk)
{
/* fPLL is clock source for fSYS */
if(SCU_PLL->PLLCON2 & SCU_PLL_PLLCON2_PINSEL_Msk)
{
/* PLL input clock is the backup clock (fOFI) */
temp = OFI_FREQUENCY;
}
else
{
/* PLL input clock is the high performance osicllator (fOSCHP) */
temp = OSCHP_GetFrequency();
}
/* check if PLL is locked */
if (SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)
{
/* PLL normal mode */
/* read back divider settings */
pdiv = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_PDIV_Msk) >> SCU_PLL_PLLCON1_PDIV_Pos) + 1;
ndiv = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_NDIV_Msk) >> SCU_PLL_PLLCON1_NDIV_Pos) + 1;
kdiv = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K2DIV_Msk) >> SCU_PLL_PLLCON1_K2DIV_Pos) + 1;
temp = (temp / (pdiv * kdiv)) * ndiv;
}
else
{
/* PLL prescalar mode */
/* read back divider settings */
kdiv = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K1DIV_Msk) >> SCU_PLL_PLLCON1_K1DIV_Pos) + 1;
temp = (temp / kdiv);
}
}
else
{
/* fOFI is clock source for fSYS */
temp = OFI_FREQUENCY;
}
temp = temp / ((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk) + 1);
temp = temp / ((SCU_CLK->CPUCLKCR & SCU_CLK_CPUCLKCR_CPUDIV_Msk) + 1);
SystemCoreClock = temp;
}
__WEAK uint32_t OSCHP_GetFrequency(void)
{
return OSCHP_FREQUENCY;
}

106
src/platform/xmc4000/system_XMC4200.h Normal file
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/*********************************************************************************************************************
* @file system_XMC4200.h
* @brief Device specific initialization for the XMC4200-Series according to CMSIS
* @version V1.6
* @date 23 October 2012
*
* @cond
*********************************************************************************************************************
* Copyright (c) 2012-2016, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
**************************** Change history *********************************
*****************************************************************************
* @endcond
*/
#ifndef SYSTEM_XMC4200_H
#define SYSTEM_XMC4200_H
/*******************************************************************************
* HEADER FILES
*******************************************************************************/
#include <stdint.h>
/*******************************************************************************
* MACROS
*******************************************************************************/
#define OFI_FREQUENCY (24000000UL) /**< 24MHz Backup Clock (fOFI) frequency. */
#define OSI_FREQUENCY (32768UL) /**< 32KHz Internal Slow Clock source (fOSI) frequency. */
/*******************************************************************************
* GLOBAL VARIABLES
*******************************************************************************/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern uint8_t g_chipid[16]; /*!< Unique chip ID */
extern uint32_t g_hrpwm_char_data[3]; /*!< HRPWM characterization data */
/*******************************************************************************
* API PROTOTYPES
*******************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Initialize the system
*
*/
void SystemInit(void);
/**
* @brief Initialize CPU settings
*
*/
void SystemCoreSetup(void);
/**
* @brief Initialize clock
*
*/
void SystemCoreClockSetup(void);
/**
* @brief Update SystemCoreClock variable
*
*/
void SystemCoreClockUpdate(void);
/**
* @brief Returns frequency of the high performace oscillator
* User needs to overload this function to return the correct oscillator frequency
*/
uint32_t OSCHP_GetFrequency(void);
#ifdef __cplusplus
}
#endif
#endif

281
src/platform/xmc4000/xmc4200_linker_script.ld Normal file
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@ -0,0 +1,281 @@
/**
* @file XMC4200x256.ld
* @date 2017-04-20
*
* @cond
*********************************************************************************************************************
* Linker file for the GNU C Compiler v1.8
* Supported devices: XMC4200-F64x256
* XMC4200-Q48x256
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-07-07:
* - Product splitting
* - Copyright notice update
*
* 2015-11-24:
* - Compatibility with GCC 4.9 2015q2
*
* 2016-03-08:
* - Fix size of BSS and DATA sections to be multiple of 4
* - Add assertion to check that region SRAM_combined does not overflowed no_init section
*
* 2017-04-07:
* - Added new symbols __text_size and eText
*
* 2017-04-20:
* - Change vtable location to flash area to save ram
*
* @endcond
*
*/
OUTPUT_FORMAT("elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(Reset_Handler)
MEMORY
{
FLASH_1_cached(RX) : ORIGIN = 0x08000000, LENGTH = 0x40000
FLASH_1_uncached(RX) : ORIGIN = 0x0C000000, LENGTH = 0x40000
PSRAM_1(!RX) : ORIGIN = 0x1FFFC000, LENGTH = 0x4000
DSRAM_1_system(!RX) : ORIGIN = 0x20000000, LENGTH = 0x6000
SRAM_combined(!RX) : ORIGIN = 0x1FFFC000, LENGTH = 0xA000
}
stack_size = DEFINED(stack_size) ? stack_size : 2048;
no_init_size = 64;
SECTIONS
{
/* TEXT section */
.text :
{
sText = .;
KEEP(*(.reset));
*(.text .text.* .gnu.linkonce.t.*);
/* C++ Support */
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata .rodata.*)
*(.gnu.linkonce.r*)
*(vtable)
. = ALIGN(4);
} > FLASH_1_cached AT > FLASH_1_uncached
.eh_frame_hdr : ALIGN (4)
{
KEEP (*(.eh_frame_hdr))
} > FLASH_1_cached AT > FLASH_1_uncached
.eh_frame : ALIGN (4)
{
KEEP (*(.eh_frame))
} > FLASH_1_cached AT > FLASH_1_uncached
/* Exception handling, exidx needs a dedicated section */
.ARM.extab : ALIGN(4)
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH_1_cached AT > FLASH_1_uncached
. = ALIGN(4);
__exidx_start = .;
.ARM.exidx : ALIGN(4)
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > FLASH_1_cached AT > FLASH_1_uncached
__exidx_end = .;
. = ALIGN(4);
/* DSRAM layout (Lowest to highest)*/
Stack (NOLOAD) :
{
__stack_start = .;
. = . + stack_size;
__stack_end = .;
__initial_sp = .;
} > SRAM_combined
/* functions with __attribute__((section(".ram_code"))) */
.ram_code :
{
. = ALIGN(4); /* section size must be multiply of 4. See startup.S file */
__ram_code_start = .;
*(.ram_code)
. = ALIGN(4); /* section size must be multiply of 4. See startup.S file */
__ram_code_end = .;
} > SRAM_combined AT > FLASH_1_uncached
__ram_code_load = LOADADDR (.ram_code);
__ram_code_size = __ram_code_end - __ram_code_start;
/* Standard DATA and user defined DATA/BSS/CONST sections */
.data :
{
. = ALIGN(4); /* section size must be multiply of 4. See startup.S file */
__data_start = .;
* (.data);
* (.data*);
*(*.data);
*(.gnu.linkonce.d*)
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
. = ALIGN(4); /* section size must be multiply of 4. See startup.S file */
__data_end = .;
} > SRAM_combined AT > FLASH_1_uncached
__data_load = LOADADDR (.data);
__data_size = __data_end - __data_start;
__text_size = (__exidx_end - sText) + __data_size + __ram_code_size;
eText = sText + __text_size;
/* BSS section */
.bss (NOLOAD) :
{
. = ALIGN(4); /* section size must be multiply of 4. See startup.S file */
__bss_start = .;
* (.bss);
* (.bss*);
* (COMMON);
*(.gnu.linkonce.b*)
. = ALIGN(4); /* section size must be multiply of 4. See startup.S file */
__bss_end = .;
} > SRAM_combined
__bss_size = __bss_end - __bss_start;
/* Shift location counter, so that ETH_RAM and USB_RAM are located above DSRAM_1_system */
__shift_loc = (__bss_end >= ORIGIN(DSRAM_1_system)) ? 0 : (ORIGIN(DSRAM_1_system) - __bss_end);
USB_RAM (__bss_end + __shift_loc) (NOLOAD) :
{
. = ALIGN(4); /* section size must be multiply of 4. See startup.S file */
USB_RAM_start = .;
*(USB_RAM)
. = ALIGN(4); /* section size must be multiply of 4. See startup.S file */
USB_RAM_end = .;
. = ALIGN(8);
Heap_Bank1_Start = .;
} > SRAM_combined
USB_RAM_size = USB_RAM_end - USB_RAM_start;
/* .no_init section contains chipid, SystemCoreClock and trimming data. See system.c file */
.no_init ORIGIN(SRAM_combined) + LENGTH(SRAM_combined) - no_init_size (NOLOAD) :
{
Heap_Bank1_End = .;
* (.no_init);
} > SRAM_combined
/* Heap - Bank1*/
Heap_Bank1_Size = Heap_Bank1_End - Heap_Bank1_Start;
ASSERT(Heap_Bank1_Start <= Heap_Bank1_End, "region SRAM_combined overflowed no_init section")
/DISCARD/ :
{
*(.comment)
}
.stab 0 (NOLOAD) : { *(.stab) }
.stabstr 0 (NOLOAD) : { *(.stabstr) }
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_pubtypes 0 : { *(.debug_pubtypes) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* DWARF 2.1 */
.debug_ranges 0 : { *(.debug_ranges) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
/* Build attributes */
.build_attributes 0 : { *(.ARM.attributes) }
}