mirror of
https://github.com/elua/elua.git
synced 2025-01-08 20:56:17 +08:00
- ADC now runs with an interrupt handler, which manages samples from each
channel. Smoothing support (rolling average) has been added. adcscope has been updated to reflect these changes, and show output from 4 channels at once. - fix for typo in stm32/platform.c
This commit is contained in:
James Snyder
parent
16e4dba18d
commit
da35498b02
@ -12,4 +12,6 @@
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void cmn_platform_init();
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void cmn_virtual_timer_cb();
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unsigned int intlog2( unsigned int v );
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#endif // #ifndef __COMMON_H__
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@ -53,7 +53,7 @@ enum
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PLATFORM_IO_PORT_SET_VALUE,
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PLATFORM_IO_PORT_GET_VALUE,
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PLATFORM_IO_PORT_DIR_INPUT,
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PLATFORM_IO_PORT_DIR_OUTPUT
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PLATFORM_IO_PORT_DIR_OUTPUT
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};
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// The platform I/O functions
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@ -176,13 +176,48 @@ u32 platform_cpu_get_frequency();
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// *****************************************************************************
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// The platform ADC functions
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int platform_adc_exists( unsigned id );
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enum
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{
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PLATFORM_ADC_CH_SETUP, // Have we set up the sequence?
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PLATFORM_ADC_CH_PENDING, // Is there a pending conversion?
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PLATFORM_ADC_CH_NONBLOCKING, // Are we in blocking or non-blocking mode? (0 - blocking, 1 - nonblocking)
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PLATFORM_ADC_CH_BURST, // Acquiring in burst mode
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PLATFORM_ADC_CH_DATA_READY // Is data ready for this channel
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};
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u32 platform_adc_op( unsigned id, int op, u32 data );
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enum
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{
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PLATFORM_ADC_GET_MAXVAL,
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PLATFORM_ADC_GET_SMOOTHING,
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PLATFORM_ADC_SET_SMOOTHING
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};
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u16 platform_adc_sample( unsigned id );
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u16 platform_adc_maxval( unsigned id );
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void platform_adc_start( unsigned id );
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int platform_adc_is_done( unsigned id );
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enum
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{
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PLATFORM_ADC_BLOCKING,
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PLATFORM_ADC_NONBLOCKING
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};
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// Platform ADC state
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struct platform_adc_state
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{
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u8 status;
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u8 burstbuffersz, burstbufferidx;
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u8 smoothbuffsz, smoothbuffidx;
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unsigned long smoothingav, smoothingsum;
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u16 *burstbuff, *smoothbuff;
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};
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void platform_adc_set_mode( unsigned id, int mode );
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void platform_adc_burst( unsigned id, u16* buf, unsigned count, u32 frequency );
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void platform_adc_burst( unsigned id, u16* buf, unsigned count, unsigned timer_id, u32 frequency );
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// *****************************************************************************
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// Ethernet specific functions
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@ -3,11 +3,36 @@ require("LM3S")
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disp.init(1000000)
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disp.clear()
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adc.setmode(0,0)
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adc.setsmoothing(1,4)
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adc.setsmoothing(1,16)
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adc.setsmoothing(2,64)
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adc.setsmoothing(3,128)
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adcvals = {}
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ctr = 0
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while ( true ) do
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adc.start(0)
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adcval = adc.sample(0)
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outstring = string.format("ADC0: %04d",adcval)
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disp.stringdraw( outstring, 10, 10, 11 )
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ctr = ctr + 1
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stime = tmr.start(0)
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adcvals[0] = adc.sample(0)
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adcvals[1] = adc.sample(1)
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adcvals[2] = adc.sample(2)
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adcvals[3] = adc.sample(3)
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etime = tmr.read(0)
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dtime = tmr.diff(0,etime,stime)
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if ( ctr == 100 ) then
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ctr = 0
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outstring = string.format("ADC0 (4): %04d",adcvals[0])
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disp.stringdraw( outstring, 10, 10, 11 )
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outstring = string.format("ADC1 (16): %04d",adcvals[1])
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disp.stringdraw( outstring, 10, 20, 11 )
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outstring = string.format("ADC2 (64): %04d",adcvals[2])
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disp.stringdraw( outstring, 10, 30, 11 )
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outstring = string.format("ADC3 (128): %04d",adcvals[3])
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disp.stringdraw( outstring, 10, 40, 11 )
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outstring = string.format("Tcyc: %06d (us)",dtime)
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disp.stringdraw( outstring, 10, 50, 11 )
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end
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end
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14
src/common.c
14
src/common.c
@ -276,3 +276,17 @@ void* platform_get_last_free_ram( unsigned id )
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return id >= sizeof( mend ) / sizeof( void* ) ? NULL : mend[ id ];
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}
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// ****************************************************************************
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// Misc support
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unsigned int intlog2( unsigned int v )
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{
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unsigned r = 0;
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while (v >>= 1)
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{
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r++;
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}
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return r;
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}
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@ -21,31 +21,20 @@ static int adc_sample( lua_State* L )
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return 1;
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}
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// Lua: start( id )
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static int adc_start( lua_State* L )
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{
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unsigned id;
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id = luaL_checkinteger( L, 1 );
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MOD_CHECK_ID( adc, id );
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platform_adc_start( id );
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return 0;
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}
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// Lua: maxval( id )
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static int adc_maxval( lua_State* L)
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{
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unsigned id;
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u16 res;
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u32 res;
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id = luaL_checkinteger( L, 1 );
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MOD_CHECK_ID( adc, id );
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res = platform_adc_maxval( id );
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res = platform_adc_op( id, PLATFORM_ADC_GET_MAXVAL, 0 );
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lua_pushinteger( L, res );
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return 1;
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}
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// Lua: is_done( id )
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// Lua: isdone( id )
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static int adc_is_done( lua_State* L )
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{
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unsigned id;
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@ -58,7 +47,7 @@ static int adc_is_done( lua_State* L )
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return 1;
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}
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// Lua: set_mode( id, mode )
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// Lua: setmode( id, mode )
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static int adc_set_mode( lua_State* L )
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{
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unsigned id, mode;
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@ -70,16 +59,50 @@ static int adc_set_mode( lua_State* L )
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return 0;
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}
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// Lua: setsmoothing( id, length )
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static int adc_set_smoothing( lua_State* L )
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{
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unsigned id, length, res;
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id = luaL_checkinteger( L, 1 );
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MOD_CHECK_ID( adc, id );
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length = luaL_checkinteger( L, 2 );
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res = platform_adc_op( id, PLATFORM_ADC_SET_SMOOTHING, length );
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if ( res )
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return luaL_error( L, "Buffer allocation failed." );
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else
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return 0;
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}
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// Lua: getsmoothing( id )
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static int adc_get_smoothing( lua_State* L)
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{
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unsigned id;
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u32 res;
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id = luaL_checkinteger( L, 1 );
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MOD_CHECK_ID( adc, id );
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res = platform_adc_op( id, PLATFORM_ADC_GET_SMOOTHING, 0 );
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lua_pushinteger( L, res );
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return 1;
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}
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// Lua: adc_burst(id, buffer)
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//static int adc_burst( )
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//void platform_adc_burst( unsigned id, u16* buf, unsigned count, unsigned timer_id, u32 frequency )
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// Module function map
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#define MIN_OPT_LEVEL 2
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#include "lrodefs.h"
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const LUA_REG_TYPE adc_map[] =
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{
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{ LSTRKEY( "sample" ), LFUNCVAL( adc_sample ) },
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{ LSTRKEY( "start" ), LFUNCVAL( adc_start ) },
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{ LSTRKEY( "maxval" ), LFUNCVAL( adc_maxval ) },
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{ LSTRKEY( "isdone" ), LFUNCVAL( adc_is_done ) },
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{ LSTRKEY( "setmode" ), LFUNCVAL( adc_set_mode ) },
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{ LSTRKEY( "setsmoothing" ), LFUNCVAL( adc_set_smoothing ) },
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{ LSTRKEY( "getsmoothing" ), LFUNCVAL( adc_get_smoothing ) },
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{ LNILKEY, LNILVAL }
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};
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@ -9,6 +9,7 @@
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#include <string.h>
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#include <ctype.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include "uip_arp.h"
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#include "elua_uip.h"
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#include "uip-conf.h"
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@ -477,70 +478,233 @@ void platform_cpu_disable_interrupts()
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IntMasterDisable();
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}
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// *****************************************************************************
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// ADC specific functions
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// ADC specific functions and variables
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const static u32 adc_ctls[] = { ADC_CTL_CH0, ADC_CTL_CH1, ADC_CTL_CH2, ADC_CTL_CH3 };
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const static u32 adc_ints[] = { INT_ADC0, INT_ADC1, INT_ADC2, INT_ADC3 };
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struct platform_adc_state adc_state[ NUM_ADC ];
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static void adcs_init(unsigned id)
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// Handle ADC interrupts
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void ADCIntHandler( void )
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{
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SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC);
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}
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u16 platform_adc_sample( unsigned id ) /* sample the specified ADC channel */
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{
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u16 samplevalue;
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/* Wait for data if not ready */
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while(!ADCIntStatus(ADC_BASE, id, false))
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unsigned long samplevalue;
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unsigned id;
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// Check each sequence for a pending sample
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for( id = 0; id < NUM_ADC; id ++ )
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{
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if( ADCIntStatus(ADC_BASE, id, false) )
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{
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ADCIntClear(ADC_BASE, id);
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// Get samples
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ADCSequenceDataGet(ADC_BASE, id, &samplevalue);
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// Smooth data if needed
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if ( adc_state[id].smoothbuffsz > 1 )
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{
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if( adc_state[id].smoothbuffidx == adc_state[id].smoothbuffsz )
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{
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adc_state[id].smoothbuffidx = 0;
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}
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// Subtract Oldest Value from Sum
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adc_state[id].smoothingsum -= adc_state[id].smoothbuff[adc_state[id].smoothbuffidx];
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// Replace Oldest Value in Buffer
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adc_state[id].smoothbuff[adc_state[id].smoothbuffidx] = (u16) samplevalue;
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// Add New Sample to Sum
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adc_state[id].smoothingsum += adc_state[id].smoothbuff[adc_state[id].smoothbuffidx];
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adc_state[id].smoothbuffidx++;
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// Calculate Average
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if ( (adc_state[id].smoothbuffsz != 0) && \
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!(adc_state[id].smoothbuffsz & (adc_state[id].smoothbuffsz - 1)) )
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adc_state[id].smoothingav = adc_state[id].smoothingsum >> intlog2( adc_state[id].smoothbuffsz );
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else
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adc_state[id].smoothingav = adc_state[id].smoothingsum / adc_state[id].smoothbuffsz;
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adc_state[id].burstbuff[0] = (u16) adc_state[id].smoothingav;
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}
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else
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adc_state[id].burstbuff[0] = (u16) samplevalue;
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// Mark channel as no longer having a fresh sample, close pending state
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HWREGBITW( &adc_state[id].status, PLATFORM_ADC_CH_DATA_READY ) = 1;
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HWREGBITW( &adc_state[id].status, PLATFORM_ADC_CH_PENDING ) = 0;
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}
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}
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/* Get sample, comes back as unsigned long... */
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ADCSequenceDataGet(ADC_BASE, id, &samplevalue);
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return samplevalue;
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}
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void platform_adc_start( unsigned id ) /* starts a conversion on the specified ADC channel and returns immediately */
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static void adcs_init()
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{
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ADCSequenceEnable(ADC_BASE, id);
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ADCProcessorTrigger(ADC_BASE, id);
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unsigned id;
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SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC);
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for( id = 0; id < NUM_ADC; id ++ )
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{
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adc_state[id].status = 0x00;
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adc_state[id].burstbuffersz = 1;
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adc_state[id].burstbufferidx = 0;
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adc_state[id].smoothbuffsz = 1;
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adc_state[id].smoothbuffidx = 0;
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adc_state[id].smoothingav = 0;
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adc_state[id].smoothingsum = 0;
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adc_state[id].burstbuff = malloc( adc_state[id].burstbuffersz * sizeof( u16 ) );
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adc_state[id].smoothbuff = malloc( adc_state[id].smoothbuffsz * sizeof( u16 ) );
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// Make sure sequencer is disabled before making changes
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ADCSequenceDisable( ADC_BASE, id );
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// Conversion initiated on processor trigger
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ADCSequenceConfigure( ADC_BASE, id, ADC_TRIGGER_PROCESSOR, id ) ;
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// ADC_CTL_IE causes an interrupt to be fired when this step is complete
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// ADC_CTL_END causes this to be the last step to be taken in the sequence
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// Samples go into sequencer of the same number as input channel
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ADCSequenceStepConfigure( ADC_BASE, id, 0, ADC_CTL_IE | ADC_CTL_END | adc_ctls[id] );
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ADCIntEnable(ADC_BASE, id);
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IntEnable(adc_ints[id]);
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// Restart Sequencer
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ADCSequenceEnable( ADC_BASE, id );
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}
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}
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u16 platform_adc_maxval( unsigned id ) /* Returns maximum possible conversion value from ADC */
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u32 platform_adc_op( unsigned id, int op, u32 data ) // Move to common?
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{
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return pow(2,ADC_BIT_RESOLUTION)-1;
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// Do we really need 32-bit in and out?
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u32 res = 0;
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u8 ctr = 0;
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switch( op )
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{
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case PLATFORM_ADC_GET_MAXVAL:
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res = pow( 2,ADC_BIT_RESOLUTION ) - 1;
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break;
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case PLATFORM_ADC_GET_SMOOTHING:
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res = adc_state[id].smoothbuffsz;
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break;
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case PLATFORM_ADC_SET_SMOOTHING:
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// If buffer length changes, alloc new buffer, and reset position
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if( (u16) data != adc_state[id].smoothbuffsz )
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{
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adc_state[id].smoothbuffsz = (u16) data;
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// Free old buffer space
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free(adc_state[id].smoothbuff); // FIXME? Compiler complains
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// Reset sum, avg, index location
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adc_state[id].smoothbuffidx = 0;
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adc_state[id].smoothingav = 0;
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adc_state[id].smoothingsum = 0;
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// Allocate and zero new smoothing buffer
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if( ( adc_state[id].smoothbuff = malloc( adc_state[id].smoothbuffsz * sizeof( u16 ) ) ) == NULL )
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{
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return 1;
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}
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for( ctr = 0; ctr < adc_state[id].smoothbuffsz; ctr ++ )
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adc_state[id].smoothbuff[ctr] = 0;
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}
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break;
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}
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return res;
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}
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int platform_adc_is_done( unsigned id ) /* returns 1 if the conversion on the specified channel ended, 0 otherwise */
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// Get a single sample from the specified ADC channel
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u16 platform_adc_sample( unsigned id )
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{
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// If no sample is pending or if were configured for burst, set to single-shot
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if ( HWREGBITW( &adc_state[id].status, PLATFORM_ADC_CH_PENDING ) == 0 || \
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HWREGBITW( &adc_state[id].status, PLATFORM_ADC_CH_BURST ) == 1)
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{
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// Make sure sequencer is disabled before making changes
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ADCSequenceDisable( ADC_BASE, id );
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// Conversion initiated on processor trigger
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ADCSequenceConfigure( ADC_BASE, id, ADC_TRIGGER_PROCESSOR, id ) ;
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// Restart Sequencer
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ADCSequenceEnable( ADC_BASE, id);
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HWREGBITW( &adc_state[id].status, PLATFORM_ADC_CH_BURST ) = 0;
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}
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// Fire Trigger to start sample conversion
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HWREGBITW( &adc_state[id].status, PLATFORM_ADC_CH_PENDING ) = 1;
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ADCProcessorTrigger( ADC_BASE, id );
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// If in blocking mode and sample is pending, wait for ready flag
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if ( HWREGBITW( &adc_state[id].status, PLATFORM_ADC_CH_NONBLOCKING ) == 0 && \
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HWREGBITW( &adc_state[id].status, PLATFORM_ADC_CH_PENDING ) == 1 )
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{
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while ( HWREGBITW( &adc_state[id].status, PLATFORM_ADC_CH_DATA_READY ) == 0 ) { ; }
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}
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// If non-blocking we return whatever we have in the buffer
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// Mark sample as old, and return
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HWREGBITW( &adc_state[id].status, PLATFORM_ADC_CH_DATA_READY ) = 0;
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return adc_state[id].burstbuff[0];
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}
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// returns 1 if the conversion on the specified channel ended, 0 otherwise
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int platform_adc_is_done( unsigned id )
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{
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return HWREGBITW( &adc_state[id].status, PLATFORM_ADC_CH_DATA_READY );
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}
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// sets the mode on the specified ADC channel to either blocking (0) or non-blocking (1)
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void platform_adc_set_mode( unsigned id, int mode )
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{
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switch( mode )
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{
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case PLATFORM_ADC_BLOCKING:
|
||||
HWREGBITW( &adc_state[id].status, PLATFORM_ADC_CH_NONBLOCKING ) = 0;
|
||||
break;
|
||||
|
||||
case PLATFORM_ADC_NONBLOCKING:
|
||||
HWREGBITW( &adc_state[id].status, PLATFORM_ADC_CH_NONBLOCKING ) = 1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
// burst conversion: read "count" samples from the ADC channel "id", storing the results in "buf". The samples are read at periodic intervals, the period is given by "frequency".
|
||||
/* -- not ready yet --
|
||||
void platform_adc_burst( unsigned id, u16* buf, unsigned count, unsigned timer_id, u32 frequency )
|
||||
{
|
||||
return !ADCIntStatus(ADC_BASE, id, false);
|
||||
}
|
||||
|
||||
|
||||
void platform_adc_set_mode( unsigned id, int mode ) /* sets the mode on the specified ADC channel to either "single shot" or "continuous" */
|
||||
{
|
||||
/* currently mode is ignored... acquisition is currently just single-shot */
|
||||
|
||||
/* Stop sequencer we're going to adjust */
|
||||
ADCSequenceDisable(ADC_BASE, id);
|
||||
|
||||
/* Set sequence id to be triggered by processor, with priority id */
|
||||
ADCSequenceConfigure(ADC_BASE, id, ADC_TRIGGER_PROCESSOR, id);
|
||||
|
||||
/* ADC_CTL_IE causes an interrupt to be fired when this step is complete */
|
||||
/* ADC_CTL_END causes this to be the last step to be taken */
|
||||
ADCSequenceStepConfigure(ADC_BASE, id, 0, ADC_CTL_IE | ADC_CTL_END | adc_ctls[id]);
|
||||
}
|
||||
|
||||
void platform_adc_burst( unsigned id, u16* buf, unsigned count, u32 frequency ) /* burst conversion: read "count" samples from the ADC channel "id", storing the results in "buf". The samples are read at periodic intervals, the period is given by "frequency". */
|
||||
{
|
||||
/* not yet implemented */
|
||||
if( HWREGBITW( &adc_state[id].status, PLATFORM_ADC_CH_BURST ) == 0 )
|
||||
{
|
||||
// Make sure sequencer is disabled before making changes
|
||||
ADCSequenceDisable( ADC_BASE, id );
|
||||
|
||||
// Set sequence id to be triggered repeatedly, with priority id
|
||||
ADCSequenceConfigure( ADC_BASE, id, ADC_TRIGGER_TIMER, id ) ;
|
||||
|
||||
// Restart Sequencer
|
||||
ADCSequenceEnable( ADC_BASE, id );
|
||||
HWREGBITW( &adc_state[id].status, PLATFORM_ADC_CH_BURST ) = 1;
|
||||
}
|
||||
|
||||
HWREGBITW( &adc_state[id].status, PLATFORM_ADC_CH_PENDING ) = 1;
|
||||
|
||||
// Enable Timer
|
||||
TimerConfigure(timer_base[timer_id], TIMER_CFG_32_BIT_PER);
|
||||
TimerLoadSet(timer_base[timer_id], TIMER_A, SysCtlClockGet() / frequency);
|
||||
TimerControlTrigger(timer_base[timer_id], TIMER_A, true);
|
||||
}
|
||||
*/
|
||||
|
||||
// ****************************************************************************
|
||||
// OLED Display specific functions
|
||||
|
||||
@ -3,25 +3,25 @@
|
||||
// startup_gcc.c - Startup code for use with GNU tools.
|
||||
//
|
||||
// Copyright (c) 2007-2008 Luminary Micro, Inc. All rights reserved.
|
||||
//
|
||||
//
|
||||
// Software License Agreement
|
||||
//
|
||||
//
|
||||
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
|
||||
// exclusively on LMI's microcontroller products.
|
||||
//
|
||||
//
|
||||
// The software is owned by LMI and/or its suppliers, and is protected under
|
||||
// applicable copyright laws. All rights are reserved. You may not combine
|
||||
// this software with "viral" open-source software in order to form a larger
|
||||
// program. Any use in violation of the foregoing restrictions may subject
|
||||
// the user to criminal sanctions under applicable laws, as well as to civil
|
||||
// liability for the breach of the terms and conditions of this license.
|
||||
//
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
//
|
||||
//
|
||||
// This is part of revision 2752 of the Stellaris Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
@ -36,9 +36,10 @@ static void NmiSR(void);
|
||||
static void FaultISR(void);
|
||||
static void IntDefaultHandler(void);
|
||||
|
||||
// External interrupt handlers (used by Ethernet)
|
||||
// External interrupt handlers
|
||||
extern void EthernetIntHandler();
|
||||
extern void SysTickIntHandler();
|
||||
extern void SysTickIntHandler();
|
||||
extern void ADCIntHandler();
|
||||
|
||||
#include "hw_memmap.h"
|
||||
|
||||
@ -90,10 +91,10 @@ void (* const g_pfnVectors[])(void) =
|
||||
IntDefaultHandler, // PWM Generator 1
|
||||
IntDefaultHandler, // PWM Generator 2
|
||||
IntDefaultHandler, // Quadrature Encoder 0
|
||||
IntDefaultHandler, // ADC Sequence 0
|
||||
IntDefaultHandler, // ADC Sequence 1
|
||||
IntDefaultHandler, // ADC Sequence 2
|
||||
IntDefaultHandler, // ADC Sequence 3
|
||||
ADCIntHandler, // ADC Sequence 0
|
||||
ADCIntHandler, // ADC Sequence 1
|
||||
ADCIntHandler, // ADC Sequence 2
|
||||
ADCIntHandler, // ADC Sequence 3
|
||||
IntDefaultHandler, // Watchdog timer
|
||||
IntDefaultHandler, // Timer 0 subtimer A
|
||||
IntDefaultHandler, // Timer 0 subtimer B
|
||||
@ -177,7 +178,7 @@ ResetISR(void)
|
||||
// Call the application's entry point.
|
||||
//
|
||||
main();
|
||||
|
||||
|
||||
while(1);
|
||||
}
|
||||
|
||||
@ -223,13 +224,13 @@ FaultISR(void)
|
||||
//
|
||||
// Enter an infinite loop.
|
||||
//
|
||||
UARTCharPut( UART0_BASE, '#' );
|
||||
UARTCharPut( UART0_BASE, '#' );
|
||||
UARTCharPut( UART0_BASE, '#' );
|
||||
UARTCharPut( UART0_BASE, '#' );
|
||||
UARTCharPut( UART0_BASE, '#' );
|
||||
UARTCharPut( UART0_BASE, '#' );
|
||||
UARTCharPut( UART0_BASE, '#' );
|
||||
UARTCharPut( UART0_BASE, '#' );
|
||||
UARTCharPut( UART0_BASE, '#' );
|
||||
UARTCharPut( UART0_BASE, '#' );
|
||||
while(1)
|
||||
{
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
@ -248,6 +249,6 @@ IntDefaultHandler(void)
|
||||
//
|
||||
while(1)
|
||||
{
|
||||
UARTCharPut( UART0_BASE, '*' );
|
||||
UARTCharPut( UART0_BASE, '*' );
|
||||
}
|
||||
}
|
||||
|
||||
@ -10,7 +10,7 @@
|
||||
#include <ctype.h>
|
||||
#include <stdio.h>
|
||||
#include "uip_arp.h"
|
||||
#include "elua_uip.h"
|
||||
#include "elua_uip.h"
|
||||
#include "uip-conf.h"
|
||||
#include "platform_conf.h"
|
||||
#include "common.h"
|
||||
@ -55,7 +55,7 @@ static void pwms_init();
|
||||
static void eth_init();
|
||||
|
||||
int platform_init()
|
||||
{
|
||||
{
|
||||
// Set the clocking to run from PLL
|
||||
RCC_Configuration();
|
||||
|
||||
@ -81,19 +81,19 @@ int platform_init()
|
||||
#endif
|
||||
|
||||
// Setup timers
|
||||
//timers_init();
|
||||
//timers_init();
|
||||
|
||||
// Setup PWMs
|
||||
//pwms_init();
|
||||
//pwms_init();
|
||||
|
||||
// Setup ethernet (TCP/IP)
|
||||
//eth_init();
|
||||
|
||||
cmn_platform_init();
|
||||
|
||||
|
||||
// All done
|
||||
return PLATFORM_OK;
|
||||
}
|
||||
}
|
||||
|
||||
// ****************************************************************************
|
||||
// Clocks
|
||||
@ -126,12 +126,12 @@ static void RCC_Configuration(void)
|
||||
|
||||
/* Flash 2 wait state */
|
||||
FLASH_SetLatency(FLASH_Latency_2);
|
||||
|
||||
|
||||
/* HCLK = SYSCLK */
|
||||
RCC_HCLKConfig(RCC_SYSCLK_Div1);
|
||||
|
||||
RCC_HCLKConfig(RCC_SYSCLK_Div1);
|
||||
|
||||
/* PCLK2 = HCLK */
|
||||
RCC_PCLK2Config(RCC_HCLK_Div1);
|
||||
RCC_PCLK2Config(RCC_HCLK_Div1);
|
||||
|
||||
/* PCLK1 = HCLK/2 */
|
||||
RCC_PCLK1Config(RCC_HCLK_Div2);
|
||||
@ -139,7 +139,7 @@ static void RCC_Configuration(void)
|
||||
/* PLLCLK = 8MHz * 9 = 72 MHz */
|
||||
RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_9);
|
||||
|
||||
/* Enable PLL */
|
||||
/* Enable PLL */
|
||||
RCC_PLLCmd(ENABLE);
|
||||
|
||||
/* Wait till PLL is ready */
|
||||
@ -154,8 +154,8 @@ static void RCC_Configuration(void)
|
||||
while(RCC_GetSYSCLKSource() != 0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE);
|
||||
}
|
||||
|
||||
@ -176,15 +176,15 @@ static void NVIC_Configuration(void)
|
||||
|
||||
NVIC_DeInit();
|
||||
|
||||
#ifdef VECT_TAB_RAM
|
||||
/* Set the Vector Table base location at 0x20000000 */
|
||||
NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0);
|
||||
#ifdef VECT_TAB_RAM
|
||||
/* Set the Vector Table base location at 0x20000000 */
|
||||
NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0);
|
||||
#else /* VECT_TAB_FLASH */
|
||||
/* Set the Vector Table base location at 0x08000000 */
|
||||
NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);
|
||||
#endif
|
||||
/* Set the Vector Table base location at 0x08000000 */
|
||||
NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);
|
||||
#endif
|
||||
|
||||
/* Configure the NVIC Preemption Priority Bits */
|
||||
/* Configure the NVIC Preemption Priority Bits */
|
||||
NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
|
||||
|
||||
/* Configure the SysTick handler priority */
|
||||
@ -208,11 +208,11 @@ static void pios_init()
|
||||
{
|
||||
// Enable clock to port.
|
||||
RCC_APB2PeriphClockCmd(pio_port_clk[port], ENABLE);
|
||||
|
||||
|
||||
// Default all port pins to input and enable port.
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_All;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
|
||||
|
||||
|
||||
GPIO_Init(pio_port[port], &GPIO_InitStructure);
|
||||
}
|
||||
}
|
||||
@ -222,69 +222,69 @@ pio_type platform_pio_op( unsigned port, pio_type pinmask, int op )
|
||||
pio_type retval = 1;
|
||||
GPIO_InitTypeDef GPIO_InitStructure;
|
||||
GPIO_TypeDef * base = pio_port[ port ];
|
||||
|
||||
|
||||
switch( op )
|
||||
{
|
||||
case PLATFORM_IO_PORT_SET_VALUE:
|
||||
case PLATFORM_IO_PORT_SET_VALUE:
|
||||
GPIO_Write(base, pinmask);
|
||||
break;
|
||||
|
||||
|
||||
case PLATFORM_IO_PIN_SET:
|
||||
GPIO_SetBits(base, pinmask);
|
||||
break;
|
||||
|
||||
|
||||
case PLATFORM_IO_PIN_CLEAR:
|
||||
GPIO_ResetBits(base, pinmask);
|
||||
break;
|
||||
|
||||
|
||||
case PLATFORM_IO_PORT_DIR_INPUT:
|
||||
pinmask = GPIO_Pin_All;
|
||||
pinmask = GPIO_Pin_All;
|
||||
case PLATFORM_IO_PIN_DIR_INPUT:
|
||||
GPIO_InitStructure.GPIO_Pin = pinmask;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
|
||||
|
||||
|
||||
GPIO_Init(base, &GPIO_InitStructure);
|
||||
break;
|
||||
|
||||
case PLATFORM_IO_PORT_DIR_OUTPUT:
|
||||
|
||||
case PLATFORM_IO_PORT_DIR_OUTPUT:
|
||||
pinmask = GPIO_Pin_All;
|
||||
case PLATFORM_IO_PIN_DIR_OUTPUT:
|
||||
GPIO_InitStructure.GPIO_Pin = pinmask;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
|
||||
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
||||
|
||||
|
||||
GPIO_Init(base, &GPIO_InitStructure);
|
||||
break;
|
||||
|
||||
break;
|
||||
|
||||
case PLATFORM_IO_PORT_GET_VALUE:
|
||||
retval = GPIO_ReadInputData(base);
|
||||
break;
|
||||
|
||||
|
||||
case PLATFORM_IO_PIN_GET:
|
||||
retval = GPIO_ReadInputDataBit(base, pinmask);
|
||||
break;
|
||||
|
||||
|
||||
case PLATFORM_IO_PIN_PULLUP:
|
||||
GPIO_InitStructure.GPIO_Pin = pinmask;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||
|
||||
|
||||
GPIO_Init(base, &GPIO_InitStructure);
|
||||
break;
|
||||
|
||||
|
||||
case PLATFORM_IO_PIN_PULLDOWN:
|
||||
GPIO_InitStructure.GPIO_Pin = pinmask;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD;
|
||||
|
||||
|
||||
GPIO_Init(base, &GPIO_InitStructure);
|
||||
break;
|
||||
|
||||
|
||||
case PLATFORM_IO_PIN_NOPULL:
|
||||
GPIO_InitStructure.GPIO_Pin = pinmask;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
|
||||
|
||||
|
||||
GPIO_Init(base, &GPIO_InitStructure);
|
||||
break;
|
||||
|
||||
|
||||
default:
|
||||
retval = 0;
|
||||
break;
|
||||
@ -325,18 +325,18 @@ int platform_spi_exists( unsigned id )
|
||||
u32 platform_spi_setup( unsigned id, int mode, u32 clock, unsigned cpol, unsigned cpha, unsigned databits )
|
||||
{
|
||||
unsigned protocol;
|
||||
|
||||
|
||||
if( cpol == 0 )
|
||||
protocol = cpha ? SSI_FRF_MOTO_MODE_1 : SSI_FRF_MOTO_MODE_0;
|
||||
else
|
||||
protocol = cpha ? SSI_FRF_MOTO_MODE_3 : SSI_FRF_MOTO_MODE_2;
|
||||
mode = mode == PLATFORM_SPI_MASTER ? SSI_MODE_MASTER : SSI_MODE_SLAVE;
|
||||
mode = mode == PLATFORM_SPI_MASTER ? SSI_MODE_MASTER : SSI_MODE_SLAVE;
|
||||
SSIDisable( spi_base[ id ] );
|
||||
|
||||
GPIOPinTypeSSI( spi_gpio_base[ id ], spi_gpio_pins[ id ] );
|
||||
|
||||
|
||||
// FIXME: not sure this is always "right"
|
||||
GPIOPadConfigSet(spi_gpio_base[ id ], spi_gpio_clk_pin[ id ], GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD_WPU);
|
||||
GPIOPadConfigSet(spi_gpio_base[ id ], spi_gpio_clk_pin[ id ], GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD_WPU);
|
||||
|
||||
SSIConfigSetExpClk( spi_base[ id ], SysCtlClockGet(), protocol, mode, clock, databits );
|
||||
SSIEnable( spi_base[ id ] );
|
||||
@ -352,7 +352,7 @@ spi_data_type platform_spi_send_recv( unsigned id, spi_data_type data )
|
||||
|
||||
void platform_spi_select( unsigned id, int is_select )
|
||||
{
|
||||
// This platform doesn't have a hardware SS pin, so there's nothing to do here
|
||||
// This platform doesn't have a hardware SS pin, so there's nothing to do here
|
||||
id = id;
|
||||
is_select = is_select;
|
||||
}
|
||||
@ -390,7 +390,7 @@ static void usart_init(u32 id, USART_InitTypeDef * initVals)
|
||||
|
||||
/* Configure USART */
|
||||
USART_Init(usart[id], initVals);
|
||||
|
||||
|
||||
/* Enable USART1 Receive and Transmit interrupts */
|
||||
//USART_ITConfig(usart[id], USART_IT_RXNE, ENABLE);
|
||||
//USART_ITConfig(usart[id], USART_IT_TXE, ENABLE);
|
||||
@ -408,7 +408,7 @@ static void uarts_init()
|
||||
RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);
|
||||
RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE);
|
||||
RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART4, ENABLE);
|
||||
|
||||
|
||||
// Configure the U(S)ART for 115,200, 8-N-1 operation.
|
||||
|
||||
USART_InitStructure.USART_BaudRate = CON_UART_SPEED;
|
||||
@ -426,10 +426,10 @@ u32 platform_uart_setup( unsigned id, u32 baud, int databits, int parity, int st
|
||||
USART_InitTypeDef USART_InitStructure;
|
||||
|
||||
USART_InitStructure.USART_BaudRate = baud;
|
||||
|
||||
|
||||
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
|
||||
USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
|
||||
|
||||
|
||||
switch( databits )
|
||||
{
|
||||
case 5:
|
||||
@ -457,7 +457,7 @@ u32 platform_uart_setup( unsigned id, u32 baud, int databits, int parity, int st
|
||||
default:
|
||||
USART_InitStructure.USART_StopBits = USART_StopBits_2;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
switch (parity)
|
||||
{
|
||||
@ -471,9 +471,9 @@ u32 platform_uart_setup( unsigned id, u32 baud, int databits, int parity, int st
|
||||
USART_InitStructure.USART_Parity = USART_Parity_No;
|
||||
break;
|
||||
}
|
||||
|
||||
|
||||
usart_init(id, &USART_InitStructure);
|
||||
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
@ -492,18 +492,17 @@ int platform_s_uart_recv( unsigned id, s32 timeout )
|
||||
if (USART_GetFlagStatus(usart[id], USART_FLAG_RXNE) == RESET)
|
||||
return -1;
|
||||
else
|
||||
return USART_ReceiveData(usart[id]);
|
||||
return USART_ReceiveData(usart[id]);
|
||||
}
|
||||
// Receive char blocking
|
||||
while(USART_GetFlagStatus(usart[id], USART_FLAG_RXNE) == RESET);
|
||||
return USART_ReceiveData(usart[id]);
|
||||
return USART_ReceiveData(usart[id]);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef STM32_USE_TIMERS
|
||||
// ****************************************************************************
|
||||
// Timers
|
||||
// Same on LM3S8962 and LM3S6965
|
||||
|
||||
// All possible LM3S timers defs
|
||||
static TIM_TypeDef * timer[] = { TIM2, TIM3, TIM4, TIM5};
|
||||
@ -544,9 +543,9 @@ static u32 platform_timer_set_clock(unsigned id, u32 clock)
|
||||
clkdiv = ((tmp & 0x8000) ? (tmp + 0x10000) : tmp) >> 16; // Round up or down and convert back to u32.0
|
||||
if (clkdiv > 0x10000) // Saturate to u16 (+1 for a clkdiv value of 1 is a reg value of 0)
|
||||
clkdiv = 0x10000;
|
||||
|
||||
|
||||
TIM_PrescalerConfig(timer[id], clkdiv - 1, TIM_PSCReloadMode_Immediate); // Update timer prescaler immediately
|
||||
|
||||
|
||||
return pclk / clkdiv; // Return actual clock rate used.
|
||||
}
|
||||
|
||||
@ -554,17 +553,17 @@ void platform_s_timer_delay( unsigned id, u32 delay_us )
|
||||
{
|
||||
timer_data_type final;
|
||||
u32 base = timer_base[ id ];
|
||||
|
||||
|
||||
final = 0xFFFFFFFF - ( ( ( u64 )delay_us * SysCtlClockGet() ) / 1000000 );
|
||||
TimerLoadSet( base, TIMER_A, 0xFFFFFFFF );
|
||||
while( TimerValueGet( base, TIMER_A ) > final );
|
||||
}
|
||||
|
||||
|
||||
u32 platform_s_timer_op( unsigned id, int op, u32 data )
|
||||
{
|
||||
u32 res = 0;
|
||||
u32 base = timer_base[ id ];
|
||||
|
||||
u32 base = timer_base[ id ];
|
||||
|
||||
data = data;
|
||||
switch( op )
|
||||
{
|
||||
@ -572,24 +571,24 @@ u32 platform_s_timer_op( unsigned id, int op, u32 data )
|
||||
res = 0xFFFFFFFF;
|
||||
TimerLoadSet( base, TIMER_A, 0xFFFFFFFF );
|
||||
break;
|
||||
|
||||
|
||||
case PLATFORM_TIMER_OP_READ:
|
||||
res = TimerValueGet( base, TIMER_A );
|
||||
break;
|
||||
|
||||
|
||||
case PLATFORM_TIMER_OP_GET_MAX_DELAY:
|
||||
res = platform_timer_get_diff_us( id, 0, 0xFFFFFFFF );
|
||||
break;
|
||||
|
||||
|
||||
case PLATFORM_TIMER_OP_GET_MIN_DELAY:
|
||||
res = platform_timer_get_diff_us( id, 0, 1 );
|
||||
break;
|
||||
|
||||
|
||||
case PLATFORM_TIMER_OP_SET_CLOCK:
|
||||
case PLATFORM_TIMER_OP_GET_CLOCK:
|
||||
res = SysCtlClockGet();
|
||||
break;
|
||||
|
||||
|
||||
}
|
||||
return res;
|
||||
}
|
||||
@ -629,7 +628,7 @@ static u32 platform_pwm_get_clock()
|
||||
{
|
||||
unsigned i;
|
||||
u32 clk;
|
||||
|
||||
|
||||
clk = SysCtlPWMClockGet();
|
||||
for( i = 0; i < sizeof( pwm_div_ctl ) / sizeof( u32 ); i ++ )
|
||||
if( clk == pwm_div_ctl[ i ] )
|
||||
@ -642,7 +641,7 @@ static u32 platform_pwm_set_clock( u32 clock )
|
||||
{
|
||||
unsigned i, min_i;
|
||||
u32 sysclk;
|
||||
|
||||
|
||||
sysclk = SysCtlClockGet();
|
||||
for( i = min_i = 0; i < sizeof( pwm_div_data ) / sizeof( u8 ); i ++ )
|
||||
if( ABSDIFF( clock, sysclk / pwm_div_data[ i ] ) < ABSDIFF( clock, sysclk / pwm_div_data[ min_i ] ) )
|
||||
@ -653,14 +652,14 @@ static u32 platform_pwm_set_clock( u32 clock )
|
||||
|
||||
int platform_pwm_exists( unsigned id )
|
||||
{
|
||||
return id < PLATFORM_NUM_PWMS;
|
||||
return id < PLATFORM_NUM_PWMS;
|
||||
}
|
||||
|
||||
u32 platform_pwm_setup( unsigned id, u32 frequency, unsigned duty )
|
||||
{
|
||||
u32 pwmclk = platform_pwm_get_clock();
|
||||
u32 period;
|
||||
|
||||
|
||||
// Set pin as PWM
|
||||
GPIOPinTypePWM( pwm_ports[ id ], pwm_pins[ id ] );
|
||||
// Compute period
|
||||
@ -677,28 +676,28 @@ u32 platform_pwm_setup( unsigned id, u32 frequency, unsigned duty )
|
||||
u32 platform_pwm_op( unsigned id, int op, u32 data )
|
||||
{
|
||||
u32 res = 0;
|
||||
|
||||
|
||||
switch( op )
|
||||
{
|
||||
case PLATFORM_PWM_OP_SET_CLOCK:
|
||||
res = platform_pwm_set_clock( data );
|
||||
break;
|
||||
|
||||
|
||||
case PLATFORM_PWM_OP_GET_CLOCK:
|
||||
res = platform_pwm_get_clock();
|
||||
break;
|
||||
|
||||
|
||||
case PLATFORM_PWM_OP_START:
|
||||
PWMOutputState( PWM_BASE, 1 << id, true );
|
||||
PWMGenEnable( PWM_BASE, pwm_gens[ id >> 1 ] );
|
||||
break;
|
||||
|
||||
|
||||
case PLATFORM_PWM_OP_STOP:
|
||||
PWMOutputState( PWM_BASE, 1 << id, false );
|
||||
PWMGenDisable( PWM_BASE, pwm_gens[ id >> 1 ] );
|
||||
break;
|
||||
}
|
||||
|
||||
|
||||
return res;
|
||||
}
|
||||
#endif
|
||||
@ -750,12 +749,12 @@ static void eth_init()
|
||||
{
|
||||
#ifdef BUILD_UIP
|
||||
u32 user0, user1, temp;
|
||||
static struct uip_eth_addr sTempAddr;
|
||||
|
||||
static struct uip_eth_addr sTempAddr;
|
||||
|
||||
// Enable and reset the controller
|
||||
SysCtlPeripheralEnable( SYSCTL_PERIPH_ETH );
|
||||
SysCtlPeripheralReset( SYSCTL_PERIPH_ETH );
|
||||
|
||||
|
||||
// Enable Ethernet LEDs
|
||||
GPIODirModeSet( GPIO_PORTF_BASE, GPIO_PIN_2 | GPIO_PIN_3, GPIO_DIR_MODE_HW );
|
||||
GPIOPadConfigSet( GPIO_PORTF_BASE, GPIO_PIN_2 | GPIO_PIN_3, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD );
|
||||
@ -764,13 +763,13 @@ static void eth_init()
|
||||
SysTickPeriodSet(SysCtlClockGet() / SYSTICKHZ);
|
||||
SysTickEnable();
|
||||
SysTickIntEnable();
|
||||
|
||||
|
||||
// Intialize the Ethernet Controller and disable all Ethernet Controller interrupt sources.
|
||||
EthernetIntDisable(ETH_BASE, (ETH_INT_PHY | ETH_INT_MDIO | ETH_INT_RXER |
|
||||
ETH_INT_RXOF | ETH_INT_TX | ETH_INT_TXER | ETH_INT_RX));
|
||||
temp = EthernetIntStatus(ETH_BASE, false);
|
||||
EthernetIntClear(ETH_BASE, temp);
|
||||
|
||||
EthernetIntClear(ETH_BASE, temp);
|
||||
|
||||
// Initialize the Ethernet Controller for operation.
|
||||
EthernetInitExpClk(ETH_BASE, SysCtlClockGet());
|
||||
|
||||
@ -788,7 +787,7 @@ static void eth_init()
|
||||
IntEnable(INT_ETH);
|
||||
|
||||
// Enable the Ethernet RX Packet interrupt source.
|
||||
EthernetIntEnable(ETH_BASE, ETH_INT_RX);
|
||||
EthernetIntEnable(ETH_BASE, ETH_INT_RX);
|
||||
|
||||
// Enable all processor interrupts.
|
||||
IntMasterEnable();
|
||||
@ -800,7 +799,7 @@ static void eth_init()
|
||||
// non-volatile USER0 and USER1 registers. These registers can be read
|
||||
// using the FlashUserGet function, as illustrated below.
|
||||
FlashUserGet(&user0, &user1);
|
||||
|
||||
|
||||
// Convert the 24/24 split MAC address from NV ram into a 32/16 split MAC
|
||||
// address needed to program the hardware registers, then program the MAC
|
||||
// address into the Ethernet Controller registers.
|
||||
@ -809,10 +808,10 @@ static void eth_init()
|
||||
sTempAddr.addr[2] = ((user0 >> 16) & 0xff);
|
||||
sTempAddr.addr[3] = ((user1 >> 0) & 0xff);
|
||||
sTempAddr.addr[4] = ((user1 >> 8) & 0xff);
|
||||
sTempAddr.addr[5] = ((user1 >> 16) & 0xff);
|
||||
sTempAddr.addr[5] = ((user1 >> 16) & 0xff);
|
||||
|
||||
// Program the hardware with it's MAC address (for filtering).
|
||||
EthernetMACAddrSet(ETH_BASE, (unsigned char *)&sTempAddr);
|
||||
EthernetMACAddrSet(ETH_BASE, (unsigned char *)&sTempAddr);
|
||||
|
||||
// Initialize the eLua uIP layer
|
||||
elua_uip_init( &sTempAddr );
|
||||
@ -824,7 +823,7 @@ static int eth_timer_fired;
|
||||
|
||||
void platform_eth_send_packet( const void* src, u32 size )
|
||||
{
|
||||
EthernetPacketPut( ETH_BASE, uip_buf, uip_len );
|
||||
EthernetPacketPut( ETH_BASE, uip_buf, uip_len );
|
||||
}
|
||||
|
||||
u32 platform_eth_get_packet_nb( void* buf, u32 maxlen )
|
||||
@ -834,7 +833,7 @@ u32 platform_eth_get_packet_nb( void* buf, u32 maxlen )
|
||||
|
||||
void platform_eth_force_interrupt()
|
||||
{
|
||||
HWREG( NVIC_SW_TRIG) |= INT_ETH - 16;
|
||||
HWREG( NVIC_SW_TRIG) |= INT_ETH - 16;
|
||||
}
|
||||
|
||||
u32 platform_eth_get_elapsed_time()
|
||||
@ -863,12 +862,12 @@ void SysTickHandler(void)
|
||||
void EthernetIntHandler()
|
||||
{
|
||||
u32 temp;
|
||||
|
||||
|
||||
// Read and Clear the interrupt.
|
||||
temp = EthernetIntStatus( ETH_BASE, false );
|
||||
EthernetIntClear( ETH_BASE, temp );
|
||||
|
||||
// Call the UIP main loop
|
||||
// Call the UIP main loop
|
||||
elua_uip_mainloop();
|
||||
}
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user