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fix typo in cyclic interrupt handling on stm32, don't enable interrupt by default.. require sei

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This commit is contained in:
James Snyder 2011-08-01 21:09:21 -05:00
parent e64f9ef3bb
commit ee759a1c4b
2 changed files with 8 additions and 3 deletions
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5
src/platform/stm32/platform.c
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@ -839,6 +839,9 @@ int platform_s_timer_set_match_int( unsigned id, u32 period_us, int type )
TIM_OCInitStructure.TIM_Pulse = final; TIM_OCInitStructure.TIM_Pulse = final;
TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High; TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;
TIM_OC1Init( base, &TIM_OCInitStructure ); TIM_OC1Init( base, &TIM_OCInitStructure );
// Patch timer configuration to reload when period is reached
TIM_SetAutoreload( base, final );
TIM_OC1PreloadConfig( base, TIM_OCPreload_Enable ); TIM_OC1PreloadConfig( base, TIM_OCPreload_Enable );
@ -846,7 +849,7 @@ int platform_s_timer_set_match_int( unsigned id, u32 period_us, int type )
TIM_SetCounter( base, 0 ); TIM_SetCounter( base, 0 );
TIM_Cmd( base, ENABLE ); TIM_Cmd( base, ENABLE );
TIM_ITConfig( base, TIM_IT_CC1, ENABLE ); //TIM_ITConfig( base, TIM_IT_CC1, ENABLE );
return PLATFORM_TIMER_INT_OK; return PLATFORM_TIMER_INT_OK;
} }

6
src/platform/stm32/platform_int.c
View File

@ -145,12 +145,14 @@ static void tmr_int_handler( int id )
if (TIM_GetITStatus( base, TIM_IT_CC1) != RESET) if (TIM_GetITStatus( base, TIM_IT_CC1) != RESET)
{ {
TIM_ClearITPendingBit( base, TIM_IT_CC1 ); TIM_ClearITPendingBit( base, TIM_IT_CC1 );
if( id == VTMR_TIMER_ID ) if( id == VTMR_TIMER_ID )
cmn_virtual_timer_cb(); cmn_virtual_timer_cb();
else else
cmn_int_handler( INT_TMR_MATCH, id ); cmn_int_handler( INT_TMR_MATCH, id );
if( stm32_timer_int_periodic_flag[ id ] != PLATFORM_TIMER_INT_CYCLIC );
//TIM_ITConfig( base, TIM_IT_CC1, DISABLE ); if( stm32_timer_int_periodic_flag[ id ] != PLATFORM_TIMER_INT_CYCLIC )
TIM_ITConfig( base, TIM_IT_CC1, DISABLE );
} }
} }