mirror of
https://github.com/GorgonMeducer/perf_counter.git
synced 2025-01-17 19:13:03 +08:00
187 lines
9.6 KiB
C
187 lines
9.6 KiB
C
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/*****************************************************************************
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* Copyright(C)2009-2019 by VSF Team *
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* *
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* Licensed under the Apache License, Version 2.0 (the "License"); *
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* you may not use this file except in compliance with the License. *
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* You may obtain a copy of the License at *
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* *
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* http://www.apache.org/licenses/LICENSE-2.0 *
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* *
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* Unless required by applicable law or agreed to in writing, software *
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* distributed under the License is distributed on an "AS IS" BASIS, *
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. *
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* See the License for the specific language governing permissions and *
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* limitations under the License. *
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* *
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****************************************************************************/
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#include <stdint.h>
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#include <stdbool.h>
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#include <stdio.h>
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#include "cmsis_compiler.h"
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/* IO definitions (access restrictions to peripheral registers) */
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/**
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\defgroup CMSIS_glob_defs CMSIS Global Defines
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<strong>IO Type Qualifiers</strong> are used
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\li to specify the access to peripheral variables.
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\li for automatic generation of peripheral register debug information.
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*/
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#ifdef __cplusplus
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#define __I volatile /*!< Defines 'read only' permissions */
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#else
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#define __I volatile const /*!< Defines 'read only' permissions */
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#endif
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#define __O volatile /*!< Defines 'write only' permissions */
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#define __IO volatile /*!< Defines 'read / write' permissions */
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/* following defines should be used for structure members */
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#define __IM volatile const /*! Defines 'read only' structure member permissions */
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#define __OM volatile /*! Defines 'write only' structure member permissions */
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#define __IOM volatile /*! Defines 'read / write' structure member permissions */
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/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
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typedef struct
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{
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__IOM uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */
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__IOM uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */
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__IOM uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */
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union {
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__IM uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */
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__OM uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */
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};
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__IOM uint32_t BAUDDIV; /* Offset: 0x010 (R/W) Baudrate Divider Register */
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} CMSDK_UART_TypeDef;
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/* CMSDK_UART DATA Register Definitions */
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#define CMSDK_UART_DATA_Pos 0 /* CMSDK_UART_DATA_Pos: DATA Position */
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#define CMSDK_UART_DATA_Msk (0xFFUL /*<< CMSDK_UART_DATA_Pos*/) /* CMSDK_UART DATA: DATA Mask */
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/* CMSDK_UART STATE Register Definitions */
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#define CMSDK_UART_STATE_RXOR_Pos 3 /* CMSDK_UART STATE: RXOR Position */
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#define CMSDK_UART_STATE_RXOR_Msk (0x1UL << CMSDK_UART_STATE_RXOR_Pos) /* CMSDK_UART STATE: RXOR Mask */
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#define CMSDK_UART_STATE_TXOR_Pos 2 /* CMSDK_UART STATE: TXOR Position */
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#define CMSDK_UART_STATE_TXOR_Msk (0x1UL << CMSDK_UART_STATE_TXOR_Pos) /* CMSDK_UART STATE: TXOR Mask */
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#define CMSDK_UART_STATE_RXBF_Pos 1 /* CMSDK_UART STATE: RXBF Position */
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#define CMSDK_UART_STATE_RXBF_Msk (0x1UL << CMSDK_UART_STATE_RXBF_Pos) /* CMSDK_UART STATE: RXBF Mask */
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#define CMSDK_UART_STATE_TXBF_Pos 0 /* CMSDK_UART STATE: TXBF Position */
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#define CMSDK_UART_STATE_TXBF_Msk (0x1UL /*<< CMSDK_UART_STATE_TXBF_Pos*/) /* CMSDK_UART STATE: TXBF Mask */
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/* CMSDK_UART CTRL Register Definitions */
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#define CMSDK_UART_CTRL_HSTM_Pos 6 /* CMSDK_UART CTRL: HSTM Position */
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#define CMSDK_UART_CTRL_HSTM_Msk (0x01UL << CMSDK_UART_CTRL_HSTM_Pos) /* CMSDK_UART CTRL: HSTM Mask */
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#define CMSDK_UART_CTRL_RXORIRQEN_Pos 5 /* CMSDK_UART CTRL: RXORIRQEN Position */
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#define CMSDK_UART_CTRL_RXORIRQEN_Msk (0x01UL << CMSDK_UART_CTRL_RXORIRQEN_Pos) /* CMSDK_UART CTRL: RXORIRQEN Mask */
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#define CMSDK_UART_CTRL_TXORIRQEN_Pos 4 /* CMSDK_UART CTRL: TXORIRQEN Position */
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#define CMSDK_UART_CTRL_TXORIRQEN_Msk (0x01UL << CMSDK_UART_CTRL_TXORIRQEN_Pos) /* CMSDK_UART CTRL: TXORIRQEN Mask */
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#define CMSDK_UART_CTRL_RXIRQEN_Pos 3 /* CMSDK_UART CTRL: RXIRQEN Position */
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#define CMSDK_UART_CTRL_RXIRQEN_Msk (0x01UL << CMSDK_UART_CTRL_RXIRQEN_Pos) /* CMSDK_UART CTRL: RXIRQEN Mask */
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#define CMSDK_UART_CTRL_TXIRQEN_Pos 2 /* CMSDK_UART CTRL: TXIRQEN Position */
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#define CMSDK_UART_CTRL_TXIRQEN_Msk (0x01UL << CMSDK_UART_CTRL_TXIRQEN_Pos) /* CMSDK_UART CTRL: TXIRQEN Mask */
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#define CMSDK_UART_CTRL_RXEN_Pos 1 /* CMSDK_UART CTRL: RXEN Position */
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#define CMSDK_UART_CTRL_RXEN_Msk (0x01UL << CMSDK_UART_CTRL_RXEN_Pos) /* CMSDK_UART CTRL: RXEN Mask */
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#define CMSDK_UART_CTRL_TXEN_Pos 0 /* CMSDK_UART CTRL: TXEN Position */
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#define CMSDK_UART_CTRL_TXEN_Msk (0x01UL /*<< CMSDK_UART_CTRL_TXEN_Pos*/) /* CMSDK_UART CTRL: TXEN Mask */
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#define CMSDK_UART_INTSTATUS_RXORIRQ_Pos 3 /* CMSDK_UART CTRL: RXORIRQ Position */
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#define CMSDK_UART_CTRL_RXORIRQ_Msk (0x01UL << CMSDK_UART_INTSTATUS_RXORIRQ_Pos) /* CMSDK_UART CTRL: RXORIRQ Mask */
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#define CMSDK_UART_CTRL_TXORIRQ_Pos 2 /* CMSDK_UART CTRL: TXORIRQ Position */
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#define CMSDK_UART_CTRL_TXORIRQ_Msk (0x01UL << CMSDK_UART_CTRL_TXORIRQ_Pos) /* CMSDK_UART CTRL: TXORIRQ Mask */
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#define CMSDK_UART_CTRL_RXIRQ_Pos 1 /* CMSDK_UART CTRL: RXIRQ Position */
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#define CMSDK_UART_CTRL_RXIRQ_Msk (0x01UL << CMSDK_UART_CTRL_RXIRQ_Pos) /* CMSDK_UART CTRL: RXIRQ Mask */
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#define CMSDK_UART_CTRL_TXIRQ_Pos 0 /* CMSDK_UART CTRL: TXIRQ Position */
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#define CMSDK_UART_CTRL_TXIRQ_Msk (0x01UL /*<< CMSDK_UART_CTRL_TXIRQ_Pos*/) /* CMSDK_UART CTRL: TXIRQ Mask */
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/* CMSDK_UART BAUDDIV Register Definitions */
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#define CMSDK_UART_BAUDDIV_Pos 0 /* CMSDK_UART BAUDDIV: BAUDDIV Position */
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#define CMSDK_UART_BAUDDIV_Msk (0xFFFFFUL /*<< CMSDK_UART_BAUDDIV_Pos*/) /* CMSDK_UART BAUDDIV: BAUDDIV Mask */
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/* ================================================================================ */
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/* ================ Peripheral declaration ================ */
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/* ================================================================================ */
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//#define CMSDK_UART0_BASE_ADDRESS (0x41303000ul)
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#define CMSDK_UART0_BASE_ADDRESS (0x40004000ul)
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#define CMSDK_UART0 ((CMSDK_UART_TypeDef *) CMSDK_UART0_BASE_ADDRESS)
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void uart_config(uint32_t wUARTFrequency)
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{
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CMSDK_UART0->CTRL = 0; /* Disable UART when changing configuration */
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CMSDK_UART0->BAUDDIV = wUARTFrequency / 115200ul; /* 25MHz / 38400 = 651 */
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CMSDK_UART0->CTRL = CMSDK_UART_CTRL_TXEN_Msk|CMSDK_UART_CTRL_RXEN_Msk;
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}
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char stdin_getchar(void)
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{
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while(!(CMSDK_UART0->STATE & CMSDK_UART_STATE_RXBF_Msk));
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return (char)(CMSDK_UART0->DATA);
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}
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int stdout_putchar(char txchar)
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{
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if (txchar == 10) stdout_putchar((char) 13);
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while(CMSDK_UART0->STATE & CMSDK_UART_STATE_TXBF_Msk);
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CMSDK_UART0->DATA = (uint32_t)txchar;
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return (int) txchar;
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}
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int stderr_putchar(char txchar)
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{
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return stdout_putchar(txchar);
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}
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void ttywrch (int ch)
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{
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stdout_putchar(ch);
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}
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#define log_str(...) \
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do { \
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const char *pchSrc = __VA_ARGS__; \
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uint_fast16_t hwSize = sizeof(__VA_ARGS__); \
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do { \
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stdout_putchar(*pchSrc++); \
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} while(--hwSize); \
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} while(0)
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__NO_RETURN
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void _sys_exit(int n)
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{
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log_str("\r\n");
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log_str("_[TEST COMPLETE]_________________________________________________\r\n");
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log_str("\r\n\r\n");
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while(1) {
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__asm volatile ("nop");
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}
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}
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#ifdef __MICROLIB
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__NO_RETURN void exit(int n)
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{
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_sys_exit(n);
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}
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#endif
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