Embedded/perf_counter
1
0
Fork 0
mirror of https://github.com/GorgonMeducer/perf_counter.git synced 2025-02-07 19:34:18 +08:00
Code Issues Packages Projects Releases Wiki Activity

add cache miss rate calculation

Browse Source
This commit is contained in:
Gabriel Wang 2024-02-28 20:27:29 +00:00
parent 90c90747b8
commit db1d3a1e29
1 changed files with 37 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

43
perfc_port_pmu.h
View File

@ -27,20 +27,43 @@
using( \ using( \
struct { \ struct { \
uint64_t dwNoInstr; \ uint64_t dwNoInstr; \
uint64_t dwNoMemAccess; \
uint64_t dwNoCacheMiss; \
uint64_t dwNoL1DCacheRefill; \
int64_t lCycles; \ int64_t lCycles; \
uint32_t wCalib; \ uint32_t wInstrCalib; \
uint32_t wMemAccessCalib; \
float fCPI; \ float fCPI; \
float fDCacheMissRate; \
} __PERF_INFO__ = {0}, \ } __PERF_INFO__ = {0}, \
({ \ ({ \
__PERF_INFO__.dwNoInstr = perfc_pmu_get_instruction_count(); \ __PERF_INFO__.dwNoInstr = perfc_pmu_get_instruction_count(); \
__PERF_INFO__.wCalib = perfc_pmu_get_instruction_count() \ __PERF_INFO__.dwNoMemAccess = perfc_pmu_get_memory_access_count(); \
__PERF_INFO__.wInstrCalib = perfc_pmu_get_instruction_count() \
- __PERF_INFO__.dwNoInstr; \ - __PERF_INFO__.dwNoInstr; \
__PERF_INFO__.wMemAccessCalib = perfc_pmu_get_memory_access_count() \
- __PERF_INFO__.dwNoMemAccess; \
__PERF_INFO__.dwNoL1DCacheRefill \
= perfc_pmu_get_L1_dcache_refill_count(); \
__PERF_INFO__.dwNoInstr = perfc_pmu_get_instruction_count(); \ __PERF_INFO__.dwNoInstr = perfc_pmu_get_instruction_count(); \
__PERF_INFO__.dwNoMemAccess = perfc_pmu_get_memory_access_count(); \
}), \ }), \
({ \ ({ \
__PERF_INFO__.dwNoInstr = perfc_pmu_get_instruction_count() \ __PERF_INFO__.dwNoInstr = perfc_pmu_get_instruction_count() \
- __PERF_INFO__.dwNoInstr \ - __PERF_INFO__.dwNoInstr \
- __PERF_INFO__.wCalib; \ - __PERF_INFO__.wInstrCalib; \
__PERF_INFO__.dwNoMemAccess = perfc_pmu_get_memory_access_count() \
- __PERF_INFO__.dwNoMemAccess \
- __PERF_INFO__.wMemAccessCalib; \
__PERF_INFO__.dwNoL1DCacheRefill \
= perfc_pmu_get_L1_dcache_refill_count() \
- __PERF_INFO__.dwNoL1DCacheRefill; \
\
__PERF_INFO__.fDCacheMissRate \
= (float)( (double)__PERF_INFO__.dwNoL1DCacheRefill \
/ (double)__PERF_INFO__.dwNoMemAccess) \
* 100.0f; \
\
__PERF_INFO__.fCPI = (float)( (double)__PERF_INFO__.lCycles \ __PERF_INFO__.fCPI = (float)( (double)__PERF_INFO__.lCycles \
/ (double)__PERF_INFO__.dwNoInstr); \ / (double)__PERF_INFO__.dwNoInstr); \
if (__PLOOC_VA_NUM_ARGS(__VA_ARGS__) == 0) { \ if (__PLOOC_VA_NUM_ARGS(__VA_ARGS__) == 0) { \
@ -49,10 +72,18 @@
"-----------------------------------------\r\n" \ "-----------------------------------------\r\n" \
"Instruction executed: %lld\r\n" \ "Instruction executed: %lld\r\n" \
"Cycle Used: %lld\r\n" \ "Cycle Used: %lld\r\n" \
"Cycles per Instructions: %3.3f \r\n", \ "Cycles per Instructions: %3.3f \r\n\r\n" \
"Memory Access Count: %lld\r\n" \
"L1 DCache Refill Count: %lld\r\n" \
"L1 DCache Miss Rate: %3.4f %% \r\n" \
, \
__PERF_INFO__.dwNoInstr, \ __PERF_INFO__.dwNoInstr, \
__PERF_INFO__.lCycles, \ __PERF_INFO__.lCycles, \
__PERF_INFO__.fCPI); \ __PERF_INFO__.fCPI, \
__PERF_INFO__.dwNoMemAccess, \
__PERF_INFO__.dwNoL1DCacheRefill, \
__PERF_INFO__.fDCacheMissRate \
); \
} else { \ } else { \
__VA_ARGS__ \ __VA_ARGS__ \
} \ } \