diff --git a/example/Blinky.sct b/example/Blinky.sct
new file mode 100644
index 0000000..a333393
--- /dev/null
+++ b/example/Blinky.sct
@@ -0,0 +1,15 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x00000000 0x00400000 { ; load region size_region
+ ER_IROM1 +0 0x00400000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ .ANY (+XO)
+ }
+ RW_IRAM1 0x20000000 0x00400000 { ; RW data
+ * (+RW +ZI)
+ }
+}
\ No newline at end of file
diff --git a/example/RTE/Device/ARMCM0/startup_ARMCM0.s b/example/RTE/Device/ARMCM0/startup_ARMCM0.s
new file mode 100644
index 0000000..e03303e
--- /dev/null
+++ b/example/RTE/Device/ARMCM0/startup_ARMCM0.s
@@ -0,0 +1,168 @@
+;/**************************************************************************//**
+; * @file startup_ARMCM0.s
+; * @brief CMSIS Core Device Startup File for
+; * ARMCM0 Device
+; * @version V1.0.1
+; * @date 23. July 2019
+; ******************************************************************************/
+;/*
+; * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+
+
+; Stack Configuration
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+__stack_limit
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; Heap Configuration
+; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Heap_Size EQU 0x00000C00
+
+ IF Heap_Size != 0 ; Heap is provided
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+ ENDIF
+
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; -14 NMI Handler
+ DCD HardFault_Handler ; -13 Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; -5 SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; -2 PendSV Handler
+ DCD SysTick_Handler ; -1 SysTick Handler
+
+ ; Interrupts
+ DCD Interrupt0_Handler ; 0 Interrupt 0
+ DCD Interrupt1_Handler ; 1 Interrupt 1
+ DCD Interrupt2_Handler ; 2 Interrupt 2
+ DCD Interrupt3_Handler ; 3 Interrupt 3
+ DCD Interrupt4_Handler ; 4 Interrupt 4
+ DCD Interrupt5_Handler ; 5 Interrupt 5
+ DCD Interrupt6_Handler ; 6 Interrupt 6
+ DCD Interrupt7_Handler ; 7 Interrupt 7
+ DCD Interrupt8_Handler ; 8 Interrupt 8
+ DCD Interrupt9_Handler ; 9 Interrupt 9
+
+ SPACE ( 22 * 4) ; Interrupts 10 .. 31 are left out
+__Vectors_End
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+
+ AREA |.text|, CODE, READONLY
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; The default macro is not used for HardFault_Handler
+; because this results in a poor debug illusion.
+HardFault_Handler PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+
+; Macro to define default exception/interrupt handlers.
+; Default handler are weak symbols with an endless loop.
+; They can be overwritten by real handlers.
+ MACRO
+ Set_Default_Handler $Handler_Name
+$Handler_Name PROC
+ EXPORT $Handler_Name [WEAK]
+ B .
+ ENDP
+ MEND
+
+
+; Default exception/interrupt handler
+
+ Set_Default_Handler NMI_Handler
+ Set_Default_Handler SVC_Handler
+ Set_Default_Handler PendSV_Handler
+ Set_Default_Handler SysTick_Handler
+
+ Set_Default_Handler Interrupt0_Handler
+ Set_Default_Handler Interrupt1_Handler
+ Set_Default_Handler Interrupt2_Handler
+ Set_Default_Handler Interrupt3_Handler
+ Set_Default_Handler Interrupt4_Handler
+ Set_Default_Handler Interrupt5_Handler
+ Set_Default_Handler Interrupt6_Handler
+ Set_Default_Handler Interrupt7_Handler
+ Set_Default_Handler Interrupt8_Handler
+ Set_Default_Handler Interrupt9_Handler
+
+ ALIGN
+
+
+; User setup Stack & Heap
+
+ IF :LNOT::DEF:__MICROLIB
+ IMPORT __use_two_region_memory
+ ENDIF
+
+ EXPORT __stack_limit
+ EXPORT __initial_sp
+ IF Heap_Size != 0 ; Heap is provided
+ EXPORT __heap_base
+ EXPORT __heap_limit
+ ENDIF
+
+ END
diff --git a/example/RTE/Device/ARMCM0/system_ARMCM0.c b/example/RTE/Device/ARMCM0/system_ARMCM0.c
new file mode 100644
index 0000000..3eb38aa
--- /dev/null
+++ b/example/RTE/Device/ARMCM0/system_ARMCM0.c
@@ -0,0 +1,56 @@
+/**************************************************************************//**
+ * @file system_ARMCM0.c
+ * @brief CMSIS Device System Source File for
+ * ARMCM0 Device
+ * @version V1.0.0
+ * @date 09. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ARMCM0.h"
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define XTAL (50000000UL) /* Oscillator frequency */
+
+#define SYSTEM_CLOCK (XTAL / 2U)
+
+
+/*----------------------------------------------------------------------------
+ System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
+
+
+/*----------------------------------------------------------------------------
+ System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+ SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+ System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+ SystemCoreClock = SYSTEM_CLOCK;
+}
diff --git a/example/RTE/Device/ARMCM3/startup_ARMCM3.s b/example/RTE/Device/ARMCM3/startup_ARMCM3.s
new file mode 100644
index 0000000..efe40c1
--- /dev/null
+++ b/example/RTE/Device/ARMCM3/startup_ARMCM3.s
@@ -0,0 +1,172 @@
+;/**************************************************************************//**
+; * @file startup_ARMCM3.s
+; * @brief CMSIS Core Device Startup File for
+; * ARMCM3 Device
+; * @version V1.0.1
+; * @date 23. July 2019
+; ******************************************************************************/
+;/*
+; * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+
+
+; Stack Configuration
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+__stack_limit
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; Heap Configuration
+; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Heap_Size EQU 0x00000C00
+
+ IF Heap_Size != 0 ; Heap is provided
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+ ENDIF
+
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; -14 NMI Handler
+ DCD HardFault_Handler ; -13 Hard Fault Handler
+ DCD MemManage_Handler ; -12 MPU Fault Handler
+ DCD BusFault_Handler ; -11 Bus Fault Handler
+ DCD UsageFault_Handler ; -10 Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; -5 SVCall Handler
+ DCD DebugMon_Handler ; -4 Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; -2 PendSV Handler
+ DCD SysTick_Handler ; -1 SysTick Handler
+
+ ; Interrupts
+ DCD Interrupt0_Handler ; 0 Interrupt 0
+ DCD Interrupt1_Handler ; 1 Interrupt 1
+ DCD Interrupt2_Handler ; 2 Interrupt 2
+ DCD Interrupt3_Handler ; 3 Interrupt 3
+ DCD Interrupt4_Handler ; 4 Interrupt 4
+ DCD Interrupt5_Handler ; 5 Interrupt 5
+ DCD Interrupt6_Handler ; 6 Interrupt 6
+ DCD Interrupt7_Handler ; 7 Interrupt 7
+ DCD Interrupt8_Handler ; 8 Interrupt 8
+ DCD Interrupt9_Handler ; 9 Interrupt 9
+
+ SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
+__Vectors_End
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+
+ AREA |.text|, CODE, READONLY
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; The default macro is not used for HardFault_Handler
+; because this results in a poor debug illusion.
+HardFault_Handler PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+
+; Macro to define default exception/interrupt handlers.
+; Default handler are weak symbols with an endless loop.
+; They can be overwritten by real handlers.
+ MACRO
+ Set_Default_Handler $Handler_Name
+$Handler_Name PROC
+ EXPORT $Handler_Name [WEAK]
+ B .
+ ENDP
+ MEND
+
+
+; Default exception/interrupt handler
+
+ Set_Default_Handler NMI_Handler
+ Set_Default_Handler MemManage_Handler
+ Set_Default_Handler BusFault_Handler
+ Set_Default_Handler UsageFault_Handler
+ Set_Default_Handler SVC_Handler
+ Set_Default_Handler DebugMon_Handler
+ Set_Default_Handler PendSV_Handler
+ Set_Default_Handler SysTick_Handler
+
+ Set_Default_Handler Interrupt0_Handler
+ Set_Default_Handler Interrupt1_Handler
+ Set_Default_Handler Interrupt2_Handler
+ Set_Default_Handler Interrupt3_Handler
+ Set_Default_Handler Interrupt4_Handler
+ Set_Default_Handler Interrupt5_Handler
+ Set_Default_Handler Interrupt6_Handler
+ Set_Default_Handler Interrupt7_Handler
+ Set_Default_Handler Interrupt8_Handler
+ Set_Default_Handler Interrupt9_Handler
+
+ ALIGN
+
+
+; User setup Stack & Heap
+
+ IF :LNOT::DEF:__MICROLIB
+ IMPORT __use_two_region_memory
+ ENDIF
+
+ EXPORT __stack_limit
+ EXPORT __initial_sp
+ IF Heap_Size != 0 ; Heap is provided
+ EXPORT __heap_base
+ EXPORT __heap_limit
+ ENDIF
+
+ END
diff --git a/example/RTE/Device/ARMCM3/system_ARMCM3.c b/example/RTE/Device/ARMCM3/system_ARMCM3.c
new file mode 100644
index 0000000..1948453
--- /dev/null
+++ b/example/RTE/Device/ARMCM3/system_ARMCM3.c
@@ -0,0 +1,65 @@
+/**************************************************************************//**
+ * @file system_ARMCM3.c
+ * @brief CMSIS Device System Source File for
+ * ARMCM3 Device
+ * @version V1.0.1
+ * @date 15. November 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ARMCM3.h"
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define XTAL (50000000UL) /* Oscillator frequency */
+
+#define SYSTEM_CLOCK (XTAL / 2U)
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+extern const VECTOR_TABLE_Type __VECTOR_TABLE[240];
+
+/*----------------------------------------------------------------------------
+ System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
+
+
+/*----------------------------------------------------------------------------
+ System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+ SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+ System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]);
+#endif
+
+ SystemCoreClock = SYSTEM_CLOCK;
+}
diff --git a/example/RTE/Device/CMSDK_CM0/RTE_Device.h b/example/RTE/Device/CMSDK_CM0/RTE_Device.h
new file mode 100644
index 0000000..1a5c51c
--- /dev/null
+++ b/example/RTE/Device/CMSDK_CM0/RTE_Device.h
@@ -0,0 +1,50 @@
+/* -----------------------------------------------------------------------------
+ * Copyright (c) 2016 ARM Ltd.
+ *
+ * This software is provided 'as-is', without any express or implied warranty.
+ * In no event will the authors be held liable for any damages arising from
+ * the use of this software. Permission is granted to anyone to use this
+ * software for any purpose, including commercial applications, and to alter
+ * it and redistribute it freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software in
+ * a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ *
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ *
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * $Date: 25. April 2016
+ * $Revision: V1.0.0
+ *
+ * Project: RTE Device Configuration for ARM CMSDK_CM device
+ * -------------------------------------------------------------------------- */
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+#ifndef __RTE_DEVICE_H
+#define __RTE_DEVICE_H
+
+// USART0 (Universal synchronous asynchronous receiver transmitter) [Driver_USART0]
+// Configuration settings for Driver_USART0 in component ::CMSIS Driver:USART
+#define RTE_USART0 1
+
+
+// USART1 (Universal synchronous asynchronous receiver transmitter) [Driver_USART1]
+// Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART
+#define RTE_USART1 0
+
+
+// USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_USART2]
+// Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART
+#define RTE_UART2 0
+
+
+// USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_USART3]
+// Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART
+#define RTE_UART3 0
+
+#endif /* __RTE_DEVICE_H */
diff --git a/example/RTE/Device/CMSDK_CM0/startup_CMSDK_CM0.s b/example/RTE/Device/CMSDK_CM0/startup_CMSDK_CM0.s
new file mode 100644
index 0000000..2c5f1e8
--- /dev/null
+++ b/example/RTE/Device/CMSDK_CM0/startup_CMSDK_CM0.s
@@ -0,0 +1,267 @@
+;/**************************************************************************//**
+; * @file startup_CMSDK_CM0.s
+; * @brief CMSIS Core Device Startup File for
+; * CMSDK_CM0 Device
+; * @version V3.05
+; * @date 09. November 2016
+; ******************************************************************************/
+;/* Copyright (c) 2011 - 2016 ARM LIMITED
+;
+; All rights reserved.
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+; - Redistributions of source code must retain the above copyright
+; notice, this list of conditions and the following disclaimer.
+; - Redistributions in binary form must reproduce the above copyright
+; notice, this list of conditions and the following disclaimer in the
+; documentation and/or other materials provided with the distribution.
+; - Neither the name of ARM nor the names of its contributors may be used
+; to endorse or promote products derived from this software without
+; specific prior written permission.
+; *
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+; POSSIBILITY OF SUCH DAMAGE.
+; ---------------------------------------------------------------------------*/
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; Stack Configuration
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; Heap Configuration
+; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Heap_Size EQU 0x00000C00
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD UART0RX_Handler ; 0 UART 0 receive interrupt
+ DCD UART0TX_Handler ; 1 UART 0 transmit interrupt
+ DCD UART1RX_Handler ; 2 UART 1 receive interrupt
+ DCD UART1TX_Handler ; 3 UART 1 transmit interrupt
+ DCD UART2RX_Handler ; 4 UART 2 receive interrupt
+ DCD UART2TX_Handler ; 5 UART 2 transmit interrupt
+ DCD GPIO0ALL_Handler ; 6 GPIO 0 combined interrupt
+ DCD GPIO1ALL_Handler ; 7 GPIO 1 combined interrupt
+ DCD TIMER0_Handler ; 8 Timer 0 interrupt
+ DCD TIMER1_Handler ; 9 Timer 1 interrupt
+ DCD DUALTIMER_Handler ; 10 Dual Timer interrupt
+ DCD SPI_0_1_Handler ; 11 SPI #0, #1 interrupt
+ DCD UART_0_1_2_OVF_Handler ; 12 UART overflow (0, 1 & 2) interrupt
+ DCD ETHERNET_Handler ; 13 Ethernet interrupt
+ DCD I2S_Handler ; 14 Audio I2S interrupt
+ DCD TOUCHSCREEN_Handler ; 15 Touch Screen interrupt
+ DCD GPIO2_Handler ; 16 GPIO 2 combined interrupt
+ DCD GPIO3_Handler ; 17 GPIO 3 combined interrupt
+ DCD UART3RX_Handler ; 18 UART 3 receive interrupt
+ DCD UART3TX_Handler ; 19 UART 3 transmit interrupt
+ DCD UART4RX_Handler ; 20 UART 4 receive interrupt
+ DCD UART4TX_Handler ; 21 UART 4 transmit interrupt
+ DCD SPI_2_Handler ; 22 SPI #2 interrupt
+ DCD SPI_3_4_Handler ; 23 SPI #3, SPI #4 interrupt
+ DCD GPIO0_0_Handler ; 24 GPIO 0 individual interrupt ( 0)
+ DCD GPIO0_1_Handler ; 25 GPIO 0 individual interrupt ( 1)
+ DCD GPIO0_2_Handler ; 26 GPIO 0 individual interrupt ( 2)
+ DCD GPIO0_3_Handler ; 27 GPIO 0 individual interrupt ( 3)
+ DCD GPIO0_4_Handler ; 28 GPIO 0 individual interrupt ( 4)
+ DCD GPIO0_5_Handler ; 29 GPIO 0 individual interrupt ( 5)
+ DCD GPIO0_6_Handler ; 30 GPIO 0 individual interrupt ( 6)
+ DCD GPIO0_7_Handler ; 31 GPIO 0 individual interrupt ( 7)
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+ EXPORT UART0RX_Handler [WEAK]
+ EXPORT UART0TX_Handler [WEAK]
+ EXPORT UART1RX_Handler [WEAK]
+ EXPORT UART1TX_Handler [WEAK]
+ EXPORT UART2RX_Handler [WEAK]
+ EXPORT UART2TX_Handler [WEAK]
+ EXPORT GPIO0ALL_Handler [WEAK]
+ EXPORT GPIO1ALL_Handler [WEAK]
+ EXPORT TIMER0_Handler [WEAK]
+ EXPORT TIMER1_Handler [WEAK]
+ EXPORT DUALTIMER_Handler [WEAK]
+ EXPORT SPI_0_1_Handler [WEAK]
+ EXPORT UART_0_1_2_OVF_Handler [WEAK]
+ EXPORT ETHERNET_Handler [WEAK]
+ EXPORT I2S_Handler [WEAK]
+ EXPORT TOUCHSCREEN_Handler [WEAK]
+ EXPORT GPIO2_Handler [WEAK]
+ EXPORT GPIO3_Handler [WEAK]
+ EXPORT UART3RX_Handler [WEAK]
+ EXPORT UART3TX_Handler [WEAK]
+ EXPORT UART4RX_Handler [WEAK]
+ EXPORT UART4TX_Handler [WEAK]
+ EXPORT SPI_2_Handler [WEAK]
+ EXPORT SPI_3_4_Handler [WEAK]
+ EXPORT GPIO0_0_Handler [WEAK]
+ EXPORT GPIO0_1_Handler [WEAK]
+ EXPORT GPIO0_2_Handler [WEAK]
+ EXPORT GPIO0_3_Handler [WEAK]
+ EXPORT GPIO0_4_Handler [WEAK]
+ EXPORT GPIO0_5_Handler [WEAK]
+ EXPORT GPIO0_6_Handler [WEAK]
+ EXPORT GPIO0_7_Handler [WEAK]
+
+UART0RX_Handler
+UART0TX_Handler
+UART1RX_Handler
+UART1TX_Handler
+UART2RX_Handler
+UART2TX_Handler
+GPIO0ALL_Handler
+GPIO1ALL_Handler
+TIMER0_Handler
+TIMER1_Handler
+DUALTIMER_Handler
+SPI_0_1_Handler
+UART_0_1_2_OVF_Handler
+ETHERNET_Handler
+I2S_Handler
+TOUCHSCREEN_Handler
+GPIO2_Handler
+GPIO3_Handler
+UART3RX_Handler
+UART3TX_Handler
+UART4RX_Handler
+UART4TX_Handler
+SPI_2_Handler
+SPI_3_4_Handler
+GPIO0_0_Handler
+GPIO0_1_Handler
+GPIO0_2_Handler
+GPIO0_3_Handler
+GPIO0_4_Handler
+GPIO0_5_Handler
+GPIO0_6_Handler
+GPIO0_7_Handler
+ B .
+
+ ENDP
+
+
+ ALIGN
+
+
+; User Initial Stack & Heap
+
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap PROC
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+ ENDP
+
+ ALIGN
+
+ ENDIF
+
+
+ END
diff --git a/example/RTE/Device/CMSDK_CM0/system_CMSDK_CM0.c b/example/RTE/Device/CMSDK_CM0/system_CMSDK_CM0.c
new file mode 100644
index 0000000..ecc1537
--- /dev/null
+++ b/example/RTE/Device/CMSDK_CM0/system_CMSDK_CM0.c
@@ -0,0 +1,60 @@
+/**************************************************************************//**
+ * @file system_CMSDK_CM0.c
+ * @brief CMSIS Device System Source File for
+ * CMSDK_M0 Device
+ * @version V4.00
+ * @date 02. November 2015
+ ******************************************************************************/
+/* Copyright (c) 2011 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#include "CMSDK_CM0.h"
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define XTAL (50000000UL) /* Oscillator frequency */
+
+#define SYSTEM_CLOCK (XTAL / 2)
+
+
+/*----------------------------------------------------------------------------
+ System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
+
+
+void SystemCoreClockUpdate (void)
+{
+ SystemCoreClock = SYSTEM_CLOCK;
+}
+
+void SystemInit (void)
+{
+ SystemCoreClock = SYSTEM_CLOCK;
+}
diff --git a/example/RTE/Device/CMSDK_CM3/RTE_Device.h b/example/RTE/Device/CMSDK_CM3/RTE_Device.h
new file mode 100644
index 0000000..1a5c51c
--- /dev/null
+++ b/example/RTE/Device/CMSDK_CM3/RTE_Device.h
@@ -0,0 +1,50 @@
+/* -----------------------------------------------------------------------------
+ * Copyright (c) 2016 ARM Ltd.
+ *
+ * This software is provided 'as-is', without any express or implied warranty.
+ * In no event will the authors be held liable for any damages arising from
+ * the use of this software. Permission is granted to anyone to use this
+ * software for any purpose, including commercial applications, and to alter
+ * it and redistribute it freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software in
+ * a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ *
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ *
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * $Date: 25. April 2016
+ * $Revision: V1.0.0
+ *
+ * Project: RTE Device Configuration for ARM CMSDK_CM device
+ * -------------------------------------------------------------------------- */
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+#ifndef __RTE_DEVICE_H
+#define __RTE_DEVICE_H
+
+// USART0 (Universal synchronous asynchronous receiver transmitter) [Driver_USART0]
+// Configuration settings for Driver_USART0 in component ::CMSIS Driver:USART
+#define RTE_USART0 1
+
+
+// USART1 (Universal synchronous asynchronous receiver transmitter) [Driver_USART1]
+// Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART
+#define RTE_USART1 0
+
+
+// USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_USART2]
+// Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART
+#define RTE_UART2 0
+
+
+// USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_USART3]
+// Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART
+#define RTE_UART3 0
+
+#endif /* __RTE_DEVICE_H */
diff --git a/example/RTE/Device/CMSDK_CM3/startup_CMSDK_CM3.s b/example/RTE/Device/CMSDK_CM3/startup_CMSDK_CM3.s
new file mode 100644
index 0000000..640ba74
--- /dev/null
+++ b/example/RTE/Device/CMSDK_CM3/startup_CMSDK_CM3.s
@@ -0,0 +1,287 @@
+;/**************************************************************************//**
+; * @file startup_CMSDK_CM3.s
+; * @brief CMSIS Core Device Startup File for
+; * CMSDK_CM3 Device
+; * @version V3.05
+; * @date 09. November 2016
+; ******************************************************************************/
+;/* Copyright (c) 2011 - 2016 ARM LIMITED
+;
+; All rights reserved.
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+; - Redistributions of source code must retain the above copyright
+; notice, this list of conditions and the following disclaimer.
+; - Redistributions in binary form must reproduce the above copyright
+; notice, this list of conditions and the following disclaimer in the
+; documentation and/or other materials provided with the distribution.
+; - Neither the name of ARM nor the names of its contributors may be used
+; to endorse or promote products derived from this software without
+; specific prior written permission.
+; *
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+; POSSIBILITY OF SUCH DAMAGE.
+; ---------------------------------------------------------------------------*/
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; Stack Configuration
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; Heap Configuration
+; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Heap_Size EQU 0x00000C00
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD UART0RX_Handler ; 0 UART 0 receive interrupt
+ DCD UART0TX_Handler ; 1 UART 0 transmit interrupt
+ DCD UART1RX_Handler ; 2 UART 1 receive interrupt
+ DCD UART1TX_Handler ; 3 UART 1 transmit interrupt
+ DCD UART2RX_Handler ; 4 UART 2 receive interrupt
+ DCD UART2TX_Handler ; 5 UART 2 transmit interrupt
+ DCD GPIO0ALL_Handler ; 6 GPIO 0 combined interrupt
+ DCD GPIO1ALL_Handler ; 7 GPIO 1 combined interrupt
+ DCD TIMER0_Handler ; 8 Timer 0 interrupt
+ DCD TIMER1_Handler ; 9 Timer 1 interrupt
+ DCD DUALTIMER_Handler ; 10 Dual Timer interrupt
+ DCD SPI_0_1_Handler ; 11 SPI #0, #1 interrupt
+ DCD UART_0_1_2_OVF_Handler ; 12 UART overflow (0, 1 & 2) interrupt
+ DCD ETHERNET_Handler ; 13 Ethernet interrupt
+ DCD I2S_Handler ; 14 Audio I2S interrupt
+ DCD TOUCHSCREEN_Handler ; 15 Touch Screen interrupt
+ DCD GPIO2_Handler ; 16 GPIO 2 combined interrupt
+ DCD GPIO3_Handler ; 17 GPIO 3 combined interrupt
+ DCD UART3RX_Handler ; 18 UART 3 receive interrupt
+ DCD UART3TX_Handler ; 19 UART 3 transmit interrupt
+ DCD UART4RX_Handler ; 20 UART 4 receive interrupt
+ DCD UART4TX_Handler ; 21 UART 4 transmit interrupt
+ DCD SPI_2_Handler ; 22 SPI #2 interrupt
+ DCD SPI_3_4_Handler ; 23 SPI #3, SPI #4 interrupt
+ DCD GPIO0_0_Handler ; 24 GPIO 0 individual interrupt ( 0)
+ DCD GPIO0_1_Handler ; 25 GPIO 0 individual interrupt ( 1)
+ DCD GPIO0_2_Handler ; 26 GPIO 0 individual interrupt ( 2)
+ DCD GPIO0_3_Handler ; 27 GPIO 0 individual interrupt ( 3)
+ DCD GPIO0_4_Handler ; 28 GPIO 0 individual interrupt ( 4)
+ DCD GPIO0_5_Handler ; 29 GPIO 0 individual interrupt ( 5)
+ DCD GPIO0_6_Handler ; 30 GPIO 0 individual interrupt ( 6)
+ DCD GPIO0_7_Handler ; 31 GPIO 0 individual interrupt ( 7)
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+ EXPORT UART0RX_Handler [WEAK]
+ EXPORT UART0TX_Handler [WEAK]
+ EXPORT UART1RX_Handler [WEAK]
+ EXPORT UART1TX_Handler [WEAK]
+ EXPORT UART2RX_Handler [WEAK]
+ EXPORT UART2TX_Handler [WEAK]
+ EXPORT GPIO0ALL_Handler [WEAK]
+ EXPORT GPIO1ALL_Handler [WEAK]
+ EXPORT TIMER0_Handler [WEAK]
+ EXPORT TIMER1_Handler [WEAK]
+ EXPORT DUALTIMER_Handler [WEAK]
+ EXPORT SPI_0_1_Handler [WEAK]
+ EXPORT UART_0_1_2_OVF_Handler [WEAK]
+ EXPORT ETHERNET_Handler [WEAK]
+ EXPORT I2S_Handler [WEAK]
+ EXPORT TOUCHSCREEN_Handler [WEAK]
+ EXPORT GPIO2_Handler [WEAK]
+ EXPORT GPIO3_Handler [WEAK]
+ EXPORT UART3RX_Handler [WEAK]
+ EXPORT UART3TX_Handler [WEAK]
+ EXPORT UART4RX_Handler [WEAK]
+ EXPORT UART4TX_Handler [WEAK]
+ EXPORT SPI_2_Handler [WEAK]
+ EXPORT SPI_3_4_Handler [WEAK]
+ EXPORT GPIO0_0_Handler [WEAK]
+ EXPORT GPIO0_1_Handler [WEAK]
+ EXPORT GPIO0_2_Handler [WEAK]
+ EXPORT GPIO0_3_Handler [WEAK]
+ EXPORT GPIO0_4_Handler [WEAK]
+ EXPORT GPIO0_5_Handler [WEAK]
+ EXPORT GPIO0_6_Handler [WEAK]
+ EXPORT GPIO0_7_Handler [WEAK]
+
+UART0RX_Handler
+UART0TX_Handler
+UART1RX_Handler
+UART1TX_Handler
+UART2RX_Handler
+UART2TX_Handler
+GPIO0ALL_Handler
+GPIO1ALL_Handler
+TIMER0_Handler
+TIMER1_Handler
+DUALTIMER_Handler
+SPI_0_1_Handler
+UART_0_1_2_OVF_Handler
+ETHERNET_Handler
+I2S_Handler
+TOUCHSCREEN_Handler
+GPIO2_Handler
+GPIO3_Handler
+UART3RX_Handler
+UART3TX_Handler
+UART4RX_Handler
+UART4TX_Handler
+SPI_2_Handler
+SPI_3_4_Handler
+GPIO0_0_Handler
+GPIO0_1_Handler
+GPIO0_2_Handler
+GPIO0_3_Handler
+GPIO0_4_Handler
+GPIO0_5_Handler
+GPIO0_6_Handler
+GPIO0_7_Handler
+ B .
+
+ ENDP
+
+
+ ALIGN
+
+
+; User Initial Stack & Heap
+
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap PROC
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+ ENDP
+
+ ALIGN
+
+ ENDIF
+
+
+ END
diff --git a/example/RTE/Device/CMSDK_CM3/system_CMSDK_CM3.c b/example/RTE/Device/CMSDK_CM3/system_CMSDK_CM3.c
new file mode 100644
index 0000000..a5483d8
--- /dev/null
+++ b/example/RTE/Device/CMSDK_CM3/system_CMSDK_CM3.c
@@ -0,0 +1,65 @@
+/**************************************************************************//**
+ * @file system_CMSDK_CM3.c
+ * @brief CMSIS Device System Source File for
+ * CMSDK_M3 Device
+ * @version V4.00
+ * @date 02. November 2015
+ ******************************************************************************/
+/* Copyright (c) 2011 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#include "CMSDK_CM3.h"
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define XTAL (50000000UL) /* Oscillator frequency */
+
+#define SYSTEM_CLOCK (XTAL / 2)
+
+
+/*----------------------------------------------------------------------------
+ System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
+
+
+void SystemCoreClockUpdate (void)
+{
+ SystemCoreClock = SYSTEM_CLOCK;
+}
+
+void SystemInit (void)
+{
+
+#ifdef UNALIGNED_SUPPORT_DISABLE
+ SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
+#endif
+
+ SystemCoreClock = SYSTEM_CLOCK;
+}
diff --git a/example/RTE/Device/CMSDK_CM7_SP/RTE_Device.h b/example/RTE/Device/CMSDK_CM7_SP/RTE_Device.h
new file mode 100644
index 0000000..1a5c51c
--- /dev/null
+++ b/example/RTE/Device/CMSDK_CM7_SP/RTE_Device.h
@@ -0,0 +1,50 @@
+/* -----------------------------------------------------------------------------
+ * Copyright (c) 2016 ARM Ltd.
+ *
+ * This software is provided 'as-is', without any express or implied warranty.
+ * In no event will the authors be held liable for any damages arising from
+ * the use of this software. Permission is granted to anyone to use this
+ * software for any purpose, including commercial applications, and to alter
+ * it and redistribute it freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software. If you use this software in
+ * a product, an acknowledgment in the product documentation would be
+ * appreciated but is not required.
+ *
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ *
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * $Date: 25. April 2016
+ * $Revision: V1.0.0
+ *
+ * Project: RTE Device Configuration for ARM CMSDK_CM device
+ * -------------------------------------------------------------------------- */
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+#ifndef __RTE_DEVICE_H
+#define __RTE_DEVICE_H
+
+// USART0 (Universal synchronous asynchronous receiver transmitter) [Driver_USART0]
+// Configuration settings for Driver_USART0 in component ::CMSIS Driver:USART
+#define RTE_USART0 1
+
+
+// USART1 (Universal synchronous asynchronous receiver transmitter) [Driver_USART1]
+// Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART
+#define RTE_USART1 0
+
+
+// USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_USART2]
+// Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART
+#define RTE_UART2 0
+
+
+// USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_USART3]
+// Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART
+#define RTE_UART3 0
+
+#endif /* __RTE_DEVICE_H */
diff --git a/example/RTE/Device/CMSDK_CM7_SP/startup_CMSDK_CM7.s b/example/RTE/Device/CMSDK_CM7_SP/startup_CMSDK_CM7.s
new file mode 100644
index 0000000..1b871da
--- /dev/null
+++ b/example/RTE/Device/CMSDK_CM7_SP/startup_CMSDK_CM7.s
@@ -0,0 +1,287 @@
+;/**************************************************************************//**
+; * @file startup_CMSDK_CM7.s
+; * @brief CMSIS Core Device Startup File for
+; * CMSDK_CM7 Device
+; * @version V3.05
+; * @date 09. November 2016
+; ******************************************************************************/
+;/* Copyright (c) 2011 - 2016 ARM LIMITED
+;
+; All rights reserved.
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+; - Redistributions of source code must retain the above copyright
+; notice, this list of conditions and the following disclaimer.
+; - Redistributions in binary form must reproduce the above copyright
+; notice, this list of conditions and the following disclaimer in the
+; documentation and/or other materials provided with the distribution.
+; - Neither the name of ARM nor the names of its contributors may be used
+; to endorse or promote products derived from this software without
+; specific prior written permission.
+; *
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+; POSSIBILITY OF SUCH DAMAGE.
+; ---------------------------------------------------------------------------*/
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; Stack Configuration
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; Heap Configuration
+; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Heap_Size EQU 0x00000C00
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD UART0RX_Handler ; 0 UART 0 receive interrupt
+ DCD UART0TX_Handler ; 1 UART 0 transmit interrupt
+ DCD UART1RX_Handler ; 2 UART 1 receive interrupt
+ DCD UART1TX_Handler ; 3 UART 1 transmit interrupt
+ DCD UART2RX_Handler ; 4 UART 2 receive interrupt
+ DCD UART2TX_Handler ; 5 UART 2 transmit interrupt
+ DCD GPIO0ALL_Handler ; 6 GPIO 0 combined interrupt
+ DCD GPIO1ALL_Handler ; 7 GPIO 1 combined interrupt
+ DCD TIMER0_Handler ; 8 Timer 0 interrupt
+ DCD TIMER1_Handler ; 9 Timer 1 interrupt
+ DCD DUALTIMER_Handler ; 10 Dual Timer interrupt
+ DCD SPI_0_1_Handler ; 11 SPI #0, #1 interrupt
+ DCD UART_0_1_2_OVF_Handler ; 12 UART overflow (0, 1 & 2) interrupt
+ DCD ETHERNET_Handler ; 13 Ethernet interrupt
+ DCD I2S_Handler ; 14 Audio I2S interrupt
+ DCD TOUCHSCREEN_Handler ; 15 Touch Screen interrupt
+ DCD GPIO2_Handler ; 16 GPIO 2 combined interrupt
+ DCD GPIO3_Handler ; 17 GPIO 3 combined interrupt
+ DCD UART3RX_Handler ; 18 UART 3 receive interrupt
+ DCD UART3TX_Handler ; 19 UART 3 transmit interrupt
+ DCD UART4RX_Handler ; 20 UART 4 receive interrupt
+ DCD UART4TX_Handler ; 21 UART 4 transmit interrupt
+ DCD SPI_2_Handler ; 22 SPI #2 interrupt
+ DCD SPI_3_4_Handler ; 23 SPI #3, SPI #4 interrupt
+ DCD GPIO0_0_Handler ; 24 GPIO 0 individual interrupt ( 0)
+ DCD GPIO0_1_Handler ; 25 GPIO 0 individual interrupt ( 1)
+ DCD GPIO0_2_Handler ; 26 GPIO 0 individual interrupt ( 2)
+ DCD GPIO0_3_Handler ; 27 GPIO 0 individual interrupt ( 3)
+ DCD GPIO0_4_Handler ; 28 GPIO 0 individual interrupt ( 4)
+ DCD GPIO0_5_Handler ; 29 GPIO 0 individual interrupt ( 5)
+ DCD GPIO0_6_Handler ; 30 GPIO 0 individual interrupt ( 6)
+ DCD GPIO0_7_Handler ; 31 GPIO 0 individual interrupt ( 7)
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+ EXPORT UART0RX_Handler [WEAK]
+ EXPORT UART0TX_Handler [WEAK]
+ EXPORT UART1RX_Handler [WEAK]
+ EXPORT UART1TX_Handler [WEAK]
+ EXPORT UART2RX_Handler [WEAK]
+ EXPORT UART2TX_Handler [WEAK]
+ EXPORT GPIO0ALL_Handler [WEAK]
+ EXPORT GPIO1ALL_Handler [WEAK]
+ EXPORT TIMER0_Handler [WEAK]
+ EXPORT TIMER1_Handler [WEAK]
+ EXPORT DUALTIMER_Handler [WEAK]
+ EXPORT SPI_0_1_Handler [WEAK]
+ EXPORT UART_0_1_2_OVF_Handler [WEAK]
+ EXPORT ETHERNET_Handler [WEAK]
+ EXPORT I2S_Handler [WEAK]
+ EXPORT TOUCHSCREEN_Handler [WEAK]
+ EXPORT GPIO2_Handler [WEAK]
+ EXPORT GPIO3_Handler [WEAK]
+ EXPORT UART3RX_Handler [WEAK]
+ EXPORT UART3TX_Handler [WEAK]
+ EXPORT UART4RX_Handler [WEAK]
+ EXPORT UART4TX_Handler [WEAK]
+ EXPORT SPI_2_Handler [WEAK]
+ EXPORT SPI_3_4_Handler [WEAK]
+ EXPORT GPIO0_0_Handler [WEAK]
+ EXPORT GPIO0_1_Handler [WEAK]
+ EXPORT GPIO0_2_Handler [WEAK]
+ EXPORT GPIO0_3_Handler [WEAK]
+ EXPORT GPIO0_4_Handler [WEAK]
+ EXPORT GPIO0_5_Handler [WEAK]
+ EXPORT GPIO0_6_Handler [WEAK]
+ EXPORT GPIO0_7_Handler [WEAK]
+
+UART0RX_Handler
+UART0TX_Handler
+UART1RX_Handler
+UART1TX_Handler
+UART2RX_Handler
+UART2TX_Handler
+GPIO0ALL_Handler
+GPIO1ALL_Handler
+TIMER0_Handler
+TIMER1_Handler
+DUALTIMER_Handler
+SPI_0_1_Handler
+UART_0_1_2_OVF_Handler
+ETHERNET_Handler
+I2S_Handler
+TOUCHSCREEN_Handler
+GPIO2_Handler
+GPIO3_Handler
+UART3RX_Handler
+UART3TX_Handler
+UART4RX_Handler
+UART4TX_Handler
+SPI_2_Handler
+SPI_3_4_Handler
+GPIO0_0_Handler
+GPIO0_1_Handler
+GPIO0_2_Handler
+GPIO0_3_Handler
+GPIO0_4_Handler
+GPIO0_5_Handler
+GPIO0_6_Handler
+GPIO0_7_Handler
+ B .
+
+ ENDP
+
+
+ ALIGN
+
+
+; User Initial Stack & Heap
+
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap PROC
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+ ENDP
+
+ ALIGN
+
+ ENDIF
+
+
+ END
diff --git a/example/RTE/Device/CMSDK_CM7_SP/system_CMSDK_CM7.c b/example/RTE/Device/CMSDK_CM7_SP/system_CMSDK_CM7.c
new file mode 100644
index 0000000..c7ee0e8
--- /dev/null
+++ b/example/RTE/Device/CMSDK_CM7_SP/system_CMSDK_CM7.c
@@ -0,0 +1,77 @@
+/**************************************************************************//**
+ * @file system_CMSDK_CM7.c
+ * @brief CMSIS Device System Source File for
+ * CMSDK_CM7 Device
+ * @version V4.00
+ * @date 02. November 2015
+ ******************************************************************************/
+/* Copyright (c) 2011 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined (CMSDK_CM7)
+ #include "CMSDK_CM7.h"
+#elif defined (CMSDK_CM7_SP)
+ #include "CMSDK_CM7_SP.h"
+#elif defined (CMSDK_CM7_DP)
+ #include "CMSDK_CM7_DP.h"
+#else
+ #error device not specified!
+#endif
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define XTAL (50000000UL) /* Oscillator frequency */
+
+#define SYSTEM_CLOCK (XTAL / 2)
+
+
+/*----------------------------------------------------------------------------
+ System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
+
+
+void SystemCoreClockUpdate (void)
+{
+ SystemCoreClock = SYSTEM_CLOCK;
+}
+
+void SystemInit (void)
+{
+ #if (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */
+ (3UL << 11*2) ); /* set CP11 Full Access */
+ #endif
+
+#ifdef UNALIGNED_SUPPORT_DISABLE
+ SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
+#endif
+
+ SystemCoreClock = SYSTEM_CLOCK;
+}
diff --git a/example/RTE/RTOS/board.c b/example/RTE/RTOS/board.c
new file mode 100644
index 0000000..473c935
--- /dev/null
+++ b/example/RTE/RTOS/board.c
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2017-07-24 Tanek the first version
+ * 2018-11-12 Ernest Chen modify copyright
+ */
+
+#include
+#include
+#include
+
+#define _SCB_BASE (0xE000E010UL)
+#define _SYSTICK_CTRL (*(rt_uint32_t *)(_SCB_BASE + 0x0))
+#define _SYSTICK_LOAD (*(rt_uint32_t *)(_SCB_BASE + 0x4))
+#define _SYSTICK_VAL (*(rt_uint32_t *)(_SCB_BASE + 0x8))
+#define _SYSTICK_CALIB (*(rt_uint32_t *)(_SCB_BASE + 0xC))
+#define _SYSTICK_PRI (*(rt_uint8_t *)(0xE000ED23UL))
+
+// Updates the variable SystemCoreClock and must be called
+// whenever the core clock is changed during program execution.
+extern void SystemCoreClockUpdate(void);
+
+// Holds the system core clock, which is the system clock
+// frequency supplied to the SysTick timer and the processor
+// core clock.
+extern uint32_t SystemCoreClock;
+
+static uint32_t _SysTick_Config(rt_uint32_t ticks)
+{
+ if ((ticks - 1) > 0xFFFFFF)
+ {
+ return 1;
+ }
+
+ _SYSTICK_LOAD = ticks - 1;
+ _SYSTICK_PRI = 0xFF;
+ _SYSTICK_VAL = 0;
+ _SYSTICK_CTRL = 0x07;
+
+ return 0;
+}
+
+#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP)
+#define RT_HEAP_SIZE 1024
+static uint32_t rt_heap[RT_HEAP_SIZE]; // heap default size: 4K(1024 * 4)
+RT_WEAK void *rt_heap_begin_get(void)
+{
+ return rt_heap;
+}
+
+RT_WEAK void *rt_heap_end_get(void)
+{
+ return rt_heap + RT_HEAP_SIZE;
+}
+#endif
+
+/**
+ * This function will initial your board.
+ */
+void rt_hw_board_init()
+{
+ /* System Clock Update */
+ SystemCoreClockUpdate();
+
+ /* System Tick Configuration */
+ _SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
+
+ /* Call components board initial (use INIT_BOARD_EXPORT()) */
+#ifdef RT_USING_COMPONENTS_INIT
+ rt_components_board_init();
+#endif
+
+#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP)
+ rt_system_heap_init(rt_heap_begin_get(), rt_heap_end_get());
+#endif
+}
+
+void SysTick_Handler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ rt_tick_increase();
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
diff --git a/example/RTE/RTOS/rtconfig.h b/example/RTE/RTOS/rtconfig.h
new file mode 100644
index 0000000..27bb044
--- /dev/null
+++ b/example/RTE/RTOS/rtconfig.h
@@ -0,0 +1,154 @@
+/* RT-Thread config file */
+
+#ifndef __RTTHREAD_CFG_H__
+#define __RTTHREAD_CFG_H__
+
+#if defined(__CC_ARM) || defined(__CLANG_ARM)
+#include "RTE_Components.h"
+
+#if defined(RTE_USING_FINSH)
+#define RT_USING_FINSH
+#endif //RTE_USING_FINSH
+
+#endif //(__CC_ARM) || (__CLANG_ARM)
+
+// <<< Use Configuration Wizard in Context Menu >>>
+// Basic Configuration
+// Maximal level of thread priority <8-256>
+// Default: 32
+#define RT_THREAD_PRIORITY_MAX 8
+// OS tick per second
+// Default: 1000 (1ms)
+#define RT_TICK_PER_SECOND 1000
+// Alignment size for CPU architecture data access
+// Default: 4
+#define RT_ALIGN_SIZE 4
+// the max length of object name<2-16>
+// Default: 8
+#define RT_NAME_MAX 8
+// Using RT-Thread components initialization
+// Using RT-Thread components initialization
+#define RT_USING_COMPONENTS_INIT
+//
+
+#define RT_USING_USER_MAIN
+
+// the stack size of main thread<1-4086>
+// Default: 512
+#define RT_MAIN_THREAD_STACK_SIZE 256
+
+//
+
+// Debug Configuration
+// enable kernel debug configuration
+// Default: enable kernel debug configuration
+//#define RT_DEBUG
+//
+// enable components initialization debug configuration<0-1>
+// Default: 0
+#define RT_DEBUG_INIT 0
+// thread stack over flow detect
+// Diable Thread stack over flow detect
+//#define RT_USING_OVERFLOW_CHECK
+//
+//
+
+// Hook Configuration
+// using hook
+// using hook
+//#define RT_USING_HOOK
+//
+// using idle hook
+// using idle hook
+//#define RT_USING_IDLE_HOOK
+//
+//
+
+// Software timers Configuration
+// Enables user timers
+#define RT_USING_TIMER_SOFT 0
+#if RT_USING_TIMER_SOFT == 0
+ #undef RT_USING_TIMER_SOFT
+#endif
+// The priority level of timer thread <0-31>
+// Default: 4
+#define RT_TIMER_THREAD_PRIO 4
+// The stack size of timer thread <0-8192>
+// Default: 512
+#define RT_TIMER_THREAD_STACK_SIZE 512
+//
+
+// IPC(Inter-process communication) Configuration
+// Using Semaphore
+// Using Semaphore
+#define RT_USING_SEMAPHORE
+//
+// Using Mutex
+// Using Mutex
+//#define RT_USING_MUTEX
+//
+// Using Event
+// Using Event
+//#define RT_USING_EVENT
+//
+// Using MailBox
+// Using MailBox
+#define RT_USING_MAILBOX
+//
+// Using Message Queue
+// Using Message Queue
+//#define RT_USING_MESSAGEQUEUE
+//
+//
+
+// Memory Management Configuration
+// Dynamic Heap Management
+// Dynamic Heap Management
+//#define RT_USING_HEAP
+//
+// using small memory
+// using small memory
+#define RT_USING_SMALL_MEM
+//
+// using tiny size of memory
+// using tiny size of memory
+//#define RT_USING_TINY_SIZE
+//
+//
+
+// Console Configuration
+// Using console
+// Using console
+#define RT_USING_CONSOLE
+//
+// the buffer size of console <1-1024>
+// the buffer size of console
+// Default: 128 (128Byte)
+#define RT_CONSOLEBUF_SIZE 128
+//
+
+#if defined(RT_USING_FINSH)
+ #define FINSH_USING_MSH
+ #define FINSH_USING_MSH_ONLY
+ // Finsh Configuration
+ // the priority of finsh thread <1-7>
+ // the priority of finsh thread
+ // Default: 6
+ #define __FINSH_THREAD_PRIORITY 5
+ #define FINSH_THREAD_PRIORITY (RT_THREAD_PRIORITY_MAX / 8 * __FINSH_THREAD_PRIORITY + 1)
+ // the stack of finsh thread <1-4096>
+ // the stack of finsh thread
+ // Default: 4096 (4096Byte)
+ #define FINSH_THREAD_STACK_SIZE 512
+ // the history lines of finsh thread <1-32>
+ // the history lines of finsh thread
+ // Default: 5
+ #define FINSH_HISTORY_LINES 1
+
+ #define FINSH_USING_SYMTAB
+ //
+#endif
+
+// <<< end of configuration section >>>
+
+#endif
diff --git a/example/RTE/_example/RTE_Components.h b/example/RTE/_example/RTE_Components.h
new file mode 100644
index 0000000..46861e4
--- /dev/null
+++ b/example/RTE/_example/RTE_Components.h
@@ -0,0 +1,24 @@
+
+/*
+ * Auto generated Run-Time-Environment Configuration File
+ * *** Do not modify ! ***
+ *
+ * Project: 'example'
+ * Target: 'example'
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File:
+ */
+#define CMSIS_device_header "ARMCM3.h"
+
+/* Keil.ARM Compiler::Compiler:I/O:STDOUT:User:1.2.0 */
+#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */
+ #define RTE_Compiler_IO_STDOUT_User /* Compiler I/O: STDOUT User */
+
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/example/RTE/_library/RTE_Components.h b/example/RTE/_library/RTE_Components.h
new file mode 100644
index 0000000..c367beb
--- /dev/null
+++ b/example/RTE/_library/RTE_Components.h
@@ -0,0 +1,21 @@
+
+/*
+ * Auto generated Run-Time-Environment Configuration File
+ * *** Do not modify ! ***
+ *
+ * Project: 'example'
+ * Target: 'library'
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File:
+ */
+#define CMSIS_device_header "ARMCM3.h"
+
+
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/example/example.uvguix b/example/example.uvguix
new file mode 100644
index 0000000..d96b552
--- /dev/null
+++ b/example/example.uvguix
@@ -0,0 +1,3403 @@
+
+
+
+ -6.1
+
+ ### uVision Project, (C) Keil Software
+
+
+
+
+
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diff --git a/example/example.uvoptx b/example/example.uvoptx
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+
+
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+ 1.0
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+ ### uVision Project, (C) Keil Software
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diff --git a/example/example.uvprojx b/example/example.uvprojx
new file mode 100644
index 0000000..599138d
--- /dev/null
+++ b/example/example.uvprojx
@@ -0,0 +1,1320 @@
+
+
+
+ 2.1
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+ ### uVision Project, (C) Keil Software
+
+
+
+ example
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+ 6150000::V6.15::ARMCLANG
+ 1
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+
+ ARMCM3
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+ http://www.keil.com/pack/
+ IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M3") CLOCK(12000000) ESEL ELITTLE
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+
+
+
+
+
+
+
+ 0
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+
+
+
+ Blinky.sct
+
+
+
+
+
+
+
+
+
+
+ application
+
+
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+ 2
+ 2
+ 2
+ 2
+ 0
+
+
+
+
+
+
+
+
+
+
+
+ stdout_USART.c
+ 1
+ .\stdout_USART.c
+
+
+ main.c
+ 1
+ .\main.c
+
+
+ platform.c
+ 1
+ .\platform.c
+
+
+
+
+ perf_counter_lib
+
+
+ perf_counter.c
+ 1
+ ..\perf_counter.c
+
+
+ perf_counter.h
+ 5
+ ..\perf_counter.h
+
+
+ systick_wrapper_ual.s
+ 2
+ ..\systick_wrapper_ual.s
+
+
+ perf_counter.lib
+ 4
+ ..\lib\perf_counter.lib
+
+
+ 2
+ 0
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+ 2
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+
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+
+
+ ::Compiler
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ RTE\Device\ARMCM0\startup_ARMCM0.s
+
+
+
+
+
+ RTE\Device\ARMCM0\system_ARMCM0.c
+
+
+
+
+
+ RTE\Device\ARMCM3\startup_ARMCM3.s
+
+
+
+
+
+
+
+
+ RTE\Device\ARMCM3\system_ARMCM3.c
+
+
+
+
+
+
+
+
+ RTE\Device\CMSDK_CM0\RTE_Device.h
+
+
+
+
+
+ RTE\Device\CMSDK_CM0\startup_CMSDK_CM0.s
+
+
+
+
+
+ RTE\Device\CMSDK_CM0\system_CMSDK_CM0.c
+
+
+
+
+
+ RTE\Device\CMSDK_CM3\RTE_Device.h
+
+
+
+
+
+ RTE\Device\CMSDK_CM3\startup_CMSDK_CM3.s
+
+
+
+
+
+ RTE\Device\CMSDK_CM3\system_CMSDK_CM3.c
+
+
+
+
+
+ RTE\Device\CMSDK_CM7_SP\RTE_Device.h
+
+
+
+
+
+ RTE\Device\CMSDK_CM7_SP\startup_CMSDK_CM7.s
+
+
+
+
+
+ RTE\Device\CMSDK_CM7_SP\system_CMSDK_CM7.c
+
+
+
+
+
+ RTE\RTOS\board.c
+
+
+
+
+
+ RTE\RTOS\rtconfig.h
+
+
+
+
+
+
+
+
+
+
+ Blinky
+ 0
+ 1
+
+
+
+
+
diff --git a/example/main.c b/example/main.c
new file mode 100644
index 0000000..1818a8b
--- /dev/null
+++ b/example/main.c
@@ -0,0 +1,88 @@
+#include
+#include
+#include
+#include "perf_counter.h"
+#include
+
+void systimer_1ms_handler(void)
+{
+ //printf("Running original Systick_Handler...\r\n");
+}
+
+typedef struct example_lv1_t {
+ uint32_t wLV1A;
+ uint16_t hwLV1B;
+ uint8_t chLV1C;
+}example_lv1_t;
+
+
+typedef struct example_lv0_t {
+
+ uint32_t wA;
+ uint16_t hwB;
+ uint8_t chC;
+ uint8_t chID;
+ example_lv1_t tLV1;
+} example_lv0_t;
+
+example_lv0_t s_tItem[8] = {
+ {.chID = 0},
+ {.chID = 1},
+ {.chID = 2},
+ {.chID = 3},
+ {.chID = 4},
+ {.chID = 5},
+ {.chID = 6},
+ {.chID = 7},
+};
+
+extern void CM7_BLX_R14_Test(void);
+
+/*----------------------------------------------------------------------------
+ Main function
+ *----------------------------------------------------------------------------*/
+int main (void)
+{
+ /*! demo of using() block */
+ using(int a = 0,printf("========= On Enter =======\r\n"),
+ printf("========= On Leave =======\r\n")) {
+ printf("\t In Body a=%d \r\n", ++a);
+ }
+
+
+ printf("\r\n\r\n\r\n\r\n");
+
+ /*! demo of __cycleof__() operation */
+ __cycleof__() {
+ foreach(example_lv0_t, s_tItem) {
+ printf("Processing item with ID = %d\r\n", _.chID);
+ }
+ }
+
+ /*! demo of with block */
+ with(example_lv0_t, &s_tItem[0], pitem) {
+ _.wA = 1;
+ _.hwB = 2;
+ _.chC = 3;
+
+ with(example_lv1_t, &pitem->tLV1) {
+ _.wLV1A = 4;
+ _.hwLV1B = 5;
+ _.chLV1C = 6;
+ }
+ }
+
+ //! demo of using clock() in timer.h
+ do {
+ clock_t tStart = clock();
+ safe_atom_code()
+ {
+ printf("no interrupt \r\n");
+ }
+ printf("used clock cycle: %d", clock() - tStart);
+ } while(0);
+
+ while (1) {
+
+ }
+}
diff --git a/example/platform.c b/example/platform.c
new file mode 100644
index 0000000..659fe15
--- /dev/null
+++ b/example/platform.c
@@ -0,0 +1,70 @@
+/*----------------------------------------------------------------------------
+ * Name: Blinky.c
+ * Purpose: LED Flasher for MPS2
+ * Note(s): possible defines set in "options for target - C/C++ - Define"
+ * __USE_LCD - enable Output on GLCD
+ * __USE_TIMER0 - use Timer0 to generate timer interrupt
+ * - use SysTick to generate timer interrupt (default)
+ *----------------------------------------------------------------------------
+ * This file is part of the uVision/ARM development tools.
+ * This software may only be used under the terms of a valid, current,
+ * end user licence from KEIL for a compatible version of KEIL software
+ * development tools. Nothing else gives you the right to use this software.
+ *
+ * This software is supplied "AS IS" without warranties of any kind.
+ *
+ * Copyright (c) 2015 Keil - An ARM Company. All rights reserved.
+ *----------------------------------------------------------------------------*/
+
+#include
+#include
+#include
+#include "ARMCM3.h" // Keil::Board Support:V2M-MPS2:Common
+#include
+
+extern
+void uart_config(uint32_t wUARTFrequency);
+
+
+__attribute__((weak))
+void systimer_1ms_handler(void)
+{
+ //assert(false);
+}
+
+static volatile uint32_t s_wMSCounter = 0;
+
+/*----------------------------------------------------------------------------
+ SysTick / Timer0 IRQ Handler
+ *----------------------------------------------------------------------------*/
+
+void SysTick_Handler (void)
+{
+ if (s_wMSCounter) {
+ s_wMSCounter--;
+ }
+
+ systimer_1ms_handler();
+}
+
+void delay_ms(uint32_t wMillisecond)
+{
+ s_wMSCounter = wMillisecond;
+ while( s_wMSCounter > 0 );
+}
+
+
+/*! \brief initialise platform before main()
+ */
+__attribute__((constructor(101)))
+void platform_init(void)
+{
+ SystemCoreClockUpdate();
+
+ uart_config(25000000ul);
+
+ /* Generate interrupt each 1 ms */
+ SysTick_Config(SystemCoreClock / 1000);
+}
+
+
diff --git a/example/stdout_USART.c b/example/stdout_USART.c
new file mode 100644
index 0000000..55c6261
--- /dev/null
+++ b/example/stdout_USART.c
@@ -0,0 +1,186 @@
+/*****************************************************************************
+ * Copyright(C)2009-2019 by VSF Team *
+ * *
+ * Licensed under the Apache License, Version 2.0 (the "License"); *
+ * you may not use this file except in compliance with the License. *
+ * You may obtain a copy of the License at *
+ * *
+ * http://www.apache.org/licenses/LICENSE-2.0 *
+ * *
+ * Unless required by applicable law or agreed to in writing, software *
+ * distributed under the License is distributed on an "AS IS" BASIS, *
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. *
+ * See the License for the specific language governing permissions and *
+ * limitations under the License. *
+ * *
+ ****************************************************************************/
+#include
+#include
+#include
+#include "cmsis_compiler.h"
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
+typedef struct
+{
+ __IOM uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */
+ __IOM uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */
+ __IOM uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */
+ union {
+ __IM uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */
+ __OM uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */
+ };
+ __IOM uint32_t BAUDDIV; /* Offset: 0x010 (R/W) Baudrate Divider Register */
+
+} CMSDK_UART_TypeDef;
+
+/* CMSDK_UART DATA Register Definitions */
+#define CMSDK_UART_DATA_Pos 0 /* CMSDK_UART_DATA_Pos: DATA Position */
+#define CMSDK_UART_DATA_Msk (0xFFUL /*<< CMSDK_UART_DATA_Pos*/) /* CMSDK_UART DATA: DATA Mask */
+
+/* CMSDK_UART STATE Register Definitions */
+#define CMSDK_UART_STATE_RXOR_Pos 3 /* CMSDK_UART STATE: RXOR Position */
+#define CMSDK_UART_STATE_RXOR_Msk (0x1UL << CMSDK_UART_STATE_RXOR_Pos) /* CMSDK_UART STATE: RXOR Mask */
+
+#define CMSDK_UART_STATE_TXOR_Pos 2 /* CMSDK_UART STATE: TXOR Position */
+#define CMSDK_UART_STATE_TXOR_Msk (0x1UL << CMSDK_UART_STATE_TXOR_Pos) /* CMSDK_UART STATE: TXOR Mask */
+
+#define CMSDK_UART_STATE_RXBF_Pos 1 /* CMSDK_UART STATE: RXBF Position */
+#define CMSDK_UART_STATE_RXBF_Msk (0x1UL << CMSDK_UART_STATE_RXBF_Pos) /* CMSDK_UART STATE: RXBF Mask */
+
+#define CMSDK_UART_STATE_TXBF_Pos 0 /* CMSDK_UART STATE: TXBF Position */
+#define CMSDK_UART_STATE_TXBF_Msk (0x1UL /*<< CMSDK_UART_STATE_TXBF_Pos*/) /* CMSDK_UART STATE: TXBF Mask */
+
+/* CMSDK_UART CTRL Register Definitions */
+#define CMSDK_UART_CTRL_HSTM_Pos 6 /* CMSDK_UART CTRL: HSTM Position */
+#define CMSDK_UART_CTRL_HSTM_Msk (0x01UL << CMSDK_UART_CTRL_HSTM_Pos) /* CMSDK_UART CTRL: HSTM Mask */
+
+#define CMSDK_UART_CTRL_RXORIRQEN_Pos 5 /* CMSDK_UART CTRL: RXORIRQEN Position */
+#define CMSDK_UART_CTRL_RXORIRQEN_Msk (0x01UL << CMSDK_UART_CTRL_RXORIRQEN_Pos) /* CMSDK_UART CTRL: RXORIRQEN Mask */
+
+#define CMSDK_UART_CTRL_TXORIRQEN_Pos 4 /* CMSDK_UART CTRL: TXORIRQEN Position */
+#define CMSDK_UART_CTRL_TXORIRQEN_Msk (0x01UL << CMSDK_UART_CTRL_TXORIRQEN_Pos) /* CMSDK_UART CTRL: TXORIRQEN Mask */
+
+#define CMSDK_UART_CTRL_RXIRQEN_Pos 3 /* CMSDK_UART CTRL: RXIRQEN Position */
+#define CMSDK_UART_CTRL_RXIRQEN_Msk (0x01UL << CMSDK_UART_CTRL_RXIRQEN_Pos) /* CMSDK_UART CTRL: RXIRQEN Mask */
+
+#define CMSDK_UART_CTRL_TXIRQEN_Pos 2 /* CMSDK_UART CTRL: TXIRQEN Position */
+#define CMSDK_UART_CTRL_TXIRQEN_Msk (0x01UL << CMSDK_UART_CTRL_TXIRQEN_Pos) /* CMSDK_UART CTRL: TXIRQEN Mask */
+
+#define CMSDK_UART_CTRL_RXEN_Pos 1 /* CMSDK_UART CTRL: RXEN Position */
+#define CMSDK_UART_CTRL_RXEN_Msk (0x01UL << CMSDK_UART_CTRL_RXEN_Pos) /* CMSDK_UART CTRL: RXEN Mask */
+
+#define CMSDK_UART_CTRL_TXEN_Pos 0 /* CMSDK_UART CTRL: TXEN Position */
+#define CMSDK_UART_CTRL_TXEN_Msk (0x01UL /*<< CMSDK_UART_CTRL_TXEN_Pos*/) /* CMSDK_UART CTRL: TXEN Mask */
+
+#define CMSDK_UART_INTSTATUS_RXORIRQ_Pos 3 /* CMSDK_UART CTRL: RXORIRQ Position */
+#define CMSDK_UART_CTRL_RXORIRQ_Msk (0x01UL << CMSDK_UART_INTSTATUS_RXORIRQ_Pos) /* CMSDK_UART CTRL: RXORIRQ Mask */
+
+#define CMSDK_UART_CTRL_TXORIRQ_Pos 2 /* CMSDK_UART CTRL: TXORIRQ Position */
+#define CMSDK_UART_CTRL_TXORIRQ_Msk (0x01UL << CMSDK_UART_CTRL_TXORIRQ_Pos) /* CMSDK_UART CTRL: TXORIRQ Mask */
+
+#define CMSDK_UART_CTRL_RXIRQ_Pos 1 /* CMSDK_UART CTRL: RXIRQ Position */
+#define CMSDK_UART_CTRL_RXIRQ_Msk (0x01UL << CMSDK_UART_CTRL_RXIRQ_Pos) /* CMSDK_UART CTRL: RXIRQ Mask */
+
+#define CMSDK_UART_CTRL_TXIRQ_Pos 0 /* CMSDK_UART CTRL: TXIRQ Position */
+#define CMSDK_UART_CTRL_TXIRQ_Msk (0x01UL /*<< CMSDK_UART_CTRL_TXIRQ_Pos*/) /* CMSDK_UART CTRL: TXIRQ Mask */
+
+/* CMSDK_UART BAUDDIV Register Definitions */
+#define CMSDK_UART_BAUDDIV_Pos 0 /* CMSDK_UART BAUDDIV: BAUDDIV Position */
+#define CMSDK_UART_BAUDDIV_Msk (0xFFFFFUL /*<< CMSDK_UART_BAUDDIV_Pos*/) /* CMSDK_UART BAUDDIV: BAUDDIV Mask */
+
+
+/* ================================================================================ */
+/* ================ Peripheral declaration ================ */
+/* ================================================================================ */
+
+//#define CMSDK_UART0_BASE_ADDRESS (0x41303000ul)
+#define CMSDK_UART0_BASE_ADDRESS (0x40004000ul)
+#define CMSDK_UART0 ((CMSDK_UART_TypeDef *) CMSDK_UART0_BASE_ADDRESS)
+
+
+void uart_config(uint32_t wUARTFrequency)
+{
+ CMSDK_UART0->CTRL = 0; /* Disable UART when changing configuration */
+ CMSDK_UART0->BAUDDIV = wUARTFrequency / 115200ul; /* 25MHz / 38400 = 651 */
+ CMSDK_UART0->CTRL = CMSDK_UART_CTRL_TXEN_Msk|CMSDK_UART_CTRL_RXEN_Msk;
+}
+
+char stdin_getchar(void)
+{
+ while(!(CMSDK_UART0->STATE & CMSDK_UART_STATE_RXBF_Msk));
+ return (char)(CMSDK_UART0->DATA);
+}
+
+
+
+int stdout_putchar(char txchar)
+{
+ if (txchar == 10) stdout_putchar((char) 13);
+
+ while(CMSDK_UART0->STATE & CMSDK_UART_STATE_TXBF_Msk);
+ CMSDK_UART0->DATA = (uint32_t)txchar;
+
+ return (int) txchar;
+}
+
+int stderr_putchar(char txchar)
+{
+ return stdout_putchar(txchar);
+}
+
+void ttywrch (int ch)
+{
+ stdout_putchar(ch);
+}
+
+
+#define log_str(...) \
+ do { \
+ const char *pchSrc = __VA_ARGS__; \
+ uint_fast16_t hwSize = sizeof(__VA_ARGS__); \
+ do { \
+ stdout_putchar(*pchSrc++); \
+ } while(--hwSize); \
+ } while(0)
+
+__NO_RETURN
+void _sys_exit(int n)
+{
+ log_str("\r\n");
+ log_str("_[TEST COMPLETE]_________________________________________________\r\n");
+ log_str("\r\n\r\n");
+
+ while(1) {
+ __asm volatile ("nop");
+ }
+}
+
+#ifdef __MICROLIB
+__NO_RETURN void exit(int n)
+{
+ _sys_exit(n);
+}
+#endif
+
+
diff --git a/lib/perf_counter.h b/lib/perf_counter.h
new file mode 100644
index 0000000..237abd5
--- /dev/null
+++ b/lib/perf_counter.h
@@ -0,0 +1,183 @@
+/****************************************************************************
+* *
+* Licensed under the Apache License, Version 2.0 (the "License"); *
+* you may not use this file except in compliance with the License. *
+* You may obtain a copy of the License at *
+* *
+* http://www.apache.org/licenses/LICENSE-2.0 *
+* *
+* Unless required by applicable law or agreed to in writing, software *
+* distributed under the License is distributed on an "AS IS" BASIS, *
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. *
+* See the License for the specific language governing permissions and *
+* limitations under the License. *
+* *
+****************************************************************************/
+
+
+
+#ifndef __PERFORMANCE_COUNTER_H__
+#define __PERFORMANCE_COUNTER_H__
+
+/*============================ INCLUDES ======================================*/
+#include
+#include
+
+/*============================ MACROS ========================================*/
+
+#define __PLOOC_VA_NUM_ARGS_IMPL( _0,_1,_2,_3,_4,_5,_6,_7,_8,_9,_10,_11,_12, \
+ _13,_14,_15,_16,__N,...) __N
+#define __PLOOC_VA_NUM_ARGS(...) \
+ __PLOOC_VA_NUM_ARGS_IMPL( 0,##__VA_ARGS__,16,15,14,13,12,11,10,9, \
+ 8,7,6,5,4,3,2,1,0)
+
+#define __CONNECT2(__A, __B) __A##__B
+#define __CONNECT3(__A, __B, __C) __A##__B##__C
+#define __CONNECT4(__A, __B, __C, __D) __A##__B##__C##__D
+#define __CONNECT5(__A, __B, __C, __D, __E) __A##__B##__C##__D##__E
+#define __CONNECT6(__A, __B, __C, __D, __E, __F) __A##__B##__C##__D##__E##__F
+#define __CONNECT7(__A, __B, __C, __D, __E, __F, __G) \
+ __A##__B##__C##__D##__E##__F##__G
+#define __CONNECT8(__A, __B, __C, __D, __E, __F, __G, __H) \
+ __A##__B##__C##__D##__E##__F##__G##__H
+#define __CONNECT9(__A, __B, __C, __D, __E, __F, __G, __H, __I) \
+ __A##__B##__C##__D##__E##__F##__G##__H##__I
+
+#define CONNECT2(__A, __B) __CONNECT2(__A, __B)
+#define CONNECT3(__A, __B, __C) __CONNECT3(__A, __B, __C)
+#define CONNECT4(__A, __B, __C, __D) __CONNECT4(__A, __B, __C, __D)
+#define CONNECT5(__A, __B, __C, __D, __E) __CONNECT5(__A, __B, __C, __D, __E)
+#define CONNECT6(__A, __B, __C, __D, __E, __F) \
+ __CONNECT6(__A, __B, __C, __D, __E, __F)
+#define CONNECT7(__A, __B, __C, __D, __E, __F, __G) \
+ __CONNECT7(__A, __B, __C, __D, __E, __F, __G)
+#define CONNECT8(__A, __B, __C, __D, __E, __F, __G, __H) \
+ __CONNECT8(__A, __B, __C, __D, __E, __F, __G, __H)
+#define CONNECT9(__A, __B, __C, __D, __E, __F, __G, __H, __I) \
+ __CONNECT9(__A, __B, __C, __D, __E, __F, __G, __H, __I)
+
+#define CONNECT(...) \
+ CONNECT2(CONNECT, __PLOOC_VA_NUM_ARGS(__VA_ARGS__))(__VA_ARGS__)
+
+
+
+#define __using1(__declare) \
+ for (__declare, *CONNECT3(__using_, __LINE__,_ptr) = NULL; \
+ CONNECT3(__using_, __LINE__,_ptr)++ == NULL; \
+ )
+
+#define __using2(__declare, __on_leave_expr) \
+ for (__declare, *CONNECT3(__using_, __LINE__,_ptr) = NULL; \
+ CONNECT3(__using_, __LINE__,_ptr)++ == NULL; \
+ __on_leave_expr \
+ )
+
+#define __using3(__declare, __on_enter_expr, __on_leave_expr) \
+ for (__declare, *CONNECT3(__using_, __LINE__,_ptr) = NULL; \
+ CONNECT3(__using_, __LINE__,_ptr)++ == NULL ? \
+ ((__on_enter_expr),1) : 0; \
+ __on_leave_expr \
+ )
+
+#define __using4(__dcl1, __dcl2, __on_enter_expr, __on_leave_expr) \
+ for (__dcl1, __dcl2, *CONNECT3(__using_, __LINE__,_ptr) = NULL; \
+ CONNECT3(__using_, __LINE__,_ptr)++ == NULL ? \
+ ((__on_enter_expr),1) : 0; \
+ __on_leave_expr \
+ )
+
+#define using(...) \
+ CONNECT2(__using, __PLOOC_VA_NUM_ARGS(__VA_ARGS__))(__VA_ARGS__)
+
+
+#define safe_atom_code() \
+ using( uint32_t CONNECT2(temp,__LINE__) = __disable_irq(), \
+ __set_PRIMASK(CONNECT2(temp,__LINE__)))
+
+#define __with2(__type, __addr) \
+ using(__type *_p=(__addr))
+#define __with3(__type, __addr, __item) \
+ using(__type *_p=(__addr), *__item = _p, _p=_p, )
+
+#define with(...) \
+ CONNECT2(__with, __PLOOC_VA_NUM_ARGS(__VA_ARGS__))(__VA_ARGS__)
+
+#undef _
+#define _ (*_p)
+
+#ifndef dimof
+# define dimof(__array) (sizeof(__array)/sizeof(__array[0]))
+#endif
+
+#define foreach2(__type, __array) \
+ using(__type *_p = __array) \
+ for ( uint_fast32_t CONNECT2(count,__LINE__) = dimof(__array); \
+ CONNECT2(count,__LINE__) > 0; \
+ _p++, CONNECT2(count,__LINE__)-- \
+ )
+
+#define foreach3(__type, __array, __item) \
+ using(__type *_p = __array, *__item = _p, _p = _p, ) \
+ for ( uint_fast32_t CONNECT2(count,__LINE__) = dimof(__array); \
+ CONNECT2(count,__LINE__) > 0; \
+ _p++, __item = _p, CONNECT2(count,__LINE__)-- \
+ )
+
+#define foreach(...) \
+ CONNECT2(foreach, __PLOOC_VA_NUM_ARGS(__VA_ARGS__))(__VA_ARGS__)
+
+#ifndef safe_atom_code
+# define safe_atom_code() \
+ using( uint32_t CONNECT2(temp,__LINE__) = __disable_irq(), \
+ __set_PRIMASK(CONNECT2(temp,__LINE__)))
+#endif
+
+/*============================ MACROFIED FUNCTIONS ===========================*/
+
+
+#define __cycleof__(__STR) \
+ for (int32_t nCycles = 0, \
+ CONNECT2(__cycle_count_s_, __LINE__) = 1; \
+ CONNECT2(__cycle_count_s_, __LINE__)-- ? \
+ (start_cycle_counter(),1) : \
+ ( \
+ printf( "\r\n-[Cycle Report]" \
+ "--------------------------------------------\r\n" \
+ __STR \
+ " total cycle count: %d [%08x]\r\n", nCycles, nCycles) \
+ ,0); \
+ nCycles = stop_cycle_counter() \
+ )
+
+/*============================ TYPES =========================================*/
+/*============================ GLOBAL VARIABLES ==============================*/
+/*============================ LOCAL VARIABLES ===============================*/
+/*============================ PROTOTYPES ====================================*/
+
+/* Function: initialise cycle counter service
+ * and don't forget to tell the function whether the systick is already
+ * used by user applications.
+ * Don't worry, this cycle counter service won't affect your existing
+ * systick service.
+ */
+extern void init_cycle_counter(bool bSysTickIsOccupied);
+
+/* Function : start_time
+ This function will be called right before starting the timed portion of the benchmark.
+ Implementation may be capturing a system timer (as implemented in the example code)
+ or zeroing some system parameters - e.g. setting the cpu clocks cycles to 0.
+*/
+extern void start_cycle_counter(void);
+
+/* Function : stop_time
+ This function will be called right after ending the timed portion of the benchmark.
+ Implementation may be capturing a system timer (as implemented in the example code)
+ or other system parameters - e.g. reading the current value of cpu cycles counter.
+*/
+extern int32_t stop_cycle_counter(void);
+
+/* Function : delay specified us with the help from systick
+ */
+extern void delay_us(int32_t iUs);
+
+#endif
diff --git a/lib/perf_counter.lib b/lib/perf_counter.lib
new file mode 100644
index 0000000..817f794
Binary files /dev/null and b/lib/perf_counter.lib differ
diff --git a/perf_counter.c b/perf_counter.c
new file mode 100644
index 0000000..e8e8883
--- /dev/null
+++ b/perf_counter.c
@@ -0,0 +1,250 @@
+#include
+#include
+#include
+#include "cmsis_compiler.h"
+#include "perf_counter.h"
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+
+/*
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/*
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5U];
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+extern uint32_t SystemCoreClock;
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+ */
+static __attribute__((always_inline)) uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ safe_atom_code(){
+ SysTick->CTRL = 0;
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ //NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ SCB->ICSR = SCB_ICSR_PENDSTCLR_Msk;
+ }
+ return (0UL); /* Function successful */
+}
+
+
+
+volatile static int32_t s_nCycleCounts = 0;
+static volatile int32_t s_nOffset = 0;
+
+volatile static int64_t s_lSystemClockCounts = 0;
+
+void user_code_insert_to_systick_handler(void)
+{
+ uint32_t wLoad = SysTick->LOAD;
+ s_nCycleCounts += wLoad;
+ s_lSystemClockCounts += wLoad;
+}
+
+void init_cycle_counter(bool bSysTickIsOccupied)
+{
+ if (!bSysTickIsOccupied) {
+ SysTick_Config(SystemCoreClock/1000);
+ }
+ start_cycle_counter();
+ //s_nSystemClockCounts = s_nCycleCounts;
+ s_nOffset = stop_cycle_counter();
+
+ extern void __ensure_systick_wrapper(void);
+ __ensure_systick_wrapper();
+}
+
+/* Function : start_time
+ This function will be called right before starting the timed portion of the benchmark.
+ Implementation may be capturing a system timer (as implemented in the example code)
+ or zeroing some system parameters - e.g. setting the cpu clocks cycles to 0.
+*/
+void start_cycle_counter(void)
+{
+ safe_atom_code(){
+ s_nCycleCounts = (int32_t)SysTick->VAL - (int32_t)SysTick->LOAD;
+ }
+}
+
+static __attribute__((always_inline)) int32_t check_systick(void)
+{
+ int32_t nTemp = 0;
+ bool bPendST = 0;
+
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
+ nTemp = (int32_t)SysTick->LOAD - (int32_t)SysTick->VAL;
+ bPendST = (0 != (SCB->ICSR & SCB_ICSR_PENDSTSET_Msk));
+ SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
+
+ /*! \note here is a corner case: SysTick->VAL is zero and SysTick Pending bit is set.
+ *! we should check this corner condition with (nTemp != SysTick->LOAD)
+ */
+ if (bPendST && (nTemp != SysTick->LOAD)) {
+ nTemp += SysTick->LOAD;
+ }
+
+ return nTemp;
+}
+
+/* Function : stop_time
+ This function will be called right after ending the timed portion of the benchmark.
+ Implementation may be capturing a system timer (as implemented in the example code)
+ or other system parameters - e.g. reading the current value of cpu cycles counter.
+*/
+int32_t stop_cycle_counter(void)
+{
+ int32_t nTemp = 0;
+
+ safe_atom_code(){
+ nTemp = check_systick() + s_nCycleCounts;
+ }
+
+ return nTemp - s_nOffset;
+}
+
+
+__attribute__((constructor(255)))
+void __perf_counter_init(void)
+{
+ init_cycle_counter(true);
+}
+
+void delay_us(int32_t iUs)
+{
+ iUs *= SystemCoreClock / 1000000ul;
+
+ start_cycle_counter();
+ while(stop_cycle_counter() < iUs);
+}
+
+
+_ARMABI
+int64_t clock(void)
+{
+ int64_t lTemp = 0;
+
+ safe_atom_code(){
+ lTemp = check_systick() + s_lSystemClockCounts;
+ }
+
+ return lTemp;
+}
diff --git a/perf_counter.h b/perf_counter.h
new file mode 100644
index 0000000..237abd5
--- /dev/null
+++ b/perf_counter.h
@@ -0,0 +1,183 @@
+/****************************************************************************
+* *
+* Licensed under the Apache License, Version 2.0 (the "License"); *
+* you may not use this file except in compliance with the License. *
+* You may obtain a copy of the License at *
+* *
+* http://www.apache.org/licenses/LICENSE-2.0 *
+* *
+* Unless required by applicable law or agreed to in writing, software *
+* distributed under the License is distributed on an "AS IS" BASIS, *
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. *
+* See the License for the specific language governing permissions and *
+* limitations under the License. *
+* *
+****************************************************************************/
+
+
+
+#ifndef __PERFORMANCE_COUNTER_H__
+#define __PERFORMANCE_COUNTER_H__
+
+/*============================ INCLUDES ======================================*/
+#include
+#include
+
+/*============================ MACROS ========================================*/
+
+#define __PLOOC_VA_NUM_ARGS_IMPL( _0,_1,_2,_3,_4,_5,_6,_7,_8,_9,_10,_11,_12, \
+ _13,_14,_15,_16,__N,...) __N
+#define __PLOOC_VA_NUM_ARGS(...) \
+ __PLOOC_VA_NUM_ARGS_IMPL( 0,##__VA_ARGS__,16,15,14,13,12,11,10,9, \
+ 8,7,6,5,4,3,2,1,0)
+
+#define __CONNECT2(__A, __B) __A##__B
+#define __CONNECT3(__A, __B, __C) __A##__B##__C
+#define __CONNECT4(__A, __B, __C, __D) __A##__B##__C##__D
+#define __CONNECT5(__A, __B, __C, __D, __E) __A##__B##__C##__D##__E
+#define __CONNECT6(__A, __B, __C, __D, __E, __F) __A##__B##__C##__D##__E##__F
+#define __CONNECT7(__A, __B, __C, __D, __E, __F, __G) \
+ __A##__B##__C##__D##__E##__F##__G
+#define __CONNECT8(__A, __B, __C, __D, __E, __F, __G, __H) \
+ __A##__B##__C##__D##__E##__F##__G##__H
+#define __CONNECT9(__A, __B, __C, __D, __E, __F, __G, __H, __I) \
+ __A##__B##__C##__D##__E##__F##__G##__H##__I
+
+#define CONNECT2(__A, __B) __CONNECT2(__A, __B)
+#define CONNECT3(__A, __B, __C) __CONNECT3(__A, __B, __C)
+#define CONNECT4(__A, __B, __C, __D) __CONNECT4(__A, __B, __C, __D)
+#define CONNECT5(__A, __B, __C, __D, __E) __CONNECT5(__A, __B, __C, __D, __E)
+#define CONNECT6(__A, __B, __C, __D, __E, __F) \
+ __CONNECT6(__A, __B, __C, __D, __E, __F)
+#define CONNECT7(__A, __B, __C, __D, __E, __F, __G) \
+ __CONNECT7(__A, __B, __C, __D, __E, __F, __G)
+#define CONNECT8(__A, __B, __C, __D, __E, __F, __G, __H) \
+ __CONNECT8(__A, __B, __C, __D, __E, __F, __G, __H)
+#define CONNECT9(__A, __B, __C, __D, __E, __F, __G, __H, __I) \
+ __CONNECT9(__A, __B, __C, __D, __E, __F, __G, __H, __I)
+
+#define CONNECT(...) \
+ CONNECT2(CONNECT, __PLOOC_VA_NUM_ARGS(__VA_ARGS__))(__VA_ARGS__)
+
+
+
+#define __using1(__declare) \
+ for (__declare, *CONNECT3(__using_, __LINE__,_ptr) = NULL; \
+ CONNECT3(__using_, __LINE__,_ptr)++ == NULL; \
+ )
+
+#define __using2(__declare, __on_leave_expr) \
+ for (__declare, *CONNECT3(__using_, __LINE__,_ptr) = NULL; \
+ CONNECT3(__using_, __LINE__,_ptr)++ == NULL; \
+ __on_leave_expr \
+ )
+
+#define __using3(__declare, __on_enter_expr, __on_leave_expr) \
+ for (__declare, *CONNECT3(__using_, __LINE__,_ptr) = NULL; \
+ CONNECT3(__using_, __LINE__,_ptr)++ == NULL ? \
+ ((__on_enter_expr),1) : 0; \
+ __on_leave_expr \
+ )
+
+#define __using4(__dcl1, __dcl2, __on_enter_expr, __on_leave_expr) \
+ for (__dcl1, __dcl2, *CONNECT3(__using_, __LINE__,_ptr) = NULL; \
+ CONNECT3(__using_, __LINE__,_ptr)++ == NULL ? \
+ ((__on_enter_expr),1) : 0; \
+ __on_leave_expr \
+ )
+
+#define using(...) \
+ CONNECT2(__using, __PLOOC_VA_NUM_ARGS(__VA_ARGS__))(__VA_ARGS__)
+
+
+#define safe_atom_code() \
+ using( uint32_t CONNECT2(temp,__LINE__) = __disable_irq(), \
+ __set_PRIMASK(CONNECT2(temp,__LINE__)))
+
+#define __with2(__type, __addr) \
+ using(__type *_p=(__addr))
+#define __with3(__type, __addr, __item) \
+ using(__type *_p=(__addr), *__item = _p, _p=_p, )
+
+#define with(...) \
+ CONNECT2(__with, __PLOOC_VA_NUM_ARGS(__VA_ARGS__))(__VA_ARGS__)
+
+#undef _
+#define _ (*_p)
+
+#ifndef dimof
+# define dimof(__array) (sizeof(__array)/sizeof(__array[0]))
+#endif
+
+#define foreach2(__type, __array) \
+ using(__type *_p = __array) \
+ for ( uint_fast32_t CONNECT2(count,__LINE__) = dimof(__array); \
+ CONNECT2(count,__LINE__) > 0; \
+ _p++, CONNECT2(count,__LINE__)-- \
+ )
+
+#define foreach3(__type, __array, __item) \
+ using(__type *_p = __array, *__item = _p, _p = _p, ) \
+ for ( uint_fast32_t CONNECT2(count,__LINE__) = dimof(__array); \
+ CONNECT2(count,__LINE__) > 0; \
+ _p++, __item = _p, CONNECT2(count,__LINE__)-- \
+ )
+
+#define foreach(...) \
+ CONNECT2(foreach, __PLOOC_VA_NUM_ARGS(__VA_ARGS__))(__VA_ARGS__)
+
+#ifndef safe_atom_code
+# define safe_atom_code() \
+ using( uint32_t CONNECT2(temp,__LINE__) = __disable_irq(), \
+ __set_PRIMASK(CONNECT2(temp,__LINE__)))
+#endif
+
+/*============================ MACROFIED FUNCTIONS ===========================*/
+
+
+#define __cycleof__(__STR) \
+ for (int32_t nCycles = 0, \
+ CONNECT2(__cycle_count_s_, __LINE__) = 1; \
+ CONNECT2(__cycle_count_s_, __LINE__)-- ? \
+ (start_cycle_counter(),1) : \
+ ( \
+ printf( "\r\n-[Cycle Report]" \
+ "--------------------------------------------\r\n" \
+ __STR \
+ " total cycle count: %d [%08x]\r\n", nCycles, nCycles) \
+ ,0); \
+ nCycles = stop_cycle_counter() \
+ )
+
+/*============================ TYPES =========================================*/
+/*============================ GLOBAL VARIABLES ==============================*/
+/*============================ LOCAL VARIABLES ===============================*/
+/*============================ PROTOTYPES ====================================*/
+
+/* Function: initialise cycle counter service
+ * and don't forget to tell the function whether the systick is already
+ * used by user applications.
+ * Don't worry, this cycle counter service won't affect your existing
+ * systick service.
+ */
+extern void init_cycle_counter(bool bSysTickIsOccupied);
+
+/* Function : start_time
+ This function will be called right before starting the timed portion of the benchmark.
+ Implementation may be capturing a system timer (as implemented in the example code)
+ or zeroing some system parameters - e.g. setting the cpu clocks cycles to 0.
+*/
+extern void start_cycle_counter(void);
+
+/* Function : stop_time
+ This function will be called right after ending the timed portion of the benchmark.
+ Implementation may be capturing a system timer (as implemented in the example code)
+ or other system parameters - e.g. reading the current value of cpu cycles counter.
+*/
+extern int32_t stop_cycle_counter(void);
+
+/* Function : delay specified us with the help from systick
+ */
+extern void delay_us(int32_t iUs);
+
+#endif
diff --git a/systick_wrapper_ual.s b/systick_wrapper_ual.s
new file mode 100644
index 0000000..9e77b66
--- /dev/null
+++ b/systick_wrapper_ual.s
@@ -0,0 +1,23 @@
+ PRESERVE8
+ THUMB
+ AREA |.text|, CODE, READONLY
+
+|$Sub$$SysTick_Handler| PROC
+ EXPORT |$Sub$$SysTick_Handler|
+ IMPORT user_code_insert_to_systick_handler
+ IMPORT |$Super$$SysTick_Handler|
+ push {r4, lr}
+ bl user_code_insert_to_systick_handler
+ pop {r4, lr}
+ b |$Super$$SysTick_Handler|
+ ENDP
+
+ AREA |.text|, CODE, READONLY
+
+__ensure_systick_wrapper PROC
+ EXPORT __ensure_systick_wrapper
+ NOP
+ BX LR
+ ENDP
+
+ END
\ No newline at end of file