mirror of
https://github.com/GorgonMeducer/perf_counter.git
synced 2025-01-31 19:33:04 +08:00
231 lines
11 KiB
C
231 lines
11 KiB
C
/****************************************************************************
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* Copyright 2024 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) *
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* *
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* Licensed under the Apache License, Version 2.0 (the "License"); *
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* you may not use this file except in compliance with the License. *
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* You may obtain a copy of the License at *
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* *
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* http://www.apache.org/licenses/LICENSE-2.0 *
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* *
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* Unless required by applicable law or agreed to in writing, software *
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* distributed under the License is distributed on an "AS IS" BASIS, *
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. *
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* See the License for the specific language governing permissions and *
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* limitations under the License. *
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* *
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****************************************************************************/
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/*============================ INCLUDES ======================================*/
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#undef __PERF_COUNT_PLATFORM_SPECIFIC_HEADER__
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#include <stdint.h>
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#include <stdbool.h>
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#include <string.h>
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#include "cmsis_compiler.h"
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#define __IMPLEMENT_PERF_COUNTER
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#include "perf_counter.h"
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#if defined(__IS_COMPILER_GCC__)
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# pragma GCC diagnostic ignored "-Wattributes"
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#endif
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#if defined(__clang__)
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# pragma clang diagnostic ignored "-Wunknown-warning-option"
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# pragma clang diagnostic ignored "-Wreserved-identifier"
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# pragma clang diagnostic ignored "-Wconditional-uninitialized"
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# pragma clang diagnostic ignored "-Wcast-align"
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# pragma clang diagnostic ignored "-Wmissing-prototypes"
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#endif
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/*============================ MACROS ========================================*/
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/* IO definitions (access restrictions to peripheral registers) */
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#ifdef __cplusplus
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#define __I volatile /*!< Defines 'read only' permissions */
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#else
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#define __I volatile const /*!< Defines 'read only' permissions */
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#endif
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#define __O volatile /*!< Defines 'write only' permissions */
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#define __IO volatile /*!< Defines 'read / write' permissions */
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/* following defines should be used for structure members */
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#define __IM volatile const /*! Defines 'read only' structure member permissions */
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#define __OM volatile /*! Defines 'write only' structure member permissions */
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#define __IOM volatile /*! Defines 'read / write' structure member permissions */
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/* Memory mapping of Core Hardware */
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#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
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#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
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#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
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#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
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#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
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/* SysTick Control / Status Register Definitions */
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#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
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#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
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#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
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#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
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#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
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#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
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#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
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#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
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/* SysTick Reload Register Definitions */
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#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
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#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
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/* SysTick Current Register Definitions */
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#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
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#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
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/* SysTick Calibration Register Definitions */
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#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
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#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
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#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
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#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
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#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
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#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
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/*@} end of group CMSIS_SysTick */
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#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
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#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
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#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
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#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
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#ifndef __PERFC_CFG_DISABLE_DEFAULT_SYSTICK_PORTING__
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# define __PERFC_CFG_DISABLE_DEFAULT_SYSTICK_PORTING__ 0
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#endif
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/*============================ MACROFIED FUNCTIONS ===========================*/
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/*============================ TYPES =========================================*/
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/*!
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\brief Structure type to access the System Timer (SysTick).
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*/
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typedef struct
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{
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__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
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__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
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__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
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__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
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} SysTick_Type;
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/*!
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\brief Structure type to access the System Control Block (SCB).
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*/
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typedef struct
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{
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__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
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__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
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__IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
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__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
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__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
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__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
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__IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
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__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
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__IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
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__IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
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__IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
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__IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
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__IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
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__IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
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__IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
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__IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
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__IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
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__IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
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__IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
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uint32_t RESERVED0[5U];
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__IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
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} SCB_Type;
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/*============================ GLOBAL VARIABLES ==============================*/
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extern uint32_t SystemCoreClock;
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/*============================ LOCAL VARIABLES ===============================*/
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/*============================ PROTOTYPES ====================================*/
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/*============================ IMPLEMENTATION ================================*/
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/*============================ INCLUDES ======================================*/
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#if !__PERFC_CFG_DISABLE_DEFAULT_SYSTICK_PORTING__
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__WEAK
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bool perfc_port_init_system_timer(bool bTimerOccupied)
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{
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do {
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if (bTimerOccupied) {
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break;
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}
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__IRQ_SAFE {
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SysTick->CTRL = 0;
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SysTick->LOAD = SysTick_LOAD_RELOAD_Msk; /* set reload register */
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//NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
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SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
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SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
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SysTick_CTRL_TICKINT_Msk |
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SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
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//SCB->ICSR = SCB_ICSR_PENDSTCLR_Msk;
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}
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} while(0);
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return true;
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}
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__WEAK
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uint32_t perfc_port_get_system_timer_freq(void)
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{
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return SystemCoreClock;
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}
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__WEAK
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bool perfc_port_is_system_timer_ovf_pending(void)
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{
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return SCB->ICSR & SCB_ICSR_PENDSTSET_Msk;
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}
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__WEAK
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int64_t perfc_port_get_system_timer_top(void)
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{
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return SysTick->LOAD;
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}
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__WEAK
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int64_t perfc_port_get_system_timer_elapsed(void)
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{
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return (int64_t)SysTick->LOAD - (uint32_t)SysTick->VAL;
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}
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__WEAK
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void perfc_port_clear_system_timer_ovf_pending(void)
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{
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SCB->ICSR = SCB_ICSR_PENDSTCLR_Msk;
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}
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__WEAK
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void perfc_port_stop_system_timer_counting(void)
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{
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SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
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}
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__WEAK
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void perfc_port_clear_system_timer_counter(void)
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{
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SysTick->VAL = 0UL;
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}
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#endif
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