mirror of
https://github.com/GorgonMeducer/perf_counter.git
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374 lines
18 KiB
C
374 lines
18 KiB
C
/****************************************************************************
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* Copyright 2021 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) *
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* *
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* Licensed under the Apache License, Version 2.0 (the "License"); *
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* you may not use this file except in compliance with the License. *
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* You may obtain a copy of the License at *
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* *
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* http://www.apache.org/licenses/LICENSE-2.0 *
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* *
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* Unless required by applicable law or agreed to in writing, software *
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* distributed under the License is distributed on an "AS IS" BASIS, *
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. *
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* See the License for the specific language governing permissions and *
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* limitations under the License. *
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* *
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****************************************************************************/
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/*============================ INCLUDES ======================================*/
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#include <stdint.h>
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#include <stdbool.h>
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#include <string.h>
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#include "cmsis_compiler.h"
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#include "perf_counter.h"
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#if defined(__IS_COMPILER_GCC__)
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# pragma GCC diagnostic ignored "-Wattributes"
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#endif
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/*============================ MACROS ========================================*/
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#ifndef PERF_CNT_COMPENSATION_THRESHOLD
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# define PERF_CNT_COMPENSATION_THRESHOLD 16
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#endif
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#ifndef PERF_CNT_DELAY_US_COMPENSATION
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# define PERF_CNT_DELAY_US_COMPENSATION 90
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#endif
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/* IO definitions (access restrictions to peripheral registers) */
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/**
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\defgroup CMSIS_glob_defs CMSIS Global Defines
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<strong>IO Type Qualifiers</strong> are used
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\li to specify the access to peripheral variables.
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\li for automatic generation of peripheral register debug information.
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*/
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#ifdef __cplusplus
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#define __I volatile /*!< Defines 'read only' permissions */
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#else
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#define __I volatile const /*!< Defines 'read only' permissions */
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#endif
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#define __O volatile /*!< Defines 'write only' permissions */
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#define __IO volatile /*!< Defines 'read / write' permissions */
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/* following defines should be used for structure members */
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#define __IM volatile const /*! Defines 'read only' structure member permissions */
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#define __OM volatile /*! Defines 'write only' structure member permissions */
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#define __IOM volatile /*! Defines 'read / write' structure member permissions */
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/* Memory mapping of Core Hardware */
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#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
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#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
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#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
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#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
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#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
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/* SysTick Control / Status Register Definitions */
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#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
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#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
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#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
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#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
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#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
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#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
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#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
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#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
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/* SysTick Reload Register Definitions */
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#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
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#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
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/* SysTick Current Register Definitions */
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#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
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#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
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/* SysTick Calibration Register Definitions */
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#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
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#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
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#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
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#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
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#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
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#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
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/*@} end of group CMSIS_SysTick */
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#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
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#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
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#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
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#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
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/*============================ MACROFIED FUNCTIONS ===========================*/
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/*============================ TYPES =========================================*/
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/*
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\brief Structure type to access the System Timer (SysTick).
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*/
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typedef struct
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{
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__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
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__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
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__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
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__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
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} SysTick_Type;
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/*
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\brief Structure type to access the System Control Block (SCB).
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*/
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typedef struct
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{
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__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
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__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
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__IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
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__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
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__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
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__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
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__IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
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__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
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__IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
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__IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
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__IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
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__IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
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__IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
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__IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
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__IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
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__IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
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__IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
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__IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
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__IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
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uint32_t RESERVED0[5U];
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__IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
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} SCB_Type;
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/*============================ GLOBAL VARIABLES ==============================*/
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extern uint32_t SystemCoreClock;
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/*============================ LOCAL VARIABLES ===============================*/
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volatile static int32_t s_nCycleCounts = 0;
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volatile static int32_t s_nOffset = 0;
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volatile static int32_t s_nUnit = 1;
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volatile static int64_t s_lSystemClockCounts = 0;
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/*============================ PROTOTYPES ====================================*/
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/*============================ IMPLEMENTATION ================================*/
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/*============================ INCLUDES ======================================*/
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/**
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\brief System Tick Configuration
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\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
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Counter is in free running mode to generate periodic interrupts.
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\param [in] ticks Number of ticks between two interrupts.
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\return 0 Function succeeded.
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\return 1 Function failed.
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\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
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function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
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must contain a vendor-specific implementation of this function.
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*/
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static __attribute__((always_inline)) uint32_t SysTick_Config(uint32_t ticks)
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{
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if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
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{
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return (1UL); /* Reload value impossible */
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}
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//__IRQ_SAFE {
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SysTick->CTRL = 0;
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SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
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//NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
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SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
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SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
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SysTick_CTRL_TICKINT_Msk |
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SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
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//SCB->ICSR = SCB_ICSR_PENDSTCLR_Msk;
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//}
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return (0UL); /* Function successful */
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}
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void user_code_insert_to_systick_handler(void)
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{
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uint32_t wLoad = SysTick->LOAD + 1;
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s_nCycleCounts += wLoad;
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s_lSystemClockCounts += wLoad;
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}
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/*! \brief initialise cycle counter service
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*! and don't forget to tell the function whether the systick is already
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*! used by user applications.
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*! Don't worry, this cycle counter service won't affect your existing
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*! systick service.
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*! \param bSysTickIsOccupied A boolean value which indicates whether SysTick
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*! is already used by user application.
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*/
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void init_cycle_counter(bool bSysTickIsOccupied)
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{
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__IRQ_SAFE {
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if (!bSysTickIsOccupied) {
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SysTick_Config(0x01000000); //!< use the longest period
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}
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SCB->ICSR = SCB_ICSR_PENDSTCLR_Msk;
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}
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start_cycle_counter();
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//s_nSystemClockCounts = s_nCycleCounts;
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s_nOffset = stop_cycle_counter();
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s_nUnit = SystemCoreClock / 1000000ul;
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#if defined(__IS_COMPILER_ARM_COMPILER_5__) \
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|| defined(__IS_COMPILER_ARM_COMPILER_6__) \
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|| defined(__IS_COMPILER_GCC__)
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extern void __ensure_systick_wrapper(void);
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__ensure_systick_wrapper();
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#endif
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}
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/*! \brief try to start the performance counter
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*! \retval false the LOAD register is too small
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*! \retval true performance counter starts
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*/
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bool start_cycle_counter(void)
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{
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if (SysTick->LOAD < PERF_CNT_COMPENSATION_THRESHOLD) {
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return false;
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}
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__IRQ_SAFE {
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s_nCycleCounts = (int32_t)SysTick->VAL - (int32_t)SysTick->LOAD;
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}
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return true;
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}
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/*! \note this function should only be called when irq is disabled
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*! hence SysTick-LOAD and (SCB->ICSR & SCB_ICSR_PENDSTSET_Msk)
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*! won't change.
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*/
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static __attribute__((always_inline)) int32_t check_systick(void)
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{
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int32_t nTemp = (int32_t)SysTick->LOAD - (int32_t)SysTick->VAL;
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/*! \note Since we cannot stop counting temporarily, there are several
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*! conditions which we should take into consideration:
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*! Condition 1: when assigning nTemp with the register value (LOAD-VAL),
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*! the underflow didn't happen but when we check the PENDSTSET bit,
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*! the underflow happens, for this condition, we should not
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*! do any compensation. When this happens, the (LOAD-nTemp) is
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*! smaller than PERF_CNT_COMPENSATION_THRESHOLD (a small value) as
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*! long as LOAD is bigger than (or equals to) the
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*! PERF_CNT_COMPENSATION_THRESHOLD;
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*! Condition 2: when assigning nTemp with the register value (LOAD-VAL),
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*! the VAL is zero and underflow happened and the PENDSTSET bit
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*! is set, for this condition, we should not do any compensation.
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*! When this happens, the (LOAD-nTemp) is equals to zero.
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*! Condition 3: when assigning nTemp with the register value (LOAD-VAL),
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*! the underflow has already happened, hence the PENDSTSET
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*! is set, for this condition, we should compensate the return
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*! value. When this happens, the (LOAD-nTemp) is bigger than (or
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*! equals to) PERF_CNT_COMPENSATION_THRESHOLD.
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*! The following code implements an equivalent logic.
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*/
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if (SCB->ICSR & SCB_ICSR_PENDSTSET_Msk){
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if (((int32_t)SysTick->LOAD - nTemp) >= PERF_CNT_COMPENSATION_THRESHOLD) {
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nTemp += SysTick->LOAD + 1;
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}
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}
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return nTemp;
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}
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/*! \brief calculate the elapsed cycle count since the last start point
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*!
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*! \note you can have multiple stop_cycle_counter following one start point
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*!
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*! \return the elapsed cycle count.
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*/
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int32_t stop_cycle_counter(void)
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{
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int32_t nTemp = 0;
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__IRQ_SAFE {
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nTemp = check_systick() + s_nCycleCounts;
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}
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return nTemp - s_nOffset;
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}
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__attribute__((constructor(255)))
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void __perf_counter_init(void)
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{
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init_cycle_counter(true);
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}
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void delay_us(int32_t nUs)
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{
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int64_t lUs = nUs * s_nUnit;
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if (lUs <= PERF_CNT_DELAY_US_COMPENSATION) {
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return ;
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}
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lUs -= PERF_CNT_DELAY_US_COMPENSATION;
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lUs += get_system_ticks();
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while(get_system_ticks() < lUs);
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}
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/*! \note the prototype of this clock() is different from the one defined in
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*! time.h. As clock_t is usually defined as unsigned int, it is
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*! not big enough in Cortex-M system to hold a time-stamp. clock()
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*! defined here returns the timestamp since the begining of main()
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*! and its unit is clock cycle (rather than 1ms). Hence, for a system
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*! running under several hundreds MHz or even 1GHz, e.g. RT10xx from
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*! NXP, it is very easy to see a counter overflow as clock_t is
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*! defined as uint32_t in timer.h.
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*! Since we are not allowed to change the defintion of clock_t in
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*! official header file, i.e. time.h, I use a compatible prototype
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*! after I checked the AAPCS spec. So, the return of the clock() is
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*! int64_t, which will use the R0 to store the lower 32bits and R1
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*! to store the higher 32bits. When you are using the prototype from
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*! timer.h, caller will only take the lower 32bits stored in R0 and
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*! the higher 32bits stored in R1 will be ignored.
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*!
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*! If you want to use the non-overflow version of this clock(), please
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*! 1) define the MACRO: __PERF_CNT_USE_LONG_CLOCK__ in your project
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*! and 2) do not include system header file <time.h>
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*!
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*/
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__attribute__((nothrow))
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int64_t clock(void)
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{
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int64_t lTemp = 0;
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__IRQ_SAFE {
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lTemp = check_systick() + s_lSystemClockCounts;
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}
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return lTemp;
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}
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__attribute__((nothrow))
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int64_t get_system_ticks(void)
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{
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int64_t lTemp = 0;
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__IRQ_SAFE {
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lTemp = check_systick() + s_lSystemClockCounts;
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}
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return lTemp;
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}
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