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https://gitee.com/Lyon1998/pikapython.git
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312 lines
9.7 KiB
C
312 lines
9.7 KiB
C
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/*!
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* @file apm32e10x_sci2c.h
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*
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* @brief This file contains all the prototypes,enumeration and macros for the SCI2C(I2C3, I2C4) peripheral
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*
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* @version V1.0.0
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*
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* @date 2021-07-26
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*
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*/
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#ifndef __APM32E10X_SCI2C_H
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#define __APM32E10X_SCI2C_H
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#include "apm32e10x.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @addtogroup Peripherals_Library Standard Peripheral Library
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@{
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*/
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/** @addtogroup SCI2C_Driver SCI2C Driver
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@{
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*/
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/** @addtogroup SCI2C_Enumerations Enumerations
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@{
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*/
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/**
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* @brief SCI2C speed enumeration
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*/
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typedef enum
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{
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SCI2C_SPEED_STANDARD = 1,
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SCI2C_SPEED_FAST,
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SCI2C_SPEED_HIGH
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}SCI2C_SPEED_T;
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/**
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* @brief Address mode
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*/
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typedef enum
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{
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SCI2C_ADDR_MODE_7BIT,
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SCI2C_ADDR_MODE_10BIT
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}SCI2C_ADDR_MODE_T;
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/**
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* @brief SCI2C mode enumeration
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*/
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typedef enum
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{
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SCI2C_MODE_MASTER,
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SCI2C_MODE_SLAVE
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}SCI2C_MODE_T;
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/**
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* @brief Restart enable or disable
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*/
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typedef enum
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{
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SCI2C_RESTART_DISABLE,
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SCI2C_RESTART_ENABLE
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}SCI2C_RESTART_T;
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/**
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* @brief Enable or disable generate stop condition
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*/
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typedef enum
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{
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SCI2C_STOP_DISABLE,
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SCI2C_STOP_ENABLE
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}SCI2C_STOP_T;
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/**
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* @brief Data direction
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*/
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typedef enum
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{
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SCI2C_DATA_DIR_WRITE,
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SCI2C_DATA_DIR_READ,
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}SCI2C_DATA_DIR_T;
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/**
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* @brief SCI2C interrupt
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*/
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typedef enum
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{
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SCI2C_INT_RFU = BIT0, //!< Rx FIFO underflow interrupt
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SCI2C_INT_RFO = BIT1, //!< Rx FIFO onverflow interrupt
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SCI2C_INT_RFF = BIT2, //!< Rx FIFO full interrupt
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SCI2C_INT_TFO = BIT3, //!< Tx FIFO onverflow interrupt
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SCI2C_INT_TFE = BIT4, //!< Tx FIFO empty interrupt
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SCI2C_INT_RR = BIT5, //!< Read request interrupt
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SCI2C_INT_TA = BIT6, //!< Tx abort interrupt
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SCI2C_INT_RD = BIT7, //!< Read done interrupt
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SCI2C_INT_ACT = BIT8, //!< Activity interrupt
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SCI2C_INT_STPD = BIT9, //!< Stop detect interrupt
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SCI2C_INT_STAD = BIT10, //!< Start detect interrupt
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SCI2C_INT_GC = BIT11, //!< Gernal call interrupt
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SCI2C_INT_RSTAD = BIT12, //!< Restart detect interrupt
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SCI2C_INT_MOH = BIT13, //!< Master on hold interrupt
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SCI2C_INT_ALL = BIT15 //!< All interrupt
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}SCI2C_INT_T;
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/**
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* @brief Flag enumeration
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*/
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typedef enum
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{
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SCI2C_FLAG_ACT = BIT0, //!< Activity flag
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SCI2C_FLAG_TFNF = BIT1, //!< Tx FIFO not full flag
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SCI2C_FLAG_TFE = BIT2, //!< Tx FIFO empty flag
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SCI2C_FLAG_RFNE = BIT3, //!< Rx FIFO not empty flag
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SCI2C_FLAG_RFF = BIT4, //!< Rx FIFO full flag
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SCI2C_FLAG_MA = BIT5, //!< Master activity flag
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SCI2C_FLAG_SA = BIT6, //!< Slave activity flag
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SCI2C_FLAG_I2CEN = BIT8 | BIT0, //!< I2C enable flag
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SCI2C_FLAG_SDWB = BIT8 | BIT1, //!< Slave disable while busy flag
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SCI2C_FLAG_SRDL = BIT8 | BIT2 //!< Slave receive data lost flag
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}SCI2C_FLAG_T;
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/**
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* @brief Tx abort source
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*/
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typedef enum
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{
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SCI2C_TAS_AD7NA = BIT0, //!< 7 bit address mode NACK
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SCI2C_TAS_AD10FBNA = BIT1, //!< 10 bit address mode first byte NACK
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SCI2C_TAS_AD10SBNA = BIT2, //!< 10 bit address mode second byte NACK
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SCI2C_TAS_TDNA = BIT3, //!< Tx data NACK
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SCI2C_TAS_GCNA = BIT4, //!< Gernal call NACK
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SCI2C_TAS_GCR = BIT5, //!< Gernal call read
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SCI2C_TAS_HSAD = BIT6, //!< High speed ack detected
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SCI2C_TAS_SNR = BIT7, //!< Start byte no restart
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SCI2C_TAS_RNR10B = BIT8, //!< Read 10bit address mode when restart disable
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SCI2C_TAS_MSTDIS = BIT9, //!< Master disable
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SCI2C_TAS_ARBLOST = BIT10, //!< Arbitration lost
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SCI2C_TAS_LFTF = BIT11, //!< Slave flush tx FIFO
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SCI2C_TAS_SAL = BIT12, //!< Slave arbitration lost
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SCI2C_TAS_SRI = BIT13, //!< Slave read done
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SCI2C_TAS_USRARB = BIT14, //!< User abort
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SCI2C_TAS_FLUCNT = BIT15 //!< Tx flush counter
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}SCI2C_TAS_T;
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/**
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* @brief DMA Enable
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*/
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typedef enum
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{
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SCI2C_DMA_RX = BIT0,
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SCI2C_DMA_TX = BIT1,
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}SCI2C_DMA_T;
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/**@} end of group SCI2C_Enumerations*/
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/** @addtogroup SCI2C_Macros Macros
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@{
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*/
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/** Macros description */
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#define SCI2C_CTRL1_RESET_VALUE ((uint32_t)0x3E)
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#define SCI2C_TARADDR_RESET_VALUE ((uint32_t)0x1055)
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#define SCI2C_SLAADDR_RESET_VALUE ((uint32_t)0x55)
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#define SCI2C_HSMC_RESET_VALUE ((uint32_t)0x07)
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#define SCI2C_DATA_RESET_VALUE ((uint32_t)0x00)
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#define SCI2C_SSCHC_RESET_VALUE ((uint32_t)0x190)
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#define SCI2C_SSCLC_RESET_VALUE ((uint32_t)0x1D6)
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#define SCI2C_FSCHC_RESET_VALUE ((uint32_t)0x3C)
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#define SCI2C_FSCLC_RESET_VALUE ((uint32_t)0x82)
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#define SCI2C_HSCHC_RESET_VALUE ((uint32_t)0x06)
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#define SCI2C_HSCLC_RESET_VALUE ((uint32_t)0x10)
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#define SCI2C_INTEN_RESET_VALUE ((uint32_t)0x00)
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#define SCI2C_RFT_RESET_VALUE ((uint32_t)0x00)
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#define SCI2C_TFT_RESET_VALUE ((uint32_t)0x00)
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#define SCI2C_CTRL2_RESET_VALUE ((uint32_t)0x00)
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#define SCI2C_TFL_RESET_VALUE ((uint32_t)0x00)
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#define SCI2C_RFL_RESET_VALUE ((uint32_t)0x00)
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#define SCI2C_SDAHOLD_RESET_VALUE ((uint32_t)0x01)
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#define SCI2C_SDNO_RESET_VALUE ((uint32_t)0x00)
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#define SCI2C_DMACTRL_RESET_VALUE ((uint32_t)0x00)
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#define SCI2C_DTDL_RESET_VALUE ((uint32_t)0x00)
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#define SCI2C_DRDL_RESET_VALUE ((uint32_t)0x00)
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#define SCI2C_SDADLY_RESET_VALUE ((uint32_t)0x64)
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#define SCI2C_GCA_RESET_VALUE ((uint32_t)0x01)
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#define SCI2C_LSSSL_RESET_VALUE ((uint32_t)0x05)
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#define SCI2C_HSSSL_RESET_VALUE ((uint32_t)0x01)
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#define SCI2C_FIFO_DEPTH (0X08)
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/**@} end of group SCI2C_Macros*/
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/** @addtogroup SCI2C_Structure Data Structure
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@{
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*/
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/**
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* @brief Struct description
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*/
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typedef struct
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{
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uint16_t slaveAddr; //!< Slave address.
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SCI2C_MODE_T mode; //!< Specifies mode, master mode or slave mode
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SCI2C_SPEED_T speed; //!< Specifies speed. Standard speed, fast speed or high speed.
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uint16_t clkLowPeriod; //!< SCL high period
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uint16_t clkHighPeriod; //!< SCL low period
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uint8_t rxFifoThreshold; //!< Rx FIFO threshold
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uint8_t txFifoThreshold; //!< Tx FIFO threshold
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SCI2C_RESTART_T restart; //!< Enable or disable restart
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SCI2C_ADDR_MODE_T addrMode; //!< Address mode. 7-bit or 10-bit mode.
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}SCI2C_Config_T;
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/**@} end of group SCI2C_Structure*/
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/** @addtogroup SCI2C_Fuctions Fuctions
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@{
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*/
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/** Reset */
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void SCI2C_Reset(SCI2C_T *i2c);
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/** Configuration */
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void SCI2C_Config(SCI2C_T *i2c, SCI2C_Config_T *sci2cConfig);
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void SCI2C_ConfigStructInit(SCI2C_Config_T *sci2cConfig);
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/** Stop detect */
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void SCI2C_EnableStopDetectAddressed(SCI2C_T *i2c);
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void SCI2C_DisableStopDetectAddressed(SCI2C_T *i2c);
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void SCI2C_EnableStopDetectMasterActivity(SCI2C_T *i2c);
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void SCI2C_DisableStopDetectMasterActivity(SCI2C_T *i2c);
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/** Restart */
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void SCI2C_EnableRestart(SCI2C_T *i2c);
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void SCI2C_DisableRestart(SCI2C_T *i2c);
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/** Speed */
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void SCI2C_ConfigSpeed(SCI2C_T *i2c, SCI2C_SPEED_T speed);
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/** Address */
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void SCI2C_ConfigMasterAddr(SCI2C_T *i2c, SCI2C_ADDR_MODE_T mode, uint16_t addr);
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void SCI2C_ConfigSlaveAddr(SCI2C_T *i2c, SCI2C_ADDR_MODE_T mode, uint16_t addr);
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/** Master mode and slave mode */
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void SCI2C_EnableMasterMode(SCI2C_T *i2c);
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void SCI2C_DisableMasterMode(SCI2C_T *i2c);
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void SCI2C_EnableSlaveMode(SCI2C_T *i2c);
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void SCI2C_DisableSlaveMode(SCI2C_T *i2c);
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void SCI2C_ConfigMasterCode(SCI2C_T *i2c, uint8_t code);
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/** Data */
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void SCI2C_ConfigDataDir(SCI2C_T *i2c, SCI2C_DATA_DIR_T dir);
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void SCI2C_TxData(SCI2C_T *i2c, uint8_t data);
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uint8_t SCI2C_RxData(SCI2C_T *i2c);
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void SCI2C_ConfigDataRegister(SCI2C_T *i2c, SCI2C_STOP_T stop, SCI2C_DATA_DIR_T dataDir, uint8_t data);
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/** Rx and Tx FIFO */
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uint8_t SCI2C_ReadRxFifoDataCnt(SCI2C_T *i2c);
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uint8_t SCI2C_ReadTxFifoDataCnt(SCI2C_T *i2c);
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void SCI2C_ConfigRxFifoThreshold(SCI2C_T *i2c, uint8_t threshold);
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void SCI2C_ConfigTxFifoThreshold(SCI2C_T *i2c, uint8_t threshold);
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/** I2C Enable, disable, abort, block */
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void SCI2C_Enable(SCI2C_T *i2c);
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void SCI2C_Disable(SCI2C_T *i2c);
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void SCI2C_Abort(SCI2C_T *i2c);
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void SCI2C_BlockTxCmd(SCI2C_T *i2c, uint8_t enable);
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/** SCL and SDA */
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void SCI2C_ConfigClkPeriod(SCI2C_T *i2c, SCI2C_SPEED_T speed, uint16_t highPeriod, uint16_t lowPeriod);
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void SCI2C_ConfigSDAHoldTime(SCI2C_T *i2c, uint16_t txHold, uint8_t rxHold);
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void SCI2C_ConfigSDADelayTime(SCI2C_T *i2c, uint8_t delay);
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/** ACK and NACK */
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void SCI2C_GernalCallAck(SCI2C_T *i2c, uint8_t enable);
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void SCI2C_SlaveDataNackOnly(SCI2C_T *i2c, uint8_t enable);
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/** Abort */
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uint32_t SCI2C_ReadTxAbortSource(SCI2C_T *i2c);
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/** DMA */
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void SCI2C_EnableDMA(SCI2C_T *i2c, SCI2C_DMA_T dma);
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void SCI2C_DisableDMA(SCI2C_T *i2c, SCI2C_DMA_T dma);
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void SCI2C_ConfigDMATxDataLevel(SCI2C_T *i2c, uint8_t cnt);
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void SCI2C_ConfigDMARxDataLevel(SCI2C_T *i2c, uint8_t cnt);
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/** Spike suppression limit */
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void SCI2C_ConfigSpikeSuppressionLimit(SCI2C_T *i2c, SCI2C_SPEED_T speed, uint8_t limit);
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/** Ingerrupt and flag */
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uint8_t SCI2C_ReadStatusFlag(SCI2C_T *i2c, SCI2C_FLAG_T flag);
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void SCI2C_ClearIntFlag(SCI2C_T *i2c, SCI2C_INT_T flag);
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uint8_t SCI2C_ReadIntFlag(SCI2C_T *i2c, SCI2C_INT_T flag);
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uint8_t SCI2C_ReadRawIntFlag(SCI2C_T *i2c, SCI2C_INT_T flag);
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void SCI2C_EnableInterrupt(SCI2C_T *i2c, uint16_t interrupt);
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void SCI2C_DisableInterrupt(SCI2C_T *i2c, uint16_t interrupt);
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/**@} end of group SCI2C_Fuctions*/
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/**@} end of group SCI2C_Driver*/
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/**@} end of group Peripherals_Library*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __APM32E10X_SCI2C_H */
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