mirror of
https://gitee.com/Lyon1998/pikapython.git
synced 2025-01-22 17:12:55 +08:00
254 lines
8.9 KiB
C
254 lines
8.9 KiB
C
|
#include "common.h"
|
|||
|
|
|||
|
/*********************************************************************************
|
|||
|
************************<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> STM32F407<EFBFBD><EFBFBD><EFBFBD>Ŀ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>******************************
|
|||
|
**********************************************************************************
|
|||
|
* <EFBFBD>ļ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: common.c *
|
|||
|
* <EFBFBD>ļ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>õĹ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ļ<EFBFBD> *
|
|||
|
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڣ<EFBFBD>2015.03.03 *
|
|||
|
* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD>V1.0 *
|
|||
|
* <EFBFBD><EFBFBD> <EFBFBD>ߣ<EFBFBD>Clever *
|
|||
|
* ˵ <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ͷ<EFBFBD><EFBFBD>塢IO<EFBFBD><EFBFBD>λ<EFBFBD><EFBFBD><EFBFBD>塢λ<EFBFBD>ζ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> *
|
|||
|
**********************************************************************************
|
|||
|
*********************************************************************************/
|
|||
|
|
|||
|
/****************************************************************************
|
|||
|
* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD>: void GPIO_group_OUT(_gpio_group *group,u16 outdata)
|
|||
|
* <EFBFBD><EFBFBD> <EFBFBD>ܣ<EFBFBD>ʹ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>16<EFBFBD><EFBFBD>IO<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><EFBFBD>16λ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|||
|
* <EFBFBD><EFBFBD><EFBFBD>ڲ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>*group<EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD>16<EFBFBD><EFBFBD>IO<EFBFBD><EFBFBD>ΪԪ<EFBFBD>صĽṹ<EFBFBD><EFBFBD>ָ<EFBFBD><EFBFBD>
|
|||
|
outdata: 16λ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ
|
|||
|
* <EFBFBD><EFBFBD><EFBFBD>ز<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|||
|
* ˵ <EFBFBD><EFBFBD><EFBFBD><EFBFBD>outdata<EFBFBD>Ӹ<EFBFBD>λ<EFBFBD><EFBFBD>ʼ<EFBFBD><EFBFBD>ֵ
|
|||
|
****************************************************************************/
|
|||
|
void GPIO_group_OUT(_gpio_group *group,u16 outdata)
|
|||
|
{
|
|||
|
u8 t;
|
|||
|
for(t=0;t<16;t++)
|
|||
|
{
|
|||
|
if((outdata&0x8000)>>15)
|
|||
|
{
|
|||
|
switch(t)
|
|||
|
{
|
|||
|
case 0: group->data15=1; break;
|
|||
|
case 1: group->data14=1; break;
|
|||
|
case 2: group->data13=1; break;
|
|||
|
case 3: group->data12=1; break;
|
|||
|
case 4: group->data11=1; break;
|
|||
|
case 5: group->data10=1; break;
|
|||
|
case 6: group->data9=1; break;
|
|||
|
case 7: group->data8=1; break;
|
|||
|
case 8: group->data7=1; break;
|
|||
|
case 9: group->data6=1; break;
|
|||
|
case 10: group->data5=1; break;
|
|||
|
case 11: group->data4=1; break;
|
|||
|
case 12: group->data3=1; break;
|
|||
|
case 13: group->data2=1; break;
|
|||
|
case 14: group->data1=1; break;
|
|||
|
case 15: group->data0=1; break;
|
|||
|
}
|
|||
|
}
|
|||
|
else
|
|||
|
{
|
|||
|
switch(t)
|
|||
|
{
|
|||
|
case 0: group->data15=0; break;
|
|||
|
case 1: group->data14=0; break;
|
|||
|
case 2: group->data13=0; break;
|
|||
|
case 3: group->data12=0; break;
|
|||
|
case 4: group->data11=0; break;
|
|||
|
case 5: group->data10=0; break;
|
|||
|
case 6: group->data9=0; break;
|
|||
|
case 7: group->data8=0; break;
|
|||
|
case 8: group->data7=0; break;
|
|||
|
case 9: group->data6=0; break;
|
|||
|
case 10: group->data5=0; break;
|
|||
|
case 11: group->data4=0; break;
|
|||
|
case 12: group->data3=0; break;
|
|||
|
case 13: group->data2=0; break;
|
|||
|
case 14: group->data1=0; break;
|
|||
|
case 15: group->data0=0; break;
|
|||
|
}
|
|||
|
}
|
|||
|
outdata<<=1;
|
|||
|
}
|
|||
|
}
|
|||
|
|
|||
|
/****************************************************************************
|
|||
|
* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD>: void GPIO_bits_OUT(GPIO_TypeDef* GPIOx, u8 start_bit, u8 bit_size,u16 outdata)
|
|||
|
* <EFBFBD><EFBFBD> <EFBFBD>ܣ<EFBFBD>λ<EFBFBD>β<EFBFBD><EFBFBD><EFBFBD>ʵ<EFBFBD>֣<EFBFBD>ͬһIO<EFBFBD>ڵļ<EFBFBD>λ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|||
|
* <EFBFBD><EFBFBD><EFBFBD>ڲ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>* GPIOx<EFBFBD><EFBFBD> <EFBFBD><EFBFBD>Ӧ<EFBFBD><EFBFBD>IO<EFBFBD><EFBFBD>
|
|||
|
* start_bit: <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼλ
|
|||
|
* bit_size: Ҫ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ<EFBFBD><EFBFBD>
|
|||
|
* <EFBFBD><EFBFBD><EFBFBD>ز<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|||
|
* ˵ <EFBFBD><EFBFBD><EFBFBD><EFBFBD>start_bit: 0~14
|
|||
|
bit_size: 1~16
|
|||
|
bit_size<=16-start_bit
|
|||
|
****************************************************************************/
|
|||
|
void GPIO_bits_OUT(GPIO_TypeDef* GPIOx, u8 start_bit, u8 bit_size,u16 outdata)
|
|||
|
{
|
|||
|
u8 i=0;
|
|||
|
u16 bu1=0;u16 middata=1;
|
|||
|
|
|||
|
if( bit_size>(16-start_bit) )
|
|||
|
bit_size=16-start_bit;
|
|||
|
|
|||
|
i=start_bit;
|
|||
|
if(i>0)
|
|||
|
{
|
|||
|
while(i--)
|
|||
|
{ bu1+=middata; middata*=2;}
|
|||
|
}
|
|||
|
|
|||
|
GPIOx->ODR&=( ( (0xffff<<bit_size) <<start_bit ) |bu1 );
|
|||
|
GPIOx->ODR|=(outdata<<start_bit);
|
|||
|
}
|
|||
|
|
|||
|
/*****************************************************************************
|
|||
|
**********************<EFBFBD><EFBFBD><EFBFBD>´<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ο<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ϣ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѧϰ<EFBFBD>ο<EFBFBD>**************************
|
|||
|
*****************************************************************************/
|
|||
|
/****************************************************************************
|
|||
|
* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD>: void Stm32_Clock_Init(u32 plln,u32 pllm,u32 pllp,u32 pllq)
|
|||
|
* <EFBFBD><EFBFBD> <EFBFBD>ܣ<EFBFBD>ʱ<EFBFBD><EFBFBD>ϵͳ<EFBFBD><EFBFBD><EFBFBD>ú<EFBFBD><EFBFBD><EFBFBD>
|
|||
|
* <EFBFBD><EFBFBD><EFBFBD>ڲ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Fvco:VCOƵ<EFBFBD><EFBFBD>
|
|||
|
SYSCLK:ϵͳʱ<EFBFBD><EFBFBD>Ƶ<EFBFBD><EFBFBD>
|
|||
|
Fusb:USB,SDIO,RNG<EFBFBD>ȵ<EFBFBD>ʱ<EFBFBD><EFBFBD>Ƶ<EFBFBD><EFBFBD>
|
|||
|
Fs:PLL<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD>Ƶ<EFBFBD><EFBFBD>,<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>HSI,HSE<EFBFBD><EFBFBD>.
|
|||
|
plln:<EFBFBD><EFBFBD>PLL<EFBFBD><EFBFBD>Ƶϵ<EFBFBD><EFBFBD>(PLL<EFBFBD><EFBFBD>Ƶ),ȡֵ<EFBFBD><EFBFBD>Χ:64~432.
|
|||
|
pllm:<EFBFBD><EFBFBD>PLL<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ƵPLL<EFBFBD><EFBFBD>Ƶϵ<EFBFBD><EFBFBD>(PLL֮ǰ<EFBFBD>ķ<EFBFBD>Ƶ),ȡֵ<EFBFBD><EFBFBD>Χ:2~63.
|
|||
|
pllp:ϵͳʱ<EFBFBD>ӵ<EFBFBD><EFBFBD><EFBFBD>PLL<EFBFBD><EFBFBD>Ƶϵ<EFBFBD><EFBFBD>(PLL֮<EFBFBD><EFBFBD><EFBFBD>ķ<EFBFBD>Ƶ),ȡֵ<EFBFBD><EFBFBD>Χ:2,4,6,8.(<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>4<EFBFBD><EFBFBD>ֵ!)
|
|||
|
pllq:USB/SDIO/<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȵ<EFBFBD><EFBFBD><EFBFBD>PLL<EFBFBD><EFBFBD>Ƶϵ<EFBFBD><EFBFBD>(PLL֮<EFBFBD><EFBFBD><EFBFBD>ķ<EFBFBD>Ƶ),ȡֵ<EFBFBD><EFBFBD>Χ:2~15.
|
|||
|
* <EFBFBD><EFBFBD><EFBFBD>ز<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|||
|
* ˵ <EFBFBD><EFBFBD><EFBFBD><EFBFBD>Fvco=Fs*(plln/pllm);
|
|||
|
SYSCLK=Fvco/pllp=Fs*(plln/(pllm*pllp));
|
|||
|
Fusb=Fvco/pllq=Fs*(plln/(pllm*pllq));<EFBFBD>ⲿ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ8M<EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD>,<EFBFBD>Ƽ<EFBFBD>ֵ:plln=336,pllm=8,pllp=2,pllq=7.
|
|||
|
<EFBFBD>õ<EFBFBD>:Fvco=8*(336/8)=336Mhz
|
|||
|
SYSCLK=336/2=168Mhz
|
|||
|
Fusb=336/7=48Mhz
|
|||
|
****************************************************************************/
|
|||
|
void Stm32_Clock_Init(u32 plln,u32 pllm,u32 pllp,u32 pllq)
|
|||
|
{
|
|||
|
HAL_StatusTypeDef ret = HAL_OK;
|
|||
|
RCC_OscInitTypeDef RCC_OscInitStructure;
|
|||
|
RCC_ClkInitTypeDef RCC_ClkInitStructure;
|
|||
|
|
|||
|
__HAL_RCC_PWR_CLK_ENABLE(); //ʹ<><CAB9>PWRʱ<52><CAB1>
|
|||
|
|
|||
|
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>õ<EFBFBD>ѹ<EFBFBD><D1B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѹ<EFBFBD><D1B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ա<EFBFBD><D4B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>δ<EFBFBD><CEB4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƶ<EFBFBD>ʹ<EFBFBD><CAB9><EFBFBD>
|
|||
|
//ʱʹ<CAB1><CAB9><EFBFBD><EFBFBD><EFBFBD>빦<EFBFBD><EBB9A6>ʵ<EFBFBD><CAB5>ƽ<EFBFBD>⡣
|
|||
|
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);//<2F><><EFBFBD>õ<EFBFBD>ѹ<EFBFBD><D1B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѹ<EFBFBD><D1B9><EFBFBD><EFBFBD>1
|
|||
|
|
|||
|
RCC_OscInitStructure.OscillatorType=RCC_OSCILLATORTYPE_HSE; //ʱ<><CAB1>ԴΪHSE
|
|||
|
RCC_OscInitStructure.HSEState=RCC_HSE_ON; //<2F><><EFBFBD><EFBFBD>HSE
|
|||
|
RCC_OscInitStructure.PLL.PLLState=RCC_PLL_ON;//<2F><><EFBFBD><EFBFBD>PLL
|
|||
|
RCC_OscInitStructure.PLL.PLLSource=RCC_PLLSOURCE_HSE;//PLLʱ<4C><CAB1>Դѡ<D4B4><D1A1>HSE
|
|||
|
RCC_OscInitStructure.PLL.PLLM=pllm; //<2F><>PLL<4C><4C><EFBFBD><EFBFBD>ƵPLL<4C><4C>Ƶϵ<C6B5><CFB5>(PLL֮ǰ<D6AE>ķ<EFBFBD>Ƶ),ȡֵ<C8A1><D6B5>Χ:2~63.
|
|||
|
RCC_OscInitStructure.PLL.PLLN=plln; //<2F><>PLL<4C><4C>Ƶϵ<C6B5><CFB5>(PLL<4C><4C>Ƶ),ȡֵ<C8A1><D6B5>Χ:64~432.
|
|||
|
RCC_OscInitStructure.PLL.PLLP=pllp; //ϵͳʱ<CDB3>ӵ<EFBFBD><D3B5><EFBFBD>PLL<4C><4C>Ƶϵ<C6B5><CFB5>(PLL֮<4C><D6AE><EFBFBD>ķ<EFBFBD>Ƶ),ȡֵ<C8A1><D6B5>Χ:2,4,6,8.(<28><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>4<EFBFBD><34>ֵ!)
|
|||
|
RCC_OscInitStructure.PLL.PLLQ=pllq; //USB/SDIO/<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȵ<EFBFBD><C8B5><EFBFBD>PLL<4C><4C>Ƶϵ<C6B5><CFB5>(PLL֮<4C><D6AE><EFBFBD>ķ<EFBFBD>Ƶ),ȡֵ<C8A1><D6B5>Χ:2~15.
|
|||
|
ret=HAL_RCC_OscConfig(&RCC_OscInitStructure);//<2F><>ʼ<EFBFBD><CABC>
|
|||
|
|
|||
|
if(ret!=HAL_OK) while(1);
|
|||
|
|
|||
|
//ѡ<><D1A1>PLL<4C><4C>Ϊϵͳʱ<CDB3><CAB1>Դ<EFBFBD><D4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>HCLK,PCLK1<4B><31>PCLK2
|
|||
|
RCC_ClkInitStructure.ClockType=(RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2);
|
|||
|
RCC_ClkInitStructure.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK;//<2F><><EFBFBD><EFBFBD>ϵͳʱ<CDB3><CAB1>ʱ<EFBFBD><CAB1>ԴΪPLL
|
|||
|
RCC_ClkInitStructure.AHBCLKDivider=RCC_SYSCLK_DIV1;//AHB<48><42>Ƶϵ<C6B5><CFB5>Ϊ1
|
|||
|
RCC_ClkInitStructure.APB1CLKDivider=RCC_HCLK_DIV4; //APB1<42><31>Ƶϵ<C6B5><CFB5>Ϊ4
|
|||
|
RCC_ClkInitStructure.APB2CLKDivider=RCC_HCLK_DIV2; //APB2<42><32>Ƶϵ<C6B5><CFB5>Ϊ2
|
|||
|
ret=HAL_RCC_ClockConfig(&RCC_ClkInitStructure,FLASH_LATENCY_5);//ͬʱ<CDAC><CAB1><EFBFBD><EFBFBD>FLASH<53><48>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>Ϊ5WS<57><53>Ҳ<EFBFBD><D2B2><EFBFBD><EFBFBD>6<EFBFBD><36>CPU<50><55><EFBFBD>ڡ<EFBFBD>
|
|||
|
|
|||
|
if(ret!=HAL_OK) while(1);
|
|||
|
|
|||
|
//STM32F405x/407x/415x/417x Z<>汾<EFBFBD><E6B1BE><EFBFBD><EFBFBD><EFBFBD><EFBFBD>֧<EFBFBD><D6A7>Ԥȡ<D4A4><C8A1><EFBFBD><EFBFBD>
|
|||
|
if (HAL_GetREVID() == 0x1001)
|
|||
|
{
|
|||
|
__HAL_FLASH_PREFETCH_BUFFER_ENABLE(); //ʹ<><CAB9>flashԤȡ
|
|||
|
}
|
|||
|
}
|
|||
|
|
|||
|
|
|||
|
////THUMBָ<42>֧<EEB2BB>ֻ<EFBFBD><D6BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|||
|
////<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>·<EFBFBD><C2B7><EFBFBD>ʵ<EFBFBD><CAB5>ִ<EFBFBD>л<EFBFBD><D0BB><EFBFBD>ָ<EFBFBD><D6B8>WFI
|
|||
|
//__asm void WFI_SET(void)
|
|||
|
//{
|
|||
|
// WFI;
|
|||
|
//}
|
|||
|
////<2F>ر<EFBFBD><D8B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>(<28><><EFBFBD>Dz<EFBFBD><C7B2><EFBFBD><EFBFBD><EFBFBD>fault<6C><74>NMI<4D>ж<EFBFBD>)
|
|||
|
//__asm void INTX_DISABLE(void)
|
|||
|
//{
|
|||
|
// CPSID I
|
|||
|
// BX LR
|
|||
|
//}
|
|||
|
////<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
|
|||
|
//__asm void INTX_ENABLE(void)
|
|||
|
//{
|
|||
|
// CPSIE I
|
|||
|
// BX LR
|
|||
|
//}
|
|||
|
////<2F><><EFBFBD><EFBFBD>ջ<EFBFBD><D5BB><EFBFBD><EFBFBD>ַ
|
|||
|
////addr:ջ<><D5BB><EFBFBD><EFBFBD>ַ
|
|||
|
//__asm void MSR_MSP(u32 addr)
|
|||
|
//{
|
|||
|
// MSR MSP, r0 //set Main Stack value
|
|||
|
// BX r14
|
|||
|
//}
|
|||
|
|
|||
|
//<2F><><EFBFBD><EFBFBD>ϵͳ<CFB5>δ<EFBFBD><CEB4><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>д<EFBFBD><D0B4><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>
|
|||
|
|
|||
|
static u8 fac_us=0; //us<75><73>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|||
|
|
|||
|
/****************************************************************************
|
|||
|
* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD>: delay_init()
|
|||
|
* <EFBFBD><EFBFBD> <EFBFBD>ܣ<EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD><EFBFBD>
|
|||
|
* <EFBFBD><EFBFBD><EFBFBD>ڲ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|||
|
* <EFBFBD><EFBFBD><EFBFBD>ز<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|||
|
* ˵ <EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|||
|
****************************************************************************/
|
|||
|
void delay_init()
|
|||
|
{
|
|||
|
HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);//SysTickƵ<6B><C6B5>ΪHCLK
|
|||
|
fac_us=SYSCLK;
|
|||
|
}
|
|||
|
|
|||
|
/****************************************************************************
|
|||
|
* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD>: void delay_us(u32 nus)
|
|||
|
* <EFBFBD><EFBFBD> <EFBFBD>ܣ<EFBFBD><EFBFBD><EFBFBD>ʱnus
|
|||
|
* <EFBFBD><EFBFBD><EFBFBD>ڲ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ҫ<EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|||
|
* <EFBFBD><EFBFBD><EFBFBD>ز<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|||
|
* ˵ <EFBFBD><EFBFBD><EFBFBD><EFBFBD>nus<EFBFBD><EFBFBD>ֵ,<EFBFBD><EFBFBD>Ҫ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>798915us
|
|||
|
****************************************************************************/
|
|||
|
void delay_us(u32 nus)
|
|||
|
{
|
|||
|
u32 ticks;
|
|||
|
u32 told,tnow,tcnt=0;
|
|||
|
u32 reload=SysTick->LOAD; //LOAD<41><44>ֵ
|
|||
|
ticks=nus*fac_us; //<2F><>Ҫ<EFBFBD>Ľ<EFBFBD><C4BD><EFBFBD><EFBFBD><EFBFBD>
|
|||
|
told=SysTick->VAL; //<2F>ս<EFBFBD><D5BD><EFBFBD>ʱ<EFBFBD>ļ<EFBFBD><C4BC><EFBFBD><EFBFBD><EFBFBD>ֵ
|
|||
|
while(1)
|
|||
|
{
|
|||
|
tnow=SysTick->VAL;
|
|||
|
if(tnow!=told)
|
|||
|
{
|
|||
|
if(tnow<told)tcnt+=told-tnow; //<2F><><EFBFBD><EFBFBD>ע<EFBFBD><D7A2>һ<EFBFBD><D2BB>SYSTICK<43><4B>һ<EFBFBD><D2BB><EFBFBD>ݼ<EFBFBD><DDBC>ļ<EFBFBD><C4BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϳ<EFBFBD><CDBF><EFBFBD><EFBFBD><EFBFBD>.
|
|||
|
else tcnt+=reload-tnow+told;
|
|||
|
told=tnow;
|
|||
|
if(tcnt>=ticks)break; //ʱ<>䳬<EFBFBD><E4B3AC>/<2F><><EFBFBD><EFBFBD>Ҫ<EFBFBD>ӳٵ<D3B3>ʱ<EFBFBD><CAB1>,<2C><><EFBFBD>˳<EFBFBD>.
|
|||
|
}
|
|||
|
};
|
|||
|
}
|
|||
|
|
|||
|
/****************************************************************************
|
|||
|
* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD>: void delay_ms(u16 nms)
|
|||
|
* <EFBFBD><EFBFBD> <EFBFBD>ܣ<EFBFBD><EFBFBD><EFBFBD>ʱnms
|
|||
|
* <EFBFBD><EFBFBD><EFBFBD>ڲ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ҫ<EFBFBD><EFBFBD>ʱ<EFBFBD>ĺ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|||
|
* <EFBFBD><EFBFBD><EFBFBD>ز<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|||
|
* ˵ <EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|||
|
****************************************************************************/
|
|||
|
void delay_ms(u16 nms)
|
|||
|
{
|
|||
|
u32 i;
|
|||
|
for(i=0;i<nms;i++) delay_us(1000);
|
|||
|
}
|
|||
|
|
|||
|
|